/src/build/lib/Target/VE/VEGenRegisterInfo.inc

Line	Count	Source (jump to first uncovered line)
1		/===- TableGen'erated file -------------------------------------- C++ --===\
2		\|* *\|
3		\|* Target Register Enum Values *\|
4		\|* *\|
5		\|* Automatically generated file, do not edit! *\|
6		\|* *\|
7		\===----------------------------------------------------------------------===/
8
9
10		#ifdef GET_REGINFO_ENUM
11		#undef GET_REGINFO_ENUM
12
13		namespace llvm {
14
15		class MCRegisterClass;
16		extern const MCRegisterClass VEMCRegisterClasses[];
17
18		namespace VE {
19		enum {
20		NoRegister,
21		IC = 1,
22		PMMR = 2,
23		PSW = 3,
24		SAR = 4,
25		USRCC = 5,
26		VIX = 6,
27		VL = 7,
28		PMC0 = 8,
29		PMC1 = 9,
30		PMC2 = 10,
31		PMC3 = 11,
32		PMC4 = 12,
33		PMC5 = 13,
34		PMC6 = 14,
35		PMC7 = 15,
36		PMC8 = 16,
37		PMC9 = 17,
38		PMC10 = 18,
39		PMC11 = 19,
40		PMC12 = 20,
41		PMC13 = 21,
42		PMC14 = 22,
43		PMCR0 = 23,
44		PMCR1 = 24,
45		PMCR2 = 25,
46		PMCR3 = 26,
47		Q0 = 27,
48		Q1 = 28,
49		Q2 = 29,
50		Q3 = 30,
51		Q4 = 31,
52		Q5 = 32,
53		Q6 = 33,
54		Q7 = 34,
55		Q8 = 35,
56		Q9 = 36,
57		Q10 = 37,
58		Q11 = 38,
59		Q12 = 39,
60		Q13 = 40,
61		Q14 = 41,
62		Q15 = 42,
63		Q16 = 43,
64		Q17 = 44,
65		Q18 = 45,
66		Q19 = 46,
67		Q20 = 47,
68		Q21 = 48,
69		Q22 = 49,
70		Q23 = 50,
71		Q24 = 51,
72		Q25 = 52,
73		Q26 = 53,
74		Q27 = 54,
75		Q28 = 55,
76		Q29 = 56,
77		Q30 = 57,
78		Q31 = 58,
79		SF0 = 59,
80		SF1 = 60,
81		SF2 = 61,
82		SF3 = 62,
83		SF4 = 63,
84		SF5 = 64,
85		SF6 = 65,
86		SF7 = 66,
87		SF8 = 67,
88		SF9 = 68,
89		SF10 = 69,
90		SF11 = 70,
91		SF12 = 71,
92		SF13 = 72,
93		SF14 = 73,
94		SF15 = 74,
95		SF16 = 75,
96		SF17 = 76,
97		SF18 = 77,
98		SF19 = 78,
99		SF20 = 79,
100		SF21 = 80,
101		SF22 = 81,
102		SF23 = 82,
103		SF24 = 83,
104		SF25 = 84,
105		SF26 = 85,
106		SF27 = 86,
107		SF28 = 87,
108		SF29 = 88,
109		SF30 = 89,
110		SF31 = 90,
111		SF32 = 91,
112		SF33 = 92,
113		SF34 = 93,
114		SF35 = 94,
115		SF36 = 95,
116		SF37 = 96,
117		SF38 = 97,
118		SF39 = 98,
119		SF40 = 99,
120		SF41 = 100,
121		SF42 = 101,
122		SF43 = 102,
123		SF44 = 103,
124		SF45 = 104,
125		SF46 = 105,
126		SF47 = 106,
127		SF48 = 107,
128		SF49 = 108,
129		SF50 = 109,
130		SF51 = 110,
131		SF52 = 111,
132		SF53 = 112,
133		SF54 = 113,
134		SF55 = 114,
135		SF56 = 115,
136		SF57 = 116,
137		SF58 = 117,
138		SF59 = 118,
139		SF60 = 119,
140		SF61 = 120,
141		SF62 = 121,
142		SF63 = 122,
143		SW0 = 123,
144		SW1 = 124,
145		SW2 = 125,
146		SW3 = 126,
147		SW4 = 127,
148		SW5 = 128,
149		SW6 = 129,
150		SW7 = 130,
151		SW8 = 131,
152		SW9 = 132,
153		SW10 = 133,
154		SW11 = 134,
155		SW12 = 135,
156		SW13 = 136,
157		SW14 = 137,
158		SW15 = 138,
159		SW16 = 139,
160		SW17 = 140,
161		SW18 = 141,
162		SW19 = 142,
163		SW20 = 143,
164		SW21 = 144,
165		SW22 = 145,
166		SW23 = 146,
167		SW24 = 147,
168		SW25 = 148,
169		SW26 = 149,
170		SW27 = 150,
171		SW28 = 151,
172		SW29 = 152,
173		SW30 = 153,
174		SW31 = 154,
175		SW32 = 155,
176		SW33 = 156,
177		SW34 = 157,
178		SW35 = 158,
179		SW36 = 159,
180		SW37 = 160,
181		SW38 = 161,
182		SW39 = 162,
183		SW40 = 163,
184		SW41 = 164,
185		SW42 = 165,
186		SW43 = 166,
187		SW44 = 167,
188		SW45 = 168,
189		SW46 = 169,
190		SW47 = 170,
191		SW48 = 171,
192		SW49 = 172,
193		SW50 = 173,
194		SW51 = 174,
195		SW52 = 175,
196		SW53 = 176,
197		SW54 = 177,
198		SW55 = 178,
199		SW56 = 179,
200		SW57 = 180,
201		SW58 = 181,
202		SW59 = 182,
203		SW60 = 183,
204		SW61 = 184,
205		SW62 = 185,
206		SW63 = 186,
207		SX0 = 187,
208		SX1 = 188,
209		SX2 = 189,
210		SX3 = 190,
211		SX4 = 191,
212		SX5 = 192,
213		SX6 = 193,
214		SX7 = 194,
215		SX8 = 195,
216		SX9 = 196,
217		SX10 = 197,
218		SX11 = 198,
219		SX12 = 199,
220		SX13 = 200,
221		SX14 = 201,
222		SX15 = 202,
223		SX16 = 203,
224		SX17 = 204,
225		SX18 = 205,
226		SX19 = 206,
227		SX20 = 207,
228		SX21 = 208,
229		SX22 = 209,
230		SX23 = 210,
231		SX24 = 211,
232		SX25 = 212,
233		SX26 = 213,
234		SX27 = 214,
235		SX28 = 215,
236		SX29 = 216,
237		SX30 = 217,
238		SX31 = 218,
239		SX32 = 219,
240		SX33 = 220,
241		SX34 = 221,
242		SX35 = 222,
243		SX36 = 223,
244		SX37 = 224,
245		SX38 = 225,
246		SX39 = 226,
247		SX40 = 227,
248		SX41 = 228,
249		SX42 = 229,
250		SX43 = 230,
251		SX44 = 231,
252		SX45 = 232,
253		SX46 = 233,
254		SX47 = 234,
255		SX48 = 235,
256		SX49 = 236,
257		SX50 = 237,
258		SX51 = 238,
259		SX52 = 239,
260		SX53 = 240,
261		SX54 = 241,
262		SX55 = 242,
263		SX56 = 243,
264		SX57 = 244,
265		SX58 = 245,
266		SX59 = 246,
267		SX60 = 247,
268		SX61 = 248,
269		SX62 = 249,
270		SX63 = 250,
271		V0 = 251,
272		V1 = 252,
273		V2 = 253,
274		V3 = 254,
275		V4 = 255,
276		V5 = 256,
277		V6 = 257,
278		V7 = 258,
279		V8 = 259,
280		V9 = 260,
281		V10 = 261,
282		V11 = 262,
283		V12 = 263,
284		V13 = 264,
285		V14 = 265,
286		V15 = 266,
287		V16 = 267,
288		V17 = 268,
289		V18 = 269,
290		V19 = 270,
291		V20 = 271,
292		V21 = 272,
293		V22 = 273,
294		V23 = 274,
295		V24 = 275,
296		V25 = 276,
297		V26 = 277,
298		V27 = 278,
299		V28 = 279,
300		V29 = 280,
301		V30 = 281,
302		V31 = 282,
303		V32 = 283,
304		V33 = 284,
305		V34 = 285,
306		V35 = 286,
307		V36 = 287,
308		V37 = 288,
309		V38 = 289,
310		V39 = 290,
311		V40 = 291,
312		V41 = 292,
313		V42 = 293,
314		V43 = 294,
315		V44 = 295,
316		V45 = 296,
317		V46 = 297,
318		V47 = 298,
319		V48 = 299,
320		V49 = 300,
321		V50 = 301,
322		V51 = 302,
323		V52 = 303,
324		V53 = 304,
325		V54 = 305,
326		V55 = 306,
327		V56 = 307,
328		V57 = 308,
329		V58 = 309,
330		V59 = 310,
331		V60 = 311,
332		V61 = 312,
333		V62 = 313,
334		V63 = 314,
335		VM0 = 315,
336		VM1 = 316,
337		VM2 = 317,
338		VM3 = 318,
339		VM4 = 319,
340		VM5 = 320,
341		VM6 = 321,
342		VM7 = 322,
343		VM8 = 323,
344		VM9 = 324,
345		VM10 = 325,
346		VM11 = 326,
347		VM12 = 327,
348		VM13 = 328,
349		VM14 = 329,
350		VM15 = 330,
351		VMP0 = 331,
352		VMP1 = 332,
353		VMP2 = 333,
354		VMP3 = 334,
355		VMP4 = 335,
356		VMP5 = 336,
357		VMP6 = 337,
358		VMP7 = 338,
359		NUM_TARGET_REGS // 339
360		};
361		} // end namespace VE
362
363		// Register classes
364
365		namespace VE {
366		enum {
367		F32RegClassID = 0,
368		I32RegClassID = 1,
369		VLSRegClassID = 2,
370		I64RegClassID = 3,
371		MISCRegClassID = 4,
372		F128RegClassID = 5,
373		VMRegClassID = 6,
374		VM512RegClassID = 7,
375		VM512_with_sub_vm_evenRegClassID = 8,
376		V64RegClassID = 9,
377
378		};
379		} // end namespace VE
380
381
382		// Register alternate name indices
383
384		namespace VE {
385		enum {
386		AsmName, // 0
387		NoRegAltName, // 1
388		NUM_TARGET_REG_ALT_NAMES = 2
389		};
390		} // end namespace VE
391
392
393		// Subregister indices
394
395		namespace VE {
396		enum : uint16_t {
397		NoSubRegister,
398		sub_even, // 1
399		sub_f32, // 2
400		sub_i32, // 3
401		sub_odd, // 4
402		sub_vm_even, // 5
403		sub_vm_odd, // 6
404		sub_odd_then_sub_f32, // 7
405		sub_odd_then_sub_i32, // 8
406		NUM_TARGET_SUBREGS
407		};
408		} // end namespace VE
409
410		// Register pressure sets enum.
411		namespace VE {
412		enum RegisterPressureSets {
413		VLS = 0,
414		VM512 = 1,
415		VM = 2,
416		VM_with_VM512 = 3,
417		MISC = 4,
418		F32 = 5,
419		V64 = 6,
420		};
421		} // end namespace VE
422
423		} // end namespace llvm
424
425		#endif // GET_REGINFO_ENUM
426
427		/===- TableGen'erated file -------------------------------------- C++ --===\
428		\|* *\|
429		\|* MC Register Information *\|
430		\|* *\|
431		\|* Automatically generated file, do not edit! *\|
432		\|* *\|
433		\===----------------------------------------------------------------------===/
434
435
436		#ifdef GET_REGINFO_MC_DESC
437		#undef GET_REGINFO_MC_DESC
438
439		namespace llvm {
440
441		extern const int16_t VERegDiffLists[] = {
442		/* 0 */ 64, -192, 0,
443		/* 3 */ 128, -192, 0,
444		/* 6 */ 64, -191, 0,
445		/* 9 */ 128, -191, 0,
446		/* 12 */ 64, -190, 0,
447		/* 15 */ 128, -190, 0,
448		/* 18 */ 64, -189, 0,
449		/* 21 */ 128, -189, 0,
450		/* 24 */ 64, -188, 0,
451		/* 27 */ 128, -188, 0,
452		/* 30 */ 64, -187, 0,
453		/* 33 */ 128, -187, 0,
454		/* 36 */ 64, -186, 0,
455		/* 39 */ 128, -186, 0,
456		/* 42 */ 64, -185, 0,
457		/* 45 */ 128, -185, 0,
458		/* 48 */ 64, -184, 0,
459		/* 51 */ 128, -184, 0,
460		/* 54 */ 64, -183, 0,
461		/* 57 */ 128, -183, 0,
462		/* 60 */ 64, -182, 0,
463		/* 63 */ 128, -182, 0,
464		/* 66 */ 64, -181, 0,
465		/* 69 */ 128, -181, 0,
466		/* 72 */ 64, -180, 0,
467		/* 75 */ 128, -180, 0,
468		/* 78 */ 64, -179, 0,
469		/* 81 */ 128, -179, 0,
470		/* 84 */ 64, -178, 0,
471		/* 87 */ 128, -178, 0,
472		/* 90 */ 64, -177, 0,
473		/* 93 */ 128, -177, 0,
474		/* 96 */ 64, -176, 0,
475		/* 99 */ 128, -176, 0,
476		/* 102 */ 64, -175, 0,
477		/* 105 */ 128, -175, 0,
478		/* 108 */ 64, -174, 0,
479		/* 111 */ 128, -174, 0,
480		/* 114 */ 64, -173, 0,
481		/* 117 */ 128, -173, 0,
482		/* 120 */ 64, -172, 0,
483		/* 123 */ 128, -172, 0,
484		/* 126 */ 64, -171, 0,
485		/* 129 */ 128, -171, 0,
486		/* 132 */ 64, -170, 0,
487		/* 135 */ 128, -170, 0,
488		/* 138 */ 64, -169, 0,
489		/* 141 */ 128, -169, 0,
490		/* 144 */ 64, -168, 0,
491		/* 147 */ 128, -168, 0,
492		/* 150 */ 64, -167, 0,
493		/* 153 */ 128, -167, 0,
494		/* 156 */ 64, -166, 0,
495		/* 159 */ 128, -166, 0,
496		/* 162 */ 64, -165, 0,
497		/* 165 */ 128, -165, 0,
498		/* 168 */ 64, -164, 0,
499		/* 171 */ 128, -164, 0,
500		/* 174 */ 64, -163, 0,
501		/* 177 */ 128, -163, 0,
502		/* 180 */ 64, -162, 0,
503		/* 183 */ 128, -162, 0,
504		/* 186 */ 64, -161, 0,
505		/* 189 */ 128, -161, 0,
506		/* 192 */ 64, -160, 0,
507		/* 195 */ 128, -160, 0,
508		/* 198 */ 160, -64, -64, 129, -64, -64, 0,
509		/* 205 */ 161, -64, -64, 129, -64, -64, 0,
510		/* 212 */ 162, -64, -64, 129, -64, -64, 0,
511		/* 219 */ 163, -64, -64, 129, -64, -64, 0,
512		/* 226 */ 164, -64, -64, 129, -64, -64, 0,
513		/* 233 */ 165, -64, -64, 129, -64, -64, 0,
514		/* 240 */ 166, -64, -64, 129, -64, -64, 0,
515		/* 247 */ 167, -64, -64, 129, -64, -64, 0,
516		/* 254 */ 168, -64, -64, 129, -64, -64, 0,
517		/* 261 */ 169, -64, -64, 129, -64, -64, 0,
518		/* 268 */ 170, -64, -64, 129, -64, -64, 0,
519		/* 275 */ 171, -64, -64, 129, -64, -64, 0,
520		/* 282 */ 172, -64, -64, 129, -64, -64, 0,
521		/* 289 */ 173, -64, -64, 129, -64, -64, 0,
522		/* 296 */ 174, -64, -64, 129, -64, -64, 0,
523		/* 303 */ 175, -64, -64, 129, -64, -64, 0,
524		/* 310 */ 176, -64, -64, 129, -64, -64, 0,
525		/* 317 */ 177, -64, -64, 129, -64, -64, 0,
526		/* 324 */ 178, -64, -64, 129, -64, -64, 0,
527		/* 331 */ 179, -64, -64, 129, -64, -64, 0,
528		/* 338 */ 180, -64, -64, 129, -64, -64, 0,
529		/* 345 */ 181, -64, -64, 129, -64, -64, 0,
530		/* 352 */ 182, -64, -64, 129, -64, -64, 0,
531		/* 359 */ 183, -64, -64, 129, -64, -64, 0,
532		/* 366 */ 184, -64, -64, 129, -64, -64, 0,
533		/* 373 */ 185, -64, -64, 129, -64, -64, 0,
534		/* 380 */ 186, -64, -64, 129, -64, -64, 0,
535		/* 387 */ 187, -64, -64, 129, -64, -64, 0,
536		/* 394 */ 188, -64, -64, 129, -64, -64, 0,
537		/* 401 */ 189, -64, -64, 129, -64, -64, 0,
538		/* 408 */ 190, -64, -64, 129, -64, -64, 0,
539		/* 415 */ 191, -64, -64, 129, -64, -64, 0,
540		/* 422 */ -15, 1, 0,
541		/* 425 */ -14, 1, 0,
542		/* 428 */ -13, 1, 0,
543		/* 431 */ -12, 1, 0,
544		/* 434 */ -11, 1, 0,
545		/* 437 */ -10, 1, 0,
546		/* 440 */ -9, 1, 0,
547		/* 443 */ 8, 0,
548		/* 445 */ 9, 0,
549		/* 447 */ 10, 0,
550		/* 449 */ 11, 0,
551		/* 451 */ 12, 0,
552		/* 453 */ 13, 0,
553		/* 455 */ 14, 0,
554		/* 457 */ 15, 0,
555		};
556
557		extern const LaneBitmask VELaneMaskLists[] = {
558		/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
559		/* 3 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
560		/* 6 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
561		};
562
563		extern const uint16_t VESubRegIdxLists[] = {
564		/* 0 */ 3, 2, 0,
565		/* 3 */ 5, 6, 0,
566		/* 6 */ 1, 3, 2, 4, 8, 7, 0,
567		};
568
569		extern const MCRegisterInfo::SubRegCoveredBits VESubRegIdxRanges[] = {
570		{ 65535, 65535 },
571		{ 0, 64 }, // sub_even
572		{ 0, 32 }, // sub_f32
573		{ 32, 32 }, // sub_i32
574		{ 64, 64 }, // sub_odd
575		{ 0, 256 }, // sub_vm_even
576		{ 256, 256 }, // sub_vm_odd
577		{ 64, 32 }, // sub_odd_then_sub_f32
578		{ 96, 32 }, // sub_odd_then_sub_i32
579		};
580
581
582		#ifdef __GNUC__
583		#pragma GCC diagnostic push
584		#pragma GCC diagnostic ignored "-Woverlength-strings"
585		#endif
586		extern const char VERegStrings[] = {
587		/* 0 */ "PMC10\0"
588		/* 6 */ "SF10\0"
589		/* 11 */ "VM10\0"
590		/* 16 */ "Q10\0"
591		/* 20 */ "V10\0"
592		/* 24 */ "SW10\0"
593		/* 29 */ "SX10\0"
594		/* 34 */ "SF20\0"
595		/* 39 */ "Q20\0"
596		/* 43 */ "V20\0"
597		/* 47 */ "SW20\0"
598		/* 52 */ "SX20\0"
599		/* 57 */ "SF30\0"
600		/* 62 */ "Q30\0"
601		/* 66 */ "V30\0"
602		/* 70 */ "SW30\0"
603		/* 75 */ "SX30\0"
604		/* 80 */ "SF40\0"
605		/* 85 */ "V40\0"
606		/* 89 */ "SW40\0"
607		/* 94 */ "SX40\0"
608		/* 99 */ "SF50\0"
609		/* 104 */ "V50\0"
610		/* 108 */ "SW50\0"
611		/* 113 */ "SX50\0"
612		/* 118 */ "SF60\0"
613		/* 123 */ "V60\0"
614		/* 127 */ "SW60\0"
615		/* 132 */ "SX60\0"
616		/* 137 */ "PMC0\0"
617		/* 142 */ "SF0\0"
618		/* 146 */ "VM0\0"
619		/* 150 */ "VMP0\0"
620		/* 155 */ "Q0\0"
621		/* 158 */ "PMCR0\0"
622		/* 164 */ "V0\0"
623		/* 167 */ "SW0\0"
624		/* 171 */ "SX0\0"
625		/* 175 */ "PMC11\0"
626		/* 181 */ "SF11\0"
627		/* 186 */ "VM11\0"
628		/* 191 */ "Q11\0"
629		/* 195 */ "V11\0"
630		/* 199 */ "SW11\0"
631		/* 204 */ "SX11\0"
632		/* 209 */ "SF21\0"
633		/* 214 */ "Q21\0"
634		/* 218 */ "V21\0"
635		/* 222 */ "SW21\0"
636		/* 227 */ "SX21\0"
637		/* 232 */ "SF31\0"
638		/* 237 */ "Q31\0"
639		/* 241 */ "V31\0"
640		/* 245 */ "SW31\0"
641		/* 250 */ "SX31\0"
642		/* 255 */ "SF41\0"
643		/* 260 */ "V41\0"
644		/* 264 */ "SW41\0"
645		/* 269 */ "SX41\0"
646		/* 274 */ "SF51\0"
647		/* 279 */ "V51\0"
648		/* 283 */ "SW51\0"
649		/* 288 */ "SX51\0"
650		/* 293 */ "SF61\0"
651		/* 298 */ "V61\0"
652		/* 302 */ "SW61\0"
653		/* 307 */ "SX61\0"
654		/* 312 */ "PMC1\0"
655		/* 317 */ "SF1\0"
656		/* 321 */ "VM1\0"
657		/* 325 */ "VMP1\0"
658		/* 330 */ "Q1\0"
659		/* 333 */ "PMCR1\0"
660		/* 339 */ "V1\0"
661		/* 342 */ "SW1\0"
662		/* 346 */ "SX1\0"
663		/* 350 */ "PMC12\0"
664		/* 356 */ "SF12\0"
665		/* 361 */ "VM12\0"
666		/* 366 */ "Q12\0"
667		/* 370 */ "V12\0"
668		/* 374 */ "SW12\0"
669		/* 379 */ "SX12\0"
670		/* 384 */ "SF22\0"
671		/* 389 */ "Q22\0"
672		/* 393 */ "V22\0"
673		/* 397 */ "SW22\0"
674		/* 402 */ "SX22\0"
675		/* 407 */ "SF32\0"
676		/* 412 */ "V32\0"
677		/* 416 */ "SW32\0"
678		/* 421 */ "SX32\0"
679		/* 426 */ "SF42\0"
680		/* 431 */ "V42\0"
681		/* 435 */ "SW42\0"
682		/* 440 */ "SX42\0"
683		/* 445 */ "SF52\0"
684		/* 450 */ "V52\0"
685		/* 454 */ "SW52\0"
686		/* 459 */ "SX52\0"
687		/* 464 */ "SF62\0"
688		/* 469 */ "V62\0"
689		/* 473 */ "SW62\0"
690		/* 478 */ "SX62\0"
691		/* 483 */ "PMC2\0"
692		/* 488 */ "SF2\0"
693		/* 492 */ "VM2\0"
694		/* 496 */ "VMP2\0"
695		/* 501 */ "Q2\0"
696		/* 504 */ "PMCR2\0"
697		/* 510 */ "V2\0"
698		/* 513 */ "SW2\0"
699		/* 517 */ "SX2\0"
700		/* 521 */ "PMC13\0"
701		/* 527 */ "SF13\0"
702		/* 532 */ "VM13\0"
703		/* 537 */ "Q13\0"
704		/* 541 */ "V13\0"
705		/* 545 */ "SW13\0"
706		/* 550 */ "SX13\0"
707		/* 555 */ "SF23\0"
708		/* 560 */ "Q23\0"
709		/* 564 */ "V23\0"
710		/* 568 */ "SW23\0"
711		/* 573 */ "SX23\0"
712		/* 578 */ "SF33\0"
713		/* 583 */ "V33\0"
714		/* 587 */ "SW33\0"
715		/* 592 */ "SX33\0"
716		/* 597 */ "SF43\0"
717		/* 602 */ "V43\0"
718		/* 606 */ "SW43\0"
719		/* 611 */ "SX43\0"
720		/* 616 */ "SF53\0"
721		/* 621 */ "V53\0"
722		/* 625 */ "SW53\0"
723		/* 630 */ "SX53\0"
724		/* 635 */ "SF63\0"
725		/* 640 */ "V63\0"
726		/* 644 */ "SW63\0"
727		/* 649 */ "SX63\0"
728		/* 654 */ "PMC3\0"
729		/* 659 */ "SF3\0"
730		/* 663 */ "VM3\0"
731		/* 667 */ "VMP3\0"
732		/* 672 */ "Q3\0"
733		/* 675 */ "PMCR3\0"
734		/* 681 */ "V3\0"
735		/* 684 */ "SW3\0"
736		/* 688 */ "SX3\0"
737		/* 692 */ "PMC14\0"
738		/* 698 */ "SF14\0"
739		/* 703 */ "VM14\0"
740		/* 708 */ "Q14\0"
741		/* 712 */ "V14\0"
742		/* 716 */ "SW14\0"
743		/* 721 */ "SX14\0"
744		/* 726 */ "SF24\0"
745		/* 731 */ "Q24\0"
746		/* 735 */ "V24\0"
747		/* 739 */ "SW24\0"
748		/* 744 */ "SX24\0"
749		/* 749 */ "SF34\0"
750		/* 754 */ "V34\0"
751		/* 758 */ "SW34\0"
752		/* 763 */ "SX34\0"
753		/* 768 */ "SF44\0"
754		/* 773 */ "V44\0"
755		/* 777 */ "SW44\0"
756		/* 782 */ "SX44\0"
757		/* 787 */ "SF54\0"
758		/* 792 */ "V54\0"
759		/* 796 */ "SW54\0"
760		/* 801 */ "SX54\0"
761		/* 806 */ "PMC4\0"
762		/* 811 */ "SF4\0"
763		/* 815 */ "VM4\0"
764		/* 819 */ "VMP4\0"
765		/* 824 */ "Q4\0"
766		/* 827 */ "V4\0"
767		/* 830 */ "SW4\0"
768		/* 834 */ "SX4\0"
769		/* 838 */ "SF15\0"
770		/* 843 */ "VM15\0"
771		/* 848 */ "Q15\0"
772		/* 852 */ "V15\0"
773		/* 856 */ "SW15\0"
774		/* 861 */ "SX15\0"
775		/* 866 */ "SF25\0"
776		/* 871 */ "Q25\0"
777		/* 875 */ "V25\0"
778		/* 879 */ "SW25\0"
779		/* 884 */ "SX25\0"
780		/* 889 */ "SF35\0"
781		/* 894 */ "V35\0"
782		/* 898 */ "SW35\0"
783		/* 903 */ "SX35\0"
784		/* 908 */ "SF45\0"
785		/* 913 */ "V45\0"
786		/* 917 */ "SW45\0"
787		/* 922 */ "SX45\0"
788		/* 927 */ "SF55\0"
789		/* 932 */ "V55\0"
790		/* 936 */ "SW55\0"
791		/* 941 */ "SX55\0"
792		/* 946 */ "PMC5\0"
793		/* 951 */ "SF5\0"
794		/* 955 */ "VM5\0"
795		/* 959 */ "VMP5\0"
796		/* 964 */ "Q5\0"
797		/* 967 */ "V5\0"
798		/* 970 */ "SW5\0"
799		/* 974 */ "SX5\0"
800		/* 978 */ "SF16\0"
801		/* 983 */ "Q16\0"
802		/* 987 */ "V16\0"
803		/* 991 */ "SW16\0"
804		/* 996 */ "SX16\0"
805		/* 1001 */ "SF26\0"
806		/* 1006 */ "Q26\0"
807		/* 1010 */ "V26\0"
808		/* 1014 */ "SW26\0"
809		/* 1019 */ "SX26\0"
810		/* 1024 */ "SF36\0"
811		/* 1029 */ "V36\0"
812		/* 1033 */ "SW36\0"
813		/* 1038 */ "SX36\0"
814		/* 1043 */ "SF46\0"
815		/* 1048 */ "V46\0"
816		/* 1052 */ "SW46\0"
817		/* 1057 */ "SX46\0"
818		/* 1062 */ "SF56\0"
819		/* 1067 */ "V56\0"
820		/* 1071 */ "SW56\0"
821		/* 1076 */ "SX56\0"
822		/* 1081 */ "PMC6\0"
823		/* 1086 */ "SF6\0"
824		/* 1090 */ "VM6\0"
825		/* 1094 */ "VMP6\0"
826		/* 1099 */ "Q6\0"
827		/* 1102 */ "V6\0"
828		/* 1105 */ "SW6\0"
829		/* 1109 */ "SX6\0"
830		/* 1113 */ "SF17\0"
831		/* 1118 */ "Q17\0"
832		/* 1122 */ "V17\0"
833		/* 1126 */ "SW17\0"
834		/* 1131 */ "SX17\0"
835		/* 1136 */ "SF27\0"
836		/* 1141 */ "Q27\0"
837		/* 1145 */ "V27\0"
838		/* 1149 */ "SW27\0"
839		/* 1154 */ "SX27\0"
840		/* 1159 */ "SF37\0"
841		/* 1164 */ "V37\0"
842		/* 1168 */ "SW37\0"
843		/* 1173 */ "SX37\0"
844		/* 1178 */ "SF47\0"
845		/* 1183 */ "V47\0"
846		/* 1187 */ "SW47\0"
847		/* 1192 */ "SX47\0"
848		/* 1197 */ "SF57\0"
849		/* 1202 */ "V57\0"
850		/* 1206 */ "SW57\0"
851		/* 1211 */ "SX57\0"
852		/* 1216 */ "PMC7\0"
853		/* 1221 */ "SF7\0"
854		/* 1225 */ "VM7\0"
855		/* 1229 */ "VMP7\0"
856		/* 1234 */ "Q7\0"
857		/* 1237 */ "V7\0"
858		/* 1240 */ "SW7\0"
859		/* 1244 */ "SX7\0"
860		/* 1248 */ "SF18\0"
861		/* 1253 */ "Q18\0"
862		/* 1257 */ "V18\0"
863		/* 1261 */ "SW18\0"
864		/* 1266 */ "SX18\0"
865		/* 1271 */ "SF28\0"
866		/* 1276 */ "Q28\0"
867		/* 1280 */ "V28\0"
868		/* 1284 */ "SW28\0"
869		/* 1289 */ "SX28\0"
870		/* 1294 */ "SF38\0"
871		/* 1299 */ "V38\0"
872		/* 1303 */ "SW38\0"
873		/* 1308 */ "SX38\0"
874		/* 1313 */ "SF48\0"
875		/* 1318 */ "V48\0"
876		/* 1322 */ "SW48\0"
877		/* 1327 */ "SX48\0"
878		/* 1332 */ "SF58\0"
879		/* 1337 */ "V58\0"
880		/* 1341 */ "SW58\0"
881		/* 1346 */ "SX58\0"
882		/* 1351 */ "PMC8\0"
883		/* 1356 */ "SF8\0"
884		/* 1360 */ "VM8\0"
885		/* 1364 */ "Q8\0"
886		/* 1367 */ "V8\0"
887		/* 1370 */ "SW8\0"
888		/* 1374 */ "SX8\0"
889		/* 1378 */ "SF19\0"
890		/* 1383 */ "Q19\0"
891		/* 1387 */ "V19\0"
892		/* 1391 */ "SW19\0"
893		/* 1396 */ "SX19\0"
894		/* 1401 */ "SF29\0"
895		/* 1406 */ "Q29\0"
896		/* 1410 */ "V29\0"
897		/* 1414 */ "SW29\0"
898		/* 1419 */ "SX29\0"
899		/* 1424 */ "SF39\0"
900		/* 1429 */ "V39\0"
901		/* 1433 */ "SW39\0"
902		/* 1438 */ "SX39\0"
903		/* 1443 */ "SF49\0"
904		/* 1448 */ "V49\0"
905		/* 1452 */ "SW49\0"
906		/* 1457 */ "SX49\0"
907		/* 1462 */ "SF59\0"
908		/* 1467 */ "V59\0"
909		/* 1471 */ "SW59\0"
910		/* 1476 */ "SX59\0"
911		/* 1481 */ "PMC9\0"
912		/* 1486 */ "SF9\0"
913		/* 1490 */ "VM9\0"
914		/* 1494 */ "Q9\0"
915		/* 1497 */ "V9\0"
916		/* 1500 */ "SW9\0"
917		/* 1504 */ "SX9\0"
918		/* 1508 */ "USRCC\0"
919		/* 1514 */ "IC\0"
920		/* 1517 */ "VL\0"
921		/* 1520 */ "SAR\0"
922		/* 1524 */ "PMMR\0"
923		/* 1529 */ "PSW\0"
924		/* 1533 */ "VIX\0"
925		};
926		#ifdef __GNUC__
927		#pragma GCC diagnostic pop
928		#endif
929
930		extern const MCRegisterDesc VERegDesc[] = { // Descriptors
931		{ 5, 0, 0, 0, 0, 0 },
932		{ 1514, 2, 2, 2, 8192, 6 },
933		{ 1524, 2, 2, 2, 8193, 6 },
934		{ 1529, 2, 2, 2, 8194, 6 },
935		{ 1520, 2, 2, 2, 8195, 6 },
936		{ 1508, 2, 2, 2, 8196, 6 },
937		{ 1533, 2, 2, 2, 8197, 6 },
938		{ 1517, 2, 2, 2, 8198, 6 },
939		{ 137, 2, 2, 2, 8199, 6 },
940		{ 312, 2, 2, 2, 8200, 6 },
941		{ 483, 2, 2, 2, 8201, 6 },
942		{ 654, 2, 2, 2, 8202, 6 },
943		{ 806, 2, 2, 2, 8203, 6 },
944		{ 946, 2, 2, 2, 8204, 6 },
945		{ 1081, 2, 2, 2, 8205, 6 },
946		{ 1216, 2, 2, 2, 8206, 6 },
947		{ 1351, 2, 2, 2, 8207, 6 },
948		{ 1481, 2, 2, 2, 8208, 6 },
949		{ 0, 2, 2, 2, 8209, 6 },
950		{ 175, 2, 2, 2, 8210, 6 },
951		{ 350, 2, 2, 2, 8211, 6 },
952		{ 521, 2, 2, 2, 8212, 6 },
953		{ 692, 2, 2, 2, 8213, 6 },
954		{ 158, 2, 2, 2, 8214, 6 },
955		{ 333, 2, 2, 2, 8215, 6 },
956		{ 504, 2, 2, 2, 8216, 6 },
957		{ 675, 2, 2, 2, 8217, 6 },
958		{ 155, 198, 2, 6, 1732634, 0 },
959		{ 330, 205, 2, 6, 1732636, 0 },
960		{ 501, 212, 2, 6, 1732638, 0 },
961		{ 672, 219, 2, 6, 1732640, 0 },
962		{ 824, 226, 2, 6, 1732642, 0 },
963		{ 964, 233, 2, 6, 1732644, 0 },
964		{ 1099, 240, 2, 6, 1732646, 0 },
965		{ 1234, 247, 2, 6, 1732648, 0 },
966		{ 1364, 254, 2, 6, 1732650, 0 },
967		{ 1494, 261, 2, 6, 1732652, 0 },
968		{ 16, 268, 2, 6, 1732654, 0 },
969		{ 191, 275, 2, 6, 1732656, 0 },
970		{ 366, 282, 2, 6, 1732658, 0 },
971		{ 537, 289, 2, 6, 1732660, 0 },
972		{ 708, 296, 2, 6, 1732662, 0 },
973		{ 848, 303, 2, 6, 1732664, 0 },
974		{ 983, 310, 2, 6, 1732666, 0 },
975		{ 1118, 317, 2, 6, 1732668, 0 },
976		{ 1253, 324, 2, 6, 1732670, 0 },
977		{ 1383, 331, 2, 6, 1732672, 0 },
978		{ 39, 338, 2, 6, 1732674, 0 },
979		{ 214, 345, 2, 6, 1732676, 0 },
980		{ 389, 352, 2, 6, 1732678, 0 },
981		{ 560, 359, 2, 6, 1732680, 0 },
982		{ 731, 366, 2, 6, 1732682, 0 },
983		{ 871, 373, 2, 6, 1732684, 0 },
984		{ 1006, 380, 2, 6, 1732686, 0 },
985		{ 1141, 387, 2, 6, 1732688, 0 },
986		{ 1276, 394, 2, 6, 1732690, 0 },
987		{ 1406, 401, 2, 6, 1732692, 0 },
988		{ 62, 408, 2, 6, 1732694, 0 },
989		{ 237, 415, 2, 6, 1732696, 0 },
990		{ 142, 2, 195, 2, 8218, 6 },
991		{ 317, 2, 189, 2, 8219, 6 },
992		{ 488, 2, 189, 2, 8220, 6 },
993		{ 659, 2, 183, 2, 8221, 6 },
994		{ 811, 2, 183, 2, 8222, 6 },
995		{ 951, 2, 177, 2, 8223, 6 },
996		{ 1086, 2, 177, 2, 8224, 6 },
997		{ 1221, 2, 171, 2, 8225, 6 },
998		{ 1356, 2, 171, 2, 8226, 6 },
999		{ 1486, 2, 165, 2, 8227, 6 },
1000		{ 6, 2, 165, 2, 8228, 6 },
1001		{ 181, 2, 159, 2, 8229, 6 },
1002		{ 356, 2, 159, 2, 8230, 6 },
1003		{ 527, 2, 153, 2, 8231, 6 },
1004		{ 698, 2, 153, 2, 8232, 6 },
1005		{ 838, 2, 147, 2, 8233, 6 },
1006		{ 978, 2, 147, 2, 8234, 6 },
1007		{ 1113, 2, 141, 2, 8235, 6 },
1008		{ 1248, 2, 141, 2, 8236, 6 },
1009		{ 1378, 2, 135, 2, 8237, 6 },
1010		{ 34, 2, 135, 2, 8238, 6 },
1011		{ 209, 2, 129, 2, 8239, 6 },
1012		{ 384, 2, 129, 2, 8240, 6 },
1013		{ 555, 2, 123, 2, 8241, 6 },
1014		{ 726, 2, 123, 2, 8242, 6 },
1015		{ 866, 2, 117, 2, 8243, 6 },
1016		{ 1001, 2, 117, 2, 8244, 6 },
1017		{ 1136, 2, 111, 2, 8245, 6 },
1018		{ 1271, 2, 111, 2, 8246, 6 },
1019		{ 1401, 2, 105, 2, 8247, 6 },
1020		{ 57, 2, 105, 2, 8248, 6 },
1021		{ 232, 2, 99, 2, 8249, 6 },
1022		{ 407, 2, 99, 2, 8250, 6 },
1023		{ 578, 2, 93, 2, 8251, 6 },
1024		{ 749, 2, 93, 2, 8252, 6 },
1025		{ 889, 2, 87, 2, 8253, 6 },
1026		{ 1024, 2, 87, 2, 8254, 6 },
1027		{ 1159, 2, 81, 2, 8255, 6 },
1028		{ 1294, 2, 81, 2, 8256, 6 },
1029		{ 1424, 2, 75, 2, 8257, 6 },
1030		{ 80, 2, 75, 2, 8258, 6 },
1031		{ 255, 2, 69, 2, 8259, 6 },
1032		{ 426, 2, 69, 2, 8260, 6 },
1033		{ 597, 2, 63, 2, 8261, 6 },
1034		{ 768, 2, 63, 2, 8262, 6 },
1035		{ 908, 2, 57, 2, 8263, 6 },
1036		{ 1043, 2, 57, 2, 8264, 6 },
1037		{ 1178, 2, 51, 2, 8265, 6 },
1038		{ 1313, 2, 51, 2, 8266, 6 },
1039		{ 1443, 2, 45, 2, 8267, 6 },
1040		{ 99, 2, 45, 2, 8268, 6 },
1041		{ 274, 2, 39, 2, 8269, 6 },
1042		{ 445, 2, 39, 2, 8270, 6 },
1043		{ 616, 2, 33, 2, 8271, 6 },
1044		{ 787, 2, 33, 2, 8272, 6 },
1045		{ 927, 2, 27, 2, 8273, 6 },
1046		{ 1062, 2, 27, 2, 8274, 6 },
1047		{ 1197, 2, 21, 2, 8275, 6 },
1048		{ 1332, 2, 21, 2, 8276, 6 },
1049		{ 1462, 2, 15, 2, 8277, 6 },
1050		{ 118, 2, 15, 2, 8278, 6 },
1051		{ 293, 2, 9, 2, 8279, 6 },
1052		{ 464, 2, 9, 2, 8280, 6 },
1053		{ 635, 2, 3, 2, 8281, 6 },
1054		{ 167, 2, 192, 2, 8218, 6 },
1055		{ 342, 2, 186, 2, 8219, 6 },
1056		{ 513, 2, 186, 2, 8220, 6 },
1057		{ 684, 2, 180, 2, 8221, 6 },
1058		{ 830, 2, 180, 2, 8222, 6 },
1059		{ 970, 2, 174, 2, 8223, 6 },
1060		{ 1105, 2, 174, 2, 8224, 6 },
1061		{ 1240, 2, 168, 2, 8225, 6 },
1062		{ 1370, 2, 168, 2, 8226, 6 },
1063		{ 1500, 2, 162, 2, 8227, 6 },
1064		{ 24, 2, 162, 2, 8228, 6 },
1065		{ 199, 2, 156, 2, 8229, 6 },
1066		{ 374, 2, 156, 2, 8230, 6 },
1067		{ 545, 2, 150, 2, 8231, 6 },
1068		{ 716, 2, 150, 2, 8232, 6 },
1069		{ 856, 2, 144, 2, 8233, 6 },
1070		{ 991, 2, 144, 2, 8234, 6 },
1071		{ 1126, 2, 138, 2, 8235, 6 },
1072		{ 1261, 2, 138, 2, 8236, 6 },
1073		{ 1391, 2, 132, 2, 8237, 6 },
1074		{ 47, 2, 132, 2, 8238, 6 },
1075		{ 222, 2, 126, 2, 8239, 6 },
1076		{ 397, 2, 126, 2, 8240, 6 },
1077		{ 568, 2, 120, 2, 8241, 6 },
1078		{ 739, 2, 120, 2, 8242, 6 },
1079		{ 879, 2, 114, 2, 8243, 6 },
1080		{ 1014, 2, 114, 2, 8244, 6 },
1081		{ 1149, 2, 108, 2, 8245, 6 },
1082		{ 1284, 2, 108, 2, 8246, 6 },
1083		{ 1414, 2, 102, 2, 8247, 6 },
1084		{ 70, 2, 102, 2, 8248, 6 },
1085		{ 245, 2, 96, 2, 8249, 6 },
1086		{ 416, 2, 96, 2, 8250, 6 },
1087		{ 587, 2, 90, 2, 8251, 6 },
1088		{ 758, 2, 90, 2, 8252, 6 },
1089		{ 898, 2, 84, 2, 8253, 6 },
1090		{ 1033, 2, 84, 2, 8254, 6 },
1091		{ 1168, 2, 78, 2, 8255, 6 },
1092		{ 1303, 2, 78, 2, 8256, 6 },
1093		{ 1433, 2, 72, 2, 8257, 6 },
1094		{ 89, 2, 72, 2, 8258, 6 },
1095		{ 264, 2, 66, 2, 8259, 6 },
1096		{ 435, 2, 66, 2, 8260, 6 },
1097		{ 606, 2, 60, 2, 8261, 6 },
1098		{ 777, 2, 60, 2, 8262, 6 },
1099		{ 917, 2, 54, 2, 8263, 6 },
1100		{ 1052, 2, 54, 2, 8264, 6 },
1101		{ 1187, 2, 48, 2, 8265, 6 },
1102		{ 1322, 2, 48, 2, 8266, 6 },
1103		{ 1452, 2, 42, 2, 8267, 6 },
1104		{ 108, 2, 42, 2, 8268, 6 },
1105		{ 283, 2, 36, 2, 8269, 6 },
1106		{ 454, 2, 36, 2, 8270, 6 },
1107		{ 625, 2, 30, 2, 8271, 6 },
1108		{ 796, 2, 30, 2, 8272, 6 },
1109		{ 936, 2, 24, 2, 8273, 6 },
1110		{ 1071, 2, 24, 2, 8274, 6 },
1111		{ 1206, 2, 18, 2, 8275, 6 },
1112		{ 1341, 2, 18, 2, 8276, 6 },
1113		{ 1471, 2, 12, 2, 8277, 6 },
1114		{ 127, 2, 12, 2, 8278, 6 },
1115		{ 302, 2, 6, 2, 8279, 6 },
1116		{ 473, 2, 6, 2, 8280, 6 },
1117		{ 644, 2, 0, 2, 8281, 6 },
1118		{ 171, 202, 193, 0, 8218, 1 },
1119		{ 346, 202, 187, 0, 8219, 1 },
1120		{ 517, 202, 187, 0, 8220, 1 },
1121		{ 688, 202, 181, 0, 8221, 1 },
1122		{ 834, 202, 181, 0, 8222, 1 },
1123		{ 974, 202, 175, 0, 8223, 1 },
1124		{ 1109, 202, 175, 0, 8224, 1 },
1125		{ 1244, 202, 169, 0, 8225, 1 },
1126		{ 1374, 202, 169, 0, 8226, 1 },
1127		{ 1504, 202, 163, 0, 8227, 1 },
1128		{ 29, 202, 163, 0, 8228, 1 },
1129		{ 204, 202, 157, 0, 8229, 1 },
1130		{ 379, 202, 157, 0, 8230, 1 },
1131		{ 550, 202, 151, 0, 8231, 1 },
1132		{ 721, 202, 151, 0, 8232, 1 },
1133		{ 861, 202, 145, 0, 8233, 1 },
1134		{ 996, 202, 145, 0, 8234, 1 },
1135		{ 1131, 202, 139, 0, 8235, 1 },
1136		{ 1266, 202, 139, 0, 8236, 1 },
1137		{ 1396, 202, 133, 0, 8237, 1 },
1138		{ 52, 202, 133, 0, 8238, 1 },
1139		{ 227, 202, 127, 0, 8239, 1 },
1140		{ 402, 202, 127, 0, 8240, 1 },
1141		{ 573, 202, 121, 0, 8241, 1 },
1142		{ 744, 202, 121, 0, 8242, 1 },
1143		{ 884, 202, 115, 0, 8243, 1 },
1144		{ 1019, 202, 115, 0, 8244, 1 },
1145		{ 1154, 202, 109, 0, 8245, 1 },
1146		{ 1289, 202, 109, 0, 8246, 1 },
1147		{ 1419, 202, 103, 0, 8247, 1 },
1148		{ 75, 202, 103, 0, 8248, 1 },
1149		{ 250, 202, 97, 0, 8249, 1 },
1150		{ 421, 202, 97, 0, 8250, 1 },
1151		{ 592, 202, 91, 0, 8251, 1 },
1152		{ 763, 202, 91, 0, 8252, 1 },
1153		{ 903, 202, 85, 0, 8253, 1 },
1154		{ 1038, 202, 85, 0, 8254, 1 },
1155		{ 1173, 202, 79, 0, 8255, 1 },
1156		{ 1308, 202, 79, 0, 8256, 1 },
1157		{ 1438, 202, 73, 0, 8257, 1 },
1158		{ 94, 202, 73, 0, 8258, 1 },
1159		{ 269, 202, 67, 0, 8259, 1 },
1160		{ 440, 202, 67, 0, 8260, 1 },
1161		{ 611, 202, 61, 0, 8261, 1 },
1162		{ 782, 202, 61, 0, 8262, 1 },
1163		{ 922, 202, 55, 0, 8263, 1 },
1164		{ 1057, 202, 55, 0, 8264, 1 },
1165		{ 1192, 202, 49, 0, 8265, 1 },
1166		{ 1327, 202, 49, 0, 8266, 1 },
1167		{ 1457, 202, 43, 0, 8267, 1 },
1168		{ 113, 202, 43, 0, 8268, 1 },
1169		{ 288, 202, 37, 0, 8269, 1 },
1170		{ 459, 202, 37, 0, 8270, 1 },
1171		{ 630, 202, 31, 0, 8271, 1 },
1172		{ 801, 202, 31, 0, 8272, 1 },
1173		{ 941, 202, 25, 0, 8273, 1 },
1174		{ 1076, 202, 25, 0, 8274, 1 },
1175		{ 1211, 202, 19, 0, 8275, 1 },
1176		{ 1346, 202, 19, 0, 8276, 1 },
1177		{ 1476, 202, 13, 0, 8277, 1 },
1178		{ 132, 202, 13, 0, 8278, 1 },
1179		{ 307, 202, 7, 0, 8279, 1 },
1180		{ 478, 202, 7, 0, 8280, 1 },
1181		{ 649, 202, 1, 0, 8281, 1 },
1182		{ 164, 2, 2, 2, 8282, 6 },
1183		{ 339, 2, 2, 2, 8283, 6 },
1184		{ 510, 2, 2, 2, 8284, 6 },
1185		{ 681, 2, 2, 2, 8285, 6 },
1186		{ 827, 2, 2, 2, 8286, 6 },
1187		{ 967, 2, 2, 2, 8287, 6 },
1188		{ 1102, 2, 2, 2, 8288, 6 },
1189		{ 1237, 2, 2, 2, 8289, 6 },
1190		{ 1367, 2, 2, 2, 8290, 6 },
1191		{ 1497, 2, 2, 2, 8291, 6 },
1192		{ 20, 2, 2, 2, 8292, 6 },
1193		{ 195, 2, 2, 2, 8293, 6 },
1194		{ 370, 2, 2, 2, 8294, 6 },
1195		{ 541, 2, 2, 2, 8295, 6 },
1196		{ 712, 2, 2, 2, 8296, 6 },
1197		{ 852, 2, 2, 2, 8297, 6 },
1198		{ 987, 2, 2, 2, 8298, 6 },
1199		{ 1122, 2, 2, 2, 8299, 6 },
1200		{ 1257, 2, 2, 2, 8300, 6 },
1201		{ 1387, 2, 2, 2, 8301, 6 },
1202		{ 43, 2, 2, 2, 8302, 6 },
1203		{ 218, 2, 2, 2, 8303, 6 },
1204		{ 393, 2, 2, 2, 8304, 6 },
1205		{ 564, 2, 2, 2, 8305, 6 },
1206		{ 735, 2, 2, 2, 8306, 6 },
1207		{ 875, 2, 2, 2, 8307, 6 },
1208		{ 1010, 2, 2, 2, 8308, 6 },
1209		{ 1145, 2, 2, 2, 8309, 6 },
1210		{ 1280, 2, 2, 2, 8310, 6 },
1211		{ 1410, 2, 2, 2, 8311, 6 },
1212		{ 66, 2, 2, 2, 8312, 6 },
1213		{ 241, 2, 2, 2, 8313, 6 },
1214		{ 412, 2, 2, 2, 8314, 6 },
1215		{ 583, 2, 2, 2, 8315, 6 },
1216		{ 754, 2, 2, 2, 8316, 6 },
1217		{ 894, 2, 2, 2, 8317, 6 },
1218		{ 1029, 2, 2, 2, 8318, 6 },
1219		{ 1164, 2, 2, 2, 8319, 6 },
1220		{ 1299, 2, 2, 2, 8320, 6 },
1221		{ 1429, 2, 2, 2, 8321, 6 },
1222		{ 85, 2, 2, 2, 8322, 6 },
1223		{ 260, 2, 2, 2, 8323, 6 },
1224		{ 431, 2, 2, 2, 8324, 6 },
1225		{ 602, 2, 2, 2, 8325, 6 },
1226		{ 773, 2, 2, 2, 8326, 6 },
1227		{ 913, 2, 2, 2, 8327, 6 },
1228		{ 1048, 2, 2, 2, 8328, 6 },
1229		{ 1183, 2, 2, 2, 8329, 6 },
1230		{ 1318, 2, 2, 2, 8330, 6 },
1231		{ 1448, 2, 2, 2, 8331, 6 },
1232		{ 104, 2, 2, 2, 8332, 6 },
1233		{ 279, 2, 2, 2, 8333, 6 },
1234		{ 450, 2, 2, 2, 8334, 6 },
1235		{ 621, 2, 2, 2, 8335, 6 },
1236		{ 792, 2, 2, 2, 8336, 6 },
1237		{ 932, 2, 2, 2, 8337, 6 },
1238		{ 1067, 2, 2, 2, 8338, 6 },
1239		{ 1202, 2, 2, 2, 8339, 6 },
1240		{ 1337, 2, 2, 2, 8340, 6 },
1241		{ 1467, 2, 2, 2, 8341, 6 },
1242		{ 123, 2, 2, 2, 8342, 6 },
1243		{ 298, 2, 2, 2, 8343, 6 },
1244		{ 469, 2, 2, 2, 8344, 6 },
1245		{ 640, 2, 2, 2, 8345, 6 },
1246		{ 146, 2, 2, 2, 8346, 6 },
1247		{ 321, 2, 2, 2, 8347, 6 },
1248		{ 492, 2, 457, 2, 8348, 6 },
1249		{ 663, 2, 455, 2, 8349, 6 },
1250		{ 815, 2, 455, 2, 8350, 6 },
1251		{ 955, 2, 453, 2, 8351, 6 },
1252		{ 1090, 2, 453, 2, 8352, 6 },
1253		{ 1225, 2, 451, 2, 8353, 6 },
1254		{ 1360, 2, 451, 2, 8354, 6 },
1255		{ 1490, 2, 449, 2, 8355, 6 },
1256		{ 11, 2, 449, 2, 8356, 6 },
1257		{ 186, 2, 447, 2, 8357, 6 },
1258		{ 361, 2, 447, 2, 8358, 6 },
1259		{ 532, 2, 445, 2, 8359, 6 },
1260		{ 703, 2, 445, 2, 8360, 6 },
1261		{ 843, 2, 443, 2, 8361, 6 },
1262		{ 150, 2, 2, 2, 8362, 6 },
1263		{ 325, 422, 2, 3, 1732764, 3 },
1264		{ 496, 425, 2, 3, 1732766, 3 },
1265		{ 667, 428, 2, 3, 1732768, 3 },
1266		{ 819, 431, 2, 3, 1732770, 3 },
1267		{ 959, 434, 2, 3, 1732772, 3 },
1268		{ 1094, 437, 2, 3, 1732774, 3 },
1269		{ 1229, 440, 2, 3, 1732776, 3 },
1270		};
1271
1272		extern const MCPhysReg VERegUnitRoots[][2] = {
1273		{ VE::IC },
1274		{ VE::PMMR },
1275		{ VE::PSW },
1276		{ VE::SAR },
1277		{ VE::USRCC },
1278		{ VE::VIX },
1279		{ VE::VL },
1280		{ VE::PMC0 },
1281		{ VE::PMC1 },
1282		{ VE::PMC2 },
1283		{ VE::PMC3 },
1284		{ VE::PMC4 },
1285		{ VE::PMC5 },
1286		{ VE::PMC6 },
1287		{ VE::PMC7 },
1288		{ VE::PMC8 },
1289		{ VE::PMC9 },
1290		{ VE::PMC10 },
1291		{ VE::PMC11 },
1292		{ VE::PMC12 },
1293		{ VE::PMC13 },
1294		{ VE::PMC14 },
1295		{ VE::PMCR0 },
1296		{ VE::PMCR1 },
1297		{ VE::PMCR2 },
1298		{ VE::PMCR3 },
1299		{ VE::SW0, VE::SF0 },
1300		{ VE::SW1, VE::SF1 },
1301		{ VE::SW2, VE::SF2 },
1302		{ VE::SW3, VE::SF3 },
1303		{ VE::SW4, VE::SF4 },
1304		{ VE::SW5, VE::SF5 },
1305		{ VE::SW6, VE::SF6 },
1306		{ VE::SW7, VE::SF7 },
1307		{ VE::SW8, VE::SF8 },
1308		{ VE::SW9, VE::SF9 },
1309		{ VE::SW10, VE::SF10 },
1310		{ VE::SW11, VE::SF11 },
1311		{ VE::SW12, VE::SF12 },
1312		{ VE::SW13, VE::SF13 },
1313		{ VE::SW14, VE::SF14 },
1314		{ VE::SW15, VE::SF15 },
1315		{ VE::SW16, VE::SF16 },
1316		{ VE::SW17, VE::SF17 },
1317		{ VE::SW18, VE::SF18 },
1318		{ VE::SW19, VE::SF19 },
1319		{ VE::SW20, VE::SF20 },
1320		{ VE::SW21, VE::SF21 },
1321		{ VE::SW22, VE::SF22 },
1322		{ VE::SW23, VE::SF23 },
1323		{ VE::SW24, VE::SF24 },
1324		{ VE::SW25, VE::SF25 },
1325		{ VE::SW26, VE::SF26 },
1326		{ VE::SW27, VE::SF27 },
1327		{ VE::SW28, VE::SF28 },
1328		{ VE::SW29, VE::SF29 },
1329		{ VE::SW30, VE::SF30 },
1330		{ VE::SW31, VE::SF31 },
1331		{ VE::SW32, VE::SF32 },
1332		{ VE::SW33, VE::SF33 },
1333		{ VE::SW34, VE::SF34 },
1334		{ VE::SW35, VE::SF35 },
1335		{ VE::SW36, VE::SF36 },
1336		{ VE::SW37, VE::SF37 },
1337		{ VE::SW38, VE::SF38 },
1338		{ VE::SW39, VE::SF39 },
1339		{ VE::SW40, VE::SF40 },
1340		{ VE::SW41, VE::SF41 },
1341		{ VE::SW42, VE::SF42 },
1342		{ VE::SW43, VE::SF43 },
1343		{ VE::SW44, VE::SF44 },
1344		{ VE::SW45, VE::SF45 },
1345		{ VE::SW46, VE::SF46 },
1346		{ VE::SW47, VE::SF47 },
1347		{ VE::SW48, VE::SF48 },
1348		{ VE::SW49, VE::SF49 },
1349		{ VE::SW50, VE::SF50 },
1350		{ VE::SW51, VE::SF51 },
1351		{ VE::SW52, VE::SF52 },
1352		{ VE::SW53, VE::SF53 },
1353		{ VE::SW54, VE::SF54 },
1354		{ VE::SW55, VE::SF55 },
1355		{ VE::SW56, VE::SF56 },
1356		{ VE::SW57, VE::SF57 },
1357		{ VE::SW58, VE::SF58 },
1358		{ VE::SW59, VE::SF59 },
1359		{ VE::SW60, VE::SF60 },
1360		{ VE::SW61, VE::SF61 },
1361		{ VE::SW62, VE::SF62 },
1362		{ VE::SW63, VE::SF63 },
1363		{ VE::V0 },
1364		{ VE::V1 },
1365		{ VE::V2 },
1366		{ VE::V3 },
1367		{ VE::V4 },
1368		{ VE::V5 },
1369		{ VE::V6 },
1370		{ VE::V7 },
1371		{ VE::V8 },
1372		{ VE::V9 },
1373		{ VE::V10 },
1374		{ VE::V11 },
1375		{ VE::V12 },
1376		{ VE::V13 },
1377		{ VE::V14 },
1378		{ VE::V15 },
1379		{ VE::V16 },
1380		{ VE::V17 },
1381		{ VE::V18 },
1382		{ VE::V19 },
1383		{ VE::V20 },
1384		{ VE::V21 },
1385		{ VE::V22 },
1386		{ VE::V23 },
1387		{ VE::V24 },
1388		{ VE::V25 },
1389		{ VE::V26 },
1390		{ VE::V27 },
1391		{ VE::V28 },
1392		{ VE::V29 },
1393		{ VE::V30 },
1394		{ VE::V31 },
1395		{ VE::V32 },
1396		{ VE::V33 },
1397		{ VE::V34 },
1398		{ VE::V35 },
1399		{ VE::V36 },
1400		{ VE::V37 },
1401		{ VE::V38 },
1402		{ VE::V39 },
1403		{ VE::V40 },
1404		{ VE::V41 },
1405		{ VE::V42 },
1406		{ VE::V43 },
1407		{ VE::V44 },
1408		{ VE::V45 },
1409		{ VE::V46 },
1410		{ VE::V47 },
1411		{ VE::V48 },
1412		{ VE::V49 },
1413		{ VE::V50 },
1414		{ VE::V51 },
1415		{ VE::V52 },
1416		{ VE::V53 },
1417		{ VE::V54 },
1418		{ VE::V55 },
1419		{ VE::V56 },
1420		{ VE::V57 },
1421		{ VE::V58 },
1422		{ VE::V59 },
1423		{ VE::V60 },
1424		{ VE::V61 },
1425		{ VE::V62 },
1426		{ VE::V63 },
1427		{ VE::VM0 },
1428		{ VE::VM1 },
1429		{ VE::VM2 },
1430		{ VE::VM3 },
1431		{ VE::VM4 },
1432		{ VE::VM5 },
1433		{ VE::VM6 },
1434		{ VE::VM7 },
1435		{ VE::VM8 },
1436		{ VE::VM9 },
1437		{ VE::VM10 },
1438		{ VE::VM11 },
1439		{ VE::VM12 },
1440		{ VE::VM13 },
1441		{ VE::VM14 },
1442		{ VE::VM15 },
1443		{ VE::VMP0 },
1444		};
1445
1446		namespace { // Register classes...
1447		// F32 Register Class...
1448		const MCPhysReg F32[] = {
1449		VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, VE::SF7, VE::SF34, VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, VE::SF63, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33,
1450		};
1451
1452		// F32 Bit set.
1453		const uint8_t F32Bits[] = {
1454		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1455		};
1456
1457		// I32 Register Class...
1458		const MCPhysReg I32[] = {
1459		VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, VE::SW7, VE::SW34, VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, VE::SW63, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33,
1460		};
1461
1462		// I32 Bit set.
1463		const uint8_t I32Bits[] = {
1464		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1465		};
1466
1467		// VLS Register Class...
1468		const MCPhysReg VLS[] = {
1469		VE::VL,
1470		};
1471
1472		// VLS Bit set.
1473		const uint8_t VLSBits[] = {
1474		0x80,
1475		};
1476
1477		// I64 Register Class...
1478		const MCPhysReg I64[] = {
1479		VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, VE::SX63, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33,
1480		};
1481
1482		// I64 Bit set.
1483		const uint8_t I64Bits[] = {
1484		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1485		};
1486
1487		// MISC Register Class...
1488		const MCPhysReg MISC[] = {
1489		VE::USRCC, VE::PSW, VE::SAR, VE::PMMR, VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, VE::PMC12, VE::PMC13, VE::PMC14,
1490		};
1491
1492		// MISC Bit set.
1493		const uint8_t MISCBits[] = {
1494		0x3c, 0xff, 0xff, 0x07,
1495		};
1496
1497		// F128 Register Class...
1498		const MCPhysReg F128[] = {
1499		VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31, VE::Q4, VE::Q5, VE::Q6, VE::Q7, VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15, VE::Q16,
1500		};
1501
1502		// F128 Bit set.
1503		const uint8_t F128Bits[] = {
1504		0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1505		};
1506
1507		// VM Register Class...
1508		const MCPhysReg VM[] = {
1509		VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15,
1510		};
1511
1512		// VM Bit set.
1513		const uint8_t VMBits[] = {
1514		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1515		};
1516
1517		// VM512 Register Class...
1518		const MCPhysReg VM512[] = {
1519		VE::VMP0, VE::VMP1, VE::VMP2, VE::VMP3, VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7,
1520		};
1521
1522		// VM512 Bit set.
1523		const uint8_t VM512Bits[] = {
1524		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1525		};
1526
1527		// VM512_with_sub_vm_even Register Class...
1528		const MCPhysReg VM512_with_sub_vm_even[] = {
1529		VE::VMP1, VE::VMP2, VE::VMP3, VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7,
1530		};
1531
1532		// VM512_with_sub_vm_even Bit set.
1533		const uint8_t VM512_with_sub_vm_evenBits[] = {
1534		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1535		};
1536
1537		// V64 Register Class...
1538		const MCPhysReg V64[] = {
1539		VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VIX,
1540		};
1541
1542		// V64 Bit set.
1543		const uint8_t V64Bits[] = {
1544		0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1545		};
1546
1547		} // end anonymous namespace
1548
1549
1550		#ifdef __GNUC__
1551		#pragma GCC diagnostic push
1552		#pragma GCC diagnostic ignored "-Woverlength-strings"
1553		#endif
1554		extern const char VERegClassStrings[] = {
1555		/* 0 */ "VM512\0"
1556		/* 6 */ "F32\0"
1557		/* 10 */ "I32\0"
1558		/* 14 */ "I64\0"
1559		/* 18 */ "V64\0"
1560		/* 22 */ "F128\0"
1561		/* 27 */ "MISC\0"
1562		/* 32 */ "VM\0"
1563		/* 35 */ "VLS\0"
1564		/* 39 */ "VM512_with_sub_vm_even\0"
1565		};
1566		#ifdef __GNUC__
1567		#pragma GCC diagnostic pop
1568		#endif
1569
1570		extern const MCRegisterClass VEMCRegisterClasses[] = {
1571		{ F32, F32Bits, 6, 64, sizeof(F32Bits), VE::F32RegClassID, 32, 1, true },
1572		{ I32, I32Bits, 10, 64, sizeof(I32Bits), VE::I32RegClassID, 32, 1, true },
1573		{ VLS, VLSBits, 35, 1, sizeof(VLSBits), VE::VLSRegClassID, 32, 1, true },
1574		{ I64, I64Bits, 14, 64, sizeof(I64Bits), VE::I64RegClassID, 64, 1, true },
1575		{ MISC, MISCBits, 27, 23, sizeof(MISCBits), VE::MISCRegClassID, 64, 1, true },
1576		{ F128, F128Bits, 22, 32, sizeof(F128Bits), VE::F128RegClassID, 128, 1, true },
1577		{ VM, VMBits, 32, 16, sizeof(VMBits), VE::VMRegClassID, 256, 1, true },
1578		{ VM512, VM512Bits, 0, 8, sizeof(VM512Bits), VE::VM512RegClassID, 512, 1, true },
1579		{ VM512_with_sub_vm_even, VM512_with_sub_vm_evenBits, 39, 7, sizeof(VM512_with_sub_vm_evenBits), VE::VM512_with_sub_vm_evenRegClassID, 512, 1, true },
1580		{ V64, V64Bits, 18, 65, sizeof(V64Bits), VE::V64RegClassID, 16384, 1, true },
1581		};
1582
1583		// VE Dwarf<->LLVM register mappings.
1584		extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[] = {
1585		{ 0U, VE::SX0 },
1586		{ 1U, VE::SX1 },
1587		{ 2U, VE::SX2 },
1588		{ 3U, VE::SX3 },
1589		{ 4U, VE::SX4 },
1590		{ 5U, VE::SX5 },
1591		{ 6U, VE::SX6 },
1592		{ 7U, VE::SX7 },
1593		{ 8U, VE::SX8 },
1594		{ 9U, VE::SX9 },
1595		{ 10U, VE::SX10 },
1596		{ 11U, VE::SX11 },
1597		{ 12U, VE::SX12 },
1598		{ 13U, VE::SX13 },
1599		{ 14U, VE::SX14 },
1600		{ 15U, VE::SX15 },
1601		{ 16U, VE::SX16 },
1602		{ 17U, VE::SX17 },
1603		{ 18U, VE::SX18 },
1604		{ 19U, VE::SX19 },
1605		{ 20U, VE::SX20 },
1606		{ 21U, VE::SX21 },
1607		{ 22U, VE::SX22 },
1608		{ 23U, VE::SX23 },
1609		{ 24U, VE::SX24 },
1610		{ 25U, VE::SX25 },
1611		{ 26U, VE::SX26 },
1612		{ 27U, VE::SX27 },
1613		{ 28U, VE::SX28 },
1614		{ 29U, VE::SX29 },
1615		{ 30U, VE::SX30 },
1616		{ 31U, VE::SX31 },
1617		{ 32U, VE::SX32 },
1618		{ 33U, VE::SX33 },
1619		{ 34U, VE::SX34 },
1620		{ 35U, VE::SX35 },
1621		{ 36U, VE::SX36 },
1622		{ 37U, VE::SX37 },
1623		{ 38U, VE::SX38 },
1624		{ 39U, VE::SX39 },
1625		{ 40U, VE::SX40 },
1626		{ 41U, VE::SX41 },
1627		{ 42U, VE::SX42 },
1628		{ 43U, VE::SX43 },
1629		{ 44U, VE::SX44 },
1630		{ 45U, VE::SX45 },
1631		{ 46U, VE::SX46 },
1632		{ 47U, VE::SX47 },
1633		{ 48U, VE::SX48 },
1634		{ 49U, VE::SX49 },
1635		{ 50U, VE::SX50 },
1636		{ 51U, VE::SX51 },
1637		{ 52U, VE::SX52 },
1638		{ 53U, VE::SX53 },
1639		{ 54U, VE::SX54 },
1640		{ 55U, VE::SX55 },
1641		{ 56U, VE::SX56 },
1642		{ 57U, VE::SX57 },
1643		{ 58U, VE::SX58 },
1644		{ 59U, VE::SX59 },
1645		{ 60U, VE::SX60 },
1646		{ 61U, VE::SX61 },
1647		{ 62U, VE::SX62 },
1648		{ 63U, VE::SX63 },
1649		{ 64U, VE::V0 },
1650		{ 65U, VE::V1 },
1651		{ 66U, VE::V2 },
1652		{ 67U, VE::V3 },
1653		{ 68U, VE::V4 },
1654		{ 69U, VE::V5 },
1655		{ 70U, VE::V6 },
1656		{ 71U, VE::V7 },
1657		{ 72U, VE::V8 },
1658		{ 73U, VE::V9 },
1659		{ 74U, VE::V10 },
1660		{ 75U, VE::V11 },
1661		{ 76U, VE::V12 },
1662		{ 77U, VE::V13 },
1663		{ 78U, VE::V14 },
1664		{ 79U, VE::V15 },
1665		{ 80U, VE::V16 },
1666		{ 81U, VE::V17 },
1667		{ 82U, VE::V18 },
1668		{ 83U, VE::V19 },
1669		{ 84U, VE::V20 },
1670		{ 85U, VE::V21 },
1671		{ 86U, VE::V22 },
1672		{ 87U, VE::V23 },
1673		{ 88U, VE::V24 },
1674		{ 89U, VE::V25 },
1675		{ 90U, VE::V26 },
1676		{ 91U, VE::V27 },
1677		{ 92U, VE::V28 },
1678		{ 93U, VE::V29 },
1679		{ 94U, VE::V30 },
1680		{ 95U, VE::V31 },
1681		{ 96U, VE::V32 },
1682		{ 97U, VE::V33 },
1683		{ 98U, VE::V34 },
1684		{ 99U, VE::V35 },
1685		{ 100U, VE::V36 },
1686		{ 101U, VE::V37 },
1687		{ 102U, VE::V38 },
1688		{ 103U, VE::V39 },
1689		{ 104U, VE::V40 },
1690		{ 105U, VE::V41 },
1691		{ 106U, VE::V42 },
1692		{ 107U, VE::V43 },
1693		{ 108U, VE::V44 },
1694		{ 109U, VE::V45 },
1695		{ 110U, VE::V46 },
1696		{ 111U, VE::V47 },
1697		{ 112U, VE::V48 },
1698		{ 113U, VE::V49 },
1699		{ 114U, VE::V50 },
1700		{ 115U, VE::V51 },
1701		{ 116U, VE::V52 },
1702		{ 117U, VE::V53 },
1703		{ 118U, VE::V54 },
1704		{ 119U, VE::V55 },
1705		{ 120U, VE::V56 },
1706		{ 121U, VE::V57 },
1707		{ 122U, VE::V58 },
1708		{ 123U, VE::V59 },
1709		{ 124U, VE::V60 },
1710		{ 125U, VE::V61 },
1711		{ 126U, VE::V62 },
1712		{ 127U, VE::V63 },
1713		{ 128U, VE::VM0 },
1714		{ 129U, VE::VM1 },
1715		{ 130U, VE::VM2 },
1716		{ 131U, VE::VM3 },
1717		{ 132U, VE::VM4 },
1718		{ 133U, VE::VM5 },
1719		{ 134U, VE::VM6 },
1720		{ 135U, VE::VM7 },
1721		{ 136U, VE::VM8 },
1722		{ 137U, VE::VM9 },
1723		{ 138U, VE::VM10 },
1724		{ 139U, VE::VM11 },
1725		{ 140U, VE::VM12 },
1726		{ 141U, VE::VM13 },
1727		{ 142U, VE::VM14 },
1728		{ 143U, VE::VM15 },
1729		};
1730		extern const unsigned VEDwarfFlavour0Dwarf2LSize = std::size(VEDwarfFlavour0Dwarf2L);
1731
1732		extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[] = {
1733		{ 0U, VE::SX0 },
1734		{ 1U, VE::SX1 },
1735		{ 2U, VE::SX2 },
1736		{ 3U, VE::SX3 },
1737		{ 4U, VE::SX4 },
1738		{ 5U, VE::SX5 },
1739		{ 6U, VE::SX6 },
1740		{ 7U, VE::SX7 },
1741		{ 8U, VE::SX8 },
1742		{ 9U, VE::SX9 },
1743		{ 10U, VE::SX10 },
1744		{ 11U, VE::SX11 },
1745		{ 12U, VE::SX12 },
1746		{ 13U, VE::SX13 },
1747		{ 14U, VE::SX14 },
1748		{ 15U, VE::SX15 },
1749		{ 16U, VE::SX16 },
1750		{ 17U, VE::SX17 },
1751		{ 18U, VE::SX18 },
1752		{ 19U, VE::SX19 },
1753		{ 20U, VE::SX20 },
1754		{ 21U, VE::SX21 },
1755		{ 22U, VE::SX22 },
1756		{ 23U, VE::SX23 },
1757		{ 24U, VE::SX24 },
1758		{ 25U, VE::SX25 },
1759		{ 26U, VE::SX26 },
1760		{ 27U, VE::SX27 },
1761		{ 28U, VE::SX28 },
1762		{ 29U, VE::SX29 },
1763		{ 30U, VE::SX30 },
1764		{ 31U, VE::SX31 },
1765		{ 32U, VE::SX32 },
1766		{ 33U, VE::SX33 },
1767		{ 34U, VE::SX34 },
1768		{ 35U, VE::SX35 },
1769		{ 36U, VE::SX36 },
1770		{ 37U, VE::SX37 },
1771		{ 38U, VE::SX38 },
1772		{ 39U, VE::SX39 },
1773		{ 40U, VE::SX40 },
1774		{ 41U, VE::SX41 },
1775		{ 42U, VE::SX42 },
1776		{ 43U, VE::SX43 },
1777		{ 44U, VE::SX44 },
1778		{ 45U, VE::SX45 },
1779		{ 46U, VE::SX46 },
1780		{ 47U, VE::SX47 },
1781		{ 48U, VE::SX48 },
1782		{ 49U, VE::SX49 },
1783		{ 50U, VE::SX50 },
1784		{ 51U, VE::SX51 },
1785		{ 52U, VE::SX52 },
1786		{ 53U, VE::SX53 },
1787		{ 54U, VE::SX54 },
1788		{ 55U, VE::SX55 },
1789		{ 56U, VE::SX56 },
1790		{ 57U, VE::SX57 },
1791		{ 58U, VE::SX58 },
1792		{ 59U, VE::SX59 },
1793		{ 60U, VE::SX60 },
1794		{ 61U, VE::SX61 },
1795		{ 62U, VE::SX62 },
1796		{ 63U, VE::SX63 },
1797		{ 64U, VE::V0 },
1798		{ 65U, VE::V1 },
1799		{ 66U, VE::V2 },
1800		{ 67U, VE::V3 },
1801		{ 68U, VE::V4 },
1802		{ 69U, VE::V5 },
1803		{ 70U, VE::V6 },
1804		{ 71U, VE::V7 },
1805		{ 72U, VE::V8 },
1806		{ 73U, VE::V9 },
1807		{ 74U, VE::V10 },
1808		{ 75U, VE::V11 },
1809		{ 76U, VE::V12 },
1810		{ 77U, VE::V13 },
1811		{ 78U, VE::V14 },
1812		{ 79U, VE::V15 },
1813		{ 80U, VE::V16 },
1814		{ 81U, VE::V17 },
1815		{ 82U, VE::V18 },
1816		{ 83U, VE::V19 },
1817		{ 84U, VE::V20 },
1818		{ 85U, VE::V21 },
1819		{ 86U, VE::V22 },
1820		{ 87U, VE::V23 },
1821		{ 88U, VE::V24 },
1822		{ 89U, VE::V25 },
1823		{ 90U, VE::V26 },
1824		{ 91U, VE::V27 },
1825		{ 92U, VE::V28 },
1826		{ 93U, VE::V29 },
1827		{ 94U, VE::V30 },
1828		{ 95U, VE::V31 },
1829		{ 96U, VE::V32 },
1830		{ 97U, VE::V33 },
1831		{ 98U, VE::V34 },
1832		{ 99U, VE::V35 },
1833		{ 100U, VE::V36 },
1834		{ 101U, VE::V37 },
1835		{ 102U, VE::V38 },
1836		{ 103U, VE::V39 },
1837		{ 104U, VE::V40 },
1838		{ 105U, VE::V41 },
1839		{ 106U, VE::V42 },
1840		{ 107U, VE::V43 },
1841		{ 108U, VE::V44 },
1842		{ 109U, VE::V45 },
1843		{ 110U, VE::V46 },
1844		{ 111U, VE::V47 },
1845		{ 112U, VE::V48 },
1846		{ 113U, VE::V49 },
1847		{ 114U, VE::V50 },
1848		{ 115U, VE::V51 },
1849		{ 116U, VE::V52 },
1850		{ 117U, VE::V53 },
1851		{ 118U, VE::V54 },
1852		{ 119U, VE::V55 },
1853		{ 120U, VE::V56 },
1854		{ 121U, VE::V57 },
1855		{ 122U, VE::V58 },
1856		{ 123U, VE::V59 },
1857		{ 124U, VE::V60 },
1858		{ 125U, VE::V61 },
1859		{ 126U, VE::V62 },
1860		{ 127U, VE::V63 },
1861		{ 128U, VE::VM0 },
1862		{ 129U, VE::VM1 },
1863		{ 130U, VE::VM2 },
1864		{ 131U, VE::VM3 },
1865		{ 132U, VE::VM4 },
1866		{ 133U, VE::VM5 },
1867		{ 134U, VE::VM6 },
1868		{ 135U, VE::VM7 },
1869		{ 136U, VE::VM8 },
1870		{ 137U, VE::VM9 },
1871		{ 138U, VE::VM10 },
1872		{ 139U, VE::VM11 },
1873		{ 140U, VE::VM12 },
1874		{ 141U, VE::VM13 },
1875		{ 142U, VE::VM14 },
1876		{ 143U, VE::VM15 },
1877		};
1878		extern const unsigned VEEHFlavour0Dwarf2LSize = std::size(VEEHFlavour0Dwarf2L);
1879
1880		extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[] = {
1881		{ VE::SF0, 0U },
1882		{ VE::SF1, 1U },
1883		{ VE::SF2, 2U },
1884		{ VE::SF3, 3U },
1885		{ VE::SF4, 4U },
1886		{ VE::SF5, 5U },
1887		{ VE::SF6, 6U },
1888		{ VE::SF7, 7U },
1889		{ VE::SF8, 8U },
1890		{ VE::SF9, 9U },
1891		{ VE::SF10, 10U },
1892		{ VE::SF11, 11U },
1893		{ VE::SF12, 12U },
1894		{ VE::SF13, 13U },
1895		{ VE::SF14, 14U },
1896		{ VE::SF15, 15U },
1897		{ VE::SF16, 16U },
1898		{ VE::SF17, 17U },
1899		{ VE::SF18, 18U },
1900		{ VE::SF19, 19U },
1901		{ VE::SF20, 20U },
1902		{ VE::SF21, 21U },
1903		{ VE::SF22, 22U },
1904		{ VE::SF23, 23U },
1905		{ VE::SF24, 24U },
1906		{ VE::SF25, 25U },
1907		{ VE::SF26, 26U },
1908		{ VE::SF27, 27U },
1909		{ VE::SF28, 28U },
1910		{ VE::SF29, 29U },
1911		{ VE::SF30, 30U },
1912		{ VE::SF31, 31U },
1913		{ VE::SF32, 32U },
1914		{ VE::SF33, 33U },
1915		{ VE::SF34, 34U },
1916		{ VE::SF35, 35U },
1917		{ VE::SF36, 36U },
1918		{ VE::SF37, 37U },
1919		{ VE::SF38, 38U },
1920		{ VE::SF39, 39U },
1921		{ VE::SF40, 40U },
1922		{ VE::SF41, 41U },
1923		{ VE::SF42, 42U },
1924		{ VE::SF43, 43U },
1925		{ VE::SF44, 44U },
1926		{ VE::SF45, 45U },
1927		{ VE::SF46, 46U },
1928		{ VE::SF47, 47U },
1929		{ VE::SF48, 48U },
1930		{ VE::SF49, 49U },
1931		{ VE::SF50, 50U },
1932		{ VE::SF51, 51U },
1933		{ VE::SF52, 52U },
1934		{ VE::SF53, 53U },
1935		{ VE::SF54, 54U },
1936		{ VE::SF55, 55U },
1937		{ VE::SF56, 56U },
1938		{ VE::SF57, 57U },
1939		{ VE::SF58, 58U },
1940		{ VE::SF59, 59U },
1941		{ VE::SF60, 60U },
1942		{ VE::SF61, 61U },
1943		{ VE::SF62, 62U },
1944		{ VE::SF63, 63U },
1945		{ VE::SW0, 0U },
1946		{ VE::SW1, 1U },
1947		{ VE::SW2, 2U },
1948		{ VE::SW3, 3U },
1949		{ VE::SW4, 4U },
1950		{ VE::SW5, 5U },
1951		{ VE::SW6, 6U },
1952		{ VE::SW7, 7U },
1953		{ VE::SW8, 8U },
1954		{ VE::SW9, 9U },
1955		{ VE::SW10, 10U },
1956		{ VE::SW11, 11U },
1957		{ VE::SW12, 12U },
1958		{ VE::SW13, 13U },
1959		{ VE::SW14, 14U },
1960		{ VE::SW15, 15U },
1961		{ VE::SW16, 16U },
1962		{ VE::SW17, 17U },
1963		{ VE::SW18, 18U },
1964		{ VE::SW19, 19U },
1965		{ VE::SW20, 20U },
1966		{ VE::SW21, 21U },
1967		{ VE::SW22, 22U },
1968		{ VE::SW23, 23U },
1969		{ VE::SW24, 24U },
1970		{ VE::SW25, 25U },
1971		{ VE::SW26, 26U },
1972		{ VE::SW27, 27U },
1973		{ VE::SW28, 28U },
1974		{ VE::SW29, 29U },
1975		{ VE::SW30, 30U },
1976		{ VE::SW31, 31U },
1977		{ VE::SW32, 32U },
1978		{ VE::SW33, 33U },
1979		{ VE::SW34, 34U },
1980		{ VE::SW35, 35U },
1981		{ VE::SW36, 36U },
1982		{ VE::SW37, 37U },
1983		{ VE::SW38, 38U },
1984		{ VE::SW39, 39U },
1985		{ VE::SW40, 40U },
1986		{ VE::SW41, 41U },
1987		{ VE::SW42, 42U },
1988		{ VE::SW43, 43U },
1989		{ VE::SW44, 44U },
1990		{ VE::SW45, 45U },
1991		{ VE::SW46, 46U },
1992		{ VE::SW47, 47U },
1993		{ VE::SW48, 48U },
1994		{ VE::SW49, 49U },
1995		{ VE::SW50, 50U },
1996		{ VE::SW51, 51U },
1997		{ VE::SW52, 52U },
1998		{ VE::SW53, 53U },
1999		{ VE::SW54, 54U },
2000		{ VE::SW55, 55U },
2001		{ VE::SW56, 56U },
2002		{ VE::SW57, 57U },
2003		{ VE::SW58, 58U },
2004		{ VE::SW59, 59U },
2005		{ VE::SW60, 60U },
2006		{ VE::SW61, 61U },
2007		{ VE::SW62, 62U },
2008		{ VE::SW63, 63U },
2009		{ VE::SX0, 0U },
2010		{ VE::SX1, 1U },
2011		{ VE::SX2, 2U },
2012		{ VE::SX3, 3U },
2013		{ VE::SX4, 4U },
2014		{ VE::SX5, 5U },
2015		{ VE::SX6, 6U },
2016		{ VE::SX7, 7U },
2017		{ VE::SX8, 8U },
2018		{ VE::SX9, 9U },
2019		{ VE::SX10, 10U },
2020		{ VE::SX11, 11U },
2021		{ VE::SX12, 12U },
2022		{ VE::SX13, 13U },
2023		{ VE::SX14, 14U },
2024		{ VE::SX15, 15U },
2025		{ VE::SX16, 16U },
2026		{ VE::SX17, 17U },
2027		{ VE::SX18, 18U },
2028		{ VE::SX19, 19U },
2029		{ VE::SX20, 20U },
2030		{ VE::SX21, 21U },
2031		{ VE::SX22, 22U },
2032		{ VE::SX23, 23U },
2033		{ VE::SX24, 24U },
2034		{ VE::SX25, 25U },
2035		{ VE::SX26, 26U },
2036		{ VE::SX27, 27U },
2037		{ VE::SX28, 28U },
2038		{ VE::SX29, 29U },
2039		{ VE::SX30, 30U },
2040		{ VE::SX31, 31U },
2041		{ VE::SX32, 32U },
2042		{ VE::SX33, 33U },
2043		{ VE::SX34, 34U },
2044		{ VE::SX35, 35U },
2045		{ VE::SX36, 36U },
2046		{ VE::SX37, 37U },
2047		{ VE::SX38, 38U },
2048		{ VE::SX39, 39U },
2049		{ VE::SX40, 40U },
2050		{ VE::SX41, 41U },
2051		{ VE::SX42, 42U },
2052		{ VE::SX43, 43U },
2053		{ VE::SX44, 44U },
2054		{ VE::SX45, 45U },
2055		{ VE::SX46, 46U },
2056		{ VE::SX47, 47U },
2057		{ VE::SX48, 48U },
2058		{ VE::SX49, 49U },
2059		{ VE::SX50, 50U },
2060		{ VE::SX51, 51U },
2061		{ VE::SX52, 52U },
2062		{ VE::SX53, 53U },
2063		{ VE::SX54, 54U },
2064		{ VE::SX55, 55U },
2065		{ VE::SX56, 56U },
2066		{ VE::SX57, 57U },
2067		{ VE::SX58, 58U },
2068		{ VE::SX59, 59U },
2069		{ VE::SX60, 60U },
2070		{ VE::SX61, 61U },
2071		{ VE::SX62, 62U },
2072		{ VE::SX63, 63U },
2073		{ VE::V0, 64U },
2074		{ VE::V1, 65U },
2075		{ VE::V2, 66U },
2076		{ VE::V3, 67U },
2077		{ VE::V4, 68U },
2078		{ VE::V5, 69U },
2079		{ VE::V6, 70U },
2080		{ VE::V7, 71U },
2081		{ VE::V8, 72U },
2082		{ VE::V9, 73U },
2083		{ VE::V10, 74U },
2084		{ VE::V11, 75U },
2085		{ VE::V12, 76U },
2086		{ VE::V13, 77U },
2087		{ VE::V14, 78U },
2088		{ VE::V15, 79U },
2089		{ VE::V16, 80U },
2090		{ VE::V17, 81U },
2091		{ VE::V18, 82U },
2092		{ VE::V19, 83U },
2093		{ VE::V20, 84U },
2094		{ VE::V21, 85U },
2095		{ VE::V22, 86U },
2096		{ VE::V23, 87U },
2097		{ VE::V24, 88U },
2098		{ VE::V25, 89U },
2099		{ VE::V26, 90U },
2100		{ VE::V27, 91U },
2101		{ VE::V28, 92U },
2102		{ VE::V29, 93U },
2103		{ VE::V30, 94U },
2104		{ VE::V31, 95U },
2105		{ VE::V32, 96U },
2106		{ VE::V33, 97U },
2107		{ VE::V34, 98U },
2108		{ VE::V35, 99U },
2109		{ VE::V36, 100U },
2110		{ VE::V37, 101U },
2111		{ VE::V38, 102U },
2112		{ VE::V39, 103U },
2113		{ VE::V40, 104U },
2114		{ VE::V41, 105U },
2115		{ VE::V42, 106U },
2116		{ VE::V43, 107U },
2117		{ VE::V44, 108U },
2118		{ VE::V45, 109U },
2119		{ VE::V46, 110U },
2120		{ VE::V47, 111U },
2121		{ VE::V48, 112U },
2122		{ VE::V49, 113U },
2123		{ VE::V50, 114U },
2124		{ VE::V51, 115U },
2125		{ VE::V52, 116U },
2126		{ VE::V53, 117U },
2127		{ VE::V54, 118U },
2128		{ VE::V55, 119U },
2129		{ VE::V56, 120U },
2130		{ VE::V57, 121U },
2131		{ VE::V58, 122U },
2132		{ VE::V59, 123U },
2133		{ VE::V60, 124U },
2134		{ VE::V61, 125U },
2135		{ VE::V62, 126U },
2136		{ VE::V63, 127U },
2137		{ VE::VM0, 128U },
2138		{ VE::VM1, 129U },
2139		{ VE::VM2, 130U },
2140		{ VE::VM3, 131U },
2141		{ VE::VM4, 132U },
2142		{ VE::VM5, 133U },
2143		{ VE::VM6, 134U },
2144		{ VE::VM7, 135U },
2145		{ VE::VM8, 136U },
2146		{ VE::VM9, 137U },
2147		{ VE::VM10, 138U },
2148		{ VE::VM11, 139U },
2149		{ VE::VM12, 140U },
2150		{ VE::VM13, 141U },
2151		{ VE::VM14, 142U },
2152		{ VE::VM15, 143U },
2153		};
2154		extern const unsigned VEDwarfFlavour0L2DwarfSize = std::size(VEDwarfFlavour0L2Dwarf);
2155
2156		extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[] = {
2157		{ VE::SF0, 0U },
2158		{ VE::SF1, 1U },
2159		{ VE::SF2, 2U },
2160		{ VE::SF3, 3U },
2161		{ VE::SF4, 4U },
2162		{ VE::SF5, 5U },
2163		{ VE::SF6, 6U },
2164		{ VE::SF7, 7U },
2165		{ VE::SF8, 8U },
2166		{ VE::SF9, 9U },
2167		{ VE::SF10, 10U },
2168		{ VE::SF11, 11U },
2169		{ VE::SF12, 12U },
2170		{ VE::SF13, 13U },
2171		{ VE::SF14, 14U },
2172		{ VE::SF15, 15U },
2173		{ VE::SF16, 16U },
2174		{ VE::SF17, 17U },
2175		{ VE::SF18, 18U },
2176		{ VE::SF19, 19U },
2177		{ VE::SF20, 20U },
2178		{ VE::SF21, 21U },
2179		{ VE::SF22, 22U },
2180		{ VE::SF23, 23U },
2181		{ VE::SF24, 24U },
2182		{ VE::SF25, 25U },
2183		{ VE::SF26, 26U },
2184		{ VE::SF27, 27U },
2185		{ VE::SF28, 28U },
2186		{ VE::SF29, 29U },
2187		{ VE::SF30, 30U },
2188		{ VE::SF31, 31U },
2189		{ VE::SF32, 32U },
2190		{ VE::SF33, 33U },
2191		{ VE::SF34, 34U },
2192		{ VE::SF35, 35U },
2193		{ VE::SF36, 36U },
2194		{ VE::SF37, 37U },
2195		{ VE::SF38, 38U },
2196		{ VE::SF39, 39U },
2197		{ VE::SF40, 40U },
2198		{ VE::SF41, 41U },
2199		{ VE::SF42, 42U },
2200		{ VE::SF43, 43U },
2201		{ VE::SF44, 44U },
2202		{ VE::SF45, 45U },
2203		{ VE::SF46, 46U },
2204		{ VE::SF47, 47U },
2205		{ VE::SF48, 48U },
2206		{ VE::SF49, 49U },
2207		{ VE::SF50, 50U },
2208		{ VE::SF51, 51U },
2209		{ VE::SF52, 52U },
2210		{ VE::SF53, 53U },
2211		{ VE::SF54, 54U },
2212		{ VE::SF55, 55U },
2213		{ VE::SF56, 56U },
2214		{ VE::SF57, 57U },
2215		{ VE::SF58, 58U },
2216		{ VE::SF59, 59U },
2217		{ VE::SF60, 60U },
2218		{ VE::SF61, 61U },
2219		{ VE::SF62, 62U },
2220		{ VE::SF63, 63U },
2221		{ VE::SW0, 0U },
2222		{ VE::SW1, 1U },
2223		{ VE::SW2, 2U },
2224		{ VE::SW3, 3U },
2225		{ VE::SW4, 4U },
2226		{ VE::SW5, 5U },
2227		{ VE::SW6, 6U },
2228		{ VE::SW7, 7U },
2229		{ VE::SW8, 8U },
2230		{ VE::SW9, 9U },
2231		{ VE::SW10, 10U },
2232		{ VE::SW11, 11U },
2233		{ VE::SW12, 12U },
2234		{ VE::SW13, 13U },
2235		{ VE::SW14, 14U },
2236		{ VE::SW15, 15U },
2237		{ VE::SW16, 16U },
2238		{ VE::SW17, 17U },
2239		{ VE::SW18, 18U },
2240		{ VE::SW19, 19U },
2241		{ VE::SW20, 20U },
2242		{ VE::SW21, 21U },
2243		{ VE::SW22, 22U },
2244		{ VE::SW23, 23U },
2245		{ VE::SW24, 24U },
2246		{ VE::SW25, 25U },
2247		{ VE::SW26, 26U },
2248		{ VE::SW27, 27U },
2249		{ VE::SW28, 28U },
2250		{ VE::SW29, 29U },
2251		{ VE::SW30, 30U },
2252		{ VE::SW31, 31U },
2253		{ VE::SW32, 32U },
2254		{ VE::SW33, 33U },
2255		{ VE::SW34, 34U },
2256		{ VE::SW35, 35U },
2257		{ VE::SW36, 36U },
2258		{ VE::SW37, 37U },
2259		{ VE::SW38, 38U },
2260		{ VE::SW39, 39U },
2261		{ VE::SW40, 40U },
2262		{ VE::SW41, 41U },
2263		{ VE::SW42, 42U },
2264		{ VE::SW43, 43U },
2265		{ VE::SW44, 44U },
2266		{ VE::SW45, 45U },
2267		{ VE::SW46, 46U },
2268		{ VE::SW47, 47U },
2269		{ VE::SW48, 48U },
2270		{ VE::SW49, 49U },
2271		{ VE::SW50, 50U },
2272		{ VE::SW51, 51U },
2273		{ VE::SW52, 52U },
2274		{ VE::SW53, 53U },
2275		{ VE::SW54, 54U },
2276		{ VE::SW55, 55U },
2277		{ VE::SW56, 56U },
2278		{ VE::SW57, 57U },
2279		{ VE::SW58, 58U },
2280		{ VE::SW59, 59U },
2281		{ VE::SW60, 60U },
2282		{ VE::SW61, 61U },
2283		{ VE::SW62, 62U },
2284		{ VE::SW63, 63U },
2285		{ VE::SX0, 0U },
2286		{ VE::SX1, 1U },
2287		{ VE::SX2, 2U },
2288		{ VE::SX3, 3U },
2289		{ VE::SX4, 4U },
2290		{ VE::SX5, 5U },
2291		{ VE::SX6, 6U },
2292		{ VE::SX7, 7U },
2293		{ VE::SX8, 8U },
2294		{ VE::SX9, 9U },
2295		{ VE::SX10, 10U },
2296		{ VE::SX11, 11U },
2297		{ VE::SX12, 12U },
2298		{ VE::SX13, 13U },
2299		{ VE::SX14, 14U },
2300		{ VE::SX15, 15U },
2301		{ VE::SX16, 16U },
2302		{ VE::SX17, 17U },
2303		{ VE::SX18, 18U },
2304		{ VE::SX19, 19U },
2305		{ VE::SX20, 20U },
2306		{ VE::SX21, 21U },
2307		{ VE::SX22, 22U },
2308		{ VE::SX23, 23U },
2309		{ VE::SX24, 24U },
2310		{ VE::SX25, 25U },
2311		{ VE::SX26, 26U },
2312		{ VE::SX27, 27U },
2313		{ VE::SX28, 28U },
2314		{ VE::SX29, 29U },
2315		{ VE::SX30, 30U },
2316		{ VE::SX31, 31U },
2317		{ VE::SX32, 32U },
2318		{ VE::SX33, 33U },
2319		{ VE::SX34, 34U },
2320		{ VE::SX35, 35U },
2321		{ VE::SX36, 36U },
2322		{ VE::SX37, 37U },
2323		{ VE::SX38, 38U },
2324		{ VE::SX39, 39U },
2325		{ VE::SX40, 40U },
2326		{ VE::SX41, 41U },
2327		{ VE::SX42, 42U },
2328		{ VE::SX43, 43U },
2329		{ VE::SX44, 44U },
2330		{ VE::SX45, 45U },
2331		{ VE::SX46, 46U },
2332		{ VE::SX47, 47U },
2333		{ VE::SX48, 48U },
2334		{ VE::SX49, 49U },
2335		{ VE::SX50, 50U },
2336		{ VE::SX51, 51U },
2337		{ VE::SX52, 52U },
2338		{ VE::SX53, 53U },
2339		{ VE::SX54, 54U },
2340		{ VE::SX55, 55U },
2341		{ VE::SX56, 56U },
2342		{ VE::SX57, 57U },
2343		{ VE::SX58, 58U },
2344		{ VE::SX59, 59U },
2345		{ VE::SX60, 60U },
2346		{ VE::SX61, 61U },
2347		{ VE::SX62, 62U },
2348		{ VE::SX63, 63U },
2349		{ VE::V0, 64U },
2350		{ VE::V1, 65U },
2351		{ VE::V2, 66U },
2352		{ VE::V3, 67U },
2353		{ VE::V4, 68U },
2354		{ VE::V5, 69U },
2355		{ VE::V6, 70U },
2356		{ VE::V7, 71U },
2357		{ VE::V8, 72U },
2358		{ VE::V9, 73U },
2359		{ VE::V10, 74U },
2360		{ VE::V11, 75U },
2361		{ VE::V12, 76U },
2362		{ VE::V13, 77U },
2363		{ VE::V14, 78U },
2364		{ VE::V15, 79U },
2365		{ VE::V16, 80U },
2366		{ VE::V17, 81U },
2367		{ VE::V18, 82U },
2368		{ VE::V19, 83U },
2369		{ VE::V20, 84U },
2370		{ VE::V21, 85U },
2371		{ VE::V22, 86U },
2372		{ VE::V23, 87U },
2373		{ VE::V24, 88U },
2374		{ VE::V25, 89U },
2375		{ VE::V26, 90U },
2376		{ VE::V27, 91U },
2377		{ VE::V28, 92U },
2378		{ VE::V29, 93U },
2379		{ VE::V30, 94U },
2380		{ VE::V31, 95U },
2381		{ VE::V32, 96U },
2382		{ VE::V33, 97U },
2383		{ VE::V34, 98U },
2384		{ VE::V35, 99U },
2385		{ VE::V36, 100U },
2386		{ VE::V37, 101U },
2387		{ VE::V38, 102U },
2388		{ VE::V39, 103U },
2389		{ VE::V40, 104U },
2390		{ VE::V41, 105U },
2391		{ VE::V42, 106U },
2392		{ VE::V43, 107U },
2393		{ VE::V44, 108U },
2394		{ VE::V45, 109U },
2395		{ VE::V46, 110U },
2396		{ VE::V47, 111U },
2397		{ VE::V48, 112U },
2398		{ VE::V49, 113U },
2399		{ VE::V50, 114U },
2400		{ VE::V51, 115U },
2401		{ VE::V52, 116U },
2402		{ VE::V53, 117U },
2403		{ VE::V54, 118U },
2404		{ VE::V55, 119U },
2405		{ VE::V56, 120U },
2406		{ VE::V57, 121U },
2407		{ VE::V58, 122U },
2408		{ VE::V59, 123U },
2409		{ VE::V60, 124U },
2410		{ VE::V61, 125U },
2411		{ VE::V62, 126U },
2412		{ VE::V63, 127U },
2413		{ VE::VM0, 128U },
2414		{ VE::VM1, 129U },
2415		{ VE::VM2, 130U },
2416		{ VE::VM3, 131U },
2417		{ VE::VM4, 132U },
2418		{ VE::VM5, 133U },
2419		{ VE::VM6, 134U },
2420		{ VE::VM7, 135U },
2421		{ VE::VM8, 136U },
2422		{ VE::VM9, 137U },
2423		{ VE::VM10, 138U },
2424		{ VE::VM11, 139U },
2425		{ VE::VM12, 140U },
2426		{ VE::VM13, 141U },
2427		{ VE::VM14, 142U },
2428		{ VE::VM15, 143U },
2429		};
2430		extern const unsigned VEEHFlavour0L2DwarfSize = std::size(VEEHFlavour0L2Dwarf);
2431
2432		extern const uint16_t VERegEncodingTable[] = {
2433		0,
2434		62,
2435		7,
2436		1,
2437		2,
2438		0,
2439		255,
2440		63,
2441		16,
2442		17,
2443		18,
2444		19,
2445		20,
2446		21,
2447		22,
2448		23,
2449		24,
2450		25,
2451		26,
2452		27,
2453		28,
2454		29,
2455		30,
2456		8,
2457		9,
2458		10,
2459		11,
2460		0,
2461		2,
2462		4,
2463		6,
2464		8,
2465		10,
2466		12,
2467		14,
2468		16,
2469		18,
2470		20,
2471		22,
2472		24,
2473		26,
2474		28,
2475		30,
2476		32,
2477		34,
2478		36,
2479		38,
2480		40,
2481		42,
2482		44,
2483		46,
2484		48,
2485		50,
2486		52,
2487		54,
2488		56,
2489		58,
2490		60,
2491		62,
2492		0,
2493		1,
2494		2,
2495		3,
2496		4,
2497		5,
2498		6,
2499		7,
2500		8,
2501		9,
2502		10,
2503		11,
2504		12,
2505		13,
2506		14,
2507		15,
2508		16,
2509		17,
2510		18,
2511		19,
2512		20,
2513		21,
2514		22,
2515		23,
2516		24,
2517		25,
2518		26,
2519		27,
2520		28,
2521		29,
2522		30,
2523		31,
2524		32,
2525		33,
2526		34,
2527		35,
2528		36,
2529		37,
2530		38,
2531		39,
2532		40,
2533		41,
2534		42,
2535		43,
2536		44,
2537		45,
2538		46,
2539		47,
2540		48,
2541		49,
2542		50,
2543		51,
2544		52,
2545		53,
2546		54,
2547		55,
2548		56,
2549		57,
2550		58,
2551		59,
2552		60,
2553		61,
2554		62,
2555		63,
2556		0,
2557		1,
2558		2,
2559		3,
2560		4,
2561		5,
2562		6,
2563		7,
2564		8,
2565		9,
2566		10,
2567		11,
2568		12,
2569		13,
2570		14,
2571		15,
2572		16,
2573		17,
2574		18,
2575		19,
2576		20,
2577		21,
2578		22,
2579		23,
2580		24,
2581		25,
2582		26,
2583		27,
2584		28,
2585		29,
2586		30,
2587		31,
2588		32,
2589		33,
2590		34,
2591		35,
2592		36,
2593		37,
2594		38,
2595		39,
2596		40,
2597		41,
2598		42,
2599		43,
2600		44,
2601		45,
2602		46,
2603		47,
2604		48,
2605		49,
2606		50,
2607		51,
2608		52,
2609		53,
2610		54,
2611		55,
2612		56,
2613		57,
2614		58,
2615		59,
2616		60,
2617		61,
2618		62,
2619		63,
2620		0,
2621		1,
2622		2,
2623		3,
2624		4,
2625		5,
2626		6,
2627		7,
2628		8,
2629		9,
2630		10,
2631		11,
2632		12,
2633		13,
2634		14,
2635		15,
2636		16,
2637		17,
2638		18,
2639		19,
2640		20,
2641		21,
2642		22,
2643		23,
2644		24,
2645		25,
2646		26,
2647		27,
2648		28,
2649		29,
2650		30,
2651		31,
2652		32,
2653		33,
2654		34,
2655		35,
2656		36,
2657		37,
2658		38,
2659		39,
2660		40,
2661		41,
2662		42,
2663		43,
2664		44,
2665		45,
2666		46,
2667		47,
2668		48,
2669		49,
2670		50,
2671		51,
2672		52,
2673		53,
2674		54,
2675		55,
2676		56,
2677		57,
2678		58,
2679		59,
2680		60,
2681		61,
2682		62,
2683		63,
2684		0,
2685		1,
2686		2,
2687		3,
2688		4,
2689		5,
2690		6,
2691		7,
2692		8,
2693		9,
2694		10,
2695		11,
2696		12,
2697		13,
2698		14,
2699		15,
2700		16,
2701		17,
2702		18,
2703		19,
2704		20,
2705		21,
2706		22,
2707		23,
2708		24,
2709		25,
2710		26,
2711		27,
2712		28,
2713		29,
2714		30,
2715		31,
2716		32,
2717		33,
2718		34,
2719		35,
2720		36,
2721		37,
2722		38,
2723		39,
2724		40,
2725		41,
2726		42,
2727		43,
2728		44,
2729		45,
2730		46,
2731		47,
2732		48,
2733		49,
2734		50,
2735		51,
2736		52,
2737		53,
2738		54,
2739		55,
2740		56,
2741		57,
2742		58,
2743		59,
2744		60,
2745		61,
2746		62,
2747		63,
2748		0,
2749		1,
2750		2,
2751		3,
2752		4,
2753		5,
2754		6,
2755		7,
2756		8,
2757		9,
2758		10,
2759		11,
2760		12,
2761		13,
2762		14,
2763		15,
2764		0,
2765		2,
2766		4,
2767		6,
2768		8,
2769		10,
2770		12,
2771		14,
2772		};
2773	2	static inline void InitVEMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
2774	2	RI->InitMCRegisterInfo(VERegDesc, 339, RA, PC, VEMCRegisterClasses, 10, VERegUnitRoots, 171, VERegDiffLists, VELaneMaskLists, VERegStrings, VERegClassStrings, VESubRegIdxLists, 9,
2775	2	VESubRegIdxRanges, VERegEncodingTable);
2776
2777	2	switch (DwarfFlavour) {
2778	0	default:
2779	0	llvm_unreachable("Unknown DWARF flavour");
2780	2	case 0:
2781	2	RI->mapDwarfRegsToLLVMRegs(VEDwarfFlavour0Dwarf2L, VEDwarfFlavour0Dwarf2LSize, false);
2782	2	break;
2783	2	}
2784	2	switch (EHFlavour) {
2785	0	default:
2786	0	llvm_unreachable("Unknown DWARF flavour");
2787	2	case 0:
2788	2	RI->mapDwarfRegsToLLVMRegs(VEEHFlavour0Dwarf2L, VEEHFlavour0Dwarf2LSize, true);
2789	2	break;
2790	2	}
2791	2	switch (DwarfFlavour) {
2792	0	default:
2793	0	llvm_unreachable("Unknown DWARF flavour");
2794	2	case 0:
2795	2	RI->mapLLVMRegsToDwarfRegs(VEDwarfFlavour0L2Dwarf, VEDwarfFlavour0L2DwarfSize, false);
2796	2	break;
2797	2	}
2798	2	switch (EHFlavour) {
2799	0	default:
2800	0	llvm_unreachable("Unknown DWARF flavour");
2801	2	case 0:
2802	2	RI->mapLLVMRegsToDwarfRegs(VEEHFlavour0L2Dwarf, VEEHFlavour0L2DwarfSize, true);
2803	2	break;
2804	2	}
2805	2	}
2806
2807		} // end namespace llvm
2808
2809		#endif // GET_REGINFO_MC_DESC
2810
2811		/===- TableGen'erated file -------------------------------------- C++ --===\
2812		\|* *\|
2813		\|* Register Information Header Fragment *\|
2814		\|* *\|
2815		\|* Automatically generated file, do not edit! *\|
2816		\|* *\|
2817		\===----------------------------------------------------------------------===/
2818
2819
2820		#ifdef GET_REGINFO_HEADER
2821		#undef GET_REGINFO_HEADER
2822
2823		#include "llvm/CodeGen/TargetRegisterInfo.h"
2824
2825		namespace llvm {
2826
2827		class VEFrameLowering;
2828
2829		struct VEGenRegisterInfo : public TargetRegisterInfo {
2830		explicit VEGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
2831		unsigned PC = 0, unsigned HwMode = 0);
2832		unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
2833		LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2834		LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2835		const TargetRegisterClass getSubClassWithSubReg(const TargetRegisterClass , unsigned) const override;
2836		const TargetRegisterClass getSubRegisterClass(const TargetRegisterClass , unsigned) const override;
2837		const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
2838		unsigned getRegUnitWeight(unsigned RegUnit) const override;
2839		unsigned getNumRegPressureSets() const override;
2840		const char *getRegPressureSetName(unsigned Idx) const override;
2841		unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
2842		const int getRegClassPressureSets(const TargetRegisterClass RC) const override;
2843		const int *getRegUnitPressureSets(unsigned RegUnit) const override;
2844		ArrayRef<const char *> getRegMaskNames() const override;
2845		ArrayRef<const uint32_t *> getRegMasks() const override;
2846		bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
2847		bool isFixedRegister(const MachineFunction &, MCRegister) const override;
2848		bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
2849		bool isConstantPhysReg(MCRegister PhysReg) const override final;
2850		/// Devirtualized TargetFrameLowering.
2851		static const VEFrameLowering *getFrameLowering(
2852		const MachineFunction &MF);
2853		};
2854
2855		namespace VE { // Register classes
2856		extern const TargetRegisterClass F32RegClass;
2857		extern const TargetRegisterClass I32RegClass;
2858		extern const TargetRegisterClass VLSRegClass;
2859		extern const TargetRegisterClass I64RegClass;
2860		extern const TargetRegisterClass MISCRegClass;
2861		extern const TargetRegisterClass F128RegClass;
2862		extern const TargetRegisterClass VMRegClass;
2863		extern const TargetRegisterClass VM512RegClass;
2864		extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass;
2865		extern const TargetRegisterClass V64RegClass;
2866		} // end namespace VE
2867
2868		} // end namespace llvm
2869
2870		#endif // GET_REGINFO_HEADER
2871
2872		/===- TableGen'erated file -------------------------------------- C++ --===\
2873		\|* *\|
2874		\|* Target Register and Register Classes Information *\|
2875		\|* *\|
2876		\|* Automatically generated file, do not edit! *\|
2877		\|* *\|
2878		\===----------------------------------------------------------------------===/
2879
2880
2881		#ifdef GET_REGINFO_TARGET_DESC
2882		#undef GET_REGINFO_TARGET_DESC
2883
2884		namespace llvm {
2885
2886		extern const MCRegisterClass VEMCRegisterClasses[];
2887
2888		static const MVT::SimpleValueType VTLists[] = {
2889		/* 0 */ MVT::i32, MVT::Other,
2890		/* 2 */ MVT::i64, MVT::Other,
2891		/* 4 */ MVT::f32, MVT::Other,
2892		/* 6 */ MVT::i64, MVT::f64, MVT::Other,
2893		/* 9 */ MVT::f128, MVT::Other,
2894		/* 11 */ MVT::v256i1, MVT::Other,
2895		/* 13 */ MVT::v512i1, MVT::Other,
2896		/* 15 */ MVT::v256f64, MVT::v512i32, MVT::v512f32, MVT::v256i64, MVT::v256i32, MVT::v256f32, MVT::Other,
2897		};
2898
2899		static const char *SubRegIndexNameTable[] = { "sub_even", "sub_f32", "sub_i32", "sub_odd", "sub_vm_even", "sub_vm_odd", "sub_odd_then_sub_f32", "sub_odd_then_sub_i32", "" };
2900
2901
2902		static const LaneBitmask SubRegIndexLaneMaskTable[] = {
2903		LaneBitmask::getAll(),
2904		LaneBitmask(0x0000000000000003), // sub_even
2905		LaneBitmask(0x0000000000000001), // sub_f32
2906		LaneBitmask(0x0000000000000002), // sub_i32
2907		LaneBitmask(0x0000000000000030), // sub_odd
2908		LaneBitmask(0x0000000000000004), // sub_vm_even
2909		LaneBitmask(0x0000000000000008), // sub_vm_odd
2910		LaneBitmask(0x0000000000000010), // sub_odd_then_sub_f32
2911		LaneBitmask(0x0000000000000020), // sub_odd_then_sub_i32
2912		};
2913
2914
2915
2916		static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
2917		// Mode = 0 (Default)
2918		{ 32, 32, 32, /VTLists+/4 }, // F32
2919		{ 32, 32, 32, /VTLists+/0 }, // I32
2920		{ 32, 32, 64, /VTLists+/0 }, // VLS
2921		{ 64, 64, 64, /VTLists+/6 }, // I64
2922		{ 64, 64, 64, /VTLists+/2 }, // MISC
2923		{ 128, 128, 128, /VTLists+/9 }, // F128
2924		{ 256, 256, 64, /VTLists+/11 }, // VM
2925		{ 512, 512, 64, /VTLists+/13 }, // VM512
2926		{ 512, 512, 64, /VTLists+/13 }, // VM512_with_sub_vm_even
2927		{ 16384, 16384, 64, /VTLists+/15 }, // V64
2928		};
2929
2930		static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
2931
2932		static const uint32_t F32SubClassMask[] = {
2933		0x00000001,
2934		0x00000028, // sub_f32
2935		0x00000020, // sub_odd_then_sub_f32
2936		};
2937
2938		static const uint32_t I32SubClassMask[] = {
2939		0x00000002,
2940		0x00000028, // sub_i32
2941		0x00000020, // sub_odd_then_sub_i32
2942		};
2943
2944		static const uint32_t VLSSubClassMask[] = {
2945		0x00000004,
2946		};
2947
2948		static const uint32_t I64SubClassMask[] = {
2949		0x00000008,
2950		0x00000020, // sub_even
2951		0x00000020, // sub_odd
2952		};
2953
2954		static const uint32_t MISCSubClassMask[] = {
2955		0x00000010,
2956		};
2957
2958		static const uint32_t F128SubClassMask[] = {
2959		0x00000020,
2960		};
2961
2962		static const uint32_t VMSubClassMask[] = {
2963		0x00000040,
2964		0x00000100, // sub_vm_even
2965		0x00000100, // sub_vm_odd
2966		};
2967
2968		static const uint32_t VM512SubClassMask[] = {
2969		0x00000180,
2970		};
2971
2972		static const uint32_t VM512_with_sub_vm_evenSubClassMask[] = {
2973		0x00000100,
2974		};
2975
2976		static const uint32_t V64SubClassMask[] = {
2977		0x00000200,
2978		};
2979
2980		static const uint16_t SuperRegIdxSeqs[] = {
2981		/* 0 */ 1, 4, 0,
2982		/* 3 */ 5, 6, 0,
2983		/* 6 */ 2, 7, 0,
2984		/* 9 */ 3, 8, 0,
2985		};
2986
2987		static const TargetRegisterClass *const VM512_with_sub_vm_evenSuperclasses[] = {
2988		&VE::VM512RegClass,
2989		nullptr
2990		};
2991
2992
2993		namespace VE { // Register class instances
2994		extern const TargetRegisterClass F32RegClass = {
2995		&VEMCRegisterClasses[F32RegClassID],
2996		F32SubClassMask,
2997		SuperRegIdxSeqs + 6,
2998		LaneBitmask(0x0000000000000001),
2999		0,
3000		false,
3001		0x00, /* TSFlags */
3002		false, /* HasDisjunctSubRegs */
3003		false, /* CoveredBySubRegs */
3004		NullRegClasses,
3005		nullptr
3006		};
3007
3008		extern const TargetRegisterClass I32RegClass = {
3009		&VEMCRegisterClasses[I32RegClassID],
3010		I32SubClassMask,
3011		SuperRegIdxSeqs + 9,
3012		LaneBitmask(0x0000000000000001),
3013		0,
3014		false,
3015		0x00, /* TSFlags */
3016		false, /* HasDisjunctSubRegs */
3017		false, /* CoveredBySubRegs */
3018		NullRegClasses,
3019		nullptr
3020		};
3021
3022		extern const TargetRegisterClass VLSRegClass = {
3023		&VEMCRegisterClasses[VLSRegClassID],
3024		VLSSubClassMask,
3025		SuperRegIdxSeqs + 2,
3026		LaneBitmask(0x0000000000000001),
3027		0,
3028		false,
3029		0x00, /* TSFlags */
3030		false, /* HasDisjunctSubRegs */
3031		false, /* CoveredBySubRegs */
3032		NullRegClasses,
3033		nullptr
3034		};
3035
3036		extern const TargetRegisterClass I64RegClass = {
3037		&VEMCRegisterClasses[I64RegClassID],
3038		I64SubClassMask,
3039		SuperRegIdxSeqs + 0,
3040		LaneBitmask(0x0000000000000003),
3041		0,
3042		false,
3043		0x00, /* TSFlags */
3044		true, /* HasDisjunctSubRegs */
3045		true, /* CoveredBySubRegs */
3046		NullRegClasses,
3047		nullptr
3048		};
3049
3050		extern const TargetRegisterClass MISCRegClass = {
3051		&VEMCRegisterClasses[MISCRegClassID],
3052		MISCSubClassMask,
3053		SuperRegIdxSeqs + 2,
3054		LaneBitmask(0x0000000000000001),
3055		0,
3056		false,
3057		0x00, /* TSFlags */
3058		false, /* HasDisjunctSubRegs */
3059		false, /* CoveredBySubRegs */
3060		NullRegClasses,
3061		nullptr
3062		};
3063
3064		extern const TargetRegisterClass F128RegClass = {
3065		&VEMCRegisterClasses[F128RegClassID],
3066		F128SubClassMask,
3067		SuperRegIdxSeqs + 2,
3068		LaneBitmask(0x0000000000000033),
3069		0,
3070		false,
3071		0x00, /* TSFlags */
3072		true, /* HasDisjunctSubRegs */
3073		true, /* CoveredBySubRegs */
3074		NullRegClasses,
3075		nullptr
3076		};
3077
3078		extern const TargetRegisterClass VMRegClass = {
3079		&VEMCRegisterClasses[VMRegClassID],
3080		VMSubClassMask,
3081		SuperRegIdxSeqs + 3,
3082		LaneBitmask(0x0000000000000001),
3083		0,
3084		false,
3085		0x00, /* TSFlags */
3086		false, /* HasDisjunctSubRegs */
3087		false, /* CoveredBySubRegs */
3088		NullRegClasses,
3089		nullptr
3090		};
3091
3092		extern const TargetRegisterClass VM512RegClass = {
3093		&VEMCRegisterClasses[VM512RegClassID],
3094		VM512SubClassMask,
3095		SuperRegIdxSeqs + 2,
3096		LaneBitmask(0x000000000000000C),
3097		0,
3098		false,
3099		0x00, /* TSFlags */
3100		true, /* HasDisjunctSubRegs */
3101		false, /* CoveredBySubRegs */
3102		NullRegClasses,
3103		nullptr
3104		};
3105
3106		extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass = {
3107		&VEMCRegisterClasses[VM512_with_sub_vm_evenRegClassID],
3108		VM512_with_sub_vm_evenSubClassMask,
3109		SuperRegIdxSeqs + 2,
3110		LaneBitmask(0x000000000000000C),
3111		0,
3112		false,
3113		0x00, /* TSFlags */
3114		true, /* HasDisjunctSubRegs */
3115		true, /* CoveredBySubRegs */
3116		VM512_with_sub_vm_evenSuperclasses,
3117		nullptr
3118		};
3119
3120		extern const TargetRegisterClass V64RegClass = {
3121		&VEMCRegisterClasses[V64RegClassID],
3122		V64SubClassMask,
3123		SuperRegIdxSeqs + 2,
3124		LaneBitmask(0x0000000000000001),
3125		0,
3126		false,
3127		0x00, /* TSFlags */
3128		false, /* HasDisjunctSubRegs */
3129		false, /* CoveredBySubRegs */
3130		NullRegClasses,
3131		nullptr
3132		};
3133
3134		} // end namespace VE
3135
3136		namespace {
3137		const TargetRegisterClass *const RegisterClasses[] = {
3138		&VE::F32RegClass,
3139		&VE::I32RegClass,
3140		&VE::VLSRegClass,
3141		&VE::I64RegClass,
3142		&VE::MISCRegClass,
3143		&VE::F128RegClass,
3144		&VE::VMRegClass,
3145		&VE::VM512RegClass,
3146		&VE::VM512_with_sub_vm_evenRegClass,
3147		&VE::V64RegClass,
3148		};
3149		} // end anonymous namespace
3150
3151		static const uint8_t CostPerUseTable[] = {
3152		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
3153
3154
3155		static const bool InAllocatableClassTable[] = {
3156		false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
3157
3158
3159		static const TargetRegisterInfoDesc VERegInfoDesc = { // Extra Descriptors
3160		CostPerUseTable, 1, InAllocatableClassTable};
3161
3162	0	unsigned VEGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
3163	0	static const uint8_t RowMap[8] = {
3164	0	0, 0, 0, 1, 0, 0, 0, 0,
3165	0	};
3166	0	static const uint8_t Rows[2][8] = {
3167	0	{ 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3168	0	{ 0, VE::sub_odd_then_sub_f32, VE::sub_odd_then_sub_i32, 0, 0, 0, 0, 0, },
3169	0	};
3170
3171	0	--IdxA; assert(IdxA < 8); (void) IdxA;
3172	0	--IdxB; assert(IdxB < 8);
3173	0	return Rows[RowMap[IdxA]][IdxB];
3174	0	}
3175
3176		struct MaskRolOp {
3177		LaneBitmask Mask;
3178		uint8_t RotateLeft;
3179		};
3180		static const MaskRolOp LaneMaskComposeSequences[] = {
3181		{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
3182		{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
3183		{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
3184		{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
3185		{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
3186		{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 } // Sequence 10
3187		};
3188		static const uint8_t CompositeSequences[] = {
3189		0, // to sub_even
3190		0, // to sub_f32
3191		2, // to sub_i32
3192		4, // to sub_odd
3193		6, // to sub_vm_even
3194		8, // to sub_vm_odd
3195		4, // to sub_odd_then_sub_f32
3196		10 // to sub_odd_then_sub_i32
3197		};
3198
3199	0	LaneBitmask VEGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3200	0	--IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
3201	0	LaneBitmask Result;
3202	0	for (const MaskRolOp *Ops =
3203	0	&LaneMaskComposeSequences[CompositeSequences[IdxA]];
3204	0	Ops->Mask.any(); ++Ops) {
3205	0	LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
3206	0	if (unsigned S = Ops->RotateLeft)
3207	0	Result \|= LaneBitmask((M << S) \| (M >> (LaneBitmask::BitWidth - S)));
3208	0	else
3209	0	Result \|= LaneBitmask(M);
3210	0	}
3211	0	return Result;
3212	0	}
3213
3214	0	LaneBitmask VEGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3215	0	LaneMask &= getSubRegIndexLaneMask(IdxA);
3216	0	--IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
3217	0	LaneBitmask Result;
3218	0	for (const MaskRolOp *Ops =
3219	0	&LaneMaskComposeSequences[CompositeSequences[IdxA]];
3220	0	Ops->Mask.any(); ++Ops) {
3221	0	LaneBitmask::Type M = LaneMask.getAsInteger();
3222	0	if (unsigned S = Ops->RotateLeft)
3223	0	Result \|= LaneBitmask((M >> S) \| (M << (LaneBitmask::BitWidth - S)));
3224	0	else
3225	0	Result \|= LaneBitmask(M);
3226	0	}
3227	0	return Result;
3228	0	}
3229
3230	53.0k	const TargetRegisterClass VEGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass RC, unsigned Idx) const {
3231	53.0k	static const uint8_t Table[10][8] = {
3232	53.0k	{ // F32
3233	53.0k	0, // sub_even
3234	53.0k	0, // sub_f32
3235	53.0k	0, // sub_i32
3236	53.0k	0, // sub_odd
3237	53.0k	0, // sub_vm_even
3238	53.0k	0, // sub_vm_odd
3239	53.0k	0, // sub_odd_then_sub_f32
3240	53.0k	0, // sub_odd_then_sub_i32
3241	53.0k	},
3242	53.0k	{ // I32
3243	53.0k	0, // sub_even
3244	53.0k	0, // sub_f32
3245	53.0k	0, // sub_i32
3246	53.0k	0, // sub_odd
3247	53.0k	0, // sub_vm_even
3248	53.0k	0, // sub_vm_odd
3249	53.0k	0, // sub_odd_then_sub_f32
3250	53.0k	0, // sub_odd_then_sub_i32
3251	53.0k	},
3252	53.0k	{ // VLS
3253	53.0k	0, // sub_even
3254	53.0k	0, // sub_f32
3255	53.0k	0, // sub_i32
3256	53.0k	0, // sub_odd
3257	53.0k	0, // sub_vm_even
3258	53.0k	0, // sub_vm_odd
3259	53.0k	0, // sub_odd_then_sub_f32
3260	53.0k	0, // sub_odd_then_sub_i32
3261	53.0k	},
3262	53.0k	{ // I64
3263	53.0k	0, // sub_even
3264	53.0k	4, // sub_f32 -> I64
3265	53.0k	4, // sub_i32 -> I64
3266	53.0k	0, // sub_odd
3267	53.0k	0, // sub_vm_even
3268	53.0k	0, // sub_vm_odd
3269	53.0k	0, // sub_odd_then_sub_f32
3270	53.0k	0, // sub_odd_then_sub_i32
3271	53.0k	},
3272	53.0k	{ // MISC
3273	53.0k	0, // sub_even
3274	53.0k	0, // sub_f32
3275	53.0k	0, // sub_i32
3276	53.0k	0, // sub_odd
3277	53.0k	0, // sub_vm_even
3278	53.0k	0, // sub_vm_odd
3279	53.0k	0, // sub_odd_then_sub_f32
3280	53.0k	0, // sub_odd_then_sub_i32
3281	53.0k	},
3282	53.0k	{ // F128
3283	53.0k	6, // sub_even -> F128
3284	53.0k	6, // sub_f32 -> F128
3285	53.0k	6, // sub_i32 -> F128
3286	53.0k	6, // sub_odd -> F128
3287	53.0k	0, // sub_vm_even
3288	53.0k	0, // sub_vm_odd
3289	53.0k	6, // sub_odd_then_sub_f32 -> F128
3290	53.0k	6, // sub_odd_then_sub_i32 -> F128
3291	53.0k	},
3292	53.0k	{ // VM
3293	53.0k	0, // sub_even
3294	53.0k	0, // sub_f32
3295	53.0k	0, // sub_i32
3296	53.0k	0, // sub_odd
3297	53.0k	0, // sub_vm_even
3298	53.0k	0, // sub_vm_odd
3299	53.0k	0, // sub_odd_then_sub_f32
3300	53.0k	0, // sub_odd_then_sub_i32
3301	53.0k	},
3302	53.0k	{ // VM512
3303	53.0k	0, // sub_even
3304	53.0k	0, // sub_f32
3305	53.0k	0, // sub_i32
3306	53.0k	0, // sub_odd
3307	53.0k	9, // sub_vm_even -> VM512_with_sub_vm_even
3308	53.0k	9, // sub_vm_odd -> VM512_with_sub_vm_even
3309	53.0k	0, // sub_odd_then_sub_f32
3310	53.0k	0, // sub_odd_then_sub_i32
3311	53.0k	},
3312	53.0k	{ // VM512_with_sub_vm_even
3313	53.0k	0, // sub_even
3314	53.0k	0, // sub_f32
3315	53.0k	0, // sub_i32
3316	53.0k	0, // sub_odd
3317	53.0k	9, // sub_vm_even -> VM512_with_sub_vm_even
3318	53.0k	9, // sub_vm_odd -> VM512_with_sub_vm_even
3319	53.0k	0, // sub_odd_then_sub_f32
3320	53.0k	0, // sub_odd_then_sub_i32
3321	53.0k	},
3322	53.0k	{ // V64
3323	53.0k	0, // sub_even
3324	53.0k	0, // sub_f32
3325	53.0k	0, // sub_i32
3326	53.0k	0, // sub_odd
3327	53.0k	0, // sub_vm_even
3328	53.0k	0, // sub_vm_odd
3329	53.0k	0, // sub_odd_then_sub_f32
3330	53.0k	0, // sub_odd_then_sub_i32
3331	53.0k	},
3332	53.0k	};
3333	53.0k	assert(RC && "Missing regclass");
3334	53.0k	if (!Idx) return RC;
3335	53.0k	--Idx;
3336	53.0k	assert(Idx < 8 && "Bad subreg");
3337	0	unsigned TV = Table[RC->getID()][Idx];
3338	53.0k	return TV ? getRegClass(TV - 1) : nullptr;
3339	53.0k	}
3340
3341	0	const TargetRegisterClass VEGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass RC, unsigned Idx) const {
3342	0	static const uint8_t Table[10][8] = {
3343	0	{ // F32
3344	0	0, // F32:sub_even
3345	0	0, // F32:sub_f32
3346	0	0, // F32:sub_i32
3347	0	0, // F32:sub_odd
3348	0	0, // F32:sub_vm_even
3349	0	0, // F32:sub_vm_odd
3350	0	0, // F32:sub_odd_then_sub_f32
3351	0	0, // F32:sub_odd_then_sub_i32
3352	0	},
3353	0	{ // I32
3354	0	0, // I32:sub_even
3355	0	0, // I32:sub_f32
3356	0	0, // I32:sub_i32
3357	0	0, // I32:sub_odd
3358	0	0, // I32:sub_vm_even
3359	0	0, // I32:sub_vm_odd
3360	0	0, // I32:sub_odd_then_sub_f32
3361	0	0, // I32:sub_odd_then_sub_i32
3362	0	},
3363	0	{ // VLS
3364	0	0, // VLS:sub_even
3365	0	0, // VLS:sub_f32
3366	0	0, // VLS:sub_i32
3367	0	0, // VLS:sub_odd
3368	0	0, // VLS:sub_vm_even
3369	0	0, // VLS:sub_vm_odd
3370	0	0, // VLS:sub_odd_then_sub_f32
3371	0	0, // VLS:sub_odd_then_sub_i32
3372	0	},
3373	0	{ // I64
3374	0	0, // I64:sub_even
3375	0	1, // I64:sub_f32 -> F32
3376	0	2, // I64:sub_i32 -> I32
3377	0	0, // I64:sub_odd
3378	0	0, // I64:sub_vm_even
3379	0	0, // I64:sub_vm_odd
3380	0	0, // I64:sub_odd_then_sub_f32
3381	0	0, // I64:sub_odd_then_sub_i32
3382	0	},
3383	0	{ // MISC
3384	0	0, // MISC:sub_even
3385	0	0, // MISC:sub_f32
3386	0	0, // MISC:sub_i32
3387	0	0, // MISC:sub_odd
3388	0	0, // MISC:sub_vm_even
3389	0	0, // MISC:sub_vm_odd
3390	0	0, // MISC:sub_odd_then_sub_f32
3391	0	0, // MISC:sub_odd_then_sub_i32
3392	0	},
3393	0	{ // F128
3394	0	4, // F128:sub_even -> I64
3395	0	1, // F128:sub_f32 -> F32
3396	0	2, // F128:sub_i32 -> I32
3397	0	4, // F128:sub_odd -> I64
3398	0	0, // F128:sub_vm_even
3399	0	0, // F128:sub_vm_odd
3400	0	1, // F128:sub_odd_then_sub_f32 -> F32
3401	0	2, // F128:sub_odd_then_sub_i32 -> I32
3402	0	},
3403	0	{ // VM
3404	0	0, // VM:sub_even
3405	0	0, // VM:sub_f32
3406	0	0, // VM:sub_i32
3407	0	0, // VM:sub_odd
3408	0	0, // VM:sub_vm_even
3409	0	0, // VM:sub_vm_odd
3410	0	0, // VM:sub_odd_then_sub_f32
3411	0	0, // VM:sub_odd_then_sub_i32
3412	0	},
3413	0	{ // VM512
3414	0	0, // VM512:sub_even
3415	0	0, // VM512:sub_f32
3416	0	0, // VM512:sub_i32
3417	0	0, // VM512:sub_odd
3418	0	7, // VM512:sub_vm_even -> VM
3419	0	7, // VM512:sub_vm_odd -> VM
3420	0	0, // VM512:sub_odd_then_sub_f32
3421	0	0, // VM512:sub_odd_then_sub_i32
3422	0	},
3423	0	{ // VM512_with_sub_vm_even
3424	0	0, // VM512_with_sub_vm_even:sub_even
3425	0	0, // VM512_with_sub_vm_even:sub_f32
3426	0	0, // VM512_with_sub_vm_even:sub_i32
3427	0	0, // VM512_with_sub_vm_even:sub_odd
3428	0	7, // VM512_with_sub_vm_even:sub_vm_even -> VM
3429	0	7, // VM512_with_sub_vm_even:sub_vm_odd -> VM
3430	0	0, // VM512_with_sub_vm_even:sub_odd_then_sub_f32
3431	0	0, // VM512_with_sub_vm_even:sub_odd_then_sub_i32
3432	0	},
3433	0	{ // V64
3434	0	0, // V64:sub_even
3435	0	0, // V64:sub_f32
3436	0	0, // V64:sub_i32
3437	0	0, // V64:sub_odd
3438	0	0, // V64:sub_vm_even
3439	0	0, // V64:sub_vm_odd
3440	0	0, // V64:sub_odd_then_sub_f32
3441	0	0, // V64:sub_odd_then_sub_i32
3442	0	},
3443	0	};
3444	0	assert(RC && "Missing regclass");
3445	0	if (!Idx) return RC;
3446	0	--Idx;
3447	0	assert(Idx < 8 && "Bad subreg");
3448	0	unsigned TV = Table[RC->getID()][Idx];
3449	0	return TV ? getRegClass(TV - 1) : nullptr;
3450	0	}
3451
3452		/// Get the weight in units of pressure for this register class.
3453		const RegClassWeight &VEGenRegisterInfo::
3454	1.64M	getRegClassWeight(const TargetRegisterClass *RC) const {
3455	1.64M	static const RegClassWeight RCWeightTable[] = {
3456	1.64M	{1, 64}, // F32
3457	1.64M	{1, 64}, // I32
3458	1.64M	{1, 1}, // VLS
3459	1.64M	{1, 64}, // I64
3460	1.64M	{1, 23}, // MISC
3461	1.64M	{2, 64}, // F128
3462	1.64M	{1, 16}, // VM
3463	1.64M	{2, 16}, // VM512
3464	1.64M	{2, 14}, // VM512_with_sub_vm_even
3465	1.64M	{1, 65}, // V64
3466	1.64M	};
3467	1.64M	return RCWeightTable[RC->getID()];
3468	1.64M	}
3469
3470		/// Get the weight in units of pressure for this register unit.
3471		unsigned VEGenRegisterInfo::
3472	26.3k	getRegUnitWeight(unsigned RegUnit) const {
3473	26.3k	assert(RegUnit < 171 && "invalid register unit");
3474	0	static const uint8_t RUWeightTable[] = {
3475	26.3k	0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, };
3476	26.3k	return RUWeightTable[RegUnit];
3477	26.3k	}
3478
3479
3480		// Get the number of dimensions of register pressure.
3481	27.7k	unsigned VEGenRegisterInfo::getNumRegPressureSets() const {
3482	27.7k	return 7;
3483	27.7k	}
3484
3485		// Get the name of this register unit pressure set.
3486		const char *VEGenRegisterInfo::
3487	0	getRegPressureSetName(unsigned Idx) const {
3488	0	static const char *PressureNameTable[] = {
3489	0	"VLS",
3490	0	"VM512",
3491	0	"VM",
3492	0	"VM_with_VM512",
3493	0	"MISC",
3494	0	"F32",
3495	0	"V64",
3496	0	};
3497	0	return PressureNameTable[Idx];
3498	0	}
3499
3500		// Get the register unit pressure limit for this dimension.
3501		// This limit must be adjusted dynamically for reserved registers.
3502		unsigned VEGenRegisterInfo::
3503	33.6k	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3504	33.6k	static const uint8_t PressureLimitTable[] = {
3505	33.6k	1, // 0: VLS
3506	33.6k	16, // 1: VM512
3507	33.6k	16, // 2: VM
3508	33.6k	18, // 3: VM_with_VM512
3509	33.6k	23, // 4: MISC
3510	33.6k	64, // 5: F32
3511	33.6k	65, // 6: V64
3512	33.6k	};
3513	33.6k	return PressureLimitTable[Idx];
3514	33.6k	}
3515
3516		/// Table of pressure sets per register class or unit.
3517		static const int RCSetsTable[] = {
3518		/* 0 */ 0, -1,
3519		/* 2 */ 1, 3, -1,
3520		/* 5 */ 1, 2, 3, -1,
3521		/* 9 */ 4, -1,
3522		/* 11 */ 5, -1,
3523		/* 13 */ 6, -1,
3524		};
3525
3526		/// Get the dimensions of register pressure impacted by this register class.
3527		/// Returns a -1 terminated array of pressure set IDs
3528		const int *VEGenRegisterInfo::
3529	1.72M	getRegClassPressureSets(const TargetRegisterClass *RC) const {
3530	1.72M	static const uint8_t RCSetStartTable[] = {
3531	1.72M	11,11,0,11,9,11,6,2,5,13,};
3532	1.72M	return &RCSetsTable[RCSetStartTable[RC->getID()]];
3533	1.72M	}
3534
3535		/// Get the dimensions of register pressure impacted by this register unit.
3536		/// Returns a -1 terminated array of pressure set IDs
3537		const int *VEGenRegisterInfo::
3538	26.3k	getRegUnitPressureSets(unsigned RegUnit) const {
3539	26.3k	assert(RegUnit < 171 && "invalid register unit");
3540	0	static const uint8_t RUSetStartTable[] = {
3541	26.3k	1,9,9,9,9,13,0,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,5,2,};
3542	26.3k	return &RCSetsTable[RUSetStartTable[RegUnit]];
3543	26.3k	}
3544
3545		extern const MCRegisterDesc VERegDesc[];
3546		extern const int16_t VERegDiffLists[];
3547		extern const LaneBitmask VELaneMaskLists[];
3548		extern const char VERegStrings[];
3549		extern const char VERegClassStrings[];
3550		extern const MCPhysReg VERegUnitRoots[][2];
3551		extern const uint16_t VESubRegIdxLists[];
3552		extern const MCRegisterInfo::SubRegCoveredBits VESubRegIdxRanges[];
3553		extern const uint16_t VERegEncodingTable[];
3554		// VE Dwarf<->LLVM register mappings.
3555		extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[];
3556		extern const unsigned VEDwarfFlavour0Dwarf2LSize;
3557
3558		extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[];
3559		extern const unsigned VEEHFlavour0Dwarf2LSize;
3560
3561		extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[];
3562		extern const unsigned VEDwarfFlavour0L2DwarfSize;
3563
3564		extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[];
3565		extern const unsigned VEEHFlavour0L2DwarfSize;
3566
3567		VEGenRegisterInfo::
3568		VEGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3569		unsigned PC, unsigned HwMode)
3570		: TargetRegisterInfo(&VERegInfoDesc, RegisterClasses, RegisterClasses+10,
3571		SubRegIndexNameTable, SubRegIndexLaneMaskTable,
3572	2	LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
3573	2	InitMCRegisterInfo(VERegDesc, 339, RA, PC,
3574	2	VEMCRegisterClasses, 10,
3575	2	VERegUnitRoots,
3576	2	171,
3577	2	VERegDiffLists,
3578	2	VELaneMaskLists,
3579	2	VERegStrings,
3580	2	VERegClassStrings,
3581	2	VESubRegIdxLists,
3582	2	9,
3583	2	VESubRegIdxRanges,
3584	2	VERegEncodingTable);
3585
3586	2	switch (DwarfFlavour) {
3587	0	default:
3588	0	llvm_unreachable("Unknown DWARF flavour");
3589	2	case 0:
3590	2	mapDwarfRegsToLLVMRegs(VEDwarfFlavour0Dwarf2L, VEDwarfFlavour0Dwarf2LSize, false);
3591	2	break;
3592	2	}
3593	2	switch (EHFlavour) {
3594	0	default:
3595	0	llvm_unreachable("Unknown DWARF flavour");
3596	2	case 0:
3597	2	mapDwarfRegsToLLVMRegs(VEEHFlavour0Dwarf2L, VEEHFlavour0Dwarf2LSize, true);
3598	2	break;
3599	2	}
3600	2	switch (DwarfFlavour) {
3601	0	default:
3602	0	llvm_unreachable("Unknown DWARF flavour");
3603	2	case 0:
3604	2	mapLLVMRegsToDwarfRegs(VEDwarfFlavour0L2Dwarf, VEDwarfFlavour0L2DwarfSize, false);
3605	2	break;
3606	2	}
3607	2	switch (EHFlavour) {
3608	0	default:
3609	0	llvm_unreachable("Unknown DWARF flavour");
3610	2	case 0:
3611	2	mapLLVMRegsToDwarfRegs(VEEHFlavour0L2Dwarf, VEEHFlavour0L2DwarfSize, true);
3612	2	break;
3613	2	}
3614	2	}
3615
3616		static const MCPhysReg CSR_SaveList[] = { VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, 0 };
3617		static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000ff0, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
3618		static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
3619		static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
3620		static const MCPhysReg CSR_preserve_all_SaveList[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, 0 };
3621		static const uint32_t CSR_preserve_all_RegMask[] = { 0xf8000000, 0xfbffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xffffffff, 0x0007ffff, };
3622
3623
3624	0	ArrayRef<const uint32_t *> VEGenRegisterInfo::getRegMasks() const {
3625	0	static const uint32_t *const Masks[] = {
3626	0	CSR_RegMask,
3627	0	CSR_NoRegs_RegMask,
3628	0	CSR_preserve_all_RegMask,
3629	0	};
3630	0	return ArrayRef(Masks);
3631	0	}
3632
3633		bool VEGenRegisterInfo::
3634	0	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3635	0	return
3636	0	false;
3637	0	}
3638
3639		bool VEGenRegisterInfo::
3640	0	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3641	0	return
3642	0	false;
3643	0	}
3644
3645		bool VEGenRegisterInfo::
3646	0	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3647	0	return
3648	0	false;
3649	0	}
3650
3651		bool VEGenRegisterInfo::
3652	30.8k	isConstantPhysReg(MCRegister PhysReg) const {
3653	30.8k	return
3654	30.8k	PhysReg == VE::VM0 \|\|
3655	30.8k	PhysReg == VE::VMP0 \|\|
3656	30.8k	false;
3657	30.8k	}
3658
3659	0	ArrayRef<const char *> VEGenRegisterInfo::getRegMaskNames() const {
3660	0	static const char *Names[] = {
3661	0	"CSR",
3662	0	"CSR_NoRegs",
3663	0	"CSR_preserve_all",
3664	0	};
3665	0	return ArrayRef(Names);
3666	0	}
3667
3668		const VEFrameLowering *
3669	60.5k	VEGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3670	60.5k	return static_cast<const VEFrameLowering *>(
3671	60.5k	MF.getSubtarget().getFrameLowering());
3672	60.5k	}
3673
3674		} // end namespace llvm
3675
3676		#endif // GET_REGINFO_TARGET_DESC
3677

Coverage Report

Created: 2024-01-17 10:31