Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* "Fast" Instruction Selector for the WebAssembly target                     *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
// FastEmit Immediate Predicate functions.
11
0
static bool Predicate_ImmI8(int64_t Imm) {
12
0
return -(1 << (8 - 1)) <= Imm && Imm < (1 << (8 - 1));
13
0
}
14
0
static bool Predicate_ImmI16(int64_t Imm) {
15
0
return -(1 << (16 - 1)) <= Imm && Imm < (1 << (16 - 1));
16
0
}
17
0
static bool Predicate_LaneIdx32(int64_t Imm) {
18
0
return 0 <= Imm && Imm < 32;
19
0
}
20
0
static bool Predicate_LaneIdx16(int64_t Imm) {
21
0
return 0 <= Imm && Imm < 16;
22
0
}
23
0
static bool Predicate_LaneIdx8(int64_t Imm) {
24
0
return 0 <= Imm && Imm < 8;
25
0
}
26
0
static bool Predicate_LaneIdx4(int64_t Imm) {
27
0
return 0 <= Imm && Imm < 4;
28
0
}
29
0
static bool Predicate_LaneIdx2(int64_t Imm) {
30
0
return 0 <= Imm && Imm < 2;
31
0
}
32
33
34
// FastEmit functions for ISD::ABS.
35
36
0
unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
37
0
  if (RetVT.SimpleTy != MVT::v16i8)
38
0
    return 0;
39
0
  if ((Subtarget->hasSIMD128())) {
40
0
    return fastEmitInst_r(WebAssembly::ABS_I8x16, &WebAssembly::V128RegClass, Op0);
41
0
  }
42
0
  return 0;
43
0
}
44
45
0
unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
46
0
  if (RetVT.SimpleTy != MVT::v8i16)
47
0
    return 0;
48
0
  if ((Subtarget->hasSIMD128())) {
49
0
    return fastEmitInst_r(WebAssembly::ABS_I16x8, &WebAssembly::V128RegClass, Op0);
50
0
  }
51
0
  return 0;
52
0
}
53
54
0
unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
55
0
  if (RetVT.SimpleTy != MVT::v4i32)
56
0
    return 0;
57
0
  if ((Subtarget->hasSIMD128())) {
58
0
    return fastEmitInst_r(WebAssembly::ABS_I32x4, &WebAssembly::V128RegClass, Op0);
59
0
  }
60
0
  return 0;
61
0
}
62
63
0
unsigned fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
64
0
  if (RetVT.SimpleTy != MVT::v2i64)
65
0
    return 0;
66
0
  if ((Subtarget->hasSIMD128())) {
67
0
    return fastEmitInst_r(WebAssembly::ABS_I64x2, &WebAssembly::V128RegClass, Op0);
68
0
  }
69
0
  return 0;
70
0
}
71
72
0
unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0) {
73
0
  switch (VT.SimpleTy) {
74
0
  case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0);
75
0
  case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0);
76
0
  case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0);
77
0
  case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0);
78
0
  default: return 0;
79
0
  }
80
0
}
81
82
// FastEmit functions for ISD::ANY_EXTEND.
83
84
0
unsigned fastEmit_ISD_ANY_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
85
0
  if (RetVT.SimpleTy != MVT::i64)
86
0
    return 0;
87
0
  return fastEmitInst_r(WebAssembly::I64_EXTEND_U_I32, &WebAssembly::I64RegClass, Op0);
88
0
}
89
90
0
unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
91
0
  switch (VT.SimpleTy) {
92
0
  case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i32_r(RetVT, Op0);
93
0
  default: return 0;
94
0
  }
95
0
}
96
97
// FastEmit functions for ISD::BITCAST.
98
99
0
unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0) {
100
0
  if (RetVT.SimpleTy != MVT::f32)
101
0
    return 0;
102
0
  return fastEmitInst_r(WebAssembly::F32_REINTERPRET_I32, &WebAssembly::F32RegClass, Op0);
103
0
}
104
105
0
unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0) {
106
0
  if (RetVT.SimpleTy != MVT::f64)
107
0
    return 0;
108
0
  return fastEmitInst_r(WebAssembly::F64_REINTERPRET_I64, &WebAssembly::F64RegClass, Op0);
109
0
}
110
111
0
unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0) {
112
0
  if (RetVT.SimpleTy != MVT::i32)
113
0
    return 0;
114
0
  return fastEmitInst_r(WebAssembly::I32_REINTERPRET_F32, &WebAssembly::I32RegClass, Op0);
115
0
}
116
117
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) {
118
0
  if (RetVT.SimpleTy != MVT::i64)
119
0
    return 0;
120
0
  return fastEmitInst_r(WebAssembly::I64_REINTERPRET_F64, &WebAssembly::I64RegClass, Op0);
121
0
}
122
123
0
unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) {
124
0
  switch (VT.SimpleTy) {
125
0
  case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
126
0
  case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
127
0
  case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
128
0
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
129
0
  default: return 0;
130
0
  }
131
0
}
132
133
// FastEmit functions for ISD::CTLZ.
134
135
0
unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) {
136
0
  if (RetVT.SimpleTy != MVT::i32)
137
0
    return 0;
138
0
  return fastEmitInst_r(WebAssembly::CLZ_I32, &WebAssembly::I32RegClass, Op0);
139
0
}
140
141
0
unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) {
142
0
  if (RetVT.SimpleTy != MVT::i64)
143
0
    return 0;
144
0
  return fastEmitInst_r(WebAssembly::CLZ_I64, &WebAssembly::I64RegClass, Op0);
145
0
}
146
147
0
unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) {
148
0
  switch (VT.SimpleTy) {
149
0
  case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
150
0
  case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
151
0
  default: return 0;
152
0
  }
153
0
}
154
155
// FastEmit functions for ISD::CTPOP.
156
157
0
unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) {
158
0
  if (RetVT.SimpleTy != MVT::i32)
159
0
    return 0;
160
0
  return fastEmitInst_r(WebAssembly::POPCNT_I32, &WebAssembly::I32RegClass, Op0);
161
0
}
162
163
0
unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) {
164
0
  if (RetVT.SimpleTy != MVT::i64)
165
0
    return 0;
166
0
  return fastEmitInst_r(WebAssembly::POPCNT_I64, &WebAssembly::I64RegClass, Op0);
167
0
}
168
169
0
unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
170
0
  if (RetVT.SimpleTy != MVT::v16i8)
171
0
    return 0;
172
0
  if ((Subtarget->hasSIMD128())) {
173
0
    return fastEmitInst_r(WebAssembly::POPCNT_I8x16, &WebAssembly::V128RegClass, Op0);
174
0
  }
175
0
  return 0;
176
0
}
177
178
0
unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) {
179
0
  switch (VT.SimpleTy) {
180
0
  case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
181
0
  case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
182
0
  case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
183
0
  default: return 0;
184
0
  }
185
0
}
186
187
// FastEmit functions for ISD::CTTZ.
188
189
0
unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0) {
190
0
  if (RetVT.SimpleTy != MVT::i32)
191
0
    return 0;
192
0
  return fastEmitInst_r(WebAssembly::CTZ_I32, &WebAssembly::I32RegClass, Op0);
193
0
}
194
195
0
unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0) {
196
0
  if (RetVT.SimpleTy != MVT::i64)
197
0
    return 0;
198
0
  return fastEmitInst_r(WebAssembly::CTZ_I64, &WebAssembly::I64RegClass, Op0);
199
0
}
200
201
0
unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0) {
202
0
  switch (VT.SimpleTy) {
203
0
  case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
204
0
  case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
205
0
  default: return 0;
206
0
  }
207
0
}
208
209
// FastEmit functions for ISD::FABS.
210
211
0
unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) {
212
0
  if (RetVT.SimpleTy != MVT::f32)
213
0
    return 0;
214
0
  return fastEmitInst_r(WebAssembly::ABS_F32, &WebAssembly::F32RegClass, Op0);
215
0
}
216
217
0
unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) {
218
0
  if (RetVT.SimpleTy != MVT::f64)
219
0
    return 0;
220
0
  return fastEmitInst_r(WebAssembly::ABS_F64, &WebAssembly::F64RegClass, Op0);
221
0
}
222
223
0
unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
224
0
  if (RetVT.SimpleTy != MVT::v4f32)
225
0
    return 0;
226
0
  if ((Subtarget->hasSIMD128())) {
227
0
    return fastEmitInst_r(WebAssembly::ABS_F32x4, &WebAssembly::V128RegClass, Op0);
228
0
  }
229
0
  return 0;
230
0
}
231
232
0
unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
233
0
  if (RetVT.SimpleTy != MVT::v2f64)
234
0
    return 0;
235
0
  if ((Subtarget->hasSIMD128())) {
236
0
    return fastEmitInst_r(WebAssembly::ABS_F64x2, &WebAssembly::V128RegClass, Op0);
237
0
  }
238
0
  return 0;
239
0
}
240
241
0
unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) {
242
0
  switch (VT.SimpleTy) {
243
0
  case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
244
0
  case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
245
0
  case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
246
0
  case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
247
0
  default: return 0;
248
0
  }
249
0
}
250
251
// FastEmit functions for ISD::FCEIL.
252
253
0
unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) {
254
0
  if (RetVT.SimpleTy != MVT::f32)
255
0
    return 0;
256
0
  return fastEmitInst_r(WebAssembly::CEIL_F32, &WebAssembly::F32RegClass, Op0);
257
0
}
258
259
0
unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) {
260
0
  if (RetVT.SimpleTy != MVT::f64)
261
0
    return 0;
262
0
  return fastEmitInst_r(WebAssembly::CEIL_F64, &WebAssembly::F64RegClass, Op0);
263
0
}
264
265
0
unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
266
0
  if (RetVT.SimpleTy != MVT::v4f32)
267
0
    return 0;
268
0
  if ((Subtarget->hasSIMD128())) {
269
0
    return fastEmitInst_r(WebAssembly::CEIL_F32x4, &WebAssembly::V128RegClass, Op0);
270
0
  }
271
0
  return 0;
272
0
}
273
274
0
unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
275
0
  if (RetVT.SimpleTy != MVT::v2f64)
276
0
    return 0;
277
0
  if ((Subtarget->hasSIMD128())) {
278
0
    return fastEmitInst_r(WebAssembly::CEIL_F64x2, &WebAssembly::V128RegClass, Op0);
279
0
  }
280
0
  return 0;
281
0
}
282
283
0
unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) {
284
0
  switch (VT.SimpleTy) {
285
0
  case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
286
0
  case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
287
0
  case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
288
0
  case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
289
0
  default: return 0;
290
0
  }
291
0
}
292
293
// FastEmit functions for ISD::FFLOOR.
294
295
0
unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
296
0
  if (RetVT.SimpleTy != MVT::f32)
297
0
    return 0;
298
0
  return fastEmitInst_r(WebAssembly::FLOOR_F32, &WebAssembly::F32RegClass, Op0);
299
0
}
300
301
0
unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
302
0
  if (RetVT.SimpleTy != MVT::f64)
303
0
    return 0;
304
0
  return fastEmitInst_r(WebAssembly::FLOOR_F64, &WebAssembly::F64RegClass, Op0);
305
0
}
306
307
0
unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
308
0
  if (RetVT.SimpleTy != MVT::v4f32)
309
0
    return 0;
310
0
  if ((Subtarget->hasSIMD128())) {
311
0
    return fastEmitInst_r(WebAssembly::FLOOR_F32x4, &WebAssembly::V128RegClass, Op0);
312
0
  }
313
0
  return 0;
314
0
}
315
316
0
unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
317
0
  if (RetVT.SimpleTy != MVT::v2f64)
318
0
    return 0;
319
0
  if ((Subtarget->hasSIMD128())) {
320
0
    return fastEmitInst_r(WebAssembly::FLOOR_F64x2, &WebAssembly::V128RegClass, Op0);
321
0
  }
322
0
  return 0;
323
0
}
324
325
0
unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) {
326
0
  switch (VT.SimpleTy) {
327
0
  case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
328
0
  case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
329
0
  case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
330
0
  case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
331
0
  default: return 0;
332
0
  }
333
0
}
334
335
// FastEmit functions for ISD::FNEARBYINT.
336
337
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
338
0
  if (RetVT.SimpleTy != MVT::f32)
339
0
    return 0;
340
0
  return fastEmitInst_r(WebAssembly::NEAREST_F32, &WebAssembly::F32RegClass, Op0);
341
0
}
342
343
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
344
0
  if (RetVT.SimpleTy != MVT::f64)
345
0
    return 0;
346
0
  return fastEmitInst_r(WebAssembly::NEAREST_F64, &WebAssembly::F64RegClass, Op0);
347
0
}
348
349
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
350
0
  if (RetVT.SimpleTy != MVT::v4f32)
351
0
    return 0;
352
0
  if ((Subtarget->hasSIMD128())) {
353
0
    return fastEmitInst_r(WebAssembly::NEAREST_F32x4, &WebAssembly::V128RegClass, Op0);
354
0
  }
355
0
  return 0;
356
0
}
357
358
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
359
0
  if (RetVT.SimpleTy != MVT::v2f64)
360
0
    return 0;
361
0
  if ((Subtarget->hasSIMD128())) {
362
0
    return fastEmitInst_r(WebAssembly::NEAREST_F64x2, &WebAssembly::V128RegClass, Op0);
363
0
  }
364
0
  return 0;
365
0
}
366
367
0
unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0) {
368
0
  switch (VT.SimpleTy) {
369
0
  case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0);
370
0
  case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0);
371
0
  case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
372
0
  case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
373
0
  default: return 0;
374
0
  }
375
0
}
376
377
// FastEmit functions for ISD::FNEG.
378
379
0
unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) {
380
0
  if (RetVT.SimpleTy != MVT::f32)
381
0
    return 0;
382
0
  return fastEmitInst_r(WebAssembly::NEG_F32, &WebAssembly::F32RegClass, Op0);
383
0
}
384
385
0
unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) {
386
0
  if (RetVT.SimpleTy != MVT::f64)
387
0
    return 0;
388
0
  return fastEmitInst_r(WebAssembly::NEG_F64, &WebAssembly::F64RegClass, Op0);
389
0
}
390
391
0
unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
392
0
  if (RetVT.SimpleTy != MVT::v4f32)
393
0
    return 0;
394
0
  if ((Subtarget->hasSIMD128())) {
395
0
    return fastEmitInst_r(WebAssembly::NEG_F32x4, &WebAssembly::V128RegClass, Op0);
396
0
  }
397
0
  return 0;
398
0
}
399
400
0
unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
401
0
  if (RetVT.SimpleTy != MVT::v2f64)
402
0
    return 0;
403
0
  if ((Subtarget->hasSIMD128())) {
404
0
    return fastEmitInst_r(WebAssembly::NEG_F64x2, &WebAssembly::V128RegClass, Op0);
405
0
  }
406
0
  return 0;
407
0
}
408
409
0
unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) {
410
0
  switch (VT.SimpleTy) {
411
0
  case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
412
0
  case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
413
0
  case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
414
0
  case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
415
0
  default: return 0;
416
0
  }
417
0
}
418
419
// FastEmit functions for ISD::FP_EXTEND.
420
421
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) {
422
0
  if (RetVT.SimpleTy != MVT::f64)
423
0
    return 0;
424
0
  return fastEmitInst_r(WebAssembly::F64_PROMOTE_F32, &WebAssembly::F64RegClass, Op0);
425
0
}
426
427
0
unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
428
0
  switch (VT.SimpleTy) {
429
0
  case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
430
0
  default: return 0;
431
0
  }
432
0
}
433
434
// FastEmit functions for ISD::FP_ROUND.
435
436
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) {
437
0
  if (RetVT.SimpleTy != MVT::f32)
438
0
    return 0;
439
0
  return fastEmitInst_r(WebAssembly::F32_DEMOTE_F64, &WebAssembly::F32RegClass, Op0);
440
0
}
441
442
0
unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) {
443
0
  switch (VT.SimpleTy) {
444
0
  case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
445
0
  default: return 0;
446
0
  }
447
0
}
448
449
// FastEmit functions for ISD::FP_TO_SINT.
450
451
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0) {
452
0
  if ((!Subtarget->hasNontrappingFPToInt())) {
453
0
    return fastEmitInst_r(WebAssembly::FP_TO_SINT_I32_F32, &WebAssembly::I32RegClass, Op0);
454
0
  }
455
0
  if ((Subtarget->hasNontrappingFPToInt())) {
456
0
    return fastEmitInst_r(WebAssembly::I32_TRUNC_S_SAT_F32, &WebAssembly::I32RegClass, Op0);
457
0
  }
458
0
  return 0;
459
0
}
460
461
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0) {
462
0
  if ((!Subtarget->hasNontrappingFPToInt())) {
463
0
    return fastEmitInst_r(WebAssembly::FP_TO_SINT_I64_F32, &WebAssembly::I64RegClass, Op0);
464
0
  }
465
0
  if ((Subtarget->hasNontrappingFPToInt())) {
466
0
    return fastEmitInst_r(WebAssembly::I64_TRUNC_S_SAT_F32, &WebAssembly::I64RegClass, Op0);
467
0
  }
468
0
  return 0;
469
0
}
470
471
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
472
0
switch (RetVT.SimpleTy) {
473
0
  case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0);
474
0
  case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0);
475
0
  default: return 0;
476
0
}
477
0
}
478
479
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0) {
480
0
  if ((!Subtarget->hasNontrappingFPToInt())) {
481
0
    return fastEmitInst_r(WebAssembly::FP_TO_SINT_I32_F64, &WebAssembly::I32RegClass, Op0);
482
0
  }
483
0
  if ((Subtarget->hasNontrappingFPToInt())) {
484
0
    return fastEmitInst_r(WebAssembly::I32_TRUNC_S_SAT_F64, &WebAssembly::I32RegClass, Op0);
485
0
  }
486
0
  return 0;
487
0
}
488
489
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0) {
490
0
  if ((!Subtarget->hasNontrappingFPToInt())) {
491
0
    return fastEmitInst_r(WebAssembly::FP_TO_SINT_I64_F64, &WebAssembly::I64RegClass, Op0);
492
0
  }
493
0
  if ((Subtarget->hasNontrappingFPToInt())) {
494
0
    return fastEmitInst_r(WebAssembly::I64_TRUNC_S_SAT_F64, &WebAssembly::I64RegClass, Op0);
495
0
  }
496
0
  return 0;
497
0
}
498
499
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
500
0
switch (RetVT.SimpleTy) {
501
0
  case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0);
502
0
  case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0);
503
0
  default: return 0;
504
0
}
505
0
}
506
507
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
508
0
  if (RetVT.SimpleTy != MVT::v4i32)
509
0
    return 0;
510
0
  if ((Subtarget->hasSIMD128())) {
511
0
    return fastEmitInst_r(WebAssembly::fp_to_sint_I32x4, &WebAssembly::V128RegClass, Op0);
512
0
  }
513
0
  return 0;
514
0
}
515
516
0
unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) {
517
0
  switch (VT.SimpleTy) {
518
0
  case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
519
0
  case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
520
0
  case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
521
0
  default: return 0;
522
0
  }
523
0
}
524
525
// FastEmit functions for ISD::FP_TO_UINT.
526
527
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0) {
528
0
  if ((!Subtarget->hasNontrappingFPToInt())) {
529
0
    return fastEmitInst_r(WebAssembly::FP_TO_UINT_I32_F32, &WebAssembly::I32RegClass, Op0);
530
0
  }
531
0
  if ((Subtarget->hasNontrappingFPToInt())) {
532
0
    return fastEmitInst_r(WebAssembly::I32_TRUNC_U_SAT_F32, &WebAssembly::I32RegClass, Op0);
533
0
  }
534
0
  return 0;
535
0
}
536
537
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0) {
538
0
  if ((!Subtarget->hasNontrappingFPToInt())) {
539
0
    return fastEmitInst_r(WebAssembly::FP_TO_UINT_I64_F32, &WebAssembly::I64RegClass, Op0);
540
0
  }
541
0
  if ((Subtarget->hasNontrappingFPToInt())) {
542
0
    return fastEmitInst_r(WebAssembly::I64_TRUNC_U_SAT_F32, &WebAssembly::I64RegClass, Op0);
543
0
  }
544
0
  return 0;
545
0
}
546
547
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
548
0
switch (RetVT.SimpleTy) {
549
0
  case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0);
550
0
  case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0);
551
0
  default: return 0;
552
0
}
553
0
}
554
555
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0) {
556
0
  if ((!Subtarget->hasNontrappingFPToInt())) {
557
0
    return fastEmitInst_r(WebAssembly::FP_TO_UINT_I32_F64, &WebAssembly::I32RegClass, Op0);
558
0
  }
559
0
  if ((Subtarget->hasNontrappingFPToInt())) {
560
0
    return fastEmitInst_r(WebAssembly::I32_TRUNC_U_SAT_F64, &WebAssembly::I32RegClass, Op0);
561
0
  }
562
0
  return 0;
563
0
}
564
565
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0) {
566
0
  if ((!Subtarget->hasNontrappingFPToInt())) {
567
0
    return fastEmitInst_r(WebAssembly::FP_TO_UINT_I64_F64, &WebAssembly::I64RegClass, Op0);
568
0
  }
569
0
  if ((Subtarget->hasNontrappingFPToInt())) {
570
0
    return fastEmitInst_r(WebAssembly::I64_TRUNC_U_SAT_F64, &WebAssembly::I64RegClass, Op0);
571
0
  }
572
0
  return 0;
573
0
}
574
575
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
576
0
switch (RetVT.SimpleTy) {
577
0
  case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0);
578
0
  case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0);
579
0
  default: return 0;
580
0
}
581
0
}
582
583
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
584
0
  if (RetVT.SimpleTy != MVT::v4i32)
585
0
    return 0;
586
0
  if ((Subtarget->hasSIMD128())) {
587
0
    return fastEmitInst_r(WebAssembly::fp_to_uint_I32x4, &WebAssembly::V128RegClass, Op0);
588
0
  }
589
0
  return 0;
590
0
}
591
592
0
unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) {
593
0
  switch (VT.SimpleTy) {
594
0
  case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
595
0
  case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
596
0
  case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
597
0
  default: return 0;
598
0
  }
599
0
}
600
601
// FastEmit functions for ISD::FRINT.
602
603
0
unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
604
0
  if (RetVT.SimpleTy != MVT::f32)
605
0
    return 0;
606
0
  return fastEmitInst_r(WebAssembly::NEAREST_F32, &WebAssembly::F32RegClass, Op0);
607
0
}
608
609
0
unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
610
0
  if (RetVT.SimpleTy != MVT::f64)
611
0
    return 0;
612
0
  return fastEmitInst_r(WebAssembly::NEAREST_F64, &WebAssembly::F64RegClass, Op0);
613
0
}
614
615
0
unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
616
0
  if (RetVT.SimpleTy != MVT::v4f32)
617
0
    return 0;
618
0
  return fastEmitInst_r(WebAssembly::NEAREST_F32x4, &WebAssembly::V128RegClass, Op0);
619
0
}
620
621
0
unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
622
0
  if (RetVT.SimpleTy != MVT::v2f64)
623
0
    return 0;
624
0
  return fastEmitInst_r(WebAssembly::NEAREST_F64x2, &WebAssembly::V128RegClass, Op0);
625
0
}
626
627
0
unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) {
628
0
  switch (VT.SimpleTy) {
629
0
  case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0);
630
0
  case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
631
0
  case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
632
0
  case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
633
0
  default: return 0;
634
0
  }
635
0
}
636
637
// FastEmit functions for ISD::FROUNDEVEN.
638
639
0
unsigned fastEmit_ISD_FROUNDEVEN_MVT_f32_r(MVT RetVT, unsigned Op0) {
640
0
  if (RetVT.SimpleTy != MVT::f32)
641
0
    return 0;
642
0
  return fastEmitInst_r(WebAssembly::NEAREST_F32, &WebAssembly::F32RegClass, Op0);
643
0
}
644
645
0
unsigned fastEmit_ISD_FROUNDEVEN_MVT_f64_r(MVT RetVT, unsigned Op0) {
646
0
  if (RetVT.SimpleTy != MVT::f64)
647
0
    return 0;
648
0
  return fastEmitInst_r(WebAssembly::NEAREST_F64, &WebAssembly::F64RegClass, Op0);
649
0
}
650
651
0
unsigned fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
652
0
  if (RetVT.SimpleTy != MVT::v4f32)
653
0
    return 0;
654
0
  return fastEmitInst_r(WebAssembly::NEAREST_F32x4, &WebAssembly::V128RegClass, Op0);
655
0
}
656
657
0
unsigned fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
658
0
  if (RetVT.SimpleTy != MVT::v2f64)
659
0
    return 0;
660
0
  return fastEmitInst_r(WebAssembly::NEAREST_F64x2, &WebAssembly::V128RegClass, Op0);
661
0
}
662
663
0
unsigned fastEmit_ISD_FROUNDEVEN_r(MVT VT, MVT RetVT, unsigned Op0) {
664
0
  switch (VT.SimpleTy) {
665
0
  case MVT::f32: return fastEmit_ISD_FROUNDEVEN_MVT_f32_r(RetVT, Op0);
666
0
  case MVT::f64: return fastEmit_ISD_FROUNDEVEN_MVT_f64_r(RetVT, Op0);
667
0
  case MVT::v4f32: return fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(RetVT, Op0);
668
0
  case MVT::v2f64: return fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(RetVT, Op0);
669
0
  default: return 0;
670
0
  }
671
0
}
672
673
// FastEmit functions for ISD::FSQRT.
674
675
0
unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) {
676
0
  if (RetVT.SimpleTy != MVT::f32)
677
0
    return 0;
678
0
  return fastEmitInst_r(WebAssembly::SQRT_F32, &WebAssembly::F32RegClass, Op0);
679
0
}
680
681
0
unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) {
682
0
  if (RetVT.SimpleTy != MVT::f64)
683
0
    return 0;
684
0
  return fastEmitInst_r(WebAssembly::SQRT_F64, &WebAssembly::F64RegClass, Op0);
685
0
}
686
687
0
unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
688
0
  if (RetVT.SimpleTy != MVT::v4f32)
689
0
    return 0;
690
0
  if ((Subtarget->hasSIMD128())) {
691
0
    return fastEmitInst_r(WebAssembly::SQRT_F32x4, &WebAssembly::V128RegClass, Op0);
692
0
  }
693
0
  return 0;
694
0
}
695
696
0
unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
697
0
  if (RetVT.SimpleTy != MVT::v2f64)
698
0
    return 0;
699
0
  if ((Subtarget->hasSIMD128())) {
700
0
    return fastEmitInst_r(WebAssembly::SQRT_F64x2, &WebAssembly::V128RegClass, Op0);
701
0
  }
702
0
  return 0;
703
0
}
704
705
0
unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
706
0
  switch (VT.SimpleTy) {
707
0
  case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
708
0
  case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
709
0
  case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
710
0
  case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
711
0
  default: return 0;
712
0
  }
713
0
}
714
715
// FastEmit functions for ISD::FTRUNC.
716
717
0
unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) {
718
0
  if (RetVT.SimpleTy != MVT::f32)
719
0
    return 0;
720
0
  return fastEmitInst_r(WebAssembly::TRUNC_F32, &WebAssembly::F32RegClass, Op0);
721
0
}
722
723
0
unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) {
724
0
  if (RetVT.SimpleTy != MVT::f64)
725
0
    return 0;
726
0
  return fastEmitInst_r(WebAssembly::TRUNC_F64, &WebAssembly::F64RegClass, Op0);
727
0
}
728
729
0
unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
730
0
  if (RetVT.SimpleTy != MVT::v4f32)
731
0
    return 0;
732
0
  if ((Subtarget->hasSIMD128())) {
733
0
    return fastEmitInst_r(WebAssembly::TRUNC_F32x4, &WebAssembly::V128RegClass, Op0);
734
0
  }
735
0
  return 0;
736
0
}
737
738
0
unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
739
0
  if (RetVT.SimpleTy != MVT::v2f64)
740
0
    return 0;
741
0
  if ((Subtarget->hasSIMD128())) {
742
0
    return fastEmitInst_r(WebAssembly::TRUNC_F64x2, &WebAssembly::V128RegClass, Op0);
743
0
  }
744
0
  return 0;
745
0
}
746
747
0
unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) {
748
0
  switch (VT.SimpleTy) {
749
0
  case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
750
0
  case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
751
0
  case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
752
0
  case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
753
0
  default: return 0;
754
0
  }
755
0
}
756
757
// FastEmit functions for ISD::SCALAR_TO_VECTOR.
758
759
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(unsigned Op0) {
760
0
  return fastEmitInst_r(WebAssembly::SPLAT_I8x16, &WebAssembly::V128RegClass, Op0);
761
0
}
762
763
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(unsigned Op0) {
764
0
  return fastEmitInst_r(WebAssembly::SPLAT_I16x8, &WebAssembly::V128RegClass, Op0);
765
0
}
766
767
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(unsigned Op0) {
768
0
  return fastEmitInst_r(WebAssembly::SPLAT_I32x4, &WebAssembly::V128RegClass, Op0);
769
0
}
770
771
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) {
772
0
switch (RetVT.SimpleTy) {
773
0
  case MVT::v16i8: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
774
0
  case MVT::v8i16: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
775
0
  case MVT::v4i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
776
0
  default: return 0;
777
0
}
778
0
}
779
780
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, unsigned Op0) {
781
0
  if (RetVT.SimpleTy != MVT::v2i64)
782
0
    return 0;
783
0
  return fastEmitInst_r(WebAssembly::SPLAT_I64x2, &WebAssembly::V128RegClass, Op0);
784
0
}
785
786
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
787
0
  if (RetVT.SimpleTy != MVT::v4f32)
788
0
    return 0;
789
0
  return fastEmitInst_r(WebAssembly::SPLAT_F32x4, &WebAssembly::V128RegClass, Op0);
790
0
}
791
792
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
793
0
  if (RetVT.SimpleTy != MVT::v2f64)
794
0
    return 0;
795
0
  return fastEmitInst_r(WebAssembly::SPLAT_F64x2, &WebAssembly::V128RegClass, Op0);
796
0
}
797
798
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) {
799
0
  switch (VT.SimpleTy) {
800
0
  case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
801
0
  case MVT::i64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
802
0
  case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
803
0
  case MVT::f64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
804
0
  default: return 0;
805
0
  }
806
0
}
807
808
// FastEmit functions for ISD::SIGN_EXTEND.
809
810
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
811
0
  if (RetVT.SimpleTy != MVT::i64)
812
0
    return 0;
813
0
  return fastEmitInst_r(WebAssembly::I64_EXTEND_S_I32, &WebAssembly::I64RegClass, Op0);
814
0
}
815
816
0
unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
817
0
  switch (VT.SimpleTy) {
818
0
  case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
819
0
  default: return 0;
820
0
  }
821
0
}
822
823
// FastEmit functions for ISD::SINT_TO_FP.
824
825
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
826
0
  return fastEmitInst_r(WebAssembly::F32_CONVERT_S_I32, &WebAssembly::F32RegClass, Op0);
827
0
}
828
829
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
830
0
  return fastEmitInst_r(WebAssembly::F64_CONVERT_S_I32, &WebAssembly::F64RegClass, Op0);
831
0
}
832
833
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
834
0
switch (RetVT.SimpleTy) {
835
0
  case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
836
0
  case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
837
0
  default: return 0;
838
0
}
839
0
}
840
841
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) {
842
0
  return fastEmitInst_r(WebAssembly::F32_CONVERT_S_I64, &WebAssembly::F32RegClass, Op0);
843
0
}
844
845
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) {
846
0
  return fastEmitInst_r(WebAssembly::F64_CONVERT_S_I64, &WebAssembly::F64RegClass, Op0);
847
0
}
848
849
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) {
850
0
switch (RetVT.SimpleTy) {
851
0
  case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
852
0
  case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
853
0
  default: return 0;
854
0
}
855
0
}
856
857
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
858
0
  if (RetVT.SimpleTy != MVT::v4f32)
859
0
    return 0;
860
0
  if ((Subtarget->hasSIMD128())) {
861
0
    return fastEmitInst_r(WebAssembly::sint_to_fp_F32x4, &WebAssembly::V128RegClass, Op0);
862
0
  }
863
0
  return 0;
864
0
}
865
866
0
unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
867
0
  switch (VT.SimpleTy) {
868
0
  case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
869
0
  case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
870
0
  case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
871
0
  default: return 0;
872
0
  }
873
0
}
874
875
// FastEmit functions for ISD::SPLAT_VECTOR.
876
877
0
unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(unsigned Op0) {
878
0
  if ((Subtarget->hasSIMD128())) {
879
0
    return fastEmitInst_r(WebAssembly::SPLAT_I8x16, &WebAssembly::V128RegClass, Op0);
880
0
  }
881
0
  return 0;
882
0
}
883
884
0
unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(unsigned Op0) {
885
0
  if ((Subtarget->hasSIMD128())) {
886
0
    return fastEmitInst_r(WebAssembly::SPLAT_I16x8, &WebAssembly::V128RegClass, Op0);
887
0
  }
888
0
  return 0;
889
0
}
890
891
0
unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(unsigned Op0) {
892
0
  if ((Subtarget->hasSIMD128())) {
893
0
    return fastEmitInst_r(WebAssembly::SPLAT_I32x4, &WebAssembly::V128RegClass, Op0);
894
0
  }
895
0
  return 0;
896
0
}
897
898
0
unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) {
899
0
switch (RetVT.SimpleTy) {
900
0
  case MVT::v16i8: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
901
0
  case MVT::v8i16: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
902
0
  case MVT::v4i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
903
0
  default: return 0;
904
0
}
905
0
}
906
907
0
unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(MVT RetVT, unsigned Op0) {
908
0
  if (RetVT.SimpleTy != MVT::v2i64)
909
0
    return 0;
910
0
  if ((Subtarget->hasSIMD128())) {
911
0
    return fastEmitInst_r(WebAssembly::SPLAT_I64x2, &WebAssembly::V128RegClass, Op0);
912
0
  }
913
0
  return 0;
914
0
}
915
916
0
unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
917
0
  if (RetVT.SimpleTy != MVT::v4f32)
918
0
    return 0;
919
0
  if ((Subtarget->hasSIMD128())) {
920
0
    return fastEmitInst_r(WebAssembly::SPLAT_F32x4, &WebAssembly::V128RegClass, Op0);
921
0
  }
922
0
  return 0;
923
0
}
924
925
0
unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
926
0
  if (RetVT.SimpleTy != MVT::v2f64)
927
0
    return 0;
928
0
  if ((Subtarget->hasSIMD128())) {
929
0
    return fastEmitInst_r(WebAssembly::SPLAT_F64x2, &WebAssembly::V128RegClass, Op0);
930
0
  }
931
0
  return 0;
932
0
}
933
934
0
unsigned fastEmit_ISD_SPLAT_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) {
935
0
  switch (VT.SimpleTy) {
936
0
  case MVT::i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(RetVT, Op0);
937
0
  case MVT::i64: return fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(RetVT, Op0);
938
0
  case MVT::f32: return fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(RetVT, Op0);
939
0
  case MVT::f64: return fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(RetVT, Op0);
940
0
  default: return 0;
941
0
  }
942
0
}
943
944
// FastEmit functions for ISD::TRUNCATE.
945
946
0
unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) {
947
0
  if (RetVT.SimpleTy != MVT::i32)
948
0
    return 0;
949
0
  return fastEmitInst_r(WebAssembly::I32_WRAP_I64, &WebAssembly::I32RegClass, Op0);
950
0
}
951
952
0
unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) {
953
0
  switch (VT.SimpleTy) {
954
0
  case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
955
0
  default: return 0;
956
0
  }
957
0
}
958
959
// FastEmit functions for ISD::UINT_TO_FP.
960
961
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
962
0
  return fastEmitInst_r(WebAssembly::F32_CONVERT_U_I32, &WebAssembly::F32RegClass, Op0);
963
0
}
964
965
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
966
0
  return fastEmitInst_r(WebAssembly::F64_CONVERT_U_I32, &WebAssembly::F64RegClass, Op0);
967
0
}
968
969
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
970
0
switch (RetVT.SimpleTy) {
971
0
  case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
972
0
  case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
973
0
  default: return 0;
974
0
}
975
0
}
976
977
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) {
978
0
  return fastEmitInst_r(WebAssembly::F32_CONVERT_U_I64, &WebAssembly::F32RegClass, Op0);
979
0
}
980
981
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) {
982
0
  return fastEmitInst_r(WebAssembly::F64_CONVERT_U_I64, &WebAssembly::F64RegClass, Op0);
983
0
}
984
985
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) {
986
0
switch (RetVT.SimpleTy) {
987
0
  case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
988
0
  case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
989
0
  default: return 0;
990
0
}
991
0
}
992
993
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
994
0
  if (RetVT.SimpleTy != MVT::v4f32)
995
0
    return 0;
996
0
  if ((Subtarget->hasSIMD128())) {
997
0
    return fastEmitInst_r(WebAssembly::uint_to_fp_F32x4, &WebAssembly::V128RegClass, Op0);
998
0
  }
999
0
  return 0;
1000
0
}
1001
1002
0
unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
1003
0
  switch (VT.SimpleTy) {
1004
0
  case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1005
0
  case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0);
1006
0
  case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1007
0
  default: return 0;
1008
0
  }
1009
0
}
1010
1011
// FastEmit functions for ISD::ZERO_EXTEND.
1012
1013
0
unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
1014
0
  if (RetVT.SimpleTy != MVT::i64)
1015
0
    return 0;
1016
0
  return fastEmitInst_r(WebAssembly::I64_EXTEND_U_I32, &WebAssembly::I64RegClass, Op0);
1017
0
}
1018
1019
0
unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
1020
0
  switch (VT.SimpleTy) {
1021
0
  case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(RetVT, Op0);
1022
0
  default: return 0;
1023
0
  }
1024
0
}
1025
1026
// FastEmit functions for WebAssemblyISD::BR_TABLE.
1027
1028
0
unsigned fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(MVT RetVT, unsigned Op0) {
1029
0
  if (RetVT.SimpleTy != MVT::isVoid)
1030
0
    return 0;
1031
0
  return fastEmitInst_r(WebAssembly::BR_TABLE_I32, &WebAssembly::I32RegClass, Op0);
1032
0
}
1033
1034
0
unsigned fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(MVT RetVT, unsigned Op0) {
1035
0
  if (RetVT.SimpleTy != MVT::isVoid)
1036
0
    return 0;
1037
0
  return fastEmitInst_r(WebAssembly::BR_TABLE_I64, &WebAssembly::I64RegClass, Op0);
1038
0
}
1039
1040
0
unsigned fastEmit_WebAssemblyISD_BR_TABLE_r(MVT VT, MVT RetVT, unsigned Op0) {
1041
0
  switch (VT.SimpleTy) {
1042
0
  case MVT::i32: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(RetVT, Op0);
1043
0
  case MVT::i64: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(RetVT, Op0);
1044
0
  default: return 0;
1045
0
  }
1046
0
}
1047
1048
// FastEmit functions for WebAssemblyISD::CONVERT_LOW_S.
1049
1050
0
unsigned fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1051
0
  if (RetVT.SimpleTy != MVT::v2f64)
1052
0
    return 0;
1053
0
  if ((Subtarget->hasSIMD128())) {
1054
0
    return fastEmitInst_r(WebAssembly::convert_low_s_F64x2, &WebAssembly::V128RegClass, Op0);
1055
0
  }
1056
0
  return 0;
1057
0
}
1058
1059
0
unsigned fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(MVT VT, MVT RetVT, unsigned Op0) {
1060
0
  switch (VT.SimpleTy) {
1061
0
  case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(RetVT, Op0);
1062
0
  default: return 0;
1063
0
  }
1064
0
}
1065
1066
// FastEmit functions for WebAssemblyISD::CONVERT_LOW_U.
1067
1068
0
unsigned fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1069
0
  if (RetVT.SimpleTy != MVT::v2f64)
1070
0
    return 0;
1071
0
  if ((Subtarget->hasSIMD128())) {
1072
0
    return fastEmitInst_r(WebAssembly::convert_low_u_F64x2, &WebAssembly::V128RegClass, Op0);
1073
0
  }
1074
0
  return 0;
1075
0
}
1076
1077
0
unsigned fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(MVT VT, MVT RetVT, unsigned Op0) {
1078
0
  switch (VT.SimpleTy) {
1079
0
  case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(RetVT, Op0);
1080
0
  default: return 0;
1081
0
  }
1082
0
}
1083
1084
// FastEmit functions for WebAssemblyISD::DEMOTE_ZERO.
1085
1086
0
unsigned fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1087
0
  if (RetVT.SimpleTy != MVT::v4f32)
1088
0
    return 0;
1089
0
  if ((Subtarget->hasSIMD128())) {
1090
0
    return fastEmitInst_r(WebAssembly::demote_zero_F32x4, &WebAssembly::V128RegClass, Op0);
1091
0
  }
1092
0
  return 0;
1093
0
}
1094
1095
0
unsigned fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(MVT VT, MVT RetVT, unsigned Op0) {
1096
0
  switch (VT.SimpleTy) {
1097
0
  case MVT::v2f64: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(RetVT, Op0);
1098
0
  default: return 0;
1099
0
  }
1100
0
}
1101
1102
// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_S.
1103
1104
0
unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1105
0
  if (RetVT.SimpleTy != MVT::v8i16)
1106
0
    return 0;
1107
0
  if ((Subtarget->hasSIMD128())) {
1108
0
    return fastEmitInst_r(WebAssembly::extend_high_s_I16x8, &WebAssembly::V128RegClass, Op0);
1109
0
  }
1110
0
  return 0;
1111
0
}
1112
1113
0
unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1114
0
  if (RetVT.SimpleTy != MVT::v4i32)
1115
0
    return 0;
1116
0
  if ((Subtarget->hasSIMD128())) {
1117
0
    return fastEmitInst_r(WebAssembly::extend_high_s_I32x4, &WebAssembly::V128RegClass, Op0);
1118
0
  }
1119
0
  return 0;
1120
0
}
1121
1122
0
unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1123
0
  if (RetVT.SimpleTy != MVT::v2i64)
1124
0
    return 0;
1125
0
  if ((Subtarget->hasSIMD128())) {
1126
0
    return fastEmitInst_r(WebAssembly::extend_high_s_I64x2, &WebAssembly::V128RegClass, Op0);
1127
0
  }
1128
0
  return 0;
1129
0
}
1130
1131
0
unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(MVT VT, MVT RetVT, unsigned Op0) {
1132
0
  switch (VT.SimpleTy) {
1133
0
  case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(RetVT, Op0);
1134
0
  case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(RetVT, Op0);
1135
0
  case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(RetVT, Op0);
1136
0
  default: return 0;
1137
0
  }
1138
0
}
1139
1140
// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_U.
1141
1142
0
unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1143
0
  if (RetVT.SimpleTy != MVT::v8i16)
1144
0
    return 0;
1145
0
  if ((Subtarget->hasSIMD128())) {
1146
0
    return fastEmitInst_r(WebAssembly::extend_high_u_I16x8, &WebAssembly::V128RegClass, Op0);
1147
0
  }
1148
0
  return 0;
1149
0
}
1150
1151
0
unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1152
0
  if (RetVT.SimpleTy != MVT::v4i32)
1153
0
    return 0;
1154
0
  if ((Subtarget->hasSIMD128())) {
1155
0
    return fastEmitInst_r(WebAssembly::extend_high_u_I32x4, &WebAssembly::V128RegClass, Op0);
1156
0
  }
1157
0
  return 0;
1158
0
}
1159
1160
0
unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1161
0
  if (RetVT.SimpleTy != MVT::v2i64)
1162
0
    return 0;
1163
0
  if ((Subtarget->hasSIMD128())) {
1164
0
    return fastEmitInst_r(WebAssembly::extend_high_u_I64x2, &WebAssembly::V128RegClass, Op0);
1165
0
  }
1166
0
  return 0;
1167
0
}
1168
1169
0
unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(MVT VT, MVT RetVT, unsigned Op0) {
1170
0
  switch (VT.SimpleTy) {
1171
0
  case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(RetVT, Op0);
1172
0
  case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(RetVT, Op0);
1173
0
  case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(RetVT, Op0);
1174
0
  default: return 0;
1175
0
  }
1176
0
}
1177
1178
// FastEmit functions for WebAssemblyISD::EXTEND_LOW_S.
1179
1180
0
unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1181
0
  if (RetVT.SimpleTy != MVT::v8i16)
1182
0
    return 0;
1183
0
  if ((Subtarget->hasSIMD128())) {
1184
0
    return fastEmitInst_r(WebAssembly::extend_low_s_I16x8, &WebAssembly::V128RegClass, Op0);
1185
0
  }
1186
0
  return 0;
1187
0
}
1188
1189
0
unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1190
0
  if (RetVT.SimpleTy != MVT::v4i32)
1191
0
    return 0;
1192
0
  if ((Subtarget->hasSIMD128())) {
1193
0
    return fastEmitInst_r(WebAssembly::extend_low_s_I32x4, &WebAssembly::V128RegClass, Op0);
1194
0
  }
1195
0
  return 0;
1196
0
}
1197
1198
0
unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1199
0
  if (RetVT.SimpleTy != MVT::v2i64)
1200
0
    return 0;
1201
0
  if ((Subtarget->hasSIMD128())) {
1202
0
    return fastEmitInst_r(WebAssembly::extend_low_s_I64x2, &WebAssembly::V128RegClass, Op0);
1203
0
  }
1204
0
  return 0;
1205
0
}
1206
1207
0
unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(MVT VT, MVT RetVT, unsigned Op0) {
1208
0
  switch (VT.SimpleTy) {
1209
0
  case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(RetVT, Op0);
1210
0
  case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(RetVT, Op0);
1211
0
  case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(RetVT, Op0);
1212
0
  default: return 0;
1213
0
  }
1214
0
}
1215
1216
// FastEmit functions for WebAssemblyISD::EXTEND_LOW_U.
1217
1218
0
unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1219
0
  if (RetVT.SimpleTy != MVT::v8i16)
1220
0
    return 0;
1221
0
  if ((Subtarget->hasSIMD128())) {
1222
0
    return fastEmitInst_r(WebAssembly::extend_low_u_I16x8, &WebAssembly::V128RegClass, Op0);
1223
0
  }
1224
0
  return 0;
1225
0
}
1226
1227
0
unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1228
0
  if (RetVT.SimpleTy != MVT::v4i32)
1229
0
    return 0;
1230
0
  if ((Subtarget->hasSIMD128())) {
1231
0
    return fastEmitInst_r(WebAssembly::extend_low_u_I32x4, &WebAssembly::V128RegClass, Op0);
1232
0
  }
1233
0
  return 0;
1234
0
}
1235
1236
0
unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1237
0
  if (RetVT.SimpleTy != MVT::v2i64)
1238
0
    return 0;
1239
0
  if ((Subtarget->hasSIMD128())) {
1240
0
    return fastEmitInst_r(WebAssembly::extend_low_u_I64x2, &WebAssembly::V128RegClass, Op0);
1241
0
  }
1242
0
  return 0;
1243
0
}
1244
1245
0
unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(MVT VT, MVT RetVT, unsigned Op0) {
1246
0
  switch (VT.SimpleTy) {
1247
0
  case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(RetVT, Op0);
1248
0
  case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(RetVT, Op0);
1249
0
  case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(RetVT, Op0);
1250
0
  default: return 0;
1251
0
  }
1252
0
}
1253
1254
// FastEmit functions for WebAssemblyISD::PROMOTE_LOW.
1255
1256
0
unsigned fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1257
0
  if (RetVT.SimpleTy != MVT::v2f64)
1258
0
    return 0;
1259
0
  if ((Subtarget->hasSIMD128())) {
1260
0
    return fastEmitInst_r(WebAssembly::promote_low_F64x2, &WebAssembly::V128RegClass, Op0);
1261
0
  }
1262
0
  return 0;
1263
0
}
1264
1265
0
unsigned fastEmit_WebAssemblyISD_PROMOTE_LOW_r(MVT VT, MVT RetVT, unsigned Op0) {
1266
0
  switch (VT.SimpleTy) {
1267
0
  case MVT::v4f32: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(RetVT, Op0);
1268
0
  default: return 0;
1269
0
  }
1270
0
}
1271
1272
// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_S.
1273
1274
0
unsigned fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1275
0
  if (RetVT.SimpleTy != MVT::v4i32)
1276
0
    return 0;
1277
0
  if ((Subtarget->hasSIMD128())) {
1278
0
    return fastEmitInst_r(WebAssembly::trunc_sat_zero_s_I32x4, &WebAssembly::V128RegClass, Op0);
1279
0
  }
1280
0
  return 0;
1281
0
}
1282
1283
0
unsigned fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(MVT VT, MVT RetVT, unsigned Op0) {
1284
0
  switch (VT.SimpleTy) {
1285
0
  case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(RetVT, Op0);
1286
0
  default: return 0;
1287
0
  }
1288
0
}
1289
1290
// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_U.
1291
1292
0
unsigned fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1293
0
  if (RetVT.SimpleTy != MVT::v4i32)
1294
0
    return 0;
1295
0
  if ((Subtarget->hasSIMD128())) {
1296
0
    return fastEmitInst_r(WebAssembly::trunc_sat_zero_u_I32x4, &WebAssembly::V128RegClass, Op0);
1297
0
  }
1298
0
  return 0;
1299
0
}
1300
1301
0
unsigned fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(MVT VT, MVT RetVT, unsigned Op0) {
1302
0
  switch (VT.SimpleTy) {
1303
0
  case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(RetVT, Op0);
1304
0
  default: return 0;
1305
0
  }
1306
0
}
1307
1308
// Top-level FastEmit function.
1309
1310
0
unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override {
1311
0
  switch (Opcode) {
1312
0
  case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0);
1313
0
  case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
1314
0
  case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1315
0
  case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1316
0
  case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1317
0
  case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
1318
0
  case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1319
0
  case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
1320
0
  case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
1321
0
  case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
1322
0
  case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1323
0
  case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1324
0
  case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1325
0
  case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1326
0
  case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1327
0
  case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1328
0
  case ISD::FROUNDEVEN: return fastEmit_ISD_FROUNDEVEN_r(VT, RetVT, Op0);
1329
0
  case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1330
0
  case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
1331
0
  case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
1332
0
  case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1333
0
  case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1334
0
  case ISD::SPLAT_VECTOR: return fastEmit_ISD_SPLAT_VECTOR_r(VT, RetVT, Op0);
1335
0
  case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
1336
0
  case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1337
0
  case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
1338
0
  case WebAssemblyISD::BR_TABLE: return fastEmit_WebAssemblyISD_BR_TABLE_r(VT, RetVT, Op0);
1339
0
  case WebAssemblyISD::CONVERT_LOW_S: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(VT, RetVT, Op0);
1340
0
  case WebAssemblyISD::CONVERT_LOW_U: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(VT, RetVT, Op0);
1341
0
  case WebAssemblyISD::DEMOTE_ZERO: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(VT, RetVT, Op0);
1342
0
  case WebAssemblyISD::EXTEND_HIGH_S: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(VT, RetVT, Op0);
1343
0
  case WebAssemblyISD::EXTEND_HIGH_U: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(VT, RetVT, Op0);
1344
0
  case WebAssemblyISD::EXTEND_LOW_S: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(VT, RetVT, Op0);
1345
0
  case WebAssemblyISD::EXTEND_LOW_U: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(VT, RetVT, Op0);
1346
0
  case WebAssemblyISD::PROMOTE_LOW: return fastEmit_WebAssemblyISD_PROMOTE_LOW_r(VT, RetVT, Op0);
1347
0
  case WebAssemblyISD::TRUNC_SAT_ZERO_S: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(VT, RetVT, Op0);
1348
0
  case WebAssemblyISD::TRUNC_SAT_ZERO_U: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(VT, RetVT, Op0);
1349
0
  default: return 0;
1350
0
  }
1351
0
}
1352
1353
// FastEmit functions for ISD::ADD.
1354
1355
0
unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1356
0
  if (RetVT.SimpleTy != MVT::i32)
1357
0
    return 0;
1358
0
  return fastEmitInst_rr(WebAssembly::ADD_I32, &WebAssembly::I32RegClass, Op0, Op1);
1359
0
}
1360
1361
0
unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1362
0
  if (RetVT.SimpleTy != MVT::i64)
1363
0
    return 0;
1364
0
  return fastEmitInst_rr(WebAssembly::ADD_I64, &WebAssembly::I64RegClass, Op0, Op1);
1365
0
}
1366
1367
0
unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1368
0
  if (RetVT.SimpleTy != MVT::v16i8)
1369
0
    return 0;
1370
0
  if ((Subtarget->hasSIMD128())) {
1371
0
    return fastEmitInst_rr(WebAssembly::ADD_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
1372
0
  }
1373
0
  return 0;
1374
0
}
1375
1376
0
unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1377
0
  if (RetVT.SimpleTy != MVT::v8i16)
1378
0
    return 0;
1379
0
  if ((Subtarget->hasSIMD128())) {
1380
0
    return fastEmitInst_rr(WebAssembly::ADD_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
1381
0
  }
1382
0
  return 0;
1383
0
}
1384
1385
0
unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1386
0
  if (RetVT.SimpleTy != MVT::v4i32)
1387
0
    return 0;
1388
0
  if ((Subtarget->hasSIMD128())) {
1389
0
    return fastEmitInst_rr(WebAssembly::ADD_I32x4, &WebAssembly::V128RegClass, Op0, Op1);
1390
0
  }
1391
0
  return 0;
1392
0
}
1393
1394
0
unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1395
0
  if (RetVT.SimpleTy != MVT::v2i64)
1396
0
    return 0;
1397
0
  if ((Subtarget->hasSIMD128())) {
1398
0
    return fastEmitInst_rr(WebAssembly::ADD_I64x2, &WebAssembly::V128RegClass, Op0, Op1);
1399
0
  }
1400
0
  return 0;
1401
0
}
1402
1403
0
unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1404
0
  switch (VT.SimpleTy) {
1405
0
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1406
0
  case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1407
0
  case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1408
0
  case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1409
0
  case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1410
0
  case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1411
0
  default: return 0;
1412
0
  }
1413
0
}
1414
1415
// FastEmit functions for ISD::AND.
1416
1417
0
unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1418
0
  if (RetVT.SimpleTy != MVT::i32)
1419
0
    return 0;
1420
0
  return fastEmitInst_rr(WebAssembly::AND_I32, &WebAssembly::I32RegClass, Op0, Op1);
1421
0
}
1422
1423
0
unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1424
0
  if (RetVT.SimpleTy != MVT::i64)
1425
0
    return 0;
1426
0
  return fastEmitInst_rr(WebAssembly::AND_I64, &WebAssembly::I64RegClass, Op0, Op1);
1427
0
}
1428
1429
0
unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1430
0
  if (RetVT.SimpleTy != MVT::v16i8)
1431
0
    return 0;
1432
0
  return fastEmitInst_rr(WebAssembly::AND, &WebAssembly::V128RegClass, Op0, Op1);
1433
0
}
1434
1435
0
unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1436
0
  if (RetVT.SimpleTy != MVT::v8i16)
1437
0
    return 0;
1438
0
  return fastEmitInst_rr(WebAssembly::AND, &WebAssembly::V128RegClass, Op0, Op1);
1439
0
}
1440
1441
0
unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1442
0
  if (RetVT.SimpleTy != MVT::v4i32)
1443
0
    return 0;
1444
0
  return fastEmitInst_rr(WebAssembly::AND, &WebAssembly::V128RegClass, Op0, Op1);
1445
0
}
1446
1447
0
unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1448
0
  if (RetVT.SimpleTy != MVT::v2i64)
1449
0
    return 0;
1450
0
  return fastEmitInst_rr(WebAssembly::AND, &WebAssembly::V128RegClass, Op0, Op1);
1451
0
}
1452
1453
0
unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1454
0
  switch (VT.SimpleTy) {
1455
0
  case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1456
0
  case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1457
0
  case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1458
0
  case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1459
0
  case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1460
0
  case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1461
0
  default: return 0;
1462
0
  }
1463
0
}
1464
1465
// FastEmit functions for ISD::FADD.
1466
1467
0
unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1468
0
  if (RetVT.SimpleTy != MVT::f32)
1469
0
    return 0;
1470
0
  return fastEmitInst_rr(WebAssembly::ADD_F32, &WebAssembly::F32RegClass, Op0, Op1);
1471
0
}
1472
1473
0
unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1474
0
  if (RetVT.SimpleTy != MVT::f64)
1475
0
    return 0;
1476
0
  return fastEmitInst_rr(WebAssembly::ADD_F64, &WebAssembly::F64RegClass, Op0, Op1);
1477
0
}
1478
1479
0
unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1480
0
  if (RetVT.SimpleTy != MVT::v4f32)
1481
0
    return 0;
1482
0
  if ((Subtarget->hasSIMD128())) {
1483
0
    return fastEmitInst_rr(WebAssembly::ADD_F32x4, &WebAssembly::V128RegClass, Op0, Op1);
1484
0
  }
1485
0
  return 0;
1486
0
}
1487
1488
0
unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1489
0
  if (RetVT.SimpleTy != MVT::v2f64)
1490
0
    return 0;
1491
0
  if ((Subtarget->hasSIMD128())) {
1492
0
    return fastEmitInst_rr(WebAssembly::ADD_F64x2, &WebAssembly::V128RegClass, Op0, Op1);
1493
0
  }
1494
0
  return 0;
1495
0
}
1496
1497
0
unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1498
0
  switch (VT.SimpleTy) {
1499
0
  case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1500
0
  case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1501
0
  case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1502
0
  case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1503
0
  default: return 0;
1504
0
  }
1505
0
}
1506
1507
// FastEmit functions for ISD::FCOPYSIGN.
1508
1509
0
unsigned fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1510
0
  if (RetVT.SimpleTy != MVT::f32)
1511
0
    return 0;
1512
0
  return fastEmitInst_rr(WebAssembly::COPYSIGN_F32, &WebAssembly::F32RegClass, Op0, Op1);
1513
0
}
1514
1515
0
unsigned fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1516
0
  if (RetVT.SimpleTy != MVT::f64)
1517
0
    return 0;
1518
0
  return fastEmitInst_rr(WebAssembly::COPYSIGN_F64, &WebAssembly::F64RegClass, Op0, Op1);
1519
0
}
1520
1521
0
unsigned fastEmit_ISD_FCOPYSIGN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1522
0
  switch (VT.SimpleTy) {
1523
0
  case MVT::f32: return fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(RetVT, Op0, Op1);
1524
0
  case MVT::f64: return fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(RetVT, Op0, Op1);
1525
0
  default: return 0;
1526
0
  }
1527
0
}
1528
1529
// FastEmit functions for ISD::FDIV.
1530
1531
0
unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1532
0
  if (RetVT.SimpleTy != MVT::f32)
1533
0
    return 0;
1534
0
  return fastEmitInst_rr(WebAssembly::DIV_F32, &WebAssembly::F32RegClass, Op0, Op1);
1535
0
}
1536
1537
0
unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1538
0
  if (RetVT.SimpleTy != MVT::f64)
1539
0
    return 0;
1540
0
  return fastEmitInst_rr(WebAssembly::DIV_F64, &WebAssembly::F64RegClass, Op0, Op1);
1541
0
}
1542
1543
0
unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1544
0
  if (RetVT.SimpleTy != MVT::v4f32)
1545
0
    return 0;
1546
0
  if ((Subtarget->hasSIMD128())) {
1547
0
    return fastEmitInst_rr(WebAssembly::DIV_F32x4, &WebAssembly::V128RegClass, Op0, Op1);
1548
0
  }
1549
0
  return 0;
1550
0
}
1551
1552
0
unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1553
0
  if (RetVT.SimpleTy != MVT::v2f64)
1554
0
    return 0;
1555
0
  if ((Subtarget->hasSIMD128())) {
1556
0
    return fastEmitInst_rr(WebAssembly::DIV_F64x2, &WebAssembly::V128RegClass, Op0, Op1);
1557
0
  }
1558
0
  return 0;
1559
0
}
1560
1561
0
unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1562
0
  switch (VT.SimpleTy) {
1563
0
  case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1564
0
  case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1565
0
  case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1566
0
  case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1567
0
  default: return 0;
1568
0
  }
1569
0
}
1570
1571
// FastEmit functions for ISD::FMAXIMUM.
1572
1573
0
unsigned fastEmit_ISD_FMAXIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1574
0
  if (RetVT.SimpleTy != MVT::f32)
1575
0
    return 0;
1576
0
  return fastEmitInst_rr(WebAssembly::MAX_F32, &WebAssembly::F32RegClass, Op0, Op1);
1577
0
}
1578
1579
0
unsigned fastEmit_ISD_FMAXIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1580
0
  if (RetVT.SimpleTy != MVT::f64)
1581
0
    return 0;
1582
0
  return fastEmitInst_rr(WebAssembly::MAX_F64, &WebAssembly::F64RegClass, Op0, Op1);
1583
0
}
1584
1585
0
unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1586
0
  if (RetVT.SimpleTy != MVT::v4f32)
1587
0
    return 0;
1588
0
  if ((Subtarget->hasSIMD128())) {
1589
0
    return fastEmitInst_rr(WebAssembly::MAX_F32x4, &WebAssembly::V128RegClass, Op0, Op1);
1590
0
  }
1591
0
  return 0;
1592
0
}
1593
1594
0
unsigned fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1595
0
  if (RetVT.SimpleTy != MVT::v2f64)
1596
0
    return 0;
1597
0
  if ((Subtarget->hasSIMD128())) {
1598
0
    return fastEmitInst_rr(WebAssembly::MAX_F64x2, &WebAssembly::V128RegClass, Op0, Op1);
1599
0
  }
1600
0
  return 0;
1601
0
}
1602
1603
0
unsigned fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1604
0
  switch (VT.SimpleTy) {
1605
0
  case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1606
0
  case MVT::f64: return fastEmit_ISD_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1607
0
  case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1608
0
  case MVT::v2f64: return fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1609
0
  default: return 0;
1610
0
  }
1611
0
}
1612
1613
// FastEmit functions for ISD::FMINIMUM.
1614
1615
0
unsigned fastEmit_ISD_FMINIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1616
0
  if (RetVT.SimpleTy != MVT::f32)
1617
0
    return 0;
1618
0
  return fastEmitInst_rr(WebAssembly::MIN_F32, &WebAssembly::F32RegClass, Op0, Op1);
1619
0
}
1620
1621
0
unsigned fastEmit_ISD_FMINIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1622
0
  if (RetVT.SimpleTy != MVT::f64)
1623
0
    return 0;
1624
0
  return fastEmitInst_rr(WebAssembly::MIN_F64, &WebAssembly::F64RegClass, Op0, Op1);
1625
0
}
1626
1627
0
unsigned fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1628
0
  if (RetVT.SimpleTy != MVT::v4f32)
1629
0
    return 0;
1630
0
  if ((Subtarget->hasSIMD128())) {
1631
0
    return fastEmitInst_rr(WebAssembly::MIN_F32x4, &WebAssembly::V128RegClass, Op0, Op1);
1632
0
  }
1633
0
  return 0;
1634
0
}
1635
1636
0
unsigned fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1637
0
  if (RetVT.SimpleTy != MVT::v2f64)
1638
0
    return 0;
1639
0
  if ((Subtarget->hasSIMD128())) {
1640
0
    return fastEmitInst_rr(WebAssembly::MIN_F64x2, &WebAssembly::V128RegClass, Op0, Op1);
1641
0
  }
1642
0
  return 0;
1643
0
}
1644
1645
0
unsigned fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1646
0
  switch (VT.SimpleTy) {
1647
0
  case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1648
0
  case MVT::f64: return fastEmit_ISD_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1649
0
  case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1650
0
  case MVT::v2f64: return fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1651
0
  default: return 0;
1652
0
  }
1653
0
}
1654
1655
// FastEmit functions for ISD::FMUL.
1656
1657
0
unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1658
0
  if (RetVT.SimpleTy != MVT::f32)
1659
0
    return 0;
1660
0
  return fastEmitInst_rr(WebAssembly::MUL_F32, &WebAssembly::F32RegClass, Op0, Op1);
1661
0
}
1662
1663
0
unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1664
0
  if (RetVT.SimpleTy != MVT::f64)
1665
0
    return 0;
1666
0
  return fastEmitInst_rr(WebAssembly::MUL_F64, &WebAssembly::F64RegClass, Op0, Op1);
1667
0
}
1668
1669
0
unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1670
0
  if (RetVT.SimpleTy != MVT::v4f32)
1671
0
    return 0;
1672
0
  if ((Subtarget->hasSIMD128())) {
1673
0
    return fastEmitInst_rr(WebAssembly::MUL_F32x4, &WebAssembly::V128RegClass, Op0, Op1);
1674
0
  }
1675
0
  return 0;
1676
0
}
1677
1678
0
unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1679
0
  if (RetVT.SimpleTy != MVT::v2f64)
1680
0
    return 0;
1681
0
  if ((Subtarget->hasSIMD128())) {
1682
0
    return fastEmitInst_rr(WebAssembly::MUL_F64x2, &WebAssembly::V128RegClass, Op0, Op1);
1683
0
  }
1684
0
  return 0;
1685
0
}
1686
1687
0
unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1688
0
  switch (VT.SimpleTy) {
1689
0
  case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1690
0
  case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1691
0
  case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1692
0
  case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1693
0
  default: return 0;
1694
0
  }
1695
0
}
1696
1697
// FastEmit functions for ISD::FSUB.
1698
1699
0
unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1700
0
  if (RetVT.SimpleTy != MVT::f32)
1701
0
    return 0;
1702
0
  return fastEmitInst_rr(WebAssembly::SUB_F32, &WebAssembly::F32RegClass, Op0, Op1);
1703
0
}
1704
1705
0
unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1706
0
  if (RetVT.SimpleTy != MVT::f64)
1707
0
    return 0;
1708
0
  return fastEmitInst_rr(WebAssembly::SUB_F64, &WebAssembly::F64RegClass, Op0, Op1);
1709
0
}
1710
1711
0
unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1712
0
  if (RetVT.SimpleTy != MVT::v4f32)
1713
0
    return 0;
1714
0
  if ((Subtarget->hasSIMD128())) {
1715
0
    return fastEmitInst_rr(WebAssembly::SUB_F32x4, &WebAssembly::V128RegClass, Op0, Op1);
1716
0
  }
1717
0
  return 0;
1718
0
}
1719
1720
0
unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1721
0
  if (RetVT.SimpleTy != MVT::v2f64)
1722
0
    return 0;
1723
0
  if ((Subtarget->hasSIMD128())) {
1724
0
    return fastEmitInst_rr(WebAssembly::SUB_F64x2, &WebAssembly::V128RegClass, Op0, Op1);
1725
0
  }
1726
0
  return 0;
1727
0
}
1728
1729
0
unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1730
0
  switch (VT.SimpleTy) {
1731
0
  case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1732
0
  case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1733
0
  case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1734
0
  case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1735
0
  default: return 0;
1736
0
  }
1737
0
}
1738
1739
// FastEmit functions for ISD::MUL.
1740
1741
0
unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1742
0
  if (RetVT.SimpleTy != MVT::i32)
1743
0
    return 0;
1744
0
  return fastEmitInst_rr(WebAssembly::MUL_I32, &WebAssembly::I32RegClass, Op0, Op1);
1745
0
}
1746
1747
0
unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1748
0
  if (RetVT.SimpleTy != MVT::i64)
1749
0
    return 0;
1750
0
  return fastEmitInst_rr(WebAssembly::MUL_I64, &WebAssembly::I64RegClass, Op0, Op1);
1751
0
}
1752
1753
0
unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1754
0
  if (RetVT.SimpleTy != MVT::v8i16)
1755
0
    return 0;
1756
0
  if ((Subtarget->hasSIMD128())) {
1757
0
    return fastEmitInst_rr(WebAssembly::MUL_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
1758
0
  }
1759
0
  return 0;
1760
0
}
1761
1762
0
unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1763
0
  if (RetVT.SimpleTy != MVT::v4i32)
1764
0
    return 0;
1765
0
  if ((Subtarget->hasSIMD128())) {
1766
0
    return fastEmitInst_rr(WebAssembly::MUL_I32x4, &WebAssembly::V128RegClass, Op0, Op1);
1767
0
  }
1768
0
  return 0;
1769
0
}
1770
1771
0
unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1772
0
  if (RetVT.SimpleTy != MVT::v2i64)
1773
0
    return 0;
1774
0
  if ((Subtarget->hasSIMD128())) {
1775
0
    return fastEmitInst_rr(WebAssembly::MUL_I64x2, &WebAssembly::V128RegClass, Op0, Op1);
1776
0
  }
1777
0
  return 0;
1778
0
}
1779
1780
0
unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1781
0
  switch (VT.SimpleTy) {
1782
0
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1783
0
  case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1784
0
  case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1785
0
  case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1786
0
  case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1787
0
  default: return 0;
1788
0
  }
1789
0
}
1790
1791
// FastEmit functions for ISD::OR.
1792
1793
0
unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1794
0
  if (RetVT.SimpleTy != MVT::i32)
1795
0
    return 0;
1796
0
  return fastEmitInst_rr(WebAssembly::OR_I32, &WebAssembly::I32RegClass, Op0, Op1);
1797
0
}
1798
1799
0
unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1800
0
  if (RetVT.SimpleTy != MVT::i64)
1801
0
    return 0;
1802
0
  return fastEmitInst_rr(WebAssembly::OR_I64, &WebAssembly::I64RegClass, Op0, Op1);
1803
0
}
1804
1805
0
unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1806
0
  if (RetVT.SimpleTy != MVT::v16i8)
1807
0
    return 0;
1808
0
  return fastEmitInst_rr(WebAssembly::OR, &WebAssembly::V128RegClass, Op0, Op1);
1809
0
}
1810
1811
0
unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1812
0
  if (RetVT.SimpleTy != MVT::v8i16)
1813
0
    return 0;
1814
0
  return fastEmitInst_rr(WebAssembly::OR, &WebAssembly::V128RegClass, Op0, Op1);
1815
0
}
1816
1817
0
unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1818
0
  if (RetVT.SimpleTy != MVT::v4i32)
1819
0
    return 0;
1820
0
  return fastEmitInst_rr(WebAssembly::OR, &WebAssembly::V128RegClass, Op0, Op1);
1821
0
}
1822
1823
0
unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1824
0
  if (RetVT.SimpleTy != MVT::v2i64)
1825
0
    return 0;
1826
0
  return fastEmitInst_rr(WebAssembly::OR, &WebAssembly::V128RegClass, Op0, Op1);
1827
0
}
1828
1829
0
unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1830
0
  switch (VT.SimpleTy) {
1831
0
  case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
1832
0
  case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
1833
0
  case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
1834
0
  case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
1835
0
  case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
1836
0
  case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
1837
0
  default: return 0;
1838
0
  }
1839
0
}
1840
1841
// FastEmit functions for ISD::ROTL.
1842
1843
0
unsigned fastEmit_ISD_ROTL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1844
0
  if (RetVT.SimpleTy != MVT::i32)
1845
0
    return 0;
1846
0
  return fastEmitInst_rr(WebAssembly::ROTL_I32, &WebAssembly::I32RegClass, Op0, Op1);
1847
0
}
1848
1849
0
unsigned fastEmit_ISD_ROTL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1850
0
  if (RetVT.SimpleTy != MVT::i64)
1851
0
    return 0;
1852
0
  return fastEmitInst_rr(WebAssembly::ROTL_I64, &WebAssembly::I64RegClass, Op0, Op1);
1853
0
}
1854
1855
0
unsigned fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1856
0
  switch (VT.SimpleTy) {
1857
0
  case MVT::i32: return fastEmit_ISD_ROTL_MVT_i32_rr(RetVT, Op0, Op1);
1858
0
  case MVT::i64: return fastEmit_ISD_ROTL_MVT_i64_rr(RetVT, Op0, Op1);
1859
0
  default: return 0;
1860
0
  }
1861
0
}
1862
1863
// FastEmit functions for ISD::ROTR.
1864
1865
0
unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1866
0
  if (RetVT.SimpleTy != MVT::i32)
1867
0
    return 0;
1868
0
  return fastEmitInst_rr(WebAssembly::ROTR_I32, &WebAssembly::I32RegClass, Op0, Op1);
1869
0
}
1870
1871
0
unsigned fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1872
0
  if (RetVT.SimpleTy != MVT::i64)
1873
0
    return 0;
1874
0
  return fastEmitInst_rr(WebAssembly::ROTR_I64, &WebAssembly::I64RegClass, Op0, Op1);
1875
0
}
1876
1877
0
unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1878
0
  switch (VT.SimpleTy) {
1879
0
  case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
1880
0
  case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op1);
1881
0
  default: return 0;
1882
0
  }
1883
0
}
1884
1885
// FastEmit functions for ISD::SADDSAT.
1886
1887
0
unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1888
0
  if (RetVT.SimpleTy != MVT::v16i8)
1889
0
    return 0;
1890
0
  if ((Subtarget->hasSIMD128())) {
1891
0
    return fastEmitInst_rr(WebAssembly::ADD_SAT_S_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
1892
0
  }
1893
0
  return 0;
1894
0
}
1895
1896
0
unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1897
0
  if (RetVT.SimpleTy != MVT::v8i16)
1898
0
    return 0;
1899
0
  if ((Subtarget->hasSIMD128())) {
1900
0
    return fastEmitInst_rr(WebAssembly::ADD_SAT_S_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
1901
0
  }
1902
0
  return 0;
1903
0
}
1904
1905
0
unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1906
0
  switch (VT.SimpleTy) {
1907
0
  case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
1908
0
  case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
1909
0
  default: return 0;
1910
0
  }
1911
0
}
1912
1913
// FastEmit functions for ISD::SDIV.
1914
1915
0
unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1916
0
  if (RetVT.SimpleTy != MVT::i32)
1917
0
    return 0;
1918
0
  return fastEmitInst_rr(WebAssembly::DIV_S_I32, &WebAssembly::I32RegClass, Op0, Op1);
1919
0
}
1920
1921
0
unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1922
0
  if (RetVT.SimpleTy != MVT::i64)
1923
0
    return 0;
1924
0
  return fastEmitInst_rr(WebAssembly::DIV_S_I64, &WebAssembly::I64RegClass, Op0, Op1);
1925
0
}
1926
1927
0
unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1928
0
  switch (VT.SimpleTy) {
1929
0
  case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
1930
0
  case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
1931
0
  default: return 0;
1932
0
  }
1933
0
}
1934
1935
// FastEmit functions for ISD::SHL.
1936
1937
0
unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1938
0
  if (RetVT.SimpleTy != MVT::i32)
1939
0
    return 0;
1940
0
  return fastEmitInst_rr(WebAssembly::SHL_I32, &WebAssembly::I32RegClass, Op0, Op1);
1941
0
}
1942
1943
0
unsigned fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1944
0
  if (RetVT.SimpleTy != MVT::i64)
1945
0
    return 0;
1946
0
  return fastEmitInst_rr(WebAssembly::SHL_I64, &WebAssembly::I64RegClass, Op0, Op1);
1947
0
}
1948
1949
0
unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1950
0
  switch (VT.SimpleTy) {
1951
0
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
1952
0
  case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op1);
1953
0
  default: return 0;
1954
0
  }
1955
0
}
1956
1957
// FastEmit functions for ISD::SMAX.
1958
1959
0
unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1960
0
  if (RetVT.SimpleTy != MVT::v16i8)
1961
0
    return 0;
1962
0
  if ((Subtarget->hasSIMD128())) {
1963
0
    return fastEmitInst_rr(WebAssembly::MAX_S_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
1964
0
  }
1965
0
  return 0;
1966
0
}
1967
1968
0
unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1969
0
  if (RetVT.SimpleTy != MVT::v8i16)
1970
0
    return 0;
1971
0
  if ((Subtarget->hasSIMD128())) {
1972
0
    return fastEmitInst_rr(WebAssembly::MAX_S_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
1973
0
  }
1974
0
  return 0;
1975
0
}
1976
1977
0
unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1978
0
  if (RetVT.SimpleTy != MVT::v4i32)
1979
0
    return 0;
1980
0
  if ((Subtarget->hasSIMD128())) {
1981
0
    return fastEmitInst_rr(WebAssembly::MAX_S_I32x4, &WebAssembly::V128RegClass, Op0, Op1);
1982
0
  }
1983
0
  return 0;
1984
0
}
1985
1986
0
unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1987
0
  switch (VT.SimpleTy) {
1988
0
  case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
1989
0
  case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
1990
0
  case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
1991
0
  default: return 0;
1992
0
  }
1993
0
}
1994
1995
// FastEmit functions for ISD::SMIN.
1996
1997
0
unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1998
0
  if (RetVT.SimpleTy != MVT::v16i8)
1999
0
    return 0;
2000
0
  if ((Subtarget->hasSIMD128())) {
2001
0
    return fastEmitInst_rr(WebAssembly::MIN_S_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
2002
0
  }
2003
0
  return 0;
2004
0
}
2005
2006
0
unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2007
0
  if (RetVT.SimpleTy != MVT::v8i16)
2008
0
    return 0;
2009
0
  if ((Subtarget->hasSIMD128())) {
2010
0
    return fastEmitInst_rr(WebAssembly::MIN_S_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
2011
0
  }
2012
0
  return 0;
2013
0
}
2014
2015
0
unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2016
0
  if (RetVT.SimpleTy != MVT::v4i32)
2017
0
    return 0;
2018
0
  if ((Subtarget->hasSIMD128())) {
2019
0
    return fastEmitInst_rr(WebAssembly::MIN_S_I32x4, &WebAssembly::V128RegClass, Op0, Op1);
2020
0
  }
2021
0
  return 0;
2022
0
}
2023
2024
0
unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2025
0
  switch (VT.SimpleTy) {
2026
0
  case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2027
0
  case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2028
0
  case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2029
0
  default: return 0;
2030
0
  }
2031
0
}
2032
2033
// FastEmit functions for ISD::SRA.
2034
2035
0
unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2036
0
  if (RetVT.SimpleTy != MVT::i32)
2037
0
    return 0;
2038
0
  return fastEmitInst_rr(WebAssembly::SHR_S_I32, &WebAssembly::I32RegClass, Op0, Op1);
2039
0
}
2040
2041
0
unsigned fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2042
0
  if (RetVT.SimpleTy != MVT::i64)
2043
0
    return 0;
2044
0
  return fastEmitInst_rr(WebAssembly::SHR_S_I64, &WebAssembly::I64RegClass, Op0, Op1);
2045
0
}
2046
2047
0
unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2048
0
  switch (VT.SimpleTy) {
2049
0
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2050
0
  case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op1);
2051
0
  default: return 0;
2052
0
  }
2053
0
}
2054
2055
// FastEmit functions for ISD::SREM.
2056
2057
0
unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2058
0
  if (RetVT.SimpleTy != MVT::i32)
2059
0
    return 0;
2060
0
  return fastEmitInst_rr(WebAssembly::REM_S_I32, &WebAssembly::I32RegClass, Op0, Op1);
2061
0
}
2062
2063
0
unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2064
0
  if (RetVT.SimpleTy != MVT::i64)
2065
0
    return 0;
2066
0
  return fastEmitInst_rr(WebAssembly::REM_S_I64, &WebAssembly::I64RegClass, Op0, Op1);
2067
0
}
2068
2069
0
unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2070
0
  switch (VT.SimpleTy) {
2071
0
  case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2072
0
  case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2073
0
  default: return 0;
2074
0
  }
2075
0
}
2076
2077
// FastEmit functions for ISD::SRL.
2078
2079
0
unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2080
0
  if (RetVT.SimpleTy != MVT::i32)
2081
0
    return 0;
2082
0
  return fastEmitInst_rr(WebAssembly::SHR_U_I32, &WebAssembly::I32RegClass, Op0, Op1);
2083
0
}
2084
2085
0
unsigned fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2086
0
  if (RetVT.SimpleTy != MVT::i64)
2087
0
    return 0;
2088
0
  return fastEmitInst_rr(WebAssembly::SHR_U_I64, &WebAssembly::I64RegClass, Op0, Op1);
2089
0
}
2090
2091
0
unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2092
0
  switch (VT.SimpleTy) {
2093
0
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2094
0
  case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op1);
2095
0
  default: return 0;
2096
0
  }
2097
0
}
2098
2099
// FastEmit functions for ISD::SUB.
2100
2101
0
unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2102
0
  if (RetVT.SimpleTy != MVT::i32)
2103
0
    return 0;
2104
0
  return fastEmitInst_rr(WebAssembly::SUB_I32, &WebAssembly::I32RegClass, Op0, Op1);
2105
0
}
2106
2107
0
unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2108
0
  if (RetVT.SimpleTy != MVT::i64)
2109
0
    return 0;
2110
0
  return fastEmitInst_rr(WebAssembly::SUB_I64, &WebAssembly::I64RegClass, Op0, Op1);
2111
0
}
2112
2113
0
unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2114
0
  if (RetVT.SimpleTy != MVT::v16i8)
2115
0
    return 0;
2116
0
  if ((Subtarget->hasSIMD128())) {
2117
0
    return fastEmitInst_rr(WebAssembly::SUB_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
2118
0
  }
2119
0
  return 0;
2120
0
}
2121
2122
0
unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2123
0
  if (RetVT.SimpleTy != MVT::v8i16)
2124
0
    return 0;
2125
0
  if ((Subtarget->hasSIMD128())) {
2126
0
    return fastEmitInst_rr(WebAssembly::SUB_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
2127
0
  }
2128
0
  return 0;
2129
0
}
2130
2131
0
unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2132
0
  if (RetVT.SimpleTy != MVT::v4i32)
2133
0
    return 0;
2134
0
  if ((Subtarget->hasSIMD128())) {
2135
0
    return fastEmitInst_rr(WebAssembly::SUB_I32x4, &WebAssembly::V128RegClass, Op0, Op1);
2136
0
  }
2137
0
  return 0;
2138
0
}
2139
2140
0
unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2141
0
  if (RetVT.SimpleTy != MVT::v2i64)
2142
0
    return 0;
2143
0
  if ((Subtarget->hasSIMD128())) {
2144
0
    return fastEmitInst_rr(WebAssembly::SUB_I64x2, &WebAssembly::V128RegClass, Op0, Op1);
2145
0
  }
2146
0
  return 0;
2147
0
}
2148
2149
0
unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2150
0
  switch (VT.SimpleTy) {
2151
0
  case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2152
0
  case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2153
0
  case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2154
0
  case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2155
0
  case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2156
0
  case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2157
0
  default: return 0;
2158
0
  }
2159
0
}
2160
2161
// FastEmit functions for ISD::UADDSAT.
2162
2163
0
unsigned fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2164
0
  if (RetVT.SimpleTy != MVT::v16i8)
2165
0
    return 0;
2166
0
  if ((Subtarget->hasSIMD128())) {
2167
0
    return fastEmitInst_rr(WebAssembly::ADD_SAT_U_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
2168
0
  }
2169
0
  return 0;
2170
0
}
2171
2172
0
unsigned fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2173
0
  if (RetVT.SimpleTy != MVT::v8i16)
2174
0
    return 0;
2175
0
  if ((Subtarget->hasSIMD128())) {
2176
0
    return fastEmitInst_rr(WebAssembly::ADD_SAT_U_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
2177
0
  }
2178
0
  return 0;
2179
0
}
2180
2181
0
unsigned fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2182
0
  switch (VT.SimpleTy) {
2183
0
  case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2184
0
  case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2185
0
  default: return 0;
2186
0
  }
2187
0
}
2188
2189
// FastEmit functions for ISD::UDIV.
2190
2191
0
unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2192
0
  if (RetVT.SimpleTy != MVT::i32)
2193
0
    return 0;
2194
0
  return fastEmitInst_rr(WebAssembly::DIV_U_I32, &WebAssembly::I32RegClass, Op0, Op1);
2195
0
}
2196
2197
0
unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2198
0
  if (RetVT.SimpleTy != MVT::i64)
2199
0
    return 0;
2200
0
  return fastEmitInst_rr(WebAssembly::DIV_U_I64, &WebAssembly::I64RegClass, Op0, Op1);
2201
0
}
2202
2203
0
unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2204
0
  switch (VT.SimpleTy) {
2205
0
  case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2206
0
  case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2207
0
  default: return 0;
2208
0
  }
2209
0
}
2210
2211
// FastEmit functions for ISD::UMAX.
2212
2213
0
unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2214
0
  if (RetVT.SimpleTy != MVT::v16i8)
2215
0
    return 0;
2216
0
  if ((Subtarget->hasSIMD128())) {
2217
0
    return fastEmitInst_rr(WebAssembly::MAX_U_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
2218
0
  }
2219
0
  return 0;
2220
0
}
2221
2222
0
unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2223
0
  if (RetVT.SimpleTy != MVT::v8i16)
2224
0
    return 0;
2225
0
  if ((Subtarget->hasSIMD128())) {
2226
0
    return fastEmitInst_rr(WebAssembly::MAX_U_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
2227
0
  }
2228
0
  return 0;
2229
0
}
2230
2231
0
unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2232
0
  if (RetVT.SimpleTy != MVT::v4i32)
2233
0
    return 0;
2234
0
  if ((Subtarget->hasSIMD128())) {
2235
0
    return fastEmitInst_rr(WebAssembly::MAX_U_I32x4, &WebAssembly::V128RegClass, Op0, Op1);
2236
0
  }
2237
0
  return 0;
2238
0
}
2239
2240
0
unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2241
0
  switch (VT.SimpleTy) {
2242
0
  case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2243
0
  case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2244
0
  case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2245
0
  default: return 0;
2246
0
  }
2247
0
}
2248
2249
// FastEmit functions for ISD::UMIN.
2250
2251
0
unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2252
0
  if (RetVT.SimpleTy != MVT::v16i8)
2253
0
    return 0;
2254
0
  if ((Subtarget->hasSIMD128())) {
2255
0
    return fastEmitInst_rr(WebAssembly::MIN_U_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
2256
0
  }
2257
0
  return 0;
2258
0
}
2259
2260
0
unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2261
0
  if (RetVT.SimpleTy != MVT::v8i16)
2262
0
    return 0;
2263
0
  if ((Subtarget->hasSIMD128())) {
2264
0
    return fastEmitInst_rr(WebAssembly::MIN_U_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
2265
0
  }
2266
0
  return 0;
2267
0
}
2268
2269
0
unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2270
0
  if (RetVT.SimpleTy != MVT::v4i32)
2271
0
    return 0;
2272
0
  if ((Subtarget->hasSIMD128())) {
2273
0
    return fastEmitInst_rr(WebAssembly::MIN_U_I32x4, &WebAssembly::V128RegClass, Op0, Op1);
2274
0
  }
2275
0
  return 0;
2276
0
}
2277
2278
0
unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2279
0
  switch (VT.SimpleTy) {
2280
0
  case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2281
0
  case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2282
0
  case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2283
0
  default: return 0;
2284
0
  }
2285
0
}
2286
2287
// FastEmit functions for ISD::UREM.
2288
2289
0
unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2290
0
  if (RetVT.SimpleTy != MVT::i32)
2291
0
    return 0;
2292
0
  return fastEmitInst_rr(WebAssembly::REM_U_I32, &WebAssembly::I32RegClass, Op0, Op1);
2293
0
}
2294
2295
0
unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2296
0
  if (RetVT.SimpleTy != MVT::i64)
2297
0
    return 0;
2298
0
  return fastEmitInst_rr(WebAssembly::REM_U_I64, &WebAssembly::I64RegClass, Op0, Op1);
2299
0
}
2300
2301
0
unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2302
0
  switch (VT.SimpleTy) {
2303
0
  case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2304
0
  case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2305
0
  default: return 0;
2306
0
  }
2307
0
}
2308
2309
// FastEmit functions for ISD::XOR.
2310
2311
0
unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2312
0
  if (RetVT.SimpleTy != MVT::i32)
2313
0
    return 0;
2314
0
  return fastEmitInst_rr(WebAssembly::XOR_I32, &WebAssembly::I32RegClass, Op0, Op1);
2315
0
}
2316
2317
0
unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2318
0
  if (RetVT.SimpleTy != MVT::i64)
2319
0
    return 0;
2320
0
  return fastEmitInst_rr(WebAssembly::XOR_I64, &WebAssembly::I64RegClass, Op0, Op1);
2321
0
}
2322
2323
0
unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2324
0
  if (RetVT.SimpleTy != MVT::v16i8)
2325
0
    return 0;
2326
0
  return fastEmitInst_rr(WebAssembly::XOR, &WebAssembly::V128RegClass, Op0, Op1);
2327
0
}
2328
2329
0
unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2330
0
  if (RetVT.SimpleTy != MVT::v8i16)
2331
0
    return 0;
2332
0
  return fastEmitInst_rr(WebAssembly::XOR, &WebAssembly::V128RegClass, Op0, Op1);
2333
0
}
2334
2335
0
unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2336
0
  if (RetVT.SimpleTy != MVT::v4i32)
2337
0
    return 0;
2338
0
  return fastEmitInst_rr(WebAssembly::XOR, &WebAssembly::V128RegClass, Op0, Op1);
2339
0
}
2340
2341
0
unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2342
0
  if (RetVT.SimpleTy != MVT::v2i64)
2343
0
    return 0;
2344
0
  return fastEmitInst_rr(WebAssembly::XOR, &WebAssembly::V128RegClass, Op0, Op1);
2345
0
}
2346
2347
0
unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2348
0
  switch (VT.SimpleTy) {
2349
0
  case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2350
0
  case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2351
0
  case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2352
0
  case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2353
0
  case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2354
0
  case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2355
0
  default: return 0;
2356
0
  }
2357
0
}
2358
2359
// FastEmit functions for WebAssemblyISD::NARROW_U.
2360
2361
0
unsigned fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2362
0
  if (RetVT.SimpleTy != MVT::v16i8)
2363
0
    return 0;
2364
0
  return fastEmitInst_rr(WebAssembly::NARROW_U_I8x16, &WebAssembly::V128RegClass, Op0, Op1);
2365
0
}
2366
2367
0
unsigned fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2368
0
  if (RetVT.SimpleTy != MVT::v8i16)
2369
0
    return 0;
2370
0
  return fastEmitInst_rr(WebAssembly::NARROW_U_I16x8, &WebAssembly::V128RegClass, Op0, Op1);
2371
0
}
2372
2373
0
unsigned fastEmit_WebAssemblyISD_NARROW_U_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2374
0
  switch (VT.SimpleTy) {
2375
0
  case MVT::v8i16: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(RetVT, Op0, Op1);
2376
0
  case MVT::v4i32: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(RetVT, Op0, Op1);
2377
0
  default: return 0;
2378
0
  }
2379
0
}
2380
2381
// FastEmit functions for WebAssemblyISD::SWIZZLE.
2382
2383
0
unsigned fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2384
0
  if (RetVT.SimpleTy != MVT::v16i8)
2385
0
    return 0;
2386
0
  if ((Subtarget->hasSIMD128())) {
2387
0
    return fastEmitInst_rr(WebAssembly::SWIZZLE, &WebAssembly::V128RegClass, Op0, Op1);
2388
0
  }
2389
0
  return 0;
2390
0
}
2391
2392
0
unsigned fastEmit_WebAssemblyISD_SWIZZLE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2393
0
  switch (VT.SimpleTy) {
2394
0
  case MVT::v16i8: return fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(RetVT, Op0, Op1);
2395
0
  default: return 0;
2396
0
  }
2397
0
}
2398
2399
// Top-level FastEmit function.
2400
2401
0
unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1) override {
2402
0
  switch (Opcode) {
2403
0
  case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
2404
0
  case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
2405
0
  case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
2406
0
  case ISD::FCOPYSIGN: return fastEmit_ISD_FCOPYSIGN_rr(VT, RetVT, Op0, Op1);
2407
0
  case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
2408
0
  case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op1);
2409
0
  case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op1);
2410
0
  case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
2411
0
  case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
2412
0
  case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
2413
0
  case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
2414
0
  case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
2415
0
  case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
2416
0
  case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
2417
0
  case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
2418
0
  case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
2419
0
  case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
2420
0
  case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
2421
0
  case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
2422
0
  case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
2423
0
  case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
2424
0
  case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
2425
0
  case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
2426
0
  case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
2427
0
  case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
2428
0
  case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
2429
0
  case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
2430
0
  case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
2431
0
  case WebAssemblyISD::NARROW_U: return fastEmit_WebAssemblyISD_NARROW_U_rr(VT, RetVT, Op0, Op1);
2432
0
  case WebAssemblyISD::SWIZZLE: return fastEmit_WebAssemblyISD_SWIZZLE_rr(VT, RetVT, Op0, Op1);
2433
0
  default: return 0;
2434
0
  }
2435
0
}
2436
2437
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2438
2439
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(MVT RetVT, unsigned Op0, uint64_t imm1) {
2440
0
  if (RetVT.SimpleTy != MVT::i32)
2441
0
    return 0;
2442
0
  return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_I8x16_u, &WebAssembly::I32RegClass, Op0, imm1);
2443
0
}
2444
2445
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
2446
0
  switch (VT.SimpleTy) {
2447
0
  case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(RetVT, Op0, imm1);
2448
0
  default: return 0;
2449
0
  }
2450
0
}
2451
2452
// Top-level FastEmit function.
2453
2454
0
unsigned fastEmit_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
2455
0
  switch (Opcode) {
2456
0
  case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(VT, RetVT, Op0, imm1);
2457
0
  default: return 0;
2458
0
  }
2459
0
}
2460
2461
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2462
2463
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(MVT RetVT, unsigned Op0, uint64_t imm1) {
2464
0
  if (RetVT.SimpleTy != MVT::i32)
2465
0
    return 0;
2466
0
  return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_I16x8_u, &WebAssembly::I32RegClass, Op0, imm1);
2467
0
}
2468
2469
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
2470
0
  switch (VT.SimpleTy) {
2471
0
  case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(RetVT, Op0, imm1);
2472
0
  default: return 0;
2473
0
  }
2474
0
}
2475
2476
// Top-level FastEmit function.
2477
2478
0
unsigned fastEmit_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
2479
0
  switch (Opcode) {
2480
0
  case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(VT, RetVT, Op0, imm1);
2481
0
  default: return 0;
2482
0
  }
2483
0
}
2484
2485
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2486
2487
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(MVT RetVT, unsigned Op0, uint64_t imm1) {
2488
0
  if (RetVT.SimpleTy != MVT::i32)
2489
0
    return 0;
2490
0
  return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_I32x4, &WebAssembly::I32RegClass, Op0, imm1);
2491
0
}
2492
2493
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(MVT RetVT, unsigned Op0, uint64_t imm1) {
2494
0
  if (RetVT.SimpleTy != MVT::f32)
2495
0
    return 0;
2496
0
  return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_F32x4, &WebAssembly::F32RegClass, Op0, imm1);
2497
0
}
2498
2499
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
2500
0
  switch (VT.SimpleTy) {
2501
0
  case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2502
0
  case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2503
0
  default: return 0;
2504
0
  }
2505
0
}
2506
2507
// Top-level FastEmit function.
2508
2509
0
unsigned fastEmit_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
2510
0
  switch (Opcode) {
2511
0
  case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(VT, RetVT, Op0, imm1);
2512
0
  default: return 0;
2513
0
  }
2514
0
}
2515
2516
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2517
2518
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(MVT RetVT, unsigned Op0, uint64_t imm1) {
2519
0
  if (RetVT.SimpleTy != MVT::i64)
2520
0
    return 0;
2521
0
  return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_I64x2, &WebAssembly::I64RegClass, Op0, imm1);
2522
0
}
2523
2524
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(MVT RetVT, unsigned Op0, uint64_t imm1) {
2525
0
  if (RetVT.SimpleTy != MVT::f64)
2526
0
    return 0;
2527
0
  return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_F64x2, &WebAssembly::F64RegClass, Op0, imm1);
2528
0
}
2529
2530
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
2531
0
  switch (VT.SimpleTy) {
2532
0
  case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2533
0
  case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2534
0
  default: return 0;
2535
0
  }
2536
0
}
2537
2538
// Top-level FastEmit function.
2539
2540
0
unsigned fastEmit_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
2541
0
  switch (Opcode) {
2542
0
  case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(VT, RetVT, Op0, imm1);
2543
0
  default: return 0;
2544
0
  }
2545
0
}
2546
2547
// FastEmit functions for ISD::ConstantFP.
2548
2549
0
unsigned fastEmit_ISD_ConstantFP_MVT_f32_f(MVT RetVT, const ConstantFP *f0) {
2550
0
  if (RetVT.SimpleTy != MVT::f32)
2551
0
    return 0;
2552
0
  return fastEmitInst_f(WebAssembly::CONST_F32, &WebAssembly::F32RegClass, f0);
2553
0
}
2554
2555
0
unsigned fastEmit_ISD_ConstantFP_MVT_f64_f(MVT RetVT, const ConstantFP *f0) {
2556
0
  if (RetVT.SimpleTy != MVT::f64)
2557
0
    return 0;
2558
0
  return fastEmitInst_f(WebAssembly::CONST_F64, &WebAssembly::F64RegClass, f0);
2559
0
}
2560
2561
0
unsigned fastEmit_ISD_ConstantFP_f(MVT VT, MVT RetVT, const ConstantFP *f0) {
2562
0
  switch (VT.SimpleTy) {
2563
0
  case MVT::f32: return fastEmit_ISD_ConstantFP_MVT_f32_f(RetVT, f0);
2564
0
  case MVT::f64: return fastEmit_ISD_ConstantFP_MVT_f64_f(RetVT, f0);
2565
0
  default: return 0;
2566
0
  }
2567
0
}
2568
2569
// Top-level FastEmit function.
2570
2571
0
unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *f0) override {
2572
0
  switch (Opcode) {
2573
0
  case ISD::ConstantFP: return fastEmit_ISD_ConstantFP_f(VT, RetVT, f0);
2574
0
  default: return 0;
2575
0
  }
2576
0
}
2577
2578
// FastEmit functions for ISD::Constant.
2579
2580
0
unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
2581
0
  if (RetVT.SimpleTy != MVT::i32)
2582
0
    return 0;
2583
0
  return fastEmitInst_i(WebAssembly::CONST_I32, &WebAssembly::I32RegClass, imm0);
2584
0
}
2585
2586
0
unsigned fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) {
2587
0
  if (RetVT.SimpleTy != MVT::i64)
2588
0
    return 0;
2589
0
  return fastEmitInst_i(WebAssembly::CONST_I64, &WebAssembly::I64RegClass, imm0);
2590
0
}
2591
2592
0
unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
2593
0
  switch (VT.SimpleTy) {
2594
0
  case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
2595
0
  case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0);
2596
0
  default: return 0;
2597
0
  }
2598
0
}
2599
2600
// Top-level FastEmit function.
2601
2602
0
unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
2603
0
  switch (Opcode) {
2604
0
  case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
2605
0
  default: return 0;
2606
0
  }
2607
0
}
2608