Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace WebAssembly {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_VALUE_LIST  = 14,
30
    DBG_INSTR_REF = 15,
31
    DBG_PHI = 16,
32
    DBG_LABEL = 17,
33
    REG_SEQUENCE  = 18,
34
    COPY  = 19,
35
    BUNDLE  = 20,
36
    LIFETIME_START  = 21,
37
    LIFETIME_END  = 22,
38
    PSEUDO_PROBE  = 23,
39
    ARITH_FENCE = 24,
40
    STACKMAP  = 25,
41
    FENTRY_CALL = 26,
42
    PATCHPOINT  = 27,
43
    LOAD_STACK_GUARD  = 28,
44
    PREALLOCATED_SETUP  = 29,
45
    PREALLOCATED_ARG  = 30,
46
    STATEPOINT  = 31,
47
    LOCAL_ESCAPE  = 32,
48
    FAULTING_OP = 33,
49
    PATCHABLE_OP  = 34,
50
    PATCHABLE_FUNCTION_ENTER  = 35,
51
    PATCHABLE_RET = 36,
52
    PATCHABLE_FUNCTION_EXIT = 37,
53
    PATCHABLE_TAIL_CALL = 38,
54
    PATCHABLE_EVENT_CALL  = 39,
55
    PATCHABLE_TYPED_EVENT_CALL  = 40,
56
    ICALL_BRANCH_FUNNEL = 41,
57
    MEMBARRIER  = 42,
58
    JUMP_TABLE_DEBUG_INFO = 43,
59
    G_ASSERT_SEXT = 44,
60
    G_ASSERT_ZEXT = 45,
61
    G_ASSERT_ALIGN  = 46,
62
    G_ADD = 47,
63
    G_SUB = 48,
64
    G_MUL = 49,
65
    G_SDIV  = 50,
66
    G_UDIV  = 51,
67
    G_SREM  = 52,
68
    G_UREM  = 53,
69
    G_SDIVREM = 54,
70
    G_UDIVREM = 55,
71
    G_AND = 56,
72
    G_OR  = 57,
73
    G_XOR = 58,
74
    G_IMPLICIT_DEF  = 59,
75
    G_PHI = 60,
76
    G_FRAME_INDEX = 61,
77
    G_GLOBAL_VALUE  = 62,
78
    G_CONSTANT_POOL = 63,
79
    G_EXTRACT = 64,
80
    G_UNMERGE_VALUES  = 65,
81
    G_INSERT  = 66,
82
    G_MERGE_VALUES  = 67,
83
    G_BUILD_VECTOR  = 68,
84
    G_BUILD_VECTOR_TRUNC  = 69,
85
    G_CONCAT_VECTORS  = 70,
86
    G_PTRTOINT  = 71,
87
    G_INTTOPTR  = 72,
88
    G_BITCAST = 73,
89
    G_FREEZE  = 74,
90
    G_CONSTANT_FOLD_BARRIER = 75,
91
    G_INTRINSIC_FPTRUNC_ROUND = 76,
92
    G_INTRINSIC_TRUNC = 77,
93
    G_INTRINSIC_ROUND = 78,
94
    G_INTRINSIC_LRINT = 79,
95
    G_INTRINSIC_ROUNDEVEN = 80,
96
    G_READCYCLECOUNTER  = 81,
97
    G_LOAD  = 82,
98
    G_SEXTLOAD  = 83,
99
    G_ZEXTLOAD  = 84,
100
    G_INDEXED_LOAD  = 85,
101
    G_INDEXED_SEXTLOAD  = 86,
102
    G_INDEXED_ZEXTLOAD  = 87,
103
    G_STORE = 88,
104
    G_INDEXED_STORE = 89,
105
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90,
106
    G_ATOMIC_CMPXCHG  = 91,
107
    G_ATOMICRMW_XCHG  = 92,
108
    G_ATOMICRMW_ADD = 93,
109
    G_ATOMICRMW_SUB = 94,
110
    G_ATOMICRMW_AND = 95,
111
    G_ATOMICRMW_NAND  = 96,
112
    G_ATOMICRMW_OR  = 97,
113
    G_ATOMICRMW_XOR = 98,
114
    G_ATOMICRMW_MAX = 99,
115
    G_ATOMICRMW_MIN = 100,
116
    G_ATOMICRMW_UMAX  = 101,
117
    G_ATOMICRMW_UMIN  = 102,
118
    G_ATOMICRMW_FADD  = 103,
119
    G_ATOMICRMW_FSUB  = 104,
120
    G_ATOMICRMW_FMAX  = 105,
121
    G_ATOMICRMW_FMIN  = 106,
122
    G_ATOMICRMW_UINC_WRAP = 107,
123
    G_ATOMICRMW_UDEC_WRAP = 108,
124
    G_FENCE = 109,
125
    G_PREFETCH  = 110,
126
    G_BRCOND  = 111,
127
    G_BRINDIRECT  = 112,
128
    G_INVOKE_REGION_START = 113,
129
    G_INTRINSIC = 114,
130
    G_INTRINSIC_W_SIDE_EFFECTS  = 115,
131
    G_INTRINSIC_CONVERGENT  = 116,
132
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117,
133
    G_ANYEXT  = 118,
134
    G_TRUNC = 119,
135
    G_CONSTANT  = 120,
136
    G_FCONSTANT = 121,
137
    G_VASTART = 122,
138
    G_VAARG = 123,
139
    G_SEXT  = 124,
140
    G_SEXT_INREG  = 125,
141
    G_ZEXT  = 126,
142
    G_SHL = 127,
143
    G_LSHR  = 128,
144
    G_ASHR  = 129,
145
    G_FSHL  = 130,
146
    G_FSHR  = 131,
147
    G_ROTR  = 132,
148
    G_ROTL  = 133,
149
    G_ICMP  = 134,
150
    G_FCMP  = 135,
151
    G_SELECT  = 136,
152
    G_UADDO = 137,
153
    G_UADDE = 138,
154
    G_USUBO = 139,
155
    G_USUBE = 140,
156
    G_SADDO = 141,
157
    G_SADDE = 142,
158
    G_SSUBO = 143,
159
    G_SSUBE = 144,
160
    G_UMULO = 145,
161
    G_SMULO = 146,
162
    G_UMULH = 147,
163
    G_SMULH = 148,
164
    G_UADDSAT = 149,
165
    G_SADDSAT = 150,
166
    G_USUBSAT = 151,
167
    G_SSUBSAT = 152,
168
    G_USHLSAT = 153,
169
    G_SSHLSAT = 154,
170
    G_SMULFIX = 155,
171
    G_UMULFIX = 156,
172
    G_SMULFIXSAT  = 157,
173
    G_UMULFIXSAT  = 158,
174
    G_SDIVFIX = 159,
175
    G_UDIVFIX = 160,
176
    G_SDIVFIXSAT  = 161,
177
    G_UDIVFIXSAT  = 162,
178
    G_FADD  = 163,
179
    G_FSUB  = 164,
180
    G_FMUL  = 165,
181
    G_FMA = 166,
182
    G_FMAD  = 167,
183
    G_FDIV  = 168,
184
    G_FREM  = 169,
185
    G_FPOW  = 170,
186
    G_FPOWI = 171,
187
    G_FEXP  = 172,
188
    G_FEXP2 = 173,
189
    G_FEXP10  = 174,
190
    G_FLOG  = 175,
191
    G_FLOG2 = 176,
192
    G_FLOG10  = 177,
193
    G_FLDEXP  = 178,
194
    G_FFREXP  = 179,
195
    G_FNEG  = 180,
196
    G_FPEXT = 181,
197
    G_FPTRUNC = 182,
198
    G_FPTOSI  = 183,
199
    G_FPTOUI  = 184,
200
    G_SITOFP  = 185,
201
    G_UITOFP  = 186,
202
    G_FABS  = 187,
203
    G_FCOPYSIGN = 188,
204
    G_IS_FPCLASS  = 189,
205
    G_FCANONICALIZE = 190,
206
    G_FMINNUM = 191,
207
    G_FMAXNUM = 192,
208
    G_FMINNUM_IEEE  = 193,
209
    G_FMAXNUM_IEEE  = 194,
210
    G_FMINIMUM  = 195,
211
    G_FMAXIMUM  = 196,
212
    G_GET_FPENV = 197,
213
    G_SET_FPENV = 198,
214
    G_RESET_FPENV = 199,
215
    G_GET_FPMODE  = 200,
216
    G_SET_FPMODE  = 201,
217
    G_RESET_FPMODE  = 202,
218
    G_PTR_ADD = 203,
219
    G_PTRMASK = 204,
220
    G_SMIN  = 205,
221
    G_SMAX  = 206,
222
    G_UMIN  = 207,
223
    G_UMAX  = 208,
224
    G_ABS = 209,
225
    G_LROUND  = 210,
226
    G_LLROUND = 211,
227
    G_BR  = 212,
228
    G_BRJT  = 213,
229
    G_INSERT_VECTOR_ELT = 214,
230
    G_EXTRACT_VECTOR_ELT  = 215,
231
    G_SHUFFLE_VECTOR  = 216,
232
    G_CTTZ  = 217,
233
    G_CTTZ_ZERO_UNDEF = 218,
234
    G_CTLZ  = 219,
235
    G_CTLZ_ZERO_UNDEF = 220,
236
    G_CTPOP = 221,
237
    G_BSWAP = 222,
238
    G_BITREVERSE  = 223,
239
    G_FCEIL = 224,
240
    G_FCOS  = 225,
241
    G_FSIN  = 226,
242
    G_FSQRT = 227,
243
    G_FFLOOR  = 228,
244
    G_FRINT = 229,
245
    G_FNEARBYINT  = 230,
246
    G_ADDRSPACE_CAST  = 231,
247
    G_BLOCK_ADDR  = 232,
248
    G_JUMP_TABLE  = 233,
249
    G_DYN_STACKALLOC  = 234,
250
    G_STACKSAVE = 235,
251
    G_STACKRESTORE  = 236,
252
    G_STRICT_FADD = 237,
253
    G_STRICT_FSUB = 238,
254
    G_STRICT_FMUL = 239,
255
    G_STRICT_FDIV = 240,
256
    G_STRICT_FREM = 241,
257
    G_STRICT_FMA  = 242,
258
    G_STRICT_FSQRT  = 243,
259
    G_STRICT_FLDEXP = 244,
260
    G_READ_REGISTER = 245,
261
    G_WRITE_REGISTER  = 246,
262
    G_MEMCPY  = 247,
263
    G_MEMCPY_INLINE = 248,
264
    G_MEMMOVE = 249,
265
    G_MEMSET  = 250,
266
    G_BZERO = 251,
267
    G_VECREDUCE_SEQ_FADD  = 252,
268
    G_VECREDUCE_SEQ_FMUL  = 253,
269
    G_VECREDUCE_FADD  = 254,
270
    G_VECREDUCE_FMUL  = 255,
271
    G_VECREDUCE_FMAX  = 256,
272
    G_VECREDUCE_FMIN  = 257,
273
    G_VECREDUCE_FMAXIMUM  = 258,
274
    G_VECREDUCE_FMINIMUM  = 259,
275
    G_VECREDUCE_ADD = 260,
276
    G_VECREDUCE_MUL = 261,
277
    G_VECREDUCE_AND = 262,
278
    G_VECREDUCE_OR  = 263,
279
    G_VECREDUCE_XOR = 264,
280
    G_VECREDUCE_SMAX  = 265,
281
    G_VECREDUCE_SMIN  = 266,
282
    G_VECREDUCE_UMAX  = 267,
283
    G_VECREDUCE_UMIN  = 268,
284
    G_SBFX  = 269,
285
    G_UBFX  = 270,
286
    CALL_PARAMS = 271,
287
    CALL_PARAMS_S = 272,
288
    CALL_RESULTS  = 273,
289
    CALL_RESULTS_S  = 274,
290
    CATCHRET  = 275,
291
    CATCHRET_S  = 276,
292
    CLEANUPRET  = 277,
293
    CLEANUPRET_S  = 278,
294
    COMPILER_FENCE  = 279,
295
    COMPILER_FENCE_S  = 280,
296
    RET_CALL_RESULTS  = 281,
297
    RET_CALL_RESULTS_S  = 282,
298
    ABS_F32 = 283,
299
    ABS_F32_S = 284,
300
    ABS_F32x4 = 285,
301
    ABS_F32x4_S = 286,
302
    ABS_F64 = 287,
303
    ABS_F64_S = 288,
304
    ABS_F64x2 = 289,
305
    ABS_F64x2_S = 290,
306
    ABS_I16x8 = 291,
307
    ABS_I16x8_S = 292,
308
    ABS_I32x4 = 293,
309
    ABS_I32x4_S = 294,
310
    ABS_I64x2 = 295,
311
    ABS_I64x2_S = 296,
312
    ABS_I8x16 = 297,
313
    ABS_I8x16_S = 298,
314
    ADD_F32 = 299,
315
    ADD_F32_S = 300,
316
    ADD_F32x4 = 301,
317
    ADD_F32x4_S = 302,
318
    ADD_F64 = 303,
319
    ADD_F64_S = 304,
320
    ADD_F64x2 = 305,
321
    ADD_F64x2_S = 306,
322
    ADD_I16x8 = 307,
323
    ADD_I16x8_S = 308,
324
    ADD_I32 = 309,
325
    ADD_I32_S = 310,
326
    ADD_I32x4 = 311,
327
    ADD_I32x4_S = 312,
328
    ADD_I64 = 313,
329
    ADD_I64_S = 314,
330
    ADD_I64x2 = 315,
331
    ADD_I64x2_S = 316,
332
    ADD_I8x16 = 317,
333
    ADD_I8x16_S = 318,
334
    ADD_SAT_S_I16x8 = 319,
335
    ADD_SAT_S_I16x8_S = 320,
336
    ADD_SAT_S_I8x16 = 321,
337
    ADD_SAT_S_I8x16_S = 322,
338
    ADD_SAT_U_I16x8 = 323,
339
    ADD_SAT_U_I16x8_S = 324,
340
    ADD_SAT_U_I8x16 = 325,
341
    ADD_SAT_U_I8x16_S = 326,
342
    ADJCALLSTACKDOWN  = 327,
343
    ADJCALLSTACKDOWN_S  = 328,
344
    ADJCALLSTACKUP  = 329,
345
    ADJCALLSTACKUP_S  = 330,
346
    ALLTRUE_I16x8 = 331,
347
    ALLTRUE_I16x8_S = 332,
348
    ALLTRUE_I32x4 = 333,
349
    ALLTRUE_I32x4_S = 334,
350
    ALLTRUE_I64x2 = 335,
351
    ALLTRUE_I64x2_S = 336,
352
    ALLTRUE_I8x16 = 337,
353
    ALLTRUE_I8x16_S = 338,
354
    AND = 339,
355
    ANDNOT  = 340,
356
    ANDNOT_S  = 341,
357
    AND_I32 = 342,
358
    AND_I32_S = 343,
359
    AND_I64 = 344,
360
    AND_I64_S = 345,
361
    AND_S = 346,
362
    ANYTRUE = 347,
363
    ANYTRUE_S = 348,
364
    ARGUMENT_externref  = 349,
365
    ARGUMENT_externref_S  = 350,
366
    ARGUMENT_f32  = 351,
367
    ARGUMENT_f32_S  = 352,
368
    ARGUMENT_f64  = 353,
369
    ARGUMENT_f64_S  = 354,
370
    ARGUMENT_funcref  = 355,
371
    ARGUMENT_funcref_S  = 356,
372
    ARGUMENT_i32  = 357,
373
    ARGUMENT_i32_S  = 358,
374
    ARGUMENT_i64  = 359,
375
    ARGUMENT_i64_S  = 360,
376
    ARGUMENT_v16i8  = 361,
377
    ARGUMENT_v16i8_S  = 362,
378
    ARGUMENT_v2f64  = 363,
379
    ARGUMENT_v2f64_S  = 364,
380
    ARGUMENT_v2i64  = 365,
381
    ARGUMENT_v2i64_S  = 366,
382
    ARGUMENT_v4f32  = 367,
383
    ARGUMENT_v4f32_S  = 368,
384
    ARGUMENT_v4i32  = 369,
385
    ARGUMENT_v4i32_S  = 370,
386
    ARGUMENT_v8i16  = 371,
387
    ARGUMENT_v8i16_S  = 372,
388
    ATOMIC_FENCE  = 373,
389
    ATOMIC_FENCE_S  = 374,
390
    ATOMIC_LOAD16_U_I32_A32 = 375,
391
    ATOMIC_LOAD16_U_I32_A32_S = 376,
392
    ATOMIC_LOAD16_U_I32_A64 = 377,
393
    ATOMIC_LOAD16_U_I32_A64_S = 378,
394
    ATOMIC_LOAD16_U_I64_A32 = 379,
395
    ATOMIC_LOAD16_U_I64_A32_S = 380,
396
    ATOMIC_LOAD16_U_I64_A64 = 381,
397
    ATOMIC_LOAD16_U_I64_A64_S = 382,
398
    ATOMIC_LOAD32_U_I64_A32 = 383,
399
    ATOMIC_LOAD32_U_I64_A32_S = 384,
400
    ATOMIC_LOAD32_U_I64_A64 = 385,
401
    ATOMIC_LOAD32_U_I64_A64_S = 386,
402
    ATOMIC_LOAD8_U_I32_A32  = 387,
403
    ATOMIC_LOAD8_U_I32_A32_S  = 388,
404
    ATOMIC_LOAD8_U_I32_A64  = 389,
405
    ATOMIC_LOAD8_U_I32_A64_S  = 390,
406
    ATOMIC_LOAD8_U_I64_A32  = 391,
407
    ATOMIC_LOAD8_U_I64_A32_S  = 392,
408
    ATOMIC_LOAD8_U_I64_A64  = 393,
409
    ATOMIC_LOAD8_U_I64_A64_S  = 394,
410
    ATOMIC_LOAD_I32_A32 = 395,
411
    ATOMIC_LOAD_I32_A32_S = 396,
412
    ATOMIC_LOAD_I32_A64 = 397,
413
    ATOMIC_LOAD_I32_A64_S = 398,
414
    ATOMIC_LOAD_I64_A32 = 399,
415
    ATOMIC_LOAD_I64_A32_S = 400,
416
    ATOMIC_LOAD_I64_A64 = 401,
417
    ATOMIC_LOAD_I64_A64_S = 402,
418
    ATOMIC_RMW16_U_ADD_I32_A32  = 403,
419
    ATOMIC_RMW16_U_ADD_I32_A32_S  = 404,
420
    ATOMIC_RMW16_U_ADD_I32_A64  = 405,
421
    ATOMIC_RMW16_U_ADD_I32_A64_S  = 406,
422
    ATOMIC_RMW16_U_ADD_I64_A32  = 407,
423
    ATOMIC_RMW16_U_ADD_I64_A32_S  = 408,
424
    ATOMIC_RMW16_U_ADD_I64_A64  = 409,
425
    ATOMIC_RMW16_U_ADD_I64_A64_S  = 410,
426
    ATOMIC_RMW16_U_AND_I32_A32  = 411,
427
    ATOMIC_RMW16_U_AND_I32_A32_S  = 412,
428
    ATOMIC_RMW16_U_AND_I32_A64  = 413,
429
    ATOMIC_RMW16_U_AND_I32_A64_S  = 414,
430
    ATOMIC_RMW16_U_AND_I64_A32  = 415,
431
    ATOMIC_RMW16_U_AND_I64_A32_S  = 416,
432
    ATOMIC_RMW16_U_AND_I64_A64  = 417,
433
    ATOMIC_RMW16_U_AND_I64_A64_S  = 418,
434
    ATOMIC_RMW16_U_CMPXCHG_I32_A32  = 419,
435
    ATOMIC_RMW16_U_CMPXCHG_I32_A32_S  = 420,
436
    ATOMIC_RMW16_U_CMPXCHG_I32_A64  = 421,
437
    ATOMIC_RMW16_U_CMPXCHG_I32_A64_S  = 422,
438
    ATOMIC_RMW16_U_CMPXCHG_I64_A32  = 423,
439
    ATOMIC_RMW16_U_CMPXCHG_I64_A32_S  = 424,
440
    ATOMIC_RMW16_U_CMPXCHG_I64_A64  = 425,
441
    ATOMIC_RMW16_U_CMPXCHG_I64_A64_S  = 426,
442
    ATOMIC_RMW16_U_OR_I32_A32 = 427,
443
    ATOMIC_RMW16_U_OR_I32_A32_S = 428,
444
    ATOMIC_RMW16_U_OR_I32_A64 = 429,
445
    ATOMIC_RMW16_U_OR_I32_A64_S = 430,
446
    ATOMIC_RMW16_U_OR_I64_A32 = 431,
447
    ATOMIC_RMW16_U_OR_I64_A32_S = 432,
448
    ATOMIC_RMW16_U_OR_I64_A64 = 433,
449
    ATOMIC_RMW16_U_OR_I64_A64_S = 434,
450
    ATOMIC_RMW16_U_SUB_I32_A32  = 435,
451
    ATOMIC_RMW16_U_SUB_I32_A32_S  = 436,
452
    ATOMIC_RMW16_U_SUB_I32_A64  = 437,
453
    ATOMIC_RMW16_U_SUB_I32_A64_S  = 438,
454
    ATOMIC_RMW16_U_SUB_I64_A32  = 439,
455
    ATOMIC_RMW16_U_SUB_I64_A32_S  = 440,
456
    ATOMIC_RMW16_U_SUB_I64_A64  = 441,
457
    ATOMIC_RMW16_U_SUB_I64_A64_S  = 442,
458
    ATOMIC_RMW16_U_XCHG_I32_A32 = 443,
459
    ATOMIC_RMW16_U_XCHG_I32_A32_S = 444,
460
    ATOMIC_RMW16_U_XCHG_I32_A64 = 445,
461
    ATOMIC_RMW16_U_XCHG_I32_A64_S = 446,
462
    ATOMIC_RMW16_U_XCHG_I64_A32 = 447,
463
    ATOMIC_RMW16_U_XCHG_I64_A32_S = 448,
464
    ATOMIC_RMW16_U_XCHG_I64_A64 = 449,
465
    ATOMIC_RMW16_U_XCHG_I64_A64_S = 450,
466
    ATOMIC_RMW16_U_XOR_I32_A32  = 451,
467
    ATOMIC_RMW16_U_XOR_I32_A32_S  = 452,
468
    ATOMIC_RMW16_U_XOR_I32_A64  = 453,
469
    ATOMIC_RMW16_U_XOR_I32_A64_S  = 454,
470
    ATOMIC_RMW16_U_XOR_I64_A32  = 455,
471
    ATOMIC_RMW16_U_XOR_I64_A32_S  = 456,
472
    ATOMIC_RMW16_U_XOR_I64_A64  = 457,
473
    ATOMIC_RMW16_U_XOR_I64_A64_S  = 458,
474
    ATOMIC_RMW32_U_ADD_I64_A32  = 459,
475
    ATOMIC_RMW32_U_ADD_I64_A32_S  = 460,
476
    ATOMIC_RMW32_U_ADD_I64_A64  = 461,
477
    ATOMIC_RMW32_U_ADD_I64_A64_S  = 462,
478
    ATOMIC_RMW32_U_AND_I64_A32  = 463,
479
    ATOMIC_RMW32_U_AND_I64_A32_S  = 464,
480
    ATOMIC_RMW32_U_AND_I64_A64  = 465,
481
    ATOMIC_RMW32_U_AND_I64_A64_S  = 466,
482
    ATOMIC_RMW32_U_CMPXCHG_I64_A32  = 467,
483
    ATOMIC_RMW32_U_CMPXCHG_I64_A32_S  = 468,
484
    ATOMIC_RMW32_U_CMPXCHG_I64_A64  = 469,
485
    ATOMIC_RMW32_U_CMPXCHG_I64_A64_S  = 470,
486
    ATOMIC_RMW32_U_OR_I64_A32 = 471,
487
    ATOMIC_RMW32_U_OR_I64_A32_S = 472,
488
    ATOMIC_RMW32_U_OR_I64_A64 = 473,
489
    ATOMIC_RMW32_U_OR_I64_A64_S = 474,
490
    ATOMIC_RMW32_U_SUB_I64_A32  = 475,
491
    ATOMIC_RMW32_U_SUB_I64_A32_S  = 476,
492
    ATOMIC_RMW32_U_SUB_I64_A64  = 477,
493
    ATOMIC_RMW32_U_SUB_I64_A64_S  = 478,
494
    ATOMIC_RMW32_U_XCHG_I64_A32 = 479,
495
    ATOMIC_RMW32_U_XCHG_I64_A32_S = 480,
496
    ATOMIC_RMW32_U_XCHG_I64_A64 = 481,
497
    ATOMIC_RMW32_U_XCHG_I64_A64_S = 482,
498
    ATOMIC_RMW32_U_XOR_I64_A32  = 483,
499
    ATOMIC_RMW32_U_XOR_I64_A32_S  = 484,
500
    ATOMIC_RMW32_U_XOR_I64_A64  = 485,
501
    ATOMIC_RMW32_U_XOR_I64_A64_S  = 486,
502
    ATOMIC_RMW8_U_ADD_I32_A32 = 487,
503
    ATOMIC_RMW8_U_ADD_I32_A32_S = 488,
504
    ATOMIC_RMW8_U_ADD_I32_A64 = 489,
505
    ATOMIC_RMW8_U_ADD_I32_A64_S = 490,
506
    ATOMIC_RMW8_U_ADD_I64_A32 = 491,
507
    ATOMIC_RMW8_U_ADD_I64_A32_S = 492,
508
    ATOMIC_RMW8_U_ADD_I64_A64 = 493,
509
    ATOMIC_RMW8_U_ADD_I64_A64_S = 494,
510
    ATOMIC_RMW8_U_AND_I32_A32 = 495,
511
    ATOMIC_RMW8_U_AND_I32_A32_S = 496,
512
    ATOMIC_RMW8_U_AND_I32_A64 = 497,
513
    ATOMIC_RMW8_U_AND_I32_A64_S = 498,
514
    ATOMIC_RMW8_U_AND_I64_A32 = 499,
515
    ATOMIC_RMW8_U_AND_I64_A32_S = 500,
516
    ATOMIC_RMW8_U_AND_I64_A64 = 501,
517
    ATOMIC_RMW8_U_AND_I64_A64_S = 502,
518
    ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 503,
519
    ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 504,
520
    ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 505,
521
    ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 506,
522
    ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 507,
523
    ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 508,
524
    ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 509,
525
    ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 510,
526
    ATOMIC_RMW8_U_OR_I32_A32  = 511,
527
    ATOMIC_RMW8_U_OR_I32_A32_S  = 512,
528
    ATOMIC_RMW8_U_OR_I32_A64  = 513,
529
    ATOMIC_RMW8_U_OR_I32_A64_S  = 514,
530
    ATOMIC_RMW8_U_OR_I64_A32  = 515,
531
    ATOMIC_RMW8_U_OR_I64_A32_S  = 516,
532
    ATOMIC_RMW8_U_OR_I64_A64  = 517,
533
    ATOMIC_RMW8_U_OR_I64_A64_S  = 518,
534
    ATOMIC_RMW8_U_SUB_I32_A32 = 519,
535
    ATOMIC_RMW8_U_SUB_I32_A32_S = 520,
536
    ATOMIC_RMW8_U_SUB_I32_A64 = 521,
537
    ATOMIC_RMW8_U_SUB_I32_A64_S = 522,
538
    ATOMIC_RMW8_U_SUB_I64_A32 = 523,
539
    ATOMIC_RMW8_U_SUB_I64_A32_S = 524,
540
    ATOMIC_RMW8_U_SUB_I64_A64 = 525,
541
    ATOMIC_RMW8_U_SUB_I64_A64_S = 526,
542
    ATOMIC_RMW8_U_XCHG_I32_A32  = 527,
543
    ATOMIC_RMW8_U_XCHG_I32_A32_S  = 528,
544
    ATOMIC_RMW8_U_XCHG_I32_A64  = 529,
545
    ATOMIC_RMW8_U_XCHG_I32_A64_S  = 530,
546
    ATOMIC_RMW8_U_XCHG_I64_A32  = 531,
547
    ATOMIC_RMW8_U_XCHG_I64_A32_S  = 532,
548
    ATOMIC_RMW8_U_XCHG_I64_A64  = 533,
549
    ATOMIC_RMW8_U_XCHG_I64_A64_S  = 534,
550
    ATOMIC_RMW8_U_XOR_I32_A32 = 535,
551
    ATOMIC_RMW8_U_XOR_I32_A32_S = 536,
552
    ATOMIC_RMW8_U_XOR_I32_A64 = 537,
553
    ATOMIC_RMW8_U_XOR_I32_A64_S = 538,
554
    ATOMIC_RMW8_U_XOR_I64_A32 = 539,
555
    ATOMIC_RMW8_U_XOR_I64_A32_S = 540,
556
    ATOMIC_RMW8_U_XOR_I64_A64 = 541,
557
    ATOMIC_RMW8_U_XOR_I64_A64_S = 542,
558
    ATOMIC_RMW_ADD_I32_A32  = 543,
559
    ATOMIC_RMW_ADD_I32_A32_S  = 544,
560
    ATOMIC_RMW_ADD_I32_A64  = 545,
561
    ATOMIC_RMW_ADD_I32_A64_S  = 546,
562
    ATOMIC_RMW_ADD_I64_A32  = 547,
563
    ATOMIC_RMW_ADD_I64_A32_S  = 548,
564
    ATOMIC_RMW_ADD_I64_A64  = 549,
565
    ATOMIC_RMW_ADD_I64_A64_S  = 550,
566
    ATOMIC_RMW_AND_I32_A32  = 551,
567
    ATOMIC_RMW_AND_I32_A32_S  = 552,
568
    ATOMIC_RMW_AND_I32_A64  = 553,
569
    ATOMIC_RMW_AND_I32_A64_S  = 554,
570
    ATOMIC_RMW_AND_I64_A32  = 555,
571
    ATOMIC_RMW_AND_I64_A32_S  = 556,
572
    ATOMIC_RMW_AND_I64_A64  = 557,
573
    ATOMIC_RMW_AND_I64_A64_S  = 558,
574
    ATOMIC_RMW_CMPXCHG_I32_A32  = 559,
575
    ATOMIC_RMW_CMPXCHG_I32_A32_S  = 560,
576
    ATOMIC_RMW_CMPXCHG_I32_A64  = 561,
577
    ATOMIC_RMW_CMPXCHG_I32_A64_S  = 562,
578
    ATOMIC_RMW_CMPXCHG_I64_A32  = 563,
579
    ATOMIC_RMW_CMPXCHG_I64_A32_S  = 564,
580
    ATOMIC_RMW_CMPXCHG_I64_A64  = 565,
581
    ATOMIC_RMW_CMPXCHG_I64_A64_S  = 566,
582
    ATOMIC_RMW_OR_I32_A32 = 567,
583
    ATOMIC_RMW_OR_I32_A32_S = 568,
584
    ATOMIC_RMW_OR_I32_A64 = 569,
585
    ATOMIC_RMW_OR_I32_A64_S = 570,
586
    ATOMIC_RMW_OR_I64_A32 = 571,
587
    ATOMIC_RMW_OR_I64_A32_S = 572,
588
    ATOMIC_RMW_OR_I64_A64 = 573,
589
    ATOMIC_RMW_OR_I64_A64_S = 574,
590
    ATOMIC_RMW_SUB_I32_A32  = 575,
591
    ATOMIC_RMW_SUB_I32_A32_S  = 576,
592
    ATOMIC_RMW_SUB_I32_A64  = 577,
593
    ATOMIC_RMW_SUB_I32_A64_S  = 578,
594
    ATOMIC_RMW_SUB_I64_A32  = 579,
595
    ATOMIC_RMW_SUB_I64_A32_S  = 580,
596
    ATOMIC_RMW_SUB_I64_A64  = 581,
597
    ATOMIC_RMW_SUB_I64_A64_S  = 582,
598
    ATOMIC_RMW_XCHG_I32_A32 = 583,
599
    ATOMIC_RMW_XCHG_I32_A32_S = 584,
600
    ATOMIC_RMW_XCHG_I32_A64 = 585,
601
    ATOMIC_RMW_XCHG_I32_A64_S = 586,
602
    ATOMIC_RMW_XCHG_I64_A32 = 587,
603
    ATOMIC_RMW_XCHG_I64_A32_S = 588,
604
    ATOMIC_RMW_XCHG_I64_A64 = 589,
605
    ATOMIC_RMW_XCHG_I64_A64_S = 590,
606
    ATOMIC_RMW_XOR_I32_A32  = 591,
607
    ATOMIC_RMW_XOR_I32_A32_S  = 592,
608
    ATOMIC_RMW_XOR_I32_A64  = 593,
609
    ATOMIC_RMW_XOR_I32_A64_S  = 594,
610
    ATOMIC_RMW_XOR_I64_A32  = 595,
611
    ATOMIC_RMW_XOR_I64_A32_S  = 596,
612
    ATOMIC_RMW_XOR_I64_A64  = 597,
613
    ATOMIC_RMW_XOR_I64_A64_S  = 598,
614
    ATOMIC_STORE16_I32_A32  = 599,
615
    ATOMIC_STORE16_I32_A32_S  = 600,
616
    ATOMIC_STORE16_I32_A64  = 601,
617
    ATOMIC_STORE16_I32_A64_S  = 602,
618
    ATOMIC_STORE16_I64_A32  = 603,
619
    ATOMIC_STORE16_I64_A32_S  = 604,
620
    ATOMIC_STORE16_I64_A64  = 605,
621
    ATOMIC_STORE16_I64_A64_S  = 606,
622
    ATOMIC_STORE32_I64_A32  = 607,
623
    ATOMIC_STORE32_I64_A32_S  = 608,
624
    ATOMIC_STORE32_I64_A64  = 609,
625
    ATOMIC_STORE32_I64_A64_S  = 610,
626
    ATOMIC_STORE8_I32_A32 = 611,
627
    ATOMIC_STORE8_I32_A32_S = 612,
628
    ATOMIC_STORE8_I32_A64 = 613,
629
    ATOMIC_STORE8_I32_A64_S = 614,
630
    ATOMIC_STORE8_I64_A32 = 615,
631
    ATOMIC_STORE8_I64_A32_S = 616,
632
    ATOMIC_STORE8_I64_A64 = 617,
633
    ATOMIC_STORE8_I64_A64_S = 618,
634
    ATOMIC_STORE_I32_A32  = 619,
635
    ATOMIC_STORE_I32_A32_S  = 620,
636
    ATOMIC_STORE_I32_A64  = 621,
637
    ATOMIC_STORE_I32_A64_S  = 622,
638
    ATOMIC_STORE_I64_A32  = 623,
639
    ATOMIC_STORE_I64_A32_S  = 624,
640
    ATOMIC_STORE_I64_A64  = 625,
641
    ATOMIC_STORE_I64_A64_S  = 626,
642
    AVGR_U_I16x8  = 627,
643
    AVGR_U_I16x8_S  = 628,
644
    AVGR_U_I8x16  = 629,
645
    AVGR_U_I8x16_S  = 630,
646
    BITMASK_I16x8 = 631,
647
    BITMASK_I16x8_S = 632,
648
    BITMASK_I32x4 = 633,
649
    BITMASK_I32x4_S = 634,
650
    BITMASK_I64x2 = 635,
651
    BITMASK_I64x2_S = 636,
652
    BITMASK_I8x16 = 637,
653
    BITMASK_I8x16_S = 638,
654
    BITSELECT = 639,
655
    BITSELECT_S = 640,
656
    BLOCK = 641,
657
    BLOCK_S = 642,
658
    BR  = 643,
659
    BR_IF = 644,
660
    BR_IF_S = 645,
661
    BR_S  = 646,
662
    BR_TABLE_I32  = 647,
663
    BR_TABLE_I32_S  = 648,
664
    BR_TABLE_I64  = 649,
665
    BR_TABLE_I64_S  = 650,
666
    BR_UNLESS = 651,
667
    BR_UNLESS_S = 652,
668
    CALL  = 653,
669
    CALL_INDIRECT = 654,
670
    CALL_INDIRECT_S = 655,
671
    CALL_S  = 656,
672
    CATCH = 657,
673
    CATCH_ALL = 658,
674
    CATCH_ALL_S = 659,
675
    CATCH_S = 660,
676
    CEIL_F32  = 661,
677
    CEIL_F32_S  = 662,
678
    CEIL_F32x4  = 663,
679
    CEIL_F32x4_S  = 664,
680
    CEIL_F64  = 665,
681
    CEIL_F64_S  = 666,
682
    CEIL_F64x2  = 667,
683
    CEIL_F64x2_S  = 668,
684
    CLZ_I32 = 669,
685
    CLZ_I32_S = 670,
686
    CLZ_I64 = 671,
687
    CLZ_I64_S = 672,
688
    CONST_F32 = 673,
689
    CONST_F32_S = 674,
690
    CONST_F64 = 675,
691
    CONST_F64_S = 676,
692
    CONST_I32 = 677,
693
    CONST_I32_S = 678,
694
    CONST_I64 = 679,
695
    CONST_I64_S = 680,
696
    CONST_V128_F32x4  = 681,
697
    CONST_V128_F32x4_S  = 682,
698
    CONST_V128_F64x2  = 683,
699
    CONST_V128_F64x2_S  = 684,
700
    CONST_V128_I16x8  = 685,
701
    CONST_V128_I16x8_S  = 686,
702
    CONST_V128_I32x4  = 687,
703
    CONST_V128_I32x4_S  = 688,
704
    CONST_V128_I64x2  = 689,
705
    CONST_V128_I64x2_S  = 690,
706
    CONST_V128_I8x16  = 691,
707
    CONST_V128_I8x16_S  = 692,
708
    COPYSIGN_F32  = 693,
709
    COPYSIGN_F32_S  = 694,
710
    COPYSIGN_F64  = 695,
711
    COPYSIGN_F64_S  = 696,
712
    COPY_EXTERNREF  = 697,
713
    COPY_EXTERNREF_S  = 698,
714
    COPY_F32  = 699,
715
    COPY_F32_S  = 700,
716
    COPY_F64  = 701,
717
    COPY_F64_S  = 702,
718
    COPY_FUNCREF  = 703,
719
    COPY_FUNCREF_S  = 704,
720
    COPY_I32  = 705,
721
    COPY_I32_S  = 706,
722
    COPY_I64  = 707,
723
    COPY_I64_S  = 708,
724
    COPY_V128 = 709,
725
    COPY_V128_S = 710,
726
    CTZ_I32 = 711,
727
    CTZ_I32_S = 712,
728
    CTZ_I64 = 713,
729
    CTZ_I64_S = 714,
730
    DEBUG_UNREACHABLE = 715,
731
    DEBUG_UNREACHABLE_S = 716,
732
    DELEGATE  = 717,
733
    DELEGATE_S  = 718,
734
    DIV_F32 = 719,
735
    DIV_F32_S = 720,
736
    DIV_F32x4 = 721,
737
    DIV_F32x4_S = 722,
738
    DIV_F64 = 723,
739
    DIV_F64_S = 724,
740
    DIV_F64x2 = 725,
741
    DIV_F64x2_S = 726,
742
    DIV_S_I32 = 727,
743
    DIV_S_I32_S = 728,
744
    DIV_S_I64 = 729,
745
    DIV_S_I64_S = 730,
746
    DIV_U_I32 = 731,
747
    DIV_U_I32_S = 732,
748
    DIV_U_I64 = 733,
749
    DIV_U_I64_S = 734,
750
    DOT = 735,
751
    DOT_S = 736,
752
    DROP_EXTERNREF  = 737,
753
    DROP_EXTERNREF_S  = 738,
754
    DROP_F32  = 739,
755
    DROP_F32_S  = 740,
756
    DROP_F64  = 741,
757
    DROP_F64_S  = 742,
758
    DROP_FUNCREF  = 743,
759
    DROP_FUNCREF_S  = 744,
760
    DROP_I32  = 745,
761
    DROP_I32_S  = 746,
762
    DROP_I64  = 747,
763
    DROP_I64_S  = 748,
764
    DROP_V128 = 749,
765
    DROP_V128_S = 750,
766
    ELSE  = 751,
767
    ELSE_S  = 752,
768
    END = 753,
769
    END_BLOCK = 754,
770
    END_BLOCK_S = 755,
771
    END_FUNCTION  = 756,
772
    END_FUNCTION_S  = 757,
773
    END_IF  = 758,
774
    END_IF_S  = 759,
775
    END_LOOP  = 760,
776
    END_LOOP_S  = 761,
777
    END_S = 762,
778
    END_TRY = 763,
779
    END_TRY_S = 764,
780
    EQZ_I32 = 765,
781
    EQZ_I32_S = 766,
782
    EQZ_I64 = 767,
783
    EQZ_I64_S = 768,
784
    EQ_F32  = 769,
785
    EQ_F32_S  = 770,
786
    EQ_F32x4  = 771,
787
    EQ_F32x4_S  = 772,
788
    EQ_F64  = 773,
789
    EQ_F64_S  = 774,
790
    EQ_F64x2  = 775,
791
    EQ_F64x2_S  = 776,
792
    EQ_I16x8  = 777,
793
    EQ_I16x8_S  = 778,
794
    EQ_I32  = 779,
795
    EQ_I32_S  = 780,
796
    EQ_I32x4  = 781,
797
    EQ_I32x4_S  = 782,
798
    EQ_I64  = 783,
799
    EQ_I64_S  = 784,
800
    EQ_I64x2  = 785,
801
    EQ_I64x2_S  = 786,
802
    EQ_I8x16  = 787,
803
    EQ_I8x16_S  = 788,
804
    EXTMUL_HIGH_S_I16x8 = 789,
805
    EXTMUL_HIGH_S_I16x8_S = 790,
806
    EXTMUL_HIGH_S_I32x4 = 791,
807
    EXTMUL_HIGH_S_I32x4_S = 792,
808
    EXTMUL_HIGH_S_I64x2 = 793,
809
    EXTMUL_HIGH_S_I64x2_S = 794,
810
    EXTMUL_HIGH_U_I16x8 = 795,
811
    EXTMUL_HIGH_U_I16x8_S = 796,
812
    EXTMUL_HIGH_U_I32x4 = 797,
813
    EXTMUL_HIGH_U_I32x4_S = 798,
814
    EXTMUL_HIGH_U_I64x2 = 799,
815
    EXTMUL_HIGH_U_I64x2_S = 800,
816
    EXTMUL_LOW_S_I16x8  = 801,
817
    EXTMUL_LOW_S_I16x8_S  = 802,
818
    EXTMUL_LOW_S_I32x4  = 803,
819
    EXTMUL_LOW_S_I32x4_S  = 804,
820
    EXTMUL_LOW_S_I64x2  = 805,
821
    EXTMUL_LOW_S_I64x2_S  = 806,
822
    EXTMUL_LOW_U_I16x8  = 807,
823
    EXTMUL_LOW_U_I16x8_S  = 808,
824
    EXTMUL_LOW_U_I32x4  = 809,
825
    EXTMUL_LOW_U_I32x4_S  = 810,
826
    EXTMUL_LOW_U_I64x2  = 811,
827
    EXTMUL_LOW_U_I64x2_S  = 812,
828
    EXTRACT_LANE_F32x4  = 813,
829
    EXTRACT_LANE_F32x4_S  = 814,
830
    EXTRACT_LANE_F64x2  = 815,
831
    EXTRACT_LANE_F64x2_S  = 816,
832
    EXTRACT_LANE_I16x8_s  = 817,
833
    EXTRACT_LANE_I16x8_s_S  = 818,
834
    EXTRACT_LANE_I16x8_u  = 819,
835
    EXTRACT_LANE_I16x8_u_S  = 820,
836
    EXTRACT_LANE_I32x4  = 821,
837
    EXTRACT_LANE_I32x4_S  = 822,
838
    EXTRACT_LANE_I64x2  = 823,
839
    EXTRACT_LANE_I64x2_S  = 824,
840
    EXTRACT_LANE_I8x16_s  = 825,
841
    EXTRACT_LANE_I8x16_s_S  = 826,
842
    EXTRACT_LANE_I8x16_u  = 827,
843
    EXTRACT_LANE_I8x16_u_S  = 828,
844
    F32_CONVERT_S_I32 = 829,
845
    F32_CONVERT_S_I32_S = 830,
846
    F32_CONVERT_S_I64 = 831,
847
    F32_CONVERT_S_I64_S = 832,
848
    F32_CONVERT_U_I32 = 833,
849
    F32_CONVERT_U_I32_S = 834,
850
    F32_CONVERT_U_I64 = 835,
851
    F32_CONVERT_U_I64_S = 836,
852
    F32_DEMOTE_F64  = 837,
853
    F32_DEMOTE_F64_S  = 838,
854
    F32_REINTERPRET_I32 = 839,
855
    F32_REINTERPRET_I32_S = 840,
856
    F64_CONVERT_S_I32 = 841,
857
    F64_CONVERT_S_I32_S = 842,
858
    F64_CONVERT_S_I64 = 843,
859
    F64_CONVERT_S_I64_S = 844,
860
    F64_CONVERT_U_I32 = 845,
861
    F64_CONVERT_U_I32_S = 846,
862
    F64_CONVERT_U_I64 = 847,
863
    F64_CONVERT_U_I64_S = 848,
864
    F64_PROMOTE_F32 = 849,
865
    F64_PROMOTE_F32_S = 850,
866
    F64_REINTERPRET_I64 = 851,
867
    F64_REINTERPRET_I64_S = 852,
868
    FALLTHROUGH_RETURN  = 853,
869
    FALLTHROUGH_RETURN_S  = 854,
870
    FLOOR_F32 = 855,
871
    FLOOR_F32_S = 856,
872
    FLOOR_F32x4 = 857,
873
    FLOOR_F32x4_S = 858,
874
    FLOOR_F64 = 859,
875
    FLOOR_F64_S = 860,
876
    FLOOR_F64x2 = 861,
877
    FLOOR_F64x2_S = 862,
878
    FP_TO_SINT_I32_F32  = 863,
879
    FP_TO_SINT_I32_F32_S  = 864,
880
    FP_TO_SINT_I32_F64  = 865,
881
    FP_TO_SINT_I32_F64_S  = 866,
882
    FP_TO_SINT_I64_F32  = 867,
883
    FP_TO_SINT_I64_F32_S  = 868,
884
    FP_TO_SINT_I64_F64  = 869,
885
    FP_TO_SINT_I64_F64_S  = 870,
886
    FP_TO_UINT_I32_F32  = 871,
887
    FP_TO_UINT_I32_F32_S  = 872,
888
    FP_TO_UINT_I32_F64  = 873,
889
    FP_TO_UINT_I32_F64_S  = 874,
890
    FP_TO_UINT_I64_F32  = 875,
891
    FP_TO_UINT_I64_F32_S  = 876,
892
    FP_TO_UINT_I64_F64  = 877,
893
    FP_TO_UINT_I64_F64_S  = 878,
894
    GE_F32  = 879,
895
    GE_F32_S  = 880,
896
    GE_F32x4  = 881,
897
    GE_F32x4_S  = 882,
898
    GE_F64  = 883,
899
    GE_F64_S  = 884,
900
    GE_F64x2  = 885,
901
    GE_F64x2_S  = 886,
902
    GE_S_I16x8  = 887,
903
    GE_S_I16x8_S  = 888,
904
    GE_S_I32  = 889,
905
    GE_S_I32_S  = 890,
906
    GE_S_I32x4  = 891,
907
    GE_S_I32x4_S  = 892,
908
    GE_S_I64  = 893,
909
    GE_S_I64_S  = 894,
910
    GE_S_I64x2  = 895,
911
    GE_S_I64x2_S  = 896,
912
    GE_S_I8x16  = 897,
913
    GE_S_I8x16_S  = 898,
914
    GE_U_I16x8  = 899,
915
    GE_U_I16x8_S  = 900,
916
    GE_U_I32  = 901,
917
    GE_U_I32_S  = 902,
918
    GE_U_I32x4  = 903,
919
    GE_U_I32x4_S  = 904,
920
    GE_U_I64  = 905,
921
    GE_U_I64_S  = 906,
922
    GE_U_I8x16  = 907,
923
    GE_U_I8x16_S  = 908,
924
    GLOBAL_GET_EXTERNREF  = 909,
925
    GLOBAL_GET_EXTERNREF_S  = 910,
926
    GLOBAL_GET_F32  = 911,
927
    GLOBAL_GET_F32_S  = 912,
928
    GLOBAL_GET_F64  = 913,
929
    GLOBAL_GET_F64_S  = 914,
930
    GLOBAL_GET_FUNCREF  = 915,
931
    GLOBAL_GET_FUNCREF_S  = 916,
932
    GLOBAL_GET_I32  = 917,
933
    GLOBAL_GET_I32_S  = 918,
934
    GLOBAL_GET_I64  = 919,
935
    GLOBAL_GET_I64_S  = 920,
936
    GLOBAL_GET_V128 = 921,
937
    GLOBAL_GET_V128_S = 922,
938
    GLOBAL_SET_EXTERNREF  = 923,
939
    GLOBAL_SET_EXTERNREF_S  = 924,
940
    GLOBAL_SET_F32  = 925,
941
    GLOBAL_SET_F32_S  = 926,
942
    GLOBAL_SET_F64  = 927,
943
    GLOBAL_SET_F64_S  = 928,
944
    GLOBAL_SET_FUNCREF  = 929,
945
    GLOBAL_SET_FUNCREF_S  = 930,
946
    GLOBAL_SET_I32  = 931,
947
    GLOBAL_SET_I32_S  = 932,
948
    GLOBAL_SET_I64  = 933,
949
    GLOBAL_SET_I64_S  = 934,
950
    GLOBAL_SET_V128 = 935,
951
    GLOBAL_SET_V128_S = 936,
952
    GT_F32  = 937,
953
    GT_F32_S  = 938,
954
    GT_F32x4  = 939,
955
    GT_F32x4_S  = 940,
956
    GT_F64  = 941,
957
    GT_F64_S  = 942,
958
    GT_F64x2  = 943,
959
    GT_F64x2_S  = 944,
960
    GT_S_I16x8  = 945,
961
    GT_S_I16x8_S  = 946,
962
    GT_S_I32  = 947,
963
    GT_S_I32_S  = 948,
964
    GT_S_I32x4  = 949,
965
    GT_S_I32x4_S  = 950,
966
    GT_S_I64  = 951,
967
    GT_S_I64_S  = 952,
968
    GT_S_I64x2  = 953,
969
    GT_S_I64x2_S  = 954,
970
    GT_S_I8x16  = 955,
971
    GT_S_I8x16_S  = 956,
972
    GT_U_I16x8  = 957,
973
    GT_U_I16x8_S  = 958,
974
    GT_U_I32  = 959,
975
    GT_U_I32_S  = 960,
976
    GT_U_I32x4  = 961,
977
    GT_U_I32x4_S  = 962,
978
    GT_U_I64  = 963,
979
    GT_U_I64_S  = 964,
980
    GT_U_I8x16  = 965,
981
    GT_U_I8x16_S  = 966,
982
    I32_EXTEND16_S_I32  = 967,
983
    I32_EXTEND16_S_I32_S  = 968,
984
    I32_EXTEND8_S_I32 = 969,
985
    I32_EXTEND8_S_I32_S = 970,
986
    I32_REINTERPRET_F32 = 971,
987
    I32_REINTERPRET_F32_S = 972,
988
    I32_TRUNC_S_F32 = 973,
989
    I32_TRUNC_S_F32_S = 974,
990
    I32_TRUNC_S_F64 = 975,
991
    I32_TRUNC_S_F64_S = 976,
992
    I32_TRUNC_S_SAT_F32 = 977,
993
    I32_TRUNC_S_SAT_F32_S = 978,
994
    I32_TRUNC_S_SAT_F64 = 979,
995
    I32_TRUNC_S_SAT_F64_S = 980,
996
    I32_TRUNC_U_F32 = 981,
997
    I32_TRUNC_U_F32_S = 982,
998
    I32_TRUNC_U_F64 = 983,
999
    I32_TRUNC_U_F64_S = 984,
1000
    I32_TRUNC_U_SAT_F32 = 985,
1001
    I32_TRUNC_U_SAT_F32_S = 986,
1002
    I32_TRUNC_U_SAT_F64 = 987,
1003
    I32_TRUNC_U_SAT_F64_S = 988,
1004
    I32_WRAP_I64  = 989,
1005
    I32_WRAP_I64_S  = 990,
1006
    I64_EXTEND16_S_I64  = 991,
1007
    I64_EXTEND16_S_I64_S  = 992,
1008
    I64_EXTEND32_S_I64  = 993,
1009
    I64_EXTEND32_S_I64_S  = 994,
1010
    I64_EXTEND8_S_I64 = 995,
1011
    I64_EXTEND8_S_I64_S = 996,
1012
    I64_EXTEND_S_I32  = 997,
1013
    I64_EXTEND_S_I32_S  = 998,
1014
    I64_EXTEND_U_I32  = 999,
1015
    I64_EXTEND_U_I32_S  = 1000,
1016
    I64_REINTERPRET_F64 = 1001,
1017
    I64_REINTERPRET_F64_S = 1002,
1018
    I64_TRUNC_S_F32 = 1003,
1019
    I64_TRUNC_S_F32_S = 1004,
1020
    I64_TRUNC_S_F64 = 1005,
1021
    I64_TRUNC_S_F64_S = 1006,
1022
    I64_TRUNC_S_SAT_F32 = 1007,
1023
    I64_TRUNC_S_SAT_F32_S = 1008,
1024
    I64_TRUNC_S_SAT_F64 = 1009,
1025
    I64_TRUNC_S_SAT_F64_S = 1010,
1026
    I64_TRUNC_U_F32 = 1011,
1027
    I64_TRUNC_U_F32_S = 1012,
1028
    I64_TRUNC_U_F64 = 1013,
1029
    I64_TRUNC_U_F64_S = 1014,
1030
    I64_TRUNC_U_SAT_F32 = 1015,
1031
    I64_TRUNC_U_SAT_F32_S = 1016,
1032
    I64_TRUNC_U_SAT_F64 = 1017,
1033
    I64_TRUNC_U_SAT_F64_S = 1018,
1034
    IF  = 1019,
1035
    IF_S  = 1020,
1036
    LANESELECT_I16x8  = 1021,
1037
    LANESELECT_I16x8_S  = 1022,
1038
    LANESELECT_I32x4  = 1023,
1039
    LANESELECT_I32x4_S  = 1024,
1040
    LANESELECT_I64x2  = 1025,
1041
    LANESELECT_I64x2_S  = 1026,
1042
    LANESELECT_I8x16  = 1027,
1043
    LANESELECT_I8x16_S  = 1028,
1044
    LE_F32  = 1029,
1045
    LE_F32_S  = 1030,
1046
    LE_F32x4  = 1031,
1047
    LE_F32x4_S  = 1032,
1048
    LE_F64  = 1033,
1049
    LE_F64_S  = 1034,
1050
    LE_F64x2  = 1035,
1051
    LE_F64x2_S  = 1036,
1052
    LE_S_I16x8  = 1037,
1053
    LE_S_I16x8_S  = 1038,
1054
    LE_S_I32  = 1039,
1055
    LE_S_I32_S  = 1040,
1056
    LE_S_I32x4  = 1041,
1057
    LE_S_I32x4_S  = 1042,
1058
    LE_S_I64  = 1043,
1059
    LE_S_I64_S  = 1044,
1060
    LE_S_I64x2  = 1045,
1061
    LE_S_I64x2_S  = 1046,
1062
    LE_S_I8x16  = 1047,
1063
    LE_S_I8x16_S  = 1048,
1064
    LE_U_I16x8  = 1049,
1065
    LE_U_I16x8_S  = 1050,
1066
    LE_U_I32  = 1051,
1067
    LE_U_I32_S  = 1052,
1068
    LE_U_I32x4  = 1053,
1069
    LE_U_I32x4_S  = 1054,
1070
    LE_U_I64  = 1055,
1071
    LE_U_I64_S  = 1056,
1072
    LE_U_I8x16  = 1057,
1073
    LE_U_I8x16_S  = 1058,
1074
    LOAD16_SPLAT_A32  = 1059,
1075
    LOAD16_SPLAT_A32_S  = 1060,
1076
    LOAD16_SPLAT_A64  = 1061,
1077
    LOAD16_SPLAT_A64_S  = 1062,
1078
    LOAD16_S_I32_A32  = 1063,
1079
    LOAD16_S_I32_A32_S  = 1064,
1080
    LOAD16_S_I32_A64  = 1065,
1081
    LOAD16_S_I32_A64_S  = 1066,
1082
    LOAD16_S_I64_A32  = 1067,
1083
    LOAD16_S_I64_A32_S  = 1068,
1084
    LOAD16_S_I64_A64  = 1069,
1085
    LOAD16_S_I64_A64_S  = 1070,
1086
    LOAD16_U_I32_A32  = 1071,
1087
    LOAD16_U_I32_A32_S  = 1072,
1088
    LOAD16_U_I32_A64  = 1073,
1089
    LOAD16_U_I32_A64_S  = 1074,
1090
    LOAD16_U_I64_A32  = 1075,
1091
    LOAD16_U_I64_A32_S  = 1076,
1092
    LOAD16_U_I64_A64  = 1077,
1093
    LOAD16_U_I64_A64_S  = 1078,
1094
    LOAD32_SPLAT_A32  = 1079,
1095
    LOAD32_SPLAT_A32_S  = 1080,
1096
    LOAD32_SPLAT_A64  = 1081,
1097
    LOAD32_SPLAT_A64_S  = 1082,
1098
    LOAD32_S_I64_A32  = 1083,
1099
    LOAD32_S_I64_A32_S  = 1084,
1100
    LOAD32_S_I64_A64  = 1085,
1101
    LOAD32_S_I64_A64_S  = 1086,
1102
    LOAD32_U_I64_A32  = 1087,
1103
    LOAD32_U_I64_A32_S  = 1088,
1104
    LOAD32_U_I64_A64  = 1089,
1105
    LOAD32_U_I64_A64_S  = 1090,
1106
    LOAD64_SPLAT_A32  = 1091,
1107
    LOAD64_SPLAT_A32_S  = 1092,
1108
    LOAD64_SPLAT_A64  = 1093,
1109
    LOAD64_SPLAT_A64_S  = 1094,
1110
    LOAD8_SPLAT_A32 = 1095,
1111
    LOAD8_SPLAT_A32_S = 1096,
1112
    LOAD8_SPLAT_A64 = 1097,
1113
    LOAD8_SPLAT_A64_S = 1098,
1114
    LOAD8_S_I32_A32 = 1099,
1115
    LOAD8_S_I32_A32_S = 1100,
1116
    LOAD8_S_I32_A64 = 1101,
1117
    LOAD8_S_I32_A64_S = 1102,
1118
    LOAD8_S_I64_A32 = 1103,
1119
    LOAD8_S_I64_A32_S = 1104,
1120
    LOAD8_S_I64_A64 = 1105,
1121
    LOAD8_S_I64_A64_S = 1106,
1122
    LOAD8_U_I32_A32 = 1107,
1123
    LOAD8_U_I32_A32_S = 1108,
1124
    LOAD8_U_I32_A64 = 1109,
1125
    LOAD8_U_I32_A64_S = 1110,
1126
    LOAD8_U_I64_A32 = 1111,
1127
    LOAD8_U_I64_A32_S = 1112,
1128
    LOAD8_U_I64_A64 = 1113,
1129
    LOAD8_U_I64_A64_S = 1114,
1130
    LOAD_EXTEND_S_I16x8_A32 = 1115,
1131
    LOAD_EXTEND_S_I16x8_A32_S = 1116,
1132
    LOAD_EXTEND_S_I16x8_A64 = 1117,
1133
    LOAD_EXTEND_S_I16x8_A64_S = 1118,
1134
    LOAD_EXTEND_S_I32x4_A32 = 1119,
1135
    LOAD_EXTEND_S_I32x4_A32_S = 1120,
1136
    LOAD_EXTEND_S_I32x4_A64 = 1121,
1137
    LOAD_EXTEND_S_I32x4_A64_S = 1122,
1138
    LOAD_EXTEND_S_I64x2_A32 = 1123,
1139
    LOAD_EXTEND_S_I64x2_A32_S = 1124,
1140
    LOAD_EXTEND_S_I64x2_A64 = 1125,
1141
    LOAD_EXTEND_S_I64x2_A64_S = 1126,
1142
    LOAD_EXTEND_U_I16x8_A32 = 1127,
1143
    LOAD_EXTEND_U_I16x8_A32_S = 1128,
1144
    LOAD_EXTEND_U_I16x8_A64 = 1129,
1145
    LOAD_EXTEND_U_I16x8_A64_S = 1130,
1146
    LOAD_EXTEND_U_I32x4_A32 = 1131,
1147
    LOAD_EXTEND_U_I32x4_A32_S = 1132,
1148
    LOAD_EXTEND_U_I32x4_A64 = 1133,
1149
    LOAD_EXTEND_U_I32x4_A64_S = 1134,
1150
    LOAD_EXTEND_U_I64x2_A32 = 1135,
1151
    LOAD_EXTEND_U_I64x2_A32_S = 1136,
1152
    LOAD_EXTEND_U_I64x2_A64 = 1137,
1153
    LOAD_EXTEND_U_I64x2_A64_S = 1138,
1154
    LOAD_F32_A32  = 1139,
1155
    LOAD_F32_A32_S  = 1140,
1156
    LOAD_F32_A64  = 1141,
1157
    LOAD_F32_A64_S  = 1142,
1158
    LOAD_F64_A32  = 1143,
1159
    LOAD_F64_A32_S  = 1144,
1160
    LOAD_F64_A64  = 1145,
1161
    LOAD_F64_A64_S  = 1146,
1162
    LOAD_I32_A32  = 1147,
1163
    LOAD_I32_A32_S  = 1148,
1164
    LOAD_I32_A64  = 1149,
1165
    LOAD_I32_A64_S  = 1150,
1166
    LOAD_I64_A32  = 1151,
1167
    LOAD_I64_A32_S  = 1152,
1168
    LOAD_I64_A64  = 1153,
1169
    LOAD_I64_A64_S  = 1154,
1170
    LOAD_LANE_I16x8_A32 = 1155,
1171
    LOAD_LANE_I16x8_A32_S = 1156,
1172
    LOAD_LANE_I16x8_A64 = 1157,
1173
    LOAD_LANE_I16x8_A64_S = 1158,
1174
    LOAD_LANE_I32x4_A32 = 1159,
1175
    LOAD_LANE_I32x4_A32_S = 1160,
1176
    LOAD_LANE_I32x4_A64 = 1161,
1177
    LOAD_LANE_I32x4_A64_S = 1162,
1178
    LOAD_LANE_I64x2_A32 = 1163,
1179
    LOAD_LANE_I64x2_A32_S = 1164,
1180
    LOAD_LANE_I64x2_A64 = 1165,
1181
    LOAD_LANE_I64x2_A64_S = 1166,
1182
    LOAD_LANE_I8x16_A32 = 1167,
1183
    LOAD_LANE_I8x16_A32_S = 1168,
1184
    LOAD_LANE_I8x16_A64 = 1169,
1185
    LOAD_LANE_I8x16_A64_S = 1170,
1186
    LOAD_V128_A32 = 1171,
1187
    LOAD_V128_A32_S = 1172,
1188
    LOAD_V128_A64 = 1173,
1189
    LOAD_V128_A64_S = 1174,
1190
    LOAD_ZERO_I32x4_A32 = 1175,
1191
    LOAD_ZERO_I32x4_A32_S = 1176,
1192
    LOAD_ZERO_I32x4_A64 = 1177,
1193
    LOAD_ZERO_I32x4_A64_S = 1178,
1194
    LOAD_ZERO_I64x2_A32 = 1179,
1195
    LOAD_ZERO_I64x2_A32_S = 1180,
1196
    LOAD_ZERO_I64x2_A64 = 1181,
1197
    LOAD_ZERO_I64x2_A64_S = 1182,
1198
    LOCAL_GET_EXTERNREF = 1183,
1199
    LOCAL_GET_EXTERNREF_S = 1184,
1200
    LOCAL_GET_F32 = 1185,
1201
    LOCAL_GET_F32_S = 1186,
1202
    LOCAL_GET_F64 = 1187,
1203
    LOCAL_GET_F64_S = 1188,
1204
    LOCAL_GET_FUNCREF = 1189,
1205
    LOCAL_GET_FUNCREF_S = 1190,
1206
    LOCAL_GET_I32 = 1191,
1207
    LOCAL_GET_I32_S = 1192,
1208
    LOCAL_GET_I64 = 1193,
1209
    LOCAL_GET_I64_S = 1194,
1210
    LOCAL_GET_V128  = 1195,
1211
    LOCAL_GET_V128_S  = 1196,
1212
    LOCAL_SET_EXTERNREF = 1197,
1213
    LOCAL_SET_EXTERNREF_S = 1198,
1214
    LOCAL_SET_F32 = 1199,
1215
    LOCAL_SET_F32_S = 1200,
1216
    LOCAL_SET_F64 = 1201,
1217
    LOCAL_SET_F64_S = 1202,
1218
    LOCAL_SET_FUNCREF = 1203,
1219
    LOCAL_SET_FUNCREF_S = 1204,
1220
    LOCAL_SET_I32 = 1205,
1221
    LOCAL_SET_I32_S = 1206,
1222
    LOCAL_SET_I64 = 1207,
1223
    LOCAL_SET_I64_S = 1208,
1224
    LOCAL_SET_V128  = 1209,
1225
    LOCAL_SET_V128_S  = 1210,
1226
    LOCAL_TEE_EXTERNREF = 1211,
1227
    LOCAL_TEE_EXTERNREF_S = 1212,
1228
    LOCAL_TEE_F32 = 1213,
1229
    LOCAL_TEE_F32_S = 1214,
1230
    LOCAL_TEE_F64 = 1215,
1231
    LOCAL_TEE_F64_S = 1216,
1232
    LOCAL_TEE_FUNCREF = 1217,
1233
    LOCAL_TEE_FUNCREF_S = 1218,
1234
    LOCAL_TEE_I32 = 1219,
1235
    LOCAL_TEE_I32_S = 1220,
1236
    LOCAL_TEE_I64 = 1221,
1237
    LOCAL_TEE_I64_S = 1222,
1238
    LOCAL_TEE_V128  = 1223,
1239
    LOCAL_TEE_V128_S  = 1224,
1240
    LOOP  = 1225,
1241
    LOOP_S  = 1226,
1242
    LT_F32  = 1227,
1243
    LT_F32_S  = 1228,
1244
    LT_F32x4  = 1229,
1245
    LT_F32x4_S  = 1230,
1246
    LT_F64  = 1231,
1247
    LT_F64_S  = 1232,
1248
    LT_F64x2  = 1233,
1249
    LT_F64x2_S  = 1234,
1250
    LT_S_I16x8  = 1235,
1251
    LT_S_I16x8_S  = 1236,
1252
    LT_S_I32  = 1237,
1253
    LT_S_I32_S  = 1238,
1254
    LT_S_I32x4  = 1239,
1255
    LT_S_I32x4_S  = 1240,
1256
    LT_S_I64  = 1241,
1257
    LT_S_I64_S  = 1242,
1258
    LT_S_I64x2  = 1243,
1259
    LT_S_I64x2_S  = 1244,
1260
    LT_S_I8x16  = 1245,
1261
    LT_S_I8x16_S  = 1246,
1262
    LT_U_I16x8  = 1247,
1263
    LT_U_I16x8_S  = 1248,
1264
    LT_U_I32  = 1249,
1265
    LT_U_I32_S  = 1250,
1266
    LT_U_I32x4  = 1251,
1267
    LT_U_I32x4_S  = 1252,
1268
    LT_U_I64  = 1253,
1269
    LT_U_I64_S  = 1254,
1270
    LT_U_I8x16  = 1255,
1271
    LT_U_I8x16_S  = 1256,
1272
    MADD_F32x4  = 1257,
1273
    MADD_F32x4_S  = 1258,
1274
    MADD_F64x2  = 1259,
1275
    MADD_F64x2_S  = 1260,
1276
    MAX_F32 = 1261,
1277
    MAX_F32_S = 1262,
1278
    MAX_F32x4 = 1263,
1279
    MAX_F32x4_S = 1264,
1280
    MAX_F64 = 1265,
1281
    MAX_F64_S = 1266,
1282
    MAX_F64x2 = 1267,
1283
    MAX_F64x2_S = 1268,
1284
    MAX_S_I16x8 = 1269,
1285
    MAX_S_I16x8_S = 1270,
1286
    MAX_S_I32x4 = 1271,
1287
    MAX_S_I32x4_S = 1272,
1288
    MAX_S_I8x16 = 1273,
1289
    MAX_S_I8x16_S = 1274,
1290
    MAX_U_I16x8 = 1275,
1291
    MAX_U_I16x8_S = 1276,
1292
    MAX_U_I32x4 = 1277,
1293
    MAX_U_I32x4_S = 1278,
1294
    MAX_U_I8x16 = 1279,
1295
    MAX_U_I8x16_S = 1280,
1296
    MEMORY_ATOMIC_NOTIFY_A32  = 1281,
1297
    MEMORY_ATOMIC_NOTIFY_A32_S  = 1282,
1298
    MEMORY_ATOMIC_NOTIFY_A64  = 1283,
1299
    MEMORY_ATOMIC_NOTIFY_A64_S  = 1284,
1300
    MEMORY_ATOMIC_WAIT32_A32  = 1285,
1301
    MEMORY_ATOMIC_WAIT32_A32_S  = 1286,
1302
    MEMORY_ATOMIC_WAIT32_A64  = 1287,
1303
    MEMORY_ATOMIC_WAIT32_A64_S  = 1288,
1304
    MEMORY_ATOMIC_WAIT64_A32  = 1289,
1305
    MEMORY_ATOMIC_WAIT64_A32_S  = 1290,
1306
    MEMORY_ATOMIC_WAIT64_A64  = 1291,
1307
    MEMORY_ATOMIC_WAIT64_A64_S  = 1292,
1308
    MIN_F32 = 1293,
1309
    MIN_F32_S = 1294,
1310
    MIN_F32x4 = 1295,
1311
    MIN_F32x4_S = 1296,
1312
    MIN_F64 = 1297,
1313
    MIN_F64_S = 1298,
1314
    MIN_F64x2 = 1299,
1315
    MIN_F64x2_S = 1300,
1316
    MIN_S_I16x8 = 1301,
1317
    MIN_S_I16x8_S = 1302,
1318
    MIN_S_I32x4 = 1303,
1319
    MIN_S_I32x4_S = 1304,
1320
    MIN_S_I8x16 = 1305,
1321
    MIN_S_I8x16_S = 1306,
1322
    MIN_U_I16x8 = 1307,
1323
    MIN_U_I16x8_S = 1308,
1324
    MIN_U_I32x4 = 1309,
1325
    MIN_U_I32x4_S = 1310,
1326
    MIN_U_I8x16 = 1311,
1327
    MIN_U_I8x16_S = 1312,
1328
    MUL_F32 = 1313,
1329
    MUL_F32_S = 1314,
1330
    MUL_F32x4 = 1315,
1331
    MUL_F32x4_S = 1316,
1332
    MUL_F64 = 1317,
1333
    MUL_F64_S = 1318,
1334
    MUL_F64x2 = 1319,
1335
    MUL_F64x2_S = 1320,
1336
    MUL_I16x8 = 1321,
1337
    MUL_I16x8_S = 1322,
1338
    MUL_I32 = 1323,
1339
    MUL_I32_S = 1324,
1340
    MUL_I32x4 = 1325,
1341
    MUL_I32x4_S = 1326,
1342
    MUL_I64 = 1327,
1343
    MUL_I64_S = 1328,
1344
    MUL_I64x2 = 1329,
1345
    MUL_I64x2_S = 1330,
1346
    NARROW_S_I16x8  = 1331,
1347
    NARROW_S_I16x8_S  = 1332,
1348
    NARROW_S_I8x16  = 1333,
1349
    NARROW_S_I8x16_S  = 1334,
1350
    NARROW_U_I16x8  = 1335,
1351
    NARROW_U_I16x8_S  = 1336,
1352
    NARROW_U_I8x16  = 1337,
1353
    NARROW_U_I8x16_S  = 1338,
1354
    NEAREST_F32 = 1339,
1355
    NEAREST_F32_S = 1340,
1356
    NEAREST_F32x4 = 1341,
1357
    NEAREST_F32x4_S = 1342,
1358
    NEAREST_F64 = 1343,
1359
    NEAREST_F64_S = 1344,
1360
    NEAREST_F64x2 = 1345,
1361
    NEAREST_F64x2_S = 1346,
1362
    NEG_F32 = 1347,
1363
    NEG_F32_S = 1348,
1364
    NEG_F32x4 = 1349,
1365
    NEG_F32x4_S = 1350,
1366
    NEG_F64 = 1351,
1367
    NEG_F64_S = 1352,
1368
    NEG_F64x2 = 1353,
1369
    NEG_F64x2_S = 1354,
1370
    NEG_I16x8 = 1355,
1371
    NEG_I16x8_S = 1356,
1372
    NEG_I32x4 = 1357,
1373
    NEG_I32x4_S = 1358,
1374
    NEG_I64x2 = 1359,
1375
    NEG_I64x2_S = 1360,
1376
    NEG_I8x16 = 1361,
1377
    NEG_I8x16_S = 1362,
1378
    NE_F32  = 1363,
1379
    NE_F32_S  = 1364,
1380
    NE_F32x4  = 1365,
1381
    NE_F32x4_S  = 1366,
1382
    NE_F64  = 1367,
1383
    NE_F64_S  = 1368,
1384
    NE_F64x2  = 1369,
1385
    NE_F64x2_S  = 1370,
1386
    NE_I16x8  = 1371,
1387
    NE_I16x8_S  = 1372,
1388
    NE_I32  = 1373,
1389
    NE_I32_S  = 1374,
1390
    NE_I32x4  = 1375,
1391
    NE_I32x4_S  = 1376,
1392
    NE_I64  = 1377,
1393
    NE_I64_S  = 1378,
1394
    NE_I64x2  = 1379,
1395
    NE_I64x2_S  = 1380,
1396
    NE_I8x16  = 1381,
1397
    NE_I8x16_S  = 1382,
1398
    NMADD_F32x4 = 1383,
1399
    NMADD_F32x4_S = 1384,
1400
    NMADD_F64x2 = 1385,
1401
    NMADD_F64x2_S = 1386,
1402
    NOP = 1387,
1403
    NOP_S = 1388,
1404
    NOT = 1389,
1405
    NOT_S = 1390,
1406
    OR  = 1391,
1407
    OR_I32  = 1392,
1408
    OR_I32_S  = 1393,
1409
    OR_I64  = 1394,
1410
    OR_I64_S  = 1395,
1411
    OR_S  = 1396,
1412
    PMAX_F32x4  = 1397,
1413
    PMAX_F32x4_S  = 1398,
1414
    PMAX_F64x2  = 1399,
1415
    PMAX_F64x2_S  = 1400,
1416
    PMIN_F32x4  = 1401,
1417
    PMIN_F32x4_S  = 1402,
1418
    PMIN_F64x2  = 1403,
1419
    PMIN_F64x2_S  = 1404,
1420
    POPCNT_I32  = 1405,
1421
    POPCNT_I32_S  = 1406,
1422
    POPCNT_I64  = 1407,
1423
    POPCNT_I64_S  = 1408,
1424
    POPCNT_I8x16  = 1409,
1425
    POPCNT_I8x16_S  = 1410,
1426
    Q15MULR_SAT_S_I16x8 = 1411,
1427
    Q15MULR_SAT_S_I16x8_S = 1412,
1428
    REF_IS_NULL_EXTERNREF = 1413,
1429
    REF_IS_NULL_EXTERNREF_S = 1414,
1430
    REF_IS_NULL_FUNCREF = 1415,
1431
    REF_IS_NULL_FUNCREF_S = 1416,
1432
    REF_NULL_EXTERNREF  = 1417,
1433
    REF_NULL_EXTERNREF_S  = 1418,
1434
    REF_NULL_FUNCREF  = 1419,
1435
    REF_NULL_FUNCREF_S  = 1420,
1436
    RELAXED_DOT = 1421,
1437
    RELAXED_DOT_ADD = 1422,
1438
    RELAXED_DOT_ADD_S = 1423,
1439
    RELAXED_DOT_BFLOAT  = 1424,
1440
    RELAXED_DOT_BFLOAT_S  = 1425,
1441
    RELAXED_DOT_S = 1426,
1442
    RELAXED_Q15MULR_S_I16x8 = 1427,
1443
    RELAXED_Q15MULR_S_I16x8_S = 1428,
1444
    RELAXED_SWIZZLE = 1429,
1445
    RELAXED_SWIZZLE_S = 1430,
1446
    REM_S_I32 = 1431,
1447
    REM_S_I32_S = 1432,
1448
    REM_S_I64 = 1433,
1449
    REM_S_I64_S = 1434,
1450
    REM_U_I32 = 1435,
1451
    REM_U_I32_S = 1436,
1452
    REM_U_I64 = 1437,
1453
    REM_U_I64_S = 1438,
1454
    REPLACE_LANE_F32x4  = 1439,
1455
    REPLACE_LANE_F32x4_S  = 1440,
1456
    REPLACE_LANE_F64x2  = 1441,
1457
    REPLACE_LANE_F64x2_S  = 1442,
1458
    REPLACE_LANE_I16x8  = 1443,
1459
    REPLACE_LANE_I16x8_S  = 1444,
1460
    REPLACE_LANE_I32x4  = 1445,
1461
    REPLACE_LANE_I32x4_S  = 1446,
1462
    REPLACE_LANE_I64x2  = 1447,
1463
    REPLACE_LANE_I64x2_S  = 1448,
1464
    REPLACE_LANE_I8x16  = 1449,
1465
    REPLACE_LANE_I8x16_S  = 1450,
1466
    RETHROW = 1451,
1467
    RETHROW_S = 1452,
1468
    RETURN  = 1453,
1469
    RETURN_S  = 1454,
1470
    RET_CALL  = 1455,
1471
    RET_CALL_INDIRECT = 1456,
1472
    RET_CALL_INDIRECT_S = 1457,
1473
    RET_CALL_S  = 1458,
1474
    ROTL_I32  = 1459,
1475
    ROTL_I32_S  = 1460,
1476
    ROTL_I64  = 1461,
1477
    ROTL_I64_S  = 1462,
1478
    ROTR_I32  = 1463,
1479
    ROTR_I32_S  = 1464,
1480
    ROTR_I64  = 1465,
1481
    ROTR_I64_S  = 1466,
1482
    SELECT_EXTERNREF  = 1467,
1483
    SELECT_EXTERNREF_S  = 1468,
1484
    SELECT_F32  = 1469,
1485
    SELECT_F32_S  = 1470,
1486
    SELECT_F64  = 1471,
1487
    SELECT_F64_S  = 1472,
1488
    SELECT_FUNCREF  = 1473,
1489
    SELECT_FUNCREF_S  = 1474,
1490
    SELECT_I32  = 1475,
1491
    SELECT_I32_S  = 1476,
1492
    SELECT_I64  = 1477,
1493
    SELECT_I64_S  = 1478,
1494
    SELECT_V128 = 1479,
1495
    SELECT_V128_S = 1480,
1496
    SHL_I16x8 = 1481,
1497
    SHL_I16x8_S = 1482,
1498
    SHL_I32 = 1483,
1499
    SHL_I32_S = 1484,
1500
    SHL_I32x4 = 1485,
1501
    SHL_I32x4_S = 1486,
1502
    SHL_I64 = 1487,
1503
    SHL_I64_S = 1488,
1504
    SHL_I64x2 = 1489,
1505
    SHL_I64x2_S = 1490,
1506
    SHL_I8x16 = 1491,
1507
    SHL_I8x16_S = 1492,
1508
    SHR_S_I16x8 = 1493,
1509
    SHR_S_I16x8_S = 1494,
1510
    SHR_S_I32 = 1495,
1511
    SHR_S_I32_S = 1496,
1512
    SHR_S_I32x4 = 1497,
1513
    SHR_S_I32x4_S = 1498,
1514
    SHR_S_I64 = 1499,
1515
    SHR_S_I64_S = 1500,
1516
    SHR_S_I64x2 = 1501,
1517
    SHR_S_I64x2_S = 1502,
1518
    SHR_S_I8x16 = 1503,
1519
    SHR_S_I8x16_S = 1504,
1520
    SHR_U_I16x8 = 1505,
1521
    SHR_U_I16x8_S = 1506,
1522
    SHR_U_I32 = 1507,
1523
    SHR_U_I32_S = 1508,
1524
    SHR_U_I32x4 = 1509,
1525
    SHR_U_I32x4_S = 1510,
1526
    SHR_U_I64 = 1511,
1527
    SHR_U_I64_S = 1512,
1528
    SHR_U_I64x2 = 1513,
1529
    SHR_U_I64x2_S = 1514,
1530
    SHR_U_I8x16 = 1515,
1531
    SHR_U_I8x16_S = 1516,
1532
    SHUFFLE = 1517,
1533
    SHUFFLE_S = 1518,
1534
    SIMD_RELAXED_FMAX_F32x4 = 1519,
1535
    SIMD_RELAXED_FMAX_F32x4_S = 1520,
1536
    SIMD_RELAXED_FMAX_F64x2 = 1521,
1537
    SIMD_RELAXED_FMAX_F64x2_S = 1522,
1538
    SIMD_RELAXED_FMIN_F32x4 = 1523,
1539
    SIMD_RELAXED_FMIN_F32x4_S = 1524,
1540
    SIMD_RELAXED_FMIN_F64x2 = 1525,
1541
    SIMD_RELAXED_FMIN_F64x2_S = 1526,
1542
    SPLAT_F32x4 = 1527,
1543
    SPLAT_F32x4_S = 1528,
1544
    SPLAT_F64x2 = 1529,
1545
    SPLAT_F64x2_S = 1530,
1546
    SPLAT_I16x8 = 1531,
1547
    SPLAT_I16x8_S = 1532,
1548
    SPLAT_I32x4 = 1533,
1549
    SPLAT_I32x4_S = 1534,
1550
    SPLAT_I64x2 = 1535,
1551
    SPLAT_I64x2_S = 1536,
1552
    SPLAT_I8x16 = 1537,
1553
    SPLAT_I8x16_S = 1538,
1554
    SQRT_F32  = 1539,
1555
    SQRT_F32_S  = 1540,
1556
    SQRT_F32x4  = 1541,
1557
    SQRT_F32x4_S  = 1542,
1558
    SQRT_F64  = 1543,
1559
    SQRT_F64_S  = 1544,
1560
    SQRT_F64x2  = 1545,
1561
    SQRT_F64x2_S  = 1546,
1562
    STORE16_I32_A32 = 1547,
1563
    STORE16_I32_A32_S = 1548,
1564
    STORE16_I32_A64 = 1549,
1565
    STORE16_I32_A64_S = 1550,
1566
    STORE16_I64_A32 = 1551,
1567
    STORE16_I64_A32_S = 1552,
1568
    STORE16_I64_A64 = 1553,
1569
    STORE16_I64_A64_S = 1554,
1570
    STORE32_I64_A32 = 1555,
1571
    STORE32_I64_A32_S = 1556,
1572
    STORE32_I64_A64 = 1557,
1573
    STORE32_I64_A64_S = 1558,
1574
    STORE8_I32_A32  = 1559,
1575
    STORE8_I32_A32_S  = 1560,
1576
    STORE8_I32_A64  = 1561,
1577
    STORE8_I32_A64_S  = 1562,
1578
    STORE8_I64_A32  = 1563,
1579
    STORE8_I64_A32_S  = 1564,
1580
    STORE8_I64_A64  = 1565,
1581
    STORE8_I64_A64_S  = 1566,
1582
    STORE_F32_A32 = 1567,
1583
    STORE_F32_A32_S = 1568,
1584
    STORE_F32_A64 = 1569,
1585
    STORE_F32_A64_S = 1570,
1586
    STORE_F64_A32 = 1571,
1587
    STORE_F64_A32_S = 1572,
1588
    STORE_F64_A64 = 1573,
1589
    STORE_F64_A64_S = 1574,
1590
    STORE_I32_A32 = 1575,
1591
    STORE_I32_A32_S = 1576,
1592
    STORE_I32_A64 = 1577,
1593
    STORE_I32_A64_S = 1578,
1594
    STORE_I64_A32 = 1579,
1595
    STORE_I64_A32_S = 1580,
1596
    STORE_I64_A64 = 1581,
1597
    STORE_I64_A64_S = 1582,
1598
    STORE_LANE_I16x8_A32  = 1583,
1599
    STORE_LANE_I16x8_A32_S  = 1584,
1600
    STORE_LANE_I16x8_A64  = 1585,
1601
    STORE_LANE_I16x8_A64_S  = 1586,
1602
    STORE_LANE_I32x4_A32  = 1587,
1603
    STORE_LANE_I32x4_A32_S  = 1588,
1604
    STORE_LANE_I32x4_A64  = 1589,
1605
    STORE_LANE_I32x4_A64_S  = 1590,
1606
    STORE_LANE_I64x2_A32  = 1591,
1607
    STORE_LANE_I64x2_A32_S  = 1592,
1608
    STORE_LANE_I64x2_A64  = 1593,
1609
    STORE_LANE_I64x2_A64_S  = 1594,
1610
    STORE_LANE_I8x16_A32  = 1595,
1611
    STORE_LANE_I8x16_A32_S  = 1596,
1612
    STORE_LANE_I8x16_A64  = 1597,
1613
    STORE_LANE_I8x16_A64_S  = 1598,
1614
    STORE_V128_A32  = 1599,
1615
    STORE_V128_A32_S  = 1600,
1616
    STORE_V128_A64  = 1601,
1617
    STORE_V128_A64_S  = 1602,
1618
    SUB_F32 = 1603,
1619
    SUB_F32_S = 1604,
1620
    SUB_F32x4 = 1605,
1621
    SUB_F32x4_S = 1606,
1622
    SUB_F64 = 1607,
1623
    SUB_F64_S = 1608,
1624
    SUB_F64x2 = 1609,
1625
    SUB_F64x2_S = 1610,
1626
    SUB_I16x8 = 1611,
1627
    SUB_I16x8_S = 1612,
1628
    SUB_I32 = 1613,
1629
    SUB_I32_S = 1614,
1630
    SUB_I32x4 = 1615,
1631
    SUB_I32x4_S = 1616,
1632
    SUB_I64 = 1617,
1633
    SUB_I64_S = 1618,
1634
    SUB_I64x2 = 1619,
1635
    SUB_I64x2_S = 1620,
1636
    SUB_I8x16 = 1621,
1637
    SUB_I8x16_S = 1622,
1638
    SUB_SAT_S_I16x8 = 1623,
1639
    SUB_SAT_S_I16x8_S = 1624,
1640
    SUB_SAT_S_I8x16 = 1625,
1641
    SUB_SAT_S_I8x16_S = 1626,
1642
    SUB_SAT_U_I16x8 = 1627,
1643
    SUB_SAT_U_I16x8_S = 1628,
1644
    SUB_SAT_U_I8x16 = 1629,
1645
    SUB_SAT_U_I8x16_S = 1630,
1646
    SWIZZLE = 1631,
1647
    SWIZZLE_S = 1632,
1648
    TABLE_COPY  = 1633,
1649
    TABLE_COPY_S  = 1634,
1650
    TABLE_FILL_EXTERNREF  = 1635,
1651
    TABLE_FILL_EXTERNREF_S  = 1636,
1652
    TABLE_FILL_FUNCREF  = 1637,
1653
    TABLE_FILL_FUNCREF_S  = 1638,
1654
    TABLE_GET_EXTERNREF = 1639,
1655
    TABLE_GET_EXTERNREF_S = 1640,
1656
    TABLE_GET_FUNCREF = 1641,
1657
    TABLE_GET_FUNCREF_S = 1642,
1658
    TABLE_GROW_EXTERNREF  = 1643,
1659
    TABLE_GROW_EXTERNREF_S  = 1644,
1660
    TABLE_GROW_FUNCREF  = 1645,
1661
    TABLE_GROW_FUNCREF_S  = 1646,
1662
    TABLE_SET_EXTERNREF = 1647,
1663
    TABLE_SET_EXTERNREF_S = 1648,
1664
    TABLE_SET_FUNCREF = 1649,
1665
    TABLE_SET_FUNCREF_S = 1650,
1666
    TABLE_SIZE  = 1651,
1667
    TABLE_SIZE_S  = 1652,
1668
    TEE_EXTERNREF = 1653,
1669
    TEE_EXTERNREF_S = 1654,
1670
    TEE_F32 = 1655,
1671
    TEE_F32_S = 1656,
1672
    TEE_F64 = 1657,
1673
    TEE_F64_S = 1658,
1674
    TEE_FUNCREF = 1659,
1675
    TEE_FUNCREF_S = 1660,
1676
    TEE_I32 = 1661,
1677
    TEE_I32_S = 1662,
1678
    TEE_I64 = 1663,
1679
    TEE_I64_S = 1664,
1680
    TEE_V128  = 1665,
1681
    TEE_V128_S  = 1666,
1682
    THROW = 1667,
1683
    THROW_S = 1668,
1684
    TRUNC_F32 = 1669,
1685
    TRUNC_F32_S = 1670,
1686
    TRUNC_F32x4 = 1671,
1687
    TRUNC_F32x4_S = 1672,
1688
    TRUNC_F64 = 1673,
1689
    TRUNC_F64_S = 1674,
1690
    TRUNC_F64x2 = 1675,
1691
    TRUNC_F64x2_S = 1676,
1692
    TRY = 1677,
1693
    TRY_S = 1678,
1694
    UNREACHABLE = 1679,
1695
    UNREACHABLE_S = 1680,
1696
    XOR = 1681,
1697
    XOR_I32 = 1682,
1698
    XOR_I32_S = 1683,
1699
    XOR_I64 = 1684,
1700
    XOR_I64_S = 1685,
1701
    XOR_S = 1686,
1702
    anonymous_7277MEMORY_GROW_A32 = 1687,
1703
    anonymous_7277MEMORY_GROW_A32_S = 1688,
1704
    anonymous_7277MEMORY_SIZE_A32 = 1689,
1705
    anonymous_7277MEMORY_SIZE_A32_S = 1690,
1706
    anonymous_7278MEMORY_GROW_A64 = 1691,
1707
    anonymous_7278MEMORY_GROW_A64_S = 1692,
1708
    anonymous_7278MEMORY_SIZE_A64 = 1693,
1709
    anonymous_7278MEMORY_SIZE_A64_S = 1694,
1710
    anonymous_7959DATA_DROP = 1695,
1711
    anonymous_7959DATA_DROP_S = 1696,
1712
    anonymous_7959MEMORY_COPY_A32 = 1697,
1713
    anonymous_7959MEMORY_COPY_A32_S = 1698,
1714
    anonymous_7959MEMORY_FILL_A32 = 1699,
1715
    anonymous_7959MEMORY_FILL_A32_S = 1700,
1716
    anonymous_7959MEMORY_INIT_A32 = 1701,
1717
    anonymous_7959MEMORY_INIT_A32_S = 1702,
1718
    anonymous_7960DATA_DROP = 1703,
1719
    anonymous_7960DATA_DROP_S = 1704,
1720
    anonymous_7960MEMORY_COPY_A64 = 1705,
1721
    anonymous_7960MEMORY_COPY_A64_S = 1706,
1722
    anonymous_7960MEMORY_FILL_A64 = 1707,
1723
    anonymous_7960MEMORY_FILL_A64_S = 1708,
1724
    anonymous_7960MEMORY_INIT_A64 = 1709,
1725
    anonymous_7960MEMORY_INIT_A64_S = 1710,
1726
    convert_low_s_F64x2 = 1711,
1727
    convert_low_s_F64x2_S = 1712,
1728
    convert_low_u_F64x2 = 1713,
1729
    convert_low_u_F64x2_S = 1714,
1730
    demote_zero_F32x4 = 1715,
1731
    demote_zero_F32x4_S = 1716,
1732
    extend_high_s_I16x8 = 1717,
1733
    extend_high_s_I16x8_S = 1718,
1734
    extend_high_s_I32x4 = 1719,
1735
    extend_high_s_I32x4_S = 1720,
1736
    extend_high_s_I64x2 = 1721,
1737
    extend_high_s_I64x2_S = 1722,
1738
    extend_high_u_I16x8 = 1723,
1739
    extend_high_u_I16x8_S = 1724,
1740
    extend_high_u_I32x4 = 1725,
1741
    extend_high_u_I32x4_S = 1726,
1742
    extend_high_u_I64x2 = 1727,
1743
    extend_high_u_I64x2_S = 1728,
1744
    extend_low_s_I16x8  = 1729,
1745
    extend_low_s_I16x8_S  = 1730,
1746
    extend_low_s_I32x4  = 1731,
1747
    extend_low_s_I32x4_S  = 1732,
1748
    extend_low_s_I64x2  = 1733,
1749
    extend_low_s_I64x2_S  = 1734,
1750
    extend_low_u_I16x8  = 1735,
1751
    extend_low_u_I16x8_S  = 1736,
1752
    extend_low_u_I32x4  = 1737,
1753
    extend_low_u_I32x4_S  = 1738,
1754
    extend_low_u_I64x2  = 1739,
1755
    extend_low_u_I64x2_S  = 1740,
1756
    fp_to_sint_I32x4  = 1741,
1757
    fp_to_sint_I32x4_S  = 1742,
1758
    fp_to_uint_I32x4  = 1743,
1759
    fp_to_uint_I32x4_S  = 1744,
1760
    int_wasm_extadd_pairwise_signed_I16x8 = 1745,
1761
    int_wasm_extadd_pairwise_signed_I16x8_S = 1746,
1762
    int_wasm_extadd_pairwise_signed_I32x4 = 1747,
1763
    int_wasm_extadd_pairwise_signed_I32x4_S = 1748,
1764
    int_wasm_extadd_pairwise_unsigned_I16x8 = 1749,
1765
    int_wasm_extadd_pairwise_unsigned_I16x8_S = 1750,
1766
    int_wasm_extadd_pairwise_unsigned_I32x4 = 1751,
1767
    int_wasm_extadd_pairwise_unsigned_I32x4_S = 1752,
1768
    int_wasm_relaxed_trunc_signed_I32x4 = 1753,
1769
    int_wasm_relaxed_trunc_signed_I32x4_S = 1754,
1770
    int_wasm_relaxed_trunc_signed_zero_I32x4  = 1755,
1771
    int_wasm_relaxed_trunc_signed_zero_I32x4_S  = 1756,
1772
    int_wasm_relaxed_trunc_unsigned_I32x4 = 1757,
1773
    int_wasm_relaxed_trunc_unsigned_I32x4_S = 1758,
1774
    int_wasm_relaxed_trunc_unsigned_zero_I32x4  = 1759,
1775
    int_wasm_relaxed_trunc_unsigned_zero_I32x4_S  = 1760,
1776
    promote_low_F64x2 = 1761,
1777
    promote_low_F64x2_S = 1762,
1778
    sint_to_fp_F32x4  = 1763,
1779
    sint_to_fp_F32x4_S  = 1764,
1780
    trunc_sat_zero_s_I32x4  = 1765,
1781
    trunc_sat_zero_s_I32x4_S  = 1766,
1782
    trunc_sat_zero_u_I32x4  = 1767,
1783
    trunc_sat_zero_u_I32x4_S  = 1768,
1784
    uint_to_fp_F32x4  = 1769,
1785
    uint_to_fp_F32x4_S  = 1770,
1786
    INSTRUCTION_LIST_END = 1771
1787
  };
1788
1789
} // end namespace WebAssembly
1790
} // end namespace llvm
1791
#endif // GET_INSTRINFO_ENUM
1792
1793
#ifdef GET_INSTRINFO_SCHED_ENUM
1794
#undef GET_INSTRINFO_SCHED_ENUM
1795
namespace llvm {
1796
1797
namespace WebAssembly {
1798
namespace Sched {
1799
  enum {
1800
    NoInstrModel  = 0,
1801
    SCHED_LIST_END = 1
1802
  };
1803
} // end namespace Sched
1804
} // end namespace WebAssembly
1805
} // end namespace llvm
1806
#endif // GET_INSTRINFO_SCHED_ENUM
1807
1808
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
1809
namespace llvm {
1810
1811
struct WebAssemblyInstrTable {
1812
  MCInstrDesc Insts[1771];
1813
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
1814
  MCOperandInfo OperandInfo[757];
1815
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
1816
  MCPhysReg ImplicitOps[10];
1817
};
1818
1819
} // end namespace llvm
1820
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
1821
1822
#ifdef GET_INSTRINFO_MC_DESC
1823
#undef GET_INSTRINFO_MC_DESC
1824
namespace llvm {
1825
1826
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
1827
static constexpr unsigned WebAssemblyImpOpBase = sizeof WebAssemblyInstrTable::OperandInfo / (sizeof(MCPhysReg));
1828
1829
extern const WebAssemblyInstrTable WebAssemblyDescs = {
1830
  {
1831
    { 1770, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1770 = uint_to_fp_F32x4_S
1832
    { 1769, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1769 = uint_to_fp_F32x4
1833
    { 1768, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1768 = trunc_sat_zero_u_I32x4_S
1834
    { 1767, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1767 = trunc_sat_zero_u_I32x4
1835
    { 1766, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1766 = trunc_sat_zero_s_I32x4_S
1836
    { 1765, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1765 = trunc_sat_zero_s_I32x4
1837
    { 1764, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1764 = sint_to_fp_F32x4_S
1838
    { 1763, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1763 = sint_to_fp_F32x4
1839
    { 1762, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1762 = promote_low_F64x2_S
1840
    { 1761, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1761 = promote_low_F64x2
1841
    { 1760, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1760 = int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
1842
    { 1759, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1759 = int_wasm_relaxed_trunc_unsigned_zero_I32x4
1843
    { 1758, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1758 = int_wasm_relaxed_trunc_unsigned_I32x4_S
1844
    { 1757, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1757 = int_wasm_relaxed_trunc_unsigned_I32x4
1845
    { 1756, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1756 = int_wasm_relaxed_trunc_signed_zero_I32x4_S
1846
    { 1755, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1755 = int_wasm_relaxed_trunc_signed_zero_I32x4
1847
    { 1754, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1754 = int_wasm_relaxed_trunc_signed_I32x4_S
1848
    { 1753, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1753 = int_wasm_relaxed_trunc_signed_I32x4
1849
    { 1752, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1752 = int_wasm_extadd_pairwise_unsigned_I32x4_S
1850
    { 1751, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1751 = int_wasm_extadd_pairwise_unsigned_I32x4
1851
    { 1750, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1750 = int_wasm_extadd_pairwise_unsigned_I16x8_S
1852
    { 1749, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1749 = int_wasm_extadd_pairwise_unsigned_I16x8
1853
    { 1748, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1748 = int_wasm_extadd_pairwise_signed_I32x4_S
1854
    { 1747, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1747 = int_wasm_extadd_pairwise_signed_I32x4
1855
    { 1746, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1746 = int_wasm_extadd_pairwise_signed_I16x8_S
1856
    { 1745, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1745 = int_wasm_extadd_pairwise_signed_I16x8
1857
    { 1744, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1744 = fp_to_uint_I32x4_S
1858
    { 1743, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1743 = fp_to_uint_I32x4
1859
    { 1742, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1742 = fp_to_sint_I32x4_S
1860
    { 1741, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1741 = fp_to_sint_I32x4
1861
    { 1740, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1740 = extend_low_u_I64x2_S
1862
    { 1739, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1739 = extend_low_u_I64x2
1863
    { 1738, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1738 = extend_low_u_I32x4_S
1864
    { 1737, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1737 = extend_low_u_I32x4
1865
    { 1736, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1736 = extend_low_u_I16x8_S
1866
    { 1735, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1735 = extend_low_u_I16x8
1867
    { 1734, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1734 = extend_low_s_I64x2_S
1868
    { 1733, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1733 = extend_low_s_I64x2
1869
    { 1732, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1732 = extend_low_s_I32x4_S
1870
    { 1731, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1731 = extend_low_s_I32x4
1871
    { 1730, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1730 = extend_low_s_I16x8_S
1872
    { 1729, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1729 = extend_low_s_I16x8
1873
    { 1728, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1728 = extend_high_u_I64x2_S
1874
    { 1727, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1727 = extend_high_u_I64x2
1875
    { 1726, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1726 = extend_high_u_I32x4_S
1876
    { 1725, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1725 = extend_high_u_I32x4
1877
    { 1724, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1724 = extend_high_u_I16x8_S
1878
    { 1723, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1723 = extend_high_u_I16x8
1879
    { 1722, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1722 = extend_high_s_I64x2_S
1880
    { 1721, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1721 = extend_high_s_I64x2
1881
    { 1720, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1720 = extend_high_s_I32x4_S
1882
    { 1719, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1719 = extend_high_s_I32x4
1883
    { 1718, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1718 = extend_high_s_I16x8_S
1884
    { 1717, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1717 = extend_high_s_I16x8
1885
    { 1716, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1716 = demote_zero_F32x4_S
1886
    { 1715, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1715 = demote_zero_F32x4
1887
    { 1714, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1714 = convert_low_u_F64x2_S
1888
    { 1713, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1713 = convert_low_u_F64x2
1889
    { 1712, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1712 = convert_low_s_F64x2_S
1890
    { 1711, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1711 = convert_low_s_F64x2
1891
    { 1710, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 737,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1710 = anonymous_7960MEMORY_INIT_A64_S
1892
    { 1709, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 752,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1709 = anonymous_7960MEMORY_INIT_A64
1893
    { 1708, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 286,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1708 = anonymous_7960MEMORY_FILL_A64_S
1894
    { 1707, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 748,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1707 = anonymous_7960MEMORY_FILL_A64
1895
    { 1706, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 737,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1706 = anonymous_7960MEMORY_COPY_A64_S
1896
    { 1705, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 743,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1705 = anonymous_7960MEMORY_COPY_A64
1897
    { 1704, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 286,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1704 = anonymous_7960DATA_DROP_S
1898
    { 1703, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 286,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1703 = anonymous_7960DATA_DROP
1899
    { 1702, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 737,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1702 = anonymous_7959MEMORY_INIT_A32_S
1900
    { 1701, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 732,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1701 = anonymous_7959MEMORY_INIT_A32
1901
    { 1700, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 286,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1700 = anonymous_7959MEMORY_FILL_A32_S
1902
    { 1699, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 739,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1699 = anonymous_7959MEMORY_FILL_A32
1903
    { 1698, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 737,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1698 = anonymous_7959MEMORY_COPY_A32_S
1904
    { 1697, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 732,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1697 = anonymous_7959MEMORY_COPY_A32
1905
    { 1696, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 286,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1696 = anonymous_7959DATA_DROP_S
1906
    { 1695, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 286,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1695 = anonymous_7959DATA_DROP
1907
    { 1694, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1694 = anonymous_7278MEMORY_SIZE_A64_S
1908
    { 1693, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1693 = anonymous_7278MEMORY_SIZE_A64
1909
    { 1692, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1692 = anonymous_7278MEMORY_GROW_A64_S
1910
    { 1691, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 729,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1691 = anonymous_7278MEMORY_GROW_A64
1911
    { 1690, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1690 = anonymous_7277MEMORY_SIZE_A32_S
1912
    { 1689, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 174,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1689 = anonymous_7277MEMORY_SIZE_A32
1913
    { 1688, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1688 = anonymous_7277MEMORY_GROW_A32_S
1914
    { 1687, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 726,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1687 = anonymous_7277MEMORY_GROW_A32
1915
    { 1686, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1686 = XOR_S
1916
    { 1685, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1685 = XOR_I64_S
1917
    { 1684, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1684 = XOR_I64
1918
    { 1683, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1683 = XOR_I32_S
1919
    { 1682, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1682 = XOR_I32
1920
    { 1681, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1681 = XOR
1921
    { 1680, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1680 = UNREACHABLE_S
1922
    { 1679, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1679 = UNREACHABLE
1923
    { 1678, 1,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1678 = TRY_S
1924
    { 1677, 1,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1677 = TRY
1925
    { 1676, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1676 = TRUNC_F64x2_S
1926
    { 1675, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1675 = TRUNC_F64x2
1927
    { 1674, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1674 = TRUNC_F64_S
1928
    { 1673, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 147,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1673 = TRUNC_F64
1929
    { 1672, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1672 = TRUNC_F32x4_S
1930
    { 1671, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1671 = TRUNC_F32x4
1931
    { 1670, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1670 = TRUNC_F32_S
1932
    { 1669, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1669 = TRUNC_F32
1933
    { 1668, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 273,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1668 = THROW_S
1934
    { 1667, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 273,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1667 = THROW
1935
    { 1666, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1666 = TEE_V128_S
1936
    { 1665, 3,  2,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1665 = TEE_V128
1937
    { 1664, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1664 = TEE_I64_S
1938
    { 1663, 3,  2,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1663 = TEE_I64
1939
    { 1662, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1662 = TEE_I32_S
1940
    { 1661, 3,  2,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1661 = TEE_I32
1941
    { 1660, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1660 = TEE_FUNCREF_S
1942
    { 1659, 3,  2,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 723,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1659 = TEE_FUNCREF
1943
    { 1658, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1658 = TEE_F64_S
1944
    { 1657, 3,  2,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 155,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1657 = TEE_F64
1945
    { 1656, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1656 = TEE_F32_S
1946
    { 1655, 3,  2,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 149,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1655 = TEE_F32
1947
    { 1654, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1654 = TEE_EXTERNREF_S
1948
    { 1653, 3,  2,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 720,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1653 = TEE_EXTERNREF
1949
    { 1652, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1652 = TABLE_SIZE_S
1950
    { 1651, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 718,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1651 = TABLE_SIZE
1951
    { 1650, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1650 = TABLE_SET_FUNCREF_S
1952
    { 1649, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 715,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1649 = TABLE_SET_FUNCREF
1953
    { 1648, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1648 = TABLE_SET_EXTERNREF_S
1954
    { 1647, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 712,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1647 = TABLE_SET_EXTERNREF
1955
    { 1646, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1646 = TABLE_GROW_FUNCREF_S
1956
    { 1645, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 708,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1645 = TABLE_GROW_FUNCREF
1957
    { 1644, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1644 = TABLE_GROW_EXTERNREF_S
1958
    { 1643, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 704,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1643 = TABLE_GROW_EXTERNREF
1959
    { 1642, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1642 = TABLE_GET_FUNCREF_S
1960
    { 1641, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 701,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1641 = TABLE_GET_FUNCREF
1961
    { 1640, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1640 = TABLE_GET_EXTERNREF_S
1962
    { 1639, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 698,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1639 = TABLE_GET_EXTERNREF
1963
    { 1638, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1638 = TABLE_FILL_FUNCREF_S
1964
    { 1637, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 694,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1637 = TABLE_FILL_FUNCREF
1965
    { 1636, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 693,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1636 = TABLE_FILL_EXTERNREF_S
1966
    { 1635, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 689,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1635 = TABLE_FILL_EXTERNREF
1967
    { 1634, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 687,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1634 = TABLE_COPY_S
1968
    { 1633, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 682,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1633 = TABLE_COPY
1969
    { 1632, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1632 = SWIZZLE_S
1970
    { 1631, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1631 = SWIZZLE
1971
    { 1630, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1630 = SUB_SAT_U_I8x16_S
1972
    { 1629, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1629 = SUB_SAT_U_I8x16
1973
    { 1628, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1628 = SUB_SAT_U_I16x8_S
1974
    { 1627, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1627 = SUB_SAT_U_I16x8
1975
    { 1626, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1626 = SUB_SAT_S_I8x16_S
1976
    { 1625, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1625 = SUB_SAT_S_I8x16
1977
    { 1624, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1624 = SUB_SAT_S_I16x8_S
1978
    { 1623, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1623 = SUB_SAT_S_I16x8
1979
    { 1622, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1622 = SUB_I8x16_S
1980
    { 1621, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1621 = SUB_I8x16
1981
    { 1620, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1620 = SUB_I64x2_S
1982
    { 1619, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1619 = SUB_I64x2
1983
    { 1618, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1618 = SUB_I64_S
1984
    { 1617, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1617 = SUB_I64
1985
    { 1616, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1616 = SUB_I32x4_S
1986
    { 1615, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1615 = SUB_I32x4
1987
    { 1614, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1614 = SUB_I32_S
1988
    { 1613, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1613 = SUB_I32
1989
    { 1612, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1612 = SUB_I16x8_S
1990
    { 1611, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1611 = SUB_I16x8
1991
    { 1610, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1610 = SUB_F64x2_S
1992
    { 1609, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1609 = SUB_F64x2
1993
    { 1608, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1608 = SUB_F64_S
1994
    { 1607, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 155,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1607 = SUB_F64
1995
    { 1606, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1606 = SUB_F32x4_S
1996
    { 1605, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1605 = SUB_F32x4
1997
    { 1604, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1604 = SUB_F32_S
1998
    { 1603, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 149,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1603 = SUB_F32
1999
    { 1602, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1602 = STORE_V128_A64_S
2000
    { 1601, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 678,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1601 = STORE_V128_A64
2001
    { 1600, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1600 = STORE_V128_A32_S
2002
    { 1599, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 674,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1599 = STORE_V128_A32
2003
    { 1598, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 493,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1598 = STORE_LANE_I8x16_A64_S
2004
    { 1597, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 669,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1597 = STORE_LANE_I8x16_A64
2005
    { 1596, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 484,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1596 = STORE_LANE_I8x16_A32_S
2006
    { 1595, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 664,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1595 = STORE_LANE_I8x16_A32
2007
    { 1594, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 493,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1594 = STORE_LANE_I64x2_A64_S
2008
    { 1593, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 669,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1593 = STORE_LANE_I64x2_A64
2009
    { 1592, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 484,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1592 = STORE_LANE_I64x2_A32_S
2010
    { 1591, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 664,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1591 = STORE_LANE_I64x2_A32
2011
    { 1590, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 493,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1590 = STORE_LANE_I32x4_A64_S
2012
    { 1589, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 669,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1589 = STORE_LANE_I32x4_A64
2013
    { 1588, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 484,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1588 = STORE_LANE_I32x4_A32_S
2014
    { 1587, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 664,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1587 = STORE_LANE_I32x4_A32
2015
    { 1586, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 493,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1586 = STORE_LANE_I16x8_A64_S
2016
    { 1585, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 669,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1585 = STORE_LANE_I16x8_A64
2017
    { 1584, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 484,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1584 = STORE_LANE_I16x8_A32_S
2018
    { 1583, 5,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 664,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1583 = STORE_LANE_I16x8_A32
2019
    { 1582, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1582 = STORE_I64_A64_S
2020
    { 1581, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 256,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1581 = STORE_I64_A64
2021
    { 1580, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1580 = STORE_I64_A32_S
2022
    { 1579, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 252,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1579 = STORE_I64_A32
2023
    { 1578, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1578 = STORE_I32_A64_S
2024
    { 1577, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 248,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1577 = STORE_I32_A64
2025
    { 1576, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1576 = STORE_I32_A32_S
2026
    { 1575, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1575 = STORE_I32_A32
2027
    { 1574, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1574 = STORE_F64_A64_S
2028
    { 1573, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 660,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1573 = STORE_F64_A64
2029
    { 1572, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1572 = STORE_F64_A32_S
2030
    { 1571, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 656,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1571 = STORE_F64_A32
2031
    { 1570, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1570 = STORE_F32_A64_S
2032
    { 1569, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 652,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1569 = STORE_F32_A64
2033
    { 1568, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1568 = STORE_F32_A32_S
2034
    { 1567, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 648,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1567 = STORE_F32_A32
2035
    { 1566, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1566 = STORE8_I64_A64_S
2036
    { 1565, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 256,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1565 = STORE8_I64_A64
2037
    { 1564, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1564 = STORE8_I64_A32_S
2038
    { 1563, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 252,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1563 = STORE8_I64_A32
2039
    { 1562, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1562 = STORE8_I32_A64_S
2040
    { 1561, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 248,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1561 = STORE8_I32_A64
2041
    { 1560, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1560 = STORE8_I32_A32_S
2042
    { 1559, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1559 = STORE8_I32_A32
2043
    { 1558, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1558 = STORE32_I64_A64_S
2044
    { 1557, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 256,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1557 = STORE32_I64_A64
2045
    { 1556, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1556 = STORE32_I64_A32_S
2046
    { 1555, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 252,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1555 = STORE32_I64_A32
2047
    { 1554, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1554 = STORE16_I64_A64_S
2048
    { 1553, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 256,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1553 = STORE16_I64_A64
2049
    { 1552, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1552 = STORE16_I64_A32_S
2050
    { 1551, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 252,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1551 = STORE16_I64_A32
2051
    { 1550, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1550 = STORE16_I32_A64_S
2052
    { 1549, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 248,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1549 = STORE16_I32_A64
2053
    { 1548, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1548 = STORE16_I32_A32_S
2054
    { 1547, 4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1547 = STORE16_I32_A32
2055
    { 1546, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1546 = SQRT_F64x2_S
2056
    { 1545, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1545 = SQRT_F64x2
2057
    { 1544, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1544 = SQRT_F64_S
2058
    { 1543, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 147,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1543 = SQRT_F64
2059
    { 1542, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1542 = SQRT_F32x4_S
2060
    { 1541, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1541 = SQRT_F32x4
2061
    { 1540, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1540 = SQRT_F32_S
2062
    { 1539, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1539 = SQRT_F32
2063
    { 1538, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1538 = SPLAT_I8x16_S
2064
    { 1537, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 644,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1537 = SPLAT_I8x16
2065
    { 1536, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1536 = SPLAT_I64x2_S
2066
    { 1535, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 646,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1535 = SPLAT_I64x2
2067
    { 1534, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1534 = SPLAT_I32x4_S
2068
    { 1533, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 644,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1533 = SPLAT_I32x4
2069
    { 1532, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1532 = SPLAT_I16x8_S
2070
    { 1531, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 644,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1531 = SPLAT_I16x8
2071
    { 1530, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1530 = SPLAT_F64x2_S
2072
    { 1529, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 642,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1529 = SPLAT_F64x2
2073
    { 1528, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1528 = SPLAT_F32x4_S
2074
    { 1527, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 640,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1527 = SPLAT_F32x4
2075
    { 1526, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1526 = SIMD_RELAXED_FMIN_F64x2_S
2076
    { 1525, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1525 = SIMD_RELAXED_FMIN_F64x2
2077
    { 1524, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1524 = SIMD_RELAXED_FMIN_F32x4_S
2078
    { 1523, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1523 = SIMD_RELAXED_FMIN_F32x4
2079
    { 1522, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1522 = SIMD_RELAXED_FMAX_F64x2_S
2080
    { 1521, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1521 = SIMD_RELAXED_FMAX_F64x2
2081
    { 1520, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1520 = SIMD_RELAXED_FMAX_F32x4_S
2082
    { 1519, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1519 = SIMD_RELAXED_FMAX_F32x4
2083
    { 1518, 16, 0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 352,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1518 = SHUFFLE_S
2084
    { 1517, 19, 1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 621,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1517 = SHUFFLE
2085
    { 1516, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1516 = SHR_U_I8x16_S
2086
    { 1515, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1515 = SHR_U_I8x16
2087
    { 1514, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1514 = SHR_U_I64x2_S
2088
    { 1513, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1513 = SHR_U_I64x2
2089
    { 1512, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1512 = SHR_U_I64_S
2090
    { 1511, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1511 = SHR_U_I64
2091
    { 1510, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1510 = SHR_U_I32x4_S
2092
    { 1509, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1509 = SHR_U_I32x4
2093
    { 1508, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1508 = SHR_U_I32_S
2094
    { 1507, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1507 = SHR_U_I32
2095
    { 1506, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1506 = SHR_U_I16x8_S
2096
    { 1505, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1505 = SHR_U_I16x8
2097
    { 1504, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1504 = SHR_S_I8x16_S
2098
    { 1503, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1503 = SHR_S_I8x16
2099
    { 1502, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1502 = SHR_S_I64x2_S
2100
    { 1501, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1501 = SHR_S_I64x2
2101
    { 1500, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1500 = SHR_S_I64_S
2102
    { 1499, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1499 = SHR_S_I64
2103
    { 1498, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1498 = SHR_S_I32x4_S
2104
    { 1497, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1497 = SHR_S_I32x4
2105
    { 1496, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1496 = SHR_S_I32_S
2106
    { 1495, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1495 = SHR_S_I32
2107
    { 1494, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1494 = SHR_S_I16x8_S
2108
    { 1493, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1493 = SHR_S_I16x8
2109
    { 1492, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1492 = SHL_I8x16_S
2110
    { 1491, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1491 = SHL_I8x16
2111
    { 1490, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1490 = SHL_I64x2_S
2112
    { 1489, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1489 = SHL_I64x2
2113
    { 1488, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1488 = SHL_I64_S
2114
    { 1487, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1487 = SHL_I64
2115
    { 1486, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1486 = SHL_I32x4_S
2116
    { 1485, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1485 = SHL_I32x4
2117
    { 1484, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1484 = SHL_I32_S
2118
    { 1483, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1483 = SHL_I32
2119
    { 1482, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1482 = SHL_I16x8_S
2120
    { 1481, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 618,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1481 = SHL_I16x8
2121
    { 1480, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1480 = SELECT_V128_S
2122
    { 1479, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 614,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1479 = SELECT_V128
2123
    { 1478, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1478 = SELECT_I64_S
2124
    { 1477, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 610,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1477 = SELECT_I64
2125
    { 1476, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1476 = SELECT_I32_S
2126
    { 1475, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 606,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1475 = SELECT_I32
2127
    { 1474, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1474 = SELECT_FUNCREF_S
2128
    { 1473, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 602,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1473 = SELECT_FUNCREF
2129
    { 1472, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1472 = SELECT_F64_S
2130
    { 1471, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 598,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1471 = SELECT_F64
2131
    { 1470, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1470 = SELECT_F32_S
2132
    { 1469, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 594,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1469 = SELECT_F32
2133
    { 1468, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1468 = SELECT_EXTERNREF_S
2134
    { 1467, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 590,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1467 = SELECT_EXTERNREF
2135
    { 1466, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1466 = ROTR_I64_S
2136
    { 1465, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1465 = ROTR_I64
2137
    { 1464, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1464 = ROTR_I32_S
2138
    { 1463, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1463 = ROTR_I32
2139
    { 1462, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1462 = ROTL_I64_S
2140
    { 1461, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1461 = ROTL_I64
2141
    { 1460, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1460 = ROTL_I32_S
2142
    { 1459, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1459 = ROTL_I32
2143
    { 1458, 1,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 140,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1458 = RET_CALL_S
2144
    { 1457, 2,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 271,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1457 = RET_CALL_INDIRECT_S
2145
    { 1456, 2,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 271,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1456 = RET_CALL_INDIRECT
2146
    { 1455, 1,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 140,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1455 = RET_CALL
2147
    { 1454, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1454 = RETURN_S
2148
    { 1453, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1453 = RETURN
2149
    { 1452, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1452 = RETHROW_S
2150
    { 1451, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1451 = RETHROW
2151
    { 1450, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1450 = REPLACE_LANE_I8x16_S
2152
    { 1449, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 582,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1449 = REPLACE_LANE_I8x16
2153
    { 1448, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1448 = REPLACE_LANE_I64x2_S
2154
    { 1447, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 586,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1447 = REPLACE_LANE_I64x2
2155
    { 1446, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1446 = REPLACE_LANE_I32x4_S
2156
    { 1445, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 582,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1445 = REPLACE_LANE_I32x4
2157
    { 1444, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1444 = REPLACE_LANE_I16x8_S
2158
    { 1443, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 582,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1443 = REPLACE_LANE_I16x8
2159
    { 1442, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1442 = REPLACE_LANE_F64x2_S
2160
    { 1441, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 578,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1441 = REPLACE_LANE_F64x2
2161
    { 1440, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1440 = REPLACE_LANE_F32x4_S
2162
    { 1439, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 574,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1439 = REPLACE_LANE_F32x4
2163
    { 1438, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1438 = REM_U_I64_S
2164
    { 1437, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1437 = REM_U_I64
2165
    { 1436, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1436 = REM_U_I32_S
2166
    { 1435, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1435 = REM_U_I32
2167
    { 1434, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1434 = REM_S_I64_S
2168
    { 1433, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1433 = REM_S_I64
2169
    { 1432, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1432 = REM_S_I32_S
2170
    { 1431, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1431 = REM_S_I32
2171
    { 1430, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1430 = RELAXED_SWIZZLE_S
2172
    { 1429, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1429 = RELAXED_SWIZZLE
2173
    { 1428, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1428 = RELAXED_Q15MULR_S_I16x8_S
2174
    { 1427, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1427 = RELAXED_Q15MULR_S_I16x8
2175
    { 1426, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1426 = RELAXED_DOT_S
2176
    { 1425, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1425 = RELAXED_DOT_BFLOAT_S
2177
    { 1424, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1424 = RELAXED_DOT_BFLOAT
2178
    { 1423, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1423 = RELAXED_DOT_ADD_S
2179
    { 1422, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1422 = RELAXED_DOT_ADD
2180
    { 1421, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1421 = RELAXED_DOT
2181
    { 1420, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1420 = REF_NULL_FUNCREF_S
2182
    { 1419, 1,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 375,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1419 = REF_NULL_FUNCREF
2183
    { 1418, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1418 = REF_NULL_EXTERNREF_S
2184
    { 1417, 1,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 372,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1417 = REF_NULL_EXTERNREF
2185
    { 1416, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1416 = REF_IS_NULL_FUNCREF_S
2186
    { 1415, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 572,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1415 = REF_IS_NULL_FUNCREF
2187
    { 1414, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1414 = REF_IS_NULL_EXTERNREF_S
2188
    { 1413, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 570,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1413 = REF_IS_NULL_EXTERNREF
2189
    { 1412, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1412 = Q15MULR_SAT_S_I16x8_S
2190
    { 1411, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1411 = Q15MULR_SAT_S_I16x8
2191
    { 1410, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1410 = POPCNT_I8x16_S
2192
    { 1409, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1409 = POPCNT_I8x16
2193
    { 1408, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1408 = POPCNT_I64_S
2194
    { 1407, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 276,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1407 = POPCNT_I64
2195
    { 1406, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1406 = POPCNT_I32_S
2196
    { 1405, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 274,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1405 = POPCNT_I32
2197
    { 1404, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1404 = PMIN_F64x2_S
2198
    { 1403, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1403 = PMIN_F64x2
2199
    { 1402, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1402 = PMIN_F32x4_S
2200
    { 1401, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1401 = PMIN_F32x4
2201
    { 1400, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1400 = PMAX_F64x2_S
2202
    { 1399, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1399 = PMAX_F64x2
2203
    { 1398, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1398 = PMAX_F32x4_S
2204
    { 1397, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1397 = PMAX_F32x4
2205
    { 1396, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1396 = OR_S
2206
    { 1395, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1395 = OR_I64_S
2207
    { 1394, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1394 = OR_I64
2208
    { 1393, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1393 = OR_I32_S
2209
    { 1392, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1392 = OR_I32
2210
    { 1391, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1391 = OR
2211
    { 1390, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1390 = NOT_S
2212
    { 1389, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1389 = NOT
2213
    { 1388, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1388 = NOP_S
2214
    { 1387, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1387 = NOP
2215
    { 1386, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1386 = NMADD_F64x2_S
2216
    { 1385, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1385 = NMADD_F64x2
2217
    { 1384, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1384 = NMADD_F32x4_S
2218
    { 1383, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1383 = NMADD_F32x4
2219
    { 1382, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1382 = NE_I8x16_S
2220
    { 1381, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1381 = NE_I8x16
2221
    { 1380, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1380 = NE_I64x2_S
2222
    { 1379, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1379 = NE_I64x2
2223
    { 1378, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1378 = NE_I64_S
2224
    { 1377, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1377 = NE_I64
2225
    { 1376, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1376 = NE_I32x4_S
2226
    { 1375, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1375 = NE_I32x4
2227
    { 1374, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1374 = NE_I32_S
2228
    { 1373, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1373 = NE_I32
2229
    { 1372, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1372 = NE_I16x8_S
2230
    { 1371, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1371 = NE_I16x8
2231
    { 1370, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1370 = NE_F64x2_S
2232
    { 1369, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1369 = NE_F64x2
2233
    { 1368, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1368 = NE_F64_S
2234
    { 1367, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 382,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1367 = NE_F64
2235
    { 1366, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1366 = NE_F32x4_S
2236
    { 1365, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1365 = NE_F32x4
2237
    { 1364, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1364 = NE_F32_S
2238
    { 1363, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 379,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1363 = NE_F32
2239
    { 1362, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1362 = NEG_I8x16_S
2240
    { 1361, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1361 = NEG_I8x16
2241
    { 1360, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1360 = NEG_I64x2_S
2242
    { 1359, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1359 = NEG_I64x2
2243
    { 1358, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1358 = NEG_I32x4_S
2244
    { 1357, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1357 = NEG_I32x4
2245
    { 1356, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1356 = NEG_I16x8_S
2246
    { 1355, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1355 = NEG_I16x8
2247
    { 1354, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1354 = NEG_F64x2_S
2248
    { 1353, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1353 = NEG_F64x2
2249
    { 1352, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1352 = NEG_F64_S
2250
    { 1351, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 147,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1351 = NEG_F64
2251
    { 1350, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1350 = NEG_F32x4_S
2252
    { 1349, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1349 = NEG_F32x4
2253
    { 1348, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1348 = NEG_F32_S
2254
    { 1347, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1347 = NEG_F32
2255
    { 1346, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1346 = NEAREST_F64x2_S
2256
    { 1345, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1345 = NEAREST_F64x2
2257
    { 1344, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1344 = NEAREST_F64_S
2258
    { 1343, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 147,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1343 = NEAREST_F64
2259
    { 1342, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1342 = NEAREST_F32x4_S
2260
    { 1341, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1341 = NEAREST_F32x4
2261
    { 1340, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1340 = NEAREST_F32_S
2262
    { 1339, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1339 = NEAREST_F32
2263
    { 1338, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1338 = NARROW_U_I8x16_S
2264
    { 1337, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1337 = NARROW_U_I8x16
2265
    { 1336, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1336 = NARROW_U_I16x8_S
2266
    { 1335, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1335 = NARROW_U_I16x8
2267
    { 1334, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1334 = NARROW_S_I8x16_S
2268
    { 1333, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1333 = NARROW_S_I8x16
2269
    { 1332, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1332 = NARROW_S_I16x8_S
2270
    { 1331, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1331 = NARROW_S_I16x8
2271
    { 1330, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1330 = MUL_I64x2_S
2272
    { 1329, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1329 = MUL_I64x2
2273
    { 1328, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1328 = MUL_I64_S
2274
    { 1327, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1327 = MUL_I64
2275
    { 1326, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1326 = MUL_I32x4_S
2276
    { 1325, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1325 = MUL_I32x4
2277
    { 1324, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1324 = MUL_I32_S
2278
    { 1323, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1323 = MUL_I32
2279
    { 1322, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1322 = MUL_I16x8_S
2280
    { 1321, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1321 = MUL_I16x8
2281
    { 1320, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1320 = MUL_F64x2_S
2282
    { 1319, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1319 = MUL_F64x2
2283
    { 1318, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1318 = MUL_F64_S
2284
    { 1317, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 155,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1317 = MUL_F64
2285
    { 1316, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1316 = MUL_F32x4_S
2286
    { 1315, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1315 = MUL_F32x4
2287
    { 1314, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1314 = MUL_F32_S
2288
    { 1313, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 149,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1313 = MUL_F32
2289
    { 1312, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1312 = MIN_U_I8x16_S
2290
    { 1311, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1311 = MIN_U_I8x16
2291
    { 1310, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1310 = MIN_U_I32x4_S
2292
    { 1309, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1309 = MIN_U_I32x4
2293
    { 1308, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1308 = MIN_U_I16x8_S
2294
    { 1307, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1307 = MIN_U_I16x8
2295
    { 1306, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1306 = MIN_S_I8x16_S
2296
    { 1305, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1305 = MIN_S_I8x16
2297
    { 1304, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1304 = MIN_S_I32x4_S
2298
    { 1303, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1303 = MIN_S_I32x4
2299
    { 1302, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1302 = MIN_S_I16x8_S
2300
    { 1301, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1301 = MIN_S_I16x8
2301
    { 1300, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1300 = MIN_F64x2_S
2302
    { 1299, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1299 = MIN_F64x2
2303
    { 1298, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1298 = MIN_F64_S
2304
    { 1297, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 155,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1297 = MIN_F64
2305
    { 1296, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1296 = MIN_F32x4_S
2306
    { 1295, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1295 = MIN_F32x4
2307
    { 1294, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1294 = MIN_F32_S
2308
    { 1293, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 149,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1293 = MIN_F32
2309
    { 1292, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1292 = MEMORY_ATOMIC_WAIT64_A64_S
2310
    { 1291, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 564,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1291 = MEMORY_ATOMIC_WAIT64_A64
2311
    { 1290, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1290 = MEMORY_ATOMIC_WAIT64_A32_S
2312
    { 1289, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 558,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1289 = MEMORY_ATOMIC_WAIT64_A32
2313
    { 1288, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1288 = MEMORY_ATOMIC_WAIT32_A64_S
2314
    { 1287, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 552,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1287 = MEMORY_ATOMIC_WAIT32_A64
2315
    { 1286, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1286 = MEMORY_ATOMIC_WAIT32_A32_S
2316
    { 1285, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 546,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1285 = MEMORY_ATOMIC_WAIT32_A32
2317
    { 1284, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1284 = MEMORY_ATOMIC_NOTIFY_A64_S
2318
    { 1283, 5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1283 = MEMORY_ATOMIC_NOTIFY_A64
2319
    { 1282, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1282 = MEMORY_ATOMIC_NOTIFY_A32_S
2320
    { 1281, 5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1281 = MEMORY_ATOMIC_NOTIFY_A32
2321
    { 1280, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1280 = MAX_U_I8x16_S
2322
    { 1279, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1279 = MAX_U_I8x16
2323
    { 1278, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1278 = MAX_U_I32x4_S
2324
    { 1277, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1277 = MAX_U_I32x4
2325
    { 1276, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1276 = MAX_U_I16x8_S
2326
    { 1275, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1275 = MAX_U_I16x8
2327
    { 1274, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1274 = MAX_S_I8x16_S
2328
    { 1273, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1273 = MAX_S_I8x16
2329
    { 1272, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1272 = MAX_S_I32x4_S
2330
    { 1271, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1271 = MAX_S_I32x4
2331
    { 1270, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1270 = MAX_S_I16x8_S
2332
    { 1269, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1269 = MAX_S_I16x8
2333
    { 1268, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1268 = MAX_F64x2_S
2334
    { 1267, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1267 = MAX_F64x2
2335
    { 1266, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1266 = MAX_F64_S
2336
    { 1265, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 155,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1265 = MAX_F64
2337
    { 1264, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1264 = MAX_F32x4_S
2338
    { 1263, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1263 = MAX_F32x4
2339
    { 1262, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1262 = MAX_F32_S
2340
    { 1261, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 149,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1261 = MAX_F32
2341
    { 1260, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1260 = MADD_F64x2_S
2342
    { 1259, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1259 = MADD_F64x2
2343
    { 1258, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1258 = MADD_F32x4_S
2344
    { 1257, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1257 = MADD_F32x4
2345
    { 1256, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1256 = LT_U_I8x16_S
2346
    { 1255, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1255 = LT_U_I8x16
2347
    { 1254, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1254 = LT_U_I64_S
2348
    { 1253, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1253 = LT_U_I64
2349
    { 1252, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1252 = LT_U_I32x4_S
2350
    { 1251, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1251 = LT_U_I32x4
2351
    { 1250, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1250 = LT_U_I32_S
2352
    { 1249, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1249 = LT_U_I32
2353
    { 1248, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1248 = LT_U_I16x8_S
2354
    { 1247, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1247 = LT_U_I16x8
2355
    { 1246, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1246 = LT_S_I8x16_S
2356
    { 1245, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1245 = LT_S_I8x16
2357
    { 1244, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1244 = LT_S_I64x2_S
2358
    { 1243, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1243 = LT_S_I64x2
2359
    { 1242, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1242 = LT_S_I64_S
2360
    { 1241, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1241 = LT_S_I64
2361
    { 1240, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1240 = LT_S_I32x4_S
2362
    { 1239, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1239 = LT_S_I32x4
2363
    { 1238, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1238 = LT_S_I32_S
2364
    { 1237, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1237 = LT_S_I32
2365
    { 1236, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1236 = LT_S_I16x8_S
2366
    { 1235, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1235 = LT_S_I16x8
2367
    { 1234, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1234 = LT_F64x2_S
2368
    { 1233, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1233 = LT_F64x2
2369
    { 1232, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1232 = LT_F64_S
2370
    { 1231, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 382,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1231 = LT_F64
2371
    { 1230, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1230 = LT_F32x4_S
2372
    { 1229, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1229 = LT_F32x4
2373
    { 1228, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1228 = LT_F32_S
2374
    { 1227, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 379,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1227 = LT_F32
2375
    { 1226, 1,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1226 = LOOP_S
2376
    { 1225, 1,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1225 = LOOP
2377
    { 1224, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1224 = LOCAL_TEE_V128_S
2378
    { 1223, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 543,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1223 = LOCAL_TEE_V128
2379
    { 1222, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1222 = LOCAL_TEE_I64_S
2380
    { 1221, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 540,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1221 = LOCAL_TEE_I64
2381
    { 1220, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1220 = LOCAL_TEE_I32_S
2382
    { 1219, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 537,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1219 = LOCAL_TEE_I32
2383
    { 1218, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1218 = LOCAL_TEE_FUNCREF_S
2384
    { 1217, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 534,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1217 = LOCAL_TEE_FUNCREF
2385
    { 1216, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1216 = LOCAL_TEE_F64_S
2386
    { 1215, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 531,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1215 = LOCAL_TEE_F64
2387
    { 1214, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1214 = LOCAL_TEE_F32_S
2388
    { 1213, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 528,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1213 = LOCAL_TEE_F32
2389
    { 1212, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1212 = LOCAL_TEE_EXTERNREF_S
2390
    { 1211, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 525,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1211 = LOCAL_TEE_EXTERNREF
2391
    { 1210, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1210 = LOCAL_SET_V128_S
2392
    { 1209, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 523,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1209 = LOCAL_SET_V128
2393
    { 1208, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1208 = LOCAL_SET_I64_S
2394
    { 1207, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 521,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1207 = LOCAL_SET_I64
2395
    { 1206, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1206 = LOCAL_SET_I32_S
2396
    { 1205, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 519,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1205 = LOCAL_SET_I32
2397
    { 1204, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1204 = LOCAL_SET_FUNCREF_S
2398
    { 1203, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 517,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1203 = LOCAL_SET_FUNCREF
2399
    { 1202, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1202 = LOCAL_SET_F64_S
2400
    { 1201, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 515,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1201 = LOCAL_SET_F64
2401
    { 1200, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1200 = LOCAL_SET_F32_S
2402
    { 1199, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 513,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1199 = LOCAL_SET_F32
2403
    { 1198, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1198 = LOCAL_SET_EXTERNREF_S
2404
    { 1197, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 511,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1197 = LOCAL_SET_EXTERNREF
2405
    { 1196, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1196 = LOCAL_GET_V128_S
2406
    { 1195, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 509,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1195 = LOCAL_GET_V128
2407
    { 1194, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1194 = LOCAL_GET_I64_S
2408
    { 1193, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 507,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1193 = LOCAL_GET_I64
2409
    { 1192, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1192 = LOCAL_GET_I32_S
2410
    { 1191, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 505,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1191 = LOCAL_GET_I32
2411
    { 1190, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1190 = LOCAL_GET_FUNCREF_S
2412
    { 1189, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 503,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1189 = LOCAL_GET_FUNCREF
2413
    { 1188, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1188 = LOCAL_GET_F64_S
2414
    { 1187, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 501,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1187 = LOCAL_GET_F64
2415
    { 1186, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1186 = LOCAL_GET_F32_S
2416
    { 1185, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 499,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1185 = LOCAL_GET_F32
2417
    { 1184, 1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 498,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1184 = LOCAL_GET_EXTERNREF_S
2418
    { 1183, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 496,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1183 = LOCAL_GET_EXTERNREF
2419
    { 1182, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1182 = LOAD_ZERO_I64x2_A64_S
2420
    { 1181, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1181 = LOAD_ZERO_I64x2_A64
2421
    { 1180, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1180 = LOAD_ZERO_I64x2_A32_S
2422
    { 1179, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1179 = LOAD_ZERO_I64x2_A32
2423
    { 1178, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1178 = LOAD_ZERO_I32x4_A64_S
2424
    { 1177, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1177 = LOAD_ZERO_I32x4_A64
2425
    { 1176, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1176 = LOAD_ZERO_I32x4_A32_S
2426
    { 1175, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1175 = LOAD_ZERO_I32x4_A32
2427
    { 1174, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1174 = LOAD_V128_A64_S
2428
    { 1173, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1173 = LOAD_V128_A64
2429
    { 1172, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1172 = LOAD_V128_A32_S
2430
    { 1171, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1171 = LOAD_V128_A32
2431
    { 1170, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 493,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1170 = LOAD_LANE_I8x16_A64_S
2432
    { 1169, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 487,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1169 = LOAD_LANE_I8x16_A64
2433
    { 1168, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 484,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1168 = LOAD_LANE_I8x16_A32_S
2434
    { 1167, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 478,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1167 = LOAD_LANE_I8x16_A32
2435
    { 1166, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 493,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1166 = LOAD_LANE_I64x2_A64_S
2436
    { 1165, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 487,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1165 = LOAD_LANE_I64x2_A64
2437
    { 1164, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 484,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1164 = LOAD_LANE_I64x2_A32_S
2438
    { 1163, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 478,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1163 = LOAD_LANE_I64x2_A32
2439
    { 1162, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 493,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1162 = LOAD_LANE_I32x4_A64_S
2440
    { 1161, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 487,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1161 = LOAD_LANE_I32x4_A64
2441
    { 1160, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 484,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1160 = LOAD_LANE_I32x4_A32_S
2442
    { 1159, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 478,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1159 = LOAD_LANE_I32x4_A32
2443
    { 1158, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 493,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1158 = LOAD_LANE_I16x8_A64_S
2444
    { 1157, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 487,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1157 = LOAD_LANE_I16x8_A64
2445
    { 1156, 3,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 484,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1156 = LOAD_LANE_I16x8_A32_S
2446
    { 1155, 6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 478,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1155 = LOAD_LANE_I16x8_A32
2447
    { 1154, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1154 = LOAD_I64_A64_S
2448
    { 1153, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1153 = LOAD_I64_A64
2449
    { 1152, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1152 = LOAD_I64_A32_S
2450
    { 1151, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1151 = LOAD_I64_A32
2451
    { 1150, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1150 = LOAD_I32_A64_S
2452
    { 1149, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 186,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1149 = LOAD_I32_A64
2453
    { 1148, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1148 = LOAD_I32_A32_S
2454
    { 1147, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 180,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1147 = LOAD_I32_A32
2455
    { 1146, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1146 = LOAD_F64_A64_S
2456
    { 1145, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 474,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1145 = LOAD_F64_A64
2457
    { 1144, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1144 = LOAD_F64_A32_S
2458
    { 1143, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 470,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1143 = LOAD_F64_A32
2459
    { 1142, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1142 = LOAD_F32_A64_S
2460
    { 1141, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 466,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1141 = LOAD_F32_A64
2461
    { 1140, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1140 = LOAD_F32_A32_S
2462
    { 1139, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 462,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1139 = LOAD_F32_A32
2463
    { 1138, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1138 = LOAD_EXTEND_U_I64x2_A64_S
2464
    { 1137, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1137 = LOAD_EXTEND_U_I64x2_A64
2465
    { 1136, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1136 = LOAD_EXTEND_U_I64x2_A32_S
2466
    { 1135, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1135 = LOAD_EXTEND_U_I64x2_A32
2467
    { 1134, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1134 = LOAD_EXTEND_U_I32x4_A64_S
2468
    { 1133, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1133 = LOAD_EXTEND_U_I32x4_A64
2469
    { 1132, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1132 = LOAD_EXTEND_U_I32x4_A32_S
2470
    { 1131, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1131 = LOAD_EXTEND_U_I32x4_A32
2471
    { 1130, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1130 = LOAD_EXTEND_U_I16x8_A64_S
2472
    { 1129, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1129 = LOAD_EXTEND_U_I16x8_A64
2473
    { 1128, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1128 = LOAD_EXTEND_U_I16x8_A32_S
2474
    { 1127, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1127 = LOAD_EXTEND_U_I16x8_A32
2475
    { 1126, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1126 = LOAD_EXTEND_S_I64x2_A64_S
2476
    { 1125, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1125 = LOAD_EXTEND_S_I64x2_A64
2477
    { 1124, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1124 = LOAD_EXTEND_S_I64x2_A32_S
2478
    { 1123, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1123 = LOAD_EXTEND_S_I64x2_A32
2479
    { 1122, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1122 = LOAD_EXTEND_S_I32x4_A64_S
2480
    { 1121, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1121 = LOAD_EXTEND_S_I32x4_A64
2481
    { 1120, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1120 = LOAD_EXTEND_S_I32x4_A32_S
2482
    { 1119, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1119 = LOAD_EXTEND_S_I32x4_A32
2483
    { 1118, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1118 = LOAD_EXTEND_S_I16x8_A64_S
2484
    { 1117, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1117 = LOAD_EXTEND_S_I16x8_A64
2485
    { 1116, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1116 = LOAD_EXTEND_S_I16x8_A32_S
2486
    { 1115, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1115 = LOAD_EXTEND_S_I16x8_A32
2487
    { 1114, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1114 = LOAD8_U_I64_A64_S
2488
    { 1113, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1113 = LOAD8_U_I64_A64
2489
    { 1112, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1112 = LOAD8_U_I64_A32_S
2490
    { 1111, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1111 = LOAD8_U_I64_A32
2491
    { 1110, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1110 = LOAD8_U_I32_A64_S
2492
    { 1109, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 186,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1109 = LOAD8_U_I32_A64
2493
    { 1108, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1108 = LOAD8_U_I32_A32_S
2494
    { 1107, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 180,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1107 = LOAD8_U_I32_A32
2495
    { 1106, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1106 = LOAD8_S_I64_A64_S
2496
    { 1105, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1105 = LOAD8_S_I64_A64
2497
    { 1104, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1104 = LOAD8_S_I64_A32_S
2498
    { 1103, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1103 = LOAD8_S_I64_A32
2499
    { 1102, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1102 = LOAD8_S_I32_A64_S
2500
    { 1101, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 186,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1101 = LOAD8_S_I32_A64
2501
    { 1100, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1100 = LOAD8_S_I32_A32_S
2502
    { 1099, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 180,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1099 = LOAD8_S_I32_A32
2503
    { 1098, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1098 = LOAD8_SPLAT_A64_S
2504
    { 1097, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1097 = LOAD8_SPLAT_A64
2505
    { 1096, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1096 = LOAD8_SPLAT_A32_S
2506
    { 1095, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1095 = LOAD8_SPLAT_A32
2507
    { 1094, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1094 = LOAD64_SPLAT_A64_S
2508
    { 1093, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1093 = LOAD64_SPLAT_A64
2509
    { 1092, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1092 = LOAD64_SPLAT_A32_S
2510
    { 1091, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1091 = LOAD64_SPLAT_A32
2511
    { 1090, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1090 = LOAD32_U_I64_A64_S
2512
    { 1089, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1089 = LOAD32_U_I64_A64
2513
    { 1088, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1088 = LOAD32_U_I64_A32_S
2514
    { 1087, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1087 = LOAD32_U_I64_A32
2515
    { 1086, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1086 = LOAD32_S_I64_A64_S
2516
    { 1085, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1085 = LOAD32_S_I64_A64
2517
    { 1084, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1084 = LOAD32_S_I64_A32_S
2518
    { 1083, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1083 = LOAD32_S_I64_A32
2519
    { 1082, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1082 = LOAD32_SPLAT_A64_S
2520
    { 1081, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1081 = LOAD32_SPLAT_A64
2521
    { 1080, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1080 = LOAD32_SPLAT_A32_S
2522
    { 1079, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1079 = LOAD32_SPLAT_A32
2523
    { 1078, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1078 = LOAD16_U_I64_A64_S
2524
    { 1077, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1077 = LOAD16_U_I64_A64
2525
    { 1076, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1076 = LOAD16_U_I64_A32_S
2526
    { 1075, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1075 = LOAD16_U_I64_A32
2527
    { 1074, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1074 = LOAD16_U_I32_A64_S
2528
    { 1073, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 186,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1073 = LOAD16_U_I32_A64
2529
    { 1072, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1072 = LOAD16_U_I32_A32_S
2530
    { 1071, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 180,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1071 = LOAD16_U_I32_A32
2531
    { 1070, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1070 = LOAD16_S_I64_A64_S
2532
    { 1069, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1069 = LOAD16_S_I64_A64
2533
    { 1068, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1068 = LOAD16_S_I64_A32_S
2534
    { 1067, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1067 = LOAD16_S_I64_A32
2535
    { 1066, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1066 = LOAD16_S_I32_A64_S
2536
    { 1065, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 186,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1065 = LOAD16_S_I32_A64
2537
    { 1064, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1064 = LOAD16_S_I32_A32_S
2538
    { 1063, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 180,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1063 = LOAD16_S_I32_A32
2539
    { 1062, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1062 = LOAD16_SPLAT_A64_S
2540
    { 1061, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 458,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1061 = LOAD16_SPLAT_A64
2541
    { 1060, 2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1060 = LOAD16_SPLAT_A32_S
2542
    { 1059, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 454,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1059 = LOAD16_SPLAT_A32
2543
    { 1058, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1058 = LE_U_I8x16_S
2544
    { 1057, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1057 = LE_U_I8x16
2545
    { 1056, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1056 = LE_U_I64_S
2546
    { 1055, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1055 = LE_U_I64
2547
    { 1054, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1054 = LE_U_I32x4_S
2548
    { 1053, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1053 = LE_U_I32x4
2549
    { 1052, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1052 = LE_U_I32_S
2550
    { 1051, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1051 = LE_U_I32
2551
    { 1050, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1050 = LE_U_I16x8_S
2552
    { 1049, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1049 = LE_U_I16x8
2553
    { 1048, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1048 = LE_S_I8x16_S
2554
    { 1047, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1047 = LE_S_I8x16
2555
    { 1046, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1046 = LE_S_I64x2_S
2556
    { 1045, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1045 = LE_S_I64x2
2557
    { 1044, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1044 = LE_S_I64_S
2558
    { 1043, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1043 = LE_S_I64
2559
    { 1042, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1042 = LE_S_I32x4_S
2560
    { 1041, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1041 = LE_S_I32x4
2561
    { 1040, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1040 = LE_S_I32_S
2562
    { 1039, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1039 = LE_S_I32
2563
    { 1038, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1038 = LE_S_I16x8_S
2564
    { 1037, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1037 = LE_S_I16x8
2565
    { 1036, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1036 = LE_F64x2_S
2566
    { 1035, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1035 = LE_F64x2
2567
    { 1034, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1034 = LE_F64_S
2568
    { 1033, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 382,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1033 = LE_F64
2569
    { 1032, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1032 = LE_F32x4_S
2570
    { 1031, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1031 = LE_F32x4
2571
    { 1030, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1030 = LE_F32_S
2572
    { 1029, 3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 379,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1029 = LE_F32
2573
    { 1028, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1028 = LANESELECT_I8x16_S
2574
    { 1027, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1027 = LANESELECT_I8x16
2575
    { 1026, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1026 = LANESELECT_I64x2_S
2576
    { 1025, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1025 = LANESELECT_I64x2
2577
    { 1024, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1024 = LANESELECT_I32x4_S
2578
    { 1023, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1023 = LANESELECT_I32x4
2579
    { 1022, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1022 = LANESELECT_I16x8_S
2580
    { 1021, 4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1021 = LANESELECT_I16x8
2581
    { 1020, 1,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1020 = IF_S
2582
    { 1019, 2,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 452,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1019 = IF
2583
    { 1018, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1018 = I64_TRUNC_U_SAT_F64_S
2584
    { 1017, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 419,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1017 = I64_TRUNC_U_SAT_F64
2585
    { 1016, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1016 = I64_TRUNC_U_SAT_F32_S
2586
    { 1015, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 417,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1015 = I64_TRUNC_U_SAT_F32
2587
    { 1014, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1014 = I64_TRUNC_U_F64_S
2588
    { 1013, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 419,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1013 = I64_TRUNC_U_F64
2589
    { 1012, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1012 = I64_TRUNC_U_F32_S
2590
    { 1011, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 417,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1011 = I64_TRUNC_U_F32
2591
    { 1010, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1010 = I64_TRUNC_S_SAT_F64_S
2592
    { 1009, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 419,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1009 = I64_TRUNC_S_SAT_F64
2593
    { 1008, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1008 = I64_TRUNC_S_SAT_F32_S
2594
    { 1007, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 417,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1007 = I64_TRUNC_S_SAT_F32
2595
    { 1006, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1006 = I64_TRUNC_S_F64_S
2596
    { 1005, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 419,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1005 = I64_TRUNC_S_F64
2597
    { 1004, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1004 = I64_TRUNC_S_F32_S
2598
    { 1003, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 417,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1003 = I64_TRUNC_S_F32
2599
    { 1002, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1002 = I64_REINTERPRET_F64_S
2600
    { 1001, 2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 419,  0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1001 = I64_REINTERPRET_F64
2601
    { 1000, 0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1000 = I64_EXTEND_U_I32_S
2602
    { 999,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 450,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #999 = I64_EXTEND_U_I32
2603
    { 998,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #998 = I64_EXTEND_S_I32_S
2604
    { 997,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 450,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #997 = I64_EXTEND_S_I32
2605
    { 996,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #996 = I64_EXTEND8_S_I64_S
2606
    { 995,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 276,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #995 = I64_EXTEND8_S_I64
2607
    { 994,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #994 = I64_EXTEND32_S_I64_S
2608
    { 993,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 276,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #993 = I64_EXTEND32_S_I64
2609
    { 992,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #992 = I64_EXTEND16_S_I64_S
2610
    { 991,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 276,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #991 = I64_EXTEND16_S_I64
2611
    { 990,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #990 = I32_WRAP_I64_S
2612
    { 989,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 377,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #989 = I32_WRAP_I64
2613
    { 988,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #988 = I32_TRUNC_U_SAT_F64_S
2614
    { 987,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 415,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #987 = I32_TRUNC_U_SAT_F64
2615
    { 986,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #986 = I32_TRUNC_U_SAT_F32_S
2616
    { 985,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 413,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #985 = I32_TRUNC_U_SAT_F32
2617
    { 984,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #984 = I32_TRUNC_U_F64_S
2618
    { 983,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 415,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #983 = I32_TRUNC_U_F64
2619
    { 982,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #982 = I32_TRUNC_U_F32_S
2620
    { 981,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 413,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #981 = I32_TRUNC_U_F32
2621
    { 980,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #980 = I32_TRUNC_S_SAT_F64_S
2622
    { 979,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 415,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #979 = I32_TRUNC_S_SAT_F64
2623
    { 978,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #978 = I32_TRUNC_S_SAT_F32_S
2624
    { 977,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 413,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #977 = I32_TRUNC_S_SAT_F32
2625
    { 976,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #976 = I32_TRUNC_S_F64_S
2626
    { 975,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 415,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #975 = I32_TRUNC_S_F64
2627
    { 974,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #974 = I32_TRUNC_S_F32_S
2628
    { 973,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 413,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #973 = I32_TRUNC_S_F32
2629
    { 972,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #972 = I32_REINTERPRET_F32_S
2630
    { 971,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 413,  0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #971 = I32_REINTERPRET_F32
2631
    { 970,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #970 = I32_EXTEND8_S_I32_S
2632
    { 969,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 274,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #969 = I32_EXTEND8_S_I32
2633
    { 968,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #968 = I32_EXTEND16_S_I32_S
2634
    { 967,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 274,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #967 = I32_EXTEND16_S_I32
2635
    { 966,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #966 = GT_U_I8x16_S
2636
    { 965,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #965 = GT_U_I8x16
2637
    { 964,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #964 = GT_U_I64_S
2638
    { 963,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #963 = GT_U_I64
2639
    { 962,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #962 = GT_U_I32x4_S
2640
    { 961,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #961 = GT_U_I32x4
2641
    { 960,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #960 = GT_U_I32_S
2642
    { 959,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #959 = GT_U_I32
2643
    { 958,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #958 = GT_U_I16x8_S
2644
    { 957,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #957 = GT_U_I16x8
2645
    { 956,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #956 = GT_S_I8x16_S
2646
    { 955,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #955 = GT_S_I8x16
2647
    { 954,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #954 = GT_S_I64x2_S
2648
    { 953,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #953 = GT_S_I64x2
2649
    { 952,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #952 = GT_S_I64_S
2650
    { 951,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #951 = GT_S_I64
2651
    { 950,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #950 = GT_S_I32x4_S
2652
    { 949,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #949 = GT_S_I32x4
2653
    { 948,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #948 = GT_S_I32_S
2654
    { 947,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #947 = GT_S_I32
2655
    { 946,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #946 = GT_S_I16x8_S
2656
    { 945,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #945 = GT_S_I16x8
2657
    { 944,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #944 = GT_F64x2_S
2658
    { 943,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #943 = GT_F64x2
2659
    { 942,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #942 = GT_F64_S
2660
    { 941,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 382,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #941 = GT_F64
2661
    { 940,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #940 = GT_F32x4_S
2662
    { 939,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #939 = GT_F32x4
2663
    { 938,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #938 = GT_F32_S
2664
    { 937,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 379,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #937 = GT_F32
2665
    { 936,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #936 = GLOBAL_SET_V128_S
2666
    { 935,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 448,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #935 = GLOBAL_SET_V128
2667
    { 934,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #934 = GLOBAL_SET_I64_S
2668
    { 933,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 446,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #933 = GLOBAL_SET_I64
2669
    { 932,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #932 = GLOBAL_SET_I32_S
2670
    { 931,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 444,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #931 = GLOBAL_SET_I32
2671
    { 930,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #930 = GLOBAL_SET_FUNCREF_S
2672
    { 929,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 442,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #929 = GLOBAL_SET_FUNCREF
2673
    { 928,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #928 = GLOBAL_SET_F64_S
2674
    { 927,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 440,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #927 = GLOBAL_SET_F64
2675
    { 926,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #926 = GLOBAL_SET_F32_S
2676
    { 925,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 438,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #925 = GLOBAL_SET_F32
2677
    { 924,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #924 = GLOBAL_SET_EXTERNREF_S
2678
    { 923,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 436,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #923 = GLOBAL_SET_EXTERNREF
2679
    { 922,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #922 = GLOBAL_GET_V128_S
2680
    { 921,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 434,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #921 = GLOBAL_GET_V128
2681
    { 920,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #920 = GLOBAL_GET_I64_S
2682
    { 919,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 432,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #919 = GLOBAL_GET_I64
2683
    { 918,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #918 = GLOBAL_GET_I32_S
2684
    { 917,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 430,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #917 = GLOBAL_GET_I32
2685
    { 916,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #916 = GLOBAL_GET_FUNCREF_S
2686
    { 915,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 428,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #915 = GLOBAL_GET_FUNCREF
2687
    { 914,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #914 = GLOBAL_GET_F64_S
2688
    { 913,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 426,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #913 = GLOBAL_GET_F64
2689
    { 912,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #912 = GLOBAL_GET_F32_S
2690
    { 911,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 424,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #911 = GLOBAL_GET_F32
2691
    { 910,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 423,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #910 = GLOBAL_GET_EXTERNREF_S
2692
    { 909,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 421,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #909 = GLOBAL_GET_EXTERNREF
2693
    { 908,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #908 = GE_U_I8x16_S
2694
    { 907,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #907 = GE_U_I8x16
2695
    { 906,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #906 = GE_U_I64_S
2696
    { 905,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #905 = GE_U_I64
2697
    { 904,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #904 = GE_U_I32x4_S
2698
    { 903,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #903 = GE_U_I32x4
2699
    { 902,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #902 = GE_U_I32_S
2700
    { 901,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #901 = GE_U_I32
2701
    { 900,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #900 = GE_U_I16x8_S
2702
    { 899,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #899 = GE_U_I16x8
2703
    { 898,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #898 = GE_S_I8x16_S
2704
    { 897,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #897 = GE_S_I8x16
2705
    { 896,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #896 = GE_S_I64x2_S
2706
    { 895,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #895 = GE_S_I64x2
2707
    { 894,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #894 = GE_S_I64_S
2708
    { 893,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #893 = GE_S_I64
2709
    { 892,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #892 = GE_S_I32x4_S
2710
    { 891,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #891 = GE_S_I32x4
2711
    { 890,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #890 = GE_S_I32_S
2712
    { 889,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #889 = GE_S_I32
2713
    { 888,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #888 = GE_S_I16x8_S
2714
    { 887,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #887 = GE_S_I16x8
2715
    { 886,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #886 = GE_F64x2_S
2716
    { 885,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #885 = GE_F64x2
2717
    { 884,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #884 = GE_F64_S
2718
    { 883,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 382,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #883 = GE_F64
2719
    { 882,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #882 = GE_F32x4_S
2720
    { 881,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #881 = GE_F32x4
2721
    { 880,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #880 = GE_F32_S
2722
    { 879,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 379,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #879 = GE_F32
2723
    { 878,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #878 = FP_TO_UINT_I64_F64_S
2724
    { 877,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 419,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #877 = FP_TO_UINT_I64_F64
2725
    { 876,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #876 = FP_TO_UINT_I64_F32_S
2726
    { 875,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 417,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #875 = FP_TO_UINT_I64_F32
2727
    { 874,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #874 = FP_TO_UINT_I32_F64_S
2728
    { 873,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 415,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #873 = FP_TO_UINT_I32_F64
2729
    { 872,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #872 = FP_TO_UINT_I32_F32_S
2730
    { 871,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 413,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #871 = FP_TO_UINT_I32_F32
2731
    { 870,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #870 = FP_TO_SINT_I64_F64_S
2732
    { 869,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 419,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #869 = FP_TO_SINT_I64_F64
2733
    { 868,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #868 = FP_TO_SINT_I64_F32_S
2734
    { 867,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 417,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #867 = FP_TO_SINT_I64_F32
2735
    { 866,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #866 = FP_TO_SINT_I32_F64_S
2736
    { 865,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 415,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #865 = FP_TO_SINT_I32_F64
2737
    { 864,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #864 = FP_TO_SINT_I32_F32_S
2738
    { 863,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 413,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #863 = FP_TO_SINT_I32_F32
2739
    { 862,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #862 = FLOOR_F64x2_S
2740
    { 861,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #861 = FLOOR_F64x2
2741
    { 860,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #860 = FLOOR_F64_S
2742
    { 859,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 147,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #859 = FLOOR_F64
2743
    { 858,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #858 = FLOOR_F32x4_S
2744
    { 857,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #857 = FLOOR_F32x4
2745
    { 856,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #856 = FLOOR_F32_S
2746
    { 855,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #855 = FLOOR_F32
2747
    { 854,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #854 = FALLTHROUGH_RETURN_S
2748
    { 853,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #853 = FALLTHROUGH_RETURN
2749
    { 852,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #852 = F64_REINTERPRET_I64_S
2750
    { 851,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 409,  0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #851 = F64_REINTERPRET_I64
2751
    { 850,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #850 = F64_PROMOTE_F32_S
2752
    { 849,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 411,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #849 = F64_PROMOTE_F32
2753
    { 848,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #848 = F64_CONVERT_U_I64_S
2754
    { 847,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 409,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #847 = F64_CONVERT_U_I64
2755
    { 846,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #846 = F64_CONVERT_U_I32_S
2756
    { 845,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 407,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #845 = F64_CONVERT_U_I32
2757
    { 844,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #844 = F64_CONVERT_S_I64_S
2758
    { 843,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 409,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #843 = F64_CONVERT_S_I64
2759
    { 842,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #842 = F64_CONVERT_S_I32_S
2760
    { 841,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 407,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #841 = F64_CONVERT_S_I32
2761
    { 840,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #840 = F32_REINTERPRET_I32_S
2762
    { 839,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 401,  0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #839 = F32_REINTERPRET_I32
2763
    { 838,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #838 = F32_DEMOTE_F64_S
2764
    { 837,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 405,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #837 = F32_DEMOTE_F64
2765
    { 836,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #836 = F32_CONVERT_U_I64_S
2766
    { 835,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 403,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #835 = F32_CONVERT_U_I64
2767
    { 834,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #834 = F32_CONVERT_U_I32_S
2768
    { 833,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 401,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #833 = F32_CONVERT_U_I32
2769
    { 832,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #832 = F32_CONVERT_S_I64_S
2770
    { 831,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 403,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #831 = F32_CONVERT_S_I64
2771
    { 830,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #830 = F32_CONVERT_S_I32_S
2772
    { 829,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 401,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #829 = F32_CONVERT_S_I32
2773
    { 828,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #828 = EXTRACT_LANE_I8x16_u_S
2774
    { 827,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 395,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #827 = EXTRACT_LANE_I8x16_u
2775
    { 826,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #826 = EXTRACT_LANE_I8x16_s_S
2776
    { 825,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 395,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #825 = EXTRACT_LANE_I8x16_s
2777
    { 824,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #824 = EXTRACT_LANE_I64x2_S
2778
    { 823,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 398,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #823 = EXTRACT_LANE_I64x2
2779
    { 822,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #822 = EXTRACT_LANE_I32x4_S
2780
    { 821,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 395,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #821 = EXTRACT_LANE_I32x4
2781
    { 820,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #820 = EXTRACT_LANE_I16x8_u_S
2782
    { 819,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 395,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #819 = EXTRACT_LANE_I16x8_u
2783
    { 818,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #818 = EXTRACT_LANE_I16x8_s_S
2784
    { 817,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 395,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #817 = EXTRACT_LANE_I16x8_s
2785
    { 816,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #816 = EXTRACT_LANE_F64x2_S
2786
    { 815,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 392,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #815 = EXTRACT_LANE_F64x2
2787
    { 814,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 391,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #814 = EXTRACT_LANE_F32x4_S
2788
    { 813,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 388,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #813 = EXTRACT_LANE_F32x4
2789
    { 812,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #812 = EXTMUL_LOW_U_I64x2_S
2790
    { 811,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #811 = EXTMUL_LOW_U_I64x2
2791
    { 810,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #810 = EXTMUL_LOW_U_I32x4_S
2792
    { 809,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #809 = EXTMUL_LOW_U_I32x4
2793
    { 808,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #808 = EXTMUL_LOW_U_I16x8_S
2794
    { 807,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #807 = EXTMUL_LOW_U_I16x8
2795
    { 806,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #806 = EXTMUL_LOW_S_I64x2_S
2796
    { 805,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #805 = EXTMUL_LOW_S_I64x2
2797
    { 804,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #804 = EXTMUL_LOW_S_I32x4_S
2798
    { 803,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #803 = EXTMUL_LOW_S_I32x4
2799
    { 802,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #802 = EXTMUL_LOW_S_I16x8_S
2800
    { 801,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #801 = EXTMUL_LOW_S_I16x8
2801
    { 800,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #800 = EXTMUL_HIGH_U_I64x2_S
2802
    { 799,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #799 = EXTMUL_HIGH_U_I64x2
2803
    { 798,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #798 = EXTMUL_HIGH_U_I32x4_S
2804
    { 797,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #797 = EXTMUL_HIGH_U_I32x4
2805
    { 796,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #796 = EXTMUL_HIGH_U_I16x8_S
2806
    { 795,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #795 = EXTMUL_HIGH_U_I16x8
2807
    { 794,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #794 = EXTMUL_HIGH_S_I64x2_S
2808
    { 793,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #793 = EXTMUL_HIGH_S_I64x2
2809
    { 792,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #792 = EXTMUL_HIGH_S_I32x4_S
2810
    { 791,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #791 = EXTMUL_HIGH_S_I32x4
2811
    { 790,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #790 = EXTMUL_HIGH_S_I16x8_S
2812
    { 789,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #789 = EXTMUL_HIGH_S_I16x8
2813
    { 788,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #788 = EQ_I8x16_S
2814
    { 787,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #787 = EQ_I8x16
2815
    { 786,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #786 = EQ_I64x2_S
2816
    { 785,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #785 = EQ_I64x2
2817
    { 784,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #784 = EQ_I64_S
2818
    { 783,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 385,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #783 = EQ_I64
2819
    { 782,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #782 = EQ_I32x4_S
2820
    { 781,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #781 = EQ_I32x4
2821
    { 780,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #780 = EQ_I32_S
2822
    { 779,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #779 = EQ_I32
2823
    { 778,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #778 = EQ_I16x8_S
2824
    { 777,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #777 = EQ_I16x8
2825
    { 776,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #776 = EQ_F64x2_S
2826
    { 775,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #775 = EQ_F64x2
2827
    { 774,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #774 = EQ_F64_S
2828
    { 773,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 382,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #773 = EQ_F64
2829
    { 772,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #772 = EQ_F32x4_S
2830
    { 771,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #771 = EQ_F32x4
2831
    { 770,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #770 = EQ_F32_S
2832
    { 769,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 379,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #769 = EQ_F32
2833
    { 768,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #768 = EQZ_I64_S
2834
    { 767,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 377,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #767 = EQZ_I64
2835
    { 766,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #766 = EQZ_I32_S
2836
    { 765,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 274,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #765 = EQZ_I32
2837
    { 764,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #764 = END_TRY_S
2838
    { 763,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #763 = END_TRY
2839
    { 762,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #762 = END_S
2840
    { 761,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #761 = END_LOOP_S
2841
    { 760,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #760 = END_LOOP
2842
    { 759,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #759 = END_IF_S
2843
    { 758,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #758 = END_IF
2844
    { 757,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #757 = END_FUNCTION_S
2845
    { 756,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #756 = END_FUNCTION
2846
    { 755,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #755 = END_BLOCK_S
2847
    { 754,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #754 = END_BLOCK
2848
    { 753,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #753 = END
2849
    { 752,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #752 = ELSE_S
2850
    { 751,  0,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #751 = ELSE
2851
    { 750,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #750 = DROP_V128_S
2852
    { 749,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 376,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #749 = DROP_V128
2853
    { 748,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #748 = DROP_I64_S
2854
    { 747,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 270,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #747 = DROP_I64
2855
    { 746,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #746 = DROP_I32_S
2856
    { 745,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 268,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #745 = DROP_I32
2857
    { 744,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #744 = DROP_FUNCREF_S
2858
    { 743,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 375,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #743 = DROP_FUNCREF
2859
    { 742,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #742 = DROP_F64_S
2860
    { 741,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 374,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #741 = DROP_F64
2861
    { 740,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #740 = DROP_F32_S
2862
    { 739,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 373,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #739 = DROP_F32
2863
    { 738,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #738 = DROP_EXTERNREF_S
2864
    { 737,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 372,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #737 = DROP_EXTERNREF
2865
    { 736,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #736 = DOT_S
2866
    { 735,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #735 = DOT
2867
    { 734,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #734 = DIV_U_I64_S
2868
    { 733,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #733 = DIV_U_I64
2869
    { 732,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #732 = DIV_U_I32_S
2870
    { 731,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #731 = DIV_U_I32
2871
    { 730,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #730 = DIV_S_I64_S
2872
    { 729,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #729 = DIV_S_I64
2873
    { 728,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #728 = DIV_S_I32_S
2874
    { 727,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #727 = DIV_S_I32
2875
    { 726,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #726 = DIV_F64x2_S
2876
    { 725,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #725 = DIV_F64x2
2877
    { 724,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #724 = DIV_F64_S
2878
    { 723,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 155,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #723 = DIV_F64
2879
    { 722,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #722 = DIV_F32x4_S
2880
    { 721,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #721 = DIV_F32x4
2881
    { 720,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #720 = DIV_F32_S
2882
    { 719,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 149,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #719 = DIV_F32
2883
    { 718,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 265,  0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #718 = DELEGATE_S
2884
    { 717,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 265,  0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #717 = DELEGATE
2885
    { 716,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #716 = DEBUG_UNREACHABLE_S
2886
    { 715,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #715 = DEBUG_UNREACHABLE
2887
    { 714,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #714 = CTZ_I64_S
2888
    { 713,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 276,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #713 = CTZ_I64
2889
    { 712,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #712 = CTZ_I32_S
2890
    { 711,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 274,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #711 = CTZ_I32
2891
    { 710,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #710 = COPY_V128_S
2892
    { 709,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #709 = COPY_V128
2893
    { 708,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #708 = COPY_I64_S
2894
    { 707,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 276,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #707 = COPY_I64
2895
    { 706,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #706 = COPY_I32_S
2896
    { 705,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 274,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #705 = COPY_I32
2897
    { 704,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #704 = COPY_FUNCREF_S
2898
    { 703,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 370,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #703 = COPY_FUNCREF
2899
    { 702,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #702 = COPY_F64_S
2900
    { 701,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 147,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #701 = COPY_F64
2901
    { 700,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #700 = COPY_F32_S
2902
    { 699,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 143,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #699 = COPY_F32
2903
    { 698,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #698 = COPY_EXTERNREF_S
2904
    { 697,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 368,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #697 = COPY_EXTERNREF
2905
    { 696,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #696 = COPYSIGN_F64_S
2906
    { 695,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 155,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #695 = COPYSIGN_F64
2907
    { 694,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #694 = COPYSIGN_F32_S
2908
    { 693,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 149,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #693 = COPYSIGN_F32
2909
    { 692,  16, 0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 352,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #692 = CONST_V128_I8x16_S
2910
    { 691,  17, 1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 335,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #691 = CONST_V128_I8x16
2911
    { 690,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 333,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #690 = CONST_V128_I64x2_S
2912
    { 689,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 330,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #689 = CONST_V128_I64x2
2913
    { 688,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 326,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #688 = CONST_V128_I32x4_S
2914
    { 687,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 321,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #687 = CONST_V128_I32x4
2915
    { 686,  8,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 313,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #686 = CONST_V128_I16x8_S
2916
    { 685,  9,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 304,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #685 = CONST_V128_I16x8
2917
    { 684,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 302,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #684 = CONST_V128_F64x2_S
2918
    { 683,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 299,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #683 = CONST_V128_F64x2
2919
    { 682,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 295,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #682 = CONST_V128_F32x4_S
2920
    { 681,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 290,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #681 = CONST_V128_F32x4
2921
    { 680,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 289,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #680 = CONST_I64_S
2922
    { 679,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 287,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #679 = CONST_I64
2923
    { 678,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 286,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #678 = CONST_I32_S
2924
    { 677,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 284,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #677 = CONST_I32
2925
    { 676,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 283,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #676 = CONST_F64_S
2926
    { 675,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 281,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #675 = CONST_F64
2927
    { 674,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 280,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #674 = CONST_F32_S
2928
    { 673,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 278,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #673 = CONST_F32
2929
    { 672,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #672 = CLZ_I64_S
2930
    { 671,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 276,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #671 = CLZ_I64
2931
    { 670,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #670 = CLZ_I32_S
2932
    { 669,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 274,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #669 = CLZ_I32
2933
    { 668,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #668 = CEIL_F64x2_S
2934
    { 667,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #667 = CEIL_F64x2
2935
    { 666,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #666 = CEIL_F64_S
2936
    { 665,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 147,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #665 = CEIL_F64
2937
    { 664,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #664 = CEIL_F32x4_S
2938
    { 663,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #663 = CEIL_F32x4
2939
    { 662,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #662 = CEIL_F32_S
2940
    { 661,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #661 = CEIL_F32
2941
    { 660,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 273,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #660 = CATCH_S
2942
    { 659,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #659 = CATCH_ALL_S
2943
    { 658,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #658 = CATCH_ALL
2944
    { 657,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 273,  0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #657 = CATCH
2945
    { 656,  1,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 140,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #656 = CALL_S
2946
    { 655,  2,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 271,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #655 = CALL_INDIRECT_S
2947
    { 654,  2,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 271,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #654 = CALL_INDIRECT
2948
    { 653,  1,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 140,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #653 = CALL
2949
    { 652,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 265,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #652 = BR_UNLESS_S
2950
    { 651,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 266,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #651 = BR_UNLESS
2951
    { 650,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 269,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #650 = BR_TABLE_I64_S
2952
    { 649,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 270,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #649 = BR_TABLE_I64
2953
    { 648,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 269,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #648 = BR_TABLE_I32_S
2954
    { 647,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 268,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #647 = BR_TABLE_I32
2955
    { 646,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 265,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #646 = BR_S
2956
    { 645,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 265,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #645 = BR_IF_S
2957
    { 644,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 266,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #644 = BR_IF
2958
    { 643,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 265,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #643 = BR
2959
    { 642,  1,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #642 = BLOCK_S
2960
    { 641,  1,  0,  0,  0,  1,  1,  WebAssemblyImpOpBase + 8, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #641 = BLOCK
2961
    { 640,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #640 = BITSELECT_S
2962
    { 639,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #639 = BITSELECT
2963
    { 638,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #638 = BITMASK_I8x16_S
2964
    { 637,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #637 = BITMASK_I8x16
2965
    { 636,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #636 = BITMASK_I64x2_S
2966
    { 635,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #635 = BITMASK_I64x2
2967
    { 634,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #634 = BITMASK_I32x4_S
2968
    { 633,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #633 = BITMASK_I32x4
2969
    { 632,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #632 = BITMASK_I16x8_S
2970
    { 631,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #631 = BITMASK_I16x8
2971
    { 630,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #630 = AVGR_U_I8x16_S
2972
    { 629,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #629 = AVGR_U_I8x16
2973
    { 628,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #628 = AVGR_U_I16x8_S
2974
    { 627,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #627 = AVGR_U_I16x8
2975
    { 626,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #626 = ATOMIC_STORE_I64_A64_S
2976
    { 625,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 256,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #625 = ATOMIC_STORE_I64_A64
2977
    { 624,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #624 = ATOMIC_STORE_I64_A32_S
2978
    { 623,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 252,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #623 = ATOMIC_STORE_I64_A32
2979
    { 622,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #622 = ATOMIC_STORE_I32_A64_S
2980
    { 621,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 248,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #621 = ATOMIC_STORE_I32_A64
2981
    { 620,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #620 = ATOMIC_STORE_I32_A32_S
2982
    { 619,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #619 = ATOMIC_STORE_I32_A32
2983
    { 618,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #618 = ATOMIC_STORE8_I64_A64_S
2984
    { 617,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 256,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #617 = ATOMIC_STORE8_I64_A64
2985
    { 616,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #616 = ATOMIC_STORE8_I64_A32_S
2986
    { 615,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 252,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #615 = ATOMIC_STORE8_I64_A32
2987
    { 614,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #614 = ATOMIC_STORE8_I32_A64_S
2988
    { 613,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 248,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #613 = ATOMIC_STORE8_I32_A64
2989
    { 612,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #612 = ATOMIC_STORE8_I32_A32_S
2990
    { 611,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #611 = ATOMIC_STORE8_I32_A32
2991
    { 610,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #610 = ATOMIC_STORE32_I64_A64_S
2992
    { 609,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 256,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #609 = ATOMIC_STORE32_I64_A64
2993
    { 608,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #608 = ATOMIC_STORE32_I64_A32_S
2994
    { 607,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 252,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #607 = ATOMIC_STORE32_I64_A32
2995
    { 606,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #606 = ATOMIC_STORE16_I64_A64_S
2996
    { 605,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 256,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #605 = ATOMIC_STORE16_I64_A64
2997
    { 604,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #604 = ATOMIC_STORE16_I64_A32_S
2998
    { 603,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 252,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #603 = ATOMIC_STORE16_I64_A32
2999
    { 602,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #602 = ATOMIC_STORE16_I32_A64_S
3000
    { 601,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 248,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #601 = ATOMIC_STORE16_I32_A64
3001
    { 600,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #600 = ATOMIC_STORE16_I32_A32_S
3002
    { 599,  4,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #599 = ATOMIC_STORE16_I32_A32
3003
    { 598,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #598 = ATOMIC_RMW_XOR_I64_A64_S
3004
    { 597,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #597 = ATOMIC_RMW_XOR_I64_A64
3005
    { 596,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #596 = ATOMIC_RMW_XOR_I64_A32_S
3006
    { 595,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #595 = ATOMIC_RMW_XOR_I64_A32
3007
    { 594,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #594 = ATOMIC_RMW_XOR_I32_A64_S
3008
    { 593,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #593 = ATOMIC_RMW_XOR_I32_A64
3009
    { 592,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #592 = ATOMIC_RMW_XOR_I32_A32_S
3010
    { 591,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #591 = ATOMIC_RMW_XOR_I32_A32
3011
    { 590,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #590 = ATOMIC_RMW_XCHG_I64_A64_S
3012
    { 589,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #589 = ATOMIC_RMW_XCHG_I64_A64
3013
    { 588,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #588 = ATOMIC_RMW_XCHG_I64_A32_S
3014
    { 587,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #587 = ATOMIC_RMW_XCHG_I64_A32
3015
    { 586,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #586 = ATOMIC_RMW_XCHG_I32_A64_S
3016
    { 585,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #585 = ATOMIC_RMW_XCHG_I32_A64
3017
    { 584,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #584 = ATOMIC_RMW_XCHG_I32_A32_S
3018
    { 583,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #583 = ATOMIC_RMW_XCHG_I32_A32
3019
    { 582,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #582 = ATOMIC_RMW_SUB_I64_A64_S
3020
    { 581,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #581 = ATOMIC_RMW_SUB_I64_A64
3021
    { 580,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #580 = ATOMIC_RMW_SUB_I64_A32_S
3022
    { 579,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #579 = ATOMIC_RMW_SUB_I64_A32
3023
    { 578,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #578 = ATOMIC_RMW_SUB_I32_A64_S
3024
    { 577,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #577 = ATOMIC_RMW_SUB_I32_A64
3025
    { 576,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #576 = ATOMIC_RMW_SUB_I32_A32_S
3026
    { 575,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #575 = ATOMIC_RMW_SUB_I32_A32
3027
    { 574,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #574 = ATOMIC_RMW_OR_I64_A64_S
3028
    { 573,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #573 = ATOMIC_RMW_OR_I64_A64
3029
    { 572,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #572 = ATOMIC_RMW_OR_I64_A32_S
3030
    { 571,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #571 = ATOMIC_RMW_OR_I64_A32
3031
    { 570,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #570 = ATOMIC_RMW_OR_I32_A64_S
3032
    { 569,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #569 = ATOMIC_RMW_OR_I32_A64
3033
    { 568,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #568 = ATOMIC_RMW_OR_I32_A32_S
3034
    { 567,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #567 = ATOMIC_RMW_OR_I32_A32
3035
    { 566,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #566 = ATOMIC_RMW_CMPXCHG_I64_A64_S
3036
    { 565,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 238,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #565 = ATOMIC_RMW_CMPXCHG_I64_A64
3037
    { 564,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #564 = ATOMIC_RMW_CMPXCHG_I64_A32_S
3038
    { 563,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 232,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #563 = ATOMIC_RMW_CMPXCHG_I64_A32
3039
    { 562,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #562 = ATOMIC_RMW_CMPXCHG_I32_A64_S
3040
    { 561,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 226,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #561 = ATOMIC_RMW_CMPXCHG_I32_A64
3041
    { 560,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #560 = ATOMIC_RMW_CMPXCHG_I32_A32_S
3042
    { 559,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 220,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #559 = ATOMIC_RMW_CMPXCHG_I32_A32
3043
    { 558,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #558 = ATOMIC_RMW_AND_I64_A64_S
3044
    { 557,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #557 = ATOMIC_RMW_AND_I64_A64
3045
    { 556,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #556 = ATOMIC_RMW_AND_I64_A32_S
3046
    { 555,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #555 = ATOMIC_RMW_AND_I64_A32
3047
    { 554,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #554 = ATOMIC_RMW_AND_I32_A64_S
3048
    { 553,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #553 = ATOMIC_RMW_AND_I32_A64
3049
    { 552,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #552 = ATOMIC_RMW_AND_I32_A32_S
3050
    { 551,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #551 = ATOMIC_RMW_AND_I32_A32
3051
    { 550,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #550 = ATOMIC_RMW_ADD_I64_A64_S
3052
    { 549,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #549 = ATOMIC_RMW_ADD_I64_A64
3053
    { 548,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #548 = ATOMIC_RMW_ADD_I64_A32_S
3054
    { 547,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #547 = ATOMIC_RMW_ADD_I64_A32
3055
    { 546,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #546 = ATOMIC_RMW_ADD_I32_A64_S
3056
    { 545,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #545 = ATOMIC_RMW_ADD_I32_A64
3057
    { 544,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #544 = ATOMIC_RMW_ADD_I32_A32_S
3058
    { 543,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #543 = ATOMIC_RMW_ADD_I32_A32
3059
    { 542,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #542 = ATOMIC_RMW8_U_XOR_I64_A64_S
3060
    { 541,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #541 = ATOMIC_RMW8_U_XOR_I64_A64
3061
    { 540,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #540 = ATOMIC_RMW8_U_XOR_I64_A32_S
3062
    { 539,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #539 = ATOMIC_RMW8_U_XOR_I64_A32
3063
    { 538,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #538 = ATOMIC_RMW8_U_XOR_I32_A64_S
3064
    { 537,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #537 = ATOMIC_RMW8_U_XOR_I32_A64
3065
    { 536,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #536 = ATOMIC_RMW8_U_XOR_I32_A32_S
3066
    { 535,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #535 = ATOMIC_RMW8_U_XOR_I32_A32
3067
    { 534,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #534 = ATOMIC_RMW8_U_XCHG_I64_A64_S
3068
    { 533,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #533 = ATOMIC_RMW8_U_XCHG_I64_A64
3069
    { 532,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #532 = ATOMIC_RMW8_U_XCHG_I64_A32_S
3070
    { 531,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #531 = ATOMIC_RMW8_U_XCHG_I64_A32
3071
    { 530,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #530 = ATOMIC_RMW8_U_XCHG_I32_A64_S
3072
    { 529,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #529 = ATOMIC_RMW8_U_XCHG_I32_A64
3073
    { 528,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #528 = ATOMIC_RMW8_U_XCHG_I32_A32_S
3074
    { 527,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #527 = ATOMIC_RMW8_U_XCHG_I32_A32
3075
    { 526,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #526 = ATOMIC_RMW8_U_SUB_I64_A64_S
3076
    { 525,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #525 = ATOMIC_RMW8_U_SUB_I64_A64
3077
    { 524,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #524 = ATOMIC_RMW8_U_SUB_I64_A32_S
3078
    { 523,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #523 = ATOMIC_RMW8_U_SUB_I64_A32
3079
    { 522,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #522 = ATOMIC_RMW8_U_SUB_I32_A64_S
3080
    { 521,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #521 = ATOMIC_RMW8_U_SUB_I32_A64
3081
    { 520,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #520 = ATOMIC_RMW8_U_SUB_I32_A32_S
3082
    { 519,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #519 = ATOMIC_RMW8_U_SUB_I32_A32
3083
    { 518,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #518 = ATOMIC_RMW8_U_OR_I64_A64_S
3084
    { 517,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #517 = ATOMIC_RMW8_U_OR_I64_A64
3085
    { 516,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #516 = ATOMIC_RMW8_U_OR_I64_A32_S
3086
    { 515,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #515 = ATOMIC_RMW8_U_OR_I64_A32
3087
    { 514,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #514 = ATOMIC_RMW8_U_OR_I32_A64_S
3088
    { 513,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #513 = ATOMIC_RMW8_U_OR_I32_A64
3089
    { 512,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #512 = ATOMIC_RMW8_U_OR_I32_A32_S
3090
    { 511,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #511 = ATOMIC_RMW8_U_OR_I32_A32
3091
    { 510,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #510 = ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
3092
    { 509,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 238,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #509 = ATOMIC_RMW8_U_CMPXCHG_I64_A64
3093
    { 508,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #508 = ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
3094
    { 507,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 232,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #507 = ATOMIC_RMW8_U_CMPXCHG_I64_A32
3095
    { 506,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #506 = ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
3096
    { 505,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 226,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #505 = ATOMIC_RMW8_U_CMPXCHG_I32_A64
3097
    { 504,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #504 = ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
3098
    { 503,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 220,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #503 = ATOMIC_RMW8_U_CMPXCHG_I32_A32
3099
    { 502,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #502 = ATOMIC_RMW8_U_AND_I64_A64_S
3100
    { 501,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #501 = ATOMIC_RMW8_U_AND_I64_A64
3101
    { 500,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #500 = ATOMIC_RMW8_U_AND_I64_A32_S
3102
    { 499,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #499 = ATOMIC_RMW8_U_AND_I64_A32
3103
    { 498,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #498 = ATOMIC_RMW8_U_AND_I32_A64_S
3104
    { 497,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #497 = ATOMIC_RMW8_U_AND_I32_A64
3105
    { 496,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #496 = ATOMIC_RMW8_U_AND_I32_A32_S
3106
    { 495,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #495 = ATOMIC_RMW8_U_AND_I32_A32
3107
    { 494,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #494 = ATOMIC_RMW8_U_ADD_I64_A64_S
3108
    { 493,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #493 = ATOMIC_RMW8_U_ADD_I64_A64
3109
    { 492,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #492 = ATOMIC_RMW8_U_ADD_I64_A32_S
3110
    { 491,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #491 = ATOMIC_RMW8_U_ADD_I64_A32
3111
    { 490,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #490 = ATOMIC_RMW8_U_ADD_I32_A64_S
3112
    { 489,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #489 = ATOMIC_RMW8_U_ADD_I32_A64
3113
    { 488,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #488 = ATOMIC_RMW8_U_ADD_I32_A32_S
3114
    { 487,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #487 = ATOMIC_RMW8_U_ADD_I32_A32
3115
    { 486,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = ATOMIC_RMW32_U_XOR_I64_A64_S
3116
    { 485,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = ATOMIC_RMW32_U_XOR_I64_A64
3117
    { 484,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = ATOMIC_RMW32_U_XOR_I64_A32_S
3118
    { 483,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = ATOMIC_RMW32_U_XOR_I64_A32
3119
    { 482,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = ATOMIC_RMW32_U_XCHG_I64_A64_S
3120
    { 481,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = ATOMIC_RMW32_U_XCHG_I64_A64
3121
    { 480,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = ATOMIC_RMW32_U_XCHG_I64_A32_S
3122
    { 479,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = ATOMIC_RMW32_U_XCHG_I64_A32
3123
    { 478,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = ATOMIC_RMW32_U_SUB_I64_A64_S
3124
    { 477,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = ATOMIC_RMW32_U_SUB_I64_A64
3125
    { 476,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = ATOMIC_RMW32_U_SUB_I64_A32_S
3126
    { 475,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = ATOMIC_RMW32_U_SUB_I64_A32
3127
    { 474,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = ATOMIC_RMW32_U_OR_I64_A64_S
3128
    { 473,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = ATOMIC_RMW32_U_OR_I64_A64
3129
    { 472,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = ATOMIC_RMW32_U_OR_I64_A32_S
3130
    { 471,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = ATOMIC_RMW32_U_OR_I64_A32
3131
    { 470,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
3132
    { 469,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 238,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = ATOMIC_RMW32_U_CMPXCHG_I64_A64
3133
    { 468,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
3134
    { 467,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 232,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = ATOMIC_RMW32_U_CMPXCHG_I64_A32
3135
    { 466,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = ATOMIC_RMW32_U_AND_I64_A64_S
3136
    { 465,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = ATOMIC_RMW32_U_AND_I64_A64
3137
    { 464,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = ATOMIC_RMW32_U_AND_I64_A32_S
3138
    { 463,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = ATOMIC_RMW32_U_AND_I64_A32
3139
    { 462,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = ATOMIC_RMW32_U_ADD_I64_A64_S
3140
    { 461,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = ATOMIC_RMW32_U_ADD_I64_A64
3141
    { 460,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = ATOMIC_RMW32_U_ADD_I64_A32_S
3142
    { 459,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = ATOMIC_RMW32_U_ADD_I64_A32
3143
    { 458,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = ATOMIC_RMW16_U_XOR_I64_A64_S
3144
    { 457,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = ATOMIC_RMW16_U_XOR_I64_A64
3145
    { 456,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = ATOMIC_RMW16_U_XOR_I64_A32_S
3146
    { 455,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = ATOMIC_RMW16_U_XOR_I64_A32
3147
    { 454,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = ATOMIC_RMW16_U_XOR_I32_A64_S
3148
    { 453,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = ATOMIC_RMW16_U_XOR_I32_A64
3149
    { 452,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = ATOMIC_RMW16_U_XOR_I32_A32_S
3150
    { 451,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = ATOMIC_RMW16_U_XOR_I32_A32
3151
    { 450,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = ATOMIC_RMW16_U_XCHG_I64_A64_S
3152
    { 449,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = ATOMIC_RMW16_U_XCHG_I64_A64
3153
    { 448,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = ATOMIC_RMW16_U_XCHG_I64_A32_S
3154
    { 447,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = ATOMIC_RMW16_U_XCHG_I64_A32
3155
    { 446,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = ATOMIC_RMW16_U_XCHG_I32_A64_S
3156
    { 445,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = ATOMIC_RMW16_U_XCHG_I32_A64
3157
    { 444,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = ATOMIC_RMW16_U_XCHG_I32_A32_S
3158
    { 443,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = ATOMIC_RMW16_U_XCHG_I32_A32
3159
    { 442,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = ATOMIC_RMW16_U_SUB_I64_A64_S
3160
    { 441,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = ATOMIC_RMW16_U_SUB_I64_A64
3161
    { 440,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = ATOMIC_RMW16_U_SUB_I64_A32_S
3162
    { 439,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = ATOMIC_RMW16_U_SUB_I64_A32
3163
    { 438,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = ATOMIC_RMW16_U_SUB_I32_A64_S
3164
    { 437,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = ATOMIC_RMW16_U_SUB_I32_A64
3165
    { 436,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = ATOMIC_RMW16_U_SUB_I32_A32_S
3166
    { 435,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = ATOMIC_RMW16_U_SUB_I32_A32
3167
    { 434,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = ATOMIC_RMW16_U_OR_I64_A64_S
3168
    { 433,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = ATOMIC_RMW16_U_OR_I64_A64
3169
    { 432,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = ATOMIC_RMW16_U_OR_I64_A32_S
3170
    { 431,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = ATOMIC_RMW16_U_OR_I64_A32
3171
    { 430,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = ATOMIC_RMW16_U_OR_I32_A64_S
3172
    { 429,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = ATOMIC_RMW16_U_OR_I32_A64
3173
    { 428,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = ATOMIC_RMW16_U_OR_I32_A32_S
3174
    { 427,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = ATOMIC_RMW16_U_OR_I32_A32
3175
    { 426,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
3176
    { 425,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 238,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = ATOMIC_RMW16_U_CMPXCHG_I64_A64
3177
    { 424,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
3178
    { 423,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 232,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = ATOMIC_RMW16_U_CMPXCHG_I64_A32
3179
    { 422,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
3180
    { 421,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 226,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = ATOMIC_RMW16_U_CMPXCHG_I32_A64
3181
    { 420,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
3182
    { 419,  6,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 220,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = ATOMIC_RMW16_U_CMPXCHG_I32_A32
3183
    { 418,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = ATOMIC_RMW16_U_AND_I64_A64_S
3184
    { 417,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = ATOMIC_RMW16_U_AND_I64_A64
3185
    { 416,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = ATOMIC_RMW16_U_AND_I64_A32_S
3186
    { 415,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = ATOMIC_RMW16_U_AND_I64_A32
3187
    { 414,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = ATOMIC_RMW16_U_AND_I32_A64_S
3188
    { 413,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = ATOMIC_RMW16_U_AND_I32_A64
3189
    { 412,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = ATOMIC_RMW16_U_AND_I32_A32_S
3190
    { 411,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = ATOMIC_RMW16_U_AND_I32_A32
3191
    { 410,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = ATOMIC_RMW16_U_ADD_I64_A64_S
3192
    { 409,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 215,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = ATOMIC_RMW16_U_ADD_I64_A64
3193
    { 408,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = ATOMIC_RMW16_U_ADD_I64_A32_S
3194
    { 407,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 210,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = ATOMIC_RMW16_U_ADD_I64_A32
3195
    { 406,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = ATOMIC_RMW16_U_ADD_I32_A64_S
3196
    { 405,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 205,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = ATOMIC_RMW16_U_ADD_I32_A64
3197
    { 404,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = ATOMIC_RMW16_U_ADD_I32_A32_S
3198
    { 403,  5,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 200,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = ATOMIC_RMW16_U_ADD_I32_A32
3199
    { 402,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = ATOMIC_LOAD_I64_A64_S
3200
    { 401,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = ATOMIC_LOAD_I64_A64
3201
    { 400,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = ATOMIC_LOAD_I64_A32_S
3202
    { 399,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = ATOMIC_LOAD_I64_A32
3203
    { 398,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = ATOMIC_LOAD_I32_A64_S
3204
    { 397,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 186,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = ATOMIC_LOAD_I32_A64
3205
    { 396,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = ATOMIC_LOAD_I32_A32_S
3206
    { 395,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 180,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = ATOMIC_LOAD_I32_A32
3207
    { 394,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = ATOMIC_LOAD8_U_I64_A64_S
3208
    { 393,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = ATOMIC_LOAD8_U_I64_A64
3209
    { 392,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = ATOMIC_LOAD8_U_I64_A32_S
3210
    { 391,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = ATOMIC_LOAD8_U_I64_A32
3211
    { 390,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = ATOMIC_LOAD8_U_I32_A64_S
3212
    { 389,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 186,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = ATOMIC_LOAD8_U_I32_A64
3213
    { 388,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = ATOMIC_LOAD8_U_I32_A32_S
3214
    { 387,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 180,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = ATOMIC_LOAD8_U_I32_A32
3215
    { 386,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = ATOMIC_LOAD32_U_I64_A64_S
3216
    { 385,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = ATOMIC_LOAD32_U_I64_A64
3217
    { 384,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = ATOMIC_LOAD32_U_I64_A32_S
3218
    { 383,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = ATOMIC_LOAD32_U_I64_A32
3219
    { 382,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = ATOMIC_LOAD16_U_I64_A64_S
3220
    { 381,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 196,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = ATOMIC_LOAD16_U_I64_A64
3221
    { 380,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = ATOMIC_LOAD16_U_I64_A32_S
3222
    { 379,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = ATOMIC_LOAD16_U_I64_A32
3223
    { 378,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 190,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = ATOMIC_LOAD16_U_I32_A64_S
3224
    { 377,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 186,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = ATOMIC_LOAD16_U_I32_A64
3225
    { 376,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 184,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = ATOMIC_LOAD16_U_I32_A32_S
3226
    { 375,  4,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 180,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = ATOMIC_LOAD16_U_I32_A32
3227
    { 374,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = ATOMIC_FENCE_S
3228
    { 373,  1,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = ATOMIC_FENCE
3229
    { 372,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = ARGUMENT_v8i16_S
3230
    { 371,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 178,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = ARGUMENT_v8i16
3231
    { 370,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = ARGUMENT_v4i32_S
3232
    { 369,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 178,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = ARGUMENT_v4i32
3233
    { 368,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = ARGUMENT_v4f32_S
3234
    { 367,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 178,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = ARGUMENT_v4f32
3235
    { 366,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = ARGUMENT_v2i64_S
3236
    { 365,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 178,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = ARGUMENT_v2i64
3237
    { 364,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = ARGUMENT_v2f64_S
3238
    { 363,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 178,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = ARGUMENT_v2f64
3239
    { 362,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = ARGUMENT_v16i8_S
3240
    { 361,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 178,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = ARGUMENT_v16i8
3241
    { 360,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = ARGUMENT_i64_S
3242
    { 359,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 176,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = ARGUMENT_i64
3243
    { 358,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = ARGUMENT_i32_S
3244
    { 357,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 174,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = ARGUMENT_i32
3245
    { 356,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = ARGUMENT_funcref_S
3246
    { 355,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 172,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = ARGUMENT_funcref
3247
    { 354,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = ARGUMENT_f64_S
3248
    { 353,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 170,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = ARGUMENT_f64
3249
    { 352,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = ARGUMENT_f32_S
3250
    { 351,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 168,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = ARGUMENT_f32
3251
    { 350,  1,  0,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = ARGUMENT_externref_S
3252
    { 349,  2,  1,  0,  0,  1,  0,  WebAssemblyImpOpBase + 3, 166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = ARGUMENT_externref
3253
    { 348,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = ANYTRUE_S
3254
    { 347,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = ANYTRUE
3255
    { 346,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = AND_S
3256
    { 345,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = AND_I64_S
3257
    { 344,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = AND_I64
3258
    { 343,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = AND_I32_S
3259
    { 342,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = AND_I32
3260
    { 341,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = ANDNOT_S
3261
    { 340,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = ANDNOT
3262
    { 339,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = AND
3263
    { 338,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = ALLTRUE_I8x16_S
3264
    { 337,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = ALLTRUE_I8x16
3265
    { 336,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = ALLTRUE_I64x2_S
3266
    { 335,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = ALLTRUE_I64x2
3267
    { 334,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = ALLTRUE_I32x4_S
3268
    { 333,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = ALLTRUE_I32x4
3269
    { 332,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = ALLTRUE_I16x8_S
3270
    { 331,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 164,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = ALLTRUE_I16x8
3271
    { 330,  2,  0,  0,  0,  2,  2,  WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = ADJCALLSTACKUP_S
3272
    { 329,  2,  0,  0,  0,  2,  2,  WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = ADJCALLSTACKUP
3273
    { 328,  2,  0,  0,  0,  2,  2,  WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = ADJCALLSTACKDOWN_S
3274
    { 327,  2,  0,  0,  0,  2,  2,  WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = ADJCALLSTACKDOWN
3275
    { 326,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = ADD_SAT_U_I8x16_S
3276
    { 325,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = ADD_SAT_U_I8x16
3277
    { 324,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = ADD_SAT_U_I16x8_S
3278
    { 323,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = ADD_SAT_U_I16x8
3279
    { 322,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = ADD_SAT_S_I8x16_S
3280
    { 321,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = ADD_SAT_S_I8x16
3281
    { 320,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = ADD_SAT_S_I16x8_S
3282
    { 319,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = ADD_SAT_S_I16x8
3283
    { 318,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = ADD_I8x16_S
3284
    { 317,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = ADD_I8x16
3285
    { 316,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = ADD_I64x2_S
3286
    { 315,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = ADD_I64x2
3287
    { 314,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = ADD_I64_S
3288
    { 313,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 161,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = ADD_I64
3289
    { 312,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = ADD_I32x4_S
3290
    { 311,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = ADD_I32x4
3291
    { 310,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ADD_I32_S
3292
    { 309,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 158,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = ADD_I32
3293
    { 308,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ADD_I16x8_S
3294
    { 307,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ADD_I16x8
3295
    { 306,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ADD_F64x2_S
3296
    { 305,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = ADD_F64x2
3297
    { 304,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = ADD_F64_S
3298
    { 303,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 155,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ADD_F64
3299
    { 302,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ADD_F32x4_S
3300
    { 301,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 152,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = ADD_F32x4
3301
    { 300,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = ADD_F32_S
3302
    { 299,  3,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 149,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = ADD_F32
3303
    { 298,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = ABS_I8x16_S
3304
    { 297,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = ABS_I8x16
3305
    { 296,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = ABS_I64x2_S
3306
    { 295,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = ABS_I64x2
3307
    { 294,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = ABS_I32x4_S
3308
    { 293,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = ABS_I32x4
3309
    { 292,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = ABS_I16x8_S
3310
    { 291,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = ABS_I16x8
3311
    { 290,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = ABS_F64x2_S
3312
    { 289,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = ABS_F64x2
3313
    { 288,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = ABS_F64_S
3314
    { 287,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 147,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = ABS_F64
3315
    { 286,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = ABS_F32x4_S
3316
    { 285,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 145,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = ABS_F32x4
3317
    { 284,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = ABS_F32_S
3318
    { 283,  2,  1,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = ABS_F32
3319
    { 282,  0,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #282 = RET_CALL_RESULTS_S
3320
    { 281,  0,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #281 = RET_CALL_RESULTS
3321
    { 280,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = COMPILER_FENCE_S
3322
    { 279,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = COMPILER_FENCE
3323
    { 278,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = CLEANUPRET_S
3324
    { 277,  0,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = CLEANUPRET
3325
    { 276,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 141,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = CATCHRET_S
3326
    { 275,  2,  0,  0,  0,  0,  1,  WebAssemblyImpOpBase + 3, 141,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = CATCHRET
3327
    { 274,  0,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #274 = CALL_RESULTS_S
3328
    { 273,  0,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL },  // Inst #273 = CALL_RESULTS
3329
    { 272,  1,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = CALL_PARAMS_S
3330
    { 271,  1,  0,  0,  0,  2,  1,  WebAssemblyImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = CALL_PARAMS
3331
    { 270,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_UBFX
3332
    { 269,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_SBFX
3333
    { 268,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_VECREDUCE_UMIN
3334
    { 267,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_VECREDUCE_UMAX
3335
    { 266,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_VECREDUCE_SMIN
3336
    { 265,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_VECREDUCE_SMAX
3337
    { 264,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_VECREDUCE_XOR
3338
    { 263,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_VECREDUCE_OR
3339
    { 262,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_VECREDUCE_AND
3340
    { 261,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_VECREDUCE_MUL
3341
    { 260,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_VECREDUCE_ADD
3342
    { 259,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_VECREDUCE_FMINIMUM
3343
    { 258,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_VECREDUCE_FMAXIMUM
3344
    { 257,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_VECREDUCE_FMIN
3345
    { 256,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_VECREDUCE_FMAX
3346
    { 255,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_VECREDUCE_FMUL
3347
    { 254,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_VECREDUCE_FADD
3348
    { 253,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
3349
    { 252,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_VECREDUCE_SEQ_FADD
3350
    { 251,  3,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_BZERO
3351
    { 250,  4,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_MEMSET
3352
    { 249,  4,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_MEMMOVE
3353
    { 248,  3,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_MEMCPY_INLINE
3354
    { 247,  4,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_MEMCPY
3355
    { 246,  2,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 130,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #246 = G_WRITE_REGISTER
3356
    { 245,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #245 = G_READ_REGISTER
3357
    { 244,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_STRICT_FLDEXP
3358
    { 243,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_STRICT_FSQRT
3359
    { 242,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_STRICT_FMA
3360
    { 241,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_STRICT_FREM
3361
    { 240,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_STRICT_FDIV
3362
    { 239,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_STRICT_FMUL
3363
    { 238,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_STRICT_FSUB
3364
    { 237,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_STRICT_FADD
3365
    { 236,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_STACKRESTORE
3366
    { 235,  1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_STACKSAVE
3367
    { 234,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_DYN_STACKALLOC
3368
    { 233,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_JUMP_TABLE
3369
    { 232,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_BLOCK_ADDR
3370
    { 231,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_ADDRSPACE_CAST
3371
    { 230,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_FNEARBYINT
3372
    { 229,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_FRINT
3373
    { 228,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_FFLOOR
3374
    { 227,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_FSQRT
3375
    { 226,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_FSIN
3376
    { 225,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_FCOS
3377
    { 224,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_FCEIL
3378
    { 223,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BITREVERSE
3379
    { 222,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BSWAP
3380
    { 221,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_CTPOP
3381
    { 220,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_CTLZ_ZERO_UNDEF
3382
    { 219,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_CTLZ
3383
    { 218,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_CTTZ_ZERO_UNDEF
3384
    { 217,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_CTTZ
3385
    { 216,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 126,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SHUFFLE_VECTOR
3386
    { 215,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_EXTRACT_VECTOR_ELT
3387
    { 214,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 119,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_INSERT_VECTOR_ELT
3388
    { 213,  3,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 116,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_BRJT
3389
    { 212,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_BR
3390
    { 211,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_LLROUND
3391
    { 210,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_LROUND
3392
    { 209,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_ABS
3393
    { 208,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_UMAX
3394
    { 207,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_UMIN
3395
    { 206,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_SMAX
3396
    { 205,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_SMIN
3397
    { 204,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_PTRMASK
3398
    { 203,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_PTR_ADD
3399
    { 202,  0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_RESET_FPMODE
3400
    { 201,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_SET_FPMODE
3401
    { 200,  1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_GET_FPMODE
3402
    { 199,  0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_RESET_FPENV
3403
    { 198,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SET_FPENV
3404
    { 197,  1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_GET_FPENV
3405
    { 196,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FMAXIMUM
3406
    { 195,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FMINIMUM
3407
    { 194,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FMAXNUM_IEEE
3408
    { 193,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FMINNUM_IEEE
3409
    { 192,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FMAXNUM
3410
    { 191,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FMINNUM
3411
    { 190,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FCANONICALIZE
3412
    { 189,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_IS_FPCLASS
3413
    { 188,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FCOPYSIGN
3414
    { 187,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FABS
3415
    { 186,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_UITOFP
3416
    { 185,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_SITOFP
3417
    { 184,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPTOUI
3418
    { 183,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPTOSI
3419
    { 182,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FPTRUNC
3420
    { 181,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPEXT
3421
    { 180,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FNEG
3422
    { 179,  3,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FFREXP
3423
    { 178,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FLDEXP
3424
    { 177,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FLOG10
3425
    { 176,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FLOG2
3426
    { 175,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FLOG
3427
    { 174,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FEXP10
3428
    { 173,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FEXP2
3429
    { 172,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_FEXP
3430
    { 171,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_FPOWI
3431
    { 170,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_FPOW
3432
    { 169,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_FREM
3433
    { 168,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_FDIV
3434
    { 167,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_FMAD
3435
    { 166,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_FMA
3436
    { 165,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_FMUL
3437
    { 164,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_FSUB
3438
    { 163,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_FADD
3439
    { 162,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UDIVFIXSAT
3440
    { 161,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SDIVFIXSAT
3441
    { 160,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UDIVFIX
3442
    { 159,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SDIVFIX
3443
    { 158,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULFIXSAT
3444
    { 157,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SMULFIXSAT
3445
    { 156,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_UMULFIX
3446
    { 155,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SMULFIX
3447
    { 154,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSHLSAT
3448
    { 153,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USHLSAT
3449
    { 152,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SSUBSAT
3450
    { 151,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_USUBSAT
3451
    { 150,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_SADDSAT
3452
    { 149,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_UADDSAT
3453
    { 148,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_SMULH
3454
    { 147,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UMULH
3455
    { 146,  4,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SMULO
3456
    { 145,  4,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UMULO
3457
    { 144,  5,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SSUBE
3458
    { 143,  4,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_SSUBO
3459
    { 142,  5,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_SADDE
3460
    { 141,  4,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_SADDO
3461
    { 140,  5,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_USUBE
3462
    { 139,  4,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_USUBO
3463
    { 138,  5,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_UADDE
3464
    { 137,  4,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_UADDO
3465
    { 136,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SELECT
3466
    { 135,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_FCMP
3467
    { 134,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ICMP
3468
    { 133,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_ROTL
3469
    { 132,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_ROTR
3470
    { 131,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_FSHR
3471
    { 130,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_FSHL
3472
    { 129,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ASHR
3473
    { 128,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_LSHR
3474
    { 127,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_SHL
3475
    { 126,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ZEXT
3476
    { 125,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_SEXT_INREG
3477
    { 124,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_SEXT
3478
    { 123,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_VAARG
3479
    { 122,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_VASTART
3480
    { 121,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_FCONSTANT
3481
    { 120,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_CONSTANT
3482
    { 119,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_TRUNC
3483
    { 118,  2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ANYEXT
3484
    { 117,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3485
    { 116,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #116 = G_INTRINSIC_CONVERGENT
3486
    { 115,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
3487
    { 114,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_INTRINSIC
3488
    { 113,  0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_INVOKE_REGION_START
3489
    { 112,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_BRINDIRECT
3490
    { 111,  2,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_BRCOND
3491
    { 110,  4,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 89, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_PREFETCH
3492
    { 109,  2,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_FENCE
3493
    { 108,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
3494
    { 107,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
3495
    { 106,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_FMIN
3496
    { 105,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_FMAX
3497
    { 104,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_FSUB
3498
    { 103,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_FADD
3499
    { 102,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_UMIN
3500
    { 101,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_UMAX
3501
    { 100,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_MIN
3502
    { 99, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMICRMW_MAX
3503
    { 98, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMICRMW_XOR
3504
    { 97, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_ATOMICRMW_OR
3505
    { 96, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_ATOMICRMW_NAND
3506
    { 95, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_ATOMICRMW_AND
3507
    { 94, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_ATOMICRMW_SUB
3508
    { 93, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ATOMICRMW_ADD
3509
    { 92, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ATOMICRMW_XCHG
3510
    { 91, 4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_ATOMIC_CMPXCHG
3511
    { 90, 5,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
3512
    { 89, 5,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_INDEXED_STORE
3513
    { 88, 2,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_STORE
3514
    { 87, 5,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INDEXED_ZEXTLOAD
3515
    { 86, 5,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INDEXED_SEXTLOAD
3516
    { 85, 5,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INDEXED_LOAD
3517
    { 84, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_ZEXTLOAD
3518
    { 83, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_SEXTLOAD
3519
    { 82, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_LOAD
3520
    { 81, 1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_READCYCLECOUNTER
3521
    { 80, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
3522
    { 79, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTRINSIC_LRINT
3523
    { 78, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTRINSIC_ROUND
3524
    { 77, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_INTRINSIC_TRUNC
3525
    { 76, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
3526
    { 75, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
3527
    { 74, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_FREEZE
3528
    { 73, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_BITCAST
3529
    { 72, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INTTOPTR
3530
    { 71, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_PTRTOINT
3531
    { 70, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONCAT_VECTORS
3532
    { 69, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_BUILD_VECTOR_TRUNC
3533
    { 68, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_BUILD_VECTOR
3534
    { 67, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_MERGE_VALUES
3535
    { 66, 4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_INSERT
3536
    { 65, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_UNMERGE_VALUES
3537
    { 64, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_EXTRACT
3538
    { 63, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_CONSTANT_POOL
3539
    { 62, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_GLOBAL_VALUE
3540
    { 61, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_FRAME_INDEX
3541
    { 60, 1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_PHI
3542
    { 59, 1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_IMPLICIT_DEF
3543
    { 58, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_XOR
3544
    { 57, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_OR
3545
    { 56, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_AND
3546
    { 55, 4,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_UDIVREM
3547
    { 54, 4,  2,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SDIVREM
3548
    { 53, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_UREM
3549
    { 52, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_SREM
3550
    { 51, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_UDIV
3551
    { 50, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_SDIV
3552
    { 49, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_MUL
3553
    { 48, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #48 = G_SUB
3554
    { 47, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #47 = G_ADD
3555
    { 46, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #46 = G_ASSERT_ALIGN
3556
    { 45, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = G_ASSERT_ZEXT
3557
    { 44, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = G_ASSERT_SEXT
3558
    { 43, 1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
3559
    { 42, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = MEMBARRIER
3560
    { 41, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
3561
    { 40, 3,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
3562
    { 39, 2,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
3563
    { 38, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
3564
    { 37, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
3565
    { 36, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
3566
    { 35, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
3567
    { 34, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
3568
    { 33, 1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
3569
    { 32, 2,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
3570
    { 31, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
3571
    { 30, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
3572
    { 29, 1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
3573
    { 28, 1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
3574
    { 27, 6,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
3575
    { 26, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
3576
    { 25, 2,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
3577
    { 24, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
3578
    { 23, 4,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
3579
    { 22, 1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
3580
    { 21, 1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
3581
    { 20, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
3582
    { 19, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
3583
    { 18, 2,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
3584
    { 17, 1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
3585
    { 16, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
3586
    { 15, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
3587
    { 14, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
3588
    { 13, 0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
3589
    { 12, 3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
3590
    { 11, 4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 9,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
3591
    { 10, 1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
3592
    { 9,  4,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 5,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
3593
    { 8,  3,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
3594
    { 7,  0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
3595
    { 6,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
3596
    { 5,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
3597
    { 4,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
3598
    { 3,  1,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
3599
    { 2,  0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
3600
    { 1,  0,  0,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
3601
    { 0,  1,  1,  0,  0,  0,  0,  WebAssemblyImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
3602
  }, {
3603
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3604
    /* 1 */
3605
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3606
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3607
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3608
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3609
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3610
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3611
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
3612
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3613
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3614
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
3615
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3616
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3617
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3618
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3619
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3620
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3621
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3622
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3623
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3624
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3625
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3626
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3627
    /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3628
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3629
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3630
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3631
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3632
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3633
    /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3634
    /* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3635
    /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3636
    /* 96 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3637
    /* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3638
    /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3639
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3640
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3641
    /* 116 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3642
    /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
3643
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
3644
    /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3645
    /* 130 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3646
    /* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3647
    /* 136 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3648
    /* 140 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
3649
    /* 141 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
3650
    /* 143 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3651
    /* 145 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3652
    /* 147 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3653
    /* 149 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3654
    /* 152 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3655
    /* 155 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3656
    /* 158 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3657
    /* 161 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3658
    /* 164 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3659
    /* 166 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3660
    /* 168 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3661
    /* 170 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3662
    /* 172 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3663
    /* 174 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3664
    /* 176 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3665
    /* 178 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3666
    /* 180 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3667
    /* 184 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 },
3668
    /* 186 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3669
    /* 190 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 },
3670
    /* 192 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3671
    /* 196 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3672
    /* 200 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3673
    /* 205 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3674
    /* 210 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3675
    /* 215 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3676
    /* 220 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3677
    /* 226 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3678
    /* 232 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3679
    /* 238 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3680
    /* 244 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3681
    /* 248 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3682
    /* 252 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3683
    /* 256 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3684
    /* 260 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3685
    /* 264 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 },
3686
    /* 265 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
3687
    /* 266 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3688
    /* 268 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3689
    /* 269 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 },
3690
    /* 270 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3691
    /* 271 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
3692
    /* 273 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 },
3693
    /* 274 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3694
    /* 276 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3695
    /* 278 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
3696
    /* 280 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
3697
    /* 281 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
3698
    /* 283 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
3699
    /* 284 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
3700
    /* 286 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
3701
    /* 287 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
3702
    /* 289 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
3703
    /* 290 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
3704
    /* 295 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
3705
    /* 299 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
3706
    /* 302 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
3707
    /* 304 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
3708
    /* 313 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
3709
    /* 321 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
3710
    /* 326 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
3711
    /* 330 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
3712
    /* 333 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
3713
    /* 335 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3714
    /* 352 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3715
    /* 368 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3716
    /* 370 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3717
    /* 372 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3718
    /* 373 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3719
    /* 374 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3720
    /* 375 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3721
    /* 376 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3722
    /* 377 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3723
    /* 379 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3724
    /* 382 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3725
    /* 385 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3726
    /* 388 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3727
    /* 391 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3728
    /* 392 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3729
    /* 395 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3730
    /* 398 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3731
    /* 401 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3732
    /* 403 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3733
    /* 405 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3734
    /* 407 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3735
    /* 409 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3736
    /* 411 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3737
    /* 413 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3738
    /* 415 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3739
    /* 417 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3740
    /* 419 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3741
    /* 421 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3742
    /* 423 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3743
    /* 424 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3744
    /* 426 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3745
    /* 428 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3746
    /* 430 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3747
    /* 432 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3748
    /* 434 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3749
    /* 436 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3750
    /* 438 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3751
    /* 440 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3752
    /* 442 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3753
    /* 444 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3754
    /* 446 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3755
    /* 448 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3756
    /* 450 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3757
    /* 452 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3758
    /* 454 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3759
    /* 458 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3760
    /* 462 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3761
    /* 466 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3762
    /* 470 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3763
    /* 474 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3764
    /* 478 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3765
    /* 484 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3766
    /* 487 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3767
    /* 493 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3768
    /* 496 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
3769
    /* 498 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
3770
    /* 499 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
3771
    /* 501 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
3772
    /* 503 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
3773
    /* 505 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
3774
    /* 507 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
3775
    /* 509 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
3776
    /* 511 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3777
    /* 513 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3778
    /* 515 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3779
    /* 517 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3780
    /* 519 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3781
    /* 521 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3782
    /* 523 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3783
    /* 525 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3784
    /* 528 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3785
    /* 531 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3786
    /* 534 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3787
    /* 537 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3788
    /* 540 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3789
    /* 543 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3790
    /* 546 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3791
    /* 552 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3792
    /* 558 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3793
    /* 564 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3794
    /* 570 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3795
    /* 572 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3796
    /* 574 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3797
    /* 578 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3798
    /* 582 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3799
    /* 586 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3800
    /* 590 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3801
    /* 594 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3802
    /* 598 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3803
    /* 602 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3804
    /* 606 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3805
    /* 610 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3806
    /* 614 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3807
    /* 618 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3808
    /* 621 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3809
    /* 640 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3810
    /* 642 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3811
    /* 644 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3812
    /* 646 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3813
    /* 648 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3814
    /* 652 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3815
    /* 656 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3816
    /* 660 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3817
    /* 664 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3818
    /* 669 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3819
    /* 674 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3820
    /* 678 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3821
    /* 682 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3822
    /* 687 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
3823
    /* 689 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3824
    /* 693 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
3825
    /* 694 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3826
    /* 698 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3827
    /* 701 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3828
    /* 704 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3829
    /* 708 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3830
    /* 712 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3831
    /* 715 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3832
    /* 718 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
3833
    /* 720 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3834
    /* 723 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3835
    /* 726 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3836
    /* 729 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3837
    /* 732 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3838
    /* 737 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
3839
    /* 739 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3840
    /* 743 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3841
    /* 748 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3842
    /* 752 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3843
  }, {
3844
    /* 0 */
3845
    /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS,
3846
    /* 3 */ WebAssembly::ARGUMENTS,
3847
    /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64,
3848
    /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK,
3849
  }
3850
};
3851
3852
3853
#ifdef __GNUC__
3854
#pragma GCC diagnostic push
3855
#pragma GCC diagnostic ignored "-Woverlength-strings"
3856
#endif
3857
extern const char WebAssemblyInstrNameData[] = {
3858
  /* 0 */ "G_FLOG10\0"
3859
  /* 9 */ "G_FEXP10\0"
3860
  /* 18 */ "LOAD_F32_A32\0"
3861
  /* 31 */ "STORE_F32_A32\0"
3862
  /* 45 */ "ATOMIC_STORE16_I32_A32\0"
3863
  /* 68 */ "ATOMIC_STORE8_I32_A32\0"
3864
  /* 90 */ "ATOMIC_RMW16_U_SUB_I32_A32\0"
3865
  /* 117 */ "ATOMIC_RMW8_U_SUB_I32_A32\0"
3866
  /* 143 */ "ATOMIC_RMW_SUB_I32_A32\0"
3867
  /* 166 */ "ATOMIC_LOAD_I32_A32\0"
3868
  /* 186 */ "ATOMIC_RMW16_U_ADD_I32_A32\0"
3869
  /* 213 */ "ATOMIC_RMW8_U_ADD_I32_A32\0"
3870
  /* 239 */ "ATOMIC_RMW_ADD_I32_A32\0"
3871
  /* 262 */ "ATOMIC_RMW16_U_AND_I32_A32\0"
3872
  /* 289 */ "ATOMIC_RMW8_U_AND_I32_A32\0"
3873
  /* 315 */ "ATOMIC_RMW_AND_I32_A32\0"
3874
  /* 338 */ "ATOMIC_STORE_I32_A32\0"
3875
  /* 359 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\0"
3876
  /* 390 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\0"
3877
  /* 420 */ "ATOMIC_RMW_CMPXCHG_I32_A32\0"
3878
  /* 447 */ "ATOMIC_RMW16_U_XCHG_I32_A32\0"
3879
  /* 475 */ "ATOMIC_RMW8_U_XCHG_I32_A32\0"
3880
  /* 502 */ "ATOMIC_RMW_XCHG_I32_A32\0"
3881
  /* 526 */ "ATOMIC_RMW16_U_XOR_I32_A32\0"
3882
  /* 553 */ "ATOMIC_RMW8_U_XOR_I32_A32\0"
3883
  /* 579 */ "ATOMIC_RMW_XOR_I32_A32\0"
3884
  /* 602 */ "ATOMIC_RMW16_U_OR_I32_A32\0"
3885
  /* 628 */ "ATOMIC_RMW8_U_OR_I32_A32\0"
3886
  /* 653 */ "ATOMIC_RMW_OR_I32_A32\0"
3887
  /* 675 */ "LOAD16_S_I32_A32\0"
3888
  /* 692 */ "LOAD8_S_I32_A32\0"
3889
  /* 708 */ "ATOMIC_LOAD16_U_I32_A32\0"
3890
  /* 732 */ "ATOMIC_LOAD8_U_I32_A32\0"
3891
  /* 755 */ "MEMORY_ATOMIC_WAIT32_A32\0"
3892
  /* 780 */ "LOAD_LANE_I64x2_A32\0"
3893
  /* 800 */ "STORE_LANE_I64x2_A32\0"
3894
  /* 821 */ "LOAD_ZERO_I64x2_A32\0"
3895
  /* 841 */ "LOAD_EXTEND_S_I64x2_A32\0"
3896
  /* 865 */ "LOAD_EXTEND_U_I64x2_A32\0"
3897
  /* 889 */ "LOAD_F64_A32\0"
3898
  /* 902 */ "STORE_F64_A32\0"
3899
  /* 916 */ "ATOMIC_STORE32_I64_A32\0"
3900
  /* 939 */ "ATOMIC_STORE16_I64_A32\0"
3901
  /* 962 */ "ATOMIC_STORE8_I64_A32\0"
3902
  /* 984 */ "ATOMIC_RMW32_U_SUB_I64_A32\0"
3903
  /* 1011 */ "ATOMIC_RMW16_U_SUB_I64_A32\0"
3904
  /* 1038 */ "ATOMIC_RMW8_U_SUB_I64_A32\0"
3905
  /* 1064 */ "ATOMIC_RMW_SUB_I64_A32\0"
3906
  /* 1087 */ "ATOMIC_LOAD_I64_A32\0"
3907
  /* 1107 */ "ATOMIC_RMW32_U_ADD_I64_A32\0"
3908
  /* 1134 */ "ATOMIC_RMW16_U_ADD_I64_A32\0"
3909
  /* 1161 */ "ATOMIC_RMW8_U_ADD_I64_A32\0"
3910
  /* 1187 */ "ATOMIC_RMW_ADD_I64_A32\0"
3911
  /* 1210 */ "ATOMIC_RMW32_U_AND_I64_A32\0"
3912
  /* 1237 */ "ATOMIC_RMW16_U_AND_I64_A32\0"
3913
  /* 1264 */ "ATOMIC_RMW8_U_AND_I64_A32\0"
3914
  /* 1290 */ "ATOMIC_RMW_AND_I64_A32\0"
3915
  /* 1313 */ "ATOMIC_STORE_I64_A32\0"
3916
  /* 1334 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\0"
3917
  /* 1365 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\0"
3918
  /* 1396 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\0"
3919
  /* 1426 */ "ATOMIC_RMW_CMPXCHG_I64_A32\0"
3920
  /* 1453 */ "ATOMIC_RMW32_U_XCHG_I64_A32\0"
3921
  /* 1481 */ "ATOMIC_RMW16_U_XCHG_I64_A32\0"
3922
  /* 1509 */ "ATOMIC_RMW8_U_XCHG_I64_A32\0"
3923
  /* 1536 */ "ATOMIC_RMW_XCHG_I64_A32\0"
3924
  /* 1560 */ "ATOMIC_RMW32_U_XOR_I64_A32\0"
3925
  /* 1587 */ "ATOMIC_RMW16_U_XOR_I64_A32\0"
3926
  /* 1614 */ "ATOMIC_RMW8_U_XOR_I64_A32\0"
3927
  /* 1640 */ "ATOMIC_RMW_XOR_I64_A32\0"
3928
  /* 1663 */ "ATOMIC_RMW32_U_OR_I64_A32\0"
3929
  /* 1689 */ "ATOMIC_RMW16_U_OR_I64_A32\0"
3930
  /* 1715 */ "ATOMIC_RMW8_U_OR_I64_A32\0"
3931
  /* 1740 */ "ATOMIC_RMW_OR_I64_A32\0"
3932
  /* 1762 */ "LOAD32_S_I64_A32\0"
3933
  /* 1779 */ "LOAD16_S_I64_A32\0"
3934
  /* 1796 */ "LOAD8_S_I64_A32\0"
3935
  /* 1812 */ "ATOMIC_LOAD32_U_I64_A32\0"
3936
  /* 1836 */ "ATOMIC_LOAD16_U_I64_A32\0"
3937
  /* 1860 */ "ATOMIC_LOAD8_U_I64_A32\0"
3938
  /* 1883 */ "MEMORY_ATOMIC_WAIT64_A32\0"
3939
  /* 1908 */ "LOAD_LANE_I32x4_A32\0"
3940
  /* 1928 */ "STORE_LANE_I32x4_A32\0"
3941
  /* 1949 */ "LOAD_ZERO_I32x4_A32\0"
3942
  /* 1969 */ "LOAD_EXTEND_S_I32x4_A32\0"
3943
  /* 1993 */ "LOAD_EXTEND_U_I32x4_A32\0"
3944
  /* 2017 */ "LOAD_LANE_I8x16_A32\0"
3945
  /* 2037 */ "STORE_LANE_I8x16_A32\0"
3946
  /* 2058 */ "LOAD_V128_A32\0"
3947
  /* 2072 */ "STORE_V128_A32\0"
3948
  /* 2087 */ "LOAD_LANE_I16x8_A32\0"
3949
  /* 2107 */ "STORE_LANE_I16x8_A32\0"
3950
  /* 2128 */ "LOAD_EXTEND_S_I16x8_A32\0"
3951
  /* 2152 */ "LOAD_EXTEND_U_I16x8_A32\0"
3952
  /* 2176 */ "anonymous_7277MEMORY_SIZE_A32\0"
3953
  /* 2206 */ "anonymous_7959MEMORY_FILL_A32\0"
3954
  /* 2236 */ "LOAD32_SPLAT_A32\0"
3955
  /* 2253 */ "LOAD64_SPLAT_A32\0"
3956
  /* 2270 */ "LOAD16_SPLAT_A32\0"
3957
  /* 2287 */ "LOAD8_SPLAT_A32\0"
3958
  /* 2303 */ "anonymous_7959MEMORY_INIT_A32\0"
3959
  /* 2333 */ "anonymous_7277MEMORY_GROW_A32\0"
3960
  /* 2363 */ "MEMORY_ATOMIC_NOTIFY_A32\0"
3961
  /* 2388 */ "anonymous_7959MEMORY_COPY_A32\0"
3962
  /* 2418 */ "FP_TO_SINT_I32_F32\0"
3963
  /* 2437 */ "FP_TO_UINT_I32_F32\0"
3964
  /* 2456 */ "FP_TO_SINT_I64_F32\0"
3965
  /* 2475 */ "FP_TO_UINT_I64_F32\0"
3966
  /* 2494 */ "SUB_F32\0"
3967
  /* 2502 */ "TRUNC_F32\0"
3968
  /* 2512 */ "ADD_F32\0"
3969
  /* 2520 */ "LOCAL_TEE_F32\0"
3970
  /* 2534 */ "GE_F32\0"
3971
  /* 2541 */ "LE_F32\0"
3972
  /* 2548 */ "NE_F32\0"
3973
  /* 2555 */ "F64_PROMOTE_F32\0"
3974
  /* 2571 */ "NEG_F32\0"
3975
  /* 2579 */ "CEIL_F32\0"
3976
  /* 2588 */ "MUL_F32\0"
3977
  /* 2596 */ "COPYSIGN_F32\0"
3978
  /* 2609 */ "MIN_F32\0"
3979
  /* 2617 */ "DROP_F32\0"
3980
  /* 2626 */ "EQ_F32\0"
3981
  /* 2633 */ "FLOOR_F32\0"
3982
  /* 2643 */ "ABS_F32\0"
3983
  /* 2651 */ "I32_TRUNC_S_F32\0"
3984
  /* 2667 */ "I64_TRUNC_S_F32\0"
3985
  /* 2683 */ "I32_TRUNC_S_SAT_F32\0"
3986
  /* 2703 */ "I64_TRUNC_S_SAT_F32\0"
3987
  /* 2723 */ "I32_TRUNC_U_SAT_F32\0"
3988
  /* 2743 */ "I64_TRUNC_U_SAT_F32\0"
3989
  /* 2763 */ "SELECT_F32\0"
3990
  /* 2774 */ "GLOBAL_GET_F32\0"
3991
  /* 2789 */ "LOCAL_GET_F32\0"
3992
  /* 2803 */ "I32_REINTERPRET_F32\0"
3993
  /* 2823 */ "GLOBAL_SET_F32\0"
3994
  /* 2838 */ "LOCAL_SET_F32\0"
3995
  /* 2852 */ "GT_F32\0"
3996
  /* 2859 */ "LT_F32\0"
3997
  /* 2866 */ "SQRT_F32\0"
3998
  /* 2875 */ "NEAREST_F32\0"
3999
  /* 2887 */ "CONST_F32\0"
4000
  /* 2897 */ "I32_TRUNC_U_F32\0"
4001
  /* 2913 */ "I64_TRUNC_U_F32\0"
4002
  /* 2929 */ "DIV_F32\0"
4003
  /* 2937 */ "MAX_F32\0"
4004
  /* 2945 */ "COPY_F32\0"
4005
  /* 2954 */ "SUB_I32\0"
4006
  /* 2962 */ "ADD_I32\0"
4007
  /* 2970 */ "AND_I32\0"
4008
  /* 2978 */ "LOCAL_TEE_I32\0"
4009
  /* 2992 */ "BR_TABLE_I32\0"
4010
  /* 3005 */ "NE_I32\0"
4011
  /* 3012 */ "SHL_I32\0"
4012
  /* 3020 */ "ROTL_I32\0"
4013
  /* 3029 */ "MUL_I32\0"
4014
  /* 3037 */ "DROP_I32\0"
4015
  /* 3046 */ "EQ_I32\0"
4016
  /* 3053 */ "XOR_I32\0"
4017
  /* 3061 */ "ROTR_I32\0"
4018
  /* 3070 */ "I32_EXTEND16_S_I32\0"
4019
  /* 3089 */ "I32_EXTEND8_S_I32\0"
4020
  /* 3107 */ "I64_EXTEND_S_I32\0"
4021
  /* 3124 */ "GE_S_I32\0"
4022
  /* 3133 */ "LE_S_I32\0"
4023
  /* 3142 */ "REM_S_I32\0"
4024
  /* 3152 */ "SHR_S_I32\0"
4025
  /* 3162 */ "GT_S_I32\0"
4026
  /* 3171 */ "LT_S_I32\0"
4027
  /* 3180 */ "F32_CONVERT_S_I32\0"
4028
  /* 3198 */ "F64_CONVERT_S_I32\0"
4029
  /* 3216 */ "DIV_S_I32\0"
4030
  /* 3226 */ "SELECT_I32\0"
4031
  /* 3237 */ "GLOBAL_GET_I32\0"
4032
  /* 3252 */ "LOCAL_GET_I32\0"
4033
  /* 3266 */ "F32_REINTERPRET_I32\0"
4034
  /* 3286 */ "GLOBAL_SET_I32\0"
4035
  /* 3301 */ "LOCAL_SET_I32\0"
4036
  /* 3315 */ "POPCNT_I32\0"
4037
  /* 3326 */ "CONST_I32\0"
4038
  /* 3336 */ "I64_EXTEND_U_I32\0"
4039
  /* 3353 */ "GE_U_I32\0"
4040
  /* 3362 */ "LE_U_I32\0"
4041
  /* 3371 */ "REM_U_I32\0"
4042
  /* 3381 */ "SHR_U_I32\0"
4043
  /* 3391 */ "GT_U_I32\0"
4044
  /* 3400 */ "LT_U_I32\0"
4045
  /* 3409 */ "F32_CONVERT_U_I32\0"
4046
  /* 3427 */ "F64_CONVERT_U_I32\0"
4047
  /* 3445 */ "DIV_U_I32\0"
4048
  /* 3455 */ "COPY_I32\0"
4049
  /* 3464 */ "CLZ_I32\0"
4050
  /* 3472 */ "EQZ_I32\0"
4051
  /* 3480 */ "CTZ_I32\0"
4052
  /* 3488 */ "ARGUMENT_v4f32\0"
4053
  /* 3503 */ "ARGUMENT_f32\0"
4054
  /* 3516 */ "ARGUMENT_v4i32\0"
4055
  /* 3531 */ "ARGUMENT_i32\0"
4056
  /* 3544 */ "G_FLOG2\0"
4057
  /* 3552 */ "G_FEXP2\0"
4058
  /* 3560 */ "CONST_V128_F64x2\0"
4059
  /* 3577 */ "SUB_F64x2\0"
4060
  /* 3587 */ "TRUNC_F64x2\0"
4061
  /* 3599 */ "NMADD_F64x2\0"
4062
  /* 3611 */ "GE_F64x2\0"
4063
  /* 3620 */ "LE_F64x2\0"
4064
  /* 3629 */ "REPLACE_LANE_F64x2\0"
4065
  /* 3648 */ "EXTRACT_LANE_F64x2\0"
4066
  /* 3667 */ "NEG_F64x2\0"
4067
  /* 3677 */ "CEIL_F64x2\0"
4068
  /* 3688 */ "MUL_F64x2\0"
4069
  /* 3698 */ "SIMD_RELAXED_FMIN_F64x2\0"
4070
  /* 3722 */ "PMIN_F64x2\0"
4071
  /* 3733 */ "EQ_F64x2\0"
4072
  /* 3742 */ "FLOOR_F64x2\0"
4073
  /* 3754 */ "ABS_F64x2\0"
4074
  /* 3764 */ "SPLAT_F64x2\0"
4075
  /* 3776 */ "GT_F64x2\0"
4076
  /* 3785 */ "LT_F64x2\0"
4077
  /* 3794 */ "SQRT_F64x2\0"
4078
  /* 3805 */ "NEAREST_F64x2\0"
4079
  /* 3819 */ "DIV_F64x2\0"
4080
  /* 3829 */ "SIMD_RELAXED_FMAX_F64x2\0"
4081
  /* 3853 */ "PMAX_F64x2\0"
4082
  /* 3864 */ "convert_low_s_F64x2\0"
4083
  /* 3884 */ "convert_low_u_F64x2\0"
4084
  /* 3904 */ "promote_low_F64x2\0"
4085
  /* 3922 */ "CONST_V128_I64x2\0"
4086
  /* 3939 */ "SUB_I64x2\0"
4087
  /* 3949 */ "ADD_I64x2\0"
4088
  /* 3959 */ "REPLACE_LANE_I64x2\0"
4089
  /* 3978 */ "EXTRACT_LANE_I64x2\0"
4090
  /* 3997 */ "ALLTRUE_I64x2\0"
4091
  /* 4011 */ "NEG_I64x2\0"
4092
  /* 4021 */ "BITMASK_I64x2\0"
4093
  /* 4035 */ "SHL_I64x2\0"
4094
  /* 4045 */ "MUL_I64x2\0"
4095
  /* 4055 */ "EQ_I64x2\0"
4096
  /* 4064 */ "ABS_I64x2\0"
4097
  /* 4074 */ "GE_S_I64x2\0"
4098
  /* 4085 */ "LE_S_I64x2\0"
4099
  /* 4096 */ "EXTMUL_HIGH_S_I64x2\0"
4100
  /* 4116 */ "SHR_S_I64x2\0"
4101
  /* 4128 */ "GT_S_I64x2\0"
4102
  /* 4139 */ "LT_S_I64x2\0"
4103
  /* 4150 */ "EXTMUL_LOW_S_I64x2\0"
4104
  /* 4169 */ "SPLAT_I64x2\0"
4105
  /* 4181 */ "LANESELECT_I64x2\0"
4106
  /* 4198 */ "EXTMUL_HIGH_U_I64x2\0"
4107
  /* 4218 */ "SHR_U_I64x2\0"
4108
  /* 4230 */ "EXTMUL_LOW_U_I64x2\0"
4109
  /* 4249 */ "extend_high_s_I64x2\0"
4110
  /* 4269 */ "extend_low_s_I64x2\0"
4111
  /* 4288 */ "extend_high_u_I64x2\0"
4112
  /* 4308 */ "extend_low_u_I64x2\0"
4113
  /* 4327 */ "LOAD_F32_A64\0"
4114
  /* 4340 */ "STORE_F32_A64\0"
4115
  /* 4354 */ "ATOMIC_STORE16_I32_A64\0"
4116
  /* 4377 */ "ATOMIC_STORE8_I32_A64\0"
4117
  /* 4399 */ "ATOMIC_RMW16_U_SUB_I32_A64\0"
4118
  /* 4426 */ "ATOMIC_RMW8_U_SUB_I32_A64\0"
4119
  /* 4452 */ "ATOMIC_RMW_SUB_I32_A64\0"
4120
  /* 4475 */ "ATOMIC_LOAD_I32_A64\0"
4121
  /* 4495 */ "ATOMIC_RMW16_U_ADD_I32_A64\0"
4122
  /* 4522 */ "ATOMIC_RMW8_U_ADD_I32_A64\0"
4123
  /* 4548 */ "ATOMIC_RMW_ADD_I32_A64\0"
4124
  /* 4571 */ "ATOMIC_RMW16_U_AND_I32_A64\0"
4125
  /* 4598 */ "ATOMIC_RMW8_U_AND_I32_A64\0"
4126
  /* 4624 */ "ATOMIC_RMW_AND_I32_A64\0"
4127
  /* 4647 */ "ATOMIC_STORE_I32_A64\0"
4128
  /* 4668 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\0"
4129
  /* 4699 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\0"
4130
  /* 4729 */ "ATOMIC_RMW_CMPXCHG_I32_A64\0"
4131
  /* 4756 */ "ATOMIC_RMW16_U_XCHG_I32_A64\0"
4132
  /* 4784 */ "ATOMIC_RMW8_U_XCHG_I32_A64\0"
4133
  /* 4811 */ "ATOMIC_RMW_XCHG_I32_A64\0"
4134
  /* 4835 */ "ATOMIC_RMW16_U_XOR_I32_A64\0"
4135
  /* 4862 */ "ATOMIC_RMW8_U_XOR_I32_A64\0"
4136
  /* 4888 */ "ATOMIC_RMW_XOR_I32_A64\0"
4137
  /* 4911 */ "ATOMIC_RMW16_U_OR_I32_A64\0"
4138
  /* 4937 */ "ATOMIC_RMW8_U_OR_I32_A64\0"
4139
  /* 4962 */ "ATOMIC_RMW_OR_I32_A64\0"
4140
  /* 4984 */ "LOAD16_S_I32_A64\0"
4141
  /* 5001 */ "LOAD8_S_I32_A64\0"
4142
  /* 5017 */ "ATOMIC_LOAD16_U_I32_A64\0"
4143
  /* 5041 */ "ATOMIC_LOAD8_U_I32_A64\0"
4144
  /* 5064 */ "MEMORY_ATOMIC_WAIT32_A64\0"
4145
  /* 5089 */ "LOAD_LANE_I64x2_A64\0"
4146
  /* 5109 */ "STORE_LANE_I64x2_A64\0"
4147
  /* 5130 */ "LOAD_ZERO_I64x2_A64\0"
4148
  /* 5150 */ "LOAD_EXTEND_S_I64x2_A64\0"
4149
  /* 5174 */ "LOAD_EXTEND_U_I64x2_A64\0"
4150
  /* 5198 */ "LOAD_F64_A64\0"
4151
  /* 5211 */ "STORE_F64_A64\0"
4152
  /* 5225 */ "ATOMIC_STORE32_I64_A64\0"
4153
  /* 5248 */ "ATOMIC_STORE16_I64_A64\0"
4154
  /* 5271 */ "ATOMIC_STORE8_I64_A64\0"
4155
  /* 5293 */ "ATOMIC_RMW32_U_SUB_I64_A64\0"
4156
  /* 5320 */ "ATOMIC_RMW16_U_SUB_I64_A64\0"
4157
  /* 5347 */ "ATOMIC_RMW8_U_SUB_I64_A64\0"
4158
  /* 5373 */ "ATOMIC_RMW_SUB_I64_A64\0"
4159
  /* 5396 */ "ATOMIC_LOAD_I64_A64\0"
4160
  /* 5416 */ "ATOMIC_RMW32_U_ADD_I64_A64\0"
4161
  /* 5443 */ "ATOMIC_RMW16_U_ADD_I64_A64\0"
4162
  /* 5470 */ "ATOMIC_RMW8_U_ADD_I64_A64\0"
4163
  /* 5496 */ "ATOMIC_RMW_ADD_I64_A64\0"
4164
  /* 5519 */ "ATOMIC_RMW32_U_AND_I64_A64\0"
4165
  /* 5546 */ "ATOMIC_RMW16_U_AND_I64_A64\0"
4166
  /* 5573 */ "ATOMIC_RMW8_U_AND_I64_A64\0"
4167
  /* 5599 */ "ATOMIC_RMW_AND_I64_A64\0"
4168
  /* 5622 */ "ATOMIC_STORE_I64_A64\0"
4169
  /* 5643 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\0"
4170
  /* 5674 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\0"
4171
  /* 5705 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\0"
4172
  /* 5735 */ "ATOMIC_RMW_CMPXCHG_I64_A64\0"
4173
  /* 5762 */ "ATOMIC_RMW32_U_XCHG_I64_A64\0"
4174
  /* 5790 */ "ATOMIC_RMW16_U_XCHG_I64_A64\0"
4175
  /* 5818 */ "ATOMIC_RMW8_U_XCHG_I64_A64\0"
4176
  /* 5845 */ "ATOMIC_RMW_XCHG_I64_A64\0"
4177
  /* 5869 */ "ATOMIC_RMW32_U_XOR_I64_A64\0"
4178
  /* 5896 */ "ATOMIC_RMW16_U_XOR_I64_A64\0"
4179
  /* 5923 */ "ATOMIC_RMW8_U_XOR_I64_A64\0"
4180
  /* 5949 */ "ATOMIC_RMW_XOR_I64_A64\0"
4181
  /* 5972 */ "ATOMIC_RMW32_U_OR_I64_A64\0"
4182
  /* 5998 */ "ATOMIC_RMW16_U_OR_I64_A64\0"
4183
  /* 6024 */ "ATOMIC_RMW8_U_OR_I64_A64\0"
4184
  /* 6049 */ "ATOMIC_RMW_OR_I64_A64\0"
4185
  /* 6071 */ "LOAD32_S_I64_A64\0"
4186
  /* 6088 */ "LOAD16_S_I64_A64\0"
4187
  /* 6105 */ "LOAD8_S_I64_A64\0"
4188
  /* 6121 */ "ATOMIC_LOAD32_U_I64_A64\0"
4189
  /* 6145 */ "ATOMIC_LOAD16_U_I64_A64\0"
4190
  /* 6169 */ "ATOMIC_LOAD8_U_I64_A64\0"
4191
  /* 6192 */ "MEMORY_ATOMIC_WAIT64_A64\0"
4192
  /* 6217 */ "LOAD_LANE_I32x4_A64\0"
4193
  /* 6237 */ "STORE_LANE_I32x4_A64\0"
4194
  /* 6258 */ "LOAD_ZERO_I32x4_A64\0"
4195
  /* 6278 */ "LOAD_EXTEND_S_I32x4_A64\0"
4196
  /* 6302 */ "LOAD_EXTEND_U_I32x4_A64\0"
4197
  /* 6326 */ "LOAD_LANE_I8x16_A64\0"
4198
  /* 6346 */ "STORE_LANE_I8x16_A64\0"
4199
  /* 6367 */ "LOAD_V128_A64\0"
4200
  /* 6381 */ "STORE_V128_A64\0"
4201
  /* 6396 */ "LOAD_LANE_I16x8_A64\0"
4202
  /* 6416 */ "STORE_LANE_I16x8_A64\0"
4203
  /* 6437 */ "LOAD_EXTEND_S_I16x8_A64\0"
4204
  /* 6461 */ "LOAD_EXTEND_U_I16x8_A64\0"
4205
  /* 6485 */ "anonymous_7278MEMORY_SIZE_A64\0"
4206
  /* 6515 */ "anonymous_7960MEMORY_FILL_A64\0"
4207
  /* 6545 */ "LOAD32_SPLAT_A64\0"
4208
  /* 6562 */ "LOAD64_SPLAT_A64\0"
4209
  /* 6579 */ "LOAD16_SPLAT_A64\0"
4210
  /* 6596 */ "LOAD8_SPLAT_A64\0"
4211
  /* 6612 */ "anonymous_7960MEMORY_INIT_A64\0"
4212
  /* 6642 */ "anonymous_7278MEMORY_GROW_A64\0"
4213
  /* 6672 */ "MEMORY_ATOMIC_NOTIFY_A64\0"
4214
  /* 6697 */ "anonymous_7960MEMORY_COPY_A64\0"
4215
  /* 6727 */ "FP_TO_SINT_I32_F64\0"
4216
  /* 6746 */ "FP_TO_UINT_I32_F64\0"
4217
  /* 6765 */ "FP_TO_SINT_I64_F64\0"
4218
  /* 6784 */ "FP_TO_UINT_I64_F64\0"
4219
  /* 6803 */ "SUB_F64\0"
4220
  /* 6811 */ "TRUNC_F64\0"
4221
  /* 6821 */ "ADD_F64\0"
4222
  /* 6829 */ "LOCAL_TEE_F64\0"
4223
  /* 6843 */ "GE_F64\0"
4224
  /* 6850 */ "LE_F64\0"
4225
  /* 6857 */ "NE_F64\0"
4226
  /* 6864 */ "F32_DEMOTE_F64\0"
4227
  /* 6879 */ "NEG_F64\0"
4228
  /* 6887 */ "CEIL_F64\0"
4229
  /* 6896 */ "MUL_F64\0"
4230
  /* 6904 */ "COPYSIGN_F64\0"
4231
  /* 6917 */ "MIN_F64\0"
4232
  /* 6925 */ "DROP_F64\0"
4233
  /* 6934 */ "EQ_F64\0"
4234
  /* 6941 */ "FLOOR_F64\0"
4235
  /* 6951 */ "ABS_F64\0"
4236
  /* 6959 */ "I32_TRUNC_S_F64\0"
4237
  /* 6975 */ "I64_TRUNC_S_F64\0"
4238
  /* 6991 */ "I32_TRUNC_S_SAT_F64\0"
4239
  /* 7011 */ "I64_TRUNC_S_SAT_F64\0"
4240
  /* 7031 */ "I32_TRUNC_U_SAT_F64\0"
4241
  /* 7051 */ "I64_TRUNC_U_SAT_F64\0"
4242
  /* 7071 */ "SELECT_F64\0"
4243
  /* 7082 */ "GLOBAL_GET_F64\0"
4244
  /* 7097 */ "LOCAL_GET_F64\0"
4245
  /* 7111 */ "I64_REINTERPRET_F64\0"
4246
  /* 7131 */ "GLOBAL_SET_F64\0"
4247
  /* 7146 */ "LOCAL_SET_F64\0"
4248
  /* 7160 */ "GT_F64\0"
4249
  /* 7167 */ "LT_F64\0"
4250
  /* 7174 */ "SQRT_F64\0"
4251
  /* 7183 */ "NEAREST_F64\0"
4252
  /* 7195 */ "CONST_F64\0"
4253
  /* 7205 */ "I32_TRUNC_U_F64\0"
4254
  /* 7221 */ "I64_TRUNC_U_F64\0"
4255
  /* 7237 */ "DIV_F64\0"
4256
  /* 7245 */ "MAX_F64\0"
4257
  /* 7253 */ "COPY_F64\0"
4258
  /* 7262 */ "SUB_I64\0"
4259
  /* 7270 */ "ADD_I64\0"
4260
  /* 7278 */ "AND_I64\0"
4261
  /* 7286 */ "LOCAL_TEE_I64\0"
4262
  /* 7300 */ "BR_TABLE_I64\0"
4263
  /* 7313 */ "NE_I64\0"
4264
  /* 7320 */ "SHL_I64\0"
4265
  /* 7328 */ "ROTL_I64\0"
4266
  /* 7337 */ "MUL_I64\0"
4267
  /* 7345 */ "I32_WRAP_I64\0"
4268
  /* 7358 */ "DROP_I64\0"
4269
  /* 7367 */ "EQ_I64\0"
4270
  /* 7374 */ "XOR_I64\0"
4271
  /* 7382 */ "ROTR_I64\0"
4272
  /* 7391 */ "I64_EXTEND32_S_I64\0"
4273
  /* 7410 */ "I64_EXTEND16_S_I64\0"
4274
  /* 7429 */ "I64_EXTEND8_S_I64\0"
4275
  /* 7447 */ "GE_S_I64\0"
4276
  /* 7456 */ "LE_S_I64\0"
4277
  /* 7465 */ "REM_S_I64\0"
4278
  /* 7475 */ "SHR_S_I64\0"
4279
  /* 7485 */ "GT_S_I64\0"
4280
  /* 7494 */ "LT_S_I64\0"
4281
  /* 7503 */ "F32_CONVERT_S_I64\0"
4282
  /* 7521 */ "F64_CONVERT_S_I64\0"
4283
  /* 7539 */ "DIV_S_I64\0"
4284
  /* 7549 */ "SELECT_I64\0"
4285
  /* 7560 */ "GLOBAL_GET_I64\0"
4286
  /* 7575 */ "LOCAL_GET_I64\0"
4287
  /* 7589 */ "F64_REINTERPRET_I64\0"
4288
  /* 7609 */ "GLOBAL_SET_I64\0"
4289
  /* 7624 */ "LOCAL_SET_I64\0"
4290
  /* 7638 */ "POPCNT_I64\0"
4291
  /* 7649 */ "CONST_I64\0"
4292
  /* 7659 */ "GE_U_I64\0"
4293
  /* 7668 */ "LE_U_I64\0"
4294
  /* 7677 */ "REM_U_I64\0"
4295
  /* 7687 */ "SHR_U_I64\0"
4296
  /* 7697 */ "GT_U_I64\0"
4297
  /* 7706 */ "LT_U_I64\0"
4298
  /* 7715 */ "F32_CONVERT_U_I64\0"
4299
  /* 7733 */ "F64_CONVERT_U_I64\0"
4300
  /* 7751 */ "DIV_U_I64\0"
4301
  /* 7761 */ "COPY_I64\0"
4302
  /* 7770 */ "CLZ_I64\0"
4303
  /* 7778 */ "EQZ_I64\0"
4304
  /* 7786 */ "CTZ_I64\0"
4305
  /* 7794 */ "ARGUMENT_v2f64\0"
4306
  /* 7809 */ "ARGUMENT_f64\0"
4307
  /* 7822 */ "ARGUMENT_v2i64\0"
4308
  /* 7837 */ "ARGUMENT_i64\0"
4309
  /* 7850 */ "CONST_V128_F32x4\0"
4310
  /* 7867 */ "SUB_F32x4\0"
4311
  /* 7877 */ "TRUNC_F32x4\0"
4312
  /* 7889 */ "NMADD_F32x4\0"
4313
  /* 7901 */ "GE_F32x4\0"
4314
  /* 7910 */ "LE_F32x4\0"
4315
  /* 7919 */ "REPLACE_LANE_F32x4\0"
4316
  /* 7938 */ "EXTRACT_LANE_F32x4\0"
4317
  /* 7957 */ "NEG_F32x4\0"
4318
  /* 7967 */ "CEIL_F32x4\0"
4319
  /* 7978 */ "MUL_F32x4\0"
4320
  /* 7988 */ "SIMD_RELAXED_FMIN_F32x4\0"
4321
  /* 8012 */ "PMIN_F32x4\0"
4322
  /* 8023 */ "EQ_F32x4\0"
4323
  /* 8032 */ "FLOOR_F32x4\0"
4324
  /* 8044 */ "ABS_F32x4\0"
4325
  /* 8054 */ "SPLAT_F32x4\0"
4326
  /* 8066 */ "GT_F32x4\0"
4327
  /* 8075 */ "LT_F32x4\0"
4328
  /* 8084 */ "SQRT_F32x4\0"
4329
  /* 8095 */ "NEAREST_F32x4\0"
4330
  /* 8109 */ "DIV_F32x4\0"
4331
  /* 8119 */ "SIMD_RELAXED_FMAX_F32x4\0"
4332
  /* 8143 */ "PMAX_F32x4\0"
4333
  /* 8154 */ "demote_zero_F32x4\0"
4334
  /* 8172 */ "sint_to_fp_F32x4\0"
4335
  /* 8189 */ "uint_to_fp_F32x4\0"
4336
  /* 8206 */ "CONST_V128_I32x4\0"
4337
  /* 8223 */ "SUB_I32x4\0"
4338
  /* 8233 */ "ADD_I32x4\0"
4339
  /* 8243 */ "REPLACE_LANE_I32x4\0"
4340
  /* 8262 */ "EXTRACT_LANE_I32x4\0"
4341
  /* 8281 */ "ALLTRUE_I32x4\0"
4342
  /* 8295 */ "NEG_I32x4\0"
4343
  /* 8305 */ "BITMASK_I32x4\0"
4344
  /* 8319 */ "SHL_I32x4\0"
4345
  /* 8329 */ "MUL_I32x4\0"
4346
  /* 8339 */ "EQ_I32x4\0"
4347
  /* 8348 */ "ABS_I32x4\0"
4348
  /* 8358 */ "GE_S_I32x4\0"
4349
  /* 8369 */ "LE_S_I32x4\0"
4350
  /* 8380 */ "EXTMUL_HIGH_S_I32x4\0"
4351
  /* 8400 */ "MIN_S_I32x4\0"
4352
  /* 8412 */ "SHR_S_I32x4\0"
4353
  /* 8424 */ "GT_S_I32x4\0"
4354
  /* 8435 */ "LT_S_I32x4\0"
4355
  /* 8446 */ "EXTMUL_LOW_S_I32x4\0"
4356
  /* 8465 */ "MAX_S_I32x4\0"
4357
  /* 8477 */ "SPLAT_I32x4\0"
4358
  /* 8489 */ "LANESELECT_I32x4\0"
4359
  /* 8506 */ "GE_U_I32x4\0"
4360
  /* 8517 */ "LE_U_I32x4\0"
4361
  /* 8528 */ "EXTMUL_HIGH_U_I32x4\0"
4362
  /* 8548 */ "MIN_U_I32x4\0"
4363
  /* 8560 */ "SHR_U_I32x4\0"
4364
  /* 8572 */ "GT_U_I32x4\0"
4365
  /* 8583 */ "LT_U_I32x4\0"
4366
  /* 8594 */ "EXTMUL_LOW_U_I32x4\0"
4367
  /* 8613 */ "MAX_U_I32x4\0"
4368
  /* 8625 */ "int_wasm_relaxed_trunc_signed_I32x4\0"
4369
  /* 8661 */ "int_wasm_extadd_pairwise_signed_I32x4\0"
4370
  /* 8699 */ "int_wasm_relaxed_trunc_unsigned_I32x4\0"
4371
  /* 8737 */ "int_wasm_extadd_pairwise_unsigned_I32x4\0"
4372
  /* 8777 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\0"
4373
  /* 8818 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\0"
4374
  /* 8861 */ "extend_high_s_I32x4\0"
4375
  /* 8881 */ "trunc_sat_zero_s_I32x4\0"
4376
  /* 8904 */ "extend_low_s_I32x4\0"
4377
  /* 8923 */ "fp_to_sint_I32x4\0"
4378
  /* 8940 */ "fp_to_uint_I32x4\0"
4379
  /* 8957 */ "extend_high_u_I32x4\0"
4380
  /* 8977 */ "trunc_sat_zero_u_I32x4\0"
4381
  /* 9000 */ "extend_low_u_I32x4\0"
4382
  /* 9019 */ "ARGUMENT_v8i16\0"
4383
  /* 9034 */ "CONST_V128_I8x16\0"
4384
  /* 9051 */ "SUB_I8x16\0"
4385
  /* 9061 */ "ADD_I8x16\0"
4386
  /* 9071 */ "REPLACE_LANE_I8x16\0"
4387
  /* 9090 */ "ALLTRUE_I8x16\0"
4388
  /* 9104 */ "NEG_I8x16\0"
4389
  /* 9114 */ "BITMASK_I8x16\0"
4390
  /* 9128 */ "SHL_I8x16\0"
4391
  /* 9138 */ "EQ_I8x16\0"
4392
  /* 9147 */ "ABS_I8x16\0"
4393
  /* 9157 */ "GE_S_I8x16\0"
4394
  /* 9168 */ "LE_S_I8x16\0"
4395
  /* 9179 */ "MIN_S_I8x16\0"
4396
  /* 9191 */ "SHR_S_I8x16\0"
4397
  /* 9203 */ "SUB_SAT_S_I8x16\0"
4398
  /* 9219 */ "ADD_SAT_S_I8x16\0"
4399
  /* 9235 */ "GT_S_I8x16\0"
4400
  /* 9246 */ "LT_S_I8x16\0"
4401
  /* 9257 */ "NARROW_S_I8x16\0"
4402
  /* 9272 */ "MAX_S_I8x16\0"
4403
  /* 9284 */ "SPLAT_I8x16\0"
4404
  /* 9296 */ "LANESELECT_I8x16\0"
4405
  /* 9313 */ "POPCNT_I8x16\0"
4406
  /* 9326 */ "GE_U_I8x16\0"
4407
  /* 9337 */ "LE_U_I8x16\0"
4408
  /* 9348 */ "MIN_U_I8x16\0"
4409
  /* 9360 */ "AVGR_U_I8x16\0"
4410
  /* 9373 */ "SHR_U_I8x16\0"
4411
  /* 9385 */ "SUB_SAT_U_I8x16\0"
4412
  /* 9401 */ "ADD_SAT_U_I8x16\0"
4413
  /* 9417 */ "GT_U_I8x16\0"
4414
  /* 9428 */ "LT_U_I8x16\0"
4415
  /* 9439 */ "NARROW_U_I8x16\0"
4416
  /* 9454 */ "MAX_U_I8x16\0"
4417
  /* 9466 */ "LOCAL_TEE_V128\0"
4418
  /* 9481 */ "DROP_V128\0"
4419
  /* 9491 */ "SELECT_V128\0"
4420
  /* 9503 */ "GLOBAL_GET_V128\0"
4421
  /* 9519 */ "LOCAL_GET_V128\0"
4422
  /* 9534 */ "GLOBAL_SET_V128\0"
4423
  /* 9550 */ "LOCAL_SET_V128\0"
4424
  /* 9565 */ "COPY_V128\0"
4425
  /* 9575 */ "ARGUMENT_v16i8\0"
4426
  /* 9590 */ "CONST_V128_I16x8\0"
4427
  /* 9607 */ "SUB_I16x8\0"
4428
  /* 9617 */ "ADD_I16x8\0"
4429
  /* 9627 */ "REPLACE_LANE_I16x8\0"
4430
  /* 9646 */ "ALLTRUE_I16x8\0"
4431
  /* 9660 */ "NEG_I16x8\0"
4432
  /* 9670 */ "BITMASK_I16x8\0"
4433
  /* 9684 */ "SHL_I16x8\0"
4434
  /* 9694 */ "MUL_I16x8\0"
4435
  /* 9704 */ "EQ_I16x8\0"
4436
  /* 9713 */ "ABS_I16x8\0"
4437
  /* 9723 */ "GE_S_I16x8\0"
4438
  /* 9734 */ "LE_S_I16x8\0"
4439
  /* 9745 */ "EXTMUL_HIGH_S_I16x8\0"
4440
  /* 9765 */ "MIN_S_I16x8\0"
4441
  /* 9777 */ "SHR_S_I16x8\0"
4442
  /* 9789 */ "RELAXED_Q15MULR_S_I16x8\0"
4443
  /* 9813 */ "SUB_SAT_S_I16x8\0"
4444
  /* 9829 */ "ADD_SAT_S_I16x8\0"
4445
  /* 9845 */ "Q15MULR_SAT_S_I16x8\0"
4446
  /* 9865 */ "GT_S_I16x8\0"
4447
  /* 9876 */ "LT_S_I16x8\0"
4448
  /* 9887 */ "EXTMUL_LOW_S_I16x8\0"
4449
  /* 9906 */ "NARROW_S_I16x8\0"
4450
  /* 9921 */ "MAX_S_I16x8\0"
4451
  /* 9933 */ "SPLAT_I16x8\0"
4452
  /* 9945 */ "LANESELECT_I16x8\0"
4453
  /* 9962 */ "GE_U_I16x8\0"
4454
  /* 9973 */ "LE_U_I16x8\0"
4455
  /* 9984 */ "EXTMUL_HIGH_U_I16x8\0"
4456
  /* 10004 */ "MIN_U_I16x8\0"
4457
  /* 10016 */ "AVGR_U_I16x8\0"
4458
  /* 10029 */ "SHR_U_I16x8\0"
4459
  /* 10041 */ "SUB_SAT_U_I16x8\0"
4460
  /* 10057 */ "ADD_SAT_U_I16x8\0"
4461
  /* 10073 */ "GT_U_I16x8\0"
4462
  /* 10084 */ "LT_U_I16x8\0"
4463
  /* 10095 */ "EXTMUL_LOW_U_I16x8\0"
4464
  /* 10114 */ "NARROW_U_I16x8\0"
4465
  /* 10129 */ "MAX_U_I16x8\0"
4466
  /* 10141 */ "int_wasm_extadd_pairwise_signed_I16x8\0"
4467
  /* 10179 */ "int_wasm_extadd_pairwise_unsigned_I16x8\0"
4468
  /* 10219 */ "extend_high_s_I16x8\0"
4469
  /* 10239 */ "extend_low_s_I16x8\0"
4470
  /* 10258 */ "extend_high_u_I16x8\0"
4471
  /* 10278 */ "extend_low_u_I16x8\0"
4472
  /* 10297 */ "G_FMA\0"
4473
  /* 10303 */ "G_STRICT_FMA\0"
4474
  /* 10316 */ "G_FSUB\0"
4475
  /* 10323 */ "G_STRICT_FSUB\0"
4476
  /* 10337 */ "G_ATOMICRMW_FSUB\0"
4477
  /* 10354 */ "G_SUB\0"
4478
  /* 10360 */ "G_ATOMICRMW_SUB\0"
4479
  /* 10376 */ "G_INTRINSIC\0"
4480
  /* 10388 */ "G_FPTRUNC\0"
4481
  /* 10398 */ "G_INTRINSIC_TRUNC\0"
4482
  /* 10416 */ "G_TRUNC\0"
4483
  /* 10424 */ "G_BUILD_VECTOR_TRUNC\0"
4484
  /* 10445 */ "G_DYN_STACKALLOC\0"
4485
  /* 10462 */ "G_FMAD\0"
4486
  /* 10469 */ "G_INDEXED_SEXTLOAD\0"
4487
  /* 10488 */ "G_SEXTLOAD\0"
4488
  /* 10499 */ "G_INDEXED_ZEXTLOAD\0"
4489
  /* 10518 */ "G_ZEXTLOAD\0"
4490
  /* 10529 */ "G_INDEXED_LOAD\0"
4491
  /* 10544 */ "G_LOAD\0"
4492
  /* 10551 */ "G_VECREDUCE_FADD\0"
4493
  /* 10568 */ "G_FADD\0"
4494
  /* 10575 */ "G_VECREDUCE_SEQ_FADD\0"
4495
  /* 10596 */ "G_STRICT_FADD\0"
4496
  /* 10610 */ "G_ATOMICRMW_FADD\0"
4497
  /* 10627 */ "G_VECREDUCE_ADD\0"
4498
  /* 10643 */ "G_ADD\0"
4499
  /* 10649 */ "G_PTR_ADD\0"
4500
  /* 10659 */ "RELAXED_DOT_ADD\0"
4501
  /* 10675 */ "G_ATOMICRMW_ADD\0"
4502
  /* 10691 */ "G_ATOMICRMW_NAND\0"
4503
  /* 10708 */ "G_VECREDUCE_AND\0"
4504
  /* 10724 */ "G_AND\0"
4505
  /* 10730 */ "G_ATOMICRMW_AND\0"
4506
  /* 10746 */ "LIFETIME_END\0"
4507
  /* 10759 */ "G_BRCOND\0"
4508
  /* 10768 */ "G_LLROUND\0"
4509
  /* 10778 */ "G_LROUND\0"
4510
  /* 10787 */ "G_INTRINSIC_ROUND\0"
4511
  /* 10805 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
4512
  /* 10831 */ "LOAD_STACK_GUARD\0"
4513
  /* 10848 */ "PSEUDO_PROBE\0"
4514
  /* 10861 */ "G_SSUBE\0"
4515
  /* 10869 */ "G_USUBE\0"
4516
  /* 10877 */ "ATOMIC_FENCE\0"
4517
  /* 10890 */ "G_FENCE\0"
4518
  /* 10898 */ "ARITH_FENCE\0"
4519
  /* 10910 */ "COMPILER_FENCE\0"
4520
  /* 10925 */ "REG_SEQUENCE\0"
4521
  /* 10938 */ "G_SADDE\0"
4522
  /* 10946 */ "G_UADDE\0"
4523
  /* 10954 */ "G_GET_FPMODE\0"
4524
  /* 10967 */ "G_RESET_FPMODE\0"
4525
  /* 10982 */ "G_SET_FPMODE\0"
4526
  /* 10995 */ "G_FMINNUM_IEEE\0"
4527
  /* 11010 */ "G_FMAXNUM_IEEE\0"
4528
  /* 11025 */ "DEBUG_UNREACHABLE\0"
4529
  /* 11043 */ "G_JUMP_TABLE\0"
4530
  /* 11056 */ "BUNDLE\0"
4531
  /* 11063 */ "SHUFFLE\0"
4532
  /* 11071 */ "RELAXED_SWIZZLE\0"
4533
  /* 11087 */ "G_MEMCPY_INLINE\0"
4534
  /* 11103 */ "LOCAL_ESCAPE\0"
4535
  /* 11116 */ "G_STACKRESTORE\0"
4536
  /* 11131 */ "G_INDEXED_STORE\0"
4537
  /* 11147 */ "G_STORE\0"
4538
  /* 11155 */ "ELSE\0"
4539
  /* 11160 */ "G_BITREVERSE\0"
4540
  /* 11173 */ "DELEGATE\0"
4541
  /* 11182 */ "DBG_VALUE\0"
4542
  /* 11192 */ "G_GLOBAL_VALUE\0"
4543
  /* 11207 */ "ANYTRUE\0"
4544
  /* 11215 */ "G_STACKSAVE\0"
4545
  /* 11227 */ "G_MEMMOVE\0"
4546
  /* 11237 */ "G_FREEZE\0"
4547
  /* 11246 */ "G_FCANONICALIZE\0"
4548
  /* 11262 */ "TABLE_SIZE\0"
4549
  /* 11273 */ "G_CTLZ_ZERO_UNDEF\0"
4550
  /* 11291 */ "G_CTTZ_ZERO_UNDEF\0"
4551
  /* 11309 */ "G_IMPLICIT_DEF\0"
4552
  /* 11324 */ "LOCAL_TEE_FUNCREF\0"
4553
  /* 11342 */ "TABLE_FILL_FUNCREF\0"
4554
  /* 11361 */ "REF_NULL_FUNCREF\0"
4555
  /* 11378 */ "REF_IS_NULL_FUNCREF\0"
4556
  /* 11398 */ "DROP_FUNCREF\0"
4557
  /* 11411 */ "SELECT_FUNCREF\0"
4558
  /* 11426 */ "TABLE_GET_FUNCREF\0"
4559
  /* 11444 */ "GLOBAL_GET_FUNCREF\0"
4560
  /* 11463 */ "LOCAL_GET_FUNCREF\0"
4561
  /* 11481 */ "TABLE_SET_FUNCREF\0"
4562
  /* 11499 */ "GLOBAL_SET_FUNCREF\0"
4563
  /* 11518 */ "LOCAL_SET_FUNCREF\0"
4564
  /* 11536 */ "TABLE_GROW_FUNCREF\0"
4565
  /* 11555 */ "COPY_FUNCREF\0"
4566
  /* 11568 */ "LOCAL_TEE_EXTERNREF\0"
4567
  /* 11588 */ "TABLE_FILL_EXTERNREF\0"
4568
  /* 11609 */ "REF_NULL_EXTERNREF\0"
4569
  /* 11628 */ "REF_IS_NULL_EXTERNREF\0"
4570
  /* 11650 */ "DROP_EXTERNREF\0"
4571
  /* 11665 */ "SELECT_EXTERNREF\0"
4572
  /* 11682 */ "TABLE_GET_EXTERNREF\0"
4573
  /* 11702 */ "GLOBAL_GET_EXTERNREF\0"
4574
  /* 11723 */ "LOCAL_GET_EXTERNREF\0"
4575
  /* 11743 */ "TABLE_SET_EXTERNREF\0"
4576
  /* 11763 */ "GLOBAL_SET_EXTERNREF\0"
4577
  /* 11784 */ "LOCAL_SET_EXTERNREF\0"
4578
  /* 11804 */ "TABLE_GROW_EXTERNREF\0"
4579
  /* 11825 */ "COPY_EXTERNREF\0"
4580
  /* 11840 */ "DBG_INSTR_REF\0"
4581
  /* 11854 */ "END_IF\0"
4582
  /* 11861 */ "BR_IF\0"
4583
  /* 11867 */ "G_FNEG\0"
4584
  /* 11874 */ "EXTRACT_SUBREG\0"
4585
  /* 11889 */ "INSERT_SUBREG\0"
4586
  /* 11903 */ "G_SEXT_INREG\0"
4587
  /* 11916 */ "SUBREG_TO_REG\0"
4588
  /* 11930 */ "G_ATOMIC_CMPXCHG\0"
4589
  /* 11947 */ "G_ATOMICRMW_XCHG\0"
4590
  /* 11964 */ "G_FLOG\0"
4591
  /* 11971 */ "G_VAARG\0"
4592
  /* 11979 */ "PREALLOCATED_ARG\0"
4593
  /* 11996 */ "CATCH\0"
4594
  /* 12002 */ "G_PREFETCH\0"
4595
  /* 12013 */ "G_SMULH\0"
4596
  /* 12021 */ "G_UMULH\0"
4597
  /* 12029 */ "DBG_PHI\0"
4598
  /* 12037 */ "G_FPTOSI\0"
4599
  /* 12046 */ "G_FPTOUI\0"
4600
  /* 12055 */ "G_FPOWI\0"
4601
  /* 12063 */ "END_BLOCK\0"
4602
  /* 12073 */ "G_PTRMASK\0"
4603
  /* 12083 */ "GC_LABEL\0"
4604
  /* 12092 */ "DBG_LABEL\0"
4605
  /* 12102 */ "EH_LABEL\0"
4606
  /* 12111 */ "ANNOTATION_LABEL\0"
4607
  /* 12128 */ "ICALL_BRANCH_FUNNEL\0"
4608
  /* 12148 */ "G_FSHL\0"
4609
  /* 12155 */ "G_SHL\0"
4610
  /* 12161 */ "G_FCEIL\0"
4611
  /* 12169 */ "PATCHABLE_TAIL_CALL\0"
4612
  /* 12189 */ "RET_CALL\0"
4613
  /* 12198 */ "PATCHABLE_TYPED_EVENT_CALL\0"
4614
  /* 12225 */ "PATCHABLE_EVENT_CALL\0"
4615
  /* 12246 */ "FENTRY_CALL\0"
4616
  /* 12258 */ "CATCH_ALL\0"
4617
  /* 12268 */ "KILL\0"
4618
  /* 12273 */ "G_CONSTANT_POOL\0"
4619
  /* 12289 */ "G_ROTL\0"
4620
  /* 12296 */ "G_VECREDUCE_FMUL\0"
4621
  /* 12313 */ "G_FMUL\0"
4622
  /* 12320 */ "G_VECREDUCE_SEQ_FMUL\0"
4623
  /* 12341 */ "G_STRICT_FMUL\0"
4624
  /* 12355 */ "G_VECREDUCE_MUL\0"
4625
  /* 12371 */ "G_MUL\0"
4626
  /* 12377 */ "G_FREM\0"
4627
  /* 12384 */ "G_STRICT_FREM\0"
4628
  /* 12398 */ "G_SREM\0"
4629
  /* 12405 */ "G_UREM\0"
4630
  /* 12412 */ "G_SDIVREM\0"
4631
  /* 12422 */ "G_UDIVREM\0"
4632
  /* 12432 */ "INLINEASM\0"
4633
  /* 12442 */ "G_VECREDUCE_FMINIMUM\0"
4634
  /* 12463 */ "G_FMINIMUM\0"
4635
  /* 12474 */ "G_VECREDUCE_FMAXIMUM\0"
4636
  /* 12495 */ "G_FMAXIMUM\0"
4637
  /* 12506 */ "G_FMINNUM\0"
4638
  /* 12516 */ "G_FMAXNUM\0"
4639
  /* 12526 */ "G_INTRINSIC_ROUNDEVEN\0"
4640
  /* 12548 */ "G_ASSERT_ALIGN\0"
4641
  /* 12563 */ "G_FCOPYSIGN\0"
4642
  /* 12575 */ "G_VECREDUCE_FMIN\0"
4643
  /* 12592 */ "G_ATOMICRMW_FMIN\0"
4644
  /* 12609 */ "G_VECREDUCE_SMIN\0"
4645
  /* 12626 */ "G_SMIN\0"
4646
  /* 12633 */ "G_VECREDUCE_UMIN\0"
4647
  /* 12650 */ "G_UMIN\0"
4648
  /* 12657 */ "G_ATOMICRMW_UMIN\0"
4649
  /* 12674 */ "G_ATOMICRMW_MIN\0"
4650
  /* 12690 */ "G_FSIN\0"
4651
  /* 12697 */ "END_FUNCTION\0"
4652
  /* 12710 */ "CFI_INSTRUCTION\0"
4653
  /* 12726 */ "FALLTHROUGH_RETURN\0"
4654
  /* 12745 */ "ADJCALLSTACKDOWN\0"
4655
  /* 12762 */ "G_SSUBO\0"
4656
  /* 12770 */ "G_USUBO\0"
4657
  /* 12778 */ "G_SADDO\0"
4658
  /* 12786 */ "G_UADDO\0"
4659
  /* 12794 */ "JUMP_TABLE_DEBUG_INFO\0"
4660
  /* 12816 */ "G_SMULO\0"
4661
  /* 12824 */ "G_UMULO\0"
4662
  /* 12832 */ "G_BZERO\0"
4663
  /* 12840 */ "STACKMAP\0"
4664
  /* 12849 */ "G_ATOMICRMW_UDEC_WRAP\0"
4665
  /* 12871 */ "G_ATOMICRMW_UINC_WRAP\0"
4666
  /* 12893 */ "G_BSWAP\0"
4667
  /* 12901 */ "G_SITOFP\0"
4668
  /* 12910 */ "G_UITOFP\0"
4669
  /* 12919 */ "G_FCMP\0"
4670
  /* 12926 */ "G_ICMP\0"
4671
  /* 12933 */ "NOP\0"
4672
  /* 12937 */ "END_LOOP\0"
4673
  /* 12946 */ "G_CTPOP\0"
4674
  /* 12954 */ "anonymous_7960DATA_DROP\0"
4675
  /* 12978 */ "anonymous_7959DATA_DROP\0"
4676
  /* 13002 */ "PATCHABLE_OP\0"
4677
  /* 13015 */ "FAULTING_OP\0"
4678
  /* 13027 */ "ADJCALLSTACKUP\0"
4679
  /* 13042 */ "PREALLOCATED_SETUP\0"
4680
  /* 13061 */ "G_FLDEXP\0"
4681
  /* 13070 */ "G_STRICT_FLDEXP\0"
4682
  /* 13086 */ "G_FEXP\0"
4683
  /* 13093 */ "G_FFREXP\0"
4684
  /* 13102 */ "G_BR\0"
4685
  /* 13107 */ "INLINEASM_BR\0"
4686
  /* 13120 */ "G_BLOCK_ADDR\0"
4687
  /* 13133 */ "MEMBARRIER\0"
4688
  /* 13144 */ "G_CONSTANT_FOLD_BARRIER\0"
4689
  /* 13168 */ "PATCHABLE_FUNCTION_ENTER\0"
4690
  /* 13193 */ "G_READCYCLECOUNTER\0"
4691
  /* 13212 */ "G_READ_REGISTER\0"
4692
  /* 13228 */ "G_WRITE_REGISTER\0"
4693
  /* 13245 */ "G_ASHR\0"
4694
  /* 13252 */ "G_FSHR\0"
4695
  /* 13259 */ "G_LSHR\0"
4696
  /* 13266 */ "G_FFLOOR\0"
4697
  /* 13275 */ "G_BUILD_VECTOR\0"
4698
  /* 13290 */ "G_SHUFFLE_VECTOR\0"
4699
  /* 13307 */ "G_VECREDUCE_XOR\0"
4700
  /* 13323 */ "G_XOR\0"
4701
  /* 13329 */ "G_ATOMICRMW_XOR\0"
4702
  /* 13345 */ "G_VECREDUCE_OR\0"
4703
  /* 13360 */ "G_OR\0"
4704
  /* 13365 */ "G_ATOMICRMW_OR\0"
4705
  /* 13380 */ "G_ROTR\0"
4706
  /* 13387 */ "G_INTTOPTR\0"
4707
  /* 13398 */ "G_FABS\0"
4708
  /* 13405 */ "G_ABS\0"
4709
  /* 13411 */ "G_UNMERGE_VALUES\0"
4710
  /* 13428 */ "G_MERGE_VALUES\0"
4711
  /* 13443 */ "CALL_PARAMS\0"
4712
  /* 13455 */ "G_FCOS\0"
4713
  /* 13462 */ "G_CONCAT_VECTORS\0"
4714
  /* 13479 */ "COPY_TO_REGCLASS\0"
4715
  /* 13496 */ "G_IS_FPCLASS\0"
4716
  /* 13509 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
4717
  /* 13539 */ "BR_UNLESS\0"
4718
  /* 13549 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
4719
  /* 13576 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
4720
  /* 13614 */ "RET_CALL_RESULTS\0"
4721
  /* 13631 */ "LOAD_F32_A32_S\0"
4722
  /* 13646 */ "STORE_F32_A32_S\0"
4723
  /* 13662 */ "ATOMIC_STORE16_I32_A32_S\0"
4724
  /* 13687 */ "ATOMIC_STORE8_I32_A32_S\0"
4725
  /* 13711 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\0"
4726
  /* 13740 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\0"
4727
  /* 13768 */ "ATOMIC_RMW_SUB_I32_A32_S\0"
4728
  /* 13793 */ "ATOMIC_LOAD_I32_A32_S\0"
4729
  /* 13815 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\0"
4730
  /* 13844 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\0"
4731
  /* 13872 */ "ATOMIC_RMW_ADD_I32_A32_S\0"
4732
  /* 13897 */ "ATOMIC_RMW16_U_AND_I32_A32_S\0"
4733
  /* 13926 */ "ATOMIC_RMW8_U_AND_I32_A32_S\0"
4734
  /* 13954 */ "ATOMIC_RMW_AND_I32_A32_S\0"
4735
  /* 13979 */ "ATOMIC_STORE_I32_A32_S\0"
4736
  /* 14002 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\0"
4737
  /* 14035 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\0"
4738
  /* 14067 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\0"
4739
  /* 14096 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\0"
4740
  /* 14126 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\0"
4741
  /* 14155 */ "ATOMIC_RMW_XCHG_I32_A32_S\0"
4742
  /* 14181 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\0"
4743
  /* 14210 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\0"
4744
  /* 14238 */ "ATOMIC_RMW_XOR_I32_A32_S\0"
4745
  /* 14263 */ "ATOMIC_RMW16_U_OR_I32_A32_S\0"
4746
  /* 14291 */ "ATOMIC_RMW8_U_OR_I32_A32_S\0"
4747
  /* 14318 */ "ATOMIC_RMW_OR_I32_A32_S\0"
4748
  /* 14342 */ "LOAD16_S_I32_A32_S\0"
4749
  /* 14361 */ "LOAD8_S_I32_A32_S\0"
4750
  /* 14379 */ "ATOMIC_LOAD16_U_I32_A32_S\0"
4751
  /* 14405 */ "ATOMIC_LOAD8_U_I32_A32_S\0"
4752
  /* 14430 */ "MEMORY_ATOMIC_WAIT32_A32_S\0"
4753
  /* 14457 */ "LOAD_LANE_I64x2_A32_S\0"
4754
  /* 14479 */ "STORE_LANE_I64x2_A32_S\0"
4755
  /* 14502 */ "LOAD_ZERO_I64x2_A32_S\0"
4756
  /* 14524 */ "LOAD_EXTEND_S_I64x2_A32_S\0"
4757
  /* 14550 */ "LOAD_EXTEND_U_I64x2_A32_S\0"
4758
  /* 14576 */ "LOAD_F64_A32_S\0"
4759
  /* 14591 */ "STORE_F64_A32_S\0"
4760
  /* 14607 */ "ATOMIC_STORE32_I64_A32_S\0"
4761
  /* 14632 */ "ATOMIC_STORE16_I64_A32_S\0"
4762
  /* 14657 */ "ATOMIC_STORE8_I64_A32_S\0"
4763
  /* 14681 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\0"
4764
  /* 14710 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\0"
4765
  /* 14739 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\0"
4766
  /* 14767 */ "ATOMIC_RMW_SUB_I64_A32_S\0"
4767
  /* 14792 */ "ATOMIC_LOAD_I64_A32_S\0"
4768
  /* 14814 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\0"
4769
  /* 14843 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\0"
4770
  /* 14872 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\0"
4771
  /* 14900 */ "ATOMIC_RMW_ADD_I64_A32_S\0"
4772
  /* 14925 */ "ATOMIC_RMW32_U_AND_I64_A32_S\0"
4773
  /* 14954 */ "ATOMIC_RMW16_U_AND_I64_A32_S\0"
4774
  /* 14983 */ "ATOMIC_RMW8_U_AND_I64_A32_S\0"
4775
  /* 15011 */ "ATOMIC_RMW_AND_I64_A32_S\0"
4776
  /* 15036 */ "ATOMIC_STORE_I64_A32_S\0"
4777
  /* 15059 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\0"
4778
  /* 15092 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\0"
4779
  /* 15125 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\0"
4780
  /* 15157 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\0"
4781
  /* 15186 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\0"
4782
  /* 15216 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\0"
4783
  /* 15246 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\0"
4784
  /* 15275 */ "ATOMIC_RMW_XCHG_I64_A32_S\0"
4785
  /* 15301 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\0"
4786
  /* 15330 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\0"
4787
  /* 15359 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\0"
4788
  /* 15387 */ "ATOMIC_RMW_XOR_I64_A32_S\0"
4789
  /* 15412 */ "ATOMIC_RMW32_U_OR_I64_A32_S\0"
4790
  /* 15440 */ "ATOMIC_RMW16_U_OR_I64_A32_S\0"
4791
  /* 15468 */ "ATOMIC_RMW8_U_OR_I64_A32_S\0"
4792
  /* 15495 */ "ATOMIC_RMW_OR_I64_A32_S\0"
4793
  /* 15519 */ "LOAD32_S_I64_A32_S\0"
4794
  /* 15538 */ "LOAD16_S_I64_A32_S\0"
4795
  /* 15557 */ "LOAD8_S_I64_A32_S\0"
4796
  /* 15575 */ "ATOMIC_LOAD32_U_I64_A32_S\0"
4797
  /* 15601 */ "ATOMIC_LOAD16_U_I64_A32_S\0"
4798
  /* 15627 */ "ATOMIC_LOAD8_U_I64_A32_S\0"
4799
  /* 15652 */ "MEMORY_ATOMIC_WAIT64_A32_S\0"
4800
  /* 15679 */ "LOAD_LANE_I32x4_A32_S\0"
4801
  /* 15701 */ "STORE_LANE_I32x4_A32_S\0"
4802
  /* 15724 */ "LOAD_ZERO_I32x4_A32_S\0"
4803
  /* 15746 */ "LOAD_EXTEND_S_I32x4_A32_S\0"
4804
  /* 15772 */ "LOAD_EXTEND_U_I32x4_A32_S\0"
4805
  /* 15798 */ "LOAD_LANE_I8x16_A32_S\0"
4806
  /* 15820 */ "STORE_LANE_I8x16_A32_S\0"
4807
  /* 15843 */ "LOAD_V128_A32_S\0"
4808
  /* 15859 */ "STORE_V128_A32_S\0"
4809
  /* 15876 */ "LOAD_LANE_I16x8_A32_S\0"
4810
  /* 15898 */ "STORE_LANE_I16x8_A32_S\0"
4811
  /* 15921 */ "LOAD_EXTEND_S_I16x8_A32_S\0"
4812
  /* 15947 */ "LOAD_EXTEND_U_I16x8_A32_S\0"
4813
  /* 15973 */ "anonymous_7277MEMORY_SIZE_A32_S\0"
4814
  /* 16005 */ "anonymous_7959MEMORY_FILL_A32_S\0"
4815
  /* 16037 */ "LOAD32_SPLAT_A32_S\0"
4816
  /* 16056 */ "LOAD64_SPLAT_A32_S\0"
4817
  /* 16075 */ "LOAD16_SPLAT_A32_S\0"
4818
  /* 16094 */ "LOAD8_SPLAT_A32_S\0"
4819
  /* 16112 */ "anonymous_7959MEMORY_INIT_A32_S\0"
4820
  /* 16144 */ "anonymous_7277MEMORY_GROW_A32_S\0"
4821
  /* 16176 */ "MEMORY_ATOMIC_NOTIFY_A32_S\0"
4822
  /* 16203 */ "anonymous_7959MEMORY_COPY_A32_S\0"
4823
  /* 16235 */ "FP_TO_SINT_I32_F32_S\0"
4824
  /* 16256 */ "FP_TO_UINT_I32_F32_S\0"
4825
  /* 16277 */ "FP_TO_SINT_I64_F32_S\0"
4826
  /* 16298 */ "FP_TO_UINT_I64_F32_S\0"
4827
  /* 16319 */ "SUB_F32_S\0"
4828
  /* 16329 */ "TRUNC_F32_S\0"
4829
  /* 16341 */ "ADD_F32_S\0"
4830
  /* 16351 */ "LOCAL_TEE_F32_S\0"
4831
  /* 16367 */ "GE_F32_S\0"
4832
  /* 16376 */ "LE_F32_S\0"
4833
  /* 16385 */ "NE_F32_S\0"
4834
  /* 16394 */ "F64_PROMOTE_F32_S\0"
4835
  /* 16412 */ "NEG_F32_S\0"
4836
  /* 16422 */ "CEIL_F32_S\0"
4837
  /* 16433 */ "MUL_F32_S\0"
4838
  /* 16443 */ "COPYSIGN_F32_S\0"
4839
  /* 16458 */ "MIN_F32_S\0"
4840
  /* 16468 */ "DROP_F32_S\0"
4841
  /* 16479 */ "EQ_F32_S\0"
4842
  /* 16488 */ "FLOOR_F32_S\0"
4843
  /* 16500 */ "ABS_F32_S\0"
4844
  /* 16510 */ "I32_TRUNC_S_F32_S\0"
4845
  /* 16528 */ "I64_TRUNC_S_F32_S\0"
4846
  /* 16546 */ "I32_TRUNC_S_SAT_F32_S\0"
4847
  /* 16568 */ "I64_TRUNC_S_SAT_F32_S\0"
4848
  /* 16590 */ "I32_TRUNC_U_SAT_F32_S\0"
4849
  /* 16612 */ "I64_TRUNC_U_SAT_F32_S\0"
4850
  /* 16634 */ "SELECT_F32_S\0"
4851
  /* 16647 */ "GLOBAL_GET_F32_S\0"
4852
  /* 16664 */ "LOCAL_GET_F32_S\0"
4853
  /* 16680 */ "I32_REINTERPRET_F32_S\0"
4854
  /* 16702 */ "GLOBAL_SET_F32_S\0"
4855
  /* 16719 */ "LOCAL_SET_F32_S\0"
4856
  /* 16735 */ "GT_F32_S\0"
4857
  /* 16744 */ "LT_F32_S\0"
4858
  /* 16753 */ "SQRT_F32_S\0"
4859
  /* 16764 */ "NEAREST_F32_S\0"
4860
  /* 16778 */ "CONST_F32_S\0"
4861
  /* 16790 */ "I32_TRUNC_U_F32_S\0"
4862
  /* 16808 */ "I64_TRUNC_U_F32_S\0"
4863
  /* 16826 */ "DIV_F32_S\0"
4864
  /* 16836 */ "MAX_F32_S\0"
4865
  /* 16846 */ "COPY_F32_S\0"
4866
  /* 16857 */ "SUB_I32_S\0"
4867
  /* 16867 */ "ADD_I32_S\0"
4868
  /* 16877 */ "AND_I32_S\0"
4869
  /* 16887 */ "LOCAL_TEE_I32_S\0"
4870
  /* 16903 */ "BR_TABLE_I32_S\0"
4871
  /* 16918 */ "NE_I32_S\0"
4872
  /* 16927 */ "SHL_I32_S\0"
4873
  /* 16937 */ "ROTL_I32_S\0"
4874
  /* 16948 */ "MUL_I32_S\0"
4875
  /* 16958 */ "DROP_I32_S\0"
4876
  /* 16969 */ "EQ_I32_S\0"
4877
  /* 16978 */ "XOR_I32_S\0"
4878
  /* 16988 */ "ROTR_I32_S\0"
4879
  /* 16999 */ "I32_EXTEND16_S_I32_S\0"
4880
  /* 17020 */ "I32_EXTEND8_S_I32_S\0"
4881
  /* 17040 */ "I64_EXTEND_S_I32_S\0"
4882
  /* 17059 */ "GE_S_I32_S\0"
4883
  /* 17070 */ "LE_S_I32_S\0"
4884
  /* 17081 */ "REM_S_I32_S\0"
4885
  /* 17093 */ "SHR_S_I32_S\0"
4886
  /* 17105 */ "GT_S_I32_S\0"
4887
  /* 17116 */ "LT_S_I32_S\0"
4888
  /* 17127 */ "F32_CONVERT_S_I32_S\0"
4889
  /* 17147 */ "F64_CONVERT_S_I32_S\0"
4890
  /* 17167 */ "DIV_S_I32_S\0"
4891
  /* 17179 */ "SELECT_I32_S\0"
4892
  /* 17192 */ "GLOBAL_GET_I32_S\0"
4893
  /* 17209 */ "LOCAL_GET_I32_S\0"
4894
  /* 17225 */ "F32_REINTERPRET_I32_S\0"
4895
  /* 17247 */ "GLOBAL_SET_I32_S\0"
4896
  /* 17264 */ "LOCAL_SET_I32_S\0"
4897
  /* 17280 */ "POPCNT_I32_S\0"
4898
  /* 17293 */ "CONST_I32_S\0"
4899
  /* 17305 */ "I64_EXTEND_U_I32_S\0"
4900
  /* 17324 */ "GE_U_I32_S\0"
4901
  /* 17335 */ "LE_U_I32_S\0"
4902
  /* 17346 */ "REM_U_I32_S\0"
4903
  /* 17358 */ "SHR_U_I32_S\0"
4904
  /* 17370 */ "GT_U_I32_S\0"
4905
  /* 17381 */ "LT_U_I32_S\0"
4906
  /* 17392 */ "F32_CONVERT_U_I32_S\0"
4907
  /* 17412 */ "F64_CONVERT_U_I32_S\0"
4908
  /* 17432 */ "DIV_U_I32_S\0"
4909
  /* 17444 */ "COPY_I32_S\0"
4910
  /* 17455 */ "CLZ_I32_S\0"
4911
  /* 17465 */ "EQZ_I32_S\0"
4912
  /* 17475 */ "CTZ_I32_S\0"
4913
  /* 17485 */ "ARGUMENT_v4f32_S\0"
4914
  /* 17502 */ "ARGUMENT_f32_S\0"
4915
  /* 17517 */ "ARGUMENT_v4i32_S\0"
4916
  /* 17534 */ "ARGUMENT_i32_S\0"
4917
  /* 17549 */ "CONST_V128_F64x2_S\0"
4918
  /* 17568 */ "SUB_F64x2_S\0"
4919
  /* 17580 */ "TRUNC_F64x2_S\0"
4920
  /* 17594 */ "NMADD_F64x2_S\0"
4921
  /* 17608 */ "GE_F64x2_S\0"
4922
  /* 17619 */ "LE_F64x2_S\0"
4923
  /* 17630 */ "REPLACE_LANE_F64x2_S\0"
4924
  /* 17651 */ "EXTRACT_LANE_F64x2_S\0"
4925
  /* 17672 */ "NEG_F64x2_S\0"
4926
  /* 17684 */ "CEIL_F64x2_S\0"
4927
  /* 17697 */ "MUL_F64x2_S\0"
4928
  /* 17709 */ "SIMD_RELAXED_FMIN_F64x2_S\0"
4929
  /* 17735 */ "PMIN_F64x2_S\0"
4930
  /* 17748 */ "EQ_F64x2_S\0"
4931
  /* 17759 */ "FLOOR_F64x2_S\0"
4932
  /* 17773 */ "ABS_F64x2_S\0"
4933
  /* 17785 */ "SPLAT_F64x2_S\0"
4934
  /* 17799 */ "GT_F64x2_S\0"
4935
  /* 17810 */ "LT_F64x2_S\0"
4936
  /* 17821 */ "SQRT_F64x2_S\0"
4937
  /* 17834 */ "NEAREST_F64x2_S\0"
4938
  /* 17850 */ "DIV_F64x2_S\0"
4939
  /* 17862 */ "SIMD_RELAXED_FMAX_F64x2_S\0"
4940
  /* 17888 */ "PMAX_F64x2_S\0"
4941
  /* 17901 */ "convert_low_s_F64x2_S\0"
4942
  /* 17923 */ "convert_low_u_F64x2_S\0"
4943
  /* 17945 */ "promote_low_F64x2_S\0"
4944
  /* 17965 */ "CONST_V128_I64x2_S\0"
4945
  /* 17984 */ "SUB_I64x2_S\0"
4946
  /* 17996 */ "ADD_I64x2_S\0"
4947
  /* 18008 */ "REPLACE_LANE_I64x2_S\0"
4948
  /* 18029 */ "EXTRACT_LANE_I64x2_S\0"
4949
  /* 18050 */ "ALLTRUE_I64x2_S\0"
4950
  /* 18066 */ "NEG_I64x2_S\0"
4951
  /* 18078 */ "BITMASK_I64x2_S\0"
4952
  /* 18094 */ "SHL_I64x2_S\0"
4953
  /* 18106 */ "MUL_I64x2_S\0"
4954
  /* 18118 */ "EQ_I64x2_S\0"
4955
  /* 18129 */ "ABS_I64x2_S\0"
4956
  /* 18141 */ "GE_S_I64x2_S\0"
4957
  /* 18154 */ "LE_S_I64x2_S\0"
4958
  /* 18167 */ "EXTMUL_HIGH_S_I64x2_S\0"
4959
  /* 18189 */ "SHR_S_I64x2_S\0"
4960
  /* 18203 */ "GT_S_I64x2_S\0"
4961
  /* 18216 */ "LT_S_I64x2_S\0"
4962
  /* 18229 */ "EXTMUL_LOW_S_I64x2_S\0"
4963
  /* 18250 */ "SPLAT_I64x2_S\0"
4964
  /* 18264 */ "LANESELECT_I64x2_S\0"
4965
  /* 18283 */ "EXTMUL_HIGH_U_I64x2_S\0"
4966
  /* 18305 */ "SHR_U_I64x2_S\0"
4967
  /* 18319 */ "EXTMUL_LOW_U_I64x2_S\0"
4968
  /* 18340 */ "extend_high_s_I64x2_S\0"
4969
  /* 18362 */ "extend_low_s_I64x2_S\0"
4970
  /* 18383 */ "extend_high_u_I64x2_S\0"
4971
  /* 18405 */ "extend_low_u_I64x2_S\0"
4972
  /* 18426 */ "LOAD_F32_A64_S\0"
4973
  /* 18441 */ "STORE_F32_A64_S\0"
4974
  /* 18457 */ "ATOMIC_STORE16_I32_A64_S\0"
4975
  /* 18482 */ "ATOMIC_STORE8_I32_A64_S\0"
4976
  /* 18506 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\0"
4977
  /* 18535 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\0"
4978
  /* 18563 */ "ATOMIC_RMW_SUB_I32_A64_S\0"
4979
  /* 18588 */ "ATOMIC_LOAD_I32_A64_S\0"
4980
  /* 18610 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\0"
4981
  /* 18639 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\0"
4982
  /* 18667 */ "ATOMIC_RMW_ADD_I32_A64_S\0"
4983
  /* 18692 */ "ATOMIC_RMW16_U_AND_I32_A64_S\0"
4984
  /* 18721 */ "ATOMIC_RMW8_U_AND_I32_A64_S\0"
4985
  /* 18749 */ "ATOMIC_RMW_AND_I32_A64_S\0"
4986
  /* 18774 */ "ATOMIC_STORE_I32_A64_S\0"
4987
  /* 18797 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\0"
4988
  /* 18830 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\0"
4989
  /* 18862 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\0"
4990
  /* 18891 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\0"
4991
  /* 18921 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\0"
4992
  /* 18950 */ "ATOMIC_RMW_XCHG_I32_A64_S\0"
4993
  /* 18976 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\0"
4994
  /* 19005 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\0"
4995
  /* 19033 */ "ATOMIC_RMW_XOR_I32_A64_S\0"
4996
  /* 19058 */ "ATOMIC_RMW16_U_OR_I32_A64_S\0"
4997
  /* 19086 */ "ATOMIC_RMW8_U_OR_I32_A64_S\0"
4998
  /* 19113 */ "ATOMIC_RMW_OR_I32_A64_S\0"
4999
  /* 19137 */ "LOAD16_S_I32_A64_S\0"
5000
  /* 19156 */ "LOAD8_S_I32_A64_S\0"
5001
  /* 19174 */ "ATOMIC_LOAD16_U_I32_A64_S\0"
5002
  /* 19200 */ "ATOMIC_LOAD8_U_I32_A64_S\0"
5003
  /* 19225 */ "MEMORY_ATOMIC_WAIT32_A64_S\0"
5004
  /* 19252 */ "LOAD_LANE_I64x2_A64_S\0"
5005
  /* 19274 */ "STORE_LANE_I64x2_A64_S\0"
5006
  /* 19297 */ "LOAD_ZERO_I64x2_A64_S\0"
5007
  /* 19319 */ "LOAD_EXTEND_S_I64x2_A64_S\0"
5008
  /* 19345 */ "LOAD_EXTEND_U_I64x2_A64_S\0"
5009
  /* 19371 */ "LOAD_F64_A64_S\0"
5010
  /* 19386 */ "STORE_F64_A64_S\0"
5011
  /* 19402 */ "ATOMIC_STORE32_I64_A64_S\0"
5012
  /* 19427 */ "ATOMIC_STORE16_I64_A64_S\0"
5013
  /* 19452 */ "ATOMIC_STORE8_I64_A64_S\0"
5014
  /* 19476 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\0"
5015
  /* 19505 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\0"
5016
  /* 19534 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\0"
5017
  /* 19562 */ "ATOMIC_RMW_SUB_I64_A64_S\0"
5018
  /* 19587 */ "ATOMIC_LOAD_I64_A64_S\0"
5019
  /* 19609 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\0"
5020
  /* 19638 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\0"
5021
  /* 19667 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\0"
5022
  /* 19695 */ "ATOMIC_RMW_ADD_I64_A64_S\0"
5023
  /* 19720 */ "ATOMIC_RMW32_U_AND_I64_A64_S\0"
5024
  /* 19749 */ "ATOMIC_RMW16_U_AND_I64_A64_S\0"
5025
  /* 19778 */ "ATOMIC_RMW8_U_AND_I64_A64_S\0"
5026
  /* 19806 */ "ATOMIC_RMW_AND_I64_A64_S\0"
5027
  /* 19831 */ "ATOMIC_STORE_I64_A64_S\0"
5028
  /* 19854 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\0"
5029
  /* 19887 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\0"
5030
  /* 19920 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\0"
5031
  /* 19952 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\0"
5032
  /* 19981 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\0"
5033
  /* 20011 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\0"
5034
  /* 20041 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\0"
5035
  /* 20070 */ "ATOMIC_RMW_XCHG_I64_A64_S\0"
5036
  /* 20096 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\0"
5037
  /* 20125 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\0"
5038
  /* 20154 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\0"
5039
  /* 20182 */ "ATOMIC_RMW_XOR_I64_A64_S\0"
5040
  /* 20207 */ "ATOMIC_RMW32_U_OR_I64_A64_S\0"
5041
  /* 20235 */ "ATOMIC_RMW16_U_OR_I64_A64_S\0"
5042
  /* 20263 */ "ATOMIC_RMW8_U_OR_I64_A64_S\0"
5043
  /* 20290 */ "ATOMIC_RMW_OR_I64_A64_S\0"
5044
  /* 20314 */ "LOAD32_S_I64_A64_S\0"
5045
  /* 20333 */ "LOAD16_S_I64_A64_S\0"
5046
  /* 20352 */ "LOAD8_S_I64_A64_S\0"
5047
  /* 20370 */ "ATOMIC_LOAD32_U_I64_A64_S\0"
5048
  /* 20396 */ "ATOMIC_LOAD16_U_I64_A64_S\0"
5049
  /* 20422 */ "ATOMIC_LOAD8_U_I64_A64_S\0"
5050
  /* 20447 */ "MEMORY_ATOMIC_WAIT64_A64_S\0"
5051
  /* 20474 */ "LOAD_LANE_I32x4_A64_S\0"
5052
  /* 20496 */ "STORE_LANE_I32x4_A64_S\0"
5053
  /* 20519 */ "LOAD_ZERO_I32x4_A64_S\0"
5054
  /* 20541 */ "LOAD_EXTEND_S_I32x4_A64_S\0"
5055
  /* 20567 */ "LOAD_EXTEND_U_I32x4_A64_S\0"
5056
  /* 20593 */ "LOAD_LANE_I8x16_A64_S\0"
5057
  /* 20615 */ "STORE_LANE_I8x16_A64_S\0"
5058
  /* 20638 */ "LOAD_V128_A64_S\0"
5059
  /* 20654 */ "STORE_V128_A64_S\0"
5060
  /* 20671 */ "LOAD_LANE_I16x8_A64_S\0"
5061
  /* 20693 */ "STORE_LANE_I16x8_A64_S\0"
5062
  /* 20716 */ "LOAD_EXTEND_S_I16x8_A64_S\0"
5063
  /* 20742 */ "LOAD_EXTEND_U_I16x8_A64_S\0"
5064
  /* 20768 */ "anonymous_7278MEMORY_SIZE_A64_S\0"
5065
  /* 20800 */ "anonymous_7960MEMORY_FILL_A64_S\0"
5066
  /* 20832 */ "LOAD32_SPLAT_A64_S\0"
5067
  /* 20851 */ "LOAD64_SPLAT_A64_S\0"
5068
  /* 20870 */ "LOAD16_SPLAT_A64_S\0"
5069
  /* 20889 */ "LOAD8_SPLAT_A64_S\0"
5070
  /* 20907 */ "anonymous_7960MEMORY_INIT_A64_S\0"
5071
  /* 20939 */ "anonymous_7278MEMORY_GROW_A64_S\0"
5072
  /* 20971 */ "MEMORY_ATOMIC_NOTIFY_A64_S\0"
5073
  /* 20998 */ "anonymous_7960MEMORY_COPY_A64_S\0"
5074
  /* 21030 */ "FP_TO_SINT_I32_F64_S\0"
5075
  /* 21051 */ "FP_TO_UINT_I32_F64_S\0"
5076
  /* 21072 */ "FP_TO_SINT_I64_F64_S\0"
5077
  /* 21093 */ "FP_TO_UINT_I64_F64_S\0"
5078
  /* 21114 */ "SUB_F64_S\0"
5079
  /* 21124 */ "TRUNC_F64_S\0"
5080
  /* 21136 */ "ADD_F64_S\0"
5081
  /* 21146 */ "LOCAL_TEE_F64_S\0"
5082
  /* 21162 */ "GE_F64_S\0"
5083
  /* 21171 */ "LE_F64_S\0"
5084
  /* 21180 */ "NE_F64_S\0"
5085
  /* 21189 */ "F32_DEMOTE_F64_S\0"
5086
  /* 21206 */ "NEG_F64_S\0"
5087
  /* 21216 */ "CEIL_F64_S\0"
5088
  /* 21227 */ "MUL_F64_S\0"
5089
  /* 21237 */ "COPYSIGN_F64_S\0"
5090
  /* 21252 */ "MIN_F64_S\0"
5091
  /* 21262 */ "DROP_F64_S\0"
5092
  /* 21273 */ "EQ_F64_S\0"
5093
  /* 21282 */ "FLOOR_F64_S\0"
5094
  /* 21294 */ "ABS_F64_S\0"
5095
  /* 21304 */ "I32_TRUNC_S_F64_S\0"
5096
  /* 21322 */ "I64_TRUNC_S_F64_S\0"
5097
  /* 21340 */ "I32_TRUNC_S_SAT_F64_S\0"
5098
  /* 21362 */ "I64_TRUNC_S_SAT_F64_S\0"
5099
  /* 21384 */ "I32_TRUNC_U_SAT_F64_S\0"
5100
  /* 21406 */ "I64_TRUNC_U_SAT_F64_S\0"
5101
  /* 21428 */ "SELECT_F64_S\0"
5102
  /* 21441 */ "GLOBAL_GET_F64_S\0"
5103
  /* 21458 */ "LOCAL_GET_F64_S\0"
5104
  /* 21474 */ "I64_REINTERPRET_F64_S\0"
5105
  /* 21496 */ "GLOBAL_SET_F64_S\0"
5106
  /* 21513 */ "LOCAL_SET_F64_S\0"
5107
  /* 21529 */ "GT_F64_S\0"
5108
  /* 21538 */ "LT_F64_S\0"
5109
  /* 21547 */ "SQRT_F64_S\0"
5110
  /* 21558 */ "NEAREST_F64_S\0"
5111
  /* 21572 */ "CONST_F64_S\0"
5112
  /* 21584 */ "I32_TRUNC_U_F64_S\0"
5113
  /* 21602 */ "I64_TRUNC_U_F64_S\0"
5114
  /* 21620 */ "DIV_F64_S\0"
5115
  /* 21630 */ "MAX_F64_S\0"
5116
  /* 21640 */ "COPY_F64_S\0"
5117
  /* 21651 */ "SUB_I64_S\0"
5118
  /* 21661 */ "ADD_I64_S\0"
5119
  /* 21671 */ "AND_I64_S\0"
5120
  /* 21681 */ "LOCAL_TEE_I64_S\0"
5121
  /* 21697 */ "BR_TABLE_I64_S\0"
5122
  /* 21712 */ "NE_I64_S\0"
5123
  /* 21721 */ "SHL_I64_S\0"
5124
  /* 21731 */ "ROTL_I64_S\0"
5125
  /* 21742 */ "MUL_I64_S\0"
5126
  /* 21752 */ "I32_WRAP_I64_S\0"
5127
  /* 21767 */ "DROP_I64_S\0"
5128
  /* 21778 */ "EQ_I64_S\0"
5129
  /* 21787 */ "XOR_I64_S\0"
5130
  /* 21797 */ "ROTR_I64_S\0"
5131
  /* 21808 */ "I64_EXTEND32_S_I64_S\0"
5132
  /* 21829 */ "I64_EXTEND16_S_I64_S\0"
5133
  /* 21850 */ "I64_EXTEND8_S_I64_S\0"
5134
  /* 21870 */ "GE_S_I64_S\0"
5135
  /* 21881 */ "LE_S_I64_S\0"
5136
  /* 21892 */ "REM_S_I64_S\0"
5137
  /* 21904 */ "SHR_S_I64_S\0"
5138
  /* 21916 */ "GT_S_I64_S\0"
5139
  /* 21927 */ "LT_S_I64_S\0"
5140
  /* 21938 */ "F32_CONVERT_S_I64_S\0"
5141
  /* 21958 */ "F64_CONVERT_S_I64_S\0"
5142
  /* 21978 */ "DIV_S_I64_S\0"
5143
  /* 21990 */ "SELECT_I64_S\0"
5144
  /* 22003 */ "GLOBAL_GET_I64_S\0"
5145
  /* 22020 */ "LOCAL_GET_I64_S\0"
5146
  /* 22036 */ "F64_REINTERPRET_I64_S\0"
5147
  /* 22058 */ "GLOBAL_SET_I64_S\0"
5148
  /* 22075 */ "LOCAL_SET_I64_S\0"
5149
  /* 22091 */ "POPCNT_I64_S\0"
5150
  /* 22104 */ "CONST_I64_S\0"
5151
  /* 22116 */ "GE_U_I64_S\0"
5152
  /* 22127 */ "LE_U_I64_S\0"
5153
  /* 22138 */ "REM_U_I64_S\0"
5154
  /* 22150 */ "SHR_U_I64_S\0"
5155
  /* 22162 */ "GT_U_I64_S\0"
5156
  /* 22173 */ "LT_U_I64_S\0"
5157
  /* 22184 */ "F32_CONVERT_U_I64_S\0"
5158
  /* 22204 */ "F64_CONVERT_U_I64_S\0"
5159
  /* 22224 */ "DIV_U_I64_S\0"
5160
  /* 22236 */ "COPY_I64_S\0"
5161
  /* 22247 */ "CLZ_I64_S\0"
5162
  /* 22257 */ "EQZ_I64_S\0"
5163
  /* 22267 */ "CTZ_I64_S\0"
5164
  /* 22277 */ "ARGUMENT_v2f64_S\0"
5165
  /* 22294 */ "ARGUMENT_f64_S\0"
5166
  /* 22309 */ "ARGUMENT_v2i64_S\0"
5167
  /* 22326 */ "ARGUMENT_i64_S\0"
5168
  /* 22341 */ "CONST_V128_F32x4_S\0"
5169
  /* 22360 */ "SUB_F32x4_S\0"
5170
  /* 22372 */ "TRUNC_F32x4_S\0"
5171
  /* 22386 */ "NMADD_F32x4_S\0"
5172
  /* 22400 */ "GE_F32x4_S\0"
5173
  /* 22411 */ "LE_F32x4_S\0"
5174
  /* 22422 */ "REPLACE_LANE_F32x4_S\0"
5175
  /* 22443 */ "EXTRACT_LANE_F32x4_S\0"
5176
  /* 22464 */ "NEG_F32x4_S\0"
5177
  /* 22476 */ "CEIL_F32x4_S\0"
5178
  /* 22489 */ "MUL_F32x4_S\0"
5179
  /* 22501 */ "SIMD_RELAXED_FMIN_F32x4_S\0"
5180
  /* 22527 */ "PMIN_F32x4_S\0"
5181
  /* 22540 */ "EQ_F32x4_S\0"
5182
  /* 22551 */ "FLOOR_F32x4_S\0"
5183
  /* 22565 */ "ABS_F32x4_S\0"
5184
  /* 22577 */ "SPLAT_F32x4_S\0"
5185
  /* 22591 */ "GT_F32x4_S\0"
5186
  /* 22602 */ "LT_F32x4_S\0"
5187
  /* 22613 */ "SQRT_F32x4_S\0"
5188
  /* 22626 */ "NEAREST_F32x4_S\0"
5189
  /* 22642 */ "DIV_F32x4_S\0"
5190
  /* 22654 */ "SIMD_RELAXED_FMAX_F32x4_S\0"
5191
  /* 22680 */ "PMAX_F32x4_S\0"
5192
  /* 22693 */ "demote_zero_F32x4_S\0"
5193
  /* 22713 */ "sint_to_fp_F32x4_S\0"
5194
  /* 22732 */ "uint_to_fp_F32x4_S\0"
5195
  /* 22751 */ "CONST_V128_I32x4_S\0"
5196
  /* 22770 */ "SUB_I32x4_S\0"
5197
  /* 22782 */ "ADD_I32x4_S\0"
5198
  /* 22794 */ "REPLACE_LANE_I32x4_S\0"
5199
  /* 22815 */ "EXTRACT_LANE_I32x4_S\0"
5200
  /* 22836 */ "ALLTRUE_I32x4_S\0"
5201
  /* 22852 */ "NEG_I32x4_S\0"
5202
  /* 22864 */ "BITMASK_I32x4_S\0"
5203
  /* 22880 */ "SHL_I32x4_S\0"
5204
  /* 22892 */ "MUL_I32x4_S\0"
5205
  /* 22904 */ "EQ_I32x4_S\0"
5206
  /* 22915 */ "ABS_I32x4_S\0"
5207
  /* 22927 */ "GE_S_I32x4_S\0"
5208
  /* 22940 */ "LE_S_I32x4_S\0"
5209
  /* 22953 */ "EXTMUL_HIGH_S_I32x4_S\0"
5210
  /* 22975 */ "MIN_S_I32x4_S\0"
5211
  /* 22989 */ "SHR_S_I32x4_S\0"
5212
  /* 23003 */ "GT_S_I32x4_S\0"
5213
  /* 23016 */ "LT_S_I32x4_S\0"
5214
  /* 23029 */ "EXTMUL_LOW_S_I32x4_S\0"
5215
  /* 23050 */ "MAX_S_I32x4_S\0"
5216
  /* 23064 */ "SPLAT_I32x4_S\0"
5217
  /* 23078 */ "LANESELECT_I32x4_S\0"
5218
  /* 23097 */ "GE_U_I32x4_S\0"
5219
  /* 23110 */ "LE_U_I32x4_S\0"
5220
  /* 23123 */ "EXTMUL_HIGH_U_I32x4_S\0"
5221
  /* 23145 */ "MIN_U_I32x4_S\0"
5222
  /* 23159 */ "SHR_U_I32x4_S\0"
5223
  /* 23173 */ "GT_U_I32x4_S\0"
5224
  /* 23186 */ "LT_U_I32x4_S\0"
5225
  /* 23199 */ "EXTMUL_LOW_U_I32x4_S\0"
5226
  /* 23220 */ "MAX_U_I32x4_S\0"
5227
  /* 23234 */ "int_wasm_relaxed_trunc_signed_I32x4_S\0"
5228
  /* 23272 */ "int_wasm_extadd_pairwise_signed_I32x4_S\0"
5229
  /* 23312 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\0"
5230
  /* 23352 */ "int_wasm_extadd_pairwise_unsigned_I32x4_S\0"
5231
  /* 23394 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\0"
5232
  /* 23437 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\0"
5233
  /* 23482 */ "extend_high_s_I32x4_S\0"
5234
  /* 23504 */ "trunc_sat_zero_s_I32x4_S\0"
5235
  /* 23529 */ "extend_low_s_I32x4_S\0"
5236
  /* 23550 */ "fp_to_sint_I32x4_S\0"
5237
  /* 23569 */ "fp_to_uint_I32x4_S\0"
5238
  /* 23588 */ "extend_high_u_I32x4_S\0"
5239
  /* 23610 */ "trunc_sat_zero_u_I32x4_S\0"
5240
  /* 23635 */ "extend_low_u_I32x4_S\0"
5241
  /* 23656 */ "ARGUMENT_v8i16_S\0"
5242
  /* 23673 */ "CONST_V128_I8x16_S\0"
5243
  /* 23692 */ "SUB_I8x16_S\0"
5244
  /* 23704 */ "ADD_I8x16_S\0"
5245
  /* 23716 */ "REPLACE_LANE_I8x16_S\0"
5246
  /* 23737 */ "ALLTRUE_I8x16_S\0"
5247
  /* 23753 */ "NEG_I8x16_S\0"
5248
  /* 23765 */ "BITMASK_I8x16_S\0"
5249
  /* 23781 */ "SHL_I8x16_S\0"
5250
  /* 23793 */ "EQ_I8x16_S\0"
5251
  /* 23804 */ "ABS_I8x16_S\0"
5252
  /* 23816 */ "GE_S_I8x16_S\0"
5253
  /* 23829 */ "LE_S_I8x16_S\0"
5254
  /* 23842 */ "MIN_S_I8x16_S\0"
5255
  /* 23856 */ "SHR_S_I8x16_S\0"
5256
  /* 23870 */ "SUB_SAT_S_I8x16_S\0"
5257
  /* 23888 */ "ADD_SAT_S_I8x16_S\0"
5258
  /* 23906 */ "GT_S_I8x16_S\0"
5259
  /* 23919 */ "LT_S_I8x16_S\0"
5260
  /* 23932 */ "NARROW_S_I8x16_S\0"
5261
  /* 23949 */ "MAX_S_I8x16_S\0"
5262
  /* 23963 */ "SPLAT_I8x16_S\0"
5263
  /* 23977 */ "LANESELECT_I8x16_S\0"
5264
  /* 23996 */ "POPCNT_I8x16_S\0"
5265
  /* 24011 */ "GE_U_I8x16_S\0"
5266
  /* 24024 */ "LE_U_I8x16_S\0"
5267
  /* 24037 */ "MIN_U_I8x16_S\0"
5268
  /* 24051 */ "AVGR_U_I8x16_S\0"
5269
  /* 24066 */ "SHR_U_I8x16_S\0"
5270
  /* 24080 */ "SUB_SAT_U_I8x16_S\0"
5271
  /* 24098 */ "ADD_SAT_U_I8x16_S\0"
5272
  /* 24116 */ "GT_U_I8x16_S\0"
5273
  /* 24129 */ "LT_U_I8x16_S\0"
5274
  /* 24142 */ "NARROW_U_I8x16_S\0"
5275
  /* 24159 */ "MAX_U_I8x16_S\0"
5276
  /* 24173 */ "LOCAL_TEE_V128_S\0"
5277
  /* 24190 */ "DROP_V128_S\0"
5278
  /* 24202 */ "SELECT_V128_S\0"
5279
  /* 24216 */ "GLOBAL_GET_V128_S\0"
5280
  /* 24234 */ "LOCAL_GET_V128_S\0"
5281
  /* 24251 */ "GLOBAL_SET_V128_S\0"
5282
  /* 24269 */ "LOCAL_SET_V128_S\0"
5283
  /* 24286 */ "COPY_V128_S\0"
5284
  /* 24298 */ "ARGUMENT_v16i8_S\0"
5285
  /* 24315 */ "CONST_V128_I16x8_S\0"
5286
  /* 24334 */ "SUB_I16x8_S\0"
5287
  /* 24346 */ "ADD_I16x8_S\0"
5288
  /* 24358 */ "REPLACE_LANE_I16x8_S\0"
5289
  /* 24379 */ "ALLTRUE_I16x8_S\0"
5290
  /* 24395 */ "NEG_I16x8_S\0"
5291
  /* 24407 */ "BITMASK_I16x8_S\0"
5292
  /* 24423 */ "SHL_I16x8_S\0"
5293
  /* 24435 */ "MUL_I16x8_S\0"
5294
  /* 24447 */ "EQ_I16x8_S\0"
5295
  /* 24458 */ "ABS_I16x8_S\0"
5296
  /* 24470 */ "GE_S_I16x8_S\0"
5297
  /* 24483 */ "LE_S_I16x8_S\0"
5298
  /* 24496 */ "EXTMUL_HIGH_S_I16x8_S\0"
5299
  /* 24518 */ "MIN_S_I16x8_S\0"
5300
  /* 24532 */ "SHR_S_I16x8_S\0"
5301
  /* 24546 */ "RELAXED_Q15MULR_S_I16x8_S\0"
5302
  /* 24572 */ "SUB_SAT_S_I16x8_S\0"
5303
  /* 24590 */ "ADD_SAT_S_I16x8_S\0"
5304
  /* 24608 */ "Q15MULR_SAT_S_I16x8_S\0"
5305
  /* 24630 */ "GT_S_I16x8_S\0"
5306
  /* 24643 */ "LT_S_I16x8_S\0"
5307
  /* 24656 */ "EXTMUL_LOW_S_I16x8_S\0"
5308
  /* 24677 */ "NARROW_S_I16x8_S\0"
5309
  /* 24694 */ "MAX_S_I16x8_S\0"
5310
  /* 24708 */ "SPLAT_I16x8_S\0"
5311
  /* 24722 */ "LANESELECT_I16x8_S\0"
5312
  /* 24741 */ "GE_U_I16x8_S\0"
5313
  /* 24754 */ "LE_U_I16x8_S\0"
5314
  /* 24767 */ "EXTMUL_HIGH_U_I16x8_S\0"
5315
  /* 24789 */ "MIN_U_I16x8_S\0"
5316
  /* 24803 */ "AVGR_U_I16x8_S\0"
5317
  /* 24818 */ "SHR_U_I16x8_S\0"
5318
  /* 24832 */ "SUB_SAT_U_I16x8_S\0"
5319
  /* 24850 */ "ADD_SAT_U_I16x8_S\0"
5320
  /* 24868 */ "GT_U_I16x8_S\0"
5321
  /* 24881 */ "LT_U_I16x8_S\0"
5322
  /* 24894 */ "EXTMUL_LOW_U_I16x8_S\0"
5323
  /* 24915 */ "NARROW_U_I16x8_S\0"
5324
  /* 24932 */ "MAX_U_I16x8_S\0"
5325
  /* 24946 */ "int_wasm_extadd_pairwise_signed_I16x8_S\0"
5326
  /* 24986 */ "int_wasm_extadd_pairwise_unsigned_I16x8_S\0"
5327
  /* 25028 */ "extend_high_s_I16x8_S\0"
5328
  /* 25050 */ "extend_low_s_I16x8_S\0"
5329
  /* 25071 */ "extend_high_u_I16x8_S\0"
5330
  /* 25093 */ "extend_low_u_I16x8_S\0"
5331
  /* 25114 */ "RELAXED_DOT_ADD_S\0"
5332
  /* 25132 */ "AND_S\0"
5333
  /* 25138 */ "END_S\0"
5334
  /* 25144 */ "ATOMIC_FENCE_S\0"
5335
  /* 25159 */ "COMPILER_FENCE_S\0"
5336
  /* 25176 */ "DEBUG_UNREACHABLE_S\0"
5337
  /* 25196 */ "SHUFFLE_S\0"
5338
  /* 25206 */ "RELAXED_SWIZZLE_S\0"
5339
  /* 25224 */ "ELSE_S\0"
5340
  /* 25231 */ "DELEGATE_S\0"
5341
  /* 25242 */ "ANYTRUE_S\0"
5342
  /* 25252 */ "TABLE_SIZE_S\0"
5343
  /* 25265 */ "LOCAL_TEE_FUNCREF_S\0"
5344
  /* 25285 */ "TABLE_FILL_FUNCREF_S\0"
5345
  /* 25306 */ "REF_NULL_FUNCREF_S\0"
5346
  /* 25325 */ "REF_IS_NULL_FUNCREF_S\0"
5347
  /* 25347 */ "DROP_FUNCREF_S\0"
5348
  /* 25362 */ "SELECT_FUNCREF_S\0"
5349
  /* 25379 */ "TABLE_GET_FUNCREF_S\0"
5350
  /* 25399 */ "GLOBAL_GET_FUNCREF_S\0"
5351
  /* 25420 */ "LOCAL_GET_FUNCREF_S\0"
5352
  /* 25440 */ "TABLE_SET_FUNCREF_S\0"
5353
  /* 25460 */ "GLOBAL_SET_FUNCREF_S\0"
5354
  /* 25481 */ "LOCAL_SET_FUNCREF_S\0"
5355
  /* 25501 */ "TABLE_GROW_FUNCREF_S\0"
5356
  /* 25522 */ "COPY_FUNCREF_S\0"
5357
  /* 25537 */ "LOCAL_TEE_EXTERNREF_S\0"
5358
  /* 25559 */ "TABLE_FILL_EXTERNREF_S\0"
5359
  /* 25582 */ "REF_NULL_EXTERNREF_S\0"
5360
  /* 25603 */ "REF_IS_NULL_EXTERNREF_S\0"
5361
  /* 25627 */ "DROP_EXTERNREF_S\0"
5362
  /* 25644 */ "SELECT_EXTERNREF_S\0"
5363
  /* 25663 */ "TABLE_GET_EXTERNREF_S\0"
5364
  /* 25685 */ "GLOBAL_GET_EXTERNREF_S\0"
5365
  /* 25708 */ "LOCAL_GET_EXTERNREF_S\0"
5366
  /* 25730 */ "TABLE_SET_EXTERNREF_S\0"
5367
  /* 25752 */ "GLOBAL_SET_EXTERNREF_S\0"
5368
  /* 25775 */ "LOCAL_SET_EXTERNREF_S\0"
5369
  /* 25797 */ "TABLE_GROW_EXTERNREF_S\0"
5370
  /* 25820 */ "COPY_EXTERNREF_S\0"
5371
  /* 25837 */ "END_IF_S\0"
5372
  /* 25846 */ "BR_IF_S\0"
5373
  /* 25854 */ "CATCH_S\0"
5374
  /* 25862 */ "END_BLOCK_S\0"
5375
  /* 25874 */ "RET_CALL_S\0"
5376
  /* 25885 */ "CATCH_ALL_S\0"
5377
  /* 25897 */ "END_FUNCTION_S\0"
5378
  /* 25912 */ "FALLTHROUGH_RETURN_S\0"
5379
  /* 25933 */ "ADJCALLSTACKDOWN_S\0"
5380
  /* 25952 */ "NOP_S\0"
5381
  /* 25958 */ "END_LOOP_S\0"
5382
  /* 25969 */ "anonymous_7960DATA_DROP_S\0"
5383
  /* 25995 */ "anonymous_7959DATA_DROP_S\0"
5384
  /* 26021 */ "ADJCALLSTACKUP_S\0"
5385
  /* 26038 */ "BR_S\0"
5386
  /* 26043 */ "XOR_S\0"
5387
  /* 26049 */ "CALL_PARAMS_S\0"
5388
  /* 26063 */ "BR_UNLESS_S\0"
5389
  /* 26075 */ "RET_CALL_RESULTS_S\0"
5390
  /* 26094 */ "RELAXED_DOT_BFLOAT_S\0"
5391
  /* 26115 */ "BITSELECT_S\0"
5392
  /* 26127 */ "RET_CALL_INDIRECT_S\0"
5393
  /* 26147 */ "CATCHRET_S\0"
5394
  /* 26158 */ "CLEANUPRET_S\0"
5395
  /* 26171 */ "RELAXED_DOT_S\0"
5396
  /* 26185 */ "ANDNOT_S\0"
5397
  /* 26194 */ "RETHROW_S\0"
5398
  /* 26204 */ "TABLE_COPY_S\0"
5399
  /* 26217 */ "END_TRY_S\0"
5400
  /* 26227 */ "ARGUMENT_funcref_S\0"
5401
  /* 26246 */ "ARGUMENT_externref_S\0"
5402
  /* 26267 */ "EXTRACT_LANE_I8x16_s_S\0"
5403
  /* 26290 */ "EXTRACT_LANE_I16x8_s_S\0"
5404
  /* 26313 */ "EXTRACT_LANE_I8x16_u_S\0"
5405
  /* 26336 */ "EXTRACT_LANE_I16x8_u_S\0"
5406
  /* 26359 */ "RELAXED_DOT_BFLOAT\0"
5407
  /* 26378 */ "G_SSUBSAT\0"
5408
  /* 26388 */ "G_USUBSAT\0"
5409
  /* 26398 */ "G_SADDSAT\0"
5410
  /* 26408 */ "G_UADDSAT\0"
5411
  /* 26418 */ "G_SSHLSAT\0"
5412
  /* 26428 */ "G_USHLSAT\0"
5413
  /* 26438 */ "G_SMULFIXSAT\0"
5414
  /* 26451 */ "G_UMULFIXSAT\0"
5415
  /* 26464 */ "G_SDIVFIXSAT\0"
5416
  /* 26477 */ "G_UDIVFIXSAT\0"
5417
  /* 26490 */ "G_EXTRACT\0"
5418
  /* 26500 */ "BITSELECT\0"
5419
  /* 26510 */ "G_SELECT\0"
5420
  /* 26519 */ "G_BRINDIRECT\0"
5421
  /* 26532 */ "RET_CALL_INDIRECT\0"
5422
  /* 26550 */ "CATCHRET\0"
5423
  /* 26559 */ "CLEANUPRET\0"
5424
  /* 26570 */ "PATCHABLE_RET\0"
5425
  /* 26584 */ "G_MEMSET\0"
5426
  /* 26593 */ "PATCHABLE_FUNCTION_EXIT\0"
5427
  /* 26617 */ "G_BRJT\0"
5428
  /* 26624 */ "G_EXTRACT_VECTOR_ELT\0"
5429
  /* 26645 */ "G_INSERT_VECTOR_ELT\0"
5430
  /* 26665 */ "G_FCONSTANT\0"
5431
  /* 26677 */ "G_CONSTANT\0"
5432
  /* 26688 */ "G_INTRINSIC_CONVERGENT\0"
5433
  /* 26711 */ "STATEPOINT\0"
5434
  /* 26722 */ "PATCHPOINT\0"
5435
  /* 26733 */ "G_PTRTOINT\0"
5436
  /* 26744 */ "G_FRINT\0"
5437
  /* 26752 */ "G_INTRINSIC_LRINT\0"
5438
  /* 26770 */ "G_FNEARBYINT\0"
5439
  /* 26783 */ "RELAXED_DOT\0"
5440
  /* 26795 */ "ANDNOT\0"
5441
  /* 26802 */ "G_VASTART\0"
5442
  /* 26812 */ "LIFETIME_START\0"
5443
  /* 26827 */ "G_INVOKE_REGION_START\0"
5444
  /* 26849 */ "G_INSERT\0"
5445
  /* 26858 */ "G_FSQRT\0"
5446
  /* 26866 */ "G_STRICT_FSQRT\0"
5447
  /* 26881 */ "G_BITCAST\0"
5448
  /* 26891 */ "G_ADDRSPACE_CAST\0"
5449
  /* 26908 */ "DBG_VALUE_LIST\0"
5450
  /* 26923 */ "G_FPEXT\0"
5451
  /* 26931 */ "G_SEXT\0"
5452
  /* 26938 */ "G_ASSERT_SEXT\0"
5453
  /* 26952 */ "G_ANYEXT\0"
5454
  /* 26961 */ "G_ZEXT\0"
5455
  /* 26968 */ "G_ASSERT_ZEXT\0"
5456
  /* 26982 */ "G_FDIV\0"
5457
  /* 26989 */ "G_STRICT_FDIV\0"
5458
  /* 27003 */ "G_SDIV\0"
5459
  /* 27010 */ "G_UDIV\0"
5460
  /* 27017 */ "G_GET_FPENV\0"
5461
  /* 27029 */ "G_RESET_FPENV\0"
5462
  /* 27043 */ "G_SET_FPENV\0"
5463
  /* 27055 */ "G_FPOW\0"
5464
  /* 27062 */ "RETHROW\0"
5465
  /* 27070 */ "G_VECREDUCE_FMAX\0"
5466
  /* 27087 */ "G_ATOMICRMW_FMAX\0"
5467
  /* 27104 */ "G_VECREDUCE_SMAX\0"
5468
  /* 27121 */ "G_SMAX\0"
5469
  /* 27128 */ "G_VECREDUCE_UMAX\0"
5470
  /* 27145 */ "G_UMAX\0"
5471
  /* 27152 */ "G_ATOMICRMW_UMAX\0"
5472
  /* 27169 */ "G_ATOMICRMW_MAX\0"
5473
  /* 27185 */ "G_FRAME_INDEX\0"
5474
  /* 27199 */ "G_SBFX\0"
5475
  /* 27206 */ "G_UBFX\0"
5476
  /* 27213 */ "G_SMULFIX\0"
5477
  /* 27223 */ "G_UMULFIX\0"
5478
  /* 27233 */ "G_SDIVFIX\0"
5479
  /* 27243 */ "G_UDIVFIX\0"
5480
  /* 27253 */ "G_MEMCPY\0"
5481
  /* 27262 */ "TABLE_COPY\0"
5482
  /* 27273 */ "END_TRY\0"
5483
  /* 27281 */ "G_CTLZ\0"
5484
  /* 27288 */ "G_CTTZ\0"
5485
  /* 27295 */ "ARGUMENT_funcref\0"
5486
  /* 27312 */ "ARGUMENT_externref\0"
5487
  /* 27331 */ "EXTRACT_LANE_I8x16_s\0"
5488
  /* 27352 */ "EXTRACT_LANE_I16x8_s\0"
5489
  /* 27373 */ "EXTRACT_LANE_I8x16_u\0"
5490
  /* 27394 */ "EXTRACT_LANE_I16x8_u\0"
5491
};
5492
#ifdef __GNUC__
5493
#pragma GCC diagnostic pop
5494
#endif
5495
5496
extern const unsigned WebAssemblyInstrNameIndices[] = {
5497
    12033U, 12432U, 13107U, 12710U, 12102U, 12083U, 12111U, 12268U, 
5498
    11874U, 11889U, 11311U, 11916U, 13479U, 11182U, 26908U, 11840U, 
5499
    12029U, 12092U, 10925U, 27268U, 11056U, 26812U, 10746U, 10848U, 
5500
    10898U, 12840U, 12246U, 26722U, 10831U, 13042U, 11979U, 26711U, 
5501
    11103U, 13015U, 13002U, 13168U, 26570U, 26593U, 12169U, 12225U, 
5502
    12198U, 12128U, 13133U, 12794U, 26938U, 26968U, 12548U, 10643U, 
5503
    10354U, 12371U, 27003U, 27010U, 12398U, 12405U, 12412U, 12422U, 
5504
    10724U, 13360U, 13323U, 11309U, 12031U, 27185U, 11192U, 12273U, 
5505
    26490U, 13411U, 26849U, 13428U, 13275U, 10424U, 13462U, 26733U, 
5506
    13387U, 26881U, 11237U, 13144U, 10805U, 10398U, 10787U, 26752U, 
5507
    12526U, 13193U, 10544U, 10488U, 10518U, 10529U, 10469U, 10499U, 
5508
    11147U, 11131U, 13509U, 11930U, 11947U, 10675U, 10360U, 10730U, 
5509
    10691U, 13365U, 13329U, 27169U, 12674U, 27152U, 12657U, 10610U, 
5510
    10337U, 27087U, 12592U, 12871U, 12849U, 10890U, 12002U, 10759U, 
5511
    26519U, 26827U, 10376U, 13549U, 26688U, 13576U, 26952U, 10416U, 
5512
    26677U, 26665U, 26802U, 11971U, 26931U, 11903U, 26961U, 12155U, 
5513
    13259U, 13245U, 12148U, 13252U, 13380U, 12289U, 12926U, 12919U, 
5514
    26510U, 12786U, 10946U, 12770U, 10869U, 12778U, 10938U, 12762U, 
5515
    10861U, 12824U, 12816U, 12021U, 12013U, 26408U, 26398U, 26388U, 
5516
    26378U, 26428U, 26418U, 27213U, 27223U, 26438U, 26451U, 27233U, 
5517
    27243U, 26464U, 26477U, 10568U, 10316U, 12313U, 10297U, 10462U, 
5518
    26982U, 12377U, 27055U, 12055U, 13086U, 3552U, 9U, 11964U, 
5519
    3544U, 0U, 13061U, 13093U, 11867U, 26923U, 10388U, 12037U, 
5520
    12046U, 12901U, 12910U, 13398U, 12563U, 13496U, 11246U, 12506U, 
5521
    12516U, 10995U, 11010U, 12463U, 12495U, 27017U, 27043U, 27029U, 
5522
    10954U, 10982U, 10967U, 10649U, 12073U, 12626U, 27121U, 12650U, 
5523
    27145U, 13405U, 10778U, 10768U, 13102U, 26617U, 26645U, 26624U, 
5524
    13290U, 27288U, 11291U, 27281U, 11273U, 12946U, 12893U, 11160U, 
5525
    12161U, 13455U, 12690U, 26858U, 13266U, 26744U, 26770U, 26891U, 
5526
    13120U, 11043U, 10445U, 11215U, 11116U, 10596U, 10323U, 12341U, 
5527
    26989U, 12384U, 10303U, 26866U, 13070U, 13212U, 13228U, 27253U, 
5528
    11087U, 11227U, 26584U, 12832U, 10575U, 12320U, 10551U, 12296U, 
5529
    27070U, 12575U, 12474U, 12442U, 10627U, 12355U, 10708U, 13345U, 
5530
    13307U, 27104U, 12609U, 27128U, 12633U, 27199U, 27206U, 13443U, 
5531
    26049U, 13618U, 26079U, 26550U, 26147U, 26559U, 26158U, 10910U, 
5532
    25159U, 13614U, 26075U, 2643U, 16500U, 8044U, 22565U, 6951U, 
5533
    21294U, 3754U, 17773U, 9713U, 24458U, 8348U, 22915U, 4064U, 
5534
    18129U, 9147U, 23804U, 2512U, 16341U, 7891U, 22388U, 6821U, 
5535
    21136U, 3601U, 17596U, 9617U, 24346U, 2962U, 16867U, 8233U, 
5536
    22782U, 7270U, 21661U, 3949U, 17996U, 9061U, 23704U, 9829U, 
5537
    24590U, 9219U, 23888U, 10057U, 24850U, 9401U, 24098U, 12745U, 
5538
    25933U, 13027U, 26021U, 9646U, 24379U, 8281U, 22836U, 3997U, 
5539
    18050U, 9090U, 23737U, 10704U, 26795U, 26185U, 2970U, 16877U, 
5540
    7278U, 21671U, 25132U, 11207U, 25242U, 27312U, 26246U, 3503U, 
5541
    17502U, 7809U, 22294U, 27295U, 26227U, 3531U, 17534U, 7837U, 
5542
    22326U, 9575U, 24298U, 7794U, 22277U, 7822U, 22309U, 3488U, 
5543
    17485U, 3516U, 17517U, 9019U, 23656U, 10877U, 25144U, 708U, 
5544
    14379U, 5017U, 19174U, 1836U, 15601U, 6145U, 20396U, 1812U, 
5545
    15575U, 6121U, 20370U, 732U, 14405U, 5041U, 19200U, 1860U, 
5546
    15627U, 6169U, 20422U, 166U, 13793U, 4475U, 18588U, 1087U, 
5547
    14792U, 5396U, 19587U, 186U, 13815U, 4495U, 18610U, 1134U, 
5548
    14843U, 5443U, 19638U, 262U, 13897U, 4571U, 18692U, 1237U, 
5549
    14954U, 5546U, 19749U, 359U, 14002U, 4668U, 18797U, 1365U, 
5550
    15092U, 5674U, 19887U, 602U, 14263U, 4911U, 19058U, 1689U, 
5551
    15440U, 5998U, 20235U, 90U, 13711U, 4399U, 18506U, 1011U, 
5552
    14710U, 5320U, 19505U, 447U, 14096U, 4756U, 18891U, 1481U, 
5553
    15216U, 5790U, 20011U, 526U, 14181U, 4835U, 18976U, 1587U, 
5554
    15330U, 5896U, 20125U, 1107U, 14814U, 5416U, 19609U, 1210U, 
5555
    14925U, 5519U, 19720U, 1334U, 15059U, 5643U, 19854U, 1663U, 
5556
    15412U, 5972U, 20207U, 984U, 14681U, 5293U, 19476U, 1453U, 
5557
    15186U, 5762U, 19981U, 1560U, 15301U, 5869U, 20096U, 213U, 
5558
    13844U, 4522U, 18639U, 1161U, 14872U, 5470U, 19667U, 289U, 
5559
    13926U, 4598U, 18721U, 1264U, 14983U, 5573U, 19778U, 390U, 
5560
    14035U, 4699U, 18830U, 1396U, 15125U, 5705U, 19920U, 628U, 
5561
    14291U, 4937U, 19086U, 1715U, 15468U, 6024U, 20263U, 117U, 
5562
    13740U, 4426U, 18535U, 1038U, 14739U, 5347U, 19534U, 475U, 
5563
    14126U, 4784U, 18921U, 1509U, 15246U, 5818U, 20041U, 553U, 
5564
    14210U, 4862U, 19005U, 1614U, 15359U, 5923U, 20154U, 239U, 
5565
    13872U, 4548U, 18667U, 1187U, 14900U, 5496U, 19695U, 315U, 
5566
    13954U, 4624U, 18749U, 1290U, 15011U, 5599U, 19806U, 420U, 
5567
    14067U, 4729U, 18862U, 1426U, 15157U, 5735U, 19952U, 653U, 
5568
    14318U, 4962U, 19113U, 1740U, 15495U, 6049U, 20290U, 143U, 
5569
    13768U, 4452U, 18563U, 1064U, 14767U, 5373U, 19562U, 502U, 
5570
    14155U, 4811U, 18950U, 1536U, 15275U, 5845U, 20070U, 579U, 
5571
    14238U, 4888U, 19033U, 1640U, 15387U, 5949U, 20182U, 45U, 
5572
    13662U, 4354U, 18457U, 939U, 14632U, 5248U, 19427U, 916U, 
5573
    14607U, 5225U, 19402U, 68U, 13687U, 4377U, 18482U, 962U, 
5574
    14657U, 5271U, 19452U, 338U, 13979U, 4647U, 18774U, 1313U, 
5575
    15036U, 5622U, 19831U, 10016U, 24803U, 9360U, 24051U, 9670U, 
5576
    24407U, 8305U, 22864U, 4021U, 18078U, 9114U, 23765U, 26500U, 
5577
    26115U, 12067U, 25866U, 13104U, 11861U, 25846U, 26038U, 2992U, 
5578
    16903U, 7300U, 21697U, 13539U, 26063U, 12184U, 26536U, 26131U, 
5579
    25878U, 11996U, 12258U, 25885U, 25854U, 2579U, 16422U, 7967U, 
5580
    22476U, 6887U, 21216U, 3677U, 17684U, 3464U, 17455U, 7770U, 
5581
    22247U, 2887U, 16778U, 7195U, 21572U, 3326U, 17293U, 7649U, 
5582
    22104U, 7850U, 22341U, 3560U, 17549U, 9590U, 24315U, 8206U, 
5583
    22751U, 3922U, 17965U, 9034U, 23673U, 2596U, 16443U, 6904U, 
5584
    21237U, 11825U, 25820U, 2945U, 16846U, 7253U, 21640U, 11555U, 
5585
    25522U, 3455U, 17444U, 7761U, 22236U, 9565U, 24286U, 3480U, 
5586
    17475U, 7786U, 22267U, 11025U, 25176U, 11173U, 25231U, 2929U, 
5587
    16826U, 8109U, 22642U, 7237U, 21620U, 3819U, 17850U, 3216U, 
5588
    17167U, 7539U, 21978U, 3445U, 17432U, 7751U, 22224U, 26791U, 
5589
    26179U, 11650U, 25627U, 2617U, 16468U, 6925U, 21262U, 11398U, 
5590
    25347U, 3037U, 16958U, 7358U, 21767U, 9481U, 24190U, 11155U, 
5591
    25224U, 10755U, 12063U, 25862U, 12697U, 25897U, 11854U, 25837U, 
5592
    12937U, 25958U, 25138U, 27273U, 26217U, 3472U, 17465U, 7778U, 
5593
    22257U, 2626U, 16479U, 8023U, 22540U, 6934U, 21273U, 3733U, 
5594
    17748U, 9704U, 24447U, 3046U, 16969U, 8339U, 22904U, 7367U, 
5595
    21778U, 4055U, 18118U, 9138U, 23793U, 9745U, 24496U, 8380U, 
5596
    22953U, 4096U, 18167U, 9984U, 24767U, 8528U, 23123U, 4198U, 
5597
    18283U, 9887U, 24656U, 8446U, 23029U, 4150U, 18229U, 10095U, 
5598
    24894U, 8594U, 23199U, 4230U, 18319U, 7938U, 22443U, 3648U, 
5599
    17651U, 27352U, 26290U, 27394U, 26336U, 8262U, 22815U, 3978U, 
5600
    18029U, 27331U, 26267U, 27373U, 26313U, 3180U, 17127U, 7503U, 
5601
    21938U, 3409U, 17392U, 7715U, 22184U, 6864U, 21189U, 3266U, 
5602
    17225U, 3198U, 17147U, 7521U, 21958U, 3427U, 17412U, 7733U, 
5603
    22204U, 2555U, 16394U, 7589U, 22036U, 12726U, 25912U, 2633U, 
5604
    16488U, 8032U, 22551U, 6941U, 21282U, 3742U, 17759U, 2418U, 
5605
    16235U, 6727U, 21030U, 2456U, 16277U, 6765U, 21072U, 2437U, 
5606
    16256U, 6746U, 21051U, 2475U, 16298U, 6784U, 21093U, 2534U, 
5607
    16367U, 7901U, 22400U, 6843U, 21162U, 3611U, 17608U, 9723U, 
5608
    24470U, 3124U, 17059U, 8358U, 22927U, 7447U, 21870U, 4074U, 
5609
    18141U, 9157U, 23816U, 9962U, 24741U, 3353U, 17324U, 8506U, 
5610
    23097U, 7659U, 22116U, 9326U, 24011U, 11702U, 25685U, 2774U, 
5611
    16647U, 7082U, 21441U, 11444U, 25399U, 3237U, 17192U, 7560U, 
5612
    22003U, 9503U, 24216U, 11763U, 25752U, 2823U, 16702U, 7131U, 
5613
    21496U, 11499U, 25460U, 3286U, 17247U, 7609U, 22058U, 9534U, 
5614
    24251U, 2852U, 16735U, 8066U, 22591U, 7160U, 21529U, 3776U, 
5615
    17799U, 9865U, 24630U, 3162U, 17105U, 8424U, 23003U, 7485U, 
5616
    21916U, 4128U, 18203U, 9235U, 23906U, 10073U, 24868U, 3391U, 
5617
    17370U, 8572U, 23173U, 7697U, 22162U, 9417U, 24116U, 3070U, 
5618
    16999U, 3089U, 17020U, 2803U, 16680U, 2651U, 16510U, 6959U, 
5619
    21304U, 2683U, 16546U, 6991U, 21340U, 2897U, 16790U, 7205U, 
5620
    21584U, 2723U, 16590U, 7031U, 21384U, 7345U, 21752U, 7410U, 
5621
    21829U, 7391U, 21808U, 7429U, 21850U, 3107U, 17040U, 3336U, 
5622
    17305U, 7111U, 21474U, 2667U, 16528U, 6975U, 21322U, 2703U, 
5623
    16568U, 7011U, 21362U, 2913U, 16808U, 7221U, 21602U, 2743U, 
5624
    16612U, 7051U, 21406U, 11858U, 25841U, 9945U, 24722U, 8489U, 
5625
    23078U, 4181U, 18264U, 9296U, 23977U, 2541U, 16376U, 7910U, 
5626
    22411U, 6850U, 21171U, 3620U, 17619U, 9734U, 24483U, 3133U, 
5627
    17070U, 8369U, 22940U, 7456U, 21881U, 4085U, 18154U, 9168U, 
5628
    23829U, 9973U, 24754U, 3362U, 17335U, 8517U, 23110U, 7668U, 
5629
    22127U, 9337U, 24024U, 2270U, 16075U, 6579U, 20870U, 675U, 
5630
    14342U, 4984U, 19137U, 1779U, 15538U, 6088U, 20333U, 715U, 
5631
    14386U, 5024U, 19181U, 1843U, 15608U, 6152U, 20403U, 2236U, 
5632
    16037U, 6545U, 20832U, 1762U, 15519U, 6071U, 20314U, 1819U, 
5633
    15582U, 6128U, 20377U, 2253U, 16056U, 6562U, 20851U, 2287U, 
5634
    16094U, 6596U, 20889U, 692U, 14361U, 5001U, 19156U, 1796U, 
5635
    15557U, 6105U, 20352U, 739U, 14412U, 5048U, 19207U, 1867U, 
5636
    15634U, 6176U, 20429U, 2128U, 15921U, 6437U, 20716U, 1969U, 
5637
    15746U, 6278U, 20541U, 841U, 14524U, 5150U, 19319U, 2152U, 
5638
    15947U, 6461U, 20742U, 1993U, 15772U, 6302U, 20567U, 865U, 
5639
    14550U, 5174U, 19345U, 18U, 13631U, 4327U, 18426U, 889U, 
5640
    14576U, 5198U, 19371U, 173U, 13800U, 4482U, 18595U, 1094U, 
5641
    14799U, 5403U, 19594U, 2087U, 15876U, 6396U, 20671U, 1908U, 
5642
    15679U, 6217U, 20474U, 780U, 14457U, 5089U, 19252U, 2017U, 
5643
    15798U, 6326U, 20593U, 2058U, 15843U, 6367U, 20638U, 1949U, 
5644
    15724U, 6258U, 20519U, 821U, 14502U, 5130U, 19297U, 11723U, 
5645
    25708U, 2789U, 16664U, 7097U, 21458U, 11463U, 25420U, 3252U, 
5646
    17209U, 7575U, 22020U, 9519U, 24234U, 11784U, 25775U, 2838U, 
5647
    16719U, 7146U, 21513U, 11518U, 25481U, 3301U, 17264U, 7624U, 
5648
    22075U, 9550U, 24269U, 11568U, 25537U, 2520U, 16351U, 6829U, 
5649
    21146U, 11324U, 25265U, 2978U, 16887U, 7286U, 21681U, 9466U, 
5650
    24173U, 12941U, 25962U, 2859U, 16744U, 8075U, 22602U, 7167U, 
5651
    21538U, 3785U, 17810U, 9876U, 24643U, 3171U, 17116U, 8435U, 
5652
    23016U, 7494U, 21927U, 4139U, 18216U, 9246U, 23919U, 10084U, 
5653
    24881U, 3400U, 17381U, 8583U, 23186U, 7706U, 22173U, 9428U, 
5654
    24129U, 7890U, 22387U, 3600U, 17595U, 2937U, 16836U, 8133U, 
5655
    22668U, 7245U, 21630U, 3843U, 17876U, 9921U, 24694U, 8465U, 
5656
    23050U, 9272U, 23949U, 10129U, 24932U, 8613U, 23220U, 9454U, 
5657
    24159U, 2363U, 16176U, 6672U, 20971U, 755U, 14430U, 5064U, 
5658
    19225U, 1883U, 15652U, 6192U, 20447U, 2609U, 16458U, 8002U, 
5659
    22515U, 6917U, 21252U, 3712U, 17723U, 9765U, 24518U, 8400U, 
5660
    22975U, 9179U, 23842U, 10004U, 24789U, 8548U, 23145U, 9348U, 
5661
    24037U, 2588U, 16433U, 7978U, 22489U, 6896U, 21227U, 3688U, 
5662
    17697U, 9694U, 24435U, 3029U, 16948U, 8329U, 22892U, 7337U, 
5663
    21742U, 4045U, 18106U, 9906U, 24677U, 9257U, 23932U, 10114U, 
5664
    24915U, 9439U, 24142U, 2875U, 16764U, 8095U, 22626U, 7183U, 
5665
    21558U, 3805U, 17834U, 2571U, 16412U, 7957U, 22464U, 6879U, 
5666
    21206U, 3667U, 17672U, 9660U, 24395U, 8295U, 22852U, 4011U, 
5667
    18066U, 9104U, 23753U, 2548U, 16385U, 7929U, 22432U, 6857U, 
5668
    21180U, 3639U, 17640U, 9637U, 24368U, 3005U, 16918U, 8253U, 
5669
    22804U, 7313U, 21712U, 3969U, 18018U, 9081U, 23726U, 7889U, 
5670
    22386U, 3599U, 17594U, 12933U, 25952U, 26798U, 26188U, 13272U, 
5671
    3054U, 16979U, 7375U, 21788U, 26044U, 8143U, 22680U, 3853U, 
5672
    17888U, 8012U, 22527U, 3722U, 17735U, 3315U, 17280U, 7638U, 
5673
    22091U, 9313U, 23996U, 9845U, 24608U, 11628U, 25603U, 11378U, 
5674
    25325U, 11609U, 25582U, 11361U, 25306U, 26783U, 10659U, 25114U, 
5675
    26359U, 26094U, 26171U, 9789U, 24546U, 11071U, 25206U, 3142U, 
5676
    17081U, 7465U, 21892U, 3371U, 17346U, 7677U, 22138U, 7919U, 
5677
    22422U, 3629U, 17630U, 9627U, 24358U, 8243U, 22794U, 3959U, 
5678
    18008U, 9071U, 23716U, 27062U, 26194U, 12738U, 25924U, 12189U, 
5679
    26532U, 26127U, 25874U, 3020U, 16937U, 7328U, 21731U, 3061U, 
5680
    16988U, 7382U, 21797U, 11665U, 25644U, 2763U, 16634U, 7071U, 
5681
    21428U, 11411U, 25362U, 3226U, 17179U, 7549U, 21990U, 9491U, 
5682
    24202U, 9684U, 24423U, 3012U, 16927U, 8319U, 22880U, 7320U, 
5683
    21721U, 4035U, 18094U, 9128U, 23781U, 9777U, 24532U, 3152U, 
5684
    17093U, 8412U, 22989U, 7475U, 21904U, 4116U, 18189U, 9191U, 
5685
    23856U, 10029U, 24818U, 3381U, 17358U, 8560U, 23159U, 7687U, 
5686
    22150U, 4218U, 18305U, 9373U, 24066U, 11063U, 25196U, 8119U, 
5687
    22654U, 3829U, 17862U, 7988U, 22501U, 3698U, 17709U, 8054U, 
5688
    22577U, 3764U, 17785U, 9933U, 24708U, 8477U, 23064U, 4169U, 
5689
    18250U, 9284U, 23963U, 2866U, 16753U, 8084U, 22613U, 7174U, 
5690
    21547U, 3794U, 17821U, 52U, 13669U, 4361U, 18464U, 946U, 
5691
    14639U, 5255U, 19434U, 923U, 14614U, 5232U, 19409U, 75U, 
5692
    13694U, 4384U, 18489U, 969U, 14664U, 5278U, 19459U, 31U, 
5693
    13646U, 4340U, 18441U, 902U, 14591U, 5211U, 19386U, 345U, 
5694
    13986U, 4654U, 18781U, 1320U, 15043U, 5629U, 19838U, 2107U, 
5695
    15898U, 6416U, 20693U, 1928U, 15701U, 6237U, 20496U, 800U, 
5696
    14479U, 5109U, 19274U, 2037U, 15820U, 6346U, 20615U, 2072U, 
5697
    15859U, 6381U, 20654U, 2494U, 16319U, 7867U, 22360U, 6803U, 
5698
    21114U, 3577U, 17568U, 9607U, 24334U, 2954U, 16857U, 8223U, 
5699
    22770U, 7262U, 21651U, 3939U, 17984U, 9051U, 23692U, 9813U, 
5700
    24572U, 9203U, 23870U, 10041U, 24832U, 9385U, 24080U, 11079U, 
5701
    25214U, 27262U, 26204U, 11588U, 25559U, 11342U, 25285U, 11682U, 
5702
    25663U, 11426U, 25379U, 11804U, 25797U, 11536U, 25501U, 11743U, 
5703
    25730U, 11481U, 25440U, 11262U, 25252U, 11574U, 25543U, 2526U, 
5704
    16357U, 6835U, 21152U, 11330U, 25271U, 2984U, 16893U, 7292U, 
5705
    21687U, 9472U, 24179U, 27064U, 26196U, 2502U, 16329U, 7877U, 
5706
    22372U, 6811U, 21124U, 3587U, 17580U, 27277U, 26221U, 11031U, 
5707
    25182U, 13319U, 3053U, 16978U, 7374U, 21787U, 26043U, 2333U, 
5708
    16144U, 2176U, 15973U, 6642U, 20939U, 6485U, 20768U, 12978U, 
5709
    25995U, 2388U, 16203U, 2206U, 16005U, 2303U, 16112U, 12954U, 
5710
    25969U, 6697U, 20998U, 6515U, 20800U, 6612U, 20907U, 3864U, 
5711
    17901U, 3884U, 17923U, 8154U, 22693U, 10219U, 25028U, 8861U, 
5712
    23482U, 4249U, 18340U, 10258U, 25071U, 8957U, 23588U, 4288U, 
5713
    18383U, 10239U, 25050U, 8904U, 23529U, 4269U, 18362U, 10278U, 
5714
    25093U, 9000U, 23635U, 4308U, 18405U, 8923U, 23550U, 8940U, 
5715
    23569U, 10141U, 24946U, 8661U, 23272U, 10179U, 24986U, 8737U, 
5716
    23352U, 8625U, 23234U, 8777U, 23394U, 8699U, 23312U, 8818U, 
5717
    23437U, 3904U, 17945U, 8172U, 22713U, 8881U, 23504U, 8977U, 
5718
    23610U, 8189U, 22732U, 
5719
};
5720
5721
2
static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) {
5722
2
  II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1771);
5723
2
}
5724
5725
} // end namespace llvm
5726
#endif // GET_INSTRINFO_MC_DESC
5727
5728
#ifdef GET_INSTRINFO_HEADER
5729
#undef GET_INSTRINFO_HEADER
5730
namespace llvm {
5731
struct WebAssemblyGenInstrInfo : public TargetInstrInfo {
5732
  explicit WebAssemblyGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
5733
  ~WebAssemblyGenInstrInfo() override = default;
5734
5735
};
5736
} // end namespace llvm
5737
#endif // GET_INSTRINFO_HEADER
5738
5739
#ifdef GET_INSTRINFO_HELPER_DECLS
5740
#undef GET_INSTRINFO_HELPER_DECLS
5741
5742
5743
#endif // GET_INSTRINFO_HELPER_DECLS
5744
5745
#ifdef GET_INSTRINFO_HELPERS
5746
#undef GET_INSTRINFO_HELPERS
5747
5748
#endif // GET_INSTRINFO_HELPERS
5749
5750
#ifdef GET_INSTRINFO_CTOR_DTOR
5751
#undef GET_INSTRINFO_CTOR_DTOR
5752
namespace llvm {
5753
extern const WebAssemblyInstrTable WebAssemblyDescs;
5754
extern const unsigned WebAssemblyInstrNameIndices[];
5755
extern const char WebAssemblyInstrNameData[];
5756
WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
5757
2
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
5758
2
  InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1771);
5759
2
}
5760
} // end namespace llvm
5761
#endif // GET_INSTRINFO_CTOR_DTOR
5762
5763
#ifdef GET_INSTRINFO_OPERAND_ENUM
5764
#undef GET_INSTRINFO_OPERAND_ENUM
5765
namespace llvm {
5766
namespace WebAssembly {
5767
namespace OpName {
5768
enum {
5769
  addr = 3,
5770
  count = 9,
5771
  dst = 0,
5772
  exp = 5,
5773
  idx = 7,
5774
  new_ = 6,
5775
  off = 2,
5776
  p2align = 1,
5777
  timeout = 10,
5778
  val = 4,
5779
  vec = 8,
5780
  OPERAND_LAST
5781
};
5782
} // end namespace OpName
5783
} // end namespace WebAssembly
5784
} // end namespace llvm
5785
#endif //GET_INSTRINFO_OPERAND_ENUM
5786
5787
#ifdef GET_INSTRINFO_NAMED_OPS
5788
#undef GET_INSTRINFO_NAMED_OPS
5789
namespace llvm {
5790
namespace WebAssembly {
5791
LLVM_READONLY
5792
75.2k
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
5793
75.2k
  static const int16_t OperandMap [][11] = {
5794
75.2k
{0, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, },
5795
75.2k
{0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, },
5796
75.2k
{0, 1, 2, 3, -1, 4, 5, -1, -1, -1, -1, },
5797
75.2k
{0, 1, 2, 3, -1, 4, -1, -1, -1, -1, 5, },
5798
75.2k
{0, 1, 2, 3, -1, -1, -1, -1, -1, 4, -1, },
5799
75.2k
{0, 1, 2, 4, -1, -1, -1, 3, 5, -1, -1, },
5800
75.2k
{-1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, },
5801
75.2k
{-1, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, },
5802
75.2k
{-1, 0, 1, 2, -1, -1, -1, -1, 3, -1, -1, },
5803
75.2k
{-1, 0, 1, 3, -1, -1, -1, 2, 4, -1, -1, },
5804
75.2k
{-1, 0, 1, -1, -1, -1, -1, 2, -1, -1, -1, },
5805
75.2k
};
5806
75.2k
  switch(Opcode) {
5807
0
  case WebAssembly::ATOMIC_LOAD16_U_I32_A32:
5808
0
  case WebAssembly::ATOMIC_LOAD16_U_I32_A64:
5809
0
  case WebAssembly::ATOMIC_LOAD16_U_I64_A32:
5810
0
  case WebAssembly::ATOMIC_LOAD16_U_I64_A64:
5811
0
  case WebAssembly::ATOMIC_LOAD32_U_I64_A32:
5812
0
  case WebAssembly::ATOMIC_LOAD32_U_I64_A64:
5813
0
  case WebAssembly::ATOMIC_LOAD8_U_I32_A32:
5814
0
  case WebAssembly::ATOMIC_LOAD8_U_I32_A64:
5815
0
  case WebAssembly::ATOMIC_LOAD8_U_I64_A32:
5816
0
  case WebAssembly::ATOMIC_LOAD8_U_I64_A64:
5817
0
  case WebAssembly::ATOMIC_LOAD_I32_A32:
5818
0
  case WebAssembly::ATOMIC_LOAD_I32_A64:
5819
0
  case WebAssembly::ATOMIC_LOAD_I64_A32:
5820
0
  case WebAssembly::ATOMIC_LOAD_I64_A64:
5821
0
  case WebAssembly::LOAD16_SPLAT_A32:
5822
0
  case WebAssembly::LOAD16_SPLAT_A64:
5823
50
  case WebAssembly::LOAD16_S_I32_A32:
5824
50
  case WebAssembly::LOAD16_S_I32_A64:
5825
50
  case WebAssembly::LOAD16_S_I64_A32:
5826
50
  case WebAssembly::LOAD16_S_I64_A64:
5827
256
  case WebAssembly::LOAD16_U_I32_A32:
5828
256
  case WebAssembly::LOAD16_U_I32_A64:
5829
256
  case WebAssembly::LOAD16_U_I64_A32:
5830
256
  case WebAssembly::LOAD16_U_I64_A64:
5831
256
  case WebAssembly::LOAD32_SPLAT_A32:
5832
256
  case WebAssembly::LOAD32_SPLAT_A64:
5833
256
  case WebAssembly::LOAD32_S_I64_A32:
5834
256
  case WebAssembly::LOAD32_S_I64_A64:
5835
256
  case WebAssembly::LOAD32_U_I64_A32:
5836
256
  case WebAssembly::LOAD32_U_I64_A64:
5837
256
  case WebAssembly::LOAD64_SPLAT_A32:
5838
256
  case WebAssembly::LOAD64_SPLAT_A64:
5839
256
  case WebAssembly::LOAD8_SPLAT_A32:
5840
256
  case WebAssembly::LOAD8_SPLAT_A64:
5841
290
  case WebAssembly::LOAD8_S_I32_A32:
5842
290
  case WebAssembly::LOAD8_S_I32_A64:
5843
290
  case WebAssembly::LOAD8_S_I64_A32:
5844
290
  case WebAssembly::LOAD8_S_I64_A64:
5845
729
  case WebAssembly::LOAD8_U_I32_A32:
5846
729
  case WebAssembly::LOAD8_U_I32_A64:
5847
729
  case WebAssembly::LOAD8_U_I64_A32:
5848
729
  case WebAssembly::LOAD8_U_I64_A64:
5849
729
  case WebAssembly::LOAD_EXTEND_S_I16x8_A32:
5850
729
  case WebAssembly::LOAD_EXTEND_S_I16x8_A64:
5851
729
  case WebAssembly::LOAD_EXTEND_S_I32x4_A32:
5852
729
  case WebAssembly::LOAD_EXTEND_S_I32x4_A64:
5853
729
  case WebAssembly::LOAD_EXTEND_S_I64x2_A32:
5854
729
  case WebAssembly::LOAD_EXTEND_S_I64x2_A64:
5855
729
  case WebAssembly::LOAD_EXTEND_U_I16x8_A32:
5856
729
  case WebAssembly::LOAD_EXTEND_U_I16x8_A64:
5857
729
  case WebAssembly::LOAD_EXTEND_U_I32x4_A32:
5858
729
  case WebAssembly::LOAD_EXTEND_U_I32x4_A64:
5859
729
  case WebAssembly::LOAD_EXTEND_U_I64x2_A32:
5860
729
  case WebAssembly::LOAD_EXTEND_U_I64x2_A64:
5861
1.02k
  case WebAssembly::LOAD_F32_A32:
5862
1.02k
  case WebAssembly::LOAD_F32_A64:
5863
1.22k
  case WebAssembly::LOAD_F64_A32:
5864
1.22k
  case WebAssembly::LOAD_F64_A64:
5865
1.71k
  case WebAssembly::LOAD_I32_A32:
5866
1.71k
  case WebAssembly::LOAD_I32_A64:
5867
1.95k
  case WebAssembly::LOAD_I64_A32:
5868
1.95k
  case WebAssembly::LOAD_I64_A64:
5869
1.95k
  case WebAssembly::LOAD_V128_A32:
5870
1.95k
  case WebAssembly::LOAD_V128_A64:
5871
1.95k
  case WebAssembly::LOAD_ZERO_I32x4_A32:
5872
1.95k
  case WebAssembly::LOAD_ZERO_I32x4_A64:
5873
1.95k
  case WebAssembly::LOAD_ZERO_I64x2_A32:
5874
1.95k
  case WebAssembly::LOAD_ZERO_I64x2_A64:
5875
1.95k
    return OperandMap[0][NamedIdx];
5876
0
  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32:
5877
0
  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64:
5878
0
  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32:
5879
0
  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64:
5880
0
  case WebAssembly::ATOMIC_RMW16_U_AND_I32_A32:
5881
0
  case WebAssembly::ATOMIC_RMW16_U_AND_I32_A64:
5882
0
  case WebAssembly::ATOMIC_RMW16_U_AND_I64_A32:
5883
0
  case WebAssembly::ATOMIC_RMW16_U_AND_I64_A64:
5884
0
  case WebAssembly::ATOMIC_RMW16_U_OR_I32_A32:
5885
0
  case WebAssembly::ATOMIC_RMW16_U_OR_I32_A64:
5886
0
  case WebAssembly::ATOMIC_RMW16_U_OR_I64_A32:
5887
0
  case WebAssembly::ATOMIC_RMW16_U_OR_I64_A64:
5888
0
  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32:
5889
0
  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64:
5890
0
  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32:
5891
0
  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64:
5892
0
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32:
5893
0
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64:
5894
0
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32:
5895
0
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64:
5896
0
  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32:
5897
0
  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64:
5898
0
  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32:
5899
0
  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64:
5900
0
  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32:
5901
0
  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64:
5902
0
  case WebAssembly::ATOMIC_RMW32_U_AND_I64_A32:
5903
0
  case WebAssembly::ATOMIC_RMW32_U_AND_I64_A64:
5904
0
  case WebAssembly::ATOMIC_RMW32_U_OR_I64_A32:
5905
0
  case WebAssembly::ATOMIC_RMW32_U_OR_I64_A64:
5906
0
  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32:
5907
0
  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64:
5908
0
  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32:
5909
0
  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64:
5910
0
  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32:
5911
0
  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64:
5912
0
  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32:
5913
0
  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64:
5914
0
  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32:
5915
0
  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64:
5916
0
  case WebAssembly::ATOMIC_RMW8_U_AND_I32_A32:
5917
0
  case WebAssembly::ATOMIC_RMW8_U_AND_I32_A64:
5918
0
  case WebAssembly::ATOMIC_RMW8_U_AND_I64_A32:
5919
0
  case WebAssembly::ATOMIC_RMW8_U_AND_I64_A64:
5920
0
  case WebAssembly::ATOMIC_RMW8_U_OR_I32_A32:
5921
0
  case WebAssembly::ATOMIC_RMW8_U_OR_I32_A64:
5922
0
  case WebAssembly::ATOMIC_RMW8_U_OR_I64_A32:
5923
0
  case WebAssembly::ATOMIC_RMW8_U_OR_I64_A64:
5924
0
  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32:
5925
0
  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64:
5926
0
  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32:
5927
0
  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64:
5928
0
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32:
5929
0
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64:
5930
0
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32:
5931
0
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64:
5932
0
  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32:
5933
0
  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64:
5934
0
  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32:
5935
0
  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64:
5936
0
  case WebAssembly::ATOMIC_RMW_ADD_I32_A32:
5937
0
  case WebAssembly::ATOMIC_RMW_ADD_I32_A64:
5938
0
  case WebAssembly::ATOMIC_RMW_ADD_I64_A32:
5939
0
  case WebAssembly::ATOMIC_RMW_ADD_I64_A64:
5940
0
  case WebAssembly::ATOMIC_RMW_AND_I32_A32:
5941
0
  case WebAssembly::ATOMIC_RMW_AND_I32_A64:
5942
0
  case WebAssembly::ATOMIC_RMW_AND_I64_A32:
5943
0
  case WebAssembly::ATOMIC_RMW_AND_I64_A64:
5944
0
  case WebAssembly::ATOMIC_RMW_OR_I32_A32:
5945
0
  case WebAssembly::ATOMIC_RMW_OR_I32_A64:
5946
0
  case WebAssembly::ATOMIC_RMW_OR_I64_A32:
5947
0
  case WebAssembly::ATOMIC_RMW_OR_I64_A64:
5948
0
  case WebAssembly::ATOMIC_RMW_SUB_I32_A32:
5949
0
  case WebAssembly::ATOMIC_RMW_SUB_I32_A64:
5950
0
  case WebAssembly::ATOMIC_RMW_SUB_I64_A32:
5951
0
  case WebAssembly::ATOMIC_RMW_SUB_I64_A64:
5952
0
  case WebAssembly::ATOMIC_RMW_XCHG_I32_A32:
5953
0
  case WebAssembly::ATOMIC_RMW_XCHG_I32_A64:
5954
0
  case WebAssembly::ATOMIC_RMW_XCHG_I64_A32:
5955
0
  case WebAssembly::ATOMIC_RMW_XCHG_I64_A64:
5956
0
  case WebAssembly::ATOMIC_RMW_XOR_I32_A32:
5957
0
  case WebAssembly::ATOMIC_RMW_XOR_I32_A64:
5958
0
  case WebAssembly::ATOMIC_RMW_XOR_I64_A32:
5959
0
  case WebAssembly::ATOMIC_RMW_XOR_I64_A64:
5960
0
    return OperandMap[1][NamedIdx];
5961
0
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32:
5962
0
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64:
5963
0
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32:
5964
0
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64:
5965
0
  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32:
5966
0
  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64:
5967
0
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32:
5968
0
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64:
5969
0
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32:
5970
0
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64:
5971
0
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32:
5972
0
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64:
5973
0
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32:
5974
0
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64:
5975
0
    return OperandMap[2][NamedIdx];
5976
0
  case WebAssembly::MEMORY_ATOMIC_WAIT32_A32:
5977
0
  case WebAssembly::MEMORY_ATOMIC_WAIT32_A64:
5978
0
  case WebAssembly::MEMORY_ATOMIC_WAIT64_A32:
5979
0
  case WebAssembly::MEMORY_ATOMIC_WAIT64_A64:
5980
0
    return OperandMap[3][NamedIdx];
5981
0
  case WebAssembly::MEMORY_ATOMIC_NOTIFY_A32:
5982
0
  case WebAssembly::MEMORY_ATOMIC_NOTIFY_A64:
5983
0
    return OperandMap[4][NamedIdx];
5984
0
  case WebAssembly::LOAD_LANE_I16x8_A32:
5985
0
  case WebAssembly::LOAD_LANE_I16x8_A64:
5986
0
  case WebAssembly::LOAD_LANE_I32x4_A32:
5987
0
  case WebAssembly::LOAD_LANE_I32x4_A64:
5988
0
  case WebAssembly::LOAD_LANE_I64x2_A32:
5989
0
  case WebAssembly::LOAD_LANE_I64x2_A64:
5990
0
  case WebAssembly::LOAD_LANE_I8x16_A32:
5991
0
  case WebAssembly::LOAD_LANE_I8x16_A64:
5992
0
    return OperandMap[5][NamedIdx];
5993
0
  case WebAssembly::ATOMIC_LOAD16_U_I32_A32_S:
5994
0
  case WebAssembly::ATOMIC_LOAD16_U_I32_A64_S:
5995
0
  case WebAssembly::ATOMIC_LOAD16_U_I64_A32_S:
5996
0
  case WebAssembly::ATOMIC_LOAD16_U_I64_A64_S:
5997
0
  case WebAssembly::ATOMIC_LOAD32_U_I64_A32_S:
5998
0
  case WebAssembly::ATOMIC_LOAD32_U_I64_A64_S:
5999
0
  case WebAssembly::ATOMIC_LOAD8_U_I32_A32_S:
6000
0
  case WebAssembly::ATOMIC_LOAD8_U_I32_A64_S:
6001
0
  case WebAssembly::ATOMIC_LOAD8_U_I64_A32_S:
6002
0
  case WebAssembly::ATOMIC_LOAD8_U_I64_A64_S:
6003
0
  case WebAssembly::ATOMIC_LOAD_I32_A32_S:
6004
0
  case WebAssembly::ATOMIC_LOAD_I32_A64_S:
6005
0
  case WebAssembly::ATOMIC_LOAD_I64_A32_S:
6006
0
  case WebAssembly::ATOMIC_LOAD_I64_A64_S:
6007
0
  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S:
6008
0
  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S:
6009
0
  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S:
6010
0
  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S:
6011
0
  case WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S:
6012
0
  case WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S:
6013
0
  case WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S:
6014
0
  case WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S:
6015
0
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S:
6016
0
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S:
6017
0
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S:
6018
0
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S:
6019
0
  case WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S:
6020
0
  case WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S:
6021
0
  case WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S:
6022
0
  case WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S:
6023
0
  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S:
6024
0
  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S:
6025
0
  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S:
6026
0
  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S:
6027
0
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S:
6028
0
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S:
6029
0
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S:
6030
0
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S:
6031
0
  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S:
6032
0
  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S:
6033
0
  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S:
6034
0
  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S:
6035
0
  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S:
6036
0
  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S:
6037
0
  case WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S:
6038
0
  case WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S:
6039
0
  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S:
6040
0
  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S:
6041
0
  case WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S:
6042
0
  case WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S:
6043
0
  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S:
6044
0
  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S:
6045
0
  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S:
6046
0
  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S:
6047
0
  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S:
6048
0
  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S:
6049
0
  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S:
6050
0
  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S:
6051
0
  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S:
6052
0
  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S:
6053
0
  case WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S:
6054
0
  case WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S:
6055
0
  case WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S:
6056
0
  case WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S:
6057
0
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S:
6058
0
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S:
6059
0
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S:
6060
0
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S:
6061
0
  case WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S:
6062
0
  case WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S:
6063
0
  case WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S:
6064
0
  case WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S:
6065
0
  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S:
6066
0
  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S:
6067
0
  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S:
6068
0
  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S:
6069
0
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S:
6070
0
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S:
6071
0
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S:
6072
0
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S:
6073
0
  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S:
6074
0
  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S:
6075
0
  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S:
6076
0
  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S:
6077
0
  case WebAssembly::ATOMIC_RMW_ADD_I32_A32_S:
6078
0
  case WebAssembly::ATOMIC_RMW_ADD_I32_A64_S:
6079
0
  case WebAssembly::ATOMIC_RMW_ADD_I64_A32_S:
6080
0
  case WebAssembly::ATOMIC_RMW_ADD_I64_A64_S:
6081
0
  case WebAssembly::ATOMIC_RMW_AND_I32_A32_S:
6082
0
  case WebAssembly::ATOMIC_RMW_AND_I32_A64_S:
6083
0
  case WebAssembly::ATOMIC_RMW_AND_I64_A32_S:
6084
0
  case WebAssembly::ATOMIC_RMW_AND_I64_A64_S:
6085
0
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S:
6086
0
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S:
6087
0
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S:
6088
0
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S:
6089
0
  case WebAssembly::ATOMIC_RMW_OR_I32_A32_S:
6090
0
  case WebAssembly::ATOMIC_RMW_OR_I32_A64_S:
6091
0
  case WebAssembly::ATOMIC_RMW_OR_I64_A32_S:
6092
0
  case WebAssembly::ATOMIC_RMW_OR_I64_A64_S:
6093
0
  case WebAssembly::ATOMIC_RMW_SUB_I32_A32_S:
6094
0
  case WebAssembly::ATOMIC_RMW_SUB_I32_A64_S:
6095
0
  case WebAssembly::ATOMIC_RMW_SUB_I64_A32_S:
6096
0
  case WebAssembly::ATOMIC_RMW_SUB_I64_A64_S:
6097
0
  case WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S:
6098
0
  case WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S:
6099
0
  case WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S:
6100
0
  case WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S:
6101
0
  case WebAssembly::ATOMIC_RMW_XOR_I32_A32_S:
6102
0
  case WebAssembly::ATOMIC_RMW_XOR_I32_A64_S:
6103
0
  case WebAssembly::ATOMIC_RMW_XOR_I64_A32_S:
6104
0
  case WebAssembly::ATOMIC_RMW_XOR_I64_A64_S:
6105
0
  case WebAssembly::ATOMIC_STORE16_I32_A32_S:
6106
0
  case WebAssembly::ATOMIC_STORE16_I32_A64_S:
6107
0
  case WebAssembly::ATOMIC_STORE16_I64_A32_S:
6108
0
  case WebAssembly::ATOMIC_STORE16_I64_A64_S:
6109
0
  case WebAssembly::ATOMIC_STORE32_I64_A32_S:
6110
0
  case WebAssembly::ATOMIC_STORE32_I64_A64_S:
6111
0
  case WebAssembly::ATOMIC_STORE8_I32_A32_S:
6112
0
  case WebAssembly::ATOMIC_STORE8_I32_A64_S:
6113
0
  case WebAssembly::ATOMIC_STORE8_I64_A32_S:
6114
0
  case WebAssembly::ATOMIC_STORE8_I64_A64_S:
6115
0
  case WebAssembly::ATOMIC_STORE_I32_A32_S:
6116
0
  case WebAssembly::ATOMIC_STORE_I32_A64_S:
6117
0
  case WebAssembly::ATOMIC_STORE_I64_A32_S:
6118
0
  case WebAssembly::ATOMIC_STORE_I64_A64_S:
6119
0
  case WebAssembly::LOAD16_SPLAT_A32_S:
6120
0
  case WebAssembly::LOAD16_SPLAT_A64_S:
6121
0
  case WebAssembly::LOAD16_S_I32_A32_S:
6122
0
  case WebAssembly::LOAD16_S_I32_A64_S:
6123
0
  case WebAssembly::LOAD16_S_I64_A32_S:
6124
0
  case WebAssembly::LOAD16_S_I64_A64_S:
6125
0
  case WebAssembly::LOAD16_U_I32_A32_S:
6126
0
  case WebAssembly::LOAD16_U_I32_A64_S:
6127
0
  case WebAssembly::LOAD16_U_I64_A32_S:
6128
0
  case WebAssembly::LOAD16_U_I64_A64_S:
6129
0
  case WebAssembly::LOAD32_SPLAT_A32_S:
6130
0
  case WebAssembly::LOAD32_SPLAT_A64_S:
6131
0
  case WebAssembly::LOAD32_S_I64_A32_S:
6132
0
  case WebAssembly::LOAD32_S_I64_A64_S:
6133
0
  case WebAssembly::LOAD32_U_I64_A32_S:
6134
0
  case WebAssembly::LOAD32_U_I64_A64_S:
6135
0
  case WebAssembly::LOAD64_SPLAT_A32_S:
6136
0
  case WebAssembly::LOAD64_SPLAT_A64_S:
6137
0
  case WebAssembly::LOAD8_SPLAT_A32_S:
6138
0
  case WebAssembly::LOAD8_SPLAT_A64_S:
6139
0
  case WebAssembly::LOAD8_S_I32_A32_S:
6140
0
  case WebAssembly::LOAD8_S_I32_A64_S:
6141
0
  case WebAssembly::LOAD8_S_I64_A32_S:
6142
0
  case WebAssembly::LOAD8_S_I64_A64_S:
6143
0
  case WebAssembly::LOAD8_U_I32_A32_S:
6144
0
  case WebAssembly::LOAD8_U_I32_A64_S:
6145
0
  case WebAssembly::LOAD8_U_I64_A32_S:
6146
0
  case WebAssembly::LOAD8_U_I64_A64_S:
6147
0
  case WebAssembly::LOAD_EXTEND_S_I16x8_A32_S:
6148
0
  case WebAssembly::LOAD_EXTEND_S_I16x8_A64_S:
6149
0
  case WebAssembly::LOAD_EXTEND_S_I32x4_A32_S:
6150
0
  case WebAssembly::LOAD_EXTEND_S_I32x4_A64_S:
6151
0
  case WebAssembly::LOAD_EXTEND_S_I64x2_A32_S:
6152
0
  case WebAssembly::LOAD_EXTEND_S_I64x2_A64_S:
6153
0
  case WebAssembly::LOAD_EXTEND_U_I16x8_A32_S:
6154
0
  case WebAssembly::LOAD_EXTEND_U_I16x8_A64_S:
6155
0
  case WebAssembly::LOAD_EXTEND_U_I32x4_A32_S:
6156
0
  case WebAssembly::LOAD_EXTEND_U_I32x4_A64_S:
6157
0
  case WebAssembly::LOAD_EXTEND_U_I64x2_A32_S:
6158
0
  case WebAssembly::LOAD_EXTEND_U_I64x2_A64_S:
6159
0
  case WebAssembly::LOAD_F32_A32_S:
6160
0
  case WebAssembly::LOAD_F32_A64_S:
6161
0
  case WebAssembly::LOAD_F64_A32_S:
6162
0
  case WebAssembly::LOAD_F64_A64_S:
6163
0
  case WebAssembly::LOAD_I32_A32_S:
6164
0
  case WebAssembly::LOAD_I32_A64_S:
6165
0
  case WebAssembly::LOAD_I64_A32_S:
6166
0
  case WebAssembly::LOAD_I64_A64_S:
6167
0
  case WebAssembly::LOAD_V128_A32_S:
6168
0
  case WebAssembly::LOAD_V128_A64_S:
6169
0
  case WebAssembly::LOAD_ZERO_I32x4_A32_S:
6170
0
  case WebAssembly::LOAD_ZERO_I32x4_A64_S:
6171
0
  case WebAssembly::LOAD_ZERO_I64x2_A32_S:
6172
0
  case WebAssembly::LOAD_ZERO_I64x2_A64_S:
6173
0
  case WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S:
6174
0
  case WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S:
6175
0
  case WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S:
6176
0
  case WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S:
6177
0
  case WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S:
6178
0
  case WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S:
6179
0
  case WebAssembly::STORE16_I32_A32_S:
6180
0
  case WebAssembly::STORE16_I32_A64_S:
6181
0
  case WebAssembly::STORE16_I64_A32_S:
6182
0
  case WebAssembly::STORE16_I64_A64_S:
6183
0
  case WebAssembly::STORE32_I64_A32_S:
6184
0
  case WebAssembly::STORE32_I64_A64_S:
6185
0
  case WebAssembly::STORE8_I32_A32_S:
6186
0
  case WebAssembly::STORE8_I32_A64_S:
6187
0
  case WebAssembly::STORE8_I64_A32_S:
6188
0
  case WebAssembly::STORE8_I64_A64_S:
6189
0
  case WebAssembly::STORE_F32_A32_S:
6190
0
  case WebAssembly::STORE_F32_A64_S:
6191
0
  case WebAssembly::STORE_F64_A32_S:
6192
0
  case WebAssembly::STORE_F64_A64_S:
6193
0
  case WebAssembly::STORE_I32_A32_S:
6194
0
  case WebAssembly::STORE_I32_A64_S:
6195
0
  case WebAssembly::STORE_I64_A32_S:
6196
0
  case WebAssembly::STORE_I64_A64_S:
6197
0
  case WebAssembly::STORE_V128_A32_S:
6198
0
  case WebAssembly::STORE_V128_A64_S:
6199
0
    return OperandMap[6][NamedIdx];
6200
0
  case WebAssembly::ATOMIC_STORE16_I32_A32:
6201
0
  case WebAssembly::ATOMIC_STORE16_I32_A64:
6202
0
  case WebAssembly::ATOMIC_STORE16_I64_A32:
6203
0
  case WebAssembly::ATOMIC_STORE16_I64_A64:
6204
0
  case WebAssembly::ATOMIC_STORE32_I64_A32:
6205
0
  case WebAssembly::ATOMIC_STORE32_I64_A64:
6206
0
  case WebAssembly::ATOMIC_STORE8_I32_A32:
6207
0
  case WebAssembly::ATOMIC_STORE8_I32_A64:
6208
0
  case WebAssembly::ATOMIC_STORE8_I64_A32:
6209
0
  case WebAssembly::ATOMIC_STORE8_I64_A64:
6210
0
  case WebAssembly::ATOMIC_STORE_I32_A32:
6211
0
  case WebAssembly::ATOMIC_STORE_I32_A64:
6212
0
  case WebAssembly::ATOMIC_STORE_I64_A32:
6213
0
  case WebAssembly::ATOMIC_STORE_I64_A64:
6214
504
  case WebAssembly::STORE16_I32_A32:
6215
504
  case WebAssembly::STORE16_I32_A64:
6216
505
  case WebAssembly::STORE16_I64_A32:
6217
505
  case WebAssembly::STORE16_I64_A64:
6218
517
  case WebAssembly::STORE32_I64_A32:
6219
517
  case WebAssembly::STORE32_I64_A64:
6220
3.22k
  case WebAssembly::STORE8_I32_A32:
6221
3.22k
  case WebAssembly::STORE8_I32_A64:
6222
3.23k
  case WebAssembly::STORE8_I64_A32:
6223
3.23k
  case WebAssembly::STORE8_I64_A64:
6224
3.84k
  case WebAssembly::STORE_F32_A32:
6225
3.84k
  case WebAssembly::STORE_F32_A64:
6226
4.12k
  case WebAssembly::STORE_F64_A32:
6227
4.12k
  case WebAssembly::STORE_F64_A64:
6228
7.22k
  case WebAssembly::STORE_I32_A32:
6229
7.22k
  case WebAssembly::STORE_I32_A64:
6230
8.08k
  case WebAssembly::STORE_I64_A32:
6231
8.08k
  case WebAssembly::STORE_I64_A64:
6232
8.08k
    return OperandMap[7][NamedIdx];
6233
0
  case WebAssembly::STORE_V128_A32:
6234
0
  case WebAssembly::STORE_V128_A64:
6235
0
    return OperandMap[8][NamedIdx];
6236
0
  case WebAssembly::STORE_LANE_I16x8_A32:
6237
0
  case WebAssembly::STORE_LANE_I16x8_A64:
6238
0
  case WebAssembly::STORE_LANE_I32x4_A32:
6239
0
  case WebAssembly::STORE_LANE_I32x4_A64:
6240
0
  case WebAssembly::STORE_LANE_I64x2_A32:
6241
0
  case WebAssembly::STORE_LANE_I64x2_A64:
6242
0
  case WebAssembly::STORE_LANE_I8x16_A32:
6243
0
  case WebAssembly::STORE_LANE_I8x16_A64:
6244
0
    return OperandMap[9][NamedIdx];
6245
0
  case WebAssembly::LOAD_LANE_I16x8_A32_S:
6246
0
  case WebAssembly::LOAD_LANE_I16x8_A64_S:
6247
0
  case WebAssembly::LOAD_LANE_I32x4_A32_S:
6248
0
  case WebAssembly::LOAD_LANE_I32x4_A64_S:
6249
0
  case WebAssembly::LOAD_LANE_I64x2_A32_S:
6250
0
  case WebAssembly::LOAD_LANE_I64x2_A64_S:
6251
0
  case WebAssembly::LOAD_LANE_I8x16_A32_S:
6252
0
  case WebAssembly::LOAD_LANE_I8x16_A64_S:
6253
0
  case WebAssembly::STORE_LANE_I16x8_A32_S:
6254
0
  case WebAssembly::STORE_LANE_I16x8_A64_S:
6255
0
  case WebAssembly::STORE_LANE_I32x4_A32_S:
6256
0
  case WebAssembly::STORE_LANE_I32x4_A64_S:
6257
0
  case WebAssembly::STORE_LANE_I64x2_A32_S:
6258
0
  case WebAssembly::STORE_LANE_I64x2_A64_S:
6259
0
  case WebAssembly::STORE_LANE_I8x16_A32_S:
6260
0
  case WebAssembly::STORE_LANE_I8x16_A64_S:
6261
0
    return OperandMap[10][NamedIdx];
6262
65.2k
  default: return -1;
6263
75.2k
  }
6264
75.2k
}
6265
} // end namespace WebAssembly
6266
} // end namespace llvm
6267
#endif //GET_INSTRINFO_NAMED_OPS
6268
6269
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
6270
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
6271
namespace llvm {
6272
namespace WebAssembly {
6273
namespace OpTypes {
6274
enum OperandType {
6275
  P2Align = 0,
6276
  Signature = 1,
6277
  TypeIndex = 2,
6278
  bb_op = 3,
6279
  brlist = 4,
6280
  f32imm = 5,
6281
  f32imm_op = 6,
6282
  f64imm = 7,
6283
  f64imm_op = 8,
6284
  function32_op = 9,
6285
  global_op32 = 10,
6286
  global_op64 = 11,
6287
  i1imm = 12,
6288
  i8imm = 13,
6289
  i16imm = 14,
6290
  i32imm = 15,
6291
  i32imm_op = 16,
6292
  i64imm = 17,
6293
  i64imm_op = 18,
6294
  local_op = 19,
6295
  offset32_op = 20,
6296
  offset64_op = 21,
6297
  ptype0 = 22,
6298
  ptype1 = 23,
6299
  ptype2 = 24,
6300
  ptype3 = 25,
6301
  ptype4 = 26,
6302
  ptype5 = 27,
6303
  table32_op = 28,
6304
  tag_op = 29,
6305
  type0 = 30,
6306
  type1 = 31,
6307
  type2 = 32,
6308
  type3 = 33,
6309
  type4 = 34,
6310
  type5 = 35,
6311
  untyped_imm_0 = 36,
6312
  vec_i8imm_op = 37,
6313
  vec_i16imm_op = 38,
6314
  vec_i32imm_op = 39,
6315
  vec_i64imm_op = 40,
6316
  EXTERNREF = 41,
6317
  F32 = 42,
6318
  F64 = 43,
6319
  FUNCREF = 44,
6320
  I32 = 45,
6321
  I64 = 46,
6322
  V128 = 47,
6323
  OPERAND_TYPE_LIST_END
6324
};
6325
} // end namespace OpTypes
6326
} // end namespace WebAssembly
6327
} // end namespace llvm
6328
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
6329
6330
#ifdef GET_INSTRINFO_OPERAND_TYPE
6331
#undef GET_INSTRINFO_OPERAND_TYPE
6332
namespace llvm {
6333
namespace WebAssembly {
6334
LLVM_READONLY
6335
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
6336
  static const uint16_t Offsets[] = {
6337
    /* PHI */
6338
    0,
6339
    /* INLINEASM */
6340
    1,
6341
    /* INLINEASM_BR */
6342
    1,
6343
    /* CFI_INSTRUCTION */
6344
    1,
6345
    /* EH_LABEL */
6346
    2,
6347
    /* GC_LABEL */
6348
    3,
6349
    /* ANNOTATION_LABEL */
6350
    4,
6351
    /* KILL */
6352
    5,
6353
    /* EXTRACT_SUBREG */
6354
    5,
6355
    /* INSERT_SUBREG */
6356
    8,
6357
    /* IMPLICIT_DEF */
6358
    12,
6359
    /* SUBREG_TO_REG */
6360
    13,
6361
    /* COPY_TO_REGCLASS */
6362
    17,
6363
    /* DBG_VALUE */
6364
    20,
6365
    /* DBG_VALUE_LIST */
6366
    20,
6367
    /* DBG_INSTR_REF */
6368
    20,
6369
    /* DBG_PHI */
6370
    20,
6371
    /* DBG_LABEL */
6372
    20,
6373
    /* REG_SEQUENCE */
6374
    21,
6375
    /* COPY */
6376
    23,
6377
    /* BUNDLE */
6378
    25,
6379
    /* LIFETIME_START */
6380
    25,
6381
    /* LIFETIME_END */
6382
    26,
6383
    /* PSEUDO_PROBE */
6384
    27,
6385
    /* ARITH_FENCE */
6386
    31,
6387
    /* STACKMAP */
6388
    33,
6389
    /* FENTRY_CALL */
6390
    35,
6391
    /* PATCHPOINT */
6392
    35,
6393
    /* LOAD_STACK_GUARD */
6394
    41,
6395
    /* PREALLOCATED_SETUP */
6396
    42,
6397
    /* PREALLOCATED_ARG */
6398
    43,
6399
    /* STATEPOINT */
6400
    46,
6401
    /* LOCAL_ESCAPE */
6402
    46,
6403
    /* FAULTING_OP */
6404
    48,
6405
    /* PATCHABLE_OP */
6406
    49,
6407
    /* PATCHABLE_FUNCTION_ENTER */
6408
    49,
6409
    /* PATCHABLE_RET */
6410
    49,
6411
    /* PATCHABLE_FUNCTION_EXIT */
6412
    49,
6413
    /* PATCHABLE_TAIL_CALL */
6414
    49,
6415
    /* PATCHABLE_EVENT_CALL */
6416
    49,
6417
    /* PATCHABLE_TYPED_EVENT_CALL */
6418
    51,
6419
    /* ICALL_BRANCH_FUNNEL */
6420
    54,
6421
    /* MEMBARRIER */
6422
    54,
6423
    /* JUMP_TABLE_DEBUG_INFO */
6424
    54,
6425
    /* G_ASSERT_SEXT */
6426
    55,
6427
    /* G_ASSERT_ZEXT */
6428
    58,
6429
    /* G_ASSERT_ALIGN */
6430
    61,
6431
    /* G_ADD */
6432
    64,
6433
    /* G_SUB */
6434
    67,
6435
    /* G_MUL */
6436
    70,
6437
    /* G_SDIV */
6438
    73,
6439
    /* G_UDIV */
6440
    76,
6441
    /* G_SREM */
6442
    79,
6443
    /* G_UREM */
6444
    82,
6445
    /* G_SDIVREM */
6446
    85,
6447
    /* G_UDIVREM */
6448
    89,
6449
    /* G_AND */
6450
    93,
6451
    /* G_OR */
6452
    96,
6453
    /* G_XOR */
6454
    99,
6455
    /* G_IMPLICIT_DEF */
6456
    102,
6457
    /* G_PHI */
6458
    103,
6459
    /* G_FRAME_INDEX */
6460
    104,
6461
    /* G_GLOBAL_VALUE */
6462
    106,
6463
    /* G_CONSTANT_POOL */
6464
    108,
6465
    /* G_EXTRACT */
6466
    110,
6467
    /* G_UNMERGE_VALUES */
6468
    113,
6469
    /* G_INSERT */
6470
    115,
6471
    /* G_MERGE_VALUES */
6472
    119,
6473
    /* G_BUILD_VECTOR */
6474
    121,
6475
    /* G_BUILD_VECTOR_TRUNC */
6476
    123,
6477
    /* G_CONCAT_VECTORS */
6478
    125,
6479
    /* G_PTRTOINT */
6480
    127,
6481
    /* G_INTTOPTR */
6482
    129,
6483
    /* G_BITCAST */
6484
    131,
6485
    /* G_FREEZE */
6486
    133,
6487
    /* G_CONSTANT_FOLD_BARRIER */
6488
    135,
6489
    /* G_INTRINSIC_FPTRUNC_ROUND */
6490
    137,
6491
    /* G_INTRINSIC_TRUNC */
6492
    140,
6493
    /* G_INTRINSIC_ROUND */
6494
    142,
6495
    /* G_INTRINSIC_LRINT */
6496
    144,
6497
    /* G_INTRINSIC_ROUNDEVEN */
6498
    146,
6499
    /* G_READCYCLECOUNTER */
6500
    148,
6501
    /* G_LOAD */
6502
    149,
6503
    /* G_SEXTLOAD */
6504
    151,
6505
    /* G_ZEXTLOAD */
6506
    153,
6507
    /* G_INDEXED_LOAD */
6508
    155,
6509
    /* G_INDEXED_SEXTLOAD */
6510
    160,
6511
    /* G_INDEXED_ZEXTLOAD */
6512
    165,
6513
    /* G_STORE */
6514
    170,
6515
    /* G_INDEXED_STORE */
6516
    172,
6517
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
6518
    177,
6519
    /* G_ATOMIC_CMPXCHG */
6520
    182,
6521
    /* G_ATOMICRMW_XCHG */
6522
    186,
6523
    /* G_ATOMICRMW_ADD */
6524
    189,
6525
    /* G_ATOMICRMW_SUB */
6526
    192,
6527
    /* G_ATOMICRMW_AND */
6528
    195,
6529
    /* G_ATOMICRMW_NAND */
6530
    198,
6531
    /* G_ATOMICRMW_OR */
6532
    201,
6533
    /* G_ATOMICRMW_XOR */
6534
    204,
6535
    /* G_ATOMICRMW_MAX */
6536
    207,
6537
    /* G_ATOMICRMW_MIN */
6538
    210,
6539
    /* G_ATOMICRMW_UMAX */
6540
    213,
6541
    /* G_ATOMICRMW_UMIN */
6542
    216,
6543
    /* G_ATOMICRMW_FADD */
6544
    219,
6545
    /* G_ATOMICRMW_FSUB */
6546
    222,
6547
    /* G_ATOMICRMW_FMAX */
6548
    225,
6549
    /* G_ATOMICRMW_FMIN */
6550
    228,
6551
    /* G_ATOMICRMW_UINC_WRAP */
6552
    231,
6553
    /* G_ATOMICRMW_UDEC_WRAP */
6554
    234,
6555
    /* G_FENCE */
6556
    237,
6557
    /* G_PREFETCH */
6558
    239,
6559
    /* G_BRCOND */
6560
    243,
6561
    /* G_BRINDIRECT */
6562
    245,
6563
    /* G_INVOKE_REGION_START */
6564
    246,
6565
    /* G_INTRINSIC */
6566
    246,
6567
    /* G_INTRINSIC_W_SIDE_EFFECTS */
6568
    247,
6569
    /* G_INTRINSIC_CONVERGENT */
6570
    248,
6571
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
6572
    249,
6573
    /* G_ANYEXT */
6574
    250,
6575
    /* G_TRUNC */
6576
    252,
6577
    /* G_CONSTANT */
6578
    254,
6579
    /* G_FCONSTANT */
6580
    256,
6581
    /* G_VASTART */
6582
    258,
6583
    /* G_VAARG */
6584
    259,
6585
    /* G_SEXT */
6586
    262,
6587
    /* G_SEXT_INREG */
6588
    264,
6589
    /* G_ZEXT */
6590
    267,
6591
    /* G_SHL */
6592
    269,
6593
    /* G_LSHR */
6594
    272,
6595
    /* G_ASHR */
6596
    275,
6597
    /* G_FSHL */
6598
    278,
6599
    /* G_FSHR */
6600
    282,
6601
    /* G_ROTR */
6602
    286,
6603
    /* G_ROTL */
6604
    289,
6605
    /* G_ICMP */
6606
    292,
6607
    /* G_FCMP */
6608
    296,
6609
    /* G_SELECT */
6610
    300,
6611
    /* G_UADDO */
6612
    304,
6613
    /* G_UADDE */
6614
    308,
6615
    /* G_USUBO */
6616
    313,
6617
    /* G_USUBE */
6618
    317,
6619
    /* G_SADDO */
6620
    322,
6621
    /* G_SADDE */
6622
    326,
6623
    /* G_SSUBO */
6624
    331,
6625
    /* G_SSUBE */
6626
    335,
6627
    /* G_UMULO */
6628
    340,
6629
    /* G_SMULO */
6630
    344,
6631
    /* G_UMULH */
6632
    348,
6633
    /* G_SMULH */
6634
    351,
6635
    /* G_UADDSAT */
6636
    354,
6637
    /* G_SADDSAT */
6638
    357,
6639
    /* G_USUBSAT */
6640
    360,
6641
    /* G_SSUBSAT */
6642
    363,
6643
    /* G_USHLSAT */
6644
    366,
6645
    /* G_SSHLSAT */
6646
    369,
6647
    /* G_SMULFIX */
6648
    372,
6649
    /* G_UMULFIX */
6650
    376,
6651
    /* G_SMULFIXSAT */
6652
    380,
6653
    /* G_UMULFIXSAT */
6654
    384,
6655
    /* G_SDIVFIX */
6656
    388,
6657
    /* G_UDIVFIX */
6658
    392,
6659
    /* G_SDIVFIXSAT */
6660
    396,
6661
    /* G_UDIVFIXSAT */
6662
    400,
6663
    /* G_FADD */
6664
    404,
6665
    /* G_FSUB */
6666
    407,
6667
    /* G_FMUL */
6668
    410,
6669
    /* G_FMA */
6670
    413,
6671
    /* G_FMAD */
6672
    417,
6673
    /* G_FDIV */
6674
    421,
6675
    /* G_FREM */
6676
    424,
6677
    /* G_FPOW */
6678
    427,
6679
    /* G_FPOWI */
6680
    430,
6681
    /* G_FEXP */
6682
    433,
6683
    /* G_FEXP2 */
6684
    435,
6685
    /* G_FEXP10 */
6686
    437,
6687
    /* G_FLOG */
6688
    439,
6689
    /* G_FLOG2 */
6690
    441,
6691
    /* G_FLOG10 */
6692
    443,
6693
    /* G_FLDEXP */
6694
    445,
6695
    /* G_FFREXP */
6696
    448,
6697
    /* G_FNEG */
6698
    451,
6699
    /* G_FPEXT */
6700
    453,
6701
    /* G_FPTRUNC */
6702
    455,
6703
    /* G_FPTOSI */
6704
    457,
6705
    /* G_FPTOUI */
6706
    459,
6707
    /* G_SITOFP */
6708
    461,
6709
    /* G_UITOFP */
6710
    463,
6711
    /* G_FABS */
6712
    465,
6713
    /* G_FCOPYSIGN */
6714
    467,
6715
    /* G_IS_FPCLASS */
6716
    470,
6717
    /* G_FCANONICALIZE */
6718
    473,
6719
    /* G_FMINNUM */
6720
    475,
6721
    /* G_FMAXNUM */
6722
    478,
6723
    /* G_FMINNUM_IEEE */
6724
    481,
6725
    /* G_FMAXNUM_IEEE */
6726
    484,
6727
    /* G_FMINIMUM */
6728
    487,
6729
    /* G_FMAXIMUM */
6730
    490,
6731
    /* G_GET_FPENV */
6732
    493,
6733
    /* G_SET_FPENV */
6734
    494,
6735
    /* G_RESET_FPENV */
6736
    495,
6737
    /* G_GET_FPMODE */
6738
    495,
6739
    /* G_SET_FPMODE */
6740
    496,
6741
    /* G_RESET_FPMODE */
6742
    497,
6743
    /* G_PTR_ADD */
6744
    497,
6745
    /* G_PTRMASK */
6746
    500,
6747
    /* G_SMIN */
6748
    503,
6749
    /* G_SMAX */
6750
    506,
6751
    /* G_UMIN */
6752
    509,
6753
    /* G_UMAX */
6754
    512,
6755
    /* G_ABS */
6756
    515,
6757
    /* G_LROUND */
6758
    517,
6759
    /* G_LLROUND */
6760
    519,
6761
    /* G_BR */
6762
    521,
6763
    /* G_BRJT */
6764
    522,
6765
    /* G_INSERT_VECTOR_ELT */
6766
    525,
6767
    /* G_EXTRACT_VECTOR_ELT */
6768
    529,
6769
    /* G_SHUFFLE_VECTOR */
6770
    532,
6771
    /* G_CTTZ */
6772
    536,
6773
    /* G_CTTZ_ZERO_UNDEF */
6774
    538,
6775
    /* G_CTLZ */
6776
    540,
6777
    /* G_CTLZ_ZERO_UNDEF */
6778
    542,
6779
    /* G_CTPOP */
6780
    544,
6781
    /* G_BSWAP */
6782
    546,
6783
    /* G_BITREVERSE */
6784
    548,
6785
    /* G_FCEIL */
6786
    550,
6787
    /* G_FCOS */
6788
    552,
6789
    /* G_FSIN */
6790
    554,
6791
    /* G_FSQRT */
6792
    556,
6793
    /* G_FFLOOR */
6794
    558,
6795
    /* G_FRINT */
6796
    560,
6797
    /* G_FNEARBYINT */
6798
    562,
6799
    /* G_ADDRSPACE_CAST */
6800
    564,
6801
    /* G_BLOCK_ADDR */
6802
    566,
6803
    /* G_JUMP_TABLE */
6804
    568,
6805
    /* G_DYN_STACKALLOC */
6806
    570,
6807
    /* G_STACKSAVE */
6808
    573,
6809
    /* G_STACKRESTORE */
6810
    574,
6811
    /* G_STRICT_FADD */
6812
    575,
6813
    /* G_STRICT_FSUB */
6814
    578,
6815
    /* G_STRICT_FMUL */
6816
    581,
6817
    /* G_STRICT_FDIV */
6818
    584,
6819
    /* G_STRICT_FREM */
6820
    587,
6821
    /* G_STRICT_FMA */
6822
    590,
6823
    /* G_STRICT_FSQRT */
6824
    594,
6825
    /* G_STRICT_FLDEXP */
6826
    596,
6827
    /* G_READ_REGISTER */
6828
    599,
6829
    /* G_WRITE_REGISTER */
6830
    601,
6831
    /* G_MEMCPY */
6832
    603,
6833
    /* G_MEMCPY_INLINE */
6834
    607,
6835
    /* G_MEMMOVE */
6836
    610,
6837
    /* G_MEMSET */
6838
    614,
6839
    /* G_BZERO */
6840
    618,
6841
    /* G_VECREDUCE_SEQ_FADD */
6842
    621,
6843
    /* G_VECREDUCE_SEQ_FMUL */
6844
    624,
6845
    /* G_VECREDUCE_FADD */
6846
    627,
6847
    /* G_VECREDUCE_FMUL */
6848
    629,
6849
    /* G_VECREDUCE_FMAX */
6850
    631,
6851
    /* G_VECREDUCE_FMIN */
6852
    633,
6853
    /* G_VECREDUCE_FMAXIMUM */
6854
    635,
6855
    /* G_VECREDUCE_FMINIMUM */
6856
    637,
6857
    /* G_VECREDUCE_ADD */
6858
    639,
6859
    /* G_VECREDUCE_MUL */
6860
    641,
6861
    /* G_VECREDUCE_AND */
6862
    643,
6863
    /* G_VECREDUCE_OR */
6864
    645,
6865
    /* G_VECREDUCE_XOR */
6866
    647,
6867
    /* G_VECREDUCE_SMAX */
6868
    649,
6869
    /* G_VECREDUCE_SMIN */
6870
    651,
6871
    /* G_VECREDUCE_UMAX */
6872
    653,
6873
    /* G_VECREDUCE_UMIN */
6874
    655,
6875
    /* G_SBFX */
6876
    657,
6877
    /* G_UBFX */
6878
    661,
6879
    /* CALL_PARAMS */
6880
    665,
6881
    /* CALL_PARAMS_S */
6882
    666,
6883
    /* CALL_RESULTS */
6884
    667,
6885
    /* CALL_RESULTS_S */
6886
    667,
6887
    /* CATCHRET */
6888
    667,
6889
    /* CATCHRET_S */
6890
    669,
6891
    /* CLEANUPRET */
6892
    671,
6893
    /* CLEANUPRET_S */
6894
    671,
6895
    /* COMPILER_FENCE */
6896
    671,
6897
    /* COMPILER_FENCE_S */
6898
    671,
6899
    /* RET_CALL_RESULTS */
6900
    671,
6901
    /* RET_CALL_RESULTS_S */
6902
    671,
6903
    /* ABS_F32 */
6904
    671,
6905
    /* ABS_F32_S */
6906
    673,
6907
    /* ABS_F32x4 */
6908
    673,
6909
    /* ABS_F32x4_S */
6910
    675,
6911
    /* ABS_F64 */
6912
    675,
6913
    /* ABS_F64_S */
6914
    677,
6915
    /* ABS_F64x2 */
6916
    677,
6917
    /* ABS_F64x2_S */
6918
    679,
6919
    /* ABS_I16x8 */
6920
    679,
6921
    /* ABS_I16x8_S */
6922
    681,
6923
    /* ABS_I32x4 */
6924
    681,
6925
    /* ABS_I32x4_S */
6926
    683,
6927
    /* ABS_I64x2 */
6928
    683,
6929
    /* ABS_I64x2_S */
6930
    685,
6931
    /* ABS_I8x16 */
6932
    685,
6933
    /* ABS_I8x16_S */
6934
    687,
6935
    /* ADD_F32 */
6936
    687,
6937
    /* ADD_F32_S */
6938
    690,
6939
    /* ADD_F32x4 */
6940
    690,
6941
    /* ADD_F32x4_S */
6942
    693,
6943
    /* ADD_F64 */
6944
    693,
6945
    /* ADD_F64_S */
6946
    696,
6947
    /* ADD_F64x2 */
6948
    696,
6949
    /* ADD_F64x2_S */
6950
    699,
6951
    /* ADD_I16x8 */
6952
    699,
6953
    /* ADD_I16x8_S */
6954
    702,
6955
    /* ADD_I32 */
6956
    702,
6957
    /* ADD_I32_S */
6958
    705,
6959
    /* ADD_I32x4 */
6960
    705,
6961
    /* ADD_I32x4_S */
6962
    708,
6963
    /* ADD_I64 */
6964
    708,
6965
    /* ADD_I64_S */
6966
    711,
6967
    /* ADD_I64x2 */
6968
    711,
6969
    /* ADD_I64x2_S */
6970
    714,
6971
    /* ADD_I8x16 */
6972
    714,
6973
    /* ADD_I8x16_S */
6974
    717,
6975
    /* ADD_SAT_S_I16x8 */
6976
    717,
6977
    /* ADD_SAT_S_I16x8_S */
6978
    720,
6979
    /* ADD_SAT_S_I8x16 */
6980
    720,
6981
    /* ADD_SAT_S_I8x16_S */
6982
    723,
6983
    /* ADD_SAT_U_I16x8 */
6984
    723,
6985
    /* ADD_SAT_U_I16x8_S */
6986
    726,
6987
    /* ADD_SAT_U_I8x16 */
6988
    726,
6989
    /* ADD_SAT_U_I8x16_S */
6990
    729,
6991
    /* ADJCALLSTACKDOWN */
6992
    729,
6993
    /* ADJCALLSTACKDOWN_S */
6994
    731,
6995
    /* ADJCALLSTACKUP */
6996
    733,
6997
    /* ADJCALLSTACKUP_S */
6998
    735,
6999
    /* ALLTRUE_I16x8 */
7000
    737,
7001
    /* ALLTRUE_I16x8_S */
7002
    739,
7003
    /* ALLTRUE_I32x4 */
7004
    739,
7005
    /* ALLTRUE_I32x4_S */
7006
    741,
7007
    /* ALLTRUE_I64x2 */
7008
    741,
7009
    /* ALLTRUE_I64x2_S */
7010
    743,
7011
    /* ALLTRUE_I8x16 */
7012
    743,
7013
    /* ALLTRUE_I8x16_S */
7014
    745,
7015
    /* AND */
7016
    745,
7017
    /* ANDNOT */
7018
    748,
7019
    /* ANDNOT_S */
7020
    751,
7021
    /* AND_I32 */
7022
    751,
7023
    /* AND_I32_S */
7024
    754,
7025
    /* AND_I64 */
7026
    754,
7027
    /* AND_I64_S */
7028
    757,
7029
    /* AND_S */
7030
    757,
7031
    /* ANYTRUE */
7032
    757,
7033
    /* ANYTRUE_S */
7034
    759,
7035
    /* ARGUMENT_externref */
7036
    759,
7037
    /* ARGUMENT_externref_S */
7038
    761,
7039
    /* ARGUMENT_f32 */
7040
    762,
7041
    /* ARGUMENT_f32_S */
7042
    764,
7043
    /* ARGUMENT_f64 */
7044
    765,
7045
    /* ARGUMENT_f64_S */
7046
    767,
7047
    /* ARGUMENT_funcref */
7048
    768,
7049
    /* ARGUMENT_funcref_S */
7050
    770,
7051
    /* ARGUMENT_i32 */
7052
    771,
7053
    /* ARGUMENT_i32_S */
7054
    773,
7055
    /* ARGUMENT_i64 */
7056
    774,
7057
    /* ARGUMENT_i64_S */
7058
    776,
7059
    /* ARGUMENT_v16i8 */
7060
    777,
7061
    /* ARGUMENT_v16i8_S */
7062
    779,
7063
    /* ARGUMENT_v2f64 */
7064
    780,
7065
    /* ARGUMENT_v2f64_S */
7066
    782,
7067
    /* ARGUMENT_v2i64 */
7068
    783,
7069
    /* ARGUMENT_v2i64_S */
7070
    785,
7071
    /* ARGUMENT_v4f32 */
7072
    786,
7073
    /* ARGUMENT_v4f32_S */
7074
    788,
7075
    /* ARGUMENT_v4i32 */
7076
    789,
7077
    /* ARGUMENT_v4i32_S */
7078
    791,
7079
    /* ARGUMENT_v8i16 */
7080
    792,
7081
    /* ARGUMENT_v8i16_S */
7082
    794,
7083
    /* ATOMIC_FENCE */
7084
    795,
7085
    /* ATOMIC_FENCE_S */
7086
    796,
7087
    /* ATOMIC_LOAD16_U_I32_A32 */
7088
    797,
7089
    /* ATOMIC_LOAD16_U_I32_A32_S */
7090
    801,
7091
    /* ATOMIC_LOAD16_U_I32_A64 */
7092
    803,
7093
    /* ATOMIC_LOAD16_U_I32_A64_S */
7094
    807,
7095
    /* ATOMIC_LOAD16_U_I64_A32 */
7096
    809,
7097
    /* ATOMIC_LOAD16_U_I64_A32_S */
7098
    813,
7099
    /* ATOMIC_LOAD16_U_I64_A64 */
7100
    815,
7101
    /* ATOMIC_LOAD16_U_I64_A64_S */
7102
    819,
7103
    /* ATOMIC_LOAD32_U_I64_A32 */
7104
    821,
7105
    /* ATOMIC_LOAD32_U_I64_A32_S */
7106
    825,
7107
    /* ATOMIC_LOAD32_U_I64_A64 */
7108
    827,
7109
    /* ATOMIC_LOAD32_U_I64_A64_S */
7110
    831,
7111
    /* ATOMIC_LOAD8_U_I32_A32 */
7112
    833,
7113
    /* ATOMIC_LOAD8_U_I32_A32_S */
7114
    837,
7115
    /* ATOMIC_LOAD8_U_I32_A64 */
7116
    839,
7117
    /* ATOMIC_LOAD8_U_I32_A64_S */
7118
    843,
7119
    /* ATOMIC_LOAD8_U_I64_A32 */
7120
    845,
7121
    /* ATOMIC_LOAD8_U_I64_A32_S */
7122
    849,
7123
    /* ATOMIC_LOAD8_U_I64_A64 */
7124
    851,
7125
    /* ATOMIC_LOAD8_U_I64_A64_S */
7126
    855,
7127
    /* ATOMIC_LOAD_I32_A32 */
7128
    857,
7129
    /* ATOMIC_LOAD_I32_A32_S */
7130
    861,
7131
    /* ATOMIC_LOAD_I32_A64 */
7132
    863,
7133
    /* ATOMIC_LOAD_I32_A64_S */
7134
    867,
7135
    /* ATOMIC_LOAD_I64_A32 */
7136
    869,
7137
    /* ATOMIC_LOAD_I64_A32_S */
7138
    873,
7139
    /* ATOMIC_LOAD_I64_A64 */
7140
    875,
7141
    /* ATOMIC_LOAD_I64_A64_S */
7142
    879,
7143
    /* ATOMIC_RMW16_U_ADD_I32_A32 */
7144
    881,
7145
    /* ATOMIC_RMW16_U_ADD_I32_A32_S */
7146
    886,
7147
    /* ATOMIC_RMW16_U_ADD_I32_A64 */
7148
    888,
7149
    /* ATOMIC_RMW16_U_ADD_I32_A64_S */
7150
    893,
7151
    /* ATOMIC_RMW16_U_ADD_I64_A32 */
7152
    895,
7153
    /* ATOMIC_RMW16_U_ADD_I64_A32_S */
7154
    900,
7155
    /* ATOMIC_RMW16_U_ADD_I64_A64 */
7156
    902,
7157
    /* ATOMIC_RMW16_U_ADD_I64_A64_S */
7158
    907,
7159
    /* ATOMIC_RMW16_U_AND_I32_A32 */
7160
    909,
7161
    /* ATOMIC_RMW16_U_AND_I32_A32_S */
7162
    914,
7163
    /* ATOMIC_RMW16_U_AND_I32_A64 */
7164
    916,
7165
    /* ATOMIC_RMW16_U_AND_I32_A64_S */
7166
    921,
7167
    /* ATOMIC_RMW16_U_AND_I64_A32 */
7168
    923,
7169
    /* ATOMIC_RMW16_U_AND_I64_A32_S */
7170
    928,
7171
    /* ATOMIC_RMW16_U_AND_I64_A64 */
7172
    930,
7173
    /* ATOMIC_RMW16_U_AND_I64_A64_S */
7174
    935,
7175
    /* ATOMIC_RMW16_U_CMPXCHG_I32_A32 */
7176
    937,
7177
    /* ATOMIC_RMW16_U_CMPXCHG_I32_A32_S */
7178
    943,
7179
    /* ATOMIC_RMW16_U_CMPXCHG_I32_A64 */
7180
    945,
7181
    /* ATOMIC_RMW16_U_CMPXCHG_I32_A64_S */
7182
    951,
7183
    /* ATOMIC_RMW16_U_CMPXCHG_I64_A32 */
7184
    953,
7185
    /* ATOMIC_RMW16_U_CMPXCHG_I64_A32_S */
7186
    959,
7187
    /* ATOMIC_RMW16_U_CMPXCHG_I64_A64 */
7188
    961,
7189
    /* ATOMIC_RMW16_U_CMPXCHG_I64_A64_S */
7190
    967,
7191
    /* ATOMIC_RMW16_U_OR_I32_A32 */
7192
    969,
7193
    /* ATOMIC_RMW16_U_OR_I32_A32_S */
7194
    974,
7195
    /* ATOMIC_RMW16_U_OR_I32_A64 */
7196
    976,
7197
    /* ATOMIC_RMW16_U_OR_I32_A64_S */
7198
    981,
7199
    /* ATOMIC_RMW16_U_OR_I64_A32 */
7200
    983,
7201
    /* ATOMIC_RMW16_U_OR_I64_A32_S */
7202
    988,
7203
    /* ATOMIC_RMW16_U_OR_I64_A64 */
7204
    990,
7205
    /* ATOMIC_RMW16_U_OR_I64_A64_S */
7206
    995,
7207
    /* ATOMIC_RMW16_U_SUB_I32_A32 */
7208
    997,
7209
    /* ATOMIC_RMW16_U_SUB_I32_A32_S */
7210
    1002,
7211
    /* ATOMIC_RMW16_U_SUB_I32_A64 */
7212
    1004,
7213
    /* ATOMIC_RMW16_U_SUB_I32_A64_S */
7214
    1009,
7215
    /* ATOMIC_RMW16_U_SUB_I64_A32 */
7216
    1011,
7217
    /* ATOMIC_RMW16_U_SUB_I64_A32_S */
7218
    1016,
7219
    /* ATOMIC_RMW16_U_SUB_I64_A64 */
7220
    1018,
7221
    /* ATOMIC_RMW16_U_SUB_I64_A64_S */
7222
    1023,
7223
    /* ATOMIC_RMW16_U_XCHG_I32_A32 */
7224
    1025,
7225
    /* ATOMIC_RMW16_U_XCHG_I32_A32_S */
7226
    1030,
7227
    /* ATOMIC_RMW16_U_XCHG_I32_A64 */
7228
    1032,
7229
    /* ATOMIC_RMW16_U_XCHG_I32_A64_S */
7230
    1037,
7231
    /* ATOMIC_RMW16_U_XCHG_I64_A32 */
7232
    1039,
7233
    /* ATOMIC_RMW16_U_XCHG_I64_A32_S */
7234
    1044,
7235
    /* ATOMIC_RMW16_U_XCHG_I64_A64 */
7236
    1046,
7237
    /* ATOMIC_RMW16_U_XCHG_I64_A64_S */
7238
    1051,
7239
    /* ATOMIC_RMW16_U_XOR_I32_A32 */
7240
    1053,
7241
    /* ATOMIC_RMW16_U_XOR_I32_A32_S */
7242
    1058,
7243
    /* ATOMIC_RMW16_U_XOR_I32_A64 */
7244
    1060,
7245
    /* ATOMIC_RMW16_U_XOR_I32_A64_S */
7246
    1065,
7247
    /* ATOMIC_RMW16_U_XOR_I64_A32 */
7248
    1067,
7249
    /* ATOMIC_RMW16_U_XOR_I64_A32_S */
7250
    1072,
7251
    /* ATOMIC_RMW16_U_XOR_I64_A64 */
7252
    1074,
7253
    /* ATOMIC_RMW16_U_XOR_I64_A64_S */
7254
    1079,
7255
    /* ATOMIC_RMW32_U_ADD_I64_A32 */
7256
    1081,
7257
    /* ATOMIC_RMW32_U_ADD_I64_A32_S */
7258
    1086,
7259
    /* ATOMIC_RMW32_U_ADD_I64_A64 */
7260
    1088,
7261
    /* ATOMIC_RMW32_U_ADD_I64_A64_S */
7262
    1093,
7263
    /* ATOMIC_RMW32_U_AND_I64_A32 */
7264
    1095,
7265
    /* ATOMIC_RMW32_U_AND_I64_A32_S */
7266
    1100,
7267
    /* ATOMIC_RMW32_U_AND_I64_A64 */
7268
    1102,
7269
    /* ATOMIC_RMW32_U_AND_I64_A64_S */
7270
    1107,
7271
    /* ATOMIC_RMW32_U_CMPXCHG_I64_A32 */
7272
    1109,
7273
    /* ATOMIC_RMW32_U_CMPXCHG_I64_A32_S */
7274
    1115,
7275
    /* ATOMIC_RMW32_U_CMPXCHG_I64_A64 */
7276
    1117,
7277
    /* ATOMIC_RMW32_U_CMPXCHG_I64_A64_S */
7278
    1123,
7279
    /* ATOMIC_RMW32_U_OR_I64_A32 */
7280
    1125,
7281
    /* ATOMIC_RMW32_U_OR_I64_A32_S */
7282
    1130,
7283
    /* ATOMIC_RMW32_U_OR_I64_A64 */
7284
    1132,
7285
    /* ATOMIC_RMW32_U_OR_I64_A64_S */
7286
    1137,
7287
    /* ATOMIC_RMW32_U_SUB_I64_A32 */
7288
    1139,
7289
    /* ATOMIC_RMW32_U_SUB_I64_A32_S */
7290
    1144,
7291
    /* ATOMIC_RMW32_U_SUB_I64_A64 */
7292
    1146,
7293
    /* ATOMIC_RMW32_U_SUB_I64_A64_S */
7294
    1151,
7295
    /* ATOMIC_RMW32_U_XCHG_I64_A32 */
7296
    1153,
7297
    /* ATOMIC_RMW32_U_XCHG_I64_A32_S */
7298
    1158,
7299
    /* ATOMIC_RMW32_U_XCHG_I64_A64 */
7300
    1160,
7301
    /* ATOMIC_RMW32_U_XCHG_I64_A64_S */
7302
    1165,
7303
    /* ATOMIC_RMW32_U_XOR_I64_A32 */
7304
    1167,
7305
    /* ATOMIC_RMW32_U_XOR_I64_A32_S */
7306
    1172,
7307
    /* ATOMIC_RMW32_U_XOR_I64_A64 */
7308
    1174,
7309
    /* ATOMIC_RMW32_U_XOR_I64_A64_S */
7310
    1179,
7311
    /* ATOMIC_RMW8_U_ADD_I32_A32 */
7312
    1181,
7313
    /* ATOMIC_RMW8_U_ADD_I32_A32_S */
7314
    1186,
7315
    /* ATOMIC_RMW8_U_ADD_I32_A64 */
7316
    1188,
7317
    /* ATOMIC_RMW8_U_ADD_I32_A64_S */
7318
    1193,
7319
    /* ATOMIC_RMW8_U_ADD_I64_A32 */
7320
    1195,
7321
    /* ATOMIC_RMW8_U_ADD_I64_A32_S */
7322
    1200,
7323
    /* ATOMIC_RMW8_U_ADD_I64_A64 */
7324
    1202,
7325
    /* ATOMIC_RMW8_U_ADD_I64_A64_S */
7326
    1207,
7327
    /* ATOMIC_RMW8_U_AND_I32_A32 */
7328
    1209,
7329
    /* ATOMIC_RMW8_U_AND_I32_A32_S */
7330
    1214,
7331
    /* ATOMIC_RMW8_U_AND_I32_A64 */
7332
    1216,
7333
    /* ATOMIC_RMW8_U_AND_I32_A64_S */
7334
    1221,
7335
    /* ATOMIC_RMW8_U_AND_I64_A32 */
7336
    1223,
7337
    /* ATOMIC_RMW8_U_AND_I64_A32_S */
7338
    1228,
7339
    /* ATOMIC_RMW8_U_AND_I64_A64 */
7340
    1230,
7341
    /* ATOMIC_RMW8_U_AND_I64_A64_S */
7342
    1235,
7343
    /* ATOMIC_RMW8_U_CMPXCHG_I32_A32 */
7344
    1237,
7345
    /* ATOMIC_RMW8_U_CMPXCHG_I32_A32_S */
7346
    1243,
7347
    /* ATOMIC_RMW8_U_CMPXCHG_I32_A64 */
7348
    1245,
7349
    /* ATOMIC_RMW8_U_CMPXCHG_I32_A64_S */
7350
    1251,
7351
    /* ATOMIC_RMW8_U_CMPXCHG_I64_A32 */
7352
    1253,
7353
    /* ATOMIC_RMW8_U_CMPXCHG_I64_A32_S */
7354
    1259,
7355
    /* ATOMIC_RMW8_U_CMPXCHG_I64_A64 */
7356
    1261,
7357
    /* ATOMIC_RMW8_U_CMPXCHG_I64_A64_S */
7358
    1267,
7359
    /* ATOMIC_RMW8_U_OR_I32_A32 */
7360
    1269,
7361
    /* ATOMIC_RMW8_U_OR_I32_A32_S */
7362
    1274,
7363
    /* ATOMIC_RMW8_U_OR_I32_A64 */
7364
    1276,
7365
    /* ATOMIC_RMW8_U_OR_I32_A64_S */
7366
    1281,
7367
    /* ATOMIC_RMW8_U_OR_I64_A32 */
7368
    1283,
7369
    /* ATOMIC_RMW8_U_OR_I64_A32_S */
7370
    1288,
7371
    /* ATOMIC_RMW8_U_OR_I64_A64 */
7372
    1290,
7373
    /* ATOMIC_RMW8_U_OR_I64_A64_S */
7374
    1295,
7375
    /* ATOMIC_RMW8_U_SUB_I32_A32 */
7376
    1297,
7377
    /* ATOMIC_RMW8_U_SUB_I32_A32_S */
7378
    1302,
7379
    /* ATOMIC_RMW8_U_SUB_I32_A64 */
7380
    1304,
7381
    /* ATOMIC_RMW8_U_SUB_I32_A64_S */
7382
    1309,
7383
    /* ATOMIC_RMW8_U_SUB_I64_A32 */
7384
    1311,
7385
    /* ATOMIC_RMW8_U_SUB_I64_A32_S */
7386
    1316,
7387
    /* ATOMIC_RMW8_U_SUB_I64_A64 */
7388
    1318,
7389
    /* ATOMIC_RMW8_U_SUB_I64_A64_S */
7390
    1323,
7391
    /* ATOMIC_RMW8_U_XCHG_I32_A32 */
7392
    1325,
7393
    /* ATOMIC_RMW8_U_XCHG_I32_A32_S */
7394
    1330,
7395
    /* ATOMIC_RMW8_U_XCHG_I32_A64 */
7396
    1332,
7397
    /* ATOMIC_RMW8_U_XCHG_I32_A64_S */
7398
    1337,
7399
    /* ATOMIC_RMW8_U_XCHG_I64_A32 */
7400
    1339,
7401
    /* ATOMIC_RMW8_U_XCHG_I64_A32_S */
7402
    1344,
7403
    /* ATOMIC_RMW8_U_XCHG_I64_A64 */
7404
    1346,
7405
    /* ATOMIC_RMW8_U_XCHG_I64_A64_S */
7406
    1351,
7407
    /* ATOMIC_RMW8_U_XOR_I32_A32 */
7408
    1353,
7409
    /* ATOMIC_RMW8_U_XOR_I32_A32_S */
7410
    1358,
7411
    /* ATOMIC_RMW8_U_XOR_I32_A64 */
7412
    1360,
7413
    /* ATOMIC_RMW8_U_XOR_I32_A64_S */
7414
    1365,
7415
    /* ATOMIC_RMW8_U_XOR_I64_A32 */
7416
    1367,
7417
    /* ATOMIC_RMW8_U_XOR_I64_A32_S */
7418
    1372,
7419
    /* ATOMIC_RMW8_U_XOR_I64_A64 */
7420
    1374,
7421
    /* ATOMIC_RMW8_U_XOR_I64_A64_S */
7422
    1379,
7423
    /* ATOMIC_RMW_ADD_I32_A32 */
7424
    1381,
7425
    /* ATOMIC_RMW_ADD_I32_A32_S */
7426
    1386,
7427
    /* ATOMIC_RMW_ADD_I32_A64 */
7428
    1388,
7429
    /* ATOMIC_RMW_ADD_I32_A64_S */
7430
    1393,
7431
    /* ATOMIC_RMW_ADD_I64_A32 */
7432
    1395,
7433
    /* ATOMIC_RMW_ADD_I64_A32_S */
7434
    1400,
7435
    /* ATOMIC_RMW_ADD_I64_A64 */
7436
    1402,
7437
    /* ATOMIC_RMW_ADD_I64_A64_S */
7438
    1407,
7439
    /* ATOMIC_RMW_AND_I32_A32 */
7440
    1409,
7441
    /* ATOMIC_RMW_AND_I32_A32_S */
7442
    1414,
7443
    /* ATOMIC_RMW_AND_I32_A64 */
7444
    1416,
7445
    /* ATOMIC_RMW_AND_I32_A64_S */
7446
    1421,
7447
    /* ATOMIC_RMW_AND_I64_A32 */
7448
    1423,
7449
    /* ATOMIC_RMW_AND_I64_A32_S */
7450
    1428,
7451
    /* ATOMIC_RMW_AND_I64_A64 */
7452
    1430,
7453
    /* ATOMIC_RMW_AND_I64_A64_S */
7454
    1435,
7455
    /* ATOMIC_RMW_CMPXCHG_I32_A32 */
7456
    1437,
7457
    /* ATOMIC_RMW_CMPXCHG_I32_A32_S */
7458
    1443,
7459
    /* ATOMIC_RMW_CMPXCHG_I32_A64 */
7460
    1445,
7461
    /* ATOMIC_RMW_CMPXCHG_I32_A64_S */
7462
    1451,
7463
    /* ATOMIC_RMW_CMPXCHG_I64_A32 */
7464
    1453,
7465
    /* ATOMIC_RMW_CMPXCHG_I64_A32_S */
7466
    1459,
7467
    /* ATOMIC_RMW_CMPXCHG_I64_A64 */
7468
    1461,
7469
    /* ATOMIC_RMW_CMPXCHG_I64_A64_S */
7470
    1467,
7471
    /* ATOMIC_RMW_OR_I32_A32 */
7472
    1469,
7473
    /* ATOMIC_RMW_OR_I32_A32_S */
7474
    1474,
7475
    /* ATOMIC_RMW_OR_I32_A64 */
7476
    1476,
7477
    /* ATOMIC_RMW_OR_I32_A64_S */
7478
    1481,
7479
    /* ATOMIC_RMW_OR_I64_A32 */
7480
    1483,
7481
    /* ATOMIC_RMW_OR_I64_A32_S */
7482
    1488,
7483
    /* ATOMIC_RMW_OR_I64_A64 */
7484
    1490,
7485
    /* ATOMIC_RMW_OR_I64_A64_S */
7486
    1495,
7487
    /* ATOMIC_RMW_SUB_I32_A32 */
7488
    1497,
7489
    /* ATOMIC_RMW_SUB_I32_A32_S */
7490
    1502,
7491
    /* ATOMIC_RMW_SUB_I32_A64 */
7492
    1504,
7493
    /* ATOMIC_RMW_SUB_I32_A64_S */
7494
    1509,
7495
    /* ATOMIC_RMW_SUB_I64_A32 */
7496
    1511,
7497
    /* ATOMIC_RMW_SUB_I64_A32_S */
7498
    1516,
7499
    /* ATOMIC_RMW_SUB_I64_A64 */
7500
    1518,
7501
    /* ATOMIC_RMW_SUB_I64_A64_S */
7502
    1523,
7503
    /* ATOMIC_RMW_XCHG_I32_A32 */
7504
    1525,
7505
    /* ATOMIC_RMW_XCHG_I32_A32_S */
7506
    1530,
7507
    /* ATOMIC_RMW_XCHG_I32_A64 */
7508
    1532,
7509
    /* ATOMIC_RMW_XCHG_I32_A64_S */
7510
    1537,
7511
    /* ATOMIC_RMW_XCHG_I64_A32 */
7512
    1539,
7513
    /* ATOMIC_RMW_XCHG_I64_A32_S */
7514
    1544,
7515
    /* ATOMIC_RMW_XCHG_I64_A64 */
7516
    1546,
7517
    /* ATOMIC_RMW_XCHG_I64_A64_S */
7518
    1551,
7519
    /* ATOMIC_RMW_XOR_I32_A32 */
7520
    1553,
7521
    /* ATOMIC_RMW_XOR_I32_A32_S */
7522
    1558,
7523
    /* ATOMIC_RMW_XOR_I32_A64 */
7524
    1560,
7525
    /* ATOMIC_RMW_XOR_I32_A64_S */
7526
    1565,
7527
    /* ATOMIC_RMW_XOR_I64_A32 */
7528
    1567,
7529
    /* ATOMIC_RMW_XOR_I64_A32_S */
7530
    1572,
7531
    /* ATOMIC_RMW_XOR_I64_A64 */
7532
    1574,
7533
    /* ATOMIC_RMW_XOR_I64_A64_S */
7534
    1579,
7535
    /* ATOMIC_STORE16_I32_A32 */
7536
    1581,
7537
    /* ATOMIC_STORE16_I32_A32_S */
7538
    1585,
7539
    /* ATOMIC_STORE16_I32_A64 */
7540
    1587,
7541
    /* ATOMIC_STORE16_I32_A64_S */
7542
    1591,
7543
    /* ATOMIC_STORE16_I64_A32 */
7544
    1593,
7545
    /* ATOMIC_STORE16_I64_A32_S */
7546
    1597,
7547
    /* ATOMIC_STORE16_I64_A64 */
7548
    1599,
7549
    /* ATOMIC_STORE16_I64_A64_S */
7550
    1603,
7551
    /* ATOMIC_STORE32_I64_A32 */
7552
    1605,
7553
    /* ATOMIC_STORE32_I64_A32_S */
7554
    1609,
7555
    /* ATOMIC_STORE32_I64_A64 */
7556
    1611,
7557
    /* ATOMIC_STORE32_I64_A64_S */
7558
    1615,
7559
    /* ATOMIC_STORE8_I32_A32 */
7560
    1617,
7561
    /* ATOMIC_STORE8_I32_A32_S */
7562
    1621,
7563
    /* ATOMIC_STORE8_I32_A64 */
7564
    1623,
7565
    /* ATOMIC_STORE8_I32_A64_S */
7566
    1627,
7567
    /* ATOMIC_STORE8_I64_A32 */
7568
    1629,
7569
    /* ATOMIC_STORE8_I64_A32_S */
7570
    1633,
7571
    /* ATOMIC_STORE8_I64_A64 */
7572
    1635,
7573
    /* ATOMIC_STORE8_I64_A64_S */
7574
    1639,
7575
    /* ATOMIC_STORE_I32_A32 */
7576
    1641,
7577
    /* ATOMIC_STORE_I32_A32_S */
7578
    1645,
7579
    /* ATOMIC_STORE_I32_A64 */
7580
    1647,
7581
    /* ATOMIC_STORE_I32_A64_S */
7582
    1651,
7583
    /* ATOMIC_STORE_I64_A32 */
7584
    1653,
7585
    /* ATOMIC_STORE_I64_A32_S */
7586
    1657,
7587
    /* ATOMIC_STORE_I64_A64 */
7588
    1659,
7589
    /* ATOMIC_STORE_I64_A64_S */
7590
    1663,
7591
    /* AVGR_U_I16x8 */
7592
    1665,
7593
    /* AVGR_U_I16x8_S */
7594
    1668,
7595
    /* AVGR_U_I8x16 */
7596
    1668,
7597
    /* AVGR_U_I8x16_S */
7598
    1671,
7599
    /* BITMASK_I16x8 */
7600
    1671,
7601
    /* BITMASK_I16x8_S */
7602
    1673,
7603
    /* BITMASK_I32x4 */
7604
    1673,
7605
    /* BITMASK_I32x4_S */
7606
    1675,
7607
    /* BITMASK_I64x2 */
7608
    1675,
7609
    /* BITMASK_I64x2_S */
7610
    1677,
7611
    /* BITMASK_I8x16 */
7612
    1677,
7613
    /* BITMASK_I8x16_S */
7614
    1679,
7615
    /* BITSELECT */
7616
    1679,
7617
    /* BITSELECT_S */
7618
    1683,
7619
    /* BLOCK */
7620
    1683,
7621
    /* BLOCK_S */
7622
    1684,
7623
    /* BR */
7624
    1685,
7625
    /* BR_IF */
7626
    1686,
7627
    /* BR_IF_S */
7628
    1688,
7629
    /* BR_S */
7630
    1689,
7631
    /* BR_TABLE_I32 */
7632
    1690,
7633
    /* BR_TABLE_I32_S */
7634
    1691,
7635
    /* BR_TABLE_I64 */
7636
    1692,
7637
    /* BR_TABLE_I64_S */
7638
    1693,
7639
    /* BR_UNLESS */
7640
    1694,
7641
    /* BR_UNLESS_S */
7642
    1696,
7643
    /* CALL */
7644
    1697,
7645
    /* CALL_INDIRECT */
7646
    1698,
7647
    /* CALL_INDIRECT_S */
7648
    1700,
7649
    /* CALL_S */
7650
    1702,
7651
    /* CATCH */
7652
    1703,
7653
    /* CATCH_ALL */
7654
    1704,
7655
    /* CATCH_ALL_S */
7656
    1704,
7657
    /* CATCH_S */
7658
    1704,
7659
    /* CEIL_F32 */
7660
    1705,
7661
    /* CEIL_F32_S */
7662
    1707,
7663
    /* CEIL_F32x4 */
7664
    1707,
7665
    /* CEIL_F32x4_S */
7666
    1709,
7667
    /* CEIL_F64 */
7668
    1709,
7669
    /* CEIL_F64_S */
7670
    1711,
7671
    /* CEIL_F64x2 */
7672
    1711,
7673
    /* CEIL_F64x2_S */
7674
    1713,
7675
    /* CLZ_I32 */
7676
    1713,
7677
    /* CLZ_I32_S */
7678
    1715,
7679
    /* CLZ_I64 */
7680
    1715,
7681
    /* CLZ_I64_S */
7682
    1717,
7683
    /* CONST_F32 */
7684
    1717,
7685
    /* CONST_F32_S */
7686
    1719,
7687
    /* CONST_F64 */
7688
    1720,
7689
    /* CONST_F64_S */
7690
    1722,
7691
    /* CONST_I32 */
7692
    1723,
7693
    /* CONST_I32_S */
7694
    1725,
7695
    /* CONST_I64 */
7696
    1726,
7697
    /* CONST_I64_S */
7698
    1728,
7699
    /* CONST_V128_F32x4 */
7700
    1729,
7701
    /* CONST_V128_F32x4_S */
7702
    1734,
7703
    /* CONST_V128_F64x2 */
7704
    1738,
7705
    /* CONST_V128_F64x2_S */
7706
    1741,
7707
    /* CONST_V128_I16x8 */
7708
    1743,
7709
    /* CONST_V128_I16x8_S */
7710
    1752,
7711
    /* CONST_V128_I32x4 */
7712
    1760,
7713
    /* CONST_V128_I32x4_S */
7714
    1765,
7715
    /* CONST_V128_I64x2 */
7716
    1769,
7717
    /* CONST_V128_I64x2_S */
7718
    1772,
7719
    /* CONST_V128_I8x16 */
7720
    1774,
7721
    /* CONST_V128_I8x16_S */
7722
    1791,
7723
    /* COPYSIGN_F32 */
7724
    1807,
7725
    /* COPYSIGN_F32_S */
7726
    1810,
7727
    /* COPYSIGN_F64 */
7728
    1810,
7729
    /* COPYSIGN_F64_S */
7730
    1813,
7731
    /* COPY_EXTERNREF */
7732
    1813,
7733
    /* COPY_EXTERNREF_S */
7734
    1815,
7735
    /* COPY_F32 */
7736
    1815,
7737
    /* COPY_F32_S */
7738
    1817,
7739
    /* COPY_F64 */
7740
    1817,
7741
    /* COPY_F64_S */
7742
    1819,
7743
    /* COPY_FUNCREF */
7744
    1819,
7745
    /* COPY_FUNCREF_S */
7746
    1821,
7747
    /* COPY_I32 */
7748
    1821,
7749
    /* COPY_I32_S */
7750
    1823,
7751
    /* COPY_I64 */
7752
    1823,
7753
    /* COPY_I64_S */
7754
    1825,
7755
    /* COPY_V128 */
7756
    1825,
7757
    /* COPY_V128_S */
7758
    1827,
7759
    /* CTZ_I32 */
7760
    1827,
7761
    /* CTZ_I32_S */
7762
    1829,
7763
    /* CTZ_I64 */
7764
    1829,
7765
    /* CTZ_I64_S */
7766
    1831,
7767
    /* DEBUG_UNREACHABLE */
7768
    1831,
7769
    /* DEBUG_UNREACHABLE_S */
7770
    1831,
7771
    /* DELEGATE */
7772
    1831,
7773
    /* DELEGATE_S */
7774
    1832,
7775
    /* DIV_F32 */
7776
    1833,
7777
    /* DIV_F32_S */
7778
    1836,
7779
    /* DIV_F32x4 */
7780
    1836,
7781
    /* DIV_F32x4_S */
7782
    1839,
7783
    /* DIV_F64 */
7784
    1839,
7785
    /* DIV_F64_S */
7786
    1842,
7787
    /* DIV_F64x2 */
7788
    1842,
7789
    /* DIV_F64x2_S */
7790
    1845,
7791
    /* DIV_S_I32 */
7792
    1845,
7793
    /* DIV_S_I32_S */
7794
    1848,
7795
    /* DIV_S_I64 */
7796
    1848,
7797
    /* DIV_S_I64_S */
7798
    1851,
7799
    /* DIV_U_I32 */
7800
    1851,
7801
    /* DIV_U_I32_S */
7802
    1854,
7803
    /* DIV_U_I64 */
7804
    1854,
7805
    /* DIV_U_I64_S */
7806
    1857,
7807
    /* DOT */
7808
    1857,
7809
    /* DOT_S */
7810
    1860,
7811
    /* DROP_EXTERNREF */
7812
    1860,
7813
    /* DROP_EXTERNREF_S */
7814
    1861,
7815
    /* DROP_F32 */
7816
    1861,
7817
    /* DROP_F32_S */
7818
    1862,
7819
    /* DROP_F64 */
7820
    1862,
7821
    /* DROP_F64_S */
7822
    1863,
7823
    /* DROP_FUNCREF */
7824
    1863,
7825
    /* DROP_FUNCREF_S */
7826
    1864,
7827
    /* DROP_I32 */
7828
    1864,
7829
    /* DROP_I32_S */
7830
    1865,
7831
    /* DROP_I64 */
7832
    1865,
7833
    /* DROP_I64_S */
7834
    1866,
7835
    /* DROP_V128 */
7836
    1866,
7837
    /* DROP_V128_S */
7838
    1867,
7839
    /* ELSE */
7840
    1867,
7841
    /* ELSE_S */
7842
    1867,
7843
    /* END */
7844
    1867,
7845
    /* END_BLOCK */
7846
    1867,
7847
    /* END_BLOCK_S */
7848
    1867,
7849
    /* END_FUNCTION */
7850
    1867,
7851
    /* END_FUNCTION_S */
7852
    1867,
7853
    /* END_IF */
7854
    1867,
7855
    /* END_IF_S */
7856
    1867,
7857
    /* END_LOOP */
7858
    1867,
7859
    /* END_LOOP_S */
7860
    1867,
7861
    /* END_S */
7862
    1867,
7863
    /* END_TRY */
7864
    1867,
7865
    /* END_TRY_S */
7866
    1867,
7867
    /* EQZ_I32 */
7868
    1867,
7869
    /* EQZ_I32_S */
7870
    1869,
7871
    /* EQZ_I64 */
7872
    1869,
7873
    /* EQZ_I64_S */
7874
    1871,
7875
    /* EQ_F32 */
7876
    1871,
7877
    /* EQ_F32_S */
7878
    1874,
7879
    /* EQ_F32x4 */
7880
    1874,
7881
    /* EQ_F32x4_S */
7882
    1877,
7883
    /* EQ_F64 */
7884
    1877,
7885
    /* EQ_F64_S */
7886
    1880,
7887
    /* EQ_F64x2 */
7888
    1880,
7889
    /* EQ_F64x2_S */
7890
    1883,
7891
    /* EQ_I16x8 */
7892
    1883,
7893
    /* EQ_I16x8_S */
7894
    1886,
7895
    /* EQ_I32 */
7896
    1886,
7897
    /* EQ_I32_S */
7898
    1889,
7899
    /* EQ_I32x4 */
7900
    1889,
7901
    /* EQ_I32x4_S */
7902
    1892,
7903
    /* EQ_I64 */
7904
    1892,
7905
    /* EQ_I64_S */
7906
    1895,
7907
    /* EQ_I64x2 */
7908
    1895,
7909
    /* EQ_I64x2_S */
7910
    1898,
7911
    /* EQ_I8x16 */
7912
    1898,
7913
    /* EQ_I8x16_S */
7914
    1901,
7915
    /* EXTMUL_HIGH_S_I16x8 */
7916
    1901,
7917
    /* EXTMUL_HIGH_S_I16x8_S */
7918
    1904,
7919
    /* EXTMUL_HIGH_S_I32x4 */
7920
    1904,
7921
    /* EXTMUL_HIGH_S_I32x4_S */
7922
    1907,
7923
    /* EXTMUL_HIGH_S_I64x2 */
7924
    1907,
7925
    /* EXTMUL_HIGH_S_I64x2_S */
7926
    1910,
7927
    /* EXTMUL_HIGH_U_I16x8 */
7928
    1910,
7929
    /* EXTMUL_HIGH_U_I16x8_S */
7930
    1913,
7931
    /* EXTMUL_HIGH_U_I32x4 */
7932
    1913,
7933
    /* EXTMUL_HIGH_U_I32x4_S */
7934
    1916,
7935
    /* EXTMUL_HIGH_U_I64x2 */
7936
    1916,
7937
    /* EXTMUL_HIGH_U_I64x2_S */
7938
    1919,
7939
    /* EXTMUL_LOW_S_I16x8 */
7940
    1919,
7941
    /* EXTMUL_LOW_S_I16x8_S */
7942
    1922,
7943
    /* EXTMUL_LOW_S_I32x4 */
7944
    1922,
7945
    /* EXTMUL_LOW_S_I32x4_S */
7946
    1925,
7947
    /* EXTMUL_LOW_S_I64x2 */
7948
    1925,
7949
    /* EXTMUL_LOW_S_I64x2_S */
7950
    1928,
7951
    /* EXTMUL_LOW_U_I16x8 */
7952
    1928,
7953
    /* EXTMUL_LOW_U_I16x8_S */
7954
    1931,
7955
    /* EXTMUL_LOW_U_I32x4 */
7956
    1931,
7957
    /* EXTMUL_LOW_U_I32x4_S */
7958
    1934,
7959
    /* EXTMUL_LOW_U_I64x2 */
7960
    1934,
7961
    /* EXTMUL_LOW_U_I64x2_S */
7962
    1937,
7963
    /* EXTRACT_LANE_F32x4 */
7964
    1937,
7965
    /* EXTRACT_LANE_F32x4_S */
7966
    1940,
7967
    /* EXTRACT_LANE_F64x2 */
7968
    1941,
7969
    /* EXTRACT_LANE_F64x2_S */
7970
    1944,
7971
    /* EXTRACT_LANE_I16x8_s */
7972
    1945,
7973
    /* EXTRACT_LANE_I16x8_s_S */
7974
    1948,
7975
    /* EXTRACT_LANE_I16x8_u */
7976
    1949,
7977
    /* EXTRACT_LANE_I16x8_u_S */
7978
    1952,
7979
    /* EXTRACT_LANE_I32x4 */
7980
    1953,
7981
    /* EXTRACT_LANE_I32x4_S */
7982
    1956,
7983
    /* EXTRACT_LANE_I64x2 */
7984
    1957,
7985
    /* EXTRACT_LANE_I64x2_S */
7986
    1960,
7987
    /* EXTRACT_LANE_I8x16_s */
7988
    1961,
7989
    /* EXTRACT_LANE_I8x16_s_S */
7990
    1964,
7991
    /* EXTRACT_LANE_I8x16_u */
7992
    1965,
7993
    /* EXTRACT_LANE_I8x16_u_S */
7994
    1968,
7995
    /* F32_CONVERT_S_I32 */
7996
    1969,
7997
    /* F32_CONVERT_S_I32_S */
7998
    1971,
7999
    /* F32_CONVERT_S_I64 */
8000
    1971,
8001
    /* F32_CONVERT_S_I64_S */
8002
    1973,
8003
    /* F32_CONVERT_U_I32 */
8004
    1973,
8005
    /* F32_CONVERT_U_I32_S */
8006
    1975,
8007
    /* F32_CONVERT_U_I64 */
8008
    1975,
8009
    /* F32_CONVERT_U_I64_S */
8010
    1977,
8011
    /* F32_DEMOTE_F64 */
8012
    1977,
8013
    /* F32_DEMOTE_F64_S */
8014
    1979,
8015
    /* F32_REINTERPRET_I32 */
8016
    1979,
8017
    /* F32_REINTERPRET_I32_S */
8018
    1981,
8019
    /* F64_CONVERT_S_I32 */
8020
    1981,
8021
    /* F64_CONVERT_S_I32_S */
8022
    1983,
8023
    /* F64_CONVERT_S_I64 */
8024
    1983,
8025
    /* F64_CONVERT_S_I64_S */
8026
    1985,
8027
    /* F64_CONVERT_U_I32 */
8028
    1985,
8029
    /* F64_CONVERT_U_I32_S */
8030
    1987,
8031
    /* F64_CONVERT_U_I64 */
8032
    1987,
8033
    /* F64_CONVERT_U_I64_S */
8034
    1989,
8035
    /* F64_PROMOTE_F32 */
8036
    1989,
8037
    /* F64_PROMOTE_F32_S */
8038
    1991,
8039
    /* F64_REINTERPRET_I64 */
8040
    1991,
8041
    /* F64_REINTERPRET_I64_S */
8042
    1993,
8043
    /* FALLTHROUGH_RETURN */
8044
    1993,
8045
    /* FALLTHROUGH_RETURN_S */
8046
    1993,
8047
    /* FLOOR_F32 */
8048
    1993,
8049
    /* FLOOR_F32_S */
8050
    1995,
8051
    /* FLOOR_F32x4 */
8052
    1995,
8053
    /* FLOOR_F32x4_S */
8054
    1997,
8055
    /* FLOOR_F64 */
8056
    1997,
8057
    /* FLOOR_F64_S */
8058
    1999,
8059
    /* FLOOR_F64x2 */
8060
    1999,
8061
    /* FLOOR_F64x2_S */
8062
    2001,
8063
    /* FP_TO_SINT_I32_F32 */
8064
    2001,
8065
    /* FP_TO_SINT_I32_F32_S */
8066
    2003,
8067
    /* FP_TO_SINT_I32_F64 */
8068
    2003,
8069
    /* FP_TO_SINT_I32_F64_S */
8070
    2005,
8071
    /* FP_TO_SINT_I64_F32 */
8072
    2005,
8073
    /* FP_TO_SINT_I64_F32_S */
8074
    2007,
8075
    /* FP_TO_SINT_I64_F64 */
8076
    2007,
8077
    /* FP_TO_SINT_I64_F64_S */
8078
    2009,
8079
    /* FP_TO_UINT_I32_F32 */
8080
    2009,
8081
    /* FP_TO_UINT_I32_F32_S */
8082
    2011,
8083
    /* FP_TO_UINT_I32_F64 */
8084
    2011,
8085
    /* FP_TO_UINT_I32_F64_S */
8086
    2013,
8087
    /* FP_TO_UINT_I64_F32 */
8088
    2013,
8089
    /* FP_TO_UINT_I64_F32_S */
8090
    2015,
8091
    /* FP_TO_UINT_I64_F64 */
8092
    2015,
8093
    /* FP_TO_UINT_I64_F64_S */
8094
    2017,
8095
    /* GE_F32 */
8096
    2017,
8097
    /* GE_F32_S */
8098
    2020,
8099
    /* GE_F32x4 */
8100
    2020,
8101
    /* GE_F32x4_S */
8102
    2023,
8103
    /* GE_F64 */
8104
    2023,
8105
    /* GE_F64_S */
8106
    2026,
8107
    /* GE_F64x2 */
8108
    2026,
8109
    /* GE_F64x2_S */
8110
    2029,
8111
    /* GE_S_I16x8 */
8112
    2029,
8113
    /* GE_S_I16x8_S */
8114
    2032,
8115
    /* GE_S_I32 */
8116
    2032,
8117
    /* GE_S_I32_S */
8118
    2035,
8119
    /* GE_S_I32x4 */
8120
    2035,
8121
    /* GE_S_I32x4_S */
8122
    2038,
8123
    /* GE_S_I64 */
8124
    2038,
8125
    /* GE_S_I64_S */
8126
    2041,
8127
    /* GE_S_I64x2 */
8128
    2041,
8129
    /* GE_S_I64x2_S */
8130
    2044,
8131
    /* GE_S_I8x16 */
8132
    2044,
8133
    /* GE_S_I8x16_S */
8134
    2047,
8135
    /* GE_U_I16x8 */
8136
    2047,
8137
    /* GE_U_I16x8_S */
8138
    2050,
8139
    /* GE_U_I32 */
8140
    2050,
8141
    /* GE_U_I32_S */
8142
    2053,
8143
    /* GE_U_I32x4 */
8144
    2053,
8145
    /* GE_U_I32x4_S */
8146
    2056,
8147
    /* GE_U_I64 */
8148
    2056,
8149
    /* GE_U_I64_S */
8150
    2059,
8151
    /* GE_U_I8x16 */
8152
    2059,
8153
    /* GE_U_I8x16_S */
8154
    2062,
8155
    /* GLOBAL_GET_EXTERNREF */
8156
    2062,
8157
    /* GLOBAL_GET_EXTERNREF_S */
8158
    2064,
8159
    /* GLOBAL_GET_F32 */
8160
    2065,
8161
    /* GLOBAL_GET_F32_S */
8162
    2067,
8163
    /* GLOBAL_GET_F64 */
8164
    2068,
8165
    /* GLOBAL_GET_F64_S */
8166
    2070,
8167
    /* GLOBAL_GET_FUNCREF */
8168
    2071,
8169
    /* GLOBAL_GET_FUNCREF_S */
8170
    2073,
8171
    /* GLOBAL_GET_I32 */
8172
    2074,
8173
    /* GLOBAL_GET_I32_S */
8174
    2076,
8175
    /* GLOBAL_GET_I64 */
8176
    2077,
8177
    /* GLOBAL_GET_I64_S */
8178
    2079,
8179
    /* GLOBAL_GET_V128 */
8180
    2080,
8181
    /* GLOBAL_GET_V128_S */
8182
    2082,
8183
    /* GLOBAL_SET_EXTERNREF */
8184
    2083,
8185
    /* GLOBAL_SET_EXTERNREF_S */
8186
    2085,
8187
    /* GLOBAL_SET_F32 */
8188
    2086,
8189
    /* GLOBAL_SET_F32_S */
8190
    2088,
8191
    /* GLOBAL_SET_F64 */
8192
    2089,
8193
    /* GLOBAL_SET_F64_S */
8194
    2091,
8195
    /* GLOBAL_SET_FUNCREF */
8196
    2092,
8197
    /* GLOBAL_SET_FUNCREF_S */
8198
    2094,
8199
    /* GLOBAL_SET_I32 */
8200
    2095,
8201
    /* GLOBAL_SET_I32_S */
8202
    2097,
8203
    /* GLOBAL_SET_I64 */
8204
    2098,
8205
    /* GLOBAL_SET_I64_S */
8206
    2100,
8207
    /* GLOBAL_SET_V128 */
8208
    2101,
8209
    /* GLOBAL_SET_V128_S */
8210
    2103,
8211
    /* GT_F32 */
8212
    2104,
8213
    /* GT_F32_S */
8214
    2107,
8215
    /* GT_F32x4 */
8216
    2107,
8217
    /* GT_F32x4_S */
8218
    2110,
8219
    /* GT_F64 */
8220
    2110,
8221
    /* GT_F64_S */
8222
    2113,
8223
    /* GT_F64x2 */
8224
    2113,
8225
    /* GT_F64x2_S */
8226
    2116,
8227
    /* GT_S_I16x8 */
8228
    2116,
8229
    /* GT_S_I16x8_S */
8230
    2119,
8231
    /* GT_S_I32 */
8232
    2119,
8233
    /* GT_S_I32_S */
8234
    2122,
8235
    /* GT_S_I32x4 */
8236
    2122,
8237
    /* GT_S_I32x4_S */
8238
    2125,
8239
    /* GT_S_I64 */
8240
    2125,
8241
    /* GT_S_I64_S */
8242
    2128,
8243
    /* GT_S_I64x2 */
8244
    2128,
8245
    /* GT_S_I64x2_S */
8246
    2131,
8247
    /* GT_S_I8x16 */
8248
    2131,
8249
    /* GT_S_I8x16_S */
8250
    2134,
8251
    /* GT_U_I16x8 */
8252
    2134,
8253
    /* GT_U_I16x8_S */
8254
    2137,
8255
    /* GT_U_I32 */
8256
    2137,
8257
    /* GT_U_I32_S */
8258
    2140,
8259
    /* GT_U_I32x4 */
8260
    2140,
8261
    /* GT_U_I32x4_S */
8262
    2143,
8263
    /* GT_U_I64 */
8264
    2143,
8265
    /* GT_U_I64_S */
8266
    2146,
8267
    /* GT_U_I8x16 */
8268
    2146,
8269
    /* GT_U_I8x16_S */
8270
    2149,
8271
    /* I32_EXTEND16_S_I32 */
8272
    2149,
8273
    /* I32_EXTEND16_S_I32_S */
8274
    2151,
8275
    /* I32_EXTEND8_S_I32 */
8276
    2151,
8277
    /* I32_EXTEND8_S_I32_S */
8278
    2153,
8279
    /* I32_REINTERPRET_F32 */
8280
    2153,
8281
    /* I32_REINTERPRET_F32_S */
8282
    2155,
8283
    /* I32_TRUNC_S_F32 */
8284
    2155,
8285
    /* I32_TRUNC_S_F32_S */
8286
    2157,
8287
    /* I32_TRUNC_S_F64 */
8288
    2157,
8289
    /* I32_TRUNC_S_F64_S */
8290
    2159,
8291
    /* I32_TRUNC_S_SAT_F32 */
8292
    2159,
8293
    /* I32_TRUNC_S_SAT_F32_S */
8294
    2161,
8295
    /* I32_TRUNC_S_SAT_F64 */
8296
    2161,
8297
    /* I32_TRUNC_S_SAT_F64_S */
8298
    2163,
8299
    /* I32_TRUNC_U_F32 */
8300
    2163,
8301
    /* I32_TRUNC_U_F32_S */
8302
    2165,
8303
    /* I32_TRUNC_U_F64 */
8304
    2165,
8305
    /* I32_TRUNC_U_F64_S */
8306
    2167,
8307
    /* I32_TRUNC_U_SAT_F32 */
8308
    2167,
8309
    /* I32_TRUNC_U_SAT_F32_S */
8310
    2169,
8311
    /* I32_TRUNC_U_SAT_F64 */
8312
    2169,
8313
    /* I32_TRUNC_U_SAT_F64_S */
8314
    2171,
8315
    /* I32_WRAP_I64 */
8316
    2171,
8317
    /* I32_WRAP_I64_S */
8318
    2173,
8319
    /* I64_EXTEND16_S_I64 */
8320
    2173,
8321
    /* I64_EXTEND16_S_I64_S */
8322
    2175,
8323
    /* I64_EXTEND32_S_I64 */
8324
    2175,
8325
    /* I64_EXTEND32_S_I64_S */
8326
    2177,
8327
    /* I64_EXTEND8_S_I64 */
8328
    2177,
8329
    /* I64_EXTEND8_S_I64_S */
8330
    2179,
8331
    /* I64_EXTEND_S_I32 */
8332
    2179,
8333
    /* I64_EXTEND_S_I32_S */
8334
    2181,
8335
    /* I64_EXTEND_U_I32 */
8336
    2181,
8337
    /* I64_EXTEND_U_I32_S */
8338
    2183,
8339
    /* I64_REINTERPRET_F64 */
8340
    2183,
8341
    /* I64_REINTERPRET_F64_S */
8342
    2185,
8343
    /* I64_TRUNC_S_F32 */
8344
    2185,
8345
    /* I64_TRUNC_S_F32_S */
8346
    2187,
8347
    /* I64_TRUNC_S_F64 */
8348
    2187,
8349
    /* I64_TRUNC_S_F64_S */
8350
    2189,
8351
    /* I64_TRUNC_S_SAT_F32 */
8352
    2189,
8353
    /* I64_TRUNC_S_SAT_F32_S */
8354
    2191,
8355
    /* I64_TRUNC_S_SAT_F64 */
8356
    2191,
8357
    /* I64_TRUNC_S_SAT_F64_S */
8358
    2193,
8359
    /* I64_TRUNC_U_F32 */
8360
    2193,
8361
    /* I64_TRUNC_U_F32_S */
8362
    2195,
8363
    /* I64_TRUNC_U_F64 */
8364
    2195,
8365
    /* I64_TRUNC_U_F64_S */
8366
    2197,
8367
    /* I64_TRUNC_U_SAT_F32 */
8368
    2197,
8369
    /* I64_TRUNC_U_SAT_F32_S */
8370
    2199,
8371
    /* I64_TRUNC_U_SAT_F64 */
8372
    2199,
8373
    /* I64_TRUNC_U_SAT_F64_S */
8374
    2201,
8375
    /* IF */
8376
    2201,
8377
    /* IF_S */
8378
    2203,
8379
    /* LANESELECT_I16x8 */
8380
    2204,
8381
    /* LANESELECT_I16x8_S */
8382
    2208,
8383
    /* LANESELECT_I32x4 */
8384
    2208,
8385
    /* LANESELECT_I32x4_S */
8386
    2212,
8387
    /* LANESELECT_I64x2 */
8388
    2212,
8389
    /* LANESELECT_I64x2_S */
8390
    2216,
8391
    /* LANESELECT_I8x16 */
8392
    2216,
8393
    /* LANESELECT_I8x16_S */
8394
    2220,
8395
    /* LE_F32 */
8396
    2220,
8397
    /* LE_F32_S */
8398
    2223,
8399
    /* LE_F32x4 */
8400
    2223,
8401
    /* LE_F32x4_S */
8402
    2226,
8403
    /* LE_F64 */
8404
    2226,
8405
    /* LE_F64_S */
8406
    2229,
8407
    /* LE_F64x2 */
8408
    2229,
8409
    /* LE_F64x2_S */
8410
    2232,
8411
    /* LE_S_I16x8 */
8412
    2232,
8413
    /* LE_S_I16x8_S */
8414
    2235,
8415
    /* LE_S_I32 */
8416
    2235,
8417
    /* LE_S_I32_S */
8418
    2238,
8419
    /* LE_S_I32x4 */
8420
    2238,
8421
    /* LE_S_I32x4_S */
8422
    2241,
8423
    /* LE_S_I64 */
8424
    2241,
8425
    /* LE_S_I64_S */
8426
    2244,
8427
    /* LE_S_I64x2 */
8428
    2244,
8429
    /* LE_S_I64x2_S */
8430
    2247,
8431
    /* LE_S_I8x16 */
8432
    2247,
8433
    /* LE_S_I8x16_S */
8434
    2250,
8435
    /* LE_U_I16x8 */
8436
    2250,
8437
    /* LE_U_I16x8_S */
8438
    2253,
8439
    /* LE_U_I32 */
8440
    2253,
8441
    /* LE_U_I32_S */
8442
    2256,
8443
    /* LE_U_I32x4 */
8444
    2256,
8445
    /* LE_U_I32x4_S */
8446
    2259,
8447
    /* LE_U_I64 */
8448
    2259,
8449
    /* LE_U_I64_S */
8450
    2262,
8451
    /* LE_U_I8x16 */
8452
    2262,
8453
    /* LE_U_I8x16_S */
8454
    2265,
8455
    /* LOAD16_SPLAT_A32 */
8456
    2265,
8457
    /* LOAD16_SPLAT_A32_S */
8458
    2269,
8459
    /* LOAD16_SPLAT_A64 */
8460
    2271,
8461
    /* LOAD16_SPLAT_A64_S */
8462
    2275,
8463
    /* LOAD16_S_I32_A32 */
8464
    2277,
8465
    /* LOAD16_S_I32_A32_S */
8466
    2281,
8467
    /* LOAD16_S_I32_A64 */
8468
    2283,
8469
    /* LOAD16_S_I32_A64_S */
8470
    2287,
8471
    /* LOAD16_S_I64_A32 */
8472
    2289,
8473
    /* LOAD16_S_I64_A32_S */
8474
    2293,
8475
    /* LOAD16_S_I64_A64 */
8476
    2295,
8477
    /* LOAD16_S_I64_A64_S */
8478
    2299,
8479
    /* LOAD16_U_I32_A32 */
8480
    2301,
8481
    /* LOAD16_U_I32_A32_S */
8482
    2305,
8483
    /* LOAD16_U_I32_A64 */
8484
    2307,
8485
    /* LOAD16_U_I32_A64_S */
8486
    2311,
8487
    /* LOAD16_U_I64_A32 */
8488
    2313,
8489
    /* LOAD16_U_I64_A32_S */
8490
    2317,
8491
    /* LOAD16_U_I64_A64 */
8492
    2319,
8493
    /* LOAD16_U_I64_A64_S */
8494
    2323,
8495
    /* LOAD32_SPLAT_A32 */
8496
    2325,
8497
    /* LOAD32_SPLAT_A32_S */
8498
    2329,
8499
    /* LOAD32_SPLAT_A64 */
8500
    2331,
8501
    /* LOAD32_SPLAT_A64_S */
8502
    2335,
8503
    /* LOAD32_S_I64_A32 */
8504
    2337,
8505
    /* LOAD32_S_I64_A32_S */
8506
    2341,
8507
    /* LOAD32_S_I64_A64 */
8508
    2343,
8509
    /* LOAD32_S_I64_A64_S */
8510
    2347,
8511
    /* LOAD32_U_I64_A32 */
8512
    2349,
8513
    /* LOAD32_U_I64_A32_S */
8514
    2353,
8515
    /* LOAD32_U_I64_A64 */
8516
    2355,
8517
    /* LOAD32_U_I64_A64_S */
8518
    2359,
8519
    /* LOAD64_SPLAT_A32 */
8520
    2361,
8521
    /* LOAD64_SPLAT_A32_S */
8522
    2365,
8523
    /* LOAD64_SPLAT_A64 */
8524
    2367,
8525
    /* LOAD64_SPLAT_A64_S */
8526
    2371,
8527
    /* LOAD8_SPLAT_A32 */
8528
    2373,
8529
    /* LOAD8_SPLAT_A32_S */
8530
    2377,
8531
    /* LOAD8_SPLAT_A64 */
8532
    2379,
8533
    /* LOAD8_SPLAT_A64_S */
8534
    2383,
8535
    /* LOAD8_S_I32_A32 */
8536
    2385,
8537
    /* LOAD8_S_I32_A32_S */
8538
    2389,
8539
    /* LOAD8_S_I32_A64 */
8540
    2391,
8541
    /* LOAD8_S_I32_A64_S */
8542
    2395,
8543
    /* LOAD8_S_I64_A32 */
8544
    2397,
8545
    /* LOAD8_S_I64_A32_S */
8546
    2401,
8547
    /* LOAD8_S_I64_A64 */
8548
    2403,
8549
    /* LOAD8_S_I64_A64_S */
8550
    2407,
8551
    /* LOAD8_U_I32_A32 */
8552
    2409,
8553
    /* LOAD8_U_I32_A32_S */
8554
    2413,
8555
    /* LOAD8_U_I32_A64 */
8556
    2415,
8557
    /* LOAD8_U_I32_A64_S */
8558
    2419,
8559
    /* LOAD8_U_I64_A32 */
8560
    2421,
8561
    /* LOAD8_U_I64_A32_S */
8562
    2425,
8563
    /* LOAD8_U_I64_A64 */
8564
    2427,
8565
    /* LOAD8_U_I64_A64_S */
8566
    2431,
8567
    /* LOAD_EXTEND_S_I16x8_A32 */
8568
    2433,
8569
    /* LOAD_EXTEND_S_I16x8_A32_S */
8570
    2437,
8571
    /* LOAD_EXTEND_S_I16x8_A64 */
8572
    2439,
8573
    /* LOAD_EXTEND_S_I16x8_A64_S */
8574
    2443,
8575
    /* LOAD_EXTEND_S_I32x4_A32 */
8576
    2445,
8577
    /* LOAD_EXTEND_S_I32x4_A32_S */
8578
    2449,
8579
    /* LOAD_EXTEND_S_I32x4_A64 */
8580
    2451,
8581
    /* LOAD_EXTEND_S_I32x4_A64_S */
8582
    2455,
8583
    /* LOAD_EXTEND_S_I64x2_A32 */
8584
    2457,
8585
    /* LOAD_EXTEND_S_I64x2_A32_S */
8586
    2461,
8587
    /* LOAD_EXTEND_S_I64x2_A64 */
8588
    2463,
8589
    /* LOAD_EXTEND_S_I64x2_A64_S */
8590
    2467,
8591
    /* LOAD_EXTEND_U_I16x8_A32 */
8592
    2469,
8593
    /* LOAD_EXTEND_U_I16x8_A32_S */
8594
    2473,
8595
    /* LOAD_EXTEND_U_I16x8_A64 */
8596
    2475,
8597
    /* LOAD_EXTEND_U_I16x8_A64_S */
8598
    2479,
8599
    /* LOAD_EXTEND_U_I32x4_A32 */
8600
    2481,
8601
    /* LOAD_EXTEND_U_I32x4_A32_S */
8602
    2485,
8603
    /* LOAD_EXTEND_U_I32x4_A64 */
8604
    2487,
8605
    /* LOAD_EXTEND_U_I32x4_A64_S */
8606
    2491,
8607
    /* LOAD_EXTEND_U_I64x2_A32 */
8608
    2493,
8609
    /* LOAD_EXTEND_U_I64x2_A32_S */
8610
    2497,
8611
    /* LOAD_EXTEND_U_I64x2_A64 */
8612
    2499,
8613
    /* LOAD_EXTEND_U_I64x2_A64_S */
8614
    2503,
8615
    /* LOAD_F32_A32 */
8616
    2505,
8617
    /* LOAD_F32_A32_S */
8618
    2509,
8619
    /* LOAD_F32_A64 */
8620
    2511,
8621
    /* LOAD_F32_A64_S */
8622
    2515,
8623
    /* LOAD_F64_A32 */
8624
    2517,
8625
    /* LOAD_F64_A32_S */
8626
    2521,
8627
    /* LOAD_F64_A64 */
8628
    2523,
8629
    /* LOAD_F64_A64_S */
8630
    2527,
8631
    /* LOAD_I32_A32 */
8632
    2529,
8633
    /* LOAD_I32_A32_S */
8634
    2533,
8635
    /* LOAD_I32_A64 */
8636
    2535,
8637
    /* LOAD_I32_A64_S */
8638
    2539,
8639
    /* LOAD_I64_A32 */
8640
    2541,
8641
    /* LOAD_I64_A32_S */
8642
    2545,
8643
    /* LOAD_I64_A64 */
8644
    2547,
8645
    /* LOAD_I64_A64_S */
8646
    2551,
8647
    /* LOAD_LANE_I16x8_A32 */
8648
    2553,
8649
    /* LOAD_LANE_I16x8_A32_S */
8650
    2559,
8651
    /* LOAD_LANE_I16x8_A64 */
8652
    2562,
8653
    /* LOAD_LANE_I16x8_A64_S */
8654
    2568,
8655
    /* LOAD_LANE_I32x4_A32 */
8656
    2571,
8657
    /* LOAD_LANE_I32x4_A32_S */
8658
    2577,
8659
    /* LOAD_LANE_I32x4_A64 */
8660
    2580,
8661
    /* LOAD_LANE_I32x4_A64_S */
8662
    2586,
8663
    /* LOAD_LANE_I64x2_A32 */
8664
    2589,
8665
    /* LOAD_LANE_I64x2_A32_S */
8666
    2595,
8667
    /* LOAD_LANE_I64x2_A64 */
8668
    2598,
8669
    /* LOAD_LANE_I64x2_A64_S */
8670
    2604,
8671
    /* LOAD_LANE_I8x16_A32 */
8672
    2607,
8673
    /* LOAD_LANE_I8x16_A32_S */
8674
    2613,
8675
    /* LOAD_LANE_I8x16_A64 */
8676
    2616,
8677
    /* LOAD_LANE_I8x16_A64_S */
8678
    2622,
8679
    /* LOAD_V128_A32 */
8680
    2625,
8681
    /* LOAD_V128_A32_S */
8682
    2629,
8683
    /* LOAD_V128_A64 */
8684
    2631,
8685
    /* LOAD_V128_A64_S */
8686
    2635,
8687
    /* LOAD_ZERO_I32x4_A32 */
8688
    2637,
8689
    /* LOAD_ZERO_I32x4_A32_S */
8690
    2641,
8691
    /* LOAD_ZERO_I32x4_A64 */
8692
    2643,
8693
    /* LOAD_ZERO_I32x4_A64_S */
8694
    2647,
8695
    /* LOAD_ZERO_I64x2_A32 */
8696
    2649,
8697
    /* LOAD_ZERO_I64x2_A32_S */
8698
    2653,
8699
    /* LOAD_ZERO_I64x2_A64 */
8700
    2655,
8701
    /* LOAD_ZERO_I64x2_A64_S */
8702
    2659,
8703
    /* LOCAL_GET_EXTERNREF */
8704
    2661,
8705
    /* LOCAL_GET_EXTERNREF_S */
8706
    2663,
8707
    /* LOCAL_GET_F32 */
8708
    2664,
8709
    /* LOCAL_GET_F32_S */
8710
    2666,
8711
    /* LOCAL_GET_F64 */
8712
    2667,
8713
    /* LOCAL_GET_F64_S */
8714
    2669,
8715
    /* LOCAL_GET_FUNCREF */
8716
    2670,
8717
    /* LOCAL_GET_FUNCREF_S */
8718
    2672,
8719
    /* LOCAL_GET_I32 */
8720
    2673,
8721
    /* LOCAL_GET_I32_S */
8722
    2675,
8723
    /* LOCAL_GET_I64 */
8724
    2676,
8725
    /* LOCAL_GET_I64_S */
8726
    2678,
8727
    /* LOCAL_GET_V128 */
8728
    2679,
8729
    /* LOCAL_GET_V128_S */
8730
    2681,
8731
    /* LOCAL_SET_EXTERNREF */
8732
    2682,
8733
    /* LOCAL_SET_EXTERNREF_S */
8734
    2684,
8735
    /* LOCAL_SET_F32 */
8736
    2685,
8737
    /* LOCAL_SET_F32_S */
8738
    2687,
8739
    /* LOCAL_SET_F64 */
8740
    2688,
8741
    /* LOCAL_SET_F64_S */
8742
    2690,
8743
    /* LOCAL_SET_FUNCREF */
8744
    2691,
8745
    /* LOCAL_SET_FUNCREF_S */
8746
    2693,
8747
    /* LOCAL_SET_I32 */
8748
    2694,
8749
    /* LOCAL_SET_I32_S */
8750
    2696,
8751
    /* LOCAL_SET_I64 */
8752
    2697,
8753
    /* LOCAL_SET_I64_S */
8754
    2699,
8755
    /* LOCAL_SET_V128 */
8756
    2700,
8757
    /* LOCAL_SET_V128_S */
8758
    2702,
8759
    /* LOCAL_TEE_EXTERNREF */
8760
    2703,
8761
    /* LOCAL_TEE_EXTERNREF_S */
8762
    2706,
8763
    /* LOCAL_TEE_F32 */
8764
    2707,
8765
    /* LOCAL_TEE_F32_S */
8766
    2710,
8767
    /* LOCAL_TEE_F64 */
8768
    2711,
8769
    /* LOCAL_TEE_F64_S */
8770
    2714,
8771
    /* LOCAL_TEE_FUNCREF */
8772
    2715,
8773
    /* LOCAL_TEE_FUNCREF_S */
8774
    2718,
8775
    /* LOCAL_TEE_I32 */
8776
    2719,
8777
    /* LOCAL_TEE_I32_S */
8778
    2722,
8779
    /* LOCAL_TEE_I64 */
8780
    2723,
8781
    /* LOCAL_TEE_I64_S */
8782
    2726,
8783
    /* LOCAL_TEE_V128 */
8784
    2727,
8785
    /* LOCAL_TEE_V128_S */
8786
    2730,
8787
    /* LOOP */
8788
    2731,
8789
    /* LOOP_S */
8790
    2732,
8791
    /* LT_F32 */
8792
    2733,
8793
    /* LT_F32_S */
8794
    2736,
8795
    /* LT_F32x4 */
8796
    2736,
8797
    /* LT_F32x4_S */
8798
    2739,
8799
    /* LT_F64 */
8800
    2739,
8801
    /* LT_F64_S */
8802
    2742,
8803
    /* LT_F64x2 */
8804
    2742,
8805
    /* LT_F64x2_S */
8806
    2745,
8807
    /* LT_S_I16x8 */
8808
    2745,
8809
    /* LT_S_I16x8_S */
8810
    2748,
8811
    /* LT_S_I32 */
8812
    2748,
8813
    /* LT_S_I32_S */
8814
    2751,
8815
    /* LT_S_I32x4 */
8816
    2751,
8817
    /* LT_S_I32x4_S */
8818
    2754,
8819
    /* LT_S_I64 */
8820
    2754,
8821
    /* LT_S_I64_S */
8822
    2757,
8823
    /* LT_S_I64x2 */
8824
    2757,
8825
    /* LT_S_I64x2_S */
8826
    2760,
8827
    /* LT_S_I8x16 */
8828
    2760,
8829
    /* LT_S_I8x16_S */
8830
    2763,
8831
    /* LT_U_I16x8 */
8832
    2763,
8833
    /* LT_U_I16x8_S */
8834
    2766,
8835
    /* LT_U_I32 */
8836
    2766,
8837
    /* LT_U_I32_S */
8838
    2769,
8839
    /* LT_U_I32x4 */
8840
    2769,
8841
    /* LT_U_I32x4_S */
8842
    2772,
8843
    /* LT_U_I64 */
8844
    2772,
8845
    /* LT_U_I64_S */
8846
    2775,
8847
    /* LT_U_I8x16 */
8848
    2775,
8849
    /* LT_U_I8x16_S */
8850
    2778,
8851
    /* MADD_F32x4 */
8852
    2778,
8853
    /* MADD_F32x4_S */
8854
    2782,
8855
    /* MADD_F64x2 */
8856
    2782,
8857
    /* MADD_F64x2_S */
8858
    2786,
8859
    /* MAX_F32 */
8860
    2786,
8861
    /* MAX_F32_S */
8862
    2789,
8863
    /* MAX_F32x4 */
8864
    2789,
8865
    /* MAX_F32x4_S */
8866
    2792,
8867
    /* MAX_F64 */
8868
    2792,
8869
    /* MAX_F64_S */
8870
    2795,
8871
    /* MAX_F64x2 */
8872
    2795,
8873
    /* MAX_F64x2_S */
8874
    2798,
8875
    /* MAX_S_I16x8 */
8876
    2798,
8877
    /* MAX_S_I16x8_S */
8878
    2801,
8879
    /* MAX_S_I32x4 */
8880
    2801,
8881
    /* MAX_S_I32x4_S */
8882
    2804,
8883
    /* MAX_S_I8x16 */
8884
    2804,
8885
    /* MAX_S_I8x16_S */
8886
    2807,
8887
    /* MAX_U_I16x8 */
8888
    2807,
8889
    /* MAX_U_I16x8_S */
8890
    2810,
8891
    /* MAX_U_I32x4 */
8892
    2810,
8893
    /* MAX_U_I32x4_S */
8894
    2813,
8895
    /* MAX_U_I8x16 */
8896
    2813,
8897
    /* MAX_U_I8x16_S */
8898
    2816,
8899
    /* MEMORY_ATOMIC_NOTIFY_A32 */
8900
    2816,
8901
    /* MEMORY_ATOMIC_NOTIFY_A32_S */
8902
    2821,
8903
    /* MEMORY_ATOMIC_NOTIFY_A64 */
8904
    2823,
8905
    /* MEMORY_ATOMIC_NOTIFY_A64_S */
8906
    2828,
8907
    /* MEMORY_ATOMIC_WAIT32_A32 */
8908
    2830,
8909
    /* MEMORY_ATOMIC_WAIT32_A32_S */
8910
    2836,
8911
    /* MEMORY_ATOMIC_WAIT32_A64 */
8912
    2838,
8913
    /* MEMORY_ATOMIC_WAIT32_A64_S */
8914
    2844,
8915
    /* MEMORY_ATOMIC_WAIT64_A32 */
8916
    2846,
8917
    /* MEMORY_ATOMIC_WAIT64_A32_S */
8918
    2852,
8919
    /* MEMORY_ATOMIC_WAIT64_A64 */
8920
    2854,
8921
    /* MEMORY_ATOMIC_WAIT64_A64_S */
8922
    2860,
8923
    /* MIN_F32 */
8924
    2862,
8925
    /* MIN_F32_S */
8926
    2865,
8927
    /* MIN_F32x4 */
8928
    2865,
8929
    /* MIN_F32x4_S */
8930
    2868,
8931
    /* MIN_F64 */
8932
    2868,
8933
    /* MIN_F64_S */
8934
    2871,
8935
    /* MIN_F64x2 */
8936
    2871,
8937
    /* MIN_F64x2_S */
8938
    2874,
8939
    /* MIN_S_I16x8 */
8940
    2874,
8941
    /* MIN_S_I16x8_S */
8942
    2877,
8943
    /* MIN_S_I32x4 */
8944
    2877,
8945
    /* MIN_S_I32x4_S */
8946
    2880,
8947
    /* MIN_S_I8x16 */
8948
    2880,
8949
    /* MIN_S_I8x16_S */
8950
    2883,
8951
    /* MIN_U_I16x8 */
8952
    2883,
8953
    /* MIN_U_I16x8_S */
8954
    2886,
8955
    /* MIN_U_I32x4 */
8956
    2886,
8957
    /* MIN_U_I32x4_S */
8958
    2889,
8959
    /* MIN_U_I8x16 */
8960
    2889,
8961
    /* MIN_U_I8x16_S */
8962
    2892,
8963
    /* MUL_F32 */
8964
    2892,
8965
    /* MUL_F32_S */
8966
    2895,
8967
    /* MUL_F32x4 */
8968
    2895,
8969
    /* MUL_F32x4_S */
8970
    2898,
8971
    /* MUL_F64 */
8972
    2898,
8973
    /* MUL_F64_S */
8974
    2901,
8975
    /* MUL_F64x2 */
8976
    2901,
8977
    /* MUL_F64x2_S */
8978
    2904,
8979
    /* MUL_I16x8 */
8980
    2904,
8981
    /* MUL_I16x8_S */
8982
    2907,
8983
    /* MUL_I32 */
8984
    2907,
8985
    /* MUL_I32_S */
8986
    2910,
8987
    /* MUL_I32x4 */
8988
    2910,
8989
    /* MUL_I32x4_S */
8990
    2913,
8991
    /* MUL_I64 */
8992
    2913,
8993
    /* MUL_I64_S */
8994
    2916,
8995
    /* MUL_I64x2 */
8996
    2916,
8997
    /* MUL_I64x2_S */
8998
    2919,
8999
    /* NARROW_S_I16x8 */
9000
    2919,
9001
    /* NARROW_S_I16x8_S */
9002
    2922,
9003
    /* NARROW_S_I8x16 */
9004
    2922,
9005
    /* NARROW_S_I8x16_S */
9006
    2925,
9007
    /* NARROW_U_I16x8 */
9008
    2925,
9009
    /* NARROW_U_I16x8_S */
9010
    2928,
9011
    /* NARROW_U_I8x16 */
9012
    2928,
9013
    /* NARROW_U_I8x16_S */
9014
    2931,
9015
    /* NEAREST_F32 */
9016
    2931,
9017
    /* NEAREST_F32_S */
9018
    2933,
9019
    /* NEAREST_F32x4 */
9020
    2933,
9021
    /* NEAREST_F32x4_S */
9022
    2935,
9023
    /* NEAREST_F64 */
9024
    2935,
9025
    /* NEAREST_F64_S */
9026
    2937,
9027
    /* NEAREST_F64x2 */
9028
    2937,
9029
    /* NEAREST_F64x2_S */
9030
    2939,
9031
    /* NEG_F32 */
9032
    2939,
9033
    /* NEG_F32_S */
9034
    2941,
9035
    /* NEG_F32x4 */
9036
    2941,
9037
    /* NEG_F32x4_S */
9038
    2943,
9039
    /* NEG_F64 */
9040
    2943,
9041
    /* NEG_F64_S */
9042
    2945,
9043
    /* NEG_F64x2 */
9044
    2945,
9045
    /* NEG_F64x2_S */
9046
    2947,
9047
    /* NEG_I16x8 */
9048
    2947,
9049
    /* NEG_I16x8_S */
9050
    2949,
9051
    /* NEG_I32x4 */
9052
    2949,
9053
    /* NEG_I32x4_S */
9054
    2951,
9055
    /* NEG_I64x2 */
9056
    2951,
9057
    /* NEG_I64x2_S */
9058
    2953,
9059
    /* NEG_I8x16 */
9060
    2953,
9061
    /* NEG_I8x16_S */
9062
    2955,
9063
    /* NE_F32 */
9064
    2955,
9065
    /* NE_F32_S */
9066
    2958,
9067
    /* NE_F32x4 */
9068
    2958,
9069
    /* NE_F32x4_S */
9070
    2961,
9071
    /* NE_F64 */
9072
    2961,
9073
    /* NE_F64_S */
9074
    2964,
9075
    /* NE_F64x2 */
9076
    2964,
9077
    /* NE_F64x2_S */
9078
    2967,
9079
    /* NE_I16x8 */
9080
    2967,
9081
    /* NE_I16x8_S */
9082
    2970,
9083
    /* NE_I32 */
9084
    2970,
9085
    /* NE_I32_S */
9086
    2973,
9087
    /* NE_I32x4 */
9088
    2973,
9089
    /* NE_I32x4_S */
9090
    2976,
9091
    /* NE_I64 */
9092
    2976,
9093
    /* NE_I64_S */
9094
    2979,
9095
    /* NE_I64x2 */
9096
    2979,
9097
    /* NE_I64x2_S */
9098
    2982,
9099
    /* NE_I8x16 */
9100
    2982,
9101
    /* NE_I8x16_S */
9102
    2985,
9103
    /* NMADD_F32x4 */
9104
    2985,
9105
    /* NMADD_F32x4_S */
9106
    2989,
9107
    /* NMADD_F64x2 */
9108
    2989,
9109
    /* NMADD_F64x2_S */
9110
    2993,
9111
    /* NOP */
9112
    2993,
9113
    /* NOP_S */
9114
    2993,
9115
    /* NOT */
9116
    2993,
9117
    /* NOT_S */
9118
    2995,
9119
    /* OR */
9120
    2995,
9121
    /* OR_I32 */
9122
    2998,
9123
    /* OR_I32_S */
9124
    3001,
9125
    /* OR_I64 */
9126
    3001,
9127
    /* OR_I64_S */
9128
    3004,
9129
    /* OR_S */
9130
    3004,
9131
    /* PMAX_F32x4 */
9132
    3004,
9133
    /* PMAX_F32x4_S */
9134
    3007,
9135
    /* PMAX_F64x2 */
9136
    3007,
9137
    /* PMAX_F64x2_S */
9138
    3010,
9139
    /* PMIN_F32x4 */
9140
    3010,
9141
    /* PMIN_F32x4_S */
9142
    3013,
9143
    /* PMIN_F64x2 */
9144
    3013,
9145
    /* PMIN_F64x2_S */
9146
    3016,
9147
    /* POPCNT_I32 */
9148
    3016,
9149
    /* POPCNT_I32_S */
9150
    3018,
9151
    /* POPCNT_I64 */
9152
    3018,
9153
    /* POPCNT_I64_S */
9154
    3020,
9155
    /* POPCNT_I8x16 */
9156
    3020,
9157
    /* POPCNT_I8x16_S */
9158
    3022,
9159
    /* Q15MULR_SAT_S_I16x8 */
9160
    3022,
9161
    /* Q15MULR_SAT_S_I16x8_S */
9162
    3025,
9163
    /* REF_IS_NULL_EXTERNREF */
9164
    3025,
9165
    /* REF_IS_NULL_EXTERNREF_S */
9166
    3027,
9167
    /* REF_IS_NULL_FUNCREF */
9168
    3027,
9169
    /* REF_IS_NULL_FUNCREF_S */
9170
    3029,
9171
    /* REF_NULL_EXTERNREF */
9172
    3029,
9173
    /* REF_NULL_EXTERNREF_S */
9174
    3030,
9175
    /* REF_NULL_FUNCREF */
9176
    3030,
9177
    /* REF_NULL_FUNCREF_S */
9178
    3031,
9179
    /* RELAXED_DOT */
9180
    3031,
9181
    /* RELAXED_DOT_ADD */
9182
    3034,
9183
    /* RELAXED_DOT_ADD_S */
9184
    3038,
9185
    /* RELAXED_DOT_BFLOAT */
9186
    3038,
9187
    /* RELAXED_DOT_BFLOAT_S */
9188
    3042,
9189
    /* RELAXED_DOT_S */
9190
    3042,
9191
    /* RELAXED_Q15MULR_S_I16x8 */
9192
    3042,
9193
    /* RELAXED_Q15MULR_S_I16x8_S */
9194
    3045,
9195
    /* RELAXED_SWIZZLE */
9196
    3045,
9197
    /* RELAXED_SWIZZLE_S */
9198
    3048,
9199
    /* REM_S_I32 */
9200
    3048,
9201
    /* REM_S_I32_S */
9202
    3051,
9203
    /* REM_S_I64 */
9204
    3051,
9205
    /* REM_S_I64_S */
9206
    3054,
9207
    /* REM_U_I32 */
9208
    3054,
9209
    /* REM_U_I32_S */
9210
    3057,
9211
    /* REM_U_I64 */
9212
    3057,
9213
    /* REM_U_I64_S */
9214
    3060,
9215
    /* REPLACE_LANE_F32x4 */
9216
    3060,
9217
    /* REPLACE_LANE_F32x4_S */
9218
    3064,
9219
    /* REPLACE_LANE_F64x2 */
9220
    3065,
9221
    /* REPLACE_LANE_F64x2_S */
9222
    3069,
9223
    /* REPLACE_LANE_I16x8 */
9224
    3070,
9225
    /* REPLACE_LANE_I16x8_S */
9226
    3074,
9227
    /* REPLACE_LANE_I32x4 */
9228
    3075,
9229
    /* REPLACE_LANE_I32x4_S */
9230
    3079,
9231
    /* REPLACE_LANE_I64x2 */
9232
    3080,
9233
    /* REPLACE_LANE_I64x2_S */
9234
    3084,
9235
    /* REPLACE_LANE_I8x16 */
9236
    3085,
9237
    /* REPLACE_LANE_I8x16_S */
9238
    3089,
9239
    /* RETHROW */
9240
    3090,
9241
    /* RETHROW_S */
9242
    3091,
9243
    /* RETURN */
9244
    3092,
9245
    /* RETURN_S */
9246
    3092,
9247
    /* RET_CALL */
9248
    3092,
9249
    /* RET_CALL_INDIRECT */
9250
    3093,
9251
    /* RET_CALL_INDIRECT_S */
9252
    3095,
9253
    /* RET_CALL_S */
9254
    3097,
9255
    /* ROTL_I32 */
9256
    3098,
9257
    /* ROTL_I32_S */
9258
    3101,
9259
    /* ROTL_I64 */
9260
    3101,
9261
    /* ROTL_I64_S */
9262
    3104,
9263
    /* ROTR_I32 */
9264
    3104,
9265
    /* ROTR_I32_S */
9266
    3107,
9267
    /* ROTR_I64 */
9268
    3107,
9269
    /* ROTR_I64_S */
9270
    3110,
9271
    /* SELECT_EXTERNREF */
9272
    3110,
9273
    /* SELECT_EXTERNREF_S */
9274
    3114,
9275
    /* SELECT_F32 */
9276
    3114,
9277
    /* SELECT_F32_S */
9278
    3118,
9279
    /* SELECT_F64 */
9280
    3118,
9281
    /* SELECT_F64_S */
9282
    3122,
9283
    /* SELECT_FUNCREF */
9284
    3122,
9285
    /* SELECT_FUNCREF_S */
9286
    3126,
9287
    /* SELECT_I32 */
9288
    3126,
9289
    /* SELECT_I32_S */
9290
    3130,
9291
    /* SELECT_I64 */
9292
    3130,
9293
    /* SELECT_I64_S */
9294
    3134,
9295
    /* SELECT_V128 */
9296
    3134,
9297
    /* SELECT_V128_S */
9298
    3138,
9299
    /* SHL_I16x8 */
9300
    3138,
9301
    /* SHL_I16x8_S */
9302
    3141,
9303
    /* SHL_I32 */
9304
    3141,
9305
    /* SHL_I32_S */
9306
    3144,
9307
    /* SHL_I32x4 */
9308
    3144,
9309
    /* SHL_I32x4_S */
9310
    3147,
9311
    /* SHL_I64 */
9312
    3147,
9313
    /* SHL_I64_S */
9314
    3150,
9315
    /* SHL_I64x2 */
9316
    3150,
9317
    /* SHL_I64x2_S */
9318
    3153,
9319
    /* SHL_I8x16 */
9320
    3153,
9321
    /* SHL_I8x16_S */
9322
    3156,
9323
    /* SHR_S_I16x8 */
9324
    3156,
9325
    /* SHR_S_I16x8_S */
9326
    3159,
9327
    /* SHR_S_I32 */
9328
    3159,
9329
    /* SHR_S_I32_S */
9330
    3162,
9331
    /* SHR_S_I32x4 */
9332
    3162,
9333
    /* SHR_S_I32x4_S */
9334
    3165,
9335
    /* SHR_S_I64 */
9336
    3165,
9337
    /* SHR_S_I64_S */
9338
    3168,
9339
    /* SHR_S_I64x2 */
9340
    3168,
9341
    /* SHR_S_I64x2_S */
9342
    3171,
9343
    /* SHR_S_I8x16 */
9344
    3171,
9345
    /* SHR_S_I8x16_S */
9346
    3174,
9347
    /* SHR_U_I16x8 */
9348
    3174,
9349
    /* SHR_U_I16x8_S */
9350
    3177,
9351
    /* SHR_U_I32 */
9352
    3177,
9353
    /* SHR_U_I32_S */
9354
    3180,
9355
    /* SHR_U_I32x4 */
9356
    3180,
9357
    /* SHR_U_I32x4_S */
9358
    3183,
9359
    /* SHR_U_I64 */
9360
    3183,
9361
    /* SHR_U_I64_S */
9362
    3186,
9363
    /* SHR_U_I64x2 */
9364
    3186,
9365
    /* SHR_U_I64x2_S */
9366
    3189,
9367
    /* SHR_U_I8x16 */
9368
    3189,
9369
    /* SHR_U_I8x16_S */
9370
    3192,
9371
    /* SHUFFLE */
9372
    3192,
9373
    /* SHUFFLE_S */
9374
    3211,
9375
    /* SIMD_RELAXED_FMAX_F32x4 */
9376
    3227,
9377
    /* SIMD_RELAXED_FMAX_F32x4_S */
9378
    3230,
9379
    /* SIMD_RELAXED_FMAX_F64x2 */
9380
    3230,
9381
    /* SIMD_RELAXED_FMAX_F64x2_S */
9382
    3233,
9383
    /* SIMD_RELAXED_FMIN_F32x4 */
9384
    3233,
9385
    /* SIMD_RELAXED_FMIN_F32x4_S */
9386
    3236,
9387
    /* SIMD_RELAXED_FMIN_F64x2 */
9388
    3236,
9389
    /* SIMD_RELAXED_FMIN_F64x2_S */
9390
    3239,
9391
    /* SPLAT_F32x4 */
9392
    3239,
9393
    /* SPLAT_F32x4_S */
9394
    3241,
9395
    /* SPLAT_F64x2 */
9396
    3241,
9397
    /* SPLAT_F64x2_S */
9398
    3243,
9399
    /* SPLAT_I16x8 */
9400
    3243,
9401
    /* SPLAT_I16x8_S */
9402
    3245,
9403
    /* SPLAT_I32x4 */
9404
    3245,
9405
    /* SPLAT_I32x4_S */
9406
    3247,
9407
    /* SPLAT_I64x2 */
9408
    3247,
9409
    /* SPLAT_I64x2_S */
9410
    3249,
9411
    /* SPLAT_I8x16 */
9412
    3249,
9413
    /* SPLAT_I8x16_S */
9414
    3251,
9415
    /* SQRT_F32 */
9416
    3251,
9417
    /* SQRT_F32_S */
9418
    3253,
9419
    /* SQRT_F32x4 */
9420
    3253,
9421
    /* SQRT_F32x4_S */
9422
    3255,
9423
    /* SQRT_F64 */
9424
    3255,
9425
    /* SQRT_F64_S */
9426
    3257,
9427
    /* SQRT_F64x2 */
9428
    3257,
9429
    /* SQRT_F64x2_S */
9430
    3259,
9431
    /* STORE16_I32_A32 */
9432
    3259,
9433
    /* STORE16_I32_A32_S */
9434
    3263,
9435
    /* STORE16_I32_A64 */
9436
    3265,
9437
    /* STORE16_I32_A64_S */
9438
    3269,
9439
    /* STORE16_I64_A32 */
9440
    3271,
9441
    /* STORE16_I64_A32_S */
9442
    3275,
9443
    /* STORE16_I64_A64 */
9444
    3277,
9445
    /* STORE16_I64_A64_S */
9446
    3281,
9447
    /* STORE32_I64_A32 */
9448
    3283,
9449
    /* STORE32_I64_A32_S */
9450
    3287,
9451
    /* STORE32_I64_A64 */
9452
    3289,
9453
    /* STORE32_I64_A64_S */
9454
    3293,
9455
    /* STORE8_I32_A32 */
9456
    3295,
9457
    /* STORE8_I32_A32_S */
9458
    3299,
9459
    /* STORE8_I32_A64 */
9460
    3301,
9461
    /* STORE8_I32_A64_S */
9462
    3305,
9463
    /* STORE8_I64_A32 */
9464
    3307,
9465
    /* STORE8_I64_A32_S */
9466
    3311,
9467
    /* STORE8_I64_A64 */
9468
    3313,
9469
    /* STORE8_I64_A64_S */
9470
    3317,
9471
    /* STORE_F32_A32 */
9472
    3319,
9473
    /* STORE_F32_A32_S */
9474
    3323,
9475
    /* STORE_F32_A64 */
9476
    3325,
9477
    /* STORE_F32_A64_S */
9478
    3329,
9479
    /* STORE_F64_A32 */
9480
    3331,
9481
    /* STORE_F64_A32_S */
9482
    3335,
9483
    /* STORE_F64_A64 */
9484
    3337,
9485
    /* STORE_F64_A64_S */
9486
    3341,
9487
    /* STORE_I32_A32 */
9488
    3343,
9489
    /* STORE_I32_A32_S */
9490
    3347,
9491
    /* STORE_I32_A64 */
9492
    3349,
9493
    /* STORE_I32_A64_S */
9494
    3353,
9495
    /* STORE_I64_A32 */
9496
    3355,
9497
    /* STORE_I64_A32_S */
9498
    3359,
9499
    /* STORE_I64_A64 */
9500
    3361,
9501
    /* STORE_I64_A64_S */
9502
    3365,
9503
    /* STORE_LANE_I16x8_A32 */
9504
    3367,
9505
    /* STORE_LANE_I16x8_A32_S */
9506
    3372,
9507
    /* STORE_LANE_I16x8_A64 */
9508
    3375,
9509
    /* STORE_LANE_I16x8_A64_S */
9510
    3380,
9511
    /* STORE_LANE_I32x4_A32 */
9512
    3383,
9513
    /* STORE_LANE_I32x4_A32_S */
9514
    3388,
9515
    /* STORE_LANE_I32x4_A64 */
9516
    3391,
9517
    /* STORE_LANE_I32x4_A64_S */
9518
    3396,
9519
    /* STORE_LANE_I64x2_A32 */
9520
    3399,
9521
    /* STORE_LANE_I64x2_A32_S */
9522
    3404,
9523
    /* STORE_LANE_I64x2_A64 */
9524
    3407,
9525
    /* STORE_LANE_I64x2_A64_S */
9526
    3412,
9527
    /* STORE_LANE_I8x16_A32 */
9528
    3415,
9529
    /* STORE_LANE_I8x16_A32_S */
9530
    3420,
9531
    /* STORE_LANE_I8x16_A64 */
9532
    3423,
9533
    /* STORE_LANE_I8x16_A64_S */
9534
    3428,
9535
    /* STORE_V128_A32 */
9536
    3431,
9537
    /* STORE_V128_A32_S */
9538
    3435,
9539
    /* STORE_V128_A64 */
9540
    3437,
9541
    /* STORE_V128_A64_S */
9542
    3441,
9543
    /* SUB_F32 */
9544
    3443,
9545
    /* SUB_F32_S */
9546
    3446,
9547
    /* SUB_F32x4 */
9548
    3446,
9549
    /* SUB_F32x4_S */
9550
    3449,
9551
    /* SUB_F64 */
9552
    3449,
9553
    /* SUB_F64_S */
9554
    3452,
9555
    /* SUB_F64x2 */
9556
    3452,
9557
    /* SUB_F64x2_S */
9558
    3455,
9559
    /* SUB_I16x8 */
9560
    3455,
9561
    /* SUB_I16x8_S */
9562
    3458,
9563
    /* SUB_I32 */
9564
    3458,
9565
    /* SUB_I32_S */
9566
    3461,
9567
    /* SUB_I32x4 */
9568
    3461,
9569
    /* SUB_I32x4_S */
9570
    3464,
9571
    /* SUB_I64 */
9572
    3464,
9573
    /* SUB_I64_S */
9574
    3467,
9575
    /* SUB_I64x2 */
9576
    3467,
9577
    /* SUB_I64x2_S */
9578
    3470,
9579
    /* SUB_I8x16 */
9580
    3470,
9581
    /* SUB_I8x16_S */
9582
    3473,
9583
    /* SUB_SAT_S_I16x8 */
9584
    3473,
9585
    /* SUB_SAT_S_I16x8_S */
9586
    3476,
9587
    /* SUB_SAT_S_I8x16 */
9588
    3476,
9589
    /* SUB_SAT_S_I8x16_S */
9590
    3479,
9591
    /* SUB_SAT_U_I16x8 */
9592
    3479,
9593
    /* SUB_SAT_U_I16x8_S */
9594
    3482,
9595
    /* SUB_SAT_U_I8x16 */
9596
    3482,
9597
    /* SUB_SAT_U_I8x16_S */
9598
    3485,
9599
    /* SWIZZLE */
9600
    3485,
9601
    /* SWIZZLE_S */
9602
    3488,
9603
    /* TABLE_COPY */
9604
    3488,
9605
    /* TABLE_COPY_S */
9606
    3493,
9607
    /* TABLE_FILL_EXTERNREF */
9608
    3495,
9609
    /* TABLE_FILL_EXTERNREF_S */
9610
    3499,
9611
    /* TABLE_FILL_FUNCREF */
9612
    3500,
9613
    /* TABLE_FILL_FUNCREF_S */
9614
    3504,
9615
    /* TABLE_GET_EXTERNREF */
9616
    3505,
9617
    /* TABLE_GET_EXTERNREF_S */
9618
    3508,
9619
    /* TABLE_GET_FUNCREF */
9620
    3509,
9621
    /* TABLE_GET_FUNCREF_S */
9622
    3512,
9623
    /* TABLE_GROW_EXTERNREF */
9624
    3513,
9625
    /* TABLE_GROW_EXTERNREF_S */
9626
    3517,
9627
    /* TABLE_GROW_FUNCREF */
9628
    3518,
9629
    /* TABLE_GROW_FUNCREF_S */
9630
    3522,
9631
    /* TABLE_SET_EXTERNREF */
9632
    3523,
9633
    /* TABLE_SET_EXTERNREF_S */
9634
    3526,
9635
    /* TABLE_SET_FUNCREF */
9636
    3527,
9637
    /* TABLE_SET_FUNCREF_S */
9638
    3530,
9639
    /* TABLE_SIZE */
9640
    3531,
9641
    /* TABLE_SIZE_S */
9642
    3533,
9643
    /* TEE_EXTERNREF */
9644
    3534,
9645
    /* TEE_EXTERNREF_S */
9646
    3537,
9647
    /* TEE_F32 */
9648
    3537,
9649
    /* TEE_F32_S */
9650
    3540,
9651
    /* TEE_F64 */
9652
    3540,
9653
    /* TEE_F64_S */
9654
    3543,
9655
    /* TEE_FUNCREF */
9656
    3543,
9657
    /* TEE_FUNCREF_S */
9658
    3546,
9659
    /* TEE_I32 */
9660
    3546,
9661
    /* TEE_I32_S */
9662
    3549,
9663
    /* TEE_I64 */
9664
    3549,
9665
    /* TEE_I64_S */
9666
    3552,
9667
    /* TEE_V128 */
9668
    3552,
9669
    /* TEE_V128_S */
9670
    3555,
9671
    /* THROW */
9672
    3555,
9673
    /* THROW_S */
9674
    3556,
9675
    /* TRUNC_F32 */
9676
    3557,
9677
    /* TRUNC_F32_S */
9678
    3559,
9679
    /* TRUNC_F32x4 */
9680
    3559,
9681
    /* TRUNC_F32x4_S */
9682
    3561,
9683
    /* TRUNC_F64 */
9684
    3561,
9685
    /* TRUNC_F64_S */
9686
    3563,
9687
    /* TRUNC_F64x2 */
9688
    3563,
9689
    /* TRUNC_F64x2_S */
9690
    3565,
9691
    /* TRY */
9692
    3565,
9693
    /* TRY_S */
9694
    3566,
9695
    /* UNREACHABLE */
9696
    3567,
9697
    /* UNREACHABLE_S */
9698
    3567,
9699
    /* XOR */
9700
    3567,
9701
    /* XOR_I32 */
9702
    3570,
9703
    /* XOR_I32_S */
9704
    3573,
9705
    /* XOR_I64 */
9706
    3573,
9707
    /* XOR_I64_S */
9708
    3576,
9709
    /* XOR_S */
9710
    3576,
9711
    /* anonymous_7277MEMORY_GROW_A32 */
9712
    3576,
9713
    /* anonymous_7277MEMORY_GROW_A32_S */
9714
    3579,
9715
    /* anonymous_7277MEMORY_SIZE_A32 */
9716
    3580,
9717
    /* anonymous_7277MEMORY_SIZE_A32_S */
9718
    3582,
9719
    /* anonymous_7278MEMORY_GROW_A64 */
9720
    3583,
9721
    /* anonymous_7278MEMORY_GROW_A64_S */
9722
    3586,
9723
    /* anonymous_7278MEMORY_SIZE_A64 */
9724
    3587,
9725
    /* anonymous_7278MEMORY_SIZE_A64_S */
9726
    3589,
9727
    /* anonymous_7959DATA_DROP */
9728
    3590,
9729
    /* anonymous_7959DATA_DROP_S */
9730
    3591,
9731
    /* anonymous_7959MEMORY_COPY_A32 */
9732
    3592,
9733
    /* anonymous_7959MEMORY_COPY_A32_S */
9734
    3597,
9735
    /* anonymous_7959MEMORY_FILL_A32 */
9736
    3599,
9737
    /* anonymous_7959MEMORY_FILL_A32_S */
9738
    3603,
9739
    /* anonymous_7959MEMORY_INIT_A32 */
9740
    3604,
9741
    /* anonymous_7959MEMORY_INIT_A32_S */
9742
    3609,
9743
    /* anonymous_7960DATA_DROP */
9744
    3611,
9745
    /* anonymous_7960DATA_DROP_S */
9746
    3612,
9747
    /* anonymous_7960MEMORY_COPY_A64 */
9748
    3613,
9749
    /* anonymous_7960MEMORY_COPY_A64_S */
9750
    3618,
9751
    /* anonymous_7960MEMORY_FILL_A64 */
9752
    3620,
9753
    /* anonymous_7960MEMORY_FILL_A64_S */
9754
    3624,
9755
    /* anonymous_7960MEMORY_INIT_A64 */
9756
    3625,
9757
    /* anonymous_7960MEMORY_INIT_A64_S */
9758
    3630,
9759
    /* convert_low_s_F64x2 */
9760
    3632,
9761
    /* convert_low_s_F64x2_S */
9762
    3634,
9763
    /* convert_low_u_F64x2 */
9764
    3634,
9765
    /* convert_low_u_F64x2_S */
9766
    3636,
9767
    /* demote_zero_F32x4 */
9768
    3636,
9769
    /* demote_zero_F32x4_S */
9770
    3638,
9771
    /* extend_high_s_I16x8 */
9772
    3638,
9773
    /* extend_high_s_I16x8_S */
9774
    3640,
9775
    /* extend_high_s_I32x4 */
9776
    3640,
9777
    /* extend_high_s_I32x4_S */
9778
    3642,
9779
    /* extend_high_s_I64x2 */
9780
    3642,
9781
    /* extend_high_s_I64x2_S */
9782
    3644,
9783
    /* extend_high_u_I16x8 */
9784
    3644,
9785
    /* extend_high_u_I16x8_S */
9786
    3646,
9787
    /* extend_high_u_I32x4 */
9788
    3646,
9789
    /* extend_high_u_I32x4_S */
9790
    3648,
9791
    /* extend_high_u_I64x2 */
9792
    3648,
9793
    /* extend_high_u_I64x2_S */
9794
    3650,
9795
    /* extend_low_s_I16x8 */
9796
    3650,
9797
    /* extend_low_s_I16x8_S */
9798
    3652,
9799
    /* extend_low_s_I32x4 */
9800
    3652,
9801
    /* extend_low_s_I32x4_S */
9802
    3654,
9803
    /* extend_low_s_I64x2 */
9804
    3654,
9805
    /* extend_low_s_I64x2_S */
9806
    3656,
9807
    /* extend_low_u_I16x8 */
9808
    3656,
9809
    /* extend_low_u_I16x8_S */
9810
    3658,
9811
    /* extend_low_u_I32x4 */
9812
    3658,
9813
    /* extend_low_u_I32x4_S */
9814
    3660,
9815
    /* extend_low_u_I64x2 */
9816
    3660,
9817
    /* extend_low_u_I64x2_S */
9818
    3662,
9819
    /* fp_to_sint_I32x4 */
9820
    3662,
9821
    /* fp_to_sint_I32x4_S */
9822
    3664,
9823
    /* fp_to_uint_I32x4 */
9824
    3664,
9825
    /* fp_to_uint_I32x4_S */
9826
    3666,
9827
    /* int_wasm_extadd_pairwise_signed_I16x8 */
9828
    3666,
9829
    /* int_wasm_extadd_pairwise_signed_I16x8_S */
9830
    3668,
9831
    /* int_wasm_extadd_pairwise_signed_I32x4 */
9832
    3668,
9833
    /* int_wasm_extadd_pairwise_signed_I32x4_S */
9834
    3670,
9835
    /* int_wasm_extadd_pairwise_unsigned_I16x8 */
9836
    3670,
9837
    /* int_wasm_extadd_pairwise_unsigned_I16x8_S */
9838
    3672,
9839
    /* int_wasm_extadd_pairwise_unsigned_I32x4 */
9840
    3672,
9841
    /* int_wasm_extadd_pairwise_unsigned_I32x4_S */
9842
    3674,
9843
    /* int_wasm_relaxed_trunc_signed_I32x4 */
9844
    3674,
9845
    /* int_wasm_relaxed_trunc_signed_I32x4_S */
9846
    3676,
9847
    /* int_wasm_relaxed_trunc_signed_zero_I32x4 */
9848
    3676,
9849
    /* int_wasm_relaxed_trunc_signed_zero_I32x4_S */
9850
    3678,
9851
    /* int_wasm_relaxed_trunc_unsigned_I32x4 */
9852
    3678,
9853
    /* int_wasm_relaxed_trunc_unsigned_I32x4_S */
9854
    3680,
9855
    /* int_wasm_relaxed_trunc_unsigned_zero_I32x4 */
9856
    3680,
9857
    /* int_wasm_relaxed_trunc_unsigned_zero_I32x4_S */
9858
    3682,
9859
    /* promote_low_F64x2 */
9860
    3682,
9861
    /* promote_low_F64x2_S */
9862
    3684,
9863
    /* sint_to_fp_F32x4 */
9864
    3684,
9865
    /* sint_to_fp_F32x4_S */
9866
    3686,
9867
    /* trunc_sat_zero_s_I32x4 */
9868
    3686,
9869
    /* trunc_sat_zero_s_I32x4_S */
9870
    3688,
9871
    /* trunc_sat_zero_u_I32x4 */
9872
    3688,
9873
    /* trunc_sat_zero_u_I32x4_S */
9874
    3690,
9875
    /* uint_to_fp_F32x4 */
9876
    3690,
9877
    /* uint_to_fp_F32x4_S */
9878
    3692,
9879
  };
9880
9881
  using namespace OpTypes;
9882
  static const int8_t OpcodeOperandTypes[] = {
9883
    
9884
    /* PHI */
9885
    -1, 
9886
    /* INLINEASM */
9887
    /* INLINEASM_BR */
9888
    /* CFI_INSTRUCTION */
9889
    i32imm, 
9890
    /* EH_LABEL */
9891
    i32imm, 
9892
    /* GC_LABEL */
9893
    i32imm, 
9894
    /* ANNOTATION_LABEL */
9895
    i32imm, 
9896
    /* KILL */
9897
    /* EXTRACT_SUBREG */
9898
    -1, -1, i32imm, 
9899
    /* INSERT_SUBREG */
9900
    -1, -1, -1, i32imm, 
9901
    /* IMPLICIT_DEF */
9902
    -1, 
9903
    /* SUBREG_TO_REG */
9904
    -1, -1, -1, i32imm, 
9905
    /* COPY_TO_REGCLASS */
9906
    -1, -1, i32imm, 
9907
    /* DBG_VALUE */
9908
    /* DBG_VALUE_LIST */
9909
    /* DBG_INSTR_REF */
9910
    /* DBG_PHI */
9911
    /* DBG_LABEL */
9912
    -1, 
9913
    /* REG_SEQUENCE */
9914
    -1, -1, 
9915
    /* COPY */
9916
    -1, -1, 
9917
    /* BUNDLE */
9918
    /* LIFETIME_START */
9919
    i32imm, 
9920
    /* LIFETIME_END */
9921
    i32imm, 
9922
    /* PSEUDO_PROBE */
9923
    i64imm, i64imm, i8imm, i32imm, 
9924
    /* ARITH_FENCE */
9925
    -1, -1, 
9926
    /* STACKMAP */
9927
    i64imm, i32imm, 
9928
    /* FENTRY_CALL */
9929
    /* PATCHPOINT */
9930
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
9931
    /* LOAD_STACK_GUARD */
9932
    -1, 
9933
    /* PREALLOCATED_SETUP */
9934
    i32imm, 
9935
    /* PREALLOCATED_ARG */
9936
    -1, i32imm, i32imm, 
9937
    /* STATEPOINT */
9938
    /* LOCAL_ESCAPE */
9939
    -1, i32imm, 
9940
    /* FAULTING_OP */
9941
    -1, 
9942
    /* PATCHABLE_OP */
9943
    /* PATCHABLE_FUNCTION_ENTER */
9944
    /* PATCHABLE_RET */
9945
    /* PATCHABLE_FUNCTION_EXIT */
9946
    /* PATCHABLE_TAIL_CALL */
9947
    /* PATCHABLE_EVENT_CALL */
9948
    -1, -1, 
9949
    /* PATCHABLE_TYPED_EVENT_CALL */
9950
    -1, -1, -1, 
9951
    /* ICALL_BRANCH_FUNNEL */
9952
    /* MEMBARRIER */
9953
    /* JUMP_TABLE_DEBUG_INFO */
9954
    i64imm, 
9955
    /* G_ASSERT_SEXT */
9956
    type0, type0, untyped_imm_0, 
9957
    /* G_ASSERT_ZEXT */
9958
    type0, type0, untyped_imm_0, 
9959
    /* G_ASSERT_ALIGN */
9960
    type0, type0, untyped_imm_0, 
9961
    /* G_ADD */
9962
    type0, type0, type0, 
9963
    /* G_SUB */
9964
    type0, type0, type0, 
9965
    /* G_MUL */
9966
    type0, type0, type0, 
9967
    /* G_SDIV */
9968
    type0, type0, type0, 
9969
    /* G_UDIV */
9970
    type0, type0, type0, 
9971
    /* G_SREM */
9972
    type0, type0, type0, 
9973
    /* G_UREM */
9974
    type0, type0, type0, 
9975
    /* G_SDIVREM */
9976
    type0, type0, type0, type0, 
9977
    /* G_UDIVREM */
9978
    type0, type0, type0, type0, 
9979
    /* G_AND */
9980
    type0, type0, type0, 
9981
    /* G_OR */
9982
    type0, type0, type0, 
9983
    /* G_XOR */
9984
    type0, type0, type0, 
9985
    /* G_IMPLICIT_DEF */
9986
    type0, 
9987
    /* G_PHI */
9988
    type0, 
9989
    /* G_FRAME_INDEX */
9990
    type0, -1, 
9991
    /* G_GLOBAL_VALUE */
9992
    type0, -1, 
9993
    /* G_CONSTANT_POOL */
9994
    type0, -1, 
9995
    /* G_EXTRACT */
9996
    type0, type1, untyped_imm_0, 
9997
    /* G_UNMERGE_VALUES */
9998
    type0, type1, 
9999
    /* G_INSERT */
10000
    type0, type0, type1, untyped_imm_0, 
10001
    /* G_MERGE_VALUES */
10002
    type0, type1, 
10003
    /* G_BUILD_VECTOR */
10004
    type0, type1, 
10005
    /* G_BUILD_VECTOR_TRUNC */
10006
    type0, type1, 
10007
    /* G_CONCAT_VECTORS */
10008
    type0, type1, 
10009
    /* G_PTRTOINT */
10010
    type0, type1, 
10011
    /* G_INTTOPTR */
10012
    type0, type1, 
10013
    /* G_BITCAST */
10014
    type0, type1, 
10015
    /* G_FREEZE */
10016
    type0, type0, 
10017
    /* G_CONSTANT_FOLD_BARRIER */
10018
    type0, type0, 
10019
    /* G_INTRINSIC_FPTRUNC_ROUND */
10020
    type0, type1, i32imm, 
10021
    /* G_INTRINSIC_TRUNC */
10022
    type0, type0, 
10023
    /* G_INTRINSIC_ROUND */
10024
    type0, type0, 
10025
    /* G_INTRINSIC_LRINT */
10026
    type0, type1, 
10027
    /* G_INTRINSIC_ROUNDEVEN */
10028
    type0, type0, 
10029
    /* G_READCYCLECOUNTER */
10030
    type0, 
10031
    /* G_LOAD */
10032
    type0, ptype1, 
10033
    /* G_SEXTLOAD */
10034
    type0, ptype1, 
10035
    /* G_ZEXTLOAD */
10036
    type0, ptype1, 
10037
    /* G_INDEXED_LOAD */
10038
    type0, ptype1, ptype1, type2, -1, 
10039
    /* G_INDEXED_SEXTLOAD */
10040
    type0, ptype1, ptype1, type2, -1, 
10041
    /* G_INDEXED_ZEXTLOAD */
10042
    type0, ptype1, ptype1, type2, -1, 
10043
    /* G_STORE */
10044
    type0, ptype1, 
10045
    /* G_INDEXED_STORE */
10046
    ptype0, type1, ptype0, ptype2, -1, 
10047
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
10048
    type0, type1, type2, type0, type0, 
10049
    /* G_ATOMIC_CMPXCHG */
10050
    type0, ptype1, type0, type0, 
10051
    /* G_ATOMICRMW_XCHG */
10052
    type0, ptype1, type0, 
10053
    /* G_ATOMICRMW_ADD */
10054
    type0, ptype1, type0, 
10055
    /* G_ATOMICRMW_SUB */
10056
    type0, ptype1, type0, 
10057
    /* G_ATOMICRMW_AND */
10058
    type0, ptype1, type0, 
10059
    /* G_ATOMICRMW_NAND */
10060
    type0, ptype1, type0, 
10061
    /* G_ATOMICRMW_OR */
10062
    type0, ptype1, type0, 
10063
    /* G_ATOMICRMW_XOR */
10064
    type0, ptype1, type0, 
10065
    /* G_ATOMICRMW_MAX */
10066
    type0, ptype1, type0, 
10067
    /* G_ATOMICRMW_MIN */
10068
    type0, ptype1, type0, 
10069
    /* G_ATOMICRMW_UMAX */
10070
    type0, ptype1, type0, 
10071
    /* G_ATOMICRMW_UMIN */
10072
    type0, ptype1, type0, 
10073
    /* G_ATOMICRMW_FADD */
10074
    type0, ptype1, type0, 
10075
    /* G_ATOMICRMW_FSUB */
10076
    type0, ptype1, type0, 
10077
    /* G_ATOMICRMW_FMAX */
10078
    type0, ptype1, type0, 
10079
    /* G_ATOMICRMW_FMIN */
10080
    type0, ptype1, type0, 
10081
    /* G_ATOMICRMW_UINC_WRAP */
10082
    type0, ptype1, type0, 
10083
    /* G_ATOMICRMW_UDEC_WRAP */
10084
    type0, ptype1, type0, 
10085
    /* G_FENCE */
10086
    i32imm, i32imm, 
10087
    /* G_PREFETCH */
10088
    ptype0, i32imm, i32imm, i32imm, 
10089
    /* G_BRCOND */
10090
    type0, -1, 
10091
    /* G_BRINDIRECT */
10092
    type0, 
10093
    /* G_INVOKE_REGION_START */
10094
    /* G_INTRINSIC */
10095
    -1, 
10096
    /* G_INTRINSIC_W_SIDE_EFFECTS */
10097
    -1, 
10098
    /* G_INTRINSIC_CONVERGENT */
10099
    -1, 
10100
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
10101
    -1, 
10102
    /* G_ANYEXT */
10103
    type0, type1, 
10104
    /* G_TRUNC */
10105
    type0, type1, 
10106
    /* G_CONSTANT */
10107
    type0, -1, 
10108
    /* G_FCONSTANT */
10109
    type0, -1, 
10110
    /* G_VASTART */
10111
    type0, 
10112
    /* G_VAARG */
10113
    type0, type1, -1, 
10114
    /* G_SEXT */
10115
    type0, type1, 
10116
    /* G_SEXT_INREG */
10117
    type0, type0, untyped_imm_0, 
10118
    /* G_ZEXT */
10119
    type0, type1, 
10120
    /* G_SHL */
10121
    type0, type0, type1, 
10122
    /* G_LSHR */
10123
    type0, type0, type1, 
10124
    /* G_ASHR */
10125
    type0, type0, type1, 
10126
    /* G_FSHL */
10127
    type0, type0, type0, type1, 
10128
    /* G_FSHR */
10129
    type0, type0, type0, type1, 
10130
    /* G_ROTR */
10131
    type0, type0, type1, 
10132
    /* G_ROTL */
10133
    type0, type0, type1, 
10134
    /* G_ICMP */
10135
    type0, -1, type1, type1, 
10136
    /* G_FCMP */
10137
    type0, -1, type1, type1, 
10138
    /* G_SELECT */
10139
    type0, type1, type0, type0, 
10140
    /* G_UADDO */
10141
    type0, type1, type0, type0, 
10142
    /* G_UADDE */
10143
    type0, type1, type0, type0, type1, 
10144
    /* G_USUBO */
10145
    type0, type1, type0, type0, 
10146
    /* G_USUBE */
10147
    type0, type1, type0, type0, type1, 
10148
    /* G_SADDO */
10149
    type0, type1, type0, type0, 
10150
    /* G_SADDE */
10151
    type0, type1, type0, type0, type1, 
10152
    /* G_SSUBO */
10153
    type0, type1, type0, type0, 
10154
    /* G_SSUBE */
10155
    type0, type1, type0, type0, type1, 
10156
    /* G_UMULO */
10157
    type0, type1, type0, type0, 
10158
    /* G_SMULO */
10159
    type0, type1, type0, type0, 
10160
    /* G_UMULH */
10161
    type0, type0, type0, 
10162
    /* G_SMULH */
10163
    type0, type0, type0, 
10164
    /* G_UADDSAT */
10165
    type0, type0, type0, 
10166
    /* G_SADDSAT */
10167
    type0, type0, type0, 
10168
    /* G_USUBSAT */
10169
    type0, type0, type0, 
10170
    /* G_SSUBSAT */
10171
    type0, type0, type0, 
10172
    /* G_USHLSAT */
10173
    type0, type0, type1, 
10174
    /* G_SSHLSAT */
10175
    type0, type0, type1, 
10176
    /* G_SMULFIX */
10177
    type0, type0, type0, untyped_imm_0, 
10178
    /* G_UMULFIX */
10179
    type0, type0, type0, untyped_imm_0, 
10180
    /* G_SMULFIXSAT */
10181
    type0, type0, type0, untyped_imm_0, 
10182
    /* G_UMULFIXSAT */
10183
    type0, type0, type0, untyped_imm_0, 
10184
    /* G_SDIVFIX */
10185
    type0, type0, type0, untyped_imm_0, 
10186
    /* G_UDIVFIX */
10187
    type0, type0, type0, untyped_imm_0, 
10188
    /* G_SDIVFIXSAT */
10189
    type0, type0, type0, untyped_imm_0, 
10190
    /* G_UDIVFIXSAT */
10191
    type0, type0, type0, untyped_imm_0, 
10192
    /* G_FADD */
10193
    type0, type0, type0, 
10194
    /* G_FSUB */
10195
    type0, type0, type0, 
10196
    /* G_FMUL */
10197
    type0, type0, type0, 
10198
    /* G_FMA */
10199
    type0, type0, type0, type0, 
10200
    /* G_FMAD */
10201
    type0, type0, type0, type0, 
10202
    /* G_FDIV */
10203
    type0, type0, type0, 
10204
    /* G_FREM */
10205
    type0, type0, type0, 
10206
    /* G_FPOW */
10207
    type0, type0, type0, 
10208
    /* G_FPOWI */
10209
    type0, type0, type1, 
10210
    /* G_FEXP */
10211
    type0, type0, 
10212
    /* G_FEXP2 */
10213
    type0, type0, 
10214
    /* G_FEXP10 */
10215
    type0, type0, 
10216
    /* G_FLOG */
10217
    type0, type0, 
10218
    /* G_FLOG2 */
10219
    type0, type0, 
10220
    /* G_FLOG10 */
10221
    type0, type0, 
10222
    /* G_FLDEXP */
10223
    type0, type0, type1, 
10224
    /* G_FFREXP */
10225
    type0, type1, type0, 
10226
    /* G_FNEG */
10227
    type0, type0, 
10228
    /* G_FPEXT */
10229
    type0, type1, 
10230
    /* G_FPTRUNC */
10231
    type0, type1, 
10232
    /* G_FPTOSI */
10233
    type0, type1, 
10234
    /* G_FPTOUI */
10235
    type0, type1, 
10236
    /* G_SITOFP */
10237
    type0, type1, 
10238
    /* G_UITOFP */
10239
    type0, type1, 
10240
    /* G_FABS */
10241
    type0, type0, 
10242
    /* G_FCOPYSIGN */
10243
    type0, type0, type1, 
10244
    /* G_IS_FPCLASS */
10245
    type0, type1, -1, 
10246
    /* G_FCANONICALIZE */
10247
    type0, type0, 
10248
    /* G_FMINNUM */
10249
    type0, type0, type0, 
10250
    /* G_FMAXNUM */
10251
    type0, type0, type0, 
10252
    /* G_FMINNUM_IEEE */
10253
    type0, type0, type0, 
10254
    /* G_FMAXNUM_IEEE */
10255
    type0, type0, type0, 
10256
    /* G_FMINIMUM */
10257
    type0, type0, type0, 
10258
    /* G_FMAXIMUM */
10259
    type0, type0, type0, 
10260
    /* G_GET_FPENV */
10261
    type0, 
10262
    /* G_SET_FPENV */
10263
    type0, 
10264
    /* G_RESET_FPENV */
10265
    /* G_GET_FPMODE */
10266
    type0, 
10267
    /* G_SET_FPMODE */
10268
    type0, 
10269
    /* G_RESET_FPMODE */
10270
    /* G_PTR_ADD */
10271
    ptype0, ptype0, type1, 
10272
    /* G_PTRMASK */
10273
    ptype0, ptype0, type1, 
10274
    /* G_SMIN */
10275
    type0, type0, type0, 
10276
    /* G_SMAX */
10277
    type0, type0, type0, 
10278
    /* G_UMIN */
10279
    type0, type0, type0, 
10280
    /* G_UMAX */
10281
    type0, type0, type0, 
10282
    /* G_ABS */
10283
    type0, type0, 
10284
    /* G_LROUND */
10285
    type0, type1, 
10286
    /* G_LLROUND */
10287
    type0, type1, 
10288
    /* G_BR */
10289
    -1, 
10290
    /* G_BRJT */
10291
    ptype0, -1, type1, 
10292
    /* G_INSERT_VECTOR_ELT */
10293
    type0, type0, type1, type2, 
10294
    /* G_EXTRACT_VECTOR_ELT */
10295
    type0, type1, type2, 
10296
    /* G_SHUFFLE_VECTOR */
10297
    type0, type1, type1, -1, 
10298
    /* G_CTTZ */
10299
    type0, type1, 
10300
    /* G_CTTZ_ZERO_UNDEF */
10301
    type0, type1, 
10302
    /* G_CTLZ */
10303
    type0, type1, 
10304
    /* G_CTLZ_ZERO_UNDEF */
10305
    type0, type1, 
10306
    /* G_CTPOP */
10307
    type0, type1, 
10308
    /* G_BSWAP */
10309
    type0, type0, 
10310
    /* G_BITREVERSE */
10311
    type0, type0, 
10312
    /* G_FCEIL */
10313
    type0, type0, 
10314
    /* G_FCOS */
10315
    type0, type0, 
10316
    /* G_FSIN */
10317
    type0, type0, 
10318
    /* G_FSQRT */
10319
    type0, type0, 
10320
    /* G_FFLOOR */
10321
    type0, type0, 
10322
    /* G_FRINT */
10323
    type0, type0, 
10324
    /* G_FNEARBYINT */
10325
    type0, type0, 
10326
    /* G_ADDRSPACE_CAST */
10327
    type0, type1, 
10328
    /* G_BLOCK_ADDR */
10329
    type0, -1, 
10330
    /* G_JUMP_TABLE */
10331
    type0, -1, 
10332
    /* G_DYN_STACKALLOC */
10333
    ptype0, type1, i32imm, 
10334
    /* G_STACKSAVE */
10335
    ptype0, 
10336
    /* G_STACKRESTORE */
10337
    ptype0, 
10338
    /* G_STRICT_FADD */
10339
    type0, type0, type0, 
10340
    /* G_STRICT_FSUB */
10341
    type0, type0, type0, 
10342
    /* G_STRICT_FMUL */
10343
    type0, type0, type0, 
10344
    /* G_STRICT_FDIV */
10345
    type0, type0, type0, 
10346
    /* G_STRICT_FREM */
10347
    type0, type0, type0, 
10348
    /* G_STRICT_FMA */
10349
    type0, type0, type0, type0, 
10350
    /* G_STRICT_FSQRT */
10351
    type0, type0, 
10352
    /* G_STRICT_FLDEXP */
10353
    type0, type0, type1, 
10354
    /* G_READ_REGISTER */
10355
    type0, -1, 
10356
    /* G_WRITE_REGISTER */
10357
    -1, type0, 
10358
    /* G_MEMCPY */
10359
    ptype0, ptype1, type2, untyped_imm_0, 
10360
    /* G_MEMCPY_INLINE */
10361
    ptype0, ptype1, type2, 
10362
    /* G_MEMMOVE */
10363
    ptype0, ptype1, type2, untyped_imm_0, 
10364
    /* G_MEMSET */
10365
    ptype0, type1, type2, untyped_imm_0, 
10366
    /* G_BZERO */
10367
    ptype0, type1, untyped_imm_0, 
10368
    /* G_VECREDUCE_SEQ_FADD */
10369
    type0, type1, type2, 
10370
    /* G_VECREDUCE_SEQ_FMUL */
10371
    type0, type1, type2, 
10372
    /* G_VECREDUCE_FADD */
10373
    type0, type1, 
10374
    /* G_VECREDUCE_FMUL */
10375
    type0, type1, 
10376
    /* G_VECREDUCE_FMAX */
10377
    type0, type1, 
10378
    /* G_VECREDUCE_FMIN */
10379
    type0, type1, 
10380
    /* G_VECREDUCE_FMAXIMUM */
10381
    type0, type1, 
10382
    /* G_VECREDUCE_FMINIMUM */
10383
    type0, type1, 
10384
    /* G_VECREDUCE_ADD */
10385
    type0, type1, 
10386
    /* G_VECREDUCE_MUL */
10387
    type0, type1, 
10388
    /* G_VECREDUCE_AND */
10389
    type0, type1, 
10390
    /* G_VECREDUCE_OR */
10391
    type0, type1, 
10392
    /* G_VECREDUCE_XOR */
10393
    type0, type1, 
10394
    /* G_VECREDUCE_SMAX */
10395
    type0, type1, 
10396
    /* G_VECREDUCE_SMIN */
10397
    type0, type1, 
10398
    /* G_VECREDUCE_UMAX */
10399
    type0, type1, 
10400
    /* G_VECREDUCE_UMIN */
10401
    type0, type1, 
10402
    /* G_SBFX */
10403
    type0, type0, type1, type1, 
10404
    /* G_UBFX */
10405
    type0, type0, type1, type1, 
10406
    /* CALL_PARAMS */
10407
    function32_op, 
10408
    /* CALL_PARAMS_S */
10409
    function32_op, 
10410
    /* CALL_RESULTS */
10411
    /* CALL_RESULTS_S */
10412
    /* CATCHRET */
10413
    bb_op, bb_op, 
10414
    /* CATCHRET_S */
10415
    bb_op, bb_op, 
10416
    /* CLEANUPRET */
10417
    /* CLEANUPRET_S */
10418
    /* COMPILER_FENCE */
10419
    /* COMPILER_FENCE_S */
10420
    /* RET_CALL_RESULTS */
10421
    /* RET_CALL_RESULTS_S */
10422
    /* ABS_F32 */
10423
    F32, F32, 
10424
    /* ABS_F32_S */
10425
    /* ABS_F32x4 */
10426
    V128, V128, 
10427
    /* ABS_F32x4_S */
10428
    /* ABS_F64 */
10429
    F64, F64, 
10430
    /* ABS_F64_S */
10431
    /* ABS_F64x2 */
10432
    V128, V128, 
10433
    /* ABS_F64x2_S */
10434
    /* ABS_I16x8 */
10435
    V128, V128, 
10436
    /* ABS_I16x8_S */
10437
    /* ABS_I32x4 */
10438
    V128, V128, 
10439
    /* ABS_I32x4_S */
10440
    /* ABS_I64x2 */
10441
    V128, V128, 
10442
    /* ABS_I64x2_S */
10443
    /* ABS_I8x16 */
10444
    V128, V128, 
10445
    /* ABS_I8x16_S */
10446
    /* ADD_F32 */
10447
    F32, F32, F32, 
10448
    /* ADD_F32_S */
10449
    /* ADD_F32x4 */
10450
    V128, V128, V128, 
10451
    /* ADD_F32x4_S */
10452
    /* ADD_F64 */
10453
    F64, F64, F64, 
10454
    /* ADD_F64_S */
10455
    /* ADD_F64x2 */
10456
    V128, V128, V128, 
10457
    /* ADD_F64x2_S */
10458
    /* ADD_I16x8 */
10459
    V128, V128, V128, 
10460
    /* ADD_I16x8_S */
10461
    /* ADD_I32 */
10462
    I32, I32, I32, 
10463
    /* ADD_I32_S */
10464
    /* ADD_I32x4 */
10465
    V128, V128, V128, 
10466
    /* ADD_I32x4_S */
10467
    /* ADD_I64 */
10468
    I64, I64, I64, 
10469
    /* ADD_I64_S */
10470
    /* ADD_I64x2 */
10471
    V128, V128, V128, 
10472
    /* ADD_I64x2_S */
10473
    /* ADD_I8x16 */
10474
    V128, V128, V128, 
10475
    /* ADD_I8x16_S */
10476
    /* ADD_SAT_S_I16x8 */
10477
    V128, V128, V128, 
10478
    /* ADD_SAT_S_I16x8_S */
10479
    /* ADD_SAT_S_I8x16 */
10480
    V128, V128, V128, 
10481
    /* ADD_SAT_S_I8x16_S */
10482
    /* ADD_SAT_U_I16x8 */
10483
    V128, V128, V128, 
10484
    /* ADD_SAT_U_I16x8_S */
10485
    /* ADD_SAT_U_I8x16 */
10486
    V128, V128, V128, 
10487
    /* ADD_SAT_U_I8x16_S */
10488
    /* ADJCALLSTACKDOWN */
10489
    i32imm, i32imm, 
10490
    /* ADJCALLSTACKDOWN_S */
10491
    i32imm, i32imm, 
10492
    /* ADJCALLSTACKUP */
10493
    i32imm, i32imm, 
10494
    /* ADJCALLSTACKUP_S */
10495
    i32imm, i32imm, 
10496
    /* ALLTRUE_I16x8 */
10497
    I32, V128, 
10498
    /* ALLTRUE_I16x8_S */
10499
    /* ALLTRUE_I32x4 */
10500
    I32, V128, 
10501
    /* ALLTRUE_I32x4_S */
10502
    /* ALLTRUE_I64x2 */
10503
    I32, V128, 
10504
    /* ALLTRUE_I64x2_S */
10505
    /* ALLTRUE_I8x16 */
10506
    I32, V128, 
10507
    /* ALLTRUE_I8x16_S */
10508
    /* AND */
10509
    V128, V128, V128, 
10510
    /* ANDNOT */
10511
    V128, V128, V128, 
10512
    /* ANDNOT_S */
10513
    /* AND_I32 */
10514
    I32, I32, I32, 
10515
    /* AND_I32_S */
10516
    /* AND_I64 */
10517
    I64, I64, I64, 
10518
    /* AND_I64_S */
10519
    /* AND_S */
10520
    /* ANYTRUE */
10521
    I32, V128, 
10522
    /* ANYTRUE_S */
10523
    /* ARGUMENT_externref */
10524
    EXTERNREF, i32imm, 
10525
    /* ARGUMENT_externref_S */
10526
    i32imm, 
10527
    /* ARGUMENT_f32 */
10528
    F32, i32imm, 
10529
    /* ARGUMENT_f32_S */
10530
    i32imm, 
10531
    /* ARGUMENT_f64 */
10532
    F64, i32imm, 
10533
    /* ARGUMENT_f64_S */
10534
    i32imm, 
10535
    /* ARGUMENT_funcref */
10536
    FUNCREF, i32imm, 
10537
    /* ARGUMENT_funcref_S */
10538
    i32imm, 
10539
    /* ARGUMENT_i32 */
10540
    I32, i32imm, 
10541
    /* ARGUMENT_i32_S */
10542
    i32imm, 
10543
    /* ARGUMENT_i64 */
10544
    I64, i32imm, 
10545
    /* ARGUMENT_i64_S */
10546
    i32imm, 
10547
    /* ARGUMENT_v16i8 */
10548
    V128, i32imm, 
10549
    /* ARGUMENT_v16i8_S */
10550
    i32imm, 
10551
    /* ARGUMENT_v2f64 */
10552
    V128, i32imm, 
10553
    /* ARGUMENT_v2f64_S */
10554
    i32imm, 
10555
    /* ARGUMENT_v2i64 */
10556
    V128, i32imm, 
10557
    /* ARGUMENT_v2i64_S */
10558
    i32imm, 
10559
    /* ARGUMENT_v4f32 */
10560
    V128, i32imm, 
10561
    /* ARGUMENT_v4f32_S */
10562
    i32imm, 
10563
    /* ARGUMENT_v4i32 */
10564
    V128, i32imm, 
10565
    /* ARGUMENT_v4i32_S */
10566
    i32imm, 
10567
    /* ARGUMENT_v8i16 */
10568
    V128, i32imm, 
10569
    /* ARGUMENT_v8i16_S */
10570
    i32imm, 
10571
    /* ATOMIC_FENCE */
10572
    i8imm, 
10573
    /* ATOMIC_FENCE_S */
10574
    i8imm, 
10575
    /* ATOMIC_LOAD16_U_I32_A32 */
10576
    I32, P2Align, offset32_op, I32, 
10577
    /* ATOMIC_LOAD16_U_I32_A32_S */
10578
    P2Align, offset32_op, 
10579
    /* ATOMIC_LOAD16_U_I32_A64 */
10580
    I32, P2Align, offset64_op, I64, 
10581
    /* ATOMIC_LOAD16_U_I32_A64_S */
10582
    P2Align, offset64_op, 
10583
    /* ATOMIC_LOAD16_U_I64_A32 */
10584
    I64, P2Align, offset32_op, I32, 
10585
    /* ATOMIC_LOAD16_U_I64_A32_S */
10586
    P2Align, offset32_op, 
10587
    /* ATOMIC_LOAD16_U_I64_A64 */
10588
    I64, P2Align, offset64_op, I64, 
10589
    /* ATOMIC_LOAD16_U_I64_A64_S */
10590
    P2Align, offset64_op, 
10591
    /* ATOMIC_LOAD32_U_I64_A32 */
10592
    I64, P2Align, offset32_op, I32, 
10593
    /* ATOMIC_LOAD32_U_I64_A32_S */
10594
    P2Align, offset32_op, 
10595
    /* ATOMIC_LOAD32_U_I64_A64 */
10596
    I64, P2Align, offset64_op, I64, 
10597
    /* ATOMIC_LOAD32_U_I64_A64_S */
10598
    P2Align, offset64_op, 
10599
    /* ATOMIC_LOAD8_U_I32_A32 */
10600
    I32, P2Align, offset32_op, I32, 
10601
    /* ATOMIC_LOAD8_U_I32_A32_S */
10602
    P2Align, offset32_op, 
10603
    /* ATOMIC_LOAD8_U_I32_A64 */
10604
    I32, P2Align, offset64_op, I64, 
10605
    /* ATOMIC_LOAD8_U_I32_A64_S */
10606
    P2Align, offset64_op, 
10607
    /* ATOMIC_LOAD8_U_I64_A32 */
10608
    I64, P2Align, offset32_op, I32, 
10609
    /* ATOMIC_LOAD8_U_I64_A32_S */
10610
    P2Align, offset32_op, 
10611
    /* ATOMIC_LOAD8_U_I64_A64 */
10612
    I64, P2Align, offset64_op, I64, 
10613
    /* ATOMIC_LOAD8_U_I64_A64_S */
10614
    P2Align, offset64_op, 
10615
    /* ATOMIC_LOAD_I32_A32 */
10616
    I32, P2Align, offset32_op, I32, 
10617
    /* ATOMIC_LOAD_I32_A32_S */
10618
    P2Align, offset32_op, 
10619
    /* ATOMIC_LOAD_I32_A64 */
10620
    I32, P2Align, offset64_op, I64, 
10621
    /* ATOMIC_LOAD_I32_A64_S */
10622
    P2Align, offset64_op, 
10623
    /* ATOMIC_LOAD_I64_A32 */
10624
    I64, P2Align, offset32_op, I32, 
10625
    /* ATOMIC_LOAD_I64_A32_S */
10626
    P2Align, offset32_op, 
10627
    /* ATOMIC_LOAD_I64_A64 */
10628
    I64, P2Align, offset64_op, I64, 
10629
    /* ATOMIC_LOAD_I64_A64_S */
10630
    P2Align, offset64_op, 
10631
    /* ATOMIC_RMW16_U_ADD_I32_A32 */
10632
    I32, P2Align, offset32_op, I32, I32, 
10633
    /* ATOMIC_RMW16_U_ADD_I32_A32_S */
10634
    P2Align, offset32_op, 
10635
    /* ATOMIC_RMW16_U_ADD_I32_A64 */
10636
    I32, P2Align, offset64_op, I64, I32, 
10637
    /* ATOMIC_RMW16_U_ADD_I32_A64_S */
10638
    P2Align, offset64_op, 
10639
    /* ATOMIC_RMW16_U_ADD_I64_A32 */
10640
    I64, P2Align, offset32_op, I32, I64, 
10641
    /* ATOMIC_RMW16_U_ADD_I64_A32_S */
10642
    P2Align, offset32_op, 
10643
    /* ATOMIC_RMW16_U_ADD_I64_A64 */
10644
    I64, P2Align, offset64_op, I64, I64, 
10645
    /* ATOMIC_RMW16_U_ADD_I64_A64_S */
10646
    P2Align, offset64_op, 
10647
    /* ATOMIC_RMW16_U_AND_I32_A32 */
10648
    I32, P2Align, offset32_op, I32, I32, 
10649
    /* ATOMIC_RMW16_U_AND_I32_A32_S */
10650
    P2Align, offset32_op, 
10651
    /* ATOMIC_RMW16_U_AND_I32_A64 */
10652
    I32, P2Align, offset64_op, I64, I32, 
10653
    /* ATOMIC_RMW16_U_AND_I32_A64_S */
10654
    P2Align, offset64_op, 
10655
    /* ATOMIC_RMW16_U_AND_I64_A32 */
10656
    I64, P2Align, offset32_op, I32, I64, 
10657
    /* ATOMIC_RMW16_U_AND_I64_A32_S */
10658
    P2Align, offset32_op, 
10659
    /* ATOMIC_RMW16_U_AND_I64_A64 */
10660
    I64, P2Align, offset64_op, I64, I64, 
10661
    /* ATOMIC_RMW16_U_AND_I64_A64_S */
10662
    P2Align, offset64_op, 
10663
    /* ATOMIC_RMW16_U_CMPXCHG_I32_A32 */
10664
    I32, P2Align, offset32_op, I32, I32, I32, 
10665
    /* ATOMIC_RMW16_U_CMPXCHG_I32_A32_S */
10666
    P2Align, offset32_op, 
10667
    /* ATOMIC_RMW16_U_CMPXCHG_I32_A64 */
10668
    I32, P2Align, offset64_op, I64, I32, I32, 
10669
    /* ATOMIC_RMW16_U_CMPXCHG_I32_A64_S */
10670
    P2Align, offset64_op, 
10671
    /* ATOMIC_RMW16_U_CMPXCHG_I64_A32 */
10672
    I64, P2Align, offset32_op, I32, I64, I64, 
10673
    /* ATOMIC_RMW16_U_CMPXCHG_I64_A32_S */
10674
    P2Align, offset32_op, 
10675
    /* ATOMIC_RMW16_U_CMPXCHG_I64_A64 */
10676
    I64, P2Align, offset64_op, I64, I64, I64, 
10677
    /* ATOMIC_RMW16_U_CMPXCHG_I64_A64_S */
10678
    P2Align, offset64_op, 
10679
    /* ATOMIC_RMW16_U_OR_I32_A32 */
10680
    I32, P2Align, offset32_op, I32, I32, 
10681
    /* ATOMIC_RMW16_U_OR_I32_A32_S */
10682
    P2Align, offset32_op, 
10683
    /* ATOMIC_RMW16_U_OR_I32_A64 */
10684
    I32, P2Align, offset64_op, I64, I32, 
10685
    /* ATOMIC_RMW16_U_OR_I32_A64_S */
10686
    P2Align, offset64_op, 
10687
    /* ATOMIC_RMW16_U_OR_I64_A32 */
10688
    I64, P2Align, offset32_op, I32, I64, 
10689
    /* ATOMIC_RMW16_U_OR_I64_A32_S */
10690
    P2Align, offset32_op, 
10691
    /* ATOMIC_RMW16_U_OR_I64_A64 */
10692
    I64, P2Align, offset64_op, I64, I64, 
10693
    /* ATOMIC_RMW16_U_OR_I64_A64_S */
10694
    P2Align, offset64_op, 
10695
    /* ATOMIC_RMW16_U_SUB_I32_A32 */
10696
    I32, P2Align, offset32_op, I32, I32, 
10697
    /* ATOMIC_RMW16_U_SUB_I32_A32_S */
10698
    P2Align, offset32_op, 
10699
    /* ATOMIC_RMW16_U_SUB_I32_A64 */
10700
    I32, P2Align, offset64_op, I64, I32, 
10701
    /* ATOMIC_RMW16_U_SUB_I32_A64_S */
10702
    P2Align, offset64_op, 
10703
    /* ATOMIC_RMW16_U_SUB_I64_A32 */
10704
    I64, P2Align, offset32_op, I32, I64, 
10705
    /* ATOMIC_RMW16_U_SUB_I64_A32_S */
10706
    P2Align, offset32_op, 
10707
    /* ATOMIC_RMW16_U_SUB_I64_A64 */
10708
    I64, P2Align, offset64_op, I64, I64, 
10709
    /* ATOMIC_RMW16_U_SUB_I64_A64_S */
10710
    P2Align, offset64_op, 
10711
    /* ATOMIC_RMW16_U_XCHG_I32_A32 */
10712
    I32, P2Align, offset32_op, I32, I32, 
10713
    /* ATOMIC_RMW16_U_XCHG_I32_A32_S */
10714
    P2Align, offset32_op, 
10715
    /* ATOMIC_RMW16_U_XCHG_I32_A64 */
10716
    I32, P2Align, offset64_op, I64, I32, 
10717
    /* ATOMIC_RMW16_U_XCHG_I32_A64_S */
10718
    P2Align, offset64_op, 
10719
    /* ATOMIC_RMW16_U_XCHG_I64_A32 */
10720
    I64, P2Align, offset32_op, I32, I64, 
10721
    /* ATOMIC_RMW16_U_XCHG_I64_A32_S */
10722
    P2Align, offset32_op, 
10723
    /* ATOMIC_RMW16_U_XCHG_I64_A64 */
10724
    I64, P2Align, offset64_op, I64, I64, 
10725
    /* ATOMIC_RMW16_U_XCHG_I64_A64_S */
10726
    P2Align, offset64_op, 
10727
    /* ATOMIC_RMW16_U_XOR_I32_A32 */
10728
    I32, P2Align, offset32_op, I32, I32, 
10729
    /* ATOMIC_RMW16_U_XOR_I32_A32_S */
10730
    P2Align, offset32_op, 
10731
    /* ATOMIC_RMW16_U_XOR_I32_A64 */
10732
    I32, P2Align, offset64_op, I64, I32, 
10733
    /* ATOMIC_RMW16_U_XOR_I32_A64_S */
10734
    P2Align, offset64_op, 
10735
    /* ATOMIC_RMW16_U_XOR_I64_A32 */
10736
    I64, P2Align, offset32_op, I32, I64, 
10737
    /* ATOMIC_RMW16_U_XOR_I64_A32_S */
10738
    P2Align, offset32_op, 
10739
    /* ATOMIC_RMW16_U_XOR_I64_A64 */
10740
    I64, P2Align, offset64_op, I64, I64, 
10741
    /* ATOMIC_RMW16_U_XOR_I64_A64_S */
10742
    P2Align, offset64_op, 
10743
    /* ATOMIC_RMW32_U_ADD_I64_A32 */
10744
    I64, P2Align, offset32_op, I32, I64, 
10745
    /* ATOMIC_RMW32_U_ADD_I64_A32_S */
10746
    P2Align, offset32_op, 
10747
    /* ATOMIC_RMW32_U_ADD_I64_A64 */
10748
    I64, P2Align, offset64_op, I64, I64, 
10749
    /* ATOMIC_RMW32_U_ADD_I64_A64_S */
10750
    P2Align, offset64_op, 
10751
    /* ATOMIC_RMW32_U_AND_I64_A32 */
10752
    I64, P2Align, offset32_op, I32, I64, 
10753
    /* ATOMIC_RMW32_U_AND_I64_A32_S */
10754
    P2Align, offset32_op, 
10755
    /* ATOMIC_RMW32_U_AND_I64_A64 */
10756
    I64, P2Align, offset64_op, I64, I64, 
10757
    /* ATOMIC_RMW32_U_AND_I64_A64_S */
10758
    P2Align, offset64_op, 
10759
    /* ATOMIC_RMW32_U_CMPXCHG_I64_A32 */
10760
    I64, P2Align, offset32_op, I32, I64, I64, 
10761
    /* ATOMIC_RMW32_U_CMPXCHG_I64_A32_S */
10762
    P2Align, offset32_op, 
10763
    /* ATOMIC_RMW32_U_CMPXCHG_I64_A64 */
10764
    I64, P2Align, offset64_op, I64, I64, I64, 
10765
    /* ATOMIC_RMW32_U_CMPXCHG_I64_A64_S */
10766
    P2Align, offset64_op, 
10767
    /* ATOMIC_RMW32_U_OR_I64_A32 */
10768
    I64, P2Align, offset32_op, I32, I64, 
10769
    /* ATOMIC_RMW32_U_OR_I64_A32_S */
10770
    P2Align, offset32_op, 
10771
    /* ATOMIC_RMW32_U_OR_I64_A64 */
10772
    I64, P2Align, offset64_op, I64, I64, 
10773
    /* ATOMIC_RMW32_U_OR_I64_A64_S */
10774
    P2Align, offset64_op, 
10775
    /* ATOMIC_RMW32_U_SUB_I64_A32 */
10776
    I64, P2Align, offset32_op, I32, I64, 
10777
    /* ATOMIC_RMW32_U_SUB_I64_A32_S */
10778
    P2Align, offset32_op, 
10779
    /* ATOMIC_RMW32_U_SUB_I64_A64 */
10780
    I64, P2Align, offset64_op, I64, I64, 
10781
    /* ATOMIC_RMW32_U_SUB_I64_A64_S */
10782
    P2Align, offset64_op, 
10783
    /* ATOMIC_RMW32_U_XCHG_I64_A32 */
10784
    I64, P2Align, offset32_op, I32, I64, 
10785
    /* ATOMIC_RMW32_U_XCHG_I64_A32_S */
10786
    P2Align, offset32_op, 
10787
    /* ATOMIC_RMW32_U_XCHG_I64_A64 */
10788
    I64, P2Align, offset64_op, I64, I64, 
10789
    /* ATOMIC_RMW32_U_XCHG_I64_A64_S */
10790
    P2Align, offset64_op, 
10791
    /* ATOMIC_RMW32_U_XOR_I64_A32 */
10792
    I64, P2Align, offset32_op, I32, I64, 
10793
    /* ATOMIC_RMW32_U_XOR_I64_A32_S */
10794
    P2Align, offset32_op, 
10795
    /* ATOMIC_RMW32_U_XOR_I64_A64 */
10796
    I64, P2Align, offset64_op, I64, I64, 
10797
    /* ATOMIC_RMW32_U_XOR_I64_A64_S */
10798
    P2Align, offset64_op, 
10799
    /* ATOMIC_RMW8_U_ADD_I32_A32 */
10800
    I32, P2Align, offset32_op, I32, I32, 
10801
    /* ATOMIC_RMW8_U_ADD_I32_A32_S */
10802
    P2Align, offset32_op, 
10803
    /* ATOMIC_RMW8_U_ADD_I32_A64 */
10804
    I32, P2Align, offset64_op, I64, I32, 
10805
    /* ATOMIC_RMW8_U_ADD_I32_A64_S */
10806
    P2Align, offset64_op, 
10807
    /* ATOMIC_RMW8_U_ADD_I64_A32 */
10808
    I64, P2Align, offset32_op, I32, I64, 
10809
    /* ATOMIC_RMW8_U_ADD_I64_A32_S */
10810
    P2Align, offset32_op, 
10811
    /* ATOMIC_RMW8_U_ADD_I64_A64 */
10812
    I64, P2Align, offset64_op, I64, I64, 
10813
    /* ATOMIC_RMW8_U_ADD_I64_A64_S */
10814
    P2Align, offset64_op, 
10815
    /* ATOMIC_RMW8_U_AND_I32_A32 */
10816
    I32, P2Align, offset32_op, I32, I32, 
10817
    /* ATOMIC_RMW8_U_AND_I32_A32_S */
10818
    P2Align, offset32_op, 
10819
    /* ATOMIC_RMW8_U_AND_I32_A64 */
10820
    I32, P2Align, offset64_op, I64, I32, 
10821
    /* ATOMIC_RMW8_U_AND_I32_A64_S */
10822
    P2Align, offset64_op, 
10823
    /* ATOMIC_RMW8_U_AND_I64_A32 */
10824
    I64, P2Align, offset32_op, I32, I64, 
10825
    /* ATOMIC_RMW8_U_AND_I64_A32_S */
10826
    P2Align, offset32_op, 
10827
    /* ATOMIC_RMW8_U_AND_I64_A64 */
10828
    I64, P2Align, offset64_op, I64, I64, 
10829
    /* ATOMIC_RMW8_U_AND_I64_A64_S */
10830
    P2Align, offset64_op, 
10831
    /* ATOMIC_RMW8_U_CMPXCHG_I32_A32 */
10832
    I32, P2Align, offset32_op, I32, I32, I32, 
10833
    /* ATOMIC_RMW8_U_CMPXCHG_I32_A32_S */
10834
    P2Align, offset32_op, 
10835
    /* ATOMIC_RMW8_U_CMPXCHG_I32_A64 */
10836
    I32, P2Align, offset64_op, I64, I32, I32, 
10837
    /* ATOMIC_RMW8_U_CMPXCHG_I32_A64_S */
10838
    P2Align, offset64_op, 
10839
    /* ATOMIC_RMW8_U_CMPXCHG_I64_A32 */
10840
    I64, P2Align, offset32_op, I32, I64, I64, 
10841
    /* ATOMIC_RMW8_U_CMPXCHG_I64_A32_S */
10842
    P2Align, offset32_op, 
10843
    /* ATOMIC_RMW8_U_CMPXCHG_I64_A64 */
10844
    I64, P2Align, offset64_op, I64, I64, I64, 
10845
    /* ATOMIC_RMW8_U_CMPXCHG_I64_A64_S */
10846
    P2Align, offset64_op, 
10847
    /* ATOMIC_RMW8_U_OR_I32_A32 */
10848
    I32, P2Align, offset32_op, I32, I32, 
10849
    /* ATOMIC_RMW8_U_OR_I32_A32_S */
10850
    P2Align, offset32_op, 
10851
    /* ATOMIC_RMW8_U_OR_I32_A64 */
10852
    I32, P2Align, offset64_op, I64, I32, 
10853
    /* ATOMIC_RMW8_U_OR_I32_A64_S */
10854
    P2Align, offset64_op, 
10855
    /* ATOMIC_RMW8_U_OR_I64_A32 */
10856
    I64, P2Align, offset32_op, I32, I64, 
10857
    /* ATOMIC_RMW8_U_OR_I64_A32_S */
10858
    P2Align, offset32_op, 
10859
    /* ATOMIC_RMW8_U_OR_I64_A64 */
10860
    I64, P2Align, offset64_op, I64, I64, 
10861
    /* ATOMIC_RMW8_U_OR_I64_A64_S */
10862
    P2Align, offset64_op, 
10863
    /* ATOMIC_RMW8_U_SUB_I32_A32 */
10864
    I32, P2Align, offset32_op, I32, I32, 
10865
    /* ATOMIC_RMW8_U_SUB_I32_A32_S */
10866
    P2Align, offset32_op, 
10867
    /* ATOMIC_RMW8_U_SUB_I32_A64 */
10868
    I32, P2Align, offset64_op, I64, I32, 
10869
    /* ATOMIC_RMW8_U_SUB_I32_A64_S */
10870
    P2Align, offset64_op, 
10871
    /* ATOMIC_RMW8_U_SUB_I64_A32 */
10872
    I64, P2Align, offset32_op, I32, I64, 
10873
    /* ATOMIC_RMW8_U_SUB_I64_A32_S */
10874
    P2Align, offset32_op, 
10875
    /* ATOMIC_RMW8_U_SUB_I64_A64 */
10876
    I64, P2Align, offset64_op, I64, I64, 
10877
    /* ATOMIC_RMW8_U_SUB_I64_A64_S */
10878
    P2Align, offset64_op, 
10879
    /* ATOMIC_RMW8_U_XCHG_I32_A32 */
10880
    I32, P2Align, offset32_op, I32, I32, 
10881
    /* ATOMIC_RMW8_U_XCHG_I32_A32_S */
10882
    P2Align, offset32_op, 
10883
    /* ATOMIC_RMW8_U_XCHG_I32_A64 */
10884
    I32, P2Align, offset64_op, I64, I32, 
10885
    /* ATOMIC_RMW8_U_XCHG_I32_A64_S */
10886
    P2Align, offset64_op, 
10887
    /* ATOMIC_RMW8_U_XCHG_I64_A32 */
10888
    I64, P2Align, offset32_op, I32, I64, 
10889
    /* ATOMIC_RMW8_U_XCHG_I64_A32_S */
10890
    P2Align, offset32_op, 
10891
    /* ATOMIC_RMW8_U_XCHG_I64_A64 */
10892
    I64, P2Align, offset64_op, I64, I64, 
10893
    /* ATOMIC_RMW8_U_XCHG_I64_A64_S */
10894
    P2Align, offset64_op, 
10895
    /* ATOMIC_RMW8_U_XOR_I32_A32 */
10896
    I32, P2Align, offset32_op, I32, I32, 
10897
    /* ATOMIC_RMW8_U_XOR_I32_A32_S */
10898
    P2Align, offset32_op, 
10899
    /* ATOMIC_RMW8_U_XOR_I32_A64 */
10900
    I32, P2Align, offset64_op, I64, I32, 
10901
    /* ATOMIC_RMW8_U_XOR_I32_A64_S */
10902
    P2Align, offset64_op, 
10903
    /* ATOMIC_RMW8_U_XOR_I64_A32 */
10904
    I64, P2Align, offset32_op, I32, I64, 
10905
    /* ATOMIC_RMW8_U_XOR_I64_A32_S */
10906
    P2Align, offset32_op, 
10907
    /* ATOMIC_RMW8_U_XOR_I64_A64 */
10908
    I64, P2Align, offset64_op, I64, I64, 
10909
    /* ATOMIC_RMW8_U_XOR_I64_A64_S */
10910
    P2Align, offset64_op, 
10911
    /* ATOMIC_RMW_ADD_I32_A32 */
10912
    I32, P2Align, offset32_op, I32, I32, 
10913
    /* ATOMIC_RMW_ADD_I32_A32_S */
10914
    P2Align, offset32_op, 
10915
    /* ATOMIC_RMW_ADD_I32_A64 */
10916
    I32, P2Align, offset64_op, I64, I32, 
10917
    /* ATOMIC_RMW_ADD_I32_A64_S */
10918
    P2Align, offset64_op, 
10919
    /* ATOMIC_RMW_ADD_I64_A32 */
10920
    I64, P2Align, offset32_op, I32, I64, 
10921
    /* ATOMIC_RMW_ADD_I64_A32_S */
10922
    P2Align, offset32_op, 
10923
    /* ATOMIC_RMW_ADD_I64_A64 */
10924
    I64, P2Align, offset64_op, I64, I64, 
10925
    /* ATOMIC_RMW_ADD_I64_A64_S */
10926
    P2Align, offset64_op, 
10927
    /* ATOMIC_RMW_AND_I32_A32 */
10928
    I32, P2Align, offset32_op, I32, I32, 
10929
    /* ATOMIC_RMW_AND_I32_A32_S */
10930
    P2Align, offset32_op, 
10931
    /* ATOMIC_RMW_AND_I32_A64 */
10932
    I32, P2Align, offset64_op, I64, I32, 
10933
    /* ATOMIC_RMW_AND_I32_A64_S */
10934
    P2Align, offset64_op, 
10935
    /* ATOMIC_RMW_AND_I64_A32 */
10936
    I64, P2Align, offset32_op, I32, I64, 
10937
    /* ATOMIC_RMW_AND_I64_A32_S */
10938
    P2Align, offset32_op, 
10939
    /* ATOMIC_RMW_AND_I64_A64 */
10940
    I64, P2Align, offset64_op, I64, I64, 
10941
    /* ATOMIC_RMW_AND_I64_A64_S */
10942
    P2Align, offset64_op, 
10943
    /* ATOMIC_RMW_CMPXCHG_I32_A32 */
10944
    I32, P2Align, offset32_op, I32, I32, I32, 
10945
    /* ATOMIC_RMW_CMPXCHG_I32_A32_S */
10946
    P2Align, offset32_op, 
10947
    /* ATOMIC_RMW_CMPXCHG_I32_A64 */
10948
    I32, P2Align, offset64_op, I64, I32, I32, 
10949
    /* ATOMIC_RMW_CMPXCHG_I32_A64_S */
10950
    P2Align, offset64_op, 
10951
    /* ATOMIC_RMW_CMPXCHG_I64_A32 */
10952
    I64, P2Align, offset32_op, I32, I64, I64, 
10953
    /* ATOMIC_RMW_CMPXCHG_I64_A32_S */
10954
    P2Align, offset32_op, 
10955
    /* ATOMIC_RMW_CMPXCHG_I64_A64 */
10956
    I64, P2Align, offset64_op, I64, I64, I64, 
10957
    /* ATOMIC_RMW_CMPXCHG_I64_A64_S */
10958
    P2Align, offset64_op, 
10959
    /* ATOMIC_RMW_OR_I32_A32 */
10960
    I32, P2Align, offset32_op, I32, I32, 
10961
    /* ATOMIC_RMW_OR_I32_A32_S */
10962
    P2Align, offset32_op, 
10963
    /* ATOMIC_RMW_OR_I32_A64 */
10964
    I32, P2Align, offset64_op, I64, I32, 
10965
    /* ATOMIC_RMW_OR_I32_A64_S */
10966
    P2Align, offset64_op, 
10967
    /* ATOMIC_RMW_OR_I64_A32 */
10968
    I64, P2Align, offset32_op, I32, I64, 
10969
    /* ATOMIC_RMW_OR_I64_A32_S */
10970
    P2Align, offset32_op, 
10971
    /* ATOMIC_RMW_OR_I64_A64 */
10972
    I64, P2Align, offset64_op, I64, I64, 
10973
    /* ATOMIC_RMW_OR_I64_A64_S */
10974
    P2Align, offset64_op, 
10975
    /* ATOMIC_RMW_SUB_I32_A32 */
10976
    I32, P2Align, offset32_op, I32, I32, 
10977
    /* ATOMIC_RMW_SUB_I32_A32_S */
10978
    P2Align, offset32_op, 
10979
    /* ATOMIC_RMW_SUB_I32_A64 */
10980
    I32, P2Align, offset64_op, I64, I32, 
10981
    /* ATOMIC_RMW_SUB_I32_A64_S */
10982
    P2Align, offset64_op, 
10983
    /* ATOMIC_RMW_SUB_I64_A32 */
10984
    I64, P2Align, offset32_op, I32, I64, 
10985
    /* ATOMIC_RMW_SUB_I64_A32_S */
10986
    P2Align, offset32_op, 
10987
    /* ATOMIC_RMW_SUB_I64_A64 */
10988
    I64, P2Align, offset64_op, I64, I64, 
10989
    /* ATOMIC_RMW_SUB_I64_A64_S */
10990
    P2Align, offset64_op, 
10991
    /* ATOMIC_RMW_XCHG_I32_A32 */
10992
    I32, P2Align, offset32_op, I32, I32, 
10993
    /* ATOMIC_RMW_XCHG_I32_A32_S */
10994
    P2Align, offset32_op, 
10995
    /* ATOMIC_RMW_XCHG_I32_A64 */
10996
    I32, P2Align, offset64_op, I64, I32, 
10997
    /* ATOMIC_RMW_XCHG_I32_A64_S */
10998
    P2Align, offset64_op, 
10999
    /* ATOMIC_RMW_XCHG_I64_A32 */
11000
    I64, P2Align, offset32_op, I32, I64, 
11001
    /* ATOMIC_RMW_XCHG_I64_A32_S */
11002
    P2Align, offset32_op, 
11003
    /* ATOMIC_RMW_XCHG_I64_A64 */
11004
    I64, P2Align, offset64_op, I64, I64, 
11005
    /* ATOMIC_RMW_XCHG_I64_A64_S */
11006
    P2Align, offset64_op, 
11007
    /* ATOMIC_RMW_XOR_I32_A32 */
11008
    I32, P2Align, offset32_op, I32, I32, 
11009
    /* ATOMIC_RMW_XOR_I32_A32_S */
11010
    P2Align, offset32_op, 
11011
    /* ATOMIC_RMW_XOR_I32_A64 */
11012
    I32, P2Align, offset64_op, I64, I32, 
11013
    /* ATOMIC_RMW_XOR_I32_A64_S */
11014
    P2Align, offset64_op, 
11015
    /* ATOMIC_RMW_XOR_I64_A32 */
11016
    I64, P2Align, offset32_op, I32, I64, 
11017
    /* ATOMIC_RMW_XOR_I64_A32_S */
11018
    P2Align, offset32_op, 
11019
    /* ATOMIC_RMW_XOR_I64_A64 */
11020
    I64, P2Align, offset64_op, I64, I64, 
11021
    /* ATOMIC_RMW_XOR_I64_A64_S */
11022
    P2Align, offset64_op, 
11023
    /* ATOMIC_STORE16_I32_A32 */
11024
    P2Align, offset32_op, I32, I32, 
11025
    /* ATOMIC_STORE16_I32_A32_S */
11026
    P2Align, offset32_op, 
11027
    /* ATOMIC_STORE16_I32_A64 */
11028
    P2Align, offset64_op, I64, I32, 
11029
    /* ATOMIC_STORE16_I32_A64_S */
11030
    P2Align, offset64_op, 
11031
    /* ATOMIC_STORE16_I64_A32 */
11032
    P2Align, offset32_op, I32, I64, 
11033
    /* ATOMIC_STORE16_I64_A32_S */
11034
    P2Align, offset32_op, 
11035
    /* ATOMIC_STORE16_I64_A64 */
11036
    P2Align, offset64_op, I64, I64, 
11037
    /* ATOMIC_STORE16_I64_A64_S */
11038
    P2Align, offset64_op, 
11039
    /* ATOMIC_STORE32_I64_A32 */
11040
    P2Align, offset32_op, I32, I64, 
11041
    /* ATOMIC_STORE32_I64_A32_S */
11042
    P2Align, offset32_op, 
11043
    /* ATOMIC_STORE32_I64_A64 */
11044
    P2Align, offset64_op, I64, I64, 
11045
    /* ATOMIC_STORE32_I64_A64_S */
11046
    P2Align, offset64_op, 
11047
    /* ATOMIC_STORE8_I32_A32 */
11048
    P2Align, offset32_op, I32, I32, 
11049
    /* ATOMIC_STORE8_I32_A32_S */
11050
    P2Align, offset32_op, 
11051
    /* ATOMIC_STORE8_I32_A64 */
11052
    P2Align, offset64_op, I64, I32, 
11053
    /* ATOMIC_STORE8_I32_A64_S */
11054
    P2Align, offset64_op, 
11055
    /* ATOMIC_STORE8_I64_A32 */
11056
    P2Align, offset32_op, I32, I64, 
11057
    /* ATOMIC_STORE8_I64_A32_S */
11058
    P2Align, offset32_op, 
11059
    /* ATOMIC_STORE8_I64_A64 */
11060
    P2Align, offset64_op, I64, I64, 
11061
    /* ATOMIC_STORE8_I64_A64_S */
11062
    P2Align, offset64_op, 
11063
    /* ATOMIC_STORE_I32_A32 */
11064
    P2Align, offset32_op, I32, I32, 
11065
    /* ATOMIC_STORE_I32_A32_S */
11066
    P2Align, offset32_op, 
11067
    /* ATOMIC_STORE_I32_A64 */
11068
    P2Align, offset64_op, I64, I32, 
11069
    /* ATOMIC_STORE_I32_A64_S */
11070
    P2Align, offset64_op, 
11071
    /* ATOMIC_STORE_I64_A32 */
11072
    P2Align, offset32_op, I32, I64, 
11073
    /* ATOMIC_STORE_I64_A32_S */
11074
    P2Align, offset32_op, 
11075
    /* ATOMIC_STORE_I64_A64 */
11076
    P2Align, offset64_op, I64, I64, 
11077
    /* ATOMIC_STORE_I64_A64_S */
11078
    P2Align, offset64_op, 
11079
    /* AVGR_U_I16x8 */
11080
    V128, V128, V128, 
11081
    /* AVGR_U_I16x8_S */
11082
    /* AVGR_U_I8x16 */
11083
    V128, V128, V128, 
11084
    /* AVGR_U_I8x16_S */
11085
    /* BITMASK_I16x8 */
11086
    I32, V128, 
11087
    /* BITMASK_I16x8_S */
11088
    /* BITMASK_I32x4 */
11089
    I32, V128, 
11090
    /* BITMASK_I32x4_S */
11091
    /* BITMASK_I64x2 */
11092
    I32, V128, 
11093
    /* BITMASK_I64x2_S */
11094
    /* BITMASK_I8x16 */
11095
    I32, V128, 
11096
    /* BITMASK_I8x16_S */
11097
    /* BITSELECT */
11098
    V128, V128, V128, V128, 
11099
    /* BITSELECT_S */
11100
    /* BLOCK */
11101
    Signature, 
11102
    /* BLOCK_S */
11103
    Signature, 
11104
    /* BR */
11105
    bb_op, 
11106
    /* BR_IF */
11107
    bb_op, I32, 
11108
    /* BR_IF_S */
11109
    bb_op, 
11110
    /* BR_S */
11111
    bb_op, 
11112
    /* BR_TABLE_I32 */
11113
    I32, 
11114
    /* BR_TABLE_I32_S */
11115
    brlist, 
11116
    /* BR_TABLE_I64 */
11117
    I64, 
11118
    /* BR_TABLE_I64_S */
11119
    brlist, 
11120
    /* BR_UNLESS */
11121
    bb_op, I32, 
11122
    /* BR_UNLESS_S */
11123
    bb_op, 
11124
    /* CALL */
11125
    function32_op, 
11126
    /* CALL_INDIRECT */
11127
    TypeIndex, table32_op, 
11128
    /* CALL_INDIRECT_S */
11129
    TypeIndex, table32_op, 
11130
    /* CALL_S */
11131
    function32_op, 
11132
    /* CATCH */
11133
    tag_op, 
11134
    /* CATCH_ALL */
11135
    /* CATCH_ALL_S */
11136
    /* CATCH_S */
11137
    tag_op, 
11138
    /* CEIL_F32 */
11139
    F32, F32, 
11140
    /* CEIL_F32_S */
11141
    /* CEIL_F32x4 */
11142
    V128, V128, 
11143
    /* CEIL_F32x4_S */
11144
    /* CEIL_F64 */
11145
    F64, F64, 
11146
    /* CEIL_F64_S */
11147
    /* CEIL_F64x2 */
11148
    V128, V128, 
11149
    /* CEIL_F64x2_S */
11150
    /* CLZ_I32 */
11151
    I32, I32, 
11152
    /* CLZ_I32_S */
11153
    /* CLZ_I64 */
11154
    I64, I64, 
11155
    /* CLZ_I64_S */
11156
    /* CONST_F32 */
11157
    F32, f32imm_op, 
11158
    /* CONST_F32_S */
11159
    f32imm_op, 
11160
    /* CONST_F64 */
11161
    F64, f64imm_op, 
11162
    /* CONST_F64_S */
11163
    f64imm_op, 
11164
    /* CONST_I32 */
11165
    I32, i32imm_op, 
11166
    /* CONST_I32_S */
11167
    i32imm_op, 
11168
    /* CONST_I64 */
11169
    I64, i64imm_op, 
11170
    /* CONST_I64_S */
11171
    i64imm_op, 
11172
    /* CONST_V128_F32x4 */
11173
    V128, f32imm_op, f32imm_op, f32imm_op, f32imm_op, 
11174
    /* CONST_V128_F32x4_S */
11175
    f32imm_op, f32imm_op, f32imm_op, f32imm_op, 
11176
    /* CONST_V128_F64x2 */
11177
    V128, f64imm_op, f64imm_op, 
11178
    /* CONST_V128_F64x2_S */
11179
    f64imm_op, f64imm_op, 
11180
    /* CONST_V128_I16x8 */
11181
    V128, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, 
11182
    /* CONST_V128_I16x8_S */
11183
    vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, 
11184
    /* CONST_V128_I32x4 */
11185
    V128, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, 
11186
    /* CONST_V128_I32x4_S */
11187
    vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, 
11188
    /* CONST_V128_I64x2 */
11189
    V128, vec_i64imm_op, vec_i64imm_op, 
11190
    /* CONST_V128_I64x2_S */
11191
    vec_i64imm_op, vec_i64imm_op, 
11192
    /* CONST_V128_I8x16 */
11193
    V128, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, 
11194
    /* CONST_V128_I8x16_S */
11195
    vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, 
11196
    /* COPYSIGN_F32 */
11197
    F32, F32, F32, 
11198
    /* COPYSIGN_F32_S */
11199
    /* COPYSIGN_F64 */
11200
    F64, F64, F64, 
11201
    /* COPYSIGN_F64_S */
11202
    /* COPY_EXTERNREF */
11203
    EXTERNREF, EXTERNREF, 
11204
    /* COPY_EXTERNREF_S */
11205
    /* COPY_F32 */
11206
    F32, F32, 
11207
    /* COPY_F32_S */
11208
    /* COPY_F64 */
11209
    F64, F64, 
11210
    /* COPY_F64_S */
11211
    /* COPY_FUNCREF */
11212
    FUNCREF, FUNCREF, 
11213
    /* COPY_FUNCREF_S */
11214
    /* COPY_I32 */
11215
    I32, I32, 
11216
    /* COPY_I32_S */
11217
    /* COPY_I64 */
11218
    I64, I64, 
11219
    /* COPY_I64_S */
11220
    /* COPY_V128 */
11221
    V128, V128, 
11222
    /* COPY_V128_S */
11223
    /* CTZ_I32 */
11224
    I32, I32, 
11225
    /* CTZ_I32_S */
11226
    /* CTZ_I64 */
11227
    I64, I64, 
11228
    /* CTZ_I64_S */
11229
    /* DEBUG_UNREACHABLE */
11230
    /* DEBUG_UNREACHABLE_S */
11231
    /* DELEGATE */
11232
    bb_op, 
11233
    /* DELEGATE_S */
11234
    bb_op, 
11235
    /* DIV_F32 */
11236
    F32, F32, F32, 
11237
    /* DIV_F32_S */
11238
    /* DIV_F32x4 */
11239
    V128, V128, V128, 
11240
    /* DIV_F32x4_S */
11241
    /* DIV_F64 */
11242
    F64, F64, F64, 
11243
    /* DIV_F64_S */
11244
    /* DIV_F64x2 */
11245
    V128, V128, V128, 
11246
    /* DIV_F64x2_S */
11247
    /* DIV_S_I32 */
11248
    I32, I32, I32, 
11249
    /* DIV_S_I32_S */
11250
    /* DIV_S_I64 */
11251
    I64, I64, I64, 
11252
    /* DIV_S_I64_S */
11253
    /* DIV_U_I32 */
11254
    I32, I32, I32, 
11255
    /* DIV_U_I32_S */
11256
    /* DIV_U_I64 */
11257
    I64, I64, I64, 
11258
    /* DIV_U_I64_S */
11259
    /* DOT */
11260
    V128, V128, V128, 
11261
    /* DOT_S */
11262
    /* DROP_EXTERNREF */
11263
    EXTERNREF, 
11264
    /* DROP_EXTERNREF_S */
11265
    /* DROP_F32 */
11266
    F32, 
11267
    /* DROP_F32_S */
11268
    /* DROP_F64 */
11269
    F64, 
11270
    /* DROP_F64_S */
11271
    /* DROP_FUNCREF */
11272
    FUNCREF, 
11273
    /* DROP_FUNCREF_S */
11274
    /* DROP_I32 */
11275
    I32, 
11276
    /* DROP_I32_S */
11277
    /* DROP_I64 */
11278
    I64, 
11279
    /* DROP_I64_S */
11280
    /* DROP_V128 */
11281
    V128, 
11282
    /* DROP_V128_S */
11283
    /* ELSE */
11284
    /* ELSE_S */
11285
    /* END */
11286
    /* END_BLOCK */
11287
    /* END_BLOCK_S */
11288
    /* END_FUNCTION */
11289
    /* END_FUNCTION_S */
11290
    /* END_IF */
11291
    /* END_IF_S */
11292
    /* END_LOOP */
11293
    /* END_LOOP_S */
11294
    /* END_S */
11295
    /* END_TRY */
11296
    /* END_TRY_S */
11297
    /* EQZ_I32 */
11298
    I32, I32, 
11299
    /* EQZ_I32_S */
11300
    /* EQZ_I64 */
11301
    I32, I64, 
11302
    /* EQZ_I64_S */
11303
    /* EQ_F32 */
11304
    I32, F32, F32, 
11305
    /* EQ_F32_S */
11306
    /* EQ_F32x4 */
11307
    V128, V128, V128, 
11308
    /* EQ_F32x4_S */
11309
    /* EQ_F64 */
11310
    I32, F64, F64, 
11311
    /* EQ_F64_S */
11312
    /* EQ_F64x2 */
11313
    V128, V128, V128, 
11314
    /* EQ_F64x2_S */
11315
    /* EQ_I16x8 */
11316
    V128, V128, V128, 
11317
    /* EQ_I16x8_S */
11318
    /* EQ_I32 */
11319
    I32, I32, I32, 
11320
    /* EQ_I32_S */
11321
    /* EQ_I32x4 */
11322
    V128, V128, V128, 
11323
    /* EQ_I32x4_S */
11324
    /* EQ_I64 */
11325
    I32, I64, I64, 
11326
    /* EQ_I64_S */
11327
    /* EQ_I64x2 */
11328
    V128, V128, V128, 
11329
    /* EQ_I64x2_S */
11330
    /* EQ_I8x16 */
11331
    V128, V128, V128, 
11332
    /* EQ_I8x16_S */
11333
    /* EXTMUL_HIGH_S_I16x8 */
11334
    V128, V128, V128, 
11335
    /* EXTMUL_HIGH_S_I16x8_S */
11336
    /* EXTMUL_HIGH_S_I32x4 */
11337
    V128, V128, V128, 
11338
    /* EXTMUL_HIGH_S_I32x4_S */
11339
    /* EXTMUL_HIGH_S_I64x2 */
11340
    V128, V128, V128, 
11341
    /* EXTMUL_HIGH_S_I64x2_S */
11342
    /* EXTMUL_HIGH_U_I16x8 */
11343
    V128, V128, V128, 
11344
    /* EXTMUL_HIGH_U_I16x8_S */
11345
    /* EXTMUL_HIGH_U_I32x4 */
11346
    V128, V128, V128, 
11347
    /* EXTMUL_HIGH_U_I32x4_S */
11348
    /* EXTMUL_HIGH_U_I64x2 */
11349
    V128, V128, V128, 
11350
    /* EXTMUL_HIGH_U_I64x2_S */
11351
    /* EXTMUL_LOW_S_I16x8 */
11352
    V128, V128, V128, 
11353
    /* EXTMUL_LOW_S_I16x8_S */
11354
    /* EXTMUL_LOW_S_I32x4 */
11355
    V128, V128, V128, 
11356
    /* EXTMUL_LOW_S_I32x4_S */
11357
    /* EXTMUL_LOW_S_I64x2 */
11358
    V128, V128, V128, 
11359
    /* EXTMUL_LOW_S_I64x2_S */
11360
    /* EXTMUL_LOW_U_I16x8 */
11361
    V128, V128, V128, 
11362
    /* EXTMUL_LOW_U_I16x8_S */
11363
    /* EXTMUL_LOW_U_I32x4 */
11364
    V128, V128, V128, 
11365
    /* EXTMUL_LOW_U_I32x4_S */
11366
    /* EXTMUL_LOW_U_I64x2 */
11367
    V128, V128, V128, 
11368
    /* EXTMUL_LOW_U_I64x2_S */
11369
    /* EXTRACT_LANE_F32x4 */
11370
    F32, V128, vec_i8imm_op, 
11371
    /* EXTRACT_LANE_F32x4_S */
11372
    vec_i8imm_op, 
11373
    /* EXTRACT_LANE_F64x2 */
11374
    F64, V128, vec_i8imm_op, 
11375
    /* EXTRACT_LANE_F64x2_S */
11376
    vec_i8imm_op, 
11377
    /* EXTRACT_LANE_I16x8_s */
11378
    I32, V128, vec_i8imm_op, 
11379
    /* EXTRACT_LANE_I16x8_s_S */
11380
    vec_i8imm_op, 
11381
    /* EXTRACT_LANE_I16x8_u */
11382
    I32, V128, vec_i8imm_op, 
11383
    /* EXTRACT_LANE_I16x8_u_S */
11384
    vec_i8imm_op, 
11385
    /* EXTRACT_LANE_I32x4 */
11386
    I32, V128, vec_i8imm_op, 
11387
    /* EXTRACT_LANE_I32x4_S */
11388
    vec_i8imm_op, 
11389
    /* EXTRACT_LANE_I64x2 */
11390
    I64, V128, vec_i8imm_op, 
11391
    /* EXTRACT_LANE_I64x2_S */
11392
    vec_i8imm_op, 
11393
    /* EXTRACT_LANE_I8x16_s */
11394
    I32, V128, vec_i8imm_op, 
11395
    /* EXTRACT_LANE_I8x16_s_S */
11396
    vec_i8imm_op, 
11397
    /* EXTRACT_LANE_I8x16_u */
11398
    I32, V128, vec_i8imm_op, 
11399
    /* EXTRACT_LANE_I8x16_u_S */
11400
    vec_i8imm_op, 
11401
    /* F32_CONVERT_S_I32 */
11402
    F32, I32, 
11403
    /* F32_CONVERT_S_I32_S */
11404
    /* F32_CONVERT_S_I64 */
11405
    F32, I64, 
11406
    /* F32_CONVERT_S_I64_S */
11407
    /* F32_CONVERT_U_I32 */
11408
    F32, I32, 
11409
    /* F32_CONVERT_U_I32_S */
11410
    /* F32_CONVERT_U_I64 */
11411
    F32, I64, 
11412
    /* F32_CONVERT_U_I64_S */
11413
    /* F32_DEMOTE_F64 */
11414
    F32, F64, 
11415
    /* F32_DEMOTE_F64_S */
11416
    /* F32_REINTERPRET_I32 */
11417
    F32, I32, 
11418
    /* F32_REINTERPRET_I32_S */
11419
    /* F64_CONVERT_S_I32 */
11420
    F64, I32, 
11421
    /* F64_CONVERT_S_I32_S */
11422
    /* F64_CONVERT_S_I64 */
11423
    F64, I64, 
11424
    /* F64_CONVERT_S_I64_S */
11425
    /* F64_CONVERT_U_I32 */
11426
    F64, I32, 
11427
    /* F64_CONVERT_U_I32_S */
11428
    /* F64_CONVERT_U_I64 */
11429
    F64, I64, 
11430
    /* F64_CONVERT_U_I64_S */
11431
    /* F64_PROMOTE_F32 */
11432
    F64, F32, 
11433
    /* F64_PROMOTE_F32_S */
11434
    /* F64_REINTERPRET_I64 */
11435
    F64, I64, 
11436
    /* F64_REINTERPRET_I64_S */
11437
    /* FALLTHROUGH_RETURN */
11438
    /* FALLTHROUGH_RETURN_S */
11439
    /* FLOOR_F32 */
11440
    F32, F32, 
11441
    /* FLOOR_F32_S */
11442
    /* FLOOR_F32x4 */
11443
    V128, V128, 
11444
    /* FLOOR_F32x4_S */
11445
    /* FLOOR_F64 */
11446
    F64, F64, 
11447
    /* FLOOR_F64_S */
11448
    /* FLOOR_F64x2 */
11449
    V128, V128, 
11450
    /* FLOOR_F64x2_S */
11451
    /* FP_TO_SINT_I32_F32 */
11452
    I32, F32, 
11453
    /* FP_TO_SINT_I32_F32_S */
11454
    /* FP_TO_SINT_I32_F64 */
11455
    I32, F64, 
11456
    /* FP_TO_SINT_I32_F64_S */
11457
    /* FP_TO_SINT_I64_F32 */
11458
    I64, F32, 
11459
    /* FP_TO_SINT_I64_F32_S */
11460
    /* FP_TO_SINT_I64_F64 */
11461
    I64, F64, 
11462
    /* FP_TO_SINT_I64_F64_S */
11463
    /* FP_TO_UINT_I32_F32 */
11464
    I32, F32, 
11465
    /* FP_TO_UINT_I32_F32_S */
11466
    /* FP_TO_UINT_I32_F64 */
11467
    I32, F64, 
11468
    /* FP_TO_UINT_I32_F64_S */
11469
    /* FP_TO_UINT_I64_F32 */
11470
    I64, F32, 
11471
    /* FP_TO_UINT_I64_F32_S */
11472
    /* FP_TO_UINT_I64_F64 */
11473
    I64, F64, 
11474
    /* FP_TO_UINT_I64_F64_S */
11475
    /* GE_F32 */
11476
    I32, F32, F32, 
11477
    /* GE_F32_S */
11478
    /* GE_F32x4 */
11479
    V128, V128, V128, 
11480
    /* GE_F32x4_S */
11481
    /* GE_F64 */
11482
    I32, F64, F64, 
11483
    /* GE_F64_S */
11484
    /* GE_F64x2 */
11485
    V128, V128, V128, 
11486
    /* GE_F64x2_S */
11487
    /* GE_S_I16x8 */
11488
    V128, V128, V128, 
11489
    /* GE_S_I16x8_S */
11490
    /* GE_S_I32 */
11491
    I32, I32, I32, 
11492
    /* GE_S_I32_S */
11493
    /* GE_S_I32x4 */
11494
    V128, V128, V128, 
11495
    /* GE_S_I32x4_S */
11496
    /* GE_S_I64 */
11497
    I32, I64, I64, 
11498
    /* GE_S_I64_S */
11499
    /* GE_S_I64x2 */
11500
    V128, V128, V128, 
11501
    /* GE_S_I64x2_S */
11502
    /* GE_S_I8x16 */
11503
    V128, V128, V128, 
11504
    /* GE_S_I8x16_S */
11505
    /* GE_U_I16x8 */
11506
    V128, V128, V128, 
11507
    /* GE_U_I16x8_S */
11508
    /* GE_U_I32 */
11509
    I32, I32, I32, 
11510
    /* GE_U_I32_S */
11511
    /* GE_U_I32x4 */
11512
    V128, V128, V128, 
11513
    /* GE_U_I32x4_S */
11514
    /* GE_U_I64 */
11515
    I32, I64, I64, 
11516
    /* GE_U_I64_S */
11517
    /* GE_U_I8x16 */
11518
    V128, V128, V128, 
11519
    /* GE_U_I8x16_S */
11520
    /* GLOBAL_GET_EXTERNREF */
11521
    EXTERNREF, global_op32, 
11522
    /* GLOBAL_GET_EXTERNREF_S */
11523
    global_op32, 
11524
    /* GLOBAL_GET_F32 */
11525
    F32, global_op32, 
11526
    /* GLOBAL_GET_F32_S */
11527
    global_op32, 
11528
    /* GLOBAL_GET_F64 */
11529
    F64, global_op32, 
11530
    /* GLOBAL_GET_F64_S */
11531
    global_op32, 
11532
    /* GLOBAL_GET_FUNCREF */
11533
    FUNCREF, global_op32, 
11534
    /* GLOBAL_GET_FUNCREF_S */
11535
    global_op32, 
11536
    /* GLOBAL_GET_I32 */
11537
    I32, global_op32, 
11538
    /* GLOBAL_GET_I32_S */
11539
    global_op32, 
11540
    /* GLOBAL_GET_I64 */
11541
    I64, global_op64, 
11542
    /* GLOBAL_GET_I64_S */
11543
    global_op64, 
11544
    /* GLOBAL_GET_V128 */
11545
    V128, global_op32, 
11546
    /* GLOBAL_GET_V128_S */
11547
    global_op32, 
11548
    /* GLOBAL_SET_EXTERNREF */
11549
    global_op32, EXTERNREF, 
11550
    /* GLOBAL_SET_EXTERNREF_S */
11551
    global_op32, 
11552
    /* GLOBAL_SET_F32 */
11553
    global_op32, F32, 
11554
    /* GLOBAL_SET_F32_S */
11555
    global_op32, 
11556
    /* GLOBAL_SET_F64 */
11557
    global_op32, F64, 
11558
    /* GLOBAL_SET_F64_S */
11559
    global_op32, 
11560
    /* GLOBAL_SET_FUNCREF */
11561
    global_op32, FUNCREF, 
11562
    /* GLOBAL_SET_FUNCREF_S */
11563
    global_op32, 
11564
    /* GLOBAL_SET_I32 */
11565
    global_op32, I32, 
11566
    /* GLOBAL_SET_I32_S */
11567
    global_op32, 
11568
    /* GLOBAL_SET_I64 */
11569
    global_op64, I64, 
11570
    /* GLOBAL_SET_I64_S */
11571
    global_op64, 
11572
    /* GLOBAL_SET_V128 */
11573
    global_op32, V128, 
11574
    /* GLOBAL_SET_V128_S */
11575
    global_op32, 
11576
    /* GT_F32 */
11577
    I32, F32, F32, 
11578
    /* GT_F32_S */
11579
    /* GT_F32x4 */
11580
    V128, V128, V128, 
11581
    /* GT_F32x4_S */
11582
    /* GT_F64 */
11583
    I32, F64, F64, 
11584
    /* GT_F64_S */
11585
    /* GT_F64x2 */
11586
    V128, V128, V128, 
11587
    /* GT_F64x2_S */
11588
    /* GT_S_I16x8 */
11589
    V128, V128, V128, 
11590
    /* GT_S_I16x8_S */
11591
    /* GT_S_I32 */
11592
    I32, I32, I32, 
11593
    /* GT_S_I32_S */
11594
    /* GT_S_I32x4 */
11595
    V128, V128, V128, 
11596
    /* GT_S_I32x4_S */
11597
    /* GT_S_I64 */
11598
    I32, I64, I64, 
11599
    /* GT_S_I64_S */
11600
    /* GT_S_I64x2 */
11601
    V128, V128, V128, 
11602
    /* GT_S_I64x2_S */
11603
    /* GT_S_I8x16 */
11604
    V128, V128, V128, 
11605
    /* GT_S_I8x16_S */
11606
    /* GT_U_I16x8 */
11607
    V128, V128, V128, 
11608
    /* GT_U_I16x8_S */
11609
    /* GT_U_I32 */
11610
    I32, I32, I32, 
11611
    /* GT_U_I32_S */
11612
    /* GT_U_I32x4 */
11613
    V128, V128, V128, 
11614
    /* GT_U_I32x4_S */
11615
    /* GT_U_I64 */
11616
    I32, I64, I64, 
11617
    /* GT_U_I64_S */
11618
    /* GT_U_I8x16 */
11619
    V128, V128, V128, 
11620
    /* GT_U_I8x16_S */
11621
    /* I32_EXTEND16_S_I32 */
11622
    I32, I32, 
11623
    /* I32_EXTEND16_S_I32_S */
11624
    /* I32_EXTEND8_S_I32 */
11625
    I32, I32, 
11626
    /* I32_EXTEND8_S_I32_S */
11627
    /* I32_REINTERPRET_F32 */
11628
    I32, F32, 
11629
    /* I32_REINTERPRET_F32_S */
11630
    /* I32_TRUNC_S_F32 */
11631
    I32, F32, 
11632
    /* I32_TRUNC_S_F32_S */
11633
    /* I32_TRUNC_S_F64 */
11634
    I32, F64, 
11635
    /* I32_TRUNC_S_F64_S */
11636
    /* I32_TRUNC_S_SAT_F32 */
11637
    I32, F32, 
11638
    /* I32_TRUNC_S_SAT_F32_S */
11639
    /* I32_TRUNC_S_SAT_F64 */
11640
    I32, F64, 
11641
    /* I32_TRUNC_S_SAT_F64_S */
11642
    /* I32_TRUNC_U_F32 */
11643
    I32, F32, 
11644
    /* I32_TRUNC_U_F32_S */
11645
    /* I32_TRUNC_U_F64 */
11646
    I32, F64, 
11647
    /* I32_TRUNC_U_F64_S */
11648
    /* I32_TRUNC_U_SAT_F32 */
11649
    I32, F32, 
11650
    /* I32_TRUNC_U_SAT_F32_S */
11651
    /* I32_TRUNC_U_SAT_F64 */
11652
    I32, F64, 
11653
    /* I32_TRUNC_U_SAT_F64_S */
11654
    /* I32_WRAP_I64 */
11655
    I32, I64, 
11656
    /* I32_WRAP_I64_S */
11657
    /* I64_EXTEND16_S_I64 */
11658
    I64, I64, 
11659
    /* I64_EXTEND16_S_I64_S */
11660
    /* I64_EXTEND32_S_I64 */
11661
    I64, I64, 
11662
    /* I64_EXTEND32_S_I64_S */
11663
    /* I64_EXTEND8_S_I64 */
11664
    I64, I64, 
11665
    /* I64_EXTEND8_S_I64_S */
11666
    /* I64_EXTEND_S_I32 */
11667
    I64, I32, 
11668
    /* I64_EXTEND_S_I32_S */
11669
    /* I64_EXTEND_U_I32 */
11670
    I64, I32, 
11671
    /* I64_EXTEND_U_I32_S */
11672
    /* I64_REINTERPRET_F64 */
11673
    I64, F64, 
11674
    /* I64_REINTERPRET_F64_S */
11675
    /* I64_TRUNC_S_F32 */
11676
    I64, F32, 
11677
    /* I64_TRUNC_S_F32_S */
11678
    /* I64_TRUNC_S_F64 */
11679
    I64, F64, 
11680
    /* I64_TRUNC_S_F64_S */
11681
    /* I64_TRUNC_S_SAT_F32 */
11682
    I64, F32, 
11683
    /* I64_TRUNC_S_SAT_F32_S */
11684
    /* I64_TRUNC_S_SAT_F64 */
11685
    I64, F64, 
11686
    /* I64_TRUNC_S_SAT_F64_S */
11687
    /* I64_TRUNC_U_F32 */
11688
    I64, F32, 
11689
    /* I64_TRUNC_U_F32_S */
11690
    /* I64_TRUNC_U_F64 */
11691
    I64, F64, 
11692
    /* I64_TRUNC_U_F64_S */
11693
    /* I64_TRUNC_U_SAT_F32 */
11694
    I64, F32, 
11695
    /* I64_TRUNC_U_SAT_F32_S */
11696
    /* I64_TRUNC_U_SAT_F64 */
11697
    I64, F64, 
11698
    /* I64_TRUNC_U_SAT_F64_S */
11699
    /* IF */
11700
    Signature, I32, 
11701
    /* IF_S */
11702
    Signature, 
11703
    /* LANESELECT_I16x8 */
11704
    V128, V128, V128, V128, 
11705
    /* LANESELECT_I16x8_S */
11706
    /* LANESELECT_I32x4 */
11707
    V128, V128, V128, V128, 
11708
    /* LANESELECT_I32x4_S */
11709
    /* LANESELECT_I64x2 */
11710
    V128, V128, V128, V128, 
11711
    /* LANESELECT_I64x2_S */
11712
    /* LANESELECT_I8x16 */
11713
    V128, V128, V128, V128, 
11714
    /* LANESELECT_I8x16_S */
11715
    /* LE_F32 */
11716
    I32, F32, F32, 
11717
    /* LE_F32_S */
11718
    /* LE_F32x4 */
11719
    V128, V128, V128, 
11720
    /* LE_F32x4_S */
11721
    /* LE_F64 */
11722
    I32, F64, F64, 
11723
    /* LE_F64_S */
11724
    /* LE_F64x2 */
11725
    V128, V128, V128, 
11726
    /* LE_F64x2_S */
11727
    /* LE_S_I16x8 */
11728
    V128, V128, V128, 
11729
    /* LE_S_I16x8_S */
11730
    /* LE_S_I32 */
11731
    I32, I32, I32, 
11732
    /* LE_S_I32_S */
11733
    /* LE_S_I32x4 */
11734
    V128, V128, V128, 
11735
    /* LE_S_I32x4_S */
11736
    /* LE_S_I64 */
11737
    I32, I64, I64, 
11738
    /* LE_S_I64_S */
11739
    /* LE_S_I64x2 */
11740
    V128, V128, V128, 
11741
    /* LE_S_I64x2_S */
11742
    /* LE_S_I8x16 */
11743
    V128, V128, V128, 
11744
    /* LE_S_I8x16_S */
11745
    /* LE_U_I16x8 */
11746
    V128, V128, V128, 
11747
    /* LE_U_I16x8_S */
11748
    /* LE_U_I32 */
11749
    I32, I32, I32, 
11750
    /* LE_U_I32_S */
11751
    /* LE_U_I32x4 */
11752
    V128, V128, V128, 
11753
    /* LE_U_I32x4_S */
11754
    /* LE_U_I64 */
11755
    I32, I64, I64, 
11756
    /* LE_U_I64_S */
11757
    /* LE_U_I8x16 */
11758
    V128, V128, V128, 
11759
    /* LE_U_I8x16_S */
11760
    /* LOAD16_SPLAT_A32 */
11761
    V128, P2Align, offset32_op, I32, 
11762
    /* LOAD16_SPLAT_A32_S */
11763
    P2Align, offset32_op, 
11764
    /* LOAD16_SPLAT_A64 */
11765
    V128, P2Align, offset64_op, I64, 
11766
    /* LOAD16_SPLAT_A64_S */
11767
    P2Align, offset64_op, 
11768
    /* LOAD16_S_I32_A32 */
11769
    I32, P2Align, offset32_op, I32, 
11770
    /* LOAD16_S_I32_A32_S */
11771
    P2Align, offset32_op, 
11772
    /* LOAD16_S_I32_A64 */
11773
    I32, P2Align, offset64_op, I64, 
11774
    /* LOAD16_S_I32_A64_S */
11775
    P2Align, offset64_op, 
11776
    /* LOAD16_S_I64_A32 */
11777
    I64, P2Align, offset32_op, I32, 
11778
    /* LOAD16_S_I64_A32_S */
11779
    P2Align, offset32_op, 
11780
    /* LOAD16_S_I64_A64 */
11781
    I64, P2Align, offset64_op, I64, 
11782
    /* LOAD16_S_I64_A64_S */
11783
    P2Align, offset64_op, 
11784
    /* LOAD16_U_I32_A32 */
11785
    I32, P2Align, offset32_op, I32, 
11786
    /* LOAD16_U_I32_A32_S */
11787
    P2Align, offset32_op, 
11788
    /* LOAD16_U_I32_A64 */
11789
    I32, P2Align, offset64_op, I64, 
11790
    /* LOAD16_U_I32_A64_S */
11791
    P2Align, offset64_op, 
11792
    /* LOAD16_U_I64_A32 */
11793
    I64, P2Align, offset32_op, I32, 
11794
    /* LOAD16_U_I64_A32_S */
11795
    P2Align, offset32_op, 
11796
    /* LOAD16_U_I64_A64 */
11797
    I64, P2Align, offset64_op, I64, 
11798
    /* LOAD16_U_I64_A64_S */
11799
    P2Align, offset64_op, 
11800
    /* LOAD32_SPLAT_A32 */
11801
    V128, P2Align, offset32_op, I32, 
11802
    /* LOAD32_SPLAT_A32_S */
11803
    P2Align, offset32_op, 
11804
    /* LOAD32_SPLAT_A64 */
11805
    V128, P2Align, offset64_op, I64, 
11806
    /* LOAD32_SPLAT_A64_S */
11807
    P2Align, offset64_op, 
11808
    /* LOAD32_S_I64_A32 */
11809
    I64, P2Align, offset32_op, I32, 
11810
    /* LOAD32_S_I64_A32_S */
11811
    P2Align, offset32_op, 
11812
    /* LOAD32_S_I64_A64 */
11813
    I64, P2Align, offset64_op, I64, 
11814
    /* LOAD32_S_I64_A64_S */
11815
    P2Align, offset64_op, 
11816
    /* LOAD32_U_I64_A32 */
11817
    I64, P2Align, offset32_op, I32, 
11818
    /* LOAD32_U_I64_A32_S */
11819
    P2Align, offset32_op, 
11820
    /* LOAD32_U_I64_A64 */
11821
    I64, P2Align, offset64_op, I64, 
11822
    /* LOAD32_U_I64_A64_S */
11823
    P2Align, offset64_op, 
11824
    /* LOAD64_SPLAT_A32 */
11825
    V128, P2Align, offset32_op, I32, 
11826
    /* LOAD64_SPLAT_A32_S */
11827
    P2Align, offset32_op, 
11828
    /* LOAD64_SPLAT_A64 */
11829
    V128, P2Align, offset64_op, I64, 
11830
    /* LOAD64_SPLAT_A64_S */
11831
    P2Align, offset64_op, 
11832
    /* LOAD8_SPLAT_A32 */
11833
    V128, P2Align, offset32_op, I32, 
11834
    /* LOAD8_SPLAT_A32_S */
11835
    P2Align, offset32_op, 
11836
    /* LOAD8_SPLAT_A64 */
11837
    V128, P2Align, offset64_op, I64, 
11838
    /* LOAD8_SPLAT_A64_S */
11839
    P2Align, offset64_op, 
11840
    /* LOAD8_S_I32_A32 */
11841
    I32, P2Align, offset32_op, I32, 
11842
    /* LOAD8_S_I32_A32_S */
11843
    P2Align, offset32_op, 
11844
    /* LOAD8_S_I32_A64 */
11845
    I32, P2Align, offset64_op, I64, 
11846
    /* LOAD8_S_I32_A64_S */
11847
    P2Align, offset64_op, 
11848
    /* LOAD8_S_I64_A32 */
11849
    I64, P2Align, offset32_op, I32, 
11850
    /* LOAD8_S_I64_A32_S */
11851
    P2Align, offset32_op, 
11852
    /* LOAD8_S_I64_A64 */
11853
    I64, P2Align, offset64_op, I64, 
11854
    /* LOAD8_S_I64_A64_S */
11855
    P2Align, offset64_op, 
11856
    /* LOAD8_U_I32_A32 */
11857
    I32, P2Align, offset32_op, I32, 
11858
    /* LOAD8_U_I32_A32_S */
11859
    P2Align, offset32_op, 
11860
    /* LOAD8_U_I32_A64 */
11861
    I32, P2Align, offset64_op, I64, 
11862
    /* LOAD8_U_I32_A64_S */
11863
    P2Align, offset64_op, 
11864
    /* LOAD8_U_I64_A32 */
11865
    I64, P2Align, offset32_op, I32, 
11866
    /* LOAD8_U_I64_A32_S */
11867
    P2Align, offset32_op, 
11868
    /* LOAD8_U_I64_A64 */
11869
    I64, P2Align, offset64_op, I64, 
11870
    /* LOAD8_U_I64_A64_S */
11871
    P2Align, offset64_op, 
11872
    /* LOAD_EXTEND_S_I16x8_A32 */
11873
    V128, P2Align, offset32_op, I32, 
11874
    /* LOAD_EXTEND_S_I16x8_A32_S */
11875
    P2Align, offset32_op, 
11876
    /* LOAD_EXTEND_S_I16x8_A64 */
11877
    V128, P2Align, offset64_op, I64, 
11878
    /* LOAD_EXTEND_S_I16x8_A64_S */
11879
    P2Align, offset64_op, 
11880
    /* LOAD_EXTEND_S_I32x4_A32 */
11881
    V128, P2Align, offset32_op, I32, 
11882
    /* LOAD_EXTEND_S_I32x4_A32_S */
11883
    P2Align, offset32_op, 
11884
    /* LOAD_EXTEND_S_I32x4_A64 */
11885
    V128, P2Align, offset64_op, I64, 
11886
    /* LOAD_EXTEND_S_I32x4_A64_S */
11887
    P2Align, offset64_op, 
11888
    /* LOAD_EXTEND_S_I64x2_A32 */
11889
    V128, P2Align, offset32_op, I32, 
11890
    /* LOAD_EXTEND_S_I64x2_A32_S */
11891
    P2Align, offset32_op, 
11892
    /* LOAD_EXTEND_S_I64x2_A64 */
11893
    V128, P2Align, offset64_op, I64, 
11894
    /* LOAD_EXTEND_S_I64x2_A64_S */
11895
    P2Align, offset64_op, 
11896
    /* LOAD_EXTEND_U_I16x8_A32 */
11897
    V128, P2Align, offset32_op, I32, 
11898
    /* LOAD_EXTEND_U_I16x8_A32_S */
11899
    P2Align, offset32_op, 
11900
    /* LOAD_EXTEND_U_I16x8_A64 */
11901
    V128, P2Align, offset64_op, I64, 
11902
    /* LOAD_EXTEND_U_I16x8_A64_S */
11903
    P2Align, offset64_op, 
11904
    /* LOAD_EXTEND_U_I32x4_A32 */
11905
    V128, P2Align, offset32_op, I32, 
11906
    /* LOAD_EXTEND_U_I32x4_A32_S */
11907
    P2Align, offset32_op, 
11908
    /* LOAD_EXTEND_U_I32x4_A64 */
11909
    V128, P2Align, offset64_op, I64, 
11910
    /* LOAD_EXTEND_U_I32x4_A64_S */
11911
    P2Align, offset64_op, 
11912
    /* LOAD_EXTEND_U_I64x2_A32 */
11913
    V128, P2Align, offset32_op, I32, 
11914
    /* LOAD_EXTEND_U_I64x2_A32_S */
11915
    P2Align, offset32_op, 
11916
    /* LOAD_EXTEND_U_I64x2_A64 */
11917
    V128, P2Align, offset64_op, I64, 
11918
    /* LOAD_EXTEND_U_I64x2_A64_S */
11919
    P2Align, offset64_op, 
11920
    /* LOAD_F32_A32 */
11921
    F32, P2Align, offset32_op, I32, 
11922
    /* LOAD_F32_A32_S */
11923
    P2Align, offset32_op, 
11924
    /* LOAD_F32_A64 */
11925
    F32, P2Align, offset64_op, I64, 
11926
    /* LOAD_F32_A64_S */
11927
    P2Align, offset64_op, 
11928
    /* LOAD_F64_A32 */
11929
    F64, P2Align, offset32_op, I32, 
11930
    /* LOAD_F64_A32_S */
11931
    P2Align, offset32_op, 
11932
    /* LOAD_F64_A64 */
11933
    F64, P2Align, offset64_op, I64, 
11934
    /* LOAD_F64_A64_S */
11935
    P2Align, offset64_op, 
11936
    /* LOAD_I32_A32 */
11937
    I32, P2Align, offset32_op, I32, 
11938
    /* LOAD_I32_A32_S */
11939
    P2Align, offset32_op, 
11940
    /* LOAD_I32_A64 */
11941
    I32, P2Align, offset64_op, I64, 
11942
    /* LOAD_I32_A64_S */
11943
    P2Align, offset64_op, 
11944
    /* LOAD_I64_A32 */
11945
    I64, P2Align, offset32_op, I32, 
11946
    /* LOAD_I64_A32_S */
11947
    P2Align, offset32_op, 
11948
    /* LOAD_I64_A64 */
11949
    I64, P2Align, offset64_op, I64, 
11950
    /* LOAD_I64_A64_S */
11951
    P2Align, offset64_op, 
11952
    /* LOAD_LANE_I16x8_A32 */
11953
    V128, P2Align, offset32_op, vec_i8imm_op, I32, V128, 
11954
    /* LOAD_LANE_I16x8_A32_S */
11955
    P2Align, offset32_op, vec_i8imm_op, 
11956
    /* LOAD_LANE_I16x8_A64 */
11957
    V128, P2Align, offset64_op, vec_i8imm_op, I64, V128, 
11958
    /* LOAD_LANE_I16x8_A64_S */
11959
    P2Align, offset64_op, vec_i8imm_op, 
11960
    /* LOAD_LANE_I32x4_A32 */
11961
    V128, P2Align, offset32_op, vec_i8imm_op, I32, V128, 
11962
    /* LOAD_LANE_I32x4_A32_S */
11963
    P2Align, offset32_op, vec_i8imm_op, 
11964
    /* LOAD_LANE_I32x4_A64 */
11965
    V128, P2Align, offset64_op, vec_i8imm_op, I64, V128, 
11966
    /* LOAD_LANE_I32x4_A64_S */
11967
    P2Align, offset64_op, vec_i8imm_op, 
11968
    /* LOAD_LANE_I64x2_A32 */
11969
    V128, P2Align, offset32_op, vec_i8imm_op, I32, V128, 
11970
    /* LOAD_LANE_I64x2_A32_S */
11971
    P2Align, offset32_op, vec_i8imm_op, 
11972
    /* LOAD_LANE_I64x2_A64 */
11973
    V128, P2Align, offset64_op, vec_i8imm_op, I64, V128, 
11974
    /* LOAD_LANE_I64x2_A64_S */
11975
    P2Align, offset64_op, vec_i8imm_op, 
11976
    /* LOAD_LANE_I8x16_A32 */
11977
    V128, P2Align, offset32_op, vec_i8imm_op, I32, V128, 
11978
    /* LOAD_LANE_I8x16_A32_S */
11979
    P2Align, offset32_op, vec_i8imm_op, 
11980
    /* LOAD_LANE_I8x16_A64 */
11981
    V128, P2Align, offset64_op, vec_i8imm_op, I64, V128, 
11982
    /* LOAD_LANE_I8x16_A64_S */
11983
    P2Align, offset64_op, vec_i8imm_op, 
11984
    /* LOAD_V128_A32 */
11985
    V128, P2Align, offset32_op, I32, 
11986
    /* LOAD_V128_A32_S */
11987
    P2Align, offset32_op, 
11988
    /* LOAD_V128_A64 */
11989
    V128, P2Align, offset64_op, I64, 
11990
    /* LOAD_V128_A64_S */
11991
    P2Align, offset64_op, 
11992
    /* LOAD_ZERO_I32x4_A32 */
11993
    V128, P2Align, offset32_op, I32, 
11994
    /* LOAD_ZERO_I32x4_A32_S */
11995
    P2Align, offset32_op, 
11996
    /* LOAD_ZERO_I32x4_A64 */
11997
    V128, P2Align, offset64_op, I64, 
11998
    /* LOAD_ZERO_I32x4_A64_S */
11999
    P2Align, offset64_op, 
12000
    /* LOAD_ZERO_I64x2_A32 */
12001
    V128, P2Align, offset32_op, I32, 
12002
    /* LOAD_ZERO_I64x2_A32_S */
12003
    P2Align, offset32_op, 
12004
    /* LOAD_ZERO_I64x2_A64 */
12005
    V128, P2Align, offset64_op, I64, 
12006
    /* LOAD_ZERO_I64x2_A64_S */
12007
    P2Align, offset64_op, 
12008
    /* LOCAL_GET_EXTERNREF */
12009
    EXTERNREF, local_op, 
12010
    /* LOCAL_GET_EXTERNREF_S */
12011
    local_op, 
12012
    /* LOCAL_GET_F32 */
12013
    F32, local_op, 
12014
    /* LOCAL_GET_F32_S */
12015
    local_op, 
12016
    /* LOCAL_GET_F64 */
12017
    F64, local_op, 
12018
    /* LOCAL_GET_F64_S */
12019
    local_op, 
12020
    /* LOCAL_GET_FUNCREF */
12021
    FUNCREF, local_op, 
12022
    /* LOCAL_GET_FUNCREF_S */
12023
    local_op, 
12024
    /* LOCAL_GET_I32 */
12025
    I32, local_op, 
12026
    /* LOCAL_GET_I32_S */
12027
    local_op, 
12028
    /* LOCAL_GET_I64 */
12029
    I64, local_op, 
12030
    /* LOCAL_GET_I64_S */
12031
    local_op, 
12032
    /* LOCAL_GET_V128 */
12033
    V128, local_op, 
12034
    /* LOCAL_GET_V128_S */
12035
    local_op, 
12036
    /* LOCAL_SET_EXTERNREF */
12037
    local_op, EXTERNREF, 
12038
    /* LOCAL_SET_EXTERNREF_S */
12039
    local_op, 
12040
    /* LOCAL_SET_F32 */
12041
    local_op, F32, 
12042
    /* LOCAL_SET_F32_S */
12043
    local_op, 
12044
    /* LOCAL_SET_F64 */
12045
    local_op, F64, 
12046
    /* LOCAL_SET_F64_S */
12047
    local_op, 
12048
    /* LOCAL_SET_FUNCREF */
12049
    local_op, FUNCREF, 
12050
    /* LOCAL_SET_FUNCREF_S */
12051
    local_op, 
12052
    /* LOCAL_SET_I32 */
12053
    local_op, I32, 
12054
    /* LOCAL_SET_I32_S */
12055
    local_op, 
12056
    /* LOCAL_SET_I64 */
12057
    local_op, I64, 
12058
    /* LOCAL_SET_I64_S */
12059
    local_op, 
12060
    /* LOCAL_SET_V128 */
12061
    local_op, V128, 
12062
    /* LOCAL_SET_V128_S */
12063
    local_op, 
12064
    /* LOCAL_TEE_EXTERNREF */
12065
    EXTERNREF, local_op, EXTERNREF, 
12066
    /* LOCAL_TEE_EXTERNREF_S */
12067
    local_op, 
12068
    /* LOCAL_TEE_F32 */
12069
    F32, local_op, F32, 
12070
    /* LOCAL_TEE_F32_S */
12071
    local_op, 
12072
    /* LOCAL_TEE_F64 */
12073
    F64, local_op, F64, 
12074
    /* LOCAL_TEE_F64_S */
12075
    local_op, 
12076
    /* LOCAL_TEE_FUNCREF */
12077
    FUNCREF, local_op, FUNCREF, 
12078
    /* LOCAL_TEE_FUNCREF_S */
12079
    local_op, 
12080
    /* LOCAL_TEE_I32 */
12081
    I32, local_op, I32, 
12082
    /* LOCAL_TEE_I32_S */
12083
    local_op, 
12084
    /* LOCAL_TEE_I64 */
12085
    I64, local_op, I64, 
12086
    /* LOCAL_TEE_I64_S */
12087
    local_op, 
12088
    /* LOCAL_TEE_V128 */
12089
    V128, local_op, V128, 
12090
    /* LOCAL_TEE_V128_S */
12091
    local_op, 
12092
    /* LOOP */
12093
    Signature, 
12094
    /* LOOP_S */
12095
    Signature, 
12096
    /* LT_F32 */
12097
    I32, F32, F32, 
12098
    /* LT_F32_S */
12099
    /* LT_F32x4 */
12100
    V128, V128, V128, 
12101
    /* LT_F32x4_S */
12102
    /* LT_F64 */
12103
    I32, F64, F64, 
12104
    /* LT_F64_S */
12105
    /* LT_F64x2 */
12106
    V128, V128, V128, 
12107
    /* LT_F64x2_S */
12108
    /* LT_S_I16x8 */
12109
    V128, V128, V128, 
12110
    /* LT_S_I16x8_S */
12111
    /* LT_S_I32 */
12112
    I32, I32, I32, 
12113
    /* LT_S_I32_S */
12114
    /* LT_S_I32x4 */
12115
    V128, V128, V128, 
12116
    /* LT_S_I32x4_S */
12117
    /* LT_S_I64 */
12118
    I32, I64, I64, 
12119
    /* LT_S_I64_S */
12120
    /* LT_S_I64x2 */
12121
    V128, V128, V128, 
12122
    /* LT_S_I64x2_S */
12123
    /* LT_S_I8x16 */
12124
    V128, V128, V128, 
12125
    /* LT_S_I8x16_S */
12126
    /* LT_U_I16x8 */
12127
    V128, V128, V128, 
12128
    /* LT_U_I16x8_S */
12129
    /* LT_U_I32 */
12130
    I32, I32, I32, 
12131
    /* LT_U_I32_S */
12132
    /* LT_U_I32x4 */
12133
    V128, V128, V128, 
12134
    /* LT_U_I32x4_S */
12135
    /* LT_U_I64 */
12136
    I32, I64, I64, 
12137
    /* LT_U_I64_S */
12138
    /* LT_U_I8x16 */
12139
    V128, V128, V128, 
12140
    /* LT_U_I8x16_S */
12141
    /* MADD_F32x4 */
12142
    V128, V128, V128, V128, 
12143
    /* MADD_F32x4_S */
12144
    /* MADD_F64x2 */
12145
    V128, V128, V128, V128, 
12146
    /* MADD_F64x2_S */
12147
    /* MAX_F32 */
12148
    F32, F32, F32, 
12149
    /* MAX_F32_S */
12150
    /* MAX_F32x4 */
12151
    V128, V128, V128, 
12152
    /* MAX_F32x4_S */
12153
    /* MAX_F64 */
12154
    F64, F64, F64, 
12155
    /* MAX_F64_S */
12156
    /* MAX_F64x2 */
12157
    V128, V128, V128, 
12158
    /* MAX_F64x2_S */
12159
    /* MAX_S_I16x8 */
12160
    V128, V128, V128, 
12161
    /* MAX_S_I16x8_S */
12162
    /* MAX_S_I32x4 */
12163
    V128, V128, V128, 
12164
    /* MAX_S_I32x4_S */
12165
    /* MAX_S_I8x16 */
12166
    V128, V128, V128, 
12167
    /* MAX_S_I8x16_S */
12168
    /* MAX_U_I16x8 */
12169
    V128, V128, V128, 
12170
    /* MAX_U_I16x8_S */
12171
    /* MAX_U_I32x4 */
12172
    V128, V128, V128, 
12173
    /* MAX_U_I32x4_S */
12174
    /* MAX_U_I8x16 */
12175
    V128, V128, V128, 
12176
    /* MAX_U_I8x16_S */
12177
    /* MEMORY_ATOMIC_NOTIFY_A32 */
12178
    I32, P2Align, offset32_op, I32, I32, 
12179
    /* MEMORY_ATOMIC_NOTIFY_A32_S */
12180
    P2Align, offset32_op, 
12181
    /* MEMORY_ATOMIC_NOTIFY_A64 */
12182
    I32, P2Align, offset64_op, I64, I32, 
12183
    /* MEMORY_ATOMIC_NOTIFY_A64_S */
12184
    P2Align, offset64_op, 
12185
    /* MEMORY_ATOMIC_WAIT32_A32 */
12186
    I32, P2Align, offset32_op, I32, I32, I64, 
12187
    /* MEMORY_ATOMIC_WAIT32_A32_S */
12188
    P2Align, offset32_op, 
12189
    /* MEMORY_ATOMIC_WAIT32_A64 */
12190
    I32, P2Align, offset64_op, I64, I32, I64, 
12191
    /* MEMORY_ATOMIC_WAIT32_A64_S */
12192
    P2Align, offset64_op, 
12193
    /* MEMORY_ATOMIC_WAIT64_A32 */
12194
    I32, P2Align, offset32_op, I32, I64, I64, 
12195
    /* MEMORY_ATOMIC_WAIT64_A32_S */
12196
    P2Align, offset32_op, 
12197
    /* MEMORY_ATOMIC_WAIT64_A64 */
12198
    I32, P2Align, offset64_op, I64, I64, I64, 
12199
    /* MEMORY_ATOMIC_WAIT64_A64_S */
12200
    P2Align, offset64_op, 
12201
    /* MIN_F32 */
12202
    F32, F32, F32, 
12203
    /* MIN_F32_S */
12204
    /* MIN_F32x4 */
12205
    V128, V128, V128, 
12206
    /* MIN_F32x4_S */
12207
    /* MIN_F64 */
12208
    F64, F64, F64, 
12209
    /* MIN_F64_S */
12210
    /* MIN_F64x2 */
12211
    V128, V128, V128, 
12212
    /* MIN_F64x2_S */
12213
    /* MIN_S_I16x8 */
12214
    V128, V128, V128, 
12215
    /* MIN_S_I16x8_S */
12216
    /* MIN_S_I32x4 */
12217
    V128, V128, V128, 
12218
    /* MIN_S_I32x4_S */
12219
    /* MIN_S_I8x16 */
12220
    V128, V128, V128, 
12221
    /* MIN_S_I8x16_S */
12222
    /* MIN_U_I16x8 */
12223
    V128, V128, V128, 
12224
    /* MIN_U_I16x8_S */
12225
    /* MIN_U_I32x4 */
12226
    V128, V128, V128, 
12227
    /* MIN_U_I32x4_S */
12228
    /* MIN_U_I8x16 */
12229
    V128, V128, V128, 
12230
    /* MIN_U_I8x16_S */
12231
    /* MUL_F32 */
12232
    F32, F32, F32, 
12233
    /* MUL_F32_S */
12234
    /* MUL_F32x4 */
12235
    V128, V128, V128, 
12236
    /* MUL_F32x4_S */
12237
    /* MUL_F64 */
12238
    F64, F64, F64, 
12239
    /* MUL_F64_S */
12240
    /* MUL_F64x2 */
12241
    V128, V128, V128, 
12242
    /* MUL_F64x2_S */
12243
    /* MUL_I16x8 */
12244
    V128, V128, V128, 
12245
    /* MUL_I16x8_S */
12246
    /* MUL_I32 */
12247
    I32, I32, I32, 
12248
    /* MUL_I32_S */
12249
    /* MUL_I32x4 */
12250
    V128, V128, V128, 
12251
    /* MUL_I32x4_S */
12252
    /* MUL_I64 */
12253
    I64, I64, I64, 
12254
    /* MUL_I64_S */
12255
    /* MUL_I64x2 */
12256
    V128, V128, V128, 
12257
    /* MUL_I64x2_S */
12258
    /* NARROW_S_I16x8 */
12259
    V128, V128, V128, 
12260
    /* NARROW_S_I16x8_S */
12261
    /* NARROW_S_I8x16 */
12262
    V128, V128, V128, 
12263
    /* NARROW_S_I8x16_S */
12264
    /* NARROW_U_I16x8 */
12265
    V128, V128, V128, 
12266
    /* NARROW_U_I16x8_S */
12267
    /* NARROW_U_I8x16 */
12268
    V128, V128, V128, 
12269
    /* NARROW_U_I8x16_S */
12270
    /* NEAREST_F32 */
12271
    F32, F32, 
12272
    /* NEAREST_F32_S */
12273
    /* NEAREST_F32x4 */
12274
    V128, V128, 
12275
    /* NEAREST_F32x4_S */
12276
    /* NEAREST_F64 */
12277
    F64, F64, 
12278
    /* NEAREST_F64_S */
12279
    /* NEAREST_F64x2 */
12280
    V128, V128, 
12281
    /* NEAREST_F64x2_S */
12282
    /* NEG_F32 */
12283
    F32, F32, 
12284
    /* NEG_F32_S */
12285
    /* NEG_F32x4 */
12286
    V128, V128, 
12287
    /* NEG_F32x4_S */
12288
    /* NEG_F64 */
12289
    F64, F64, 
12290
    /* NEG_F64_S */
12291
    /* NEG_F64x2 */
12292
    V128, V128, 
12293
    /* NEG_F64x2_S */
12294
    /* NEG_I16x8 */
12295
    V128, V128, 
12296
    /* NEG_I16x8_S */
12297
    /* NEG_I32x4 */
12298
    V128, V128, 
12299
    /* NEG_I32x4_S */
12300
    /* NEG_I64x2 */
12301
    V128, V128, 
12302
    /* NEG_I64x2_S */
12303
    /* NEG_I8x16 */
12304
    V128, V128, 
12305
    /* NEG_I8x16_S */
12306
    /* NE_F32 */
12307
    I32, F32, F32, 
12308
    /* NE_F32_S */
12309
    /* NE_F32x4 */
12310
    V128, V128, V128, 
12311
    /* NE_F32x4_S */
12312
    /* NE_F64 */
12313
    I32, F64, F64, 
12314
    /* NE_F64_S */
12315
    /* NE_F64x2 */
12316
    V128, V128, V128, 
12317
    /* NE_F64x2_S */
12318
    /* NE_I16x8 */
12319
    V128, V128, V128, 
12320
    /* NE_I16x8_S */
12321
    /* NE_I32 */
12322
    I32, I32, I32, 
12323
    /* NE_I32_S */
12324
    /* NE_I32x4 */
12325
    V128, V128, V128, 
12326
    /* NE_I32x4_S */
12327
    /* NE_I64 */
12328
    I32, I64, I64, 
12329
    /* NE_I64_S */
12330
    /* NE_I64x2 */
12331
    V128, V128, V128, 
12332
    /* NE_I64x2_S */
12333
    /* NE_I8x16 */
12334
    V128, V128, V128, 
12335
    /* NE_I8x16_S */
12336
    /* NMADD_F32x4 */
12337
    V128, V128, V128, V128, 
12338
    /* NMADD_F32x4_S */
12339
    /* NMADD_F64x2 */
12340
    V128, V128, V128, V128, 
12341
    /* NMADD_F64x2_S */
12342
    /* NOP */
12343
    /* NOP_S */
12344
    /* NOT */
12345
    V128, V128, 
12346
    /* NOT_S */
12347
    /* OR */
12348
    V128, V128, V128, 
12349
    /* OR_I32 */
12350
    I32, I32, I32, 
12351
    /* OR_I32_S */
12352
    /* OR_I64 */
12353
    I64, I64, I64, 
12354
    /* OR_I64_S */
12355
    /* OR_S */
12356
    /* PMAX_F32x4 */
12357
    V128, V128, V128, 
12358
    /* PMAX_F32x4_S */
12359
    /* PMAX_F64x2 */
12360
    V128, V128, V128, 
12361
    /* PMAX_F64x2_S */
12362
    /* PMIN_F32x4 */
12363
    V128, V128, V128, 
12364
    /* PMIN_F32x4_S */
12365
    /* PMIN_F64x2 */
12366
    V128, V128, V128, 
12367
    /* PMIN_F64x2_S */
12368
    /* POPCNT_I32 */
12369
    I32, I32, 
12370
    /* POPCNT_I32_S */
12371
    /* POPCNT_I64 */
12372
    I64, I64, 
12373
    /* POPCNT_I64_S */
12374
    /* POPCNT_I8x16 */
12375
    V128, V128, 
12376
    /* POPCNT_I8x16_S */
12377
    /* Q15MULR_SAT_S_I16x8 */
12378
    V128, V128, V128, 
12379
    /* Q15MULR_SAT_S_I16x8_S */
12380
    /* REF_IS_NULL_EXTERNREF */
12381
    I32, EXTERNREF, 
12382
    /* REF_IS_NULL_EXTERNREF_S */
12383
    /* REF_IS_NULL_FUNCREF */
12384
    I32, FUNCREF, 
12385
    /* REF_IS_NULL_FUNCREF_S */
12386
    /* REF_NULL_EXTERNREF */
12387
    EXTERNREF, 
12388
    /* REF_NULL_EXTERNREF_S */
12389
    /* REF_NULL_FUNCREF */
12390
    FUNCREF, 
12391
    /* REF_NULL_FUNCREF_S */
12392
    /* RELAXED_DOT */
12393
    V128, V128, V128, 
12394
    /* RELAXED_DOT_ADD */
12395
    V128, V128, V128, V128, 
12396
    /* RELAXED_DOT_ADD_S */
12397
    /* RELAXED_DOT_BFLOAT */
12398
    V128, V128, V128, V128, 
12399
    /* RELAXED_DOT_BFLOAT_S */
12400
    /* RELAXED_DOT_S */
12401
    /* RELAXED_Q15MULR_S_I16x8 */
12402
    V128, V128, V128, 
12403
    /* RELAXED_Q15MULR_S_I16x8_S */
12404
    /* RELAXED_SWIZZLE */
12405
    V128, V128, V128, 
12406
    /* RELAXED_SWIZZLE_S */
12407
    /* REM_S_I32 */
12408
    I32, I32, I32, 
12409
    /* REM_S_I32_S */
12410
    /* REM_S_I64 */
12411
    I64, I64, I64, 
12412
    /* REM_S_I64_S */
12413
    /* REM_U_I32 */
12414
    I32, I32, I32, 
12415
    /* REM_U_I32_S */
12416
    /* REM_U_I64 */
12417
    I64, I64, I64, 
12418
    /* REM_U_I64_S */
12419
    /* REPLACE_LANE_F32x4 */
12420
    V128, V128, vec_i8imm_op, F32, 
12421
    /* REPLACE_LANE_F32x4_S */
12422
    vec_i8imm_op, 
12423
    /* REPLACE_LANE_F64x2 */
12424
    V128, V128, vec_i8imm_op, F64, 
12425
    /* REPLACE_LANE_F64x2_S */
12426
    vec_i8imm_op, 
12427
    /* REPLACE_LANE_I16x8 */
12428
    V128, V128, vec_i8imm_op, I32, 
12429
    /* REPLACE_LANE_I16x8_S */
12430
    vec_i8imm_op, 
12431
    /* REPLACE_LANE_I32x4 */
12432
    V128, V128, vec_i8imm_op, I32, 
12433
    /* REPLACE_LANE_I32x4_S */
12434
    vec_i8imm_op, 
12435
    /* REPLACE_LANE_I64x2 */
12436
    V128, V128, vec_i8imm_op, I64, 
12437
    /* REPLACE_LANE_I64x2_S */
12438
    vec_i8imm_op, 
12439
    /* REPLACE_LANE_I8x16 */
12440
    V128, V128, vec_i8imm_op, I32, 
12441
    /* REPLACE_LANE_I8x16_S */
12442
    vec_i8imm_op, 
12443
    /* RETHROW */
12444
    i32imm, 
12445
    /* RETHROW_S */
12446
    i32imm, 
12447
    /* RETURN */
12448
    /* RETURN_S */
12449
    /* RET_CALL */
12450
    function32_op, 
12451
    /* RET_CALL_INDIRECT */
12452
    TypeIndex, table32_op, 
12453
    /* RET_CALL_INDIRECT_S */
12454
    TypeIndex, table32_op, 
12455
    /* RET_CALL_S */
12456
    function32_op, 
12457
    /* ROTL_I32 */
12458
    I32, I32, I32, 
12459
    /* ROTL_I32_S */
12460
    /* ROTL_I64 */
12461
    I64, I64, I64, 
12462
    /* ROTL_I64_S */
12463
    /* ROTR_I32 */
12464
    I32, I32, I32, 
12465
    /* ROTR_I32_S */
12466
    /* ROTR_I64 */
12467
    I64, I64, I64, 
12468
    /* ROTR_I64_S */
12469
    /* SELECT_EXTERNREF */
12470
    EXTERNREF, EXTERNREF, EXTERNREF, I32, 
12471
    /* SELECT_EXTERNREF_S */
12472
    /* SELECT_F32 */
12473
    F32, F32, F32, I32, 
12474
    /* SELECT_F32_S */
12475
    /* SELECT_F64 */
12476
    F64, F64, F64, I32, 
12477
    /* SELECT_F64_S */
12478
    /* SELECT_FUNCREF */
12479
    FUNCREF, FUNCREF, FUNCREF, I32, 
12480
    /* SELECT_FUNCREF_S */
12481
    /* SELECT_I32 */
12482
    I32, I32, I32, I32, 
12483
    /* SELECT_I32_S */
12484
    /* SELECT_I64 */
12485
    I64, I64, I64, I32, 
12486
    /* SELECT_I64_S */
12487
    /* SELECT_V128 */
12488
    V128, V128, V128, I32, 
12489
    /* SELECT_V128_S */
12490
    /* SHL_I16x8 */
12491
    V128, V128, I32, 
12492
    /* SHL_I16x8_S */
12493
    /* SHL_I32 */
12494
    I32, I32, I32, 
12495
    /* SHL_I32_S */
12496
    /* SHL_I32x4 */
12497
    V128, V128, I32, 
12498
    /* SHL_I32x4_S */
12499
    /* SHL_I64 */
12500
    I64, I64, I64, 
12501
    /* SHL_I64_S */
12502
    /* SHL_I64x2 */
12503
    V128, V128, I32, 
12504
    /* SHL_I64x2_S */
12505
    /* SHL_I8x16 */
12506
    V128, V128, I32, 
12507
    /* SHL_I8x16_S */
12508
    /* SHR_S_I16x8 */
12509
    V128, V128, I32, 
12510
    /* SHR_S_I16x8_S */
12511
    /* SHR_S_I32 */
12512
    I32, I32, I32, 
12513
    /* SHR_S_I32_S */
12514
    /* SHR_S_I32x4 */
12515
    V128, V128, I32, 
12516
    /* SHR_S_I32x4_S */
12517
    /* SHR_S_I64 */
12518
    I64, I64, I64, 
12519
    /* SHR_S_I64_S */
12520
    /* SHR_S_I64x2 */
12521
    V128, V128, I32, 
12522
    /* SHR_S_I64x2_S */
12523
    /* SHR_S_I8x16 */
12524
    V128, V128, I32, 
12525
    /* SHR_S_I8x16_S */
12526
    /* SHR_U_I16x8 */
12527
    V128, V128, I32, 
12528
    /* SHR_U_I16x8_S */
12529
    /* SHR_U_I32 */
12530
    I32, I32, I32, 
12531
    /* SHR_U_I32_S */
12532
    /* SHR_U_I32x4 */
12533
    V128, V128, I32, 
12534
    /* SHR_U_I32x4_S */
12535
    /* SHR_U_I64 */
12536
    I64, I64, I64, 
12537
    /* SHR_U_I64_S */
12538
    /* SHR_U_I64x2 */
12539
    V128, V128, I32, 
12540
    /* SHR_U_I64x2_S */
12541
    /* SHR_U_I8x16 */
12542
    V128, V128, I32, 
12543
    /* SHR_U_I8x16_S */
12544
    /* SHUFFLE */
12545
    V128, V128, V128, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, 
12546
    /* SHUFFLE_S */
12547
    vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, 
12548
    /* SIMD_RELAXED_FMAX_F32x4 */
12549
    V128, V128, V128, 
12550
    /* SIMD_RELAXED_FMAX_F32x4_S */
12551
    /* SIMD_RELAXED_FMAX_F64x2 */
12552
    V128, V128, V128, 
12553
    /* SIMD_RELAXED_FMAX_F64x2_S */
12554
    /* SIMD_RELAXED_FMIN_F32x4 */
12555
    V128, V128, V128, 
12556
    /* SIMD_RELAXED_FMIN_F32x4_S */
12557
    /* SIMD_RELAXED_FMIN_F64x2 */
12558
    V128, V128, V128, 
12559
    /* SIMD_RELAXED_FMIN_F64x2_S */
12560
    /* SPLAT_F32x4 */
12561
    V128, F32, 
12562
    /* SPLAT_F32x4_S */
12563
    /* SPLAT_F64x2 */
12564
    V128, F64, 
12565
    /* SPLAT_F64x2_S */
12566
    /* SPLAT_I16x8 */
12567
    V128, I32, 
12568
    /* SPLAT_I16x8_S */
12569
    /* SPLAT_I32x4 */
12570
    V128, I32, 
12571
    /* SPLAT_I32x4_S */
12572
    /* SPLAT_I64x2 */
12573
    V128, I64, 
12574
    /* SPLAT_I64x2_S */
12575
    /* SPLAT_I8x16 */
12576
    V128, I32, 
12577
    /* SPLAT_I8x16_S */
12578
    /* SQRT_F32 */
12579
    F32, F32, 
12580
    /* SQRT_F32_S */
12581
    /* SQRT_F32x4 */
12582
    V128, V128, 
12583
    /* SQRT_F32x4_S */
12584
    /* SQRT_F64 */
12585
    F64, F64, 
12586
    /* SQRT_F64_S */
12587
    /* SQRT_F64x2 */
12588
    V128, V128, 
12589
    /* SQRT_F64x2_S */
12590
    /* STORE16_I32_A32 */
12591
    P2Align, offset32_op, I32, I32, 
12592
    /* STORE16_I32_A32_S */
12593
    P2Align, offset32_op, 
12594
    /* STORE16_I32_A64 */
12595
    P2Align, offset64_op, I64, I32, 
12596
    /* STORE16_I32_A64_S */
12597
    P2Align, offset64_op, 
12598
    /* STORE16_I64_A32 */
12599
    P2Align, offset32_op, I32, I64, 
12600
    /* STORE16_I64_A32_S */
12601
    P2Align, offset32_op, 
12602
    /* STORE16_I64_A64 */
12603
    P2Align, offset64_op, I64, I64, 
12604
    /* STORE16_I64_A64_S */
12605
    P2Align, offset64_op, 
12606
    /* STORE32_I64_A32 */
12607
    P2Align, offset32_op, I32, I64, 
12608
    /* STORE32_I64_A32_S */
12609
    P2Align, offset32_op, 
12610
    /* STORE32_I64_A64 */
12611
    P2Align, offset64_op, I64, I64, 
12612
    /* STORE32_I64_A64_S */
12613
    P2Align, offset64_op, 
12614
    /* STORE8_I32_A32 */
12615
    P2Align, offset32_op, I32, I32, 
12616
    /* STORE8_I32_A32_S */
12617
    P2Align, offset32_op, 
12618
    /* STORE8_I32_A64 */
12619
    P2Align, offset64_op, I64, I32, 
12620
    /* STORE8_I32_A64_S */
12621
    P2Align, offset64_op, 
12622
    /* STORE8_I64_A32 */
12623
    P2Align, offset32_op, I32, I64, 
12624
    /* STORE8_I64_A32_S */
12625
    P2Align, offset32_op, 
12626
    /* STORE8_I64_A64 */
12627
    P2Align, offset64_op, I64, I64, 
12628
    /* STORE8_I64_A64_S */
12629
    P2Align, offset64_op, 
12630
    /* STORE_F32_A32 */
12631
    P2Align, offset32_op, I32, F32, 
12632
    /* STORE_F32_A32_S */
12633
    P2Align, offset32_op, 
12634
    /* STORE_F32_A64 */
12635
    P2Align, offset64_op, I64, F32, 
12636
    /* STORE_F32_A64_S */
12637
    P2Align, offset64_op, 
12638
    /* STORE_F64_A32 */
12639
    P2Align, offset32_op, I32, F64, 
12640
    /* STORE_F64_A32_S */
12641
    P2Align, offset32_op, 
12642
    /* STORE_F64_A64 */
12643
    P2Align, offset64_op, I64, F64, 
12644
    /* STORE_F64_A64_S */
12645
    P2Align, offset64_op, 
12646
    /* STORE_I32_A32 */
12647
    P2Align, offset32_op, I32, I32, 
12648
    /* STORE_I32_A32_S */
12649
    P2Align, offset32_op, 
12650
    /* STORE_I32_A64 */
12651
    P2Align, offset64_op, I64, I32, 
12652
    /* STORE_I32_A64_S */
12653
    P2Align, offset64_op, 
12654
    /* STORE_I64_A32 */
12655
    P2Align, offset32_op, I32, I64, 
12656
    /* STORE_I64_A32_S */
12657
    P2Align, offset32_op, 
12658
    /* STORE_I64_A64 */
12659
    P2Align, offset64_op, I64, I64, 
12660
    /* STORE_I64_A64_S */
12661
    P2Align, offset64_op, 
12662
    /* STORE_LANE_I16x8_A32 */
12663
    P2Align, offset32_op, vec_i8imm_op, I32, V128, 
12664
    /* STORE_LANE_I16x8_A32_S */
12665
    P2Align, offset32_op, vec_i8imm_op, 
12666
    /* STORE_LANE_I16x8_A64 */
12667
    P2Align, offset64_op, vec_i8imm_op, I64, V128, 
12668
    /* STORE_LANE_I16x8_A64_S */
12669
    P2Align, offset64_op, vec_i8imm_op, 
12670
    /* STORE_LANE_I32x4_A32 */
12671
    P2Align, offset32_op, vec_i8imm_op, I32, V128, 
12672
    /* STORE_LANE_I32x4_A32_S */
12673
    P2Align, offset32_op, vec_i8imm_op, 
12674
    /* STORE_LANE_I32x4_A64 */
12675
    P2Align, offset64_op, vec_i8imm_op, I64, V128, 
12676
    /* STORE_LANE_I32x4_A64_S */
12677
    P2Align, offset64_op, vec_i8imm_op, 
12678
    /* STORE_LANE_I64x2_A32 */
12679
    P2Align, offset32_op, vec_i8imm_op, I32, V128, 
12680
    /* STORE_LANE_I64x2_A32_S */
12681
    P2Align, offset32_op, vec_i8imm_op, 
12682
    /* STORE_LANE_I64x2_A64 */
12683
    P2Align, offset64_op, vec_i8imm_op, I64, V128, 
12684
    /* STORE_LANE_I64x2_A64_S */
12685
    P2Align, offset64_op, vec_i8imm_op, 
12686
    /* STORE_LANE_I8x16_A32 */
12687
    P2Align, offset32_op, vec_i8imm_op, I32, V128, 
12688
    /* STORE_LANE_I8x16_A32_S */
12689
    P2Align, offset32_op, vec_i8imm_op, 
12690
    /* STORE_LANE_I8x16_A64 */
12691
    P2Align, offset64_op, vec_i8imm_op, I64, V128, 
12692
    /* STORE_LANE_I8x16_A64_S */
12693
    P2Align, offset64_op, vec_i8imm_op, 
12694
    /* STORE_V128_A32 */
12695
    P2Align, offset32_op, I32, V128, 
12696
    /* STORE_V128_A32_S */
12697
    P2Align, offset32_op, 
12698
    /* STORE_V128_A64 */
12699
    P2Align, offset64_op, I64, V128, 
12700
    /* STORE_V128_A64_S */
12701
    P2Align, offset64_op, 
12702
    /* SUB_F32 */
12703
    F32, F32, F32, 
12704
    /* SUB_F32_S */
12705
    /* SUB_F32x4 */
12706
    V128, V128, V128, 
12707
    /* SUB_F32x4_S */
12708
    /* SUB_F64 */
12709
    F64, F64, F64, 
12710
    /* SUB_F64_S */
12711
    /* SUB_F64x2 */
12712
    V128, V128, V128, 
12713
    /* SUB_F64x2_S */
12714
    /* SUB_I16x8 */
12715
    V128, V128, V128, 
12716
    /* SUB_I16x8_S */
12717
    /* SUB_I32 */
12718
    I32, I32, I32, 
12719
    /* SUB_I32_S */
12720
    /* SUB_I32x4 */
12721
    V128, V128, V128, 
12722
    /* SUB_I32x4_S */
12723
    /* SUB_I64 */
12724
    I64, I64, I64, 
12725
    /* SUB_I64_S */
12726
    /* SUB_I64x2 */
12727
    V128, V128, V128, 
12728
    /* SUB_I64x2_S */
12729
    /* SUB_I8x16 */
12730
    V128, V128, V128, 
12731
    /* SUB_I8x16_S */
12732
    /* SUB_SAT_S_I16x8 */
12733
    V128, V128, V128, 
12734
    /* SUB_SAT_S_I16x8_S */
12735
    /* SUB_SAT_S_I8x16 */
12736
    V128, V128, V128, 
12737
    /* SUB_SAT_S_I8x16_S */
12738
    /* SUB_SAT_U_I16x8 */
12739
    V128, V128, V128, 
12740
    /* SUB_SAT_U_I16x8_S */
12741
    /* SUB_SAT_U_I8x16 */
12742
    V128, V128, V128, 
12743
    /* SUB_SAT_U_I8x16_S */
12744
    /* SWIZZLE */
12745
    V128, V128, V128, 
12746
    /* SWIZZLE_S */
12747
    /* TABLE_COPY */
12748
    table32_op, table32_op, I32, I32, I32, 
12749
    /* TABLE_COPY_S */
12750
    table32_op, table32_op, 
12751
    /* TABLE_FILL_EXTERNREF */
12752
    table32_op, I32, EXTERNREF, I32, 
12753
    /* TABLE_FILL_EXTERNREF_S */
12754
    table32_op, 
12755
    /* TABLE_FILL_FUNCREF */
12756
    table32_op, I32, FUNCREF, I32, 
12757
    /* TABLE_FILL_FUNCREF_S */
12758
    table32_op, 
12759
    /* TABLE_GET_EXTERNREF */
12760
    EXTERNREF, table32_op, I32, 
12761
    /* TABLE_GET_EXTERNREF_S */
12762
    table32_op, 
12763
    /* TABLE_GET_FUNCREF */
12764
    FUNCREF, table32_op, I32, 
12765
    /* TABLE_GET_FUNCREF_S */
12766
    table32_op, 
12767
    /* TABLE_GROW_EXTERNREF */
12768
    I32, table32_op, EXTERNREF, I32, 
12769
    /* TABLE_GROW_EXTERNREF_S */
12770
    table32_op, 
12771
    /* TABLE_GROW_FUNCREF */
12772
    I32, table32_op, FUNCREF, I32, 
12773
    /* TABLE_GROW_FUNCREF_S */
12774
    table32_op, 
12775
    /* TABLE_SET_EXTERNREF */
12776
    table32_op, I32, EXTERNREF, 
12777
    /* TABLE_SET_EXTERNREF_S */
12778
    table32_op, 
12779
    /* TABLE_SET_FUNCREF */
12780
    table32_op, I32, FUNCREF, 
12781
    /* TABLE_SET_FUNCREF_S */
12782
    table32_op, 
12783
    /* TABLE_SIZE */
12784
    I32, table32_op, 
12785
    /* TABLE_SIZE_S */
12786
    table32_op, 
12787
    /* TEE_EXTERNREF */
12788
    EXTERNREF, EXTERNREF, EXTERNREF, 
12789
    /* TEE_EXTERNREF_S */
12790
    /* TEE_F32 */
12791
    F32, F32, F32, 
12792
    /* TEE_F32_S */
12793
    /* TEE_F64 */
12794
    F64, F64, F64, 
12795
    /* TEE_F64_S */
12796
    /* TEE_FUNCREF */
12797
    FUNCREF, FUNCREF, FUNCREF, 
12798
    /* TEE_FUNCREF_S */
12799
    /* TEE_I32 */
12800
    I32, I32, I32, 
12801
    /* TEE_I32_S */
12802
    /* TEE_I64 */
12803
    I64, I64, I64, 
12804
    /* TEE_I64_S */
12805
    /* TEE_V128 */
12806
    V128, V128, V128, 
12807
    /* TEE_V128_S */
12808
    /* THROW */
12809
    tag_op, 
12810
    /* THROW_S */
12811
    tag_op, 
12812
    /* TRUNC_F32 */
12813
    F32, F32, 
12814
    /* TRUNC_F32_S */
12815
    /* TRUNC_F32x4 */
12816
    V128, V128, 
12817
    /* TRUNC_F32x4_S */
12818
    /* TRUNC_F64 */
12819
    F64, F64, 
12820
    /* TRUNC_F64_S */
12821
    /* TRUNC_F64x2 */
12822
    V128, V128, 
12823
    /* TRUNC_F64x2_S */
12824
    /* TRY */
12825
    Signature, 
12826
    /* TRY_S */
12827
    Signature, 
12828
    /* UNREACHABLE */
12829
    /* UNREACHABLE_S */
12830
    /* XOR */
12831
    V128, V128, V128, 
12832
    /* XOR_I32 */
12833
    I32, I32, I32, 
12834
    /* XOR_I32_S */
12835
    /* XOR_I64 */
12836
    I64, I64, I64, 
12837
    /* XOR_I64_S */
12838
    /* XOR_S */
12839
    /* anonymous_7277MEMORY_GROW_A32 */
12840
    I32, i32imm, I32, 
12841
    /* anonymous_7277MEMORY_GROW_A32_S */
12842
    i32imm, 
12843
    /* anonymous_7277MEMORY_SIZE_A32 */
12844
    I32, i32imm, 
12845
    /* anonymous_7277MEMORY_SIZE_A32_S */
12846
    i32imm, 
12847
    /* anonymous_7278MEMORY_GROW_A64 */
12848
    I64, i32imm, I64, 
12849
    /* anonymous_7278MEMORY_GROW_A64_S */
12850
    i32imm, 
12851
    /* anonymous_7278MEMORY_SIZE_A64 */
12852
    I64, i32imm, 
12853
    /* anonymous_7278MEMORY_SIZE_A64_S */
12854
    i32imm, 
12855
    /* anonymous_7959DATA_DROP */
12856
    i32imm_op, 
12857
    /* anonymous_7959DATA_DROP_S */
12858
    i32imm_op, 
12859
    /* anonymous_7959MEMORY_COPY_A32 */
12860
    i32imm_op, i32imm_op, I32, I32, I32, 
12861
    /* anonymous_7959MEMORY_COPY_A32_S */
12862
    i32imm_op, i32imm_op, 
12863
    /* anonymous_7959MEMORY_FILL_A32 */
12864
    i32imm_op, I32, I32, I32, 
12865
    /* anonymous_7959MEMORY_FILL_A32_S */
12866
    i32imm_op, 
12867
    /* anonymous_7959MEMORY_INIT_A32 */
12868
    i32imm_op, i32imm_op, I32, I32, I32, 
12869
    /* anonymous_7959MEMORY_INIT_A32_S */
12870
    i32imm_op, i32imm_op, 
12871
    /* anonymous_7960DATA_DROP */
12872
    i32imm_op, 
12873
    /* anonymous_7960DATA_DROP_S */
12874
    i32imm_op, 
12875
    /* anonymous_7960MEMORY_COPY_A64 */
12876
    i32imm_op, i32imm_op, I64, I64, I64, 
12877
    /* anonymous_7960MEMORY_COPY_A64_S */
12878
    i32imm_op, i32imm_op, 
12879
    /* anonymous_7960MEMORY_FILL_A64 */
12880
    i32imm_op, I64, I32, I64, 
12881
    /* anonymous_7960MEMORY_FILL_A64_S */
12882
    i32imm_op, 
12883
    /* anonymous_7960MEMORY_INIT_A64 */
12884
    i32imm_op, i32imm_op, I64, I32, I32, 
12885
    /* anonymous_7960MEMORY_INIT_A64_S */
12886
    i32imm_op, i32imm_op, 
12887
    /* convert_low_s_F64x2 */
12888
    V128, V128, 
12889
    /* convert_low_s_F64x2_S */
12890
    /* convert_low_u_F64x2 */
12891
    V128, V128, 
12892
    /* convert_low_u_F64x2_S */
12893
    /* demote_zero_F32x4 */
12894
    V128, V128, 
12895
    /* demote_zero_F32x4_S */
12896
    /* extend_high_s_I16x8 */
12897
    V128, V128, 
12898
    /* extend_high_s_I16x8_S */
12899
    /* extend_high_s_I32x4 */
12900
    V128, V128, 
12901
    /* extend_high_s_I32x4_S */
12902
    /* extend_high_s_I64x2 */
12903
    V128, V128, 
12904
    /* extend_high_s_I64x2_S */
12905
    /* extend_high_u_I16x8 */
12906
    V128, V128, 
12907
    /* extend_high_u_I16x8_S */
12908
    /* extend_high_u_I32x4 */
12909
    V128, V128, 
12910
    /* extend_high_u_I32x4_S */
12911
    /* extend_high_u_I64x2 */
12912
    V128, V128, 
12913
    /* extend_high_u_I64x2_S */
12914
    /* extend_low_s_I16x8 */
12915
    V128, V128, 
12916
    /* extend_low_s_I16x8_S */
12917
    /* extend_low_s_I32x4 */
12918
    V128, V128, 
12919
    /* extend_low_s_I32x4_S */
12920
    /* extend_low_s_I64x2 */
12921
    V128, V128, 
12922
    /* extend_low_s_I64x2_S */
12923
    /* extend_low_u_I16x8 */
12924
    V128, V128, 
12925
    /* extend_low_u_I16x8_S */
12926
    /* extend_low_u_I32x4 */
12927
    V128, V128, 
12928
    /* extend_low_u_I32x4_S */
12929
    /* extend_low_u_I64x2 */
12930
    V128, V128, 
12931
    /* extend_low_u_I64x2_S */
12932
    /* fp_to_sint_I32x4 */
12933
    V128, V128, 
12934
    /* fp_to_sint_I32x4_S */
12935
    /* fp_to_uint_I32x4 */
12936
    V128, V128, 
12937
    /* fp_to_uint_I32x4_S */
12938
    /* int_wasm_extadd_pairwise_signed_I16x8 */
12939
    V128, V128, 
12940
    /* int_wasm_extadd_pairwise_signed_I16x8_S */
12941
    /* int_wasm_extadd_pairwise_signed_I32x4 */
12942
    V128, V128, 
12943
    /* int_wasm_extadd_pairwise_signed_I32x4_S */
12944
    /* int_wasm_extadd_pairwise_unsigned_I16x8 */
12945
    V128, V128, 
12946
    /* int_wasm_extadd_pairwise_unsigned_I16x8_S */
12947
    /* int_wasm_extadd_pairwise_unsigned_I32x4 */
12948
    V128, V128, 
12949
    /* int_wasm_extadd_pairwise_unsigned_I32x4_S */
12950
    /* int_wasm_relaxed_trunc_signed_I32x4 */
12951
    V128, V128, 
12952
    /* int_wasm_relaxed_trunc_signed_I32x4_S */
12953
    /* int_wasm_relaxed_trunc_signed_zero_I32x4 */
12954
    V128, V128, 
12955
    /* int_wasm_relaxed_trunc_signed_zero_I32x4_S */
12956
    /* int_wasm_relaxed_trunc_unsigned_I32x4 */
12957
    V128, V128, 
12958
    /* int_wasm_relaxed_trunc_unsigned_I32x4_S */
12959
    /* int_wasm_relaxed_trunc_unsigned_zero_I32x4 */
12960
    V128, V128, 
12961
    /* int_wasm_relaxed_trunc_unsigned_zero_I32x4_S */
12962
    /* promote_low_F64x2 */
12963
    V128, V128, 
12964
    /* promote_low_F64x2_S */
12965
    /* sint_to_fp_F32x4 */
12966
    V128, V128, 
12967
    /* sint_to_fp_F32x4_S */
12968
    /* trunc_sat_zero_s_I32x4 */
12969
    V128, V128, 
12970
    /* trunc_sat_zero_s_I32x4_S */
12971
    /* trunc_sat_zero_u_I32x4 */
12972
    V128, V128, 
12973
    /* trunc_sat_zero_u_I32x4_S */
12974
    /* uint_to_fp_F32x4 */
12975
    V128, V128, 
12976
  };
12977
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
12978
}
12979
} // end namespace WebAssembly
12980
} // end namespace llvm
12981
#endif // GET_INSTRINFO_OPERAND_TYPE
12982
12983
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
12984
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
12985
namespace llvm {
12986
namespace WebAssembly {
12987
LLVM_READONLY
12988
static int getMemOperandSize(int OpType) {
12989
  switch (OpType) {
12990
  default: return 0;
12991
  }
12992
}
12993
} // end namespace WebAssembly
12994
} // end namespace llvm
12995
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
12996
12997
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
12998
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
12999
namespace llvm {
13000
namespace WebAssembly {
13001
LLVM_READONLY static unsigned
13002
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
13003
  return LogicalOpIdx;
13004
}
13005
LLVM_READONLY static inline unsigned
13006
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
13007
  auto S = 0U;
13008
  for (auto i = 0U; i < LogicalOpIdx; ++i)
13009
    S += getLogicalOperandSize(Opcode, i);
13010
  return S;
13011
}
13012
} // end namespace WebAssembly
13013
} // end namespace llvm
13014
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
13015
13016
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
13017
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
13018
namespace llvm {
13019
namespace WebAssembly {
13020
LLVM_READONLY static int
13021
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
13022
  return -1;
13023
}
13024
} // end namespace WebAssembly
13025
} // end namespace llvm
13026
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
13027
13028
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
13029
#undef GET_INSTRINFO_MC_HELPER_DECLS
13030
13031
namespace llvm {
13032
class MCInst;
13033
class FeatureBitset;
13034
13035
namespace WebAssembly_MC {
13036
13037
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
13038
13039
} // end namespace WebAssembly_MC
13040
} // end namespace llvm
13041
13042
#endif // GET_INSTRINFO_MC_HELPER_DECLS
13043
13044
#ifdef GET_INSTRINFO_MC_HELPERS
13045
#undef GET_INSTRINFO_MC_HELPERS
13046
13047
namespace llvm {
13048
namespace WebAssembly_MC {
13049
13050
} // end namespace WebAssembly_MC
13051
} // end namespace llvm
13052
13053
#endif // GET_GENISTRINFO_MC_HELPERS
13054
13055
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
13056
    defined(GET_AVAILABLE_OPCODE_CHECKER)
13057
#define GET_COMPUTE_FEATURES
13058
#endif
13059
#ifdef GET_COMPUTE_FEATURES
13060
#undef GET_COMPUTE_FEATURES
13061
namespace llvm {
13062
namespace WebAssembly_MC {
13063
13064
// Bits for subtarget features that participate in instruction matching.
13065
enum SubtargetFeatureBits : uint8_t {
13066
  Feature_HasSIMD128Bit = 9,
13067
  Feature_HasRelaxedSIMDBit = 8,
13068
  Feature_HasAtomicsBit = 0,
13069
  Feature_HasMultivalueBit = 5,
13070
  Feature_HasNontrappingFPToIntBit = 6,
13071
  Feature_NotHasNontrappingFPToIntBit = 12,
13072
  Feature_HasSignExtBit = 10,
13073
  Feature_HasTailCallBit = 11,
13074
  Feature_HasExceptionHandlingBit = 2,
13075
  Feature_HasBulkMemoryBit = 1,
13076
  Feature_HasReferenceTypesBit = 7,
13077
  Feature_HasExtendedConstBit = 3,
13078
  Feature_HasMultiMemoryBit = 4,
13079
};
13080
13081
102k
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
13082
102k
  FeatureBitset Features;
13083
102k
  if (FB[WebAssembly::FeatureSIMD128])
13084
0
    Features.set(Feature_HasSIMD128Bit);
13085
102k
  if (FB[WebAssembly::FeatureRelaxedSIMD])
13086
0
    Features.set(Feature_HasRelaxedSIMDBit);
13087
102k
  if (FB[WebAssembly::FeatureAtomics])
13088
0
    Features.set(Feature_HasAtomicsBit);
13089
102k
  if (FB[WebAssembly::FeatureMultivalue])
13090
0
    Features.set(Feature_HasMultivalueBit);
13091
102k
  if (FB[WebAssembly::FeatureNontrappingFPToInt])
13092
0
    Features.set(Feature_HasNontrappingFPToIntBit);
13093
102k
  if (!FB[WebAssembly::FeatureNontrappingFPToInt])
13094
102k
    Features.set(Feature_NotHasNontrappingFPToIntBit);
13095
102k
  if (FB[WebAssembly::FeatureSignExt])
13096
102k
    Features.set(Feature_HasSignExtBit);
13097
102k
  if (FB[WebAssembly::FeatureTailCall])
13098
0
    Features.set(Feature_HasTailCallBit);
13099
102k
  if (FB[WebAssembly::FeatureExceptionHandling])
13100
0
    Features.set(Feature_HasExceptionHandlingBit);
13101
102k
  if (FB[WebAssembly::FeatureBulkMemory])
13102
0
    Features.set(Feature_HasBulkMemoryBit);
13103
102k
  if (FB[WebAssembly::FeatureReferenceTypes])
13104
0
    Features.set(Feature_HasReferenceTypesBit);
13105
102k
  if (FB[WebAssembly::FeatureExtendedConst])
13106
0
    Features.set(Feature_HasExtendedConstBit);
13107
102k
  if (FB[WebAssembly::FeatureMultiMemory])
13108
0
    Features.set(Feature_HasMultiMemoryBit);
13109
102k
  return Features;
13110
102k
}
13111
13112
102k
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
13113
102k
  enum : uint8_t {
13114
102k
    CEFBS_None,
13115
102k
    CEFBS_HasAtomics,
13116
102k
    CEFBS_HasBulkMemory,
13117
102k
    CEFBS_HasExceptionHandling,
13118
102k
    CEFBS_HasNontrappingFPToInt,
13119
102k
    CEFBS_HasReferenceTypes,
13120
102k
    CEFBS_HasRelaxedSIMD,
13121
102k
    CEFBS_HasSIMD128,
13122
102k
    CEFBS_HasSignExt,
13123
102k
    CEFBS_HasTailCall,
13124
102k
    CEFBS_NotHasNontrappingFPToInt,
13125
102k
  };
13126
13127
102k
  static constexpr FeatureBitset FeatureBitsets[] = {
13128
102k
    {}, // CEFBS_None
13129
102k
    {Feature_HasAtomicsBit, },
13130
102k
    {Feature_HasBulkMemoryBit, },
13131
102k
    {Feature_HasExceptionHandlingBit, },
13132
102k
    {Feature_HasNontrappingFPToIntBit, },
13133
102k
    {Feature_HasReferenceTypesBit, },
13134
102k
    {Feature_HasRelaxedSIMDBit, },
13135
102k
    {Feature_HasSIMD128Bit, },
13136
102k
    {Feature_HasSignExtBit, },
13137
102k
    {Feature_HasTailCallBit, },
13138
102k
    {Feature_NotHasNontrappingFPToIntBit, },
13139
102k
  };
13140
102k
  static constexpr uint8_t RequiredFeaturesRefs[] = {
13141
102k
    CEFBS_None, // PHI = 0
13142
102k
    CEFBS_None, // INLINEASM = 1
13143
102k
    CEFBS_None, // INLINEASM_BR = 2
13144
102k
    CEFBS_None, // CFI_INSTRUCTION = 3
13145
102k
    CEFBS_None, // EH_LABEL = 4
13146
102k
    CEFBS_None, // GC_LABEL = 5
13147
102k
    CEFBS_None, // ANNOTATION_LABEL = 6
13148
102k
    CEFBS_None, // KILL = 7
13149
102k
    CEFBS_None, // EXTRACT_SUBREG = 8
13150
102k
    CEFBS_None, // INSERT_SUBREG = 9
13151
102k
    CEFBS_None, // IMPLICIT_DEF = 10
13152
102k
    CEFBS_None, // SUBREG_TO_REG = 11
13153
102k
    CEFBS_None, // COPY_TO_REGCLASS = 12
13154
102k
    CEFBS_None, // DBG_VALUE = 13
13155
102k
    CEFBS_None, // DBG_VALUE_LIST = 14
13156
102k
    CEFBS_None, // DBG_INSTR_REF = 15
13157
102k
    CEFBS_None, // DBG_PHI = 16
13158
102k
    CEFBS_None, // DBG_LABEL = 17
13159
102k
    CEFBS_None, // REG_SEQUENCE = 18
13160
102k
    CEFBS_None, // COPY = 19
13161
102k
    CEFBS_None, // BUNDLE = 20
13162
102k
    CEFBS_None, // LIFETIME_START = 21
13163
102k
    CEFBS_None, // LIFETIME_END = 22
13164
102k
    CEFBS_None, // PSEUDO_PROBE = 23
13165
102k
    CEFBS_None, // ARITH_FENCE = 24
13166
102k
    CEFBS_None, // STACKMAP = 25
13167
102k
    CEFBS_None, // FENTRY_CALL = 26
13168
102k
    CEFBS_None, // PATCHPOINT = 27
13169
102k
    CEFBS_None, // LOAD_STACK_GUARD = 28
13170
102k
    CEFBS_None, // PREALLOCATED_SETUP = 29
13171
102k
    CEFBS_None, // PREALLOCATED_ARG = 30
13172
102k
    CEFBS_None, // STATEPOINT = 31
13173
102k
    CEFBS_None, // LOCAL_ESCAPE = 32
13174
102k
    CEFBS_None, // FAULTING_OP = 33
13175
102k
    CEFBS_None, // PATCHABLE_OP = 34
13176
102k
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
13177
102k
    CEFBS_None, // PATCHABLE_RET = 36
13178
102k
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
13179
102k
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
13180
102k
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
13181
102k
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
13182
102k
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
13183
102k
    CEFBS_None, // MEMBARRIER = 42
13184
102k
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
13185
102k
    CEFBS_None, // G_ASSERT_SEXT = 44
13186
102k
    CEFBS_None, // G_ASSERT_ZEXT = 45
13187
102k
    CEFBS_None, // G_ASSERT_ALIGN = 46
13188
102k
    CEFBS_None, // G_ADD = 47
13189
102k
    CEFBS_None, // G_SUB = 48
13190
102k
    CEFBS_None, // G_MUL = 49
13191
102k
    CEFBS_None, // G_SDIV = 50
13192
102k
    CEFBS_None, // G_UDIV = 51
13193
102k
    CEFBS_None, // G_SREM = 52
13194
102k
    CEFBS_None, // G_UREM = 53
13195
102k
    CEFBS_None, // G_SDIVREM = 54
13196
102k
    CEFBS_None, // G_UDIVREM = 55
13197
102k
    CEFBS_None, // G_AND = 56
13198
102k
    CEFBS_None, // G_OR = 57
13199
102k
    CEFBS_None, // G_XOR = 58
13200
102k
    CEFBS_None, // G_IMPLICIT_DEF = 59
13201
102k
    CEFBS_None, // G_PHI = 60
13202
102k
    CEFBS_None, // G_FRAME_INDEX = 61
13203
102k
    CEFBS_None, // G_GLOBAL_VALUE = 62
13204
102k
    CEFBS_None, // G_CONSTANT_POOL = 63
13205
102k
    CEFBS_None, // G_EXTRACT = 64
13206
102k
    CEFBS_None, // G_UNMERGE_VALUES = 65
13207
102k
    CEFBS_None, // G_INSERT = 66
13208
102k
    CEFBS_None, // G_MERGE_VALUES = 67
13209
102k
    CEFBS_None, // G_BUILD_VECTOR = 68
13210
102k
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 69
13211
102k
    CEFBS_None, // G_CONCAT_VECTORS = 70
13212
102k
    CEFBS_None, // G_PTRTOINT = 71
13213
102k
    CEFBS_None, // G_INTTOPTR = 72
13214
102k
    CEFBS_None, // G_BITCAST = 73
13215
102k
    CEFBS_None, // G_FREEZE = 74
13216
102k
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 75
13217
102k
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 76
13218
102k
    CEFBS_None, // G_INTRINSIC_TRUNC = 77
13219
102k
    CEFBS_None, // G_INTRINSIC_ROUND = 78
13220
102k
    CEFBS_None, // G_INTRINSIC_LRINT = 79
13221
102k
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 80
13222
102k
    CEFBS_None, // G_READCYCLECOUNTER = 81
13223
102k
    CEFBS_None, // G_LOAD = 82
13224
102k
    CEFBS_None, // G_SEXTLOAD = 83
13225
102k
    CEFBS_None, // G_ZEXTLOAD = 84
13226
102k
    CEFBS_None, // G_INDEXED_LOAD = 85
13227
102k
    CEFBS_None, // G_INDEXED_SEXTLOAD = 86
13228
102k
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 87
13229
102k
    CEFBS_None, // G_STORE = 88
13230
102k
    CEFBS_None, // G_INDEXED_STORE = 89
13231
102k
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90
13232
102k
    CEFBS_None, // G_ATOMIC_CMPXCHG = 91
13233
102k
    CEFBS_None, // G_ATOMICRMW_XCHG = 92
13234
102k
    CEFBS_None, // G_ATOMICRMW_ADD = 93
13235
102k
    CEFBS_None, // G_ATOMICRMW_SUB = 94
13236
102k
    CEFBS_None, // G_ATOMICRMW_AND = 95
13237
102k
    CEFBS_None, // G_ATOMICRMW_NAND = 96
13238
102k
    CEFBS_None, // G_ATOMICRMW_OR = 97
13239
102k
    CEFBS_None, // G_ATOMICRMW_XOR = 98
13240
102k
    CEFBS_None, // G_ATOMICRMW_MAX = 99
13241
102k
    CEFBS_None, // G_ATOMICRMW_MIN = 100
13242
102k
    CEFBS_None, // G_ATOMICRMW_UMAX = 101
13243
102k
    CEFBS_None, // G_ATOMICRMW_UMIN = 102
13244
102k
    CEFBS_None, // G_ATOMICRMW_FADD = 103
13245
102k
    CEFBS_None, // G_ATOMICRMW_FSUB = 104
13246
102k
    CEFBS_None, // G_ATOMICRMW_FMAX = 105
13247
102k
    CEFBS_None, // G_ATOMICRMW_FMIN = 106
13248
102k
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 107
13249
102k
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 108
13250
102k
    CEFBS_None, // G_FENCE = 109
13251
102k
    CEFBS_None, // G_PREFETCH = 110
13252
102k
    CEFBS_None, // G_BRCOND = 111
13253
102k
    CEFBS_None, // G_BRINDIRECT = 112
13254
102k
    CEFBS_None, // G_INVOKE_REGION_START = 113
13255
102k
    CEFBS_None, // G_INTRINSIC = 114
13256
102k
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 115
13257
102k
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 116
13258
102k
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117
13259
102k
    CEFBS_None, // G_ANYEXT = 118
13260
102k
    CEFBS_None, // G_TRUNC = 119
13261
102k
    CEFBS_None, // G_CONSTANT = 120
13262
102k
    CEFBS_None, // G_FCONSTANT = 121
13263
102k
    CEFBS_None, // G_VASTART = 122
13264
102k
    CEFBS_None, // G_VAARG = 123
13265
102k
    CEFBS_None, // G_SEXT = 124
13266
102k
    CEFBS_None, // G_SEXT_INREG = 125
13267
102k
    CEFBS_None, // G_ZEXT = 126
13268
102k
    CEFBS_None, // G_SHL = 127
13269
102k
    CEFBS_None, // G_LSHR = 128
13270
102k
    CEFBS_None, // G_ASHR = 129
13271
102k
    CEFBS_None, // G_FSHL = 130
13272
102k
    CEFBS_None, // G_FSHR = 131
13273
102k
    CEFBS_None, // G_ROTR = 132
13274
102k
    CEFBS_None, // G_ROTL = 133
13275
102k
    CEFBS_None, // G_ICMP = 134
13276
102k
    CEFBS_None, // G_FCMP = 135
13277
102k
    CEFBS_None, // G_SELECT = 136
13278
102k
    CEFBS_None, // G_UADDO = 137
13279
102k
    CEFBS_None, // G_UADDE = 138
13280
102k
    CEFBS_None, // G_USUBO = 139
13281
102k
    CEFBS_None, // G_USUBE = 140
13282
102k
    CEFBS_None, // G_SADDO = 141
13283
102k
    CEFBS_None, // G_SADDE = 142
13284
102k
    CEFBS_None, // G_SSUBO = 143
13285
102k
    CEFBS_None, // G_SSUBE = 144
13286
102k
    CEFBS_None, // G_UMULO = 145
13287
102k
    CEFBS_None, // G_SMULO = 146
13288
102k
    CEFBS_None, // G_UMULH = 147
13289
102k
    CEFBS_None, // G_SMULH = 148
13290
102k
    CEFBS_None, // G_UADDSAT = 149
13291
102k
    CEFBS_None, // G_SADDSAT = 150
13292
102k
    CEFBS_None, // G_USUBSAT = 151
13293
102k
    CEFBS_None, // G_SSUBSAT = 152
13294
102k
    CEFBS_None, // G_USHLSAT = 153
13295
102k
    CEFBS_None, // G_SSHLSAT = 154
13296
102k
    CEFBS_None, // G_SMULFIX = 155
13297
102k
    CEFBS_None, // G_UMULFIX = 156
13298
102k
    CEFBS_None, // G_SMULFIXSAT = 157
13299
102k
    CEFBS_None, // G_UMULFIXSAT = 158
13300
102k
    CEFBS_None, // G_SDIVFIX = 159
13301
102k
    CEFBS_None, // G_UDIVFIX = 160
13302
102k
    CEFBS_None, // G_SDIVFIXSAT = 161
13303
102k
    CEFBS_None, // G_UDIVFIXSAT = 162
13304
102k
    CEFBS_None, // G_FADD = 163
13305
102k
    CEFBS_None, // G_FSUB = 164
13306
102k
    CEFBS_None, // G_FMUL = 165
13307
102k
    CEFBS_None, // G_FMA = 166
13308
102k
    CEFBS_None, // G_FMAD = 167
13309
102k
    CEFBS_None, // G_FDIV = 168
13310
102k
    CEFBS_None, // G_FREM = 169
13311
102k
    CEFBS_None, // G_FPOW = 170
13312
102k
    CEFBS_None, // G_FPOWI = 171
13313
102k
    CEFBS_None, // G_FEXP = 172
13314
102k
    CEFBS_None, // G_FEXP2 = 173
13315
102k
    CEFBS_None, // G_FEXP10 = 174
13316
102k
    CEFBS_None, // G_FLOG = 175
13317
102k
    CEFBS_None, // G_FLOG2 = 176
13318
102k
    CEFBS_None, // G_FLOG10 = 177
13319
102k
    CEFBS_None, // G_FLDEXP = 178
13320
102k
    CEFBS_None, // G_FFREXP = 179
13321
102k
    CEFBS_None, // G_FNEG = 180
13322
102k
    CEFBS_None, // G_FPEXT = 181
13323
102k
    CEFBS_None, // G_FPTRUNC = 182
13324
102k
    CEFBS_None, // G_FPTOSI = 183
13325
102k
    CEFBS_None, // G_FPTOUI = 184
13326
102k
    CEFBS_None, // G_SITOFP = 185
13327
102k
    CEFBS_None, // G_UITOFP = 186
13328
102k
    CEFBS_None, // G_FABS = 187
13329
102k
    CEFBS_None, // G_FCOPYSIGN = 188
13330
102k
    CEFBS_None, // G_IS_FPCLASS = 189
13331
102k
    CEFBS_None, // G_FCANONICALIZE = 190
13332
102k
    CEFBS_None, // G_FMINNUM = 191
13333
102k
    CEFBS_None, // G_FMAXNUM = 192
13334
102k
    CEFBS_None, // G_FMINNUM_IEEE = 193
13335
102k
    CEFBS_None, // G_FMAXNUM_IEEE = 194
13336
102k
    CEFBS_None, // G_FMINIMUM = 195
13337
102k
    CEFBS_None, // G_FMAXIMUM = 196
13338
102k
    CEFBS_None, // G_GET_FPENV = 197
13339
102k
    CEFBS_None, // G_SET_FPENV = 198
13340
102k
    CEFBS_None, // G_RESET_FPENV = 199
13341
102k
    CEFBS_None, // G_GET_FPMODE = 200
13342
102k
    CEFBS_None, // G_SET_FPMODE = 201
13343
102k
    CEFBS_None, // G_RESET_FPMODE = 202
13344
102k
    CEFBS_None, // G_PTR_ADD = 203
13345
102k
    CEFBS_None, // G_PTRMASK = 204
13346
102k
    CEFBS_None, // G_SMIN = 205
13347
102k
    CEFBS_None, // G_SMAX = 206
13348
102k
    CEFBS_None, // G_UMIN = 207
13349
102k
    CEFBS_None, // G_UMAX = 208
13350
102k
    CEFBS_None, // G_ABS = 209
13351
102k
    CEFBS_None, // G_LROUND = 210
13352
102k
    CEFBS_None, // G_LLROUND = 211
13353
102k
    CEFBS_None, // G_BR = 212
13354
102k
    CEFBS_None, // G_BRJT = 213
13355
102k
    CEFBS_None, // G_INSERT_VECTOR_ELT = 214
13356
102k
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 215
13357
102k
    CEFBS_None, // G_SHUFFLE_VECTOR = 216
13358
102k
    CEFBS_None, // G_CTTZ = 217
13359
102k
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 218
13360
102k
    CEFBS_None, // G_CTLZ = 219
13361
102k
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 220
13362
102k
    CEFBS_None, // G_CTPOP = 221
13363
102k
    CEFBS_None, // G_BSWAP = 222
13364
102k
    CEFBS_None, // G_BITREVERSE = 223
13365
102k
    CEFBS_None, // G_FCEIL = 224
13366
102k
    CEFBS_None, // G_FCOS = 225
13367
102k
    CEFBS_None, // G_FSIN = 226
13368
102k
    CEFBS_None, // G_FSQRT = 227
13369
102k
    CEFBS_None, // G_FFLOOR = 228
13370
102k
    CEFBS_None, // G_FRINT = 229
13371
102k
    CEFBS_None, // G_FNEARBYINT = 230
13372
102k
    CEFBS_None, // G_ADDRSPACE_CAST = 231
13373
102k
    CEFBS_None, // G_BLOCK_ADDR = 232
13374
102k
    CEFBS_None, // G_JUMP_TABLE = 233
13375
102k
    CEFBS_None, // G_DYN_STACKALLOC = 234
13376
102k
    CEFBS_None, // G_STACKSAVE = 235
13377
102k
    CEFBS_None, // G_STACKRESTORE = 236
13378
102k
    CEFBS_None, // G_STRICT_FADD = 237
13379
102k
    CEFBS_None, // G_STRICT_FSUB = 238
13380
102k
    CEFBS_None, // G_STRICT_FMUL = 239
13381
102k
    CEFBS_None, // G_STRICT_FDIV = 240
13382
102k
    CEFBS_None, // G_STRICT_FREM = 241
13383
102k
    CEFBS_None, // G_STRICT_FMA = 242
13384
102k
    CEFBS_None, // G_STRICT_FSQRT = 243
13385
102k
    CEFBS_None, // G_STRICT_FLDEXP = 244
13386
102k
    CEFBS_None, // G_READ_REGISTER = 245
13387
102k
    CEFBS_None, // G_WRITE_REGISTER = 246
13388
102k
    CEFBS_None, // G_MEMCPY = 247
13389
102k
    CEFBS_None, // G_MEMCPY_INLINE = 248
13390
102k
    CEFBS_None, // G_MEMMOVE = 249
13391
102k
    CEFBS_None, // G_MEMSET = 250
13392
102k
    CEFBS_None, // G_BZERO = 251
13393
102k
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 252
13394
102k
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 253
13395
102k
    CEFBS_None, // G_VECREDUCE_FADD = 254
13396
102k
    CEFBS_None, // G_VECREDUCE_FMUL = 255
13397
102k
    CEFBS_None, // G_VECREDUCE_FMAX = 256
13398
102k
    CEFBS_None, // G_VECREDUCE_FMIN = 257
13399
102k
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 258
13400
102k
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 259
13401
102k
    CEFBS_None, // G_VECREDUCE_ADD = 260
13402
102k
    CEFBS_None, // G_VECREDUCE_MUL = 261
13403
102k
    CEFBS_None, // G_VECREDUCE_AND = 262
13404
102k
    CEFBS_None, // G_VECREDUCE_OR = 263
13405
102k
    CEFBS_None, // G_VECREDUCE_XOR = 264
13406
102k
    CEFBS_None, // G_VECREDUCE_SMAX = 265
13407
102k
    CEFBS_None, // G_VECREDUCE_SMIN = 266
13408
102k
    CEFBS_None, // G_VECREDUCE_UMAX = 267
13409
102k
    CEFBS_None, // G_VECREDUCE_UMIN = 268
13410
102k
    CEFBS_None, // G_SBFX = 269
13411
102k
    CEFBS_None, // G_UBFX = 270
13412
102k
    CEFBS_None, // CALL_PARAMS = 271
13413
102k
    CEFBS_None, // CALL_PARAMS_S = 272
13414
102k
    CEFBS_None, // CALL_RESULTS = 273
13415
102k
    CEFBS_None, // CALL_RESULTS_S = 274
13416
102k
    CEFBS_HasExceptionHandling, // CATCHRET = 275
13417
102k
    CEFBS_HasExceptionHandling, // CATCHRET_S = 276
13418
102k
    CEFBS_HasExceptionHandling, // CLEANUPRET = 277
13419
102k
    CEFBS_HasExceptionHandling, // CLEANUPRET_S = 278
13420
102k
    CEFBS_HasAtomics, // COMPILER_FENCE = 279
13421
102k
    CEFBS_HasAtomics, // COMPILER_FENCE_S = 280
13422
102k
    CEFBS_None, // RET_CALL_RESULTS = 281
13423
102k
    CEFBS_None, // RET_CALL_RESULTS_S = 282
13424
102k
    CEFBS_None, // ABS_F32 = 283
13425
102k
    CEFBS_None, // ABS_F32_S = 284
13426
102k
    CEFBS_HasSIMD128, // ABS_F32x4 = 285
13427
102k
    CEFBS_HasSIMD128, // ABS_F32x4_S = 286
13428
102k
    CEFBS_None, // ABS_F64 = 287
13429
102k
    CEFBS_None, // ABS_F64_S = 288
13430
102k
    CEFBS_HasSIMD128, // ABS_F64x2 = 289
13431
102k
    CEFBS_HasSIMD128, // ABS_F64x2_S = 290
13432
102k
    CEFBS_HasSIMD128, // ABS_I16x8 = 291
13433
102k
    CEFBS_HasSIMD128, // ABS_I16x8_S = 292
13434
102k
    CEFBS_HasSIMD128, // ABS_I32x4 = 293
13435
102k
    CEFBS_HasSIMD128, // ABS_I32x4_S = 294
13436
102k
    CEFBS_HasSIMD128, // ABS_I64x2 = 295
13437
102k
    CEFBS_HasSIMD128, // ABS_I64x2_S = 296
13438
102k
    CEFBS_HasSIMD128, // ABS_I8x16 = 297
13439
102k
    CEFBS_HasSIMD128, // ABS_I8x16_S = 298
13440
102k
    CEFBS_None, // ADD_F32 = 299
13441
102k
    CEFBS_None, // ADD_F32_S = 300
13442
102k
    CEFBS_HasSIMD128, // ADD_F32x4 = 301
13443
102k
    CEFBS_HasSIMD128, // ADD_F32x4_S = 302
13444
102k
    CEFBS_None, // ADD_F64 = 303
13445
102k
    CEFBS_None, // ADD_F64_S = 304
13446
102k
    CEFBS_HasSIMD128, // ADD_F64x2 = 305
13447
102k
    CEFBS_HasSIMD128, // ADD_F64x2_S = 306
13448
102k
    CEFBS_HasSIMD128, // ADD_I16x8 = 307
13449
102k
    CEFBS_HasSIMD128, // ADD_I16x8_S = 308
13450
102k
    CEFBS_None, // ADD_I32 = 309
13451
102k
    CEFBS_None, // ADD_I32_S = 310
13452
102k
    CEFBS_HasSIMD128, // ADD_I32x4 = 311
13453
102k
    CEFBS_HasSIMD128, // ADD_I32x4_S = 312
13454
102k
    CEFBS_None, // ADD_I64 = 313
13455
102k
    CEFBS_None, // ADD_I64_S = 314
13456
102k
    CEFBS_HasSIMD128, // ADD_I64x2 = 315
13457
102k
    CEFBS_HasSIMD128, // ADD_I64x2_S = 316
13458
102k
    CEFBS_HasSIMD128, // ADD_I8x16 = 317
13459
102k
    CEFBS_HasSIMD128, // ADD_I8x16_S = 318
13460
102k
    CEFBS_HasSIMD128, // ADD_SAT_S_I16x8 = 319
13461
102k
    CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S = 320
13462
102k
    CEFBS_HasSIMD128, // ADD_SAT_S_I8x16 = 321
13463
102k
    CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S = 322
13464
102k
    CEFBS_HasSIMD128, // ADD_SAT_U_I16x8 = 323
13465
102k
    CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S = 324
13466
102k
    CEFBS_HasSIMD128, // ADD_SAT_U_I8x16 = 325
13467
102k
    CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S = 326
13468
102k
    CEFBS_None, // ADJCALLSTACKDOWN = 327
13469
102k
    CEFBS_None, // ADJCALLSTACKDOWN_S = 328
13470
102k
    CEFBS_None, // ADJCALLSTACKUP = 329
13471
102k
    CEFBS_None, // ADJCALLSTACKUP_S = 330
13472
102k
    CEFBS_HasSIMD128, // ALLTRUE_I16x8 = 331
13473
102k
    CEFBS_HasSIMD128, // ALLTRUE_I16x8_S = 332
13474
102k
    CEFBS_HasSIMD128, // ALLTRUE_I32x4 = 333
13475
102k
    CEFBS_HasSIMD128, // ALLTRUE_I32x4_S = 334
13476
102k
    CEFBS_HasSIMD128, // ALLTRUE_I64x2 = 335
13477
102k
    CEFBS_HasSIMD128, // ALLTRUE_I64x2_S = 336
13478
102k
    CEFBS_HasSIMD128, // ALLTRUE_I8x16 = 337
13479
102k
    CEFBS_HasSIMD128, // ALLTRUE_I8x16_S = 338
13480
102k
    CEFBS_HasSIMD128, // AND = 339
13481
102k
    CEFBS_HasSIMD128, // ANDNOT = 340
13482
102k
    CEFBS_HasSIMD128, // ANDNOT_S = 341
13483
102k
    CEFBS_None, // AND_I32 = 342
13484
102k
    CEFBS_None, // AND_I32_S = 343
13485
102k
    CEFBS_None, // AND_I64 = 344
13486
102k
    CEFBS_None, // AND_I64_S = 345
13487
102k
    CEFBS_HasSIMD128, // AND_S = 346
13488
102k
    CEFBS_HasSIMD128, // ANYTRUE = 347
13489
102k
    CEFBS_HasSIMD128, // ANYTRUE_S = 348
13490
102k
    CEFBS_None, // ARGUMENT_externref = 349
13491
102k
    CEFBS_None, // ARGUMENT_externref_S = 350
13492
102k
    CEFBS_None, // ARGUMENT_f32 = 351
13493
102k
    CEFBS_None, // ARGUMENT_f32_S = 352
13494
102k
    CEFBS_None, // ARGUMENT_f64 = 353
13495
102k
    CEFBS_None, // ARGUMENT_f64_S = 354
13496
102k
    CEFBS_None, // ARGUMENT_funcref = 355
13497
102k
    CEFBS_None, // ARGUMENT_funcref_S = 356
13498
102k
    CEFBS_None, // ARGUMENT_i32 = 357
13499
102k
    CEFBS_None, // ARGUMENT_i32_S = 358
13500
102k
    CEFBS_None, // ARGUMENT_i64 = 359
13501
102k
    CEFBS_None, // ARGUMENT_i64_S = 360
13502
102k
    CEFBS_None, // ARGUMENT_v16i8 = 361
13503
102k
    CEFBS_None, // ARGUMENT_v16i8_S = 362
13504
102k
    CEFBS_None, // ARGUMENT_v2f64 = 363
13505
102k
    CEFBS_None, // ARGUMENT_v2f64_S = 364
13506
102k
    CEFBS_None, // ARGUMENT_v2i64 = 365
13507
102k
    CEFBS_None, // ARGUMENT_v2i64_S = 366
13508
102k
    CEFBS_None, // ARGUMENT_v4f32 = 367
13509
102k
    CEFBS_None, // ARGUMENT_v4f32_S = 368
13510
102k
    CEFBS_None, // ARGUMENT_v4i32 = 369
13511
102k
    CEFBS_None, // ARGUMENT_v4i32_S = 370
13512
102k
    CEFBS_None, // ARGUMENT_v8i16 = 371
13513
102k
    CEFBS_None, // ARGUMENT_v8i16_S = 372
13514
102k
    CEFBS_HasAtomics, // ATOMIC_FENCE = 373
13515
102k
    CEFBS_HasAtomics, // ATOMIC_FENCE_S = 374
13516
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32 = 375
13517
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S = 376
13518
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64 = 377
13519
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S = 378
13520
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32 = 379
13521
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S = 380
13522
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64 = 381
13523
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S = 382
13524
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32 = 383
13525
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S = 384
13526
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64 = 385
13527
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S = 386
13528
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32 = 387
13529
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S = 388
13530
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64 = 389
13531
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S = 390
13532
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32 = 391
13533
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S = 392
13534
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64 = 393
13535
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S = 394
13536
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32 = 395
13537
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S = 396
13538
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64 = 397
13539
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S = 398
13540
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32 = 399
13541
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S = 400
13542
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64 = 401
13543
102k
    CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S = 402
13544
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32 = 403
13545
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S = 404
13546
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64 = 405
13547
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S = 406
13548
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32 = 407
13549
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S = 408
13550
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64 = 409
13551
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S = 410
13552
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32 = 411
13553
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S = 412
13554
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64 = 413
13555
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S = 414
13556
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32 = 415
13557
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S = 416
13558
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64 = 417
13559
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S = 418
13560
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 419
13561
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 420
13562
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 421
13563
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 422
13564
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 423
13565
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 424
13566
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 425
13567
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 426
13568
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32 = 427
13569
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S = 428
13570
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64 = 429
13571
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S = 430
13572
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32 = 431
13573
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S = 432
13574
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64 = 433
13575
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S = 434
13576
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32 = 435
13577
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S = 436
13578
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64 = 437
13579
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S = 438
13580
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32 = 439
13581
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S = 440
13582
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64 = 441
13583
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S = 442
13584
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32 = 443
13585
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S = 444
13586
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64 = 445
13587
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S = 446
13588
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32 = 447
13589
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S = 448
13590
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64 = 449
13591
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S = 450
13592
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32 = 451
13593
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S = 452
13594
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64 = 453
13595
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S = 454
13596
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32 = 455
13597
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S = 456
13598
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64 = 457
13599
102k
    CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S = 458
13600
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32 = 459
13601
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S = 460
13602
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64 = 461
13603
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S = 462
13604
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32 = 463
13605
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S = 464
13606
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64 = 465
13607
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S = 466
13608
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 467
13609
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 468
13610
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 469
13611
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 470
13612
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32 = 471
13613
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S = 472
13614
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64 = 473
13615
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S = 474
13616
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32 = 475
13617
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S = 476
13618
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64 = 477
13619
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S = 478
13620
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32 = 479
13621
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S = 480
13622
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64 = 481
13623
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S = 482
13624
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32 = 483
13625
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S = 484
13626
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64 = 485
13627
102k
    CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S = 486
13628
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32 = 487
13629
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S = 488
13630
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64 = 489
13631
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S = 490
13632
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32 = 491
13633
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S = 492
13634
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64 = 493
13635
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S = 494
13636
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32 = 495
13637
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S = 496
13638
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64 = 497
13639
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S = 498
13640
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32 = 499
13641
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S = 500
13642
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64 = 501
13643
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S = 502
13644
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 503
13645
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 504
13646
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 505
13647
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 506
13648
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 507
13649
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 508
13650
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 509
13651
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 510
13652
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32 = 511
13653
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S = 512
13654
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64 = 513
13655
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S = 514
13656
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32 = 515
13657
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S = 516
13658
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64 = 517
13659
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S = 518
13660
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32 = 519
13661
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S = 520
13662
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64 = 521
13663
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S = 522
13664
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32 = 523
13665
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S = 524
13666
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64 = 525
13667
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S = 526
13668
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32 = 527
13669
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S = 528
13670
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64 = 529
13671
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S = 530
13672
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32 = 531
13673
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S = 532
13674
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64 = 533
13675
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S = 534
13676
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32 = 535
13677
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S = 536
13678
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64 = 537
13679
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S = 538
13680
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32 = 539
13681
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S = 540
13682
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64 = 541
13683
102k
    CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S = 542
13684
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32 = 543
13685
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S = 544
13686
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64 = 545
13687
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S = 546
13688
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32 = 547
13689
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S = 548
13690
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64 = 549
13691
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S = 550
13692
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32 = 551
13693
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S = 552
13694
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64 = 553
13695
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S = 554
13696
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32 = 555
13697
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S = 556
13698
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64 = 557
13699
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S = 558
13700
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32 = 559
13701
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S = 560
13702
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64 = 561
13703
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S = 562
13704
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32 = 563
13705
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S = 564
13706
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64 = 565
13707
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S = 566
13708
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32 = 567
13709
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S = 568
13710
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64 = 569
13711
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S = 570
13712
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32 = 571
13713
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S = 572
13714
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64 = 573
13715
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S = 574
13716
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32 = 575
13717
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S = 576
13718
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64 = 577
13719
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S = 578
13720
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32 = 579
13721
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S = 580
13722
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64 = 581
13723
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S = 582
13724
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32 = 583
13725
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S = 584
13726
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64 = 585
13727
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S = 586
13728
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32 = 587
13729
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S = 588
13730
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64 = 589
13731
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S = 590
13732
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32 = 591
13733
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S = 592
13734
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64 = 593
13735
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S = 594
13736
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32 = 595
13737
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S = 596
13738
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64 = 597
13739
102k
    CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S = 598
13740
102k
    CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32 = 599
13741
102k
    CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S = 600
13742
102k
    CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64 = 601
13743
102k
    CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S = 602
13744
102k
    CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32 = 603
13745
102k
    CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S = 604
13746
102k
    CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64 = 605
13747
102k
    CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S = 606
13748
102k
    CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32 = 607
13749
102k
    CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S = 608
13750
102k
    CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64 = 609
13751
102k
    CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S = 610
13752
102k
    CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32 = 611
13753
102k
    CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S = 612
13754
102k
    CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64 = 613
13755
102k
    CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S = 614
13756
102k
    CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32 = 615
13757
102k
    CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S = 616
13758
102k
    CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64 = 617
13759
102k
    CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S = 618
13760
102k
    CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32 = 619
13761
102k
    CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S = 620
13762
102k
    CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64 = 621
13763
102k
    CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S = 622
13764
102k
    CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32 = 623
13765
102k
    CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S = 624
13766
102k
    CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64 = 625
13767
102k
    CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S = 626
13768
102k
    CEFBS_HasSIMD128, // AVGR_U_I16x8 = 627
13769
102k
    CEFBS_HasSIMD128, // AVGR_U_I16x8_S = 628
13770
102k
    CEFBS_HasSIMD128, // AVGR_U_I8x16 = 629
13771
102k
    CEFBS_HasSIMD128, // AVGR_U_I8x16_S = 630
13772
102k
    CEFBS_HasSIMD128, // BITMASK_I16x8 = 631
13773
102k
    CEFBS_HasSIMD128, // BITMASK_I16x8_S = 632
13774
102k
    CEFBS_HasSIMD128, // BITMASK_I32x4 = 633
13775
102k
    CEFBS_HasSIMD128, // BITMASK_I32x4_S = 634
13776
102k
    CEFBS_HasSIMD128, // BITMASK_I64x2 = 635
13777
102k
    CEFBS_HasSIMD128, // BITMASK_I64x2_S = 636
13778
102k
    CEFBS_HasSIMD128, // BITMASK_I8x16 = 637
13779
102k
    CEFBS_HasSIMD128, // BITMASK_I8x16_S = 638
13780
102k
    CEFBS_HasSIMD128, // BITSELECT = 639
13781
102k
    CEFBS_HasSIMD128, // BITSELECT_S = 640
13782
102k
    CEFBS_None, // BLOCK = 641
13783
102k
    CEFBS_None, // BLOCK_S = 642
13784
102k
    CEFBS_None, // BR = 643
13785
102k
    CEFBS_None, // BR_IF = 644
13786
102k
    CEFBS_None, // BR_IF_S = 645
13787
102k
    CEFBS_None, // BR_S = 646
13788
102k
    CEFBS_None, // BR_TABLE_I32 = 647
13789
102k
    CEFBS_None, // BR_TABLE_I32_S = 648
13790
102k
    CEFBS_None, // BR_TABLE_I64 = 649
13791
102k
    CEFBS_None, // BR_TABLE_I64_S = 650
13792
102k
    CEFBS_None, // BR_UNLESS = 651
13793
102k
    CEFBS_None, // BR_UNLESS_S = 652
13794
102k
    CEFBS_None, // CALL = 653
13795
102k
    CEFBS_None, // CALL_INDIRECT = 654
13796
102k
    CEFBS_None, // CALL_INDIRECT_S = 655
13797
102k
    CEFBS_None, // CALL_S = 656
13798
102k
    CEFBS_HasExceptionHandling, // CATCH = 657
13799
102k
    CEFBS_HasExceptionHandling, // CATCH_ALL = 658
13800
102k
    CEFBS_HasExceptionHandling, // CATCH_ALL_S = 659
13801
102k
    CEFBS_HasExceptionHandling, // CATCH_S = 660
13802
102k
    CEFBS_None, // CEIL_F32 = 661
13803
102k
    CEFBS_None, // CEIL_F32_S = 662
13804
102k
    CEFBS_HasSIMD128, // CEIL_F32x4 = 663
13805
102k
    CEFBS_HasSIMD128, // CEIL_F32x4_S = 664
13806
102k
    CEFBS_None, // CEIL_F64 = 665
13807
102k
    CEFBS_None, // CEIL_F64_S = 666
13808
102k
    CEFBS_HasSIMD128, // CEIL_F64x2 = 667
13809
102k
    CEFBS_HasSIMD128, // CEIL_F64x2_S = 668
13810
102k
    CEFBS_None, // CLZ_I32 = 669
13811
102k
    CEFBS_None, // CLZ_I32_S = 670
13812
102k
    CEFBS_None, // CLZ_I64 = 671
13813
102k
    CEFBS_None, // CLZ_I64_S = 672
13814
102k
    CEFBS_None, // CONST_F32 = 673
13815
102k
    CEFBS_None, // CONST_F32_S = 674
13816
102k
    CEFBS_None, // CONST_F64 = 675
13817
102k
    CEFBS_None, // CONST_F64_S = 676
13818
102k
    CEFBS_None, // CONST_I32 = 677
13819
102k
    CEFBS_None, // CONST_I32_S = 678
13820
102k
    CEFBS_None, // CONST_I64 = 679
13821
102k
    CEFBS_None, // CONST_I64_S = 680
13822
102k
    CEFBS_HasSIMD128, // CONST_V128_F32x4 = 681
13823
102k
    CEFBS_HasSIMD128, // CONST_V128_F32x4_S = 682
13824
102k
    CEFBS_HasSIMD128, // CONST_V128_F64x2 = 683
13825
102k
    CEFBS_HasSIMD128, // CONST_V128_F64x2_S = 684
13826
102k
    CEFBS_HasSIMD128, // CONST_V128_I16x8 = 685
13827
102k
    CEFBS_HasSIMD128, // CONST_V128_I16x8_S = 686
13828
102k
    CEFBS_HasSIMD128, // CONST_V128_I32x4 = 687
13829
102k
    CEFBS_HasSIMD128, // CONST_V128_I32x4_S = 688
13830
102k
    CEFBS_HasSIMD128, // CONST_V128_I64x2 = 689
13831
102k
    CEFBS_HasSIMD128, // CONST_V128_I64x2_S = 690
13832
102k
    CEFBS_HasSIMD128, // CONST_V128_I8x16 = 691
13833
102k
    CEFBS_HasSIMD128, // CONST_V128_I8x16_S = 692
13834
102k
    CEFBS_None, // COPYSIGN_F32 = 693
13835
102k
    CEFBS_None, // COPYSIGN_F32_S = 694
13836
102k
    CEFBS_None, // COPYSIGN_F64 = 695
13837
102k
    CEFBS_None, // COPYSIGN_F64_S = 696
13838
102k
    CEFBS_HasReferenceTypes, // COPY_EXTERNREF = 697
13839
102k
    CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S = 698
13840
102k
    CEFBS_None, // COPY_F32 = 699
13841
102k
    CEFBS_None, // COPY_F32_S = 700
13842
102k
    CEFBS_None, // COPY_F64 = 701
13843
102k
    CEFBS_None, // COPY_F64_S = 702
13844
102k
    CEFBS_HasReferenceTypes, // COPY_FUNCREF = 703
13845
102k
    CEFBS_HasReferenceTypes, // COPY_FUNCREF_S = 704
13846
102k
    CEFBS_None, // COPY_I32 = 705
13847
102k
    CEFBS_None, // COPY_I32_S = 706
13848
102k
    CEFBS_None, // COPY_I64 = 707
13849
102k
    CEFBS_None, // COPY_I64_S = 708
13850
102k
    CEFBS_HasSIMD128, // COPY_V128 = 709
13851
102k
    CEFBS_HasSIMD128, // COPY_V128_S = 710
13852
102k
    CEFBS_None, // CTZ_I32 = 711
13853
102k
    CEFBS_None, // CTZ_I32_S = 712
13854
102k
    CEFBS_None, // CTZ_I64 = 713
13855
102k
    CEFBS_None, // CTZ_I64_S = 714
13856
102k
    CEFBS_None, // DEBUG_UNREACHABLE = 715
13857
102k
    CEFBS_None, // DEBUG_UNREACHABLE_S = 716
13858
102k
    CEFBS_HasExceptionHandling, // DELEGATE = 717
13859
102k
    CEFBS_HasExceptionHandling, // DELEGATE_S = 718
13860
102k
    CEFBS_None, // DIV_F32 = 719
13861
102k
    CEFBS_None, // DIV_F32_S = 720
13862
102k
    CEFBS_HasSIMD128, // DIV_F32x4 = 721
13863
102k
    CEFBS_HasSIMD128, // DIV_F32x4_S = 722
13864
102k
    CEFBS_None, // DIV_F64 = 723
13865
102k
    CEFBS_None, // DIV_F64_S = 724
13866
102k
    CEFBS_HasSIMD128, // DIV_F64x2 = 725
13867
102k
    CEFBS_HasSIMD128, // DIV_F64x2_S = 726
13868
102k
    CEFBS_None, // DIV_S_I32 = 727
13869
102k
    CEFBS_None, // DIV_S_I32_S = 728
13870
102k
    CEFBS_None, // DIV_S_I64 = 729
13871
102k
    CEFBS_None, // DIV_S_I64_S = 730
13872
102k
    CEFBS_None, // DIV_U_I32 = 731
13873
102k
    CEFBS_None, // DIV_U_I32_S = 732
13874
102k
    CEFBS_None, // DIV_U_I64 = 733
13875
102k
    CEFBS_None, // DIV_U_I64_S = 734
13876
102k
    CEFBS_HasSIMD128, // DOT = 735
13877
102k
    CEFBS_HasSIMD128, // DOT_S = 736
13878
102k
    CEFBS_HasReferenceTypes, // DROP_EXTERNREF = 737
13879
102k
    CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S = 738
13880
102k
    CEFBS_None, // DROP_F32 = 739
13881
102k
    CEFBS_None, // DROP_F32_S = 740
13882
102k
    CEFBS_None, // DROP_F64 = 741
13883
102k
    CEFBS_None, // DROP_F64_S = 742
13884
102k
    CEFBS_HasReferenceTypes, // DROP_FUNCREF = 743
13885
102k
    CEFBS_HasReferenceTypes, // DROP_FUNCREF_S = 744
13886
102k
    CEFBS_None, // DROP_I32 = 745
13887
102k
    CEFBS_None, // DROP_I32_S = 746
13888
102k
    CEFBS_None, // DROP_I64 = 747
13889
102k
    CEFBS_None, // DROP_I64_S = 748
13890
102k
    CEFBS_HasSIMD128, // DROP_V128 = 749
13891
102k
    CEFBS_HasSIMD128, // DROP_V128_S = 750
13892
102k
    CEFBS_None, // ELSE = 751
13893
102k
    CEFBS_None, // ELSE_S = 752
13894
102k
    CEFBS_None, // END = 753
13895
102k
    CEFBS_None, // END_BLOCK = 754
13896
102k
    CEFBS_None, // END_BLOCK_S = 755
13897
102k
    CEFBS_None, // END_FUNCTION = 756
13898
102k
    CEFBS_None, // END_FUNCTION_S = 757
13899
102k
    CEFBS_None, // END_IF = 758
13900
102k
    CEFBS_None, // END_IF_S = 759
13901
102k
    CEFBS_None, // END_LOOP = 760
13902
102k
    CEFBS_None, // END_LOOP_S = 761
13903
102k
    CEFBS_None, // END_S = 762
13904
102k
    CEFBS_HasExceptionHandling, // END_TRY = 763
13905
102k
    CEFBS_HasExceptionHandling, // END_TRY_S = 764
13906
102k
    CEFBS_None, // EQZ_I32 = 765
13907
102k
    CEFBS_None, // EQZ_I32_S = 766
13908
102k
    CEFBS_None, // EQZ_I64 = 767
13909
102k
    CEFBS_None, // EQZ_I64_S = 768
13910
102k
    CEFBS_None, // EQ_F32 = 769
13911
102k
    CEFBS_None, // EQ_F32_S = 770
13912
102k
    CEFBS_HasSIMD128, // EQ_F32x4 = 771
13913
102k
    CEFBS_HasSIMD128, // EQ_F32x4_S = 772
13914
102k
    CEFBS_None, // EQ_F64 = 773
13915
102k
    CEFBS_None, // EQ_F64_S = 774
13916
102k
    CEFBS_HasSIMD128, // EQ_F64x2 = 775
13917
102k
    CEFBS_HasSIMD128, // EQ_F64x2_S = 776
13918
102k
    CEFBS_HasSIMD128, // EQ_I16x8 = 777
13919
102k
    CEFBS_HasSIMD128, // EQ_I16x8_S = 778
13920
102k
    CEFBS_None, // EQ_I32 = 779
13921
102k
    CEFBS_None, // EQ_I32_S = 780
13922
102k
    CEFBS_HasSIMD128, // EQ_I32x4 = 781
13923
102k
    CEFBS_HasSIMD128, // EQ_I32x4_S = 782
13924
102k
    CEFBS_None, // EQ_I64 = 783
13925
102k
    CEFBS_None, // EQ_I64_S = 784
13926
102k
    CEFBS_HasSIMD128, // EQ_I64x2 = 785
13927
102k
    CEFBS_HasSIMD128, // EQ_I64x2_S = 786
13928
102k
    CEFBS_HasSIMD128, // EQ_I8x16 = 787
13929
102k
    CEFBS_HasSIMD128, // EQ_I8x16_S = 788
13930
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8 = 789
13931
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S = 790
13932
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4 = 791
13933
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S = 792
13934
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2 = 793
13935
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S = 794
13936
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8 = 795
13937
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S = 796
13938
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4 = 797
13939
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S = 798
13940
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2 = 799
13941
102k
    CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S = 800
13942
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8 = 801
13943
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S = 802
13944
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4 = 803
13945
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S = 804
13946
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2 = 805
13947
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S = 806
13948
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8 = 807
13949
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S = 808
13950
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4 = 809
13951
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S = 810
13952
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2 = 811
13953
102k
    CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S = 812
13954
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4 = 813
13955
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S = 814
13956
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2 = 815
13957
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S = 816
13958
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s = 817
13959
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S = 818
13960
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u = 819
13961
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S = 820
13962
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4 = 821
13963
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S = 822
13964
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2 = 823
13965
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S = 824
13966
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s = 825
13967
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S = 826
13968
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u = 827
13969
102k
    CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S = 828
13970
102k
    CEFBS_None, // F32_CONVERT_S_I32 = 829
13971
102k
    CEFBS_None, // F32_CONVERT_S_I32_S = 830
13972
102k
    CEFBS_None, // F32_CONVERT_S_I64 = 831
13973
102k
    CEFBS_None, // F32_CONVERT_S_I64_S = 832
13974
102k
    CEFBS_None, // F32_CONVERT_U_I32 = 833
13975
102k
    CEFBS_None, // F32_CONVERT_U_I32_S = 834
13976
102k
    CEFBS_None, // F32_CONVERT_U_I64 = 835
13977
102k
    CEFBS_None, // F32_CONVERT_U_I64_S = 836
13978
102k
    CEFBS_None, // F32_DEMOTE_F64 = 837
13979
102k
    CEFBS_None, // F32_DEMOTE_F64_S = 838
13980
102k
    CEFBS_None, // F32_REINTERPRET_I32 = 839
13981
102k
    CEFBS_None, // F32_REINTERPRET_I32_S = 840
13982
102k
    CEFBS_None, // F64_CONVERT_S_I32 = 841
13983
102k
    CEFBS_None, // F64_CONVERT_S_I32_S = 842
13984
102k
    CEFBS_None, // F64_CONVERT_S_I64 = 843
13985
102k
    CEFBS_None, // F64_CONVERT_S_I64_S = 844
13986
102k
    CEFBS_None, // F64_CONVERT_U_I32 = 845
13987
102k
    CEFBS_None, // F64_CONVERT_U_I32_S = 846
13988
102k
    CEFBS_None, // F64_CONVERT_U_I64 = 847
13989
102k
    CEFBS_None, // F64_CONVERT_U_I64_S = 848
13990
102k
    CEFBS_None, // F64_PROMOTE_F32 = 849
13991
102k
    CEFBS_None, // F64_PROMOTE_F32_S = 850
13992
102k
    CEFBS_None, // F64_REINTERPRET_I64 = 851
13993
102k
    CEFBS_None, // F64_REINTERPRET_I64_S = 852
13994
102k
    CEFBS_None, // FALLTHROUGH_RETURN = 853
13995
102k
    CEFBS_None, // FALLTHROUGH_RETURN_S = 854
13996
102k
    CEFBS_None, // FLOOR_F32 = 855
13997
102k
    CEFBS_None, // FLOOR_F32_S = 856
13998
102k
    CEFBS_HasSIMD128, // FLOOR_F32x4 = 857
13999
102k
    CEFBS_HasSIMD128, // FLOOR_F32x4_S = 858
14000
102k
    CEFBS_None, // FLOOR_F64 = 859
14001
102k
    CEFBS_None, // FLOOR_F64_S = 860
14002
102k
    CEFBS_HasSIMD128, // FLOOR_F64x2 = 861
14003
102k
    CEFBS_HasSIMD128, // FLOOR_F64x2_S = 862
14004
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32 = 863
14005
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S = 864
14006
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64 = 865
14007
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S = 866
14008
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32 = 867
14009
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S = 868
14010
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64 = 869
14011
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S = 870
14012
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32 = 871
14013
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S = 872
14014
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64 = 873
14015
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S = 874
14016
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32 = 875
14017
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S = 876
14018
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64 = 877
14019
102k
    CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S = 878
14020
102k
    CEFBS_None, // GE_F32 = 879
14021
102k
    CEFBS_None, // GE_F32_S = 880
14022
102k
    CEFBS_HasSIMD128, // GE_F32x4 = 881
14023
102k
    CEFBS_HasSIMD128, // GE_F32x4_S = 882
14024
102k
    CEFBS_None, // GE_F64 = 883
14025
102k
    CEFBS_None, // GE_F64_S = 884
14026
102k
    CEFBS_HasSIMD128, // GE_F64x2 = 885
14027
102k
    CEFBS_HasSIMD128, // GE_F64x2_S = 886
14028
102k
    CEFBS_HasSIMD128, // GE_S_I16x8 = 887
14029
102k
    CEFBS_HasSIMD128, // GE_S_I16x8_S = 888
14030
102k
    CEFBS_None, // GE_S_I32 = 889
14031
102k
    CEFBS_None, // GE_S_I32_S = 890
14032
102k
    CEFBS_HasSIMD128, // GE_S_I32x4 = 891
14033
102k
    CEFBS_HasSIMD128, // GE_S_I32x4_S = 892
14034
102k
    CEFBS_None, // GE_S_I64 = 893
14035
102k
    CEFBS_None, // GE_S_I64_S = 894
14036
102k
    CEFBS_HasSIMD128, // GE_S_I64x2 = 895
14037
102k
    CEFBS_HasSIMD128, // GE_S_I64x2_S = 896
14038
102k
    CEFBS_HasSIMD128, // GE_S_I8x16 = 897
14039
102k
    CEFBS_HasSIMD128, // GE_S_I8x16_S = 898
14040
102k
    CEFBS_HasSIMD128, // GE_U_I16x8 = 899
14041
102k
    CEFBS_HasSIMD128, // GE_U_I16x8_S = 900
14042
102k
    CEFBS_None, // GE_U_I32 = 901
14043
102k
    CEFBS_None, // GE_U_I32_S = 902
14044
102k
    CEFBS_HasSIMD128, // GE_U_I32x4 = 903
14045
102k
    CEFBS_HasSIMD128, // GE_U_I32x4_S = 904
14046
102k
    CEFBS_None, // GE_U_I64 = 905
14047
102k
    CEFBS_None, // GE_U_I64_S = 906
14048
102k
    CEFBS_HasSIMD128, // GE_U_I8x16 = 907
14049
102k
    CEFBS_HasSIMD128, // GE_U_I8x16_S = 908
14050
102k
    CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF = 909
14051
102k
    CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S = 910
14052
102k
    CEFBS_None, // GLOBAL_GET_F32 = 911
14053
102k
    CEFBS_None, // GLOBAL_GET_F32_S = 912
14054
102k
    CEFBS_None, // GLOBAL_GET_F64 = 913
14055
102k
    CEFBS_None, // GLOBAL_GET_F64_S = 914
14056
102k
    CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF = 915
14057
102k
    CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S = 916
14058
102k
    CEFBS_None, // GLOBAL_GET_I32 = 917
14059
102k
    CEFBS_None, // GLOBAL_GET_I32_S = 918
14060
102k
    CEFBS_None, // GLOBAL_GET_I64 = 919
14061
102k
    CEFBS_None, // GLOBAL_GET_I64_S = 920
14062
102k
    CEFBS_HasSIMD128, // GLOBAL_GET_V128 = 921
14063
102k
    CEFBS_HasSIMD128, // GLOBAL_GET_V128_S = 922
14064
102k
    CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF = 923
14065
102k
    CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S = 924
14066
102k
    CEFBS_None, // GLOBAL_SET_F32 = 925
14067
102k
    CEFBS_None, // GLOBAL_SET_F32_S = 926
14068
102k
    CEFBS_None, // GLOBAL_SET_F64 = 927
14069
102k
    CEFBS_None, // GLOBAL_SET_F64_S = 928
14070
102k
    CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF = 929
14071
102k
    CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S = 930
14072
102k
    CEFBS_None, // GLOBAL_SET_I32 = 931
14073
102k
    CEFBS_None, // GLOBAL_SET_I32_S = 932
14074
102k
    CEFBS_None, // GLOBAL_SET_I64 = 933
14075
102k
    CEFBS_None, // GLOBAL_SET_I64_S = 934
14076
102k
    CEFBS_HasSIMD128, // GLOBAL_SET_V128 = 935
14077
102k
    CEFBS_HasSIMD128, // GLOBAL_SET_V128_S = 936
14078
102k
    CEFBS_None, // GT_F32 = 937
14079
102k
    CEFBS_None, // GT_F32_S = 938
14080
102k
    CEFBS_HasSIMD128, // GT_F32x4 = 939
14081
102k
    CEFBS_HasSIMD128, // GT_F32x4_S = 940
14082
102k
    CEFBS_None, // GT_F64 = 941
14083
102k
    CEFBS_None, // GT_F64_S = 942
14084
102k
    CEFBS_HasSIMD128, // GT_F64x2 = 943
14085
102k
    CEFBS_HasSIMD128, // GT_F64x2_S = 944
14086
102k
    CEFBS_HasSIMD128, // GT_S_I16x8 = 945
14087
102k
    CEFBS_HasSIMD128, // GT_S_I16x8_S = 946
14088
102k
    CEFBS_None, // GT_S_I32 = 947
14089
102k
    CEFBS_None, // GT_S_I32_S = 948
14090
102k
    CEFBS_HasSIMD128, // GT_S_I32x4 = 949
14091
102k
    CEFBS_HasSIMD128, // GT_S_I32x4_S = 950
14092
102k
    CEFBS_None, // GT_S_I64 = 951
14093
102k
    CEFBS_None, // GT_S_I64_S = 952
14094
102k
    CEFBS_HasSIMD128, // GT_S_I64x2 = 953
14095
102k
    CEFBS_HasSIMD128, // GT_S_I64x2_S = 954
14096
102k
    CEFBS_HasSIMD128, // GT_S_I8x16 = 955
14097
102k
    CEFBS_HasSIMD128, // GT_S_I8x16_S = 956
14098
102k
    CEFBS_HasSIMD128, // GT_U_I16x8 = 957
14099
102k
    CEFBS_HasSIMD128, // GT_U_I16x8_S = 958
14100
102k
    CEFBS_None, // GT_U_I32 = 959
14101
102k
    CEFBS_None, // GT_U_I32_S = 960
14102
102k
    CEFBS_HasSIMD128, // GT_U_I32x4 = 961
14103
102k
    CEFBS_HasSIMD128, // GT_U_I32x4_S = 962
14104
102k
    CEFBS_None, // GT_U_I64 = 963
14105
102k
    CEFBS_None, // GT_U_I64_S = 964
14106
102k
    CEFBS_HasSIMD128, // GT_U_I8x16 = 965
14107
102k
    CEFBS_HasSIMD128, // GT_U_I8x16_S = 966
14108
102k
    CEFBS_HasSignExt, // I32_EXTEND16_S_I32 = 967
14109
102k
    CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S = 968
14110
102k
    CEFBS_HasSignExt, // I32_EXTEND8_S_I32 = 969
14111
102k
    CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S = 970
14112
102k
    CEFBS_None, // I32_REINTERPRET_F32 = 971
14113
102k
    CEFBS_None, // I32_REINTERPRET_F32_S = 972
14114
102k
    CEFBS_None, // I32_TRUNC_S_F32 = 973
14115
102k
    CEFBS_None, // I32_TRUNC_S_F32_S = 974
14116
102k
    CEFBS_None, // I32_TRUNC_S_F64 = 975
14117
102k
    CEFBS_None, // I32_TRUNC_S_F64_S = 976
14118
102k
    CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32 = 977
14119
102k
    CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S = 978
14120
102k
    CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64 = 979
14121
102k
    CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S = 980
14122
102k
    CEFBS_None, // I32_TRUNC_U_F32 = 981
14123
102k
    CEFBS_None, // I32_TRUNC_U_F32_S = 982
14124
102k
    CEFBS_None, // I32_TRUNC_U_F64 = 983
14125
102k
    CEFBS_None, // I32_TRUNC_U_F64_S = 984
14126
102k
    CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32 = 985
14127
102k
    CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S = 986
14128
102k
    CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64 = 987
14129
102k
    CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S = 988
14130
102k
    CEFBS_None, // I32_WRAP_I64 = 989
14131
102k
    CEFBS_None, // I32_WRAP_I64_S = 990
14132
102k
    CEFBS_HasSignExt, // I64_EXTEND16_S_I64 = 991
14133
102k
    CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S = 992
14134
102k
    CEFBS_HasSignExt, // I64_EXTEND32_S_I64 = 993
14135
102k
    CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S = 994
14136
102k
    CEFBS_HasSignExt, // I64_EXTEND8_S_I64 = 995
14137
102k
    CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S = 996
14138
102k
    CEFBS_None, // I64_EXTEND_S_I32 = 997
14139
102k
    CEFBS_None, // I64_EXTEND_S_I32_S = 998
14140
102k
    CEFBS_None, // I64_EXTEND_U_I32 = 999
14141
102k
    CEFBS_None, // I64_EXTEND_U_I32_S = 1000
14142
102k
    CEFBS_None, // I64_REINTERPRET_F64 = 1001
14143
102k
    CEFBS_None, // I64_REINTERPRET_F64_S = 1002
14144
102k
    CEFBS_None, // I64_TRUNC_S_F32 = 1003
14145
102k
    CEFBS_None, // I64_TRUNC_S_F32_S = 1004
14146
102k
    CEFBS_None, // I64_TRUNC_S_F64 = 1005
14147
102k
    CEFBS_None, // I64_TRUNC_S_F64_S = 1006
14148
102k
    CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32 = 1007
14149
102k
    CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S = 1008
14150
102k
    CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64 = 1009
14151
102k
    CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S = 1010
14152
102k
    CEFBS_None, // I64_TRUNC_U_F32 = 1011
14153
102k
    CEFBS_None, // I64_TRUNC_U_F32_S = 1012
14154
102k
    CEFBS_None, // I64_TRUNC_U_F64 = 1013
14155
102k
    CEFBS_None, // I64_TRUNC_U_F64_S = 1014
14156
102k
    CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32 = 1015
14157
102k
    CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S = 1016
14158
102k
    CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64 = 1017
14159
102k
    CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S = 1018
14160
102k
    CEFBS_None, // IF = 1019
14161
102k
    CEFBS_None, // IF_S = 1020
14162
102k
    CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8 = 1021
14163
102k
    CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S = 1022
14164
102k
    CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4 = 1023
14165
102k
    CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S = 1024
14166
102k
    CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2 = 1025
14167
102k
    CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S = 1026
14168
102k
    CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16 = 1027
14169
102k
    CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S = 1028
14170
102k
    CEFBS_None, // LE_F32 = 1029
14171
102k
    CEFBS_None, // LE_F32_S = 1030
14172
102k
    CEFBS_HasSIMD128, // LE_F32x4 = 1031
14173
102k
    CEFBS_HasSIMD128, // LE_F32x4_S = 1032
14174
102k
    CEFBS_None, // LE_F64 = 1033
14175
102k
    CEFBS_None, // LE_F64_S = 1034
14176
102k
    CEFBS_HasSIMD128, // LE_F64x2 = 1035
14177
102k
    CEFBS_HasSIMD128, // LE_F64x2_S = 1036
14178
102k
    CEFBS_HasSIMD128, // LE_S_I16x8 = 1037
14179
102k
    CEFBS_HasSIMD128, // LE_S_I16x8_S = 1038
14180
102k
    CEFBS_None, // LE_S_I32 = 1039
14181
102k
    CEFBS_None, // LE_S_I32_S = 1040
14182
102k
    CEFBS_HasSIMD128, // LE_S_I32x4 = 1041
14183
102k
    CEFBS_HasSIMD128, // LE_S_I32x4_S = 1042
14184
102k
    CEFBS_None, // LE_S_I64 = 1043
14185
102k
    CEFBS_None, // LE_S_I64_S = 1044
14186
102k
    CEFBS_HasSIMD128, // LE_S_I64x2 = 1045
14187
102k
    CEFBS_HasSIMD128, // LE_S_I64x2_S = 1046
14188
102k
    CEFBS_HasSIMD128, // LE_S_I8x16 = 1047
14189
102k
    CEFBS_HasSIMD128, // LE_S_I8x16_S = 1048
14190
102k
    CEFBS_HasSIMD128, // LE_U_I16x8 = 1049
14191
102k
    CEFBS_HasSIMD128, // LE_U_I16x8_S = 1050
14192
102k
    CEFBS_None, // LE_U_I32 = 1051
14193
102k
    CEFBS_None, // LE_U_I32_S = 1052
14194
102k
    CEFBS_HasSIMD128, // LE_U_I32x4 = 1053
14195
102k
    CEFBS_HasSIMD128, // LE_U_I32x4_S = 1054
14196
102k
    CEFBS_None, // LE_U_I64 = 1055
14197
102k
    CEFBS_None, // LE_U_I64_S = 1056
14198
102k
    CEFBS_HasSIMD128, // LE_U_I8x16 = 1057
14199
102k
    CEFBS_HasSIMD128, // LE_U_I8x16_S = 1058
14200
102k
    CEFBS_HasSIMD128, // LOAD16_SPLAT_A32 = 1059
14201
102k
    CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S = 1060
14202
102k
    CEFBS_HasSIMD128, // LOAD16_SPLAT_A64 = 1061
14203
102k
    CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S = 1062
14204
102k
    CEFBS_None, // LOAD16_S_I32_A32 = 1063
14205
102k
    CEFBS_None, // LOAD16_S_I32_A32_S = 1064
14206
102k
    CEFBS_None, // LOAD16_S_I32_A64 = 1065
14207
102k
    CEFBS_None, // LOAD16_S_I32_A64_S = 1066
14208
102k
    CEFBS_None, // LOAD16_S_I64_A32 = 1067
14209
102k
    CEFBS_None, // LOAD16_S_I64_A32_S = 1068
14210
102k
    CEFBS_None, // LOAD16_S_I64_A64 = 1069
14211
102k
    CEFBS_None, // LOAD16_S_I64_A64_S = 1070
14212
102k
    CEFBS_None, // LOAD16_U_I32_A32 = 1071
14213
102k
    CEFBS_None, // LOAD16_U_I32_A32_S = 1072
14214
102k
    CEFBS_None, // LOAD16_U_I32_A64 = 1073
14215
102k
    CEFBS_None, // LOAD16_U_I32_A64_S = 1074
14216
102k
    CEFBS_None, // LOAD16_U_I64_A32 = 1075
14217
102k
    CEFBS_None, // LOAD16_U_I64_A32_S = 1076
14218
102k
    CEFBS_None, // LOAD16_U_I64_A64 = 1077
14219
102k
    CEFBS_None, // LOAD16_U_I64_A64_S = 1078
14220
102k
    CEFBS_HasSIMD128, // LOAD32_SPLAT_A32 = 1079
14221
102k
    CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S = 1080
14222
102k
    CEFBS_HasSIMD128, // LOAD32_SPLAT_A64 = 1081
14223
102k
    CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S = 1082
14224
102k
    CEFBS_None, // LOAD32_S_I64_A32 = 1083
14225
102k
    CEFBS_None, // LOAD32_S_I64_A32_S = 1084
14226
102k
    CEFBS_None, // LOAD32_S_I64_A64 = 1085
14227
102k
    CEFBS_None, // LOAD32_S_I64_A64_S = 1086
14228
102k
    CEFBS_None, // LOAD32_U_I64_A32 = 1087
14229
102k
    CEFBS_None, // LOAD32_U_I64_A32_S = 1088
14230
102k
    CEFBS_None, // LOAD32_U_I64_A64 = 1089
14231
102k
    CEFBS_None, // LOAD32_U_I64_A64_S = 1090
14232
102k
    CEFBS_HasSIMD128, // LOAD64_SPLAT_A32 = 1091
14233
102k
    CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S = 1092
14234
102k
    CEFBS_HasSIMD128, // LOAD64_SPLAT_A64 = 1093
14235
102k
    CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S = 1094
14236
102k
    CEFBS_HasSIMD128, // LOAD8_SPLAT_A32 = 1095
14237
102k
    CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S = 1096
14238
102k
    CEFBS_HasSIMD128, // LOAD8_SPLAT_A64 = 1097
14239
102k
    CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S = 1098
14240
102k
    CEFBS_None, // LOAD8_S_I32_A32 = 1099
14241
102k
    CEFBS_None, // LOAD8_S_I32_A32_S = 1100
14242
102k
    CEFBS_None, // LOAD8_S_I32_A64 = 1101
14243
102k
    CEFBS_None, // LOAD8_S_I32_A64_S = 1102
14244
102k
    CEFBS_None, // LOAD8_S_I64_A32 = 1103
14245
102k
    CEFBS_None, // LOAD8_S_I64_A32_S = 1104
14246
102k
    CEFBS_None, // LOAD8_S_I64_A64 = 1105
14247
102k
    CEFBS_None, // LOAD8_S_I64_A64_S = 1106
14248
102k
    CEFBS_None, // LOAD8_U_I32_A32 = 1107
14249
102k
    CEFBS_None, // LOAD8_U_I32_A32_S = 1108
14250
102k
    CEFBS_None, // LOAD8_U_I32_A64 = 1109
14251
102k
    CEFBS_None, // LOAD8_U_I32_A64_S = 1110
14252
102k
    CEFBS_None, // LOAD8_U_I64_A32 = 1111
14253
102k
    CEFBS_None, // LOAD8_U_I64_A32_S = 1112
14254
102k
    CEFBS_None, // LOAD8_U_I64_A64 = 1113
14255
102k
    CEFBS_None, // LOAD8_U_I64_A64_S = 1114
14256
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32 = 1115
14257
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S = 1116
14258
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64 = 1117
14259
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S = 1118
14260
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32 = 1119
14261
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S = 1120
14262
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64 = 1121
14263
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S = 1122
14264
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32 = 1123
14265
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S = 1124
14266
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64 = 1125
14267
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S = 1126
14268
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32 = 1127
14269
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S = 1128
14270
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64 = 1129
14271
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S = 1130
14272
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32 = 1131
14273
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S = 1132
14274
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64 = 1133
14275
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S = 1134
14276
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32 = 1135
14277
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S = 1136
14278
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64 = 1137
14279
102k
    CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S = 1138
14280
102k
    CEFBS_None, // LOAD_F32_A32 = 1139
14281
102k
    CEFBS_None, // LOAD_F32_A32_S = 1140
14282
102k
    CEFBS_None, // LOAD_F32_A64 = 1141
14283
102k
    CEFBS_None, // LOAD_F32_A64_S = 1142
14284
102k
    CEFBS_None, // LOAD_F64_A32 = 1143
14285
102k
    CEFBS_None, // LOAD_F64_A32_S = 1144
14286
102k
    CEFBS_None, // LOAD_F64_A64 = 1145
14287
102k
    CEFBS_None, // LOAD_F64_A64_S = 1146
14288
102k
    CEFBS_None, // LOAD_I32_A32 = 1147
14289
102k
    CEFBS_None, // LOAD_I32_A32_S = 1148
14290
102k
    CEFBS_None, // LOAD_I32_A64 = 1149
14291
102k
    CEFBS_None, // LOAD_I32_A64_S = 1150
14292
102k
    CEFBS_None, // LOAD_I64_A32 = 1151
14293
102k
    CEFBS_None, // LOAD_I64_A32_S = 1152
14294
102k
    CEFBS_None, // LOAD_I64_A64 = 1153
14295
102k
    CEFBS_None, // LOAD_I64_A64_S = 1154
14296
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I16x8_A32 = 1155
14297
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I16x8_A32_S = 1156
14298
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I16x8_A64 = 1157
14299
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I16x8_A64_S = 1158
14300
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I32x4_A32 = 1159
14301
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I32x4_A32_S = 1160
14302
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I32x4_A64 = 1161
14303
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I32x4_A64_S = 1162
14304
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I64x2_A32 = 1163
14305
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I64x2_A32_S = 1164
14306
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I64x2_A64 = 1165
14307
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I64x2_A64_S = 1166
14308
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I8x16_A32 = 1167
14309
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I8x16_A32_S = 1168
14310
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I8x16_A64 = 1169
14311
102k
    CEFBS_HasSIMD128, // LOAD_LANE_I8x16_A64_S = 1170
14312
102k
    CEFBS_HasSIMD128, // LOAD_V128_A32 = 1171
14313
102k
    CEFBS_HasSIMD128, // LOAD_V128_A32_S = 1172
14314
102k
    CEFBS_HasSIMD128, // LOAD_V128_A64 = 1173
14315
102k
    CEFBS_HasSIMD128, // LOAD_V128_A64_S = 1174
14316
102k
    CEFBS_HasSIMD128, // LOAD_ZERO_I32x4_A32 = 1175
14317
102k
    CEFBS_HasSIMD128, // LOAD_ZERO_I32x4_A32_S = 1176
14318
102k
    CEFBS_HasSIMD128, // LOAD_ZERO_I32x4_A64 = 1177
14319
102k
    CEFBS_HasSIMD128, // LOAD_ZERO_I32x4_A64_S = 1178
14320
102k
    CEFBS_HasSIMD128, // LOAD_ZERO_I64x2_A32 = 1179
14321
102k
    CEFBS_HasSIMD128, // LOAD_ZERO_I64x2_A32_S = 1180
14322
102k
    CEFBS_HasSIMD128, // LOAD_ZERO_I64x2_A64 = 1181
14323
102k
    CEFBS_HasSIMD128, // LOAD_ZERO_I64x2_A64_S = 1182
14324
102k
    CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF = 1183
14325
102k
    CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S = 1184
14326
102k
    CEFBS_None, // LOCAL_GET_F32 = 1185
14327
102k
    CEFBS_None, // LOCAL_GET_F32_S = 1186
14328
102k
    CEFBS_None, // LOCAL_GET_F64 = 1187
14329
102k
    CEFBS_None, // LOCAL_GET_F64_S = 1188
14330
102k
    CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF = 1189
14331
102k
    CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S = 1190
14332
102k
    CEFBS_None, // LOCAL_GET_I32 = 1191
14333
102k
    CEFBS_None, // LOCAL_GET_I32_S = 1192
14334
102k
    CEFBS_None, // LOCAL_GET_I64 = 1193
14335
102k
    CEFBS_None, // LOCAL_GET_I64_S = 1194
14336
102k
    CEFBS_HasSIMD128, // LOCAL_GET_V128 = 1195
14337
102k
    CEFBS_HasSIMD128, // LOCAL_GET_V128_S = 1196
14338
102k
    CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF = 1197
14339
102k
    CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S = 1198
14340
102k
    CEFBS_None, // LOCAL_SET_F32 = 1199
14341
102k
    CEFBS_None, // LOCAL_SET_F32_S = 1200
14342
102k
    CEFBS_None, // LOCAL_SET_F64 = 1201
14343
102k
    CEFBS_None, // LOCAL_SET_F64_S = 1202
14344
102k
    CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF = 1203
14345
102k
    CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S = 1204
14346
102k
    CEFBS_None, // LOCAL_SET_I32 = 1205
14347
102k
    CEFBS_None, // LOCAL_SET_I32_S = 1206
14348
102k
    CEFBS_None, // LOCAL_SET_I64 = 1207
14349
102k
    CEFBS_None, // LOCAL_SET_I64_S = 1208
14350
102k
    CEFBS_HasSIMD128, // LOCAL_SET_V128 = 1209
14351
102k
    CEFBS_HasSIMD128, // LOCAL_SET_V128_S = 1210
14352
102k
    CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF = 1211
14353
102k
    CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S = 1212
14354
102k
    CEFBS_None, // LOCAL_TEE_F32 = 1213
14355
102k
    CEFBS_None, // LOCAL_TEE_F32_S = 1214
14356
102k
    CEFBS_None, // LOCAL_TEE_F64 = 1215
14357
102k
    CEFBS_None, // LOCAL_TEE_F64_S = 1216
14358
102k
    CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF = 1217
14359
102k
    CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S = 1218
14360
102k
    CEFBS_None, // LOCAL_TEE_I32 = 1219
14361
102k
    CEFBS_None, // LOCAL_TEE_I32_S = 1220
14362
102k
    CEFBS_None, // LOCAL_TEE_I64 = 1221
14363
102k
    CEFBS_None, // LOCAL_TEE_I64_S = 1222
14364
102k
    CEFBS_HasSIMD128, // LOCAL_TEE_V128 = 1223
14365
102k
    CEFBS_HasSIMD128, // LOCAL_TEE_V128_S = 1224
14366
102k
    CEFBS_None, // LOOP = 1225
14367
102k
    CEFBS_None, // LOOP_S = 1226
14368
102k
    CEFBS_None, // LT_F32 = 1227
14369
102k
    CEFBS_None, // LT_F32_S = 1228
14370
102k
    CEFBS_HasSIMD128, // LT_F32x4 = 1229
14371
102k
    CEFBS_HasSIMD128, // LT_F32x4_S = 1230
14372
102k
    CEFBS_None, // LT_F64 = 1231
14373
102k
    CEFBS_None, // LT_F64_S = 1232
14374
102k
    CEFBS_HasSIMD128, // LT_F64x2 = 1233
14375
102k
    CEFBS_HasSIMD128, // LT_F64x2_S = 1234
14376
102k
    CEFBS_HasSIMD128, // LT_S_I16x8 = 1235
14377
102k
    CEFBS_HasSIMD128, // LT_S_I16x8_S = 1236
14378
102k
    CEFBS_None, // LT_S_I32 = 1237
14379
102k
    CEFBS_None, // LT_S_I32_S = 1238
14380
102k
    CEFBS_HasSIMD128, // LT_S_I32x4 = 1239
14381
102k
    CEFBS_HasSIMD128, // LT_S_I32x4_S = 1240
14382
102k
    CEFBS_None, // LT_S_I64 = 1241
14383
102k
    CEFBS_None, // LT_S_I64_S = 1242
14384
102k
    CEFBS_HasSIMD128, // LT_S_I64x2 = 1243
14385
102k
    CEFBS_HasSIMD128, // LT_S_I64x2_S = 1244
14386
102k
    CEFBS_HasSIMD128, // LT_S_I8x16 = 1245
14387
102k
    CEFBS_HasSIMD128, // LT_S_I8x16_S = 1246
14388
102k
    CEFBS_HasSIMD128, // LT_U_I16x8 = 1247
14389
102k
    CEFBS_HasSIMD128, // LT_U_I16x8_S = 1248
14390
102k
    CEFBS_None, // LT_U_I32 = 1249
14391
102k
    CEFBS_None, // LT_U_I32_S = 1250
14392
102k
    CEFBS_HasSIMD128, // LT_U_I32x4 = 1251
14393
102k
    CEFBS_HasSIMD128, // LT_U_I32x4_S = 1252
14394
102k
    CEFBS_None, // LT_U_I64 = 1253
14395
102k
    CEFBS_None, // LT_U_I64_S = 1254
14396
102k
    CEFBS_HasSIMD128, // LT_U_I8x16 = 1255
14397
102k
    CEFBS_HasSIMD128, // LT_U_I8x16_S = 1256
14398
102k
    CEFBS_HasRelaxedSIMD, // MADD_F32x4 = 1257
14399
102k
    CEFBS_HasRelaxedSIMD, // MADD_F32x4_S = 1258
14400
102k
    CEFBS_HasRelaxedSIMD, // MADD_F64x2 = 1259
14401
102k
    CEFBS_HasRelaxedSIMD, // MADD_F64x2_S = 1260
14402
102k
    CEFBS_None, // MAX_F32 = 1261
14403
102k
    CEFBS_None, // MAX_F32_S = 1262
14404
102k
    CEFBS_HasSIMD128, // MAX_F32x4 = 1263
14405
102k
    CEFBS_HasSIMD128, // MAX_F32x4_S = 1264
14406
102k
    CEFBS_None, // MAX_F64 = 1265
14407
102k
    CEFBS_None, // MAX_F64_S = 1266
14408
102k
    CEFBS_HasSIMD128, // MAX_F64x2 = 1267
14409
102k
    CEFBS_HasSIMD128, // MAX_F64x2_S = 1268
14410
102k
    CEFBS_HasSIMD128, // MAX_S_I16x8 = 1269
14411
102k
    CEFBS_HasSIMD128, // MAX_S_I16x8_S = 1270
14412
102k
    CEFBS_HasSIMD128, // MAX_S_I32x4 = 1271
14413
102k
    CEFBS_HasSIMD128, // MAX_S_I32x4_S = 1272
14414
102k
    CEFBS_HasSIMD128, // MAX_S_I8x16 = 1273
14415
102k
    CEFBS_HasSIMD128, // MAX_S_I8x16_S = 1274
14416
102k
    CEFBS_HasSIMD128, // MAX_U_I16x8 = 1275
14417
102k
    CEFBS_HasSIMD128, // MAX_U_I16x8_S = 1276
14418
102k
    CEFBS_HasSIMD128, // MAX_U_I32x4 = 1277
14419
102k
    CEFBS_HasSIMD128, // MAX_U_I32x4_S = 1278
14420
102k
    CEFBS_HasSIMD128, // MAX_U_I8x16 = 1279
14421
102k
    CEFBS_HasSIMD128, // MAX_U_I8x16_S = 1280
14422
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32 = 1281
14423
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S = 1282
14424
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64 = 1283
14425
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S = 1284
14426
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32 = 1285
14427
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S = 1286
14428
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64 = 1287
14429
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S = 1288
14430
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32 = 1289
14431
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S = 1290
14432
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64 = 1291
14433
102k
    CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S = 1292
14434
102k
    CEFBS_None, // MIN_F32 = 1293
14435
102k
    CEFBS_None, // MIN_F32_S = 1294
14436
102k
    CEFBS_HasSIMD128, // MIN_F32x4 = 1295
14437
102k
    CEFBS_HasSIMD128, // MIN_F32x4_S = 1296
14438
102k
    CEFBS_None, // MIN_F64 = 1297
14439
102k
    CEFBS_None, // MIN_F64_S = 1298
14440
102k
    CEFBS_HasSIMD128, // MIN_F64x2 = 1299
14441
102k
    CEFBS_HasSIMD128, // MIN_F64x2_S = 1300
14442
102k
    CEFBS_HasSIMD128, // MIN_S_I16x8 = 1301
14443
102k
    CEFBS_HasSIMD128, // MIN_S_I16x8_S = 1302
14444
102k
    CEFBS_HasSIMD128, // MIN_S_I32x4 = 1303
14445
102k
    CEFBS_HasSIMD128, // MIN_S_I32x4_S = 1304
14446
102k
    CEFBS_HasSIMD128, // MIN_S_I8x16 = 1305
14447
102k
    CEFBS_HasSIMD128, // MIN_S_I8x16_S = 1306
14448
102k
    CEFBS_HasSIMD128, // MIN_U_I16x8 = 1307
14449
102k
    CEFBS_HasSIMD128, // MIN_U_I16x8_S = 1308
14450
102k
    CEFBS_HasSIMD128, // MIN_U_I32x4 = 1309
14451
102k
    CEFBS_HasSIMD128, // MIN_U_I32x4_S = 1310
14452
102k
    CEFBS_HasSIMD128, // MIN_U_I8x16 = 1311
14453
102k
    CEFBS_HasSIMD128, // MIN_U_I8x16_S = 1312
14454
102k
    CEFBS_None, // MUL_F32 = 1313
14455
102k
    CEFBS_None, // MUL_F32_S = 1314
14456
102k
    CEFBS_HasSIMD128, // MUL_F32x4 = 1315
14457
102k
    CEFBS_HasSIMD128, // MUL_F32x4_S = 1316
14458
102k
    CEFBS_None, // MUL_F64 = 1317
14459
102k
    CEFBS_None, // MUL_F64_S = 1318
14460
102k
    CEFBS_HasSIMD128, // MUL_F64x2 = 1319
14461
102k
    CEFBS_HasSIMD128, // MUL_F64x2_S = 1320
14462
102k
    CEFBS_HasSIMD128, // MUL_I16x8 = 1321
14463
102k
    CEFBS_HasSIMD128, // MUL_I16x8_S = 1322
14464
102k
    CEFBS_None, // MUL_I32 = 1323
14465
102k
    CEFBS_None, // MUL_I32_S = 1324
14466
102k
    CEFBS_HasSIMD128, // MUL_I32x4 = 1325
14467
102k
    CEFBS_HasSIMD128, // MUL_I32x4_S = 1326
14468
102k
    CEFBS_None, // MUL_I64 = 1327
14469
102k
    CEFBS_None, // MUL_I64_S = 1328
14470
102k
    CEFBS_HasSIMD128, // MUL_I64x2 = 1329
14471
102k
    CEFBS_HasSIMD128, // MUL_I64x2_S = 1330
14472
102k
    CEFBS_HasSIMD128, // NARROW_S_I16x8 = 1331
14473
102k
    CEFBS_HasSIMD128, // NARROW_S_I16x8_S = 1332
14474
102k
    CEFBS_HasSIMD128, // NARROW_S_I8x16 = 1333
14475
102k
    CEFBS_HasSIMD128, // NARROW_S_I8x16_S = 1334
14476
102k
    CEFBS_HasSIMD128, // NARROW_U_I16x8 = 1335
14477
102k
    CEFBS_HasSIMD128, // NARROW_U_I16x8_S = 1336
14478
102k
    CEFBS_HasSIMD128, // NARROW_U_I8x16 = 1337
14479
102k
    CEFBS_HasSIMD128, // NARROW_U_I8x16_S = 1338
14480
102k
    CEFBS_None, // NEAREST_F32 = 1339
14481
102k
    CEFBS_None, // NEAREST_F32_S = 1340
14482
102k
    CEFBS_HasSIMD128, // NEAREST_F32x4 = 1341
14483
102k
    CEFBS_HasSIMD128, // NEAREST_F32x4_S = 1342
14484
102k
    CEFBS_None, // NEAREST_F64 = 1343
14485
102k
    CEFBS_None, // NEAREST_F64_S = 1344
14486
102k
    CEFBS_HasSIMD128, // NEAREST_F64x2 = 1345
14487
102k
    CEFBS_HasSIMD128, // NEAREST_F64x2_S = 1346
14488
102k
    CEFBS_None, // NEG_F32 = 1347
14489
102k
    CEFBS_None, // NEG_F32_S = 1348
14490
102k
    CEFBS_HasSIMD128, // NEG_F32x4 = 1349
14491
102k
    CEFBS_HasSIMD128, // NEG_F32x4_S = 1350
14492
102k
    CEFBS_None, // NEG_F64 = 1351
14493
102k
    CEFBS_None, // NEG_F64_S = 1352
14494
102k
    CEFBS_HasSIMD128, // NEG_F64x2 = 1353
14495
102k
    CEFBS_HasSIMD128, // NEG_F64x2_S = 1354
14496
102k
    CEFBS_HasSIMD128, // NEG_I16x8 = 1355
14497
102k
    CEFBS_HasSIMD128, // NEG_I16x8_S = 1356
14498
102k
    CEFBS_HasSIMD128, // NEG_I32x4 = 1357
14499
102k
    CEFBS_HasSIMD128, // NEG_I32x4_S = 1358
14500
102k
    CEFBS_HasSIMD128, // NEG_I64x2 = 1359
14501
102k
    CEFBS_HasSIMD128, // NEG_I64x2_S = 1360
14502
102k
    CEFBS_HasSIMD128, // NEG_I8x16 = 1361
14503
102k
    CEFBS_HasSIMD128, // NEG_I8x16_S = 1362
14504
102k
    CEFBS_None, // NE_F32 = 1363
14505
102k
    CEFBS_None, // NE_F32_S = 1364
14506
102k
    CEFBS_HasSIMD128, // NE_F32x4 = 1365
14507
102k
    CEFBS_HasSIMD128, // NE_F32x4_S = 1366
14508
102k
    CEFBS_None, // NE_F64 = 1367
14509
102k
    CEFBS_None, // NE_F64_S = 1368
14510
102k
    CEFBS_HasSIMD128, // NE_F64x2 = 1369
14511
102k
    CEFBS_HasSIMD128, // NE_F64x2_S = 1370
14512
102k
    CEFBS_HasSIMD128, // NE_I16x8 = 1371
14513
102k
    CEFBS_HasSIMD128, // NE_I16x8_S = 1372
14514
102k
    CEFBS_None, // NE_I32 = 1373
14515
102k
    CEFBS_None, // NE_I32_S = 1374
14516
102k
    CEFBS_HasSIMD128, // NE_I32x4 = 1375
14517
102k
    CEFBS_HasSIMD128, // NE_I32x4_S = 1376
14518
102k
    CEFBS_None, // NE_I64 = 1377
14519
102k
    CEFBS_None, // NE_I64_S = 1378
14520
102k
    CEFBS_HasSIMD128, // NE_I64x2 = 1379
14521
102k
    CEFBS_HasSIMD128, // NE_I64x2_S = 1380
14522
102k
    CEFBS_HasSIMD128, // NE_I8x16 = 1381
14523
102k
    CEFBS_HasSIMD128, // NE_I8x16_S = 1382
14524
102k
    CEFBS_HasRelaxedSIMD, // NMADD_F32x4 = 1383
14525
102k
    CEFBS_HasRelaxedSIMD, // NMADD_F32x4_S = 1384
14526
102k
    CEFBS_HasRelaxedSIMD, // NMADD_F64x2 = 1385
14527
102k
    CEFBS_HasRelaxedSIMD, // NMADD_F64x2_S = 1386
14528
102k
    CEFBS_None, // NOP = 1387
14529
102k
    CEFBS_None, // NOP_S = 1388
14530
102k
    CEFBS_HasSIMD128, // NOT = 1389
14531
102k
    CEFBS_HasSIMD128, // NOT_S = 1390
14532
102k
    CEFBS_HasSIMD128, // OR = 1391
14533
102k
    CEFBS_None, // OR_I32 = 1392
14534
102k
    CEFBS_None, // OR_I32_S = 1393
14535
102k
    CEFBS_None, // OR_I64 = 1394
14536
102k
    CEFBS_None, // OR_I64_S = 1395
14537
102k
    CEFBS_HasSIMD128, // OR_S = 1396
14538
102k
    CEFBS_HasSIMD128, // PMAX_F32x4 = 1397
14539
102k
    CEFBS_HasSIMD128, // PMAX_F32x4_S = 1398
14540
102k
    CEFBS_HasSIMD128, // PMAX_F64x2 = 1399
14541
102k
    CEFBS_HasSIMD128, // PMAX_F64x2_S = 1400
14542
102k
    CEFBS_HasSIMD128, // PMIN_F32x4 = 1401
14543
102k
    CEFBS_HasSIMD128, // PMIN_F32x4_S = 1402
14544
102k
    CEFBS_HasSIMD128, // PMIN_F64x2 = 1403
14545
102k
    CEFBS_HasSIMD128, // PMIN_F64x2_S = 1404
14546
102k
    CEFBS_None, // POPCNT_I32 = 1405
14547
102k
    CEFBS_None, // POPCNT_I32_S = 1406
14548
102k
    CEFBS_None, // POPCNT_I64 = 1407
14549
102k
    CEFBS_None, // POPCNT_I64_S = 1408
14550
102k
    CEFBS_HasSIMD128, // POPCNT_I8x16 = 1409
14551
102k
    CEFBS_HasSIMD128, // POPCNT_I8x16_S = 1410
14552
102k
    CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8 = 1411
14553
102k
    CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S = 1412
14554
102k
    CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF = 1413
14555
102k
    CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S = 1414
14556
102k
    CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF = 1415
14557
102k
    CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S = 1416
14558
102k
    CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF = 1417
14559
102k
    CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S = 1418
14560
102k
    CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF = 1419
14561
102k
    CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S = 1420
14562
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_DOT = 1421
14563
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD = 1422
14564
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S = 1423
14565
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT = 1424
14566
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S = 1425
14567
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S = 1426
14568
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8 = 1427
14569
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S = 1428
14570
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE = 1429
14571
102k
    CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S = 1430
14572
102k
    CEFBS_None, // REM_S_I32 = 1431
14573
102k
    CEFBS_None, // REM_S_I32_S = 1432
14574
102k
    CEFBS_None, // REM_S_I64 = 1433
14575
102k
    CEFBS_None, // REM_S_I64_S = 1434
14576
102k
    CEFBS_None, // REM_U_I32 = 1435
14577
102k
    CEFBS_None, // REM_U_I32_S = 1436
14578
102k
    CEFBS_None, // REM_U_I64 = 1437
14579
102k
    CEFBS_None, // REM_U_I64_S = 1438
14580
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_F32x4 = 1439
14581
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S = 1440
14582
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_F64x2 = 1441
14583
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S = 1442
14584
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_I16x8 = 1443
14585
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S = 1444
14586
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_I32x4 = 1445
14587
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S = 1446
14588
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_I64x2 = 1447
14589
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S = 1448
14590
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_I8x16 = 1449
14591
102k
    CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S = 1450
14592
102k
    CEFBS_HasExceptionHandling, // RETHROW = 1451
14593
102k
    CEFBS_HasExceptionHandling, // RETHROW_S = 1452
14594
102k
    CEFBS_None, // RETURN = 1453
14595
102k
    CEFBS_None, // RETURN_S = 1454
14596
102k
    CEFBS_HasTailCall, // RET_CALL = 1455
14597
102k
    CEFBS_HasTailCall, // RET_CALL_INDIRECT = 1456
14598
102k
    CEFBS_HasTailCall, // RET_CALL_INDIRECT_S = 1457
14599
102k
    CEFBS_HasTailCall, // RET_CALL_S = 1458
14600
102k
    CEFBS_None, // ROTL_I32 = 1459
14601
102k
    CEFBS_None, // ROTL_I32_S = 1460
14602
102k
    CEFBS_None, // ROTL_I64 = 1461
14603
102k
    CEFBS_None, // ROTL_I64_S = 1462
14604
102k
    CEFBS_None, // ROTR_I32 = 1463
14605
102k
    CEFBS_None, // ROTR_I32_S = 1464
14606
102k
    CEFBS_None, // ROTR_I64 = 1465
14607
102k
    CEFBS_None, // ROTR_I64_S = 1466
14608
102k
    CEFBS_HasReferenceTypes, // SELECT_EXTERNREF = 1467
14609
102k
    CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S = 1468
14610
102k
    CEFBS_None, // SELECT_F32 = 1469
14611
102k
    CEFBS_None, // SELECT_F32_S = 1470
14612
102k
    CEFBS_None, // SELECT_F64 = 1471
14613
102k
    CEFBS_None, // SELECT_F64_S = 1472
14614
102k
    CEFBS_HasReferenceTypes, // SELECT_FUNCREF = 1473
14615
102k
    CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S = 1474
14616
102k
    CEFBS_None, // SELECT_I32 = 1475
14617
102k
    CEFBS_None, // SELECT_I32_S = 1476
14618
102k
    CEFBS_None, // SELECT_I64 = 1477
14619
102k
    CEFBS_None, // SELECT_I64_S = 1478
14620
102k
    CEFBS_None, // SELECT_V128 = 1479
14621
102k
    CEFBS_None, // SELECT_V128_S = 1480
14622
102k
    CEFBS_HasSIMD128, // SHL_I16x8 = 1481
14623
102k
    CEFBS_HasSIMD128, // SHL_I16x8_S = 1482
14624
102k
    CEFBS_None, // SHL_I32 = 1483
14625
102k
    CEFBS_None, // SHL_I32_S = 1484
14626
102k
    CEFBS_HasSIMD128, // SHL_I32x4 = 1485
14627
102k
    CEFBS_HasSIMD128, // SHL_I32x4_S = 1486
14628
102k
    CEFBS_None, // SHL_I64 = 1487
14629
102k
    CEFBS_None, // SHL_I64_S = 1488
14630
102k
    CEFBS_HasSIMD128, // SHL_I64x2 = 1489
14631
102k
    CEFBS_HasSIMD128, // SHL_I64x2_S = 1490
14632
102k
    CEFBS_HasSIMD128, // SHL_I8x16 = 1491
14633
102k
    CEFBS_HasSIMD128, // SHL_I8x16_S = 1492
14634
102k
    CEFBS_HasSIMD128, // SHR_S_I16x8 = 1493
14635
102k
    CEFBS_HasSIMD128, // SHR_S_I16x8_S = 1494
14636
102k
    CEFBS_None, // SHR_S_I32 = 1495
14637
102k
    CEFBS_None, // SHR_S_I32_S = 1496
14638
102k
    CEFBS_HasSIMD128, // SHR_S_I32x4 = 1497
14639
102k
    CEFBS_HasSIMD128, // SHR_S_I32x4_S = 1498
14640
102k
    CEFBS_None, // SHR_S_I64 = 1499
14641
102k
    CEFBS_None, // SHR_S_I64_S = 1500
14642
102k
    CEFBS_HasSIMD128, // SHR_S_I64x2 = 1501
14643
102k
    CEFBS_HasSIMD128, // SHR_S_I64x2_S = 1502
14644
102k
    CEFBS_HasSIMD128, // SHR_S_I8x16 = 1503
14645
102k
    CEFBS_HasSIMD128, // SHR_S_I8x16_S = 1504
14646
102k
    CEFBS_HasSIMD128, // SHR_U_I16x8 = 1505
14647
102k
    CEFBS_HasSIMD128, // SHR_U_I16x8_S = 1506
14648
102k
    CEFBS_None, // SHR_U_I32 = 1507
14649
102k
    CEFBS_None, // SHR_U_I32_S = 1508
14650
102k
    CEFBS_HasSIMD128, // SHR_U_I32x4 = 1509
14651
102k
    CEFBS_HasSIMD128, // SHR_U_I32x4_S = 1510
14652
102k
    CEFBS_None, // SHR_U_I64 = 1511
14653
102k
    CEFBS_None, // SHR_U_I64_S = 1512
14654
102k
    CEFBS_HasSIMD128, // SHR_U_I64x2 = 1513
14655
102k
    CEFBS_HasSIMD128, // SHR_U_I64x2_S = 1514
14656
102k
    CEFBS_HasSIMD128, // SHR_U_I8x16 = 1515
14657
102k
    CEFBS_HasSIMD128, // SHR_U_I8x16_S = 1516
14658
102k
    CEFBS_HasSIMD128, // SHUFFLE = 1517
14659
102k
    CEFBS_HasSIMD128, // SHUFFLE_S = 1518
14660
102k
    CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4 = 1519
14661
102k
    CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S = 1520
14662
102k
    CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2 = 1521
14663
102k
    CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S = 1522
14664
102k
    CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4 = 1523
14665
102k
    CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S = 1524
14666
102k
    CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2 = 1525
14667
102k
    CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S = 1526
14668
102k
    CEFBS_HasSIMD128, // SPLAT_F32x4 = 1527
14669
102k
    CEFBS_HasSIMD128, // SPLAT_F32x4_S = 1528
14670
102k
    CEFBS_HasSIMD128, // SPLAT_F64x2 = 1529
14671
102k
    CEFBS_HasSIMD128, // SPLAT_F64x2_S = 1530
14672
102k
    CEFBS_HasSIMD128, // SPLAT_I16x8 = 1531
14673
102k
    CEFBS_HasSIMD128, // SPLAT_I16x8_S = 1532
14674
102k
    CEFBS_HasSIMD128, // SPLAT_I32x4 = 1533
14675
102k
    CEFBS_HasSIMD128, // SPLAT_I32x4_S = 1534
14676
102k
    CEFBS_HasSIMD128, // SPLAT_I64x2 = 1535
14677
102k
    CEFBS_HasSIMD128, // SPLAT_I64x2_S = 1536
14678
102k
    CEFBS_HasSIMD128, // SPLAT_I8x16 = 1537
14679
102k
    CEFBS_HasSIMD128, // SPLAT_I8x16_S = 1538
14680
102k
    CEFBS_None, // SQRT_F32 = 1539
14681
102k
    CEFBS_None, // SQRT_F32_S = 1540
14682
102k
    CEFBS_HasSIMD128, // SQRT_F32x4 = 1541
14683
102k
    CEFBS_HasSIMD128, // SQRT_F32x4_S = 1542
14684
102k
    CEFBS_None, // SQRT_F64 = 1543
14685
102k
    CEFBS_None, // SQRT_F64_S = 1544
14686
102k
    CEFBS_HasSIMD128, // SQRT_F64x2 = 1545
14687
102k
    CEFBS_HasSIMD128, // SQRT_F64x2_S = 1546
14688
102k
    CEFBS_None, // STORE16_I32_A32 = 1547
14689
102k
    CEFBS_None, // STORE16_I32_A32_S = 1548
14690
102k
    CEFBS_None, // STORE16_I32_A64 = 1549
14691
102k
    CEFBS_None, // STORE16_I32_A64_S = 1550
14692
102k
    CEFBS_None, // STORE16_I64_A32 = 1551
14693
102k
    CEFBS_None, // STORE16_I64_A32_S = 1552
14694
102k
    CEFBS_None, // STORE16_I64_A64 = 1553
14695
102k
    CEFBS_None, // STORE16_I64_A64_S = 1554
14696
102k
    CEFBS_None, // STORE32_I64_A32 = 1555
14697
102k
    CEFBS_None, // STORE32_I64_A32_S = 1556
14698
102k
    CEFBS_None, // STORE32_I64_A64 = 1557
14699
102k
    CEFBS_None, // STORE32_I64_A64_S = 1558
14700
102k
    CEFBS_None, // STORE8_I32_A32 = 1559
14701
102k
    CEFBS_None, // STORE8_I32_A32_S = 1560
14702
102k
    CEFBS_None, // STORE8_I32_A64 = 1561
14703
102k
    CEFBS_None, // STORE8_I32_A64_S = 1562
14704
102k
    CEFBS_None, // STORE8_I64_A32 = 1563
14705
102k
    CEFBS_None, // STORE8_I64_A32_S = 1564
14706
102k
    CEFBS_None, // STORE8_I64_A64 = 1565
14707
102k
    CEFBS_None, // STORE8_I64_A64_S = 1566
14708
102k
    CEFBS_None, // STORE_F32_A32 = 1567
14709
102k
    CEFBS_None, // STORE_F32_A32_S = 1568
14710
102k
    CEFBS_None, // STORE_F32_A64 = 1569
14711
102k
    CEFBS_None, // STORE_F32_A64_S = 1570
14712
102k
    CEFBS_None, // STORE_F64_A32 = 1571
14713
102k
    CEFBS_None, // STORE_F64_A32_S = 1572
14714
102k
    CEFBS_None, // STORE_F64_A64 = 1573
14715
102k
    CEFBS_None, // STORE_F64_A64_S = 1574
14716
102k
    CEFBS_None, // STORE_I32_A32 = 1575
14717
102k
    CEFBS_None, // STORE_I32_A32_S = 1576
14718
102k
    CEFBS_None, // STORE_I32_A64 = 1577
14719
102k
    CEFBS_None, // STORE_I32_A64_S = 1578
14720
102k
    CEFBS_None, // STORE_I64_A32 = 1579
14721
102k
    CEFBS_None, // STORE_I64_A32_S = 1580
14722
102k
    CEFBS_None, // STORE_I64_A64 = 1581
14723
102k
    CEFBS_None, // STORE_I64_A64_S = 1582
14724
102k
    CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32 = 1583
14725
102k
    CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S = 1584
14726
102k
    CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64 = 1585
14727
102k
    CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S = 1586
14728
102k
    CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32 = 1587
14729
102k
    CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S = 1588
14730
102k
    CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64 = 1589
14731
102k
    CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S = 1590
14732
102k
    CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32 = 1591
14733
102k
    CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S = 1592
14734
102k
    CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64 = 1593
14735
102k
    CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S = 1594
14736
102k
    CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32 = 1595
14737
102k
    CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S = 1596
14738
102k
    CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64 = 1597
14739
102k
    CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S = 1598
14740
102k
    CEFBS_HasSIMD128, // STORE_V128_A32 = 1599
14741
102k
    CEFBS_HasSIMD128, // STORE_V128_A32_S = 1600
14742
102k
    CEFBS_HasSIMD128, // STORE_V128_A64 = 1601
14743
102k
    CEFBS_HasSIMD128, // STORE_V128_A64_S = 1602
14744
102k
    CEFBS_None, // SUB_F32 = 1603
14745
102k
    CEFBS_None, // SUB_F32_S = 1604
14746
102k
    CEFBS_HasSIMD128, // SUB_F32x4 = 1605
14747
102k
    CEFBS_HasSIMD128, // SUB_F32x4_S = 1606
14748
102k
    CEFBS_None, // SUB_F64 = 1607
14749
102k
    CEFBS_None, // SUB_F64_S = 1608
14750
102k
    CEFBS_HasSIMD128, // SUB_F64x2 = 1609
14751
102k
    CEFBS_HasSIMD128, // SUB_F64x2_S = 1610
14752
102k
    CEFBS_HasSIMD128, // SUB_I16x8 = 1611
14753
102k
    CEFBS_HasSIMD128, // SUB_I16x8_S = 1612
14754
102k
    CEFBS_None, // SUB_I32 = 1613
14755
102k
    CEFBS_None, // SUB_I32_S = 1614
14756
102k
    CEFBS_HasSIMD128, // SUB_I32x4 = 1615
14757
102k
    CEFBS_HasSIMD128, // SUB_I32x4_S = 1616
14758
102k
    CEFBS_None, // SUB_I64 = 1617
14759
102k
    CEFBS_None, // SUB_I64_S = 1618
14760
102k
    CEFBS_HasSIMD128, // SUB_I64x2 = 1619
14761
102k
    CEFBS_HasSIMD128, // SUB_I64x2_S = 1620
14762
102k
    CEFBS_HasSIMD128, // SUB_I8x16 = 1621
14763
102k
    CEFBS_HasSIMD128, // SUB_I8x16_S = 1622
14764
102k
    CEFBS_HasSIMD128, // SUB_SAT_S_I16x8 = 1623
14765
102k
    CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S = 1624
14766
102k
    CEFBS_HasSIMD128, // SUB_SAT_S_I8x16 = 1625
14767
102k
    CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S = 1626
14768
102k
    CEFBS_HasSIMD128, // SUB_SAT_U_I16x8 = 1627
14769
102k
    CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S = 1628
14770
102k
    CEFBS_HasSIMD128, // SUB_SAT_U_I8x16 = 1629
14771
102k
    CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S = 1630
14772
102k
    CEFBS_HasSIMD128, // SWIZZLE = 1631
14773
102k
    CEFBS_HasSIMD128, // SWIZZLE_S = 1632
14774
102k
    CEFBS_HasReferenceTypes, // TABLE_COPY = 1633
14775
102k
    CEFBS_HasReferenceTypes, // TABLE_COPY_S = 1634
14776
102k
    CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF = 1635
14777
102k
    CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S = 1636
14778
102k
    CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF = 1637
14779
102k
    CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S = 1638
14780
102k
    CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF = 1639
14781
102k
    CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S = 1640
14782
102k
    CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF = 1641
14783
102k
    CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S = 1642
14784
102k
    CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF = 1643
14785
102k
    CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S = 1644
14786
102k
    CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF = 1645
14787
102k
    CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S = 1646
14788
102k
    CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF = 1647
14789
102k
    CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S = 1648
14790
102k
    CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF = 1649
14791
102k
    CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S = 1650
14792
102k
    CEFBS_HasReferenceTypes, // TABLE_SIZE = 1651
14793
102k
    CEFBS_HasReferenceTypes, // TABLE_SIZE_S = 1652
14794
102k
    CEFBS_HasReferenceTypes, // TEE_EXTERNREF = 1653
14795
102k
    CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S = 1654
14796
102k
    CEFBS_None, // TEE_F32 = 1655
14797
102k
    CEFBS_None, // TEE_F32_S = 1656
14798
102k
    CEFBS_None, // TEE_F64 = 1657
14799
102k
    CEFBS_None, // TEE_F64_S = 1658
14800
102k
    CEFBS_HasReferenceTypes, // TEE_FUNCREF = 1659
14801
102k
    CEFBS_HasReferenceTypes, // TEE_FUNCREF_S = 1660
14802
102k
    CEFBS_None, // TEE_I32 = 1661
14803
102k
    CEFBS_None, // TEE_I32_S = 1662
14804
102k
    CEFBS_None, // TEE_I64 = 1663
14805
102k
    CEFBS_None, // TEE_I64_S = 1664
14806
102k
    CEFBS_HasSIMD128, // TEE_V128 = 1665
14807
102k
    CEFBS_HasSIMD128, // TEE_V128_S = 1666
14808
102k
    CEFBS_HasExceptionHandling, // THROW = 1667
14809
102k
    CEFBS_HasExceptionHandling, // THROW_S = 1668
14810
102k
    CEFBS_None, // TRUNC_F32 = 1669
14811
102k
    CEFBS_None, // TRUNC_F32_S = 1670
14812
102k
    CEFBS_HasSIMD128, // TRUNC_F32x4 = 1671
14813
102k
    CEFBS_HasSIMD128, // TRUNC_F32x4_S = 1672
14814
102k
    CEFBS_None, // TRUNC_F64 = 1673
14815
102k
    CEFBS_None, // TRUNC_F64_S = 1674
14816
102k
    CEFBS_HasSIMD128, // TRUNC_F64x2 = 1675
14817
102k
    CEFBS_HasSIMD128, // TRUNC_F64x2_S = 1676
14818
102k
    CEFBS_HasExceptionHandling, // TRY = 1677
14819
102k
    CEFBS_HasExceptionHandling, // TRY_S = 1678
14820
102k
    CEFBS_None, // UNREACHABLE = 1679
14821
102k
    CEFBS_None, // UNREACHABLE_S = 1680
14822
102k
    CEFBS_HasSIMD128, // XOR = 1681
14823
102k
    CEFBS_None, // XOR_I32 = 1682
14824
102k
    CEFBS_None, // XOR_I32_S = 1683
14825
102k
    CEFBS_None, // XOR_I64 = 1684
14826
102k
    CEFBS_None, // XOR_I64_S = 1685
14827
102k
    CEFBS_HasSIMD128, // XOR_S = 1686
14828
102k
    CEFBS_None, // anonymous_7277MEMORY_GROW_A32 = 1687
14829
102k
    CEFBS_None, // anonymous_7277MEMORY_GROW_A32_S = 1688
14830
102k
    CEFBS_None, // anonymous_7277MEMORY_SIZE_A32 = 1689
14831
102k
    CEFBS_None, // anonymous_7277MEMORY_SIZE_A32_S = 1690
14832
102k
    CEFBS_None, // anonymous_7278MEMORY_GROW_A64 = 1691
14833
102k
    CEFBS_None, // anonymous_7278MEMORY_GROW_A64_S = 1692
14834
102k
    CEFBS_None, // anonymous_7278MEMORY_SIZE_A64 = 1693
14835
102k
    CEFBS_None, // anonymous_7278MEMORY_SIZE_A64_S = 1694
14836
102k
    CEFBS_HasBulkMemory, // anonymous_7959DATA_DROP = 1695
14837
102k
    CEFBS_HasBulkMemory, // anonymous_7959DATA_DROP_S = 1696
14838
102k
    CEFBS_HasBulkMemory, // anonymous_7959MEMORY_COPY_A32 = 1697
14839
102k
    CEFBS_HasBulkMemory, // anonymous_7959MEMORY_COPY_A32_S = 1698
14840
102k
    CEFBS_HasBulkMemory, // anonymous_7959MEMORY_FILL_A32 = 1699
14841
102k
    CEFBS_HasBulkMemory, // anonymous_7959MEMORY_FILL_A32_S = 1700
14842
102k
    CEFBS_HasBulkMemory, // anonymous_7959MEMORY_INIT_A32 = 1701
14843
102k
    CEFBS_HasBulkMemory, // anonymous_7959MEMORY_INIT_A32_S = 1702
14844
102k
    CEFBS_HasBulkMemory, // anonymous_7960DATA_DROP = 1703
14845
102k
    CEFBS_HasBulkMemory, // anonymous_7960DATA_DROP_S = 1704
14846
102k
    CEFBS_HasBulkMemory, // anonymous_7960MEMORY_COPY_A64 = 1705
14847
102k
    CEFBS_HasBulkMemory, // anonymous_7960MEMORY_COPY_A64_S = 1706
14848
102k
    CEFBS_HasBulkMemory, // anonymous_7960MEMORY_FILL_A64 = 1707
14849
102k
    CEFBS_HasBulkMemory, // anonymous_7960MEMORY_FILL_A64_S = 1708
14850
102k
    CEFBS_HasBulkMemory, // anonymous_7960MEMORY_INIT_A64 = 1709
14851
102k
    CEFBS_HasBulkMemory, // anonymous_7960MEMORY_INIT_A64_S = 1710
14852
102k
    CEFBS_HasSIMD128, // convert_low_s_F64x2 = 1711
14853
102k
    CEFBS_HasSIMD128, // convert_low_s_F64x2_S = 1712
14854
102k
    CEFBS_HasSIMD128, // convert_low_u_F64x2 = 1713
14855
102k
    CEFBS_HasSIMD128, // convert_low_u_F64x2_S = 1714
14856
102k
    CEFBS_HasSIMD128, // demote_zero_F32x4 = 1715
14857
102k
    CEFBS_HasSIMD128, // demote_zero_F32x4_S = 1716
14858
102k
    CEFBS_HasSIMD128, // extend_high_s_I16x8 = 1717
14859
102k
    CEFBS_HasSIMD128, // extend_high_s_I16x8_S = 1718
14860
102k
    CEFBS_HasSIMD128, // extend_high_s_I32x4 = 1719
14861
102k
    CEFBS_HasSIMD128, // extend_high_s_I32x4_S = 1720
14862
102k
    CEFBS_HasSIMD128, // extend_high_s_I64x2 = 1721
14863
102k
    CEFBS_HasSIMD128, // extend_high_s_I64x2_S = 1722
14864
102k
    CEFBS_HasSIMD128, // extend_high_u_I16x8 = 1723
14865
102k
    CEFBS_HasSIMD128, // extend_high_u_I16x8_S = 1724
14866
102k
    CEFBS_HasSIMD128, // extend_high_u_I32x4 = 1725
14867
102k
    CEFBS_HasSIMD128, // extend_high_u_I32x4_S = 1726
14868
102k
    CEFBS_HasSIMD128, // extend_high_u_I64x2 = 1727
14869
102k
    CEFBS_HasSIMD128, // extend_high_u_I64x2_S = 1728
14870
102k
    CEFBS_HasSIMD128, // extend_low_s_I16x8 = 1729
14871
102k
    CEFBS_HasSIMD128, // extend_low_s_I16x8_S = 1730
14872
102k
    CEFBS_HasSIMD128, // extend_low_s_I32x4 = 1731
14873
102k
    CEFBS_HasSIMD128, // extend_low_s_I32x4_S = 1732
14874
102k
    CEFBS_HasSIMD128, // extend_low_s_I64x2 = 1733
14875
102k
    CEFBS_HasSIMD128, // extend_low_s_I64x2_S = 1734
14876
102k
    CEFBS_HasSIMD128, // extend_low_u_I16x8 = 1735
14877
102k
    CEFBS_HasSIMD128, // extend_low_u_I16x8_S = 1736
14878
102k
    CEFBS_HasSIMD128, // extend_low_u_I32x4 = 1737
14879
102k
    CEFBS_HasSIMD128, // extend_low_u_I32x4_S = 1738
14880
102k
    CEFBS_HasSIMD128, // extend_low_u_I64x2 = 1739
14881
102k
    CEFBS_HasSIMD128, // extend_low_u_I64x2_S = 1740
14882
102k
    CEFBS_HasSIMD128, // fp_to_sint_I32x4 = 1741
14883
102k
    CEFBS_HasSIMD128, // fp_to_sint_I32x4_S = 1742
14884
102k
    CEFBS_HasSIMD128, // fp_to_uint_I32x4 = 1743
14885
102k
    CEFBS_HasSIMD128, // fp_to_uint_I32x4_S = 1744
14886
102k
    CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I16x8 = 1745
14887
102k
    CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I16x8_S = 1746
14888
102k
    CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I32x4 = 1747
14889
102k
    CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I32x4_S = 1748
14890
102k
    CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I16x8 = 1749
14891
102k
    CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I16x8_S = 1750
14892
102k
    CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I32x4 = 1751
14893
102k
    CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I32x4_S = 1752
14894
102k
    CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4 = 1753
14895
102k
    CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S = 1754
14896
102k
    CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4 = 1755
14897
102k
    CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1756
14898
102k
    CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4 = 1757
14899
102k
    CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S = 1758
14900
102k
    CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1759
14901
102k
    CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1760
14902
102k
    CEFBS_HasSIMD128, // promote_low_F64x2 = 1761
14903
102k
    CEFBS_HasSIMD128, // promote_low_F64x2_S = 1762
14904
102k
    CEFBS_HasSIMD128, // sint_to_fp_F32x4 = 1763
14905
102k
    CEFBS_HasSIMD128, // sint_to_fp_F32x4_S = 1764
14906
102k
    CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4 = 1765
14907
102k
    CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S = 1766
14908
102k
    CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4 = 1767
14909
102k
    CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S = 1768
14910
102k
    CEFBS_HasSIMD128, // uint_to_fp_F32x4 = 1769
14911
102k
    CEFBS_HasSIMD128, // uint_to_fp_F32x4_S = 1770
14912
102k
  };
14913
14914
102k
  assert(Opcode < 1771);
14915
0
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
14916
102k
}
14917
14918
} // end namespace WebAssembly_MC
14919
} // end namespace llvm
14920
#endif // GET_COMPUTE_FEATURES
14921
14922
#ifdef GET_AVAILABLE_OPCODE_CHECKER
14923
#undef GET_AVAILABLE_OPCODE_CHECKER
14924
namespace llvm {
14925
namespace WebAssembly_MC {
14926
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
14927
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
14928
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
14929
  FeatureBitset MissingFeatures =
14930
      (AvailableFeatures & RequiredFeatures) ^
14931
      RequiredFeatures;
14932
  return !MissingFeatures.any();
14933
}
14934
} // end namespace WebAssembly_MC
14935
} // end namespace llvm
14936
#endif // GET_AVAILABLE_OPCODE_CHECKER
14937
14938
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
14939
#undef ENABLE_INSTR_PREDICATE_VERIFIER
14940
#include <sstream>
14941
14942
namespace llvm {
14943
namespace WebAssembly_MC {
14944
14945
#ifndef NDEBUG
14946
static const char *SubtargetFeatureNames[] = {
14947
  "Feature_HasAtomics",
14948
  "Feature_HasBulkMemory",
14949
  "Feature_HasExceptionHandling",
14950
  "Feature_HasExtendedConst",
14951
  "Feature_HasMultiMemory",
14952
  "Feature_HasMultivalue",
14953
  "Feature_HasNontrappingFPToInt",
14954
  "Feature_HasReferenceTypes",
14955
  "Feature_HasRelaxedSIMD",
14956
  "Feature_HasSIMD128",
14957
  "Feature_HasSignExt",
14958
  "Feature_HasTailCall",
14959
  "Feature_NotHasNontrappingFPToInt",
14960
  nullptr
14961
};
14962
14963
#endif // NDEBUG
14964
14965
void verifyInstructionPredicates(
14966
102k
    unsigned Opcode, const FeatureBitset &Features) {
14967
102k
#ifndef NDEBUG
14968
102k
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
14969
102k
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
14970
102k
  FeatureBitset MissingFeatures =
14971
102k
      (AvailableFeatures & RequiredFeatures) ^
14972
102k
      RequiredFeatures;
14973
102k
  if (MissingFeatures.any()) {
14974
0
    std::ostringstream Msg;
14975
0
    Msg << "Attempting to emit " << &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]]
14976
0
        << " instruction but the ";
14977
0
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
14978
0
      if (MissingFeatures.test(i))
14979
0
        Msg << SubtargetFeatureNames[i] << " ";
14980
0
    Msg << "predicate(s) are not met";
14981
0
    report_fatal_error(Msg.str().c_str());
14982
0
  }
14983
102k
#endif // NDEBUG
14984
102k
}
14985
} // end namespace WebAssembly_MC
14986
} // end namespace llvm
14987
#endif // ENABLE_INSTR_PREDICATE_VERIFIER
14988
14989
#ifdef GET_INSTRMAP_INFO
14990
#undef GET_INSTRMAP_INFO
14991
namespace llvm {
14992
14993
namespace WebAssembly {
14994
14995
enum IsWasm64 {
14996
  IsWasm64_1
14997
};
14998
14999
enum StackBased {
15000
  StackBased_0,
15001
  StackBased_1
15002
};
15003
15004
// getRegisterOpcode
15005
LLVM_READONLY
15006
0
int getRegisterOpcode(uint16_t Opcode) {
15007
0
static const uint16_t getRegisterOpcodeTable[][2] = {
15008
0
  { WebAssembly::CALL_PARAMS_S, WebAssembly::CALL_PARAMS },
15009
0
  { WebAssembly::CALL_RESULTS_S, WebAssembly::CALL_RESULTS },
15010
0
  { WebAssembly::CATCHRET_S, WebAssembly::CATCHRET },
15011
0
  { WebAssembly::CLEANUPRET_S, WebAssembly::CLEANUPRET },
15012
0
  { WebAssembly::COMPILER_FENCE_S, WebAssembly::COMPILER_FENCE },
15013
0
  { WebAssembly::RET_CALL_RESULTS_S, WebAssembly::RET_CALL_RESULTS },
15014
0
  { WebAssembly::ABS_F32_S, WebAssembly::ABS_F32 },
15015
0
  { WebAssembly::ABS_F32x4_S, WebAssembly::ABS_F32x4 },
15016
0
  { WebAssembly::ABS_F64_S, WebAssembly::ABS_F64 },
15017
0
  { WebAssembly::ABS_F64x2_S, WebAssembly::ABS_F64x2 },
15018
0
  { WebAssembly::ABS_I16x8_S, WebAssembly::ABS_I16x8 },
15019
0
  { WebAssembly::ABS_I32x4_S, WebAssembly::ABS_I32x4 },
15020
0
  { WebAssembly::ABS_I64x2_S, WebAssembly::ABS_I64x2 },
15021
0
  { WebAssembly::ABS_I8x16_S, WebAssembly::ABS_I8x16 },
15022
0
  { WebAssembly::ADD_F32_S, WebAssembly::ADD_F32 },
15023
0
  { WebAssembly::ADD_F32x4_S, WebAssembly::ADD_F32x4 },
15024
0
  { WebAssembly::ADD_F64_S, WebAssembly::ADD_F64 },
15025
0
  { WebAssembly::ADD_F64x2_S, WebAssembly::ADD_F64x2 },
15026
0
  { WebAssembly::ADD_I16x8_S, WebAssembly::ADD_I16x8 },
15027
0
  { WebAssembly::ADD_I32_S, WebAssembly::ADD_I32 },
15028
0
  { WebAssembly::ADD_I32x4_S, WebAssembly::ADD_I32x4 },
15029
0
  { WebAssembly::ADD_I64_S, WebAssembly::ADD_I64 },
15030
0
  { WebAssembly::ADD_I64x2_S, WebAssembly::ADD_I64x2 },
15031
0
  { WebAssembly::ADD_I8x16_S, WebAssembly::ADD_I8x16 },
15032
0
  { WebAssembly::ADD_SAT_S_I16x8_S, WebAssembly::ADD_SAT_S_I16x8 },
15033
0
  { WebAssembly::ADD_SAT_S_I8x16_S, WebAssembly::ADD_SAT_S_I8x16 },
15034
0
  { WebAssembly::ADD_SAT_U_I16x8_S, WebAssembly::ADD_SAT_U_I16x8 },
15035
0
  { WebAssembly::ADD_SAT_U_I8x16_S, WebAssembly::ADD_SAT_U_I8x16 },
15036
0
  { WebAssembly::ADJCALLSTACKDOWN_S, WebAssembly::ADJCALLSTACKDOWN },
15037
0
  { WebAssembly::ADJCALLSTACKUP_S, WebAssembly::ADJCALLSTACKUP },
15038
0
  { WebAssembly::ALLTRUE_I16x8_S, WebAssembly::ALLTRUE_I16x8 },
15039
0
  { WebAssembly::ALLTRUE_I32x4_S, WebAssembly::ALLTRUE_I32x4 },
15040
0
  { WebAssembly::ALLTRUE_I64x2_S, WebAssembly::ALLTRUE_I64x2 },
15041
0
  { WebAssembly::ALLTRUE_I8x16_S, WebAssembly::ALLTRUE_I8x16 },
15042
0
  { WebAssembly::ANDNOT_S, WebAssembly::ANDNOT },
15043
0
  { WebAssembly::AND_I32_S, WebAssembly::AND_I32 },
15044
0
  { WebAssembly::AND_I64_S, WebAssembly::AND_I64 },
15045
0
  { WebAssembly::AND_S, WebAssembly::AND },
15046
0
  { WebAssembly::ANYTRUE_S, WebAssembly::ANYTRUE },
15047
0
  { WebAssembly::ARGUMENT_externref_S, WebAssembly::ARGUMENT_externref },
15048
0
  { WebAssembly::ARGUMENT_f32_S, WebAssembly::ARGUMENT_f32 },
15049
0
  { WebAssembly::ARGUMENT_f64_S, WebAssembly::ARGUMENT_f64 },
15050
0
  { WebAssembly::ARGUMENT_funcref_S, WebAssembly::ARGUMENT_funcref },
15051
0
  { WebAssembly::ARGUMENT_i32_S, WebAssembly::ARGUMENT_i32 },
15052
0
  { WebAssembly::ARGUMENT_i64_S, WebAssembly::ARGUMENT_i64 },
15053
0
  { WebAssembly::ARGUMENT_v16i8_S, WebAssembly::ARGUMENT_v16i8 },
15054
0
  { WebAssembly::ARGUMENT_v2f64_S, WebAssembly::ARGUMENT_v2f64 },
15055
0
  { WebAssembly::ARGUMENT_v2i64_S, WebAssembly::ARGUMENT_v2i64 },
15056
0
  { WebAssembly::ARGUMENT_v4f32_S, WebAssembly::ARGUMENT_v4f32 },
15057
0
  { WebAssembly::ARGUMENT_v4i32_S, WebAssembly::ARGUMENT_v4i32 },
15058
0
  { WebAssembly::ARGUMENT_v8i16_S, WebAssembly::ARGUMENT_v8i16 },
15059
0
  { WebAssembly::ATOMIC_FENCE_S, WebAssembly::ATOMIC_FENCE },
15060
0
  { WebAssembly::ATOMIC_LOAD16_U_I32_A32_S, WebAssembly::ATOMIC_LOAD16_U_I32_A32 },
15061
0
  { WebAssembly::ATOMIC_LOAD16_U_I32_A64_S, WebAssembly::ATOMIC_LOAD16_U_I32_A64 },
15062
0
  { WebAssembly::ATOMIC_LOAD16_U_I64_A32_S, WebAssembly::ATOMIC_LOAD16_U_I64_A32 },
15063
0
  { WebAssembly::ATOMIC_LOAD16_U_I64_A64_S, WebAssembly::ATOMIC_LOAD16_U_I64_A64 },
15064
0
  { WebAssembly::ATOMIC_LOAD32_U_I64_A32_S, WebAssembly::ATOMIC_LOAD32_U_I64_A32 },
15065
0
  { WebAssembly::ATOMIC_LOAD32_U_I64_A64_S, WebAssembly::ATOMIC_LOAD32_U_I64_A64 },
15066
0
  { WebAssembly::ATOMIC_LOAD8_U_I32_A32_S, WebAssembly::ATOMIC_LOAD8_U_I32_A32 },
15067
0
  { WebAssembly::ATOMIC_LOAD8_U_I32_A64_S, WebAssembly::ATOMIC_LOAD8_U_I32_A64 },
15068
0
  { WebAssembly::ATOMIC_LOAD8_U_I64_A32_S, WebAssembly::ATOMIC_LOAD8_U_I64_A32 },
15069
0
  { WebAssembly::ATOMIC_LOAD8_U_I64_A64_S, WebAssembly::ATOMIC_LOAD8_U_I64_A64 },
15070
0
  { WebAssembly::ATOMIC_LOAD_I32_A32_S, WebAssembly::ATOMIC_LOAD_I32_A32 },
15071
0
  { WebAssembly::ATOMIC_LOAD_I32_A64_S, WebAssembly::ATOMIC_LOAD_I32_A64 },
15072
0
  { WebAssembly::ATOMIC_LOAD_I64_A32_S, WebAssembly::ATOMIC_LOAD_I64_A32 },
15073
0
  { WebAssembly::ATOMIC_LOAD_I64_A64_S, WebAssembly::ATOMIC_LOAD_I64_A64 },
15074
0
  { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32 },
15075
0
  { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64 },
15076
0
  { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32 },
15077
0
  { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64 },
15078
0
  { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A32 },
15079
0
  { WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64 },
15080
0
  { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A32 },
15081
0
  { WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64 },
15082
0
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32 },
15083
0
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
15084
0
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32 },
15085
0
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
15086
0
  { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A32 },
15087
0
  { WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64 },
15088
0
  { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A32 },
15089
0
  { WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64 },
15090
0
  { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32 },
15091
0
  { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64 },
15092
0
  { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32 },
15093
0
  { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64 },
15094
0
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32 },
15095
0
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64 },
15096
0
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32 },
15097
0
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64 },
15098
0
  { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32 },
15099
0
  { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64 },
15100
0
  { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32 },
15101
0
  { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64 },
15102
0
  { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32 },
15103
0
  { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64 },
15104
0
  { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A32 },
15105
0
  { WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64 },
15106
0
  { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32 },
15107
0
  { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
15108
0
  { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A32 },
15109
0
  { WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64 },
15110
0
  { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32 },
15111
0
  { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64 },
15112
0
  { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32 },
15113
0
  { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64 },
15114
0
  { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32 },
15115
0
  { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64 },
15116
0
  { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32 },
15117
0
  { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64 },
15118
0
  { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32 },
15119
0
  { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64 },
15120
0
  { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A32 },
15121
0
  { WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64 },
15122
0
  { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A32 },
15123
0
  { WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64 },
15124
0
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32 },
15125
0
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
15126
0
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32 },
15127
0
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
15128
0
  { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A32 },
15129
0
  { WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64 },
15130
0
  { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A32 },
15131
0
  { WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64 },
15132
0
  { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32 },
15133
0
  { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64 },
15134
0
  { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32 },
15135
0
  { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64 },
15136
0
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32 },
15137
0
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64 },
15138
0
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32 },
15139
0
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64 },
15140
0
  { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32 },
15141
0
  { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64 },
15142
0
  { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32 },
15143
0
  { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64 },
15144
0
  { WebAssembly::ATOMIC_RMW_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW_ADD_I32_A32 },
15145
0
  { WebAssembly::ATOMIC_RMW_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW_ADD_I32_A64 },
15146
0
  { WebAssembly::ATOMIC_RMW_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW_ADD_I64_A32 },
15147
0
  { WebAssembly::ATOMIC_RMW_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW_ADD_I64_A64 },
15148
0
  { WebAssembly::ATOMIC_RMW_AND_I32_A32_S, WebAssembly::ATOMIC_RMW_AND_I32_A32 },
15149
0
  { WebAssembly::ATOMIC_RMW_AND_I32_A64_S, WebAssembly::ATOMIC_RMW_AND_I32_A64 },
15150
0
  { WebAssembly::ATOMIC_RMW_AND_I64_A32_S, WebAssembly::ATOMIC_RMW_AND_I64_A32 },
15151
0
  { WebAssembly::ATOMIC_RMW_AND_I64_A64_S, WebAssembly::ATOMIC_RMW_AND_I64_A64 },
15152
0
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32 },
15153
0
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64 },
15154
0
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32 },
15155
0
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64 },
15156
0
  { WebAssembly::ATOMIC_RMW_OR_I32_A32_S, WebAssembly::ATOMIC_RMW_OR_I32_A32 },
15157
0
  { WebAssembly::ATOMIC_RMW_OR_I32_A64_S, WebAssembly::ATOMIC_RMW_OR_I32_A64 },
15158
0
  { WebAssembly::ATOMIC_RMW_OR_I64_A32_S, WebAssembly::ATOMIC_RMW_OR_I64_A32 },
15159
0
  { WebAssembly::ATOMIC_RMW_OR_I64_A64_S, WebAssembly::ATOMIC_RMW_OR_I64_A64 },
15160
0
  { WebAssembly::ATOMIC_RMW_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW_SUB_I32_A32 },
15161
0
  { WebAssembly::ATOMIC_RMW_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW_SUB_I32_A64 },
15162
0
  { WebAssembly::ATOMIC_RMW_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW_SUB_I64_A32 },
15163
0
  { WebAssembly::ATOMIC_RMW_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW_SUB_I64_A64 },
15164
0
  { WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A32 },
15165
0
  { WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A64 },
15166
0
  { WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A32 },
15167
0
  { WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A64 },
15168
0
  { WebAssembly::ATOMIC_RMW_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW_XOR_I32_A32 },
15169
0
  { WebAssembly::ATOMIC_RMW_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW_XOR_I32_A64 },
15170
0
  { WebAssembly::ATOMIC_RMW_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW_XOR_I64_A32 },
15171
0
  { WebAssembly::ATOMIC_RMW_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW_XOR_I64_A64 },
15172
0
  { WebAssembly::ATOMIC_STORE16_I32_A32_S, WebAssembly::ATOMIC_STORE16_I32_A32 },
15173
0
  { WebAssembly::ATOMIC_STORE16_I32_A64_S, WebAssembly::ATOMIC_STORE16_I32_A64 },
15174
0
  { WebAssembly::ATOMIC_STORE16_I64_A32_S, WebAssembly::ATOMIC_STORE16_I64_A32 },
15175
0
  { WebAssembly::ATOMIC_STORE16_I64_A64_S, WebAssembly::ATOMIC_STORE16_I64_A64 },
15176
0
  { WebAssembly::ATOMIC_STORE32_I64_A32_S, WebAssembly::ATOMIC_STORE32_I64_A32 },
15177
0
  { WebAssembly::ATOMIC_STORE32_I64_A64_S, WebAssembly::ATOMIC_STORE32_I64_A64 },
15178
0
  { WebAssembly::ATOMIC_STORE8_I32_A32_S, WebAssembly::ATOMIC_STORE8_I32_A32 },
15179
0
  { WebAssembly::ATOMIC_STORE8_I32_A64_S, WebAssembly::ATOMIC_STORE8_I32_A64 },
15180
0
  { WebAssembly::ATOMIC_STORE8_I64_A32_S, WebAssembly::ATOMIC_STORE8_I64_A32 },
15181
0
  { WebAssembly::ATOMIC_STORE8_I64_A64_S, WebAssembly::ATOMIC_STORE8_I64_A64 },
15182
0
  { WebAssembly::ATOMIC_STORE_I32_A32_S, WebAssembly::ATOMIC_STORE_I32_A32 },
15183
0
  { WebAssembly::ATOMIC_STORE_I32_A64_S, WebAssembly::ATOMIC_STORE_I32_A64 },
15184
0
  { WebAssembly::ATOMIC_STORE_I64_A32_S, WebAssembly::ATOMIC_STORE_I64_A32 },
15185
0
  { WebAssembly::ATOMIC_STORE_I64_A64_S, WebAssembly::ATOMIC_STORE_I64_A64 },
15186
0
  { WebAssembly::AVGR_U_I16x8_S, WebAssembly::AVGR_U_I16x8 },
15187
0
  { WebAssembly::AVGR_U_I8x16_S, WebAssembly::AVGR_U_I8x16 },
15188
0
  { WebAssembly::BITMASK_I16x8_S, WebAssembly::BITMASK_I16x8 },
15189
0
  { WebAssembly::BITMASK_I32x4_S, WebAssembly::BITMASK_I32x4 },
15190
0
  { WebAssembly::BITMASK_I64x2_S, WebAssembly::BITMASK_I64x2 },
15191
0
  { WebAssembly::BITMASK_I8x16_S, WebAssembly::BITMASK_I8x16 },
15192
0
  { WebAssembly::BITSELECT_S, WebAssembly::BITSELECT },
15193
0
  { WebAssembly::BLOCK_S, WebAssembly::BLOCK },
15194
0
  { WebAssembly::BR_IF_S, WebAssembly::BR_IF },
15195
0
  { WebAssembly::BR_S, WebAssembly::BR },
15196
0
  { WebAssembly::BR_TABLE_I32_S, WebAssembly::BR_TABLE_I32 },
15197
0
  { WebAssembly::BR_TABLE_I64_S, WebAssembly::BR_TABLE_I64 },
15198
0
  { WebAssembly::BR_UNLESS_S, WebAssembly::BR_UNLESS },
15199
0
  { WebAssembly::CALL_INDIRECT_S, WebAssembly::CALL_INDIRECT },
15200
0
  { WebAssembly::CALL_S, WebAssembly::CALL },
15201
0
  { WebAssembly::CATCH_ALL_S, WebAssembly::CATCH_ALL },
15202
0
  { WebAssembly::CATCH_S, WebAssembly::CATCH },
15203
0
  { WebAssembly::CEIL_F32_S, WebAssembly::CEIL_F32 },
15204
0
  { WebAssembly::CEIL_F32x4_S, WebAssembly::CEIL_F32x4 },
15205
0
  { WebAssembly::CEIL_F64_S, WebAssembly::CEIL_F64 },
15206
0
  { WebAssembly::CEIL_F64x2_S, WebAssembly::CEIL_F64x2 },
15207
0
  { WebAssembly::CLZ_I32_S, WebAssembly::CLZ_I32 },
15208
0
  { WebAssembly::CLZ_I64_S, WebAssembly::CLZ_I64 },
15209
0
  { WebAssembly::CONST_F32_S, WebAssembly::CONST_F32 },
15210
0
  { WebAssembly::CONST_F64_S, WebAssembly::CONST_F64 },
15211
0
  { WebAssembly::CONST_I32_S, WebAssembly::CONST_I32 },
15212
0
  { WebAssembly::CONST_I64_S, WebAssembly::CONST_I64 },
15213
0
  { WebAssembly::CONST_V128_F32x4_S, WebAssembly::CONST_V128_F32x4 },
15214
0
  { WebAssembly::CONST_V128_F64x2_S, WebAssembly::CONST_V128_F64x2 },
15215
0
  { WebAssembly::CONST_V128_I16x8_S, WebAssembly::CONST_V128_I16x8 },
15216
0
  { WebAssembly::CONST_V128_I32x4_S, WebAssembly::CONST_V128_I32x4 },
15217
0
  { WebAssembly::CONST_V128_I64x2_S, WebAssembly::CONST_V128_I64x2 },
15218
0
  { WebAssembly::CONST_V128_I8x16_S, WebAssembly::CONST_V128_I8x16 },
15219
0
  { WebAssembly::COPYSIGN_F32_S, WebAssembly::COPYSIGN_F32 },
15220
0
  { WebAssembly::COPYSIGN_F64_S, WebAssembly::COPYSIGN_F64 },
15221
0
  { WebAssembly::COPY_EXTERNREF_S, WebAssembly::COPY_EXTERNREF },
15222
0
  { WebAssembly::COPY_F32_S, WebAssembly::COPY_F32 },
15223
0
  { WebAssembly::COPY_F64_S, WebAssembly::COPY_F64 },
15224
0
  { WebAssembly::COPY_FUNCREF_S, WebAssembly::COPY_FUNCREF },
15225
0
  { WebAssembly::COPY_I32_S, WebAssembly::COPY_I32 },
15226
0
  { WebAssembly::COPY_I64_S, WebAssembly::COPY_I64 },
15227
0
  { WebAssembly::COPY_V128_S, WebAssembly::COPY_V128 },
15228
0
  { WebAssembly::CTZ_I32_S, WebAssembly::CTZ_I32 },
15229
0
  { WebAssembly::CTZ_I64_S, WebAssembly::CTZ_I64 },
15230
0
  { WebAssembly::DEBUG_UNREACHABLE_S, WebAssembly::DEBUG_UNREACHABLE },
15231
0
  { WebAssembly::DELEGATE_S, WebAssembly::DELEGATE },
15232
0
  { WebAssembly::DIV_F32_S, WebAssembly::DIV_F32 },
15233
0
  { WebAssembly::DIV_F32x4_S, WebAssembly::DIV_F32x4 },
15234
0
  { WebAssembly::DIV_F64_S, WebAssembly::DIV_F64 },
15235
0
  { WebAssembly::DIV_F64x2_S, WebAssembly::DIV_F64x2 },
15236
0
  { WebAssembly::DIV_S_I32_S, WebAssembly::DIV_S_I32 },
15237
0
  { WebAssembly::DIV_S_I64_S, WebAssembly::DIV_S_I64 },
15238
0
  { WebAssembly::DIV_U_I32_S, WebAssembly::DIV_U_I32 },
15239
0
  { WebAssembly::DIV_U_I64_S, WebAssembly::DIV_U_I64 },
15240
0
  { WebAssembly::DOT_S, WebAssembly::DOT },
15241
0
  { WebAssembly::DROP_EXTERNREF_S, WebAssembly::DROP_EXTERNREF },
15242
0
  { WebAssembly::DROP_F32_S, WebAssembly::DROP_F32 },
15243
0
  { WebAssembly::DROP_F64_S, WebAssembly::DROP_F64 },
15244
0
  { WebAssembly::DROP_FUNCREF_S, WebAssembly::DROP_FUNCREF },
15245
0
  { WebAssembly::DROP_I32_S, WebAssembly::DROP_I32 },
15246
0
  { WebAssembly::DROP_I64_S, WebAssembly::DROP_I64 },
15247
0
  { WebAssembly::DROP_V128_S, WebAssembly::DROP_V128 },
15248
0
  { WebAssembly::ELSE_S, WebAssembly::ELSE },
15249
0
  { WebAssembly::END_BLOCK_S, WebAssembly::END_BLOCK },
15250
0
  { WebAssembly::END_FUNCTION_S, WebAssembly::END_FUNCTION },
15251
0
  { WebAssembly::END_IF_S, WebAssembly::END_IF },
15252
0
  { WebAssembly::END_LOOP_S, WebAssembly::END_LOOP },
15253
0
  { WebAssembly::END_S, WebAssembly::END },
15254
0
  { WebAssembly::END_TRY_S, WebAssembly::END_TRY },
15255
0
  { WebAssembly::EQZ_I32_S, WebAssembly::EQZ_I32 },
15256
0
  { WebAssembly::EQZ_I64_S, WebAssembly::EQZ_I64 },
15257
0
  { WebAssembly::EQ_F32_S, WebAssembly::EQ_F32 },
15258
0
  { WebAssembly::EQ_F32x4_S, WebAssembly::EQ_F32x4 },
15259
0
  { WebAssembly::EQ_F64_S, WebAssembly::EQ_F64 },
15260
0
  { WebAssembly::EQ_F64x2_S, WebAssembly::EQ_F64x2 },
15261
0
  { WebAssembly::EQ_I16x8_S, WebAssembly::EQ_I16x8 },
15262
0
  { WebAssembly::EQ_I32_S, WebAssembly::EQ_I32 },
15263
0
  { WebAssembly::EQ_I32x4_S, WebAssembly::EQ_I32x4 },
15264
0
  { WebAssembly::EQ_I64_S, WebAssembly::EQ_I64 },
15265
0
  { WebAssembly::EQ_I64x2_S, WebAssembly::EQ_I64x2 },
15266
0
  { WebAssembly::EQ_I8x16_S, WebAssembly::EQ_I8x16 },
15267
0
  { WebAssembly::EXTMUL_HIGH_S_I16x8_S, WebAssembly::EXTMUL_HIGH_S_I16x8 },
15268
0
  { WebAssembly::EXTMUL_HIGH_S_I32x4_S, WebAssembly::EXTMUL_HIGH_S_I32x4 },
15269
0
  { WebAssembly::EXTMUL_HIGH_S_I64x2_S, WebAssembly::EXTMUL_HIGH_S_I64x2 },
15270
0
  { WebAssembly::EXTMUL_HIGH_U_I16x8_S, WebAssembly::EXTMUL_HIGH_U_I16x8 },
15271
0
  { WebAssembly::EXTMUL_HIGH_U_I32x4_S, WebAssembly::EXTMUL_HIGH_U_I32x4 },
15272
0
  { WebAssembly::EXTMUL_HIGH_U_I64x2_S, WebAssembly::EXTMUL_HIGH_U_I64x2 },
15273
0
  { WebAssembly::EXTMUL_LOW_S_I16x8_S, WebAssembly::EXTMUL_LOW_S_I16x8 },
15274
0
  { WebAssembly::EXTMUL_LOW_S_I32x4_S, WebAssembly::EXTMUL_LOW_S_I32x4 },
15275
0
  { WebAssembly::EXTMUL_LOW_S_I64x2_S, WebAssembly::EXTMUL_LOW_S_I64x2 },
15276
0
  { WebAssembly::EXTMUL_LOW_U_I16x8_S, WebAssembly::EXTMUL_LOW_U_I16x8 },
15277
0
  { WebAssembly::EXTMUL_LOW_U_I32x4_S, WebAssembly::EXTMUL_LOW_U_I32x4 },
15278
0
  { WebAssembly::EXTMUL_LOW_U_I64x2_S, WebAssembly::EXTMUL_LOW_U_I64x2 },
15279
0
  { WebAssembly::EXTRACT_LANE_F32x4_S, WebAssembly::EXTRACT_LANE_F32x4 },
15280
0
  { WebAssembly::EXTRACT_LANE_F64x2_S, WebAssembly::EXTRACT_LANE_F64x2 },
15281
0
  { WebAssembly::EXTRACT_LANE_I16x8_s_S, WebAssembly::EXTRACT_LANE_I16x8_s },
15282
0
  { WebAssembly::EXTRACT_LANE_I16x8_u_S, WebAssembly::EXTRACT_LANE_I16x8_u },
15283
0
  { WebAssembly::EXTRACT_LANE_I32x4_S, WebAssembly::EXTRACT_LANE_I32x4 },
15284
0
  { WebAssembly::EXTRACT_LANE_I64x2_S, WebAssembly::EXTRACT_LANE_I64x2 },
15285
0
  { WebAssembly::EXTRACT_LANE_I8x16_s_S, WebAssembly::EXTRACT_LANE_I8x16_s },
15286
0
  { WebAssembly::EXTRACT_LANE_I8x16_u_S, WebAssembly::EXTRACT_LANE_I8x16_u },
15287
0
  { WebAssembly::F32_CONVERT_S_I32_S, WebAssembly::F32_CONVERT_S_I32 },
15288
0
  { WebAssembly::F32_CONVERT_S_I64_S, WebAssembly::F32_CONVERT_S_I64 },
15289
0
  { WebAssembly::F32_CONVERT_U_I32_S, WebAssembly::F32_CONVERT_U_I32 },
15290
0
  { WebAssembly::F32_CONVERT_U_I64_S, WebAssembly::F32_CONVERT_U_I64 },
15291
0
  { WebAssembly::F32_DEMOTE_F64_S, WebAssembly::F32_DEMOTE_F64 },
15292
0
  { WebAssembly::F32_REINTERPRET_I32_S, WebAssembly::F32_REINTERPRET_I32 },
15293
0
  { WebAssembly::F64_CONVERT_S_I32_S, WebAssembly::F64_CONVERT_S_I32 },
15294
0
  { WebAssembly::F64_CONVERT_S_I64_S, WebAssembly::F64_CONVERT_S_I64 },
15295
0
  { WebAssembly::F64_CONVERT_U_I32_S, WebAssembly::F64_CONVERT_U_I32 },
15296
0
  { WebAssembly::F64_CONVERT_U_I64_S, WebAssembly::F64_CONVERT_U_I64 },
15297
0
  { WebAssembly::F64_PROMOTE_F32_S, WebAssembly::F64_PROMOTE_F32 },
15298
0
  { WebAssembly::F64_REINTERPRET_I64_S, WebAssembly::F64_REINTERPRET_I64 },
15299
0
  { WebAssembly::FALLTHROUGH_RETURN_S, WebAssembly::FALLTHROUGH_RETURN },
15300
0
  { WebAssembly::FLOOR_F32_S, WebAssembly::FLOOR_F32 },
15301
0
  { WebAssembly::FLOOR_F32x4_S, WebAssembly::FLOOR_F32x4 },
15302
0
  { WebAssembly::FLOOR_F64_S, WebAssembly::FLOOR_F64 },
15303
0
  { WebAssembly::FLOOR_F64x2_S, WebAssembly::FLOOR_F64x2 },
15304
0
  { WebAssembly::FP_TO_SINT_I32_F32_S, WebAssembly::FP_TO_SINT_I32_F32 },
15305
0
  { WebAssembly::FP_TO_SINT_I32_F64_S, WebAssembly::FP_TO_SINT_I32_F64 },
15306
0
  { WebAssembly::FP_TO_SINT_I64_F32_S, WebAssembly::FP_TO_SINT_I64_F32 },
15307
0
  { WebAssembly::FP_TO_SINT_I64_F64_S, WebAssembly::FP_TO_SINT_I64_F64 },
15308
0
  { WebAssembly::FP_TO_UINT_I32_F32_S, WebAssembly::FP_TO_UINT_I32_F32 },
15309
0
  { WebAssembly::FP_TO_UINT_I32_F64_S, WebAssembly::FP_TO_UINT_I32_F64 },
15310
0
  { WebAssembly::FP_TO_UINT_I64_F32_S, WebAssembly::FP_TO_UINT_I64_F32 },
15311
0
  { WebAssembly::FP_TO_UINT_I64_F64_S, WebAssembly::FP_TO_UINT_I64_F64 },
15312
0
  { WebAssembly::GE_F32_S, WebAssembly::GE_F32 },
15313
0
  { WebAssembly::GE_F32x4_S, WebAssembly::GE_F32x4 },
15314
0
  { WebAssembly::GE_F64_S, WebAssembly::GE_F64 },
15315
0
  { WebAssembly::GE_F64x2_S, WebAssembly::GE_F64x2 },
15316
0
  { WebAssembly::GE_S_I16x8_S, WebAssembly::GE_S_I16x8 },
15317
0
  { WebAssembly::GE_S_I32_S, WebAssembly::GE_S_I32 },
15318
0
  { WebAssembly::GE_S_I32x4_S, WebAssembly::GE_S_I32x4 },
15319
0
  { WebAssembly::GE_S_I64_S, WebAssembly::GE_S_I64 },
15320
0
  { WebAssembly::GE_S_I64x2_S, WebAssembly::GE_S_I64x2 },
15321
0
  { WebAssembly::GE_S_I8x16_S, WebAssembly::GE_S_I8x16 },
15322
0
  { WebAssembly::GE_U_I16x8_S, WebAssembly::GE_U_I16x8 },
15323
0
  { WebAssembly::GE_U_I32_S, WebAssembly::GE_U_I32 },
15324
0
  { WebAssembly::GE_U_I32x4_S, WebAssembly::GE_U_I32x4 },
15325
0
  { WebAssembly::GE_U_I64_S, WebAssembly::GE_U_I64 },
15326
0
  { WebAssembly::GE_U_I8x16_S, WebAssembly::GE_U_I8x16 },
15327
0
  { WebAssembly::GLOBAL_GET_EXTERNREF_S, WebAssembly::GLOBAL_GET_EXTERNREF },
15328
0
  { WebAssembly::GLOBAL_GET_F32_S, WebAssembly::GLOBAL_GET_F32 },
15329
0
  { WebAssembly::GLOBAL_GET_F64_S, WebAssembly::GLOBAL_GET_F64 },
15330
0
  { WebAssembly::GLOBAL_GET_FUNCREF_S, WebAssembly::GLOBAL_GET_FUNCREF },
15331
0
  { WebAssembly::GLOBAL_GET_I32_S, WebAssembly::GLOBAL_GET_I32 },
15332
0
  { WebAssembly::GLOBAL_GET_I64_S, WebAssembly::GLOBAL_GET_I64 },
15333
0
  { WebAssembly::GLOBAL_GET_V128_S, WebAssembly::GLOBAL_GET_V128 },
15334
0
  { WebAssembly::GLOBAL_SET_EXTERNREF_S, WebAssembly::GLOBAL_SET_EXTERNREF },
15335
0
  { WebAssembly::GLOBAL_SET_F32_S, WebAssembly::GLOBAL_SET_F32 },
15336
0
  { WebAssembly::GLOBAL_SET_F64_S, WebAssembly::GLOBAL_SET_F64 },
15337
0
  { WebAssembly::GLOBAL_SET_FUNCREF_S, WebAssembly::GLOBAL_SET_FUNCREF },
15338
0
  { WebAssembly::GLOBAL_SET_I32_S, WebAssembly::GLOBAL_SET_I32 },
15339
0
  { WebAssembly::GLOBAL_SET_I64_S, WebAssembly::GLOBAL_SET_I64 },
15340
0
  { WebAssembly::GLOBAL_SET_V128_S, WebAssembly::GLOBAL_SET_V128 },
15341
0
  { WebAssembly::GT_F32_S, WebAssembly::GT_F32 },
15342
0
  { WebAssembly::GT_F32x4_S, WebAssembly::GT_F32x4 },
15343
0
  { WebAssembly::GT_F64_S, WebAssembly::GT_F64 },
15344
0
  { WebAssembly::GT_F64x2_S, WebAssembly::GT_F64x2 },
15345
0
  { WebAssembly::GT_S_I16x8_S, WebAssembly::GT_S_I16x8 },
15346
0
  { WebAssembly::GT_S_I32_S, WebAssembly::GT_S_I32 },
15347
0
  { WebAssembly::GT_S_I32x4_S, WebAssembly::GT_S_I32x4 },
15348
0
  { WebAssembly::GT_S_I64_S, WebAssembly::GT_S_I64 },
15349
0
  { WebAssembly::GT_S_I64x2_S, WebAssembly::GT_S_I64x2 },
15350
0
  { WebAssembly::GT_S_I8x16_S, WebAssembly::GT_S_I8x16 },
15351
0
  { WebAssembly::GT_U_I16x8_S, WebAssembly::GT_U_I16x8 },
15352
0
  { WebAssembly::GT_U_I32_S, WebAssembly::GT_U_I32 },
15353
0
  { WebAssembly::GT_U_I32x4_S, WebAssembly::GT_U_I32x4 },
15354
0
  { WebAssembly::GT_U_I64_S, WebAssembly::GT_U_I64 },
15355
0
  { WebAssembly::GT_U_I8x16_S, WebAssembly::GT_U_I8x16 },
15356
0
  { WebAssembly::I32_EXTEND16_S_I32_S, WebAssembly::I32_EXTEND16_S_I32 },
15357
0
  { WebAssembly::I32_EXTEND8_S_I32_S, WebAssembly::I32_EXTEND8_S_I32 },
15358
0
  { WebAssembly::I32_REINTERPRET_F32_S, WebAssembly::I32_REINTERPRET_F32 },
15359
0
  { WebAssembly::I32_TRUNC_S_F32_S, WebAssembly::I32_TRUNC_S_F32 },
15360
0
  { WebAssembly::I32_TRUNC_S_F64_S, WebAssembly::I32_TRUNC_S_F64 },
15361
0
  { WebAssembly::I32_TRUNC_S_SAT_F32_S, WebAssembly::I32_TRUNC_S_SAT_F32 },
15362
0
  { WebAssembly::I32_TRUNC_S_SAT_F64_S, WebAssembly::I32_TRUNC_S_SAT_F64 },
15363
0
  { WebAssembly::I32_TRUNC_U_F32_S, WebAssembly::I32_TRUNC_U_F32 },
15364
0
  { WebAssembly::I32_TRUNC_U_F64_S, WebAssembly::I32_TRUNC_U_F64 },
15365
0
  { WebAssembly::I32_TRUNC_U_SAT_F32_S, WebAssembly::I32_TRUNC_U_SAT_F32 },
15366
0
  { WebAssembly::I32_TRUNC_U_SAT_F64_S, WebAssembly::I32_TRUNC_U_SAT_F64 },
15367
0
  { WebAssembly::I32_WRAP_I64_S, WebAssembly::I32_WRAP_I64 },
15368
0
  { WebAssembly::I64_EXTEND16_S_I64_S, WebAssembly::I64_EXTEND16_S_I64 },
15369
0
  { WebAssembly::I64_EXTEND32_S_I64_S, WebAssembly::I64_EXTEND32_S_I64 },
15370
0
  { WebAssembly::I64_EXTEND8_S_I64_S, WebAssembly::I64_EXTEND8_S_I64 },
15371
0
  { WebAssembly::I64_EXTEND_S_I32_S, WebAssembly::I64_EXTEND_S_I32 },
15372
0
  { WebAssembly::I64_EXTEND_U_I32_S, WebAssembly::I64_EXTEND_U_I32 },
15373
0
  { WebAssembly::I64_REINTERPRET_F64_S, WebAssembly::I64_REINTERPRET_F64 },
15374
0
  { WebAssembly::I64_TRUNC_S_F32_S, WebAssembly::I64_TRUNC_S_F32 },
15375
0
  { WebAssembly::I64_TRUNC_S_F64_S, WebAssembly::I64_TRUNC_S_F64 },
15376
0
  { WebAssembly::I64_TRUNC_S_SAT_F32_S, WebAssembly::I64_TRUNC_S_SAT_F32 },
15377
0
  { WebAssembly::I64_TRUNC_S_SAT_F64_S, WebAssembly::I64_TRUNC_S_SAT_F64 },
15378
0
  { WebAssembly::I64_TRUNC_U_F32_S, WebAssembly::I64_TRUNC_U_F32 },
15379
0
  { WebAssembly::I64_TRUNC_U_F64_S, WebAssembly::I64_TRUNC_U_F64 },
15380
0
  { WebAssembly::I64_TRUNC_U_SAT_F32_S, WebAssembly::I64_TRUNC_U_SAT_F32 },
15381
0
  { WebAssembly::I64_TRUNC_U_SAT_F64_S, WebAssembly::I64_TRUNC_U_SAT_F64 },
15382
0
  { WebAssembly::IF_S, WebAssembly::IF },
15383
0
  { WebAssembly::LANESELECT_I16x8_S, WebAssembly::LANESELECT_I16x8 },
15384
0
  { WebAssembly::LANESELECT_I32x4_S, WebAssembly::LANESELECT_I32x4 },
15385
0
  { WebAssembly::LANESELECT_I64x2_S, WebAssembly::LANESELECT_I64x2 },
15386
0
  { WebAssembly::LANESELECT_I8x16_S, WebAssembly::LANESELECT_I8x16 },
15387
0
  { WebAssembly::LE_F32_S, WebAssembly::LE_F32 },
15388
0
  { WebAssembly::LE_F32x4_S, WebAssembly::LE_F32x4 },
15389
0
  { WebAssembly::LE_F64_S, WebAssembly::LE_F64 },
15390
0
  { WebAssembly::LE_F64x2_S, WebAssembly::LE_F64x2 },
15391
0
  { WebAssembly::LE_S_I16x8_S, WebAssembly::LE_S_I16x8 },
15392
0
  { WebAssembly::LE_S_I32_S, WebAssembly::LE_S_I32 },
15393
0
  { WebAssembly::LE_S_I32x4_S, WebAssembly::LE_S_I32x4 },
15394
0
  { WebAssembly::LE_S_I64_S, WebAssembly::LE_S_I64 },
15395
0
  { WebAssembly::LE_S_I64x2_S, WebAssembly::LE_S_I64x2 },
15396
0
  { WebAssembly::LE_S_I8x16_S, WebAssembly::LE_S_I8x16 },
15397
0
  { WebAssembly::LE_U_I16x8_S, WebAssembly::LE_U_I16x8 },
15398
0
  { WebAssembly::LE_U_I32_S, WebAssembly::LE_U_I32 },
15399
0
  { WebAssembly::LE_U_I32x4_S, WebAssembly::LE_U_I32x4 },
15400
0
  { WebAssembly::LE_U_I64_S, WebAssembly::LE_U_I64 },
15401
0
  { WebAssembly::LE_U_I8x16_S, WebAssembly::LE_U_I8x16 },
15402
0
  { WebAssembly::LOAD16_SPLAT_A32_S, WebAssembly::LOAD16_SPLAT_A32 },
15403
0
  { WebAssembly::LOAD16_SPLAT_A64_S, WebAssembly::LOAD16_SPLAT_A64 },
15404
0
  { WebAssembly::LOAD16_S_I32_A32_S, WebAssembly::LOAD16_S_I32_A32 },
15405
0
  { WebAssembly::LOAD16_S_I32_A64_S, WebAssembly::LOAD16_S_I32_A64 },
15406
0
  { WebAssembly::LOAD16_S_I64_A32_S, WebAssembly::LOAD16_S_I64_A32 },
15407
0
  { WebAssembly::LOAD16_S_I64_A64_S, WebAssembly::LOAD16_S_I64_A64 },
15408
0
  { WebAssembly::LOAD16_U_I32_A32_S, WebAssembly::LOAD16_U_I32_A32 },
15409
0
  { WebAssembly::LOAD16_U_I32_A64_S, WebAssembly::LOAD16_U_I32_A64 },
15410
0
  { WebAssembly::LOAD16_U_I64_A32_S, WebAssembly::LOAD16_U_I64_A32 },
15411
0
  { WebAssembly::LOAD16_U_I64_A64_S, WebAssembly::LOAD16_U_I64_A64 },
15412
0
  { WebAssembly::LOAD32_SPLAT_A32_S, WebAssembly::LOAD32_SPLAT_A32 },
15413
0
  { WebAssembly::LOAD32_SPLAT_A64_S, WebAssembly::LOAD32_SPLAT_A64 },
15414
0
  { WebAssembly::LOAD32_S_I64_A32_S, WebAssembly::LOAD32_S_I64_A32 },
15415
0
  { WebAssembly::LOAD32_S_I64_A64_S, WebAssembly::LOAD32_S_I64_A64 },
15416
0
  { WebAssembly::LOAD32_U_I64_A32_S, WebAssembly::LOAD32_U_I64_A32 },
15417
0
  { WebAssembly::LOAD32_U_I64_A64_S, WebAssembly::LOAD32_U_I64_A64 },
15418
0
  { WebAssembly::LOAD64_SPLAT_A32_S, WebAssembly::LOAD64_SPLAT_A32 },
15419
0
  { WebAssembly::LOAD64_SPLAT_A64_S, WebAssembly::LOAD64_SPLAT_A64 },
15420
0
  { WebAssembly::LOAD8_SPLAT_A32_S, WebAssembly::LOAD8_SPLAT_A32 },
15421
0
  { WebAssembly::LOAD8_SPLAT_A64_S, WebAssembly::LOAD8_SPLAT_A64 },
15422
0
  { WebAssembly::LOAD8_S_I32_A32_S, WebAssembly::LOAD8_S_I32_A32 },
15423
0
  { WebAssembly::LOAD8_S_I32_A64_S, WebAssembly::LOAD8_S_I32_A64 },
15424
0
  { WebAssembly::LOAD8_S_I64_A32_S, WebAssembly::LOAD8_S_I64_A32 },
15425
0
  { WebAssembly::LOAD8_S_I64_A64_S, WebAssembly::LOAD8_S_I64_A64 },
15426
0
  { WebAssembly::LOAD8_U_I32_A32_S, WebAssembly::LOAD8_U_I32_A32 },
15427
0
  { WebAssembly::LOAD8_U_I32_A64_S, WebAssembly::LOAD8_U_I32_A64 },
15428
0
  { WebAssembly::LOAD8_U_I64_A32_S, WebAssembly::LOAD8_U_I64_A32 },
15429
0
  { WebAssembly::LOAD8_U_I64_A64_S, WebAssembly::LOAD8_U_I64_A64 },
15430
0
  { WebAssembly::LOAD_EXTEND_S_I16x8_A32_S, WebAssembly::LOAD_EXTEND_S_I16x8_A32 },
15431
0
  { WebAssembly::LOAD_EXTEND_S_I16x8_A64_S, WebAssembly::LOAD_EXTEND_S_I16x8_A64 },
15432
0
  { WebAssembly::LOAD_EXTEND_S_I32x4_A32_S, WebAssembly::LOAD_EXTEND_S_I32x4_A32 },
15433
0
  { WebAssembly::LOAD_EXTEND_S_I32x4_A64_S, WebAssembly::LOAD_EXTEND_S_I32x4_A64 },
15434
0
  { WebAssembly::LOAD_EXTEND_S_I64x2_A32_S, WebAssembly::LOAD_EXTEND_S_I64x2_A32 },
15435
0
  { WebAssembly::LOAD_EXTEND_S_I64x2_A64_S, WebAssembly::LOAD_EXTEND_S_I64x2_A64 },
15436
0
  { WebAssembly::LOAD_EXTEND_U_I16x8_A32_S, WebAssembly::LOAD_EXTEND_U_I16x8_A32 },
15437
0
  { WebAssembly::LOAD_EXTEND_U_I16x8_A64_S, WebAssembly::LOAD_EXTEND_U_I16x8_A64 },
15438
0
  { WebAssembly::LOAD_EXTEND_U_I32x4_A32_S, WebAssembly::LOAD_EXTEND_U_I32x4_A32 },
15439
0
  { WebAssembly::LOAD_EXTEND_U_I32x4_A64_S, WebAssembly::LOAD_EXTEND_U_I32x4_A64 },
15440
0
  { WebAssembly::LOAD_EXTEND_U_I64x2_A32_S, WebAssembly::LOAD_EXTEND_U_I64x2_A32 },
15441
0
  { WebAssembly::LOAD_EXTEND_U_I64x2_A64_S, WebAssembly::LOAD_EXTEND_U_I64x2_A64 },
15442
0
  { WebAssembly::LOAD_F32_A32_S, WebAssembly::LOAD_F32_A32 },
15443
0
  { WebAssembly::LOAD_F32_A64_S, WebAssembly::LOAD_F32_A64 },
15444
0
  { WebAssembly::LOAD_F64_A32_S, WebAssembly::LOAD_F64_A32 },
15445
0
  { WebAssembly::LOAD_F64_A64_S, WebAssembly::LOAD_F64_A64 },
15446
0
  { WebAssembly::LOAD_I32_A32_S, WebAssembly::LOAD_I32_A32 },
15447
0
  { WebAssembly::LOAD_I32_A64_S, WebAssembly::LOAD_I32_A64 },
15448
0
  { WebAssembly::LOAD_I64_A32_S, WebAssembly::LOAD_I64_A32 },
15449
0
  { WebAssembly::LOAD_I64_A64_S, WebAssembly::LOAD_I64_A64 },
15450
0
  { WebAssembly::LOAD_LANE_I16x8_A32_S, WebAssembly::LOAD_LANE_I16x8_A32 },
15451
0
  { WebAssembly::LOAD_LANE_I16x8_A64_S, WebAssembly::LOAD_LANE_I16x8_A64 },
15452
0
  { WebAssembly::LOAD_LANE_I32x4_A32_S, WebAssembly::LOAD_LANE_I32x4_A32 },
15453
0
  { WebAssembly::LOAD_LANE_I32x4_A64_S, WebAssembly::LOAD_LANE_I32x4_A64 },
15454
0
  { WebAssembly::LOAD_LANE_I64x2_A32_S, WebAssembly::LOAD_LANE_I64x2_A32 },
15455
0
  { WebAssembly::LOAD_LANE_I64x2_A64_S, WebAssembly::LOAD_LANE_I64x2_A64 },
15456
0
  { WebAssembly::LOAD_LANE_I8x16_A32_S, WebAssembly::LOAD_LANE_I8x16_A32 },
15457
0
  { WebAssembly::LOAD_LANE_I8x16_A64_S, WebAssembly::LOAD_LANE_I8x16_A64 },
15458
0
  { WebAssembly::LOAD_V128_A32_S, WebAssembly::LOAD_V128_A32 },
15459
0
  { WebAssembly::LOAD_V128_A64_S, WebAssembly::LOAD_V128_A64 },
15460
0
  { WebAssembly::LOAD_ZERO_I32x4_A32_S, WebAssembly::LOAD_ZERO_I32x4_A32 },
15461
0
  { WebAssembly::LOAD_ZERO_I32x4_A64_S, WebAssembly::LOAD_ZERO_I32x4_A64 },
15462
0
  { WebAssembly::LOAD_ZERO_I64x2_A32_S, WebAssembly::LOAD_ZERO_I64x2_A32 },
15463
0
  { WebAssembly::LOAD_ZERO_I64x2_A64_S, WebAssembly::LOAD_ZERO_I64x2_A64 },
15464
0
  { WebAssembly::LOCAL_GET_EXTERNREF_S, WebAssembly::LOCAL_GET_EXTERNREF },
15465
0
  { WebAssembly::LOCAL_GET_F32_S, WebAssembly::LOCAL_GET_F32 },
15466
0
  { WebAssembly::LOCAL_GET_F64_S, WebAssembly::LOCAL_GET_F64 },
15467
0
  { WebAssembly::LOCAL_GET_FUNCREF_S, WebAssembly::LOCAL_GET_FUNCREF },
15468
0
  { WebAssembly::LOCAL_GET_I32_S, WebAssembly::LOCAL_GET_I32 },
15469
0
  { WebAssembly::LOCAL_GET_I64_S, WebAssembly::LOCAL_GET_I64 },
15470
0
  { WebAssembly::LOCAL_GET_V128_S, WebAssembly::LOCAL_GET_V128 },
15471
0
  { WebAssembly::LOCAL_SET_EXTERNREF_S, WebAssembly::LOCAL_SET_EXTERNREF },
15472
0
  { WebAssembly::LOCAL_SET_F32_S, WebAssembly::LOCAL_SET_F32 },
15473
0
  { WebAssembly::LOCAL_SET_F64_S, WebAssembly::LOCAL_SET_F64 },
15474
0
  { WebAssembly::LOCAL_SET_FUNCREF_S, WebAssembly::LOCAL_SET_FUNCREF },
15475
0
  { WebAssembly::LOCAL_SET_I32_S, WebAssembly::LOCAL_SET_I32 },
15476
0
  { WebAssembly::LOCAL_SET_I64_S, WebAssembly::LOCAL_SET_I64 },
15477
0
  { WebAssembly::LOCAL_SET_V128_S, WebAssembly::LOCAL_SET_V128 },
15478
0
  { WebAssembly::LOCAL_TEE_EXTERNREF_S, WebAssembly::LOCAL_TEE_EXTERNREF },
15479
0
  { WebAssembly::LOCAL_TEE_F32_S, WebAssembly::LOCAL_TEE_F32 },
15480
0
  { WebAssembly::LOCAL_TEE_F64_S, WebAssembly::LOCAL_TEE_F64 },
15481
0
  { WebAssembly::LOCAL_TEE_FUNCREF_S, WebAssembly::LOCAL_TEE_FUNCREF },
15482
0
  { WebAssembly::LOCAL_TEE_I32_S, WebAssembly::LOCAL_TEE_I32 },
15483
0
  { WebAssembly::LOCAL_TEE_I64_S, WebAssembly::LOCAL_TEE_I64 },
15484
0
  { WebAssembly::LOCAL_TEE_V128_S, WebAssembly::LOCAL_TEE_V128 },
15485
0
  { WebAssembly::LOOP_S, WebAssembly::LOOP },
15486
0
  { WebAssembly::LT_F32_S, WebAssembly::LT_F32 },
15487
0
  { WebAssembly::LT_F32x4_S, WebAssembly::LT_F32x4 },
15488
0
  { WebAssembly::LT_F64_S, WebAssembly::LT_F64 },
15489
0
  { WebAssembly::LT_F64x2_S, WebAssembly::LT_F64x2 },
15490
0
  { WebAssembly::LT_S_I16x8_S, WebAssembly::LT_S_I16x8 },
15491
0
  { WebAssembly::LT_S_I32_S, WebAssembly::LT_S_I32 },
15492
0
  { WebAssembly::LT_S_I32x4_S, WebAssembly::LT_S_I32x4 },
15493
0
  { WebAssembly::LT_S_I64_S, WebAssembly::LT_S_I64 },
15494
0
  { WebAssembly::LT_S_I64x2_S, WebAssembly::LT_S_I64x2 },
15495
0
  { WebAssembly::LT_S_I8x16_S, WebAssembly::LT_S_I8x16 },
15496
0
  { WebAssembly::LT_U_I16x8_S, WebAssembly::LT_U_I16x8 },
15497
0
  { WebAssembly::LT_U_I32_S, WebAssembly::LT_U_I32 },
15498
0
  { WebAssembly::LT_U_I32x4_S, WebAssembly::LT_U_I32x4 },
15499
0
  { WebAssembly::LT_U_I64_S, WebAssembly::LT_U_I64 },
15500
0
  { WebAssembly::LT_U_I8x16_S, WebAssembly::LT_U_I8x16 },
15501
0
  { WebAssembly::MADD_F32x4_S, WebAssembly::MADD_F32x4 },
15502
0
  { WebAssembly::MADD_F64x2_S, WebAssembly::MADD_F64x2 },
15503
0
  { WebAssembly::MAX_F32_S, WebAssembly::MAX_F32 },
15504
0
  { WebAssembly::MAX_F32x4_S, WebAssembly::MAX_F32x4 },
15505
0
  { WebAssembly::MAX_F64_S, WebAssembly::MAX_F64 },
15506
0
  { WebAssembly::MAX_F64x2_S, WebAssembly::MAX_F64x2 },
15507
0
  { WebAssembly::MAX_S_I16x8_S, WebAssembly::MAX_S_I16x8 },
15508
0
  { WebAssembly::MAX_S_I32x4_S, WebAssembly::MAX_S_I32x4 },
15509
0
  { WebAssembly::MAX_S_I8x16_S, WebAssembly::MAX_S_I8x16 },
15510
0
  { WebAssembly::MAX_U_I16x8_S, WebAssembly::MAX_U_I16x8 },
15511
0
  { WebAssembly::MAX_U_I32x4_S, WebAssembly::MAX_U_I32x4 },
15512
0
  { WebAssembly::MAX_U_I8x16_S, WebAssembly::MAX_U_I8x16 },
15513
0
  { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A32 },
15514
0
  { WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64 },
15515
0
  { WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A32 },
15516
0
  { WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A64 },
15517
0
  { WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A32 },
15518
0
  { WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A64 },
15519
0
  { WebAssembly::MIN_F32_S, WebAssembly::MIN_F32 },
15520
0
  { WebAssembly::MIN_F32x4_S, WebAssembly::MIN_F32x4 },
15521
0
  { WebAssembly::MIN_F64_S, WebAssembly::MIN_F64 },
15522
0
  { WebAssembly::MIN_F64x2_S, WebAssembly::MIN_F64x2 },
15523
0
  { WebAssembly::MIN_S_I16x8_S, WebAssembly::MIN_S_I16x8 },
15524
0
  { WebAssembly::MIN_S_I32x4_S, WebAssembly::MIN_S_I32x4 },
15525
0
  { WebAssembly::MIN_S_I8x16_S, WebAssembly::MIN_S_I8x16 },
15526
0
  { WebAssembly::MIN_U_I16x8_S, WebAssembly::MIN_U_I16x8 },
15527
0
  { WebAssembly::MIN_U_I32x4_S, WebAssembly::MIN_U_I32x4 },
15528
0
  { WebAssembly::MIN_U_I8x16_S, WebAssembly::MIN_U_I8x16 },
15529
0
  { WebAssembly::MUL_F32_S, WebAssembly::MUL_F32 },
15530
0
  { WebAssembly::MUL_F32x4_S, WebAssembly::MUL_F32x4 },
15531
0
  { WebAssembly::MUL_F64_S, WebAssembly::MUL_F64 },
15532
0
  { WebAssembly::MUL_F64x2_S, WebAssembly::MUL_F64x2 },
15533
0
  { WebAssembly::MUL_I16x8_S, WebAssembly::MUL_I16x8 },
15534
0
  { WebAssembly::MUL_I32_S, WebAssembly::MUL_I32 },
15535
0
  { WebAssembly::MUL_I32x4_S, WebAssembly::MUL_I32x4 },
15536
0
  { WebAssembly::MUL_I64_S, WebAssembly::MUL_I64 },
15537
0
  { WebAssembly::MUL_I64x2_S, WebAssembly::MUL_I64x2 },
15538
0
  { WebAssembly::NARROW_S_I16x8_S, WebAssembly::NARROW_S_I16x8 },
15539
0
  { WebAssembly::NARROW_S_I8x16_S, WebAssembly::NARROW_S_I8x16 },
15540
0
  { WebAssembly::NARROW_U_I16x8_S, WebAssembly::NARROW_U_I16x8 },
15541
0
  { WebAssembly::NARROW_U_I8x16_S, WebAssembly::NARROW_U_I8x16 },
15542
0
  { WebAssembly::NEAREST_F32_S, WebAssembly::NEAREST_F32 },
15543
0
  { WebAssembly::NEAREST_F32x4_S, WebAssembly::NEAREST_F32x4 },
15544
0
  { WebAssembly::NEAREST_F64_S, WebAssembly::NEAREST_F64 },
15545
0
  { WebAssembly::NEAREST_F64x2_S, WebAssembly::NEAREST_F64x2 },
15546
0
  { WebAssembly::NEG_F32_S, WebAssembly::NEG_F32 },
15547
0
  { WebAssembly::NEG_F32x4_S, WebAssembly::NEG_F32x4 },
15548
0
  { WebAssembly::NEG_F64_S, WebAssembly::NEG_F64 },
15549
0
  { WebAssembly::NEG_F64x2_S, WebAssembly::NEG_F64x2 },
15550
0
  { WebAssembly::NEG_I16x8_S, WebAssembly::NEG_I16x8 },
15551
0
  { WebAssembly::NEG_I32x4_S, WebAssembly::NEG_I32x4 },
15552
0
  { WebAssembly::NEG_I64x2_S, WebAssembly::NEG_I64x2 },
15553
0
  { WebAssembly::NEG_I8x16_S, WebAssembly::NEG_I8x16 },
15554
0
  { WebAssembly::NE_F32_S, WebAssembly::NE_F32 },
15555
0
  { WebAssembly::NE_F32x4_S, WebAssembly::NE_F32x4 },
15556
0
  { WebAssembly::NE_F64_S, WebAssembly::NE_F64 },
15557
0
  { WebAssembly::NE_F64x2_S, WebAssembly::NE_F64x2 },
15558
0
  { WebAssembly::NE_I16x8_S, WebAssembly::NE_I16x8 },
15559
0
  { WebAssembly::NE_I32_S, WebAssembly::NE_I32 },
15560
0
  { WebAssembly::NE_I32x4_S, WebAssembly::NE_I32x4 },
15561
0
  { WebAssembly::NE_I64_S, WebAssembly::NE_I64 },
15562
0
  { WebAssembly::NE_I64x2_S, WebAssembly::NE_I64x2 },
15563
0
  { WebAssembly::NE_I8x16_S, WebAssembly::NE_I8x16 },
15564
0
  { WebAssembly::NMADD_F32x4_S, WebAssembly::NMADD_F32x4 },
15565
0
  { WebAssembly::NMADD_F64x2_S, WebAssembly::NMADD_F64x2 },
15566
0
  { WebAssembly::NOP_S, WebAssembly::NOP },
15567
0
  { WebAssembly::NOT_S, WebAssembly::NOT },
15568
0
  { WebAssembly::OR_I32_S, WebAssembly::OR_I32 },
15569
0
  { WebAssembly::OR_I64_S, WebAssembly::OR_I64 },
15570
0
  { WebAssembly::OR_S, WebAssembly::OR },
15571
0
  { WebAssembly::PMAX_F32x4_S, WebAssembly::PMAX_F32x4 },
15572
0
  { WebAssembly::PMAX_F64x2_S, WebAssembly::PMAX_F64x2 },
15573
0
  { WebAssembly::PMIN_F32x4_S, WebAssembly::PMIN_F32x4 },
15574
0
  { WebAssembly::PMIN_F64x2_S, WebAssembly::PMIN_F64x2 },
15575
0
  { WebAssembly::POPCNT_I32_S, WebAssembly::POPCNT_I32 },
15576
0
  { WebAssembly::POPCNT_I64_S, WebAssembly::POPCNT_I64 },
15577
0
  { WebAssembly::POPCNT_I8x16_S, WebAssembly::POPCNT_I8x16 },
15578
0
  { WebAssembly::Q15MULR_SAT_S_I16x8_S, WebAssembly::Q15MULR_SAT_S_I16x8 },
15579
0
  { WebAssembly::REF_IS_NULL_EXTERNREF_S, WebAssembly::REF_IS_NULL_EXTERNREF },
15580
0
  { WebAssembly::REF_IS_NULL_FUNCREF_S, WebAssembly::REF_IS_NULL_FUNCREF },
15581
0
  { WebAssembly::REF_NULL_EXTERNREF_S, WebAssembly::REF_NULL_EXTERNREF },
15582
0
  { WebAssembly::REF_NULL_FUNCREF_S, WebAssembly::REF_NULL_FUNCREF },
15583
0
  { WebAssembly::RELAXED_DOT_ADD_S, WebAssembly::RELAXED_DOT_ADD },
15584
0
  { WebAssembly::RELAXED_DOT_BFLOAT_S, WebAssembly::RELAXED_DOT_BFLOAT },
15585
0
  { WebAssembly::RELAXED_DOT_S, WebAssembly::RELAXED_DOT },
15586
0
  { WebAssembly::RELAXED_Q15MULR_S_I16x8_S, WebAssembly::RELAXED_Q15MULR_S_I16x8 },
15587
0
  { WebAssembly::RELAXED_SWIZZLE_S, WebAssembly::RELAXED_SWIZZLE },
15588
0
  { WebAssembly::REM_S_I32_S, WebAssembly::REM_S_I32 },
15589
0
  { WebAssembly::REM_S_I64_S, WebAssembly::REM_S_I64 },
15590
0
  { WebAssembly::REM_U_I32_S, WebAssembly::REM_U_I32 },
15591
0
  { WebAssembly::REM_U_I64_S, WebAssembly::REM_U_I64 },
15592
0
  { WebAssembly::REPLACE_LANE_F32x4_S, WebAssembly::REPLACE_LANE_F32x4 },
15593
0
  { WebAssembly::REPLACE_LANE_F64x2_S, WebAssembly::REPLACE_LANE_F64x2 },
15594
0
  { WebAssembly::REPLACE_LANE_I16x8_S, WebAssembly::REPLACE_LANE_I16x8 },
15595
0
  { WebAssembly::REPLACE_LANE_I32x4_S, WebAssembly::REPLACE_LANE_I32x4 },
15596
0
  { WebAssembly::REPLACE_LANE_I64x2_S, WebAssembly::REPLACE_LANE_I64x2 },
15597
0
  { WebAssembly::REPLACE_LANE_I8x16_S, WebAssembly::REPLACE_LANE_I8x16 },
15598
0
  { WebAssembly::RETHROW_S, WebAssembly::RETHROW },
15599
0
  { WebAssembly::RETURN_S, WebAssembly::RETURN },
15600
0
  { WebAssembly::RET_CALL_INDIRECT_S, WebAssembly::RET_CALL_INDIRECT },
15601
0
  { WebAssembly::RET_CALL_S, WebAssembly::RET_CALL },
15602
0
  { WebAssembly::ROTL_I32_S, WebAssembly::ROTL_I32 },
15603
0
  { WebAssembly::ROTL_I64_S, WebAssembly::ROTL_I64 },
15604
0
  { WebAssembly::ROTR_I32_S, WebAssembly::ROTR_I32 },
15605
0
  { WebAssembly::ROTR_I64_S, WebAssembly::ROTR_I64 },
15606
0
  { WebAssembly::SELECT_EXTERNREF_S, WebAssembly::SELECT_EXTERNREF },
15607
0
  { WebAssembly::SELECT_F32_S, WebAssembly::SELECT_F32 },
15608
0
  { WebAssembly::SELECT_F64_S, WebAssembly::SELECT_F64 },
15609
0
  { WebAssembly::SELECT_FUNCREF_S, WebAssembly::SELECT_FUNCREF },
15610
0
  { WebAssembly::SELECT_I32_S, WebAssembly::SELECT_I32 },
15611
0
  { WebAssembly::SELECT_I64_S, WebAssembly::SELECT_I64 },
15612
0
  { WebAssembly::SELECT_V128_S, WebAssembly::SELECT_V128 },
15613
0
  { WebAssembly::SHL_I16x8_S, WebAssembly::SHL_I16x8 },
15614
0
  { WebAssembly::SHL_I32_S, WebAssembly::SHL_I32 },
15615
0
  { WebAssembly::SHL_I32x4_S, WebAssembly::SHL_I32x4 },
15616
0
  { WebAssembly::SHL_I64_S, WebAssembly::SHL_I64 },
15617
0
  { WebAssembly::SHL_I64x2_S, WebAssembly::SHL_I64x2 },
15618
0
  { WebAssembly::SHL_I8x16_S, WebAssembly::SHL_I8x16 },
15619
0
  { WebAssembly::SHR_S_I16x8_S, WebAssembly::SHR_S_I16x8 },
15620
0
  { WebAssembly::SHR_S_I32_S, WebAssembly::SHR_S_I32 },
15621
0
  { WebAssembly::SHR_S_I32x4_S, WebAssembly::SHR_S_I32x4 },
15622
0
  { WebAssembly::SHR_S_I64_S, WebAssembly::SHR_S_I64 },
15623
0
  { WebAssembly::SHR_S_I64x2_S, WebAssembly::SHR_S_I64x2 },
15624
0
  { WebAssembly::SHR_S_I8x16_S, WebAssembly::SHR_S_I8x16 },
15625
0
  { WebAssembly::SHR_U_I16x8_S, WebAssembly::SHR_U_I16x8 },
15626
0
  { WebAssembly::SHR_U_I32_S, WebAssembly::SHR_U_I32 },
15627
0
  { WebAssembly::SHR_U_I32x4_S, WebAssembly::SHR_U_I32x4 },
15628
0
  { WebAssembly::SHR_U_I64_S, WebAssembly::SHR_U_I64 },
15629
0
  { WebAssembly::SHR_U_I64x2_S, WebAssembly::SHR_U_I64x2 },
15630
0
  { WebAssembly::SHR_U_I8x16_S, WebAssembly::SHR_U_I8x16 },
15631
0
  { WebAssembly::SHUFFLE_S, WebAssembly::SHUFFLE },
15632
0
  { WebAssembly::SIMD_RELAXED_FMAX_F32x4_S, WebAssembly::SIMD_RELAXED_FMAX_F32x4 },
15633
0
  { WebAssembly::SIMD_RELAXED_FMAX_F64x2_S, WebAssembly::SIMD_RELAXED_FMAX_F64x2 },
15634
0
  { WebAssembly::SIMD_RELAXED_FMIN_F32x4_S, WebAssembly::SIMD_RELAXED_FMIN_F32x4 },
15635
0
  { WebAssembly::SIMD_RELAXED_FMIN_F64x2_S, WebAssembly::SIMD_RELAXED_FMIN_F64x2 },
15636
0
  { WebAssembly::SPLAT_F32x4_S, WebAssembly::SPLAT_F32x4 },
15637
0
  { WebAssembly::SPLAT_F64x2_S, WebAssembly::SPLAT_F64x2 },
15638
0
  { WebAssembly::SPLAT_I16x8_S, WebAssembly::SPLAT_I16x8 },
15639
0
  { WebAssembly::SPLAT_I32x4_S, WebAssembly::SPLAT_I32x4 },
15640
0
  { WebAssembly::SPLAT_I64x2_S, WebAssembly::SPLAT_I64x2 },
15641
0
  { WebAssembly::SPLAT_I8x16_S, WebAssembly::SPLAT_I8x16 },
15642
0
  { WebAssembly::SQRT_F32_S, WebAssembly::SQRT_F32 },
15643
0
  { WebAssembly::SQRT_F32x4_S, WebAssembly::SQRT_F32x4 },
15644
0
  { WebAssembly::SQRT_F64_S, WebAssembly::SQRT_F64 },
15645
0
  { WebAssembly::SQRT_F64x2_S, WebAssembly::SQRT_F64x2 },
15646
0
  { WebAssembly::STORE16_I32_A32_S, WebAssembly::STORE16_I32_A32 },
15647
0
  { WebAssembly::STORE16_I32_A64_S, WebAssembly::STORE16_I32_A64 },
15648
0
  { WebAssembly::STORE16_I64_A32_S, WebAssembly::STORE16_I64_A32 },
15649
0
  { WebAssembly::STORE16_I64_A64_S, WebAssembly::STORE16_I64_A64 },
15650
0
  { WebAssembly::STORE32_I64_A32_S, WebAssembly::STORE32_I64_A32 },
15651
0
  { WebAssembly::STORE32_I64_A64_S, WebAssembly::STORE32_I64_A64 },
15652
0
  { WebAssembly::STORE8_I32_A32_S, WebAssembly::STORE8_I32_A32 },
15653
0
  { WebAssembly::STORE8_I32_A64_S, WebAssembly::STORE8_I32_A64 },
15654
0
  { WebAssembly::STORE8_I64_A32_S, WebAssembly::STORE8_I64_A32 },
15655
0
  { WebAssembly::STORE8_I64_A64_S, WebAssembly::STORE8_I64_A64 },
15656
0
  { WebAssembly::STORE_F32_A32_S, WebAssembly::STORE_F32_A32 },
15657
0
  { WebAssembly::STORE_F32_A64_S, WebAssembly::STORE_F32_A64 },
15658
0
  { WebAssembly::STORE_F64_A32_S, WebAssembly::STORE_F64_A32 },
15659
0
  { WebAssembly::STORE_F64_A64_S, WebAssembly::STORE_F64_A64 },
15660
0
  { WebAssembly::STORE_I32_A32_S, WebAssembly::STORE_I32_A32 },
15661
0
  { WebAssembly::STORE_I32_A64_S, WebAssembly::STORE_I32_A64 },
15662
0
  { WebAssembly::STORE_I64_A32_S, WebAssembly::STORE_I64_A32 },
15663
0
  { WebAssembly::STORE_I64_A64_S, WebAssembly::STORE_I64_A64 },
15664
0
  { WebAssembly::STORE_LANE_I16x8_A32_S, WebAssembly::STORE_LANE_I16x8_A32 },
15665
0
  { WebAssembly::STORE_LANE_I16x8_A64_S, WebAssembly::STORE_LANE_I16x8_A64 },
15666
0
  { WebAssembly::STORE_LANE_I32x4_A32_S, WebAssembly::STORE_LANE_I32x4_A32 },
15667
0
  { WebAssembly::STORE_LANE_I32x4_A64_S, WebAssembly::STORE_LANE_I32x4_A64 },
15668
0
  { WebAssembly::STORE_LANE_I64x2_A32_S, WebAssembly::STORE_LANE_I64x2_A32 },
15669
0
  { WebAssembly::STORE_LANE_I64x2_A64_S, WebAssembly::STORE_LANE_I64x2_A64 },
15670
0
  { WebAssembly::STORE_LANE_I8x16_A32_S, WebAssembly::STORE_LANE_I8x16_A32 },
15671
0
  { WebAssembly::STORE_LANE_I8x16_A64_S, WebAssembly::STORE_LANE_I8x16_A64 },
15672
0
  { WebAssembly::STORE_V128_A32_S, WebAssembly::STORE_V128_A32 },
15673
0
  { WebAssembly::STORE_V128_A64_S, WebAssembly::STORE_V128_A64 },
15674
0
  { WebAssembly::SUB_F32_S, WebAssembly::SUB_F32 },
15675
0
  { WebAssembly::SUB_F32x4_S, WebAssembly::SUB_F32x4 },
15676
0
  { WebAssembly::SUB_F64_S, WebAssembly::SUB_F64 },
15677
0
  { WebAssembly::SUB_F64x2_S, WebAssembly::SUB_F64x2 },
15678
0
  { WebAssembly::SUB_I16x8_S, WebAssembly::SUB_I16x8 },
15679
0
  { WebAssembly::SUB_I32_S, WebAssembly::SUB_I32 },
15680
0
  { WebAssembly::SUB_I32x4_S, WebAssembly::SUB_I32x4 },
15681
0
  { WebAssembly::SUB_I64_S, WebAssembly::SUB_I64 },
15682
0
  { WebAssembly::SUB_I64x2_S, WebAssembly::SUB_I64x2 },
15683
0
  { WebAssembly::SUB_I8x16_S, WebAssembly::SUB_I8x16 },
15684
0
  { WebAssembly::SUB_SAT_S_I16x8_S, WebAssembly::SUB_SAT_S_I16x8 },
15685
0
  { WebAssembly::SUB_SAT_S_I8x16_S, WebAssembly::SUB_SAT_S_I8x16 },
15686
0
  { WebAssembly::SUB_SAT_U_I16x8_S, WebAssembly::SUB_SAT_U_I16x8 },
15687
0
  { WebAssembly::SUB_SAT_U_I8x16_S, WebAssembly::SUB_SAT_U_I8x16 },
15688
0
  { WebAssembly::SWIZZLE_S, WebAssembly::SWIZZLE },
15689
0
  { WebAssembly::TABLE_COPY_S, WebAssembly::TABLE_COPY },
15690
0
  { WebAssembly::TABLE_FILL_EXTERNREF_S, WebAssembly::TABLE_FILL_EXTERNREF },
15691
0
  { WebAssembly::TABLE_FILL_FUNCREF_S, WebAssembly::TABLE_FILL_FUNCREF },
15692
0
  { WebAssembly::TABLE_GET_EXTERNREF_S, WebAssembly::TABLE_GET_EXTERNREF },
15693
0
  { WebAssembly::TABLE_GET_FUNCREF_S, WebAssembly::TABLE_GET_FUNCREF },
15694
0
  { WebAssembly::TABLE_GROW_EXTERNREF_S, WebAssembly::TABLE_GROW_EXTERNREF },
15695
0
  { WebAssembly::TABLE_GROW_FUNCREF_S, WebAssembly::TABLE_GROW_FUNCREF },
15696
0
  { WebAssembly::TABLE_SET_EXTERNREF_S, WebAssembly::TABLE_SET_EXTERNREF },
15697
0
  { WebAssembly::TABLE_SET_FUNCREF_S, WebAssembly::TABLE_SET_FUNCREF },
15698
0
  { WebAssembly::TABLE_SIZE_S, WebAssembly::TABLE_SIZE },
15699
0
  { WebAssembly::TEE_EXTERNREF_S, WebAssembly::TEE_EXTERNREF },
15700
0
  { WebAssembly::TEE_F32_S, WebAssembly::TEE_F32 },
15701
0
  { WebAssembly::TEE_F64_S, WebAssembly::TEE_F64 },
15702
0
  { WebAssembly::TEE_FUNCREF_S, WebAssembly::TEE_FUNCREF },
15703
0
  { WebAssembly::TEE_I32_S, WebAssembly::TEE_I32 },
15704
0
  { WebAssembly::TEE_I64_S, WebAssembly::TEE_I64 },
15705
0
  { WebAssembly::TEE_V128_S, WebAssembly::TEE_V128 },
15706
0
  { WebAssembly::THROW_S, WebAssembly::THROW },
15707
0
  { WebAssembly::TRUNC_F32_S, WebAssembly::TRUNC_F32 },
15708
0
  { WebAssembly::TRUNC_F32x4_S, WebAssembly::TRUNC_F32x4 },
15709
0
  { WebAssembly::TRUNC_F64_S, WebAssembly::TRUNC_F64 },
15710
0
  { WebAssembly::TRUNC_F64x2_S, WebAssembly::TRUNC_F64x2 },
15711
0
  { WebAssembly::TRY_S, WebAssembly::TRY },
15712
0
  { WebAssembly::UNREACHABLE_S, WebAssembly::UNREACHABLE },
15713
0
  { WebAssembly::XOR_I32_S, WebAssembly::XOR_I32 },
15714
0
  { WebAssembly::XOR_I64_S, WebAssembly::XOR_I64 },
15715
0
  { WebAssembly::XOR_S, WebAssembly::XOR },
15716
0
  { WebAssembly::anonymous_7277MEMORY_GROW_A32_S, WebAssembly::anonymous_7277MEMORY_GROW_A32 },
15717
0
  { WebAssembly::anonymous_7277MEMORY_SIZE_A32_S, WebAssembly::anonymous_7277MEMORY_SIZE_A32 },
15718
0
  { WebAssembly::anonymous_7278MEMORY_GROW_A64_S, WebAssembly::anonymous_7278MEMORY_GROW_A64 },
15719
0
  { WebAssembly::anonymous_7278MEMORY_SIZE_A64_S, WebAssembly::anonymous_7278MEMORY_SIZE_A64 },
15720
0
  { WebAssembly::anonymous_7959DATA_DROP_S, WebAssembly::anonymous_7959DATA_DROP },
15721
0
  { WebAssembly::anonymous_7959MEMORY_COPY_A32_S, WebAssembly::anonymous_7959MEMORY_COPY_A32 },
15722
0
  { WebAssembly::anonymous_7959MEMORY_FILL_A32_S, WebAssembly::anonymous_7959MEMORY_FILL_A32 },
15723
0
  { WebAssembly::anonymous_7959MEMORY_INIT_A32_S, WebAssembly::anonymous_7959MEMORY_INIT_A32 },
15724
0
  { WebAssembly::anonymous_7960DATA_DROP_S, WebAssembly::anonymous_7960DATA_DROP },
15725
0
  { WebAssembly::anonymous_7960MEMORY_COPY_A64_S, WebAssembly::anonymous_7960MEMORY_COPY_A64 },
15726
0
  { WebAssembly::anonymous_7960MEMORY_FILL_A64_S, WebAssembly::anonymous_7960MEMORY_FILL_A64 },
15727
0
  { WebAssembly::anonymous_7960MEMORY_INIT_A64_S, WebAssembly::anonymous_7960MEMORY_INIT_A64 },
15728
0
  { WebAssembly::convert_low_s_F64x2_S, WebAssembly::convert_low_s_F64x2 },
15729
0
  { WebAssembly::convert_low_u_F64x2_S, WebAssembly::convert_low_u_F64x2 },
15730
0
  { WebAssembly::demote_zero_F32x4_S, WebAssembly::demote_zero_F32x4 },
15731
0
  { WebAssembly::extend_high_s_I16x8_S, WebAssembly::extend_high_s_I16x8 },
15732
0
  { WebAssembly::extend_high_s_I32x4_S, WebAssembly::extend_high_s_I32x4 },
15733
0
  { WebAssembly::extend_high_s_I64x2_S, WebAssembly::extend_high_s_I64x2 },
15734
0
  { WebAssembly::extend_high_u_I16x8_S, WebAssembly::extend_high_u_I16x8 },
15735
0
  { WebAssembly::extend_high_u_I32x4_S, WebAssembly::extend_high_u_I32x4 },
15736
0
  { WebAssembly::extend_high_u_I64x2_S, WebAssembly::extend_high_u_I64x2 },
15737
0
  { WebAssembly::extend_low_s_I16x8_S, WebAssembly::extend_low_s_I16x8 },
15738
0
  { WebAssembly::extend_low_s_I32x4_S, WebAssembly::extend_low_s_I32x4 },
15739
0
  { WebAssembly::extend_low_s_I64x2_S, WebAssembly::extend_low_s_I64x2 },
15740
0
  { WebAssembly::extend_low_u_I16x8_S, WebAssembly::extend_low_u_I16x8 },
15741
0
  { WebAssembly::extend_low_u_I32x4_S, WebAssembly::extend_low_u_I32x4 },
15742
0
  { WebAssembly::extend_low_u_I64x2_S, WebAssembly::extend_low_u_I64x2 },
15743
0
  { WebAssembly::fp_to_sint_I32x4_S, WebAssembly::fp_to_sint_I32x4 },
15744
0
  { WebAssembly::fp_to_uint_I32x4_S, WebAssembly::fp_to_uint_I32x4 },
15745
0
  { WebAssembly::int_wasm_extadd_pairwise_signed_I16x8_S, WebAssembly::int_wasm_extadd_pairwise_signed_I16x8 },
15746
0
  { WebAssembly::int_wasm_extadd_pairwise_signed_I32x4_S, WebAssembly::int_wasm_extadd_pairwise_signed_I32x4 },
15747
0
  { WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8_S, WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8 },
15748
0
  { WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4_S, WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4 },
15749
0
  { WebAssembly::int_wasm_relaxed_trunc_signed_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_signed_I32x4 },
15750
0
  { WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4 },
15751
0
  { WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4 },
15752
0
  { WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4 },
15753
0
  { WebAssembly::promote_low_F64x2_S, WebAssembly::promote_low_F64x2 },
15754
0
  { WebAssembly::sint_to_fp_F32x4_S, WebAssembly::sint_to_fp_F32x4 },
15755
0
  { WebAssembly::trunc_sat_zero_s_I32x4_S, WebAssembly::trunc_sat_zero_s_I32x4 },
15756
0
  { WebAssembly::trunc_sat_zero_u_I32x4_S, WebAssembly::trunc_sat_zero_u_I32x4 },
15757
0
  { WebAssembly::uint_to_fp_F32x4_S, WebAssembly::uint_to_fp_F32x4 },
15758
0
}; // End of getRegisterOpcodeTable
15759
15760
0
  unsigned mid;
15761
0
  unsigned start = 0;
15762
0
  unsigned end = 750;
15763
0
  while (start < end) {
15764
0
    mid = start + (end - start) / 2;
15765
0
    if (Opcode == getRegisterOpcodeTable[mid][0]) {
15766
0
      break;
15767
0
    }
15768
0
    if (Opcode < getRegisterOpcodeTable[mid][0])
15769
0
      end = mid;
15770
0
    else
15771
0
      start = mid + 1;
15772
0
  }
15773
0
  if (start == end)
15774
0
    return -1; // Instruction doesn't exist in this table.
15775
15776
0
  return getRegisterOpcodeTable[mid][1];
15777
0
}
15778
15779
// getStackOpcode
15780
LLVM_READONLY
15781
95.5k
int getStackOpcode(uint16_t Opcode) {
15782
95.5k
static const uint16_t getStackOpcodeTable[][2] = {
15783
95.5k
  { WebAssembly::CALL_PARAMS, WebAssembly::CALL_PARAMS_S },
15784
95.5k
  { WebAssembly::CALL_RESULTS, WebAssembly::CALL_RESULTS_S },
15785
95.5k
  { WebAssembly::CATCHRET, WebAssembly::CATCHRET_S },
15786
95.5k
  { WebAssembly::CLEANUPRET, WebAssembly::CLEANUPRET_S },
15787
95.5k
  { WebAssembly::COMPILER_FENCE, WebAssembly::COMPILER_FENCE_S },
15788
95.5k
  { WebAssembly::RET_CALL_RESULTS, WebAssembly::RET_CALL_RESULTS_S },
15789
95.5k
  { WebAssembly::ABS_F32, WebAssembly::ABS_F32_S },
15790
95.5k
  { WebAssembly::ABS_F32x4, WebAssembly::ABS_F32x4_S },
15791
95.5k
  { WebAssembly::ABS_F64, WebAssembly::ABS_F64_S },
15792
95.5k
  { WebAssembly::ABS_F64x2, WebAssembly::ABS_F64x2_S },
15793
95.5k
  { WebAssembly::ABS_I16x8, WebAssembly::ABS_I16x8_S },
15794
95.5k
  { WebAssembly::ABS_I32x4, WebAssembly::ABS_I32x4_S },
15795
95.5k
  { WebAssembly::ABS_I64x2, WebAssembly::ABS_I64x2_S },
15796
95.5k
  { WebAssembly::ABS_I8x16, WebAssembly::ABS_I8x16_S },
15797
95.5k
  { WebAssembly::ADD_F32, WebAssembly::ADD_F32_S },
15798
95.5k
  { WebAssembly::ADD_F32x4, WebAssembly::ADD_F32x4_S },
15799
95.5k
  { WebAssembly::ADD_F64, WebAssembly::ADD_F64_S },
15800
95.5k
  { WebAssembly::ADD_F64x2, WebAssembly::ADD_F64x2_S },
15801
95.5k
  { WebAssembly::ADD_I16x8, WebAssembly::ADD_I16x8_S },
15802
95.5k
  { WebAssembly::ADD_I32, WebAssembly::ADD_I32_S },
15803
95.5k
  { WebAssembly::ADD_I32x4, WebAssembly::ADD_I32x4_S },
15804
95.5k
  { WebAssembly::ADD_I64, WebAssembly::ADD_I64_S },
15805
95.5k
  { WebAssembly::ADD_I64x2, WebAssembly::ADD_I64x2_S },
15806
95.5k
  { WebAssembly::ADD_I8x16, WebAssembly::ADD_I8x16_S },
15807
95.5k
  { WebAssembly::ADD_SAT_S_I16x8, WebAssembly::ADD_SAT_S_I16x8_S },
15808
95.5k
  { WebAssembly::ADD_SAT_S_I8x16, WebAssembly::ADD_SAT_S_I8x16_S },
15809
95.5k
  { WebAssembly::ADD_SAT_U_I16x8, WebAssembly::ADD_SAT_U_I16x8_S },
15810
95.5k
  { WebAssembly::ADD_SAT_U_I8x16, WebAssembly::ADD_SAT_U_I8x16_S },
15811
95.5k
  { WebAssembly::ADJCALLSTACKDOWN, WebAssembly::ADJCALLSTACKDOWN_S },
15812
95.5k
  { WebAssembly::ADJCALLSTACKUP, WebAssembly::ADJCALLSTACKUP_S },
15813
95.5k
  { WebAssembly::ALLTRUE_I16x8, WebAssembly::ALLTRUE_I16x8_S },
15814
95.5k
  { WebAssembly::ALLTRUE_I32x4, WebAssembly::ALLTRUE_I32x4_S },
15815
95.5k
  { WebAssembly::ALLTRUE_I64x2, WebAssembly::ALLTRUE_I64x2_S },
15816
95.5k
  { WebAssembly::ALLTRUE_I8x16, WebAssembly::ALLTRUE_I8x16_S },
15817
95.5k
  { WebAssembly::AND, WebAssembly::AND_S },
15818
95.5k
  { WebAssembly::ANDNOT, WebAssembly::ANDNOT_S },
15819
95.5k
  { WebAssembly::AND_I32, WebAssembly::AND_I32_S },
15820
95.5k
  { WebAssembly::AND_I64, WebAssembly::AND_I64_S },
15821
95.5k
  { WebAssembly::ANYTRUE, WebAssembly::ANYTRUE_S },
15822
95.5k
  { WebAssembly::ARGUMENT_externref, WebAssembly::ARGUMENT_externref_S },
15823
95.5k
  { WebAssembly::ARGUMENT_f32, WebAssembly::ARGUMENT_f32_S },
15824
95.5k
  { WebAssembly::ARGUMENT_f64, WebAssembly::ARGUMENT_f64_S },
15825
95.5k
  { WebAssembly::ARGUMENT_funcref, WebAssembly::ARGUMENT_funcref_S },
15826
95.5k
  { WebAssembly::ARGUMENT_i32, WebAssembly::ARGUMENT_i32_S },
15827
95.5k
  { WebAssembly::ARGUMENT_i64, WebAssembly::ARGUMENT_i64_S },
15828
95.5k
  { WebAssembly::ARGUMENT_v16i8, WebAssembly::ARGUMENT_v16i8_S },
15829
95.5k
  { WebAssembly::ARGUMENT_v2f64, WebAssembly::ARGUMENT_v2f64_S },
15830
95.5k
  { WebAssembly::ARGUMENT_v2i64, WebAssembly::ARGUMENT_v2i64_S },
15831
95.5k
  { WebAssembly::ARGUMENT_v4f32, WebAssembly::ARGUMENT_v4f32_S },
15832
95.5k
  { WebAssembly::ARGUMENT_v4i32, WebAssembly::ARGUMENT_v4i32_S },
15833
95.5k
  { WebAssembly::ARGUMENT_v8i16, WebAssembly::ARGUMENT_v8i16_S },
15834
95.5k
  { WebAssembly::ATOMIC_FENCE, WebAssembly::ATOMIC_FENCE_S },
15835
95.5k
  { WebAssembly::ATOMIC_LOAD16_U_I32_A32, WebAssembly::ATOMIC_LOAD16_U_I32_A32_S },
15836
95.5k
  { WebAssembly::ATOMIC_LOAD16_U_I32_A64, WebAssembly::ATOMIC_LOAD16_U_I32_A64_S },
15837
95.5k
  { WebAssembly::ATOMIC_LOAD16_U_I64_A32, WebAssembly::ATOMIC_LOAD16_U_I64_A32_S },
15838
95.5k
  { WebAssembly::ATOMIC_LOAD16_U_I64_A64, WebAssembly::ATOMIC_LOAD16_U_I64_A64_S },
15839
95.5k
  { WebAssembly::ATOMIC_LOAD32_U_I64_A32, WebAssembly::ATOMIC_LOAD32_U_I64_A32_S },
15840
95.5k
  { WebAssembly::ATOMIC_LOAD32_U_I64_A64, WebAssembly::ATOMIC_LOAD32_U_I64_A64_S },
15841
95.5k
  { WebAssembly::ATOMIC_LOAD8_U_I32_A32, WebAssembly::ATOMIC_LOAD8_U_I32_A32_S },
15842
95.5k
  { WebAssembly::ATOMIC_LOAD8_U_I32_A64, WebAssembly::ATOMIC_LOAD8_U_I32_A64_S },
15843
95.5k
  { WebAssembly::ATOMIC_LOAD8_U_I64_A32, WebAssembly::ATOMIC_LOAD8_U_I64_A32_S },
15844
95.5k
  { WebAssembly::ATOMIC_LOAD8_U_I64_A64, WebAssembly::ATOMIC_LOAD8_U_I64_A64_S },
15845
95.5k
  { WebAssembly::ATOMIC_LOAD_I32_A32, WebAssembly::ATOMIC_LOAD_I32_A32_S },
15846
95.5k
  { WebAssembly::ATOMIC_LOAD_I32_A64, WebAssembly::ATOMIC_LOAD_I32_A64_S },
15847
95.5k
  { WebAssembly::ATOMIC_LOAD_I64_A32, WebAssembly::ATOMIC_LOAD_I64_A32_S },
15848
95.5k
  { WebAssembly::ATOMIC_LOAD_I64_A64, WebAssembly::ATOMIC_LOAD_I64_A64_S },
15849
95.5k
  { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S },
15850
95.5k
  { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S },
15851
95.5k
  { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S },
15852
95.5k
  { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S },
15853
95.5k
  { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32, WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S },
15854
95.5k
  { WebAssembly::ATOMIC_RMW16_U_AND_I32_A64, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S },
15855
95.5k
  { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32, WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S },
15856
95.5k
  { WebAssembly::ATOMIC_RMW16_U_AND_I64_A64, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S },
15857
95.5k
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S },
15858
95.5k
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
15859
95.5k
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S },
15860
95.5k
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
15861
95.5k
  { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32, WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S },
15862
95.5k
  { WebAssembly::ATOMIC_RMW16_U_OR_I32_A64, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S },
15863
95.5k
  { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32, WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S },
15864
95.5k
  { WebAssembly::ATOMIC_RMW16_U_OR_I64_A64, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S },
15865
95.5k
  { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S },
15866
95.5k
  { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S },
15867
95.5k
  { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S },
15868
95.5k
  { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S },
15869
95.5k
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S },
15870
95.5k
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S },
15871
95.5k
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S },
15872
95.5k
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S },
15873
95.5k
  { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S },
15874
95.5k
  { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S },
15875
95.5k
  { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S },
15876
95.5k
  { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S },
15877
95.5k
  { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S },
15878
95.5k
  { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S },
15879
95.5k
  { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32, WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S },
15880
95.5k
  { WebAssembly::ATOMIC_RMW32_U_AND_I64_A64, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S },
15881
95.5k
  { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S },
15882
95.5k
  { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
15883
95.5k
  { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32, WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S },
15884
95.5k
  { WebAssembly::ATOMIC_RMW32_U_OR_I64_A64, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S },
15885
95.5k
  { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S },
15886
95.5k
  { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S },
15887
95.5k
  { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S },
15888
95.5k
  { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S },
15889
95.5k
  { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S },
15890
95.5k
  { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S },
15891
95.5k
  { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S },
15892
95.5k
  { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S },
15893
95.5k
  { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S },
15894
95.5k
  { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S },
15895
95.5k
  { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32, WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S },
15896
95.5k
  { WebAssembly::ATOMIC_RMW8_U_AND_I32_A64, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S },
15897
95.5k
  { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32, WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S },
15898
95.5k
  { WebAssembly::ATOMIC_RMW8_U_AND_I64_A64, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S },
15899
95.5k
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S },
15900
95.5k
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
15901
95.5k
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S },
15902
95.5k
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
15903
95.5k
  { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32, WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S },
15904
95.5k
  { WebAssembly::ATOMIC_RMW8_U_OR_I32_A64, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S },
15905
95.5k
  { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32, WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S },
15906
95.5k
  { WebAssembly::ATOMIC_RMW8_U_OR_I64_A64, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S },
15907
95.5k
  { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S },
15908
95.5k
  { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S },
15909
95.5k
  { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S },
15910
95.5k
  { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S },
15911
95.5k
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S },
15912
95.5k
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S },
15913
95.5k
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S },
15914
95.5k
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S },
15915
95.5k
  { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S },
15916
95.5k
  { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S },
15917
95.5k
  { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S },
15918
95.5k
  { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S },
15919
95.5k
  { WebAssembly::ATOMIC_RMW_ADD_I32_A32, WebAssembly::ATOMIC_RMW_ADD_I32_A32_S },
15920
95.5k
  { WebAssembly::ATOMIC_RMW_ADD_I32_A64, WebAssembly::ATOMIC_RMW_ADD_I32_A64_S },
15921
95.5k
  { WebAssembly::ATOMIC_RMW_ADD_I64_A32, WebAssembly::ATOMIC_RMW_ADD_I64_A32_S },
15922
95.5k
  { WebAssembly::ATOMIC_RMW_ADD_I64_A64, WebAssembly::ATOMIC_RMW_ADD_I64_A64_S },
15923
95.5k
  { WebAssembly::ATOMIC_RMW_AND_I32_A32, WebAssembly::ATOMIC_RMW_AND_I32_A32_S },
15924
95.5k
  { WebAssembly::ATOMIC_RMW_AND_I32_A64, WebAssembly::ATOMIC_RMW_AND_I32_A64_S },
15925
95.5k
  { WebAssembly::ATOMIC_RMW_AND_I64_A32, WebAssembly::ATOMIC_RMW_AND_I64_A32_S },
15926
95.5k
  { WebAssembly::ATOMIC_RMW_AND_I64_A64, WebAssembly::ATOMIC_RMW_AND_I64_A64_S },
15927
95.5k
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S },
15928
95.5k
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S },
15929
95.5k
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S },
15930
95.5k
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S },
15931
95.5k
  { WebAssembly::ATOMIC_RMW_OR_I32_A32, WebAssembly::ATOMIC_RMW_OR_I32_A32_S },
15932
95.5k
  { WebAssembly::ATOMIC_RMW_OR_I32_A64, WebAssembly::ATOMIC_RMW_OR_I32_A64_S },
15933
95.5k
  { WebAssembly::ATOMIC_RMW_OR_I64_A32, WebAssembly::ATOMIC_RMW_OR_I64_A32_S },
15934
95.5k
  { WebAssembly::ATOMIC_RMW_OR_I64_A64, WebAssembly::ATOMIC_RMW_OR_I64_A64_S },
15935
95.5k
  { WebAssembly::ATOMIC_RMW_SUB_I32_A32, WebAssembly::ATOMIC_RMW_SUB_I32_A32_S },
15936
95.5k
  { WebAssembly::ATOMIC_RMW_SUB_I32_A64, WebAssembly::ATOMIC_RMW_SUB_I32_A64_S },
15937
95.5k
  { WebAssembly::ATOMIC_RMW_SUB_I64_A32, WebAssembly::ATOMIC_RMW_SUB_I64_A32_S },
15938
95.5k
  { WebAssembly::ATOMIC_RMW_SUB_I64_A64, WebAssembly::ATOMIC_RMW_SUB_I64_A64_S },
15939
95.5k
  { WebAssembly::ATOMIC_RMW_XCHG_I32_A32, WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S },
15940
95.5k
  { WebAssembly::ATOMIC_RMW_XCHG_I32_A64, WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S },
15941
95.5k
  { WebAssembly::ATOMIC_RMW_XCHG_I64_A32, WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S },
15942
95.5k
  { WebAssembly::ATOMIC_RMW_XCHG_I64_A64, WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S },
15943
95.5k
  { WebAssembly::ATOMIC_RMW_XOR_I32_A32, WebAssembly::ATOMIC_RMW_XOR_I32_A32_S },
15944
95.5k
  { WebAssembly::ATOMIC_RMW_XOR_I32_A64, WebAssembly::ATOMIC_RMW_XOR_I32_A64_S },
15945
95.5k
  { WebAssembly::ATOMIC_RMW_XOR_I64_A32, WebAssembly::ATOMIC_RMW_XOR_I64_A32_S },
15946
95.5k
  { WebAssembly::ATOMIC_RMW_XOR_I64_A64, WebAssembly::ATOMIC_RMW_XOR_I64_A64_S },
15947
95.5k
  { WebAssembly::ATOMIC_STORE16_I32_A32, WebAssembly::ATOMIC_STORE16_I32_A32_S },
15948
95.5k
  { WebAssembly::ATOMIC_STORE16_I32_A64, WebAssembly::ATOMIC_STORE16_I32_A64_S },
15949
95.5k
  { WebAssembly::ATOMIC_STORE16_I64_A32, WebAssembly::ATOMIC_STORE16_I64_A32_S },
15950
95.5k
  { WebAssembly::ATOMIC_STORE16_I64_A64, WebAssembly::ATOMIC_STORE16_I64_A64_S },
15951
95.5k
  { WebAssembly::ATOMIC_STORE32_I64_A32, WebAssembly::ATOMIC_STORE32_I64_A32_S },
15952
95.5k
  { WebAssembly::ATOMIC_STORE32_I64_A64, WebAssembly::ATOMIC_STORE32_I64_A64_S },
15953
95.5k
  { WebAssembly::ATOMIC_STORE8_I32_A32, WebAssembly::ATOMIC_STORE8_I32_A32_S },
15954
95.5k
  { WebAssembly::ATOMIC_STORE8_I32_A64, WebAssembly::ATOMIC_STORE8_I32_A64_S },
15955
95.5k
  { WebAssembly::ATOMIC_STORE8_I64_A32, WebAssembly::ATOMIC_STORE8_I64_A32_S },
15956
95.5k
  { WebAssembly::ATOMIC_STORE8_I64_A64, WebAssembly::ATOMIC_STORE8_I64_A64_S },
15957
95.5k
  { WebAssembly::ATOMIC_STORE_I32_A32, WebAssembly::ATOMIC_STORE_I32_A32_S },
15958
95.5k
  { WebAssembly::ATOMIC_STORE_I32_A64, WebAssembly::ATOMIC_STORE_I32_A64_S },
15959
95.5k
  { WebAssembly::ATOMIC_STORE_I64_A32, WebAssembly::ATOMIC_STORE_I64_A32_S },
15960
95.5k
  { WebAssembly::ATOMIC_STORE_I64_A64, WebAssembly::ATOMIC_STORE_I64_A64_S },
15961
95.5k
  { WebAssembly::AVGR_U_I16x8, WebAssembly::AVGR_U_I16x8_S },
15962
95.5k
  { WebAssembly::AVGR_U_I8x16, WebAssembly::AVGR_U_I8x16_S },
15963
95.5k
  { WebAssembly::BITMASK_I16x8, WebAssembly::BITMASK_I16x8_S },
15964
95.5k
  { WebAssembly::BITMASK_I32x4, WebAssembly::BITMASK_I32x4_S },
15965
95.5k
  { WebAssembly::BITMASK_I64x2, WebAssembly::BITMASK_I64x2_S },
15966
95.5k
  { WebAssembly::BITMASK_I8x16, WebAssembly::BITMASK_I8x16_S },
15967
95.5k
  { WebAssembly::BITSELECT, WebAssembly::BITSELECT_S },
15968
95.5k
  { WebAssembly::BLOCK, WebAssembly::BLOCK_S },
15969
95.5k
  { WebAssembly::BR, WebAssembly::BR_S },
15970
95.5k
  { WebAssembly::BR_IF, WebAssembly::BR_IF_S },
15971
95.5k
  { WebAssembly::BR_TABLE_I32, WebAssembly::BR_TABLE_I32_S },
15972
95.5k
  { WebAssembly::BR_TABLE_I64, WebAssembly::BR_TABLE_I64_S },
15973
95.5k
  { WebAssembly::BR_UNLESS, WebAssembly::BR_UNLESS_S },
15974
95.5k
  { WebAssembly::CALL, WebAssembly::CALL_S },
15975
95.5k
  { WebAssembly::CALL_INDIRECT, WebAssembly::CALL_INDIRECT_S },
15976
95.5k
  { WebAssembly::CATCH, WebAssembly::CATCH_S },
15977
95.5k
  { WebAssembly::CATCH_ALL, WebAssembly::CATCH_ALL_S },
15978
95.5k
  { WebAssembly::CEIL_F32, WebAssembly::CEIL_F32_S },
15979
95.5k
  { WebAssembly::CEIL_F32x4, WebAssembly::CEIL_F32x4_S },
15980
95.5k
  { WebAssembly::CEIL_F64, WebAssembly::CEIL_F64_S },
15981
95.5k
  { WebAssembly::CEIL_F64x2, WebAssembly::CEIL_F64x2_S },
15982
95.5k
  { WebAssembly::CLZ_I32, WebAssembly::CLZ_I32_S },
15983
95.5k
  { WebAssembly::CLZ_I64, WebAssembly::CLZ_I64_S },
15984
95.5k
  { WebAssembly::CONST_F32, WebAssembly::CONST_F32_S },
15985
95.5k
  { WebAssembly::CONST_F64, WebAssembly::CONST_F64_S },
15986
95.5k
  { WebAssembly::CONST_I32, WebAssembly::CONST_I32_S },
15987
95.5k
  { WebAssembly::CONST_I64, WebAssembly::CONST_I64_S },
15988
95.5k
  { WebAssembly::CONST_V128_F32x4, WebAssembly::CONST_V128_F32x4_S },
15989
95.5k
  { WebAssembly::CONST_V128_F64x2, WebAssembly::CONST_V128_F64x2_S },
15990
95.5k
  { WebAssembly::CONST_V128_I16x8, WebAssembly::CONST_V128_I16x8_S },
15991
95.5k
  { WebAssembly::CONST_V128_I32x4, WebAssembly::CONST_V128_I32x4_S },
15992
95.5k
  { WebAssembly::CONST_V128_I64x2, WebAssembly::CONST_V128_I64x2_S },
15993
95.5k
  { WebAssembly::CONST_V128_I8x16, WebAssembly::CONST_V128_I8x16_S },
15994
95.5k
  { WebAssembly::COPYSIGN_F32, WebAssembly::COPYSIGN_F32_S },
15995
95.5k
  { WebAssembly::COPYSIGN_F64, WebAssembly::COPYSIGN_F64_S },
15996
95.5k
  { WebAssembly::COPY_EXTERNREF, WebAssembly::COPY_EXTERNREF_S },
15997
95.5k
  { WebAssembly::COPY_F32, WebAssembly::COPY_F32_S },
15998
95.5k
  { WebAssembly::COPY_F64, WebAssembly::COPY_F64_S },
15999
95.5k
  { WebAssembly::COPY_FUNCREF, WebAssembly::COPY_FUNCREF_S },
16000
95.5k
  { WebAssembly::COPY_I32, WebAssembly::COPY_I32_S },
16001
95.5k
  { WebAssembly::COPY_I64, WebAssembly::COPY_I64_S },
16002
95.5k
  { WebAssembly::COPY_V128, WebAssembly::COPY_V128_S },
16003
95.5k
  { WebAssembly::CTZ_I32, WebAssembly::CTZ_I32_S },
16004
95.5k
  { WebAssembly::CTZ_I64, WebAssembly::CTZ_I64_S },
16005
95.5k
  { WebAssembly::DEBUG_UNREACHABLE, WebAssembly::DEBUG_UNREACHABLE_S },
16006
95.5k
  { WebAssembly::DELEGATE, WebAssembly::DELEGATE_S },
16007
95.5k
  { WebAssembly::DIV_F32, WebAssembly::DIV_F32_S },
16008
95.5k
  { WebAssembly::DIV_F32x4, WebAssembly::DIV_F32x4_S },
16009
95.5k
  { WebAssembly::DIV_F64, WebAssembly::DIV_F64_S },
16010
95.5k
  { WebAssembly::DIV_F64x2, WebAssembly::DIV_F64x2_S },
16011
95.5k
  { WebAssembly::DIV_S_I32, WebAssembly::DIV_S_I32_S },
16012
95.5k
  { WebAssembly::DIV_S_I64, WebAssembly::DIV_S_I64_S },
16013
95.5k
  { WebAssembly::DIV_U_I32, WebAssembly::DIV_U_I32_S },
16014
95.5k
  { WebAssembly::DIV_U_I64, WebAssembly::DIV_U_I64_S },
16015
95.5k
  { WebAssembly::DOT, WebAssembly::DOT_S },
16016
95.5k
  { WebAssembly::DROP_EXTERNREF, WebAssembly::DROP_EXTERNREF_S },
16017
95.5k
  { WebAssembly::DROP_F32, WebAssembly::DROP_F32_S },
16018
95.5k
  { WebAssembly::DROP_F64, WebAssembly::DROP_F64_S },
16019
95.5k
  { WebAssembly::DROP_FUNCREF, WebAssembly::DROP_FUNCREF_S },
16020
95.5k
  { WebAssembly::DROP_I32, WebAssembly::DROP_I32_S },
16021
95.5k
  { WebAssembly::DROP_I64, WebAssembly::DROP_I64_S },
16022
95.5k
  { WebAssembly::DROP_V128, WebAssembly::DROP_V128_S },
16023
95.5k
  { WebAssembly::ELSE, WebAssembly::ELSE_S },
16024
95.5k
  { WebAssembly::END, WebAssembly::END_S },
16025
95.5k
  { WebAssembly::END_BLOCK, WebAssembly::END_BLOCK_S },
16026
95.5k
  { WebAssembly::END_FUNCTION, WebAssembly::END_FUNCTION_S },
16027
95.5k
  { WebAssembly::END_IF, WebAssembly::END_IF_S },
16028
95.5k
  { WebAssembly::END_LOOP, WebAssembly::END_LOOP_S },
16029
95.5k
  { WebAssembly::END_TRY, WebAssembly::END_TRY_S },
16030
95.5k
  { WebAssembly::EQZ_I32, WebAssembly::EQZ_I32_S },
16031
95.5k
  { WebAssembly::EQZ_I64, WebAssembly::EQZ_I64_S },
16032
95.5k
  { WebAssembly::EQ_F32, WebAssembly::EQ_F32_S },
16033
95.5k
  { WebAssembly::EQ_F32x4, WebAssembly::EQ_F32x4_S },
16034
95.5k
  { WebAssembly::EQ_F64, WebAssembly::EQ_F64_S },
16035
95.5k
  { WebAssembly::EQ_F64x2, WebAssembly::EQ_F64x2_S },
16036
95.5k
  { WebAssembly::EQ_I16x8, WebAssembly::EQ_I16x8_S },
16037
95.5k
  { WebAssembly::EQ_I32, WebAssembly::EQ_I32_S },
16038
95.5k
  { WebAssembly::EQ_I32x4, WebAssembly::EQ_I32x4_S },
16039
95.5k
  { WebAssembly::EQ_I64, WebAssembly::EQ_I64_S },
16040
95.5k
  { WebAssembly::EQ_I64x2, WebAssembly::EQ_I64x2_S },
16041
95.5k
  { WebAssembly::EQ_I8x16, WebAssembly::EQ_I8x16_S },
16042
95.5k
  { WebAssembly::EXTMUL_HIGH_S_I16x8, WebAssembly::EXTMUL_HIGH_S_I16x8_S },
16043
95.5k
  { WebAssembly::EXTMUL_HIGH_S_I32x4, WebAssembly::EXTMUL_HIGH_S_I32x4_S },
16044
95.5k
  { WebAssembly::EXTMUL_HIGH_S_I64x2, WebAssembly::EXTMUL_HIGH_S_I64x2_S },
16045
95.5k
  { WebAssembly::EXTMUL_HIGH_U_I16x8, WebAssembly::EXTMUL_HIGH_U_I16x8_S },
16046
95.5k
  { WebAssembly::EXTMUL_HIGH_U_I32x4, WebAssembly::EXTMUL_HIGH_U_I32x4_S },
16047
95.5k
  { WebAssembly::EXTMUL_HIGH_U_I64x2, WebAssembly::EXTMUL_HIGH_U_I64x2_S },
16048
95.5k
  { WebAssembly::EXTMUL_LOW_S_I16x8, WebAssembly::EXTMUL_LOW_S_I16x8_S },
16049
95.5k
  { WebAssembly::EXTMUL_LOW_S_I32x4, WebAssembly::EXTMUL_LOW_S_I32x4_S },
16050
95.5k
  { WebAssembly::EXTMUL_LOW_S_I64x2, WebAssembly::EXTMUL_LOW_S_I64x2_S },
16051
95.5k
  { WebAssembly::EXTMUL_LOW_U_I16x8, WebAssembly::EXTMUL_LOW_U_I16x8_S },
16052
95.5k
  { WebAssembly::EXTMUL_LOW_U_I32x4, WebAssembly::EXTMUL_LOW_U_I32x4_S },
16053
95.5k
  { WebAssembly::EXTMUL_LOW_U_I64x2, WebAssembly::EXTMUL_LOW_U_I64x2_S },
16054
95.5k
  { WebAssembly::EXTRACT_LANE_F32x4, WebAssembly::EXTRACT_LANE_F32x4_S },
16055
95.5k
  { WebAssembly::EXTRACT_LANE_F64x2, WebAssembly::EXTRACT_LANE_F64x2_S },
16056
95.5k
  { WebAssembly::EXTRACT_LANE_I16x8_s, WebAssembly::EXTRACT_LANE_I16x8_s_S },
16057
95.5k
  { WebAssembly::EXTRACT_LANE_I16x8_u, WebAssembly::EXTRACT_LANE_I16x8_u_S },
16058
95.5k
  { WebAssembly::EXTRACT_LANE_I32x4, WebAssembly::EXTRACT_LANE_I32x4_S },
16059
95.5k
  { WebAssembly::EXTRACT_LANE_I64x2, WebAssembly::EXTRACT_LANE_I64x2_S },
16060
95.5k
  { WebAssembly::EXTRACT_LANE_I8x16_s, WebAssembly::EXTRACT_LANE_I8x16_s_S },
16061
95.5k
  { WebAssembly::EXTRACT_LANE_I8x16_u, WebAssembly::EXTRACT_LANE_I8x16_u_S },
16062
95.5k
  { WebAssembly::F32_CONVERT_S_I32, WebAssembly::F32_CONVERT_S_I32_S },
16063
95.5k
  { WebAssembly::F32_CONVERT_S_I64, WebAssembly::F32_CONVERT_S_I64_S },
16064
95.5k
  { WebAssembly::F32_CONVERT_U_I32, WebAssembly::F32_CONVERT_U_I32_S },
16065
95.5k
  { WebAssembly::F32_CONVERT_U_I64, WebAssembly::F32_CONVERT_U_I64_S },
16066
95.5k
  { WebAssembly::F32_DEMOTE_F64, WebAssembly::F32_DEMOTE_F64_S },
16067
95.5k
  { WebAssembly::F32_REINTERPRET_I32, WebAssembly::F32_REINTERPRET_I32_S },
16068
95.5k
  { WebAssembly::F64_CONVERT_S_I32, WebAssembly::F64_CONVERT_S_I32_S },
16069
95.5k
  { WebAssembly::F64_CONVERT_S_I64, WebAssembly::F64_CONVERT_S_I64_S },
16070
95.5k
  { WebAssembly::F64_CONVERT_U_I32, WebAssembly::F64_CONVERT_U_I32_S },
16071
95.5k
  { WebAssembly::F64_CONVERT_U_I64, WebAssembly::F64_CONVERT_U_I64_S },
16072
95.5k
  { WebAssembly::F64_PROMOTE_F32, WebAssembly::F64_PROMOTE_F32_S },
16073
95.5k
  { WebAssembly::F64_REINTERPRET_I64, WebAssembly::F64_REINTERPRET_I64_S },
16074
95.5k
  { WebAssembly::FALLTHROUGH_RETURN, WebAssembly::FALLTHROUGH_RETURN_S },
16075
95.5k
  { WebAssembly::FLOOR_F32, WebAssembly::FLOOR_F32_S },
16076
95.5k
  { WebAssembly::FLOOR_F32x4, WebAssembly::FLOOR_F32x4_S },
16077
95.5k
  { WebAssembly::FLOOR_F64, WebAssembly::FLOOR_F64_S },
16078
95.5k
  { WebAssembly::FLOOR_F64x2, WebAssembly::FLOOR_F64x2_S },
16079
95.5k
  { WebAssembly::FP_TO_SINT_I32_F32, WebAssembly::FP_TO_SINT_I32_F32_S },
16080
95.5k
  { WebAssembly::FP_TO_SINT_I32_F64, WebAssembly::FP_TO_SINT_I32_F64_S },
16081
95.5k
  { WebAssembly::FP_TO_SINT_I64_F32, WebAssembly::FP_TO_SINT_I64_F32_S },
16082
95.5k
  { WebAssembly::FP_TO_SINT_I64_F64, WebAssembly::FP_TO_SINT_I64_F64_S },
16083
95.5k
  { WebAssembly::FP_TO_UINT_I32_F32, WebAssembly::FP_TO_UINT_I32_F32_S },
16084
95.5k
  { WebAssembly::FP_TO_UINT_I32_F64, WebAssembly::FP_TO_UINT_I32_F64_S },
16085
95.5k
  { WebAssembly::FP_TO_UINT_I64_F32, WebAssembly::FP_TO_UINT_I64_F32_S },
16086
95.5k
  { WebAssembly::FP_TO_UINT_I64_F64, WebAssembly::FP_TO_UINT_I64_F64_S },
16087
95.5k
  { WebAssembly::GE_F32, WebAssembly::GE_F32_S },
16088
95.5k
  { WebAssembly::GE_F32x4, WebAssembly::GE_F32x4_S },
16089
95.5k
  { WebAssembly::GE_F64, WebAssembly::GE_F64_S },
16090
95.5k
  { WebAssembly::GE_F64x2, WebAssembly::GE_F64x2_S },
16091
95.5k
  { WebAssembly::GE_S_I16x8, WebAssembly::GE_S_I16x8_S },
16092
95.5k
  { WebAssembly::GE_S_I32, WebAssembly::GE_S_I32_S },
16093
95.5k
  { WebAssembly::GE_S_I32x4, WebAssembly::GE_S_I32x4_S },
16094
95.5k
  { WebAssembly::GE_S_I64, WebAssembly::GE_S_I64_S },
16095
95.5k
  { WebAssembly::GE_S_I64x2, WebAssembly::GE_S_I64x2_S },
16096
95.5k
  { WebAssembly::GE_S_I8x16, WebAssembly::GE_S_I8x16_S },
16097
95.5k
  { WebAssembly::GE_U_I16x8, WebAssembly::GE_U_I16x8_S },
16098
95.5k
  { WebAssembly::GE_U_I32, WebAssembly::GE_U_I32_S },
16099
95.5k
  { WebAssembly::GE_U_I32x4, WebAssembly::GE_U_I32x4_S },
16100
95.5k
  { WebAssembly::GE_U_I64, WebAssembly::GE_U_I64_S },
16101
95.5k
  { WebAssembly::GE_U_I8x16, WebAssembly::GE_U_I8x16_S },
16102
95.5k
  { WebAssembly::GLOBAL_GET_EXTERNREF, WebAssembly::GLOBAL_GET_EXTERNREF_S },
16103
95.5k
  { WebAssembly::GLOBAL_GET_F32, WebAssembly::GLOBAL_GET_F32_S },
16104
95.5k
  { WebAssembly::GLOBAL_GET_F64, WebAssembly::GLOBAL_GET_F64_S },
16105
95.5k
  { WebAssembly::GLOBAL_GET_FUNCREF, WebAssembly::GLOBAL_GET_FUNCREF_S },
16106
95.5k
  { WebAssembly::GLOBAL_GET_I32, WebAssembly::GLOBAL_GET_I32_S },
16107
95.5k
  { WebAssembly::GLOBAL_GET_I64, WebAssembly::GLOBAL_GET_I64_S },
16108
95.5k
  { WebAssembly::GLOBAL_GET_V128, WebAssembly::GLOBAL_GET_V128_S },
16109
95.5k
  { WebAssembly::GLOBAL_SET_EXTERNREF, WebAssembly::GLOBAL_SET_EXTERNREF_S },
16110
95.5k
  { WebAssembly::GLOBAL_SET_F32, WebAssembly::GLOBAL_SET_F32_S },
16111
95.5k
  { WebAssembly::GLOBAL_SET_F64, WebAssembly::GLOBAL_SET_F64_S },
16112
95.5k
  { WebAssembly::GLOBAL_SET_FUNCREF, WebAssembly::GLOBAL_SET_FUNCREF_S },
16113
95.5k
  { WebAssembly::GLOBAL_SET_I32, WebAssembly::GLOBAL_SET_I32_S },
16114
95.5k
  { WebAssembly::GLOBAL_SET_I64, WebAssembly::GLOBAL_SET_I64_S },
16115
95.5k
  { WebAssembly::GLOBAL_SET_V128, WebAssembly::GLOBAL_SET_V128_S },
16116
95.5k
  { WebAssembly::GT_F32, WebAssembly::GT_F32_S },
16117
95.5k
  { WebAssembly::GT_F32x4, WebAssembly::GT_F32x4_S },
16118
95.5k
  { WebAssembly::GT_F64, WebAssembly::GT_F64_S },
16119
95.5k
  { WebAssembly::GT_F64x2, WebAssembly::GT_F64x2_S },
16120
95.5k
  { WebAssembly::GT_S_I16x8, WebAssembly::GT_S_I16x8_S },
16121
95.5k
  { WebAssembly::GT_S_I32, WebAssembly::GT_S_I32_S },
16122
95.5k
  { WebAssembly::GT_S_I32x4, WebAssembly::GT_S_I32x4_S },
16123
95.5k
  { WebAssembly::GT_S_I64, WebAssembly::GT_S_I64_S },
16124
95.5k
  { WebAssembly::GT_S_I64x2, WebAssembly::GT_S_I64x2_S },
16125
95.5k
  { WebAssembly::GT_S_I8x16, WebAssembly::GT_S_I8x16_S },
16126
95.5k
  { WebAssembly::GT_U_I16x8, WebAssembly::GT_U_I16x8_S },
16127
95.5k
  { WebAssembly::GT_U_I32, WebAssembly::GT_U_I32_S },
16128
95.5k
  { WebAssembly::GT_U_I32x4, WebAssembly::GT_U_I32x4_S },
16129
95.5k
  { WebAssembly::GT_U_I64, WebAssembly::GT_U_I64_S },
16130
95.5k
  { WebAssembly::GT_U_I8x16, WebAssembly::GT_U_I8x16_S },
16131
95.5k
  { WebAssembly::I32_EXTEND16_S_I32, WebAssembly::I32_EXTEND16_S_I32_S },
16132
95.5k
  { WebAssembly::I32_EXTEND8_S_I32, WebAssembly::I32_EXTEND8_S_I32_S },
16133
95.5k
  { WebAssembly::I32_REINTERPRET_F32, WebAssembly::I32_REINTERPRET_F32_S },
16134
95.5k
  { WebAssembly::I32_TRUNC_S_F32, WebAssembly::I32_TRUNC_S_F32_S },
16135
95.5k
  { WebAssembly::I32_TRUNC_S_F64, WebAssembly::I32_TRUNC_S_F64_S },
16136
95.5k
  { WebAssembly::I32_TRUNC_S_SAT_F32, WebAssembly::I32_TRUNC_S_SAT_F32_S },
16137
95.5k
  { WebAssembly::I32_TRUNC_S_SAT_F64, WebAssembly::I32_TRUNC_S_SAT_F64_S },
16138
95.5k
  { WebAssembly::I32_TRUNC_U_F32, WebAssembly::I32_TRUNC_U_F32_S },
16139
95.5k
  { WebAssembly::I32_TRUNC_U_F64, WebAssembly::I32_TRUNC_U_F64_S },
16140
95.5k
  { WebAssembly::I32_TRUNC_U_SAT_F32, WebAssembly::I32_TRUNC_U_SAT_F32_S },
16141
95.5k
  { WebAssembly::I32_TRUNC_U_SAT_F64, WebAssembly::I32_TRUNC_U_SAT_F64_S },
16142
95.5k
  { WebAssembly::I32_WRAP_I64, WebAssembly::I32_WRAP_I64_S },
16143
95.5k
  { WebAssembly::I64_EXTEND16_S_I64, WebAssembly::I64_EXTEND16_S_I64_S },
16144
95.5k
  { WebAssembly::I64_EXTEND32_S_I64, WebAssembly::I64_EXTEND32_S_I64_S },
16145
95.5k
  { WebAssembly::I64_EXTEND8_S_I64, WebAssembly::I64_EXTEND8_S_I64_S },
16146
95.5k
  { WebAssembly::I64_EXTEND_S_I32, WebAssembly::I64_EXTEND_S_I32_S },
16147
95.5k
  { WebAssembly::I64_EXTEND_U_I32, WebAssembly::I64_EXTEND_U_I32_S },
16148
95.5k
  { WebAssembly::I64_REINTERPRET_F64, WebAssembly::I64_REINTERPRET_F64_S },
16149
95.5k
  { WebAssembly::I64_TRUNC_S_F32, WebAssembly::I64_TRUNC_S_F32_S },
16150
95.5k
  { WebAssembly::I64_TRUNC_S_F64, WebAssembly::I64_TRUNC_S_F64_S },
16151
95.5k
  { WebAssembly::I64_TRUNC_S_SAT_F32, WebAssembly::I64_TRUNC_S_SAT_F32_S },
16152
95.5k
  { WebAssembly::I64_TRUNC_S_SAT_F64, WebAssembly::I64_TRUNC_S_SAT_F64_S },
16153
95.5k
  { WebAssembly::I64_TRUNC_U_F32, WebAssembly::I64_TRUNC_U_F32_S },
16154
95.5k
  { WebAssembly::I64_TRUNC_U_F64, WebAssembly::I64_TRUNC_U_F64_S },
16155
95.5k
  { WebAssembly::I64_TRUNC_U_SAT_F32, WebAssembly::I64_TRUNC_U_SAT_F32_S },
16156
95.5k
  { WebAssembly::I64_TRUNC_U_SAT_F64, WebAssembly::I64_TRUNC_U_SAT_F64_S },
16157
95.5k
  { WebAssembly::IF, WebAssembly::IF_S },
16158
95.5k
  { WebAssembly::LANESELECT_I16x8, WebAssembly::LANESELECT_I16x8_S },
16159
95.5k
  { WebAssembly::LANESELECT_I32x4, WebAssembly::LANESELECT_I32x4_S },
16160
95.5k
  { WebAssembly::LANESELECT_I64x2, WebAssembly::LANESELECT_I64x2_S },
16161
95.5k
  { WebAssembly::LANESELECT_I8x16, WebAssembly::LANESELECT_I8x16_S },
16162
95.5k
  { WebAssembly::LE_F32, WebAssembly::LE_F32_S },
16163
95.5k
  { WebAssembly::LE_F32x4, WebAssembly::LE_F32x4_S },
16164
95.5k
  { WebAssembly::LE_F64, WebAssembly::LE_F64_S },
16165
95.5k
  { WebAssembly::LE_F64x2, WebAssembly::LE_F64x2_S },
16166
95.5k
  { WebAssembly::LE_S_I16x8, WebAssembly::LE_S_I16x8_S },
16167
95.5k
  { WebAssembly::LE_S_I32, WebAssembly::LE_S_I32_S },
16168
95.5k
  { WebAssembly::LE_S_I32x4, WebAssembly::LE_S_I32x4_S },
16169
95.5k
  { WebAssembly::LE_S_I64, WebAssembly::LE_S_I64_S },
16170
95.5k
  { WebAssembly::LE_S_I64x2, WebAssembly::LE_S_I64x2_S },
16171
95.5k
  { WebAssembly::LE_S_I8x16, WebAssembly::LE_S_I8x16_S },
16172
95.5k
  { WebAssembly::LE_U_I16x8, WebAssembly::LE_U_I16x8_S },
16173
95.5k
  { WebAssembly::LE_U_I32, WebAssembly::LE_U_I32_S },
16174
95.5k
  { WebAssembly::LE_U_I32x4, WebAssembly::LE_U_I32x4_S },
16175
95.5k
  { WebAssembly::LE_U_I64, WebAssembly::LE_U_I64_S },
16176
95.5k
  { WebAssembly::LE_U_I8x16, WebAssembly::LE_U_I8x16_S },
16177
95.5k
  { WebAssembly::LOAD16_SPLAT_A32, WebAssembly::LOAD16_SPLAT_A32_S },
16178
95.5k
  { WebAssembly::LOAD16_SPLAT_A64, WebAssembly::LOAD16_SPLAT_A64_S },
16179
95.5k
  { WebAssembly::LOAD16_S_I32_A32, WebAssembly::LOAD16_S_I32_A32_S },
16180
95.5k
  { WebAssembly::LOAD16_S_I32_A64, WebAssembly::LOAD16_S_I32_A64_S },
16181
95.5k
  { WebAssembly::LOAD16_S_I64_A32, WebAssembly::LOAD16_S_I64_A32_S },
16182
95.5k
  { WebAssembly::LOAD16_S_I64_A64, WebAssembly::LOAD16_S_I64_A64_S },
16183
95.5k
  { WebAssembly::LOAD16_U_I32_A32, WebAssembly::LOAD16_U_I32_A32_S },
16184
95.5k
  { WebAssembly::LOAD16_U_I32_A64, WebAssembly::LOAD16_U_I32_A64_S },
16185
95.5k
  { WebAssembly::LOAD16_U_I64_A32, WebAssembly::LOAD16_U_I64_A32_S },
16186
95.5k
  { WebAssembly::LOAD16_U_I64_A64, WebAssembly::LOAD16_U_I64_A64_S },
16187
95.5k
  { WebAssembly::LOAD32_SPLAT_A32, WebAssembly::LOAD32_SPLAT_A32_S },
16188
95.5k
  { WebAssembly::LOAD32_SPLAT_A64, WebAssembly::LOAD32_SPLAT_A64_S },
16189
95.5k
  { WebAssembly::LOAD32_S_I64_A32, WebAssembly::LOAD32_S_I64_A32_S },
16190
95.5k
  { WebAssembly::LOAD32_S_I64_A64, WebAssembly::LOAD32_S_I64_A64_S },
16191
95.5k
  { WebAssembly::LOAD32_U_I64_A32, WebAssembly::LOAD32_U_I64_A32_S },
16192
95.5k
  { WebAssembly::LOAD32_U_I64_A64, WebAssembly::LOAD32_U_I64_A64_S },
16193
95.5k
  { WebAssembly::LOAD64_SPLAT_A32, WebAssembly::LOAD64_SPLAT_A32_S },
16194
95.5k
  { WebAssembly::LOAD64_SPLAT_A64, WebAssembly::LOAD64_SPLAT_A64_S },
16195
95.5k
  { WebAssembly::LOAD8_SPLAT_A32, WebAssembly::LOAD8_SPLAT_A32_S },
16196
95.5k
  { WebAssembly::LOAD8_SPLAT_A64, WebAssembly::LOAD8_SPLAT_A64_S },
16197
95.5k
  { WebAssembly::LOAD8_S_I32_A32, WebAssembly::LOAD8_S_I32_A32_S },
16198
95.5k
  { WebAssembly::LOAD8_S_I32_A64, WebAssembly::LOAD8_S_I32_A64_S },
16199
95.5k
  { WebAssembly::LOAD8_S_I64_A32, WebAssembly::LOAD8_S_I64_A32_S },
16200
95.5k
  { WebAssembly::LOAD8_S_I64_A64, WebAssembly::LOAD8_S_I64_A64_S },
16201
95.5k
  { WebAssembly::LOAD8_U_I32_A32, WebAssembly::LOAD8_U_I32_A32_S },
16202
95.5k
  { WebAssembly::LOAD8_U_I32_A64, WebAssembly::LOAD8_U_I32_A64_S },
16203
95.5k
  { WebAssembly::LOAD8_U_I64_A32, WebAssembly::LOAD8_U_I64_A32_S },
16204
95.5k
  { WebAssembly::LOAD8_U_I64_A64, WebAssembly::LOAD8_U_I64_A64_S },
16205
95.5k
  { WebAssembly::LOAD_EXTEND_S_I16x8_A32, WebAssembly::LOAD_EXTEND_S_I16x8_A32_S },
16206
95.5k
  { WebAssembly::LOAD_EXTEND_S_I16x8_A64, WebAssembly::LOAD_EXTEND_S_I16x8_A64_S },
16207
95.5k
  { WebAssembly::LOAD_EXTEND_S_I32x4_A32, WebAssembly::LOAD_EXTEND_S_I32x4_A32_S },
16208
95.5k
  { WebAssembly::LOAD_EXTEND_S_I32x4_A64, WebAssembly::LOAD_EXTEND_S_I32x4_A64_S },
16209
95.5k
  { WebAssembly::LOAD_EXTEND_S_I64x2_A32, WebAssembly::LOAD_EXTEND_S_I64x2_A32_S },
16210
95.5k
  { WebAssembly::LOAD_EXTEND_S_I64x2_A64, WebAssembly::LOAD_EXTEND_S_I64x2_A64_S },
16211
95.5k
  { WebAssembly::LOAD_EXTEND_U_I16x8_A32, WebAssembly::LOAD_EXTEND_U_I16x8_A32_S },
16212
95.5k
  { WebAssembly::LOAD_EXTEND_U_I16x8_A64, WebAssembly::LOAD_EXTEND_U_I16x8_A64_S },
16213
95.5k
  { WebAssembly::LOAD_EXTEND_U_I32x4_A32, WebAssembly::LOAD_EXTEND_U_I32x4_A32_S },
16214
95.5k
  { WebAssembly::LOAD_EXTEND_U_I32x4_A64, WebAssembly::LOAD_EXTEND_U_I32x4_A64_S },
16215
95.5k
  { WebAssembly::LOAD_EXTEND_U_I64x2_A32, WebAssembly::LOAD_EXTEND_U_I64x2_A32_S },
16216
95.5k
  { WebAssembly::LOAD_EXTEND_U_I64x2_A64, WebAssembly::LOAD_EXTEND_U_I64x2_A64_S },
16217
95.5k
  { WebAssembly::LOAD_F32_A32, WebAssembly::LOAD_F32_A32_S },
16218
95.5k
  { WebAssembly::LOAD_F32_A64, WebAssembly::LOAD_F32_A64_S },
16219
95.5k
  { WebAssembly::LOAD_F64_A32, WebAssembly::LOAD_F64_A32_S },
16220
95.5k
  { WebAssembly::LOAD_F64_A64, WebAssembly::LOAD_F64_A64_S },
16221
95.5k
  { WebAssembly::LOAD_I32_A32, WebAssembly::LOAD_I32_A32_S },
16222
95.5k
  { WebAssembly::LOAD_I32_A64, WebAssembly::LOAD_I32_A64_S },
16223
95.5k
  { WebAssembly::LOAD_I64_A32, WebAssembly::LOAD_I64_A32_S },
16224
95.5k
  { WebAssembly::LOAD_I64_A64, WebAssembly::LOAD_I64_A64_S },
16225
95.5k
  { WebAssembly::LOAD_LANE_I16x8_A32, WebAssembly::LOAD_LANE_I16x8_A32_S },
16226
95.5k
  { WebAssembly::LOAD_LANE_I16x8_A64, WebAssembly::LOAD_LANE_I16x8_A64_S },
16227
95.5k
  { WebAssembly::LOAD_LANE_I32x4_A32, WebAssembly::LOAD_LANE_I32x4_A32_S },
16228
95.5k
  { WebAssembly::LOAD_LANE_I32x4_A64, WebAssembly::LOAD_LANE_I32x4_A64_S },
16229
95.5k
  { WebAssembly::LOAD_LANE_I64x2_A32, WebAssembly::LOAD_LANE_I64x2_A32_S },
16230
95.5k
  { WebAssembly::LOAD_LANE_I64x2_A64, WebAssembly::LOAD_LANE_I64x2_A64_S },
16231
95.5k
  { WebAssembly::LOAD_LANE_I8x16_A32, WebAssembly::LOAD_LANE_I8x16_A32_S },
16232
95.5k
  { WebAssembly::LOAD_LANE_I8x16_A64, WebAssembly::LOAD_LANE_I8x16_A64_S },
16233
95.5k
  { WebAssembly::LOAD_V128_A32, WebAssembly::LOAD_V128_A32_S },
16234
95.5k
  { WebAssembly::LOAD_V128_A64, WebAssembly::LOAD_V128_A64_S },
16235
95.5k
  { WebAssembly::LOAD_ZERO_I32x4_A32, WebAssembly::LOAD_ZERO_I32x4_A32_S },
16236
95.5k
  { WebAssembly::LOAD_ZERO_I32x4_A64, WebAssembly::LOAD_ZERO_I32x4_A64_S },
16237
95.5k
  { WebAssembly::LOAD_ZERO_I64x2_A32, WebAssembly::LOAD_ZERO_I64x2_A32_S },
16238
95.5k
  { WebAssembly::LOAD_ZERO_I64x2_A64, WebAssembly::LOAD_ZERO_I64x2_A64_S },
16239
95.5k
  { WebAssembly::LOCAL_GET_EXTERNREF, WebAssembly::LOCAL_GET_EXTERNREF_S },
16240
95.5k
  { WebAssembly::LOCAL_GET_F32, WebAssembly::LOCAL_GET_F32_S },
16241
95.5k
  { WebAssembly::LOCAL_GET_F64, WebAssembly::LOCAL_GET_F64_S },
16242
95.5k
  { WebAssembly::LOCAL_GET_FUNCREF, WebAssembly::LOCAL_GET_FUNCREF_S },
16243
95.5k
  { WebAssembly::LOCAL_GET_I32, WebAssembly::LOCAL_GET_I32_S },
16244
95.5k
  { WebAssembly::LOCAL_GET_I64, WebAssembly::LOCAL_GET_I64_S },
16245
95.5k
  { WebAssembly::LOCAL_GET_V128, WebAssembly::LOCAL_GET_V128_S },
16246
95.5k
  { WebAssembly::LOCAL_SET_EXTERNREF, WebAssembly::LOCAL_SET_EXTERNREF_S },
16247
95.5k
  { WebAssembly::LOCAL_SET_F32, WebAssembly::LOCAL_SET_F32_S },
16248
95.5k
  { WebAssembly::LOCAL_SET_F64, WebAssembly::LOCAL_SET_F64_S },
16249
95.5k
  { WebAssembly::LOCAL_SET_FUNCREF, WebAssembly::LOCAL_SET_FUNCREF_S },
16250
95.5k
  { WebAssembly::LOCAL_SET_I32, WebAssembly::LOCAL_SET_I32_S },
16251
95.5k
  { WebAssembly::LOCAL_SET_I64, WebAssembly::LOCAL_SET_I64_S },
16252
95.5k
  { WebAssembly::LOCAL_SET_V128, WebAssembly::LOCAL_SET_V128_S },
16253
95.5k
  { WebAssembly::LOCAL_TEE_EXTERNREF, WebAssembly::LOCAL_TEE_EXTERNREF_S },
16254
95.5k
  { WebAssembly::LOCAL_TEE_F32, WebAssembly::LOCAL_TEE_F32_S },
16255
95.5k
  { WebAssembly::LOCAL_TEE_F64, WebAssembly::LOCAL_TEE_F64_S },
16256
95.5k
  { WebAssembly::LOCAL_TEE_FUNCREF, WebAssembly::LOCAL_TEE_FUNCREF_S },
16257
95.5k
  { WebAssembly::LOCAL_TEE_I32, WebAssembly::LOCAL_TEE_I32_S },
16258
95.5k
  { WebAssembly::LOCAL_TEE_I64, WebAssembly::LOCAL_TEE_I64_S },
16259
95.5k
  { WebAssembly::LOCAL_TEE_V128, WebAssembly::LOCAL_TEE_V128_S },
16260
95.5k
  { WebAssembly::LOOP, WebAssembly::LOOP_S },
16261
95.5k
  { WebAssembly::LT_F32, WebAssembly::LT_F32_S },
16262
95.5k
  { WebAssembly::LT_F32x4, WebAssembly::LT_F32x4_S },
16263
95.5k
  { WebAssembly::LT_F64, WebAssembly::LT_F64_S },
16264
95.5k
  { WebAssembly::LT_F64x2, WebAssembly::LT_F64x2_S },
16265
95.5k
  { WebAssembly::LT_S_I16x8, WebAssembly::LT_S_I16x8_S },
16266
95.5k
  { WebAssembly::LT_S_I32, WebAssembly::LT_S_I32_S },
16267
95.5k
  { WebAssembly::LT_S_I32x4, WebAssembly::LT_S_I32x4_S },
16268
95.5k
  { WebAssembly::LT_S_I64, WebAssembly::LT_S_I64_S },
16269
95.5k
  { WebAssembly::LT_S_I64x2, WebAssembly::LT_S_I64x2_S },
16270
95.5k
  { WebAssembly::LT_S_I8x16, WebAssembly::LT_S_I8x16_S },
16271
95.5k
  { WebAssembly::LT_U_I16x8, WebAssembly::LT_U_I16x8_S },
16272
95.5k
  { WebAssembly::LT_U_I32, WebAssembly::LT_U_I32_S },
16273
95.5k
  { WebAssembly::LT_U_I32x4, WebAssembly::LT_U_I32x4_S },
16274
95.5k
  { WebAssembly::LT_U_I64, WebAssembly::LT_U_I64_S },
16275
95.5k
  { WebAssembly::LT_U_I8x16, WebAssembly::LT_U_I8x16_S },
16276
95.5k
  { WebAssembly::MADD_F32x4, WebAssembly::MADD_F32x4_S },
16277
95.5k
  { WebAssembly::MADD_F64x2, WebAssembly::MADD_F64x2_S },
16278
95.5k
  { WebAssembly::MAX_F32, WebAssembly::MAX_F32_S },
16279
95.5k
  { WebAssembly::MAX_F32x4, WebAssembly::MAX_F32x4_S },
16280
95.5k
  { WebAssembly::MAX_F64, WebAssembly::MAX_F64_S },
16281
95.5k
  { WebAssembly::MAX_F64x2, WebAssembly::MAX_F64x2_S },
16282
95.5k
  { WebAssembly::MAX_S_I16x8, WebAssembly::MAX_S_I16x8_S },
16283
95.5k
  { WebAssembly::MAX_S_I32x4, WebAssembly::MAX_S_I32x4_S },
16284
95.5k
  { WebAssembly::MAX_S_I8x16, WebAssembly::MAX_S_I8x16_S },
16285
95.5k
  { WebAssembly::MAX_U_I16x8, WebAssembly::MAX_U_I16x8_S },
16286
95.5k
  { WebAssembly::MAX_U_I32x4, WebAssembly::MAX_U_I32x4_S },
16287
95.5k
  { WebAssembly::MAX_U_I8x16, WebAssembly::MAX_U_I8x16_S },
16288
95.5k
  { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32, WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S },
16289
95.5k
  { WebAssembly::MEMORY_ATOMIC_NOTIFY_A64, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S },
16290
95.5k
  { WebAssembly::MEMORY_ATOMIC_WAIT32_A32, WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S },
16291
95.5k
  { WebAssembly::MEMORY_ATOMIC_WAIT32_A64, WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S },
16292
95.5k
  { WebAssembly::MEMORY_ATOMIC_WAIT64_A32, WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S },
16293
95.5k
  { WebAssembly::MEMORY_ATOMIC_WAIT64_A64, WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S },
16294
95.5k
  { WebAssembly::MIN_F32, WebAssembly::MIN_F32_S },
16295
95.5k
  { WebAssembly::MIN_F32x4, WebAssembly::MIN_F32x4_S },
16296
95.5k
  { WebAssembly::MIN_F64, WebAssembly::MIN_F64_S },
16297
95.5k
  { WebAssembly::MIN_F64x2, WebAssembly::MIN_F64x2_S },
16298
95.5k
  { WebAssembly::MIN_S_I16x8, WebAssembly::MIN_S_I16x8_S },
16299
95.5k
  { WebAssembly::MIN_S_I32x4, WebAssembly::MIN_S_I32x4_S },
16300
95.5k
  { WebAssembly::MIN_S_I8x16, WebAssembly::MIN_S_I8x16_S },
16301
95.5k
  { WebAssembly::MIN_U_I16x8, WebAssembly::MIN_U_I16x8_S },
16302
95.5k
  { WebAssembly::MIN_U_I32x4, WebAssembly::MIN_U_I32x4_S },
16303
95.5k
  { WebAssembly::MIN_U_I8x16, WebAssembly::MIN_U_I8x16_S },
16304
95.5k
  { WebAssembly::MUL_F32, WebAssembly::MUL_F32_S },
16305
95.5k
  { WebAssembly::MUL_F32x4, WebAssembly::MUL_F32x4_S },
16306
95.5k
  { WebAssembly::MUL_F64, WebAssembly::MUL_F64_S },
16307
95.5k
  { WebAssembly::MUL_F64x2, WebAssembly::MUL_F64x2_S },
16308
95.5k
  { WebAssembly::MUL_I16x8, WebAssembly::MUL_I16x8_S },
16309
95.5k
  { WebAssembly::MUL_I32, WebAssembly::MUL_I32_S },
16310
95.5k
  { WebAssembly::MUL_I32x4, WebAssembly::MUL_I32x4_S },
16311
95.5k
  { WebAssembly::MUL_I64, WebAssembly::MUL_I64_S },
16312
95.5k
  { WebAssembly::MUL_I64x2, WebAssembly::MUL_I64x2_S },
16313
95.5k
  { WebAssembly::NARROW_S_I16x8, WebAssembly::NARROW_S_I16x8_S },
16314
95.5k
  { WebAssembly::NARROW_S_I8x16, WebAssembly::NARROW_S_I8x16_S },
16315
95.5k
  { WebAssembly::NARROW_U_I16x8, WebAssembly::NARROW_U_I16x8_S },
16316
95.5k
  { WebAssembly::NARROW_U_I8x16, WebAssembly::NARROW_U_I8x16_S },
16317
95.5k
  { WebAssembly::NEAREST_F32, WebAssembly::NEAREST_F32_S },
16318
95.5k
  { WebAssembly::NEAREST_F32x4, WebAssembly::NEAREST_F32x4_S },
16319
95.5k
  { WebAssembly::NEAREST_F64, WebAssembly::NEAREST_F64_S },
16320
95.5k
  { WebAssembly::NEAREST_F64x2, WebAssembly::NEAREST_F64x2_S },
16321
95.5k
  { WebAssembly::NEG_F32, WebAssembly::NEG_F32_S },
16322
95.5k
  { WebAssembly::NEG_F32x4, WebAssembly::NEG_F32x4_S },
16323
95.5k
  { WebAssembly::NEG_F64, WebAssembly::NEG_F64_S },
16324
95.5k
  { WebAssembly::NEG_F64x2, WebAssembly::NEG_F64x2_S },
16325
95.5k
  { WebAssembly::NEG_I16x8, WebAssembly::NEG_I16x8_S },
16326
95.5k
  { WebAssembly::NEG_I32x4, WebAssembly::NEG_I32x4_S },
16327
95.5k
  { WebAssembly::NEG_I64x2, WebAssembly::NEG_I64x2_S },
16328
95.5k
  { WebAssembly::NEG_I8x16, WebAssembly::NEG_I8x16_S },
16329
95.5k
  { WebAssembly::NE_F32, WebAssembly::NE_F32_S },
16330
95.5k
  { WebAssembly::NE_F32x4, WebAssembly::NE_F32x4_S },
16331
95.5k
  { WebAssembly::NE_F64, WebAssembly::NE_F64_S },
16332
95.5k
  { WebAssembly::NE_F64x2, WebAssembly::NE_F64x2_S },
16333
95.5k
  { WebAssembly::NE_I16x8, WebAssembly::NE_I16x8_S },
16334
95.5k
  { WebAssembly::NE_I32, WebAssembly::NE_I32_S },
16335
95.5k
  { WebAssembly::NE_I32x4, WebAssembly::NE_I32x4_S },
16336
95.5k
  { WebAssembly::NE_I64, WebAssembly::NE_I64_S },
16337
95.5k
  { WebAssembly::NE_I64x2, WebAssembly::NE_I64x2_S },
16338
95.5k
  { WebAssembly::NE_I8x16, WebAssembly::NE_I8x16_S },
16339
95.5k
  { WebAssembly::NMADD_F32x4, WebAssembly::NMADD_F32x4_S },
16340
95.5k
  { WebAssembly::NMADD_F64x2, WebAssembly::NMADD_F64x2_S },
16341
95.5k
  { WebAssembly::NOP, WebAssembly::NOP_S },
16342
95.5k
  { WebAssembly::NOT, WebAssembly::NOT_S },
16343
95.5k
  { WebAssembly::OR, WebAssembly::OR_S },
16344
95.5k
  { WebAssembly::OR_I32, WebAssembly::OR_I32_S },
16345
95.5k
  { WebAssembly::OR_I64, WebAssembly::OR_I64_S },
16346
95.5k
  { WebAssembly::PMAX_F32x4, WebAssembly::PMAX_F32x4_S },
16347
95.5k
  { WebAssembly::PMAX_F64x2, WebAssembly::PMAX_F64x2_S },
16348
95.5k
  { WebAssembly::PMIN_F32x4, WebAssembly::PMIN_F32x4_S },
16349
95.5k
  { WebAssembly::PMIN_F64x2, WebAssembly::PMIN_F64x2_S },
16350
95.5k
  { WebAssembly::POPCNT_I32, WebAssembly::POPCNT_I32_S },
16351
95.5k
  { WebAssembly::POPCNT_I64, WebAssembly::POPCNT_I64_S },
16352
95.5k
  { WebAssembly::POPCNT_I8x16, WebAssembly::POPCNT_I8x16_S },
16353
95.5k
  { WebAssembly::Q15MULR_SAT_S_I16x8, WebAssembly::Q15MULR_SAT_S_I16x8_S },
16354
95.5k
  { WebAssembly::REF_IS_NULL_EXTERNREF, WebAssembly::REF_IS_NULL_EXTERNREF_S },
16355
95.5k
  { WebAssembly::REF_IS_NULL_FUNCREF, WebAssembly::REF_IS_NULL_FUNCREF_S },
16356
95.5k
  { WebAssembly::REF_NULL_EXTERNREF, WebAssembly::REF_NULL_EXTERNREF_S },
16357
95.5k
  { WebAssembly::REF_NULL_FUNCREF, WebAssembly::REF_NULL_FUNCREF_S },
16358
95.5k
  { WebAssembly::RELAXED_DOT, WebAssembly::RELAXED_DOT_S },
16359
95.5k
  { WebAssembly::RELAXED_DOT_ADD, WebAssembly::RELAXED_DOT_ADD_S },
16360
95.5k
  { WebAssembly::RELAXED_DOT_BFLOAT, WebAssembly::RELAXED_DOT_BFLOAT_S },
16361
95.5k
  { WebAssembly::RELAXED_Q15MULR_S_I16x8, WebAssembly::RELAXED_Q15MULR_S_I16x8_S },
16362
95.5k
  { WebAssembly::RELAXED_SWIZZLE, WebAssembly::RELAXED_SWIZZLE_S },
16363
95.5k
  { WebAssembly::REM_S_I32, WebAssembly::REM_S_I32_S },
16364
95.5k
  { WebAssembly::REM_S_I64, WebAssembly::REM_S_I64_S },
16365
95.5k
  { WebAssembly::REM_U_I32, WebAssembly::REM_U_I32_S },
16366
95.5k
  { WebAssembly::REM_U_I64, WebAssembly::REM_U_I64_S },
16367
95.5k
  { WebAssembly::REPLACE_LANE_F32x4, WebAssembly::REPLACE_LANE_F32x4_S },
16368
95.5k
  { WebAssembly::REPLACE_LANE_F64x2, WebAssembly::REPLACE_LANE_F64x2_S },
16369
95.5k
  { WebAssembly::REPLACE_LANE_I16x8, WebAssembly::REPLACE_LANE_I16x8_S },
16370
95.5k
  { WebAssembly::REPLACE_LANE_I32x4, WebAssembly::REPLACE_LANE_I32x4_S },
16371
95.5k
  { WebAssembly::REPLACE_LANE_I64x2, WebAssembly::REPLACE_LANE_I64x2_S },
16372
95.5k
  { WebAssembly::REPLACE_LANE_I8x16, WebAssembly::REPLACE_LANE_I8x16_S },
16373
95.5k
  { WebAssembly::RETHROW, WebAssembly::RETHROW_S },
16374
95.5k
  { WebAssembly::RETURN, WebAssembly::RETURN_S },
16375
95.5k
  { WebAssembly::RET_CALL, WebAssembly::RET_CALL_S },
16376
95.5k
  { WebAssembly::RET_CALL_INDIRECT, WebAssembly::RET_CALL_INDIRECT_S },
16377
95.5k
  { WebAssembly::ROTL_I32, WebAssembly::ROTL_I32_S },
16378
95.5k
  { WebAssembly::ROTL_I64, WebAssembly::ROTL_I64_S },
16379
95.5k
  { WebAssembly::ROTR_I32, WebAssembly::ROTR_I32_S },
16380
95.5k
  { WebAssembly::ROTR_I64, WebAssembly::ROTR_I64_S },
16381
95.5k
  { WebAssembly::SELECT_EXTERNREF, WebAssembly::SELECT_EXTERNREF_S },
16382
95.5k
  { WebAssembly::SELECT_F32, WebAssembly::SELECT_F32_S },
16383
95.5k
  { WebAssembly::SELECT_F64, WebAssembly::SELECT_F64_S },
16384
95.5k
  { WebAssembly::SELECT_FUNCREF, WebAssembly::SELECT_FUNCREF_S },
16385
95.5k
  { WebAssembly::SELECT_I32, WebAssembly::SELECT_I32_S },
16386
95.5k
  { WebAssembly::SELECT_I64, WebAssembly::SELECT_I64_S },
16387
95.5k
  { WebAssembly::SELECT_V128, WebAssembly::SELECT_V128_S },
16388
95.5k
  { WebAssembly::SHL_I16x8, WebAssembly::SHL_I16x8_S },
16389
95.5k
  { WebAssembly::SHL_I32, WebAssembly::SHL_I32_S },
16390
95.5k
  { WebAssembly::SHL_I32x4, WebAssembly::SHL_I32x4_S },
16391
95.5k
  { WebAssembly::SHL_I64, WebAssembly::SHL_I64_S },
16392
95.5k
  { WebAssembly::SHL_I64x2, WebAssembly::SHL_I64x2_S },
16393
95.5k
  { WebAssembly::SHL_I8x16, WebAssembly::SHL_I8x16_S },
16394
95.5k
  { WebAssembly::SHR_S_I16x8, WebAssembly::SHR_S_I16x8_S },
16395
95.5k
  { WebAssembly::SHR_S_I32, WebAssembly::SHR_S_I32_S },
16396
95.5k
  { WebAssembly::SHR_S_I32x4, WebAssembly::SHR_S_I32x4_S },
16397
95.5k
  { WebAssembly::SHR_S_I64, WebAssembly::SHR_S_I64_S },
16398
95.5k
  { WebAssembly::SHR_S_I64x2, WebAssembly::SHR_S_I64x2_S },
16399
95.5k
  { WebAssembly::SHR_S_I8x16, WebAssembly::SHR_S_I8x16_S },
16400
95.5k
  { WebAssembly::SHR_U_I16x8, WebAssembly::SHR_U_I16x8_S },
16401
95.5k
  { WebAssembly::SHR_U_I32, WebAssembly::SHR_U_I32_S },
16402
95.5k
  { WebAssembly::SHR_U_I32x4, WebAssembly::SHR_U_I32x4_S },
16403
95.5k
  { WebAssembly::SHR_U_I64, WebAssembly::SHR_U_I64_S },
16404
95.5k
  { WebAssembly::SHR_U_I64x2, WebAssembly::SHR_U_I64x2_S },
16405
95.5k
  { WebAssembly::SHR_U_I8x16, WebAssembly::SHR_U_I8x16_S },
16406
95.5k
  { WebAssembly::SHUFFLE, WebAssembly::SHUFFLE_S },
16407
95.5k
  { WebAssembly::SIMD_RELAXED_FMAX_F32x4, WebAssembly::SIMD_RELAXED_FMAX_F32x4_S },
16408
95.5k
  { WebAssembly::SIMD_RELAXED_FMAX_F64x2, WebAssembly::SIMD_RELAXED_FMAX_F64x2_S },
16409
95.5k
  { WebAssembly::SIMD_RELAXED_FMIN_F32x4, WebAssembly::SIMD_RELAXED_FMIN_F32x4_S },
16410
95.5k
  { WebAssembly::SIMD_RELAXED_FMIN_F64x2, WebAssembly::SIMD_RELAXED_FMIN_F64x2_S },
16411
95.5k
  { WebAssembly::SPLAT_F32x4, WebAssembly::SPLAT_F32x4_S },
16412
95.5k
  { WebAssembly::SPLAT_F64x2, WebAssembly::SPLAT_F64x2_S },
16413
95.5k
  { WebAssembly::SPLAT_I16x8, WebAssembly::SPLAT_I16x8_S },
16414
95.5k
  { WebAssembly::SPLAT_I32x4, WebAssembly::SPLAT_I32x4_S },
16415
95.5k
  { WebAssembly::SPLAT_I64x2, WebAssembly::SPLAT_I64x2_S },
16416
95.5k
  { WebAssembly::SPLAT_I8x16, WebAssembly::SPLAT_I8x16_S },
16417
95.5k
  { WebAssembly::SQRT_F32, WebAssembly::SQRT_F32_S },
16418
95.5k
  { WebAssembly::SQRT_F32x4, WebAssembly::SQRT_F32x4_S },
16419
95.5k
  { WebAssembly::SQRT_F64, WebAssembly::SQRT_F64_S },
16420
95.5k
  { WebAssembly::SQRT_F64x2, WebAssembly::SQRT_F64x2_S },
16421
95.5k
  { WebAssembly::STORE16_I32_A32, WebAssembly::STORE16_I32_A32_S },
16422
95.5k
  { WebAssembly::STORE16_I32_A64, WebAssembly::STORE16_I32_A64_S },
16423
95.5k
  { WebAssembly::STORE16_I64_A32, WebAssembly::STORE16_I64_A32_S },
16424
95.5k
  { WebAssembly::STORE16_I64_A64, WebAssembly::STORE16_I64_A64_S },
16425
95.5k
  { WebAssembly::STORE32_I64_A32, WebAssembly::STORE32_I64_A32_S },
16426
95.5k
  { WebAssembly::STORE32_I64_A64, WebAssembly::STORE32_I64_A64_S },
16427
95.5k
  { WebAssembly::STORE8_I32_A32, WebAssembly::STORE8_I32_A32_S },
16428
95.5k
  { WebAssembly::STORE8_I32_A64, WebAssembly::STORE8_I32_A64_S },
16429
95.5k
  { WebAssembly::STORE8_I64_A32, WebAssembly::STORE8_I64_A32_S },
16430
95.5k
  { WebAssembly::STORE8_I64_A64, WebAssembly::STORE8_I64_A64_S },
16431
95.5k
  { WebAssembly::STORE_F32_A32, WebAssembly::STORE_F32_A32_S },
16432
95.5k
  { WebAssembly::STORE_F32_A64, WebAssembly::STORE_F32_A64_S },
16433
95.5k
  { WebAssembly::STORE_F64_A32, WebAssembly::STORE_F64_A32_S },
16434
95.5k
  { WebAssembly::STORE_F64_A64, WebAssembly::STORE_F64_A64_S },
16435
95.5k
  { WebAssembly::STORE_I32_A32, WebAssembly::STORE_I32_A32_S },
16436
95.5k
  { WebAssembly::STORE_I32_A64, WebAssembly::STORE_I32_A64_S },
16437
95.5k
  { WebAssembly::STORE_I64_A32, WebAssembly::STORE_I64_A32_S },
16438
95.5k
  { WebAssembly::STORE_I64_A64, WebAssembly::STORE_I64_A64_S },
16439
95.5k
  { WebAssembly::STORE_LANE_I16x8_A32, WebAssembly::STORE_LANE_I16x8_A32_S },
16440
95.5k
  { WebAssembly::STORE_LANE_I16x8_A64, WebAssembly::STORE_LANE_I16x8_A64_S },
16441
95.5k
  { WebAssembly::STORE_LANE_I32x4_A32, WebAssembly::STORE_LANE_I32x4_A32_S },
16442
95.5k
  { WebAssembly::STORE_LANE_I32x4_A64, WebAssembly::STORE_LANE_I32x4_A64_S },
16443
95.5k
  { WebAssembly::STORE_LANE_I64x2_A32, WebAssembly::STORE_LANE_I64x2_A32_S },
16444
95.5k
  { WebAssembly::STORE_LANE_I64x2_A64, WebAssembly::STORE_LANE_I64x2_A64_S },
16445
95.5k
  { WebAssembly::STORE_LANE_I8x16_A32, WebAssembly::STORE_LANE_I8x16_A32_S },
16446
95.5k
  { WebAssembly::STORE_LANE_I8x16_A64, WebAssembly::STORE_LANE_I8x16_A64_S },
16447
95.5k
  { WebAssembly::STORE_V128_A32, WebAssembly::STORE_V128_A32_S },
16448
95.5k
  { WebAssembly::STORE_V128_A64, WebAssembly::STORE_V128_A64_S },
16449
95.5k
  { WebAssembly::SUB_F32, WebAssembly::SUB_F32_S },
16450
95.5k
  { WebAssembly::SUB_F32x4, WebAssembly::SUB_F32x4_S },
16451
95.5k
  { WebAssembly::SUB_F64, WebAssembly::SUB_F64_S },
16452
95.5k
  { WebAssembly::SUB_F64x2, WebAssembly::SUB_F64x2_S },
16453
95.5k
  { WebAssembly::SUB_I16x8, WebAssembly::SUB_I16x8_S },
16454
95.5k
  { WebAssembly::SUB_I32, WebAssembly::SUB_I32_S },
16455
95.5k
  { WebAssembly::SUB_I32x4, WebAssembly::SUB_I32x4_S },
16456
95.5k
  { WebAssembly::SUB_I64, WebAssembly::SUB_I64_S },
16457
95.5k
  { WebAssembly::SUB_I64x2, WebAssembly::SUB_I64x2_S },
16458
95.5k
  { WebAssembly::SUB_I8x16, WebAssembly::SUB_I8x16_S },
16459
95.5k
  { WebAssembly::SUB_SAT_S_I16x8, WebAssembly::SUB_SAT_S_I16x8_S },
16460
95.5k
  { WebAssembly::SUB_SAT_S_I8x16, WebAssembly::SUB_SAT_S_I8x16_S },
16461
95.5k
  { WebAssembly::SUB_SAT_U_I16x8, WebAssembly::SUB_SAT_U_I16x8_S },
16462
95.5k
  { WebAssembly::SUB_SAT_U_I8x16, WebAssembly::SUB_SAT_U_I8x16_S },
16463
95.5k
  { WebAssembly::SWIZZLE, WebAssembly::SWIZZLE_S },
16464
95.5k
  { WebAssembly::TABLE_COPY, WebAssembly::TABLE_COPY_S },
16465
95.5k
  { WebAssembly::TABLE_FILL_EXTERNREF, WebAssembly::TABLE_FILL_EXTERNREF_S },
16466
95.5k
  { WebAssembly::TABLE_FILL_FUNCREF, WebAssembly::TABLE_FILL_FUNCREF_S },
16467
95.5k
  { WebAssembly::TABLE_GET_EXTERNREF, WebAssembly::TABLE_GET_EXTERNREF_S },
16468
95.5k
  { WebAssembly::TABLE_GET_FUNCREF, WebAssembly::TABLE_GET_FUNCREF_S },
16469
95.5k
  { WebAssembly::TABLE_GROW_EXTERNREF, WebAssembly::TABLE_GROW_EXTERNREF_S },
16470
95.5k
  { WebAssembly::TABLE_GROW_FUNCREF, WebAssembly::TABLE_GROW_FUNCREF_S },
16471
95.5k
  { WebAssembly::TABLE_SET_EXTERNREF, WebAssembly::TABLE_SET_EXTERNREF_S },
16472
95.5k
  { WebAssembly::TABLE_SET_FUNCREF, WebAssembly::TABLE_SET_FUNCREF_S },
16473
95.5k
  { WebAssembly::TABLE_SIZE, WebAssembly::TABLE_SIZE_S },
16474
95.5k
  { WebAssembly::TEE_EXTERNREF, WebAssembly::TEE_EXTERNREF_S },
16475
95.5k
  { WebAssembly::TEE_F32, WebAssembly::TEE_F32_S },
16476
95.5k
  { WebAssembly::TEE_F64, WebAssembly::TEE_F64_S },
16477
95.5k
  { WebAssembly::TEE_FUNCREF, WebAssembly::TEE_FUNCREF_S },
16478
95.5k
  { WebAssembly::TEE_I32, WebAssembly::TEE_I32_S },
16479
95.5k
  { WebAssembly::TEE_I64, WebAssembly::TEE_I64_S },
16480
95.5k
  { WebAssembly::TEE_V128, WebAssembly::TEE_V128_S },
16481
95.5k
  { WebAssembly::THROW, WebAssembly::THROW_S },
16482
95.5k
  { WebAssembly::TRUNC_F32, WebAssembly::TRUNC_F32_S },
16483
95.5k
  { WebAssembly::TRUNC_F32x4, WebAssembly::TRUNC_F32x4_S },
16484
95.5k
  { WebAssembly::TRUNC_F64, WebAssembly::TRUNC_F64_S },
16485
95.5k
  { WebAssembly::TRUNC_F64x2, WebAssembly::TRUNC_F64x2_S },
16486
95.5k
  { WebAssembly::TRY, WebAssembly::TRY_S },
16487
95.5k
  { WebAssembly::UNREACHABLE, WebAssembly::UNREACHABLE_S },
16488
95.5k
  { WebAssembly::XOR, WebAssembly::XOR_S },
16489
95.5k
  { WebAssembly::XOR_I32, WebAssembly::XOR_I32_S },
16490
95.5k
  { WebAssembly::XOR_I64, WebAssembly::XOR_I64_S },
16491
95.5k
  { WebAssembly::anonymous_7277MEMORY_GROW_A32, WebAssembly::anonymous_7277MEMORY_GROW_A32_S },
16492
95.5k
  { WebAssembly::anonymous_7277MEMORY_SIZE_A32, WebAssembly::anonymous_7277MEMORY_SIZE_A32_S },
16493
95.5k
  { WebAssembly::anonymous_7278MEMORY_GROW_A64, WebAssembly::anonymous_7278MEMORY_GROW_A64_S },
16494
95.5k
  { WebAssembly::anonymous_7278MEMORY_SIZE_A64, WebAssembly::anonymous_7278MEMORY_SIZE_A64_S },
16495
95.5k
  { WebAssembly::anonymous_7959DATA_DROP, WebAssembly::anonymous_7959DATA_DROP_S },
16496
95.5k
  { WebAssembly::anonymous_7959MEMORY_COPY_A32, WebAssembly::anonymous_7959MEMORY_COPY_A32_S },
16497
95.5k
  { WebAssembly::anonymous_7959MEMORY_FILL_A32, WebAssembly::anonymous_7959MEMORY_FILL_A32_S },
16498
95.5k
  { WebAssembly::anonymous_7959MEMORY_INIT_A32, WebAssembly::anonymous_7959MEMORY_INIT_A32_S },
16499
95.5k
  { WebAssembly::anonymous_7960DATA_DROP, WebAssembly::anonymous_7960DATA_DROP_S },
16500
95.5k
  { WebAssembly::anonymous_7960MEMORY_COPY_A64, WebAssembly::anonymous_7960MEMORY_COPY_A64_S },
16501
95.5k
  { WebAssembly::anonymous_7960MEMORY_FILL_A64, WebAssembly::anonymous_7960MEMORY_FILL_A64_S },
16502
95.5k
  { WebAssembly::anonymous_7960MEMORY_INIT_A64, WebAssembly::anonymous_7960MEMORY_INIT_A64_S },
16503
95.5k
  { WebAssembly::convert_low_s_F64x2, WebAssembly::convert_low_s_F64x2_S },
16504
95.5k
  { WebAssembly::convert_low_u_F64x2, WebAssembly::convert_low_u_F64x2_S },
16505
95.5k
  { WebAssembly::demote_zero_F32x4, WebAssembly::demote_zero_F32x4_S },
16506
95.5k
  { WebAssembly::extend_high_s_I16x8, WebAssembly::extend_high_s_I16x8_S },
16507
95.5k
  { WebAssembly::extend_high_s_I32x4, WebAssembly::extend_high_s_I32x4_S },
16508
95.5k
  { WebAssembly::extend_high_s_I64x2, WebAssembly::extend_high_s_I64x2_S },
16509
95.5k
  { WebAssembly::extend_high_u_I16x8, WebAssembly::extend_high_u_I16x8_S },
16510
95.5k
  { WebAssembly::extend_high_u_I32x4, WebAssembly::extend_high_u_I32x4_S },
16511
95.5k
  { WebAssembly::extend_high_u_I64x2, WebAssembly::extend_high_u_I64x2_S },
16512
95.5k
  { WebAssembly::extend_low_s_I16x8, WebAssembly::extend_low_s_I16x8_S },
16513
95.5k
  { WebAssembly::extend_low_s_I32x4, WebAssembly::extend_low_s_I32x4_S },
16514
95.5k
  { WebAssembly::extend_low_s_I64x2, WebAssembly::extend_low_s_I64x2_S },
16515
95.5k
  { WebAssembly::extend_low_u_I16x8, WebAssembly::extend_low_u_I16x8_S },
16516
95.5k
  { WebAssembly::extend_low_u_I32x4, WebAssembly::extend_low_u_I32x4_S },
16517
95.5k
  { WebAssembly::extend_low_u_I64x2, WebAssembly::extend_low_u_I64x2_S },
16518
95.5k
  { WebAssembly::fp_to_sint_I32x4, WebAssembly::fp_to_sint_I32x4_S },
16519
95.5k
  { WebAssembly::fp_to_uint_I32x4, WebAssembly::fp_to_uint_I32x4_S },
16520
95.5k
  { WebAssembly::int_wasm_extadd_pairwise_signed_I16x8, WebAssembly::int_wasm_extadd_pairwise_signed_I16x8_S },
16521
95.5k
  { WebAssembly::int_wasm_extadd_pairwise_signed_I32x4, WebAssembly::int_wasm_extadd_pairwise_signed_I32x4_S },
16522
95.5k
  { WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8, WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8_S },
16523
95.5k
  { WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4, WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4_S },
16524
95.5k
  { WebAssembly::int_wasm_relaxed_trunc_signed_I32x4, WebAssembly::int_wasm_relaxed_trunc_signed_I32x4_S },
16525
95.5k
  { WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4, WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4_S },
16526
95.5k
  { WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4, WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4_S },
16527
95.5k
  { WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4, WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4_S },
16528
95.5k
  { WebAssembly::promote_low_F64x2, WebAssembly::promote_low_F64x2_S },
16529
95.5k
  { WebAssembly::sint_to_fp_F32x4, WebAssembly::sint_to_fp_F32x4_S },
16530
95.5k
  { WebAssembly::trunc_sat_zero_s_I32x4, WebAssembly::trunc_sat_zero_s_I32x4_S },
16531
95.5k
  { WebAssembly::trunc_sat_zero_u_I32x4, WebAssembly::trunc_sat_zero_u_I32x4_S },
16532
95.5k
  { WebAssembly::uint_to_fp_F32x4, WebAssembly::uint_to_fp_F32x4_S },
16533
95.5k
}; // End of getStackOpcodeTable
16534
16535
95.5k
  unsigned mid;
16536
95.5k
  unsigned start = 0;
16537
95.5k
  unsigned end = 750;
16538
850k
  while (start < end) {
16539
850k
    mid = start + (end - start) / 2;
16540
850k
    if (Opcode == getStackOpcodeTable[mid][0]) {
16541
95.5k
      break;
16542
95.5k
    }
16543
754k
    if (Opcode < getStackOpcodeTable[mid][0])
16544
412k
      end = mid;
16545
341k
    else
16546
341k
      start = mid + 1;
16547
754k
  }
16548
95.5k
  if (start == end)
16549
0
    return -1; // Instruction doesn't exist in this table.
16550
16551
95.5k
  return getStackOpcodeTable[mid][1];
16552
95.5k
}
16553
16554
// getWasm64Opcode
16555
LLVM_READONLY
16556
0
int getWasm64Opcode(uint16_t Opcode) {
16557
0
static const uint16_t getWasm64OpcodeTable[][2] = {
16558
0
  { WebAssembly::ATOMIC_LOAD16_U_I32_A32, WebAssembly::ATOMIC_LOAD16_U_I32_A64 },
16559
0
  { WebAssembly::ATOMIC_LOAD16_U_I32_A32_S, WebAssembly::ATOMIC_LOAD16_U_I32_A64_S },
16560
0
  { WebAssembly::ATOMIC_LOAD16_U_I64_A32, WebAssembly::ATOMIC_LOAD16_U_I64_A64 },
16561
0
  { WebAssembly::ATOMIC_LOAD16_U_I64_A32_S, WebAssembly::ATOMIC_LOAD16_U_I64_A64_S },
16562
0
  { WebAssembly::ATOMIC_LOAD32_U_I64_A32, WebAssembly::ATOMIC_LOAD32_U_I64_A64 },
16563
0
  { WebAssembly::ATOMIC_LOAD32_U_I64_A32_S, WebAssembly::ATOMIC_LOAD32_U_I64_A64_S },
16564
0
  { WebAssembly::ATOMIC_LOAD8_U_I32_A32, WebAssembly::ATOMIC_LOAD8_U_I32_A64 },
16565
0
  { WebAssembly::ATOMIC_LOAD8_U_I32_A32_S, WebAssembly::ATOMIC_LOAD8_U_I32_A64_S },
16566
0
  { WebAssembly::ATOMIC_LOAD8_U_I64_A32, WebAssembly::ATOMIC_LOAD8_U_I64_A64 },
16567
0
  { WebAssembly::ATOMIC_LOAD8_U_I64_A32_S, WebAssembly::ATOMIC_LOAD8_U_I64_A64_S },
16568
0
  { WebAssembly::ATOMIC_LOAD_I32_A32, WebAssembly::ATOMIC_LOAD_I32_A64 },
16569
0
  { WebAssembly::ATOMIC_LOAD_I32_A32_S, WebAssembly::ATOMIC_LOAD_I32_A64_S },
16570
0
  { WebAssembly::ATOMIC_LOAD_I64_A32, WebAssembly::ATOMIC_LOAD_I64_A64 },
16571
0
  { WebAssembly::ATOMIC_LOAD_I64_A32_S, WebAssembly::ATOMIC_LOAD_I64_A64_S },
16572
0
  { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64 },
16573
0
  { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S },
16574
0
  { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64 },
16575
0
  { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S },
16576
0
  { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64 },
16577
0
  { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S },
16578
0
  { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64 },
16579
0
  { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S },
16580
0
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
16581
0
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
16582
0
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
16583
0
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
16584
0
  { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64 },
16585
0
  { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S },
16586
0
  { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64 },
16587
0
  { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S },
16588
0
  { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64 },
16589
0
  { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S },
16590
0
  { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64 },
16591
0
  { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S },
16592
0
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64 },
16593
0
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S },
16594
0
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64 },
16595
0
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S },
16596
0
  { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64 },
16597
0
  { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S },
16598
0
  { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64 },
16599
0
  { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S },
16600
0
  { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64 },
16601
0
  { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S },
16602
0
  { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64 },
16603
0
  { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S },
16604
0
  { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
16605
0
  { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
16606
0
  { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64 },
16607
0
  { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S },
16608
0
  { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64 },
16609
0
  { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S },
16610
0
  { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64 },
16611
0
  { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S },
16612
0
  { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64 },
16613
0
  { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S },
16614
0
  { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64 },
16615
0
  { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S },
16616
0
  { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64 },
16617
0
  { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S },
16618
0
  { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64 },
16619
0
  { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S },
16620
0
  { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64 },
16621
0
  { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S },
16622
0
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
16623
0
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
16624
0
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
16625
0
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
16626
0
  { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64 },
16627
0
  { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S },
16628
0
  { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64 },
16629
0
  { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S },
16630
0
  { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64 },
16631
0
  { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S },
16632
0
  { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64 },
16633
0
  { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S },
16634
0
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64 },
16635
0
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S },
16636
0
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64 },
16637
0
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S },
16638
0
  { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64 },
16639
0
  { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S },
16640
0
  { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64 },
16641
0
  { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S },
16642
0
  { WebAssembly::ATOMIC_RMW_ADD_I32_A32, WebAssembly::ATOMIC_RMW_ADD_I32_A64 },
16643
0
  { WebAssembly::ATOMIC_RMW_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW_ADD_I32_A64_S },
16644
0
  { WebAssembly::ATOMIC_RMW_ADD_I64_A32, WebAssembly::ATOMIC_RMW_ADD_I64_A64 },
16645
0
  { WebAssembly::ATOMIC_RMW_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW_ADD_I64_A64_S },
16646
0
  { WebAssembly::ATOMIC_RMW_AND_I32_A32, WebAssembly::ATOMIC_RMW_AND_I32_A64 },
16647
0
  { WebAssembly::ATOMIC_RMW_AND_I32_A32_S, WebAssembly::ATOMIC_RMW_AND_I32_A64_S },
16648
0
  { WebAssembly::ATOMIC_RMW_AND_I64_A32, WebAssembly::ATOMIC_RMW_AND_I64_A64 },
16649
0
  { WebAssembly::ATOMIC_RMW_AND_I64_A32_S, WebAssembly::ATOMIC_RMW_AND_I64_A64_S },
16650
0
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64 },
16651
0
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S },
16652
0
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64 },
16653
0
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S },
16654
0
  { WebAssembly::ATOMIC_RMW_OR_I32_A32, WebAssembly::ATOMIC_RMW_OR_I32_A64 },
16655
0
  { WebAssembly::ATOMIC_RMW_OR_I32_A32_S, WebAssembly::ATOMIC_RMW_OR_I32_A64_S },
16656
0
  { WebAssembly::ATOMIC_RMW_OR_I64_A32, WebAssembly::ATOMIC_RMW_OR_I64_A64 },
16657
0
  { WebAssembly::ATOMIC_RMW_OR_I64_A32_S, WebAssembly::ATOMIC_RMW_OR_I64_A64_S },
16658
0
  { WebAssembly::ATOMIC_RMW_SUB_I32_A32, WebAssembly::ATOMIC_RMW_SUB_I32_A64 },
16659
0
  { WebAssembly::ATOMIC_RMW_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW_SUB_I32_A64_S },
16660
0
  { WebAssembly::ATOMIC_RMW_SUB_I64_A32, WebAssembly::ATOMIC_RMW_SUB_I64_A64 },
16661
0
  { WebAssembly::ATOMIC_RMW_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW_SUB_I64_A64_S },
16662
0
  { WebAssembly::ATOMIC_RMW_XCHG_I32_A32, WebAssembly::ATOMIC_RMW_XCHG_I32_A64 },
16663
0
  { WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S },
16664
0
  { WebAssembly::ATOMIC_RMW_XCHG_I64_A32, WebAssembly::ATOMIC_RMW_XCHG_I64_A64 },
16665
0
  { WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S },
16666
0
  { WebAssembly::ATOMIC_RMW_XOR_I32_A32, WebAssembly::ATOMIC_RMW_XOR_I32_A64 },
16667
0
  { WebAssembly::ATOMIC_RMW_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW_XOR_I32_A64_S },
16668
0
  { WebAssembly::ATOMIC_RMW_XOR_I64_A32, WebAssembly::ATOMIC_RMW_XOR_I64_A64 },
16669
0
  { WebAssembly::ATOMIC_RMW_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW_XOR_I64_A64_S },
16670
0
  { WebAssembly::ATOMIC_STORE16_I32_A32, WebAssembly::ATOMIC_STORE16_I32_A64 },
16671
0
  { WebAssembly::ATOMIC_STORE16_I32_A32_S, WebAssembly::ATOMIC_STORE16_I32_A64_S },
16672
0
  { WebAssembly::ATOMIC_STORE16_I64_A32, WebAssembly::ATOMIC_STORE16_I64_A64 },
16673
0
  { WebAssembly::ATOMIC_STORE16_I64_A32_S, WebAssembly::ATOMIC_STORE16_I64_A64_S },
16674
0
  { WebAssembly::ATOMIC_STORE32_I64_A32, WebAssembly::ATOMIC_STORE32_I64_A64 },
16675
0
  { WebAssembly::ATOMIC_STORE32_I64_A32_S, WebAssembly::ATOMIC_STORE32_I64_A64_S },
16676
0
  { WebAssembly::ATOMIC_STORE8_I32_A32, WebAssembly::ATOMIC_STORE8_I32_A64 },
16677
0
  { WebAssembly::ATOMIC_STORE8_I32_A32_S, WebAssembly::ATOMIC_STORE8_I32_A64_S },
16678
0
  { WebAssembly::ATOMIC_STORE8_I64_A32, WebAssembly::ATOMIC_STORE8_I64_A64 },
16679
0
  { WebAssembly::ATOMIC_STORE8_I64_A32_S, WebAssembly::ATOMIC_STORE8_I64_A64_S },
16680
0
  { WebAssembly::ATOMIC_STORE_I32_A32, WebAssembly::ATOMIC_STORE_I32_A64 },
16681
0
  { WebAssembly::ATOMIC_STORE_I32_A32_S, WebAssembly::ATOMIC_STORE_I32_A64_S },
16682
0
  { WebAssembly::ATOMIC_STORE_I64_A32, WebAssembly::ATOMIC_STORE_I64_A64 },
16683
0
  { WebAssembly::ATOMIC_STORE_I64_A32_S, WebAssembly::ATOMIC_STORE_I64_A64_S },
16684
0
  { WebAssembly::LOAD16_S_I32_A32, WebAssembly::LOAD16_S_I32_A64 },
16685
0
  { WebAssembly::LOAD16_S_I32_A32_S, WebAssembly::LOAD16_S_I32_A64_S },
16686
0
  { WebAssembly::LOAD16_S_I64_A32, WebAssembly::LOAD16_S_I64_A64 },
16687
0
  { WebAssembly::LOAD16_S_I64_A32_S, WebAssembly::LOAD16_S_I64_A64_S },
16688
0
  { WebAssembly::LOAD16_U_I32_A32, WebAssembly::LOAD16_U_I32_A64 },
16689
0
  { WebAssembly::LOAD16_U_I32_A32_S, WebAssembly::LOAD16_U_I32_A64_S },
16690
0
  { WebAssembly::LOAD16_U_I64_A32, WebAssembly::LOAD16_U_I64_A64 },
16691
0
  { WebAssembly::LOAD16_U_I64_A32_S, WebAssembly::LOAD16_U_I64_A64_S },
16692
0
  { WebAssembly::LOAD32_S_I64_A32, WebAssembly::LOAD32_S_I64_A64 },
16693
0
  { WebAssembly::LOAD32_S_I64_A32_S, WebAssembly::LOAD32_S_I64_A64_S },
16694
0
  { WebAssembly::LOAD32_U_I64_A32, WebAssembly::LOAD32_U_I64_A64 },
16695
0
  { WebAssembly::LOAD32_U_I64_A32_S, WebAssembly::LOAD32_U_I64_A64_S },
16696
0
  { WebAssembly::LOAD8_S_I32_A32, WebAssembly::LOAD8_S_I32_A64 },
16697
0
  { WebAssembly::LOAD8_S_I32_A32_S, WebAssembly::LOAD8_S_I32_A64_S },
16698
0
  { WebAssembly::LOAD8_S_I64_A32, WebAssembly::LOAD8_S_I64_A64 },
16699
0
  { WebAssembly::LOAD8_S_I64_A32_S, WebAssembly::LOAD8_S_I64_A64_S },
16700
0
  { WebAssembly::LOAD8_U_I32_A32, WebAssembly::LOAD8_U_I32_A64 },
16701
0
  { WebAssembly::LOAD8_U_I32_A32_S, WebAssembly::LOAD8_U_I32_A64_S },
16702
0
  { WebAssembly::LOAD8_U_I64_A32, WebAssembly::LOAD8_U_I64_A64 },
16703
0
  { WebAssembly::LOAD8_U_I64_A32_S, WebAssembly::LOAD8_U_I64_A64_S },
16704
0
  { WebAssembly::LOAD_F32_A32, WebAssembly::LOAD_F32_A64 },
16705
0
  { WebAssembly::LOAD_F32_A32_S, WebAssembly::LOAD_F32_A64_S },
16706
0
  { WebAssembly::LOAD_F64_A32, WebAssembly::LOAD_F64_A64 },
16707
0
  { WebAssembly::LOAD_F64_A32_S, WebAssembly::LOAD_F64_A64_S },
16708
0
  { WebAssembly::LOAD_I32_A32, WebAssembly::LOAD_I32_A64 },
16709
0
  { WebAssembly::LOAD_I32_A32_S, WebAssembly::LOAD_I32_A64_S },
16710
0
  { WebAssembly::LOAD_I64_A32, WebAssembly::LOAD_I64_A64 },
16711
0
  { WebAssembly::LOAD_I64_A32_S, WebAssembly::LOAD_I64_A64_S },
16712
0
  { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64 },
16713
0
  { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S },
16714
0
  { WebAssembly::MEMORY_ATOMIC_WAIT32_A32, WebAssembly::MEMORY_ATOMIC_WAIT32_A64 },
16715
0
  { WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S },
16716
0
  { WebAssembly::MEMORY_ATOMIC_WAIT64_A32, WebAssembly::MEMORY_ATOMIC_WAIT64_A64 },
16717
0
  { WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S },
16718
0
  { WebAssembly::STORE16_I32_A32, WebAssembly::STORE16_I32_A64 },
16719
0
  { WebAssembly::STORE16_I32_A32_S, WebAssembly::STORE16_I32_A64_S },
16720
0
  { WebAssembly::STORE16_I64_A32, WebAssembly::STORE16_I64_A64 },
16721
0
  { WebAssembly::STORE16_I64_A32_S, WebAssembly::STORE16_I64_A64_S },
16722
0
  { WebAssembly::STORE32_I64_A32, WebAssembly::STORE32_I64_A64 },
16723
0
  { WebAssembly::STORE32_I64_A32_S, WebAssembly::STORE32_I64_A64_S },
16724
0
  { WebAssembly::STORE8_I32_A32, WebAssembly::STORE8_I32_A64 },
16725
0
  { WebAssembly::STORE8_I32_A32_S, WebAssembly::STORE8_I32_A64_S },
16726
0
  { WebAssembly::STORE8_I64_A32, WebAssembly::STORE8_I64_A64 },
16727
0
  { WebAssembly::STORE8_I64_A32_S, WebAssembly::STORE8_I64_A64_S },
16728
0
  { WebAssembly::STORE_F32_A32, WebAssembly::STORE_F32_A64 },
16729
0
  { WebAssembly::STORE_F32_A32_S, WebAssembly::STORE_F32_A64_S },
16730
0
  { WebAssembly::STORE_F64_A32, WebAssembly::STORE_F64_A64 },
16731
0
  { WebAssembly::STORE_F64_A32_S, WebAssembly::STORE_F64_A64_S },
16732
0
  { WebAssembly::STORE_I32_A32, WebAssembly::STORE_I32_A64 },
16733
0
  { WebAssembly::STORE_I32_A32_S, WebAssembly::STORE_I32_A64_S },
16734
0
  { WebAssembly::STORE_I64_A32, WebAssembly::STORE_I64_A64 },
16735
0
  { WebAssembly::STORE_I64_A32_S, WebAssembly::STORE_I64_A64_S },
16736
0
}; // End of getWasm64OpcodeTable
16737
16738
0
  unsigned mid;
16739
0
  unsigned start = 0;
16740
0
  unsigned end = 178;
16741
0
  while (start < end) {
16742
0
    mid = start + (end - start) / 2;
16743
0
    if (Opcode == getWasm64OpcodeTable[mid][0]) {
16744
0
      break;
16745
0
    }
16746
0
    if (Opcode < getWasm64OpcodeTable[mid][0])
16747
0
      end = mid;
16748
0
    else
16749
0
      start = mid + 1;
16750
0
  }
16751
0
  if (start == end)
16752
0
    return -1; // Instruction doesn't exist in this table.
16753
16754
0
  return getWasm64OpcodeTable[mid][1];
16755
0
}
16756
16757
} // end namespace WebAssembly
16758
} // end namespace llvm
16759
#endif // GET_INSTRMAP_INFO
16760