/src/build/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass WebAssemblyMCRegisterClasses[];

namespace WebAssembly {
enum {
  NoRegister,
  ARGUMENTS = 1,
  VALUE_STACK = 2,
  EXTERNREF_0 = 3,
  FP32 = 4,
  FP64 = 5,
  FUNCREF_0 = 6,
  SP32 = 7,
  SP64 = 8,
  F32_0 = 9,
  F64_0 = 10,
  I32_0 = 11,
  I64_0 = 12,
  V128_0 = 13,
  NUM_TARGET_REGS // 14
};
} // end namespace WebAssembly

// Register classes

namespace WebAssembly {
enum {
  EXTERNREFRegClassID = 0,
  FUNCREFRegClassID = 1,
  I32RegClassID = 2,
  F32RegClassID = 3,
  I64RegClassID = 4,
  F64RegClassID = 5,
  V128RegClassID = 6,

};
} // end namespace WebAssembly

// Register pressure sets enum.
namespace WebAssembly {
enum RegisterPressureSets {
  EXTERNREF = 0,
  FUNCREF = 1,
  F32 = 2,
  F64 = 3,
  V128 = 4,
  I32 = 5,
  I64 = 6,
};
} // end namespace WebAssembly

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const int16_t WebAssemblyRegDiffLists[] = {
  /* 0 */ 0,
};

extern const LaneBitmask WebAssemblyLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
};

extern const uint16_t WebAssemblySubRegIdxLists[] = {
  /* 0 */ 0,
};

extern const MCRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRanges[] = {
  { 65535, 65535 },
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char WebAssemblyRegStrings[] = {
  /* 0 */ "F32_0\0"
  /* 6 */ "I32_0\0"
  /* 12 */ "F64_0\0"
  /* 18 */ "I64_0\0"
  /* 24 */ "V128_0\0"
  /* 31 */ "FUNCREF_0\0"
  /* 41 */ "EXTERNREF_0\0"
  /* 53 */ "FP32\0"
  /* 58 */ "SP32\0"
  /* 63 */ "FP64\0"
  /* 68 */ "SP64\0"
  /* 73 */ "VALUE_STACK\0"
  /* 85 */ "ARGUMENTS\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc WebAssemblyRegDesc[] = { // Descriptors
  { 5, 0, 0, 0, 0, 0 },
  { 85, 0, 0, 0, 0, 0 },
  { 73, 0, 0, 0, 1, 0 },
  { 41, 0, 0, 0, 2, 0 },
  { 53, 0, 0, 0, 3, 0 },
  { 63, 0, 0, 0, 4, 0 },
  { 31, 0, 0, 0, 5, 0 },
  { 58, 0, 0, 0, 6, 0 },
  { 68, 0, 0, 0, 7, 0 },
  { 0, 0, 0, 0, 8, 0 },
  { 12, 0, 0, 0, 9, 0 },
  { 6, 0, 0, 0, 10, 0 },
  { 18, 0, 0, 0, 11, 0 },
  { 24, 0, 0, 0, 12, 0 },
};

extern const MCPhysReg WebAssemblyRegUnitRoots[][2] = {
  { WebAssembly::ARGUMENTS },
  { WebAssembly::VALUE_STACK },
  { WebAssembly::EXTERNREF_0 },
  { WebAssembly::FP32 },
  { WebAssembly::FP64 },
  { WebAssembly::FUNCREF_0 },
  { WebAssembly::SP32 },
  { WebAssembly::SP64 },
  { WebAssembly::F32_0 },
  { WebAssembly::F64_0 },
  { WebAssembly::I32_0 },
  { WebAssembly::I64_0 },
  { WebAssembly::V128_0 },
};

namespace {     // Register classes...
  // EXTERNREF Register Class...
  const MCPhysReg EXTERNREF[] = {
    WebAssembly::EXTERNREF_0, 
  };

  // EXTERNREF Bit set.
  const uint8_t EXTERNREFBits[] = {
    0x08, 
  };

  // FUNCREF Register Class...
  const MCPhysReg FUNCREF[] = {
    WebAssembly::FUNCREF_0, 
  };

  // FUNCREF Bit set.
  const uint8_t FUNCREFBits[] = {
    0x40, 
  };

  // I32 Register Class...
  const MCPhysReg I32[] = {
    WebAssembly::FP32, WebAssembly::SP32, WebAssembly::I32_0, 
  };

  // I32 Bit set.
  const uint8_t I32Bits[] = {
    0x90, 0x08, 
  };

  // F32 Register Class...
  const MCPhysReg F32[] = {
    WebAssembly::F32_0, 
  };

  // F32 Bit set.
  const uint8_t F32Bits[] = {
    0x00, 0x02, 
  };

  // I64 Register Class...
  const MCPhysReg I64[] = {
    WebAssembly::FP64, WebAssembly::SP64, WebAssembly::I64_0, 
  };

  // I64 Bit set.
  const uint8_t I64Bits[] = {
    0x20, 0x11, 
  };

  // F64 Register Class...
  const MCPhysReg F64[] = {
    WebAssembly::F64_0, 
  };

  // F64 Bit set.
  const uint8_t F64Bits[] = {
    0x00, 0x04, 
  };

  // V128 Register Class...
  const MCPhysReg V128[] = {
    WebAssembly::V128_0, 
  };

  // V128 Bit set.
  const uint8_t V128Bits[] = {
    0x00, 0x20, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char WebAssemblyRegClassStrings[] = {
  /* 0 */ "F32\0"
  /* 4 */ "I32\0"
  /* 8 */ "F64\0"
  /* 12 */ "I64\0"
  /* 16 */ "V128\0"
  /* 21 */ "FUNCREF\0"
  /* 29 */ "EXTERNREF\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass WebAssemblyMCRegisterClasses[] = {
  { EXTERNREF, EXTERNREFBits, 29, 1, sizeof(EXTERNREFBits), WebAssembly::EXTERNREFRegClassID, 0, 1, true },
  { FUNCREF, FUNCREFBits, 21, 1, sizeof(FUNCREFBits), WebAssembly::FUNCREFRegClassID, 0, 1, true },
  { I32, I32Bits, 4, 3, sizeof(I32Bits), WebAssembly::I32RegClassID, 32, 1, true },
  { F32, F32Bits, 0, 1, sizeof(F32Bits), WebAssembly::F32RegClassID, 32, 1, true },
  { I64, I64Bits, 12, 3, sizeof(I64Bits), WebAssembly::I64RegClassID, 64, 1, true },
  { F64, F64Bits, 8, 1, sizeof(F64Bits), WebAssembly::F64RegClassID, 64, 1, true },
  { V128, V128Bits, 16, 1, sizeof(V128Bits), WebAssembly::V128RegClassID, 128, 1, true },
};

extern const uint16_t WebAssemblyRegEncodingTable[] = {
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
};
static inline void InitWebAssemblyMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(WebAssemblyRegDesc, 14, RA, PC, WebAssemblyMCRegisterClasses, 7, WebAssemblyRegUnitRoots, 13, WebAssemblyRegDiffLists, WebAssemblyLaneMaskLists, WebAssemblyRegStrings, WebAssemblyRegClassStrings, WebAssemblySubRegIdxLists, 1,
WebAssemblySubRegIdxRanges, WebAssemblyRegEncodingTable);

}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class WebAssemblyFrameLowering;

struct WebAssemblyGenRegisterInfo : public TargetRegisterInfo {
  explicit WebAssemblyGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const WebAssemblyFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace WebAssembly { // Register classes
  extern const TargetRegisterClass EXTERNREFRegClass;
  extern const TargetRegisterClass FUNCREFRegClass;
  extern const TargetRegisterClass I32RegClass;
  extern const TargetRegisterClass F32RegClass;
  extern const TargetRegisterClass I64RegClass;
  extern const TargetRegisterClass F64RegClass;
  extern const TargetRegisterClass V128RegClass;
} // end namespace WebAssembly

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass WebAssemblyMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i32, MVT::Other,
  /* 2 */ MVT::i64, MVT::Other,
  /* 4 */ MVT::f32, MVT::Other,
  /* 6 */ MVT::f64, MVT::Other,
  /* 8 */ MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::Other,
  /* 15 */ MVT::funcref, MVT::Other,
  /* 17 */ MVT::externref, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 0, 0, 0, /*VTLists+*/17 },    // EXTERNREF
  { 0, 0, 0, /*VTLists+*/15 },    // FUNCREF
  { 32, 32, 32, /*VTLists+*/0 },    // I32
  { 32, 32, 32, /*VTLists+*/4 },    // F32
  { 64, 64, 64, /*VTLists+*/2 },    // I64
  { 64, 64, 64, /*VTLists+*/6 },    // F64
  { 128, 128, 128, /*VTLists+*/8 },    // V128
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t EXTERNREFSubClassMask[] = {
  0x00000001, 
};

static const uint32_t FUNCREFSubClassMask[] = {
  0x00000002, 
};

static const uint32_t I32SubClassMask[] = {
  0x00000004, 
};

static const uint32_t F32SubClassMask[] = {
  0x00000008, 
};

static const uint32_t I64SubClassMask[] = {
  0x00000010, 
};

static const uint32_t F64SubClassMask[] = {
  0x00000020, 
};

static const uint32_t V128SubClassMask[] = {
  0x00000040, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 0,
};


namespace WebAssembly {   // Register class instances
  extern const TargetRegisterClass EXTERNREFRegClass = {
    &WebAssemblyMCRegisterClasses[EXTERNREFRegClassID],
    EXTERNREFSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass FUNCREFRegClass = {
    &WebAssemblyMCRegisterClasses[FUNCREFRegClassID],
    FUNCREFSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass I32RegClass = {
    &WebAssemblyMCRegisterClasses[I32RegClassID],
    I32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass F32RegClass = {
    &WebAssemblyMCRegisterClasses[F32RegClassID],
    F32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass I64RegClass = {
    &WebAssemblyMCRegisterClasses[I64RegClassID],
    I64SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass F64RegClass = {
    &WebAssemblyMCRegisterClasses[F64RegClassID],
    F64SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass V128RegClass = {
    &WebAssemblyMCRegisterClasses[V128RegClassID],
    V128SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

} // end namespace WebAssembly

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &WebAssembly::EXTERNREFRegClass,
    &WebAssembly::FUNCREFRegClass,
    &WebAssembly::I32RegClass,
    &WebAssembly::F32RegClass,
    &WebAssembly::I64RegClass,
    &WebAssembly::F64RegClass,
    &WebAssembly::V128RegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, false, false, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

/// Get the weight in units of pressure for this register class.
const RegClassWeight &WebAssemblyGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 1},   // EXTERNREF
    {1, 1},   // FUNCREF
    {1, 3},   // I32
    {1, 1},   // F32
    {1, 3},   // I64
    {1, 1},   // F64
    {1, 1},   // V128
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned WebAssemblyGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 13 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
  return 7;
}

// Get the name of this register unit pressure set.
const char *WebAssemblyGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "EXTERNREF",
    "FUNCREF",
    "F32",
    "F64",
    "V128",
    "I32",
    "I64",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned WebAssemblyGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,    // 0: EXTERNREF
    1,    // 1: FUNCREF
    1,    // 2: F32
    1,    // 3: F64
    1,    // 4: V128
    3,    // 5: I32
    3,    // 6: I64
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 0, -1,
  /* 2 */ 1, -1,
  /* 4 */ 2, -1,
  /* 6 */ 3, -1,
  /* 8 */ 4, -1,
  /* 10 */ 5, -1,
  /* 12 */ 6, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *WebAssemblyGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    0,2,10,4,12,6,8,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *WebAssemblyGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 13 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    1,1,0,10,12,2,10,12,4,6,10,12,8,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc WebAssemblyRegDesc[];
extern const int16_t WebAssemblyRegDiffLists[];
extern const LaneBitmask WebAssemblyLaneMaskLists[];
extern const char WebAssemblyRegStrings[];
extern const char WebAssemblyRegClassStrings[];
extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
extern const uint16_t WebAssemblySubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRanges[];
extern const uint16_t WebAssemblyRegEncodingTable[];
WebAssemblyGenRegisterInfo::
WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&WebAssemblyRegInfoDesc, RegisterClasses, RegisterClasses+7,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(WebAssemblyRegDesc, 14, RA, PC,
                     WebAssemblyMCRegisterClasses, 7,
                     WebAssemblyRegUnitRoots,
                     13,
                     WebAssemblyRegDiffLists,
                     WebAssemblyLaneMaskLists,
                     WebAssemblyRegStrings,
                     WebAssemblyRegClassStrings,
                     WebAssemblySubRegIdxLists,
                     1,
                     WebAssemblySubRegIdxRanges,
                     WebAssemblyRegEncodingTable);

}



ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
  return std::nullopt;
}

bool WebAssemblyGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool WebAssemblyGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool WebAssemblyGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool WebAssemblyGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      false;
}

ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
  return std::nullopt;
}

const WebAssemblyFrameLowering *
WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const WebAssemblyFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC


Coverage Report

Created: 2024-01-17 10:31

Line	Count	Source (jump to first uncovered line)
1		/===- TableGen'erated file -------------------------------------- C++ --===\
2		\|* *\|
3		\|* Target Register Enum Values *\|
4		\|* *\|
5		\|* Automatically generated file, do not edit! *\|
6		\|* *\|
7		\===----------------------------------------------------------------------===/
8
9
10		#ifdef GET_REGINFO_ENUM
11		#undef GET_REGINFO_ENUM
12
13		namespace llvm {
14
15		class MCRegisterClass;
16		extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
17
18		namespace WebAssembly {
19		enum {
20		NoRegister,
21		ARGUMENTS = 1,
22		VALUE_STACK = 2,
23		EXTERNREF_0 = 3,
24		FP32 = 4,
25		FP64 = 5,
26		FUNCREF_0 = 6,
27		SP32 = 7,
28		SP64 = 8,
29		F32_0 = 9,
30		F64_0 = 10,
31		I32_0 = 11,
32		I64_0 = 12,
33		V128_0 = 13,
34		NUM_TARGET_REGS // 14
35		};
36		} // end namespace WebAssembly
37
38		// Register classes
39
40		namespace WebAssembly {
41		enum {
42		EXTERNREFRegClassID = 0,
43		FUNCREFRegClassID = 1,
44		I32RegClassID = 2,
45		F32RegClassID = 3,
46		I64RegClassID = 4,
47		F64RegClassID = 5,
48		V128RegClassID = 6,
49
50		};
51		} // end namespace WebAssembly
52
53		// Register pressure sets enum.
54		namespace WebAssembly {
55		enum RegisterPressureSets {
56		EXTERNREF = 0,
57		FUNCREF = 1,
58		F32 = 2,
59		F64 = 3,
60		V128 = 4,
61		I32 = 5,
62		I64 = 6,
63		};
64		} // end namespace WebAssembly
65
66		} // end namespace llvm
67
68		#endif // GET_REGINFO_ENUM
69
70		/===- TableGen'erated file -------------------------------------- C++ --===\
71		\|* *\|
72		\|* MC Register Information *\|
73		\|* *\|
74		\|* Automatically generated file, do not edit! *\|
75		\|* *\|
76		\===----------------------------------------------------------------------===/
77
78
79		#ifdef GET_REGINFO_MC_DESC
80		#undef GET_REGINFO_MC_DESC
81
82		namespace llvm {
83
84		extern const int16_t WebAssemblyRegDiffLists[] = {
85		/* 0 */ 0,
86		};
87
88		extern const LaneBitmask WebAssemblyLaneMaskLists[] = {
89		/* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
90		};
91
92		extern const uint16_t WebAssemblySubRegIdxLists[] = {
93		/* 0 */ 0,
94		};
95
96		extern const MCRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRanges[] = {
97		{ 65535, 65535 },
98		};
99
100
101		#ifdef __GNUC__
102		#pragma GCC diagnostic push
103		#pragma GCC diagnostic ignored "-Woverlength-strings"
104		#endif
105		extern const char WebAssemblyRegStrings[] = {
106		/* 0 */ "F32_0\0"
107		/* 6 */ "I32_0\0"
108		/* 12 */ "F64_0\0"
109		/* 18 */ "I64_0\0"
110		/* 24 */ "V128_0\0"
111		/* 31 */ "FUNCREF_0\0"
112		/* 41 */ "EXTERNREF_0\0"
113		/* 53 */ "FP32\0"
114		/* 58 */ "SP32\0"
115		/* 63 */ "FP64\0"
116		/* 68 */ "SP64\0"
117		/* 73 */ "VALUE_STACK\0"
118		/* 85 */ "ARGUMENTS\0"
119		};
120		#ifdef __GNUC__
121		#pragma GCC diagnostic pop
122		#endif
123
124		extern const MCRegisterDesc WebAssemblyRegDesc[] = { // Descriptors
125		{ 5, 0, 0, 0, 0, 0 },
126		{ 85, 0, 0, 0, 0, 0 },
127		{ 73, 0, 0, 0, 1, 0 },
128		{ 41, 0, 0, 0, 2, 0 },
129		{ 53, 0, 0, 0, 3, 0 },
130		{ 63, 0, 0, 0, 4, 0 },
131		{ 31, 0, 0, 0, 5, 0 },
132		{ 58, 0, 0, 0, 6, 0 },
133		{ 68, 0, 0, 0, 7, 0 },
134		{ 0, 0, 0, 0, 8, 0 },
135		{ 12, 0, 0, 0, 9, 0 },
136		{ 6, 0, 0, 0, 10, 0 },
137		{ 18, 0, 0, 0, 11, 0 },
138		{ 24, 0, 0, 0, 12, 0 },
139		};
140
141		extern const MCPhysReg WebAssemblyRegUnitRoots[][2] = {
142		{ WebAssembly::ARGUMENTS },
143		{ WebAssembly::VALUE_STACK },
144		{ WebAssembly::EXTERNREF_0 },
145		{ WebAssembly::FP32 },
146		{ WebAssembly::FP64 },
147		{ WebAssembly::FUNCREF_0 },
148		{ WebAssembly::SP32 },
149		{ WebAssembly::SP64 },
150		{ WebAssembly::F32_0 },
151		{ WebAssembly::F64_0 },
152		{ WebAssembly::I32_0 },
153		{ WebAssembly::I64_0 },
154		{ WebAssembly::V128_0 },
155		};
156
157		namespace { // Register classes...
158		// EXTERNREF Register Class...
159		const MCPhysReg EXTERNREF[] = {
160		WebAssembly::EXTERNREF_0,
161		};
162
163		// EXTERNREF Bit set.
164		const uint8_t EXTERNREFBits[] = {
165		0x08,
166		};
167
168		// FUNCREF Register Class...
169		const MCPhysReg FUNCREF[] = {
170		WebAssembly::FUNCREF_0,
171		};
172
173		// FUNCREF Bit set.
174		const uint8_t FUNCREFBits[] = {
175		0x40,
176		};
177
178		// I32 Register Class...
179		const MCPhysReg I32[] = {
180		WebAssembly::FP32, WebAssembly::SP32, WebAssembly::I32_0,
181		};
182
183		// I32 Bit set.
184		const uint8_t I32Bits[] = {
185		0x90, 0x08,
186		};
187
188		// F32 Register Class...
189		const MCPhysReg F32[] = {
190		WebAssembly::F32_0,
191		};
192
193		// F32 Bit set.
194		const uint8_t F32Bits[] = {
195		0x00, 0x02,
196		};
197
198		// I64 Register Class...
199		const MCPhysReg I64[] = {
200		WebAssembly::FP64, WebAssembly::SP64, WebAssembly::I64_0,
201		};
202
203		// I64 Bit set.
204		const uint8_t I64Bits[] = {
205		0x20, 0x11,
206		};
207
208		// F64 Register Class...
209		const MCPhysReg F64[] = {
210		WebAssembly::F64_0,
211		};
212
213		// F64 Bit set.
214		const uint8_t F64Bits[] = {
215		0x00, 0x04,
216		};
217
218		// V128 Register Class...
219		const MCPhysReg V128[] = {
220		WebAssembly::V128_0,
221		};
222
223		// V128 Bit set.
224		const uint8_t V128Bits[] = {
225		0x00, 0x20,
226		};
227
228		} // end anonymous namespace
229
230
231		#ifdef __GNUC__
232		#pragma GCC diagnostic push
233		#pragma GCC diagnostic ignored "-Woverlength-strings"
234		#endif
235		extern const char WebAssemblyRegClassStrings[] = {
236		/* 0 */ "F32\0"
237		/* 4 */ "I32\0"
238		/* 8 */ "F64\0"
239		/* 12 */ "I64\0"
240		/* 16 */ "V128\0"
241		/* 21 */ "FUNCREF\0"
242		/* 29 */ "EXTERNREF\0"
243		};
244		#ifdef __GNUC__
245		#pragma GCC diagnostic pop
246		#endif
247
248		extern const MCRegisterClass WebAssemblyMCRegisterClasses[] = {
249		{ EXTERNREF, EXTERNREFBits, 29, 1, sizeof(EXTERNREFBits), WebAssembly::EXTERNREFRegClassID, 0, 1, true },
250		{ FUNCREF, FUNCREFBits, 21, 1, sizeof(FUNCREFBits), WebAssembly::FUNCREFRegClassID, 0, 1, true },
251		{ I32, I32Bits, 4, 3, sizeof(I32Bits), WebAssembly::I32RegClassID, 32, 1, true },
252		{ F32, F32Bits, 0, 1, sizeof(F32Bits), WebAssembly::F32RegClassID, 32, 1, true },
253		{ I64, I64Bits, 12, 3, sizeof(I64Bits), WebAssembly::I64RegClassID, 64, 1, true },
254		{ F64, F64Bits, 8, 1, sizeof(F64Bits), WebAssembly::F64RegClassID, 64, 1, true },
255		{ V128, V128Bits, 16, 1, sizeof(V128Bits), WebAssembly::V128RegClassID, 128, 1, true },
256		};
257
258		extern const uint16_t WebAssemblyRegEncodingTable[] = {
259		0,
260		0,
261		0,
262		0,
263		0,
264		0,
265		0,
266		0,
267		0,
268		0,
269		0,
270		0,
271		0,
272		0,
273		};
274	2	static inline void InitWebAssemblyMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
275	2	RI->InitMCRegisterInfo(WebAssemblyRegDesc, 14, RA, PC, WebAssemblyMCRegisterClasses, 7, WebAssemblyRegUnitRoots, 13, WebAssemblyRegDiffLists, WebAssemblyLaneMaskLists, WebAssemblyRegStrings, WebAssemblyRegClassStrings, WebAssemblySubRegIdxLists, 1,
276	2	WebAssemblySubRegIdxRanges, WebAssemblyRegEncodingTable);
277
278	2	}
279
280		} // end namespace llvm
281
282		#endif // GET_REGINFO_MC_DESC
283
284		/===- TableGen'erated file -------------------------------------- C++ --===\
285		\|* *\|
286		\|* Register Information Header Fragment *\|
287		\|* *\|
288		\|* Automatically generated file, do not edit! *\|
289		\|* *\|
290		\===----------------------------------------------------------------------===/
291
292
293		#ifdef GET_REGINFO_HEADER
294		#undef GET_REGINFO_HEADER
295
296		#include "llvm/CodeGen/TargetRegisterInfo.h"
297
298		namespace llvm {
299
300		class WebAssemblyFrameLowering;
301
302		struct WebAssemblyGenRegisterInfo : public TargetRegisterInfo {
303		explicit WebAssemblyGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
304		unsigned PC = 0, unsigned HwMode = 0);
305		const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
306		unsigned getRegUnitWeight(unsigned RegUnit) const override;
307		unsigned getNumRegPressureSets() const override;
308		const char *getRegPressureSetName(unsigned Idx) const override;
309		unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
310		const int getRegClassPressureSets(const TargetRegisterClass RC) const override;
311		const int *getRegUnitPressureSets(unsigned RegUnit) const override;
312		ArrayRef<const char *> getRegMaskNames() const override;
313		ArrayRef<const uint32_t *> getRegMasks() const override;
314		bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
315		bool isFixedRegister(const MachineFunction &, MCRegister) const override;
316		bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
317		bool isConstantPhysReg(MCRegister PhysReg) const override final;
318		/// Devirtualized TargetFrameLowering.
319		static const WebAssemblyFrameLowering *getFrameLowering(
320		const MachineFunction &MF);
321		};
322
323		namespace WebAssembly { // Register classes
324		extern const TargetRegisterClass EXTERNREFRegClass;
325		extern const TargetRegisterClass FUNCREFRegClass;
326		extern const TargetRegisterClass I32RegClass;
327		extern const TargetRegisterClass F32RegClass;
328		extern const TargetRegisterClass I64RegClass;
329		extern const TargetRegisterClass F64RegClass;
330		extern const TargetRegisterClass V128RegClass;
331		} // end namespace WebAssembly
332
333		} // end namespace llvm
334
335		#endif // GET_REGINFO_HEADER
336
337		/===- TableGen'erated file -------------------------------------- C++ --===\
338		\|* *\|
339		\|* Target Register and Register Classes Information *\|
340		\|* *\|
341		\|* Automatically generated file, do not edit! *\|
342		\|* *\|
343		\===----------------------------------------------------------------------===/
344
345
346		#ifdef GET_REGINFO_TARGET_DESC
347		#undef GET_REGINFO_TARGET_DESC
348
349		namespace llvm {
350
351		extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
352
353		static const MVT::SimpleValueType VTLists[] = {
354		/* 0 */ MVT::i32, MVT::Other,
355		/* 2 */ MVT::i64, MVT::Other,
356		/* 4 */ MVT::f32, MVT::Other,
357		/* 6 */ MVT::f64, MVT::Other,
358		/* 8 */ MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::Other,
359		/* 15 */ MVT::funcref, MVT::Other,
360		/* 17 */ MVT::externref, MVT::Other,
361		};
362
363		static const char *SubRegIndexNameTable[] = { "" };
364
365
366		static const LaneBitmask SubRegIndexLaneMaskTable[] = {
367		LaneBitmask::getAll(),
368		};
369
370
371
372		static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
373		// Mode = 0 (Default)
374		{ 0, 0, 0, /VTLists+/17 }, // EXTERNREF
375		{ 0, 0, 0, /VTLists+/15 }, // FUNCREF
376		{ 32, 32, 32, /VTLists+/0 }, // I32
377		{ 32, 32, 32, /VTLists+/4 }, // F32
378		{ 64, 64, 64, /VTLists+/2 }, // I64
379		{ 64, 64, 64, /VTLists+/6 }, // F64
380		{ 128, 128, 128, /VTLists+/8 }, // V128
381		};
382
383		static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
384
385		static const uint32_t EXTERNREFSubClassMask[] = {
386		0x00000001,
387		};
388
389		static const uint32_t FUNCREFSubClassMask[] = {
390		0x00000002,
391		};
392
393		static const uint32_t I32SubClassMask[] = {
394		0x00000004,
395		};
396
397		static const uint32_t F32SubClassMask[] = {
398		0x00000008,
399		};
400
401		static const uint32_t I64SubClassMask[] = {
402		0x00000010,
403		};
404
405		static const uint32_t F64SubClassMask[] = {
406		0x00000020,
407		};
408
409		static const uint32_t V128SubClassMask[] = {
410		0x00000040,
411		};
412
413		static const uint16_t SuperRegIdxSeqs[] = {
414		/* 0 */ 0,
415		};
416
417
418		namespace WebAssembly { // Register class instances
419		extern const TargetRegisterClass EXTERNREFRegClass = {
420		&WebAssemblyMCRegisterClasses[EXTERNREFRegClassID],
421		EXTERNREFSubClassMask,
422		SuperRegIdxSeqs + 0,
423		LaneBitmask(0x0000000000000001),
424		0,
425		false,
426		0x00, /* TSFlags */
427		false, /* HasDisjunctSubRegs */
428		false, /* CoveredBySubRegs */
429		NullRegClasses,
430		nullptr
431		};
432
433		extern const TargetRegisterClass FUNCREFRegClass = {
434		&WebAssemblyMCRegisterClasses[FUNCREFRegClassID],
435		FUNCREFSubClassMask,
436		SuperRegIdxSeqs + 0,
437		LaneBitmask(0x0000000000000001),
438		0,
439		false,
440		0x00, /* TSFlags */
441		false, /* HasDisjunctSubRegs */
442		false, /* CoveredBySubRegs */
443		NullRegClasses,
444		nullptr
445		};
446
447		extern const TargetRegisterClass I32RegClass = {
448		&WebAssemblyMCRegisterClasses[I32RegClassID],
449		I32SubClassMask,
450		SuperRegIdxSeqs + 0,
451		LaneBitmask(0x0000000000000001),
452		0,
453		false,
454		0x00, /* TSFlags */
455		false, /* HasDisjunctSubRegs */
456		false, /* CoveredBySubRegs */
457		NullRegClasses,
458		nullptr
459		};
460
461		extern const TargetRegisterClass F32RegClass = {
462		&WebAssemblyMCRegisterClasses[F32RegClassID],
463		F32SubClassMask,
464		SuperRegIdxSeqs + 0,
465		LaneBitmask(0x0000000000000001),
466		0,
467		false,
468		0x00, /* TSFlags */
469		false, /* HasDisjunctSubRegs */
470		false, /* CoveredBySubRegs */
471		NullRegClasses,
472		nullptr
473		};
474
475		extern const TargetRegisterClass I64RegClass = {
476		&WebAssemblyMCRegisterClasses[I64RegClassID],
477		I64SubClassMask,
478		SuperRegIdxSeqs + 0,
479		LaneBitmask(0x0000000000000001),
480		0,
481		false,
482		0x00, /* TSFlags */
483		false, /* HasDisjunctSubRegs */
484		false, /* CoveredBySubRegs */
485		NullRegClasses,
486		nullptr
487		};
488
489		extern const TargetRegisterClass F64RegClass = {
490		&WebAssemblyMCRegisterClasses[F64RegClassID],
491		F64SubClassMask,
492		SuperRegIdxSeqs + 0,
493		LaneBitmask(0x0000000000000001),
494		0,
495		false,
496		0x00, /* TSFlags */
497		false, /* HasDisjunctSubRegs */
498		false, /* CoveredBySubRegs */
499		NullRegClasses,
500		nullptr
501		};
502
503		extern const TargetRegisterClass V128RegClass = {
504		&WebAssemblyMCRegisterClasses[V128RegClassID],
505		V128SubClassMask,
506		SuperRegIdxSeqs + 0,
507		LaneBitmask(0x0000000000000001),
508		0,
509		false,
510		0x00, /* TSFlags */
511		false, /* HasDisjunctSubRegs */
512		false, /* CoveredBySubRegs */
513		NullRegClasses,
514		nullptr
515		};
516
517		} // end namespace WebAssembly
518
519		namespace {
520		const TargetRegisterClass *const RegisterClasses[] = {
521		&WebAssembly::EXTERNREFRegClass,
522		&WebAssembly::FUNCREFRegClass,
523		&WebAssembly::I32RegClass,
524		&WebAssembly::F32RegClass,
525		&WebAssembly::I64RegClass,
526		&WebAssembly::F64RegClass,
527		&WebAssembly::V128RegClass,
528		};
529		} // end anonymous namespace
530
531		static const uint8_t CostPerUseTable[] = {
532		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
533
534
535		static const bool InAllocatableClassTable[] = {
536		false, false, false, true, true, true, true, true, true, true, true, true, true, true, };
537
538
539		static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
540		CostPerUseTable, 1, InAllocatableClassTable};
541
542		/// Get the weight in units of pressure for this register class.
543		const RegClassWeight &WebAssemblyGenRegisterInfo::
544	44.7k	getRegClassWeight(const TargetRegisterClass *RC) const {
545	44.7k	static const RegClassWeight RCWeightTable[] = {
546	44.7k	{1, 1}, // EXTERNREF
547	44.7k	{1, 1}, // FUNCREF
548	44.7k	{1, 3}, // I32
549	44.7k	{1, 1}, // F32
550	44.7k	{1, 3}, // I64
551	44.7k	{1, 1}, // F64
552	44.7k	{1, 1}, // V128
553	44.7k	};
554	44.7k	return RCWeightTable[RC->getID()];
555	44.7k	}
556
557		/// Get the weight in units of pressure for this register unit.
558		unsigned WebAssemblyGenRegisterInfo::
559	0	getRegUnitWeight(unsigned RegUnit) const {
560	0	assert(RegUnit < 13 && "invalid register unit");
561		// All register units have unit weight.
562	0	return 1;
563	0	}
564
565
566		// Get the number of dimensions of register pressure.
567	6.99k	unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
568	6.99k	return 7;
569	6.99k	}
570
571		// Get the name of this register unit pressure set.
572		const char *WebAssemblyGenRegisterInfo::
573	0	getRegPressureSetName(unsigned Idx) const {
574	0	static const char *PressureNameTable[] = {
575	0	"EXTERNREF",
576	0	"FUNCREF",
577	0	"F32",
578	0	"F64",
579	0	"V128",
580	0	"I32",
581	0	"I64",
582	0	};
583	0	return PressureNameTable[Idx];
584	0	}
585
586		// Get the register unit pressure limit for this dimension.
587		// This limit must be adjusted dynamically for reserved registers.
588		unsigned WebAssemblyGenRegisterInfo::
589	47.2k	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
590	47.2k	static const uint8_t PressureLimitTable[] = {
591	47.2k	1, // 0: EXTERNREF
592	47.2k	1, // 1: FUNCREF
593	47.2k	1, // 2: F32
594	47.2k	1, // 3: F64
595	47.2k	1, // 4: V128
596	47.2k	3, // 5: I32
597	47.2k	3, // 6: I64
598	47.2k	};
599	47.2k	return PressureLimitTable[Idx];
600	47.2k	}
601
602		/// Table of pressure sets per register class or unit.
603		static const int RCSetsTable[] = {
604		/* 0 */ 0, -1,
605		/* 2 */ 1, -1,
606		/* 4 */ 2, -1,
607		/* 6 */ 3, -1,
608		/* 8 */ 4, -1,
609		/* 10 */ 5, -1,
610		/* 12 */ 6, -1,
611		};
612
613		/// Get the dimensions of register pressure impacted by this register class.
614		/// Returns a -1 terminated array of pressure set IDs
615		const int *WebAssemblyGenRegisterInfo::
616	29.4k	getRegClassPressureSets(const TargetRegisterClass *RC) const {
617	29.4k	static const uint8_t RCSetStartTable[] = {
618	29.4k	0,2,10,4,12,6,8,};
619	29.4k	return &RCSetsTable[RCSetStartTable[RC->getID()]];
620	29.4k	}
621
622		/// Get the dimensions of register pressure impacted by this register unit.
623		/// Returns a -1 terminated array of pressure set IDs
624		const int *WebAssemblyGenRegisterInfo::
625	0	getRegUnitPressureSets(unsigned RegUnit) const {
626	0	assert(RegUnit < 13 && "invalid register unit");
627	0	static const uint8_t RUSetStartTable[] = {
628	0	1,1,0,10,12,2,10,12,4,6,10,12,8,};
629	0	return &RCSetsTable[RUSetStartTable[RegUnit]];
630	0	}
631
632		extern const MCRegisterDesc WebAssemblyRegDesc[];
633		extern const int16_t WebAssemblyRegDiffLists[];
634		extern const LaneBitmask WebAssemblyLaneMaskLists[];
635		extern const char WebAssemblyRegStrings[];
636		extern const char WebAssemblyRegClassStrings[];
637		extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
638		extern const uint16_t WebAssemblySubRegIdxLists[];
639		extern const MCRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRanges[];
640		extern const uint16_t WebAssemblyRegEncodingTable[];
641		WebAssemblyGenRegisterInfo::
642		WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
643		unsigned PC, unsigned HwMode)
644		: TargetRegisterInfo(&WebAssemblyRegInfoDesc, RegisterClasses, RegisterClasses+7,
645		SubRegIndexNameTable, SubRegIndexLaneMaskTable,
646	2	LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
647	2	InitMCRegisterInfo(WebAssemblyRegDesc, 14, RA, PC,
648	2	WebAssemblyMCRegisterClasses, 7,
649	2	WebAssemblyRegUnitRoots,
650	2	13,
651	2	WebAssemblyRegDiffLists,
652	2	WebAssemblyLaneMaskLists,
653	2	WebAssemblyRegStrings,
654	2	WebAssemblyRegClassStrings,
655	2	WebAssemblySubRegIdxLists,
656	2	1,
657	2	WebAssemblySubRegIdxRanges,
658	2	WebAssemblyRegEncodingTable);
659
660	2	}
661
662
663
664	0	ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
665	0	return std::nullopt;
666	0	}
667
668		bool WebAssemblyGenRegisterInfo::
669	0	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
670	0	return
671	0	false;
672	0	}
673
674		bool WebAssemblyGenRegisterInfo::
675	0	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
676	0	return
677	0	false;
678	0	}
679
680		bool WebAssemblyGenRegisterInfo::
681	0	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
682	0	return
683	0	false;
684	0	}
685
686		bool WebAssemblyGenRegisterInfo::
687	21.8k	isConstantPhysReg(MCRegister PhysReg) const {
688	21.8k	return
689	21.8k	false;
690	21.8k	}
691
692	0	ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
693	0	return std::nullopt;
694	0	}
695
696		const WebAssemblyFrameLowering *
697	30.7k	WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
698	30.7k	return static_cast<const WebAssemblyFrameLowering *>(
699	30.7k	MF.getSubtarget().getFrameLowering());
700	30.7k	}
701
702		} // end namespace llvm
703
704		#endif // GET_REGINFO_TARGET_DESC
705