/src/build/lib/Target/X86/X86GenCallingConv.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Calling Convention Implementation Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifndef GET_CC_REGISTER_LISTS |
10 | | |
11 | | static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, |
12 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
13 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
14 | | bool llvm::CC_X86(unsigned ValNo, MVT ValVT, |
15 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
16 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
17 | | static bool CC_X86_32(unsigned ValNo, MVT ValVT, |
18 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
19 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
20 | | static bool CC_X86_32_C(unsigned ValNo, MVT ValVT, |
21 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
22 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
23 | | static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT, |
24 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
25 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
26 | | static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT, |
27 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
28 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
29 | | static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT, |
30 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
31 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
32 | | static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT, |
33 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
34 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
35 | | static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT, |
36 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
37 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
38 | | static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT, |
39 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
40 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
41 | | static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT, |
42 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
43 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
44 | | static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT, |
45 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
46 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
47 | | static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT, |
48 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
49 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
50 | | static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT, |
51 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
52 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
53 | | static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT, |
54 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
55 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
56 | | static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT, |
57 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
58 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
59 | | static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT, |
60 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
61 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
62 | | static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT, |
63 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
64 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
65 | | static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT, |
66 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
67 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
68 | | static bool CC_X86_64(unsigned ValNo, MVT ValVT, |
69 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
70 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
71 | | static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, |
72 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
73 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
74 | | static bool CC_X86_64_C(unsigned ValNo, MVT ValVT, |
75 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
76 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
77 | | static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT, |
78 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
79 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
80 | | static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT, |
81 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
82 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
83 | | static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, |
84 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
85 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
86 | | static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, |
87 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
88 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
89 | | static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT, |
90 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
91 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
92 | | static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT, |
93 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
94 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
95 | | static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT, |
96 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
97 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
98 | | static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, |
99 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
100 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
101 | | static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT, |
102 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
103 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
104 | | static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT, |
105 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
106 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
107 | | static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, |
108 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
109 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
110 | | bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT, |
111 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
112 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
113 | | static bool RetCC_X86Common(unsigned ValNo, MVT ValVT, |
114 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
115 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
116 | | static bool RetCC_X86_32(unsigned ValNo, MVT ValVT, |
117 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
118 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
119 | | static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT, |
120 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
121 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
122 | | static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT, |
123 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
124 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
125 | | static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT, |
126 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
127 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
128 | | static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT, |
129 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
130 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
131 | | static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT, |
132 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
133 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
134 | | static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT, |
135 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
136 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
137 | | static bool RetCC_X86_64(unsigned ValNo, MVT ValVT, |
138 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
139 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
140 | | static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, |
141 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
142 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
143 | | static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT, |
144 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
145 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
146 | | static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT, |
147 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
148 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
149 | | static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT, |
150 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
151 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
152 | | static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT, |
153 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
154 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
155 | | static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, |
156 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
157 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
158 | | static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT, |
159 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
160 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
161 | | static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, |
162 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
163 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
164 | | static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT, |
165 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
166 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
167 | | |
168 | | |
169 | | static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, |
170 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
171 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
172 | |
|
173 | 0 | if (LocVT == MVT::i32) { |
174 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
175 | 0 | static const MCPhysReg RegList1[] = { |
176 | 0 | X86::ECX, X86::EDX, X86::R8D, X86::R9D |
177 | 0 | }; |
178 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
179 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
180 | 0 | return false; |
181 | 0 | } |
182 | 0 | } |
183 | 0 | } |
184 | | |
185 | 0 | if (LocVT == MVT::i64) { |
186 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
187 | 0 | static const MCPhysReg RegList2[] = { |
188 | 0 | X86::RCX, X86::RDX, X86::R8, X86::R9 |
189 | 0 | }; |
190 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
191 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
192 | 0 | return false; |
193 | 0 | } |
194 | 0 | } |
195 | 0 | } |
196 | | |
197 | 0 | if (LocVT == MVT::i32) { |
198 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
199 | 0 | static const MCPhysReg RegList3[] = { |
200 | 0 | X86::EDI, X86::ESI, X86::EDX, X86::ECX |
201 | 0 | }; |
202 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
203 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
204 | 0 | return false; |
205 | 0 | } |
206 | 0 | } |
207 | 0 | } |
208 | | |
209 | 0 | if (LocVT == MVT::i64) { |
210 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
211 | 0 | static const MCPhysReg RegList4[] = { |
212 | 0 | X86::RDI, X86::RSI, X86::RDX, X86::RCX |
213 | 0 | }; |
214 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
215 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
216 | 0 | return false; |
217 | 0 | } |
218 | 0 | } |
219 | 0 | } |
220 | | |
221 | 0 | if (LocVT == MVT::i32) { |
222 | 0 | int64_t Offset5 = State.AllocateStack(4, Align(4)); |
223 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); |
224 | 0 | return false; |
225 | 0 | } |
226 | | |
227 | 0 | if (LocVT == MVT::f32 || |
228 | 0 | LocVT == MVT::f64 || |
229 | 0 | LocVT == MVT::v4i32 || |
230 | 0 | LocVT == MVT::v2i64 || |
231 | 0 | LocVT == MVT::v4f32 || |
232 | 0 | LocVT == MVT::v2f64) { |
233 | 0 | static const MCPhysReg RegList6[] = { |
234 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
235 | 0 | }; |
236 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
237 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
238 | 0 | return false; |
239 | 0 | } |
240 | 0 | } |
241 | | |
242 | 0 | if (LocVT == MVT::v8f32 || |
243 | 0 | LocVT == MVT::v4f64 || |
244 | 0 | LocVT == MVT::v8i32 || |
245 | 0 | LocVT == MVT::v4i64) { |
246 | 0 | static const MCPhysReg RegList7[] = { |
247 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 |
248 | 0 | }; |
249 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
250 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
251 | 0 | return false; |
252 | 0 | } |
253 | 0 | } |
254 | | |
255 | 0 | if (LocVT == MVT::v16f32 || |
256 | 0 | LocVT == MVT::v8f64 || |
257 | 0 | LocVT == MVT::v16i32 || |
258 | 0 | LocVT == MVT::v8i64) { |
259 | 0 | static const MCPhysReg RegList8[] = { |
260 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 |
261 | 0 | }; |
262 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
263 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
264 | 0 | return false; |
265 | 0 | } |
266 | 0 | } |
267 | | |
268 | 0 | if (LocVT == MVT::v16i1 || |
269 | 0 | LocVT == MVT::v8i1) { |
270 | 0 | if (unsigned Reg = State.AllocateReg(X86::K1)) { |
271 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
272 | 0 | return false; |
273 | 0 | } |
274 | 0 | } |
275 | | |
276 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
277 | 0 | if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
278 | 0 | return false; |
279 | 0 | } |
280 | | |
281 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
282 | 0 | if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
283 | 0 | return false; |
284 | 0 | } |
285 | | |
286 | 0 | if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
287 | 0 | return false; |
288 | | |
289 | 0 | return true; // CC didn't match. |
290 | 0 | } |
291 | | |
292 | | |
293 | | bool llvm::CC_X86(unsigned ValNo, MVT ValVT, |
294 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
295 | 42.8k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
296 | | |
297 | 42.8k | if (State.getCallingConv() == CallingConv::Intel_OCL_BI) { |
298 | 0 | if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
299 | 0 | return false; |
300 | 0 | } |
301 | | |
302 | 42.8k | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
303 | 42.8k | if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
304 | 42.8k | return false; |
305 | 42.8k | } |
306 | | |
307 | 0 | if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
308 | 0 | return false; |
309 | | |
310 | 0 | return true; // CC didn't match. |
311 | 0 | } |
312 | | |
313 | | |
314 | | static bool CC_X86_32(unsigned ValNo, MVT ValVT, |
315 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
316 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
317 | |
|
318 | 0 | if (State.getCallingConv() == CallingConv::X86_INTR) { |
319 | 0 | if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
320 | 0 | return false; |
321 | 0 | } |
322 | | |
323 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) { |
324 | 0 | if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
325 | 0 | return false; |
326 | 0 | } |
327 | | |
328 | 0 | if (State.getCallingConv() == CallingConv::X86_FastCall) { |
329 | 0 | if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
330 | 0 | return false; |
331 | 0 | } |
332 | | |
333 | 0 | if (State.getCallingConv() == CallingConv::X86_VectorCall) { |
334 | 0 | if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
335 | 0 | return false; |
336 | 0 | } |
337 | | |
338 | 0 | if (State.getCallingConv() == CallingConv::X86_ThisCall) { |
339 | 0 | if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
340 | 0 | return false; |
341 | 0 | } |
342 | | |
343 | 0 | if (State.getCallingConv() == CallingConv::CFGuard_Check) { |
344 | 0 | if (!CC_X86_Win32_CFGuard_Check(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
345 | 0 | return false; |
346 | 0 | } |
347 | | |
348 | 0 | if (State.getCallingConv() == CallingConv::Fast) { |
349 | 0 | if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
350 | 0 | return false; |
351 | 0 | } |
352 | | |
353 | 0 | if (State.getCallingConv() == CallingConv::Tail) { |
354 | 0 | if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
355 | 0 | return false; |
356 | 0 | } |
357 | | |
358 | 0 | if (State.getCallingConv() == CallingConv::GHC) { |
359 | 0 | if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
360 | 0 | return false; |
361 | 0 | } |
362 | | |
363 | 0 | if (State.getCallingConv() == CallingConv::HiPE) { |
364 | 0 | if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
365 | 0 | return false; |
366 | 0 | } |
367 | | |
368 | 0 | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
369 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin32()) { |
370 | 0 | if (State.getMachineFunction().getFunction().getParent()->getModuleFlag("RegCallv4")!=nullptr) { |
371 | 0 | if (!CC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
372 | 0 | return false; |
373 | 0 | } |
374 | 0 | } |
375 | 0 | } |
376 | | |
377 | 0 | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
378 | 0 | if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
379 | 0 | return false; |
380 | 0 | } |
381 | | |
382 | 0 | if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
383 | 0 | return false; |
384 | | |
385 | 0 | return true; // CC didn't match. |
386 | 0 | } |
387 | | |
388 | | |
389 | | static bool CC_X86_32_C(unsigned ValNo, MVT ValVT, |
390 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
391 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
392 | |
|
393 | 0 | if (LocVT == MVT::i1 || |
394 | 0 | LocVT == MVT::i8 || |
395 | 0 | LocVT == MVT::i16 || |
396 | 0 | LocVT == MVT::v1i1) { |
397 | 0 | LocVT = MVT::i32; |
398 | 0 | if (ArgFlags.isSExt()) |
399 | 0 | LocInfo = CCValAssign::SExt; |
400 | 0 | else if (ArgFlags.isZExt()) |
401 | 0 | LocInfo = CCValAssign::ZExt; |
402 | 0 | else |
403 | 0 | LocInfo = CCValAssign::AExt; |
404 | 0 | } |
405 | |
|
406 | 0 | if (ArgFlags.isNest()) { |
407 | 0 | if (unsigned Reg = State.AllocateReg(X86::ECX)) { |
408 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
409 | 0 | return false; |
410 | 0 | } |
411 | 0 | } |
412 | | |
413 | 0 | if (State.getCallingConv() == CallingConv::SwiftTail) { |
414 | 0 | if (ArgFlags.isSwiftSelf()) { |
415 | 0 | if (LocVT == MVT::i32) { |
416 | 0 | if (unsigned Reg = State.AllocateReg(X86::ECX)) { |
417 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
418 | 0 | return false; |
419 | 0 | } |
420 | 0 | } |
421 | 0 | } |
422 | 0 | } |
423 | | |
424 | 0 | if (!State.isVarArg()) { |
425 | 0 | if (ArgFlags.isInReg()) { |
426 | 0 | if (LocVT == MVT::i32) { |
427 | 0 | static const MCPhysReg RegList1[] = { |
428 | 0 | X86::EAX, X86::EDX, X86::ECX |
429 | 0 | }; |
430 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
431 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
432 | 0 | return false; |
433 | 0 | } |
434 | 0 | } |
435 | 0 | } |
436 | 0 | } |
437 | | |
438 | 0 | if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
439 | 0 | return false; |
440 | | |
441 | 0 | return true; // CC didn't match. |
442 | 0 | } |
443 | | |
444 | | |
445 | | static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT, |
446 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
447 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
448 | |
|
449 | 0 | if (ArgFlags.isByVal()) { |
450 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
451 | 0 | return false; |
452 | 0 | } |
453 | | |
454 | 0 | if (ArgFlags.isPreallocated()) { |
455 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
456 | 0 | return false; |
457 | 0 | } |
458 | | |
459 | 0 | if (!State.isVarArg()) { |
460 | 0 | if (ArgFlags.isInReg()) { |
461 | 0 | if (LocVT == MVT::f32 || |
462 | 0 | LocVT == MVT::f64) { |
463 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { |
464 | 0 | static const MCPhysReg RegList1[] = { |
465 | 0 | X86::XMM0, X86::XMM1, X86::XMM2 |
466 | 0 | }; |
467 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
468 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
469 | 0 | return false; |
470 | 0 | } |
471 | 0 | } |
472 | 0 | } |
473 | 0 | } |
474 | 0 | } |
475 | | |
476 | 0 | if (!State.isVarArg()) { |
477 | 0 | if (ArgFlags.isInReg()) { |
478 | 0 | if (LocVT == MVT::f16) { |
479 | 0 | static const MCPhysReg RegList2[] = { |
480 | 0 | X86::XMM0, X86::XMM1, X86::XMM2 |
481 | 0 | }; |
482 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
483 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
484 | 0 | return false; |
485 | 0 | } |
486 | 0 | } |
487 | 0 | } |
488 | 0 | } |
489 | | |
490 | 0 | if (!State.isVarArg()) { |
491 | 0 | if (LocVT == MVT::x86mmx) { |
492 | 0 | static const MCPhysReg RegList3[] = { |
493 | 0 | X86::MM0, X86::MM1, X86::MM2 |
494 | 0 | }; |
495 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
496 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
497 | 0 | return false; |
498 | 0 | } |
499 | 0 | } |
500 | 0 | } |
501 | | |
502 | 0 | if (LocVT == MVT::f16) { |
503 | 0 | int64_t Offset4 = State.AllocateStack(4, Align(4)); |
504 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
505 | 0 | return false; |
506 | 0 | } |
507 | | |
508 | 0 | if (LocVT == MVT::i32 || |
509 | 0 | LocVT == MVT::f32) { |
510 | 0 | int64_t Offset5 = State.AllocateStack(4, Align(4)); |
511 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); |
512 | 0 | return false; |
513 | 0 | } |
514 | | |
515 | 0 | if (LocVT == MVT::f64) { |
516 | 0 | int64_t Offset6 = State.AllocateStack(8, Align(4)); |
517 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); |
518 | 0 | return false; |
519 | 0 | } |
520 | | |
521 | 0 | if (LocVT == MVT::f80) { |
522 | 0 | int64_t Offset7 = State.AllocateStack( |
523 | 0 | State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), |
524 | 0 | State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()))); |
525 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); |
526 | 0 | return false; |
527 | 0 | } |
528 | | |
529 | 0 | if (LocVT == MVT::v2i1) { |
530 | 0 | LocVT = MVT::v2i64; |
531 | 0 | if (ArgFlags.isSExt()) |
532 | 0 | LocInfo = CCValAssign::SExt; |
533 | 0 | else if (ArgFlags.isZExt()) |
534 | 0 | LocInfo = CCValAssign::ZExt; |
535 | 0 | else |
536 | 0 | LocInfo = CCValAssign::AExt; |
537 | 0 | } |
538 | |
|
539 | 0 | if (LocVT == MVT::v4i1) { |
540 | 0 | LocVT = MVT::v4i32; |
541 | 0 | if (ArgFlags.isSExt()) |
542 | 0 | LocInfo = CCValAssign::SExt; |
543 | 0 | else if (ArgFlags.isZExt()) |
544 | 0 | LocInfo = CCValAssign::ZExt; |
545 | 0 | else |
546 | 0 | LocInfo = CCValAssign::AExt; |
547 | 0 | } |
548 | |
|
549 | 0 | if (LocVT == MVT::v8i1) { |
550 | 0 | LocVT = MVT::v8i16; |
551 | 0 | if (ArgFlags.isSExt()) |
552 | 0 | LocInfo = CCValAssign::SExt; |
553 | 0 | else if (ArgFlags.isZExt()) |
554 | 0 | LocInfo = CCValAssign::ZExt; |
555 | 0 | else |
556 | 0 | LocInfo = CCValAssign::AExt; |
557 | 0 | } |
558 | |
|
559 | 0 | if (LocVT == MVT::v16i1) { |
560 | 0 | LocVT = MVT::v16i8; |
561 | 0 | if (ArgFlags.isSExt()) |
562 | 0 | LocInfo = CCValAssign::SExt; |
563 | 0 | else if (ArgFlags.isZExt()) |
564 | 0 | LocInfo = CCValAssign::ZExt; |
565 | 0 | else |
566 | 0 | LocInfo = CCValAssign::AExt; |
567 | 0 | } |
568 | |
|
569 | 0 | if (LocVT == MVT::v32i1) { |
570 | 0 | LocVT = MVT::v32i8; |
571 | 0 | if (ArgFlags.isSExt()) |
572 | 0 | LocInfo = CCValAssign::SExt; |
573 | 0 | else if (ArgFlags.isZExt()) |
574 | 0 | LocInfo = CCValAssign::ZExt; |
575 | 0 | else |
576 | 0 | LocInfo = CCValAssign::AExt; |
577 | 0 | } |
578 | |
|
579 | 0 | if (LocVT == MVT::v64i1) { |
580 | 0 | LocVT = MVT::v64i8; |
581 | 0 | if (ArgFlags.isSExt()) |
582 | 0 | LocInfo = CCValAssign::SExt; |
583 | 0 | else if (ArgFlags.isZExt()) |
584 | 0 | LocInfo = CCValAssign::ZExt; |
585 | 0 | else |
586 | 0 | LocInfo = CCValAssign::AExt; |
587 | 0 | } |
588 | |
|
589 | 0 | if (LocVT == MVT::x86mmx) { |
590 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(4)); |
591 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
592 | 0 | return false; |
593 | 0 | } |
594 | | |
595 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) { |
596 | 0 | if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
597 | 0 | return false; |
598 | 0 | } |
599 | | |
600 | 0 | if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
601 | 0 | return false; |
602 | | |
603 | 0 | return true; // CC didn't match. |
604 | 0 | } |
605 | | |
606 | | |
607 | | static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT, |
608 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
609 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
610 | |
|
611 | 0 | if (ArgFlags.isByVal()) { |
612 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
613 | 0 | return false; |
614 | 0 | } |
615 | | |
616 | 0 | if (LocVT == MVT::i1 || |
617 | 0 | LocVT == MVT::i8 || |
618 | 0 | LocVT == MVT::i16 || |
619 | 0 | LocVT == MVT::v1i1) { |
620 | 0 | LocVT = MVT::i32; |
621 | 0 | if (ArgFlags.isSExt()) |
622 | 0 | LocInfo = CCValAssign::SExt; |
623 | 0 | else if (ArgFlags.isZExt()) |
624 | 0 | LocInfo = CCValAssign::ZExt; |
625 | 0 | else |
626 | 0 | LocInfo = CCValAssign::AExt; |
627 | 0 | } |
628 | |
|
629 | 0 | if (ArgFlags.isNest()) { |
630 | 0 | if (unsigned Reg = State.AllocateReg(X86::EAX)) { |
631 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
632 | 0 | return false; |
633 | 0 | } |
634 | 0 | } |
635 | | |
636 | 0 | if (LocVT == MVT::i32) { |
637 | 0 | static const MCPhysReg RegList1[] = { |
638 | 0 | X86::ECX, X86::EDX |
639 | 0 | }; |
640 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
641 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
642 | 0 | return false; |
643 | 0 | } |
644 | 0 | } |
645 | | |
646 | 0 | if (!State.isVarArg()) { |
647 | 0 | if (LocVT == MVT::f32 || |
648 | 0 | LocVT == MVT::f64) { |
649 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { |
650 | 0 | static const MCPhysReg RegList2[] = { |
651 | 0 | X86::XMM0, X86::XMM1, X86::XMM2 |
652 | 0 | }; |
653 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
654 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
655 | 0 | return false; |
656 | 0 | } |
657 | 0 | } |
658 | 0 | } |
659 | 0 | } |
660 | | |
661 | 0 | if (LocVT == MVT::f64) { |
662 | 0 | int64_t Offset3 = State.AllocateStack(8, Align(8)); |
663 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
664 | 0 | return false; |
665 | 0 | } |
666 | | |
667 | 0 | if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
668 | 0 | return false; |
669 | | |
670 | 0 | return true; // CC didn't match. |
671 | 0 | } |
672 | | |
673 | | |
674 | | static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT, |
675 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
676 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
677 | |
|
678 | 0 | if (LocVT == MVT::i1) { |
679 | 0 | LocVT = MVT::i8; |
680 | 0 | if (ArgFlags.isSExt()) |
681 | 0 | LocInfo = CCValAssign::SExt; |
682 | 0 | else if (ArgFlags.isZExt()) |
683 | 0 | LocInfo = CCValAssign::ZExt; |
684 | 0 | else |
685 | 0 | LocInfo = CCValAssign::AExt; |
686 | 0 | } |
687 | |
|
688 | 0 | if (ArgFlags.isNest()) { |
689 | 0 | if (unsigned Reg = State.AllocateReg(X86::EAX)) { |
690 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
691 | 0 | return false; |
692 | 0 | } |
693 | 0 | } |
694 | | |
695 | 0 | if (ArgFlags.isInReg()) { |
696 | 0 | if (LocVT == MVT::i8) { |
697 | 0 | static const MCPhysReg RegList1[] = { |
698 | 0 | X86::CL, X86::DL |
699 | 0 | }; |
700 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
701 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
702 | 0 | return false; |
703 | 0 | } |
704 | 0 | } |
705 | 0 | } |
706 | | |
707 | 0 | if (ArgFlags.isInReg()) { |
708 | 0 | if (LocVT == MVT::i16) { |
709 | 0 | static const MCPhysReg RegList2[] = { |
710 | 0 | X86::CX, X86::DX |
711 | 0 | }; |
712 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
713 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
714 | 0 | return false; |
715 | 0 | } |
716 | 0 | } |
717 | 0 | } |
718 | | |
719 | 0 | if (ArgFlags.isInReg()) { |
720 | 0 | if (LocVT == MVT::i32) { |
721 | 0 | static const MCPhysReg RegList3[] = { |
722 | 0 | X86::ECX, X86::EDX |
723 | 0 | }; |
724 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
725 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
726 | 0 | return false; |
727 | 0 | } |
728 | 0 | } |
729 | 0 | } |
730 | | |
731 | 0 | if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
732 | 0 | return false; |
733 | | |
734 | 0 | return true; // CC didn't match. |
735 | 0 | } |
736 | | |
737 | | |
738 | | static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT, |
739 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
740 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
741 | |
|
742 | 0 | if (LocVT == MVT::i8 || |
743 | 0 | LocVT == MVT::i16) { |
744 | 0 | LocVT = MVT::i32; |
745 | 0 | if (ArgFlags.isSExt()) |
746 | 0 | LocInfo = CCValAssign::SExt; |
747 | 0 | else if (ArgFlags.isZExt()) |
748 | 0 | LocInfo = CCValAssign::ZExt; |
749 | 0 | else |
750 | 0 | LocInfo = CCValAssign::AExt; |
751 | 0 | } |
752 | |
|
753 | 0 | if (LocVT == MVT::i32) { |
754 | 0 | static const MCPhysReg RegList1[] = { |
755 | 0 | X86::EBX, X86::EBP, X86::EDI, X86::ESI |
756 | 0 | }; |
757 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
758 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
759 | 0 | return false; |
760 | 0 | } |
761 | 0 | } |
762 | | |
763 | 0 | return true; // CC didn't match. |
764 | 0 | } |
765 | | |
766 | | |
767 | | static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT, |
768 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
769 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
770 | |
|
771 | 0 | if (LocVT == MVT::i8 || |
772 | 0 | LocVT == MVT::i16) { |
773 | 0 | LocVT = MVT::i32; |
774 | 0 | if (ArgFlags.isSExt()) |
775 | 0 | LocInfo = CCValAssign::SExt; |
776 | 0 | else if (ArgFlags.isZExt()) |
777 | 0 | LocInfo = CCValAssign::ZExt; |
778 | 0 | else |
779 | 0 | LocInfo = CCValAssign::AExt; |
780 | 0 | } |
781 | |
|
782 | 0 | if (LocVT == MVT::i32) { |
783 | 0 | static const MCPhysReg RegList1[] = { |
784 | 0 | X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX |
785 | 0 | }; |
786 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
787 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
788 | 0 | return false; |
789 | 0 | } |
790 | 0 | } |
791 | | |
792 | 0 | if (LocVT == MVT::i32 || |
793 | 0 | LocVT == MVT::f32) { |
794 | 0 | int64_t Offset2 = State.AllocateStack(4, Align(4)); |
795 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
796 | 0 | return false; |
797 | 0 | } |
798 | | |
799 | 0 | return true; // CC didn't match. |
800 | 0 | } |
801 | | |
802 | | |
803 | | static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT, |
804 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
805 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
806 | |
|
807 | 0 | if (ArgFlags.isByVal()) { |
808 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
809 | 0 | return false; |
810 | 0 | } |
811 | | |
812 | 0 | if (LocVT == MVT::i1 || |
813 | 0 | LocVT == MVT::i8 || |
814 | 0 | LocVT == MVT::i16 || |
815 | 0 | LocVT == MVT::v1i1) { |
816 | 0 | LocVT = MVT::i32; |
817 | 0 | if (ArgFlags.isSExt()) |
818 | 0 | LocInfo = CCValAssign::SExt; |
819 | 0 | else if (ArgFlags.isZExt()) |
820 | 0 | LocInfo = CCValAssign::ZExt; |
821 | 0 | else |
822 | 0 | LocInfo = CCValAssign::AExt; |
823 | 0 | } |
824 | |
|
825 | 0 | if (!State.isVarArg()) { |
826 | 0 | if (LocVT == MVT::i32) { |
827 | 0 | if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
828 | 0 | return false; |
829 | 0 | } |
830 | 0 | } |
831 | | |
832 | 0 | if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
833 | 0 | return false; |
834 | | |
835 | 0 | return true; // CC didn't match. |
836 | 0 | } |
837 | | |
838 | | |
839 | | static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT, |
840 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
841 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
842 | |
|
843 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
844 | 0 | if (ArgFlags.isByVal()) { |
845 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
846 | 0 | return false; |
847 | 0 | } |
848 | 0 | } |
849 | | |
850 | 0 | if (ArgFlags.isByVal()) { |
851 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
852 | 0 | return false; |
853 | 0 | } |
854 | | |
855 | 0 | if (LocVT == MVT::i1 || |
856 | 0 | LocVT == MVT::i8 || |
857 | 0 | LocVT == MVT::i16 || |
858 | 0 | LocVT == MVT::v1i1) { |
859 | 0 | LocVT = MVT::i32; |
860 | 0 | if (ArgFlags.isSExt()) |
861 | 0 | LocInfo = CCValAssign::SExt; |
862 | 0 | else if (ArgFlags.isZExt()) |
863 | 0 | LocInfo = CCValAssign::ZExt; |
864 | 0 | else |
865 | 0 | LocInfo = CCValAssign::AExt; |
866 | 0 | } |
867 | |
|
868 | 0 | if (LocVT == MVT::v8i1 || |
869 | 0 | LocVT == MVT::v16i1 || |
870 | 0 | LocVT == MVT::v32i1) { |
871 | 0 | LocVT = MVT::i32; |
872 | 0 | if (ArgFlags.isSExt()) |
873 | 0 | LocInfo = CCValAssign::SExt; |
874 | 0 | else if (ArgFlags.isZExt()) |
875 | 0 | LocInfo = CCValAssign::ZExt; |
876 | 0 | else |
877 | 0 | LocInfo = CCValAssign::AExt; |
878 | 0 | } |
879 | |
|
880 | 0 | if (LocVT == MVT::i32) { |
881 | 0 | static const MCPhysReg RegList1[] = { |
882 | 0 | X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI |
883 | 0 | }; |
884 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
885 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
886 | 0 | return false; |
887 | 0 | } |
888 | 0 | } |
889 | | |
890 | 0 | if (LocVT == MVT::i64) { |
891 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
892 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
893 | 0 | return false; |
894 | 0 | } |
895 | 0 | } |
896 | | |
897 | 0 | if (LocVT == MVT::v64i1) { |
898 | 0 | LocVT = MVT::i64; |
899 | 0 | if (ArgFlags.isSExt()) |
900 | 0 | LocInfo = CCValAssign::SExt; |
901 | 0 | else if (ArgFlags.isZExt()) |
902 | 0 | LocInfo = CCValAssign::ZExt; |
903 | 0 | else |
904 | 0 | LocInfo = CCValAssign::AExt; |
905 | 0 | } |
906 | |
|
907 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
908 | 0 | if (LocVT == MVT::i64) { |
909 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
910 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
911 | 0 | return false; |
912 | 0 | } |
913 | 0 | } |
914 | 0 | } |
915 | | |
916 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
917 | 0 | if (LocVT == MVT::i64) { |
918 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
919 | 0 | return false; |
920 | 0 | } |
921 | 0 | } |
922 | | |
923 | 0 | if (LocVT == MVT::f32 || |
924 | 0 | LocVT == MVT::f64 || |
925 | 0 | LocVT == MVT::f128) { |
926 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
927 | 0 | static const MCPhysReg RegList2[] = { |
928 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
929 | 0 | }; |
930 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
931 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
932 | 0 | return false; |
933 | 0 | } |
934 | 0 | } |
935 | 0 | } |
936 | | |
937 | 0 | if (LocVT == MVT::f80) { |
938 | 0 | if (unsigned Reg = State.AllocateReg(X86::FP0)) { |
939 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
940 | 0 | return false; |
941 | 0 | } |
942 | 0 | } |
943 | | |
944 | 0 | if (LocVT == MVT::v16i8 || |
945 | 0 | LocVT == MVT::v8i16 || |
946 | 0 | LocVT == MVT::v4i32 || |
947 | 0 | LocVT == MVT::v2i64 || |
948 | 0 | LocVT == MVT::v4f32 || |
949 | 0 | LocVT == MVT::v2f64) { |
950 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
951 | 0 | static const MCPhysReg RegList3[] = { |
952 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
953 | 0 | }; |
954 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
955 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
956 | 0 | return false; |
957 | 0 | } |
958 | 0 | } |
959 | 0 | } |
960 | | |
961 | 0 | if (LocVT == MVT::v32i8 || |
962 | 0 | LocVT == MVT::v16i16 || |
963 | 0 | LocVT == MVT::v8i32 || |
964 | 0 | LocVT == MVT::v4i64 || |
965 | 0 | LocVT == MVT::v8f32 || |
966 | 0 | LocVT == MVT::v4f64) { |
967 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
968 | 0 | static const MCPhysReg RegList4[] = { |
969 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 |
970 | 0 | }; |
971 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
972 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
973 | 0 | return false; |
974 | 0 | } |
975 | 0 | } |
976 | 0 | } |
977 | | |
978 | 0 | if (LocVT == MVT::v64i8 || |
979 | 0 | LocVT == MVT::v32i16 || |
980 | 0 | LocVT == MVT::v16i32 || |
981 | 0 | LocVT == MVT::v8i64 || |
982 | 0 | LocVT == MVT::v16f32 || |
983 | 0 | LocVT == MVT::v8f64) { |
984 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
985 | 0 | static const MCPhysReg RegList5[] = { |
986 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 |
987 | 0 | }; |
988 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
989 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
990 | 0 | return false; |
991 | 0 | } |
992 | 0 | } |
993 | 0 | } |
994 | | |
995 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
996 | 0 | if (LocVT == MVT::i32 || |
997 | 0 | LocVT == MVT::i64 || |
998 | 0 | LocVT == MVT::f32 || |
999 | 0 | LocVT == MVT::f64) { |
1000 | 0 | int64_t Offset6 = State.AllocateStack(8, Align(8)); |
1001 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); |
1002 | 0 | return false; |
1003 | 0 | } |
1004 | 0 | } |
1005 | | |
1006 | 0 | if (LocVT == MVT::i32 || |
1007 | 0 | LocVT == MVT::f32) { |
1008 | 0 | int64_t Offset7 = State.AllocateStack(4, Align(4)); |
1009 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); |
1010 | 0 | return false; |
1011 | 0 | } |
1012 | | |
1013 | 0 | if (LocVT == MVT::i64 || |
1014 | 0 | LocVT == MVT::f64) { |
1015 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(4)); |
1016 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
1017 | 0 | return false; |
1018 | 0 | } |
1019 | | |
1020 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
1021 | 0 | if (LocVT == MVT::x86mmx) { |
1022 | 0 | int64_t Offset9 = State.AllocateStack(8, Align(8)); |
1023 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
1024 | 0 | return false; |
1025 | 0 | } |
1026 | 0 | } |
1027 | | |
1028 | 0 | if (LocVT == MVT::x86mmx) { |
1029 | 0 | int64_t Offset10 = State.AllocateStack(8, Align(4)); |
1030 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); |
1031 | 0 | return false; |
1032 | 0 | } |
1033 | | |
1034 | 0 | if (LocVT == MVT::f80 || |
1035 | 0 | LocVT == MVT::f128) { |
1036 | 0 | int64_t Offset11 = State.AllocateStack( |
1037 | 0 | State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), |
1038 | 0 | State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()))); |
1039 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); |
1040 | 0 | return false; |
1041 | 0 | } |
1042 | | |
1043 | 0 | if (LocVT == MVT::v16i8 || |
1044 | 0 | LocVT == MVT::v8i16 || |
1045 | 0 | LocVT == MVT::v4i32 || |
1046 | 0 | LocVT == MVT::v2i64 || |
1047 | 0 | LocVT == MVT::v4f32 || |
1048 | 0 | LocVT == MVT::v2f64) { |
1049 | 0 | int64_t Offset12 = State.AllocateStack(16, Align(16)); |
1050 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); |
1051 | 0 | return false; |
1052 | 0 | } |
1053 | | |
1054 | 0 | if (LocVT == MVT::v32i8 || |
1055 | 0 | LocVT == MVT::v16i16 || |
1056 | 0 | LocVT == MVT::v8i32 || |
1057 | 0 | LocVT == MVT::v4i64 || |
1058 | 0 | LocVT == MVT::v8f32 || |
1059 | 0 | LocVT == MVT::v4f64) { |
1060 | 0 | int64_t Offset13 = State.AllocateStack(32, Align(32)); |
1061 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
1062 | 0 | return false; |
1063 | 0 | } |
1064 | | |
1065 | 0 | if (LocVT == MVT::v64i8 || |
1066 | 0 | LocVT == MVT::v32i16 || |
1067 | 0 | LocVT == MVT::v16i32 || |
1068 | 0 | LocVT == MVT::v8i64 || |
1069 | 0 | LocVT == MVT::v16f32 || |
1070 | 0 | LocVT == MVT::v8f64) { |
1071 | 0 | int64_t Offset14 = State.AllocateStack(64, Align(64)); |
1072 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); |
1073 | 0 | return false; |
1074 | 0 | } |
1075 | | |
1076 | 0 | return true; // CC didn't match. |
1077 | 0 | } |
1078 | | |
1079 | | |
1080 | | static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT, |
1081 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1082 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1083 | |
|
1084 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
1085 | 0 | if (ArgFlags.isByVal()) { |
1086 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
1087 | 0 | return false; |
1088 | 0 | } |
1089 | 0 | } |
1090 | | |
1091 | 0 | if (ArgFlags.isByVal()) { |
1092 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
1093 | 0 | return false; |
1094 | 0 | } |
1095 | | |
1096 | 0 | if (LocVT == MVT::i1 || |
1097 | 0 | LocVT == MVT::i8 || |
1098 | 0 | LocVT == MVT::i16 || |
1099 | 0 | LocVT == MVT::v1i1) { |
1100 | 0 | LocVT = MVT::i32; |
1101 | 0 | if (ArgFlags.isSExt()) |
1102 | 0 | LocInfo = CCValAssign::SExt; |
1103 | 0 | else if (ArgFlags.isZExt()) |
1104 | 0 | LocInfo = CCValAssign::ZExt; |
1105 | 0 | else |
1106 | 0 | LocInfo = CCValAssign::AExt; |
1107 | 0 | } |
1108 | |
|
1109 | 0 | if (LocVT == MVT::v8i1 || |
1110 | 0 | LocVT == MVT::v16i1 || |
1111 | 0 | LocVT == MVT::v32i1) { |
1112 | 0 | LocVT = MVT::i32; |
1113 | 0 | if (ArgFlags.isSExt()) |
1114 | 0 | LocInfo = CCValAssign::SExt; |
1115 | 0 | else if (ArgFlags.isZExt()) |
1116 | 0 | LocInfo = CCValAssign::ZExt; |
1117 | 0 | else |
1118 | 0 | LocInfo = CCValAssign::AExt; |
1119 | 0 | } |
1120 | |
|
1121 | 0 | if (LocVT == MVT::i32) { |
1122 | 0 | static const MCPhysReg RegList1[] = { |
1123 | 0 | X86::ECX, X86::EDX, X86::EDI, X86::ESI |
1124 | 0 | }; |
1125 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
1126 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1127 | 0 | return false; |
1128 | 0 | } |
1129 | 0 | } |
1130 | | |
1131 | 0 | if (LocVT == MVT::i64) { |
1132 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
1133 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1134 | 0 | return false; |
1135 | 0 | } |
1136 | 0 | } |
1137 | | |
1138 | 0 | if (LocVT == MVT::v64i1) { |
1139 | 0 | LocVT = MVT::i64; |
1140 | 0 | if (ArgFlags.isSExt()) |
1141 | 0 | LocInfo = CCValAssign::SExt; |
1142 | 0 | else if (ArgFlags.isZExt()) |
1143 | 0 | LocInfo = CCValAssign::ZExt; |
1144 | 0 | else |
1145 | 0 | LocInfo = CCValAssign::AExt; |
1146 | 0 | } |
1147 | |
|
1148 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
1149 | 0 | if (LocVT == MVT::i64) { |
1150 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
1151 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1152 | 0 | return false; |
1153 | 0 | } |
1154 | 0 | } |
1155 | 0 | } |
1156 | | |
1157 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
1158 | 0 | if (LocVT == MVT::i64) { |
1159 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1160 | 0 | return false; |
1161 | 0 | } |
1162 | 0 | } |
1163 | | |
1164 | 0 | if (LocVT == MVT::f32 || |
1165 | 0 | LocVT == MVT::f64 || |
1166 | 0 | LocVT == MVT::f128) { |
1167 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
1168 | 0 | static const MCPhysReg RegList2[] = { |
1169 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
1170 | 0 | }; |
1171 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
1172 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1173 | 0 | return false; |
1174 | 0 | } |
1175 | 0 | } |
1176 | 0 | } |
1177 | | |
1178 | 0 | if (LocVT == MVT::f80) { |
1179 | 0 | if (unsigned Reg = State.AllocateReg(X86::FP0)) { |
1180 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1181 | 0 | return false; |
1182 | 0 | } |
1183 | 0 | } |
1184 | | |
1185 | 0 | if (LocVT == MVT::v16i8 || |
1186 | 0 | LocVT == MVT::v8i16 || |
1187 | 0 | LocVT == MVT::v4i32 || |
1188 | 0 | LocVT == MVT::v2i64 || |
1189 | 0 | LocVT == MVT::v4f32 || |
1190 | 0 | LocVT == MVT::v2f64) { |
1191 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
1192 | 0 | static const MCPhysReg RegList3[] = { |
1193 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
1194 | 0 | }; |
1195 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
1196 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1197 | 0 | return false; |
1198 | 0 | } |
1199 | 0 | } |
1200 | 0 | } |
1201 | | |
1202 | 0 | if (LocVT == MVT::v32i8 || |
1203 | 0 | LocVT == MVT::v16i16 || |
1204 | 0 | LocVT == MVT::v8i32 || |
1205 | 0 | LocVT == MVT::v4i64 || |
1206 | 0 | LocVT == MVT::v8f32 || |
1207 | 0 | LocVT == MVT::v4f64) { |
1208 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
1209 | 0 | static const MCPhysReg RegList4[] = { |
1210 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 |
1211 | 0 | }; |
1212 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
1213 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1214 | 0 | return false; |
1215 | 0 | } |
1216 | 0 | } |
1217 | 0 | } |
1218 | | |
1219 | 0 | if (LocVT == MVT::v64i8 || |
1220 | 0 | LocVT == MVT::v32i16 || |
1221 | 0 | LocVT == MVT::v16i32 || |
1222 | 0 | LocVT == MVT::v8i64 || |
1223 | 0 | LocVT == MVT::v16f32 || |
1224 | 0 | LocVT == MVT::v8f64) { |
1225 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
1226 | 0 | static const MCPhysReg RegList5[] = { |
1227 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 |
1228 | 0 | }; |
1229 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
1230 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1231 | 0 | return false; |
1232 | 0 | } |
1233 | 0 | } |
1234 | 0 | } |
1235 | | |
1236 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
1237 | 0 | if (LocVT == MVT::i32 || |
1238 | 0 | LocVT == MVT::i64 || |
1239 | 0 | LocVT == MVT::f32 || |
1240 | 0 | LocVT == MVT::f64) { |
1241 | 0 | int64_t Offset6 = State.AllocateStack(8, Align(8)); |
1242 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); |
1243 | 0 | return false; |
1244 | 0 | } |
1245 | 0 | } |
1246 | | |
1247 | 0 | if (LocVT == MVT::i32 || |
1248 | 0 | LocVT == MVT::f32) { |
1249 | 0 | int64_t Offset7 = State.AllocateStack(4, Align(4)); |
1250 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); |
1251 | 0 | return false; |
1252 | 0 | } |
1253 | | |
1254 | 0 | if (LocVT == MVT::i64 || |
1255 | 0 | LocVT == MVT::f64) { |
1256 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(4)); |
1257 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
1258 | 0 | return false; |
1259 | 0 | } |
1260 | | |
1261 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
1262 | 0 | if (LocVT == MVT::x86mmx) { |
1263 | 0 | int64_t Offset9 = State.AllocateStack(8, Align(8)); |
1264 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
1265 | 0 | return false; |
1266 | 0 | } |
1267 | 0 | } |
1268 | | |
1269 | 0 | if (LocVT == MVT::x86mmx) { |
1270 | 0 | int64_t Offset10 = State.AllocateStack(8, Align(4)); |
1271 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); |
1272 | 0 | return false; |
1273 | 0 | } |
1274 | | |
1275 | 0 | if (LocVT == MVT::f80 || |
1276 | 0 | LocVT == MVT::f128) { |
1277 | 0 | int64_t Offset11 = State.AllocateStack( |
1278 | 0 | State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), |
1279 | 0 | State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()))); |
1280 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); |
1281 | 0 | return false; |
1282 | 0 | } |
1283 | | |
1284 | 0 | if (LocVT == MVT::v16i8 || |
1285 | 0 | LocVT == MVT::v8i16 || |
1286 | 0 | LocVT == MVT::v4i32 || |
1287 | 0 | LocVT == MVT::v2i64 || |
1288 | 0 | LocVT == MVT::v4f32 || |
1289 | 0 | LocVT == MVT::v2f64) { |
1290 | 0 | int64_t Offset12 = State.AllocateStack(16, Align(16)); |
1291 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); |
1292 | 0 | return false; |
1293 | 0 | } |
1294 | | |
1295 | 0 | if (LocVT == MVT::v32i8 || |
1296 | 0 | LocVT == MVT::v16i16 || |
1297 | 0 | LocVT == MVT::v8i32 || |
1298 | 0 | LocVT == MVT::v4i64 || |
1299 | 0 | LocVT == MVT::v8f32 || |
1300 | 0 | LocVT == MVT::v4f64) { |
1301 | 0 | int64_t Offset13 = State.AllocateStack(32, Align(32)); |
1302 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
1303 | 0 | return false; |
1304 | 0 | } |
1305 | | |
1306 | 0 | if (LocVT == MVT::v64i8 || |
1307 | 0 | LocVT == MVT::v32i16 || |
1308 | 0 | LocVT == MVT::v16i32 || |
1309 | 0 | LocVT == MVT::v8i64 || |
1310 | 0 | LocVT == MVT::v16f32 || |
1311 | 0 | LocVT == MVT::v8f64) { |
1312 | 0 | int64_t Offset14 = State.AllocateStack(64, Align(64)); |
1313 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); |
1314 | 0 | return false; |
1315 | 0 | } |
1316 | | |
1317 | 0 | return true; // CC didn't match. |
1318 | 0 | } |
1319 | | |
1320 | | |
1321 | | static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT, |
1322 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1323 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1324 | |
|
1325 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) { |
1326 | 0 | if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1327 | 0 | return false; |
1328 | 0 | } |
1329 | | |
1330 | 0 | if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1331 | 0 | return false; |
1332 | | |
1333 | 0 | return true; // CC didn't match. |
1334 | 0 | } |
1335 | | |
1336 | | |
1337 | | static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT, |
1338 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1339 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1340 | |
|
1341 | 0 | if (LocVT == MVT::i32) { |
1342 | 0 | if (unsigned Reg = State.AllocateReg(X86::ECX)) { |
1343 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1344 | 0 | return false; |
1345 | 0 | } |
1346 | 0 | } |
1347 | | |
1348 | 0 | if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1349 | 0 | return false; |
1350 | | |
1351 | 0 | return true; // CC didn't match. |
1352 | 0 | } |
1353 | | |
1354 | | |
1355 | | static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT, |
1356 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1357 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1358 | |
|
1359 | 0 | if (LocVT == MVT::i1 || |
1360 | 0 | LocVT == MVT::i8 || |
1361 | 0 | LocVT == MVT::i16 || |
1362 | 0 | LocVT == MVT::v1i1) { |
1363 | 0 | LocVT = MVT::i32; |
1364 | 0 | if (ArgFlags.isSExt()) |
1365 | 0 | LocInfo = CCValAssign::SExt; |
1366 | 0 | else if (ArgFlags.isZExt()) |
1367 | 0 | LocInfo = CCValAssign::ZExt; |
1368 | 0 | else |
1369 | 0 | LocInfo = CCValAssign::AExt; |
1370 | 0 | } |
1371 | |
|
1372 | 0 | if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1373 | 0 | return false; |
1374 | | |
1375 | 0 | return true; // CC didn't match. |
1376 | 0 | } |
1377 | | |
1378 | | |
1379 | | static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT, |
1380 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1381 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1382 | |
|
1383 | 0 | if (LocVT == MVT::i1 || |
1384 | 0 | LocVT == MVT::i8 || |
1385 | 0 | LocVT == MVT::i16 || |
1386 | 0 | LocVT == MVT::v1i1) { |
1387 | 0 | LocVT = MVT::i32; |
1388 | 0 | if (ArgFlags.isSExt()) |
1389 | 0 | LocInfo = CCValAssign::SExt; |
1390 | 0 | else if (ArgFlags.isZExt()) |
1391 | 0 | LocInfo = CCValAssign::ZExt; |
1392 | 0 | else |
1393 | 0 | LocInfo = CCValAssign::AExt; |
1394 | 0 | } |
1395 | |
|
1396 | 0 | if (ArgFlags.isSRet()) { |
1397 | 0 | int64_t Offset1 = State.AllocateStack(4, Align(4)); |
1398 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); |
1399 | 0 | return false; |
1400 | 0 | } |
1401 | | |
1402 | 0 | if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1403 | 0 | return false; |
1404 | | |
1405 | 0 | return true; // CC didn't match. |
1406 | 0 | } |
1407 | | |
1408 | | |
1409 | | static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT, |
1410 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1411 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1412 | |
|
1413 | 0 | if (LocVT == MVT::v16i8 || |
1414 | 0 | LocVT == MVT::v8i16 || |
1415 | 0 | LocVT == MVT::v4i32 || |
1416 | 0 | LocVT == MVT::v2i64 || |
1417 | 0 | LocVT == MVT::v8f16 || |
1418 | 0 | LocVT == MVT::v4f32 || |
1419 | 0 | LocVT == MVT::v2f64) { |
1420 | 0 | int64_t Offset1 = State.AllocateStack(16, Align(16)); |
1421 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); |
1422 | 0 | return false; |
1423 | 0 | } |
1424 | | |
1425 | 0 | if (LocVT == MVT::v32i8 || |
1426 | 0 | LocVT == MVT::v16i16 || |
1427 | 0 | LocVT == MVT::v8i32 || |
1428 | 0 | LocVT == MVT::v4i64 || |
1429 | 0 | LocVT == MVT::v16f16 || |
1430 | 0 | LocVT == MVT::v8f32 || |
1431 | 0 | LocVT == MVT::v4f64) { |
1432 | 0 | int64_t Offset2 = State.AllocateStack(32, Align(32)); |
1433 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
1434 | 0 | return false; |
1435 | 0 | } |
1436 | | |
1437 | 0 | if (LocVT == MVT::v64i8 || |
1438 | 0 | LocVT == MVT::v32i16 || |
1439 | 0 | LocVT == MVT::v16i32 || |
1440 | 0 | LocVT == MVT::v8i64 || |
1441 | 0 | LocVT == MVT::v32f16 || |
1442 | 0 | LocVT == MVT::v16f32 || |
1443 | 0 | LocVT == MVT::v8f64) { |
1444 | 0 | int64_t Offset3 = State.AllocateStack(64, Align(64)); |
1445 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
1446 | 0 | return false; |
1447 | 0 | } |
1448 | | |
1449 | 0 | return true; // CC didn't match. |
1450 | 0 | } |
1451 | | |
1452 | | |
1453 | | static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT, |
1454 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1455 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1456 | |
|
1457 | 0 | if (!State.isVarArg()) { |
1458 | 0 | if (LocVT == MVT::v16i8 || |
1459 | 0 | LocVT == MVT::v8i16 || |
1460 | 0 | LocVT == MVT::v4i32 || |
1461 | 0 | LocVT == MVT::v2i64 || |
1462 | 0 | LocVT == MVT::v8f16 || |
1463 | 0 | LocVT == MVT::v4f32 || |
1464 | 0 | LocVT == MVT::v2f64) { |
1465 | 0 | static const MCPhysReg RegList1[] = { |
1466 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
1467 | 0 | }; |
1468 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
1469 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1470 | 0 | return false; |
1471 | 0 | } |
1472 | 0 | } |
1473 | 0 | } |
1474 | | |
1475 | 0 | if (!State.isVarArg()) { |
1476 | 0 | if (LocVT == MVT::v32i8 || |
1477 | 0 | LocVT == MVT::v16i16 || |
1478 | 0 | LocVT == MVT::v8i32 || |
1479 | 0 | LocVT == MVT::v4i64 || |
1480 | 0 | LocVT == MVT::v16f16 || |
1481 | 0 | LocVT == MVT::v8f32 || |
1482 | 0 | LocVT == MVT::v4f64) { |
1483 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
1484 | 0 | static const MCPhysReg RegList2[] = { |
1485 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 |
1486 | 0 | }; |
1487 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
1488 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1489 | 0 | return false; |
1490 | 0 | } |
1491 | 0 | } |
1492 | 0 | } |
1493 | 0 | } |
1494 | | |
1495 | 0 | if (!State.isVarArg()) { |
1496 | 0 | if (LocVT == MVT::v64i8 || |
1497 | 0 | LocVT == MVT::v32i16 || |
1498 | 0 | LocVT == MVT::v16i32 || |
1499 | 0 | LocVT == MVT::v8i64 || |
1500 | 0 | LocVT == MVT::v32f16 || |
1501 | 0 | LocVT == MVT::v16f32 || |
1502 | 0 | LocVT == MVT::v8f64) { |
1503 | 0 | static const MCPhysReg RegList3[] = { |
1504 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 |
1505 | 0 | }; |
1506 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
1507 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1508 | 0 | return false; |
1509 | 0 | } |
1510 | 0 | } |
1511 | 0 | } |
1512 | | |
1513 | 0 | if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1514 | 0 | return false; |
1515 | | |
1516 | 0 | return true; // CC didn't match. |
1517 | 0 | } |
1518 | | |
1519 | | |
1520 | | static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT, |
1521 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1522 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1523 | |
|
1524 | 0 | if (!State.isVarArg()) { |
1525 | 0 | if (LocVT == MVT::v16i8 || |
1526 | 0 | LocVT == MVT::v8i16 || |
1527 | 0 | LocVT == MVT::v4i32 || |
1528 | 0 | LocVT == MVT::v2i64 || |
1529 | 0 | LocVT == MVT::v8f16 || |
1530 | 0 | LocVT == MVT::v4f32 || |
1531 | 0 | LocVT == MVT::v2f64) { |
1532 | 0 | static const MCPhysReg RegList1[] = { |
1533 | 0 | X86::XMM0, X86::XMM1, X86::XMM2 |
1534 | 0 | }; |
1535 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
1536 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1537 | 0 | return false; |
1538 | 0 | } |
1539 | 0 | } |
1540 | 0 | } |
1541 | | |
1542 | 0 | if (!State.isVarArg()) { |
1543 | 0 | if (LocVT == MVT::v32i8 || |
1544 | 0 | LocVT == MVT::v16i16 || |
1545 | 0 | LocVT == MVT::v8i32 || |
1546 | 0 | LocVT == MVT::v4i64 || |
1547 | 0 | LocVT == MVT::v16f16 || |
1548 | 0 | LocVT == MVT::v8f32 || |
1549 | 0 | LocVT == MVT::v4f64) { |
1550 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
1551 | 0 | static const MCPhysReg RegList2[] = { |
1552 | 0 | X86::YMM0, X86::YMM1, X86::YMM2 |
1553 | 0 | }; |
1554 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
1555 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1556 | 0 | return false; |
1557 | 0 | } |
1558 | 0 | } |
1559 | 0 | } |
1560 | 0 | } |
1561 | | |
1562 | 0 | if (!State.isVarArg()) { |
1563 | 0 | if (LocVT == MVT::v64i8 || |
1564 | 0 | LocVT == MVT::v32i16 || |
1565 | 0 | LocVT == MVT::v16i32 || |
1566 | 0 | LocVT == MVT::v8i64 || |
1567 | 0 | LocVT == MVT::v32f16 || |
1568 | 0 | LocVT == MVT::v16f32 || |
1569 | 0 | LocVT == MVT::v8f64) { |
1570 | 0 | static const MCPhysReg RegList3[] = { |
1571 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2 |
1572 | 0 | }; |
1573 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
1574 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1575 | 0 | return false; |
1576 | 0 | } |
1577 | 0 | } |
1578 | 0 | } |
1579 | | |
1580 | 0 | if (State.isVarArg() && State.getMachineFunction().getSubtarget().getTargetTriple().isWindowsMSVCEnvironment()) { |
1581 | 0 | if (!CC_X86_Win32_Vector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1582 | 0 | return false; |
1583 | 0 | } |
1584 | | |
1585 | 0 | if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1586 | 0 | return false; |
1587 | | |
1588 | 0 | return true; // CC didn't match. |
1589 | 0 | } |
1590 | | |
1591 | | |
1592 | | static bool CC_X86_64(unsigned ValNo, MVT ValVT, |
1593 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1594 | 42.8k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1595 | | |
1596 | 42.8k | if (State.getCallingConv() == CallingConv::GHC) { |
1597 | 0 | if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1598 | 0 | return false; |
1599 | 0 | } |
1600 | | |
1601 | 42.8k | if (State.getCallingConv() == CallingConv::HiPE) { |
1602 | 0 | if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1603 | 0 | return false; |
1604 | 0 | } |
1605 | | |
1606 | 42.8k | if (State.getCallingConv() == CallingConv::AnyReg) { |
1607 | 0 | if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1608 | 0 | return false; |
1609 | 0 | } |
1610 | | |
1611 | 42.8k | if (State.getCallingConv() == CallingConv::Win64) { |
1612 | 0 | if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1613 | 0 | return false; |
1614 | 0 | } |
1615 | | |
1616 | 42.8k | if (State.getCallingConv() == CallingConv::X86_64_SysV) { |
1617 | 0 | if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1618 | 0 | return false; |
1619 | 0 | } |
1620 | | |
1621 | 42.8k | if (State.getCallingConv() == CallingConv::X86_VectorCall) { |
1622 | 0 | if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1623 | 0 | return false; |
1624 | 0 | } |
1625 | | |
1626 | 42.8k | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
1627 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
1628 | 0 | if (State.getMachineFunction().getFunction().getParent()->getModuleFlag("RegCallv4")!=nullptr) { |
1629 | 0 | if (!CC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1630 | 0 | return false; |
1631 | 0 | } |
1632 | 0 | } |
1633 | 0 | } |
1634 | | |
1635 | 42.8k | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
1636 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
1637 | 0 | if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1638 | 0 | return false; |
1639 | 0 | } |
1640 | 0 | } |
1641 | | |
1642 | 42.8k | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
1643 | 0 | if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1644 | 0 | return false; |
1645 | 0 | } |
1646 | | |
1647 | 42.8k | if (State.getCallingConv() == CallingConv::X86_INTR) { |
1648 | 0 | if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1649 | 0 | return false; |
1650 | 0 | } |
1651 | | |
1652 | 42.8k | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
1653 | 0 | if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1654 | 0 | return false; |
1655 | 0 | } |
1656 | | |
1657 | 42.8k | if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1658 | 42.8k | return false; |
1659 | | |
1660 | 0 | return true; // CC didn't match. |
1661 | 42.8k | } |
1662 | | |
1663 | | |
1664 | | static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, |
1665 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1666 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1667 | |
|
1668 | 0 | if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1669 | 0 | return false; |
1670 | | |
1671 | 0 | return true; // CC didn't match. |
1672 | 0 | } |
1673 | | |
1674 | | |
1675 | | static bool CC_X86_64_C(unsigned ValNo, MVT ValVT, |
1676 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1677 | 42.8k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1678 | | |
1679 | 42.8k | if (ArgFlags.isByVal()) { |
1680 | 3 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
1681 | 3 | return false; |
1682 | 3 | } |
1683 | | |
1684 | 42.8k | if (LocVT == MVT::i1 || |
1685 | 42.8k | LocVT == MVT::i8 || |
1686 | 42.8k | LocVT == MVT::i16 || |
1687 | 42.8k | LocVT == MVT::v1i1) { |
1688 | 7.39k | LocVT = MVT::i32; |
1689 | 7.39k | if (ArgFlags.isSExt()) |
1690 | 36 | LocInfo = CCValAssign::SExt; |
1691 | 7.35k | else if (ArgFlags.isZExt()) |
1692 | 98 | LocInfo = CCValAssign::ZExt; |
1693 | 7.25k | else |
1694 | 7.25k | LocInfo = CCValAssign::AExt; |
1695 | 7.39k | } |
1696 | | |
1697 | 42.8k | if (ArgFlags.isNest()) { |
1698 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) { |
1699 | 0 | if (unsigned Reg = State.AllocateReg(X86::R10D)) { |
1700 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1701 | 0 | return false; |
1702 | 0 | } |
1703 | 0 | } |
1704 | 0 | } |
1705 | | |
1706 | 42.8k | if (ArgFlags.isNest()) { |
1707 | 0 | if (unsigned Reg = State.AllocateReg(X86::R10)) { |
1708 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1709 | 0 | return false; |
1710 | 0 | } |
1711 | 0 | } |
1712 | | |
1713 | 42.8k | if (ArgFlags.isSwiftSelf()) { |
1714 | 0 | if (LocVT == MVT::i64) { |
1715 | 0 | if (unsigned Reg = State.AllocateReg(X86::R13)) { |
1716 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1717 | 0 | return false; |
1718 | 0 | } |
1719 | 0 | } |
1720 | 0 | } |
1721 | | |
1722 | 42.8k | if (ArgFlags.isSwiftError()) { |
1723 | 0 | if (LocVT == MVT::i64) { |
1724 | 0 | if (unsigned Reg = State.AllocateReg(X86::R12)) { |
1725 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1726 | 0 | return false; |
1727 | 0 | } |
1728 | 0 | } |
1729 | 0 | } |
1730 | | |
1731 | 42.8k | if (ArgFlags.isSwiftAsync()) { |
1732 | 0 | if (LocVT == MVT::i64) { |
1733 | 0 | if (unsigned Reg = State.AllocateReg(X86::R14)) { |
1734 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1735 | 0 | return false; |
1736 | 0 | } |
1737 | 0 | } |
1738 | 0 | } |
1739 | | |
1740 | 42.8k | if (State.getCallingConv() == CallingConv::Swift) { |
1741 | 0 | if (ArgFlags.isSRet()) { |
1742 | 0 | if (LocVT == MVT::i64) { |
1743 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
1744 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1745 | 0 | return false; |
1746 | 0 | } |
1747 | 0 | } |
1748 | 0 | } |
1749 | 0 | } |
1750 | | |
1751 | 42.8k | if (State.getCallingConv() == CallingConv::SwiftTail) { |
1752 | 0 | if (ArgFlags.isSRet()) { |
1753 | 0 | if (LocVT == MVT::i64) { |
1754 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
1755 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1756 | 0 | return false; |
1757 | 0 | } |
1758 | 0 | } |
1759 | 0 | } |
1760 | 0 | } |
1761 | | |
1762 | 42.8k | if (ArgFlags.isPointer()) { |
1763 | 7.34k | if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1764 | 0 | return false; |
1765 | 7.34k | } |
1766 | | |
1767 | 42.8k | if (LocVT == MVT::i32) { |
1768 | 16.8k | static const MCPhysReg RegList1[] = { |
1769 | 16.8k | X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D |
1770 | 16.8k | }; |
1771 | 16.8k | if (unsigned Reg = State.AllocateReg(RegList1)) { |
1772 | 16.8k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1773 | 16.8k | return false; |
1774 | 16.8k | } |
1775 | 16.8k | } |
1776 | | |
1777 | 25.9k | if (LocVT == MVT::i64) { |
1778 | 10.5k | if (ArgFlags.isSplit()) { |
1779 | 450 | static const MCPhysReg RegList2[] = { |
1780 | 450 | X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 |
1781 | 450 | }; |
1782 | 450 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
1783 | 435 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1784 | 435 | return false; |
1785 | 435 | } |
1786 | 450 | } |
1787 | 10.5k | } |
1788 | | |
1789 | 25.5k | if (LocVT == MVT::i64) { |
1790 | 10.1k | if (ArgFlags.isSplit()) { |
1791 | 15 | static const MCPhysReg ShadowRegList3[] = { |
1792 | 15 | X86::R9 |
1793 | 15 | }; |
1794 | 15 | int64_t Offset4 = State.AllocateStack(8, Align(16), ShadowRegList3); |
1795 | 15 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
1796 | 15 | return false; |
1797 | 15 | } |
1798 | 10.1k | } |
1799 | | |
1800 | 25.5k | if (LocVT == MVT::i64) { |
1801 | 10.1k | static const MCPhysReg RegList5[] = { |
1802 | 10.1k | X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 |
1803 | 10.1k | }; |
1804 | 10.1k | if (unsigned Reg = State.AllocateReg(RegList5)) { |
1805 | 9.63k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1806 | 9.63k | return false; |
1807 | 9.63k | } |
1808 | 10.1k | } |
1809 | | |
1810 | 15.9k | if (LocVT == MVT::x86mmx) { |
1811 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) { |
1812 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { |
1813 | 0 | LocVT = MVT::v2i64; |
1814 | 0 | if (ArgFlags.isSExt()) |
1815 | 0 | LocInfo = CCValAssign::SExt; |
1816 | 0 | else if (ArgFlags.isZExt()) |
1817 | 0 | LocInfo = CCValAssign::ZExt; |
1818 | 0 | else |
1819 | 0 | LocInfo = CCValAssign::AExt; |
1820 | 0 | } |
1821 | 0 | } |
1822 | 0 | } |
1823 | | |
1824 | 15.9k | if (LocVT == MVT::v2i1) { |
1825 | 0 | LocVT = MVT::v2i64; |
1826 | 0 | if (ArgFlags.isSExt()) |
1827 | 0 | LocInfo = CCValAssign::SExt; |
1828 | 0 | else if (ArgFlags.isZExt()) |
1829 | 0 | LocInfo = CCValAssign::ZExt; |
1830 | 0 | else |
1831 | 0 | LocInfo = CCValAssign::AExt; |
1832 | 0 | } |
1833 | | |
1834 | 15.9k | if (LocVT == MVT::v4i1) { |
1835 | 0 | LocVT = MVT::v4i32; |
1836 | 0 | if (ArgFlags.isSExt()) |
1837 | 0 | LocInfo = CCValAssign::SExt; |
1838 | 0 | else if (ArgFlags.isZExt()) |
1839 | 0 | LocInfo = CCValAssign::ZExt; |
1840 | 0 | else |
1841 | 0 | LocInfo = CCValAssign::AExt; |
1842 | 0 | } |
1843 | | |
1844 | 15.9k | if (LocVT == MVT::v8i1) { |
1845 | 0 | LocVT = MVT::v8i16; |
1846 | 0 | if (ArgFlags.isSExt()) |
1847 | 0 | LocInfo = CCValAssign::SExt; |
1848 | 0 | else if (ArgFlags.isZExt()) |
1849 | 0 | LocInfo = CCValAssign::ZExt; |
1850 | 0 | else |
1851 | 0 | LocInfo = CCValAssign::AExt; |
1852 | 0 | } |
1853 | | |
1854 | 15.9k | if (LocVT == MVT::v16i1) { |
1855 | 0 | LocVT = MVT::v16i8; |
1856 | 0 | if (ArgFlags.isSExt()) |
1857 | 0 | LocInfo = CCValAssign::SExt; |
1858 | 0 | else if (ArgFlags.isZExt()) |
1859 | 0 | LocInfo = CCValAssign::ZExt; |
1860 | 0 | else |
1861 | 0 | LocInfo = CCValAssign::AExt; |
1862 | 0 | } |
1863 | | |
1864 | 15.9k | if (LocVT == MVT::v32i1) { |
1865 | 0 | LocVT = MVT::v32i8; |
1866 | 0 | if (ArgFlags.isSExt()) |
1867 | 0 | LocInfo = CCValAssign::SExt; |
1868 | 0 | else if (ArgFlags.isZExt()) |
1869 | 0 | LocInfo = CCValAssign::ZExt; |
1870 | 0 | else |
1871 | 0 | LocInfo = CCValAssign::AExt; |
1872 | 0 | } |
1873 | | |
1874 | 15.9k | if (LocVT == MVT::v64i1) { |
1875 | 0 | LocVT = MVT::v64i8; |
1876 | 0 | if (ArgFlags.isSExt()) |
1877 | 0 | LocInfo = CCValAssign::SExt; |
1878 | 0 | else if (ArgFlags.isZExt()) |
1879 | 0 | LocInfo = CCValAssign::ZExt; |
1880 | 0 | else |
1881 | 0 | LocInfo = CCValAssign::AExt; |
1882 | 0 | } |
1883 | | |
1884 | 15.9k | if (LocVT == MVT::f16 || |
1885 | 15.9k | LocVT == MVT::f32 || |
1886 | 15.9k | LocVT == MVT::f64 || |
1887 | 15.9k | LocVT == MVT::f128 || |
1888 | 15.9k | LocVT == MVT::v16i8 || |
1889 | 15.9k | LocVT == MVT::v8i16 || |
1890 | 15.9k | LocVT == MVT::v4i32 || |
1891 | 15.9k | LocVT == MVT::v2i64 || |
1892 | 15.9k | LocVT == MVT::v8f16 || |
1893 | 15.9k | LocVT == MVT::v4f32 || |
1894 | 15.9k | LocVT == MVT::v2f64) { |
1895 | 15.2k | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
1896 | 15.2k | static const MCPhysReg RegList6[] = { |
1897 | 15.2k | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
1898 | 15.2k | }; |
1899 | 15.2k | if (unsigned Reg = State.AllocateReg(RegList6)) { |
1900 | 15.1k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1901 | 15.1k | return false; |
1902 | 15.1k | } |
1903 | 15.2k | } |
1904 | 15.2k | } |
1905 | | |
1906 | 754 | if (!State.isVarArg()) { |
1907 | 754 | if (LocVT == MVT::v32i8 || |
1908 | 754 | LocVT == MVT::v16i16 || |
1909 | 754 | LocVT == MVT::v8i32 || |
1910 | 754 | LocVT == MVT::v4i64 || |
1911 | 754 | LocVT == MVT::v16f16 || |
1912 | 754 | LocVT == MVT::v8f32 || |
1913 | 754 | LocVT == MVT::v4f64) { |
1914 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
1915 | 0 | static const MCPhysReg RegList7[] = { |
1916 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 |
1917 | 0 | }; |
1918 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
1919 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1920 | 0 | return false; |
1921 | 0 | } |
1922 | 0 | } |
1923 | 0 | } |
1924 | 754 | } |
1925 | | |
1926 | 754 | if (!State.isVarArg()) { |
1927 | 754 | if (LocVT == MVT::v64i8 || |
1928 | 754 | LocVT == MVT::v32i16 || |
1929 | 754 | LocVT == MVT::v16i32 || |
1930 | 754 | LocVT == MVT::v8i64 || |
1931 | 754 | LocVT == MVT::v32f16 || |
1932 | 754 | LocVT == MVT::v16f32 || |
1933 | 754 | LocVT == MVT::v8f64) { |
1934 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
1935 | 0 | static const MCPhysReg RegList8[] = { |
1936 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 |
1937 | 0 | }; |
1938 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
1939 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1940 | 0 | return false; |
1941 | 0 | } |
1942 | 0 | } |
1943 | 0 | } |
1944 | 754 | } |
1945 | | |
1946 | 754 | if (LocVT == MVT::i32 || |
1947 | 754 | LocVT == MVT::i64 || |
1948 | 754 | LocVT == MVT::f16 || |
1949 | 754 | LocVT == MVT::f32 || |
1950 | 754 | LocVT == MVT::f64) { |
1951 | 570 | int64_t Offset9 = State.AllocateStack(8, Align(8)); |
1952 | 570 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
1953 | 570 | return false; |
1954 | 570 | } |
1955 | | |
1956 | 184 | if (LocVT == MVT::f80 || |
1957 | 184 | LocVT == MVT::f128) { |
1958 | 40 | int64_t Offset10 = State.AllocateStack( |
1959 | 40 | State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), |
1960 | 40 | State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()))); |
1961 | 40 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); |
1962 | 40 | return false; |
1963 | 40 | } |
1964 | | |
1965 | 144 | if (LocVT == MVT::v16i8 || |
1966 | 144 | LocVT == MVT::v8i16 || |
1967 | 144 | LocVT == MVT::v4i32 || |
1968 | 144 | LocVT == MVT::v2i64 || |
1969 | 144 | LocVT == MVT::v8f16 || |
1970 | 144 | LocVT == MVT::v4f32 || |
1971 | 144 | LocVT == MVT::v2f64) { |
1972 | 144 | int64_t Offset11 = State.AllocateStack(16, Align(16)); |
1973 | 144 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); |
1974 | 144 | return false; |
1975 | 144 | } |
1976 | | |
1977 | 0 | if (LocVT == MVT::v32i8 || |
1978 | 0 | LocVT == MVT::v16i16 || |
1979 | 0 | LocVT == MVT::v8i32 || |
1980 | 0 | LocVT == MVT::v4i64 || |
1981 | 0 | LocVT == MVT::v16f16 || |
1982 | 0 | LocVT == MVT::v8f32 || |
1983 | 0 | LocVT == MVT::v4f64) { |
1984 | 0 | int64_t Offset12 = State.AllocateStack(32, Align(32)); |
1985 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); |
1986 | 0 | return false; |
1987 | 0 | } |
1988 | | |
1989 | 0 | if (LocVT == MVT::v64i8 || |
1990 | 0 | LocVT == MVT::v32i16 || |
1991 | 0 | LocVT == MVT::v16i32 || |
1992 | 0 | LocVT == MVT::v8i64 || |
1993 | 0 | LocVT == MVT::v32f16 || |
1994 | 0 | LocVT == MVT::v16f32 || |
1995 | 0 | LocVT == MVT::v8f64) { |
1996 | 0 | int64_t Offset13 = State.AllocateStack(64, Align(64)); |
1997 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
1998 | 0 | return false; |
1999 | 0 | } |
2000 | | |
2001 | 0 | return true; // CC didn't match. |
2002 | 0 | } |
2003 | | |
2004 | | |
2005 | | static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT, |
2006 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2007 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2008 | |
|
2009 | 0 | if (LocVT == MVT::i8 || |
2010 | 0 | LocVT == MVT::i16 || |
2011 | 0 | LocVT == MVT::i32) { |
2012 | 0 | LocVT = MVT::i64; |
2013 | 0 | if (ArgFlags.isSExt()) |
2014 | 0 | LocInfo = CCValAssign::SExt; |
2015 | 0 | else if (ArgFlags.isZExt()) |
2016 | 0 | LocInfo = CCValAssign::ZExt; |
2017 | 0 | else |
2018 | 0 | LocInfo = CCValAssign::AExt; |
2019 | 0 | } |
2020 | |
|
2021 | 0 | if (LocVT == MVT::i64) { |
2022 | 0 | static const MCPhysReg RegList1[] = { |
2023 | 0 | X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15 |
2024 | 0 | }; |
2025 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
2026 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2027 | 0 | return false; |
2028 | 0 | } |
2029 | 0 | } |
2030 | | |
2031 | 0 | if (LocVT == MVT::f32 || |
2032 | 0 | LocVT == MVT::f64 || |
2033 | 0 | LocVT == MVT::v16i8 || |
2034 | 0 | LocVT == MVT::v8i16 || |
2035 | 0 | LocVT == MVT::v4i32 || |
2036 | 0 | LocVT == MVT::v2i64 || |
2037 | 0 | LocVT == MVT::v4f32 || |
2038 | 0 | LocVT == MVT::v2f64) { |
2039 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
2040 | 0 | static const MCPhysReg RegList2[] = { |
2041 | 0 | X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6 |
2042 | 0 | }; |
2043 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
2044 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2045 | 0 | return false; |
2046 | 0 | } |
2047 | 0 | } |
2048 | 0 | } |
2049 | | |
2050 | 0 | if (LocVT == MVT::v32i8 || |
2051 | 0 | LocVT == MVT::v16i16 || |
2052 | 0 | LocVT == MVT::v8i32 || |
2053 | 0 | LocVT == MVT::v4i64 || |
2054 | 0 | LocVT == MVT::v8f32 || |
2055 | 0 | LocVT == MVT::v4f64) { |
2056 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
2057 | 0 | static const MCPhysReg RegList3[] = { |
2058 | 0 | X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6 |
2059 | 0 | }; |
2060 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
2061 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2062 | 0 | return false; |
2063 | 0 | } |
2064 | 0 | } |
2065 | 0 | } |
2066 | | |
2067 | 0 | if (LocVT == MVT::v64i8 || |
2068 | 0 | LocVT == MVT::v32i16 || |
2069 | 0 | LocVT == MVT::v16i32 || |
2070 | 0 | LocVT == MVT::v8i64 || |
2071 | 0 | LocVT == MVT::v16f32 || |
2072 | 0 | LocVT == MVT::v8f64) { |
2073 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
2074 | 0 | static const MCPhysReg RegList4[] = { |
2075 | 0 | X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 |
2076 | 0 | }; |
2077 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
2078 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2079 | 0 | return false; |
2080 | 0 | } |
2081 | 0 | } |
2082 | 0 | } |
2083 | | |
2084 | 0 | return true; // CC didn't match. |
2085 | 0 | } |
2086 | | |
2087 | | |
2088 | | static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT, |
2089 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2090 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2091 | |
|
2092 | 0 | if (LocVT == MVT::i8 || |
2093 | 0 | LocVT == MVT::i16 || |
2094 | 0 | LocVT == MVT::i32) { |
2095 | 0 | LocVT = MVT::i64; |
2096 | 0 | if (ArgFlags.isSExt()) |
2097 | 0 | LocInfo = CCValAssign::SExt; |
2098 | 0 | else if (ArgFlags.isZExt()) |
2099 | 0 | LocInfo = CCValAssign::ZExt; |
2100 | 0 | else |
2101 | 0 | LocInfo = CCValAssign::AExt; |
2102 | 0 | } |
2103 | |
|
2104 | 0 | if (LocVT == MVT::i64) { |
2105 | 0 | static const MCPhysReg RegList1[] = { |
2106 | 0 | X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8 |
2107 | 0 | }; |
2108 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
2109 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2110 | 0 | return false; |
2111 | 0 | } |
2112 | 0 | } |
2113 | | |
2114 | 0 | if (LocVT == MVT::i32 || |
2115 | 0 | LocVT == MVT::i64 || |
2116 | 0 | LocVT == MVT::f32 || |
2117 | 0 | LocVT == MVT::f64) { |
2118 | 0 | int64_t Offset2 = State.AllocateStack(8, Align(8)); |
2119 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
2120 | 0 | return false; |
2121 | 0 | } |
2122 | | |
2123 | 0 | return true; // CC didn't match. |
2124 | 0 | } |
2125 | | |
2126 | | |
2127 | | static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, |
2128 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2129 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2130 | |
|
2131 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2132 | 0 | if (ArgFlags.isByVal()) { |
2133 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
2134 | 0 | return false; |
2135 | 0 | } |
2136 | 0 | } |
2137 | | |
2138 | 0 | if (ArgFlags.isByVal()) { |
2139 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
2140 | 0 | return false; |
2141 | 0 | } |
2142 | | |
2143 | 0 | if (LocVT == MVT::i1 || |
2144 | 0 | LocVT == MVT::i8 || |
2145 | 0 | LocVT == MVT::i16 || |
2146 | 0 | LocVT == MVT::v1i1) { |
2147 | 0 | LocVT = MVT::i32; |
2148 | 0 | if (ArgFlags.isSExt()) |
2149 | 0 | LocInfo = CCValAssign::SExt; |
2150 | 0 | else if (ArgFlags.isZExt()) |
2151 | 0 | LocInfo = CCValAssign::ZExt; |
2152 | 0 | else |
2153 | 0 | LocInfo = CCValAssign::AExt; |
2154 | 0 | } |
2155 | |
|
2156 | 0 | if (LocVT == MVT::v8i1 || |
2157 | 0 | LocVT == MVT::v16i1 || |
2158 | 0 | LocVT == MVT::v32i1) { |
2159 | 0 | LocVT = MVT::i32; |
2160 | 0 | if (ArgFlags.isSExt()) |
2161 | 0 | LocInfo = CCValAssign::SExt; |
2162 | 0 | else if (ArgFlags.isZExt()) |
2163 | 0 | LocInfo = CCValAssign::ZExt; |
2164 | 0 | else |
2165 | 0 | LocInfo = CCValAssign::AExt; |
2166 | 0 | } |
2167 | |
|
2168 | 0 | if (LocVT == MVT::i32) { |
2169 | 0 | static const MCPhysReg RegList1[] = { |
2170 | 0 | X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D |
2171 | 0 | }; |
2172 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
2173 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2174 | 0 | return false; |
2175 | 0 | } |
2176 | 0 | } |
2177 | | |
2178 | 0 | if (LocVT == MVT::i64) { |
2179 | 0 | static const MCPhysReg RegList2[] = { |
2180 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 |
2181 | 0 | }; |
2182 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
2183 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2184 | 0 | return false; |
2185 | 0 | } |
2186 | 0 | } |
2187 | | |
2188 | 0 | if (LocVT == MVT::v64i1) { |
2189 | 0 | LocVT = MVT::i64; |
2190 | 0 | if (ArgFlags.isSExt()) |
2191 | 0 | LocInfo = CCValAssign::SExt; |
2192 | 0 | else if (ArgFlags.isZExt()) |
2193 | 0 | LocInfo = CCValAssign::ZExt; |
2194 | 0 | else |
2195 | 0 | LocInfo = CCValAssign::AExt; |
2196 | 0 | } |
2197 | |
|
2198 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2199 | 0 | if (LocVT == MVT::i64) { |
2200 | 0 | static const MCPhysReg RegList3[] = { |
2201 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 |
2202 | 0 | }; |
2203 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
2204 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2205 | 0 | return false; |
2206 | 0 | } |
2207 | 0 | } |
2208 | 0 | } |
2209 | | |
2210 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
2211 | 0 | if (LocVT == MVT::i64) { |
2212 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
2213 | 0 | return false; |
2214 | 0 | } |
2215 | 0 | } |
2216 | | |
2217 | 0 | if (LocVT == MVT::f32 || |
2218 | 0 | LocVT == MVT::f64 || |
2219 | 0 | LocVT == MVT::f128) { |
2220 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
2221 | 0 | static const MCPhysReg RegList4[] = { |
2222 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
2223 | 0 | }; |
2224 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
2225 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2226 | 0 | return false; |
2227 | 0 | } |
2228 | 0 | } |
2229 | 0 | } |
2230 | | |
2231 | 0 | if (LocVT == MVT::f80) { |
2232 | 0 | if (unsigned Reg = State.AllocateReg(X86::FP0)) { |
2233 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2234 | 0 | return false; |
2235 | 0 | } |
2236 | 0 | } |
2237 | | |
2238 | 0 | if (LocVT == MVT::v16i8 || |
2239 | 0 | LocVT == MVT::v8i16 || |
2240 | 0 | LocVT == MVT::v4i32 || |
2241 | 0 | LocVT == MVT::v2i64 || |
2242 | 0 | LocVT == MVT::v4f32 || |
2243 | 0 | LocVT == MVT::v2f64) { |
2244 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
2245 | 0 | static const MCPhysReg RegList5[] = { |
2246 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
2247 | 0 | }; |
2248 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
2249 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2250 | 0 | return false; |
2251 | 0 | } |
2252 | 0 | } |
2253 | 0 | } |
2254 | | |
2255 | 0 | if (LocVT == MVT::v32i8 || |
2256 | 0 | LocVT == MVT::v16i16 || |
2257 | 0 | LocVT == MVT::v8i32 || |
2258 | 0 | LocVT == MVT::v4i64 || |
2259 | 0 | LocVT == MVT::v8f32 || |
2260 | 0 | LocVT == MVT::v4f64) { |
2261 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
2262 | 0 | static const MCPhysReg RegList6[] = { |
2263 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 |
2264 | 0 | }; |
2265 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
2266 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2267 | 0 | return false; |
2268 | 0 | } |
2269 | 0 | } |
2270 | 0 | } |
2271 | | |
2272 | 0 | if (LocVT == MVT::v64i8 || |
2273 | 0 | LocVT == MVT::v32i16 || |
2274 | 0 | LocVT == MVT::v16i32 || |
2275 | 0 | LocVT == MVT::v8i64 || |
2276 | 0 | LocVT == MVT::v16f32 || |
2277 | 0 | LocVT == MVT::v8f64) { |
2278 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
2279 | 0 | static const MCPhysReg RegList7[] = { |
2280 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 |
2281 | 0 | }; |
2282 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
2283 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2284 | 0 | return false; |
2285 | 0 | } |
2286 | 0 | } |
2287 | 0 | } |
2288 | | |
2289 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2290 | 0 | if (LocVT == MVT::i32 || |
2291 | 0 | LocVT == MVT::i64 || |
2292 | 0 | LocVT == MVT::f32 || |
2293 | 0 | LocVT == MVT::f64) { |
2294 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(8)); |
2295 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
2296 | 0 | return false; |
2297 | 0 | } |
2298 | 0 | } |
2299 | | |
2300 | 0 | if (LocVT == MVT::i32 || |
2301 | 0 | LocVT == MVT::f32) { |
2302 | 0 | int64_t Offset9 = State.AllocateStack(4, Align(4)); |
2303 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
2304 | 0 | return false; |
2305 | 0 | } |
2306 | | |
2307 | 0 | if (LocVT == MVT::i64 || |
2308 | 0 | LocVT == MVT::f64) { |
2309 | 0 | int64_t Offset10 = State.AllocateStack(8, Align(4)); |
2310 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); |
2311 | 0 | return false; |
2312 | 0 | } |
2313 | | |
2314 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2315 | 0 | if (LocVT == MVT::x86mmx) { |
2316 | 0 | int64_t Offset11 = State.AllocateStack(8, Align(8)); |
2317 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); |
2318 | 0 | return false; |
2319 | 0 | } |
2320 | 0 | } |
2321 | | |
2322 | 0 | if (LocVT == MVT::x86mmx) { |
2323 | 0 | int64_t Offset12 = State.AllocateStack(8, Align(4)); |
2324 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); |
2325 | 0 | return false; |
2326 | 0 | } |
2327 | | |
2328 | 0 | if (LocVT == MVT::f80 || |
2329 | 0 | LocVT == MVT::f128) { |
2330 | 0 | int64_t Offset13 = State.AllocateStack( |
2331 | 0 | State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), |
2332 | 0 | State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()))); |
2333 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
2334 | 0 | return false; |
2335 | 0 | } |
2336 | | |
2337 | 0 | if (LocVT == MVT::v16i8 || |
2338 | 0 | LocVT == MVT::v8i16 || |
2339 | 0 | LocVT == MVT::v4i32 || |
2340 | 0 | LocVT == MVT::v2i64 || |
2341 | 0 | LocVT == MVT::v4f32 || |
2342 | 0 | LocVT == MVT::v2f64) { |
2343 | 0 | int64_t Offset14 = State.AllocateStack(16, Align(16)); |
2344 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); |
2345 | 0 | return false; |
2346 | 0 | } |
2347 | | |
2348 | 0 | if (LocVT == MVT::v32i8 || |
2349 | 0 | LocVT == MVT::v16i16 || |
2350 | 0 | LocVT == MVT::v8i32 || |
2351 | 0 | LocVT == MVT::v4i64 || |
2352 | 0 | LocVT == MVT::v8f32 || |
2353 | 0 | LocVT == MVT::v4f64) { |
2354 | 0 | int64_t Offset15 = State.AllocateStack(32, Align(32)); |
2355 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); |
2356 | 0 | return false; |
2357 | 0 | } |
2358 | | |
2359 | 0 | if (LocVT == MVT::v64i8 || |
2360 | 0 | LocVT == MVT::v32i16 || |
2361 | 0 | LocVT == MVT::v16i32 || |
2362 | 0 | LocVT == MVT::v8i64 || |
2363 | 0 | LocVT == MVT::v16f32 || |
2364 | 0 | LocVT == MVT::v8f64) { |
2365 | 0 | int64_t Offset16 = State.AllocateStack(64, Align(64)); |
2366 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); |
2367 | 0 | return false; |
2368 | 0 | } |
2369 | | |
2370 | 0 | return true; // CC didn't match. |
2371 | 0 | } |
2372 | | |
2373 | | |
2374 | | static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, |
2375 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2376 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2377 | |
|
2378 | 0 | if (LocVT == MVT::i32) { |
2379 | 0 | if (unsigned Reg = State.AllocateReg(X86::ECX)) { |
2380 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2381 | 0 | return false; |
2382 | 0 | } |
2383 | 0 | } |
2384 | | |
2385 | 0 | return true; // CC didn't match. |
2386 | 0 | } |
2387 | | |
2388 | | |
2389 | | static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT, |
2390 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2391 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2392 | |
|
2393 | 0 | if (LocVT == MVT::v16i8 || |
2394 | 0 | LocVT == MVT::v8i16 || |
2395 | 0 | LocVT == MVT::v4i32 || |
2396 | 0 | LocVT == MVT::v2i64 || |
2397 | 0 | LocVT == MVT::v8f16 || |
2398 | 0 | LocVT == MVT::v4f32 || |
2399 | 0 | LocVT == MVT::v2f64) { |
2400 | 0 | int64_t Offset1 = State.AllocateStack(16, Align(4)); |
2401 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); |
2402 | 0 | return false; |
2403 | 0 | } |
2404 | | |
2405 | 0 | if (LocVT == MVT::v32i8 || |
2406 | 0 | LocVT == MVT::v16i16 || |
2407 | 0 | LocVT == MVT::v8i32 || |
2408 | 0 | LocVT == MVT::v4i64 || |
2409 | 0 | LocVT == MVT::v16f16 || |
2410 | 0 | LocVT == MVT::v8f32 || |
2411 | 0 | LocVT == MVT::v4f64) { |
2412 | 0 | int64_t Offset2 = State.AllocateStack(32, Align(4)); |
2413 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
2414 | 0 | return false; |
2415 | 0 | } |
2416 | | |
2417 | 0 | if (LocVT == MVT::v64i8 || |
2418 | 0 | LocVT == MVT::v32i16 || |
2419 | 0 | LocVT == MVT::v16i32 || |
2420 | 0 | LocVT == MVT::v8i64 || |
2421 | 0 | LocVT == MVT::v32f16 || |
2422 | 0 | LocVT == MVT::v16f32 || |
2423 | 0 | LocVT == MVT::v8f64) { |
2424 | 0 | int64_t Offset3 = State.AllocateStack(64, Align(4)); |
2425 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
2426 | 0 | return false; |
2427 | 0 | } |
2428 | | |
2429 | 0 | return true; // CC didn't match. |
2430 | 0 | } |
2431 | | |
2432 | | |
2433 | | static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT, |
2434 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2435 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2436 | |
|
2437 | 0 | if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
2438 | 0 | return false; |
2439 | | |
2440 | 0 | if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
2441 | 0 | return false; |
2442 | | |
2443 | 0 | return true; // CC didn't match. |
2444 | 0 | } |
2445 | | |
2446 | | |
2447 | | static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT, |
2448 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2449 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2450 | |
|
2451 | 0 | if (ArgFlags.isByVal()) { |
2452 | 0 | LocVT = MVT::i64; |
2453 | 0 | LocInfo = CCValAssign::Indirect; |
2454 | 0 | } |
2455 | |
|
2456 | 0 | if (LocVT == MVT::i1 || |
2457 | 0 | LocVT == MVT::v1i1) { |
2458 | 0 | LocVT = MVT::i8; |
2459 | 0 | if (ArgFlags.isSExt()) |
2460 | 0 | LocInfo = CCValAssign::SExt; |
2461 | 0 | else if (ArgFlags.isZExt()) |
2462 | 0 | LocInfo = CCValAssign::ZExt; |
2463 | 0 | else |
2464 | 0 | LocInfo = CCValAssign::AExt; |
2465 | 0 | } |
2466 | |
|
2467 | 0 | if (ArgFlags.isNest()) { |
2468 | 0 | if (unsigned Reg = State.AllocateReg(X86::R10)) { |
2469 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2470 | 0 | return false; |
2471 | 0 | } |
2472 | 0 | } |
2473 | | |
2474 | 0 | if (ArgFlags.isSwiftError()) { |
2475 | 0 | if (LocVT == MVT::i64) { |
2476 | 0 | if (unsigned Reg = State.AllocateReg(X86::R12)) { |
2477 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2478 | 0 | return false; |
2479 | 0 | } |
2480 | 0 | } |
2481 | 0 | } |
2482 | | |
2483 | 0 | if (ArgFlags.isSwiftSelf()) { |
2484 | 0 | if (LocVT == MVT::i64) { |
2485 | 0 | if (unsigned Reg = State.AllocateReg(X86::R13)) { |
2486 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2487 | 0 | return false; |
2488 | 0 | } |
2489 | 0 | } |
2490 | 0 | } |
2491 | | |
2492 | 0 | if (ArgFlags.isSwiftAsync()) { |
2493 | 0 | if (LocVT == MVT::i64) { |
2494 | 0 | if (unsigned Reg = State.AllocateReg(X86::R14)) { |
2495 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2496 | 0 | return false; |
2497 | 0 | } |
2498 | 0 | } |
2499 | 0 | } |
2500 | | |
2501 | 0 | if (ArgFlags.isCFGuardTarget()) { |
2502 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
2503 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2504 | 0 | return false; |
2505 | 0 | } |
2506 | 0 | } |
2507 | | |
2508 | 0 | if (LocVT == MVT::v16i8 || |
2509 | 0 | LocVT == MVT::v8i16 || |
2510 | 0 | LocVT == MVT::v4i32 || |
2511 | 0 | LocVT == MVT::v2i64 || |
2512 | 0 | LocVT == MVT::v8f16 || |
2513 | 0 | LocVT == MVT::v4f32 || |
2514 | 0 | LocVT == MVT::v2f64) { |
2515 | 0 | LocVT = MVT::i64; |
2516 | 0 | LocInfo = CCValAssign::Indirect; |
2517 | 0 | } |
2518 | |
|
2519 | 0 | if (LocVT == MVT::v32i8 || |
2520 | 0 | LocVT == MVT::v16i16 || |
2521 | 0 | LocVT == MVT::v8i32 || |
2522 | 0 | LocVT == MVT::v4i64 || |
2523 | 0 | LocVT == MVT::v16f16 || |
2524 | 0 | LocVT == MVT::v8f32 || |
2525 | 0 | LocVT == MVT::v4f64) { |
2526 | 0 | LocVT = MVT::i64; |
2527 | 0 | LocInfo = CCValAssign::Indirect; |
2528 | 0 | } |
2529 | |
|
2530 | 0 | if (LocVT == MVT::v64i8 || |
2531 | 0 | LocVT == MVT::v32i16 || |
2532 | 0 | LocVT == MVT::v16i32 || |
2533 | 0 | LocVT == MVT::v32f16 || |
2534 | 0 | LocVT == MVT::v16f32 || |
2535 | 0 | LocVT == MVT::v8f64 || |
2536 | 0 | LocVT == MVT::v8i64) { |
2537 | 0 | LocVT = MVT::i64; |
2538 | 0 | LocInfo = CCValAssign::Indirect; |
2539 | 0 | } |
2540 | |
|
2541 | 0 | if (LocVT == MVT::f80) { |
2542 | 0 | LocVT = MVT::i64; |
2543 | 0 | LocInfo = CCValAssign::Indirect; |
2544 | 0 | } |
2545 | |
|
2546 | 0 | if (LocVT == MVT::x86mmx) { |
2547 | 0 | LocVT = MVT::i64; |
2548 | 0 | LocInfo = CCValAssign::BCvt; |
2549 | 0 | } |
2550 | |
|
2551 | 0 | if (LocVT == MVT::f32) { |
2552 | 0 | if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
2553 | 0 | LocVT = MVT::i32; |
2554 | 0 | LocInfo = CCValAssign::BCvt; |
2555 | 0 | } |
2556 | 0 | } |
2557 | |
|
2558 | 0 | if (LocVT == MVT::f64) { |
2559 | 0 | if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
2560 | 0 | LocVT = MVT::i64; |
2561 | 0 | LocInfo = CCValAssign::BCvt; |
2562 | 0 | } |
2563 | 0 | } |
2564 | |
|
2565 | 0 | if (LocVT == MVT::f16 || |
2566 | 0 | LocVT == MVT::f32 || |
2567 | 0 | LocVT == MVT::f64) { |
2568 | 0 | static const MCPhysReg RegList1[] = { |
2569 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
2570 | 0 | }; |
2571 | 0 | static const MCPhysReg RegList2[] = { |
2572 | 0 | X86::RCX, X86::RDX, X86::R8, X86::R9 |
2573 | 0 | }; |
2574 | 0 | if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { |
2575 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2576 | 0 | return false; |
2577 | 0 | } |
2578 | 0 | } |
2579 | | |
2580 | 0 | if (LocVT == MVT::i8) { |
2581 | 0 | static const MCPhysReg RegList3[] = { |
2582 | 0 | X86::CL, X86::DL, X86::R8B, X86::R9B |
2583 | 0 | }; |
2584 | 0 | static const MCPhysReg RegList4[] = { |
2585 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
2586 | 0 | }; |
2587 | 0 | if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) { |
2588 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2589 | 0 | return false; |
2590 | 0 | } |
2591 | 0 | } |
2592 | | |
2593 | 0 | if (LocVT == MVT::i16) { |
2594 | 0 | static const MCPhysReg RegList5[] = { |
2595 | 0 | X86::CX, X86::DX, X86::R8W, X86::R9W |
2596 | 0 | }; |
2597 | 0 | static const MCPhysReg RegList6[] = { |
2598 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
2599 | 0 | }; |
2600 | 0 | if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { |
2601 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2602 | 0 | return false; |
2603 | 0 | } |
2604 | 0 | } |
2605 | | |
2606 | 0 | if (LocVT == MVT::i32) { |
2607 | 0 | static const MCPhysReg RegList7[] = { |
2608 | 0 | X86::ECX, X86::EDX, X86::R8D, X86::R9D |
2609 | 0 | }; |
2610 | 0 | static const MCPhysReg RegList8[] = { |
2611 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
2612 | 0 | }; |
2613 | 0 | if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) { |
2614 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2615 | 0 | return false; |
2616 | 0 | } |
2617 | 0 | } |
2618 | | |
2619 | 0 | if (State.getCallingConv() == CallingConv::X86_ThisCall) { |
2620 | 0 | if (ArgFlags.isSRet()) { |
2621 | 0 | if (LocVT == MVT::i64) { |
2622 | 0 | static const MCPhysReg RegList9[] = { |
2623 | 0 | X86::RDX, X86::R8, X86::R9 |
2624 | 0 | }; |
2625 | 0 | static const MCPhysReg RegList10[] = { |
2626 | 0 | X86::XMM1, X86::XMM2, X86::XMM3 |
2627 | 0 | }; |
2628 | 0 | if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) { |
2629 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2630 | 0 | return false; |
2631 | 0 | } |
2632 | 0 | } |
2633 | 0 | } |
2634 | 0 | } |
2635 | | |
2636 | 0 | if (LocVT == MVT::i64) { |
2637 | 0 | static const MCPhysReg RegList11[] = { |
2638 | 0 | X86::RCX, X86::RDX, X86::R8, X86::R9 |
2639 | 0 | }; |
2640 | 0 | static const MCPhysReg RegList12[] = { |
2641 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
2642 | 0 | }; |
2643 | 0 | if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) { |
2644 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2645 | 0 | return false; |
2646 | 0 | } |
2647 | 0 | } |
2648 | | |
2649 | 0 | if (LocVT == MVT::i8 || |
2650 | 0 | LocVT == MVT::i16 || |
2651 | 0 | LocVT == MVT::i32 || |
2652 | 0 | LocVT == MVT::i64 || |
2653 | 0 | LocVT == MVT::f16 || |
2654 | 0 | LocVT == MVT::f32 || |
2655 | 0 | LocVT == MVT::f64) { |
2656 | 0 | int64_t Offset13 = State.AllocateStack(8, Align(8)); |
2657 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
2658 | 0 | return false; |
2659 | 0 | } |
2660 | | |
2661 | 0 | return true; // CC didn't match. |
2662 | 0 | } |
2663 | | |
2664 | | |
2665 | | static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, |
2666 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2667 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2668 | |
|
2669 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2670 | 0 | if (ArgFlags.isByVal()) { |
2671 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
2672 | 0 | return false; |
2673 | 0 | } |
2674 | 0 | } |
2675 | | |
2676 | 0 | if (ArgFlags.isByVal()) { |
2677 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
2678 | 0 | return false; |
2679 | 0 | } |
2680 | | |
2681 | 0 | if (LocVT == MVT::i1 || |
2682 | 0 | LocVT == MVT::i8 || |
2683 | 0 | LocVT == MVT::i16 || |
2684 | 0 | LocVT == MVT::v1i1) { |
2685 | 0 | LocVT = MVT::i32; |
2686 | 0 | if (ArgFlags.isSExt()) |
2687 | 0 | LocInfo = CCValAssign::SExt; |
2688 | 0 | else if (ArgFlags.isZExt()) |
2689 | 0 | LocInfo = CCValAssign::ZExt; |
2690 | 0 | else |
2691 | 0 | LocInfo = CCValAssign::AExt; |
2692 | 0 | } |
2693 | |
|
2694 | 0 | if (LocVT == MVT::v8i1 || |
2695 | 0 | LocVT == MVT::v16i1 || |
2696 | 0 | LocVT == MVT::v32i1) { |
2697 | 0 | LocVT = MVT::i32; |
2698 | 0 | if (ArgFlags.isSExt()) |
2699 | 0 | LocInfo = CCValAssign::SExt; |
2700 | 0 | else if (ArgFlags.isZExt()) |
2701 | 0 | LocInfo = CCValAssign::ZExt; |
2702 | 0 | else |
2703 | 0 | LocInfo = CCValAssign::AExt; |
2704 | 0 | } |
2705 | |
|
2706 | 0 | if (LocVT == MVT::i32) { |
2707 | 0 | static const MCPhysReg RegList1[] = { |
2708 | 0 | X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D |
2709 | 0 | }; |
2710 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
2711 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2712 | 0 | return false; |
2713 | 0 | } |
2714 | 0 | } |
2715 | | |
2716 | 0 | if (LocVT == MVT::i64) { |
2717 | 0 | static const MCPhysReg RegList2[] = { |
2718 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 |
2719 | 0 | }; |
2720 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
2721 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2722 | 0 | return false; |
2723 | 0 | } |
2724 | 0 | } |
2725 | | |
2726 | 0 | if (LocVT == MVT::v64i1) { |
2727 | 0 | LocVT = MVT::i64; |
2728 | 0 | if (ArgFlags.isSExt()) |
2729 | 0 | LocInfo = CCValAssign::SExt; |
2730 | 0 | else if (ArgFlags.isZExt()) |
2731 | 0 | LocInfo = CCValAssign::ZExt; |
2732 | 0 | else |
2733 | 0 | LocInfo = CCValAssign::AExt; |
2734 | 0 | } |
2735 | |
|
2736 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2737 | 0 | if (LocVT == MVT::i64) { |
2738 | 0 | static const MCPhysReg RegList3[] = { |
2739 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 |
2740 | 0 | }; |
2741 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
2742 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2743 | 0 | return false; |
2744 | 0 | } |
2745 | 0 | } |
2746 | 0 | } |
2747 | | |
2748 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
2749 | 0 | if (LocVT == MVT::i64) { |
2750 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
2751 | 0 | return false; |
2752 | 0 | } |
2753 | 0 | } |
2754 | | |
2755 | 0 | if (LocVT == MVT::f32 || |
2756 | 0 | LocVT == MVT::f64 || |
2757 | 0 | LocVT == MVT::f128) { |
2758 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
2759 | 0 | static const MCPhysReg RegList4[] = { |
2760 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
2761 | 0 | }; |
2762 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
2763 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2764 | 0 | return false; |
2765 | 0 | } |
2766 | 0 | } |
2767 | 0 | } |
2768 | | |
2769 | 0 | if (LocVT == MVT::f80) { |
2770 | 0 | if (unsigned Reg = State.AllocateReg(X86::FP0)) { |
2771 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2772 | 0 | return false; |
2773 | 0 | } |
2774 | 0 | } |
2775 | | |
2776 | 0 | if (LocVT == MVT::v16i8 || |
2777 | 0 | LocVT == MVT::v8i16 || |
2778 | 0 | LocVT == MVT::v4i32 || |
2779 | 0 | LocVT == MVT::v2i64 || |
2780 | 0 | LocVT == MVT::v4f32 || |
2781 | 0 | LocVT == MVT::v2f64) { |
2782 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
2783 | 0 | static const MCPhysReg RegList5[] = { |
2784 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
2785 | 0 | }; |
2786 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
2787 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2788 | 0 | return false; |
2789 | 0 | } |
2790 | 0 | } |
2791 | 0 | } |
2792 | | |
2793 | 0 | if (LocVT == MVT::v32i8 || |
2794 | 0 | LocVT == MVT::v16i16 || |
2795 | 0 | LocVT == MVT::v8i32 || |
2796 | 0 | LocVT == MVT::v4i64 || |
2797 | 0 | LocVT == MVT::v8f32 || |
2798 | 0 | LocVT == MVT::v4f64) { |
2799 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
2800 | 0 | static const MCPhysReg RegList6[] = { |
2801 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 |
2802 | 0 | }; |
2803 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
2804 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2805 | 0 | return false; |
2806 | 0 | } |
2807 | 0 | } |
2808 | 0 | } |
2809 | | |
2810 | 0 | if (LocVT == MVT::v64i8 || |
2811 | 0 | LocVT == MVT::v32i16 || |
2812 | 0 | LocVT == MVT::v16i32 || |
2813 | 0 | LocVT == MVT::v8i64 || |
2814 | 0 | LocVT == MVT::v16f32 || |
2815 | 0 | LocVT == MVT::v8f64) { |
2816 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
2817 | 0 | static const MCPhysReg RegList7[] = { |
2818 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 |
2819 | 0 | }; |
2820 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
2821 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2822 | 0 | return false; |
2823 | 0 | } |
2824 | 0 | } |
2825 | 0 | } |
2826 | | |
2827 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2828 | 0 | if (LocVT == MVT::i32 || |
2829 | 0 | LocVT == MVT::i64 || |
2830 | 0 | LocVT == MVT::f32 || |
2831 | 0 | LocVT == MVT::f64) { |
2832 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(8)); |
2833 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
2834 | 0 | return false; |
2835 | 0 | } |
2836 | 0 | } |
2837 | | |
2838 | 0 | if (LocVT == MVT::i32 || |
2839 | 0 | LocVT == MVT::f32) { |
2840 | 0 | int64_t Offset9 = State.AllocateStack(4, Align(4)); |
2841 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
2842 | 0 | return false; |
2843 | 0 | } |
2844 | | |
2845 | 0 | if (LocVT == MVT::i64 || |
2846 | 0 | LocVT == MVT::f64) { |
2847 | 0 | int64_t Offset10 = State.AllocateStack(8, Align(4)); |
2848 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); |
2849 | 0 | return false; |
2850 | 0 | } |
2851 | | |
2852 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2853 | 0 | if (LocVT == MVT::x86mmx) { |
2854 | 0 | int64_t Offset11 = State.AllocateStack(8, Align(8)); |
2855 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); |
2856 | 0 | return false; |
2857 | 0 | } |
2858 | 0 | } |
2859 | | |
2860 | 0 | if (LocVT == MVT::x86mmx) { |
2861 | 0 | int64_t Offset12 = State.AllocateStack(8, Align(4)); |
2862 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); |
2863 | 0 | return false; |
2864 | 0 | } |
2865 | | |
2866 | 0 | if (LocVT == MVT::f80 || |
2867 | 0 | LocVT == MVT::f128) { |
2868 | 0 | int64_t Offset13 = State.AllocateStack( |
2869 | 0 | State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), |
2870 | 0 | State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()))); |
2871 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
2872 | 0 | return false; |
2873 | 0 | } |
2874 | | |
2875 | 0 | if (LocVT == MVT::v16i8 || |
2876 | 0 | LocVT == MVT::v8i16 || |
2877 | 0 | LocVT == MVT::v4i32 || |
2878 | 0 | LocVT == MVT::v2i64 || |
2879 | 0 | LocVT == MVT::v4f32 || |
2880 | 0 | LocVT == MVT::v2f64) { |
2881 | 0 | int64_t Offset14 = State.AllocateStack(16, Align(16)); |
2882 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); |
2883 | 0 | return false; |
2884 | 0 | } |
2885 | | |
2886 | 0 | if (LocVT == MVT::v32i8 || |
2887 | 0 | LocVT == MVT::v16i16 || |
2888 | 0 | LocVT == MVT::v8i32 || |
2889 | 0 | LocVT == MVT::v4i64 || |
2890 | 0 | LocVT == MVT::v8f32 || |
2891 | 0 | LocVT == MVT::v4f64) { |
2892 | 0 | int64_t Offset15 = State.AllocateStack(32, Align(32)); |
2893 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); |
2894 | 0 | return false; |
2895 | 0 | } |
2896 | | |
2897 | 0 | if (LocVT == MVT::v64i8 || |
2898 | 0 | LocVT == MVT::v32i16 || |
2899 | 0 | LocVT == MVT::v16i32 || |
2900 | 0 | LocVT == MVT::v8i64 || |
2901 | 0 | LocVT == MVT::v16f32 || |
2902 | 0 | LocVT == MVT::v8f64) { |
2903 | 0 | int64_t Offset16 = State.AllocateStack(64, Align(64)); |
2904 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); |
2905 | 0 | return false; |
2906 | 0 | } |
2907 | | |
2908 | 0 | return true; // CC didn't match. |
2909 | 0 | } |
2910 | | |
2911 | | |
2912 | | static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT, |
2913 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
2914 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
2915 | |
|
2916 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2917 | 0 | if (ArgFlags.isByVal()) { |
2918 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
2919 | 0 | return false; |
2920 | 0 | } |
2921 | 0 | } |
2922 | | |
2923 | 0 | if (ArgFlags.isByVal()) { |
2924 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
2925 | 0 | return false; |
2926 | 0 | } |
2927 | | |
2928 | 0 | if (LocVT == MVT::i1 || |
2929 | 0 | LocVT == MVT::i8 || |
2930 | 0 | LocVT == MVT::i16 || |
2931 | 0 | LocVT == MVT::v1i1) { |
2932 | 0 | LocVT = MVT::i32; |
2933 | 0 | if (ArgFlags.isSExt()) |
2934 | 0 | LocInfo = CCValAssign::SExt; |
2935 | 0 | else if (ArgFlags.isZExt()) |
2936 | 0 | LocInfo = CCValAssign::ZExt; |
2937 | 0 | else |
2938 | 0 | LocInfo = CCValAssign::AExt; |
2939 | 0 | } |
2940 | |
|
2941 | 0 | if (LocVT == MVT::v8i1 || |
2942 | 0 | LocVT == MVT::v16i1 || |
2943 | 0 | LocVT == MVT::v32i1) { |
2944 | 0 | LocVT = MVT::i32; |
2945 | 0 | if (ArgFlags.isSExt()) |
2946 | 0 | LocInfo = CCValAssign::SExt; |
2947 | 0 | else if (ArgFlags.isZExt()) |
2948 | 0 | LocInfo = CCValAssign::ZExt; |
2949 | 0 | else |
2950 | 0 | LocInfo = CCValAssign::AExt; |
2951 | 0 | } |
2952 | |
|
2953 | 0 | if (LocVT == MVT::i32) { |
2954 | 0 | static const MCPhysReg RegList1[] = { |
2955 | 0 | X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D |
2956 | 0 | }; |
2957 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
2958 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2959 | 0 | return false; |
2960 | 0 | } |
2961 | 0 | } |
2962 | | |
2963 | 0 | if (LocVT == MVT::i64) { |
2964 | 0 | static const MCPhysReg RegList2[] = { |
2965 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15 |
2966 | 0 | }; |
2967 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
2968 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2969 | 0 | return false; |
2970 | 0 | } |
2971 | 0 | } |
2972 | | |
2973 | 0 | if (LocVT == MVT::v64i1) { |
2974 | 0 | LocVT = MVT::i64; |
2975 | 0 | if (ArgFlags.isSExt()) |
2976 | 0 | LocInfo = CCValAssign::SExt; |
2977 | 0 | else if (ArgFlags.isZExt()) |
2978 | 0 | LocInfo = CCValAssign::ZExt; |
2979 | 0 | else |
2980 | 0 | LocInfo = CCValAssign::AExt; |
2981 | 0 | } |
2982 | |
|
2983 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
2984 | 0 | if (LocVT == MVT::i64) { |
2985 | 0 | static const MCPhysReg RegList3[] = { |
2986 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15 |
2987 | 0 | }; |
2988 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
2989 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
2990 | 0 | return false; |
2991 | 0 | } |
2992 | 0 | } |
2993 | 0 | } |
2994 | | |
2995 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
2996 | 0 | if (LocVT == MVT::i64) { |
2997 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
2998 | 0 | return false; |
2999 | 0 | } |
3000 | 0 | } |
3001 | | |
3002 | 0 | if (LocVT == MVT::f32 || |
3003 | 0 | LocVT == MVT::f64 || |
3004 | 0 | LocVT == MVT::f128) { |
3005 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
3006 | 0 | static const MCPhysReg RegList4[] = { |
3007 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
3008 | 0 | }; |
3009 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
3010 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3011 | 0 | return false; |
3012 | 0 | } |
3013 | 0 | } |
3014 | 0 | } |
3015 | | |
3016 | 0 | if (LocVT == MVT::f80) { |
3017 | 0 | if (unsigned Reg = State.AllocateReg(X86::FP0)) { |
3018 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3019 | 0 | return false; |
3020 | 0 | } |
3021 | 0 | } |
3022 | | |
3023 | 0 | if (LocVT == MVT::v16i8 || |
3024 | 0 | LocVT == MVT::v8i16 || |
3025 | 0 | LocVT == MVT::v4i32 || |
3026 | 0 | LocVT == MVT::v2i64 || |
3027 | 0 | LocVT == MVT::v4f32 || |
3028 | 0 | LocVT == MVT::v2f64) { |
3029 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
3030 | 0 | static const MCPhysReg RegList5[] = { |
3031 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
3032 | 0 | }; |
3033 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
3034 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3035 | 0 | return false; |
3036 | 0 | } |
3037 | 0 | } |
3038 | 0 | } |
3039 | | |
3040 | 0 | if (LocVT == MVT::v32i8 || |
3041 | 0 | LocVT == MVT::v16i16 || |
3042 | 0 | LocVT == MVT::v8i32 || |
3043 | 0 | LocVT == MVT::v4i64 || |
3044 | 0 | LocVT == MVT::v8f32 || |
3045 | 0 | LocVT == MVT::v4f64) { |
3046 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
3047 | 0 | static const MCPhysReg RegList6[] = { |
3048 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 |
3049 | 0 | }; |
3050 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
3051 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3052 | 0 | return false; |
3053 | 0 | } |
3054 | 0 | } |
3055 | 0 | } |
3056 | | |
3057 | 0 | if (LocVT == MVT::v64i8 || |
3058 | 0 | LocVT == MVT::v32i16 || |
3059 | 0 | LocVT == MVT::v16i32 || |
3060 | 0 | LocVT == MVT::v8i64 || |
3061 | 0 | LocVT == MVT::v16f32 || |
3062 | 0 | LocVT == MVT::v8f64) { |
3063 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
3064 | 0 | static const MCPhysReg RegList7[] = { |
3065 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 |
3066 | 0 | }; |
3067 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
3068 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3069 | 0 | return false; |
3070 | 0 | } |
3071 | 0 | } |
3072 | 0 | } |
3073 | | |
3074 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
3075 | 0 | if (LocVT == MVT::i32 || |
3076 | 0 | LocVT == MVT::i64 || |
3077 | 0 | LocVT == MVT::f32 || |
3078 | 0 | LocVT == MVT::f64) { |
3079 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(8)); |
3080 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
3081 | 0 | return false; |
3082 | 0 | } |
3083 | 0 | } |
3084 | | |
3085 | 0 | if (LocVT == MVT::i32 || |
3086 | 0 | LocVT == MVT::f32) { |
3087 | 0 | int64_t Offset9 = State.AllocateStack(4, Align(4)); |
3088 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
3089 | 0 | return false; |
3090 | 0 | } |
3091 | | |
3092 | 0 | if (LocVT == MVT::i64 || |
3093 | 0 | LocVT == MVT::f64) { |
3094 | 0 | int64_t Offset10 = State.AllocateStack(8, Align(4)); |
3095 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); |
3096 | 0 | return false; |
3097 | 0 | } |
3098 | | |
3099 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
3100 | 0 | if (LocVT == MVT::x86mmx) { |
3101 | 0 | int64_t Offset11 = State.AllocateStack(8, Align(8)); |
3102 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); |
3103 | 0 | return false; |
3104 | 0 | } |
3105 | 0 | } |
3106 | | |
3107 | 0 | if (LocVT == MVT::x86mmx) { |
3108 | 0 | int64_t Offset12 = State.AllocateStack(8, Align(4)); |
3109 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); |
3110 | 0 | return false; |
3111 | 0 | } |
3112 | | |
3113 | 0 | if (LocVT == MVT::f80 || |
3114 | 0 | LocVT == MVT::f128) { |
3115 | 0 | int64_t Offset13 = State.AllocateStack( |
3116 | 0 | State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), |
3117 | 0 | State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()))); |
3118 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
3119 | 0 | return false; |
3120 | 0 | } |
3121 | | |
3122 | 0 | if (LocVT == MVT::v16i8 || |
3123 | 0 | LocVT == MVT::v8i16 || |
3124 | 0 | LocVT == MVT::v4i32 || |
3125 | 0 | LocVT == MVT::v2i64 || |
3126 | 0 | LocVT == MVT::v4f32 || |
3127 | 0 | LocVT == MVT::v2f64) { |
3128 | 0 | int64_t Offset14 = State.AllocateStack(16, Align(16)); |
3129 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); |
3130 | 0 | return false; |
3131 | 0 | } |
3132 | | |
3133 | 0 | if (LocVT == MVT::v32i8 || |
3134 | 0 | LocVT == MVT::v16i16 || |
3135 | 0 | LocVT == MVT::v8i32 || |
3136 | 0 | LocVT == MVT::v4i64 || |
3137 | 0 | LocVT == MVT::v8f32 || |
3138 | 0 | LocVT == MVT::v4f64) { |
3139 | 0 | int64_t Offset15 = State.AllocateStack(32, Align(32)); |
3140 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); |
3141 | 0 | return false; |
3142 | 0 | } |
3143 | | |
3144 | 0 | if (LocVT == MVT::v64i8 || |
3145 | 0 | LocVT == MVT::v32i16 || |
3146 | 0 | LocVT == MVT::v16i32 || |
3147 | 0 | LocVT == MVT::v8i64 || |
3148 | 0 | LocVT == MVT::v16f32 || |
3149 | 0 | LocVT == MVT::v8f64) { |
3150 | 0 | int64_t Offset16 = State.AllocateStack(64, Align(64)); |
3151 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); |
3152 | 0 | return false; |
3153 | 0 | } |
3154 | | |
3155 | 0 | return true; // CC didn't match. |
3156 | 0 | } |
3157 | | |
3158 | | |
3159 | | static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT, |
3160 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3161 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3162 | |
|
3163 | 0 | if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3164 | 0 | return false; |
3165 | | |
3166 | 0 | if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3167 | 0 | return false; |
3168 | | |
3169 | 0 | return true; // CC didn't match. |
3170 | 0 | } |
3171 | | |
3172 | | |
3173 | | static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, |
3174 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3175 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3176 | |
|
3177 | 0 | if (LocVT == MVT::f32 || |
3178 | 0 | LocVT == MVT::f64 || |
3179 | 0 | LocVT == MVT::v4i32 || |
3180 | 0 | LocVT == MVT::v2i64 || |
3181 | 0 | LocVT == MVT::v4f32 || |
3182 | 0 | LocVT == MVT::v2f64) { |
3183 | 0 | static const MCPhysReg RegList1[] = { |
3184 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
3185 | 0 | }; |
3186 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
3187 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3188 | 0 | return false; |
3189 | 0 | } |
3190 | 0 | } |
3191 | | |
3192 | 0 | if (LocVT == MVT::v8f32 || |
3193 | 0 | LocVT == MVT::v4f64 || |
3194 | 0 | LocVT == MVT::v8i32 || |
3195 | 0 | LocVT == MVT::v4i64) { |
3196 | 0 | static const MCPhysReg RegList2[] = { |
3197 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 |
3198 | 0 | }; |
3199 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
3200 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3201 | 0 | return false; |
3202 | 0 | } |
3203 | 0 | } |
3204 | | |
3205 | 0 | if (LocVT == MVT::v16f32 || |
3206 | 0 | LocVT == MVT::v8f64 || |
3207 | 0 | LocVT == MVT::v16i32 || |
3208 | 0 | LocVT == MVT::v8i64) { |
3209 | 0 | static const MCPhysReg RegList3[] = { |
3210 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 |
3211 | 0 | }; |
3212 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
3213 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3214 | 0 | return false; |
3215 | 0 | } |
3216 | 0 | } |
3217 | | |
3218 | 0 | if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3219 | 0 | return false; |
3220 | | |
3221 | 0 | return true; // CC didn't match. |
3222 | 0 | } |
3223 | | |
3224 | | |
3225 | | bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT, |
3226 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3227 | 47.3k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3228 | | |
3229 | 47.3k | if (State.getCallingConv() == CallingConv::Intel_OCL_BI) { |
3230 | 0 | if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3231 | 0 | return false; |
3232 | 0 | } |
3233 | | |
3234 | 47.3k | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
3235 | 47.3k | if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3236 | 47.3k | return false; |
3237 | 47.3k | } |
3238 | | |
3239 | 53 | if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3240 | 14 | return false; |
3241 | | |
3242 | 39 | return true; // CC didn't match. |
3243 | 53 | } |
3244 | | |
3245 | | |
3246 | | static bool RetCC_X86Common(unsigned ValNo, MVT ValVT, |
3247 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3248 | 37.6k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3249 | | |
3250 | 37.6k | if (LocVT == MVT::v1i1) { |
3251 | 0 | LocVT = MVT::i8; |
3252 | 0 | if (ArgFlags.isSExt()) |
3253 | 0 | LocInfo = CCValAssign::SExt; |
3254 | 0 | else if (ArgFlags.isZExt()) |
3255 | 0 | LocInfo = CCValAssign::ZExt; |
3256 | 0 | else |
3257 | 0 | LocInfo = CCValAssign::AExt; |
3258 | 0 | } |
3259 | | |
3260 | 37.6k | if (LocVT == MVT::i1) { |
3261 | 0 | LocVT = MVT::i8; |
3262 | 0 | if (ArgFlags.isSExt()) |
3263 | 0 | LocInfo = CCValAssign::SExt; |
3264 | 0 | else if (ArgFlags.isZExt()) |
3265 | 0 | LocInfo = CCValAssign::ZExt; |
3266 | 0 | else |
3267 | 0 | LocInfo = CCValAssign::AExt; |
3268 | 0 | } |
3269 | | |
3270 | 37.6k | if (LocVT == MVT::i8) { |
3271 | 11.7k | static const MCPhysReg RegList1[] = { |
3272 | 11.7k | X86::AL, X86::DL, X86::CL |
3273 | 11.7k | }; |
3274 | 11.7k | if (unsigned Reg = State.AllocateReg(RegList1)) { |
3275 | 11.7k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3276 | 11.7k | return false; |
3277 | 11.7k | } |
3278 | 11.7k | } |
3279 | | |
3280 | 25.8k | if (LocVT == MVT::i16) { |
3281 | 660 | static const MCPhysReg RegList2[] = { |
3282 | 660 | X86::AX, X86::DX, X86::CX |
3283 | 660 | }; |
3284 | 660 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
3285 | 660 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3286 | 660 | return false; |
3287 | 660 | } |
3288 | 660 | } |
3289 | | |
3290 | 25.2k | if (LocVT == MVT::i32) { |
3291 | 9.46k | static const MCPhysReg RegList3[] = { |
3292 | 9.46k | X86::EAX, X86::EDX, X86::ECX |
3293 | 9.46k | }; |
3294 | 9.46k | if (unsigned Reg = State.AllocateReg(RegList3)) { |
3295 | 9.46k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3296 | 9.46k | return false; |
3297 | 9.46k | } |
3298 | 9.46k | } |
3299 | | |
3300 | 15.7k | if (LocVT == MVT::i64) { |
3301 | 2.98k | static const MCPhysReg RegList4[] = { |
3302 | 2.98k | X86::RAX, X86::RDX, X86::RCX |
3303 | 2.98k | }; |
3304 | 2.98k | if (unsigned Reg = State.AllocateReg(RegList4)) { |
3305 | 2.93k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3306 | 2.93k | return false; |
3307 | 2.93k | } |
3308 | 2.98k | } |
3309 | | |
3310 | 12.8k | if (LocVT == MVT::v2i1) { |
3311 | 0 | LocVT = MVT::v2i64; |
3312 | 0 | if (ArgFlags.isSExt()) |
3313 | 0 | LocInfo = CCValAssign::SExt; |
3314 | 0 | else if (ArgFlags.isZExt()) |
3315 | 0 | LocInfo = CCValAssign::ZExt; |
3316 | 0 | else |
3317 | 0 | LocInfo = CCValAssign::AExt; |
3318 | 0 | } |
3319 | | |
3320 | 12.8k | if (LocVT == MVT::v4i1) { |
3321 | 0 | LocVT = MVT::v4i32; |
3322 | 0 | if (ArgFlags.isSExt()) |
3323 | 0 | LocInfo = CCValAssign::SExt; |
3324 | 0 | else if (ArgFlags.isZExt()) |
3325 | 0 | LocInfo = CCValAssign::ZExt; |
3326 | 0 | else |
3327 | 0 | LocInfo = CCValAssign::AExt; |
3328 | 0 | } |
3329 | | |
3330 | 12.8k | if (LocVT == MVT::v8i1) { |
3331 | 0 | LocVT = MVT::v8i16; |
3332 | 0 | if (ArgFlags.isSExt()) |
3333 | 0 | LocInfo = CCValAssign::SExt; |
3334 | 0 | else if (ArgFlags.isZExt()) |
3335 | 0 | LocInfo = CCValAssign::ZExt; |
3336 | 0 | else |
3337 | 0 | LocInfo = CCValAssign::AExt; |
3338 | 0 | } |
3339 | | |
3340 | 12.8k | if (LocVT == MVT::v16i1) { |
3341 | 0 | LocVT = MVT::v16i8; |
3342 | 0 | if (ArgFlags.isSExt()) |
3343 | 0 | LocInfo = CCValAssign::SExt; |
3344 | 0 | else if (ArgFlags.isZExt()) |
3345 | 0 | LocInfo = CCValAssign::ZExt; |
3346 | 0 | else |
3347 | 0 | LocInfo = CCValAssign::AExt; |
3348 | 0 | } |
3349 | | |
3350 | 12.8k | if (LocVT == MVT::v32i1) { |
3351 | 0 | LocVT = MVT::v32i8; |
3352 | 0 | if (ArgFlags.isSExt()) |
3353 | 0 | LocInfo = CCValAssign::SExt; |
3354 | 0 | else if (ArgFlags.isZExt()) |
3355 | 0 | LocInfo = CCValAssign::ZExt; |
3356 | 0 | else |
3357 | 0 | LocInfo = CCValAssign::AExt; |
3358 | 0 | } |
3359 | | |
3360 | 12.8k | if (LocVT == MVT::v64i1) { |
3361 | 0 | LocVT = MVT::v64i8; |
3362 | 0 | if (ArgFlags.isSExt()) |
3363 | 0 | LocInfo = CCValAssign::SExt; |
3364 | 0 | else if (ArgFlags.isZExt()) |
3365 | 0 | LocInfo = CCValAssign::ZExt; |
3366 | 0 | else |
3367 | 0 | LocInfo = CCValAssign::AExt; |
3368 | 0 | } |
3369 | | |
3370 | 12.8k | if (LocVT == MVT::v16i8 || |
3371 | 12.8k | LocVT == MVT::v8i16 || |
3372 | 12.8k | LocVT == MVT::v4i32 || |
3373 | 12.8k | LocVT == MVT::v2i64 || |
3374 | 12.8k | LocVT == MVT::v8f16 || |
3375 | 12.8k | LocVT == MVT::v4f32 || |
3376 | 12.8k | LocVT == MVT::v2f64) { |
3377 | 12.6k | static const MCPhysReg RegList5[] = { |
3378 | 12.6k | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
3379 | 12.6k | }; |
3380 | 12.6k | if (unsigned Reg = State.AllocateReg(RegList5)) { |
3381 | 12.6k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3382 | 12.6k | return false; |
3383 | 12.6k | } |
3384 | 12.6k | } |
3385 | | |
3386 | 142 | if (LocVT == MVT::v32i8 || |
3387 | 142 | LocVT == MVT::v16i16 || |
3388 | 142 | LocVT == MVT::v8i32 || |
3389 | 142 | LocVT == MVT::v4i64 || |
3390 | 142 | LocVT == MVT::v16f16 || |
3391 | 142 | LocVT == MVT::v8f32 || |
3392 | 142 | LocVT == MVT::v4f64) { |
3393 | 0 | static const MCPhysReg RegList6[] = { |
3394 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 |
3395 | 0 | }; |
3396 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
3397 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3398 | 0 | return false; |
3399 | 0 | } |
3400 | 0 | } |
3401 | | |
3402 | 142 | if (LocVT == MVT::v64i8 || |
3403 | 142 | LocVT == MVT::v32i16 || |
3404 | 142 | LocVT == MVT::v16i32 || |
3405 | 142 | LocVT == MVT::v8i64 || |
3406 | 142 | LocVT == MVT::v32f16 || |
3407 | 142 | LocVT == MVT::v16f32 || |
3408 | 142 | LocVT == MVT::v8f64) { |
3409 | 0 | static const MCPhysReg RegList7[] = { |
3410 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 |
3411 | 0 | }; |
3412 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
3413 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3414 | 0 | return false; |
3415 | 0 | } |
3416 | 0 | } |
3417 | | |
3418 | 142 | if (LocVT == MVT::x86mmx) { |
3419 | 0 | if (unsigned Reg = State.AllocateReg(X86::MM0)) { |
3420 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3421 | 0 | return false; |
3422 | 0 | } |
3423 | 0 | } |
3424 | | |
3425 | 142 | if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
3426 | 142 | if (LocVT == MVT::f80) { |
3427 | 50 | static const MCPhysReg RegList8[] = { |
3428 | 50 | X86::FP0, X86::FP1 |
3429 | 50 | }; |
3430 | 50 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
3431 | 50 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3432 | 50 | return false; |
3433 | 50 | } |
3434 | 50 | } |
3435 | 142 | } |
3436 | | |
3437 | 92 | return true; // CC didn't match. |
3438 | 142 | } |
3439 | | |
3440 | | |
3441 | | static bool RetCC_X86_32(unsigned ValNo, MVT ValVT, |
3442 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3443 | 53 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3444 | | |
3445 | 53 | if (State.getCallingConv() == CallingConv::Fast) { |
3446 | 0 | if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3447 | 0 | return false; |
3448 | 0 | } |
3449 | | |
3450 | 53 | if (State.getCallingConv() == CallingConv::Tail) { |
3451 | 0 | if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3452 | 0 | return false; |
3453 | 0 | } |
3454 | | |
3455 | 53 | if (State.getCallingConv() == CallingConv::HiPE) { |
3456 | 0 | if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3457 | 0 | return false; |
3458 | 0 | } |
3459 | | |
3460 | 53 | if (State.getCallingConv() == CallingConv::X86_VectorCall) { |
3461 | 0 | if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3462 | 0 | return false; |
3463 | 0 | } |
3464 | | |
3465 | 53 | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
3466 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin32()) { |
3467 | 0 | if (State.getMachineFunction().getFunction().getParent()->getModuleFlag("RegCallv4")!=nullptr) { |
3468 | 0 | if (!RetCC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3469 | 0 | return false; |
3470 | 0 | } |
3471 | 0 | } |
3472 | 0 | } |
3473 | | |
3474 | 53 | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
3475 | 0 | if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3476 | 0 | return false; |
3477 | 0 | } |
3478 | | |
3479 | 53 | if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3480 | 14 | return false; |
3481 | | |
3482 | 39 | return true; // CC didn't match. |
3483 | 53 | } |
3484 | | |
3485 | | |
3486 | | static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT, |
3487 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3488 | 53 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3489 | | |
3490 | 53 | if (ArgFlags.isInReg()) { |
3491 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { |
3492 | 0 | if (LocVT == MVT::f32 || |
3493 | 0 | LocVT == MVT::f64) { |
3494 | 0 | static const MCPhysReg RegList1[] = { |
3495 | 0 | X86::XMM0, X86::XMM1, X86::XMM2 |
3496 | 0 | }; |
3497 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
3498 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3499 | 0 | return false; |
3500 | 0 | } |
3501 | 0 | } |
3502 | 0 | } |
3503 | 0 | } |
3504 | | |
3505 | 53 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasX87()) { |
3506 | 53 | if (LocVT == MVT::f32 || |
3507 | 53 | LocVT == MVT::f64) { |
3508 | 16 | static const MCPhysReg RegList2[] = { |
3509 | 16 | X86::FP0, X86::FP1 |
3510 | 16 | }; |
3511 | 16 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
3512 | 14 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3513 | 14 | return false; |
3514 | 14 | } |
3515 | 16 | } |
3516 | 53 | } |
3517 | | |
3518 | 39 | if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasX87()) { |
3519 | 0 | if (LocVT == MVT::f32) { |
3520 | 0 | static const MCPhysReg RegList3[] = { |
3521 | 0 | X86::EAX, X86::EDX, X86::ECX |
3522 | 0 | }; |
3523 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
3524 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3525 | 0 | return false; |
3526 | 0 | } |
3527 | 0 | } |
3528 | 0 | } |
3529 | | |
3530 | 39 | if (LocVT == MVT::f16) { |
3531 | 0 | static const MCPhysReg RegList4[] = { |
3532 | 0 | X86::XMM0, X86::XMM1, X86::XMM2 |
3533 | 0 | }; |
3534 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
3535 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3536 | 0 | return false; |
3537 | 0 | } |
3538 | 0 | } |
3539 | | |
3540 | 39 | if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3541 | 0 | return false; |
3542 | | |
3543 | 39 | return true; // CC didn't match. |
3544 | 39 | } |
3545 | | |
3546 | | |
3547 | | static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT, |
3548 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3549 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3550 | |
|
3551 | 0 | if (LocVT == MVT::f32) { |
3552 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { |
3553 | 0 | static const MCPhysReg RegList1[] = { |
3554 | 0 | X86::XMM0, X86::XMM1, X86::XMM2 |
3555 | 0 | }; |
3556 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
3557 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3558 | 0 | return false; |
3559 | 0 | } |
3560 | 0 | } |
3561 | 0 | } |
3562 | | |
3563 | 0 | if (LocVT == MVT::f64) { |
3564 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { |
3565 | 0 | static const MCPhysReg RegList2[] = { |
3566 | 0 | X86::XMM0, X86::XMM1, X86::XMM2 |
3567 | 0 | }; |
3568 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
3569 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3570 | 0 | return false; |
3571 | 0 | } |
3572 | 0 | } |
3573 | 0 | } |
3574 | | |
3575 | 0 | if (LocVT == MVT::i8) { |
3576 | 0 | static const MCPhysReg RegList3[] = { |
3577 | 0 | X86::AL, X86::DL, X86::CL |
3578 | 0 | }; |
3579 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
3580 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3581 | 0 | return false; |
3582 | 0 | } |
3583 | 0 | } |
3584 | | |
3585 | 0 | if (LocVT == MVT::i16) { |
3586 | 0 | static const MCPhysReg RegList4[] = { |
3587 | 0 | X86::AX, X86::DX, X86::CX |
3588 | 0 | }; |
3589 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
3590 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3591 | 0 | return false; |
3592 | 0 | } |
3593 | 0 | } |
3594 | | |
3595 | 0 | if (LocVT == MVT::i32) { |
3596 | 0 | static const MCPhysReg RegList5[] = { |
3597 | 0 | X86::EAX, X86::EDX, X86::ECX |
3598 | 0 | }; |
3599 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
3600 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3601 | 0 | return false; |
3602 | 0 | } |
3603 | 0 | } |
3604 | | |
3605 | 0 | if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3606 | 0 | return false; |
3607 | | |
3608 | 0 | return true; // CC didn't match. |
3609 | 0 | } |
3610 | | |
3611 | | |
3612 | | static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT, |
3613 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3614 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3615 | |
|
3616 | 0 | if (LocVT == MVT::i8 || |
3617 | 0 | LocVT == MVT::i16) { |
3618 | 0 | LocVT = MVT::i32; |
3619 | 0 | if (ArgFlags.isSExt()) |
3620 | 0 | LocInfo = CCValAssign::SExt; |
3621 | 0 | else if (ArgFlags.isZExt()) |
3622 | 0 | LocInfo = CCValAssign::ZExt; |
3623 | 0 | else |
3624 | 0 | LocInfo = CCValAssign::AExt; |
3625 | 0 | } |
3626 | |
|
3627 | 0 | if (LocVT == MVT::i32) { |
3628 | 0 | static const MCPhysReg RegList1[] = { |
3629 | 0 | X86::ESI, X86::EBP, X86::EAX, X86::EDX |
3630 | 0 | }; |
3631 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
3632 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3633 | 0 | return false; |
3634 | 0 | } |
3635 | 0 | } |
3636 | | |
3637 | 0 | return true; // CC didn't match. |
3638 | 0 | } |
3639 | | |
3640 | | |
3641 | | static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT, |
3642 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3643 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3644 | |
|
3645 | 0 | if (LocVT == MVT::i1 || |
3646 | 0 | LocVT == MVT::v1i1 || |
3647 | 0 | LocVT == MVT::v8i1) { |
3648 | 0 | LocVT = MVT::i8; |
3649 | 0 | if (ArgFlags.isSExt()) |
3650 | 0 | LocInfo = CCValAssign::SExt; |
3651 | 0 | else if (ArgFlags.isZExt()) |
3652 | 0 | LocInfo = CCValAssign::ZExt; |
3653 | 0 | else |
3654 | 0 | LocInfo = CCValAssign::AExt; |
3655 | 0 | } |
3656 | |
|
3657 | 0 | if (LocVT == MVT::v16i1) { |
3658 | 0 | LocVT = MVT::i16; |
3659 | 0 | if (ArgFlags.isSExt()) |
3660 | 0 | LocInfo = CCValAssign::SExt; |
3661 | 0 | else if (ArgFlags.isZExt()) |
3662 | 0 | LocInfo = CCValAssign::ZExt; |
3663 | 0 | else |
3664 | 0 | LocInfo = CCValAssign::AExt; |
3665 | 0 | } |
3666 | |
|
3667 | 0 | if (LocVT == MVT::v32i1) { |
3668 | 0 | LocVT = MVT::i32; |
3669 | 0 | if (ArgFlags.isSExt()) |
3670 | 0 | LocInfo = CCValAssign::SExt; |
3671 | 0 | else if (ArgFlags.isZExt()) |
3672 | 0 | LocInfo = CCValAssign::ZExt; |
3673 | 0 | else |
3674 | 0 | LocInfo = CCValAssign::AExt; |
3675 | 0 | } |
3676 | |
|
3677 | 0 | if (LocVT == MVT::i8) { |
3678 | 0 | static const MCPhysReg RegList1[] = { |
3679 | 0 | X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL |
3680 | 0 | }; |
3681 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
3682 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3683 | 0 | return false; |
3684 | 0 | } |
3685 | 0 | } |
3686 | | |
3687 | 0 | if (LocVT == MVT::i16) { |
3688 | 0 | static const MCPhysReg RegList2[] = { |
3689 | 0 | X86::AX, X86::CX, X86::DX, X86::DI, X86::SI |
3690 | 0 | }; |
3691 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
3692 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3693 | 0 | return false; |
3694 | 0 | } |
3695 | 0 | } |
3696 | | |
3697 | 0 | if (LocVT == MVT::i32) { |
3698 | 0 | static const MCPhysReg RegList3[] = { |
3699 | 0 | X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI |
3700 | 0 | }; |
3701 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
3702 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3703 | 0 | return false; |
3704 | 0 | } |
3705 | 0 | } |
3706 | | |
3707 | 0 | if (LocVT == MVT::i64) { |
3708 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
3709 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3710 | 0 | return false; |
3711 | 0 | } |
3712 | 0 | } |
3713 | | |
3714 | 0 | if (LocVT == MVT::v64i1) { |
3715 | 0 | LocVT = MVT::i64; |
3716 | 0 | if (ArgFlags.isSExt()) |
3717 | 0 | LocInfo = CCValAssign::SExt; |
3718 | 0 | else if (ArgFlags.isZExt()) |
3719 | 0 | LocInfo = CCValAssign::ZExt; |
3720 | 0 | else |
3721 | 0 | LocInfo = CCValAssign::AExt; |
3722 | 0 | } |
3723 | |
|
3724 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
3725 | 0 | if (LocVT == MVT::i64) { |
3726 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
3727 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3728 | 0 | return false; |
3729 | 0 | } |
3730 | 0 | } |
3731 | 0 | } |
3732 | | |
3733 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
3734 | 0 | if (LocVT == MVT::i64) { |
3735 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3736 | 0 | return false; |
3737 | 0 | } |
3738 | 0 | } |
3739 | | |
3740 | 0 | if (LocVT == MVT::f80) { |
3741 | 0 | static const MCPhysReg RegList4[] = { |
3742 | 0 | X86::FP0, X86::FP1 |
3743 | 0 | }; |
3744 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
3745 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3746 | 0 | return false; |
3747 | 0 | } |
3748 | 0 | } |
3749 | | |
3750 | 0 | if (LocVT == MVT::f32 || |
3751 | 0 | LocVT == MVT::f64 || |
3752 | 0 | LocVT == MVT::f128) { |
3753 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
3754 | 0 | static const MCPhysReg RegList5[] = { |
3755 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
3756 | 0 | }; |
3757 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
3758 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3759 | 0 | return false; |
3760 | 0 | } |
3761 | 0 | } |
3762 | 0 | } |
3763 | | |
3764 | 0 | if (LocVT == MVT::v16i8 || |
3765 | 0 | LocVT == MVT::v8i16 || |
3766 | 0 | LocVT == MVT::v4i32 || |
3767 | 0 | LocVT == MVT::v2i64 || |
3768 | 0 | LocVT == MVT::v4f32 || |
3769 | 0 | LocVT == MVT::v2f64) { |
3770 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
3771 | 0 | static const MCPhysReg RegList6[] = { |
3772 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
3773 | 0 | }; |
3774 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
3775 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3776 | 0 | return false; |
3777 | 0 | } |
3778 | 0 | } |
3779 | 0 | } |
3780 | | |
3781 | 0 | if (LocVT == MVT::v32i8 || |
3782 | 0 | LocVT == MVT::v16i16 || |
3783 | 0 | LocVT == MVT::v8i32 || |
3784 | 0 | LocVT == MVT::v4i64 || |
3785 | 0 | LocVT == MVT::v8f32 || |
3786 | 0 | LocVT == MVT::v4f64) { |
3787 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
3788 | 0 | static const MCPhysReg RegList7[] = { |
3789 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 |
3790 | 0 | }; |
3791 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
3792 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3793 | 0 | return false; |
3794 | 0 | } |
3795 | 0 | } |
3796 | 0 | } |
3797 | | |
3798 | 0 | if (LocVT == MVT::v64i8 || |
3799 | 0 | LocVT == MVT::v32i16 || |
3800 | 0 | LocVT == MVT::v16i32 || |
3801 | 0 | LocVT == MVT::v8i64 || |
3802 | 0 | LocVT == MVT::v16f32 || |
3803 | 0 | LocVT == MVT::v8f64) { |
3804 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
3805 | 0 | static const MCPhysReg RegList8[] = { |
3806 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 |
3807 | 0 | }; |
3808 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
3809 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3810 | 0 | return false; |
3811 | 0 | } |
3812 | 0 | } |
3813 | 0 | } |
3814 | | |
3815 | 0 | return true; // CC didn't match. |
3816 | 0 | } |
3817 | | |
3818 | | |
3819 | | static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT, |
3820 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3821 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
3822 | |
|
3823 | 0 | if (LocVT == MVT::i1 || |
3824 | 0 | LocVT == MVT::v1i1 || |
3825 | 0 | LocVT == MVT::v8i1) { |
3826 | 0 | LocVT = MVT::i8; |
3827 | 0 | if (ArgFlags.isSExt()) |
3828 | 0 | LocInfo = CCValAssign::SExt; |
3829 | 0 | else if (ArgFlags.isZExt()) |
3830 | 0 | LocInfo = CCValAssign::ZExt; |
3831 | 0 | else |
3832 | 0 | LocInfo = CCValAssign::AExt; |
3833 | 0 | } |
3834 | |
|
3835 | 0 | if (LocVT == MVT::v16i1) { |
3836 | 0 | LocVT = MVT::i16; |
3837 | 0 | if (ArgFlags.isSExt()) |
3838 | 0 | LocInfo = CCValAssign::SExt; |
3839 | 0 | else if (ArgFlags.isZExt()) |
3840 | 0 | LocInfo = CCValAssign::ZExt; |
3841 | 0 | else |
3842 | 0 | LocInfo = CCValAssign::AExt; |
3843 | 0 | } |
3844 | |
|
3845 | 0 | if (LocVT == MVT::v32i1) { |
3846 | 0 | LocVT = MVT::i32; |
3847 | 0 | if (ArgFlags.isSExt()) |
3848 | 0 | LocInfo = CCValAssign::SExt; |
3849 | 0 | else if (ArgFlags.isZExt()) |
3850 | 0 | LocInfo = CCValAssign::ZExt; |
3851 | 0 | else |
3852 | 0 | LocInfo = CCValAssign::AExt; |
3853 | 0 | } |
3854 | |
|
3855 | 0 | if (LocVT == MVT::i8) { |
3856 | 0 | static const MCPhysReg RegList1[] = { |
3857 | 0 | X86::CL, X86::DL, X86::DIL, X86::SIL |
3858 | 0 | }; |
3859 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
3860 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3861 | 0 | return false; |
3862 | 0 | } |
3863 | 0 | } |
3864 | | |
3865 | 0 | if (LocVT == MVT::i16) { |
3866 | 0 | static const MCPhysReg RegList2[] = { |
3867 | 0 | X86::CX, X86::DX, X86::DI, X86::SI |
3868 | 0 | }; |
3869 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
3870 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3871 | 0 | return false; |
3872 | 0 | } |
3873 | 0 | } |
3874 | | |
3875 | 0 | if (LocVT == MVT::i32) { |
3876 | 0 | static const MCPhysReg RegList3[] = { |
3877 | 0 | X86::ECX, X86::EDX, X86::EDI, X86::ESI |
3878 | 0 | }; |
3879 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
3880 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3881 | 0 | return false; |
3882 | 0 | } |
3883 | 0 | } |
3884 | | |
3885 | 0 | if (LocVT == MVT::i64) { |
3886 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
3887 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3888 | 0 | return false; |
3889 | 0 | } |
3890 | 0 | } |
3891 | | |
3892 | 0 | if (LocVT == MVT::v64i1) { |
3893 | 0 | LocVT = MVT::i64; |
3894 | 0 | if (ArgFlags.isSExt()) |
3895 | 0 | LocInfo = CCValAssign::SExt; |
3896 | 0 | else if (ArgFlags.isZExt()) |
3897 | 0 | LocInfo = CCValAssign::ZExt; |
3898 | 0 | else |
3899 | 0 | LocInfo = CCValAssign::AExt; |
3900 | 0 | } |
3901 | |
|
3902 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
3903 | 0 | if (LocVT == MVT::i64) { |
3904 | 0 | if (unsigned Reg = State.AllocateReg(X86::RAX)) { |
3905 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3906 | 0 | return false; |
3907 | 0 | } |
3908 | 0 | } |
3909 | 0 | } |
3910 | | |
3911 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
3912 | 0 | if (LocVT == MVT::i64) { |
3913 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
3914 | 0 | return false; |
3915 | 0 | } |
3916 | 0 | } |
3917 | | |
3918 | 0 | if (LocVT == MVT::f80) { |
3919 | 0 | static const MCPhysReg RegList4[] = { |
3920 | 0 | X86::FP0, X86::FP1 |
3921 | 0 | }; |
3922 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
3923 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3924 | 0 | return false; |
3925 | 0 | } |
3926 | 0 | } |
3927 | | |
3928 | 0 | if (LocVT == MVT::f32 || |
3929 | 0 | LocVT == MVT::f64 || |
3930 | 0 | LocVT == MVT::f128) { |
3931 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
3932 | 0 | static const MCPhysReg RegList5[] = { |
3933 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
3934 | 0 | }; |
3935 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
3936 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3937 | 0 | return false; |
3938 | 0 | } |
3939 | 0 | } |
3940 | 0 | } |
3941 | | |
3942 | 0 | if (LocVT == MVT::v16i8 || |
3943 | 0 | LocVT == MVT::v8i16 || |
3944 | 0 | LocVT == MVT::v4i32 || |
3945 | 0 | LocVT == MVT::v2i64 || |
3946 | 0 | LocVT == MVT::v4f32 || |
3947 | 0 | LocVT == MVT::v2f64) { |
3948 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
3949 | 0 | static const MCPhysReg RegList6[] = { |
3950 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
3951 | 0 | }; |
3952 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
3953 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3954 | 0 | return false; |
3955 | 0 | } |
3956 | 0 | } |
3957 | 0 | } |
3958 | | |
3959 | 0 | if (LocVT == MVT::v32i8 || |
3960 | 0 | LocVT == MVT::v16i16 || |
3961 | 0 | LocVT == MVT::v8i32 || |
3962 | 0 | LocVT == MVT::v4i64 || |
3963 | 0 | LocVT == MVT::v8f32 || |
3964 | 0 | LocVT == MVT::v4f64) { |
3965 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
3966 | 0 | static const MCPhysReg RegList7[] = { |
3967 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 |
3968 | 0 | }; |
3969 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
3970 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3971 | 0 | return false; |
3972 | 0 | } |
3973 | 0 | } |
3974 | 0 | } |
3975 | | |
3976 | 0 | if (LocVT == MVT::v64i8 || |
3977 | 0 | LocVT == MVT::v32i16 || |
3978 | 0 | LocVT == MVT::v16i32 || |
3979 | 0 | LocVT == MVT::v8i64 || |
3980 | 0 | LocVT == MVT::v16f32 || |
3981 | 0 | LocVT == MVT::v8f64) { |
3982 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
3983 | 0 | static const MCPhysReg RegList8[] = { |
3984 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 |
3985 | 0 | }; |
3986 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
3987 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
3988 | 0 | return false; |
3989 | 0 | } |
3990 | 0 | } |
3991 | 0 | } |
3992 | | |
3993 | 0 | return true; // CC didn't match. |
3994 | 0 | } |
3995 | | |
3996 | | |
3997 | | static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT, |
3998 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
3999 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4000 | |
|
4001 | 0 | if (LocVT == MVT::f32 || |
4002 | 0 | LocVT == MVT::f64 || |
4003 | 0 | LocVT == MVT::f128) { |
4004 | 0 | static const MCPhysReg RegList1[] = { |
4005 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
4006 | 0 | }; |
4007 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
4008 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4009 | 0 | return false; |
4010 | 0 | } |
4011 | 0 | } |
4012 | | |
4013 | 0 | if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4014 | 0 | return false; |
4015 | | |
4016 | 0 | return true; // CC didn't match. |
4017 | 0 | } |
4018 | | |
4019 | | |
4020 | | static bool RetCC_X86_64(unsigned ValNo, MVT ValVT, |
4021 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4022 | 47.3k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4023 | | |
4024 | 47.3k | if (State.getCallingConv() == CallingConv::HiPE) { |
4025 | 0 | if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4026 | 0 | return false; |
4027 | 0 | } |
4028 | | |
4029 | 47.3k | if (State.getCallingConv() == CallingConv::AnyReg) { |
4030 | 0 | if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4031 | 0 | return false; |
4032 | 0 | } |
4033 | | |
4034 | 47.3k | if (State.getCallingConv() == CallingConv::Swift) { |
4035 | 0 | if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4036 | 0 | return false; |
4037 | 0 | } |
4038 | | |
4039 | 47.3k | if (State.getCallingConv() == CallingConv::SwiftTail) { |
4040 | 0 | if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4041 | 0 | return false; |
4042 | 0 | } |
4043 | | |
4044 | 47.3k | if (State.getCallingConv() == CallingConv::Win64) { |
4045 | 0 | if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4046 | 0 | return false; |
4047 | 0 | } |
4048 | | |
4049 | 47.3k | if (State.getCallingConv() == CallingConv::X86_64_SysV) { |
4050 | 0 | if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4051 | 0 | return false; |
4052 | 0 | } |
4053 | | |
4054 | 47.3k | if (State.getCallingConv() == CallingConv::X86_VectorCall) { |
4055 | 0 | if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4056 | 0 | return false; |
4057 | 0 | } |
4058 | | |
4059 | 47.3k | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
4060 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
4061 | 0 | if (State.getMachineFunction().getFunction().getParent()->getModuleFlag("RegCallv4")!=nullptr) { |
4062 | 0 | if (!RetCC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4063 | 0 | return false; |
4064 | 0 | } |
4065 | 0 | } |
4066 | 0 | } |
4067 | | |
4068 | 47.3k | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
4069 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
4070 | 0 | if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4071 | 0 | return false; |
4072 | 0 | } |
4073 | 0 | } |
4074 | | |
4075 | 47.3k | if (State.getCallingConv() == CallingConv::X86_RegCall) { |
4076 | 0 | if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4077 | 0 | return false; |
4078 | 0 | } |
4079 | | |
4080 | 47.3k | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { |
4081 | 0 | if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4082 | 0 | return false; |
4083 | 0 | } |
4084 | | |
4085 | 47.3k | if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4086 | 47.3k | return false; |
4087 | | |
4088 | 53 | return true; // CC didn't match. |
4089 | 47.3k | } |
4090 | | |
4091 | | |
4092 | | static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, |
4093 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4094 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4095 | |
|
4096 | 0 | if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4097 | 0 | return false; |
4098 | | |
4099 | 0 | return true; // CC didn't match. |
4100 | 0 | } |
4101 | | |
4102 | | |
4103 | | static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT, |
4104 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4105 | 47.3k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4106 | | |
4107 | 47.3k | if (LocVT == MVT::f16) { |
4108 | 858 | static const MCPhysReg RegList1[] = { |
4109 | 858 | X86::XMM0, X86::XMM1 |
4110 | 858 | }; |
4111 | 858 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
4112 | 858 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4113 | 858 | return false; |
4114 | 858 | } |
4115 | 858 | } |
4116 | | |
4117 | 46.4k | if (LocVT == MVT::f32) { |
4118 | 5.92k | static const MCPhysReg RegList2[] = { |
4119 | 5.92k | X86::XMM0, X86::XMM1 |
4120 | 5.92k | }; |
4121 | 5.92k | if (unsigned Reg = State.AllocateReg(RegList2)) { |
4122 | 5.91k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4123 | 5.91k | return false; |
4124 | 5.91k | } |
4125 | 5.92k | } |
4126 | | |
4127 | 40.5k | if (LocVT == MVT::f64) { |
4128 | 2.82k | static const MCPhysReg RegList3[] = { |
4129 | 2.82k | X86::XMM0, X86::XMM1 |
4130 | 2.82k | }; |
4131 | 2.82k | if (unsigned Reg = State.AllocateReg(RegList3)) { |
4132 | 2.81k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4133 | 2.81k | return false; |
4134 | 2.81k | } |
4135 | 2.82k | } |
4136 | | |
4137 | 37.7k | if (LocVT == MVT::f128) { |
4138 | 173 | static const MCPhysReg RegList4[] = { |
4139 | 173 | X86::XMM0, X86::XMM1 |
4140 | 173 | }; |
4141 | 173 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
4142 | 173 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4143 | 173 | return false; |
4144 | 173 | } |
4145 | 173 | } |
4146 | | |
4147 | 37.5k | if (LocVT == MVT::x86mmx) { |
4148 | 0 | static const MCPhysReg RegList5[] = { |
4149 | 0 | X86::XMM0, X86::XMM1 |
4150 | 0 | }; |
4151 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
4152 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4153 | 0 | return false; |
4154 | 0 | } |
4155 | 0 | } |
4156 | | |
4157 | 37.5k | if (ArgFlags.isPointer()) { |
4158 | 344 | if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4159 | 0 | return false; |
4160 | 344 | } |
4161 | | |
4162 | 37.5k | if (ArgFlags.isSwiftError()) { |
4163 | 0 | if (LocVT == MVT::i64) { |
4164 | 0 | if (unsigned Reg = State.AllocateReg(X86::R12)) { |
4165 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4166 | 0 | return false; |
4167 | 0 | } |
4168 | 0 | } |
4169 | 0 | } |
4170 | | |
4171 | 37.5k | if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4172 | 37.5k | return false; |
4173 | | |
4174 | 53 | return true; // CC didn't match. |
4175 | 37.5k | } |
4176 | | |
4177 | | |
4178 | | static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT, |
4179 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4180 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4181 | |
|
4182 | 0 | if (LocVT == MVT::i8 || |
4183 | 0 | LocVT == MVT::i16 || |
4184 | 0 | LocVT == MVT::i32) { |
4185 | 0 | LocVT = MVT::i64; |
4186 | 0 | if (ArgFlags.isSExt()) |
4187 | 0 | LocInfo = CCValAssign::SExt; |
4188 | 0 | else if (ArgFlags.isZExt()) |
4189 | 0 | LocInfo = CCValAssign::ZExt; |
4190 | 0 | else |
4191 | 0 | LocInfo = CCValAssign::AExt; |
4192 | 0 | } |
4193 | |
|
4194 | 0 | if (LocVT == MVT::i64) { |
4195 | 0 | static const MCPhysReg RegList1[] = { |
4196 | 0 | X86::R15, X86::RBP, X86::RAX, X86::RDX |
4197 | 0 | }; |
4198 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
4199 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4200 | 0 | return false; |
4201 | 0 | } |
4202 | 0 | } |
4203 | | |
4204 | 0 | return true; // CC didn't match. |
4205 | 0 | } |
4206 | | |
4207 | | |
4208 | | static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT, |
4209 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4210 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4211 | |
|
4212 | 0 | if (ArgFlags.isSwiftError()) { |
4213 | 0 | if (LocVT == MVT::i64) { |
4214 | 0 | if (unsigned Reg = State.AllocateReg(X86::R12)) { |
4215 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4216 | 0 | return false; |
4217 | 0 | } |
4218 | 0 | } |
4219 | 0 | } |
4220 | | |
4221 | 0 | if (LocVT == MVT::v1i1) { |
4222 | 0 | LocVT = MVT::i8; |
4223 | 0 | if (ArgFlags.isSExt()) |
4224 | 0 | LocInfo = CCValAssign::SExt; |
4225 | 0 | else if (ArgFlags.isZExt()) |
4226 | 0 | LocInfo = CCValAssign::ZExt; |
4227 | 0 | else |
4228 | 0 | LocInfo = CCValAssign::AExt; |
4229 | 0 | } |
4230 | |
|
4231 | 0 | if (LocVT == MVT::i1) { |
4232 | 0 | LocVT = MVT::i8; |
4233 | 0 | if (ArgFlags.isSExt()) |
4234 | 0 | LocInfo = CCValAssign::SExt; |
4235 | 0 | else if (ArgFlags.isZExt()) |
4236 | 0 | LocInfo = CCValAssign::ZExt; |
4237 | 0 | else |
4238 | 0 | LocInfo = CCValAssign::AExt; |
4239 | 0 | } |
4240 | |
|
4241 | 0 | if (LocVT == MVT::i8) { |
4242 | 0 | static const MCPhysReg RegList1[] = { |
4243 | 0 | X86::AL, X86::DL, X86::CL, X86::R8B |
4244 | 0 | }; |
4245 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
4246 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4247 | 0 | return false; |
4248 | 0 | } |
4249 | 0 | } |
4250 | | |
4251 | 0 | if (LocVT == MVT::i16) { |
4252 | 0 | static const MCPhysReg RegList2[] = { |
4253 | 0 | X86::AX, X86::DX, X86::CX, X86::R8W |
4254 | 0 | }; |
4255 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
4256 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4257 | 0 | return false; |
4258 | 0 | } |
4259 | 0 | } |
4260 | | |
4261 | 0 | if (LocVT == MVT::i32) { |
4262 | 0 | static const MCPhysReg RegList3[] = { |
4263 | 0 | X86::EAX, X86::EDX, X86::ECX, X86::R8D |
4264 | 0 | }; |
4265 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
4266 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4267 | 0 | return false; |
4268 | 0 | } |
4269 | 0 | } |
4270 | | |
4271 | 0 | if (LocVT == MVT::i64) { |
4272 | 0 | static const MCPhysReg RegList4[] = { |
4273 | 0 | X86::RAX, X86::RDX, X86::RCX, X86::R8 |
4274 | 0 | }; |
4275 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
4276 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4277 | 0 | return false; |
4278 | 0 | } |
4279 | 0 | } |
4280 | | |
4281 | 0 | if (LocVT == MVT::f32) { |
4282 | 0 | static const MCPhysReg RegList5[] = { |
4283 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
4284 | 0 | }; |
4285 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
4286 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4287 | 0 | return false; |
4288 | 0 | } |
4289 | 0 | } |
4290 | | |
4291 | 0 | if (LocVT == MVT::f64) { |
4292 | 0 | static const MCPhysReg RegList6[] = { |
4293 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
4294 | 0 | }; |
4295 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
4296 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4297 | 0 | return false; |
4298 | 0 | } |
4299 | 0 | } |
4300 | | |
4301 | 0 | if (LocVT == MVT::f128) { |
4302 | 0 | static const MCPhysReg RegList7[] = { |
4303 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
4304 | 0 | }; |
4305 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
4306 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4307 | 0 | return false; |
4308 | 0 | } |
4309 | 0 | } |
4310 | | |
4311 | 0 | if (LocVT == MVT::x86mmx) { |
4312 | 0 | static const MCPhysReg RegList8[] = { |
4313 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
4314 | 0 | }; |
4315 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
4316 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4317 | 0 | return false; |
4318 | 0 | } |
4319 | 0 | } |
4320 | | |
4321 | 0 | if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4322 | 0 | return false; |
4323 | | |
4324 | 0 | return true; // CC didn't match. |
4325 | 0 | } |
4326 | | |
4327 | | |
4328 | | static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT, |
4329 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4330 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4331 | |
|
4332 | 0 | if (LocVT == MVT::f32 || |
4333 | 0 | LocVT == MVT::f64 || |
4334 | 0 | LocVT == MVT::f128) { |
4335 | 0 | static const MCPhysReg RegList1[] = { |
4336 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
4337 | 0 | }; |
4338 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
4339 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4340 | 0 | return false; |
4341 | 0 | } |
4342 | 0 | } |
4343 | | |
4344 | 0 | if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4345 | 0 | return false; |
4346 | | |
4347 | 0 | return true; // CC didn't match. |
4348 | 0 | } |
4349 | | |
4350 | | |
4351 | | static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, |
4352 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4353 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4354 | |
|
4355 | 0 | if (LocVT == MVT::i1 || |
4356 | 0 | LocVT == MVT::v1i1 || |
4357 | 0 | LocVT == MVT::v8i1) { |
4358 | 0 | LocVT = MVT::i8; |
4359 | 0 | if (ArgFlags.isSExt()) |
4360 | 0 | LocInfo = CCValAssign::SExt; |
4361 | 0 | else if (ArgFlags.isZExt()) |
4362 | 0 | LocInfo = CCValAssign::ZExt; |
4363 | 0 | else |
4364 | 0 | LocInfo = CCValAssign::AExt; |
4365 | 0 | } |
4366 | |
|
4367 | 0 | if (LocVT == MVT::v16i1) { |
4368 | 0 | LocVT = MVT::i16; |
4369 | 0 | if (ArgFlags.isSExt()) |
4370 | 0 | LocInfo = CCValAssign::SExt; |
4371 | 0 | else if (ArgFlags.isZExt()) |
4372 | 0 | LocInfo = CCValAssign::ZExt; |
4373 | 0 | else |
4374 | 0 | LocInfo = CCValAssign::AExt; |
4375 | 0 | } |
4376 | |
|
4377 | 0 | if (LocVT == MVT::v32i1) { |
4378 | 0 | LocVT = MVT::i32; |
4379 | 0 | if (ArgFlags.isSExt()) |
4380 | 0 | LocInfo = CCValAssign::SExt; |
4381 | 0 | else if (ArgFlags.isZExt()) |
4382 | 0 | LocInfo = CCValAssign::ZExt; |
4383 | 0 | else |
4384 | 0 | LocInfo = CCValAssign::AExt; |
4385 | 0 | } |
4386 | |
|
4387 | 0 | if (LocVT == MVT::i8) { |
4388 | 0 | static const MCPhysReg RegList1[] = { |
4389 | 0 | X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B |
4390 | 0 | }; |
4391 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
4392 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4393 | 0 | return false; |
4394 | 0 | } |
4395 | 0 | } |
4396 | | |
4397 | 0 | if (LocVT == MVT::i16) { |
4398 | 0 | static const MCPhysReg RegList2[] = { |
4399 | 0 | X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W |
4400 | 0 | }; |
4401 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
4402 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4403 | 0 | return false; |
4404 | 0 | } |
4405 | 0 | } |
4406 | | |
4407 | 0 | if (LocVT == MVT::i32) { |
4408 | 0 | static const MCPhysReg RegList3[] = { |
4409 | 0 | X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D |
4410 | 0 | }; |
4411 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
4412 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4413 | 0 | return false; |
4414 | 0 | } |
4415 | 0 | } |
4416 | | |
4417 | 0 | if (LocVT == MVT::i64) { |
4418 | 0 | static const MCPhysReg RegList4[] = { |
4419 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 |
4420 | 0 | }; |
4421 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
4422 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4423 | 0 | return false; |
4424 | 0 | } |
4425 | 0 | } |
4426 | | |
4427 | 0 | if (LocVT == MVT::v64i1) { |
4428 | 0 | LocVT = MVT::i64; |
4429 | 0 | if (ArgFlags.isSExt()) |
4430 | 0 | LocInfo = CCValAssign::SExt; |
4431 | 0 | else if (ArgFlags.isZExt()) |
4432 | 0 | LocInfo = CCValAssign::ZExt; |
4433 | 0 | else |
4434 | 0 | LocInfo = CCValAssign::AExt; |
4435 | 0 | } |
4436 | |
|
4437 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
4438 | 0 | if (LocVT == MVT::i64) { |
4439 | 0 | static const MCPhysReg RegList5[] = { |
4440 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 |
4441 | 0 | }; |
4442 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
4443 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4444 | 0 | return false; |
4445 | 0 | } |
4446 | 0 | } |
4447 | 0 | } |
4448 | | |
4449 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
4450 | 0 | if (LocVT == MVT::i64) { |
4451 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4452 | 0 | return false; |
4453 | 0 | } |
4454 | 0 | } |
4455 | | |
4456 | 0 | if (LocVT == MVT::f80) { |
4457 | 0 | static const MCPhysReg RegList6[] = { |
4458 | 0 | X86::FP0, X86::FP1 |
4459 | 0 | }; |
4460 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
4461 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4462 | 0 | return false; |
4463 | 0 | } |
4464 | 0 | } |
4465 | | |
4466 | 0 | if (LocVT == MVT::f32 || |
4467 | 0 | LocVT == MVT::f64 || |
4468 | 0 | LocVT == MVT::f128) { |
4469 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
4470 | 0 | static const MCPhysReg RegList7[] = { |
4471 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
4472 | 0 | }; |
4473 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
4474 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4475 | 0 | return false; |
4476 | 0 | } |
4477 | 0 | } |
4478 | 0 | } |
4479 | | |
4480 | 0 | if (LocVT == MVT::v16i8 || |
4481 | 0 | LocVT == MVT::v8i16 || |
4482 | 0 | LocVT == MVT::v4i32 || |
4483 | 0 | LocVT == MVT::v2i64 || |
4484 | 0 | LocVT == MVT::v4f32 || |
4485 | 0 | LocVT == MVT::v2f64) { |
4486 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
4487 | 0 | static const MCPhysReg RegList8[] = { |
4488 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
4489 | 0 | }; |
4490 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
4491 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4492 | 0 | return false; |
4493 | 0 | } |
4494 | 0 | } |
4495 | 0 | } |
4496 | | |
4497 | 0 | if (LocVT == MVT::v32i8 || |
4498 | 0 | LocVT == MVT::v16i16 || |
4499 | 0 | LocVT == MVT::v8i32 || |
4500 | 0 | LocVT == MVT::v4i64 || |
4501 | 0 | LocVT == MVT::v8f32 || |
4502 | 0 | LocVT == MVT::v4f64) { |
4503 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
4504 | 0 | static const MCPhysReg RegList9[] = { |
4505 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 |
4506 | 0 | }; |
4507 | 0 | if (unsigned Reg = State.AllocateReg(RegList9)) { |
4508 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4509 | 0 | return false; |
4510 | 0 | } |
4511 | 0 | } |
4512 | 0 | } |
4513 | | |
4514 | 0 | if (LocVT == MVT::v64i8 || |
4515 | 0 | LocVT == MVT::v32i16 || |
4516 | 0 | LocVT == MVT::v16i32 || |
4517 | 0 | LocVT == MVT::v8i64 || |
4518 | 0 | LocVT == MVT::v16f32 || |
4519 | 0 | LocVT == MVT::v8f64) { |
4520 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
4521 | 0 | static const MCPhysReg RegList10[] = { |
4522 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 |
4523 | 0 | }; |
4524 | 0 | if (unsigned Reg = State.AllocateReg(RegList10)) { |
4525 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4526 | 0 | return false; |
4527 | 0 | } |
4528 | 0 | } |
4529 | 0 | } |
4530 | | |
4531 | 0 | return true; // CC didn't match. |
4532 | 0 | } |
4533 | | |
4534 | | |
4535 | | static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT, |
4536 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4537 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4538 | |
|
4539 | 0 | if (LocVT == MVT::x86mmx) { |
4540 | 0 | LocVT = MVT::i64; |
4541 | 0 | LocInfo = CCValAssign::BCvt; |
4542 | 0 | } |
4543 | |
|
4544 | 0 | if (LocVT == MVT::f32) { |
4545 | 0 | if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
4546 | 0 | LocVT = MVT::i32; |
4547 | 0 | LocInfo = CCValAssign::BCvt; |
4548 | 0 | } |
4549 | 0 | } |
4550 | |
|
4551 | 0 | if (LocVT == MVT::f64) { |
4552 | 0 | if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
4553 | 0 | LocVT = MVT::i64; |
4554 | 0 | LocInfo = CCValAssign::BCvt; |
4555 | 0 | } |
4556 | 0 | } |
4557 | |
|
4558 | 0 | if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4559 | 0 | return false; |
4560 | | |
4561 | 0 | return true; // CC didn't match. |
4562 | 0 | } |
4563 | | |
4564 | | |
4565 | | static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, |
4566 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4567 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4568 | |
|
4569 | 0 | if (LocVT == MVT::i1 || |
4570 | 0 | LocVT == MVT::v1i1 || |
4571 | 0 | LocVT == MVT::v8i1) { |
4572 | 0 | LocVT = MVT::i8; |
4573 | 0 | if (ArgFlags.isSExt()) |
4574 | 0 | LocInfo = CCValAssign::SExt; |
4575 | 0 | else if (ArgFlags.isZExt()) |
4576 | 0 | LocInfo = CCValAssign::ZExt; |
4577 | 0 | else |
4578 | 0 | LocInfo = CCValAssign::AExt; |
4579 | 0 | } |
4580 | |
|
4581 | 0 | if (LocVT == MVT::v16i1) { |
4582 | 0 | LocVT = MVT::i16; |
4583 | 0 | if (ArgFlags.isSExt()) |
4584 | 0 | LocInfo = CCValAssign::SExt; |
4585 | 0 | else if (ArgFlags.isZExt()) |
4586 | 0 | LocInfo = CCValAssign::ZExt; |
4587 | 0 | else |
4588 | 0 | LocInfo = CCValAssign::AExt; |
4589 | 0 | } |
4590 | |
|
4591 | 0 | if (LocVT == MVT::v32i1) { |
4592 | 0 | LocVT = MVT::i32; |
4593 | 0 | if (ArgFlags.isSExt()) |
4594 | 0 | LocInfo = CCValAssign::SExt; |
4595 | 0 | else if (ArgFlags.isZExt()) |
4596 | 0 | LocInfo = CCValAssign::ZExt; |
4597 | 0 | else |
4598 | 0 | LocInfo = CCValAssign::AExt; |
4599 | 0 | } |
4600 | |
|
4601 | 0 | if (LocVT == MVT::i8) { |
4602 | 0 | static const MCPhysReg RegList1[] = { |
4603 | 0 | X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B |
4604 | 0 | }; |
4605 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
4606 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4607 | 0 | return false; |
4608 | 0 | } |
4609 | 0 | } |
4610 | | |
4611 | 0 | if (LocVT == MVT::i16) { |
4612 | 0 | static const MCPhysReg RegList2[] = { |
4613 | 0 | X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W |
4614 | 0 | }; |
4615 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
4616 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4617 | 0 | return false; |
4618 | 0 | } |
4619 | 0 | } |
4620 | | |
4621 | 0 | if (LocVT == MVT::i32) { |
4622 | 0 | static const MCPhysReg RegList3[] = { |
4623 | 0 | X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D |
4624 | 0 | }; |
4625 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
4626 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4627 | 0 | return false; |
4628 | 0 | } |
4629 | 0 | } |
4630 | | |
4631 | 0 | if (LocVT == MVT::i64) { |
4632 | 0 | static const MCPhysReg RegList4[] = { |
4633 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 |
4634 | 0 | }; |
4635 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
4636 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4637 | 0 | return false; |
4638 | 0 | } |
4639 | 0 | } |
4640 | | |
4641 | 0 | if (LocVT == MVT::v64i1) { |
4642 | 0 | LocVT = MVT::i64; |
4643 | 0 | if (ArgFlags.isSExt()) |
4644 | 0 | LocInfo = CCValAssign::SExt; |
4645 | 0 | else if (ArgFlags.isZExt()) |
4646 | 0 | LocInfo = CCValAssign::ZExt; |
4647 | 0 | else |
4648 | 0 | LocInfo = CCValAssign::AExt; |
4649 | 0 | } |
4650 | |
|
4651 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
4652 | 0 | if (LocVT == MVT::i64) { |
4653 | 0 | static const MCPhysReg RegList5[] = { |
4654 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 |
4655 | 0 | }; |
4656 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
4657 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4658 | 0 | return false; |
4659 | 0 | } |
4660 | 0 | } |
4661 | 0 | } |
4662 | | |
4663 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
4664 | 0 | if (LocVT == MVT::i64) { |
4665 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4666 | 0 | return false; |
4667 | 0 | } |
4668 | 0 | } |
4669 | | |
4670 | 0 | if (LocVT == MVT::f80) { |
4671 | 0 | static const MCPhysReg RegList6[] = { |
4672 | 0 | X86::FP0, X86::FP1 |
4673 | 0 | }; |
4674 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
4675 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4676 | 0 | return false; |
4677 | 0 | } |
4678 | 0 | } |
4679 | | |
4680 | 0 | if (LocVT == MVT::f32 || |
4681 | 0 | LocVT == MVT::f64 || |
4682 | 0 | LocVT == MVT::f128) { |
4683 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
4684 | 0 | static const MCPhysReg RegList7[] = { |
4685 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
4686 | 0 | }; |
4687 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
4688 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4689 | 0 | return false; |
4690 | 0 | } |
4691 | 0 | } |
4692 | 0 | } |
4693 | | |
4694 | 0 | if (LocVT == MVT::v16i8 || |
4695 | 0 | LocVT == MVT::v8i16 || |
4696 | 0 | LocVT == MVT::v4i32 || |
4697 | 0 | LocVT == MVT::v2i64 || |
4698 | 0 | LocVT == MVT::v4f32 || |
4699 | 0 | LocVT == MVT::v2f64) { |
4700 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
4701 | 0 | static const MCPhysReg RegList8[] = { |
4702 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
4703 | 0 | }; |
4704 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
4705 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4706 | 0 | return false; |
4707 | 0 | } |
4708 | 0 | } |
4709 | 0 | } |
4710 | | |
4711 | 0 | if (LocVT == MVT::v32i8 || |
4712 | 0 | LocVT == MVT::v16i16 || |
4713 | 0 | LocVT == MVT::v8i32 || |
4714 | 0 | LocVT == MVT::v4i64 || |
4715 | 0 | LocVT == MVT::v8f32 || |
4716 | 0 | LocVT == MVT::v4f64) { |
4717 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
4718 | 0 | static const MCPhysReg RegList9[] = { |
4719 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 |
4720 | 0 | }; |
4721 | 0 | if (unsigned Reg = State.AllocateReg(RegList9)) { |
4722 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4723 | 0 | return false; |
4724 | 0 | } |
4725 | 0 | } |
4726 | 0 | } |
4727 | | |
4728 | 0 | if (LocVT == MVT::v64i8 || |
4729 | 0 | LocVT == MVT::v32i16 || |
4730 | 0 | LocVT == MVT::v16i32 || |
4731 | 0 | LocVT == MVT::v8i64 || |
4732 | 0 | LocVT == MVT::v16f32 || |
4733 | 0 | LocVT == MVT::v8f64) { |
4734 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
4735 | 0 | static const MCPhysReg RegList10[] = { |
4736 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 |
4737 | 0 | }; |
4738 | 0 | if (unsigned Reg = State.AllocateReg(RegList10)) { |
4739 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4740 | 0 | return false; |
4741 | 0 | } |
4742 | 0 | } |
4743 | 0 | } |
4744 | | |
4745 | 0 | return true; // CC didn't match. |
4746 | 0 | } |
4747 | | |
4748 | | |
4749 | | static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT, |
4750 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
4751 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
4752 | |
|
4753 | 0 | if (LocVT == MVT::i1 || |
4754 | 0 | LocVT == MVT::v1i1 || |
4755 | 0 | LocVT == MVT::v8i1) { |
4756 | 0 | LocVT = MVT::i8; |
4757 | 0 | if (ArgFlags.isSExt()) |
4758 | 0 | LocInfo = CCValAssign::SExt; |
4759 | 0 | else if (ArgFlags.isZExt()) |
4760 | 0 | LocInfo = CCValAssign::ZExt; |
4761 | 0 | else |
4762 | 0 | LocInfo = CCValAssign::AExt; |
4763 | 0 | } |
4764 | |
|
4765 | 0 | if (LocVT == MVT::v16i1) { |
4766 | 0 | LocVT = MVT::i16; |
4767 | 0 | if (ArgFlags.isSExt()) |
4768 | 0 | LocInfo = CCValAssign::SExt; |
4769 | 0 | else if (ArgFlags.isZExt()) |
4770 | 0 | LocInfo = CCValAssign::ZExt; |
4771 | 0 | else |
4772 | 0 | LocInfo = CCValAssign::AExt; |
4773 | 0 | } |
4774 | |
|
4775 | 0 | if (LocVT == MVT::v32i1) { |
4776 | 0 | LocVT = MVT::i32; |
4777 | 0 | if (ArgFlags.isSExt()) |
4778 | 0 | LocInfo = CCValAssign::SExt; |
4779 | 0 | else if (ArgFlags.isZExt()) |
4780 | 0 | LocInfo = CCValAssign::ZExt; |
4781 | 0 | else |
4782 | 0 | LocInfo = CCValAssign::AExt; |
4783 | 0 | } |
4784 | |
|
4785 | 0 | if (LocVT == MVT::i8) { |
4786 | 0 | static const MCPhysReg RegList1[] = { |
4787 | 0 | X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R11B, X86::R12B, X86::R14B, X86::R15B |
4788 | 0 | }; |
4789 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
4790 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4791 | 0 | return false; |
4792 | 0 | } |
4793 | 0 | } |
4794 | | |
4795 | 0 | if (LocVT == MVT::i16) { |
4796 | 0 | static const MCPhysReg RegList2[] = { |
4797 | 0 | X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R11W, X86::R12W, X86::R14W, X86::R15W |
4798 | 0 | }; |
4799 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
4800 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4801 | 0 | return false; |
4802 | 0 | } |
4803 | 0 | } |
4804 | | |
4805 | 0 | if (LocVT == MVT::i32) { |
4806 | 0 | static const MCPhysReg RegList3[] = { |
4807 | 0 | X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D |
4808 | 0 | }; |
4809 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
4810 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4811 | 0 | return false; |
4812 | 0 | } |
4813 | 0 | } |
4814 | | |
4815 | 0 | if (LocVT == MVT::i64) { |
4816 | 0 | static const MCPhysReg RegList4[] = { |
4817 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15 |
4818 | 0 | }; |
4819 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
4820 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4821 | 0 | return false; |
4822 | 0 | } |
4823 | 0 | } |
4824 | | |
4825 | 0 | if (LocVT == MVT::v64i1) { |
4826 | 0 | LocVT = MVT::i64; |
4827 | 0 | if (ArgFlags.isSExt()) |
4828 | 0 | LocInfo = CCValAssign::SExt; |
4829 | 0 | else if (ArgFlags.isZExt()) |
4830 | 0 | LocInfo = CCValAssign::ZExt; |
4831 | 0 | else |
4832 | 0 | LocInfo = CCValAssign::AExt; |
4833 | 0 | } |
4834 | |
|
4835 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { |
4836 | 0 | if (LocVT == MVT::i64) { |
4837 | 0 | static const MCPhysReg RegList5[] = { |
4838 | 0 | X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15 |
4839 | 0 | }; |
4840 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
4841 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4842 | 0 | return false; |
4843 | 0 | } |
4844 | 0 | } |
4845 | 0 | } |
4846 | | |
4847 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { |
4848 | 0 | if (LocVT == MVT::i64) { |
4849 | 0 | if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
4850 | 0 | return false; |
4851 | 0 | } |
4852 | 0 | } |
4853 | | |
4854 | 0 | if (LocVT == MVT::f80) { |
4855 | 0 | static const MCPhysReg RegList6[] = { |
4856 | 0 | X86::FP0, X86::FP1 |
4857 | 0 | }; |
4858 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
4859 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4860 | 0 | return false; |
4861 | 0 | } |
4862 | 0 | } |
4863 | | |
4864 | 0 | if (LocVT == MVT::f32 || |
4865 | 0 | LocVT == MVT::f64 || |
4866 | 0 | LocVT == MVT::f128) { |
4867 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
4868 | 0 | static const MCPhysReg RegList7[] = { |
4869 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
4870 | 0 | }; |
4871 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
4872 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4873 | 0 | return false; |
4874 | 0 | } |
4875 | 0 | } |
4876 | 0 | } |
4877 | | |
4878 | 0 | if (LocVT == MVT::v16i8 || |
4879 | 0 | LocVT == MVT::v8i16 || |
4880 | 0 | LocVT == MVT::v4i32 || |
4881 | 0 | LocVT == MVT::v2i64 || |
4882 | 0 | LocVT == MVT::v4f32 || |
4883 | 0 | LocVT == MVT::v2f64) { |
4884 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { |
4885 | 0 | static const MCPhysReg RegList8[] = { |
4886 | 0 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 |
4887 | 0 | }; |
4888 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
4889 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4890 | 0 | return false; |
4891 | 0 | } |
4892 | 0 | } |
4893 | 0 | } |
4894 | | |
4895 | 0 | if (LocVT == MVT::v32i8 || |
4896 | 0 | LocVT == MVT::v16i16 || |
4897 | 0 | LocVT == MVT::v8i32 || |
4898 | 0 | LocVT == MVT::v4i64 || |
4899 | 0 | LocVT == MVT::v8f32 || |
4900 | 0 | LocVT == MVT::v4f64) { |
4901 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { |
4902 | 0 | static const MCPhysReg RegList9[] = { |
4903 | 0 | X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 |
4904 | 0 | }; |
4905 | 0 | if (unsigned Reg = State.AllocateReg(RegList9)) { |
4906 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4907 | 0 | return false; |
4908 | 0 | } |
4909 | 0 | } |
4910 | 0 | } |
4911 | | |
4912 | 0 | if (LocVT == MVT::v64i8 || |
4913 | 0 | LocVT == MVT::v32i16 || |
4914 | 0 | LocVT == MVT::v16i32 || |
4915 | 0 | LocVT == MVT::v8i64 || |
4916 | 0 | LocVT == MVT::v16f32 || |
4917 | 0 | LocVT == MVT::v8f64) { |
4918 | 0 | if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { |
4919 | 0 | static const MCPhysReg RegList10[] = { |
4920 | 0 | X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 |
4921 | 0 | }; |
4922 | 0 | if (unsigned Reg = State.AllocateReg(RegList10)) { |
4923 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
4924 | 0 | return false; |
4925 | 0 | } |
4926 | 0 | } |
4927 | 0 | } |
4928 | | |
4929 | 0 | return true; // CC didn't match. |
4930 | 0 | } |
4931 | | |
4932 | | #else |
4933 | | |
4934 | | const MCRegister CC_Intel_OCL_BI_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::K1, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 }; |
4935 | | const MCRegister CC_X86_ArgRegs[] = { 0 }; |
4936 | | const MCRegister CC_X86_32_ArgRegs[] = { 0 }; |
4937 | | const MCRegister CC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX }; |
4938 | | const MCRegister CC_X86_32_Common_ArgRegs[] = { X86::MM0, X86::MM1, X86::MM2, X86::XMM0, X86::XMM1, X86::XMM2 }; |
4939 | | const MCRegister CC_X86_32_FastCC_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 }; |
4940 | | const MCRegister CC_X86_32_FastCall_ArgRegs[] = { X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX }; |
4941 | | const MCRegister CC_X86_32_GHC_ArgRegs[] = { X86::EBP, X86::EBX, X86::EDI, X86::ESI }; |
4942 | | const MCRegister CC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::ECX, X86::EDX, X86::ESI }; |
4943 | | const MCRegister CC_X86_32_MCU_ArgRegs[] = { 0 }; |
4944 | | const MCRegister CC_X86_32_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 }; |
4945 | | const MCRegister CC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 }; |
4946 | | const MCRegister CC_X86_32_ThisCall_ArgRegs[] = { 0 }; |
4947 | | const MCRegister CC_X86_32_ThisCall_Common_ArgRegs[] = { X86::ECX }; |
4948 | | const MCRegister CC_X86_32_ThisCall_Mingw_ArgRegs[] = { 0 }; |
4949 | | const MCRegister CC_X86_32_ThisCall_Win_ArgRegs[] = { 0 }; |
4950 | | const MCRegister CC_X86_32_Vector_Common_ArgRegs[] = { 0 }; |
4951 | | const MCRegister CC_X86_32_Vector_Darwin_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 }; |
4952 | | const MCRegister CC_X86_32_Vector_Standard_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::YMM0, X86::YMM1, X86::YMM2, X86::ZMM0, X86::ZMM1, X86::ZMM2 }; |
4953 | | const MCRegister CC_X86_64_ArgRegs[] = { 0 }; |
4954 | | const MCRegister CC_X86_64_AnyReg_ArgRegs[] = { 0 }; |
4955 | | const MCRegister CC_X86_64_C_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R10, X86::R10D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 }; |
4956 | | const MCRegister CC_X86_64_GHC_ArgRegs[] = { X86::R12, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RBP, X86::RBX, X86::RDI, X86::RSI, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 }; |
4957 | | const MCRegister CC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::R8, X86::RBP, X86::RCX, X86::RDX, X86::RSI }; |
4958 | | const MCRegister CC_X86_SysV64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 }; |
4959 | | const MCRegister CC_X86_Win32_CFGuard_Check_ArgRegs[] = { X86::ECX }; |
4960 | | const MCRegister CC_X86_Win32_Vector_ArgRegs[] = { 0 }; |
4961 | | const MCRegister CC_X86_Win32_VectorCall_ArgRegs[] = { 0 }; |
4962 | | const MCRegister CC_X86_Win64_C_ArgRegs[] = { X86::R10, X86::RAX }; |
4963 | | const MCRegister CC_X86_Win64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R10, X86::R10D, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 }; |
4964 | | const MCRegister CC_X86_Win64_RegCallv4_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 }; |
4965 | | const MCRegister CC_X86_Win64_VectorCall_ArgRegs[] = { 0 }; |
4966 | | const MCRegister RetCC_Intel_OCL_BI_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 }; |
4967 | | const MCRegister RetCC_X86_ArgRegs[] = { 0 }; |
4968 | | const MCRegister RetCC_X86Common_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::MM0, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 }; |
4969 | | const MCRegister RetCC_X86_32_ArgRegs[] = { 0 }; |
4970 | | const MCRegister RetCC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::XMM0, X86::XMM1, X86::XMM2 }; |
4971 | | const MCRegister RetCC_X86_32_Fast_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 }; |
4972 | | const MCRegister RetCC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::EDX, X86::ESI }; |
4973 | | const MCRegister RetCC_X86_32_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 }; |
4974 | | const MCRegister RetCC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 }; |
4975 | | const MCRegister RetCC_X86_32_VectorCall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 }; |
4976 | | const MCRegister RetCC_X86_64_ArgRegs[] = { 0 }; |
4977 | | const MCRegister RetCC_X86_64_AnyReg_ArgRegs[] = { 0 }; |
4978 | | const MCRegister RetCC_X86_64_C_ArgRegs[] = { X86::XMM0, X86::XMM1 }; |
4979 | | const MCRegister RetCC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::RAX, X86::RBP, X86::RDX }; |
4980 | | const MCRegister RetCC_X86_64_Swift_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 }; |
4981 | | const MCRegister RetCC_X86_64_Vectorcall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 }; |
4982 | | const MCRegister RetCC_X86_SysV64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R13, X86::R13B, X86::R13D, X86::R13W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 }; |
4983 | | const MCRegister RetCC_X86_Win64_C_ArgRegs[] = { 0 }; |
4984 | | const MCRegister RetCC_X86_Win64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R10, X86::R10B, X86::R10D, X86::R10W, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 }; |
4985 | | const MCRegister RetCC_X86_Win64_RegCallv4_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 }; |
4986 | | |
4987 | | // Registers used by Swift. |
4988 | | const MCRegister CC_X86_64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 }; |
4989 | | const MCRegister CC_X86_Win64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 }; |
4990 | | const MCRegister RetCC_X86_64_C_Swift_ArgRegs[] = { X86::R12 }; |
4991 | | const MCRegister RetCC_X86_64_Swift_Swift_ArgRegs[] = { X86::R12 }; |
4992 | | |
4993 | | #endif // CC_REGISTER_LIST |