Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/X86/X86GenMnemonicTables.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* X86 Mnemonic tables                                                        *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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namespace llvm {
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namespace X86 {
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#ifdef GET_X86_MNEMONIC_TABLES_H
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#undef GET_X86_MNEMONIC_TABLES_H
14
15
bool isFSUBRP(unsigned Opcode);
16
bool isVPDPBUSDS(unsigned Opcode);
17
bool isPUNPCKLWD(unsigned Opcode);
18
bool isPUNPCKLQDQ(unsigned Opcode);
19
bool isRDFSBASE(unsigned Opcode);
20
bool isVPCMOV(unsigned Opcode);
21
bool isVDIVSD(unsigned Opcode);
22
bool isVPEXTRW(unsigned Opcode);
23
bool isLODSD(unsigned Opcode);
24
bool isVPTESTNMQ(unsigned Opcode);
25
bool isCVTSS2SD(unsigned Opcode);
26
bool isVGETMANTPD(unsigned Opcode);
27
bool isVMOVDQA64(unsigned Opcode);
28
bool isINVLPG(unsigned Opcode);
29
bool isVBROADCASTF64X4(unsigned Opcode);
30
bool isVPERMI2Q(unsigned Opcode);
31
bool isVPMOVSXBD(unsigned Opcode);
32
bool isVFMSUB132SS(unsigned Opcode);
33
bool isVPMOVUSDW(unsigned Opcode);
34
bool isAAD(unsigned Opcode);
35
bool isIDIV(unsigned Opcode);
36
bool isCVTTPS2DQ(unsigned Opcode);
37
bool isVBROADCASTF32X8(unsigned Opcode);
38
bool isVFMSUBSS(unsigned Opcode);
39
bool isEMMS(unsigned Opcode);
40
bool isVPDPBSUD(unsigned Opcode);
41
bool isPMOVSXWQ(unsigned Opcode);
42
bool isPSRLW(unsigned Opcode);
43
bool isMOVNTDQA(unsigned Opcode);
44
bool isFUCOMPI(unsigned Opcode);
45
bool isANDNPS(unsigned Opcode);
46
bool isVINSERTF64X2(unsigned Opcode);
47
bool isCLTS(unsigned Opcode);
48
bool isSETSSBSY(unsigned Opcode);
49
bool isVMULPD(unsigned Opcode);
50
bool isVFMADDSUB132PS(unsigned Opcode);
51
bool isVPMADCSWD(unsigned Opcode);
52
bool isVSCATTERPF0DPS(unsigned Opcode);
53
bool isXCHG(unsigned Opcode);
54
bool isVGATHERPF1QPS(unsigned Opcode);
55
bool isVCVTNEPS2BF16(unsigned Opcode);
56
bool isVFMADDSS(unsigned Opcode);
57
bool isINTO(unsigned Opcode);
58
bool isANDPD(unsigned Opcode);
59
bool isSEAMCALL(unsigned Opcode);
60
bool isVPDPBSSDS(unsigned Opcode);
61
bool isUNPCKHPS(unsigned Opcode);
62
bool isSHLD(unsigned Opcode);
63
bool isSHUFPD(unsigned Opcode);
64
bool isFCMOVNB(unsigned Opcode);
65
bool isCVTTSS2SI(unsigned Opcode);
66
bool isEXTRQ(unsigned Opcode);
67
bool isVBROADCASTSS(unsigned Opcode);
68
bool isCLUI(unsigned Opcode);
69
bool isVINSERTI128(unsigned Opcode);
70
bool isVBLENDPD(unsigned Opcode);
71
bool isVPSHLDW(unsigned Opcode);
72
bool isVCVTNEEPH2PS(unsigned Opcode);
73
bool isVCVTTSD2SI(unsigned Opcode);
74
bool isVSM4KEY4(unsigned Opcode);
75
bool isWRMSRNS(unsigned Opcode);
76
bool isCMPSB(unsigned Opcode);
77
bool isMULSS(unsigned Opcode);
78
bool isVMRUN(unsigned Opcode);
79
bool isVPSRLVD(unsigned Opcode);
80
bool isLEAVE(unsigned Opcode);
81
bool isVGETMANTPS(unsigned Opcode);
82
bool isXSHA256(unsigned Opcode);
83
bool isBOUND(unsigned Opcode);
84
bool isSFENCE(unsigned Opcode);
85
bool isVPHADDD(unsigned Opcode);
86
bool isADOX(unsigned Opcode);
87
bool isVPSLLQ(unsigned Opcode);
88
bool isPFRSQIT1(unsigned Opcode);
89
bool isCLAC(unsigned Opcode);
90
bool isKNOTW(unsigned Opcode);
91
bool isVCVTPH2PD(unsigned Opcode);
92
bool isVAESENC(unsigned Opcode);
93
bool isMOVNTI(unsigned Opcode);
94
bool isFXCH(unsigned Opcode);
95
bool isPOPP(unsigned Opcode);
96
bool isVPBLENDMD(unsigned Opcode);
97
bool isFSINCOS(unsigned Opcode);
98
bool isVPMULLW(unsigned Opcode);
99
bool isVPMOVSXBW(unsigned Opcode);
100
bool isSTC(unsigned Opcode);
101
bool isVPINSRB(unsigned Opcode);
102
bool isLWPVAL(unsigned Opcode);
103
bool isKXORB(unsigned Opcode);
104
bool isRSTORSSP(unsigned Opcode);
105
bool isVPRORQ(unsigned Opcode);
106
bool isVSM3MSG1(unsigned Opcode);
107
bool isFICOM(unsigned Opcode);
108
bool isMAXPS(unsigned Opcode);
109
bool isFNCLEX(unsigned Opcode);
110
bool isVMOVMSKPS(unsigned Opcode);
111
bool isVPMOVDB(unsigned Opcode);
112
bool isLLWPCB(unsigned Opcode);
113
bool isVMULSS(unsigned Opcode);
114
bool isAESENCLAST(unsigned Opcode);
115
bool isVPMAXUB(unsigned Opcode);
116
bool isAAS(unsigned Opcode);
117
bool isFADD(unsigned Opcode);
118
bool isJMP(unsigned Opcode);
119
bool isXCRYPTECB(unsigned Opcode);
120
bool isPFRCPIT1(unsigned Opcode);
121
bool isPMULHRW(unsigned Opcode);
122
bool isVCVTPH2PS(unsigned Opcode);
123
bool isVPBLENDVB(unsigned Opcode);
124
bool isPCMPESTRI(unsigned Opcode);
125
bool isSENDUIPI(unsigned Opcode);
126
bool isFLDLN2(unsigned Opcode);
127
bool isVPMACSWD(unsigned Opcode);
128
bool isSHA1MSG1(unsigned Opcode);
129
bool isVADDPS(unsigned Opcode);
130
bool isVCVTPS2DQ(unsigned Opcode);
131
bool isPFPNACC(unsigned Opcode);
132
bool isFMUL(unsigned Opcode);
133
bool isFNSAVE(unsigned Opcode);
134
bool isCDQE(unsigned Opcode);
135
bool isVPMACSDD(unsigned Opcode);
136
bool isVSQRTPS(unsigned Opcode);
137
bool isCMPSQ(unsigned Opcode);
138
bool isVPSCATTERDD(unsigned Opcode);
139
bool isVRNDSCALESD(unsigned Opcode);
140
bool isSUBPS(unsigned Opcode);
141
bool isVMAXSH(unsigned Opcode);
142
bool isFLDZ(unsigned Opcode);
143
bool isVFNMADD132SS(unsigned Opcode);
144
bool isLGDTW(unsigned Opcode);
145
bool isINC(unsigned Opcode);
146
bool isVPANDN(unsigned Opcode);
147
bool isPABSB(unsigned Opcode);
148
bool isVSHA512RNDS2(unsigned Opcode);
149
bool isPHADDSW(unsigned Opcode);
150
bool isVPMOVSQW(unsigned Opcode);
151
bool isVPMAXUD(unsigned Opcode);
152
bool isADDSUBPS(unsigned Opcode);
153
bool isVPMACSSDQL(unsigned Opcode);
154
bool isPXOR(unsigned Opcode);
155
bool isVPSRAD(unsigned Opcode);
156
bool isVPSHAB(unsigned Opcode);
157
bool isBTR(unsigned Opcode);
158
bool isKORW(unsigned Opcode);
159
bool isVRANGESS(unsigned Opcode);
160
bool isVCMPPS(unsigned Opcode);
161
bool isVPLZCNTD(unsigned Opcode);
162
bool isTDPBUUD(unsigned Opcode);
163
bool isROUNDPS(unsigned Opcode);
164
bool isFABS(unsigned Opcode);
165
bool isSUBPD(unsigned Opcode);
166
bool isGF2P8MULB(unsigned Opcode);
167
bool isTZMSK(unsigned Opcode);
168
bool isANDPS(unsigned Opcode);
169
bool isVEXTRACTF32X8(unsigned Opcode);
170
bool isSEAMRET(unsigned Opcode);
171
bool isVPCOMW(unsigned Opcode);
172
bool isVFIXUPIMMPD(unsigned Opcode);
173
bool isKANDND(unsigned Opcode);
174
bool isVMRESUME(unsigned Opcode);
175
bool isCVTPD2DQ(unsigned Opcode);
176
bool isVFNMADD213PS(unsigned Opcode);
177
bool isVPEXTRD(unsigned Opcode);
178
bool isPACKUSWB(unsigned Opcode);
179
bool isVEXTRACTI32X8(unsigned Opcode);
180
bool isVHADDPD(unsigned Opcode);
181
bool isVPSADBW(unsigned Opcode);
182
bool isMOVDQ2Q(unsigned Opcode);
183
bool isPUNPCKHBW(unsigned Opcode);
184
bool isXOR(unsigned Opcode);
185
bool isPSIGNB(unsigned Opcode);
186
bool isVPHADDSW(unsigned Opcode);
187
bool isFADDP(unsigned Opcode);
188
bool isNEG(unsigned Opcode);
189
bool isFLDLG2(unsigned Opcode);
190
bool isFNOP(unsigned Opcode);
191
bool isVMINSS(unsigned Opcode);
192
bool isPCMPISTRM(unsigned Opcode);
193
bool isVFMADD132SS(unsigned Opcode);
194
bool isFDIVRP(unsigned Opcode);
195
bool isPUSHAL(unsigned Opcode);
196
bool isVPMACSDQL(unsigned Opcode);
197
bool isSUBSD(unsigned Opcode);
198
bool isVPBLENDMQ(unsigned Opcode);
199
bool isVGATHERDPS(unsigned Opcode);
200
bool isSYSRET(unsigned Opcode);
201
bool isVPADDB(unsigned Opcode);
202
bool isXEND(unsigned Opcode);
203
bool isWRSSD(unsigned Opcode);
204
bool isVCVTDQ2PH(unsigned Opcode);
205
bool isCVTPD2PS(unsigned Opcode);
206
bool isMAXPD(unsigned Opcode);
207
bool isRCPSS(unsigned Opcode);
208
bool isVMOVAPD(unsigned Opcode);
209
bool isVPSUBSB(unsigned Opcode);
210
bool isRDTSC(unsigned Opcode);
211
bool isVPMADCSSWD(unsigned Opcode);
212
bool isVFNMADD213PH(unsigned Opcode);
213
bool isVGF2P8AFFINEQB(unsigned Opcode);
214
bool isPMOVZXWD(unsigned Opcode);
215
bool isPMINUD(unsigned Opcode);
216
bool isVCVTPH2UW(unsigned Opcode);
217
bool isPADDSW(unsigned Opcode);
218
bool isXSUSLDTRK(unsigned Opcode);
219
bool isLFENCE(unsigned Opcode);
220
bool isCRC32(unsigned Opcode);
221
bool isAESENCWIDE256KL(unsigned Opcode);
222
bool isMOVAPD(unsigned Opcode);
223
bool isVFMADD213PS(unsigned Opcode);
224
bool isVPDPWUUDS(unsigned Opcode);
225
bool isMOVSLDUP(unsigned Opcode);
226
bool isCLDEMOTE(unsigned Opcode);
227
bool isVFNMADD231PS(unsigned Opcode);
228
bool isVMOVMSKPD(unsigned Opcode);
229
bool isPREFETCHT0(unsigned Opcode);
230
bool isVCVTNEOBF162PS(unsigned Opcode);
231
bool isVPCMPUD(unsigned Opcode);
232
bool isVMAXSD(unsigned Opcode);
233
bool isVRCP28SD(unsigned Opcode);
234
bool isVMAXPS(unsigned Opcode);
235
bool isVPMOVD2M(unsigned Opcode);
236
bool isVPMACSSWD(unsigned Opcode);
237
bool isVUCOMISD(unsigned Opcode);
238
bool isLTR(unsigned Opcode);
239
bool isVCVTUSI2SH(unsigned Opcode);
240
bool isVSCATTERPF1QPS(unsigned Opcode);
241
bool isWRGSBASE(unsigned Opcode);
242
bool isSTOSQ(unsigned Opcode);
243
bool isVSQRTSD(unsigned Opcode);
244
bool isVPERMIL2PD(unsigned Opcode);
245
bool isVFCMADDCSH(unsigned Opcode);
246
bool isVFMADDSUB213PS(unsigned Opcode);
247
bool isPFSUB(unsigned Opcode);
248
bool isVSQRTSS(unsigned Opcode);
249
bool isVEXPANDPS(unsigned Opcode);
250
bool isVPCOMPRESSW(unsigned Opcode);
251
bool isPEXTRD(unsigned Opcode);
252
bool isSYSEXITQ(unsigned Opcode);
253
bool isROUNDSD(unsigned Opcode);
254
bool isFCOM(unsigned Opcode);
255
bool isVFNMSUBSS(unsigned Opcode);
256
bool isKSHIFTLW(unsigned Opcode);
257
bool isSCASD(unsigned Opcode);
258
bool isVMPTRLD(unsigned Opcode);
259
bool isVAESDECLAST(unsigned Opcode);
260
bool isVFMADDSUBPS(unsigned Opcode);
261
bool isVCVTUQQ2PS(unsigned Opcode);
262
bool isVPMOVUSDB(unsigned Opcode);
263
bool isVPROTW(unsigned Opcode);
264
bool isVDPPS(unsigned Opcode);
265
bool isVRSQRT14PD(unsigned Opcode);
266
bool isVTESTPD(unsigned Opcode);
267
bool isVFNMADD231SH(unsigned Opcode);
268
bool isENDBR64(unsigned Opcode);
269
bool isMULSD(unsigned Opcode);
270
bool isXRSTORS(unsigned Opcode);
271
bool isPREFETCHNTA(unsigned Opcode);
272
bool isVPCOMD(unsigned Opcode);
273
bool isVPCOMUB(unsigned Opcode);
274
bool isVPHSUBD(unsigned Opcode);
275
bool isVBROADCASTI64X2(unsigned Opcode);
276
bool isFPATAN(unsigned Opcode);
277
bool isLOOPE(unsigned Opcode);
278
bool isPCMPEQW(unsigned Opcode);
279
bool isVFMADDCSH(unsigned Opcode);
280
bool isVPDPBSSD(unsigned Opcode);
281
bool isVFMSUBADD132PH(unsigned Opcode);
282
bool isVPADDSB(unsigned Opcode);
283
bool isKADDW(unsigned Opcode);
284
bool isPTEST(unsigned Opcode);
285
bool isVRSQRT28PS(unsigned Opcode);
286
bool isVGF2P8AFFINEINVQB(unsigned Opcode);
287
bool isSERIALIZE(unsigned Opcode);
288
bool isVPHADDWQ(unsigned Opcode);
289
bool isVRNDSCALESH(unsigned Opcode);
290
bool isAAA(unsigned Opcode);
291
bool isWRMSRLIST(unsigned Opcode);
292
bool isXORPS(unsigned Opcode);
293
bool isVCVTPH2PSX(unsigned Opcode);
294
bool isVFMSUB231PH(unsigned Opcode);
295
bool isVGATHERQPD(unsigned Opcode);
296
bool isKADDB(unsigned Opcode);
297
bool isCVTPD2PI(unsigned Opcode);
298
bool isVFNMSUB213PH(unsigned Opcode);
299
bool isVPCMPESTRI(unsigned Opcode);
300
bool isVPSHRDW(unsigned Opcode);
301
bool isPOP2(unsigned Opcode);
302
bool isRDMSRLIST(unsigned Opcode);
303
bool isVPDPBUSD(unsigned Opcode);
304
bool isVCMPPH(unsigned Opcode);
305
bool isVANDNPD(unsigned Opcode);
306
bool isSUB(unsigned Opcode);
307
bool isVRSQRT28PD(unsigned Opcode);
308
bool isVFNMADD132PH(unsigned Opcode);
309
bool isVPMACSSWW(unsigned Opcode);
310
bool isXSTORE(unsigned Opcode);
311
bool isVPROTQ(unsigned Opcode);
312
bool isVPHADDBD(unsigned Opcode);
313
bool isVPMAXSB(unsigned Opcode);
314
bool isVMOVDQU8(unsigned Opcode);
315
bool isVPMOVSXWD(unsigned Opcode);
316
bool isSHA256RNDS2(unsigned Opcode);
317
bool isKANDB(unsigned Opcode);
318
bool isTPAUSE(unsigned Opcode);
319
bool isPUSH(unsigned Opcode);
320
bool isVRNDSCALESS(unsigned Opcode);
321
bool isVPCMPISTRI(unsigned Opcode);
322
bool isSTGI(unsigned Opcode);
323
bool isSBB(unsigned Opcode);
324
bool isBLCS(unsigned Opcode);
325
bool isVCVTSD2SH(unsigned Opcode);
326
bool isVPERMW(unsigned Opcode);
327
bool isXRESLDTRK(unsigned Opcode);
328
bool isAESENC256KL(unsigned Opcode);
329
bool isVGATHERDPD(unsigned Opcode);
330
bool isHRESET(unsigned Opcode);
331
bool isVFMSUBADD231PD(unsigned Opcode);
332
bool isVFRCZSS(unsigned Opcode);
333
bool isMINPS(unsigned Opcode);
334
bool isFPREM1(unsigned Opcode);
335
bool isVPCMPUB(unsigned Opcode);
336
bool isVSQRTPD(unsigned Opcode);
337
bool isVFRCZPS(unsigned Opcode);
338
bool isVFNMADD213SS(unsigned Opcode);
339
bool isVPMOVDW(unsigned Opcode);
340
bool isVPSHRDVQ(unsigned Opcode);
341
bool isVBROADCASTSD(unsigned Opcode);
342
bool isVSHUFPD(unsigned Opcode);
343
bool isVPSUBSW(unsigned Opcode);
344
bool isKUNPCKBW(unsigned Opcode);
345
bool isVPBLENDD(unsigned Opcode);
346
bool isUNPCKHPD(unsigned Opcode);
347
bool isVFNMADD231SD(unsigned Opcode);
348
bool isVPBROADCASTMW2D(unsigned Opcode);
349
bool isVPMULTISHIFTQB(unsigned Opcode);
350
bool isVP2INTERSECTQ(unsigned Opcode);
351
bool isVPUNPCKHWD(unsigned Opcode);
352
bool isVPERM2F128(unsigned Opcode);
353
bool isINSD(unsigned Opcode);
354
bool isLFS(unsigned Opcode);
355
bool isFMULP(unsigned Opcode);
356
bool isCWD(unsigned Opcode);
357
bool isVDIVSS(unsigned Opcode);
358
bool isVPSRLQ(unsigned Opcode);
359
bool isFSQRT(unsigned Opcode);
360
bool isJRCXZ(unsigned Opcode);
361
bool isVPMOVMSKB(unsigned Opcode);
362
bool isAESDEC256KL(unsigned Opcode);
363
bool isFLDENV(unsigned Opcode);
364
bool isVPHSUBWD(unsigned Opcode);
365
bool isWBNOINVD(unsigned Opcode);
366
bool isVEXPANDPD(unsigned Opcode);
367
bool isFYL2XP1(unsigned Opcode);
368
bool isPREFETCHT2(unsigned Opcode);
369
bool isVPDPBSUDS(unsigned Opcode);
370
bool isVSHA512MSG2(unsigned Opcode);
371
bool isPMULHUW(unsigned Opcode);
372
bool isKANDNB(unsigned Opcode);
373
bool isVCVTUW2PH(unsigned Opcode);
374
bool isAESDECWIDE256KL(unsigned Opcode);
375
bool isVPGATHERDD(unsigned Opcode);
376
bool isVREDUCESH(unsigned Opcode);
377
bool isPOPFQ(unsigned Opcode);
378
bool isPAVGUSB(unsigned Opcode);
379
bool isVALIGND(unsigned Opcode);
380
bool isVPHMINPOSUW(unsigned Opcode);
381
bool isLIDTD(unsigned Opcode);
382
bool isVPERMT2PD(unsigned Opcode);
383
bool isVMLAUNCH(unsigned Opcode);
384
bool isVPXORQ(unsigned Opcode);
385
bool isMOVNTDQ(unsigned Opcode);
386
bool isPOP2P(unsigned Opcode);
387
bool isVADDPD(unsigned Opcode);
388
bool isSMSW(unsigned Opcode);
389
bool isVEXP2PD(unsigned Opcode);
390
bool isPMULUDQ(unsigned Opcode);
391
bool isIRET(unsigned Opcode);
392
bool isMULPS(unsigned Opcode);
393
bool isVFNMSUBPD(unsigned Opcode);
394
bool isPHADDW(unsigned Opcode);
395
bool isRDSEED(unsigned Opcode);
396
bool isVPSHLW(unsigned Opcode);
397
bool isRMPUPDATE(unsigned Opcode);
398
bool isVFMADD231PH(unsigned Opcode);
399
bool isVPSHAD(unsigned Opcode);
400
bool isCLWB(unsigned Opcode);
401
bool isPSUBUSB(unsigned Opcode);
402
bool isVCVTTSD2USI(unsigned Opcode);
403
bool isVEXTRACTPS(unsigned Opcode);
404
bool isMOVLPD(unsigned Opcode);
405
bool isLGDTD(unsigned Opcode);
406
bool isVPBROADCASTMB2Q(unsigned Opcode);
407
bool isOUT(unsigned Opcode);
408
bool isVMSAVE(unsigned Opcode);
409
bool isVCVTQQ2PD(unsigned Opcode);
410
bool isVFMADD213PH(unsigned Opcode);
411
bool isFCMOVBE(unsigned Opcode);
412
bool isMOVSHDUP(unsigned Opcode);
413
bool isVPMOVUSQB(unsigned Opcode);
414
bool isFIST(unsigned Opcode);
415
bool isHADDPD(unsigned Opcode);
416
bool isPACKSSWB(unsigned Opcode);
417
bool isVPMACSSDQH(unsigned Opcode);
418
bool isVFNMSUB132SD(unsigned Opcode);
419
bool isVPMASKMOVQ(unsigned Opcode);
420
bool isVCOMPRESSPD(unsigned Opcode);
421
bool isVFMADD213SS(unsigned Opcode);
422
bool isVPCMPQ(unsigned Opcode);
423
bool isVADDSH(unsigned Opcode);
424
bool isVFNMADDSD(unsigned Opcode);
425
bool isUMWAIT(unsigned Opcode);
426
bool isVPUNPCKHDQ(unsigned Opcode);
427
bool isLCALL(unsigned Opcode);
428
bool isAESDEC128KL(unsigned Opcode);
429
bool isVSUBPS(unsigned Opcode);
430
bool isFSTP(unsigned Opcode);
431
bool isVCVTUDQ2PD(unsigned Opcode);
432
bool isVPMOVSWB(unsigned Opcode);
433
bool isVPANDNQ(unsigned Opcode);
434
bool isSYSENTER(unsigned Opcode);
435
bool isVPHADDWD(unsigned Opcode);
436
bool isVMOVHPD(unsigned Opcode);
437
bool isMOVHPD(unsigned Opcode);
438
bool isVDIVPH(unsigned Opcode);
439
bool isFFREE(unsigned Opcode);
440
bool isVGATHERPF1DPS(unsigned Opcode);
441
bool isVFNMADD231PD(unsigned Opcode);
442
bool isVFCMULCPH(unsigned Opcode);
443
bool isVPADDD(unsigned Opcode);
444
bool isVSM3MSG2(unsigned Opcode);
445
bool isVPCOMUQ(unsigned Opcode);
446
bool isVERR(unsigned Opcode);
447
bool isKORTESTQ(unsigned Opcode);
448
bool isVFMSUB132SD(unsigned Opcode);
449
bool isTILEZERO(unsigned Opcode);
450
bool isPFADD(unsigned Opcode);
451
bool isVCVTSI2SD(unsigned Opcode);
452
bool isVSTMXCSR(unsigned Opcode);
453
bool isVCVTTSH2SI(unsigned Opcode);
454
bool isRET(unsigned Opcode);
455
bool isLZCNT(unsigned Opcode);
456
bool isMULPD(unsigned Opcode);
457
bool isVBROADCASTI32X2(unsigned Opcode);
458
bool isVCVTPH2W(unsigned Opcode);
459
bool isCQO(unsigned Opcode);
460
bool isFSUBR(unsigned Opcode);
461
bool isDPPD(unsigned Opcode);
462
bool isFCOS(unsigned Opcode);
463
bool isXSAVES(unsigned Opcode);
464
bool isTZCNT(unsigned Opcode);
465
bool isLJMP(unsigned Opcode);
466
bool isCMOVCC(unsigned Opcode);
467
bool isVCVTSS2SD(unsigned Opcode);
468
bool isINVEPT(unsigned Opcode);
469
bool isADDSUBPD(unsigned Opcode);
470
bool isVMOVSHDUP(unsigned Opcode);
471
bool isKSHIFTRD(unsigned Opcode);
472
bool isVPTERNLOGD(unsigned Opcode);
473
bool isPADDQ(unsigned Opcode);
474
bool isVEXTRACTI64X4(unsigned Opcode);
475
bool isVFMSUB231SS(unsigned Opcode);
476
bool isVPCMPEQB(unsigned Opcode);
477
bool isLEA(unsigned Opcode);
478
bool isPSUBB(unsigned Opcode);
479
bool isKADDQ(unsigned Opcode);
480
bool isMOVSX(unsigned Opcode);
481
bool isVALIGNQ(unsigned Opcode);
482
bool isVCVTNE2PS2BF16(unsigned Opcode);
483
bool isVPSRAW(unsigned Opcode);
484
bool isVFMSUBADD231PH(unsigned Opcode);
485
bool isCVTDQ2PS(unsigned Opcode);
486
bool isFBLD(unsigned Opcode);
487
bool isLMSW(unsigned Opcode);
488
bool isWRMSR(unsigned Opcode);
489
bool isMINSS(unsigned Opcode);
490
bool isFSCALE(unsigned Opcode);
491
bool isVFNMADD213SH(unsigned Opcode);
492
bool isVPHADDUBD(unsigned Opcode);
493
bool isRDSSPQ(unsigned Opcode);
494
bool isLGDT(unsigned Opcode);
495
bool isVPSHLDVD(unsigned Opcode);
496
bool isPFCMPGT(unsigned Opcode);
497
bool isVRNDSCALEPH(unsigned Opcode);
498
bool isJCXZ(unsigned Opcode);
499
bool isVPMOVZXBW(unsigned Opcode);
500
bool isVFMADDSUB231PD(unsigned Opcode);
501
bool isVBLENDMPD(unsigned Opcode);
502
bool isHSUBPS(unsigned Opcode);
503
bool isPREFETCHIT0(unsigned Opcode);
504
bool isKTESTD(unsigned Opcode);
505
bool isVCVTNEOPH2PS(unsigned Opcode);
506
bool isVBLENDVPD(unsigned Opcode);
507
bool isVCVTSS2USI(unsigned Opcode);
508
bool isVPANDD(unsigned Opcode);
509
bool isPMINSW(unsigned Opcode);
510
bool isSTAC(unsigned Opcode);
511
bool isVFMSUB213PS(unsigned Opcode);
512
bool isPOPAL(unsigned Opcode);
513
bool isVCVTPS2UQQ(unsigned Opcode);
514
bool isRDRAND(unsigned Opcode);
515
bool isJCC(unsigned Opcode);
516
bool isVPMINSQ(unsigned Opcode);
517
bool isVADDSD(unsigned Opcode);
518
bool isDPPS(unsigned Opcode);
519
bool isPINSRQ(unsigned Opcode);
520
bool isVUCOMISS(unsigned Opcode);
521
bool isVPDPWSUD(unsigned Opcode);
522
bool isKANDNW(unsigned Opcode);
523
bool isAOR(unsigned Opcode);
524
bool isPMAXUB(unsigned Opcode);
525
bool isANDNPD(unsigned Opcode);
526
bool isINVPCID(unsigned Opcode);
527
bool isRDGSBASE(unsigned Opcode);
528
bool isVPMOVSQD(unsigned Opcode);
529
bool isBT(unsigned Opcode);
530
bool isVPROLVQ(unsigned Opcode);
531
bool isVFMADDSUB132PD(unsigned Opcode);
532
bool isRORX(unsigned Opcode);
533
bool isPADDUSW(unsigned Opcode);
534
bool isPFNACC(unsigned Opcode);
535
bool isAND(unsigned Opcode);
536
bool isPSLLQ(unsigned Opcode);
537
bool isVFMSUB132PH(unsigned Opcode);
538
bool isXSAVE(unsigned Opcode);
539
bool isKNOTQ(unsigned Opcode);
540
bool isXTEST(unsigned Opcode);
541
bool isVINSERTPS(unsigned Opcode);
542
bool isXSAVEOPT(unsigned Opcode);
543
bool isLDS(unsigned Opcode);
544
bool isVFMADDSUB213PD(unsigned Opcode);
545
bool isVINSERTF32X4(unsigned Opcode);
546
bool isVRSQRTPS(unsigned Opcode);
547
bool isVSUBPH(unsigned Opcode);
548
bool isPMOVSXBW(unsigned Opcode);
549
bool isVPSRLDQ(unsigned Opcode);
550
bool isADC(unsigned Opcode);
551
bool isPHADDD(unsigned Opcode);
552
bool isVMINPH(unsigned Opcode);
553
bool isVMINSD(unsigned Opcode);
554
bool isVROUNDPD(unsigned Opcode);
555
bool isVFCMADDCPH(unsigned Opcode);
556
bool isINCSSPQ(unsigned Opcode);
557
bool isVPUNPCKLDQ(unsigned Opcode);
558
bool isVMINSH(unsigned Opcode);
559
bool isINSERTQ(unsigned Opcode);
560
bool isBLCI(unsigned Opcode);
561
bool isHLT(unsigned Opcode);
562
bool isVPCOMUW(unsigned Opcode);
563
bool isVPMOVSXDQ(unsigned Opcode);
564
bool isVFNMSUB231PS(unsigned Opcode);
565
bool isVFNMSUB213SH(unsigned Opcode);
566
bool isVCVTTPD2UQQ(unsigned Opcode);
567
bool isSQRTSS(unsigned Opcode);
568
bool isIMUL(unsigned Opcode);
569
bool isVCVTSS2SI(unsigned Opcode);
570
bool isPUSHAW(unsigned Opcode);
571
bool isSTOSD(unsigned Opcode);
572
bool isPSRLDQ(unsigned Opcode);
573
bool isVSCATTERQPS(unsigned Opcode);
574
bool isFIDIV(unsigned Opcode);
575
bool isVFMSUB213PD(unsigned Opcode);
576
bool isVFMADDSUB231PH(unsigned Opcode);
577
bool isTDCALL(unsigned Opcode);
578
bool isPVALIDATE(unsigned Opcode);
579
bool isVPSHUFLW(unsigned Opcode);
580
bool isPCLMULQDQ(unsigned Opcode);
581
bool isCMPXCHG8B(unsigned Opcode);
582
bool isVPMOVM2B(unsigned Opcode);
583
bool isVCVTUDQ2PH(unsigned Opcode);
584
bool isPEXTRQ(unsigned Opcode);
585
bool isXCRYPTCTR(unsigned Opcode);
586
bool isVREDUCEPH(unsigned Opcode);
587
bool isUCOMISD(unsigned Opcode);
588
bool isOUTSD(unsigned Opcode);
589
bool isSUBSS(unsigned Opcode);
590
bool isVFMSUBPS(unsigned Opcode);
591
bool isVPBLENDW(unsigned Opcode);
592
bool isBZHI(unsigned Opcode);
593
bool isVPRORVD(unsigned Opcode);
594
bool isRMPQUERY(unsigned Opcode);
595
bool isVPEXPANDB(unsigned Opcode);
596
bool isVPSCATTERDQ(unsigned Opcode);
597
bool isPSMASH(unsigned Opcode);
598
bool isVPSHLDQ(unsigned Opcode);
599
bool isVSCATTERPF1DPD(unsigned Opcode);
600
bool isMONTMUL(unsigned Opcode);
601
bool isVCVTPH2UQQ(unsigned Opcode);
602
bool isPSLLD(unsigned Opcode);
603
bool isSAR(unsigned Opcode);
604
bool isLDTILECFG(unsigned Opcode);
605
bool isPMINUB(unsigned Opcode);
606
bool isVCVTNEEBF162PS(unsigned Opcode);
607
bool isMOVDIR64B(unsigned Opcode);
608
bool isSTR(unsigned Opcode);
609
bool isKANDNQ(unsigned Opcode);
610
bool isBSF(unsigned Opcode);
611
bool isVPDPBUUDS(unsigned Opcode);
612
bool isINCSSPD(unsigned Opcode);
613
bool isSQRTPS(unsigned Opcode);
614
bool isCMPXCHG(unsigned Opcode);
615
bool isVPSIGNW(unsigned Opcode);
616
bool isLES(unsigned Opcode);
617
bool isCVTSS2SI(unsigned Opcode);
618
bool isVPMOVUSWB(unsigned Opcode);
619
bool isFCOMPI(unsigned Opcode);
620
bool isPUNPCKHWD(unsigned Opcode);
621
bool isPFACC(unsigned Opcode);
622
bool isVPTESTNMW(unsigned Opcode);
623
bool isVPMULDQ(unsigned Opcode);
624
bool isSHRX(unsigned Opcode);
625
bool isKXORQ(unsigned Opcode);
626
bool isVGETEXPSD(unsigned Opcode);
627
bool isV4FNMADDPS(unsigned Opcode);
628
bool isVFNMSUB231SD(unsigned Opcode);
629
bool isVPSHLD(unsigned Opcode);
630
bool isPAVGB(unsigned Opcode);
631
bool isPMOVZXBD(unsigned Opcode);
632
bool isKORTESTW(unsigned Opcode);
633
bool isVSHUFPS(unsigned Opcode);
634
bool isAESENCWIDE128KL(unsigned Opcode);
635
bool isVPXORD(unsigned Opcode);
636
bool isVPSHAW(unsigned Opcode);
637
bool isVPERMT2B(unsigned Opcode);
638
bool isVFMADD213PD(unsigned Opcode);
639
bool isVPGATHERQD(unsigned Opcode);
640
bool isVPCMPGTW(unsigned Opcode);
641
bool isVGETMANTSH(unsigned Opcode);
642
bool isVANDPS(unsigned Opcode);
643
bool isVDIVPS(unsigned Opcode);
644
bool isVANDNPS(unsigned Opcode);
645
bool isVPBROADCASTW(unsigned Opcode);
646
bool isFLDL2T(unsigned Opcode);
647
bool isVPERMB(unsigned Opcode);
648
bool isFCMOVNBE(unsigned Opcode);
649
bool isVCVTTPH2W(unsigned Opcode);
650
bool isPMOVZXBQ(unsigned Opcode);
651
bool isPF2ID(unsigned Opcode);
652
bool isVFNMADD132PD(unsigned Opcode);
653
bool isPMULHRSW(unsigned Opcode);
654
bool isKADDD(unsigned Opcode);
655
bool isVFNMSUB132SH(unsigned Opcode);
656
bool isUIRET(unsigned Opcode);
657
bool isBSR(unsigned Opcode);
658
bool isPCMPEQQ(unsigned Opcode);
659
bool isCDQ(unsigned Opcode);
660
bool isPMAXSW(unsigned Opcode);
661
bool isSIDTD(unsigned Opcode);
662
bool isVCVTPS2PHX(unsigned Opcode);
663
bool isVPSLLVQ(unsigned Opcode);
664
bool isMOVQ(unsigned Opcode);
665
bool isPREFETCH(unsigned Opcode);
666
bool isCLRSSBSY(unsigned Opcode);
667
bool isPSHUFW(unsigned Opcode);
668
bool isVPDPWSUDS(unsigned Opcode);
669
bool isVPMOVSXBQ(unsigned Opcode);
670
bool isFICOMP(unsigned Opcode);
671
bool isVLDMXCSR(unsigned Opcode);
672
bool isVPSUBUSW(unsigned Opcode);
673
bool isVFNMSUB132SS(unsigned Opcode);
674
bool isRETF(unsigned Opcode);
675
bool isKMOVQ(unsigned Opcode);
676
bool isVPADDUSW(unsigned Opcode);
677
bool isPACKSSDW(unsigned Opcode);
678
bool isUMONITOR(unsigned Opcode);
679
bool isENQCMDS(unsigned Opcode);
680
bool isVPMAXSQ(unsigned Opcode);
681
bool isVPERMT2Q(unsigned Opcode);
682
bool isFDECSTP(unsigned Opcode);
683
bool isVPTESTMQ(unsigned Opcode);
684
bool isVRCP14PD(unsigned Opcode);
685
bool isARPL(unsigned Opcode);
686
bool isVFMSUB213SD(unsigned Opcode);
687
bool isJMPABS(unsigned Opcode);
688
bool isVUNPCKHPS(unsigned Opcode);
689
bool isVFNMADDSS(unsigned Opcode);
690
bool isSIDT(unsigned Opcode);
691
bool isVPCMPGTB(unsigned Opcode);
692
bool isVPRORD(unsigned Opcode);
693
bool isVSUBSS(unsigned Opcode);
694
bool isPUSHFQ(unsigned Opcode);
695
bool isVPCLMULQDQ(unsigned Opcode);
696
bool isVPADDUSB(unsigned Opcode);
697
bool isVPCMPD(unsigned Opcode);
698
bool isMOVSD(unsigned Opcode);
699
bool isPSUBUSW(unsigned Opcode);
700
bool isVFMSUBADD132PS(unsigned Opcode);
701
bool isMOVMSKPS(unsigned Opcode);
702
bool isVFIXUPIMMSS(unsigned Opcode);
703
bool isMFENCE(unsigned Opcode);
704
bool isFTST(unsigned Opcode);
705
bool isVPMADDWD(unsigned Opcode);
706
bool isPOP(unsigned Opcode);
707
bool isPSUBW(unsigned Opcode);
708
bool isBSWAP(unsigned Opcode);
709
bool isPFMIN(unsigned Opcode);
710
bool isVFPCLASSPD(unsigned Opcode);
711
bool isVPSHRDVD(unsigned Opcode);
712
bool isPADDW(unsigned Opcode);
713
bool isCVTSI2SD(unsigned Opcode);
714
bool isENQCMD(unsigned Opcode);
715
bool isXSHA1(unsigned Opcode);
716
bool isVFNMADD132SD(unsigned Opcode);
717
bool isMOVZX(unsigned Opcode);
718
bool isVFIXUPIMMSD(unsigned Opcode);
719
bool isINVD(unsigned Opcode);
720
bool isVFIXUPIMMPS(unsigned Opcode);
721
bool isMOVDQU(unsigned Opcode);
722
bool isVFPCLASSPS(unsigned Opcode);
723
bool isMOVSQ(unsigned Opcode);
724
bool isAESDECWIDE128KL(unsigned Opcode);
725
bool isROUNDSS(unsigned Opcode);
726
bool isVPERMILPS(unsigned Opcode);
727
bool isVPMOVW2M(unsigned Opcode);
728
bool isVMULSD(unsigned Opcode);
729
bool isVPERMI2W(unsigned Opcode);
730
bool isVPSHUFB(unsigned Opcode);
731
bool isFST(unsigned Opcode);
732
bool isVPHSUBW(unsigned Opcode);
733
bool isVREDUCESS(unsigned Opcode);
734
bool isFRNDINT(unsigned Opcode);
735
bool isSHR(unsigned Opcode);
736
bool isLOOPNE(unsigned Opcode);
737
bool isVCVTTPH2UQQ(unsigned Opcode);
738
bool isSHA1NEXTE(unsigned Opcode);
739
bool isVFMADD132SD(unsigned Opcode);
740
bool isPSRAW(unsigned Opcode);
741
bool isVPBROADCASTQ(unsigned Opcode);
742
bool isCLC(unsigned Opcode);
743
bool isPOPAW(unsigned Opcode);
744
bool isTCMMIMFP16PS(unsigned Opcode);
745
bool isVCVTTPS2UQQ(unsigned Opcode);
746
bool isVCVTQQ2PH(unsigned Opcode);
747
bool isVMOVUPD(unsigned Opcode);
748
bool isFPTAN(unsigned Opcode);
749
bool isVMASKMOVPD(unsigned Opcode);
750
bool isVMOVLHPS(unsigned Opcode);
751
bool isAESKEYGENASSIST(unsigned Opcode);
752
bool isXSAVEOPT64(unsigned Opcode);
753
bool isXSAVEC(unsigned Opcode);
754
bool isVPLZCNTQ(unsigned Opcode);
755
bool isVPSUBW(unsigned Opcode);
756
bool isVFMSUBADD213PH(unsigned Opcode);
757
bool isVFMADDSUBPD(unsigned Opcode);
758
bool isVPMINSW(unsigned Opcode);
759
bool isVFNMSUB132PS(unsigned Opcode);
760
bool isVMOVAPS(unsigned Opcode);
761
bool isVPEXTRQ(unsigned Opcode);
762
bool isVSCALEFSH(unsigned Opcode);
763
bool isVCVTPD2PS(unsigned Opcode);
764
bool isCLGI(unsigned Opcode);
765
bool isVAESDEC(unsigned Opcode);
766
bool isPFMUL(unsigned Opcode);
767
bool isMOVDIRI(unsigned Opcode);
768
bool isSHUFPS(unsigned Opcode);
769
bool isVFNMSUB231SS(unsigned Opcode);
770
bool isVMWRITE(unsigned Opcode);
771
bool isVINSERTF128(unsigned Opcode);
772
bool isFISUBR(unsigned Opcode);
773
bool isVINSERTI32X4(unsigned Opcode);
774
bool isVPSLLDQ(unsigned Opcode);
775
bool isPOPCNT(unsigned Opcode);
776
bool isVXORPD(unsigned Opcode);
777
bool isXLATB(unsigned Opcode);
778
bool isDIV(unsigned Opcode);
779
bool isVPSHLDVQ(unsigned Opcode);
780
bool isMOVDDUP(unsigned Opcode);
781
bool isVMOVDQU64(unsigned Opcode);
782
bool isVPCOMPRESSQ(unsigned Opcode);
783
bool isVFMSUBADD132PD(unsigned Opcode);
784
bool isADDSD(unsigned Opcode);
785
bool isBLENDPD(unsigned Opcode);
786
bool isVPERMILPD(unsigned Opcode);
787
bool isPMADDUBSW(unsigned Opcode);
788
bool isPOPFD(unsigned Opcode);
789
bool isCMPSW(unsigned Opcode);
790
bool isLDMXCSR(unsigned Opcode);
791
bool isVMULPS(unsigned Opcode);
792
bool isVROUNDSD(unsigned Opcode);
793
bool isVFMADD132PD(unsigned Opcode);
794
bool isVPANDQ(unsigned Opcode);
795
bool isVPSRAQ(unsigned Opcode);
796
bool isVCOMISD(unsigned Opcode);
797
bool isFFREEP(unsigned Opcode);
798
bool isVFNMADD213PD(unsigned Opcode);
799
bool isVCMPPD(unsigned Opcode);
800
bool isVFNMSUB132PH(unsigned Opcode);
801
bool isVPHADDBW(unsigned Opcode);
802
bool isVPPERM(unsigned Opcode);
803
bool isVCVTPS2PD(unsigned Opcode);
804
bool isCBW(unsigned Opcode);
805
bool isVMOVUPS(unsigned Opcode);
806
bool isVPMAXUQ(unsigned Opcode);
807
bool isWRSSQ(unsigned Opcode);
808
bool isPACKUSDW(unsigned Opcode);
809
bool isXBEGIN(unsigned Opcode);
810
bool isVCVTPD2UQQ(unsigned Opcode);
811
bool isFCMOVB(unsigned Opcode);
812
bool isNOP(unsigned Opcode);
813
bool isVPABSQ(unsigned Opcode);
814
bool isVTESTPS(unsigned Opcode);
815
bool isPHSUBW(unsigned Opcode);
816
bool isPUSH2P(unsigned Opcode);
817
bool isFISTTP(unsigned Opcode);
818
bool isPCMPESTRM(unsigned Opcode);
819
bool isVPINSRD(unsigned Opcode);
820
bool isVFNMSUB213PS(unsigned Opcode);
821
bool isPHSUBD(unsigned Opcode);
822
bool isSLDT(unsigned Opcode);
823
bool isVPMINSD(unsigned Opcode);
824
bool isVHADDPS(unsigned Opcode);
825
bool isVMOVNTDQ(unsigned Opcode);
826
bool isVFRCZSD(unsigned Opcode);
827
bool isVPTESTMW(unsigned Opcode);
828
bool isVPMOVZXWD(unsigned Opcode);
829
bool isPSADBW(unsigned Opcode);
830
bool isVCVTSD2SI(unsigned Opcode);
831
bool isVMAXPH(unsigned Opcode);
832
bool isLODSB(unsigned Opcode);
833
bool isPHMINPOSUW(unsigned Opcode);
834
bool isVPROLVD(unsigned Opcode);
835
bool isWRFSBASE(unsigned Opcode);
836
bool isVRSQRT14PS(unsigned Opcode);
837
bool isVPHSUBDQ(unsigned Opcode);
838
bool isIRETD(unsigned Opcode);
839
bool isCVTSI2SS(unsigned Opcode);
840
bool isVPMULHRSW(unsigned Opcode);
841
bool isPI2FD(unsigned Opcode);
842
bool isGF2P8AFFINEQB(unsigned Opcode);
843
bool isPAND(unsigned Opcode);
844
bool isVFNMSUB231SH(unsigned Opcode);
845
bool isVMOVHLPS(unsigned Opcode);
846
bool isPEXTRB(unsigned Opcode);
847
bool isKNOTD(unsigned Opcode);
848
bool isVPUNPCKLQDQ(unsigned Opcode);
849
bool isVMMCALL(unsigned Opcode);
850
bool isVCVTSH2SS(unsigned Opcode);
851
bool isVPERMIL2PS(unsigned Opcode);
852
bool isVPCMPGTD(unsigned Opcode);
853
bool isCMPXCHG16B(unsigned Opcode);
854
bool isVZEROUPPER(unsigned Opcode);
855
bool isMOVAPS(unsigned Opcode);
856
bool isVPCMPW(unsigned Opcode);
857
bool isFUCOMPP(unsigned Opcode);
858
bool isXSETBV(unsigned Opcode);
859
bool isSLWPCB(unsigned Opcode);
860
bool isSCASW(unsigned Opcode);
861
bool isFCMOVNE(unsigned Opcode);
862
bool isPBNDKB(unsigned Opcode);
863
bool isVPMULLD(unsigned Opcode);
864
bool isVP4DPWSSDS(unsigned Opcode);
865
bool isPINSRW(unsigned Opcode);
866
bool isVCVTSI2SH(unsigned Opcode);
867
bool isVINSERTF32X8(unsigned Opcode);
868
bool isKSHIFTLB(unsigned Opcode);
869
bool isSEAMOPS(unsigned Opcode);
870
bool isVPMULUDQ(unsigned Opcode);
871
bool isVPMOVSQB(unsigned Opcode);
872
bool isVPTESTMD(unsigned Opcode);
873
bool isVPHADDDQ(unsigned Opcode);
874
bool isKUNPCKDQ(unsigned Opcode);
875
bool isT1MSKC(unsigned Opcode);
876
bool isVPCOMB(unsigned Opcode);
877
bool isVBLENDPS(unsigned Opcode);
878
bool isPTWRITE(unsigned Opcode);
879
bool isCVTPS2PI(unsigned Opcode);
880
bool isVPROTD(unsigned Opcode);
881
bool isCALL(unsigned Opcode);
882
bool isVPERMPS(unsigned Opcode);
883
bool isVPSHUFBITQMB(unsigned Opcode);
884
bool isVMOVSLDUP(unsigned Opcode);
885
bool isINVLPGA(unsigned Opcode);
886
bool isVCVTPH2QQ(unsigned Opcode);
887
bool isADD(unsigned Opcode);
888
bool isPSUBSW(unsigned Opcode);
889
bool isSIDTW(unsigned Opcode);
890
bool isVFNMADD231PH(unsigned Opcode);
891
bool isVEXTRACTF64X2(unsigned Opcode);
892
bool isFCOMI(unsigned Opcode);
893
bool isRSM(unsigned Opcode);
894
bool isVPCOMUD(unsigned Opcode);
895
bool isVPMOVZXBQ(unsigned Opcode);
896
bool isUWRMSR(unsigned Opcode);
897
bool isLGS(unsigned Opcode);
898
bool isVMOVNTPD(unsigned Opcode);
899
bool isRDPRU(unsigned Opcode);
900
bool isVPUNPCKHBW(unsigned Opcode);
901
bool isANDN(unsigned Opcode);
902
bool isVCVTTPH2UW(unsigned Opcode);
903
bool isVMFUNC(unsigned Opcode);
904
bool isFIMUL(unsigned Opcode);
905
bool isBLCFILL(unsigned Opcode);
906
bool isVGATHERPF0DPS(unsigned Opcode);
907
bool isVFMSUBADD231PS(unsigned Opcode);
908
bool isVREDUCESD(unsigned Opcode);
909
bool isVXORPS(unsigned Opcode);
910
bool isPSWAPD(unsigned Opcode);
911
bool isPMAXSD(unsigned Opcode);
912
bool isVCMPSS(unsigned Opcode);
913
bool isEXTRACTPS(unsigned Opcode);
914
bool isVPMOVZXBD(unsigned Opcode);
915
bool isOUTSW(unsigned Opcode);
916
bool isKORTESTB(unsigned Opcode);
917
bool isVREDUCEPS(unsigned Opcode);
918
bool isPEXTRW(unsigned Opcode);
919
bool isFNINIT(unsigned Opcode);
920
bool isROL(unsigned Opcode);
921
bool isVCVTPS2QQ(unsigned Opcode);
922
bool isVGETMANTPH(unsigned Opcode);
923
bool isPUNPCKLDQ(unsigned Opcode);
924
bool isPADDD(unsigned Opcode);
925
bool isVPSLLD(unsigned Opcode);
926
bool isPFCMPGE(unsigned Opcode);
927
bool isVPMOVM2D(unsigned Opcode);
928
bool isVHSUBPS(unsigned Opcode);
929
bool isENDBR32(unsigned Opcode);
930
bool isMOVSXD(unsigned Opcode);
931
bool isPSIGND(unsigned Opcode);
932
bool isVPTEST(unsigned Opcode);
933
bool isVPDPWUSD(unsigned Opcode);
934
bool isHSUBPD(unsigned Opcode);
935
bool isADCX(unsigned Opcode);
936
bool isCVTTPD2PI(unsigned Opcode);
937
bool isPDEP(unsigned Opcode);
938
bool isTDPBUSD(unsigned Opcode);
939
bool isVBROADCASTI32X4(unsigned Opcode);
940
bool isVCVTPH2UDQ(unsigned Opcode);
941
bool isVPHADDW(unsigned Opcode);
942
bool isFLDL2E(unsigned Opcode);
943
bool isCLZERO(unsigned Opcode);
944
bool isPBLENDW(unsigned Opcode);
945
bool isVCVTSH2USI(unsigned Opcode);
946
bool isVANDPD(unsigned Opcode);
947
bool isBEXTR(unsigned Opcode);
948
bool isSTD(unsigned Opcode);
949
bool isVAESKEYGENASSIST(unsigned Opcode);
950
bool isCMPSD(unsigned Opcode);
951
bool isMOVSS(unsigned Opcode);
952
bool isVCVTUQQ2PD(unsigned Opcode);
953
bool isVEXTRACTI32X4(unsigned Opcode);
954
bool isFLDCW(unsigned Opcode);
955
bool isINSW(unsigned Opcode);
956
bool isRDPID(unsigned Opcode);
957
bool isKANDQ(unsigned Opcode);
958
bool isV4FMADDPS(unsigned Opcode);
959
bool isPMOVZXWQ(unsigned Opcode);
960
bool isVFPCLASSSD(unsigned Opcode);
961
bool isBLENDPS(unsigned Opcode);
962
bool isVPACKSSDW(unsigned Opcode);
963
bool isVPINSRW(unsigned Opcode);
964
bool isFXAM(unsigned Opcode);
965
bool isVPHSUBBW(unsigned Opcode);
966
bool isVSHUFF64X2(unsigned Opcode);
967
bool isVPACKUSWB(unsigned Opcode);
968
bool isVRSQRT28SS(unsigned Opcode);
969
bool isGETSEC(unsigned Opcode);
970
bool isVEXTRACTF64X4(unsigned Opcode);
971
bool isBLSR(unsigned Opcode);
972
bool isFILD(unsigned Opcode);
973
bool isRETFQ(unsigned Opcode);
974
bool isVADDSS(unsigned Opcode);
975
bool isCOMISS(unsigned Opcode);
976
bool isCLI(unsigned Opcode);
977
bool isVERW(unsigned Opcode);
978
bool isBTC(unsigned Opcode);
979
bool isVPHADDUBQ(unsigned Opcode);
980
bool isVPORQ(unsigned Opcode);
981
bool isORPD(unsigned Opcode);
982
bool isVMOVSS(unsigned Opcode);
983
bool isVPSUBD(unsigned Opcode);
984
bool isVGATHERPF1QPD(unsigned Opcode);
985
bool isENCODEKEY256(unsigned Opcode);
986
bool isGF2P8AFFINEINVQB(unsigned Opcode);
987
bool isXRSTOR64(unsigned Opcode);
988
bool isKANDW(unsigned Opcode);
989
bool isLODSQ(unsigned Opcode);
990
bool isVSUBSH(unsigned Opcode);
991
bool isLSS(unsigned Opcode);
992
bool isPMOVSXBQ(unsigned Opcode);
993
bool isVCMPSH(unsigned Opcode);
994
bool isVFMADD132PS(unsigned Opcode);
995
bool isVPACKSSWB(unsigned Opcode);
996
bool isPCMPGTQ(unsigned Opcode);
997
bool isVFMADD132SH(unsigned Opcode);
998
bool isVCVTUQQ2PH(unsigned Opcode);
999
bool isVCVTQQ2PS(unsigned Opcode);
1000
bool isVCVTTSS2USI(unsigned Opcode);
1001
bool isVPMOVM2Q(unsigned Opcode);
1002
bool isVMOVD(unsigned Opcode);
1003
bool isVFPCLASSPH(unsigned Opcode);
1004
bool isVCVTSS2SH(unsigned Opcode);
1005
bool isSCASB(unsigned Opcode);
1006
bool isPSRLD(unsigned Opcode);
1007
bool isVADDPH(unsigned Opcode);
1008
bool isFSUB(unsigned Opcode);
1009
bool isVEXTRACTI64X2(unsigned Opcode);
1010
bool isPMINUW(unsigned Opcode);
1011
bool isPSUBSB(unsigned Opcode);
1012
bool isVPSHLDD(unsigned Opcode);
1013
bool isVPCMPEQD(unsigned Opcode);
1014
bool isVPSCATTERQD(unsigned Opcode);
1015
bool isKXNORB(unsigned Opcode);
1016
bool isCMPCC(unsigned Opcode);
1017
bool isMASKMOVQ(unsigned Opcode);
1018
bool isLDDQU(unsigned Opcode);
1019
bool isPABSW(unsigned Opcode);
1020
bool isVPROLD(unsigned Opcode);
1021
bool isVSCATTERDPD(unsigned Opcode);
1022
bool isVPCOMQ(unsigned Opcode);
1023
bool isFXRSTOR(unsigned Opcode);
1024
bool isVPCMPUW(unsigned Opcode);
1025
bool isWBINVD(unsigned Opcode);
1026
bool isVCVTTPD2UDQ(unsigned Opcode);
1027
bool isPFRCPIT2(unsigned Opcode);
1028
bool isVPERMT2W(unsigned Opcode);
1029
bool isVEXTRACTF32X4(unsigned Opcode);
1030
bool isVGATHERPF0DPD(unsigned Opcode);
1031
bool isVBROADCASTF32X2(unsigned Opcode);
1032
bool isVRCP14SD(unsigned Opcode);
1033
bool isPABSD(unsigned Opcode);
1034
bool isLAHF(unsigned Opcode);
1035
bool isPINSRB(unsigned Opcode);
1036
bool isSKINIT(unsigned Opcode);
1037
bool isENTER(unsigned Opcode);
1038
bool isVCVTSI2SS(unsigned Opcode);
1039
bool isVFMADD231PD(unsigned Opcode);
1040
bool isLOADIWKEY(unsigned Opcode);
1041
bool isVMOVNTDQA(unsigned Opcode);
1042
bool isVPERMT2PS(unsigned Opcode);
1043
bool isPUSHF(unsigned Opcode);
1044
bool isMPSADBW(unsigned Opcode);
1045
bool isVRSQRT14SS(unsigned Opcode);
1046
bool isVCVTDQ2PD(unsigned Opcode);
1047
bool isVORPS(unsigned Opcode);
1048
bool isVPEXPANDQ(unsigned Opcode);
1049
bool isVPSHRDD(unsigned Opcode);
1050
bool isTDPBSSD(unsigned Opcode);
1051
bool isTESTUI(unsigned Opcode);
1052
bool isVFMADDPD(unsigned Opcode);
1053
bool isVPANDND(unsigned Opcode);
1054
bool isVPMOVSDB(unsigned Opcode);
1055
bool isVPBROADCASTB(unsigned Opcode);
1056
bool isCVTPI2PD(unsigned Opcode);
1057
bool isVPERMI2B(unsigned Opcode);
1058
bool isVPMINSB(unsigned Opcode);
1059
bool isLAR(unsigned Opcode);
1060
bool isINVLPGB(unsigned Opcode);
1061
bool isTLBSYNC(unsigned Opcode);
1062
bool isFDIVP(unsigned Opcode);
1063
bool isVPSRLW(unsigned Opcode);
1064
bool isVRCP28SS(unsigned Opcode);
1065
bool isVMOVHPS(unsigned Opcode);
1066
bool isVPMACSSDD(unsigned Opcode);
1067
bool isPEXT(unsigned Opcode);
1068
bool isVRSQRT14SD(unsigned Opcode);
1069
bool isVPDPWSSD(unsigned Opcode);
1070
bool isVFMSUB231SD(unsigned Opcode);
1071
bool isVPMOVZXWQ(unsigned Opcode);
1072
bool isVMOVDQA(unsigned Opcode);
1073
bool isVFNMSUB213SD(unsigned Opcode);
1074
bool isVMINPS(unsigned Opcode);
1075
bool isVFMSUB231PS(unsigned Opcode);
1076
bool isVPCOMPRESSB(unsigned Opcode);
1077
bool isVPCMPEQQ(unsigned Opcode);
1078
bool isVRCPSS(unsigned Opcode);
1079
bool isVSCATTERPF1DPS(unsigned Opcode);
1080
bool isVPHADDUBW(unsigned Opcode);
1081
bool isXORPD(unsigned Opcode);
1082
bool isVPSCATTERQQ(unsigned Opcode);
1083
bool isVCVTW2PH(unsigned Opcode);
1084
bool isVFMADDCPH(unsigned Opcode);
1085
bool isVSUBPD(unsigned Opcode);
1086
bool isVPACKUSDW(unsigned Opcode);
1087
bool isVSCALEFSS(unsigned Opcode);
1088
bool isAESIMC(unsigned Opcode);
1089
bool isVRCP28PS(unsigned Opcode);
1090
bool isAAND(unsigned Opcode);
1091
bool isDAA(unsigned Opcode);
1092
bool isVCVTPD2UDQ(unsigned Opcode);
1093
bool isKTESTW(unsigned Opcode);
1094
bool isVPADDQ(unsigned Opcode);
1095
bool isPALIGNR(unsigned Opcode);
1096
bool isPMAXUW(unsigned Opcode);
1097
bool isVFMADDSD(unsigned Opcode);
1098
bool isPFMAX(unsigned Opcode);
1099
bool isVPOR(unsigned Opcode);
1100
bool isVPSUBB(unsigned Opcode);
1101
bool isVPAVGB(unsigned Opcode);
1102
bool isINSB(unsigned Opcode);
1103
bool isFYL2X(unsigned Opcode);
1104
bool isVFNMSUB132PD(unsigned Opcode);
1105
bool isVFNMSUBPS(unsigned Opcode);
1106
bool isVFMADD231PS(unsigned Opcode);
1107
bool isVCVTTSS2SI(unsigned Opcode);
1108
bool isTCMMRLFP16PS(unsigned Opcode);
1109
bool isFCOMPP(unsigned Opcode);
1110
bool isMOVD(unsigned Opcode);
1111
bool isMOVBE(unsigned Opcode);
1112
bool isVP2INTERSECTD(unsigned Opcode);
1113
bool isVPMULLQ(unsigned Opcode);
1114
bool isVSCALEFPS(unsigned Opcode);
1115
bool isVPMACSDQH(unsigned Opcode);
1116
bool isVPTESTNMD(unsigned Opcode);
1117
bool isFCOMP(unsigned Opcode);
1118
bool isPREFETCHWT1(unsigned Opcode);
1119
bool isVCMPSD(unsigned Opcode);
1120
bool isSGDTD(unsigned Opcode);
1121
bool isWRUSSD(unsigned Opcode);
1122
bool isFSUBP(unsigned Opcode);
1123
bool isVUNPCKLPS(unsigned Opcode);
1124
bool isVFNMSUB213SS(unsigned Opcode);
1125
bool isROUNDPD(unsigned Opcode);
1126
bool isVPMAXSW(unsigned Opcode);
1127
bool isVCVTTPH2DQ(unsigned Opcode);
1128
bool isVPUNPCKLWD(unsigned Opcode);
1129
bool isKSHIFTLD(unsigned Opcode);
1130
bool isVFMADD231SD(unsigned Opcode);
1131
bool isADDPS(unsigned Opcode);
1132
bool isVPSLLVD(unsigned Opcode);
1133
bool isVFNMADD132SH(unsigned Opcode);
1134
bool isVMOVNTPS(unsigned Opcode);
1135
bool isVCVTPD2DQ(unsigned Opcode);
1136
bool isVPXOR(unsigned Opcode);
1137
bool isSTMXCSR(unsigned Opcode);
1138
bool isVRCP14SS(unsigned Opcode);
1139
bool isUD2(unsigned Opcode);
1140
bool isVPOPCNTW(unsigned Opcode);
1141
bool isVRSQRTSH(unsigned Opcode);
1142
bool isVSCATTERPF0DPD(unsigned Opcode);
1143
bool isVFMADDPS(unsigned Opcode);
1144
bool isXSAVEC64(unsigned Opcode);
1145
bool isVPMADDUBSW(unsigned Opcode);
1146
bool isVPMOVZXDQ(unsigned Opcode);
1147
bool isVRCP14PS(unsigned Opcode);
1148
bool isVSQRTSH(unsigned Opcode);
1149
bool isLOOP(unsigned Opcode);
1150
bool isSTUI(unsigned Opcode);
1151
bool isVCVTTPS2UDQ(unsigned Opcode);
1152
bool isVCOMPRESSPS(unsigned Opcode);
1153
bool isXABORT(unsigned Opcode);
1154
bool isVPADDW(unsigned Opcode);
1155
bool isVPSIGND(unsigned Opcode);
1156
bool isVRNDSCALEPS(unsigned Opcode);
1157
bool isVPHADDUWD(unsigned Opcode);
1158
bool isVDBPSADBW(unsigned Opcode);
1159
bool isPSLLW(unsigned Opcode);
1160
bool isVPMOVQD(unsigned Opcode);
1161
bool isVINSERTI64X4(unsigned Opcode);
1162
bool isVPERMI2PS(unsigned Opcode);
1163
bool isVMULPH(unsigned Opcode);
1164
bool isVPCMPUQ(unsigned Opcode);
1165
bool isVCVTUSI2SD(unsigned Opcode);
1166
bool isKXNORW(unsigned Opcode);
1167
bool isBLCIC(unsigned Opcode);
1168
bool isVFNMADD213SD(unsigned Opcode);
1169
bool isVPMACSWW(unsigned Opcode);
1170
bool isVMOVLPS(unsigned Opcode);
1171
bool isPCONFIG(unsigned Opcode);
1172
bool isPANDN(unsigned Opcode);
1173
bool isVGETEXPPD(unsigned Opcode);
1174
bool isVPSRLVQ(unsigned Opcode);
1175
bool isUD1(unsigned Opcode);
1176
bool isPMAXSB(unsigned Opcode);
1177
bool isVPROLQ(unsigned Opcode);
1178
bool isVSCATTERPF1QPD(unsigned Opcode);
1179
bool isVPSRLD(unsigned Opcode);
1180
bool isINT3(unsigned Opcode);
1181
bool isXRSTORS64(unsigned Opcode);
1182
bool isCVTSD2SI(unsigned Opcode);
1183
bool isVMAXSS(unsigned Opcode);
1184
bool isVPMINUB(unsigned Opcode);
1185
bool isKXNORQ(unsigned Opcode);
1186
bool isFLD(unsigned Opcode);
1187
bool isVSHUFI32X4(unsigned Opcode);
1188
bool isSAHF(unsigned Opcode);
1189
bool isPFRSQRT(unsigned Opcode);
1190
bool isSHRD(unsigned Opcode);
1191
bool isSYSEXIT(unsigned Opcode);
1192
bool isXSAVE64(unsigned Opcode);
1193
bool isVPMAXSD(unsigned Opcode);
1194
bool isCVTTSD2SI(unsigned Opcode);
1195
bool isPMOVMSKB(unsigned Opcode);
1196
bool isVRANGEPS(unsigned Opcode);
1197
bool isVADDSUBPS(unsigned Opcode);
1198
bool isVBROADCASTI128(unsigned Opcode);
1199
bool isPADDUSB(unsigned Opcode);
1200
bool isENCODEKEY128(unsigned Opcode);
1201
bool isOR(unsigned Opcode);
1202
bool isSTOSW(unsigned Opcode);
1203
bool isPAVGW(unsigned Opcode);
1204
bool isVCVTPD2PH(unsigned Opcode);
1205
bool isSHLX(unsigned Opcode);
1206
bool isVCVTSH2SD(unsigned Opcode);
1207
bool isVFMADD231SS(unsigned Opcode);
1208
bool isMOVNTSD(unsigned Opcode);
1209
bool isFLDPI(unsigned Opcode);
1210
bool isVCVTUSI2SS(unsigned Opcode);
1211
bool isPMOVSXBD(unsigned Opcode);
1212
bool isVPRORVQ(unsigned Opcode);
1213
bool isVPERMT2D(unsigned Opcode);
1214
bool isADDSS(unsigned Opcode);
1215
bool isAADD(unsigned Opcode);
1216
bool isVPSRLVW(unsigned Opcode);
1217
bool isVRSQRTPH(unsigned Opcode);
1218
bool isVLDDQU(unsigned Opcode);
1219
bool isKMOVD(unsigned Opcode);
1220
bool isENCLV(unsigned Opcode);
1221
bool isENCLU(unsigned Opcode);
1222
bool isPREFETCHT1(unsigned Opcode);
1223
bool isRSQRTPS(unsigned Opcode);
1224
bool isVCVTTSH2USI(unsigned Opcode);
1225
bool isPADDB(unsigned Opcode);
1226
bool isVMASKMOVDQU(unsigned Opcode);
1227
bool isPUNPCKLBW(unsigned Opcode);
1228
bool isMOV(unsigned Opcode);
1229
bool isMUL(unsigned Opcode);
1230
bool isRCL(unsigned Opcode);
1231
bool isVRCPSH(unsigned Opcode);
1232
bool isPFCMPEQ(unsigned Opcode);
1233
bool isMONITOR(unsigned Opcode);
1234
bool isFDIVR(unsigned Opcode);
1235
bool isPMINSD(unsigned Opcode);
1236
bool isPFRCP(unsigned Opcode);
1237
bool isKTESTQ(unsigned Opcode);
1238
bool isVCVTTPD2DQ(unsigned Opcode);
1239
bool isVSHUFF32X4(unsigned Opcode);
1240
bool isVPSLLVW(unsigned Opcode);
1241
bool isTDPBSUD(unsigned Opcode);
1242
bool isVPMINUQ(unsigned Opcode);
1243
bool isFIADD(unsigned Opcode);
1244
bool isFCMOVNU(unsigned Opcode);
1245
bool isVHSUBPD(unsigned Opcode);
1246
bool isKSHIFTRQ(unsigned Opcode);
1247
bool isMOVUPS(unsigned Opcode);
1248
bool isVMCALL(unsigned Opcode);
1249
bool isXADD(unsigned Opcode);
1250
bool isXRSTOR(unsigned Opcode);
1251
bool isVGATHERPF1DPD(unsigned Opcode);
1252
bool isRCR(unsigned Opcode);
1253
bool isFNSTCW(unsigned Opcode);
1254
bool isVPMOVSDW(unsigned Opcode);
1255
bool isVFMSUB132SH(unsigned Opcode);
1256
bool isVPCONFLICTQ(unsigned Opcode);
1257
bool isSWAPGS(unsigned Opcode);
1258
bool isVPMOVQ2M(unsigned Opcode);
1259
bool isVPSRAVW(unsigned Opcode);
1260
bool isMOVDQA(unsigned Opcode);
1261
bool isDIVSD(unsigned Opcode);
1262
bool isPCMPGTB(unsigned Opcode);
1263
bool isSHA256MSG2(unsigned Opcode);
1264
bool isKXORW(unsigned Opcode);
1265
bool isLIDTW(unsigned Opcode);
1266
bool isPMULHW(unsigned Opcode);
1267
bool isVAESENCLAST(unsigned Opcode);
1268
bool isVINSERTI32X8(unsigned Opcode);
1269
bool isVRCPPS(unsigned Opcode);
1270
bool isVGATHERQPS(unsigned Opcode);
1271
bool isPMADDWD(unsigned Opcode);
1272
bool isUCOMISS(unsigned Opcode);
1273
bool isXGETBV(unsigned Opcode);
1274
bool isVCVTPD2QQ(unsigned Opcode);
1275
bool isVGETEXPPS(unsigned Opcode);
1276
bool isFISTP(unsigned Opcode);
1277
bool isVINSERTF64X4(unsigned Opcode);
1278
bool isVMOVDQU16(unsigned Opcode);
1279
bool isVFMADD132PH(unsigned Opcode);
1280
bool isVFMSUBADD213PS(unsigned Opcode);
1281
bool isVMOVDQU32(unsigned Opcode);
1282
bool isFUCOM(unsigned Opcode);
1283
bool isHADDPS(unsigned Opcode);
1284
bool isCMP(unsigned Opcode);
1285
bool isCVTTPS2PI(unsigned Opcode);
1286
bool isIRETQ(unsigned Opcode);
1287
bool isPF2IW(unsigned Opcode);
1288
bool isPSHUFD(unsigned Opcode);
1289
bool isVDPPD(unsigned Opcode);
1290
bool isPSHUFHW(unsigned Opcode);
1291
bool isRMPADJUST(unsigned Opcode);
1292
bool isPI2FW(unsigned Opcode);
1293
bool isVCVTTPH2QQ(unsigned Opcode);
1294
bool isDIVPD(unsigned Opcode);
1295
bool isCLFLUSH(unsigned Opcode);
1296
bool isVPMINUW(unsigned Opcode);
1297
bool isIN(unsigned Opcode);
1298
bool isWRPKRU(unsigned Opcode);
1299
bool isINSERTPS(unsigned Opcode);
1300
bool isAAM(unsigned Opcode);
1301
bool isVPHADDUDQ(unsigned Opcode);
1302
bool isVSHA512MSG1(unsigned Opcode);
1303
bool isDIVPS(unsigned Opcode);
1304
bool isKNOTB(unsigned Opcode);
1305
bool isBLSFILL(unsigned Opcode);
1306
bool isVPCMPGTQ(unsigned Opcode);
1307
bool isMINSD(unsigned Opcode);
1308
bool isFPREM(unsigned Opcode);
1309
bool isVPUNPCKHQDQ(unsigned Opcode);
1310
bool isMINPD(unsigned Opcode);
1311
bool isVCVTTPD2QQ(unsigned Opcode);
1312
bool isVFMSUBPD(unsigned Opcode);
1313
bool isV4FMADDSS(unsigned Opcode);
1314
bool isCPUID(unsigned Opcode);
1315
bool isSETCC(unsigned Opcode);
1316
bool isVPDPWUUD(unsigned Opcode);
1317
bool isPMOVSXDQ(unsigned Opcode);
1318
bool isMWAIT(unsigned Opcode);
1319
bool isVPEXTRB(unsigned Opcode);
1320
bool isINVVPID(unsigned Opcode);
1321
bool isVPSHUFD(unsigned Opcode);
1322
bool isMOVLPS(unsigned Opcode);
1323
bool isVBLENDMPS(unsigned Opcode);
1324
bool isPMULLW(unsigned Opcode);
1325
bool isVCVTSH2SI(unsigned Opcode);
1326
bool isVPMOVSXWQ(unsigned Opcode);
1327
bool isFNSTENV(unsigned Opcode);
1328
bool isVPERMI2PD(unsigned Opcode);
1329
bool isMAXSS(unsigned Opcode);
1330
bool isCWDE(unsigned Opcode);
1331
bool isVBROADCASTI32X8(unsigned Opcode);
1332
bool isINT(unsigned Opcode);
1333
bool isENCLS(unsigned Opcode);
1334
bool isMOVNTQ(unsigned Opcode);
1335
bool isVDIVSH(unsigned Opcode);
1336
bool isMOVHLPS(unsigned Opcode);
1337
bool isVPMASKMOVD(unsigned Opcode);
1338
bool isVMOVSD(unsigned Opcode);
1339
bool isVPMINUD(unsigned Opcode);
1340
bool isVPCMPISTRM(unsigned Opcode);
1341
bool isVGETMANTSD(unsigned Opcode);
1342
bool isKSHIFTRW(unsigned Opcode);
1343
bool isAESDECLAST(unsigned Opcode);
1344
bool isVPTESTMB(unsigned Opcode);
1345
bool isVMPTRST(unsigned Opcode);
1346
bool isLLDT(unsigned Opcode);
1347
bool isMOVSB(unsigned Opcode);
1348
bool isTILELOADD(unsigned Opcode);
1349
bool isKTESTB(unsigned Opcode);
1350
bool isMOVUPD(unsigned Opcode);
1351
bool isSGDTW(unsigned Opcode);
1352
bool isDIVSS(unsigned Opcode);
1353
bool isPUNPCKHQDQ(unsigned Opcode);
1354
bool isVFMADD213SD(unsigned Opcode);
1355
bool isKXORD(unsigned Opcode);
1356
bool isVPMOVB2M(unsigned Opcode);
1357
bool isVMREAD(unsigned Opcode);
1358
bool isVPDPWSSDS(unsigned Opcode);
1359
bool isTILERELEASE(unsigned Opcode);
1360
bool isCLFLUSHOPT(unsigned Opcode);
1361
bool isDAS(unsigned Opcode);
1362
bool isVSCALEFPH(unsigned Opcode);
1363
bool isVSUBSD(unsigned Opcode);
1364
bool isVCOMISS(unsigned Opcode);
1365
bool isORPS(unsigned Opcode);
1366
bool isTDPFP16PS(unsigned Opcode);
1367
bool isVMAXPD(unsigned Opcode);
1368
bool isVPMOVWB(unsigned Opcode);
1369
bool isVEXP2PS(unsigned Opcode);
1370
bool isVPGATHERDQ(unsigned Opcode);
1371
bool isVPSRAVQ(unsigned Opcode);
1372
bool isPCMPISTRI(unsigned Opcode);
1373
bool isVFMSUB231PD(unsigned Opcode);
1374
bool isRDMSR(unsigned Opcode);
1375
bool isKORTESTD(unsigned Opcode);
1376
bool isVPBLENDMW(unsigned Opcode);
1377
bool isPSHUFB(unsigned Opcode);
1378
bool isVDPBF16PS(unsigned Opcode);
1379
bool isTDPBF16PS(unsigned Opcode);
1380
bool isFCMOVE(unsigned Opcode);
1381
bool isCMPSS(unsigned Opcode);
1382
bool isMASKMOVDQU(unsigned Opcode);
1383
bool isVPDPWUSDS(unsigned Opcode);
1384
bool isSARX(unsigned Opcode);
1385
bool isSGDT(unsigned Opcode);
1386
bool isVFMULCPH(unsigned Opcode);
1387
bool isURDMSR(unsigned Opcode);
1388
bool isKUNPCKWD(unsigned Opcode);
1389
bool isCVTPS2PD(unsigned Opcode);
1390
bool isFBSTP(unsigned Opcode);
1391
bool isPSUBQ(unsigned Opcode);
1392
bool isFXSAVE64(unsigned Opcode);
1393
bool isKMOVW(unsigned Opcode);
1394
bool isBTS(unsigned Opcode);
1395
bool isVPHADDBQ(unsigned Opcode);
1396
bool isFRSTOR(unsigned Opcode);
1397
bool isVFMSUB132PD(unsigned Opcode);
1398
bool isPMULLD(unsigned Opcode);
1399
bool isSHA1MSG2(unsigned Opcode);
1400
bool isJECXZ(unsigned Opcode);
1401
bool isVCVTUDQ2PS(unsigned Opcode);
1402
bool isAESENC(unsigned Opcode);
1403
bool isPSIGNW(unsigned Opcode);
1404
bool isUNPCKLPD(unsigned Opcode);
1405
bool isPUSHP(unsigned Opcode);
1406
bool isBLSI(unsigned Opcode);
1407
bool isVPTESTNMB(unsigned Opcode);
1408
bool isWRUSSQ(unsigned Opcode);
1409
bool isVGF2P8MULB(unsigned Opcode);
1410
bool isVPUNPCKLBW(unsigned Opcode);
1411
bool isVRANGESD(unsigned Opcode);
1412
bool isCLD(unsigned Opcode);
1413
bool isVSCALEFPD(unsigned Opcode);
1414
bool isVPERMQ(unsigned Opcode);
1415
bool isVPSHLDVW(unsigned Opcode);
1416
bool isROR(unsigned Opcode);
1417
bool isVFMADDSUB132PH(unsigned Opcode);
1418
bool isDEC(unsigned Opcode);
1419
bool isVGETEXPSH(unsigned Opcode);
1420
bool isAESDEC(unsigned Opcode);
1421
bool isKORD(unsigned Opcode);
1422
bool isVPMULHW(unsigned Opcode);
1423
bool isTILELOADDT1(unsigned Opcode);
1424
bool isVMASKMOVPS(unsigned Opcode);
1425
bool isPMOVZXDQ(unsigned Opcode);
1426
bool isVCVTPS2PH(unsigned Opcode);
1427
bool isCVTDQ2PD(unsigned Opcode);
1428
bool isVCVTSD2SS(unsigned Opcode);
1429
bool isVFMSUB213PH(unsigned Opcode);
1430
bool isVPROTB(unsigned Opcode);
1431
bool isPINSRD(unsigned Opcode);
1432
bool isVMXON(unsigned Opcode);
1433
bool isVFCMULCSH(unsigned Opcode);
1434
bool isVFMULCSH(unsigned Opcode);
1435
bool isVRANGEPD(unsigned Opcode);
1436
bool isCMC(unsigned Opcode);
1437
bool isSHA256MSG1(unsigned Opcode);
1438
bool isFLD1(unsigned Opcode);
1439
bool isCMPPS(unsigned Opcode);
1440
bool isVPAVGW(unsigned Opcode);
1441
bool isVFMADD213SH(unsigned Opcode);
1442
bool isVPINSRQ(unsigned Opcode);
1443
bool isMOVABS(unsigned Opcode);
1444
bool isVPSHAQ(unsigned Opcode);
1445
bool isRDTSCP(unsigned Opcode);
1446
bool isVFNMADD231SS(unsigned Opcode);
1447
bool isTEST(unsigned Opcode);
1448
bool isVPERMD(unsigned Opcode);
1449
bool isVBCSTNESH2PS(unsigned Opcode);
1450
bool isVGATHERPF0QPD(unsigned Opcode);
1451
bool isVPERM2I128(unsigned Opcode);
1452
bool isVMPSADBW(unsigned Opcode);
1453
bool isVFNMSUB231PD(unsigned Opcode);
1454
bool isPADDSB(unsigned Opcode);
1455
bool isMWAITX(unsigned Opcode);
1456
bool isMONITORX(unsigned Opcode);
1457
bool isVPEXPANDD(unsigned Opcode);
1458
bool isVFRCZPD(unsigned Opcode);
1459
bool isVRCPPH(unsigned Opcode);
1460
bool isFEMMS(unsigned Opcode);
1461
bool isVSCATTERQPD(unsigned Opcode);
1462
bool isVMOVW(unsigned Opcode);
1463
bool isVPBROADCASTD(unsigned Opcode);
1464
bool isSTOSB(unsigned Opcode);
1465
bool isFUCOMI(unsigned Opcode);
1466
bool isVBROADCASTI64X4(unsigned Opcode);
1467
bool isFCMOVU(unsigned Opcode);
1468
bool isPSHUFLW(unsigned Opcode);
1469
bool isCVTPI2PS(unsigned Opcode);
1470
bool isVFMADD231SH(unsigned Opcode);
1471
bool isSYSCALL(unsigned Opcode);
1472
bool isVPOPCNTB(unsigned Opcode);
1473
bool isPMOVZXBW(unsigned Opcode);
1474
bool isVCVTDQ2PS(unsigned Opcode);
1475
bool isPSUBD(unsigned Opcode);
1476
bool isVPCMPEQW(unsigned Opcode);
1477
bool isMOVSW(unsigned Opcode);
1478
bool isVSM3RNDS2(unsigned Opcode);
1479
bool isVPMOVUSQD(unsigned Opcode);
1480
bool isCVTTPD2DQ(unsigned Opcode);
1481
bool isVPEXPANDW(unsigned Opcode);
1482
bool isVUCOMISH(unsigned Opcode);
1483
bool isVZEROALL(unsigned Opcode);
1484
bool isVPAND(unsigned Opcode);
1485
bool isPMULDQ(unsigned Opcode);
1486
bool isVPSHUFHW(unsigned Opcode);
1487
bool isVPALIGNR(unsigned Opcode);
1488
bool isSQRTSD(unsigned Opcode);
1489
bool isVCVTTPH2UDQ(unsigned Opcode);
1490
bool isVGETEXPPH(unsigned Opcode);
1491
bool isADDPD(unsigned Opcode);
1492
bool isVFNMADDPD(unsigned Opcode);
1493
bool isSTTILECFG(unsigned Opcode);
1494
bool isVMINPD(unsigned Opcode);
1495
bool isSHA1RNDS4(unsigned Opcode);
1496
bool isPBLENDVB(unsigned Opcode);
1497
bool isVBROADCASTF128(unsigned Opcode);
1498
bool isVPSHRDQ(unsigned Opcode);
1499
bool isVAESIMC(unsigned Opcode);
1500
bool isCOMISD(unsigned Opcode);
1501
bool isVMOVSH(unsigned Opcode);
1502
bool isPFSUBR(unsigned Opcode);
1503
bool isRDSSPD(unsigned Opcode);
1504
bool isWAIT(unsigned Opcode);
1505
bool isVFPCLASSSS(unsigned Opcode);
1506
bool isPCMPGTD(unsigned Opcode);
1507
bool isVGATHERPF0QPS(unsigned Opcode);
1508
bool isBLENDVPS(unsigned Opcode);
1509
bool isVBROADCASTF32X4(unsigned Opcode);
1510
bool isVPMADD52LUQ(unsigned Opcode);
1511
bool isVMOVLPD(unsigned Opcode);
1512
bool isVMOVQ(unsigned Opcode);
1513
bool isVMOVDQU(unsigned Opcode);
1514
bool isAESENC128KL(unsigned Opcode);
1515
bool isVFMADDSUB231PS(unsigned Opcode);
1516
bool isVFNMSUB213PD(unsigned Opcode);
1517
bool isVPCONFLICTD(unsigned Opcode);
1518
bool isVFMADDSUB213PH(unsigned Opcode);
1519
bool isVPHSUBSW(unsigned Opcode);
1520
bool isPUNPCKHDQ(unsigned Opcode);
1521
bool isVSHUFI64X2(unsigned Opcode);
1522
bool isVFMSUBSD(unsigned Opcode);
1523
bool isVPORD(unsigned Opcode);
1524
bool isRCPPS(unsigned Opcode);
1525
bool isVEXTRACTI128(unsigned Opcode);
1526
bool isVPSHRDVW(unsigned Opcode);
1527
bool isVUNPCKLPD(unsigned Opcode);
1528
bool isVPSRAVD(unsigned Opcode);
1529
bool isVMULSH(unsigned Opcode);
1530
bool isMOVNTSS(unsigned Opcode);
1531
bool isSTI(unsigned Opcode);
1532
bool isVSM4RNDS4(unsigned Opcode);
1533
bool isVMCLEAR(unsigned Opcode);
1534
bool isVPMADD52HUQ(unsigned Opcode);
1535
bool isLIDT(unsigned Opcode);
1536
bool isPUSH2(unsigned Opcode);
1537
bool isRDPKRU(unsigned Opcode);
1538
bool isVPCMPB(unsigned Opcode);
1539
bool isFINCSTP(unsigned Opcode);
1540
bool isKORQ(unsigned Opcode);
1541
bool isXCRYPTCBC(unsigned Opcode);
1542
bool isRDPMC(unsigned Opcode);
1543
bool isMOVMSKPD(unsigned Opcode);
1544
bool isVFMSUB231SH(unsigned Opcode);
1545
bool isVEXTRACTF128(unsigned Opcode);
1546
bool isVPSHLB(unsigned Opcode);
1547
bool isXSAVES64(unsigned Opcode);
1548
bool isSHL(unsigned Opcode);
1549
bool isAXOR(unsigned Opcode);
1550
bool isVINSERTI64X2(unsigned Opcode);
1551
bool isSYSRETQ(unsigned Opcode);
1552
bool isVSCATTERPF0QPD(unsigned Opcode);
1553
bool isVFMSUB213SH(unsigned Opcode);
1554
bool isVPMOVQW(unsigned Opcode);
1555
bool isVREDUCEPD(unsigned Opcode);
1556
bool isNOT(unsigned Opcode);
1557
bool isLWPINS(unsigned Opcode);
1558
bool isVSCATTERDPS(unsigned Opcode);
1559
bool isVPMOVM2W(unsigned Opcode);
1560
bool isVFNMADD132PS(unsigned Opcode);
1561
bool isMOVNTPS(unsigned Opcode);
1562
bool isVRSQRTSS(unsigned Opcode);
1563
bool isKMOVB(unsigned Opcode);
1564
bool isCVTSD2SS(unsigned Opcode);
1565
bool isVBROADCASTF64X2(unsigned Opcode);
1566
bool isMOVNTPD(unsigned Opcode);
1567
bool isMAXSD(unsigned Opcode);
1568
bool isCMPPD(unsigned Opcode);
1569
bool isVPCMPESTRM(unsigned Opcode);
1570
bool isVFMSUB132PS(unsigned Opcode);
1571
bool isVCOMISH(unsigned Opcode);
1572
bool isF2XM1(unsigned Opcode);
1573
bool isSQRTPD(unsigned Opcode);
1574
bool isVFMSUBADDPS(unsigned Opcode);
1575
bool isFXTRACT(unsigned Opcode);
1576
bool isVP4DPWSSD(unsigned Opcode);
1577
bool isVFMSUBADDPD(unsigned Opcode);
1578
bool isVBCSTNEBF162PS(unsigned Opcode);
1579
bool isVPGATHERQQ(unsigned Opcode);
1580
bool isPCMPEQB(unsigned Opcode);
1581
bool isTILESTORED(unsigned Opcode);
1582
bool isBLSMSK(unsigned Opcode);
1583
bool isVCVTTPS2DQ(unsigned Opcode);
1584
bool isVRNDSCALEPD(unsigned Opcode);
1585
bool isVMLOAD(unsigned Opcode);
1586
bool isVPTERNLOGQ(unsigned Opcode);
1587
bool isKXNORD(unsigned Opcode);
1588
bool isFXSAVE(unsigned Opcode);
1589
bool isVUNPCKHPD(unsigned Opcode);
1590
bool isCVTPS2DQ(unsigned Opcode);
1591
bool isVFMSUB213SS(unsigned Opcode);
1592
bool isVPOPCNTD(unsigned Opcode);
1593
bool isSALC(unsigned Opcode);
1594
bool isV4FNMADDSS(unsigned Opcode);
1595
bool isXCRYPTOFB(unsigned Opcode);
1596
bool isVORPD(unsigned Opcode);
1597
bool isLSL(unsigned Opcode);
1598
bool isXCRYPTCFB(unsigned Opcode);
1599
bool isVGETEXPSS(unsigned Opcode);
1600
bool isPSLLDQ(unsigned Opcode);
1601
bool isVPDPBUUD(unsigned Opcode);
1602
bool isVMXOFF(unsigned Opcode);
1603
bool isBLSIC(unsigned Opcode);
1604
bool isMOVLHPS(unsigned Opcode);
1605
bool isVFNMSUBSD(unsigned Opcode);
1606
bool isVFPCLASSSH(unsigned Opcode);
1607
bool isVPSHLQ(unsigned Opcode);
1608
bool isVROUNDPS(unsigned Opcode);
1609
bool isVSCATTERPF0QPS(unsigned Opcode);
1610
bool isVPERMI2D(unsigned Opcode);
1611
bool isFUCOMP(unsigned Opcode);
1612
bool isVCVTTPS2QQ(unsigned Opcode);
1613
bool isPUSHFD(unsigned Opcode);
1614
bool isKORB(unsigned Opcode);
1615
bool isVRCP28PD(unsigned Opcode);
1616
bool isVPABSD(unsigned Opcode);
1617
bool isVROUNDSS(unsigned Opcode);
1618
bool isVCVTSD2USI(unsigned Opcode);
1619
bool isVPERMPD(unsigned Opcode);
1620
bool isPMAXUD(unsigned Opcode);
1621
bool isVPMULHUW(unsigned Opcode);
1622
bool isVPABSB(unsigned Opcode);
1623
bool isFCHS(unsigned Opcode);
1624
bool isVPBLENDMB(unsigned Opcode);
1625
bool isVGETMANTSS(unsigned Opcode);
1626
bool isVPSLLW(unsigned Opcode);
1627
bool isVDIVPD(unsigned Opcode);
1628
bool isBLCMSK(unsigned Opcode);
1629
bool isFDIV(unsigned Opcode);
1630
bool isRSQRTSS(unsigned Opcode);
1631
bool isPOR(unsigned Opcode);
1632
bool isVMOVDQA32(unsigned Opcode);
1633
bool isVPHADDUWQ(unsigned Opcode);
1634
bool isPSRAD(unsigned Opcode);
1635
bool isPREFETCHW(unsigned Opcode);
1636
bool isFIDIVR(unsigned Opcode);
1637
bool isMOVHPS(unsigned Opcode);
1638
bool isVFNMSUB231PH(unsigned Opcode);
1639
bool isUNPCKLPS(unsigned Opcode);
1640
bool isVPSIGNB(unsigned Opcode);
1641
bool isSAVEPREVSSP(unsigned Opcode);
1642
bool isVSCALEFSD(unsigned Opcode);
1643
bool isFSIN(unsigned Opcode);
1644
bool isSCASQ(unsigned Opcode);
1645
bool isPCMPGTW(unsigned Opcode);
1646
bool isMULX(unsigned Opcode);
1647
bool isVPMAXUW(unsigned Opcode);
1648
bool isPAUSE(unsigned Opcode);
1649
bool isMOVQ2DQ(unsigned Opcode);
1650
bool isVPSUBQ(unsigned Opcode);
1651
bool isVPABSW(unsigned Opcode);
1652
bool isVPCOMPRESSD(unsigned Opcode);
1653
bool isVPMOVUSQW(unsigned Opcode);
1654
bool isBLENDVPD(unsigned Opcode);
1655
bool isVPMOVQB(unsigned Opcode);
1656
bool isVBLENDVPS(unsigned Opcode);
1657
bool isKSHIFTLQ(unsigned Opcode);
1658
bool isPMOVSXWD(unsigned Opcode);
1659
bool isPHSUBSW(unsigned Opcode);
1660
bool isPSRLQ(unsigned Opcode);
1661
bool isVCVTPH2DQ(unsigned Opcode);
1662
bool isFISUB(unsigned Opcode);
1663
bool isVCVTPS2UDQ(unsigned Opcode);
1664
bool isVMOVDDUP(unsigned Opcode);
1665
bool isPCMPEQD(unsigned Opcode);
1666
bool isVRSQRT28SD(unsigned Opcode);
1667
bool isLODSW(unsigned Opcode);
1668
bool isVPOPCNTQ(unsigned Opcode);
1669
bool isKSHIFTRB(unsigned Opcode);
1670
bool isVFNMADDPS(unsigned Opcode);
1671
bool isFXRSTOR64(unsigned Opcode);
1672
bool isVFMSUBADD213PD(unsigned Opcode);
1673
bool isVSQRTPH(unsigned Opcode);
1674
bool isPOPF(unsigned Opcode);
1675
bool isVPSUBUSB(unsigned Opcode);
1676
bool isPREFETCHIT1(unsigned Opcode);
1677
bool isVPADDSW(unsigned Opcode);
1678
bool isVADDSUBPD(unsigned Opcode);
1679
bool isKANDD(unsigned Opcode);
1680
bool isOUTSB(unsigned Opcode);
1681
bool isFNSTSW(unsigned Opcode);
1682
bool isPMINSB(unsigned Opcode);
1683
#endif // GET_X86_MNEMONIC_TABLES_H
1684
1685
#ifdef GET_X86_MNEMONIC_TABLES_CPP
1686
#undef GET_X86_MNEMONIC_TABLES_CPP
1687
1688
0
bool isFSUBRP(unsigned Opcode) {
1689
0
  return Opcode == SUBR_FPrST0;
1690
0
}
1691
1692
0
bool isVPDPBUSDS(unsigned Opcode) {
1693
0
  switch (Opcode) {
1694
0
  case VPDPBUSDSYrm:
1695
0
  case VPDPBUSDSYrr:
1696
0
  case VPDPBUSDSZ128m:
1697
0
  case VPDPBUSDSZ128mb:
1698
0
  case VPDPBUSDSZ128mbk:
1699
0
  case VPDPBUSDSZ128mbkz:
1700
0
  case VPDPBUSDSZ128mk:
1701
0
  case VPDPBUSDSZ128mkz:
1702
0
  case VPDPBUSDSZ128r:
1703
0
  case VPDPBUSDSZ128rk:
1704
0
  case VPDPBUSDSZ128rkz:
1705
0
  case VPDPBUSDSZ256m:
1706
0
  case VPDPBUSDSZ256mb:
1707
0
  case VPDPBUSDSZ256mbk:
1708
0
  case VPDPBUSDSZ256mbkz:
1709
0
  case VPDPBUSDSZ256mk:
1710
0
  case VPDPBUSDSZ256mkz:
1711
0
  case VPDPBUSDSZ256r:
1712
0
  case VPDPBUSDSZ256rk:
1713
0
  case VPDPBUSDSZ256rkz:
1714
0
  case VPDPBUSDSZm:
1715
0
  case VPDPBUSDSZmb:
1716
0
  case VPDPBUSDSZmbk:
1717
0
  case VPDPBUSDSZmbkz:
1718
0
  case VPDPBUSDSZmk:
1719
0
  case VPDPBUSDSZmkz:
1720
0
  case VPDPBUSDSZr:
1721
0
  case VPDPBUSDSZrk:
1722
0
  case VPDPBUSDSZrkz:
1723
0
  case VPDPBUSDSrm:
1724
0
  case VPDPBUSDSrr:
1725
0
    return true;
1726
0
  }
1727
0
  return false;
1728
0
}
1729
1730
0
bool isPUNPCKLWD(unsigned Opcode) {
1731
0
  switch (Opcode) {
1732
0
  case MMX_PUNPCKLWDrm:
1733
0
  case MMX_PUNPCKLWDrr:
1734
0
  case PUNPCKLWDrm:
1735
0
  case PUNPCKLWDrr:
1736
0
    return true;
1737
0
  }
1738
0
  return false;
1739
0
}
1740
1741
0
bool isPUNPCKLQDQ(unsigned Opcode) {
1742
0
  switch (Opcode) {
1743
0
  case PUNPCKLQDQrm:
1744
0
  case PUNPCKLQDQrr:
1745
0
    return true;
1746
0
  }
1747
0
  return false;
1748
0
}
1749
1750
0
bool isRDFSBASE(unsigned Opcode) {
1751
0
  switch (Opcode) {
1752
0
  case RDFSBASE:
1753
0
  case RDFSBASE64:
1754
0
    return true;
1755
0
  }
1756
0
  return false;
1757
0
}
1758
1759
0
bool isVPCMOV(unsigned Opcode) {
1760
0
  switch (Opcode) {
1761
0
  case VPCMOVYrmr:
1762
0
  case VPCMOVYrrm:
1763
0
  case VPCMOVYrrr:
1764
0
  case VPCMOVYrrr_REV:
1765
0
  case VPCMOVrmr:
1766
0
  case VPCMOVrrm:
1767
0
  case VPCMOVrrr:
1768
0
  case VPCMOVrrr_REV:
1769
0
    return true;
1770
0
  }
1771
0
  return false;
1772
0
}
1773
1774
0
bool isVDIVSD(unsigned Opcode) {
1775
0
  switch (Opcode) {
1776
0
  case VDIVSDZrm_Int:
1777
0
  case VDIVSDZrm_Intk:
1778
0
  case VDIVSDZrm_Intkz:
1779
0
  case VDIVSDZrr_Int:
1780
0
  case VDIVSDZrr_Intk:
1781
0
  case VDIVSDZrr_Intkz:
1782
0
  case VDIVSDZrrb_Int:
1783
0
  case VDIVSDZrrb_Intk:
1784
0
  case VDIVSDZrrb_Intkz:
1785
0
  case VDIVSDrm_Int:
1786
0
  case VDIVSDrr_Int:
1787
0
    return true;
1788
0
  }
1789
0
  return false;
1790
0
}
1791
1792
0
bool isVPEXTRW(unsigned Opcode) {
1793
0
  switch (Opcode) {
1794
0
  case VPEXTRWZmr:
1795
0
  case VPEXTRWZrr:
1796
0
  case VPEXTRWZrr_REV:
1797
0
  case VPEXTRWmr:
1798
0
  case VPEXTRWrr:
1799
0
  case VPEXTRWrr_REV:
1800
0
    return true;
1801
0
  }
1802
0
  return false;
1803
0
}
1804
1805
0
bool isLODSD(unsigned Opcode) {
1806
0
  return Opcode == LODSL;
1807
0
}
1808
1809
0
bool isVPTESTNMQ(unsigned Opcode) {
1810
0
  switch (Opcode) {
1811
0
  case VPTESTNMQZ128rm:
1812
0
  case VPTESTNMQZ128rmb:
1813
0
  case VPTESTNMQZ128rmbk:
1814
0
  case VPTESTNMQZ128rmk:
1815
0
  case VPTESTNMQZ128rr:
1816
0
  case VPTESTNMQZ128rrk:
1817
0
  case VPTESTNMQZ256rm:
1818
0
  case VPTESTNMQZ256rmb:
1819
0
  case VPTESTNMQZ256rmbk:
1820
0
  case VPTESTNMQZ256rmk:
1821
0
  case VPTESTNMQZ256rr:
1822
0
  case VPTESTNMQZ256rrk:
1823
0
  case VPTESTNMQZrm:
1824
0
  case VPTESTNMQZrmb:
1825
0
  case VPTESTNMQZrmbk:
1826
0
  case VPTESTNMQZrmk:
1827
0
  case VPTESTNMQZrr:
1828
0
  case VPTESTNMQZrrk:
1829
0
    return true;
1830
0
  }
1831
0
  return false;
1832
0
}
1833
1834
0
bool isCVTSS2SD(unsigned Opcode) {
1835
0
  switch (Opcode) {
1836
0
  case CVTSS2SDrm_Int:
1837
0
  case CVTSS2SDrr_Int:
1838
0
    return true;
1839
0
  }
1840
0
  return false;
1841
0
}
1842
1843
0
bool isVGETMANTPD(unsigned Opcode) {
1844
0
  switch (Opcode) {
1845
0
  case VGETMANTPDZ128rmbi:
1846
0
  case VGETMANTPDZ128rmbik:
1847
0
  case VGETMANTPDZ128rmbikz:
1848
0
  case VGETMANTPDZ128rmi:
1849
0
  case VGETMANTPDZ128rmik:
1850
0
  case VGETMANTPDZ128rmikz:
1851
0
  case VGETMANTPDZ128rri:
1852
0
  case VGETMANTPDZ128rrik:
1853
0
  case VGETMANTPDZ128rrikz:
1854
0
  case VGETMANTPDZ256rmbi:
1855
0
  case VGETMANTPDZ256rmbik:
1856
0
  case VGETMANTPDZ256rmbikz:
1857
0
  case VGETMANTPDZ256rmi:
1858
0
  case VGETMANTPDZ256rmik:
1859
0
  case VGETMANTPDZ256rmikz:
1860
0
  case VGETMANTPDZ256rri:
1861
0
  case VGETMANTPDZ256rrik:
1862
0
  case VGETMANTPDZ256rrikz:
1863
0
  case VGETMANTPDZrmbi:
1864
0
  case VGETMANTPDZrmbik:
1865
0
  case VGETMANTPDZrmbikz:
1866
0
  case VGETMANTPDZrmi:
1867
0
  case VGETMANTPDZrmik:
1868
0
  case VGETMANTPDZrmikz:
1869
0
  case VGETMANTPDZrri:
1870
0
  case VGETMANTPDZrrib:
1871
0
  case VGETMANTPDZrribk:
1872
0
  case VGETMANTPDZrribkz:
1873
0
  case VGETMANTPDZrrik:
1874
0
  case VGETMANTPDZrrikz:
1875
0
    return true;
1876
0
  }
1877
0
  return false;
1878
0
}
1879
1880
0
bool isVMOVDQA64(unsigned Opcode) {
1881
0
  switch (Opcode) {
1882
0
  case VMOVDQA64Z128mr:
1883
0
  case VMOVDQA64Z128mrk:
1884
0
  case VMOVDQA64Z128rm:
1885
0
  case VMOVDQA64Z128rmk:
1886
0
  case VMOVDQA64Z128rmkz:
1887
0
  case VMOVDQA64Z128rr:
1888
0
  case VMOVDQA64Z128rr_REV:
1889
0
  case VMOVDQA64Z128rrk:
1890
0
  case VMOVDQA64Z128rrk_REV:
1891
0
  case VMOVDQA64Z128rrkz:
1892
0
  case VMOVDQA64Z128rrkz_REV:
1893
0
  case VMOVDQA64Z256mr:
1894
0
  case VMOVDQA64Z256mrk:
1895
0
  case VMOVDQA64Z256rm:
1896
0
  case VMOVDQA64Z256rmk:
1897
0
  case VMOVDQA64Z256rmkz:
1898
0
  case VMOVDQA64Z256rr:
1899
0
  case VMOVDQA64Z256rr_REV:
1900
0
  case VMOVDQA64Z256rrk:
1901
0
  case VMOVDQA64Z256rrk_REV:
1902
0
  case VMOVDQA64Z256rrkz:
1903
0
  case VMOVDQA64Z256rrkz_REV:
1904
0
  case VMOVDQA64Zmr:
1905
0
  case VMOVDQA64Zmrk:
1906
0
  case VMOVDQA64Zrm:
1907
0
  case VMOVDQA64Zrmk:
1908
0
  case VMOVDQA64Zrmkz:
1909
0
  case VMOVDQA64Zrr:
1910
0
  case VMOVDQA64Zrr_REV:
1911
0
  case VMOVDQA64Zrrk:
1912
0
  case VMOVDQA64Zrrk_REV:
1913
0
  case VMOVDQA64Zrrkz:
1914
0
  case VMOVDQA64Zrrkz_REV:
1915
0
    return true;
1916
0
  }
1917
0
  return false;
1918
0
}
1919
1920
0
bool isINVLPG(unsigned Opcode) {
1921
0
  return Opcode == INVLPG;
1922
0
}
1923
1924
0
bool isVBROADCASTF64X4(unsigned Opcode) {
1925
0
  switch (Opcode) {
1926
0
  case VBROADCASTF64X4rm:
1927
0
  case VBROADCASTF64X4rmk:
1928
0
  case VBROADCASTF64X4rmkz:
1929
0
    return true;
1930
0
  }
1931
0
  return false;
1932
0
}
1933
1934
0
bool isVPERMI2Q(unsigned Opcode) {
1935
0
  switch (Opcode) {
1936
0
  case VPERMI2QZ128rm:
1937
0
  case VPERMI2QZ128rmb:
1938
0
  case VPERMI2QZ128rmbk:
1939
0
  case VPERMI2QZ128rmbkz:
1940
0
  case VPERMI2QZ128rmk:
1941
0
  case VPERMI2QZ128rmkz:
1942
0
  case VPERMI2QZ128rr:
1943
0
  case VPERMI2QZ128rrk:
1944
0
  case VPERMI2QZ128rrkz:
1945
0
  case VPERMI2QZ256rm:
1946
0
  case VPERMI2QZ256rmb:
1947
0
  case VPERMI2QZ256rmbk:
1948
0
  case VPERMI2QZ256rmbkz:
1949
0
  case VPERMI2QZ256rmk:
1950
0
  case VPERMI2QZ256rmkz:
1951
0
  case VPERMI2QZ256rr:
1952
0
  case VPERMI2QZ256rrk:
1953
0
  case VPERMI2QZ256rrkz:
1954
0
  case VPERMI2QZrm:
1955
0
  case VPERMI2QZrmb:
1956
0
  case VPERMI2QZrmbk:
1957
0
  case VPERMI2QZrmbkz:
1958
0
  case VPERMI2QZrmk:
1959
0
  case VPERMI2QZrmkz:
1960
0
  case VPERMI2QZrr:
1961
0
  case VPERMI2QZrrk:
1962
0
  case VPERMI2QZrrkz:
1963
0
    return true;
1964
0
  }
1965
0
  return false;
1966
0
}
1967
1968
0
bool isVPMOVSXBD(unsigned Opcode) {
1969
0
  switch (Opcode) {
1970
0
  case VPMOVSXBDYrm:
1971
0
  case VPMOVSXBDYrr:
1972
0
  case VPMOVSXBDZ128rm:
1973
0
  case VPMOVSXBDZ128rmk:
1974
0
  case VPMOVSXBDZ128rmkz:
1975
0
  case VPMOVSXBDZ128rr:
1976
0
  case VPMOVSXBDZ128rrk:
1977
0
  case VPMOVSXBDZ128rrkz:
1978
0
  case VPMOVSXBDZ256rm:
1979
0
  case VPMOVSXBDZ256rmk:
1980
0
  case VPMOVSXBDZ256rmkz:
1981
0
  case VPMOVSXBDZ256rr:
1982
0
  case VPMOVSXBDZ256rrk:
1983
0
  case VPMOVSXBDZ256rrkz:
1984
0
  case VPMOVSXBDZrm:
1985
0
  case VPMOVSXBDZrmk:
1986
0
  case VPMOVSXBDZrmkz:
1987
0
  case VPMOVSXBDZrr:
1988
0
  case VPMOVSXBDZrrk:
1989
0
  case VPMOVSXBDZrrkz:
1990
0
  case VPMOVSXBDrm:
1991
0
  case VPMOVSXBDrr:
1992
0
    return true;
1993
0
  }
1994
0
  return false;
1995
0
}
1996
1997
0
bool isVFMSUB132SS(unsigned Opcode) {
1998
0
  switch (Opcode) {
1999
0
  case VFMSUB132SSZm_Int:
2000
0
  case VFMSUB132SSZm_Intk:
2001
0
  case VFMSUB132SSZm_Intkz:
2002
0
  case VFMSUB132SSZr_Int:
2003
0
  case VFMSUB132SSZr_Intk:
2004
0
  case VFMSUB132SSZr_Intkz:
2005
0
  case VFMSUB132SSZrb_Int:
2006
0
  case VFMSUB132SSZrb_Intk:
2007
0
  case VFMSUB132SSZrb_Intkz:
2008
0
  case VFMSUB132SSm_Int:
2009
0
  case VFMSUB132SSr_Int:
2010
0
    return true;
2011
0
  }
2012
0
  return false;
2013
0
}
2014
2015
0
bool isVPMOVUSDW(unsigned Opcode) {
2016
0
  switch (Opcode) {
2017
0
  case VPMOVUSDWZ128mr:
2018
0
  case VPMOVUSDWZ128mrk:
2019
0
  case VPMOVUSDWZ128rr:
2020
0
  case VPMOVUSDWZ128rrk:
2021
0
  case VPMOVUSDWZ128rrkz:
2022
0
  case VPMOVUSDWZ256mr:
2023
0
  case VPMOVUSDWZ256mrk:
2024
0
  case VPMOVUSDWZ256rr:
2025
0
  case VPMOVUSDWZ256rrk:
2026
0
  case VPMOVUSDWZ256rrkz:
2027
0
  case VPMOVUSDWZmr:
2028
0
  case VPMOVUSDWZmrk:
2029
0
  case VPMOVUSDWZrr:
2030
0
  case VPMOVUSDWZrrk:
2031
0
  case VPMOVUSDWZrrkz:
2032
0
    return true;
2033
0
  }
2034
0
  return false;
2035
0
}
2036
2037
0
bool isAAD(unsigned Opcode) {
2038
0
  return Opcode == AAD8i8;
2039
0
}
2040
2041
0
bool isIDIV(unsigned Opcode) {
2042
0
  switch (Opcode) {
2043
0
  case IDIV16m:
2044
0
  case IDIV16m_EVEX:
2045
0
  case IDIV16m_NF:
2046
0
  case IDIV16r:
2047
0
  case IDIV16r_EVEX:
2048
0
  case IDIV16r_NF:
2049
0
  case IDIV32m:
2050
0
  case IDIV32m_EVEX:
2051
0
  case IDIV32m_NF:
2052
0
  case IDIV32r:
2053
0
  case IDIV32r_EVEX:
2054
0
  case IDIV32r_NF:
2055
0
  case IDIV64m:
2056
0
  case IDIV64m_EVEX:
2057
0
  case IDIV64m_NF:
2058
0
  case IDIV64r:
2059
0
  case IDIV64r_EVEX:
2060
0
  case IDIV64r_NF:
2061
0
  case IDIV8m:
2062
0
  case IDIV8m_EVEX:
2063
0
  case IDIV8m_NF:
2064
0
  case IDIV8r:
2065
0
  case IDIV8r_EVEX:
2066
0
  case IDIV8r_NF:
2067
0
    return true;
2068
0
  }
2069
0
  return false;
2070
0
}
2071
2072
0
bool isCVTTPS2DQ(unsigned Opcode) {
2073
0
  switch (Opcode) {
2074
0
  case CVTTPS2DQrm:
2075
0
  case CVTTPS2DQrr:
2076
0
    return true;
2077
0
  }
2078
0
  return false;
2079
0
}
2080
2081
0
bool isVBROADCASTF32X8(unsigned Opcode) {
2082
0
  switch (Opcode) {
2083
0
  case VBROADCASTF32X8rm:
2084
0
  case VBROADCASTF32X8rmk:
2085
0
  case VBROADCASTF32X8rmkz:
2086
0
    return true;
2087
0
  }
2088
0
  return false;
2089
0
}
2090
2091
0
bool isVFMSUBSS(unsigned Opcode) {
2092
0
  switch (Opcode) {
2093
0
  case VFMSUBSS4mr:
2094
0
  case VFMSUBSS4rm:
2095
0
  case VFMSUBSS4rr:
2096
0
  case VFMSUBSS4rr_REV:
2097
0
    return true;
2098
0
  }
2099
0
  return false;
2100
0
}
2101
2102
0
bool isEMMS(unsigned Opcode) {
2103
0
  return Opcode == MMX_EMMS;
2104
0
}
2105
2106
0
bool isVPDPBSUD(unsigned Opcode) {
2107
0
  switch (Opcode) {
2108
0
  case VPDPBSUDYrm:
2109
0
  case VPDPBSUDYrr:
2110
0
  case VPDPBSUDrm:
2111
0
  case VPDPBSUDrr:
2112
0
    return true;
2113
0
  }
2114
0
  return false;
2115
0
}
2116
2117
0
bool isPMOVSXWQ(unsigned Opcode) {
2118
0
  switch (Opcode) {
2119
0
  case PMOVSXWQrm:
2120
0
  case PMOVSXWQrr:
2121
0
    return true;
2122
0
  }
2123
0
  return false;
2124
0
}
2125
2126
0
bool isPSRLW(unsigned Opcode) {
2127
0
  switch (Opcode) {
2128
0
  case MMX_PSRLWri:
2129
0
  case MMX_PSRLWrm:
2130
0
  case MMX_PSRLWrr:
2131
0
  case PSRLWri:
2132
0
  case PSRLWrm:
2133
0
  case PSRLWrr:
2134
0
    return true;
2135
0
  }
2136
0
  return false;
2137
0
}
2138
2139
0
bool isMOVNTDQA(unsigned Opcode) {
2140
0
  return Opcode == MOVNTDQArm;
2141
0
}
2142
2143
0
bool isFUCOMPI(unsigned Opcode) {
2144
0
  return Opcode == UCOM_FIPr;
2145
0
}
2146
2147
0
bool isANDNPS(unsigned Opcode) {
2148
0
  switch (Opcode) {
2149
0
  case ANDNPSrm:
2150
0
  case ANDNPSrr:
2151
0
    return true;
2152
0
  }
2153
0
  return false;
2154
0
}
2155
2156
0
bool isVINSERTF64X2(unsigned Opcode) {
2157
0
  switch (Opcode) {
2158
0
  case VINSERTF64x2Z256rm:
2159
0
  case VINSERTF64x2Z256rmk:
2160
0
  case VINSERTF64x2Z256rmkz:
2161
0
  case VINSERTF64x2Z256rr:
2162
0
  case VINSERTF64x2Z256rrk:
2163
0
  case VINSERTF64x2Z256rrkz:
2164
0
  case VINSERTF64x2Zrm:
2165
0
  case VINSERTF64x2Zrmk:
2166
0
  case VINSERTF64x2Zrmkz:
2167
0
  case VINSERTF64x2Zrr:
2168
0
  case VINSERTF64x2Zrrk:
2169
0
  case VINSERTF64x2Zrrkz:
2170
0
    return true;
2171
0
  }
2172
0
  return false;
2173
0
}
2174
2175
0
bool isCLTS(unsigned Opcode) {
2176
0
  return Opcode == CLTS;
2177
0
}
2178
2179
0
bool isSETSSBSY(unsigned Opcode) {
2180
0
  return Opcode == SETSSBSY;
2181
0
}
2182
2183
0
bool isVMULPD(unsigned Opcode) {
2184
0
  switch (Opcode) {
2185
0
  case VMULPDYrm:
2186
0
  case VMULPDYrr:
2187
0
  case VMULPDZ128rm:
2188
0
  case VMULPDZ128rmb:
2189
0
  case VMULPDZ128rmbk:
2190
0
  case VMULPDZ128rmbkz:
2191
0
  case VMULPDZ128rmk:
2192
0
  case VMULPDZ128rmkz:
2193
0
  case VMULPDZ128rr:
2194
0
  case VMULPDZ128rrk:
2195
0
  case VMULPDZ128rrkz:
2196
0
  case VMULPDZ256rm:
2197
0
  case VMULPDZ256rmb:
2198
0
  case VMULPDZ256rmbk:
2199
0
  case VMULPDZ256rmbkz:
2200
0
  case VMULPDZ256rmk:
2201
0
  case VMULPDZ256rmkz:
2202
0
  case VMULPDZ256rr:
2203
0
  case VMULPDZ256rrk:
2204
0
  case VMULPDZ256rrkz:
2205
0
  case VMULPDZrm:
2206
0
  case VMULPDZrmb:
2207
0
  case VMULPDZrmbk:
2208
0
  case VMULPDZrmbkz:
2209
0
  case VMULPDZrmk:
2210
0
  case VMULPDZrmkz:
2211
0
  case VMULPDZrr:
2212
0
  case VMULPDZrrb:
2213
0
  case VMULPDZrrbk:
2214
0
  case VMULPDZrrbkz:
2215
0
  case VMULPDZrrk:
2216
0
  case VMULPDZrrkz:
2217
0
  case VMULPDrm:
2218
0
  case VMULPDrr:
2219
0
    return true;
2220
0
  }
2221
0
  return false;
2222
0
}
2223
2224
0
bool isVFMADDSUB132PS(unsigned Opcode) {
2225
0
  switch (Opcode) {
2226
0
  case VFMADDSUB132PSYm:
2227
0
  case VFMADDSUB132PSYr:
2228
0
  case VFMADDSUB132PSZ128m:
2229
0
  case VFMADDSUB132PSZ128mb:
2230
0
  case VFMADDSUB132PSZ128mbk:
2231
0
  case VFMADDSUB132PSZ128mbkz:
2232
0
  case VFMADDSUB132PSZ128mk:
2233
0
  case VFMADDSUB132PSZ128mkz:
2234
0
  case VFMADDSUB132PSZ128r:
2235
0
  case VFMADDSUB132PSZ128rk:
2236
0
  case VFMADDSUB132PSZ128rkz:
2237
0
  case VFMADDSUB132PSZ256m:
2238
0
  case VFMADDSUB132PSZ256mb:
2239
0
  case VFMADDSUB132PSZ256mbk:
2240
0
  case VFMADDSUB132PSZ256mbkz:
2241
0
  case VFMADDSUB132PSZ256mk:
2242
0
  case VFMADDSUB132PSZ256mkz:
2243
0
  case VFMADDSUB132PSZ256r:
2244
0
  case VFMADDSUB132PSZ256rk:
2245
0
  case VFMADDSUB132PSZ256rkz:
2246
0
  case VFMADDSUB132PSZm:
2247
0
  case VFMADDSUB132PSZmb:
2248
0
  case VFMADDSUB132PSZmbk:
2249
0
  case VFMADDSUB132PSZmbkz:
2250
0
  case VFMADDSUB132PSZmk:
2251
0
  case VFMADDSUB132PSZmkz:
2252
0
  case VFMADDSUB132PSZr:
2253
0
  case VFMADDSUB132PSZrb:
2254
0
  case VFMADDSUB132PSZrbk:
2255
0
  case VFMADDSUB132PSZrbkz:
2256
0
  case VFMADDSUB132PSZrk:
2257
0
  case VFMADDSUB132PSZrkz:
2258
0
  case VFMADDSUB132PSm:
2259
0
  case VFMADDSUB132PSr:
2260
0
    return true;
2261
0
  }
2262
0
  return false;
2263
0
}
2264
2265
0
bool isVPMADCSWD(unsigned Opcode) {
2266
0
  switch (Opcode) {
2267
0
  case VPMADCSWDrm:
2268
0
  case VPMADCSWDrr:
2269
0
    return true;
2270
0
  }
2271
0
  return false;
2272
0
}
2273
2274
0
bool isVSCATTERPF0DPS(unsigned Opcode) {
2275
0
  return Opcode == VSCATTERPF0DPSm;
2276
0
}
2277
2278
0
bool isXCHG(unsigned Opcode) {
2279
0
  switch (Opcode) {
2280
0
  case XCHG16ar:
2281
0
  case XCHG16rm:
2282
0
  case XCHG16rr:
2283
0
  case XCHG32ar:
2284
0
  case XCHG32rm:
2285
0
  case XCHG32rr:
2286
0
  case XCHG64ar:
2287
0
  case XCHG64rm:
2288
0
  case XCHG64rr:
2289
0
  case XCHG8rm:
2290
0
  case XCHG8rr:
2291
0
    return true;
2292
0
  }
2293
0
  return false;
2294
0
}
2295
2296
0
bool isVGATHERPF1QPS(unsigned Opcode) {
2297
0
  return Opcode == VGATHERPF1QPSm;
2298
0
}
2299
2300
0
bool isVCVTNEPS2BF16(unsigned Opcode) {
2301
0
  switch (Opcode) {
2302
0
  case VCVTNEPS2BF16Yrm:
2303
0
  case VCVTNEPS2BF16Yrr:
2304
0
  case VCVTNEPS2BF16Z128rm:
2305
0
  case VCVTNEPS2BF16Z128rmb:
2306
0
  case VCVTNEPS2BF16Z128rmbk:
2307
0
  case VCVTNEPS2BF16Z128rmbkz:
2308
0
  case VCVTNEPS2BF16Z128rmk:
2309
0
  case VCVTNEPS2BF16Z128rmkz:
2310
0
  case VCVTNEPS2BF16Z128rr:
2311
0
  case VCVTNEPS2BF16Z128rrk:
2312
0
  case VCVTNEPS2BF16Z128rrkz:
2313
0
  case VCVTNEPS2BF16Z256rm:
2314
0
  case VCVTNEPS2BF16Z256rmb:
2315
0
  case VCVTNEPS2BF16Z256rmbk:
2316
0
  case VCVTNEPS2BF16Z256rmbkz:
2317
0
  case VCVTNEPS2BF16Z256rmk:
2318
0
  case VCVTNEPS2BF16Z256rmkz:
2319
0
  case VCVTNEPS2BF16Z256rr:
2320
0
  case VCVTNEPS2BF16Z256rrk:
2321
0
  case VCVTNEPS2BF16Z256rrkz:
2322
0
  case VCVTNEPS2BF16Zrm:
2323
0
  case VCVTNEPS2BF16Zrmb:
2324
0
  case VCVTNEPS2BF16Zrmbk:
2325
0
  case VCVTNEPS2BF16Zrmbkz:
2326
0
  case VCVTNEPS2BF16Zrmk:
2327
0
  case VCVTNEPS2BF16Zrmkz:
2328
0
  case VCVTNEPS2BF16Zrr:
2329
0
  case VCVTNEPS2BF16Zrrk:
2330
0
  case VCVTNEPS2BF16Zrrkz:
2331
0
  case VCVTNEPS2BF16rm:
2332
0
  case VCVTNEPS2BF16rr:
2333
0
    return true;
2334
0
  }
2335
0
  return false;
2336
0
}
2337
2338
0
bool isVFMADDSS(unsigned Opcode) {
2339
0
  switch (Opcode) {
2340
0
  case VFMADDSS4mr:
2341
0
  case VFMADDSS4rm:
2342
0
  case VFMADDSS4rr:
2343
0
  case VFMADDSS4rr_REV:
2344
0
    return true;
2345
0
  }
2346
0
  return false;
2347
0
}
2348
2349
0
bool isINTO(unsigned Opcode) {
2350
0
  return Opcode == INTO;
2351
0
}
2352
2353
0
bool isANDPD(unsigned Opcode) {
2354
0
  switch (Opcode) {
2355
0
  case ANDPDrm:
2356
0
  case ANDPDrr:
2357
0
    return true;
2358
0
  }
2359
0
  return false;
2360
0
}
2361
2362
0
bool isSEAMCALL(unsigned Opcode) {
2363
0
  return Opcode == SEAMCALL;
2364
0
}
2365
2366
0
bool isVPDPBSSDS(unsigned Opcode) {
2367
0
  switch (Opcode) {
2368
0
  case VPDPBSSDSYrm:
2369
0
  case VPDPBSSDSYrr:
2370
0
  case VPDPBSSDSrm:
2371
0
  case VPDPBSSDSrr:
2372
0
    return true;
2373
0
  }
2374
0
  return false;
2375
0
}
2376
2377
0
bool isUNPCKHPS(unsigned Opcode) {
2378
0
  switch (Opcode) {
2379
0
  case UNPCKHPSrm:
2380
0
  case UNPCKHPSrr:
2381
0
    return true;
2382
0
  }
2383
0
  return false;
2384
0
}
2385
2386
0
bool isSHLD(unsigned Opcode) {
2387
0
  switch (Opcode) {
2388
0
  case SHLD16mrCL:
2389
0
  case SHLD16mri8:
2390
0
  case SHLD16rrCL:
2391
0
  case SHLD16rri8:
2392
0
  case SHLD32mrCL:
2393
0
  case SHLD32mri8:
2394
0
  case SHLD32rrCL:
2395
0
  case SHLD32rri8:
2396
0
  case SHLD64mrCL:
2397
0
  case SHLD64mri8:
2398
0
  case SHLD64rrCL:
2399
0
  case SHLD64rri8:
2400
0
    return true;
2401
0
  }
2402
0
  return false;
2403
0
}
2404
2405
0
bool isSHUFPD(unsigned Opcode) {
2406
0
  switch (Opcode) {
2407
0
  case SHUFPDrmi:
2408
0
  case SHUFPDrri:
2409
0
    return true;
2410
0
  }
2411
0
  return false;
2412
0
}
2413
2414
0
bool isFCMOVNB(unsigned Opcode) {
2415
0
  return Opcode == CMOVNB_F;
2416
0
}
2417
2418
0
bool isCVTTSS2SI(unsigned Opcode) {
2419
0
  switch (Opcode) {
2420
0
  case CVTTSS2SI64rm_Int:
2421
0
  case CVTTSS2SI64rr_Int:
2422
0
  case CVTTSS2SIrm_Int:
2423
0
  case CVTTSS2SIrr_Int:
2424
0
    return true;
2425
0
  }
2426
0
  return false;
2427
0
}
2428
2429
0
bool isEXTRQ(unsigned Opcode) {
2430
0
  switch (Opcode) {
2431
0
  case EXTRQ:
2432
0
  case EXTRQI:
2433
0
    return true;
2434
0
  }
2435
0
  return false;
2436
0
}
2437
2438
0
bool isVBROADCASTSS(unsigned Opcode) {
2439
0
  switch (Opcode) {
2440
0
  case VBROADCASTSSYrm:
2441
0
  case VBROADCASTSSYrr:
2442
0
  case VBROADCASTSSZ128rm:
2443
0
  case VBROADCASTSSZ128rmk:
2444
0
  case VBROADCASTSSZ128rmkz:
2445
0
  case VBROADCASTSSZ128rr:
2446
0
  case VBROADCASTSSZ128rrk:
2447
0
  case VBROADCASTSSZ128rrkz:
2448
0
  case VBROADCASTSSZ256rm:
2449
0
  case VBROADCASTSSZ256rmk:
2450
0
  case VBROADCASTSSZ256rmkz:
2451
0
  case VBROADCASTSSZ256rr:
2452
0
  case VBROADCASTSSZ256rrk:
2453
0
  case VBROADCASTSSZ256rrkz:
2454
0
  case VBROADCASTSSZrm:
2455
0
  case VBROADCASTSSZrmk:
2456
0
  case VBROADCASTSSZrmkz:
2457
0
  case VBROADCASTSSZrr:
2458
0
  case VBROADCASTSSZrrk:
2459
0
  case VBROADCASTSSZrrkz:
2460
0
  case VBROADCASTSSrm:
2461
0
  case VBROADCASTSSrr:
2462
0
    return true;
2463
0
  }
2464
0
  return false;
2465
0
}
2466
2467
0
bool isCLUI(unsigned Opcode) {
2468
0
  return Opcode == CLUI;
2469
0
}
2470
2471
0
bool isVINSERTI128(unsigned Opcode) {
2472
0
  switch (Opcode) {
2473
0
  case VINSERTI128rm:
2474
0
  case VINSERTI128rr:
2475
0
    return true;
2476
0
  }
2477
0
  return false;
2478
0
}
2479
2480
0
bool isVBLENDPD(unsigned Opcode) {
2481
0
  switch (Opcode) {
2482
0
  case VBLENDPDYrmi:
2483
0
  case VBLENDPDYrri:
2484
0
  case VBLENDPDrmi:
2485
0
  case VBLENDPDrri:
2486
0
    return true;
2487
0
  }
2488
0
  return false;
2489
0
}
2490
2491
0
bool isVPSHLDW(unsigned Opcode) {
2492
0
  switch (Opcode) {
2493
0
  case VPSHLDWZ128rmi:
2494
0
  case VPSHLDWZ128rmik:
2495
0
  case VPSHLDWZ128rmikz:
2496
0
  case VPSHLDWZ128rri:
2497
0
  case VPSHLDWZ128rrik:
2498
0
  case VPSHLDWZ128rrikz:
2499
0
  case VPSHLDWZ256rmi:
2500
0
  case VPSHLDWZ256rmik:
2501
0
  case VPSHLDWZ256rmikz:
2502
0
  case VPSHLDWZ256rri:
2503
0
  case VPSHLDWZ256rrik:
2504
0
  case VPSHLDWZ256rrikz:
2505
0
  case VPSHLDWZrmi:
2506
0
  case VPSHLDWZrmik:
2507
0
  case VPSHLDWZrmikz:
2508
0
  case VPSHLDWZrri:
2509
0
  case VPSHLDWZrrik:
2510
0
  case VPSHLDWZrrikz:
2511
0
    return true;
2512
0
  }
2513
0
  return false;
2514
0
}
2515
2516
0
bool isVCVTNEEPH2PS(unsigned Opcode) {
2517
0
  switch (Opcode) {
2518
0
  case VCVTNEEPH2PSYrm:
2519
0
  case VCVTNEEPH2PSrm:
2520
0
    return true;
2521
0
  }
2522
0
  return false;
2523
0
}
2524
2525
0
bool isVCVTTSD2SI(unsigned Opcode) {
2526
0
  switch (Opcode) {
2527
0
  case VCVTTSD2SI64Zrm_Int:
2528
0
  case VCVTTSD2SI64Zrr_Int:
2529
0
  case VCVTTSD2SI64Zrrb_Int:
2530
0
  case VCVTTSD2SI64rm_Int:
2531
0
  case VCVTTSD2SI64rr_Int:
2532
0
  case VCVTTSD2SIZrm_Int:
2533
0
  case VCVTTSD2SIZrr_Int:
2534
0
  case VCVTTSD2SIZrrb_Int:
2535
0
  case VCVTTSD2SIrm_Int:
2536
0
  case VCVTTSD2SIrr_Int:
2537
0
    return true;
2538
0
  }
2539
0
  return false;
2540
0
}
2541
2542
0
bool isVSM4KEY4(unsigned Opcode) {
2543
0
  switch (Opcode) {
2544
0
  case VSM4KEY4Yrm:
2545
0
  case VSM4KEY4Yrr:
2546
0
  case VSM4KEY4rm:
2547
0
  case VSM4KEY4rr:
2548
0
    return true;
2549
0
  }
2550
0
  return false;
2551
0
}
2552
2553
0
bool isWRMSRNS(unsigned Opcode) {
2554
0
  return Opcode == WRMSRNS;
2555
0
}
2556
2557
0
bool isCMPSB(unsigned Opcode) {
2558
0
  return Opcode == CMPSB;
2559
0
}
2560
2561
0
bool isMULSS(unsigned Opcode) {
2562
0
  switch (Opcode) {
2563
0
  case MULSSrm_Int:
2564
0
  case MULSSrr_Int:
2565
0
    return true;
2566
0
  }
2567
0
  return false;
2568
0
}
2569
2570
0
bool isVMRUN(unsigned Opcode) {
2571
0
  switch (Opcode) {
2572
0
  case VMRUN32:
2573
0
  case VMRUN64:
2574
0
    return true;
2575
0
  }
2576
0
  return false;
2577
0
}
2578
2579
0
bool isVPSRLVD(unsigned Opcode) {
2580
0
  switch (Opcode) {
2581
0
  case VPSRLVDYrm:
2582
0
  case VPSRLVDYrr:
2583
0
  case VPSRLVDZ128rm:
2584
0
  case VPSRLVDZ128rmb:
2585
0
  case VPSRLVDZ128rmbk:
2586
0
  case VPSRLVDZ128rmbkz:
2587
0
  case VPSRLVDZ128rmk:
2588
0
  case VPSRLVDZ128rmkz:
2589
0
  case VPSRLVDZ128rr:
2590
0
  case VPSRLVDZ128rrk:
2591
0
  case VPSRLVDZ128rrkz:
2592
0
  case VPSRLVDZ256rm:
2593
0
  case VPSRLVDZ256rmb:
2594
0
  case VPSRLVDZ256rmbk:
2595
0
  case VPSRLVDZ256rmbkz:
2596
0
  case VPSRLVDZ256rmk:
2597
0
  case VPSRLVDZ256rmkz:
2598
0
  case VPSRLVDZ256rr:
2599
0
  case VPSRLVDZ256rrk:
2600
0
  case VPSRLVDZ256rrkz:
2601
0
  case VPSRLVDZrm:
2602
0
  case VPSRLVDZrmb:
2603
0
  case VPSRLVDZrmbk:
2604
0
  case VPSRLVDZrmbkz:
2605
0
  case VPSRLVDZrmk:
2606
0
  case VPSRLVDZrmkz:
2607
0
  case VPSRLVDZrr:
2608
0
  case VPSRLVDZrrk:
2609
0
  case VPSRLVDZrrkz:
2610
0
  case VPSRLVDrm:
2611
0
  case VPSRLVDrr:
2612
0
    return true;
2613
0
  }
2614
0
  return false;
2615
0
}
2616
2617
0
bool isLEAVE(unsigned Opcode) {
2618
0
  switch (Opcode) {
2619
0
  case LEAVE:
2620
0
  case LEAVE64:
2621
0
    return true;
2622
0
  }
2623
0
  return false;
2624
0
}
2625
2626
0
bool isVGETMANTPS(unsigned Opcode) {
2627
0
  switch (Opcode) {
2628
0
  case VGETMANTPSZ128rmbi:
2629
0
  case VGETMANTPSZ128rmbik:
2630
0
  case VGETMANTPSZ128rmbikz:
2631
0
  case VGETMANTPSZ128rmi:
2632
0
  case VGETMANTPSZ128rmik:
2633
0
  case VGETMANTPSZ128rmikz:
2634
0
  case VGETMANTPSZ128rri:
2635
0
  case VGETMANTPSZ128rrik:
2636
0
  case VGETMANTPSZ128rrikz:
2637
0
  case VGETMANTPSZ256rmbi:
2638
0
  case VGETMANTPSZ256rmbik:
2639
0
  case VGETMANTPSZ256rmbikz:
2640
0
  case VGETMANTPSZ256rmi:
2641
0
  case VGETMANTPSZ256rmik:
2642
0
  case VGETMANTPSZ256rmikz:
2643
0
  case VGETMANTPSZ256rri:
2644
0
  case VGETMANTPSZ256rrik:
2645
0
  case VGETMANTPSZ256rrikz:
2646
0
  case VGETMANTPSZrmbi:
2647
0
  case VGETMANTPSZrmbik:
2648
0
  case VGETMANTPSZrmbikz:
2649
0
  case VGETMANTPSZrmi:
2650
0
  case VGETMANTPSZrmik:
2651
0
  case VGETMANTPSZrmikz:
2652
0
  case VGETMANTPSZrri:
2653
0
  case VGETMANTPSZrrib:
2654
0
  case VGETMANTPSZrribk:
2655
0
  case VGETMANTPSZrribkz:
2656
0
  case VGETMANTPSZrrik:
2657
0
  case VGETMANTPSZrrikz:
2658
0
    return true;
2659
0
  }
2660
0
  return false;
2661
0
}
2662
2663
0
bool isXSHA256(unsigned Opcode) {
2664
0
  return Opcode == XSHA256;
2665
0
}
2666
2667
0
bool isBOUND(unsigned Opcode) {
2668
0
  switch (Opcode) {
2669
0
  case BOUNDS16rm:
2670
0
  case BOUNDS32rm:
2671
0
    return true;
2672
0
  }
2673
0
  return false;
2674
0
}
2675
2676
0
bool isSFENCE(unsigned Opcode) {
2677
0
  return Opcode == SFENCE;
2678
0
}
2679
2680
0
bool isVPHADDD(unsigned Opcode) {
2681
0
  switch (Opcode) {
2682
0
  case VPHADDDYrm:
2683
0
  case VPHADDDYrr:
2684
0
  case VPHADDDrm:
2685
0
  case VPHADDDrr:
2686
0
    return true;
2687
0
  }
2688
0
  return false;
2689
0
}
2690
2691
0
bool isADOX(unsigned Opcode) {
2692
0
  switch (Opcode) {
2693
0
  case ADOX32rm:
2694
0
  case ADOX32rm_EVEX:
2695
0
  case ADOX32rm_ND:
2696
0
  case ADOX32rr:
2697
0
  case ADOX32rr_EVEX:
2698
0
  case ADOX32rr_ND:
2699
0
  case ADOX64rm:
2700
0
  case ADOX64rm_EVEX:
2701
0
  case ADOX64rm_ND:
2702
0
  case ADOX64rr:
2703
0
  case ADOX64rr_EVEX:
2704
0
  case ADOX64rr_ND:
2705
0
    return true;
2706
0
  }
2707
0
  return false;
2708
0
}
2709
2710
0
bool isVPSLLQ(unsigned Opcode) {
2711
0
  switch (Opcode) {
2712
0
  case VPSLLQYri:
2713
0
  case VPSLLQYrm:
2714
0
  case VPSLLQYrr:
2715
0
  case VPSLLQZ128mbi:
2716
0
  case VPSLLQZ128mbik:
2717
0
  case VPSLLQZ128mbikz:
2718
0
  case VPSLLQZ128mi:
2719
0
  case VPSLLQZ128mik:
2720
0
  case VPSLLQZ128mikz:
2721
0
  case VPSLLQZ128ri:
2722
0
  case VPSLLQZ128rik:
2723
0
  case VPSLLQZ128rikz:
2724
0
  case VPSLLQZ128rm:
2725
0
  case VPSLLQZ128rmk:
2726
0
  case VPSLLQZ128rmkz:
2727
0
  case VPSLLQZ128rr:
2728
0
  case VPSLLQZ128rrk:
2729
0
  case VPSLLQZ128rrkz:
2730
0
  case VPSLLQZ256mbi:
2731
0
  case VPSLLQZ256mbik:
2732
0
  case VPSLLQZ256mbikz:
2733
0
  case VPSLLQZ256mi:
2734
0
  case VPSLLQZ256mik:
2735
0
  case VPSLLQZ256mikz:
2736
0
  case VPSLLQZ256ri:
2737
0
  case VPSLLQZ256rik:
2738
0
  case VPSLLQZ256rikz:
2739
0
  case VPSLLQZ256rm:
2740
0
  case VPSLLQZ256rmk:
2741
0
  case VPSLLQZ256rmkz:
2742
0
  case VPSLLQZ256rr:
2743
0
  case VPSLLQZ256rrk:
2744
0
  case VPSLLQZ256rrkz:
2745
0
  case VPSLLQZmbi:
2746
0
  case VPSLLQZmbik:
2747
0
  case VPSLLQZmbikz:
2748
0
  case VPSLLQZmi:
2749
0
  case VPSLLQZmik:
2750
0
  case VPSLLQZmikz:
2751
0
  case VPSLLQZri:
2752
0
  case VPSLLQZrik:
2753
0
  case VPSLLQZrikz:
2754
0
  case VPSLLQZrm:
2755
0
  case VPSLLQZrmk:
2756
0
  case VPSLLQZrmkz:
2757
0
  case VPSLLQZrr:
2758
0
  case VPSLLQZrrk:
2759
0
  case VPSLLQZrrkz:
2760
0
  case VPSLLQri:
2761
0
  case VPSLLQrm:
2762
0
  case VPSLLQrr:
2763
0
    return true;
2764
0
  }
2765
0
  return false;
2766
0
}
2767
2768
0
bool isPFRSQIT1(unsigned Opcode) {
2769
0
  switch (Opcode) {
2770
0
  case PFRSQIT1rm:
2771
0
  case PFRSQIT1rr:
2772
0
    return true;
2773
0
  }
2774
0
  return false;
2775
0
}
2776
2777
0
bool isCLAC(unsigned Opcode) {
2778
0
  return Opcode == CLAC;
2779
0
}
2780
2781
0
bool isKNOTW(unsigned Opcode) {
2782
0
  return Opcode == KNOTWrr;
2783
0
}
2784
2785
0
bool isVCVTPH2PD(unsigned Opcode) {
2786
0
  switch (Opcode) {
2787
0
  case VCVTPH2PDZ128rm:
2788
0
  case VCVTPH2PDZ128rmb:
2789
0
  case VCVTPH2PDZ128rmbk:
2790
0
  case VCVTPH2PDZ128rmbkz:
2791
0
  case VCVTPH2PDZ128rmk:
2792
0
  case VCVTPH2PDZ128rmkz:
2793
0
  case VCVTPH2PDZ128rr:
2794
0
  case VCVTPH2PDZ128rrk:
2795
0
  case VCVTPH2PDZ128rrkz:
2796
0
  case VCVTPH2PDZ256rm:
2797
0
  case VCVTPH2PDZ256rmb:
2798
0
  case VCVTPH2PDZ256rmbk:
2799
0
  case VCVTPH2PDZ256rmbkz:
2800
0
  case VCVTPH2PDZ256rmk:
2801
0
  case VCVTPH2PDZ256rmkz:
2802
0
  case VCVTPH2PDZ256rr:
2803
0
  case VCVTPH2PDZ256rrk:
2804
0
  case VCVTPH2PDZ256rrkz:
2805
0
  case VCVTPH2PDZrm:
2806
0
  case VCVTPH2PDZrmb:
2807
0
  case VCVTPH2PDZrmbk:
2808
0
  case VCVTPH2PDZrmbkz:
2809
0
  case VCVTPH2PDZrmk:
2810
0
  case VCVTPH2PDZrmkz:
2811
0
  case VCVTPH2PDZrr:
2812
0
  case VCVTPH2PDZrrb:
2813
0
  case VCVTPH2PDZrrbk:
2814
0
  case VCVTPH2PDZrrbkz:
2815
0
  case VCVTPH2PDZrrk:
2816
0
  case VCVTPH2PDZrrkz:
2817
0
    return true;
2818
0
  }
2819
0
  return false;
2820
0
}
2821
2822
0
bool isVAESENC(unsigned Opcode) {
2823
0
  switch (Opcode) {
2824
0
  case VAESENCYrm:
2825
0
  case VAESENCYrr:
2826
0
  case VAESENCZ128rm:
2827
0
  case VAESENCZ128rr:
2828
0
  case VAESENCZ256rm:
2829
0
  case VAESENCZ256rr:
2830
0
  case VAESENCZrm:
2831
0
  case VAESENCZrr:
2832
0
  case VAESENCrm:
2833
0
  case VAESENCrr:
2834
0
    return true;
2835
0
  }
2836
0
  return false;
2837
0
}
2838
2839
0
bool isMOVNTI(unsigned Opcode) {
2840
0
  switch (Opcode) {
2841
0
  case MOVNTI_64mr:
2842
0
  case MOVNTImr:
2843
0
    return true;
2844
0
  }
2845
0
  return false;
2846
0
}
2847
2848
0
bool isFXCH(unsigned Opcode) {
2849
0
  return Opcode == XCH_F;
2850
0
}
2851
2852
0
bool isPOPP(unsigned Opcode) {
2853
0
  return Opcode == POPP64r;
2854
0
}
2855
2856
0
bool isVPBLENDMD(unsigned Opcode) {
2857
0
  switch (Opcode) {
2858
0
  case VPBLENDMDZ128rm:
2859
0
  case VPBLENDMDZ128rmb:
2860
0
  case VPBLENDMDZ128rmbk:
2861
0
  case VPBLENDMDZ128rmbkz:
2862
0
  case VPBLENDMDZ128rmk:
2863
0
  case VPBLENDMDZ128rmkz:
2864
0
  case VPBLENDMDZ128rr:
2865
0
  case VPBLENDMDZ128rrk:
2866
0
  case VPBLENDMDZ128rrkz:
2867
0
  case VPBLENDMDZ256rm:
2868
0
  case VPBLENDMDZ256rmb:
2869
0
  case VPBLENDMDZ256rmbk:
2870
0
  case VPBLENDMDZ256rmbkz:
2871
0
  case VPBLENDMDZ256rmk:
2872
0
  case VPBLENDMDZ256rmkz:
2873
0
  case VPBLENDMDZ256rr:
2874
0
  case VPBLENDMDZ256rrk:
2875
0
  case VPBLENDMDZ256rrkz:
2876
0
  case VPBLENDMDZrm:
2877
0
  case VPBLENDMDZrmb:
2878
0
  case VPBLENDMDZrmbk:
2879
0
  case VPBLENDMDZrmbkz:
2880
0
  case VPBLENDMDZrmk:
2881
0
  case VPBLENDMDZrmkz:
2882
0
  case VPBLENDMDZrr:
2883
0
  case VPBLENDMDZrrk:
2884
0
  case VPBLENDMDZrrkz:
2885
0
    return true;
2886
0
  }
2887
0
  return false;
2888
0
}
2889
2890
0
bool isFSINCOS(unsigned Opcode) {
2891
0
  return Opcode == FSINCOS;
2892
0
}
2893
2894
0
bool isVPMULLW(unsigned Opcode) {
2895
0
  switch (Opcode) {
2896
0
  case VPMULLWYrm:
2897
0
  case VPMULLWYrr:
2898
0
  case VPMULLWZ128rm:
2899
0
  case VPMULLWZ128rmk:
2900
0
  case VPMULLWZ128rmkz:
2901
0
  case VPMULLWZ128rr:
2902
0
  case VPMULLWZ128rrk:
2903
0
  case VPMULLWZ128rrkz:
2904
0
  case VPMULLWZ256rm:
2905
0
  case VPMULLWZ256rmk:
2906
0
  case VPMULLWZ256rmkz:
2907
0
  case VPMULLWZ256rr:
2908
0
  case VPMULLWZ256rrk:
2909
0
  case VPMULLWZ256rrkz:
2910
0
  case VPMULLWZrm:
2911
0
  case VPMULLWZrmk:
2912
0
  case VPMULLWZrmkz:
2913
0
  case VPMULLWZrr:
2914
0
  case VPMULLWZrrk:
2915
0
  case VPMULLWZrrkz:
2916
0
  case VPMULLWrm:
2917
0
  case VPMULLWrr:
2918
0
    return true;
2919
0
  }
2920
0
  return false;
2921
0
}
2922
2923
0
bool isVPMOVSXBW(unsigned Opcode) {
2924
0
  switch (Opcode) {
2925
0
  case VPMOVSXBWYrm:
2926
0
  case VPMOVSXBWYrr:
2927
0
  case VPMOVSXBWZ128rm:
2928
0
  case VPMOVSXBWZ128rmk:
2929
0
  case VPMOVSXBWZ128rmkz:
2930
0
  case VPMOVSXBWZ128rr:
2931
0
  case VPMOVSXBWZ128rrk:
2932
0
  case VPMOVSXBWZ128rrkz:
2933
0
  case VPMOVSXBWZ256rm:
2934
0
  case VPMOVSXBWZ256rmk:
2935
0
  case VPMOVSXBWZ256rmkz:
2936
0
  case VPMOVSXBWZ256rr:
2937
0
  case VPMOVSXBWZ256rrk:
2938
0
  case VPMOVSXBWZ256rrkz:
2939
0
  case VPMOVSXBWZrm:
2940
0
  case VPMOVSXBWZrmk:
2941
0
  case VPMOVSXBWZrmkz:
2942
0
  case VPMOVSXBWZrr:
2943
0
  case VPMOVSXBWZrrk:
2944
0
  case VPMOVSXBWZrrkz:
2945
0
  case VPMOVSXBWrm:
2946
0
  case VPMOVSXBWrr:
2947
0
    return true;
2948
0
  }
2949
0
  return false;
2950
0
}
2951
2952
0
bool isSTC(unsigned Opcode) {
2953
0
  return Opcode == STC;
2954
0
}
2955
2956
0
bool isVPINSRB(unsigned Opcode) {
2957
0
  switch (Opcode) {
2958
0
  case VPINSRBZrm:
2959
0
  case VPINSRBZrr:
2960
0
  case VPINSRBrm:
2961
0
  case VPINSRBrr:
2962
0
    return true;
2963
0
  }
2964
0
  return false;
2965
0
}
2966
2967
0
bool isLWPVAL(unsigned Opcode) {
2968
0
  switch (Opcode) {
2969
0
  case LWPVAL32rmi:
2970
0
  case LWPVAL32rri:
2971
0
  case LWPVAL64rmi:
2972
0
  case LWPVAL64rri:
2973
0
    return true;
2974
0
  }
2975
0
  return false;
2976
0
}
2977
2978
0
bool isKXORB(unsigned Opcode) {
2979
0
  return Opcode == KXORBrr;
2980
0
}
2981
2982
0
bool isRSTORSSP(unsigned Opcode) {
2983
0
  return Opcode == RSTORSSP;
2984
0
}
2985
2986
0
bool isVPRORQ(unsigned Opcode) {
2987
0
  switch (Opcode) {
2988
0
  case VPRORQZ128mbi:
2989
0
  case VPRORQZ128mbik:
2990
0
  case VPRORQZ128mbikz:
2991
0
  case VPRORQZ128mi:
2992
0
  case VPRORQZ128mik:
2993
0
  case VPRORQZ128mikz:
2994
0
  case VPRORQZ128ri:
2995
0
  case VPRORQZ128rik:
2996
0
  case VPRORQZ128rikz:
2997
0
  case VPRORQZ256mbi:
2998
0
  case VPRORQZ256mbik:
2999
0
  case VPRORQZ256mbikz:
3000
0
  case VPRORQZ256mi:
3001
0
  case VPRORQZ256mik:
3002
0
  case VPRORQZ256mikz:
3003
0
  case VPRORQZ256ri:
3004
0
  case VPRORQZ256rik:
3005
0
  case VPRORQZ256rikz:
3006
0
  case VPRORQZmbi:
3007
0
  case VPRORQZmbik:
3008
0
  case VPRORQZmbikz:
3009
0
  case VPRORQZmi:
3010
0
  case VPRORQZmik:
3011
0
  case VPRORQZmikz:
3012
0
  case VPRORQZri:
3013
0
  case VPRORQZrik:
3014
0
  case VPRORQZrikz:
3015
0
    return true;
3016
0
  }
3017
0
  return false;
3018
0
}
3019
3020
0
bool isVSM3MSG1(unsigned Opcode) {
3021
0
  switch (Opcode) {
3022
0
  case VSM3MSG1rm:
3023
0
  case VSM3MSG1rr:
3024
0
    return true;
3025
0
  }
3026
0
  return false;
3027
0
}
3028
3029
0
bool isFICOM(unsigned Opcode) {
3030
0
  switch (Opcode) {
3031
0
  case FICOM16m:
3032
0
  case FICOM32m:
3033
0
    return true;
3034
0
  }
3035
0
  return false;
3036
0
}
3037
3038
0
bool isMAXPS(unsigned Opcode) {
3039
0
  switch (Opcode) {
3040
0
  case MAXPSrm:
3041
0
  case MAXPSrr:
3042
0
    return true;
3043
0
  }
3044
0
  return false;
3045
0
}
3046
3047
0
bool isFNCLEX(unsigned Opcode) {
3048
0
  return Opcode == FNCLEX;
3049
0
}
3050
3051
0
bool isVMOVMSKPS(unsigned Opcode) {
3052
0
  switch (Opcode) {
3053
0
  case VMOVMSKPSYrr:
3054
0
  case VMOVMSKPSrr:
3055
0
    return true;
3056
0
  }
3057
0
  return false;
3058
0
}
3059
3060
0
bool isVPMOVDB(unsigned Opcode) {
3061
0
  switch (Opcode) {
3062
0
  case VPMOVDBZ128mr:
3063
0
  case VPMOVDBZ128mrk:
3064
0
  case VPMOVDBZ128rr:
3065
0
  case VPMOVDBZ128rrk:
3066
0
  case VPMOVDBZ128rrkz:
3067
0
  case VPMOVDBZ256mr:
3068
0
  case VPMOVDBZ256mrk:
3069
0
  case VPMOVDBZ256rr:
3070
0
  case VPMOVDBZ256rrk:
3071
0
  case VPMOVDBZ256rrkz:
3072
0
  case VPMOVDBZmr:
3073
0
  case VPMOVDBZmrk:
3074
0
  case VPMOVDBZrr:
3075
0
  case VPMOVDBZrrk:
3076
0
  case VPMOVDBZrrkz:
3077
0
    return true;
3078
0
  }
3079
0
  return false;
3080
0
}
3081
3082
0
bool isLLWPCB(unsigned Opcode) {
3083
0
  switch (Opcode) {
3084
0
  case LLWPCB:
3085
0
  case LLWPCB64:
3086
0
    return true;
3087
0
  }
3088
0
  return false;
3089
0
}
3090
3091
0
bool isVMULSS(unsigned Opcode) {
3092
0
  switch (Opcode) {
3093
0
  case VMULSSZrm_Int:
3094
0
  case VMULSSZrm_Intk:
3095
0
  case VMULSSZrm_Intkz:
3096
0
  case VMULSSZrr_Int:
3097
0
  case VMULSSZrr_Intk:
3098
0
  case VMULSSZrr_Intkz:
3099
0
  case VMULSSZrrb_Int:
3100
0
  case VMULSSZrrb_Intk:
3101
0
  case VMULSSZrrb_Intkz:
3102
0
  case VMULSSrm_Int:
3103
0
  case VMULSSrr_Int:
3104
0
    return true;
3105
0
  }
3106
0
  return false;
3107
0
}
3108
3109
0
bool isAESENCLAST(unsigned Opcode) {
3110
0
  switch (Opcode) {
3111
0
  case AESENCLASTrm:
3112
0
  case AESENCLASTrr:
3113
0
    return true;
3114
0
  }
3115
0
  return false;
3116
0
}
3117
3118
0
bool isVPMAXUB(unsigned Opcode) {
3119
0
  switch (Opcode) {
3120
0
  case VPMAXUBYrm:
3121
0
  case VPMAXUBYrr:
3122
0
  case VPMAXUBZ128rm:
3123
0
  case VPMAXUBZ128rmk:
3124
0
  case VPMAXUBZ128rmkz:
3125
0
  case VPMAXUBZ128rr:
3126
0
  case VPMAXUBZ128rrk:
3127
0
  case VPMAXUBZ128rrkz:
3128
0
  case VPMAXUBZ256rm:
3129
0
  case VPMAXUBZ256rmk:
3130
0
  case VPMAXUBZ256rmkz:
3131
0
  case VPMAXUBZ256rr:
3132
0
  case VPMAXUBZ256rrk:
3133
0
  case VPMAXUBZ256rrkz:
3134
0
  case VPMAXUBZrm:
3135
0
  case VPMAXUBZrmk:
3136
0
  case VPMAXUBZrmkz:
3137
0
  case VPMAXUBZrr:
3138
0
  case VPMAXUBZrrk:
3139
0
  case VPMAXUBZrrkz:
3140
0
  case VPMAXUBrm:
3141
0
  case VPMAXUBrr:
3142
0
    return true;
3143
0
  }
3144
0
  return false;
3145
0
}
3146
3147
0
bool isAAS(unsigned Opcode) {
3148
0
  return Opcode == AAS;
3149
0
}
3150
3151
0
bool isFADD(unsigned Opcode) {
3152
0
  switch (Opcode) {
3153
0
  case ADD_F32m:
3154
0
  case ADD_F64m:
3155
0
  case ADD_FST0r:
3156
0
  case ADD_FrST0:
3157
0
    return true;
3158
0
  }
3159
0
  return false;
3160
0
}
3161
3162
0
bool isJMP(unsigned Opcode) {
3163
0
  switch (Opcode) {
3164
0
  case FARJMP32m:
3165
0
  case JMP16m:
3166
0
  case JMP16r:
3167
0
  case JMP32m:
3168
0
  case JMP32r:
3169
0
  case JMP64m:
3170
0
  case JMP64r:
3171
0
  case JMP_1:
3172
0
  case JMP_2:
3173
0
  case JMP_4:
3174
0
    return true;
3175
0
  }
3176
0
  return false;
3177
0
}
3178
3179
0
bool isXCRYPTECB(unsigned Opcode) {
3180
0
  return Opcode == XCRYPTECB;
3181
0
}
3182
3183
0
bool isPFRCPIT1(unsigned Opcode) {
3184
0
  switch (Opcode) {
3185
0
  case PFRCPIT1rm:
3186
0
  case PFRCPIT1rr:
3187
0
    return true;
3188
0
  }
3189
0
  return false;
3190
0
}
3191
3192
0
bool isPMULHRW(unsigned Opcode) {
3193
0
  switch (Opcode) {
3194
0
  case PMULHRWrm:
3195
0
  case PMULHRWrr:
3196
0
    return true;
3197
0
  }
3198
0
  return false;
3199
0
}
3200
3201
0
bool isVCVTPH2PS(unsigned Opcode) {
3202
0
  switch (Opcode) {
3203
0
  case VCVTPH2PSYrm:
3204
0
  case VCVTPH2PSYrr:
3205
0
  case VCVTPH2PSZ128rm:
3206
0
  case VCVTPH2PSZ128rmk:
3207
0
  case VCVTPH2PSZ128rmkz:
3208
0
  case VCVTPH2PSZ128rr:
3209
0
  case VCVTPH2PSZ128rrk:
3210
0
  case VCVTPH2PSZ128rrkz:
3211
0
  case VCVTPH2PSZ256rm:
3212
0
  case VCVTPH2PSZ256rmk:
3213
0
  case VCVTPH2PSZ256rmkz:
3214
0
  case VCVTPH2PSZ256rr:
3215
0
  case VCVTPH2PSZ256rrk:
3216
0
  case VCVTPH2PSZ256rrkz:
3217
0
  case VCVTPH2PSZrm:
3218
0
  case VCVTPH2PSZrmk:
3219
0
  case VCVTPH2PSZrmkz:
3220
0
  case VCVTPH2PSZrr:
3221
0
  case VCVTPH2PSZrrb:
3222
0
  case VCVTPH2PSZrrbk:
3223
0
  case VCVTPH2PSZrrbkz:
3224
0
  case VCVTPH2PSZrrk:
3225
0
  case VCVTPH2PSZrrkz:
3226
0
  case VCVTPH2PSrm:
3227
0
  case VCVTPH2PSrr:
3228
0
    return true;
3229
0
  }
3230
0
  return false;
3231
0
}
3232
3233
0
bool isVPBLENDVB(unsigned Opcode) {
3234
0
  switch (Opcode) {
3235
0
  case VPBLENDVBYrm:
3236
0
  case VPBLENDVBYrr:
3237
0
  case VPBLENDVBrm:
3238
0
  case VPBLENDVBrr:
3239
0
    return true;
3240
0
  }
3241
0
  return false;
3242
0
}
3243
3244
0
bool isPCMPESTRI(unsigned Opcode) {
3245
0
  switch (Opcode) {
3246
0
  case PCMPESTRIrm:
3247
0
  case PCMPESTRIrr:
3248
0
    return true;
3249
0
  }
3250
0
  return false;
3251
0
}
3252
3253
0
bool isSENDUIPI(unsigned Opcode) {
3254
0
  return Opcode == SENDUIPI;
3255
0
}
3256
3257
0
bool isFLDLN2(unsigned Opcode) {
3258
0
  return Opcode == FLDLN2;
3259
0
}
3260
3261
0
bool isVPMACSWD(unsigned Opcode) {
3262
0
  switch (Opcode) {
3263
0
  case VPMACSWDrm:
3264
0
  case VPMACSWDrr:
3265
0
    return true;
3266
0
  }
3267
0
  return false;
3268
0
}
3269
3270
0
bool isSHA1MSG1(unsigned Opcode) {
3271
0
  switch (Opcode) {
3272
0
  case SHA1MSG1rm:
3273
0
  case SHA1MSG1rm_EVEX:
3274
0
  case SHA1MSG1rr:
3275
0
  case SHA1MSG1rr_EVEX:
3276
0
    return true;
3277
0
  }
3278
0
  return false;
3279
0
}
3280
3281
0
bool isVADDPS(unsigned Opcode) {
3282
0
  switch (Opcode) {
3283
0
  case VADDPSYrm:
3284
0
  case VADDPSYrr:
3285
0
  case VADDPSZ128rm:
3286
0
  case VADDPSZ128rmb:
3287
0
  case VADDPSZ128rmbk:
3288
0
  case VADDPSZ128rmbkz:
3289
0
  case VADDPSZ128rmk:
3290
0
  case VADDPSZ128rmkz:
3291
0
  case VADDPSZ128rr:
3292
0
  case VADDPSZ128rrk:
3293
0
  case VADDPSZ128rrkz:
3294
0
  case VADDPSZ256rm:
3295
0
  case VADDPSZ256rmb:
3296
0
  case VADDPSZ256rmbk:
3297
0
  case VADDPSZ256rmbkz:
3298
0
  case VADDPSZ256rmk:
3299
0
  case VADDPSZ256rmkz:
3300
0
  case VADDPSZ256rr:
3301
0
  case VADDPSZ256rrk:
3302
0
  case VADDPSZ256rrkz:
3303
0
  case VADDPSZrm:
3304
0
  case VADDPSZrmb:
3305
0
  case VADDPSZrmbk:
3306
0
  case VADDPSZrmbkz:
3307
0
  case VADDPSZrmk:
3308
0
  case VADDPSZrmkz:
3309
0
  case VADDPSZrr:
3310
0
  case VADDPSZrrb:
3311
0
  case VADDPSZrrbk:
3312
0
  case VADDPSZrrbkz:
3313
0
  case VADDPSZrrk:
3314
0
  case VADDPSZrrkz:
3315
0
  case VADDPSrm:
3316
0
  case VADDPSrr:
3317
0
    return true;
3318
0
  }
3319
0
  return false;
3320
0
}
3321
3322
0
bool isVCVTPS2DQ(unsigned Opcode) {
3323
0
  switch (Opcode) {
3324
0
  case VCVTPS2DQYrm:
3325
0
  case VCVTPS2DQYrr:
3326
0
  case VCVTPS2DQZ128rm:
3327
0
  case VCVTPS2DQZ128rmb:
3328
0
  case VCVTPS2DQZ128rmbk:
3329
0
  case VCVTPS2DQZ128rmbkz:
3330
0
  case VCVTPS2DQZ128rmk:
3331
0
  case VCVTPS2DQZ128rmkz:
3332
0
  case VCVTPS2DQZ128rr:
3333
0
  case VCVTPS2DQZ128rrk:
3334
0
  case VCVTPS2DQZ128rrkz:
3335
0
  case VCVTPS2DQZ256rm:
3336
0
  case VCVTPS2DQZ256rmb:
3337
0
  case VCVTPS2DQZ256rmbk:
3338
0
  case VCVTPS2DQZ256rmbkz:
3339
0
  case VCVTPS2DQZ256rmk:
3340
0
  case VCVTPS2DQZ256rmkz:
3341
0
  case VCVTPS2DQZ256rr:
3342
0
  case VCVTPS2DQZ256rrk:
3343
0
  case VCVTPS2DQZ256rrkz:
3344
0
  case VCVTPS2DQZrm:
3345
0
  case VCVTPS2DQZrmb:
3346
0
  case VCVTPS2DQZrmbk:
3347
0
  case VCVTPS2DQZrmbkz:
3348
0
  case VCVTPS2DQZrmk:
3349
0
  case VCVTPS2DQZrmkz:
3350
0
  case VCVTPS2DQZrr:
3351
0
  case VCVTPS2DQZrrb:
3352
0
  case VCVTPS2DQZrrbk:
3353
0
  case VCVTPS2DQZrrbkz:
3354
0
  case VCVTPS2DQZrrk:
3355
0
  case VCVTPS2DQZrrkz:
3356
0
  case VCVTPS2DQrm:
3357
0
  case VCVTPS2DQrr:
3358
0
    return true;
3359
0
  }
3360
0
  return false;
3361
0
}
3362
3363
0
bool isPFPNACC(unsigned Opcode) {
3364
0
  switch (Opcode) {
3365
0
  case PFPNACCrm:
3366
0
  case PFPNACCrr:
3367
0
    return true;
3368
0
  }
3369
0
  return false;
3370
0
}
3371
3372
0
bool isFMUL(unsigned Opcode) {
3373
0
  switch (Opcode) {
3374
0
  case MUL_F32m:
3375
0
  case MUL_F64m:
3376
0
  case MUL_FST0r:
3377
0
  case MUL_FrST0:
3378
0
    return true;
3379
0
  }
3380
0
  return false;
3381
0
}
3382
3383
0
bool isFNSAVE(unsigned Opcode) {
3384
0
  return Opcode == FSAVEm;
3385
0
}
3386
3387
0
bool isCDQE(unsigned Opcode) {
3388
0
  return Opcode == CDQE;
3389
0
}
3390
3391
0
bool isVPMACSDD(unsigned Opcode) {
3392
0
  switch (Opcode) {
3393
0
  case VPMACSDDrm:
3394
0
  case VPMACSDDrr:
3395
0
    return true;
3396
0
  }
3397
0
  return false;
3398
0
}
3399
3400
0
bool isVSQRTPS(unsigned Opcode) {
3401
0
  switch (Opcode) {
3402
0
  case VSQRTPSYm:
3403
0
  case VSQRTPSYr:
3404
0
  case VSQRTPSZ128m:
3405
0
  case VSQRTPSZ128mb:
3406
0
  case VSQRTPSZ128mbk:
3407
0
  case VSQRTPSZ128mbkz:
3408
0
  case VSQRTPSZ128mk:
3409
0
  case VSQRTPSZ128mkz:
3410
0
  case VSQRTPSZ128r:
3411
0
  case VSQRTPSZ128rk:
3412
0
  case VSQRTPSZ128rkz:
3413
0
  case VSQRTPSZ256m:
3414
0
  case VSQRTPSZ256mb:
3415
0
  case VSQRTPSZ256mbk:
3416
0
  case VSQRTPSZ256mbkz:
3417
0
  case VSQRTPSZ256mk:
3418
0
  case VSQRTPSZ256mkz:
3419
0
  case VSQRTPSZ256r:
3420
0
  case VSQRTPSZ256rk:
3421
0
  case VSQRTPSZ256rkz:
3422
0
  case VSQRTPSZm:
3423
0
  case VSQRTPSZmb:
3424
0
  case VSQRTPSZmbk:
3425
0
  case VSQRTPSZmbkz:
3426
0
  case VSQRTPSZmk:
3427
0
  case VSQRTPSZmkz:
3428
0
  case VSQRTPSZr:
3429
0
  case VSQRTPSZrb:
3430
0
  case VSQRTPSZrbk:
3431
0
  case VSQRTPSZrbkz:
3432
0
  case VSQRTPSZrk:
3433
0
  case VSQRTPSZrkz:
3434
0
  case VSQRTPSm:
3435
0
  case VSQRTPSr:
3436
0
    return true;
3437
0
  }
3438
0
  return false;
3439
0
}
3440
3441
0
bool isCMPSQ(unsigned Opcode) {
3442
0
  return Opcode == CMPSQ;
3443
0
}
3444
3445
0
bool isVPSCATTERDD(unsigned Opcode) {
3446
0
  switch (Opcode) {
3447
0
  case VPSCATTERDDZ128mr:
3448
0
  case VPSCATTERDDZ256mr:
3449
0
  case VPSCATTERDDZmr:
3450
0
    return true;
3451
0
  }
3452
0
  return false;
3453
0
}
3454
3455
0
bool isVRNDSCALESD(unsigned Opcode) {
3456
0
  switch (Opcode) {
3457
0
  case VRNDSCALESDZm_Int:
3458
0
  case VRNDSCALESDZm_Intk:
3459
0
  case VRNDSCALESDZm_Intkz:
3460
0
  case VRNDSCALESDZr_Int:
3461
0
  case VRNDSCALESDZr_Intk:
3462
0
  case VRNDSCALESDZr_Intkz:
3463
0
  case VRNDSCALESDZrb_Int:
3464
0
  case VRNDSCALESDZrb_Intk:
3465
0
  case VRNDSCALESDZrb_Intkz:
3466
0
    return true;
3467
0
  }
3468
0
  return false;
3469
0
}
3470
3471
0
bool isSUBPS(unsigned Opcode) {
3472
0
  switch (Opcode) {
3473
0
  case SUBPSrm:
3474
0
  case SUBPSrr:
3475
0
    return true;
3476
0
  }
3477
0
  return false;
3478
0
}
3479
3480
0
bool isVMAXSH(unsigned Opcode) {
3481
0
  switch (Opcode) {
3482
0
  case VMAXSHZrm_Int:
3483
0
  case VMAXSHZrm_Intk:
3484
0
  case VMAXSHZrm_Intkz:
3485
0
  case VMAXSHZrr_Int:
3486
0
  case VMAXSHZrr_Intk:
3487
0
  case VMAXSHZrr_Intkz:
3488
0
  case VMAXSHZrrb_Int:
3489
0
  case VMAXSHZrrb_Intk:
3490
0
  case VMAXSHZrrb_Intkz:
3491
0
    return true;
3492
0
  }
3493
0
  return false;
3494
0
}
3495
3496
0
bool isFLDZ(unsigned Opcode) {
3497
0
  return Opcode == LD_F0;
3498
0
}
3499
3500
0
bool isVFNMADD132SS(unsigned Opcode) {
3501
0
  switch (Opcode) {
3502
0
  case VFNMADD132SSZm_Int:
3503
0
  case VFNMADD132SSZm_Intk:
3504
0
  case VFNMADD132SSZm_Intkz:
3505
0
  case VFNMADD132SSZr_Int:
3506
0
  case VFNMADD132SSZr_Intk:
3507
0
  case VFNMADD132SSZr_Intkz:
3508
0
  case VFNMADD132SSZrb_Int:
3509
0
  case VFNMADD132SSZrb_Intk:
3510
0
  case VFNMADD132SSZrb_Intkz:
3511
0
  case VFNMADD132SSm_Int:
3512
0
  case VFNMADD132SSr_Int:
3513
0
    return true;
3514
0
  }
3515
0
  return false;
3516
0
}
3517
3518
0
bool isLGDTW(unsigned Opcode) {
3519
0
  return Opcode == LGDT16m;
3520
0
}
3521
3522
0
bool isINC(unsigned Opcode) {
3523
0
  switch (Opcode) {
3524
0
  case INC16m:
3525
0
  case INC16m_EVEX:
3526
0
  case INC16m_ND:
3527
0
  case INC16m_NF:
3528
0
  case INC16m_NF_ND:
3529
0
  case INC16r:
3530
0
  case INC16r_EVEX:
3531
0
  case INC16r_ND:
3532
0
  case INC16r_NF:
3533
0
  case INC16r_NF_ND:
3534
0
  case INC16r_alt:
3535
0
  case INC32m:
3536
0
  case INC32m_EVEX:
3537
0
  case INC32m_ND:
3538
0
  case INC32m_NF:
3539
0
  case INC32m_NF_ND:
3540
0
  case INC32r:
3541
0
  case INC32r_EVEX:
3542
0
  case INC32r_ND:
3543
0
  case INC32r_NF:
3544
0
  case INC32r_NF_ND:
3545
0
  case INC32r_alt:
3546
0
  case INC64m:
3547
0
  case INC64m_EVEX:
3548
0
  case INC64m_ND:
3549
0
  case INC64m_NF:
3550
0
  case INC64m_NF_ND:
3551
0
  case INC64r:
3552
0
  case INC64r_EVEX:
3553
0
  case INC64r_ND:
3554
0
  case INC64r_NF:
3555
0
  case INC64r_NF_ND:
3556
0
  case INC8m:
3557
0
  case INC8m_EVEX:
3558
0
  case INC8m_ND:
3559
0
  case INC8m_NF:
3560
0
  case INC8m_NF_ND:
3561
0
  case INC8r:
3562
0
  case INC8r_EVEX:
3563
0
  case INC8r_ND:
3564
0
  case INC8r_NF:
3565
0
  case INC8r_NF_ND:
3566
0
    return true;
3567
0
  }
3568
0
  return false;
3569
0
}
3570
3571
0
bool isVPANDN(unsigned Opcode) {
3572
0
  switch (Opcode) {
3573
0
  case VPANDNYrm:
3574
0
  case VPANDNYrr:
3575
0
  case VPANDNrm:
3576
0
  case VPANDNrr:
3577
0
    return true;
3578
0
  }
3579
0
  return false;
3580
0
}
3581
3582
0
bool isPABSB(unsigned Opcode) {
3583
0
  switch (Opcode) {
3584
0
  case MMX_PABSBrm:
3585
0
  case MMX_PABSBrr:
3586
0
  case PABSBrm:
3587
0
  case PABSBrr:
3588
0
    return true;
3589
0
  }
3590
0
  return false;
3591
0
}
3592
3593
0
bool isVSHA512RNDS2(unsigned Opcode) {
3594
0
  return Opcode == VSHA512RNDS2rr;
3595
0
}
3596
3597
0
bool isPHADDSW(unsigned Opcode) {
3598
0
  switch (Opcode) {
3599
0
  case MMX_PHADDSWrm:
3600
0
  case MMX_PHADDSWrr:
3601
0
  case PHADDSWrm:
3602
0
  case PHADDSWrr:
3603
0
    return true;
3604
0
  }
3605
0
  return false;
3606
0
}
3607
3608
0
bool isVPMOVSQW(unsigned Opcode) {
3609
0
  switch (Opcode) {
3610
0
  case VPMOVSQWZ128mr:
3611
0
  case VPMOVSQWZ128mrk:
3612
0
  case VPMOVSQWZ128rr:
3613
0
  case VPMOVSQWZ128rrk:
3614
0
  case VPMOVSQWZ128rrkz:
3615
0
  case VPMOVSQWZ256mr:
3616
0
  case VPMOVSQWZ256mrk:
3617
0
  case VPMOVSQWZ256rr:
3618
0
  case VPMOVSQWZ256rrk:
3619
0
  case VPMOVSQWZ256rrkz:
3620
0
  case VPMOVSQWZmr:
3621
0
  case VPMOVSQWZmrk:
3622
0
  case VPMOVSQWZrr:
3623
0
  case VPMOVSQWZrrk:
3624
0
  case VPMOVSQWZrrkz:
3625
0
    return true;
3626
0
  }
3627
0
  return false;
3628
0
}
3629
3630
0
bool isVPMAXUD(unsigned Opcode) {
3631
0
  switch (Opcode) {
3632
0
  case VPMAXUDYrm:
3633
0
  case VPMAXUDYrr:
3634
0
  case VPMAXUDZ128rm:
3635
0
  case VPMAXUDZ128rmb:
3636
0
  case VPMAXUDZ128rmbk:
3637
0
  case VPMAXUDZ128rmbkz:
3638
0
  case VPMAXUDZ128rmk:
3639
0
  case VPMAXUDZ128rmkz:
3640
0
  case VPMAXUDZ128rr:
3641
0
  case VPMAXUDZ128rrk:
3642
0
  case VPMAXUDZ128rrkz:
3643
0
  case VPMAXUDZ256rm:
3644
0
  case VPMAXUDZ256rmb:
3645
0
  case VPMAXUDZ256rmbk:
3646
0
  case VPMAXUDZ256rmbkz:
3647
0
  case VPMAXUDZ256rmk:
3648
0
  case VPMAXUDZ256rmkz:
3649
0
  case VPMAXUDZ256rr:
3650
0
  case VPMAXUDZ256rrk:
3651
0
  case VPMAXUDZ256rrkz:
3652
0
  case VPMAXUDZrm:
3653
0
  case VPMAXUDZrmb:
3654
0
  case VPMAXUDZrmbk:
3655
0
  case VPMAXUDZrmbkz:
3656
0
  case VPMAXUDZrmk:
3657
0
  case VPMAXUDZrmkz:
3658
0
  case VPMAXUDZrr:
3659
0
  case VPMAXUDZrrk:
3660
0
  case VPMAXUDZrrkz:
3661
0
  case VPMAXUDrm:
3662
0
  case VPMAXUDrr:
3663
0
    return true;
3664
0
  }
3665
0
  return false;
3666
0
}
3667
3668
0
bool isADDSUBPS(unsigned Opcode) {
3669
0
  switch (Opcode) {
3670
0
  case ADDSUBPSrm:
3671
0
  case ADDSUBPSrr:
3672
0
    return true;
3673
0
  }
3674
0
  return false;
3675
0
}
3676
3677
0
bool isVPMACSSDQL(unsigned Opcode) {
3678
0
  switch (Opcode) {
3679
0
  case VPMACSSDQLrm:
3680
0
  case VPMACSSDQLrr:
3681
0
    return true;
3682
0
  }
3683
0
  return false;
3684
0
}
3685
3686
0
bool isPXOR(unsigned Opcode) {
3687
0
  switch (Opcode) {
3688
0
  case MMX_PXORrm:
3689
0
  case MMX_PXORrr:
3690
0
  case PXORrm:
3691
0
  case PXORrr:
3692
0
    return true;
3693
0
  }
3694
0
  return false;
3695
0
}
3696
3697
0
bool isVPSRAD(unsigned Opcode) {
3698
0
  switch (Opcode) {
3699
0
  case VPSRADYri:
3700
0
  case VPSRADYrm:
3701
0
  case VPSRADYrr:
3702
0
  case VPSRADZ128mbi:
3703
0
  case VPSRADZ128mbik:
3704
0
  case VPSRADZ128mbikz:
3705
0
  case VPSRADZ128mi:
3706
0
  case VPSRADZ128mik:
3707
0
  case VPSRADZ128mikz:
3708
0
  case VPSRADZ128ri:
3709
0
  case VPSRADZ128rik:
3710
0
  case VPSRADZ128rikz:
3711
0
  case VPSRADZ128rm:
3712
0
  case VPSRADZ128rmk:
3713
0
  case VPSRADZ128rmkz:
3714
0
  case VPSRADZ128rr:
3715
0
  case VPSRADZ128rrk:
3716
0
  case VPSRADZ128rrkz:
3717
0
  case VPSRADZ256mbi:
3718
0
  case VPSRADZ256mbik:
3719
0
  case VPSRADZ256mbikz:
3720
0
  case VPSRADZ256mi:
3721
0
  case VPSRADZ256mik:
3722
0
  case VPSRADZ256mikz:
3723
0
  case VPSRADZ256ri:
3724
0
  case VPSRADZ256rik:
3725
0
  case VPSRADZ256rikz:
3726
0
  case VPSRADZ256rm:
3727
0
  case VPSRADZ256rmk:
3728
0
  case VPSRADZ256rmkz:
3729
0
  case VPSRADZ256rr:
3730
0
  case VPSRADZ256rrk:
3731
0
  case VPSRADZ256rrkz:
3732
0
  case VPSRADZmbi:
3733
0
  case VPSRADZmbik:
3734
0
  case VPSRADZmbikz:
3735
0
  case VPSRADZmi:
3736
0
  case VPSRADZmik:
3737
0
  case VPSRADZmikz:
3738
0
  case VPSRADZri:
3739
0
  case VPSRADZrik:
3740
0
  case VPSRADZrikz:
3741
0
  case VPSRADZrm:
3742
0
  case VPSRADZrmk:
3743
0
  case VPSRADZrmkz:
3744
0
  case VPSRADZrr:
3745
0
  case VPSRADZrrk:
3746
0
  case VPSRADZrrkz:
3747
0
  case VPSRADri:
3748
0
  case VPSRADrm:
3749
0
  case VPSRADrr:
3750
0
    return true;
3751
0
  }
3752
0
  return false;
3753
0
}
3754
3755
0
bool isVPSHAB(unsigned Opcode) {
3756
0
  switch (Opcode) {
3757
0
  case VPSHABmr:
3758
0
  case VPSHABrm:
3759
0
  case VPSHABrr:
3760
0
  case VPSHABrr_REV:
3761
0
    return true;
3762
0
  }
3763
0
  return false;
3764
0
}
3765
3766
0
bool isBTR(unsigned Opcode) {
3767
0
  switch (Opcode) {
3768
0
  case BTR16mi8:
3769
0
  case BTR16mr:
3770
0
  case BTR16ri8:
3771
0
  case BTR16rr:
3772
0
  case BTR32mi8:
3773
0
  case BTR32mr:
3774
0
  case BTR32ri8:
3775
0
  case BTR32rr:
3776
0
  case BTR64mi8:
3777
0
  case BTR64mr:
3778
0
  case BTR64ri8:
3779
0
  case BTR64rr:
3780
0
    return true;
3781
0
  }
3782
0
  return false;
3783
0
}
3784
3785
0
bool isKORW(unsigned Opcode) {
3786
0
  return Opcode == KORWrr;
3787
0
}
3788
3789
0
bool isVRANGESS(unsigned Opcode) {
3790
0
  switch (Opcode) {
3791
0
  case VRANGESSZrmi:
3792
0
  case VRANGESSZrmik:
3793
0
  case VRANGESSZrmikz:
3794
0
  case VRANGESSZrri:
3795
0
  case VRANGESSZrrib:
3796
0
  case VRANGESSZrribk:
3797
0
  case VRANGESSZrribkz:
3798
0
  case VRANGESSZrrik:
3799
0
  case VRANGESSZrrikz:
3800
0
    return true;
3801
0
  }
3802
0
  return false;
3803
0
}
3804
3805
0
bool isVCMPPS(unsigned Opcode) {
3806
0
  switch (Opcode) {
3807
0
  case VCMPPSYrmi:
3808
0
  case VCMPPSYrri:
3809
0
  case VCMPPSZ128rmbi:
3810
0
  case VCMPPSZ128rmbik:
3811
0
  case VCMPPSZ128rmi:
3812
0
  case VCMPPSZ128rmik:
3813
0
  case VCMPPSZ128rri:
3814
0
  case VCMPPSZ128rrik:
3815
0
  case VCMPPSZ256rmbi:
3816
0
  case VCMPPSZ256rmbik:
3817
0
  case VCMPPSZ256rmi:
3818
0
  case VCMPPSZ256rmik:
3819
0
  case VCMPPSZ256rri:
3820
0
  case VCMPPSZ256rrik:
3821
0
  case VCMPPSZrmbi:
3822
0
  case VCMPPSZrmbik:
3823
0
  case VCMPPSZrmi:
3824
0
  case VCMPPSZrmik:
3825
0
  case VCMPPSZrri:
3826
0
  case VCMPPSZrrib:
3827
0
  case VCMPPSZrribk:
3828
0
  case VCMPPSZrrik:
3829
0
  case VCMPPSrmi:
3830
0
  case VCMPPSrri:
3831
0
    return true;
3832
0
  }
3833
0
  return false;
3834
0
}
3835
3836
0
bool isVPLZCNTD(unsigned Opcode) {
3837
0
  switch (Opcode) {
3838
0
  case VPLZCNTDZ128rm:
3839
0
  case VPLZCNTDZ128rmb:
3840
0
  case VPLZCNTDZ128rmbk:
3841
0
  case VPLZCNTDZ128rmbkz:
3842
0
  case VPLZCNTDZ128rmk:
3843
0
  case VPLZCNTDZ128rmkz:
3844
0
  case VPLZCNTDZ128rr:
3845
0
  case VPLZCNTDZ128rrk:
3846
0
  case VPLZCNTDZ128rrkz:
3847
0
  case VPLZCNTDZ256rm:
3848
0
  case VPLZCNTDZ256rmb:
3849
0
  case VPLZCNTDZ256rmbk:
3850
0
  case VPLZCNTDZ256rmbkz:
3851
0
  case VPLZCNTDZ256rmk:
3852
0
  case VPLZCNTDZ256rmkz:
3853
0
  case VPLZCNTDZ256rr:
3854
0
  case VPLZCNTDZ256rrk:
3855
0
  case VPLZCNTDZ256rrkz:
3856
0
  case VPLZCNTDZrm:
3857
0
  case VPLZCNTDZrmb:
3858
0
  case VPLZCNTDZrmbk:
3859
0
  case VPLZCNTDZrmbkz:
3860
0
  case VPLZCNTDZrmk:
3861
0
  case VPLZCNTDZrmkz:
3862
0
  case VPLZCNTDZrr:
3863
0
  case VPLZCNTDZrrk:
3864
0
  case VPLZCNTDZrrkz:
3865
0
    return true;
3866
0
  }
3867
0
  return false;
3868
0
}
3869
3870
0
bool isTDPBUUD(unsigned Opcode) {
3871
0
  return Opcode == TDPBUUD;
3872
0
}
3873
3874
0
bool isROUNDPS(unsigned Opcode) {
3875
0
  switch (Opcode) {
3876
0
  case ROUNDPSm:
3877
0
  case ROUNDPSr:
3878
0
    return true;
3879
0
  }
3880
0
  return false;
3881
0
}
3882
3883
0
bool isFABS(unsigned Opcode) {
3884
0
  return Opcode == ABS_F;
3885
0
}
3886
3887
0
bool isSUBPD(unsigned Opcode) {
3888
0
  switch (Opcode) {
3889
0
  case SUBPDrm:
3890
0
  case SUBPDrr:
3891
0
    return true;
3892
0
  }
3893
0
  return false;
3894
0
}
3895
3896
0
bool isGF2P8MULB(unsigned Opcode) {
3897
0
  switch (Opcode) {
3898
0
  case GF2P8MULBrm:
3899
0
  case GF2P8MULBrr:
3900
0
    return true;
3901
0
  }
3902
0
  return false;
3903
0
}
3904
3905
0
bool isTZMSK(unsigned Opcode) {
3906
0
  switch (Opcode) {
3907
0
  case TZMSK32rm:
3908
0
  case TZMSK32rr:
3909
0
  case TZMSK64rm:
3910
0
  case TZMSK64rr:
3911
0
    return true;
3912
0
  }
3913
0
  return false;
3914
0
}
3915
3916
0
bool isANDPS(unsigned Opcode) {
3917
0
  switch (Opcode) {
3918
0
  case ANDPSrm:
3919
0
  case ANDPSrr:
3920
0
    return true;
3921
0
  }
3922
0
  return false;
3923
0
}
3924
3925
0
bool isVEXTRACTF32X8(unsigned Opcode) {
3926
0
  switch (Opcode) {
3927
0
  case VEXTRACTF32x8Zmr:
3928
0
  case VEXTRACTF32x8Zmrk:
3929
0
  case VEXTRACTF32x8Zrr:
3930
0
  case VEXTRACTF32x8Zrrk:
3931
0
  case VEXTRACTF32x8Zrrkz:
3932
0
    return true;
3933
0
  }
3934
0
  return false;
3935
0
}
3936
3937
0
bool isSEAMRET(unsigned Opcode) {
3938
0
  return Opcode == SEAMRET;
3939
0
}
3940
3941
0
bool isVPCOMW(unsigned Opcode) {
3942
0
  switch (Opcode) {
3943
0
  case VPCOMWmi:
3944
0
  case VPCOMWri:
3945
0
    return true;
3946
0
  }
3947
0
  return false;
3948
0
}
3949
3950
0
bool isVFIXUPIMMPD(unsigned Opcode) {
3951
0
  switch (Opcode) {
3952
0
  case VFIXUPIMMPDZ128rmbi:
3953
0
  case VFIXUPIMMPDZ128rmbik:
3954
0
  case VFIXUPIMMPDZ128rmbikz:
3955
0
  case VFIXUPIMMPDZ128rmi:
3956
0
  case VFIXUPIMMPDZ128rmik:
3957
0
  case VFIXUPIMMPDZ128rmikz:
3958
0
  case VFIXUPIMMPDZ128rri:
3959
0
  case VFIXUPIMMPDZ128rrik:
3960
0
  case VFIXUPIMMPDZ128rrikz:
3961
0
  case VFIXUPIMMPDZ256rmbi:
3962
0
  case VFIXUPIMMPDZ256rmbik:
3963
0
  case VFIXUPIMMPDZ256rmbikz:
3964
0
  case VFIXUPIMMPDZ256rmi:
3965
0
  case VFIXUPIMMPDZ256rmik:
3966
0
  case VFIXUPIMMPDZ256rmikz:
3967
0
  case VFIXUPIMMPDZ256rri:
3968
0
  case VFIXUPIMMPDZ256rrik:
3969
0
  case VFIXUPIMMPDZ256rrikz:
3970
0
  case VFIXUPIMMPDZrmbi:
3971
0
  case VFIXUPIMMPDZrmbik:
3972
0
  case VFIXUPIMMPDZrmbikz:
3973
0
  case VFIXUPIMMPDZrmi:
3974
0
  case VFIXUPIMMPDZrmik:
3975
0
  case VFIXUPIMMPDZrmikz:
3976
0
  case VFIXUPIMMPDZrri:
3977
0
  case VFIXUPIMMPDZrrib:
3978
0
  case VFIXUPIMMPDZrribk:
3979
0
  case VFIXUPIMMPDZrribkz:
3980
0
  case VFIXUPIMMPDZrrik:
3981
0
  case VFIXUPIMMPDZrrikz:
3982
0
    return true;
3983
0
  }
3984
0
  return false;
3985
0
}
3986
3987
0
bool isKANDND(unsigned Opcode) {
3988
0
  return Opcode == KANDNDrr;
3989
0
}
3990
3991
0
bool isVMRESUME(unsigned Opcode) {
3992
0
  return Opcode == VMRESUME;
3993
0
}
3994
3995
0
bool isCVTPD2DQ(unsigned Opcode) {
3996
0
  switch (Opcode) {
3997
0
  case CVTPD2DQrm:
3998
0
  case CVTPD2DQrr:
3999
0
    return true;
4000
0
  }
4001
0
  return false;
4002
0
}
4003
4004
0
bool isVFNMADD213PS(unsigned Opcode) {
4005
0
  switch (Opcode) {
4006
0
  case VFNMADD213PSYm:
4007
0
  case VFNMADD213PSYr:
4008
0
  case VFNMADD213PSZ128m:
4009
0
  case VFNMADD213PSZ128mb:
4010
0
  case VFNMADD213PSZ128mbk:
4011
0
  case VFNMADD213PSZ128mbkz:
4012
0
  case VFNMADD213PSZ128mk:
4013
0
  case VFNMADD213PSZ128mkz:
4014
0
  case VFNMADD213PSZ128r:
4015
0
  case VFNMADD213PSZ128rk:
4016
0
  case VFNMADD213PSZ128rkz:
4017
0
  case VFNMADD213PSZ256m:
4018
0
  case VFNMADD213PSZ256mb:
4019
0
  case VFNMADD213PSZ256mbk:
4020
0
  case VFNMADD213PSZ256mbkz:
4021
0
  case VFNMADD213PSZ256mk:
4022
0
  case VFNMADD213PSZ256mkz:
4023
0
  case VFNMADD213PSZ256r:
4024
0
  case VFNMADD213PSZ256rk:
4025
0
  case VFNMADD213PSZ256rkz:
4026
0
  case VFNMADD213PSZm:
4027
0
  case VFNMADD213PSZmb:
4028
0
  case VFNMADD213PSZmbk:
4029
0
  case VFNMADD213PSZmbkz:
4030
0
  case VFNMADD213PSZmk:
4031
0
  case VFNMADD213PSZmkz:
4032
0
  case VFNMADD213PSZr:
4033
0
  case VFNMADD213PSZrb:
4034
0
  case VFNMADD213PSZrbk:
4035
0
  case VFNMADD213PSZrbkz:
4036
0
  case VFNMADD213PSZrk:
4037
0
  case VFNMADD213PSZrkz:
4038
0
  case VFNMADD213PSm:
4039
0
  case VFNMADD213PSr:
4040
0
    return true;
4041
0
  }
4042
0
  return false;
4043
0
}
4044
4045
0
bool isVPEXTRD(unsigned Opcode) {
4046
0
  switch (Opcode) {
4047
0
  case VPEXTRDZmr:
4048
0
  case VPEXTRDZrr:
4049
0
  case VPEXTRDmr:
4050
0
  case VPEXTRDrr:
4051
0
    return true;
4052
0
  }
4053
0
  return false;
4054
0
}
4055
4056
0
bool isPACKUSWB(unsigned Opcode) {
4057
0
  switch (Opcode) {
4058
0
  case MMX_PACKUSWBrm:
4059
0
  case MMX_PACKUSWBrr:
4060
0
  case PACKUSWBrm:
4061
0
  case PACKUSWBrr:
4062
0
    return true;
4063
0
  }
4064
0
  return false;
4065
0
}
4066
4067
0
bool isVEXTRACTI32X8(unsigned Opcode) {
4068
0
  switch (Opcode) {
4069
0
  case VEXTRACTI32x8Zmr:
4070
0
  case VEXTRACTI32x8Zmrk:
4071
0
  case VEXTRACTI32x8Zrr:
4072
0
  case VEXTRACTI32x8Zrrk:
4073
0
  case VEXTRACTI32x8Zrrkz:
4074
0
    return true;
4075
0
  }
4076
0
  return false;
4077
0
}
4078
4079
0
bool isVHADDPD(unsigned Opcode) {
4080
0
  switch (Opcode) {
4081
0
  case VHADDPDYrm:
4082
0
  case VHADDPDYrr:
4083
0
  case VHADDPDrm:
4084
0
  case VHADDPDrr:
4085
0
    return true;
4086
0
  }
4087
0
  return false;
4088
0
}
4089
4090
0
bool isVPSADBW(unsigned Opcode) {
4091
0
  switch (Opcode) {
4092
0
  case VPSADBWYrm:
4093
0
  case VPSADBWYrr:
4094
0
  case VPSADBWZ128rm:
4095
0
  case VPSADBWZ128rr:
4096
0
  case VPSADBWZ256rm:
4097
0
  case VPSADBWZ256rr:
4098
0
  case VPSADBWZrm:
4099
0
  case VPSADBWZrr:
4100
0
  case VPSADBWrm:
4101
0
  case VPSADBWrr:
4102
0
    return true;
4103
0
  }
4104
0
  return false;
4105
0
}
4106
4107
0
bool isMOVDQ2Q(unsigned Opcode) {
4108
0
  return Opcode == MMX_MOVDQ2Qrr;
4109
0
}
4110
4111
0
bool isPUNPCKHBW(unsigned Opcode) {
4112
0
  switch (Opcode) {
4113
0
  case MMX_PUNPCKHBWrm:
4114
0
  case MMX_PUNPCKHBWrr:
4115
0
  case PUNPCKHBWrm:
4116
0
  case PUNPCKHBWrr:
4117
0
    return true;
4118
0
  }
4119
0
  return false;
4120
0
}
4121
4122
0
bool isXOR(unsigned Opcode) {
4123
0
  switch (Opcode) {
4124
0
  case XOR16i16:
4125
0
  case XOR16mi:
4126
0
  case XOR16mi8:
4127
0
  case XOR16mi8_EVEX:
4128
0
  case XOR16mi8_ND:
4129
0
  case XOR16mi8_NF:
4130
0
  case XOR16mi8_NF_ND:
4131
0
  case XOR16mi_EVEX:
4132
0
  case XOR16mi_ND:
4133
0
  case XOR16mi_NF:
4134
0
  case XOR16mi_NF_ND:
4135
0
  case XOR16mr:
4136
0
  case XOR16mr_EVEX:
4137
0
  case XOR16mr_ND:
4138
0
  case XOR16mr_NF:
4139
0
  case XOR16mr_NF_ND:
4140
0
  case XOR16ri:
4141
0
  case XOR16ri8:
4142
0
  case XOR16ri8_EVEX:
4143
0
  case XOR16ri8_ND:
4144
0
  case XOR16ri8_NF:
4145
0
  case XOR16ri8_NF_ND:
4146
0
  case XOR16ri_EVEX:
4147
0
  case XOR16ri_ND:
4148
0
  case XOR16ri_NF:
4149
0
  case XOR16ri_NF_ND:
4150
0
  case XOR16rm:
4151
0
  case XOR16rm_EVEX:
4152
0
  case XOR16rm_ND:
4153
0
  case XOR16rm_NF:
4154
0
  case XOR16rm_NF_ND:
4155
0
  case XOR16rr:
4156
0
  case XOR16rr_EVEX:
4157
0
  case XOR16rr_EVEX_REV:
4158
0
  case XOR16rr_ND:
4159
0
  case XOR16rr_ND_REV:
4160
0
  case XOR16rr_NF:
4161
0
  case XOR16rr_NF_ND:
4162
0
  case XOR16rr_NF_ND_REV:
4163
0
  case XOR16rr_NF_REV:
4164
0
  case XOR16rr_REV:
4165
0
  case XOR32i32:
4166
0
  case XOR32mi:
4167
0
  case XOR32mi8:
4168
0
  case XOR32mi8_EVEX:
4169
0
  case XOR32mi8_ND:
4170
0
  case XOR32mi8_NF:
4171
0
  case XOR32mi8_NF_ND:
4172
0
  case XOR32mi_EVEX:
4173
0
  case XOR32mi_ND:
4174
0
  case XOR32mi_NF:
4175
0
  case XOR32mi_NF_ND:
4176
0
  case XOR32mr:
4177
0
  case XOR32mr_EVEX:
4178
0
  case XOR32mr_ND:
4179
0
  case XOR32mr_NF:
4180
0
  case XOR32mr_NF_ND:
4181
0
  case XOR32ri:
4182
0
  case XOR32ri8:
4183
0
  case XOR32ri8_EVEX:
4184
0
  case XOR32ri8_ND:
4185
0
  case XOR32ri8_NF:
4186
0
  case XOR32ri8_NF_ND:
4187
0
  case XOR32ri_EVEX:
4188
0
  case XOR32ri_ND:
4189
0
  case XOR32ri_NF:
4190
0
  case XOR32ri_NF_ND:
4191
0
  case XOR32rm:
4192
0
  case XOR32rm_EVEX:
4193
0
  case XOR32rm_ND:
4194
0
  case XOR32rm_NF:
4195
0
  case XOR32rm_NF_ND:
4196
0
  case XOR32rr:
4197
0
  case XOR32rr_EVEX:
4198
0
  case XOR32rr_EVEX_REV:
4199
0
  case XOR32rr_ND:
4200
0
  case XOR32rr_ND_REV:
4201
0
  case XOR32rr_NF:
4202
0
  case XOR32rr_NF_ND:
4203
0
  case XOR32rr_NF_ND_REV:
4204
0
  case XOR32rr_NF_REV:
4205
0
  case XOR32rr_REV:
4206
0
  case XOR64i32:
4207
0
  case XOR64mi32:
4208
0
  case XOR64mi32_EVEX:
4209
0
  case XOR64mi32_ND:
4210
0
  case XOR64mi32_NF:
4211
0
  case XOR64mi32_NF_ND:
4212
0
  case XOR64mi8:
4213
0
  case XOR64mi8_EVEX:
4214
0
  case XOR64mi8_ND:
4215
0
  case XOR64mi8_NF:
4216
0
  case XOR64mi8_NF_ND:
4217
0
  case XOR64mr:
4218
0
  case XOR64mr_EVEX:
4219
0
  case XOR64mr_ND:
4220
0
  case XOR64mr_NF:
4221
0
  case XOR64mr_NF_ND:
4222
0
  case XOR64ri32:
4223
0
  case XOR64ri32_EVEX:
4224
0
  case XOR64ri32_ND:
4225
0
  case XOR64ri32_NF:
4226
0
  case XOR64ri32_NF_ND:
4227
0
  case XOR64ri8:
4228
0
  case XOR64ri8_EVEX:
4229
0
  case XOR64ri8_ND:
4230
0
  case XOR64ri8_NF:
4231
0
  case XOR64ri8_NF_ND:
4232
0
  case XOR64rm:
4233
0
  case XOR64rm_EVEX:
4234
0
  case XOR64rm_ND:
4235
0
  case XOR64rm_NF:
4236
0
  case XOR64rm_NF_ND:
4237
0
  case XOR64rr:
4238
0
  case XOR64rr_EVEX:
4239
0
  case XOR64rr_EVEX_REV:
4240
0
  case XOR64rr_ND:
4241
0
  case XOR64rr_ND_REV:
4242
0
  case XOR64rr_NF:
4243
0
  case XOR64rr_NF_ND:
4244
0
  case XOR64rr_NF_ND_REV:
4245
0
  case XOR64rr_NF_REV:
4246
0
  case XOR64rr_REV:
4247
0
  case XOR8i8:
4248
0
  case XOR8mi:
4249
0
  case XOR8mi8:
4250
0
  case XOR8mi_EVEX:
4251
0
  case XOR8mi_ND:
4252
0
  case XOR8mi_NF:
4253
0
  case XOR8mi_NF_ND:
4254
0
  case XOR8mr:
4255
0
  case XOR8mr_EVEX:
4256
0
  case XOR8mr_ND:
4257
0
  case XOR8mr_NF:
4258
0
  case XOR8mr_NF_ND:
4259
0
  case XOR8ri:
4260
0
  case XOR8ri8:
4261
0
  case XOR8ri_EVEX:
4262
0
  case XOR8ri_ND:
4263
0
  case XOR8ri_NF:
4264
0
  case XOR8ri_NF_ND:
4265
0
  case XOR8rm:
4266
0
  case XOR8rm_EVEX:
4267
0
  case XOR8rm_ND:
4268
0
  case XOR8rm_NF:
4269
0
  case XOR8rm_NF_ND:
4270
0
  case XOR8rr:
4271
0
  case XOR8rr_EVEX:
4272
0
  case XOR8rr_EVEX_REV:
4273
0
  case XOR8rr_ND:
4274
0
  case XOR8rr_ND_REV:
4275
0
  case XOR8rr_NF:
4276
0
  case XOR8rr_NF_ND:
4277
0
  case XOR8rr_NF_ND_REV:
4278
0
  case XOR8rr_NF_REV:
4279
0
  case XOR8rr_REV:
4280
0
    return true;
4281
0
  }
4282
0
  return false;
4283
0
}
4284
4285
0
bool isPSIGNB(unsigned Opcode) {
4286
0
  switch (Opcode) {
4287
0
  case MMX_PSIGNBrm:
4288
0
  case MMX_PSIGNBrr:
4289
0
  case PSIGNBrm:
4290
0
  case PSIGNBrr:
4291
0
    return true;
4292
0
  }
4293
0
  return false;
4294
0
}
4295
4296
0
bool isVPHADDSW(unsigned Opcode) {
4297
0
  switch (Opcode) {
4298
0
  case VPHADDSWYrm:
4299
0
  case VPHADDSWYrr:
4300
0
  case VPHADDSWrm:
4301
0
  case VPHADDSWrr:
4302
0
    return true;
4303
0
  }
4304
0
  return false;
4305
0
}
4306
4307
0
bool isFADDP(unsigned Opcode) {
4308
0
  return Opcode == ADD_FPrST0;
4309
0
}
4310
4311
0
bool isNEG(unsigned Opcode) {
4312
0
  switch (Opcode) {
4313
0
  case NEG16m:
4314
0
  case NEG16m_EVEX:
4315
0
  case NEG16m_ND:
4316
0
  case NEG16m_NF:
4317
0
  case NEG16m_NF_ND:
4318
0
  case NEG16r:
4319
0
  case NEG16r_EVEX:
4320
0
  case NEG16r_ND:
4321
0
  case NEG16r_NF:
4322
0
  case NEG16r_NF_ND:
4323
0
  case NEG32m:
4324
0
  case NEG32m_EVEX:
4325
0
  case NEG32m_ND:
4326
0
  case NEG32m_NF:
4327
0
  case NEG32m_NF_ND:
4328
0
  case NEG32r:
4329
0
  case NEG32r_EVEX:
4330
0
  case NEG32r_ND:
4331
0
  case NEG32r_NF:
4332
0
  case NEG32r_NF_ND:
4333
0
  case NEG64m:
4334
0
  case NEG64m_EVEX:
4335
0
  case NEG64m_ND:
4336
0
  case NEG64m_NF:
4337
0
  case NEG64m_NF_ND:
4338
0
  case NEG64r:
4339
0
  case NEG64r_EVEX:
4340
0
  case NEG64r_ND:
4341
0
  case NEG64r_NF:
4342
0
  case NEG64r_NF_ND:
4343
0
  case NEG8m:
4344
0
  case NEG8m_EVEX:
4345
0
  case NEG8m_ND:
4346
0
  case NEG8m_NF:
4347
0
  case NEG8m_NF_ND:
4348
0
  case NEG8r:
4349
0
  case NEG8r_EVEX:
4350
0
  case NEG8r_ND:
4351
0
  case NEG8r_NF:
4352
0
  case NEG8r_NF_ND:
4353
0
    return true;
4354
0
  }
4355
0
  return false;
4356
0
}
4357
4358
0
bool isFLDLG2(unsigned Opcode) {
4359
0
  return Opcode == FLDLG2;
4360
0
}
4361
4362
0
bool isFNOP(unsigned Opcode) {
4363
0
  return Opcode == FNOP;
4364
0
}
4365
4366
0
bool isVMINSS(unsigned Opcode) {
4367
0
  switch (Opcode) {
4368
0
  case VMINSSZrm_Int:
4369
0
  case VMINSSZrm_Intk:
4370
0
  case VMINSSZrm_Intkz:
4371
0
  case VMINSSZrr_Int:
4372
0
  case VMINSSZrr_Intk:
4373
0
  case VMINSSZrr_Intkz:
4374
0
  case VMINSSZrrb_Int:
4375
0
  case VMINSSZrrb_Intk:
4376
0
  case VMINSSZrrb_Intkz:
4377
0
  case VMINSSrm_Int:
4378
0
  case VMINSSrr_Int:
4379
0
    return true;
4380
0
  }
4381
0
  return false;
4382
0
}
4383
4384
0
bool isPCMPISTRM(unsigned Opcode) {
4385
0
  switch (Opcode) {
4386
0
  case PCMPISTRMrm:
4387
0
  case PCMPISTRMrr:
4388
0
    return true;
4389
0
  }
4390
0
  return false;
4391
0
}
4392
4393
0
bool isVFMADD132SS(unsigned Opcode) {
4394
0
  switch (Opcode) {
4395
0
  case VFMADD132SSZm_Int:
4396
0
  case VFMADD132SSZm_Intk:
4397
0
  case VFMADD132SSZm_Intkz:
4398
0
  case VFMADD132SSZr_Int:
4399
0
  case VFMADD132SSZr_Intk:
4400
0
  case VFMADD132SSZr_Intkz:
4401
0
  case VFMADD132SSZrb_Int:
4402
0
  case VFMADD132SSZrb_Intk:
4403
0
  case VFMADD132SSZrb_Intkz:
4404
0
  case VFMADD132SSm_Int:
4405
0
  case VFMADD132SSr_Int:
4406
0
    return true;
4407
0
  }
4408
0
  return false;
4409
0
}
4410
4411
0
bool isFDIVRP(unsigned Opcode) {
4412
0
  return Opcode == DIVR_FPrST0;
4413
0
}
4414
4415
0
bool isPUSHAL(unsigned Opcode) {
4416
0
  return Opcode == PUSHA32;
4417
0
}
4418
4419
0
bool isVPMACSDQL(unsigned Opcode) {
4420
0
  switch (Opcode) {
4421
0
  case VPMACSDQLrm:
4422
0
  case VPMACSDQLrr:
4423
0
    return true;
4424
0
  }
4425
0
  return false;
4426
0
}
4427
4428
0
bool isSUBSD(unsigned Opcode) {
4429
0
  switch (Opcode) {
4430
0
  case SUBSDrm_Int:
4431
0
  case SUBSDrr_Int:
4432
0
    return true;
4433
0
  }
4434
0
  return false;
4435
0
}
4436
4437
0
bool isVPBLENDMQ(unsigned Opcode) {
4438
0
  switch (Opcode) {
4439
0
  case VPBLENDMQZ128rm:
4440
0
  case VPBLENDMQZ128rmb:
4441
0
  case VPBLENDMQZ128rmbk:
4442
0
  case VPBLENDMQZ128rmbkz:
4443
0
  case VPBLENDMQZ128rmk:
4444
0
  case VPBLENDMQZ128rmkz:
4445
0
  case VPBLENDMQZ128rr:
4446
0
  case VPBLENDMQZ128rrk:
4447
0
  case VPBLENDMQZ128rrkz:
4448
0
  case VPBLENDMQZ256rm:
4449
0
  case VPBLENDMQZ256rmb:
4450
0
  case VPBLENDMQZ256rmbk:
4451
0
  case VPBLENDMQZ256rmbkz:
4452
0
  case VPBLENDMQZ256rmk:
4453
0
  case VPBLENDMQZ256rmkz:
4454
0
  case VPBLENDMQZ256rr:
4455
0
  case VPBLENDMQZ256rrk:
4456
0
  case VPBLENDMQZ256rrkz:
4457
0
  case VPBLENDMQZrm:
4458
0
  case VPBLENDMQZrmb:
4459
0
  case VPBLENDMQZrmbk:
4460
0
  case VPBLENDMQZrmbkz:
4461
0
  case VPBLENDMQZrmk:
4462
0
  case VPBLENDMQZrmkz:
4463
0
  case VPBLENDMQZrr:
4464
0
  case VPBLENDMQZrrk:
4465
0
  case VPBLENDMQZrrkz:
4466
0
    return true;
4467
0
  }
4468
0
  return false;
4469
0
}
4470
4471
0
bool isVGATHERDPS(unsigned Opcode) {
4472
0
  switch (Opcode) {
4473
0
  case VGATHERDPSYrm:
4474
0
  case VGATHERDPSZ128rm:
4475
0
  case VGATHERDPSZ256rm:
4476
0
  case VGATHERDPSZrm:
4477
0
  case VGATHERDPSrm:
4478
0
    return true;
4479
0
  }
4480
0
  return false;
4481
0
}
4482
4483
0
bool isSYSRET(unsigned Opcode) {
4484
0
  return Opcode == SYSRET;
4485
0
}
4486
4487
0
bool isVPADDB(unsigned Opcode) {
4488
0
  switch (Opcode) {
4489
0
  case VPADDBYrm:
4490
0
  case VPADDBYrr:
4491
0
  case VPADDBZ128rm:
4492
0
  case VPADDBZ128rmk:
4493
0
  case VPADDBZ128rmkz:
4494
0
  case VPADDBZ128rr:
4495
0
  case VPADDBZ128rrk:
4496
0
  case VPADDBZ128rrkz:
4497
0
  case VPADDBZ256rm:
4498
0
  case VPADDBZ256rmk:
4499
0
  case VPADDBZ256rmkz:
4500
0
  case VPADDBZ256rr:
4501
0
  case VPADDBZ256rrk:
4502
0
  case VPADDBZ256rrkz:
4503
0
  case VPADDBZrm:
4504
0
  case VPADDBZrmk:
4505
0
  case VPADDBZrmkz:
4506
0
  case VPADDBZrr:
4507
0
  case VPADDBZrrk:
4508
0
  case VPADDBZrrkz:
4509
0
  case VPADDBrm:
4510
0
  case VPADDBrr:
4511
0
    return true;
4512
0
  }
4513
0
  return false;
4514
0
}
4515
4516
0
bool isXEND(unsigned Opcode) {
4517
0
  return Opcode == XEND;
4518
0
}
4519
4520
0
bool isWRSSD(unsigned Opcode) {
4521
0
  switch (Opcode) {
4522
0
  case WRSSD:
4523
0
  case WRSSD_EVEX:
4524
0
    return true;
4525
0
  }
4526
0
  return false;
4527
0
}
4528
4529
0
bool isVCVTDQ2PH(unsigned Opcode) {
4530
0
  switch (Opcode) {
4531
0
  case VCVTDQ2PHZ128rm:
4532
0
  case VCVTDQ2PHZ128rmb:
4533
0
  case VCVTDQ2PHZ128rmbk:
4534
0
  case VCVTDQ2PHZ128rmbkz:
4535
0
  case VCVTDQ2PHZ128rmk:
4536
0
  case VCVTDQ2PHZ128rmkz:
4537
0
  case VCVTDQ2PHZ128rr:
4538
0
  case VCVTDQ2PHZ128rrk:
4539
0
  case VCVTDQ2PHZ128rrkz:
4540
0
  case VCVTDQ2PHZ256rm:
4541
0
  case VCVTDQ2PHZ256rmb:
4542
0
  case VCVTDQ2PHZ256rmbk:
4543
0
  case VCVTDQ2PHZ256rmbkz:
4544
0
  case VCVTDQ2PHZ256rmk:
4545
0
  case VCVTDQ2PHZ256rmkz:
4546
0
  case VCVTDQ2PHZ256rr:
4547
0
  case VCVTDQ2PHZ256rrk:
4548
0
  case VCVTDQ2PHZ256rrkz:
4549
0
  case VCVTDQ2PHZrm:
4550
0
  case VCVTDQ2PHZrmb:
4551
0
  case VCVTDQ2PHZrmbk:
4552
0
  case VCVTDQ2PHZrmbkz:
4553
0
  case VCVTDQ2PHZrmk:
4554
0
  case VCVTDQ2PHZrmkz:
4555
0
  case VCVTDQ2PHZrr:
4556
0
  case VCVTDQ2PHZrrb:
4557
0
  case VCVTDQ2PHZrrbk:
4558
0
  case VCVTDQ2PHZrrbkz:
4559
0
  case VCVTDQ2PHZrrk:
4560
0
  case VCVTDQ2PHZrrkz:
4561
0
    return true;
4562
0
  }
4563
0
  return false;
4564
0
}
4565
4566
0
bool isCVTPD2PS(unsigned Opcode) {
4567
0
  switch (Opcode) {
4568
0
  case CVTPD2PSrm:
4569
0
  case CVTPD2PSrr:
4570
0
    return true;
4571
0
  }
4572
0
  return false;
4573
0
}
4574
4575
0
bool isMAXPD(unsigned Opcode) {
4576
0
  switch (Opcode) {
4577
0
  case MAXPDrm:
4578
0
  case MAXPDrr:
4579
0
    return true;
4580
0
  }
4581
0
  return false;
4582
0
}
4583
4584
0
bool isRCPSS(unsigned Opcode) {
4585
0
  switch (Opcode) {
4586
0
  case RCPSSm_Int:
4587
0
  case RCPSSr_Int:
4588
0
    return true;
4589
0
  }
4590
0
  return false;
4591
0
}
4592
4593
0
bool isVMOVAPD(unsigned Opcode) {
4594
0
  switch (Opcode) {
4595
0
  case VMOVAPDYmr:
4596
0
  case VMOVAPDYrm:
4597
0
  case VMOVAPDYrr:
4598
0
  case VMOVAPDYrr_REV:
4599
0
  case VMOVAPDZ128mr:
4600
0
  case VMOVAPDZ128mrk:
4601
0
  case VMOVAPDZ128rm:
4602
0
  case VMOVAPDZ128rmk:
4603
0
  case VMOVAPDZ128rmkz:
4604
0
  case VMOVAPDZ128rr:
4605
0
  case VMOVAPDZ128rr_REV:
4606
0
  case VMOVAPDZ128rrk:
4607
0
  case VMOVAPDZ128rrk_REV:
4608
0
  case VMOVAPDZ128rrkz:
4609
0
  case VMOVAPDZ128rrkz_REV:
4610
0
  case VMOVAPDZ256mr:
4611
0
  case VMOVAPDZ256mrk:
4612
0
  case VMOVAPDZ256rm:
4613
0
  case VMOVAPDZ256rmk:
4614
0
  case VMOVAPDZ256rmkz:
4615
0
  case VMOVAPDZ256rr:
4616
0
  case VMOVAPDZ256rr_REV:
4617
0
  case VMOVAPDZ256rrk:
4618
0
  case VMOVAPDZ256rrk_REV:
4619
0
  case VMOVAPDZ256rrkz:
4620
0
  case VMOVAPDZ256rrkz_REV:
4621
0
  case VMOVAPDZmr:
4622
0
  case VMOVAPDZmrk:
4623
0
  case VMOVAPDZrm:
4624
0
  case VMOVAPDZrmk:
4625
0
  case VMOVAPDZrmkz:
4626
0
  case VMOVAPDZrr:
4627
0
  case VMOVAPDZrr_REV:
4628
0
  case VMOVAPDZrrk:
4629
0
  case VMOVAPDZrrk_REV:
4630
0
  case VMOVAPDZrrkz:
4631
0
  case VMOVAPDZrrkz_REV:
4632
0
  case VMOVAPDmr:
4633
0
  case VMOVAPDrm:
4634
0
  case VMOVAPDrr:
4635
0
  case VMOVAPDrr_REV:
4636
0
    return true;
4637
0
  }
4638
0
  return false;
4639
0
}
4640
4641
0
bool isVPSUBSB(unsigned Opcode) {
4642
0
  switch (Opcode) {
4643
0
  case VPSUBSBYrm:
4644
0
  case VPSUBSBYrr:
4645
0
  case VPSUBSBZ128rm:
4646
0
  case VPSUBSBZ128rmk:
4647
0
  case VPSUBSBZ128rmkz:
4648
0
  case VPSUBSBZ128rr:
4649
0
  case VPSUBSBZ128rrk:
4650
0
  case VPSUBSBZ128rrkz:
4651
0
  case VPSUBSBZ256rm:
4652
0
  case VPSUBSBZ256rmk:
4653
0
  case VPSUBSBZ256rmkz:
4654
0
  case VPSUBSBZ256rr:
4655
0
  case VPSUBSBZ256rrk:
4656
0
  case VPSUBSBZ256rrkz:
4657
0
  case VPSUBSBZrm:
4658
0
  case VPSUBSBZrmk:
4659
0
  case VPSUBSBZrmkz:
4660
0
  case VPSUBSBZrr:
4661
0
  case VPSUBSBZrrk:
4662
0
  case VPSUBSBZrrkz:
4663
0
  case VPSUBSBrm:
4664
0
  case VPSUBSBrr:
4665
0
    return true;
4666
0
  }
4667
0
  return false;
4668
0
}
4669
4670
0
bool isRDTSC(unsigned Opcode) {
4671
0
  return Opcode == RDTSC;
4672
0
}
4673
4674
0
bool isVPMADCSSWD(unsigned Opcode) {
4675
0
  switch (Opcode) {
4676
0
  case VPMADCSSWDrm:
4677
0
  case VPMADCSSWDrr:
4678
0
    return true;
4679
0
  }
4680
0
  return false;
4681
0
}
4682
4683
0
bool isVFNMADD213PH(unsigned Opcode) {
4684
0
  switch (Opcode) {
4685
0
  case VFNMADD213PHZ128m:
4686
0
  case VFNMADD213PHZ128mb:
4687
0
  case VFNMADD213PHZ128mbk:
4688
0
  case VFNMADD213PHZ128mbkz:
4689
0
  case VFNMADD213PHZ128mk:
4690
0
  case VFNMADD213PHZ128mkz:
4691
0
  case VFNMADD213PHZ128r:
4692
0
  case VFNMADD213PHZ128rk:
4693
0
  case VFNMADD213PHZ128rkz:
4694
0
  case VFNMADD213PHZ256m:
4695
0
  case VFNMADD213PHZ256mb:
4696
0
  case VFNMADD213PHZ256mbk:
4697
0
  case VFNMADD213PHZ256mbkz:
4698
0
  case VFNMADD213PHZ256mk:
4699
0
  case VFNMADD213PHZ256mkz:
4700
0
  case VFNMADD213PHZ256r:
4701
0
  case VFNMADD213PHZ256rk:
4702
0
  case VFNMADD213PHZ256rkz:
4703
0
  case VFNMADD213PHZm:
4704
0
  case VFNMADD213PHZmb:
4705
0
  case VFNMADD213PHZmbk:
4706
0
  case VFNMADD213PHZmbkz:
4707
0
  case VFNMADD213PHZmk:
4708
0
  case VFNMADD213PHZmkz:
4709
0
  case VFNMADD213PHZr:
4710
0
  case VFNMADD213PHZrb:
4711
0
  case VFNMADD213PHZrbk:
4712
0
  case VFNMADD213PHZrbkz:
4713
0
  case VFNMADD213PHZrk:
4714
0
  case VFNMADD213PHZrkz:
4715
0
    return true;
4716
0
  }
4717
0
  return false;
4718
0
}
4719
4720
0
bool isVGF2P8AFFINEQB(unsigned Opcode) {
4721
0
  switch (Opcode) {
4722
0
  case VGF2P8AFFINEQBYrmi:
4723
0
  case VGF2P8AFFINEQBYrri:
4724
0
  case VGF2P8AFFINEQBZ128rmbi:
4725
0
  case VGF2P8AFFINEQBZ128rmbik:
4726
0
  case VGF2P8AFFINEQBZ128rmbikz:
4727
0
  case VGF2P8AFFINEQBZ128rmi:
4728
0
  case VGF2P8AFFINEQBZ128rmik:
4729
0
  case VGF2P8AFFINEQBZ128rmikz:
4730
0
  case VGF2P8AFFINEQBZ128rri:
4731
0
  case VGF2P8AFFINEQBZ128rrik:
4732
0
  case VGF2P8AFFINEQBZ128rrikz:
4733
0
  case VGF2P8AFFINEQBZ256rmbi:
4734
0
  case VGF2P8AFFINEQBZ256rmbik:
4735
0
  case VGF2P8AFFINEQBZ256rmbikz:
4736
0
  case VGF2P8AFFINEQBZ256rmi:
4737
0
  case VGF2P8AFFINEQBZ256rmik:
4738
0
  case VGF2P8AFFINEQBZ256rmikz:
4739
0
  case VGF2P8AFFINEQBZ256rri:
4740
0
  case VGF2P8AFFINEQBZ256rrik:
4741
0
  case VGF2P8AFFINEQBZ256rrikz:
4742
0
  case VGF2P8AFFINEQBZrmbi:
4743
0
  case VGF2P8AFFINEQBZrmbik:
4744
0
  case VGF2P8AFFINEQBZrmbikz:
4745
0
  case VGF2P8AFFINEQBZrmi:
4746
0
  case VGF2P8AFFINEQBZrmik:
4747
0
  case VGF2P8AFFINEQBZrmikz:
4748
0
  case VGF2P8AFFINEQBZrri:
4749
0
  case VGF2P8AFFINEQBZrrik:
4750
0
  case VGF2P8AFFINEQBZrrikz:
4751
0
  case VGF2P8AFFINEQBrmi:
4752
0
  case VGF2P8AFFINEQBrri:
4753
0
    return true;
4754
0
  }
4755
0
  return false;
4756
0
}
4757
4758
0
bool isPMOVZXWD(unsigned Opcode) {
4759
0
  switch (Opcode) {
4760
0
  case PMOVZXWDrm:
4761
0
  case PMOVZXWDrr:
4762
0
    return true;
4763
0
  }
4764
0
  return false;
4765
0
}
4766
4767
0
bool isPMINUD(unsigned Opcode) {
4768
0
  switch (Opcode) {
4769
0
  case PMINUDrm:
4770
0
  case PMINUDrr:
4771
0
    return true;
4772
0
  }
4773
0
  return false;
4774
0
}
4775
4776
0
bool isVCVTPH2UW(unsigned Opcode) {
4777
0
  switch (Opcode) {
4778
0
  case VCVTPH2UWZ128rm:
4779
0
  case VCVTPH2UWZ128rmb:
4780
0
  case VCVTPH2UWZ128rmbk:
4781
0
  case VCVTPH2UWZ128rmbkz:
4782
0
  case VCVTPH2UWZ128rmk:
4783
0
  case VCVTPH2UWZ128rmkz:
4784
0
  case VCVTPH2UWZ128rr:
4785
0
  case VCVTPH2UWZ128rrk:
4786
0
  case VCVTPH2UWZ128rrkz:
4787
0
  case VCVTPH2UWZ256rm:
4788
0
  case VCVTPH2UWZ256rmb:
4789
0
  case VCVTPH2UWZ256rmbk:
4790
0
  case VCVTPH2UWZ256rmbkz:
4791
0
  case VCVTPH2UWZ256rmk:
4792
0
  case VCVTPH2UWZ256rmkz:
4793
0
  case VCVTPH2UWZ256rr:
4794
0
  case VCVTPH2UWZ256rrk:
4795
0
  case VCVTPH2UWZ256rrkz:
4796
0
  case VCVTPH2UWZrm:
4797
0
  case VCVTPH2UWZrmb:
4798
0
  case VCVTPH2UWZrmbk:
4799
0
  case VCVTPH2UWZrmbkz:
4800
0
  case VCVTPH2UWZrmk:
4801
0
  case VCVTPH2UWZrmkz:
4802
0
  case VCVTPH2UWZrr:
4803
0
  case VCVTPH2UWZrrb:
4804
0
  case VCVTPH2UWZrrbk:
4805
0
  case VCVTPH2UWZrrbkz:
4806
0
  case VCVTPH2UWZrrk:
4807
0
  case VCVTPH2UWZrrkz:
4808
0
    return true;
4809
0
  }
4810
0
  return false;
4811
0
}
4812
4813
0
bool isPADDSW(unsigned Opcode) {
4814
0
  switch (Opcode) {
4815
0
  case MMX_PADDSWrm:
4816
0
  case MMX_PADDSWrr:
4817
0
  case PADDSWrm:
4818
0
  case PADDSWrr:
4819
0
    return true;
4820
0
  }
4821
0
  return false;
4822
0
}
4823
4824
0
bool isXSUSLDTRK(unsigned Opcode) {
4825
0
  return Opcode == XSUSLDTRK;
4826
0
}
4827
4828
0
bool isLFENCE(unsigned Opcode) {
4829
0
  return Opcode == LFENCE;
4830
0
}
4831
4832
0
bool isCRC32(unsigned Opcode) {
4833
0
  switch (Opcode) {
4834
0
  case CRC32r32m16:
4835
0
  case CRC32r32m16_EVEX:
4836
0
  case CRC32r32m32:
4837
0
  case CRC32r32m32_EVEX:
4838
0
  case CRC32r32m8:
4839
0
  case CRC32r32m8_EVEX:
4840
0
  case CRC32r32r16:
4841
0
  case CRC32r32r16_EVEX:
4842
0
  case CRC32r32r32:
4843
0
  case CRC32r32r32_EVEX:
4844
0
  case CRC32r32r8:
4845
0
  case CRC32r32r8_EVEX:
4846
0
  case CRC32r64m64:
4847
0
  case CRC32r64m64_EVEX:
4848
0
  case CRC32r64m8:
4849
0
  case CRC32r64m8_EVEX:
4850
0
  case CRC32r64r64:
4851
0
  case CRC32r64r64_EVEX:
4852
0
  case CRC32r64r8:
4853
0
  case CRC32r64r8_EVEX:
4854
0
    return true;
4855
0
  }
4856
0
  return false;
4857
0
}
4858
4859
0
bool isAESENCWIDE256KL(unsigned Opcode) {
4860
0
  return Opcode == AESENCWIDE256KL;
4861
0
}
4862
4863
0
bool isMOVAPD(unsigned Opcode) {
4864
0
  switch (Opcode) {
4865
0
  case MOVAPDmr:
4866
0
  case MOVAPDrm:
4867
0
  case MOVAPDrr:
4868
0
  case MOVAPDrr_REV:
4869
0
    return true;
4870
0
  }
4871
0
  return false;
4872
0
}
4873
4874
0
bool isVFMADD213PS(unsigned Opcode) {
4875
0
  switch (Opcode) {
4876
0
  case VFMADD213PSYm:
4877
0
  case VFMADD213PSYr:
4878
0
  case VFMADD213PSZ128m:
4879
0
  case VFMADD213PSZ128mb:
4880
0
  case VFMADD213PSZ128mbk:
4881
0
  case VFMADD213PSZ128mbkz:
4882
0
  case VFMADD213PSZ128mk:
4883
0
  case VFMADD213PSZ128mkz:
4884
0
  case VFMADD213PSZ128r:
4885
0
  case VFMADD213PSZ128rk:
4886
0
  case VFMADD213PSZ128rkz:
4887
0
  case VFMADD213PSZ256m:
4888
0
  case VFMADD213PSZ256mb:
4889
0
  case VFMADD213PSZ256mbk:
4890
0
  case VFMADD213PSZ256mbkz:
4891
0
  case VFMADD213PSZ256mk:
4892
0
  case VFMADD213PSZ256mkz:
4893
0
  case VFMADD213PSZ256r:
4894
0
  case VFMADD213PSZ256rk:
4895
0
  case VFMADD213PSZ256rkz:
4896
0
  case VFMADD213PSZm:
4897
0
  case VFMADD213PSZmb:
4898
0
  case VFMADD213PSZmbk:
4899
0
  case VFMADD213PSZmbkz:
4900
0
  case VFMADD213PSZmk:
4901
0
  case VFMADD213PSZmkz:
4902
0
  case VFMADD213PSZr:
4903
0
  case VFMADD213PSZrb:
4904
0
  case VFMADD213PSZrbk:
4905
0
  case VFMADD213PSZrbkz:
4906
0
  case VFMADD213PSZrk:
4907
0
  case VFMADD213PSZrkz:
4908
0
  case VFMADD213PSm:
4909
0
  case VFMADD213PSr:
4910
0
    return true;
4911
0
  }
4912
0
  return false;
4913
0
}
4914
4915
0
bool isVPDPWUUDS(unsigned Opcode) {
4916
0
  switch (Opcode) {
4917
0
  case VPDPWUUDSYrm:
4918
0
  case VPDPWUUDSYrr:
4919
0
  case VPDPWUUDSrm:
4920
0
  case VPDPWUUDSrr:
4921
0
    return true;
4922
0
  }
4923
0
  return false;
4924
0
}
4925
4926
0
bool isMOVSLDUP(unsigned Opcode) {
4927
0
  switch (Opcode) {
4928
0
  case MOVSLDUPrm:
4929
0
  case MOVSLDUPrr:
4930
0
    return true;
4931
0
  }
4932
0
  return false;
4933
0
}
4934
4935
0
bool isCLDEMOTE(unsigned Opcode) {
4936
0
  return Opcode == CLDEMOTE;
4937
0
}
4938
4939
0
bool isVFNMADD231PS(unsigned Opcode) {
4940
0
  switch (Opcode) {
4941
0
  case VFNMADD231PSYm:
4942
0
  case VFNMADD231PSYr:
4943
0
  case VFNMADD231PSZ128m:
4944
0
  case VFNMADD231PSZ128mb:
4945
0
  case VFNMADD231PSZ128mbk:
4946
0
  case VFNMADD231PSZ128mbkz:
4947
0
  case VFNMADD231PSZ128mk:
4948
0
  case VFNMADD231PSZ128mkz:
4949
0
  case VFNMADD231PSZ128r:
4950
0
  case VFNMADD231PSZ128rk:
4951
0
  case VFNMADD231PSZ128rkz:
4952
0
  case VFNMADD231PSZ256m:
4953
0
  case VFNMADD231PSZ256mb:
4954
0
  case VFNMADD231PSZ256mbk:
4955
0
  case VFNMADD231PSZ256mbkz:
4956
0
  case VFNMADD231PSZ256mk:
4957
0
  case VFNMADD231PSZ256mkz:
4958
0
  case VFNMADD231PSZ256r:
4959
0
  case VFNMADD231PSZ256rk:
4960
0
  case VFNMADD231PSZ256rkz:
4961
0
  case VFNMADD231PSZm:
4962
0
  case VFNMADD231PSZmb:
4963
0
  case VFNMADD231PSZmbk:
4964
0
  case VFNMADD231PSZmbkz:
4965
0
  case VFNMADD231PSZmk:
4966
0
  case VFNMADD231PSZmkz:
4967
0
  case VFNMADD231PSZr:
4968
0
  case VFNMADD231PSZrb:
4969
0
  case VFNMADD231PSZrbk:
4970
0
  case VFNMADD231PSZrbkz:
4971
0
  case VFNMADD231PSZrk:
4972
0
  case VFNMADD231PSZrkz:
4973
0
  case VFNMADD231PSm:
4974
0
  case VFNMADD231PSr:
4975
0
    return true;
4976
0
  }
4977
0
  return false;
4978
0
}
4979
4980
0
bool isVMOVMSKPD(unsigned Opcode) {
4981
0
  switch (Opcode) {
4982
0
  case VMOVMSKPDYrr:
4983
0
  case VMOVMSKPDrr:
4984
0
    return true;
4985
0
  }
4986
0
  return false;
4987
0
}
4988
4989
0
bool isPREFETCHT0(unsigned Opcode) {
4990
0
  return Opcode == PREFETCHT0;
4991
0
}
4992
4993
0
bool isVCVTNEOBF162PS(unsigned Opcode) {
4994
0
  switch (Opcode) {
4995
0
  case VCVTNEOBF162PSYrm:
4996
0
  case VCVTNEOBF162PSrm:
4997
0
    return true;
4998
0
  }
4999
0
  return false;
5000
0
}
5001
5002
0
bool isVPCMPUD(unsigned Opcode) {
5003
0
  switch (Opcode) {
5004
0
  case VPCMPUDZ128rmi:
5005
0
  case VPCMPUDZ128rmib:
5006
0
  case VPCMPUDZ128rmibk:
5007
0
  case VPCMPUDZ128rmik:
5008
0
  case VPCMPUDZ128rri:
5009
0
  case VPCMPUDZ128rrik:
5010
0
  case VPCMPUDZ256rmi:
5011
0
  case VPCMPUDZ256rmib:
5012
0
  case VPCMPUDZ256rmibk:
5013
0
  case VPCMPUDZ256rmik:
5014
0
  case VPCMPUDZ256rri:
5015
0
  case VPCMPUDZ256rrik:
5016
0
  case VPCMPUDZrmi:
5017
0
  case VPCMPUDZrmib:
5018
0
  case VPCMPUDZrmibk:
5019
0
  case VPCMPUDZrmik:
5020
0
  case VPCMPUDZrri:
5021
0
  case VPCMPUDZrrik:
5022
0
    return true;
5023
0
  }
5024
0
  return false;
5025
0
}
5026
5027
0
bool isVMAXSD(unsigned Opcode) {
5028
0
  switch (Opcode) {
5029
0
  case VMAXSDZrm_Int:
5030
0
  case VMAXSDZrm_Intk:
5031
0
  case VMAXSDZrm_Intkz:
5032
0
  case VMAXSDZrr_Int:
5033
0
  case VMAXSDZrr_Intk:
5034
0
  case VMAXSDZrr_Intkz:
5035
0
  case VMAXSDZrrb_Int:
5036
0
  case VMAXSDZrrb_Intk:
5037
0
  case VMAXSDZrrb_Intkz:
5038
0
  case VMAXSDrm_Int:
5039
0
  case VMAXSDrr_Int:
5040
0
    return true;
5041
0
  }
5042
0
  return false;
5043
0
}
5044
5045
0
bool isVRCP28SD(unsigned Opcode) {
5046
0
  switch (Opcode) {
5047
0
  case VRCP28SDZm:
5048
0
  case VRCP28SDZmk:
5049
0
  case VRCP28SDZmkz:
5050
0
  case VRCP28SDZr:
5051
0
  case VRCP28SDZrb:
5052
0
  case VRCP28SDZrbk:
5053
0
  case VRCP28SDZrbkz:
5054
0
  case VRCP28SDZrk:
5055
0
  case VRCP28SDZrkz:
5056
0
    return true;
5057
0
  }
5058
0
  return false;
5059
0
}
5060
5061
0
bool isVMAXPS(unsigned Opcode) {
5062
0
  switch (Opcode) {
5063
0
  case VMAXPSYrm:
5064
0
  case VMAXPSYrr:
5065
0
  case VMAXPSZ128rm:
5066
0
  case VMAXPSZ128rmb:
5067
0
  case VMAXPSZ128rmbk:
5068
0
  case VMAXPSZ128rmbkz:
5069
0
  case VMAXPSZ128rmk:
5070
0
  case VMAXPSZ128rmkz:
5071
0
  case VMAXPSZ128rr:
5072
0
  case VMAXPSZ128rrk:
5073
0
  case VMAXPSZ128rrkz:
5074
0
  case VMAXPSZ256rm:
5075
0
  case VMAXPSZ256rmb:
5076
0
  case VMAXPSZ256rmbk:
5077
0
  case VMAXPSZ256rmbkz:
5078
0
  case VMAXPSZ256rmk:
5079
0
  case VMAXPSZ256rmkz:
5080
0
  case VMAXPSZ256rr:
5081
0
  case VMAXPSZ256rrk:
5082
0
  case VMAXPSZ256rrkz:
5083
0
  case VMAXPSZrm:
5084
0
  case VMAXPSZrmb:
5085
0
  case VMAXPSZrmbk:
5086
0
  case VMAXPSZrmbkz:
5087
0
  case VMAXPSZrmk:
5088
0
  case VMAXPSZrmkz:
5089
0
  case VMAXPSZrr:
5090
0
  case VMAXPSZrrb:
5091
0
  case VMAXPSZrrbk:
5092
0
  case VMAXPSZrrbkz:
5093
0
  case VMAXPSZrrk:
5094
0
  case VMAXPSZrrkz:
5095
0
  case VMAXPSrm:
5096
0
  case VMAXPSrr:
5097
0
    return true;
5098
0
  }
5099
0
  return false;
5100
0
}
5101
5102
0
bool isVPMOVD2M(unsigned Opcode) {
5103
0
  switch (Opcode) {
5104
0
  case VPMOVD2MZ128rr:
5105
0
  case VPMOVD2MZ256rr:
5106
0
  case VPMOVD2MZrr:
5107
0
    return true;
5108
0
  }
5109
0
  return false;
5110
0
}
5111
5112
0
bool isVPMACSSWD(unsigned Opcode) {
5113
0
  switch (Opcode) {
5114
0
  case VPMACSSWDrm:
5115
0
  case VPMACSSWDrr:
5116
0
    return true;
5117
0
  }
5118
0
  return false;
5119
0
}
5120
5121
0
bool isVUCOMISD(unsigned Opcode) {
5122
0
  switch (Opcode) {
5123
0
  case VUCOMISDZrm:
5124
0
  case VUCOMISDZrr:
5125
0
  case VUCOMISDZrrb:
5126
0
  case VUCOMISDrm:
5127
0
  case VUCOMISDrr:
5128
0
    return true;
5129
0
  }
5130
0
  return false;
5131
0
}
5132
5133
0
bool isLTR(unsigned Opcode) {
5134
0
  switch (Opcode) {
5135
0
  case LTRm:
5136
0
  case LTRr:
5137
0
    return true;
5138
0
  }
5139
0
  return false;
5140
0
}
5141
5142
0
bool isVCVTUSI2SH(unsigned Opcode) {
5143
0
  switch (Opcode) {
5144
0
  case VCVTUSI2SHZrm_Int:
5145
0
  case VCVTUSI2SHZrr_Int:
5146
0
  case VCVTUSI2SHZrrb_Int:
5147
0
  case VCVTUSI642SHZrm_Int:
5148
0
  case VCVTUSI642SHZrr_Int:
5149
0
  case VCVTUSI642SHZrrb_Int:
5150
0
    return true;
5151
0
  }
5152
0
  return false;
5153
0
}
5154
5155
0
bool isVSCATTERPF1QPS(unsigned Opcode) {
5156
0
  return Opcode == VSCATTERPF1QPSm;
5157
0
}
5158
5159
0
bool isWRGSBASE(unsigned Opcode) {
5160
0
  switch (Opcode) {
5161
0
  case WRGSBASE:
5162
0
  case WRGSBASE64:
5163
0
    return true;
5164
0
  }
5165
0
  return false;
5166
0
}
5167
5168
0
bool isSTOSQ(unsigned Opcode) {
5169
0
  return Opcode == STOSQ;
5170
0
}
5171
5172
0
bool isVSQRTSD(unsigned Opcode) {
5173
0
  switch (Opcode) {
5174
0
  case VSQRTSDZm_Int:
5175
0
  case VSQRTSDZm_Intk:
5176
0
  case VSQRTSDZm_Intkz:
5177
0
  case VSQRTSDZr_Int:
5178
0
  case VSQRTSDZr_Intk:
5179
0
  case VSQRTSDZr_Intkz:
5180
0
  case VSQRTSDZrb_Int:
5181
0
  case VSQRTSDZrb_Intk:
5182
0
  case VSQRTSDZrb_Intkz:
5183
0
  case VSQRTSDm_Int:
5184
0
  case VSQRTSDr_Int:
5185
0
    return true;
5186
0
  }
5187
0
  return false;
5188
0
}
5189
5190
0
bool isVPERMIL2PD(unsigned Opcode) {
5191
0
  switch (Opcode) {
5192
0
  case VPERMIL2PDYmr:
5193
0
  case VPERMIL2PDYrm:
5194
0
  case VPERMIL2PDYrr:
5195
0
  case VPERMIL2PDYrr_REV:
5196
0
  case VPERMIL2PDmr:
5197
0
  case VPERMIL2PDrm:
5198
0
  case VPERMIL2PDrr:
5199
0
  case VPERMIL2PDrr_REV:
5200
0
    return true;
5201
0
  }
5202
0
  return false;
5203
0
}
5204
5205
0
bool isVFCMADDCSH(unsigned Opcode) {
5206
0
  switch (Opcode) {
5207
0
  case VFCMADDCSHZm:
5208
0
  case VFCMADDCSHZmk:
5209
0
  case VFCMADDCSHZmkz:
5210
0
  case VFCMADDCSHZr:
5211
0
  case VFCMADDCSHZrb:
5212
0
  case VFCMADDCSHZrbk:
5213
0
  case VFCMADDCSHZrbkz:
5214
0
  case VFCMADDCSHZrk:
5215
0
  case VFCMADDCSHZrkz:
5216
0
    return true;
5217
0
  }
5218
0
  return false;
5219
0
}
5220
5221
0
bool isVFMADDSUB213PS(unsigned Opcode) {
5222
0
  switch (Opcode) {
5223
0
  case VFMADDSUB213PSYm:
5224
0
  case VFMADDSUB213PSYr:
5225
0
  case VFMADDSUB213PSZ128m:
5226
0
  case VFMADDSUB213PSZ128mb:
5227
0
  case VFMADDSUB213PSZ128mbk:
5228
0
  case VFMADDSUB213PSZ128mbkz:
5229
0
  case VFMADDSUB213PSZ128mk:
5230
0
  case VFMADDSUB213PSZ128mkz:
5231
0
  case VFMADDSUB213PSZ128r:
5232
0
  case VFMADDSUB213PSZ128rk:
5233
0
  case VFMADDSUB213PSZ128rkz:
5234
0
  case VFMADDSUB213PSZ256m:
5235
0
  case VFMADDSUB213PSZ256mb:
5236
0
  case VFMADDSUB213PSZ256mbk:
5237
0
  case VFMADDSUB213PSZ256mbkz:
5238
0
  case VFMADDSUB213PSZ256mk:
5239
0
  case VFMADDSUB213PSZ256mkz:
5240
0
  case VFMADDSUB213PSZ256r:
5241
0
  case VFMADDSUB213PSZ256rk:
5242
0
  case VFMADDSUB213PSZ256rkz:
5243
0
  case VFMADDSUB213PSZm:
5244
0
  case VFMADDSUB213PSZmb:
5245
0
  case VFMADDSUB213PSZmbk:
5246
0
  case VFMADDSUB213PSZmbkz:
5247
0
  case VFMADDSUB213PSZmk:
5248
0
  case VFMADDSUB213PSZmkz:
5249
0
  case VFMADDSUB213PSZr:
5250
0
  case VFMADDSUB213PSZrb:
5251
0
  case VFMADDSUB213PSZrbk:
5252
0
  case VFMADDSUB213PSZrbkz:
5253
0
  case VFMADDSUB213PSZrk:
5254
0
  case VFMADDSUB213PSZrkz:
5255
0
  case VFMADDSUB213PSm:
5256
0
  case VFMADDSUB213PSr:
5257
0
    return true;
5258
0
  }
5259
0
  return false;
5260
0
}
5261
5262
0
bool isPFSUB(unsigned Opcode) {
5263
0
  switch (Opcode) {
5264
0
  case PFSUBrm:
5265
0
  case PFSUBrr:
5266
0
    return true;
5267
0
  }
5268
0
  return false;
5269
0
}
5270
5271
0
bool isVSQRTSS(unsigned Opcode) {
5272
0
  switch (Opcode) {
5273
0
  case VSQRTSSZm_Int:
5274
0
  case VSQRTSSZm_Intk:
5275
0
  case VSQRTSSZm_Intkz:
5276
0
  case VSQRTSSZr_Int:
5277
0
  case VSQRTSSZr_Intk:
5278
0
  case VSQRTSSZr_Intkz:
5279
0
  case VSQRTSSZrb_Int:
5280
0
  case VSQRTSSZrb_Intk:
5281
0
  case VSQRTSSZrb_Intkz:
5282
0
  case VSQRTSSm_Int:
5283
0
  case VSQRTSSr_Int:
5284
0
    return true;
5285
0
  }
5286
0
  return false;
5287
0
}
5288
5289
0
bool isVEXPANDPS(unsigned Opcode) {
5290
0
  switch (Opcode) {
5291
0
  case VEXPANDPSZ128rm:
5292
0
  case VEXPANDPSZ128rmk:
5293
0
  case VEXPANDPSZ128rmkz:
5294
0
  case VEXPANDPSZ128rr:
5295
0
  case VEXPANDPSZ128rrk:
5296
0
  case VEXPANDPSZ128rrkz:
5297
0
  case VEXPANDPSZ256rm:
5298
0
  case VEXPANDPSZ256rmk:
5299
0
  case VEXPANDPSZ256rmkz:
5300
0
  case VEXPANDPSZ256rr:
5301
0
  case VEXPANDPSZ256rrk:
5302
0
  case VEXPANDPSZ256rrkz:
5303
0
  case VEXPANDPSZrm:
5304
0
  case VEXPANDPSZrmk:
5305
0
  case VEXPANDPSZrmkz:
5306
0
  case VEXPANDPSZrr:
5307
0
  case VEXPANDPSZrrk:
5308
0
  case VEXPANDPSZrrkz:
5309
0
    return true;
5310
0
  }
5311
0
  return false;
5312
0
}
5313
5314
0
bool isVPCOMPRESSW(unsigned Opcode) {
5315
0
  switch (Opcode) {
5316
0
  case VPCOMPRESSWZ128mr:
5317
0
  case VPCOMPRESSWZ128mrk:
5318
0
  case VPCOMPRESSWZ128rr:
5319
0
  case VPCOMPRESSWZ128rrk:
5320
0
  case VPCOMPRESSWZ128rrkz:
5321
0
  case VPCOMPRESSWZ256mr:
5322
0
  case VPCOMPRESSWZ256mrk:
5323
0
  case VPCOMPRESSWZ256rr:
5324
0
  case VPCOMPRESSWZ256rrk:
5325
0
  case VPCOMPRESSWZ256rrkz:
5326
0
  case VPCOMPRESSWZmr:
5327
0
  case VPCOMPRESSWZmrk:
5328
0
  case VPCOMPRESSWZrr:
5329
0
  case VPCOMPRESSWZrrk:
5330
0
  case VPCOMPRESSWZrrkz:
5331
0
    return true;
5332
0
  }
5333
0
  return false;
5334
0
}
5335
5336
0
bool isPEXTRD(unsigned Opcode) {
5337
0
  switch (Opcode) {
5338
0
  case PEXTRDmr:
5339
0
  case PEXTRDrr:
5340
0
    return true;
5341
0
  }
5342
0
  return false;
5343
0
}
5344
5345
0
bool isSYSEXITQ(unsigned Opcode) {
5346
0
  return Opcode == SYSEXIT64;
5347
0
}
5348
5349
0
bool isROUNDSD(unsigned Opcode) {
5350
0
  switch (Opcode) {
5351
0
  case ROUNDSDm_Int:
5352
0
  case ROUNDSDr_Int:
5353
0
    return true;
5354
0
  }
5355
0
  return false;
5356
0
}
5357
5358
0
bool isFCOM(unsigned Opcode) {
5359
0
  switch (Opcode) {
5360
0
  case COM_FST0r:
5361
0
  case FCOM32m:
5362
0
  case FCOM64m:
5363
0
    return true;
5364
0
  }
5365
0
  return false;
5366
0
}
5367
5368
0
bool isVFNMSUBSS(unsigned Opcode) {
5369
0
  switch (Opcode) {
5370
0
  case VFNMSUBSS4mr:
5371
0
  case VFNMSUBSS4rm:
5372
0
  case VFNMSUBSS4rr:
5373
0
  case VFNMSUBSS4rr_REV:
5374
0
    return true;
5375
0
  }
5376
0
  return false;
5377
0
}
5378
5379
0
bool isKSHIFTLW(unsigned Opcode) {
5380
0
  return Opcode == KSHIFTLWri;
5381
0
}
5382
5383
0
bool isSCASD(unsigned Opcode) {
5384
0
  return Opcode == SCASL;
5385
0
}
5386
5387
0
bool isVMPTRLD(unsigned Opcode) {
5388
0
  return Opcode == VMPTRLDm;
5389
0
}
5390
5391
0
bool isVAESDECLAST(unsigned Opcode) {
5392
0
  switch (Opcode) {
5393
0
  case VAESDECLASTYrm:
5394
0
  case VAESDECLASTYrr:
5395
0
  case VAESDECLASTZ128rm:
5396
0
  case VAESDECLASTZ128rr:
5397
0
  case VAESDECLASTZ256rm:
5398
0
  case VAESDECLASTZ256rr:
5399
0
  case VAESDECLASTZrm:
5400
0
  case VAESDECLASTZrr:
5401
0
  case VAESDECLASTrm:
5402
0
  case VAESDECLASTrr:
5403
0
    return true;
5404
0
  }
5405
0
  return false;
5406
0
}
5407
5408
0
bool isVFMADDSUBPS(unsigned Opcode) {
5409
0
  switch (Opcode) {
5410
0
  case VFMADDSUBPS4Ymr:
5411
0
  case VFMADDSUBPS4Yrm:
5412
0
  case VFMADDSUBPS4Yrr:
5413
0
  case VFMADDSUBPS4Yrr_REV:
5414
0
  case VFMADDSUBPS4mr:
5415
0
  case VFMADDSUBPS4rm:
5416
0
  case VFMADDSUBPS4rr:
5417
0
  case VFMADDSUBPS4rr_REV:
5418
0
    return true;
5419
0
  }
5420
0
  return false;
5421
0
}
5422
5423
0
bool isVCVTUQQ2PS(unsigned Opcode) {
5424
0
  switch (Opcode) {
5425
0
  case VCVTUQQ2PSZ128rm:
5426
0
  case VCVTUQQ2PSZ128rmb:
5427
0
  case VCVTUQQ2PSZ128rmbk:
5428
0
  case VCVTUQQ2PSZ128rmbkz:
5429
0
  case VCVTUQQ2PSZ128rmk:
5430
0
  case VCVTUQQ2PSZ128rmkz:
5431
0
  case VCVTUQQ2PSZ128rr:
5432
0
  case VCVTUQQ2PSZ128rrk:
5433
0
  case VCVTUQQ2PSZ128rrkz:
5434
0
  case VCVTUQQ2PSZ256rm:
5435
0
  case VCVTUQQ2PSZ256rmb:
5436
0
  case VCVTUQQ2PSZ256rmbk:
5437
0
  case VCVTUQQ2PSZ256rmbkz:
5438
0
  case VCVTUQQ2PSZ256rmk:
5439
0
  case VCVTUQQ2PSZ256rmkz:
5440
0
  case VCVTUQQ2PSZ256rr:
5441
0
  case VCVTUQQ2PSZ256rrk:
5442
0
  case VCVTUQQ2PSZ256rrkz:
5443
0
  case VCVTUQQ2PSZrm:
5444
0
  case VCVTUQQ2PSZrmb:
5445
0
  case VCVTUQQ2PSZrmbk:
5446
0
  case VCVTUQQ2PSZrmbkz:
5447
0
  case VCVTUQQ2PSZrmk:
5448
0
  case VCVTUQQ2PSZrmkz:
5449
0
  case VCVTUQQ2PSZrr:
5450
0
  case VCVTUQQ2PSZrrb:
5451
0
  case VCVTUQQ2PSZrrbk:
5452
0
  case VCVTUQQ2PSZrrbkz:
5453
0
  case VCVTUQQ2PSZrrk:
5454
0
  case VCVTUQQ2PSZrrkz:
5455
0
    return true;
5456
0
  }
5457
0
  return false;
5458
0
}
5459
5460
0
bool isVPMOVUSDB(unsigned Opcode) {
5461
0
  switch (Opcode) {
5462
0
  case VPMOVUSDBZ128mr:
5463
0
  case VPMOVUSDBZ128mrk:
5464
0
  case VPMOVUSDBZ128rr:
5465
0
  case VPMOVUSDBZ128rrk:
5466
0
  case VPMOVUSDBZ128rrkz:
5467
0
  case VPMOVUSDBZ256mr:
5468
0
  case VPMOVUSDBZ256mrk:
5469
0
  case VPMOVUSDBZ256rr:
5470
0
  case VPMOVUSDBZ256rrk:
5471
0
  case VPMOVUSDBZ256rrkz:
5472
0
  case VPMOVUSDBZmr:
5473
0
  case VPMOVUSDBZmrk:
5474
0
  case VPMOVUSDBZrr:
5475
0
  case VPMOVUSDBZrrk:
5476
0
  case VPMOVUSDBZrrkz:
5477
0
    return true;
5478
0
  }
5479
0
  return false;
5480
0
}
5481
5482
0
bool isVPROTW(unsigned Opcode) {
5483
0
  switch (Opcode) {
5484
0
  case VPROTWmi:
5485
0
  case VPROTWmr:
5486
0
  case VPROTWri:
5487
0
  case VPROTWrm:
5488
0
  case VPROTWrr:
5489
0
  case VPROTWrr_REV:
5490
0
    return true;
5491
0
  }
5492
0
  return false;
5493
0
}
5494
5495
0
bool isVDPPS(unsigned Opcode) {
5496
0
  switch (Opcode) {
5497
0
  case VDPPSYrmi:
5498
0
  case VDPPSYrri:
5499
0
  case VDPPSrmi:
5500
0
  case VDPPSrri:
5501
0
    return true;
5502
0
  }
5503
0
  return false;
5504
0
}
5505
5506
0
bool isVRSQRT14PD(unsigned Opcode) {
5507
0
  switch (Opcode) {
5508
0
  case VRSQRT14PDZ128m:
5509
0
  case VRSQRT14PDZ128mb:
5510
0
  case VRSQRT14PDZ128mbk:
5511
0
  case VRSQRT14PDZ128mbkz:
5512
0
  case VRSQRT14PDZ128mk:
5513
0
  case VRSQRT14PDZ128mkz:
5514
0
  case VRSQRT14PDZ128r:
5515
0
  case VRSQRT14PDZ128rk:
5516
0
  case VRSQRT14PDZ128rkz:
5517
0
  case VRSQRT14PDZ256m:
5518
0
  case VRSQRT14PDZ256mb:
5519
0
  case VRSQRT14PDZ256mbk:
5520
0
  case VRSQRT14PDZ256mbkz:
5521
0
  case VRSQRT14PDZ256mk:
5522
0
  case VRSQRT14PDZ256mkz:
5523
0
  case VRSQRT14PDZ256r:
5524
0
  case VRSQRT14PDZ256rk:
5525
0
  case VRSQRT14PDZ256rkz:
5526
0
  case VRSQRT14PDZm:
5527
0
  case VRSQRT14PDZmb:
5528
0
  case VRSQRT14PDZmbk:
5529
0
  case VRSQRT14PDZmbkz:
5530
0
  case VRSQRT14PDZmk:
5531
0
  case VRSQRT14PDZmkz:
5532
0
  case VRSQRT14PDZr:
5533
0
  case VRSQRT14PDZrk:
5534
0
  case VRSQRT14PDZrkz:
5535
0
    return true;
5536
0
  }
5537
0
  return false;
5538
0
}
5539
5540
0
bool isVTESTPD(unsigned Opcode) {
5541
0
  switch (Opcode) {
5542
0
  case VTESTPDYrm:
5543
0
  case VTESTPDYrr:
5544
0
  case VTESTPDrm:
5545
0
  case VTESTPDrr:
5546
0
    return true;
5547
0
  }
5548
0
  return false;
5549
0
}
5550
5551
0
bool isVFNMADD231SH(unsigned Opcode) {
5552
0
  switch (Opcode) {
5553
0
  case VFNMADD231SHZm_Int:
5554
0
  case VFNMADD231SHZm_Intk:
5555
0
  case VFNMADD231SHZm_Intkz:
5556
0
  case VFNMADD231SHZr_Int:
5557
0
  case VFNMADD231SHZr_Intk:
5558
0
  case VFNMADD231SHZr_Intkz:
5559
0
  case VFNMADD231SHZrb_Int:
5560
0
  case VFNMADD231SHZrb_Intk:
5561
0
  case VFNMADD231SHZrb_Intkz:
5562
0
    return true;
5563
0
  }
5564
0
  return false;
5565
0
}
5566
5567
0
bool isENDBR64(unsigned Opcode) {
5568
0
  return Opcode == ENDBR64;
5569
0
}
5570
5571
0
bool isMULSD(unsigned Opcode) {
5572
0
  switch (Opcode) {
5573
0
  case MULSDrm_Int:
5574
0
  case MULSDrr_Int:
5575
0
    return true;
5576
0
  }
5577
0
  return false;
5578
0
}
5579
5580
0
bool isXRSTORS(unsigned Opcode) {
5581
0
  return Opcode == XRSTORS;
5582
0
}
5583
5584
0
bool isPREFETCHNTA(unsigned Opcode) {
5585
0
  return Opcode == PREFETCHNTA;
5586
0
}
5587
5588
0
bool isVPCOMD(unsigned Opcode) {
5589
0
  switch (Opcode) {
5590
0
  case VPCOMDmi:
5591
0
  case VPCOMDri:
5592
0
    return true;
5593
0
  }
5594
0
  return false;
5595
0
}
5596
5597
0
bool isVPCOMUB(unsigned Opcode) {
5598
0
  switch (Opcode) {
5599
0
  case VPCOMUBmi:
5600
0
  case VPCOMUBri:
5601
0
    return true;
5602
0
  }
5603
0
  return false;
5604
0
}
5605
5606
0
bool isVPHSUBD(unsigned Opcode) {
5607
0
  switch (Opcode) {
5608
0
  case VPHSUBDYrm:
5609
0
  case VPHSUBDYrr:
5610
0
  case VPHSUBDrm:
5611
0
  case VPHSUBDrr:
5612
0
    return true;
5613
0
  }
5614
0
  return false;
5615
0
}
5616
5617
0
bool isVBROADCASTI64X2(unsigned Opcode) {
5618
0
  switch (Opcode) {
5619
0
  case VBROADCASTI64X2Z128rm:
5620
0
  case VBROADCASTI64X2Z128rmk:
5621
0
  case VBROADCASTI64X2Z128rmkz:
5622
0
  case VBROADCASTI64X2rm:
5623
0
  case VBROADCASTI64X2rmk:
5624
0
  case VBROADCASTI64X2rmkz:
5625
0
    return true;
5626
0
  }
5627
0
  return false;
5628
0
}
5629
5630
0
bool isFPATAN(unsigned Opcode) {
5631
0
  return Opcode == FPATAN;
5632
0
}
5633
5634
0
bool isLOOPE(unsigned Opcode) {
5635
0
  return Opcode == LOOPE;
5636
0
}
5637
5638
0
bool isPCMPEQW(unsigned Opcode) {
5639
0
  switch (Opcode) {
5640
0
  case MMX_PCMPEQWrm:
5641
0
  case MMX_PCMPEQWrr:
5642
0
  case PCMPEQWrm:
5643
0
  case PCMPEQWrr:
5644
0
    return true;
5645
0
  }
5646
0
  return false;
5647
0
}
5648
5649
0
bool isVFMADDCSH(unsigned Opcode) {
5650
0
  switch (Opcode) {
5651
0
  case VFMADDCSHZm:
5652
0
  case VFMADDCSHZmk:
5653
0
  case VFMADDCSHZmkz:
5654
0
  case VFMADDCSHZr:
5655
0
  case VFMADDCSHZrb:
5656
0
  case VFMADDCSHZrbk:
5657
0
  case VFMADDCSHZrbkz:
5658
0
  case VFMADDCSHZrk:
5659
0
  case VFMADDCSHZrkz:
5660
0
    return true;
5661
0
  }
5662
0
  return false;
5663
0
}
5664
5665
0
bool isVPDPBSSD(unsigned Opcode) {
5666
0
  switch (Opcode) {
5667
0
  case VPDPBSSDYrm:
5668
0
  case VPDPBSSDYrr:
5669
0
  case VPDPBSSDrm:
5670
0
  case VPDPBSSDrr:
5671
0
    return true;
5672
0
  }
5673
0
  return false;
5674
0
}
5675
5676
0
bool isVFMSUBADD132PH(unsigned Opcode) {
5677
0
  switch (Opcode) {
5678
0
  case VFMSUBADD132PHZ128m:
5679
0
  case VFMSUBADD132PHZ128mb:
5680
0
  case VFMSUBADD132PHZ128mbk:
5681
0
  case VFMSUBADD132PHZ128mbkz:
5682
0
  case VFMSUBADD132PHZ128mk:
5683
0
  case VFMSUBADD132PHZ128mkz:
5684
0
  case VFMSUBADD132PHZ128r:
5685
0
  case VFMSUBADD132PHZ128rk:
5686
0
  case VFMSUBADD132PHZ128rkz:
5687
0
  case VFMSUBADD132PHZ256m:
5688
0
  case VFMSUBADD132PHZ256mb:
5689
0
  case VFMSUBADD132PHZ256mbk:
5690
0
  case VFMSUBADD132PHZ256mbkz:
5691
0
  case VFMSUBADD132PHZ256mk:
5692
0
  case VFMSUBADD132PHZ256mkz:
5693
0
  case VFMSUBADD132PHZ256r:
5694
0
  case VFMSUBADD132PHZ256rk:
5695
0
  case VFMSUBADD132PHZ256rkz:
5696
0
  case VFMSUBADD132PHZm:
5697
0
  case VFMSUBADD132PHZmb:
5698
0
  case VFMSUBADD132PHZmbk:
5699
0
  case VFMSUBADD132PHZmbkz:
5700
0
  case VFMSUBADD132PHZmk:
5701
0
  case VFMSUBADD132PHZmkz:
5702
0
  case VFMSUBADD132PHZr:
5703
0
  case VFMSUBADD132PHZrb:
5704
0
  case VFMSUBADD132PHZrbk:
5705
0
  case VFMSUBADD132PHZrbkz:
5706
0
  case VFMSUBADD132PHZrk:
5707
0
  case VFMSUBADD132PHZrkz:
5708
0
    return true;
5709
0
  }
5710
0
  return false;
5711
0
}
5712
5713
0
bool isVPADDSB(unsigned Opcode) {
5714
0
  switch (Opcode) {
5715
0
  case VPADDSBYrm:
5716
0
  case VPADDSBYrr:
5717
0
  case VPADDSBZ128rm:
5718
0
  case VPADDSBZ128rmk:
5719
0
  case VPADDSBZ128rmkz:
5720
0
  case VPADDSBZ128rr:
5721
0
  case VPADDSBZ128rrk:
5722
0
  case VPADDSBZ128rrkz:
5723
0
  case VPADDSBZ256rm:
5724
0
  case VPADDSBZ256rmk:
5725
0
  case VPADDSBZ256rmkz:
5726
0
  case VPADDSBZ256rr:
5727
0
  case VPADDSBZ256rrk:
5728
0
  case VPADDSBZ256rrkz:
5729
0
  case VPADDSBZrm:
5730
0
  case VPADDSBZrmk:
5731
0
  case VPADDSBZrmkz:
5732
0
  case VPADDSBZrr:
5733
0
  case VPADDSBZrrk:
5734
0
  case VPADDSBZrrkz:
5735
0
  case VPADDSBrm:
5736
0
  case VPADDSBrr:
5737
0
    return true;
5738
0
  }
5739
0
  return false;
5740
0
}
5741
5742
0
bool isKADDW(unsigned Opcode) {
5743
0
  return Opcode == KADDWrr;
5744
0
}
5745
5746
0
bool isPTEST(unsigned Opcode) {
5747
0
  switch (Opcode) {
5748
0
  case PTESTrm:
5749
0
  case PTESTrr:
5750
0
    return true;
5751
0
  }
5752
0
  return false;
5753
0
}
5754
5755
0
bool isVRSQRT28PS(unsigned Opcode) {
5756
0
  switch (Opcode) {
5757
0
  case VRSQRT28PSZm:
5758
0
  case VRSQRT28PSZmb:
5759
0
  case VRSQRT28PSZmbk:
5760
0
  case VRSQRT28PSZmbkz:
5761
0
  case VRSQRT28PSZmk:
5762
0
  case VRSQRT28PSZmkz:
5763
0
  case VRSQRT28PSZr:
5764
0
  case VRSQRT28PSZrb:
5765
0
  case VRSQRT28PSZrbk:
5766
0
  case VRSQRT28PSZrbkz:
5767
0
  case VRSQRT28PSZrk:
5768
0
  case VRSQRT28PSZrkz:
5769
0
    return true;
5770
0
  }
5771
0
  return false;
5772
0
}
5773
5774
0
bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
5775
0
  switch (Opcode) {
5776
0
  case VGF2P8AFFINEINVQBYrmi:
5777
0
  case VGF2P8AFFINEINVQBYrri:
5778
0
  case VGF2P8AFFINEINVQBZ128rmbi:
5779
0
  case VGF2P8AFFINEINVQBZ128rmbik:
5780
0
  case VGF2P8AFFINEINVQBZ128rmbikz:
5781
0
  case VGF2P8AFFINEINVQBZ128rmi:
5782
0
  case VGF2P8AFFINEINVQBZ128rmik:
5783
0
  case VGF2P8AFFINEINVQBZ128rmikz:
5784
0
  case VGF2P8AFFINEINVQBZ128rri:
5785
0
  case VGF2P8AFFINEINVQBZ128rrik:
5786
0
  case VGF2P8AFFINEINVQBZ128rrikz:
5787
0
  case VGF2P8AFFINEINVQBZ256rmbi:
5788
0
  case VGF2P8AFFINEINVQBZ256rmbik:
5789
0
  case VGF2P8AFFINEINVQBZ256rmbikz:
5790
0
  case VGF2P8AFFINEINVQBZ256rmi:
5791
0
  case VGF2P8AFFINEINVQBZ256rmik:
5792
0
  case VGF2P8AFFINEINVQBZ256rmikz:
5793
0
  case VGF2P8AFFINEINVQBZ256rri:
5794
0
  case VGF2P8AFFINEINVQBZ256rrik:
5795
0
  case VGF2P8AFFINEINVQBZ256rrikz:
5796
0
  case VGF2P8AFFINEINVQBZrmbi:
5797
0
  case VGF2P8AFFINEINVQBZrmbik:
5798
0
  case VGF2P8AFFINEINVQBZrmbikz:
5799
0
  case VGF2P8AFFINEINVQBZrmi:
5800
0
  case VGF2P8AFFINEINVQBZrmik:
5801
0
  case VGF2P8AFFINEINVQBZrmikz:
5802
0
  case VGF2P8AFFINEINVQBZrri:
5803
0
  case VGF2P8AFFINEINVQBZrrik:
5804
0
  case VGF2P8AFFINEINVQBZrrikz:
5805
0
  case VGF2P8AFFINEINVQBrmi:
5806
0
  case VGF2P8AFFINEINVQBrri:
5807
0
    return true;
5808
0
  }
5809
0
  return false;
5810
0
}
5811
5812
0
bool isSERIALIZE(unsigned Opcode) {
5813
0
  return Opcode == SERIALIZE;
5814
0
}
5815
5816
0
bool isVPHADDWQ(unsigned Opcode) {
5817
0
  switch (Opcode) {
5818
0
  case VPHADDWQrm:
5819
0
  case VPHADDWQrr:
5820
0
    return true;
5821
0
  }
5822
0
  return false;
5823
0
}
5824
5825
0
bool isVRNDSCALESH(unsigned Opcode) {
5826
0
  switch (Opcode) {
5827
0
  case VRNDSCALESHZm_Int:
5828
0
  case VRNDSCALESHZm_Intk:
5829
0
  case VRNDSCALESHZm_Intkz:
5830
0
  case VRNDSCALESHZr_Int:
5831
0
  case VRNDSCALESHZr_Intk:
5832
0
  case VRNDSCALESHZr_Intkz:
5833
0
  case VRNDSCALESHZrb_Int:
5834
0
  case VRNDSCALESHZrb_Intk:
5835
0
  case VRNDSCALESHZrb_Intkz:
5836
0
    return true;
5837
0
  }
5838
0
  return false;
5839
0
}
5840
5841
0
bool isAAA(unsigned Opcode) {
5842
0
  return Opcode == AAA;
5843
0
}
5844
5845
0
bool isWRMSRLIST(unsigned Opcode) {
5846
0
  return Opcode == WRMSRLIST;
5847
0
}
5848
5849
0
bool isXORPS(unsigned Opcode) {
5850
0
  switch (Opcode) {
5851
0
  case XORPSrm:
5852
0
  case XORPSrr:
5853
0
    return true;
5854
0
  }
5855
0
  return false;
5856
0
}
5857
5858
0
bool isVCVTPH2PSX(unsigned Opcode) {
5859
0
  switch (Opcode) {
5860
0
  case VCVTPH2PSXZ128rm:
5861
0
  case VCVTPH2PSXZ128rmb:
5862
0
  case VCVTPH2PSXZ128rmbk:
5863
0
  case VCVTPH2PSXZ128rmbkz:
5864
0
  case VCVTPH2PSXZ128rmk:
5865
0
  case VCVTPH2PSXZ128rmkz:
5866
0
  case VCVTPH2PSXZ128rr:
5867
0
  case VCVTPH2PSXZ128rrk:
5868
0
  case VCVTPH2PSXZ128rrkz:
5869
0
  case VCVTPH2PSXZ256rm:
5870
0
  case VCVTPH2PSXZ256rmb:
5871
0
  case VCVTPH2PSXZ256rmbk:
5872
0
  case VCVTPH2PSXZ256rmbkz:
5873
0
  case VCVTPH2PSXZ256rmk:
5874
0
  case VCVTPH2PSXZ256rmkz:
5875
0
  case VCVTPH2PSXZ256rr:
5876
0
  case VCVTPH2PSXZ256rrk:
5877
0
  case VCVTPH2PSXZ256rrkz:
5878
0
  case VCVTPH2PSXZrm:
5879
0
  case VCVTPH2PSXZrmb:
5880
0
  case VCVTPH2PSXZrmbk:
5881
0
  case VCVTPH2PSXZrmbkz:
5882
0
  case VCVTPH2PSXZrmk:
5883
0
  case VCVTPH2PSXZrmkz:
5884
0
  case VCVTPH2PSXZrr:
5885
0
  case VCVTPH2PSXZrrb:
5886
0
  case VCVTPH2PSXZrrbk:
5887
0
  case VCVTPH2PSXZrrbkz:
5888
0
  case VCVTPH2PSXZrrk:
5889
0
  case VCVTPH2PSXZrrkz:
5890
0
    return true;
5891
0
  }
5892
0
  return false;
5893
0
}
5894
5895
0
bool isVFMSUB231PH(unsigned Opcode) {
5896
0
  switch (Opcode) {
5897
0
  case VFMSUB231PHZ128m:
5898
0
  case VFMSUB231PHZ128mb:
5899
0
  case VFMSUB231PHZ128mbk:
5900
0
  case VFMSUB231PHZ128mbkz:
5901
0
  case VFMSUB231PHZ128mk:
5902
0
  case VFMSUB231PHZ128mkz:
5903
0
  case VFMSUB231PHZ128r:
5904
0
  case VFMSUB231PHZ128rk:
5905
0
  case VFMSUB231PHZ128rkz:
5906
0
  case VFMSUB231PHZ256m:
5907
0
  case VFMSUB231PHZ256mb:
5908
0
  case VFMSUB231PHZ256mbk:
5909
0
  case VFMSUB231PHZ256mbkz:
5910
0
  case VFMSUB231PHZ256mk:
5911
0
  case VFMSUB231PHZ256mkz:
5912
0
  case VFMSUB231PHZ256r:
5913
0
  case VFMSUB231PHZ256rk:
5914
0
  case VFMSUB231PHZ256rkz:
5915
0
  case VFMSUB231PHZm:
5916
0
  case VFMSUB231PHZmb:
5917
0
  case VFMSUB231PHZmbk:
5918
0
  case VFMSUB231PHZmbkz:
5919
0
  case VFMSUB231PHZmk:
5920
0
  case VFMSUB231PHZmkz:
5921
0
  case VFMSUB231PHZr:
5922
0
  case VFMSUB231PHZrb:
5923
0
  case VFMSUB231PHZrbk:
5924
0
  case VFMSUB231PHZrbkz:
5925
0
  case VFMSUB231PHZrk:
5926
0
  case VFMSUB231PHZrkz:
5927
0
    return true;
5928
0
  }
5929
0
  return false;
5930
0
}
5931
5932
0
bool isVGATHERQPD(unsigned Opcode) {
5933
0
  switch (Opcode) {
5934
0
  case VGATHERQPDYrm:
5935
0
  case VGATHERQPDZ128rm:
5936
0
  case VGATHERQPDZ256rm:
5937
0
  case VGATHERQPDZrm:
5938
0
  case VGATHERQPDrm:
5939
0
    return true;
5940
0
  }
5941
0
  return false;
5942
0
}
5943
5944
0
bool isKADDB(unsigned Opcode) {
5945
0
  return Opcode == KADDBrr;
5946
0
}
5947
5948
0
bool isCVTPD2PI(unsigned Opcode) {
5949
0
  switch (Opcode) {
5950
0
  case MMX_CVTPD2PIrm:
5951
0
  case MMX_CVTPD2PIrr:
5952
0
    return true;
5953
0
  }
5954
0
  return false;
5955
0
}
5956
5957
0
bool isVFNMSUB213PH(unsigned Opcode) {
5958
0
  switch (Opcode) {
5959
0
  case VFNMSUB213PHZ128m:
5960
0
  case VFNMSUB213PHZ128mb:
5961
0
  case VFNMSUB213PHZ128mbk:
5962
0
  case VFNMSUB213PHZ128mbkz:
5963
0
  case VFNMSUB213PHZ128mk:
5964
0
  case VFNMSUB213PHZ128mkz:
5965
0
  case VFNMSUB213PHZ128r:
5966
0
  case VFNMSUB213PHZ128rk:
5967
0
  case VFNMSUB213PHZ128rkz:
5968
0
  case VFNMSUB213PHZ256m:
5969
0
  case VFNMSUB213PHZ256mb:
5970
0
  case VFNMSUB213PHZ256mbk:
5971
0
  case VFNMSUB213PHZ256mbkz:
5972
0
  case VFNMSUB213PHZ256mk:
5973
0
  case VFNMSUB213PHZ256mkz:
5974
0
  case VFNMSUB213PHZ256r:
5975
0
  case VFNMSUB213PHZ256rk:
5976
0
  case VFNMSUB213PHZ256rkz:
5977
0
  case VFNMSUB213PHZm:
5978
0
  case VFNMSUB213PHZmb:
5979
0
  case VFNMSUB213PHZmbk:
5980
0
  case VFNMSUB213PHZmbkz:
5981
0
  case VFNMSUB213PHZmk:
5982
0
  case VFNMSUB213PHZmkz:
5983
0
  case VFNMSUB213PHZr:
5984
0
  case VFNMSUB213PHZrb:
5985
0
  case VFNMSUB213PHZrbk:
5986
0
  case VFNMSUB213PHZrbkz:
5987
0
  case VFNMSUB213PHZrk:
5988
0
  case VFNMSUB213PHZrkz:
5989
0
    return true;
5990
0
  }
5991
0
  return false;
5992
0
}
5993
5994
0
bool isVPCMPESTRI(unsigned Opcode) {
5995
0
  switch (Opcode) {
5996
0
  case VPCMPESTRIrm:
5997
0
  case VPCMPESTRIrr:
5998
0
    return true;
5999
0
  }
6000
0
  return false;
6001
0
}
6002
6003
0
bool isVPSHRDW(unsigned Opcode) {
6004
0
  switch (Opcode) {
6005
0
  case VPSHRDWZ128rmi:
6006
0
  case VPSHRDWZ128rmik:
6007
0
  case VPSHRDWZ128rmikz:
6008
0
  case VPSHRDWZ128rri:
6009
0
  case VPSHRDWZ128rrik:
6010
0
  case VPSHRDWZ128rrikz:
6011
0
  case VPSHRDWZ256rmi:
6012
0
  case VPSHRDWZ256rmik:
6013
0
  case VPSHRDWZ256rmikz:
6014
0
  case VPSHRDWZ256rri:
6015
0
  case VPSHRDWZ256rrik:
6016
0
  case VPSHRDWZ256rrikz:
6017
0
  case VPSHRDWZrmi:
6018
0
  case VPSHRDWZrmik:
6019
0
  case VPSHRDWZrmikz:
6020
0
  case VPSHRDWZrri:
6021
0
  case VPSHRDWZrrik:
6022
0
  case VPSHRDWZrrikz:
6023
0
    return true;
6024
0
  }
6025
0
  return false;
6026
0
}
6027
6028
0
bool isPOP2(unsigned Opcode) {
6029
0
  return Opcode == POP2;
6030
0
}
6031
6032
0
bool isRDMSRLIST(unsigned Opcode) {
6033
0
  return Opcode == RDMSRLIST;
6034
0
}
6035
6036
0
bool isVPDPBUSD(unsigned Opcode) {
6037
0
  switch (Opcode) {
6038
0
  case VPDPBUSDYrm:
6039
0
  case VPDPBUSDYrr:
6040
0
  case VPDPBUSDZ128m:
6041
0
  case VPDPBUSDZ128mb:
6042
0
  case VPDPBUSDZ128mbk:
6043
0
  case VPDPBUSDZ128mbkz:
6044
0
  case VPDPBUSDZ128mk:
6045
0
  case VPDPBUSDZ128mkz:
6046
0
  case VPDPBUSDZ128r:
6047
0
  case VPDPBUSDZ128rk:
6048
0
  case VPDPBUSDZ128rkz:
6049
0
  case VPDPBUSDZ256m:
6050
0
  case VPDPBUSDZ256mb:
6051
0
  case VPDPBUSDZ256mbk:
6052
0
  case VPDPBUSDZ256mbkz:
6053
0
  case VPDPBUSDZ256mk:
6054
0
  case VPDPBUSDZ256mkz:
6055
0
  case VPDPBUSDZ256r:
6056
0
  case VPDPBUSDZ256rk:
6057
0
  case VPDPBUSDZ256rkz:
6058
0
  case VPDPBUSDZm:
6059
0
  case VPDPBUSDZmb:
6060
0
  case VPDPBUSDZmbk:
6061
0
  case VPDPBUSDZmbkz:
6062
0
  case VPDPBUSDZmk:
6063
0
  case VPDPBUSDZmkz:
6064
0
  case VPDPBUSDZr:
6065
0
  case VPDPBUSDZrk:
6066
0
  case VPDPBUSDZrkz:
6067
0
  case VPDPBUSDrm:
6068
0
  case VPDPBUSDrr:
6069
0
    return true;
6070
0
  }
6071
0
  return false;
6072
0
}
6073
6074
0
bool isVCMPPH(unsigned Opcode) {
6075
0
  switch (Opcode) {
6076
0
  case VCMPPHZ128rmbi:
6077
0
  case VCMPPHZ128rmbik:
6078
0
  case VCMPPHZ128rmi:
6079
0
  case VCMPPHZ128rmik:
6080
0
  case VCMPPHZ128rri:
6081
0
  case VCMPPHZ128rrik:
6082
0
  case VCMPPHZ256rmbi:
6083
0
  case VCMPPHZ256rmbik:
6084
0
  case VCMPPHZ256rmi:
6085
0
  case VCMPPHZ256rmik:
6086
0
  case VCMPPHZ256rri:
6087
0
  case VCMPPHZ256rrik:
6088
0
  case VCMPPHZrmbi:
6089
0
  case VCMPPHZrmbik:
6090
0
  case VCMPPHZrmi:
6091
0
  case VCMPPHZrmik:
6092
0
  case VCMPPHZrri:
6093
0
  case VCMPPHZrrib:
6094
0
  case VCMPPHZrribk:
6095
0
  case VCMPPHZrrik:
6096
0
    return true;
6097
0
  }
6098
0
  return false;
6099
0
}
6100
6101
0
bool isVANDNPD(unsigned Opcode) {
6102
0
  switch (Opcode) {
6103
0
  case VANDNPDYrm:
6104
0
  case VANDNPDYrr:
6105
0
  case VANDNPDZ128rm:
6106
0
  case VANDNPDZ128rmb:
6107
0
  case VANDNPDZ128rmbk:
6108
0
  case VANDNPDZ128rmbkz:
6109
0
  case VANDNPDZ128rmk:
6110
0
  case VANDNPDZ128rmkz:
6111
0
  case VANDNPDZ128rr:
6112
0
  case VANDNPDZ128rrk:
6113
0
  case VANDNPDZ128rrkz:
6114
0
  case VANDNPDZ256rm:
6115
0
  case VANDNPDZ256rmb:
6116
0
  case VANDNPDZ256rmbk:
6117
0
  case VANDNPDZ256rmbkz:
6118
0
  case VANDNPDZ256rmk:
6119
0
  case VANDNPDZ256rmkz:
6120
0
  case VANDNPDZ256rr:
6121
0
  case VANDNPDZ256rrk:
6122
0
  case VANDNPDZ256rrkz:
6123
0
  case VANDNPDZrm:
6124
0
  case VANDNPDZrmb:
6125
0
  case VANDNPDZrmbk:
6126
0
  case VANDNPDZrmbkz:
6127
0
  case VANDNPDZrmk:
6128
0
  case VANDNPDZrmkz:
6129
0
  case VANDNPDZrr:
6130
0
  case VANDNPDZrrk:
6131
0
  case VANDNPDZrrkz:
6132
0
  case VANDNPDrm:
6133
0
  case VANDNPDrr:
6134
0
    return true;
6135
0
  }
6136
0
  return false;
6137
0
}
6138
6139
0
bool isSUB(unsigned Opcode) {
6140
0
  switch (Opcode) {
6141
0
  case SUB16i16:
6142
0
  case SUB16mi:
6143
0
  case SUB16mi8:
6144
0
  case SUB16mi8_EVEX:
6145
0
  case SUB16mi8_ND:
6146
0
  case SUB16mi8_NF:
6147
0
  case SUB16mi8_NF_ND:
6148
0
  case SUB16mi_EVEX:
6149
0
  case SUB16mi_ND:
6150
0
  case SUB16mi_NF:
6151
0
  case SUB16mi_NF_ND:
6152
0
  case SUB16mr:
6153
0
  case SUB16mr_EVEX:
6154
0
  case SUB16mr_ND:
6155
0
  case SUB16mr_NF:
6156
0
  case SUB16mr_NF_ND:
6157
0
  case SUB16ri:
6158
0
  case SUB16ri8:
6159
0
  case SUB16ri8_EVEX:
6160
0
  case SUB16ri8_ND:
6161
0
  case SUB16ri8_NF:
6162
0
  case SUB16ri8_NF_ND:
6163
0
  case SUB16ri_EVEX:
6164
0
  case SUB16ri_ND:
6165
0
  case SUB16ri_NF:
6166
0
  case SUB16ri_NF_ND:
6167
0
  case SUB16rm:
6168
0
  case SUB16rm_EVEX:
6169
0
  case SUB16rm_ND:
6170
0
  case SUB16rm_NF:
6171
0
  case SUB16rm_NF_ND:
6172
0
  case SUB16rr:
6173
0
  case SUB16rr_EVEX:
6174
0
  case SUB16rr_EVEX_REV:
6175
0
  case SUB16rr_ND:
6176
0
  case SUB16rr_ND_REV:
6177
0
  case SUB16rr_NF:
6178
0
  case SUB16rr_NF_ND:
6179
0
  case SUB16rr_NF_ND_REV:
6180
0
  case SUB16rr_NF_REV:
6181
0
  case SUB16rr_REV:
6182
0
  case SUB32i32:
6183
0
  case SUB32mi:
6184
0
  case SUB32mi8:
6185
0
  case SUB32mi8_EVEX:
6186
0
  case SUB32mi8_ND:
6187
0
  case SUB32mi8_NF:
6188
0
  case SUB32mi8_NF_ND:
6189
0
  case SUB32mi_EVEX:
6190
0
  case SUB32mi_ND:
6191
0
  case SUB32mi_NF:
6192
0
  case SUB32mi_NF_ND:
6193
0
  case SUB32mr:
6194
0
  case SUB32mr_EVEX:
6195
0
  case SUB32mr_ND:
6196
0
  case SUB32mr_NF:
6197
0
  case SUB32mr_NF_ND:
6198
0
  case SUB32ri:
6199
0
  case SUB32ri8:
6200
0
  case SUB32ri8_EVEX:
6201
0
  case SUB32ri8_ND:
6202
0
  case SUB32ri8_NF:
6203
0
  case SUB32ri8_NF_ND:
6204
0
  case SUB32ri_EVEX:
6205
0
  case SUB32ri_ND:
6206
0
  case SUB32ri_NF:
6207
0
  case SUB32ri_NF_ND:
6208
0
  case SUB32rm:
6209
0
  case SUB32rm_EVEX:
6210
0
  case SUB32rm_ND:
6211
0
  case SUB32rm_NF:
6212
0
  case SUB32rm_NF_ND:
6213
0
  case SUB32rr:
6214
0
  case SUB32rr_EVEX:
6215
0
  case SUB32rr_EVEX_REV:
6216
0
  case SUB32rr_ND:
6217
0
  case SUB32rr_ND_REV:
6218
0
  case SUB32rr_NF:
6219
0
  case SUB32rr_NF_ND:
6220
0
  case SUB32rr_NF_ND_REV:
6221
0
  case SUB32rr_NF_REV:
6222
0
  case SUB32rr_REV:
6223
0
  case SUB64i32:
6224
0
  case SUB64mi32:
6225
0
  case SUB64mi32_EVEX:
6226
0
  case SUB64mi32_ND:
6227
0
  case SUB64mi32_NF:
6228
0
  case SUB64mi32_NF_ND:
6229
0
  case SUB64mi8:
6230
0
  case SUB64mi8_EVEX:
6231
0
  case SUB64mi8_ND:
6232
0
  case SUB64mi8_NF:
6233
0
  case SUB64mi8_NF_ND:
6234
0
  case SUB64mr:
6235
0
  case SUB64mr_EVEX:
6236
0
  case SUB64mr_ND:
6237
0
  case SUB64mr_NF:
6238
0
  case SUB64mr_NF_ND:
6239
0
  case SUB64ri32:
6240
0
  case SUB64ri32_EVEX:
6241
0
  case SUB64ri32_ND:
6242
0
  case SUB64ri32_NF:
6243
0
  case SUB64ri32_NF_ND:
6244
0
  case SUB64ri8:
6245
0
  case SUB64ri8_EVEX:
6246
0
  case SUB64ri8_ND:
6247
0
  case SUB64ri8_NF:
6248
0
  case SUB64ri8_NF_ND:
6249
0
  case SUB64rm:
6250
0
  case SUB64rm_EVEX:
6251
0
  case SUB64rm_ND:
6252
0
  case SUB64rm_NF:
6253
0
  case SUB64rm_NF_ND:
6254
0
  case SUB64rr:
6255
0
  case SUB64rr_EVEX:
6256
0
  case SUB64rr_EVEX_REV:
6257
0
  case SUB64rr_ND:
6258
0
  case SUB64rr_ND_REV:
6259
0
  case SUB64rr_NF:
6260
0
  case SUB64rr_NF_ND:
6261
0
  case SUB64rr_NF_ND_REV:
6262
0
  case SUB64rr_NF_REV:
6263
0
  case SUB64rr_REV:
6264
0
  case SUB8i8:
6265
0
  case SUB8mi:
6266
0
  case SUB8mi8:
6267
0
  case SUB8mi_EVEX:
6268
0
  case SUB8mi_ND:
6269
0
  case SUB8mi_NF:
6270
0
  case SUB8mi_NF_ND:
6271
0
  case SUB8mr:
6272
0
  case SUB8mr_EVEX:
6273
0
  case SUB8mr_ND:
6274
0
  case SUB8mr_NF:
6275
0
  case SUB8mr_NF_ND:
6276
0
  case SUB8ri:
6277
0
  case SUB8ri8:
6278
0
  case SUB8ri_EVEX:
6279
0
  case SUB8ri_ND:
6280
0
  case SUB8ri_NF:
6281
0
  case SUB8ri_NF_ND:
6282
0
  case SUB8rm:
6283
0
  case SUB8rm_EVEX:
6284
0
  case SUB8rm_ND:
6285
0
  case SUB8rm_NF:
6286
0
  case SUB8rm_NF_ND:
6287
0
  case SUB8rr:
6288
0
  case SUB8rr_EVEX:
6289
0
  case SUB8rr_EVEX_REV:
6290
0
  case SUB8rr_ND:
6291
0
  case SUB8rr_ND_REV:
6292
0
  case SUB8rr_NF:
6293
0
  case SUB8rr_NF_ND:
6294
0
  case SUB8rr_NF_ND_REV:
6295
0
  case SUB8rr_NF_REV:
6296
0
  case SUB8rr_REV:
6297
0
    return true;
6298
0
  }
6299
0
  return false;
6300
0
}
6301
6302
0
bool isVRSQRT28PD(unsigned Opcode) {
6303
0
  switch (Opcode) {
6304
0
  case VRSQRT28PDZm:
6305
0
  case VRSQRT28PDZmb:
6306
0
  case VRSQRT28PDZmbk:
6307
0
  case VRSQRT28PDZmbkz:
6308
0
  case VRSQRT28PDZmk:
6309
0
  case VRSQRT28PDZmkz:
6310
0
  case VRSQRT28PDZr:
6311
0
  case VRSQRT28PDZrb:
6312
0
  case VRSQRT28PDZrbk:
6313
0
  case VRSQRT28PDZrbkz:
6314
0
  case VRSQRT28PDZrk:
6315
0
  case VRSQRT28PDZrkz:
6316
0
    return true;
6317
0
  }
6318
0
  return false;
6319
0
}
6320
6321
0
bool isVFNMADD132PH(unsigned Opcode) {
6322
0
  switch (Opcode) {
6323
0
  case VFNMADD132PHZ128m:
6324
0
  case VFNMADD132PHZ128mb:
6325
0
  case VFNMADD132PHZ128mbk:
6326
0
  case VFNMADD132PHZ128mbkz:
6327
0
  case VFNMADD132PHZ128mk:
6328
0
  case VFNMADD132PHZ128mkz:
6329
0
  case VFNMADD132PHZ128r:
6330
0
  case VFNMADD132PHZ128rk:
6331
0
  case VFNMADD132PHZ128rkz:
6332
0
  case VFNMADD132PHZ256m:
6333
0
  case VFNMADD132PHZ256mb:
6334
0
  case VFNMADD132PHZ256mbk:
6335
0
  case VFNMADD132PHZ256mbkz:
6336
0
  case VFNMADD132PHZ256mk:
6337
0
  case VFNMADD132PHZ256mkz:
6338
0
  case VFNMADD132PHZ256r:
6339
0
  case VFNMADD132PHZ256rk:
6340
0
  case VFNMADD132PHZ256rkz:
6341
0
  case VFNMADD132PHZm:
6342
0
  case VFNMADD132PHZmb:
6343
0
  case VFNMADD132PHZmbk:
6344
0
  case VFNMADD132PHZmbkz:
6345
0
  case VFNMADD132PHZmk:
6346
0
  case VFNMADD132PHZmkz:
6347
0
  case VFNMADD132PHZr:
6348
0
  case VFNMADD132PHZrb:
6349
0
  case VFNMADD132PHZrbk:
6350
0
  case VFNMADD132PHZrbkz:
6351
0
  case VFNMADD132PHZrk:
6352
0
  case VFNMADD132PHZrkz:
6353
0
    return true;
6354
0
  }
6355
0
  return false;
6356
0
}
6357
6358
0
bool isVPMACSSWW(unsigned Opcode) {
6359
0
  switch (Opcode) {
6360
0
  case VPMACSSWWrm:
6361
0
  case VPMACSSWWrr:
6362
0
    return true;
6363
0
  }
6364
0
  return false;
6365
0
}
6366
6367
0
bool isXSTORE(unsigned Opcode) {
6368
0
  return Opcode == XSTORE;
6369
0
}
6370
6371
0
bool isVPROTQ(unsigned Opcode) {
6372
0
  switch (Opcode) {
6373
0
  case VPROTQmi:
6374
0
  case VPROTQmr:
6375
0
  case VPROTQri:
6376
0
  case VPROTQrm:
6377
0
  case VPROTQrr:
6378
0
  case VPROTQrr_REV:
6379
0
    return true;
6380
0
  }
6381
0
  return false;
6382
0
}
6383
6384
0
bool isVPHADDBD(unsigned Opcode) {
6385
0
  switch (Opcode) {
6386
0
  case VPHADDBDrm:
6387
0
  case VPHADDBDrr:
6388
0
    return true;
6389
0
  }
6390
0
  return false;
6391
0
}
6392
6393
0
bool isVPMAXSB(unsigned Opcode) {
6394
0
  switch (Opcode) {
6395
0
  case VPMAXSBYrm:
6396
0
  case VPMAXSBYrr:
6397
0
  case VPMAXSBZ128rm:
6398
0
  case VPMAXSBZ128rmk:
6399
0
  case VPMAXSBZ128rmkz:
6400
0
  case VPMAXSBZ128rr:
6401
0
  case VPMAXSBZ128rrk:
6402
0
  case VPMAXSBZ128rrkz:
6403
0
  case VPMAXSBZ256rm:
6404
0
  case VPMAXSBZ256rmk:
6405
0
  case VPMAXSBZ256rmkz:
6406
0
  case VPMAXSBZ256rr:
6407
0
  case VPMAXSBZ256rrk:
6408
0
  case VPMAXSBZ256rrkz:
6409
0
  case VPMAXSBZrm:
6410
0
  case VPMAXSBZrmk:
6411
0
  case VPMAXSBZrmkz:
6412
0
  case VPMAXSBZrr:
6413
0
  case VPMAXSBZrrk:
6414
0
  case VPMAXSBZrrkz:
6415
0
  case VPMAXSBrm:
6416
0
  case VPMAXSBrr:
6417
0
    return true;
6418
0
  }
6419
0
  return false;
6420
0
}
6421
6422
0
bool isVMOVDQU8(unsigned Opcode) {
6423
0
  switch (Opcode) {
6424
0
  case VMOVDQU8Z128mr:
6425
0
  case VMOVDQU8Z128mrk:
6426
0
  case VMOVDQU8Z128rm:
6427
0
  case VMOVDQU8Z128rmk:
6428
0
  case VMOVDQU8Z128rmkz:
6429
0
  case VMOVDQU8Z128rr:
6430
0
  case VMOVDQU8Z128rr_REV:
6431
0
  case VMOVDQU8Z128rrk:
6432
0
  case VMOVDQU8Z128rrk_REV:
6433
0
  case VMOVDQU8Z128rrkz:
6434
0
  case VMOVDQU8Z128rrkz_REV:
6435
0
  case VMOVDQU8Z256mr:
6436
0
  case VMOVDQU8Z256mrk:
6437
0
  case VMOVDQU8Z256rm:
6438
0
  case VMOVDQU8Z256rmk:
6439
0
  case VMOVDQU8Z256rmkz:
6440
0
  case VMOVDQU8Z256rr:
6441
0
  case VMOVDQU8Z256rr_REV:
6442
0
  case VMOVDQU8Z256rrk:
6443
0
  case VMOVDQU8Z256rrk_REV:
6444
0
  case VMOVDQU8Z256rrkz:
6445
0
  case VMOVDQU8Z256rrkz_REV:
6446
0
  case VMOVDQU8Zmr:
6447
0
  case VMOVDQU8Zmrk:
6448
0
  case VMOVDQU8Zrm:
6449
0
  case VMOVDQU8Zrmk:
6450
0
  case VMOVDQU8Zrmkz:
6451
0
  case VMOVDQU8Zrr:
6452
0
  case VMOVDQU8Zrr_REV:
6453
0
  case VMOVDQU8Zrrk:
6454
0
  case VMOVDQU8Zrrk_REV:
6455
0
  case VMOVDQU8Zrrkz:
6456
0
  case VMOVDQU8Zrrkz_REV:
6457
0
    return true;
6458
0
  }
6459
0
  return false;
6460
0
}
6461
6462
0
bool isVPMOVSXWD(unsigned Opcode) {
6463
0
  switch (Opcode) {
6464
0
  case VPMOVSXWDYrm:
6465
0
  case VPMOVSXWDYrr:
6466
0
  case VPMOVSXWDZ128rm:
6467
0
  case VPMOVSXWDZ128rmk:
6468
0
  case VPMOVSXWDZ128rmkz:
6469
0
  case VPMOVSXWDZ128rr:
6470
0
  case VPMOVSXWDZ128rrk:
6471
0
  case VPMOVSXWDZ128rrkz:
6472
0
  case VPMOVSXWDZ256rm:
6473
0
  case VPMOVSXWDZ256rmk:
6474
0
  case VPMOVSXWDZ256rmkz:
6475
0
  case VPMOVSXWDZ256rr:
6476
0
  case VPMOVSXWDZ256rrk:
6477
0
  case VPMOVSXWDZ256rrkz:
6478
0
  case VPMOVSXWDZrm:
6479
0
  case VPMOVSXWDZrmk:
6480
0
  case VPMOVSXWDZrmkz:
6481
0
  case VPMOVSXWDZrr:
6482
0
  case VPMOVSXWDZrrk:
6483
0
  case VPMOVSXWDZrrkz:
6484
0
  case VPMOVSXWDrm:
6485
0
  case VPMOVSXWDrr:
6486
0
    return true;
6487
0
  }
6488
0
  return false;
6489
0
}
6490
6491
0
bool isSHA256RNDS2(unsigned Opcode) {
6492
0
  switch (Opcode) {
6493
0
  case SHA256RNDS2rm:
6494
0
  case SHA256RNDS2rm_EVEX:
6495
0
  case SHA256RNDS2rr:
6496
0
  case SHA256RNDS2rr_EVEX:
6497
0
    return true;
6498
0
  }
6499
0
  return false;
6500
0
}
6501
6502
0
bool isKANDB(unsigned Opcode) {
6503
0
  return Opcode == KANDBrr;
6504
0
}
6505
6506
0
bool isTPAUSE(unsigned Opcode) {
6507
0
  return Opcode == TPAUSE;
6508
0
}
6509
6510
0
bool isPUSH(unsigned Opcode) {
6511
0
  switch (Opcode) {
6512
0
  case PUSH16i:
6513
0
  case PUSH16i8:
6514
0
  case PUSH16r:
6515
0
  case PUSH16rmm:
6516
0
  case PUSH16rmr:
6517
0
  case PUSH32i:
6518
0
  case PUSH32i8:
6519
0
  case PUSH32r:
6520
0
  case PUSH32rmm:
6521
0
  case PUSH32rmr:
6522
0
  case PUSH64i32:
6523
0
  case PUSH64i8:
6524
0
  case PUSH64r:
6525
0
  case PUSH64rmm:
6526
0
  case PUSH64rmr:
6527
0
  case PUSHCS16:
6528
0
  case PUSHCS32:
6529
0
  case PUSHDS16:
6530
0
  case PUSHDS32:
6531
0
  case PUSHES16:
6532
0
  case PUSHES32:
6533
0
  case PUSHFS16:
6534
0
  case PUSHFS32:
6535
0
  case PUSHFS64:
6536
0
  case PUSHGS16:
6537
0
  case PUSHGS32:
6538
0
  case PUSHGS64:
6539
0
  case PUSHSS16:
6540
0
  case PUSHSS32:
6541
0
    return true;
6542
0
  }
6543
0
  return false;
6544
0
}
6545
6546
0
bool isVRNDSCALESS(unsigned Opcode) {
6547
0
  switch (Opcode) {
6548
0
  case VRNDSCALESSZm_Int:
6549
0
  case VRNDSCALESSZm_Intk:
6550
0
  case VRNDSCALESSZm_Intkz:
6551
0
  case VRNDSCALESSZr_Int:
6552
0
  case VRNDSCALESSZr_Intk:
6553
0
  case VRNDSCALESSZr_Intkz:
6554
0
  case VRNDSCALESSZrb_Int:
6555
0
  case VRNDSCALESSZrb_Intk:
6556
0
  case VRNDSCALESSZrb_Intkz:
6557
0
    return true;
6558
0
  }
6559
0
  return false;
6560
0
}
6561
6562
0
bool isVPCMPISTRI(unsigned Opcode) {
6563
0
  switch (Opcode) {
6564
0
  case VPCMPISTRIrm:
6565
0
  case VPCMPISTRIrr:
6566
0
    return true;
6567
0
  }
6568
0
  return false;
6569
0
}
6570
6571
0
bool isSTGI(unsigned Opcode) {
6572
0
  return Opcode == STGI;
6573
0
}
6574
6575
0
bool isSBB(unsigned Opcode) {
6576
0
  switch (Opcode) {
6577
0
  case SBB16i16:
6578
0
  case SBB16mi:
6579
0
  case SBB16mi8:
6580
0
  case SBB16mi8_EVEX:
6581
0
  case SBB16mi8_ND:
6582
0
  case SBB16mi_EVEX:
6583
0
  case SBB16mi_ND:
6584
0
  case SBB16mr:
6585
0
  case SBB16mr_EVEX:
6586
0
  case SBB16mr_ND:
6587
0
  case SBB16ri:
6588
0
  case SBB16ri8:
6589
0
  case SBB16ri8_EVEX:
6590
0
  case SBB16ri8_ND:
6591
0
  case SBB16ri_EVEX:
6592
0
  case SBB16ri_ND:
6593
0
  case SBB16rm:
6594
0
  case SBB16rm_EVEX:
6595
0
  case SBB16rm_ND:
6596
0
  case SBB16rr:
6597
0
  case SBB16rr_EVEX:
6598
0
  case SBB16rr_EVEX_REV:
6599
0
  case SBB16rr_ND:
6600
0
  case SBB16rr_ND_REV:
6601
0
  case SBB16rr_REV:
6602
0
  case SBB32i32:
6603
0
  case SBB32mi:
6604
0
  case SBB32mi8:
6605
0
  case SBB32mi8_EVEX:
6606
0
  case SBB32mi8_ND:
6607
0
  case SBB32mi_EVEX:
6608
0
  case SBB32mi_ND:
6609
0
  case SBB32mr:
6610
0
  case SBB32mr_EVEX:
6611
0
  case SBB32mr_ND:
6612
0
  case SBB32ri:
6613
0
  case SBB32ri8:
6614
0
  case SBB32ri8_EVEX:
6615
0
  case SBB32ri8_ND:
6616
0
  case SBB32ri_EVEX:
6617
0
  case SBB32ri_ND:
6618
0
  case SBB32rm:
6619
0
  case SBB32rm_EVEX:
6620
0
  case SBB32rm_ND:
6621
0
  case SBB32rr:
6622
0
  case SBB32rr_EVEX:
6623
0
  case SBB32rr_EVEX_REV:
6624
0
  case SBB32rr_ND:
6625
0
  case SBB32rr_ND_REV:
6626
0
  case SBB32rr_REV:
6627
0
  case SBB64i32:
6628
0
  case SBB64mi32:
6629
0
  case SBB64mi32_EVEX:
6630
0
  case SBB64mi32_ND:
6631
0
  case SBB64mi8:
6632
0
  case SBB64mi8_EVEX:
6633
0
  case SBB64mi8_ND:
6634
0
  case SBB64mr:
6635
0
  case SBB64mr_EVEX:
6636
0
  case SBB64mr_ND:
6637
0
  case SBB64ri32:
6638
0
  case SBB64ri32_EVEX:
6639
0
  case SBB64ri32_ND:
6640
0
  case SBB64ri8:
6641
0
  case SBB64ri8_EVEX:
6642
0
  case SBB64ri8_ND:
6643
0
  case SBB64rm:
6644
0
  case SBB64rm_EVEX:
6645
0
  case SBB64rm_ND:
6646
0
  case SBB64rr:
6647
0
  case SBB64rr_EVEX:
6648
0
  case SBB64rr_EVEX_REV:
6649
0
  case SBB64rr_ND:
6650
0
  case SBB64rr_ND_REV:
6651
0
  case SBB64rr_REV:
6652
0
  case SBB8i8:
6653
0
  case SBB8mi:
6654
0
  case SBB8mi8:
6655
0
  case SBB8mi_EVEX:
6656
0
  case SBB8mi_ND:
6657
0
  case SBB8mr:
6658
0
  case SBB8mr_EVEX:
6659
0
  case SBB8mr_ND:
6660
0
  case SBB8ri:
6661
0
  case SBB8ri8:
6662
0
  case SBB8ri_EVEX:
6663
0
  case SBB8ri_ND:
6664
0
  case SBB8rm:
6665
0
  case SBB8rm_EVEX:
6666
0
  case SBB8rm_ND:
6667
0
  case SBB8rr:
6668
0
  case SBB8rr_EVEX:
6669
0
  case SBB8rr_EVEX_REV:
6670
0
  case SBB8rr_ND:
6671
0
  case SBB8rr_ND_REV:
6672
0
  case SBB8rr_REV:
6673
0
    return true;
6674
0
  }
6675
0
  return false;
6676
0
}
6677
6678
0
bool isBLCS(unsigned Opcode) {
6679
0
  switch (Opcode) {
6680
0
  case BLCS32rm:
6681
0
  case BLCS32rr:
6682
0
  case BLCS64rm:
6683
0
  case BLCS64rr:
6684
0
    return true;
6685
0
  }
6686
0
  return false;
6687
0
}
6688
6689
0
bool isVCVTSD2SH(unsigned Opcode) {
6690
0
  switch (Opcode) {
6691
0
  case VCVTSD2SHZrm_Int:
6692
0
  case VCVTSD2SHZrm_Intk:
6693
0
  case VCVTSD2SHZrm_Intkz:
6694
0
  case VCVTSD2SHZrr_Int:
6695
0
  case VCVTSD2SHZrr_Intk:
6696
0
  case VCVTSD2SHZrr_Intkz:
6697
0
  case VCVTSD2SHZrrb_Int:
6698
0
  case VCVTSD2SHZrrb_Intk:
6699
0
  case VCVTSD2SHZrrb_Intkz:
6700
0
    return true;
6701
0
  }
6702
0
  return false;
6703
0
}
6704
6705
0
bool isVPERMW(unsigned Opcode) {
6706
0
  switch (Opcode) {
6707
0
  case VPERMWZ128rm:
6708
0
  case VPERMWZ128rmk:
6709
0
  case VPERMWZ128rmkz:
6710
0
  case VPERMWZ128rr:
6711
0
  case VPERMWZ128rrk:
6712
0
  case VPERMWZ128rrkz:
6713
0
  case VPERMWZ256rm:
6714
0
  case VPERMWZ256rmk:
6715
0
  case VPERMWZ256rmkz:
6716
0
  case VPERMWZ256rr:
6717
0
  case VPERMWZ256rrk:
6718
0
  case VPERMWZ256rrkz:
6719
0
  case VPERMWZrm:
6720
0
  case VPERMWZrmk:
6721
0
  case VPERMWZrmkz:
6722
0
  case VPERMWZrr:
6723
0
  case VPERMWZrrk:
6724
0
  case VPERMWZrrkz:
6725
0
    return true;
6726
0
  }
6727
0
  return false;
6728
0
}
6729
6730
0
bool isXRESLDTRK(unsigned Opcode) {
6731
0
  return Opcode == XRESLDTRK;
6732
0
}
6733
6734
0
bool isAESENC256KL(unsigned Opcode) {
6735
0
  return Opcode == AESENC256KL;
6736
0
}
6737
6738
0
bool isVGATHERDPD(unsigned Opcode) {
6739
0
  switch (Opcode) {
6740
0
  case VGATHERDPDYrm:
6741
0
  case VGATHERDPDZ128rm:
6742
0
  case VGATHERDPDZ256rm:
6743
0
  case VGATHERDPDZrm:
6744
0
  case VGATHERDPDrm:
6745
0
    return true;
6746
0
  }
6747
0
  return false;
6748
0
}
6749
6750
0
bool isHRESET(unsigned Opcode) {
6751
0
  return Opcode == HRESET;
6752
0
}
6753
6754
0
bool isVFMSUBADD231PD(unsigned Opcode) {
6755
0
  switch (Opcode) {
6756
0
  case VFMSUBADD231PDYm:
6757
0
  case VFMSUBADD231PDYr:
6758
0
  case VFMSUBADD231PDZ128m:
6759
0
  case VFMSUBADD231PDZ128mb:
6760
0
  case VFMSUBADD231PDZ128mbk:
6761
0
  case VFMSUBADD231PDZ128mbkz:
6762
0
  case VFMSUBADD231PDZ128mk:
6763
0
  case VFMSUBADD231PDZ128mkz:
6764
0
  case VFMSUBADD231PDZ128r:
6765
0
  case VFMSUBADD231PDZ128rk:
6766
0
  case VFMSUBADD231PDZ128rkz:
6767
0
  case VFMSUBADD231PDZ256m:
6768
0
  case VFMSUBADD231PDZ256mb:
6769
0
  case VFMSUBADD231PDZ256mbk:
6770
0
  case VFMSUBADD231PDZ256mbkz:
6771
0
  case VFMSUBADD231PDZ256mk:
6772
0
  case VFMSUBADD231PDZ256mkz:
6773
0
  case VFMSUBADD231PDZ256r:
6774
0
  case VFMSUBADD231PDZ256rk:
6775
0
  case VFMSUBADD231PDZ256rkz:
6776
0
  case VFMSUBADD231PDZm:
6777
0
  case VFMSUBADD231PDZmb:
6778
0
  case VFMSUBADD231PDZmbk:
6779
0
  case VFMSUBADD231PDZmbkz:
6780
0
  case VFMSUBADD231PDZmk:
6781
0
  case VFMSUBADD231PDZmkz:
6782
0
  case VFMSUBADD231PDZr:
6783
0
  case VFMSUBADD231PDZrb:
6784
0
  case VFMSUBADD231PDZrbk:
6785
0
  case VFMSUBADD231PDZrbkz:
6786
0
  case VFMSUBADD231PDZrk:
6787
0
  case VFMSUBADD231PDZrkz:
6788
0
  case VFMSUBADD231PDm:
6789
0
  case VFMSUBADD231PDr:
6790
0
    return true;
6791
0
  }
6792
0
  return false;
6793
0
}
6794
6795
0
bool isVFRCZSS(unsigned Opcode) {
6796
0
  switch (Opcode) {
6797
0
  case VFRCZSSrm:
6798
0
  case VFRCZSSrr:
6799
0
    return true;
6800
0
  }
6801
0
  return false;
6802
0
}
6803
6804
0
bool isMINPS(unsigned Opcode) {
6805
0
  switch (Opcode) {
6806
0
  case MINPSrm:
6807
0
  case MINPSrr:
6808
0
    return true;
6809
0
  }
6810
0
  return false;
6811
0
}
6812
6813
0
bool isFPREM1(unsigned Opcode) {
6814
0
  return Opcode == FPREM1;
6815
0
}
6816
6817
0
bool isVPCMPUB(unsigned Opcode) {
6818
0
  switch (Opcode) {
6819
0
  case VPCMPUBZ128rmi:
6820
0
  case VPCMPUBZ128rmik:
6821
0
  case VPCMPUBZ128rri:
6822
0
  case VPCMPUBZ128rrik:
6823
0
  case VPCMPUBZ256rmi:
6824
0
  case VPCMPUBZ256rmik:
6825
0
  case VPCMPUBZ256rri:
6826
0
  case VPCMPUBZ256rrik:
6827
0
  case VPCMPUBZrmi:
6828
0
  case VPCMPUBZrmik:
6829
0
  case VPCMPUBZrri:
6830
0
  case VPCMPUBZrrik:
6831
0
    return true;
6832
0
  }
6833
0
  return false;
6834
0
}
6835
6836
0
bool isVSQRTPD(unsigned Opcode) {
6837
0
  switch (Opcode) {
6838
0
  case VSQRTPDYm:
6839
0
  case VSQRTPDYr:
6840
0
  case VSQRTPDZ128m:
6841
0
  case VSQRTPDZ128mb:
6842
0
  case VSQRTPDZ128mbk:
6843
0
  case VSQRTPDZ128mbkz:
6844
0
  case VSQRTPDZ128mk:
6845
0
  case VSQRTPDZ128mkz:
6846
0
  case VSQRTPDZ128r:
6847
0
  case VSQRTPDZ128rk:
6848
0
  case VSQRTPDZ128rkz:
6849
0
  case VSQRTPDZ256m:
6850
0
  case VSQRTPDZ256mb:
6851
0
  case VSQRTPDZ256mbk:
6852
0
  case VSQRTPDZ256mbkz:
6853
0
  case VSQRTPDZ256mk:
6854
0
  case VSQRTPDZ256mkz:
6855
0
  case VSQRTPDZ256r:
6856
0
  case VSQRTPDZ256rk:
6857
0
  case VSQRTPDZ256rkz:
6858
0
  case VSQRTPDZm:
6859
0
  case VSQRTPDZmb:
6860
0
  case VSQRTPDZmbk:
6861
0
  case VSQRTPDZmbkz:
6862
0
  case VSQRTPDZmk:
6863
0
  case VSQRTPDZmkz:
6864
0
  case VSQRTPDZr:
6865
0
  case VSQRTPDZrb:
6866
0
  case VSQRTPDZrbk:
6867
0
  case VSQRTPDZrbkz:
6868
0
  case VSQRTPDZrk:
6869
0
  case VSQRTPDZrkz:
6870
0
  case VSQRTPDm:
6871
0
  case VSQRTPDr:
6872
0
    return true;
6873
0
  }
6874
0
  return false;
6875
0
}
6876
6877
0
bool isVFRCZPS(unsigned Opcode) {
6878
0
  switch (Opcode) {
6879
0
  case VFRCZPSYrm:
6880
0
  case VFRCZPSYrr:
6881
0
  case VFRCZPSrm:
6882
0
  case VFRCZPSrr:
6883
0
    return true;
6884
0
  }
6885
0
  return false;
6886
0
}
6887
6888
0
bool isVFNMADD213SS(unsigned Opcode) {
6889
0
  switch (Opcode) {
6890
0
  case VFNMADD213SSZm_Int:
6891
0
  case VFNMADD213SSZm_Intk:
6892
0
  case VFNMADD213SSZm_Intkz:
6893
0
  case VFNMADD213SSZr_Int:
6894
0
  case VFNMADD213SSZr_Intk:
6895
0
  case VFNMADD213SSZr_Intkz:
6896
0
  case VFNMADD213SSZrb_Int:
6897
0
  case VFNMADD213SSZrb_Intk:
6898
0
  case VFNMADD213SSZrb_Intkz:
6899
0
  case VFNMADD213SSm_Int:
6900
0
  case VFNMADD213SSr_Int:
6901
0
    return true;
6902
0
  }
6903
0
  return false;
6904
0
}
6905
6906
0
bool isVPMOVDW(unsigned Opcode) {
6907
0
  switch (Opcode) {
6908
0
  case VPMOVDWZ128mr:
6909
0
  case VPMOVDWZ128mrk:
6910
0
  case VPMOVDWZ128rr:
6911
0
  case VPMOVDWZ128rrk:
6912
0
  case VPMOVDWZ128rrkz:
6913
0
  case VPMOVDWZ256mr:
6914
0
  case VPMOVDWZ256mrk:
6915
0
  case VPMOVDWZ256rr:
6916
0
  case VPMOVDWZ256rrk:
6917
0
  case VPMOVDWZ256rrkz:
6918
0
  case VPMOVDWZmr:
6919
0
  case VPMOVDWZmrk:
6920
0
  case VPMOVDWZrr:
6921
0
  case VPMOVDWZrrk:
6922
0
  case VPMOVDWZrrkz:
6923
0
    return true;
6924
0
  }
6925
0
  return false;
6926
0
}
6927
6928
0
bool isVPSHRDVQ(unsigned Opcode) {
6929
0
  switch (Opcode) {
6930
0
  case VPSHRDVQZ128m:
6931
0
  case VPSHRDVQZ128mb:
6932
0
  case VPSHRDVQZ128mbk:
6933
0
  case VPSHRDVQZ128mbkz:
6934
0
  case VPSHRDVQZ128mk:
6935
0
  case VPSHRDVQZ128mkz:
6936
0
  case VPSHRDVQZ128r:
6937
0
  case VPSHRDVQZ128rk:
6938
0
  case VPSHRDVQZ128rkz:
6939
0
  case VPSHRDVQZ256m:
6940
0
  case VPSHRDVQZ256mb:
6941
0
  case VPSHRDVQZ256mbk:
6942
0
  case VPSHRDVQZ256mbkz:
6943
0
  case VPSHRDVQZ256mk:
6944
0
  case VPSHRDVQZ256mkz:
6945
0
  case VPSHRDVQZ256r:
6946
0
  case VPSHRDVQZ256rk:
6947
0
  case VPSHRDVQZ256rkz:
6948
0
  case VPSHRDVQZm:
6949
0
  case VPSHRDVQZmb:
6950
0
  case VPSHRDVQZmbk:
6951
0
  case VPSHRDVQZmbkz:
6952
0
  case VPSHRDVQZmk:
6953
0
  case VPSHRDVQZmkz:
6954
0
  case VPSHRDVQZr:
6955
0
  case VPSHRDVQZrk:
6956
0
  case VPSHRDVQZrkz:
6957
0
    return true;
6958
0
  }
6959
0
  return false;
6960
0
}
6961
6962
0
bool isVBROADCASTSD(unsigned Opcode) {
6963
0
  switch (Opcode) {
6964
0
  case VBROADCASTSDYrm:
6965
0
  case VBROADCASTSDYrr:
6966
0
  case VBROADCASTSDZ256rm:
6967
0
  case VBROADCASTSDZ256rmk:
6968
0
  case VBROADCASTSDZ256rmkz:
6969
0
  case VBROADCASTSDZ256rr:
6970
0
  case VBROADCASTSDZ256rrk:
6971
0
  case VBROADCASTSDZ256rrkz:
6972
0
  case VBROADCASTSDZrm:
6973
0
  case VBROADCASTSDZrmk:
6974
0
  case VBROADCASTSDZrmkz:
6975
0
  case VBROADCASTSDZrr:
6976
0
  case VBROADCASTSDZrrk:
6977
0
  case VBROADCASTSDZrrkz:
6978
0
    return true;
6979
0
  }
6980
0
  return false;
6981
0
}
6982
6983
0
bool isVSHUFPD(unsigned Opcode) {
6984
0
  switch (Opcode) {
6985
0
  case VSHUFPDYrmi:
6986
0
  case VSHUFPDYrri:
6987
0
  case VSHUFPDZ128rmbi:
6988
0
  case VSHUFPDZ128rmbik:
6989
0
  case VSHUFPDZ128rmbikz:
6990
0
  case VSHUFPDZ128rmi:
6991
0
  case VSHUFPDZ128rmik:
6992
0
  case VSHUFPDZ128rmikz:
6993
0
  case VSHUFPDZ128rri:
6994
0
  case VSHUFPDZ128rrik:
6995
0
  case VSHUFPDZ128rrikz:
6996
0
  case VSHUFPDZ256rmbi:
6997
0
  case VSHUFPDZ256rmbik:
6998
0
  case VSHUFPDZ256rmbikz:
6999
0
  case VSHUFPDZ256rmi:
7000
0
  case VSHUFPDZ256rmik:
7001
0
  case VSHUFPDZ256rmikz:
7002
0
  case VSHUFPDZ256rri:
7003
0
  case VSHUFPDZ256rrik:
7004
0
  case VSHUFPDZ256rrikz:
7005
0
  case VSHUFPDZrmbi:
7006
0
  case VSHUFPDZrmbik:
7007
0
  case VSHUFPDZrmbikz:
7008
0
  case VSHUFPDZrmi:
7009
0
  case VSHUFPDZrmik:
7010
0
  case VSHUFPDZrmikz:
7011
0
  case VSHUFPDZrri:
7012
0
  case VSHUFPDZrrik:
7013
0
  case VSHUFPDZrrikz:
7014
0
  case VSHUFPDrmi:
7015
0
  case VSHUFPDrri:
7016
0
    return true;
7017
0
  }
7018
0
  return false;
7019
0
}
7020
7021
0
bool isVPSUBSW(unsigned Opcode) {
7022
0
  switch (Opcode) {
7023
0
  case VPSUBSWYrm:
7024
0
  case VPSUBSWYrr:
7025
0
  case VPSUBSWZ128rm:
7026
0
  case VPSUBSWZ128rmk:
7027
0
  case VPSUBSWZ128rmkz:
7028
0
  case VPSUBSWZ128rr:
7029
0
  case VPSUBSWZ128rrk:
7030
0
  case VPSUBSWZ128rrkz:
7031
0
  case VPSUBSWZ256rm:
7032
0
  case VPSUBSWZ256rmk:
7033
0
  case VPSUBSWZ256rmkz:
7034
0
  case VPSUBSWZ256rr:
7035
0
  case VPSUBSWZ256rrk:
7036
0
  case VPSUBSWZ256rrkz:
7037
0
  case VPSUBSWZrm:
7038
0
  case VPSUBSWZrmk:
7039
0
  case VPSUBSWZrmkz:
7040
0
  case VPSUBSWZrr:
7041
0
  case VPSUBSWZrrk:
7042
0
  case VPSUBSWZrrkz:
7043
0
  case VPSUBSWrm:
7044
0
  case VPSUBSWrr:
7045
0
    return true;
7046
0
  }
7047
0
  return false;
7048
0
}
7049
7050
0
bool isKUNPCKBW(unsigned Opcode) {
7051
0
  return Opcode == KUNPCKBWrr;
7052
0
}
7053
7054
0
bool isVPBLENDD(unsigned Opcode) {
7055
0
  switch (Opcode) {
7056
0
  case VPBLENDDYrmi:
7057
0
  case VPBLENDDYrri:
7058
0
  case VPBLENDDrmi:
7059
0
  case VPBLENDDrri:
7060
0
    return true;
7061
0
  }
7062
0
  return false;
7063
0
}
7064
7065
0
bool isUNPCKHPD(unsigned Opcode) {
7066
0
  switch (Opcode) {
7067
0
  case UNPCKHPDrm:
7068
0
  case UNPCKHPDrr:
7069
0
    return true;
7070
0
  }
7071
0
  return false;
7072
0
}
7073
7074
0
bool isVFNMADD231SD(unsigned Opcode) {
7075
0
  switch (Opcode) {
7076
0
  case VFNMADD231SDZm_Int:
7077
0
  case VFNMADD231SDZm_Intk:
7078
0
  case VFNMADD231SDZm_Intkz:
7079
0
  case VFNMADD231SDZr_Int:
7080
0
  case VFNMADD231SDZr_Intk:
7081
0
  case VFNMADD231SDZr_Intkz:
7082
0
  case VFNMADD231SDZrb_Int:
7083
0
  case VFNMADD231SDZrb_Intk:
7084
0
  case VFNMADD231SDZrb_Intkz:
7085
0
  case VFNMADD231SDm_Int:
7086
0
  case VFNMADD231SDr_Int:
7087
0
    return true;
7088
0
  }
7089
0
  return false;
7090
0
}
7091
7092
0
bool isVPBROADCASTMW2D(unsigned Opcode) {
7093
0
  switch (Opcode) {
7094
0
  case VPBROADCASTMW2DZ128rr:
7095
0
  case VPBROADCASTMW2DZ256rr:
7096
0
  case VPBROADCASTMW2DZrr:
7097
0
    return true;
7098
0
  }
7099
0
  return false;
7100
0
}
7101
7102
0
bool isVPMULTISHIFTQB(unsigned Opcode) {
7103
0
  switch (Opcode) {
7104
0
  case VPMULTISHIFTQBZ128rm:
7105
0
  case VPMULTISHIFTQBZ128rmb:
7106
0
  case VPMULTISHIFTQBZ128rmbk:
7107
0
  case VPMULTISHIFTQBZ128rmbkz:
7108
0
  case VPMULTISHIFTQBZ128rmk:
7109
0
  case VPMULTISHIFTQBZ128rmkz:
7110
0
  case VPMULTISHIFTQBZ128rr:
7111
0
  case VPMULTISHIFTQBZ128rrk:
7112
0
  case VPMULTISHIFTQBZ128rrkz:
7113
0
  case VPMULTISHIFTQBZ256rm:
7114
0
  case VPMULTISHIFTQBZ256rmb:
7115
0
  case VPMULTISHIFTQBZ256rmbk:
7116
0
  case VPMULTISHIFTQBZ256rmbkz:
7117
0
  case VPMULTISHIFTQBZ256rmk:
7118
0
  case VPMULTISHIFTQBZ256rmkz:
7119
0
  case VPMULTISHIFTQBZ256rr:
7120
0
  case VPMULTISHIFTQBZ256rrk:
7121
0
  case VPMULTISHIFTQBZ256rrkz:
7122
0
  case VPMULTISHIFTQBZrm:
7123
0
  case VPMULTISHIFTQBZrmb:
7124
0
  case VPMULTISHIFTQBZrmbk:
7125
0
  case VPMULTISHIFTQBZrmbkz:
7126
0
  case VPMULTISHIFTQBZrmk:
7127
0
  case VPMULTISHIFTQBZrmkz:
7128
0
  case VPMULTISHIFTQBZrr:
7129
0
  case VPMULTISHIFTQBZrrk:
7130
0
  case VPMULTISHIFTQBZrrkz:
7131
0
    return true;
7132
0
  }
7133
0
  return false;
7134
0
}
7135
7136
0
bool isVP2INTERSECTQ(unsigned Opcode) {
7137
0
  switch (Opcode) {
7138
0
  case VP2INTERSECTQZ128rm:
7139
0
  case VP2INTERSECTQZ128rmb:
7140
0
  case VP2INTERSECTQZ128rr:
7141
0
  case VP2INTERSECTQZ256rm:
7142
0
  case VP2INTERSECTQZ256rmb:
7143
0
  case VP2INTERSECTQZ256rr:
7144
0
  case VP2INTERSECTQZrm:
7145
0
  case VP2INTERSECTQZrmb:
7146
0
  case VP2INTERSECTQZrr:
7147
0
    return true;
7148
0
  }
7149
0
  return false;
7150
0
}
7151
7152
0
bool isVPUNPCKHWD(unsigned Opcode) {
7153
0
  switch (Opcode) {
7154
0
  case VPUNPCKHWDYrm:
7155
0
  case VPUNPCKHWDYrr:
7156
0
  case VPUNPCKHWDZ128rm:
7157
0
  case VPUNPCKHWDZ128rmk:
7158
0
  case VPUNPCKHWDZ128rmkz:
7159
0
  case VPUNPCKHWDZ128rr:
7160
0
  case VPUNPCKHWDZ128rrk:
7161
0
  case VPUNPCKHWDZ128rrkz:
7162
0
  case VPUNPCKHWDZ256rm:
7163
0
  case VPUNPCKHWDZ256rmk:
7164
0
  case VPUNPCKHWDZ256rmkz:
7165
0
  case VPUNPCKHWDZ256rr:
7166
0
  case VPUNPCKHWDZ256rrk:
7167
0
  case VPUNPCKHWDZ256rrkz:
7168
0
  case VPUNPCKHWDZrm:
7169
0
  case VPUNPCKHWDZrmk:
7170
0
  case VPUNPCKHWDZrmkz:
7171
0
  case VPUNPCKHWDZrr:
7172
0
  case VPUNPCKHWDZrrk:
7173
0
  case VPUNPCKHWDZrrkz:
7174
0
  case VPUNPCKHWDrm:
7175
0
  case VPUNPCKHWDrr:
7176
0
    return true;
7177
0
  }
7178
0
  return false;
7179
0
}
7180
7181
0
bool isVPERM2F128(unsigned Opcode) {
7182
0
  switch (Opcode) {
7183
0
  case VPERM2F128rm:
7184
0
  case VPERM2F128rr:
7185
0
    return true;
7186
0
  }
7187
0
  return false;
7188
0
}
7189
7190
0
bool isINSD(unsigned Opcode) {
7191
0
  return Opcode == INSL;
7192
0
}
7193
7194
0
bool isLFS(unsigned Opcode) {
7195
0
  switch (Opcode) {
7196
0
  case LFS16rm:
7197
0
  case LFS32rm:
7198
0
  case LFS64rm:
7199
0
    return true;
7200
0
  }
7201
0
  return false;
7202
0
}
7203
7204
0
bool isFMULP(unsigned Opcode) {
7205
0
  return Opcode == MUL_FPrST0;
7206
0
}
7207
7208
0
bool isCWD(unsigned Opcode) {
7209
0
  return Opcode == CWD;
7210
0
}
7211
7212
0
bool isVDIVSS(unsigned Opcode) {
7213
0
  switch (Opcode) {
7214
0
  case VDIVSSZrm_Int:
7215
0
  case VDIVSSZrm_Intk:
7216
0
  case VDIVSSZrm_Intkz:
7217
0
  case VDIVSSZrr_Int:
7218
0
  case VDIVSSZrr_Intk:
7219
0
  case VDIVSSZrr_Intkz:
7220
0
  case VDIVSSZrrb_Int:
7221
0
  case VDIVSSZrrb_Intk:
7222
0
  case VDIVSSZrrb_Intkz:
7223
0
  case VDIVSSrm_Int:
7224
0
  case VDIVSSrr_Int:
7225
0
    return true;
7226
0
  }
7227
0
  return false;
7228
0
}
7229
7230
0
bool isVPSRLQ(unsigned Opcode) {
7231
0
  switch (Opcode) {
7232
0
  case VPSRLQYri:
7233
0
  case VPSRLQYrm:
7234
0
  case VPSRLQYrr:
7235
0
  case VPSRLQZ128mbi:
7236
0
  case VPSRLQZ128mbik:
7237
0
  case VPSRLQZ128mbikz:
7238
0
  case VPSRLQZ128mi:
7239
0
  case VPSRLQZ128mik:
7240
0
  case VPSRLQZ128mikz:
7241
0
  case VPSRLQZ128ri:
7242
0
  case VPSRLQZ128rik:
7243
0
  case VPSRLQZ128rikz:
7244
0
  case VPSRLQZ128rm:
7245
0
  case VPSRLQZ128rmk:
7246
0
  case VPSRLQZ128rmkz:
7247
0
  case VPSRLQZ128rr:
7248
0
  case VPSRLQZ128rrk:
7249
0
  case VPSRLQZ128rrkz:
7250
0
  case VPSRLQZ256mbi:
7251
0
  case VPSRLQZ256mbik:
7252
0
  case VPSRLQZ256mbikz:
7253
0
  case VPSRLQZ256mi:
7254
0
  case VPSRLQZ256mik:
7255
0
  case VPSRLQZ256mikz:
7256
0
  case VPSRLQZ256ri:
7257
0
  case VPSRLQZ256rik:
7258
0
  case VPSRLQZ256rikz:
7259
0
  case VPSRLQZ256rm:
7260
0
  case VPSRLQZ256rmk:
7261
0
  case VPSRLQZ256rmkz:
7262
0
  case VPSRLQZ256rr:
7263
0
  case VPSRLQZ256rrk:
7264
0
  case VPSRLQZ256rrkz:
7265
0
  case VPSRLQZmbi:
7266
0
  case VPSRLQZmbik:
7267
0
  case VPSRLQZmbikz:
7268
0
  case VPSRLQZmi:
7269
0
  case VPSRLQZmik:
7270
0
  case VPSRLQZmikz:
7271
0
  case VPSRLQZri:
7272
0
  case VPSRLQZrik:
7273
0
  case VPSRLQZrikz:
7274
0
  case VPSRLQZrm:
7275
0
  case VPSRLQZrmk:
7276
0
  case VPSRLQZrmkz:
7277
0
  case VPSRLQZrr:
7278
0
  case VPSRLQZrrk:
7279
0
  case VPSRLQZrrkz:
7280
0
  case VPSRLQri:
7281
0
  case VPSRLQrm:
7282
0
  case VPSRLQrr:
7283
0
    return true;
7284
0
  }
7285
0
  return false;
7286
0
}
7287
7288
0
bool isFSQRT(unsigned Opcode) {
7289
0
  return Opcode == SQRT_F;
7290
0
}
7291
7292
0
bool isJRCXZ(unsigned Opcode) {
7293
0
  return Opcode == JRCXZ;
7294
0
}
7295
7296
0
bool isVPMOVMSKB(unsigned Opcode) {
7297
0
  switch (Opcode) {
7298
0
  case VPMOVMSKBYrr:
7299
0
  case VPMOVMSKBrr:
7300
0
    return true;
7301
0
  }
7302
0
  return false;
7303
0
}
7304
7305
0
bool isAESDEC256KL(unsigned Opcode) {
7306
0
  return Opcode == AESDEC256KL;
7307
0
}
7308
7309
0
bool isFLDENV(unsigned Opcode) {
7310
0
  return Opcode == FLDENVm;
7311
0
}
7312
7313
0
bool isVPHSUBWD(unsigned Opcode) {
7314
0
  switch (Opcode) {
7315
0
  case VPHSUBWDrm:
7316
0
  case VPHSUBWDrr:
7317
0
    return true;
7318
0
  }
7319
0
  return false;
7320
0
}
7321
7322
0
bool isWBNOINVD(unsigned Opcode) {
7323
0
  return Opcode == WBNOINVD;
7324
0
}
7325
7326
0
bool isVEXPANDPD(unsigned Opcode) {
7327
0
  switch (Opcode) {
7328
0
  case VEXPANDPDZ128rm:
7329
0
  case VEXPANDPDZ128rmk:
7330
0
  case VEXPANDPDZ128rmkz:
7331
0
  case VEXPANDPDZ128rr:
7332
0
  case VEXPANDPDZ128rrk:
7333
0
  case VEXPANDPDZ128rrkz:
7334
0
  case VEXPANDPDZ256rm:
7335
0
  case VEXPANDPDZ256rmk:
7336
0
  case VEXPANDPDZ256rmkz:
7337
0
  case VEXPANDPDZ256rr:
7338
0
  case VEXPANDPDZ256rrk:
7339
0
  case VEXPANDPDZ256rrkz:
7340
0
  case VEXPANDPDZrm:
7341
0
  case VEXPANDPDZrmk:
7342
0
  case VEXPANDPDZrmkz:
7343
0
  case VEXPANDPDZrr:
7344
0
  case VEXPANDPDZrrk:
7345
0
  case VEXPANDPDZrrkz:
7346
0
    return true;
7347
0
  }
7348
0
  return false;
7349
0
}
7350
7351
0
bool isFYL2XP1(unsigned Opcode) {
7352
0
  return Opcode == FYL2XP1;
7353
0
}
7354
7355
0
bool isPREFETCHT2(unsigned Opcode) {
7356
0
  return Opcode == PREFETCHT2;
7357
0
}
7358
7359
0
bool isVPDPBSUDS(unsigned Opcode) {
7360
0
  switch (Opcode) {
7361
0
  case VPDPBSUDSYrm:
7362
0
  case VPDPBSUDSYrr:
7363
0
  case VPDPBSUDSrm:
7364
0
  case VPDPBSUDSrr:
7365
0
    return true;
7366
0
  }
7367
0
  return false;
7368
0
}
7369
7370
0
bool isVSHA512MSG2(unsigned Opcode) {
7371
0
  return Opcode == VSHA512MSG2rr;
7372
0
}
7373
7374
0
bool isPMULHUW(unsigned Opcode) {
7375
0
  switch (Opcode) {
7376
0
  case MMX_PMULHUWrm:
7377
0
  case MMX_PMULHUWrr:
7378
0
  case PMULHUWrm:
7379
0
  case PMULHUWrr:
7380
0
    return true;
7381
0
  }
7382
0
  return false;
7383
0
}
7384
7385
0
bool isKANDNB(unsigned Opcode) {
7386
0
  return Opcode == KANDNBrr;
7387
0
}
7388
7389
0
bool isVCVTUW2PH(unsigned Opcode) {
7390
0
  switch (Opcode) {
7391
0
  case VCVTUW2PHZ128rm:
7392
0
  case VCVTUW2PHZ128rmb:
7393
0
  case VCVTUW2PHZ128rmbk:
7394
0
  case VCVTUW2PHZ128rmbkz:
7395
0
  case VCVTUW2PHZ128rmk:
7396
0
  case VCVTUW2PHZ128rmkz:
7397
0
  case VCVTUW2PHZ128rr:
7398
0
  case VCVTUW2PHZ128rrk:
7399
0
  case VCVTUW2PHZ128rrkz:
7400
0
  case VCVTUW2PHZ256rm:
7401
0
  case VCVTUW2PHZ256rmb:
7402
0
  case VCVTUW2PHZ256rmbk:
7403
0
  case VCVTUW2PHZ256rmbkz:
7404
0
  case VCVTUW2PHZ256rmk:
7405
0
  case VCVTUW2PHZ256rmkz:
7406
0
  case VCVTUW2PHZ256rr:
7407
0
  case VCVTUW2PHZ256rrk:
7408
0
  case VCVTUW2PHZ256rrkz:
7409
0
  case VCVTUW2PHZrm:
7410
0
  case VCVTUW2PHZrmb:
7411
0
  case VCVTUW2PHZrmbk:
7412
0
  case VCVTUW2PHZrmbkz:
7413
0
  case VCVTUW2PHZrmk:
7414
0
  case VCVTUW2PHZrmkz:
7415
0
  case VCVTUW2PHZrr:
7416
0
  case VCVTUW2PHZrrb:
7417
0
  case VCVTUW2PHZrrbk:
7418
0
  case VCVTUW2PHZrrbkz:
7419
0
  case VCVTUW2PHZrrk:
7420
0
  case VCVTUW2PHZrrkz:
7421
0
    return true;
7422
0
  }
7423
0
  return false;
7424
0
}
7425
7426
0
bool isAESDECWIDE256KL(unsigned Opcode) {
7427
0
  return Opcode == AESDECWIDE256KL;
7428
0
}
7429
7430
0
bool isVPGATHERDD(unsigned Opcode) {
7431
0
  switch (Opcode) {
7432
0
  case VPGATHERDDYrm:
7433
0
  case VPGATHERDDZ128rm:
7434
0
  case VPGATHERDDZ256rm:
7435
0
  case VPGATHERDDZrm:
7436
0
  case VPGATHERDDrm:
7437
0
    return true;
7438
0
  }
7439
0
  return false;
7440
0
}
7441
7442
0
bool isVREDUCESH(unsigned Opcode) {
7443
0
  switch (Opcode) {
7444
0
  case VREDUCESHZrmi:
7445
0
  case VREDUCESHZrmik:
7446
0
  case VREDUCESHZrmikz:
7447
0
  case VREDUCESHZrri:
7448
0
  case VREDUCESHZrrib:
7449
0
  case VREDUCESHZrribk:
7450
0
  case VREDUCESHZrribkz:
7451
0
  case VREDUCESHZrrik:
7452
0
  case VREDUCESHZrrikz:
7453
0
    return true;
7454
0
  }
7455
0
  return false;
7456
0
}
7457
7458
0
bool isPOPFQ(unsigned Opcode) {
7459
0
  return Opcode == POPF64;
7460
0
}
7461
7462
0
bool isPAVGUSB(unsigned Opcode) {
7463
0
  switch (Opcode) {
7464
0
  case PAVGUSBrm:
7465
0
  case PAVGUSBrr:
7466
0
    return true;
7467
0
  }
7468
0
  return false;
7469
0
}
7470
7471
0
bool isVALIGND(unsigned Opcode) {
7472
0
  switch (Opcode) {
7473
0
  case VALIGNDZ128rmbi:
7474
0
  case VALIGNDZ128rmbik:
7475
0
  case VALIGNDZ128rmbikz:
7476
0
  case VALIGNDZ128rmi:
7477
0
  case VALIGNDZ128rmik:
7478
0
  case VALIGNDZ128rmikz:
7479
0
  case VALIGNDZ128rri:
7480
0
  case VALIGNDZ128rrik:
7481
0
  case VALIGNDZ128rrikz:
7482
0
  case VALIGNDZ256rmbi:
7483
0
  case VALIGNDZ256rmbik:
7484
0
  case VALIGNDZ256rmbikz:
7485
0
  case VALIGNDZ256rmi:
7486
0
  case VALIGNDZ256rmik:
7487
0
  case VALIGNDZ256rmikz:
7488
0
  case VALIGNDZ256rri:
7489
0
  case VALIGNDZ256rrik:
7490
0
  case VALIGNDZ256rrikz:
7491
0
  case VALIGNDZrmbi:
7492
0
  case VALIGNDZrmbik:
7493
0
  case VALIGNDZrmbikz:
7494
0
  case VALIGNDZrmi:
7495
0
  case VALIGNDZrmik:
7496
0
  case VALIGNDZrmikz:
7497
0
  case VALIGNDZrri:
7498
0
  case VALIGNDZrrik:
7499
0
  case VALIGNDZrrikz:
7500
0
    return true;
7501
0
  }
7502
0
  return false;
7503
0
}
7504
7505
0
bool isVPHMINPOSUW(unsigned Opcode) {
7506
0
  switch (Opcode) {
7507
0
  case VPHMINPOSUWrm:
7508
0
  case VPHMINPOSUWrr:
7509
0
    return true;
7510
0
  }
7511
0
  return false;
7512
0
}
7513
7514
0
bool isLIDTD(unsigned Opcode) {
7515
0
  return Opcode == LIDT32m;
7516
0
}
7517
7518
0
bool isVPERMT2PD(unsigned Opcode) {
7519
0
  switch (Opcode) {
7520
0
  case VPERMT2PDZ128rm:
7521
0
  case VPERMT2PDZ128rmb:
7522
0
  case VPERMT2PDZ128rmbk:
7523
0
  case VPERMT2PDZ128rmbkz:
7524
0
  case VPERMT2PDZ128rmk:
7525
0
  case VPERMT2PDZ128rmkz:
7526
0
  case VPERMT2PDZ128rr:
7527
0
  case VPERMT2PDZ128rrk:
7528
0
  case VPERMT2PDZ128rrkz:
7529
0
  case VPERMT2PDZ256rm:
7530
0
  case VPERMT2PDZ256rmb:
7531
0
  case VPERMT2PDZ256rmbk:
7532
0
  case VPERMT2PDZ256rmbkz:
7533
0
  case VPERMT2PDZ256rmk:
7534
0
  case VPERMT2PDZ256rmkz:
7535
0
  case VPERMT2PDZ256rr:
7536
0
  case VPERMT2PDZ256rrk:
7537
0
  case VPERMT2PDZ256rrkz:
7538
0
  case VPERMT2PDZrm:
7539
0
  case VPERMT2PDZrmb:
7540
0
  case VPERMT2PDZrmbk:
7541
0
  case VPERMT2PDZrmbkz:
7542
0
  case VPERMT2PDZrmk:
7543
0
  case VPERMT2PDZrmkz:
7544
0
  case VPERMT2PDZrr:
7545
0
  case VPERMT2PDZrrk:
7546
0
  case VPERMT2PDZrrkz:
7547
0
    return true;
7548
0
  }
7549
0
  return false;
7550
0
}
7551
7552
0
bool isVMLAUNCH(unsigned Opcode) {
7553
0
  return Opcode == VMLAUNCH;
7554
0
}
7555
7556
0
bool isVPXORQ(unsigned Opcode) {
7557
0
  switch (Opcode) {
7558
0
  case VPXORQZ128rm:
7559
0
  case VPXORQZ128rmb:
7560
0
  case VPXORQZ128rmbk:
7561
0
  case VPXORQZ128rmbkz:
7562
0
  case VPXORQZ128rmk:
7563
0
  case VPXORQZ128rmkz:
7564
0
  case VPXORQZ128rr:
7565
0
  case VPXORQZ128rrk:
7566
0
  case VPXORQZ128rrkz:
7567
0
  case VPXORQZ256rm:
7568
0
  case VPXORQZ256rmb:
7569
0
  case VPXORQZ256rmbk:
7570
0
  case VPXORQZ256rmbkz:
7571
0
  case VPXORQZ256rmk:
7572
0
  case VPXORQZ256rmkz:
7573
0
  case VPXORQZ256rr:
7574
0
  case VPXORQZ256rrk:
7575
0
  case VPXORQZ256rrkz:
7576
0
  case VPXORQZrm:
7577
0
  case VPXORQZrmb:
7578
0
  case VPXORQZrmbk:
7579
0
  case VPXORQZrmbkz:
7580
0
  case VPXORQZrmk:
7581
0
  case VPXORQZrmkz:
7582
0
  case VPXORQZrr:
7583
0
  case VPXORQZrrk:
7584
0
  case VPXORQZrrkz:
7585
0
    return true;
7586
0
  }
7587
0
  return false;
7588
0
}
7589
7590
0
bool isMOVNTDQ(unsigned Opcode) {
7591
0
  return Opcode == MOVNTDQmr;
7592
0
}
7593
7594
0
bool isPOP2P(unsigned Opcode) {
7595
0
  return Opcode == POP2P;
7596
0
}
7597
7598
0
bool isVADDPD(unsigned Opcode) {
7599
0
  switch (Opcode) {
7600
0
  case VADDPDYrm:
7601
0
  case VADDPDYrr:
7602
0
  case VADDPDZ128rm:
7603
0
  case VADDPDZ128rmb:
7604
0
  case VADDPDZ128rmbk:
7605
0
  case VADDPDZ128rmbkz:
7606
0
  case VADDPDZ128rmk:
7607
0
  case VADDPDZ128rmkz:
7608
0
  case VADDPDZ128rr:
7609
0
  case VADDPDZ128rrk:
7610
0
  case VADDPDZ128rrkz:
7611
0
  case VADDPDZ256rm:
7612
0
  case VADDPDZ256rmb:
7613
0
  case VADDPDZ256rmbk:
7614
0
  case VADDPDZ256rmbkz:
7615
0
  case VADDPDZ256rmk:
7616
0
  case VADDPDZ256rmkz:
7617
0
  case VADDPDZ256rr:
7618
0
  case VADDPDZ256rrk:
7619
0
  case VADDPDZ256rrkz:
7620
0
  case VADDPDZrm:
7621
0
  case VADDPDZrmb:
7622
0
  case VADDPDZrmbk:
7623
0
  case VADDPDZrmbkz:
7624
0
  case VADDPDZrmk:
7625
0
  case VADDPDZrmkz:
7626
0
  case VADDPDZrr:
7627
0
  case VADDPDZrrb:
7628
0
  case VADDPDZrrbk:
7629
0
  case VADDPDZrrbkz:
7630
0
  case VADDPDZrrk:
7631
0
  case VADDPDZrrkz:
7632
0
  case VADDPDrm:
7633
0
  case VADDPDrr:
7634
0
    return true;
7635
0
  }
7636
0
  return false;
7637
0
}
7638
7639
0
bool isSMSW(unsigned Opcode) {
7640
0
  switch (Opcode) {
7641
0
  case SMSW16m:
7642
0
  case SMSW16r:
7643
0
  case SMSW32r:
7644
0
  case SMSW64r:
7645
0
    return true;
7646
0
  }
7647
0
  return false;
7648
0
}
7649
7650
0
bool isVEXP2PD(unsigned Opcode) {
7651
0
  switch (Opcode) {
7652
0
  case VEXP2PDZm:
7653
0
  case VEXP2PDZmb:
7654
0
  case VEXP2PDZmbk:
7655
0
  case VEXP2PDZmbkz:
7656
0
  case VEXP2PDZmk:
7657
0
  case VEXP2PDZmkz:
7658
0
  case VEXP2PDZr:
7659
0
  case VEXP2PDZrb:
7660
0
  case VEXP2PDZrbk:
7661
0
  case VEXP2PDZrbkz:
7662
0
  case VEXP2PDZrk:
7663
0
  case VEXP2PDZrkz:
7664
0
    return true;
7665
0
  }
7666
0
  return false;
7667
0
}
7668
7669
0
bool isPMULUDQ(unsigned Opcode) {
7670
0
  switch (Opcode) {
7671
0
  case MMX_PMULUDQrm:
7672
0
  case MMX_PMULUDQrr:
7673
0
  case PMULUDQrm:
7674
0
  case PMULUDQrr:
7675
0
    return true;
7676
0
  }
7677
0
  return false;
7678
0
}
7679
7680
0
bool isIRET(unsigned Opcode) {
7681
0
  return Opcode == IRET16;
7682
0
}
7683
7684
0
bool isMULPS(unsigned Opcode) {
7685
0
  switch (Opcode) {
7686
0
  case MULPSrm:
7687
0
  case MULPSrr:
7688
0
    return true;
7689
0
  }
7690
0
  return false;
7691
0
}
7692
7693
0
bool isVFNMSUBPD(unsigned Opcode) {
7694
0
  switch (Opcode) {
7695
0
  case VFNMSUBPD4Ymr:
7696
0
  case VFNMSUBPD4Yrm:
7697
0
  case VFNMSUBPD4Yrr:
7698
0
  case VFNMSUBPD4Yrr_REV:
7699
0
  case VFNMSUBPD4mr:
7700
0
  case VFNMSUBPD4rm:
7701
0
  case VFNMSUBPD4rr:
7702
0
  case VFNMSUBPD4rr_REV:
7703
0
    return true;
7704
0
  }
7705
0
  return false;
7706
0
}
7707
7708
0
bool isPHADDW(unsigned Opcode) {
7709
0
  switch (Opcode) {
7710
0
  case MMX_PHADDWrm:
7711
0
  case MMX_PHADDWrr:
7712
0
  case PHADDWrm:
7713
0
  case PHADDWrr:
7714
0
    return true;
7715
0
  }
7716
0
  return false;
7717
0
}
7718
7719
0
bool isRDSEED(unsigned Opcode) {
7720
0
  switch (Opcode) {
7721
0
  case RDSEED16r:
7722
0
  case RDSEED32r:
7723
0
  case RDSEED64r:
7724
0
    return true;
7725
0
  }
7726
0
  return false;
7727
0
}
7728
7729
0
bool isVPSHLW(unsigned Opcode) {
7730
0
  switch (Opcode) {
7731
0
  case VPSHLWmr:
7732
0
  case VPSHLWrm:
7733
0
  case VPSHLWrr:
7734
0
  case VPSHLWrr_REV:
7735
0
    return true;
7736
0
  }
7737
0
  return false;
7738
0
}
7739
7740
0
bool isRMPUPDATE(unsigned Opcode) {
7741
0
  return Opcode == RMPUPDATE;
7742
0
}
7743
7744
0
bool isVFMADD231PH(unsigned Opcode) {
7745
0
  switch (Opcode) {
7746
0
  case VFMADD231PHZ128m:
7747
0
  case VFMADD231PHZ128mb:
7748
0
  case VFMADD231PHZ128mbk:
7749
0
  case VFMADD231PHZ128mbkz:
7750
0
  case VFMADD231PHZ128mk:
7751
0
  case VFMADD231PHZ128mkz:
7752
0
  case VFMADD231PHZ128r:
7753
0
  case VFMADD231PHZ128rk:
7754
0
  case VFMADD231PHZ128rkz:
7755
0
  case VFMADD231PHZ256m:
7756
0
  case VFMADD231PHZ256mb:
7757
0
  case VFMADD231PHZ256mbk:
7758
0
  case VFMADD231PHZ256mbkz:
7759
0
  case VFMADD231PHZ256mk:
7760
0
  case VFMADD231PHZ256mkz:
7761
0
  case VFMADD231PHZ256r:
7762
0
  case VFMADD231PHZ256rk:
7763
0
  case VFMADD231PHZ256rkz:
7764
0
  case VFMADD231PHZm:
7765
0
  case VFMADD231PHZmb:
7766
0
  case VFMADD231PHZmbk:
7767
0
  case VFMADD231PHZmbkz:
7768
0
  case VFMADD231PHZmk:
7769
0
  case VFMADD231PHZmkz:
7770
0
  case VFMADD231PHZr:
7771
0
  case VFMADD231PHZrb:
7772
0
  case VFMADD231PHZrbk:
7773
0
  case VFMADD231PHZrbkz:
7774
0
  case VFMADD231PHZrk:
7775
0
  case VFMADD231PHZrkz:
7776
0
    return true;
7777
0
  }
7778
0
  return false;
7779
0
}
7780
7781
0
bool isVPSHAD(unsigned Opcode) {
7782
0
  switch (Opcode) {
7783
0
  case VPSHADmr:
7784
0
  case VPSHADrm:
7785
0
  case VPSHADrr:
7786
0
  case VPSHADrr_REV:
7787
0
    return true;
7788
0
  }
7789
0
  return false;
7790
0
}
7791
7792
0
bool isCLWB(unsigned Opcode) {
7793
0
  return Opcode == CLWB;
7794
0
}
7795
7796
0
bool isPSUBUSB(unsigned Opcode) {
7797
0
  switch (Opcode) {
7798
0
  case MMX_PSUBUSBrm:
7799
0
  case MMX_PSUBUSBrr:
7800
0
  case PSUBUSBrm:
7801
0
  case PSUBUSBrr:
7802
0
    return true;
7803
0
  }
7804
0
  return false;
7805
0
}
7806
7807
0
bool isVCVTTSD2USI(unsigned Opcode) {
7808
0
  switch (Opcode) {
7809
0
  case VCVTTSD2USI64Zrm_Int:
7810
0
  case VCVTTSD2USI64Zrr_Int:
7811
0
  case VCVTTSD2USI64Zrrb_Int:
7812
0
  case VCVTTSD2USIZrm_Int:
7813
0
  case VCVTTSD2USIZrr_Int:
7814
0
  case VCVTTSD2USIZrrb_Int:
7815
0
    return true;
7816
0
  }
7817
0
  return false;
7818
0
}
7819
7820
0
bool isVEXTRACTPS(unsigned Opcode) {
7821
0
  switch (Opcode) {
7822
0
  case VEXTRACTPSZmr:
7823
0
  case VEXTRACTPSZrr:
7824
0
  case VEXTRACTPSmr:
7825
0
  case VEXTRACTPSrr:
7826
0
    return true;
7827
0
  }
7828
0
  return false;
7829
0
}
7830
7831
0
bool isMOVLPD(unsigned Opcode) {
7832
0
  switch (Opcode) {
7833
0
  case MOVLPDmr:
7834
0
  case MOVLPDrm:
7835
0
    return true;
7836
0
  }
7837
0
  return false;
7838
0
}
7839
7840
0
bool isLGDTD(unsigned Opcode) {
7841
0
  return Opcode == LGDT32m;
7842
0
}
7843
7844
0
bool isVPBROADCASTMB2Q(unsigned Opcode) {
7845
0
  switch (Opcode) {
7846
0
  case VPBROADCASTMB2QZ128rr:
7847
0
  case VPBROADCASTMB2QZ256rr:
7848
0
  case VPBROADCASTMB2QZrr:
7849
0
    return true;
7850
0
  }
7851
0
  return false;
7852
0
}
7853
7854
0
bool isOUT(unsigned Opcode) {
7855
0
  switch (Opcode) {
7856
0
  case OUT16ir:
7857
0
  case OUT16rr:
7858
0
  case OUT32ir:
7859
0
  case OUT32rr:
7860
0
  case OUT8ir:
7861
0
  case OUT8rr:
7862
0
    return true;
7863
0
  }
7864
0
  return false;
7865
0
}
7866
7867
0
bool isVMSAVE(unsigned Opcode) {
7868
0
  switch (Opcode) {
7869
0
  case VMSAVE32:
7870
0
  case VMSAVE64:
7871
0
    return true;
7872
0
  }
7873
0
  return false;
7874
0
}
7875
7876
0
bool isVCVTQQ2PD(unsigned Opcode) {
7877
0
  switch (Opcode) {
7878
0
  case VCVTQQ2PDZ128rm:
7879
0
  case VCVTQQ2PDZ128rmb:
7880
0
  case VCVTQQ2PDZ128rmbk:
7881
0
  case VCVTQQ2PDZ128rmbkz:
7882
0
  case VCVTQQ2PDZ128rmk:
7883
0
  case VCVTQQ2PDZ128rmkz:
7884
0
  case VCVTQQ2PDZ128rr:
7885
0
  case VCVTQQ2PDZ128rrk:
7886
0
  case VCVTQQ2PDZ128rrkz:
7887
0
  case VCVTQQ2PDZ256rm:
7888
0
  case VCVTQQ2PDZ256rmb:
7889
0
  case VCVTQQ2PDZ256rmbk:
7890
0
  case VCVTQQ2PDZ256rmbkz:
7891
0
  case VCVTQQ2PDZ256rmk:
7892
0
  case VCVTQQ2PDZ256rmkz:
7893
0
  case VCVTQQ2PDZ256rr:
7894
0
  case VCVTQQ2PDZ256rrk:
7895
0
  case VCVTQQ2PDZ256rrkz:
7896
0
  case VCVTQQ2PDZrm:
7897
0
  case VCVTQQ2PDZrmb:
7898
0
  case VCVTQQ2PDZrmbk:
7899
0
  case VCVTQQ2PDZrmbkz:
7900
0
  case VCVTQQ2PDZrmk:
7901
0
  case VCVTQQ2PDZrmkz:
7902
0
  case VCVTQQ2PDZrr:
7903
0
  case VCVTQQ2PDZrrb:
7904
0
  case VCVTQQ2PDZrrbk:
7905
0
  case VCVTQQ2PDZrrbkz:
7906
0
  case VCVTQQ2PDZrrk:
7907
0
  case VCVTQQ2PDZrrkz:
7908
0
    return true;
7909
0
  }
7910
0
  return false;
7911
0
}
7912
7913
0
bool isVFMADD213PH(unsigned Opcode) {
7914
0
  switch (Opcode) {
7915
0
  case VFMADD213PHZ128m:
7916
0
  case VFMADD213PHZ128mb:
7917
0
  case VFMADD213PHZ128mbk:
7918
0
  case VFMADD213PHZ128mbkz:
7919
0
  case VFMADD213PHZ128mk:
7920
0
  case VFMADD213PHZ128mkz:
7921
0
  case VFMADD213PHZ128r:
7922
0
  case VFMADD213PHZ128rk:
7923
0
  case VFMADD213PHZ128rkz:
7924
0
  case VFMADD213PHZ256m:
7925
0
  case VFMADD213PHZ256mb:
7926
0
  case VFMADD213PHZ256mbk:
7927
0
  case VFMADD213PHZ256mbkz:
7928
0
  case VFMADD213PHZ256mk:
7929
0
  case VFMADD213PHZ256mkz:
7930
0
  case VFMADD213PHZ256r:
7931
0
  case VFMADD213PHZ256rk:
7932
0
  case VFMADD213PHZ256rkz:
7933
0
  case VFMADD213PHZm:
7934
0
  case VFMADD213PHZmb:
7935
0
  case VFMADD213PHZmbk:
7936
0
  case VFMADD213PHZmbkz:
7937
0
  case VFMADD213PHZmk:
7938
0
  case VFMADD213PHZmkz:
7939
0
  case VFMADD213PHZr:
7940
0
  case VFMADD213PHZrb:
7941
0
  case VFMADD213PHZrbk:
7942
0
  case VFMADD213PHZrbkz:
7943
0
  case VFMADD213PHZrk:
7944
0
  case VFMADD213PHZrkz:
7945
0
    return true;
7946
0
  }
7947
0
  return false;
7948
0
}
7949
7950
0
bool isFCMOVBE(unsigned Opcode) {
7951
0
  return Opcode == CMOVBE_F;
7952
0
}
7953
7954
0
bool isMOVSHDUP(unsigned Opcode) {
7955
0
  switch (Opcode) {
7956
0
  case MOVSHDUPrm:
7957
0
  case MOVSHDUPrr:
7958
0
    return true;
7959
0
  }
7960
0
  return false;
7961
0
}
7962
7963
0
bool isVPMOVUSQB(unsigned Opcode) {
7964
0
  switch (Opcode) {
7965
0
  case VPMOVUSQBZ128mr:
7966
0
  case VPMOVUSQBZ128mrk:
7967
0
  case VPMOVUSQBZ128rr:
7968
0
  case VPMOVUSQBZ128rrk:
7969
0
  case VPMOVUSQBZ128rrkz:
7970
0
  case VPMOVUSQBZ256mr:
7971
0
  case VPMOVUSQBZ256mrk:
7972
0
  case VPMOVUSQBZ256rr:
7973
0
  case VPMOVUSQBZ256rrk:
7974
0
  case VPMOVUSQBZ256rrkz:
7975
0
  case VPMOVUSQBZmr:
7976
0
  case VPMOVUSQBZmrk:
7977
0
  case VPMOVUSQBZrr:
7978
0
  case VPMOVUSQBZrrk:
7979
0
  case VPMOVUSQBZrrkz:
7980
0
    return true;
7981
0
  }
7982
0
  return false;
7983
0
}
7984
7985
0
bool isFIST(unsigned Opcode) {
7986
0
  switch (Opcode) {
7987
0
  case IST_F16m:
7988
0
  case IST_F32m:
7989
0
    return true;
7990
0
  }
7991
0
  return false;
7992
0
}
7993
7994
0
bool isHADDPD(unsigned Opcode) {
7995
0
  switch (Opcode) {
7996
0
  case HADDPDrm:
7997
0
  case HADDPDrr:
7998
0
    return true;
7999
0
  }
8000
0
  return false;
8001
0
}
8002
8003
0
bool isPACKSSWB(unsigned Opcode) {
8004
0
  switch (Opcode) {
8005
0
  case MMX_PACKSSWBrm:
8006
0
  case MMX_PACKSSWBrr:
8007
0
  case PACKSSWBrm:
8008
0
  case PACKSSWBrr:
8009
0
    return true;
8010
0
  }
8011
0
  return false;
8012
0
}
8013
8014
0
bool isVPMACSSDQH(unsigned Opcode) {
8015
0
  switch (Opcode) {
8016
0
  case VPMACSSDQHrm:
8017
0
  case VPMACSSDQHrr:
8018
0
    return true;
8019
0
  }
8020
0
  return false;
8021
0
}
8022
8023
0
bool isVFNMSUB132SD(unsigned Opcode) {
8024
0
  switch (Opcode) {
8025
0
  case VFNMSUB132SDZm_Int:
8026
0
  case VFNMSUB132SDZm_Intk:
8027
0
  case VFNMSUB132SDZm_Intkz:
8028
0
  case VFNMSUB132SDZr_Int:
8029
0
  case VFNMSUB132SDZr_Intk:
8030
0
  case VFNMSUB132SDZr_Intkz:
8031
0
  case VFNMSUB132SDZrb_Int:
8032
0
  case VFNMSUB132SDZrb_Intk:
8033
0
  case VFNMSUB132SDZrb_Intkz:
8034
0
  case VFNMSUB132SDm_Int:
8035
0
  case VFNMSUB132SDr_Int:
8036
0
    return true;
8037
0
  }
8038
0
  return false;
8039
0
}
8040
8041
0
bool isVPMASKMOVQ(unsigned Opcode) {
8042
0
  switch (Opcode) {
8043
0
  case VPMASKMOVQYmr:
8044
0
  case VPMASKMOVQYrm:
8045
0
  case VPMASKMOVQmr:
8046
0
  case VPMASKMOVQrm:
8047
0
    return true;
8048
0
  }
8049
0
  return false;
8050
0
}
8051
8052
0
bool isVCOMPRESSPD(unsigned Opcode) {
8053
0
  switch (Opcode) {
8054
0
  case VCOMPRESSPDZ128mr:
8055
0
  case VCOMPRESSPDZ128mrk:
8056
0
  case VCOMPRESSPDZ128rr:
8057
0
  case VCOMPRESSPDZ128rrk:
8058
0
  case VCOMPRESSPDZ128rrkz:
8059
0
  case VCOMPRESSPDZ256mr:
8060
0
  case VCOMPRESSPDZ256mrk:
8061
0
  case VCOMPRESSPDZ256rr:
8062
0
  case VCOMPRESSPDZ256rrk:
8063
0
  case VCOMPRESSPDZ256rrkz:
8064
0
  case VCOMPRESSPDZmr:
8065
0
  case VCOMPRESSPDZmrk:
8066
0
  case VCOMPRESSPDZrr:
8067
0
  case VCOMPRESSPDZrrk:
8068
0
  case VCOMPRESSPDZrrkz:
8069
0
    return true;
8070
0
  }
8071
0
  return false;
8072
0
}
8073
8074
0
bool isVFMADD213SS(unsigned Opcode) {
8075
0
  switch (Opcode) {
8076
0
  case VFMADD213SSZm_Int:
8077
0
  case VFMADD213SSZm_Intk:
8078
0
  case VFMADD213SSZm_Intkz:
8079
0
  case VFMADD213SSZr_Int:
8080
0
  case VFMADD213SSZr_Intk:
8081
0
  case VFMADD213SSZr_Intkz:
8082
0
  case VFMADD213SSZrb_Int:
8083
0
  case VFMADD213SSZrb_Intk:
8084
0
  case VFMADD213SSZrb_Intkz:
8085
0
  case VFMADD213SSm_Int:
8086
0
  case VFMADD213SSr_Int:
8087
0
    return true;
8088
0
  }
8089
0
  return false;
8090
0
}
8091
8092
0
bool isVPCMPQ(unsigned Opcode) {
8093
0
  switch (Opcode) {
8094
0
  case VPCMPQZ128rmi:
8095
0
  case VPCMPQZ128rmib:
8096
0
  case VPCMPQZ128rmibk:
8097
0
  case VPCMPQZ128rmik:
8098
0
  case VPCMPQZ128rri:
8099
0
  case VPCMPQZ128rrik:
8100
0
  case VPCMPQZ256rmi:
8101
0
  case VPCMPQZ256rmib:
8102
0
  case VPCMPQZ256rmibk:
8103
0
  case VPCMPQZ256rmik:
8104
0
  case VPCMPQZ256rri:
8105
0
  case VPCMPQZ256rrik:
8106
0
  case VPCMPQZrmi:
8107
0
  case VPCMPQZrmib:
8108
0
  case VPCMPQZrmibk:
8109
0
  case VPCMPQZrmik:
8110
0
  case VPCMPQZrri:
8111
0
  case VPCMPQZrrik:
8112
0
    return true;
8113
0
  }
8114
0
  return false;
8115
0
}
8116
8117
0
bool isVADDSH(unsigned Opcode) {
8118
0
  switch (Opcode) {
8119
0
  case VADDSHZrm_Int:
8120
0
  case VADDSHZrm_Intk:
8121
0
  case VADDSHZrm_Intkz:
8122
0
  case VADDSHZrr_Int:
8123
0
  case VADDSHZrr_Intk:
8124
0
  case VADDSHZrr_Intkz:
8125
0
  case VADDSHZrrb_Int:
8126
0
  case VADDSHZrrb_Intk:
8127
0
  case VADDSHZrrb_Intkz:
8128
0
    return true;
8129
0
  }
8130
0
  return false;
8131
0
}
8132
8133
0
bool isVFNMADDSD(unsigned Opcode) {
8134
0
  switch (Opcode) {
8135
0
  case VFNMADDSD4mr:
8136
0
  case VFNMADDSD4rm:
8137
0
  case VFNMADDSD4rr:
8138
0
  case VFNMADDSD4rr_REV:
8139
0
    return true;
8140
0
  }
8141
0
  return false;
8142
0
}
8143
8144
0
bool isUMWAIT(unsigned Opcode) {
8145
0
  return Opcode == UMWAIT;
8146
0
}
8147
8148
0
bool isVPUNPCKHDQ(unsigned Opcode) {
8149
0
  switch (Opcode) {
8150
0
  case VPUNPCKHDQYrm:
8151
0
  case VPUNPCKHDQYrr:
8152
0
  case VPUNPCKHDQZ128rm:
8153
0
  case VPUNPCKHDQZ128rmb:
8154
0
  case VPUNPCKHDQZ128rmbk:
8155
0
  case VPUNPCKHDQZ128rmbkz:
8156
0
  case VPUNPCKHDQZ128rmk:
8157
0
  case VPUNPCKHDQZ128rmkz:
8158
0
  case VPUNPCKHDQZ128rr:
8159
0
  case VPUNPCKHDQZ128rrk:
8160
0
  case VPUNPCKHDQZ128rrkz:
8161
0
  case VPUNPCKHDQZ256rm:
8162
0
  case VPUNPCKHDQZ256rmb:
8163
0
  case VPUNPCKHDQZ256rmbk:
8164
0
  case VPUNPCKHDQZ256rmbkz:
8165
0
  case VPUNPCKHDQZ256rmk:
8166
0
  case VPUNPCKHDQZ256rmkz:
8167
0
  case VPUNPCKHDQZ256rr:
8168
0
  case VPUNPCKHDQZ256rrk:
8169
0
  case VPUNPCKHDQZ256rrkz:
8170
0
  case VPUNPCKHDQZrm:
8171
0
  case VPUNPCKHDQZrmb:
8172
0
  case VPUNPCKHDQZrmbk:
8173
0
  case VPUNPCKHDQZrmbkz:
8174
0
  case VPUNPCKHDQZrmk:
8175
0
  case VPUNPCKHDQZrmkz:
8176
0
  case VPUNPCKHDQZrr:
8177
0
  case VPUNPCKHDQZrrk:
8178
0
  case VPUNPCKHDQZrrkz:
8179
0
  case VPUNPCKHDQrm:
8180
0
  case VPUNPCKHDQrr:
8181
0
    return true;
8182
0
  }
8183
0
  return false;
8184
0
}
8185
8186
0
bool isLCALL(unsigned Opcode) {
8187
0
  switch (Opcode) {
8188
0
  case FARCALL16i:
8189
0
  case FARCALL16m:
8190
0
  case FARCALL32i:
8191
0
  case FARCALL64m:
8192
0
    return true;
8193
0
  }
8194
0
  return false;
8195
0
}
8196
8197
0
bool isAESDEC128KL(unsigned Opcode) {
8198
0
  return Opcode == AESDEC128KL;
8199
0
}
8200
8201
0
bool isVSUBPS(unsigned Opcode) {
8202
0
  switch (Opcode) {
8203
0
  case VSUBPSYrm:
8204
0
  case VSUBPSYrr:
8205
0
  case VSUBPSZ128rm:
8206
0
  case VSUBPSZ128rmb:
8207
0
  case VSUBPSZ128rmbk:
8208
0
  case VSUBPSZ128rmbkz:
8209
0
  case VSUBPSZ128rmk:
8210
0
  case VSUBPSZ128rmkz:
8211
0
  case VSUBPSZ128rr:
8212
0
  case VSUBPSZ128rrk:
8213
0
  case VSUBPSZ128rrkz:
8214
0
  case VSUBPSZ256rm:
8215
0
  case VSUBPSZ256rmb:
8216
0
  case VSUBPSZ256rmbk:
8217
0
  case VSUBPSZ256rmbkz:
8218
0
  case VSUBPSZ256rmk:
8219
0
  case VSUBPSZ256rmkz:
8220
0
  case VSUBPSZ256rr:
8221
0
  case VSUBPSZ256rrk:
8222
0
  case VSUBPSZ256rrkz:
8223
0
  case VSUBPSZrm:
8224
0
  case VSUBPSZrmb:
8225
0
  case VSUBPSZrmbk:
8226
0
  case VSUBPSZrmbkz:
8227
0
  case VSUBPSZrmk:
8228
0
  case VSUBPSZrmkz:
8229
0
  case VSUBPSZrr:
8230
0
  case VSUBPSZrrb:
8231
0
  case VSUBPSZrrbk:
8232
0
  case VSUBPSZrrbkz:
8233
0
  case VSUBPSZrrk:
8234
0
  case VSUBPSZrrkz:
8235
0
  case VSUBPSrm:
8236
0
  case VSUBPSrr:
8237
0
    return true;
8238
0
  }
8239
0
  return false;
8240
0
}
8241
8242
0
bool isFSTP(unsigned Opcode) {
8243
0
  switch (Opcode) {
8244
0
  case ST_FP32m:
8245
0
  case ST_FP64m:
8246
0
  case ST_FP80m:
8247
0
  case ST_FPrr:
8248
0
    return true;
8249
0
  }
8250
0
  return false;
8251
0
}
8252
8253
0
bool isVCVTUDQ2PD(unsigned Opcode) {
8254
0
  switch (Opcode) {
8255
0
  case VCVTUDQ2PDZ128rm:
8256
0
  case VCVTUDQ2PDZ128rmb:
8257
0
  case VCVTUDQ2PDZ128rmbk:
8258
0
  case VCVTUDQ2PDZ128rmbkz:
8259
0
  case VCVTUDQ2PDZ128rmk:
8260
0
  case VCVTUDQ2PDZ128rmkz:
8261
0
  case VCVTUDQ2PDZ128rr:
8262
0
  case VCVTUDQ2PDZ128rrk:
8263
0
  case VCVTUDQ2PDZ128rrkz:
8264
0
  case VCVTUDQ2PDZ256rm:
8265
0
  case VCVTUDQ2PDZ256rmb:
8266
0
  case VCVTUDQ2PDZ256rmbk:
8267
0
  case VCVTUDQ2PDZ256rmbkz:
8268
0
  case VCVTUDQ2PDZ256rmk:
8269
0
  case VCVTUDQ2PDZ256rmkz:
8270
0
  case VCVTUDQ2PDZ256rr:
8271
0
  case VCVTUDQ2PDZ256rrk:
8272
0
  case VCVTUDQ2PDZ256rrkz:
8273
0
  case VCVTUDQ2PDZrm:
8274
0
  case VCVTUDQ2PDZrmb:
8275
0
  case VCVTUDQ2PDZrmbk:
8276
0
  case VCVTUDQ2PDZrmbkz:
8277
0
  case VCVTUDQ2PDZrmk:
8278
0
  case VCVTUDQ2PDZrmkz:
8279
0
  case VCVTUDQ2PDZrr:
8280
0
  case VCVTUDQ2PDZrrk:
8281
0
  case VCVTUDQ2PDZrrkz:
8282
0
    return true;
8283
0
  }
8284
0
  return false;
8285
0
}
8286
8287
0
bool isVPMOVSWB(unsigned Opcode) {
8288
0
  switch (Opcode) {
8289
0
  case VPMOVSWBZ128mr:
8290
0
  case VPMOVSWBZ128mrk:
8291
0
  case VPMOVSWBZ128rr:
8292
0
  case VPMOVSWBZ128rrk:
8293
0
  case VPMOVSWBZ128rrkz:
8294
0
  case VPMOVSWBZ256mr:
8295
0
  case VPMOVSWBZ256mrk:
8296
0
  case VPMOVSWBZ256rr:
8297
0
  case VPMOVSWBZ256rrk:
8298
0
  case VPMOVSWBZ256rrkz:
8299
0
  case VPMOVSWBZmr:
8300
0
  case VPMOVSWBZmrk:
8301
0
  case VPMOVSWBZrr:
8302
0
  case VPMOVSWBZrrk:
8303
0
  case VPMOVSWBZrrkz:
8304
0
    return true;
8305
0
  }
8306
0
  return false;
8307
0
}
8308
8309
0
bool isVPANDNQ(unsigned Opcode) {
8310
0
  switch (Opcode) {
8311
0
  case VPANDNQZ128rm:
8312
0
  case VPANDNQZ128rmb:
8313
0
  case VPANDNQZ128rmbk:
8314
0
  case VPANDNQZ128rmbkz:
8315
0
  case VPANDNQZ128rmk:
8316
0
  case VPANDNQZ128rmkz:
8317
0
  case VPANDNQZ128rr:
8318
0
  case VPANDNQZ128rrk:
8319
0
  case VPANDNQZ128rrkz:
8320
0
  case VPANDNQZ256rm:
8321
0
  case VPANDNQZ256rmb:
8322
0
  case VPANDNQZ256rmbk:
8323
0
  case VPANDNQZ256rmbkz:
8324
0
  case VPANDNQZ256rmk:
8325
0
  case VPANDNQZ256rmkz:
8326
0
  case VPANDNQZ256rr:
8327
0
  case VPANDNQZ256rrk:
8328
0
  case VPANDNQZ256rrkz:
8329
0
  case VPANDNQZrm:
8330
0
  case VPANDNQZrmb:
8331
0
  case VPANDNQZrmbk:
8332
0
  case VPANDNQZrmbkz:
8333
0
  case VPANDNQZrmk:
8334
0
  case VPANDNQZrmkz:
8335
0
  case VPANDNQZrr:
8336
0
  case VPANDNQZrrk:
8337
0
  case VPANDNQZrrkz:
8338
0
    return true;
8339
0
  }
8340
0
  return false;
8341
0
}
8342
8343
0
bool isSYSENTER(unsigned Opcode) {
8344
0
  return Opcode == SYSENTER;
8345
0
}
8346
8347
0
bool isVPHADDWD(unsigned Opcode) {
8348
0
  switch (Opcode) {
8349
0
  case VPHADDWDrm:
8350
0
  case VPHADDWDrr:
8351
0
    return true;
8352
0
  }
8353
0
  return false;
8354
0
}
8355
8356
0
bool isVMOVHPD(unsigned Opcode) {
8357
0
  switch (Opcode) {
8358
0
  case VMOVHPDZ128mr:
8359
0
  case VMOVHPDZ128rm:
8360
0
  case VMOVHPDmr:
8361
0
  case VMOVHPDrm:
8362
0
    return true;
8363
0
  }
8364
0
  return false;
8365
0
}
8366
8367
0
bool isMOVHPD(unsigned Opcode) {
8368
0
  switch (Opcode) {
8369
0
  case MOVHPDmr:
8370
0
  case MOVHPDrm:
8371
0
    return true;
8372
0
  }
8373
0
  return false;
8374
0
}
8375
8376
0
bool isVDIVPH(unsigned Opcode) {
8377
0
  switch (Opcode) {
8378
0
  case VDIVPHZ128rm:
8379
0
  case VDIVPHZ128rmb:
8380
0
  case VDIVPHZ128rmbk:
8381
0
  case VDIVPHZ128rmbkz:
8382
0
  case VDIVPHZ128rmk:
8383
0
  case VDIVPHZ128rmkz:
8384
0
  case VDIVPHZ128rr:
8385
0
  case VDIVPHZ128rrk:
8386
0
  case VDIVPHZ128rrkz:
8387
0
  case VDIVPHZ256rm:
8388
0
  case VDIVPHZ256rmb:
8389
0
  case VDIVPHZ256rmbk:
8390
0
  case VDIVPHZ256rmbkz:
8391
0
  case VDIVPHZ256rmk:
8392
0
  case VDIVPHZ256rmkz:
8393
0
  case VDIVPHZ256rr:
8394
0
  case VDIVPHZ256rrk:
8395
0
  case VDIVPHZ256rrkz:
8396
0
  case VDIVPHZrm:
8397
0
  case VDIVPHZrmb:
8398
0
  case VDIVPHZrmbk:
8399
0
  case VDIVPHZrmbkz:
8400
0
  case VDIVPHZrmk:
8401
0
  case VDIVPHZrmkz:
8402
0
  case VDIVPHZrr:
8403
0
  case VDIVPHZrrb:
8404
0
  case VDIVPHZrrbk:
8405
0
  case VDIVPHZrrbkz:
8406
0
  case VDIVPHZrrk:
8407
0
  case VDIVPHZrrkz:
8408
0
    return true;
8409
0
  }
8410
0
  return false;
8411
0
}
8412
8413
0
bool isFFREE(unsigned Opcode) {
8414
0
  return Opcode == FFREE;
8415
0
}
8416
8417
0
bool isVGATHERPF1DPS(unsigned Opcode) {
8418
0
  return Opcode == VGATHERPF1DPSm;
8419
0
}
8420
8421
0
bool isVFNMADD231PD(unsigned Opcode) {
8422
0
  switch (Opcode) {
8423
0
  case VFNMADD231PDYm:
8424
0
  case VFNMADD231PDYr:
8425
0
  case VFNMADD231PDZ128m:
8426
0
  case VFNMADD231PDZ128mb:
8427
0
  case VFNMADD231PDZ128mbk:
8428
0
  case VFNMADD231PDZ128mbkz:
8429
0
  case VFNMADD231PDZ128mk:
8430
0
  case VFNMADD231PDZ128mkz:
8431
0
  case VFNMADD231PDZ128r:
8432
0
  case VFNMADD231PDZ128rk:
8433
0
  case VFNMADD231PDZ128rkz:
8434
0
  case VFNMADD231PDZ256m:
8435
0
  case VFNMADD231PDZ256mb:
8436
0
  case VFNMADD231PDZ256mbk:
8437
0
  case VFNMADD231PDZ256mbkz:
8438
0
  case VFNMADD231PDZ256mk:
8439
0
  case VFNMADD231PDZ256mkz:
8440
0
  case VFNMADD231PDZ256r:
8441
0
  case VFNMADD231PDZ256rk:
8442
0
  case VFNMADD231PDZ256rkz:
8443
0
  case VFNMADD231PDZm:
8444
0
  case VFNMADD231PDZmb:
8445
0
  case VFNMADD231PDZmbk:
8446
0
  case VFNMADD231PDZmbkz:
8447
0
  case VFNMADD231PDZmk:
8448
0
  case VFNMADD231PDZmkz:
8449
0
  case VFNMADD231PDZr:
8450
0
  case VFNMADD231PDZrb:
8451
0
  case VFNMADD231PDZrbk:
8452
0
  case VFNMADD231PDZrbkz:
8453
0
  case VFNMADD231PDZrk:
8454
0
  case VFNMADD231PDZrkz:
8455
0
  case VFNMADD231PDm:
8456
0
  case VFNMADD231PDr:
8457
0
    return true;
8458
0
  }
8459
0
  return false;
8460
0
}
8461
8462
0
bool isVFCMULCPH(unsigned Opcode) {
8463
0
  switch (Opcode) {
8464
0
  case VFCMULCPHZ128rm:
8465
0
  case VFCMULCPHZ128rmb:
8466
0
  case VFCMULCPHZ128rmbk:
8467
0
  case VFCMULCPHZ128rmbkz:
8468
0
  case VFCMULCPHZ128rmk:
8469
0
  case VFCMULCPHZ128rmkz:
8470
0
  case VFCMULCPHZ128rr:
8471
0
  case VFCMULCPHZ128rrk:
8472
0
  case VFCMULCPHZ128rrkz:
8473
0
  case VFCMULCPHZ256rm:
8474
0
  case VFCMULCPHZ256rmb:
8475
0
  case VFCMULCPHZ256rmbk:
8476
0
  case VFCMULCPHZ256rmbkz:
8477
0
  case VFCMULCPHZ256rmk:
8478
0
  case VFCMULCPHZ256rmkz:
8479
0
  case VFCMULCPHZ256rr:
8480
0
  case VFCMULCPHZ256rrk:
8481
0
  case VFCMULCPHZ256rrkz:
8482
0
  case VFCMULCPHZrm:
8483
0
  case VFCMULCPHZrmb:
8484
0
  case VFCMULCPHZrmbk:
8485
0
  case VFCMULCPHZrmbkz:
8486
0
  case VFCMULCPHZrmk:
8487
0
  case VFCMULCPHZrmkz:
8488
0
  case VFCMULCPHZrr:
8489
0
  case VFCMULCPHZrrb:
8490
0
  case VFCMULCPHZrrbk:
8491
0
  case VFCMULCPHZrrbkz:
8492
0
  case VFCMULCPHZrrk:
8493
0
  case VFCMULCPHZrrkz:
8494
0
    return true;
8495
0
  }
8496
0
  return false;
8497
0
}
8498
8499
0
bool isVPADDD(unsigned Opcode) {
8500
0
  switch (Opcode) {
8501
0
  case VPADDDYrm:
8502
0
  case VPADDDYrr:
8503
0
  case VPADDDZ128rm:
8504
0
  case VPADDDZ128rmb:
8505
0
  case VPADDDZ128rmbk:
8506
0
  case VPADDDZ128rmbkz:
8507
0
  case VPADDDZ128rmk:
8508
0
  case VPADDDZ128rmkz:
8509
0
  case VPADDDZ128rr:
8510
0
  case VPADDDZ128rrk:
8511
0
  case VPADDDZ128rrkz:
8512
0
  case VPADDDZ256rm:
8513
0
  case VPADDDZ256rmb:
8514
0
  case VPADDDZ256rmbk:
8515
0
  case VPADDDZ256rmbkz:
8516
0
  case VPADDDZ256rmk:
8517
0
  case VPADDDZ256rmkz:
8518
0
  case VPADDDZ256rr:
8519
0
  case VPADDDZ256rrk:
8520
0
  case VPADDDZ256rrkz:
8521
0
  case VPADDDZrm:
8522
0
  case VPADDDZrmb:
8523
0
  case VPADDDZrmbk:
8524
0
  case VPADDDZrmbkz:
8525
0
  case VPADDDZrmk:
8526
0
  case VPADDDZrmkz:
8527
0
  case VPADDDZrr:
8528
0
  case VPADDDZrrk:
8529
0
  case VPADDDZrrkz:
8530
0
  case VPADDDrm:
8531
0
  case VPADDDrr:
8532
0
    return true;
8533
0
  }
8534
0
  return false;
8535
0
}
8536
8537
0
bool isVSM3MSG2(unsigned Opcode) {
8538
0
  switch (Opcode) {
8539
0
  case VSM3MSG2rm:
8540
0
  case VSM3MSG2rr:
8541
0
    return true;
8542
0
  }
8543
0
  return false;
8544
0
}
8545
8546
0
bool isVPCOMUQ(unsigned Opcode) {
8547
0
  switch (Opcode) {
8548
0
  case VPCOMUQmi:
8549
0
  case VPCOMUQri:
8550
0
    return true;
8551
0
  }
8552
0
  return false;
8553
0
}
8554
8555
0
bool isVERR(unsigned Opcode) {
8556
0
  switch (Opcode) {
8557
0
  case VERRm:
8558
0
  case VERRr:
8559
0
    return true;
8560
0
  }
8561
0
  return false;
8562
0
}
8563
8564
0
bool isKORTESTQ(unsigned Opcode) {
8565
0
  return Opcode == KORTESTQrr;
8566
0
}
8567
8568
0
bool isVFMSUB132SD(unsigned Opcode) {
8569
0
  switch (Opcode) {
8570
0
  case VFMSUB132SDZm_Int:
8571
0
  case VFMSUB132SDZm_Intk:
8572
0
  case VFMSUB132SDZm_Intkz:
8573
0
  case VFMSUB132SDZr_Int:
8574
0
  case VFMSUB132SDZr_Intk:
8575
0
  case VFMSUB132SDZr_Intkz:
8576
0
  case VFMSUB132SDZrb_Int:
8577
0
  case VFMSUB132SDZrb_Intk:
8578
0
  case VFMSUB132SDZrb_Intkz:
8579
0
  case VFMSUB132SDm_Int:
8580
0
  case VFMSUB132SDr_Int:
8581
0
    return true;
8582
0
  }
8583
0
  return false;
8584
0
}
8585
8586
0
bool isTILEZERO(unsigned Opcode) {
8587
0
  return Opcode == TILEZERO;
8588
0
}
8589
8590
0
bool isPFADD(unsigned Opcode) {
8591
0
  switch (Opcode) {
8592
0
  case PFADDrm:
8593
0
  case PFADDrr:
8594
0
    return true;
8595
0
  }
8596
0
  return false;
8597
0
}
8598
8599
0
bool isVCVTSI2SD(unsigned Opcode) {
8600
0
  switch (Opcode) {
8601
0
  case VCVTSI2SDZrm_Int:
8602
0
  case VCVTSI2SDZrr_Int:
8603
0
  case VCVTSI2SDrm_Int:
8604
0
  case VCVTSI2SDrr_Int:
8605
0
  case VCVTSI642SDZrm_Int:
8606
0
  case VCVTSI642SDZrr_Int:
8607
0
  case VCVTSI642SDZrrb_Int:
8608
0
  case VCVTSI642SDrm_Int:
8609
0
  case VCVTSI642SDrr_Int:
8610
0
    return true;
8611
0
  }
8612
0
  return false;
8613
0
}
8614
8615
0
bool isVSTMXCSR(unsigned Opcode) {
8616
0
  return Opcode == VSTMXCSR;
8617
0
}
8618
8619
0
bool isVCVTTSH2SI(unsigned Opcode) {
8620
0
  switch (Opcode) {
8621
0
  case VCVTTSH2SI64Zrm_Int:
8622
0
  case VCVTTSH2SI64Zrr_Int:
8623
0
  case VCVTTSH2SI64Zrrb_Int:
8624
0
  case VCVTTSH2SIZrm_Int:
8625
0
  case VCVTTSH2SIZrr_Int:
8626
0
  case VCVTTSH2SIZrrb_Int:
8627
0
    return true;
8628
0
  }
8629
0
  return false;
8630
0
}
8631
8632
0
bool isRET(unsigned Opcode) {
8633
0
  switch (Opcode) {
8634
0
  case RET16:
8635
0
  case RET32:
8636
0
  case RET64:
8637
0
  case RETI16:
8638
0
  case RETI32:
8639
0
  case RETI64:
8640
0
    return true;
8641
0
  }
8642
0
  return false;
8643
0
}
8644
8645
0
bool isLZCNT(unsigned Opcode) {
8646
0
  switch (Opcode) {
8647
0
  case LZCNT16rm:
8648
0
  case LZCNT16rr:
8649
0
  case LZCNT32rm:
8650
0
  case LZCNT32rr:
8651
0
  case LZCNT64rm:
8652
0
  case LZCNT64rr:
8653
0
    return true;
8654
0
  }
8655
0
  return false;
8656
0
}
8657
8658
0
bool isMULPD(unsigned Opcode) {
8659
0
  switch (Opcode) {
8660
0
  case MULPDrm:
8661
0
  case MULPDrr:
8662
0
    return true;
8663
0
  }
8664
0
  return false;
8665
0
}
8666
8667
0
bool isVBROADCASTI32X2(unsigned Opcode) {
8668
0
  switch (Opcode) {
8669
0
  case VBROADCASTI32X2Z128rm:
8670
0
  case VBROADCASTI32X2Z128rmk:
8671
0
  case VBROADCASTI32X2Z128rmkz:
8672
0
  case VBROADCASTI32X2Z128rr:
8673
0
  case VBROADCASTI32X2Z128rrk:
8674
0
  case VBROADCASTI32X2Z128rrkz:
8675
0
  case VBROADCASTI32X2Z256rm:
8676
0
  case VBROADCASTI32X2Z256rmk:
8677
0
  case VBROADCASTI32X2Z256rmkz:
8678
0
  case VBROADCASTI32X2Z256rr:
8679
0
  case VBROADCASTI32X2Z256rrk:
8680
0
  case VBROADCASTI32X2Z256rrkz:
8681
0
  case VBROADCASTI32X2Zrm:
8682
0
  case VBROADCASTI32X2Zrmk:
8683
0
  case VBROADCASTI32X2Zrmkz:
8684
0
  case VBROADCASTI32X2Zrr:
8685
0
  case VBROADCASTI32X2Zrrk:
8686
0
  case VBROADCASTI32X2Zrrkz:
8687
0
    return true;
8688
0
  }
8689
0
  return false;
8690
0
}
8691
8692
0
bool isVCVTPH2W(unsigned Opcode) {
8693
0
  switch (Opcode) {
8694
0
  case VCVTPH2WZ128rm:
8695
0
  case VCVTPH2WZ128rmb:
8696
0
  case VCVTPH2WZ128rmbk:
8697
0
  case VCVTPH2WZ128rmbkz:
8698
0
  case VCVTPH2WZ128rmk:
8699
0
  case VCVTPH2WZ128rmkz:
8700
0
  case VCVTPH2WZ128rr:
8701
0
  case VCVTPH2WZ128rrk:
8702
0
  case VCVTPH2WZ128rrkz:
8703
0
  case VCVTPH2WZ256rm:
8704
0
  case VCVTPH2WZ256rmb:
8705
0
  case VCVTPH2WZ256rmbk:
8706
0
  case VCVTPH2WZ256rmbkz:
8707
0
  case VCVTPH2WZ256rmk:
8708
0
  case VCVTPH2WZ256rmkz:
8709
0
  case VCVTPH2WZ256rr:
8710
0
  case VCVTPH2WZ256rrk:
8711
0
  case VCVTPH2WZ256rrkz:
8712
0
  case VCVTPH2WZrm:
8713
0
  case VCVTPH2WZrmb:
8714
0
  case VCVTPH2WZrmbk:
8715
0
  case VCVTPH2WZrmbkz:
8716
0
  case VCVTPH2WZrmk:
8717
0
  case VCVTPH2WZrmkz:
8718
0
  case VCVTPH2WZrr:
8719
0
  case VCVTPH2WZrrb:
8720
0
  case VCVTPH2WZrrbk:
8721
0
  case VCVTPH2WZrrbkz:
8722
0
  case VCVTPH2WZrrk:
8723
0
  case VCVTPH2WZrrkz:
8724
0
    return true;
8725
0
  }
8726
0
  return false;
8727
0
}
8728
8729
0
bool isCQO(unsigned Opcode) {
8730
0
  return Opcode == CQO;
8731
0
}
8732
8733
0
bool isFSUBR(unsigned Opcode) {
8734
0
  switch (Opcode) {
8735
0
  case SUBR_F32m:
8736
0
  case SUBR_F64m:
8737
0
  case SUBR_FST0r:
8738
0
  case SUBR_FrST0:
8739
0
    return true;
8740
0
  }
8741
0
  return false;
8742
0
}
8743
8744
0
bool isDPPD(unsigned Opcode) {
8745
0
  switch (Opcode) {
8746
0
  case DPPDrmi:
8747
0
  case DPPDrri:
8748
0
    return true;
8749
0
  }
8750
0
  return false;
8751
0
}
8752
8753
0
bool isFCOS(unsigned Opcode) {
8754
0
  return Opcode == FCOS;
8755
0
}
8756
8757
0
bool isXSAVES(unsigned Opcode) {
8758
0
  return Opcode == XSAVES;
8759
0
}
8760
8761
0
bool isTZCNT(unsigned Opcode) {
8762
0
  switch (Opcode) {
8763
0
  case TZCNT16rm:
8764
0
  case TZCNT16rr:
8765
0
  case TZCNT32rm:
8766
0
  case TZCNT32rr:
8767
0
  case TZCNT64rm:
8768
0
  case TZCNT64rr:
8769
0
    return true;
8770
0
  }
8771
0
  return false;
8772
0
}
8773
8774
0
bool isLJMP(unsigned Opcode) {
8775
0
  switch (Opcode) {
8776
0
  case FARJMP16i:
8777
0
  case FARJMP16m:
8778
0
  case FARJMP32i:
8779
0
  case FARJMP64m:
8780
0
    return true;
8781
0
  }
8782
0
  return false;
8783
0
}
8784
8785
332k
bool isCMOVCC(unsigned Opcode) {
8786
332k
  switch (Opcode) {
8787
0
  case CMOV16rm:
8788
10
  case CMOV16rr:
8789
60
  case CMOV32rm:
8790
4.07k
  case CMOV32rr:
8791
4.12k
  case CMOV64rm:
8792
4.63k
  case CMOV64rr:
8793
4.63k
    return true;
8794
332k
  }
8795
327k
  return false;
8796
332k
}
8797
8798
0
bool isVCVTSS2SD(unsigned Opcode) {
8799
0
  switch (Opcode) {
8800
0
  case VCVTSS2SDZrm_Int:
8801
0
  case VCVTSS2SDZrm_Intk:
8802
0
  case VCVTSS2SDZrm_Intkz:
8803
0
  case VCVTSS2SDZrr_Int:
8804
0
  case VCVTSS2SDZrr_Intk:
8805
0
  case VCVTSS2SDZrr_Intkz:
8806
0
  case VCVTSS2SDZrrb_Int:
8807
0
  case VCVTSS2SDZrrb_Intk:
8808
0
  case VCVTSS2SDZrrb_Intkz:
8809
0
  case VCVTSS2SDrm_Int:
8810
0
  case VCVTSS2SDrr_Int:
8811
0
    return true;
8812
0
  }
8813
0
  return false;
8814
0
}
8815
8816
0
bool isINVEPT(unsigned Opcode) {
8817
0
  switch (Opcode) {
8818
0
  case INVEPT32:
8819
0
  case INVEPT64:
8820
0
  case INVEPT64_EVEX:
8821
0
    return true;
8822
0
  }
8823
0
  return false;
8824
0
}
8825
8826
0
bool isADDSUBPD(unsigned Opcode) {
8827
0
  switch (Opcode) {
8828
0
  case ADDSUBPDrm:
8829
0
  case ADDSUBPDrr:
8830
0
    return true;
8831
0
  }
8832
0
  return false;
8833
0
}
8834
8835
0
bool isVMOVSHDUP(unsigned Opcode) {
8836
0
  switch (Opcode) {
8837
0
  case VMOVSHDUPYrm:
8838
0
  case VMOVSHDUPYrr:
8839
0
  case VMOVSHDUPZ128rm:
8840
0
  case VMOVSHDUPZ128rmk:
8841
0
  case VMOVSHDUPZ128rmkz:
8842
0
  case VMOVSHDUPZ128rr:
8843
0
  case VMOVSHDUPZ128rrk:
8844
0
  case VMOVSHDUPZ128rrkz:
8845
0
  case VMOVSHDUPZ256rm:
8846
0
  case VMOVSHDUPZ256rmk:
8847
0
  case VMOVSHDUPZ256rmkz:
8848
0
  case VMOVSHDUPZ256rr:
8849
0
  case VMOVSHDUPZ256rrk:
8850
0
  case VMOVSHDUPZ256rrkz:
8851
0
  case VMOVSHDUPZrm:
8852
0
  case VMOVSHDUPZrmk:
8853
0
  case VMOVSHDUPZrmkz:
8854
0
  case VMOVSHDUPZrr:
8855
0
  case VMOVSHDUPZrrk:
8856
0
  case VMOVSHDUPZrrkz:
8857
0
  case VMOVSHDUPrm:
8858
0
  case VMOVSHDUPrr:
8859
0
    return true;
8860
0
  }
8861
0
  return false;
8862
0
}
8863
8864
0
bool isKSHIFTRD(unsigned Opcode) {
8865
0
  return Opcode == KSHIFTRDri;
8866
0
}
8867
8868
0
bool isVPTERNLOGD(unsigned Opcode) {
8869
0
  switch (Opcode) {
8870
0
  case VPTERNLOGDZ128rmbi:
8871
0
  case VPTERNLOGDZ128rmbik:
8872
0
  case VPTERNLOGDZ128rmbikz:
8873
0
  case VPTERNLOGDZ128rmi:
8874
0
  case VPTERNLOGDZ128rmik:
8875
0
  case VPTERNLOGDZ128rmikz:
8876
0
  case VPTERNLOGDZ128rri:
8877
0
  case VPTERNLOGDZ128rrik:
8878
0
  case VPTERNLOGDZ128rrikz:
8879
0
  case VPTERNLOGDZ256rmbi:
8880
0
  case VPTERNLOGDZ256rmbik:
8881
0
  case VPTERNLOGDZ256rmbikz:
8882
0
  case VPTERNLOGDZ256rmi:
8883
0
  case VPTERNLOGDZ256rmik:
8884
0
  case VPTERNLOGDZ256rmikz:
8885
0
  case VPTERNLOGDZ256rri:
8886
0
  case VPTERNLOGDZ256rrik:
8887
0
  case VPTERNLOGDZ256rrikz:
8888
0
  case VPTERNLOGDZrmbi:
8889
0
  case VPTERNLOGDZrmbik:
8890
0
  case VPTERNLOGDZrmbikz:
8891
0
  case VPTERNLOGDZrmi:
8892
0
  case VPTERNLOGDZrmik:
8893
0
  case VPTERNLOGDZrmikz:
8894
0
  case VPTERNLOGDZrri:
8895
0
  case VPTERNLOGDZrrik:
8896
0
  case VPTERNLOGDZrrikz:
8897
0
    return true;
8898
0
  }
8899
0
  return false;
8900
0
}
8901
8902
0
bool isPADDQ(unsigned Opcode) {
8903
0
  switch (Opcode) {
8904
0
  case MMX_PADDQrm:
8905
0
  case MMX_PADDQrr:
8906
0
  case PADDQrm:
8907
0
  case PADDQrr:
8908
0
    return true;
8909
0
  }
8910
0
  return false;
8911
0
}
8912
8913
0
bool isVEXTRACTI64X4(unsigned Opcode) {
8914
0
  switch (Opcode) {
8915
0
  case VEXTRACTI64x4Zmr:
8916
0
  case VEXTRACTI64x4Zmrk:
8917
0
  case VEXTRACTI64x4Zrr:
8918
0
  case VEXTRACTI64x4Zrrk:
8919
0
  case VEXTRACTI64x4Zrrkz:
8920
0
    return true;
8921
0
  }
8922
0
  return false;
8923
0
}
8924
8925
0
bool isVFMSUB231SS(unsigned Opcode) {
8926
0
  switch (Opcode) {
8927
0
  case VFMSUB231SSZm_Int:
8928
0
  case VFMSUB231SSZm_Intk:
8929
0
  case VFMSUB231SSZm_Intkz:
8930
0
  case VFMSUB231SSZr_Int:
8931
0
  case VFMSUB231SSZr_Intk:
8932
0
  case VFMSUB231SSZr_Intkz:
8933
0
  case VFMSUB231SSZrb_Int:
8934
0
  case VFMSUB231SSZrb_Intk:
8935
0
  case VFMSUB231SSZrb_Intkz:
8936
0
  case VFMSUB231SSm_Int:
8937
0
  case VFMSUB231SSr_Int:
8938
0
    return true;
8939
0
  }
8940
0
  return false;
8941
0
}
8942
8943
0
bool isVPCMPEQB(unsigned Opcode) {
8944
0
  switch (Opcode) {
8945
0
  case VPCMPEQBYrm:
8946
0
  case VPCMPEQBYrr:
8947
0
  case VPCMPEQBZ128rm:
8948
0
  case VPCMPEQBZ128rmk:
8949
0
  case VPCMPEQBZ128rr:
8950
0
  case VPCMPEQBZ128rrk:
8951
0
  case VPCMPEQBZ256rm:
8952
0
  case VPCMPEQBZ256rmk:
8953
0
  case VPCMPEQBZ256rr:
8954
0
  case VPCMPEQBZ256rrk:
8955
0
  case VPCMPEQBZrm:
8956
0
  case VPCMPEQBZrmk:
8957
0
  case VPCMPEQBZrr:
8958
0
  case VPCMPEQBZrrk:
8959
0
  case VPCMPEQBrm:
8960
0
  case VPCMPEQBrr:
8961
0
    return true;
8962
0
  }
8963
0
  return false;
8964
0
}
8965
8966
0
bool isLEA(unsigned Opcode) {
8967
0
  switch (Opcode) {
8968
0
  case LEA16r:
8969
0
  case LEA32r:
8970
0
  case LEA64_32r:
8971
0
  case LEA64r:
8972
0
    return true;
8973
0
  }
8974
0
  return false;
8975
0
}
8976
8977
0
bool isPSUBB(unsigned Opcode) {
8978
0
  switch (Opcode) {
8979
0
  case MMX_PSUBBrm:
8980
0
  case MMX_PSUBBrr:
8981
0
  case PSUBBrm:
8982
0
  case PSUBBrr:
8983
0
    return true;
8984
0
  }
8985
0
  return false;
8986
0
}
8987
8988
0
bool isKADDQ(unsigned Opcode) {
8989
0
  return Opcode == KADDQrr;
8990
0
}
8991
8992
0
bool isMOVSX(unsigned Opcode) {
8993
0
  switch (Opcode) {
8994
0
  case MOVSX16rm16:
8995
0
  case MOVSX16rm8:
8996
0
  case MOVSX16rr16:
8997
0
  case MOVSX16rr8:
8998
0
  case MOVSX32rm16:
8999
0
  case MOVSX32rm8:
9000
0
  case MOVSX32rr16:
9001
0
  case MOVSX32rr8:
9002
0
  case MOVSX64rm16:
9003
0
  case MOVSX64rm8:
9004
0
  case MOVSX64rr16:
9005
0
  case MOVSX64rr8:
9006
0
    return true;
9007
0
  }
9008
0
  return false;
9009
0
}
9010
9011
0
bool isVALIGNQ(unsigned Opcode) {
9012
0
  switch (Opcode) {
9013
0
  case VALIGNQZ128rmbi:
9014
0
  case VALIGNQZ128rmbik:
9015
0
  case VALIGNQZ128rmbikz:
9016
0
  case VALIGNQZ128rmi:
9017
0
  case VALIGNQZ128rmik:
9018
0
  case VALIGNQZ128rmikz:
9019
0
  case VALIGNQZ128rri:
9020
0
  case VALIGNQZ128rrik:
9021
0
  case VALIGNQZ128rrikz:
9022
0
  case VALIGNQZ256rmbi:
9023
0
  case VALIGNQZ256rmbik:
9024
0
  case VALIGNQZ256rmbikz:
9025
0
  case VALIGNQZ256rmi:
9026
0
  case VALIGNQZ256rmik:
9027
0
  case VALIGNQZ256rmikz:
9028
0
  case VALIGNQZ256rri:
9029
0
  case VALIGNQZ256rrik:
9030
0
  case VALIGNQZ256rrikz:
9031
0
  case VALIGNQZrmbi:
9032
0
  case VALIGNQZrmbik:
9033
0
  case VALIGNQZrmbikz:
9034
0
  case VALIGNQZrmi:
9035
0
  case VALIGNQZrmik:
9036
0
  case VALIGNQZrmikz:
9037
0
  case VALIGNQZrri:
9038
0
  case VALIGNQZrrik:
9039
0
  case VALIGNQZrrikz:
9040
0
    return true;
9041
0
  }
9042
0
  return false;
9043
0
}
9044
9045
0
bool isVCVTNE2PS2BF16(unsigned Opcode) {
9046
0
  switch (Opcode) {
9047
0
  case VCVTNE2PS2BF16Z128rm:
9048
0
  case VCVTNE2PS2BF16Z128rmb:
9049
0
  case VCVTNE2PS2BF16Z128rmbk:
9050
0
  case VCVTNE2PS2BF16Z128rmbkz:
9051
0
  case VCVTNE2PS2BF16Z128rmk:
9052
0
  case VCVTNE2PS2BF16Z128rmkz:
9053
0
  case VCVTNE2PS2BF16Z128rr:
9054
0
  case VCVTNE2PS2BF16Z128rrk:
9055
0
  case VCVTNE2PS2BF16Z128rrkz:
9056
0
  case VCVTNE2PS2BF16Z256rm:
9057
0
  case VCVTNE2PS2BF16Z256rmb:
9058
0
  case VCVTNE2PS2BF16Z256rmbk:
9059
0
  case VCVTNE2PS2BF16Z256rmbkz:
9060
0
  case VCVTNE2PS2BF16Z256rmk:
9061
0
  case VCVTNE2PS2BF16Z256rmkz:
9062
0
  case VCVTNE2PS2BF16Z256rr:
9063
0
  case VCVTNE2PS2BF16Z256rrk:
9064
0
  case VCVTNE2PS2BF16Z256rrkz:
9065
0
  case VCVTNE2PS2BF16Zrm:
9066
0
  case VCVTNE2PS2BF16Zrmb:
9067
0
  case VCVTNE2PS2BF16Zrmbk:
9068
0
  case VCVTNE2PS2BF16Zrmbkz:
9069
0
  case VCVTNE2PS2BF16Zrmk:
9070
0
  case VCVTNE2PS2BF16Zrmkz:
9071
0
  case VCVTNE2PS2BF16Zrr:
9072
0
  case VCVTNE2PS2BF16Zrrk:
9073
0
  case VCVTNE2PS2BF16Zrrkz:
9074
0
    return true;
9075
0
  }
9076
0
  return false;
9077
0
}
9078
9079
0
bool isVPSRAW(unsigned Opcode) {
9080
0
  switch (Opcode) {
9081
0
  case VPSRAWYri:
9082
0
  case VPSRAWYrm:
9083
0
  case VPSRAWYrr:
9084
0
  case VPSRAWZ128mi:
9085
0
  case VPSRAWZ128mik:
9086
0
  case VPSRAWZ128mikz:
9087
0
  case VPSRAWZ128ri:
9088
0
  case VPSRAWZ128rik:
9089
0
  case VPSRAWZ128rikz:
9090
0
  case VPSRAWZ128rm:
9091
0
  case VPSRAWZ128rmk:
9092
0
  case VPSRAWZ128rmkz:
9093
0
  case VPSRAWZ128rr:
9094
0
  case VPSRAWZ128rrk:
9095
0
  case VPSRAWZ128rrkz:
9096
0
  case VPSRAWZ256mi:
9097
0
  case VPSRAWZ256mik:
9098
0
  case VPSRAWZ256mikz:
9099
0
  case VPSRAWZ256ri:
9100
0
  case VPSRAWZ256rik:
9101
0
  case VPSRAWZ256rikz:
9102
0
  case VPSRAWZ256rm:
9103
0
  case VPSRAWZ256rmk:
9104
0
  case VPSRAWZ256rmkz:
9105
0
  case VPSRAWZ256rr:
9106
0
  case VPSRAWZ256rrk:
9107
0
  case VPSRAWZ256rrkz:
9108
0
  case VPSRAWZmi:
9109
0
  case VPSRAWZmik:
9110
0
  case VPSRAWZmikz:
9111
0
  case VPSRAWZri:
9112
0
  case VPSRAWZrik:
9113
0
  case VPSRAWZrikz:
9114
0
  case VPSRAWZrm:
9115
0
  case VPSRAWZrmk:
9116
0
  case VPSRAWZrmkz:
9117
0
  case VPSRAWZrr:
9118
0
  case VPSRAWZrrk:
9119
0
  case VPSRAWZrrkz:
9120
0
  case VPSRAWri:
9121
0
  case VPSRAWrm:
9122
0
  case VPSRAWrr:
9123
0
    return true;
9124
0
  }
9125
0
  return false;
9126
0
}
9127
9128
0
bool isVFMSUBADD231PH(unsigned Opcode) {
9129
0
  switch (Opcode) {
9130
0
  case VFMSUBADD231PHZ128m:
9131
0
  case VFMSUBADD231PHZ128mb:
9132
0
  case VFMSUBADD231PHZ128mbk:
9133
0
  case VFMSUBADD231PHZ128mbkz:
9134
0
  case VFMSUBADD231PHZ128mk:
9135
0
  case VFMSUBADD231PHZ128mkz:
9136
0
  case VFMSUBADD231PHZ128r:
9137
0
  case VFMSUBADD231PHZ128rk:
9138
0
  case VFMSUBADD231PHZ128rkz:
9139
0
  case VFMSUBADD231PHZ256m:
9140
0
  case VFMSUBADD231PHZ256mb:
9141
0
  case VFMSUBADD231PHZ256mbk:
9142
0
  case VFMSUBADD231PHZ256mbkz:
9143
0
  case VFMSUBADD231PHZ256mk:
9144
0
  case VFMSUBADD231PHZ256mkz:
9145
0
  case VFMSUBADD231PHZ256r:
9146
0
  case VFMSUBADD231PHZ256rk:
9147
0
  case VFMSUBADD231PHZ256rkz:
9148
0
  case VFMSUBADD231PHZm:
9149
0
  case VFMSUBADD231PHZmb:
9150
0
  case VFMSUBADD231PHZmbk:
9151
0
  case VFMSUBADD231PHZmbkz:
9152
0
  case VFMSUBADD231PHZmk:
9153
0
  case VFMSUBADD231PHZmkz:
9154
0
  case VFMSUBADD231PHZr:
9155
0
  case VFMSUBADD231PHZrb:
9156
0
  case VFMSUBADD231PHZrbk:
9157
0
  case VFMSUBADD231PHZrbkz:
9158
0
  case VFMSUBADD231PHZrk:
9159
0
  case VFMSUBADD231PHZrkz:
9160
0
    return true;
9161
0
  }
9162
0
  return false;
9163
0
}
9164
9165
0
bool isCVTDQ2PS(unsigned Opcode) {
9166
0
  switch (Opcode) {
9167
0
  case CVTDQ2PSrm:
9168
0
  case CVTDQ2PSrr:
9169
0
    return true;
9170
0
  }
9171
0
  return false;
9172
0
}
9173
9174
0
bool isFBLD(unsigned Opcode) {
9175
0
  return Opcode == FBLDm;
9176
0
}
9177
9178
0
bool isLMSW(unsigned Opcode) {
9179
0
  switch (Opcode) {
9180
0
  case LMSW16m:
9181
0
  case LMSW16r:
9182
0
    return true;
9183
0
  }
9184
0
  return false;
9185
0
}
9186
9187
0
bool isWRMSR(unsigned Opcode) {
9188
0
  return Opcode == WRMSR;
9189
0
}
9190
9191
0
bool isMINSS(unsigned Opcode) {
9192
0
  switch (Opcode) {
9193
0
  case MINSSrm_Int:
9194
0
  case MINSSrr_Int:
9195
0
    return true;
9196
0
  }
9197
0
  return false;
9198
0
}
9199
9200
0
bool isFSCALE(unsigned Opcode) {
9201
0
  return Opcode == FSCALE;
9202
0
}
9203
9204
0
bool isVFNMADD213SH(unsigned Opcode) {
9205
0
  switch (Opcode) {
9206
0
  case VFNMADD213SHZm_Int:
9207
0
  case VFNMADD213SHZm_Intk:
9208
0
  case VFNMADD213SHZm_Intkz:
9209
0
  case VFNMADD213SHZr_Int:
9210
0
  case VFNMADD213SHZr_Intk:
9211
0
  case VFNMADD213SHZr_Intkz:
9212
0
  case VFNMADD213SHZrb_Int:
9213
0
  case VFNMADD213SHZrb_Intk:
9214
0
  case VFNMADD213SHZrb_Intkz:
9215
0
    return true;
9216
0
  }
9217
0
  return false;
9218
0
}
9219
9220
0
bool isVPHADDUBD(unsigned Opcode) {
9221
0
  switch (Opcode) {
9222
0
  case VPHADDUBDrm:
9223
0
  case VPHADDUBDrr:
9224
0
    return true;
9225
0
  }
9226
0
  return false;
9227
0
}
9228
9229
0
bool isRDSSPQ(unsigned Opcode) {
9230
0
  return Opcode == RDSSPQ;
9231
0
}
9232
9233
0
bool isLGDT(unsigned Opcode) {
9234
0
  return Opcode == LGDT64m;
9235
0
}
9236
9237
0
bool isVPSHLDVD(unsigned Opcode) {
9238
0
  switch (Opcode) {
9239
0
  case VPSHLDVDZ128m:
9240
0
  case VPSHLDVDZ128mb:
9241
0
  case VPSHLDVDZ128mbk:
9242
0
  case VPSHLDVDZ128mbkz:
9243
0
  case VPSHLDVDZ128mk:
9244
0
  case VPSHLDVDZ128mkz:
9245
0
  case VPSHLDVDZ128r:
9246
0
  case VPSHLDVDZ128rk:
9247
0
  case VPSHLDVDZ128rkz:
9248
0
  case VPSHLDVDZ256m:
9249
0
  case VPSHLDVDZ256mb:
9250
0
  case VPSHLDVDZ256mbk:
9251
0
  case VPSHLDVDZ256mbkz:
9252
0
  case VPSHLDVDZ256mk:
9253
0
  case VPSHLDVDZ256mkz:
9254
0
  case VPSHLDVDZ256r:
9255
0
  case VPSHLDVDZ256rk:
9256
0
  case VPSHLDVDZ256rkz:
9257
0
  case VPSHLDVDZm:
9258
0
  case VPSHLDVDZmb:
9259
0
  case VPSHLDVDZmbk:
9260
0
  case VPSHLDVDZmbkz:
9261
0
  case VPSHLDVDZmk:
9262
0
  case VPSHLDVDZmkz:
9263
0
  case VPSHLDVDZr:
9264
0
  case VPSHLDVDZrk:
9265
0
  case VPSHLDVDZrkz:
9266
0
    return true;
9267
0
  }
9268
0
  return false;
9269
0
}
9270
9271
0
bool isPFCMPGT(unsigned Opcode) {
9272
0
  switch (Opcode) {
9273
0
  case PFCMPGTrm:
9274
0
  case PFCMPGTrr:
9275
0
    return true;
9276
0
  }
9277
0
  return false;
9278
0
}
9279
9280
0
bool isVRNDSCALEPH(unsigned Opcode) {
9281
0
  switch (Opcode) {
9282
0
  case VRNDSCALEPHZ128rmbi:
9283
0
  case VRNDSCALEPHZ128rmbik:
9284
0
  case VRNDSCALEPHZ128rmbikz:
9285
0
  case VRNDSCALEPHZ128rmi:
9286
0
  case VRNDSCALEPHZ128rmik:
9287
0
  case VRNDSCALEPHZ128rmikz:
9288
0
  case VRNDSCALEPHZ128rri:
9289
0
  case VRNDSCALEPHZ128rrik:
9290
0
  case VRNDSCALEPHZ128rrikz:
9291
0
  case VRNDSCALEPHZ256rmbi:
9292
0
  case VRNDSCALEPHZ256rmbik:
9293
0
  case VRNDSCALEPHZ256rmbikz:
9294
0
  case VRNDSCALEPHZ256rmi:
9295
0
  case VRNDSCALEPHZ256rmik:
9296
0
  case VRNDSCALEPHZ256rmikz:
9297
0
  case VRNDSCALEPHZ256rri:
9298
0
  case VRNDSCALEPHZ256rrik:
9299
0
  case VRNDSCALEPHZ256rrikz:
9300
0
  case VRNDSCALEPHZrmbi:
9301
0
  case VRNDSCALEPHZrmbik:
9302
0
  case VRNDSCALEPHZrmbikz:
9303
0
  case VRNDSCALEPHZrmi:
9304
0
  case VRNDSCALEPHZrmik:
9305
0
  case VRNDSCALEPHZrmikz:
9306
0
  case VRNDSCALEPHZrri:
9307
0
  case VRNDSCALEPHZrrib:
9308
0
  case VRNDSCALEPHZrribk:
9309
0
  case VRNDSCALEPHZrribkz:
9310
0
  case VRNDSCALEPHZrrik:
9311
0
  case VRNDSCALEPHZrrikz:
9312
0
    return true;
9313
0
  }
9314
0
  return false;
9315
0
}
9316
9317
0
bool isJCXZ(unsigned Opcode) {
9318
0
  return Opcode == JCXZ;
9319
0
}
9320
9321
0
bool isVPMOVZXBW(unsigned Opcode) {
9322
0
  switch (Opcode) {
9323
0
  case VPMOVZXBWYrm:
9324
0
  case VPMOVZXBWYrr:
9325
0
  case VPMOVZXBWZ128rm:
9326
0
  case VPMOVZXBWZ128rmk:
9327
0
  case VPMOVZXBWZ128rmkz:
9328
0
  case VPMOVZXBWZ128rr:
9329
0
  case VPMOVZXBWZ128rrk:
9330
0
  case VPMOVZXBWZ128rrkz:
9331
0
  case VPMOVZXBWZ256rm:
9332
0
  case VPMOVZXBWZ256rmk:
9333
0
  case VPMOVZXBWZ256rmkz:
9334
0
  case VPMOVZXBWZ256rr:
9335
0
  case VPMOVZXBWZ256rrk:
9336
0
  case VPMOVZXBWZ256rrkz:
9337
0
  case VPMOVZXBWZrm:
9338
0
  case VPMOVZXBWZrmk:
9339
0
  case VPMOVZXBWZrmkz:
9340
0
  case VPMOVZXBWZrr:
9341
0
  case VPMOVZXBWZrrk:
9342
0
  case VPMOVZXBWZrrkz:
9343
0
  case VPMOVZXBWrm:
9344
0
  case VPMOVZXBWrr:
9345
0
    return true;
9346
0
  }
9347
0
  return false;
9348
0
}
9349
9350
0
bool isVFMADDSUB231PD(unsigned Opcode) {
9351
0
  switch (Opcode) {
9352
0
  case VFMADDSUB231PDYm:
9353
0
  case VFMADDSUB231PDYr:
9354
0
  case VFMADDSUB231PDZ128m:
9355
0
  case VFMADDSUB231PDZ128mb:
9356
0
  case VFMADDSUB231PDZ128mbk:
9357
0
  case VFMADDSUB231PDZ128mbkz:
9358
0
  case VFMADDSUB231PDZ128mk:
9359
0
  case VFMADDSUB231PDZ128mkz:
9360
0
  case VFMADDSUB231PDZ128r:
9361
0
  case VFMADDSUB231PDZ128rk:
9362
0
  case VFMADDSUB231PDZ128rkz:
9363
0
  case VFMADDSUB231PDZ256m:
9364
0
  case VFMADDSUB231PDZ256mb:
9365
0
  case VFMADDSUB231PDZ256mbk:
9366
0
  case VFMADDSUB231PDZ256mbkz:
9367
0
  case VFMADDSUB231PDZ256mk:
9368
0
  case VFMADDSUB231PDZ256mkz:
9369
0
  case VFMADDSUB231PDZ256r:
9370
0
  case VFMADDSUB231PDZ256rk:
9371
0
  case VFMADDSUB231PDZ256rkz:
9372
0
  case VFMADDSUB231PDZm:
9373
0
  case VFMADDSUB231PDZmb:
9374
0
  case VFMADDSUB231PDZmbk:
9375
0
  case VFMADDSUB231PDZmbkz:
9376
0
  case VFMADDSUB231PDZmk:
9377
0
  case VFMADDSUB231PDZmkz:
9378
0
  case VFMADDSUB231PDZr:
9379
0
  case VFMADDSUB231PDZrb:
9380
0
  case VFMADDSUB231PDZrbk:
9381
0
  case VFMADDSUB231PDZrbkz:
9382
0
  case VFMADDSUB231PDZrk:
9383
0
  case VFMADDSUB231PDZrkz:
9384
0
  case VFMADDSUB231PDm:
9385
0
  case VFMADDSUB231PDr:
9386
0
    return true;
9387
0
  }
9388
0
  return false;
9389
0
}
9390
9391
0
bool isVBLENDMPD(unsigned Opcode) {
9392
0
  switch (Opcode) {
9393
0
  case VBLENDMPDZ128rm:
9394
0
  case VBLENDMPDZ128rmb:
9395
0
  case VBLENDMPDZ128rmbk:
9396
0
  case VBLENDMPDZ128rmbkz:
9397
0
  case VBLENDMPDZ128rmk:
9398
0
  case VBLENDMPDZ128rmkz:
9399
0
  case VBLENDMPDZ128rr:
9400
0
  case VBLENDMPDZ128rrk:
9401
0
  case VBLENDMPDZ128rrkz:
9402
0
  case VBLENDMPDZ256rm:
9403
0
  case VBLENDMPDZ256rmb:
9404
0
  case VBLENDMPDZ256rmbk:
9405
0
  case VBLENDMPDZ256rmbkz:
9406
0
  case VBLENDMPDZ256rmk:
9407
0
  case VBLENDMPDZ256rmkz:
9408
0
  case VBLENDMPDZ256rr:
9409
0
  case VBLENDMPDZ256rrk:
9410
0
  case VBLENDMPDZ256rrkz:
9411
0
  case VBLENDMPDZrm:
9412
0
  case VBLENDMPDZrmb:
9413
0
  case VBLENDMPDZrmbk:
9414
0
  case VBLENDMPDZrmbkz:
9415
0
  case VBLENDMPDZrmk:
9416
0
  case VBLENDMPDZrmkz:
9417
0
  case VBLENDMPDZrr:
9418
0
  case VBLENDMPDZrrk:
9419
0
  case VBLENDMPDZrrkz:
9420
0
    return true;
9421
0
  }
9422
0
  return false;
9423
0
}
9424
9425
0
bool isHSUBPS(unsigned Opcode) {
9426
0
  switch (Opcode) {
9427
0
  case HSUBPSrm:
9428
0
  case HSUBPSrr:
9429
0
    return true;
9430
0
  }
9431
0
  return false;
9432
0
}
9433
9434
0
bool isPREFETCHIT0(unsigned Opcode) {
9435
0
  return Opcode == PREFETCHIT0;
9436
0
}
9437
9438
0
bool isKTESTD(unsigned Opcode) {
9439
0
  return Opcode == KTESTDrr;
9440
0
}
9441
9442
0
bool isVCVTNEOPH2PS(unsigned Opcode) {
9443
0
  switch (Opcode) {
9444
0
  case VCVTNEOPH2PSYrm:
9445
0
  case VCVTNEOPH2PSrm:
9446
0
    return true;
9447
0
  }
9448
0
  return false;
9449
0
}
9450
9451
0
bool isVBLENDVPD(unsigned Opcode) {
9452
0
  switch (Opcode) {
9453
0
  case VBLENDVPDYrm:
9454
0
  case VBLENDVPDYrr:
9455
0
  case VBLENDVPDrm:
9456
0
  case VBLENDVPDrr:
9457
0
    return true;
9458
0
  }
9459
0
  return false;
9460
0
}
9461
9462
0
bool isVCVTSS2USI(unsigned Opcode) {
9463
0
  switch (Opcode) {
9464
0
  case VCVTSS2USI64Zrm_Int:
9465
0
  case VCVTSS2USI64Zrr_Int:
9466
0
  case VCVTSS2USI64Zrrb_Int:
9467
0
  case VCVTSS2USIZrm_Int:
9468
0
  case VCVTSS2USIZrr_Int:
9469
0
  case VCVTSS2USIZrrb_Int:
9470
0
    return true;
9471
0
  }
9472
0
  return false;
9473
0
}
9474
9475
0
bool isVPANDD(unsigned Opcode) {
9476
0
  switch (Opcode) {
9477
0
  case VPANDDZ128rm:
9478
0
  case VPANDDZ128rmb:
9479
0
  case VPANDDZ128rmbk:
9480
0
  case VPANDDZ128rmbkz:
9481
0
  case VPANDDZ128rmk:
9482
0
  case VPANDDZ128rmkz:
9483
0
  case VPANDDZ128rr:
9484
0
  case VPANDDZ128rrk:
9485
0
  case VPANDDZ128rrkz:
9486
0
  case VPANDDZ256rm:
9487
0
  case VPANDDZ256rmb:
9488
0
  case VPANDDZ256rmbk:
9489
0
  case VPANDDZ256rmbkz:
9490
0
  case VPANDDZ256rmk:
9491
0
  case VPANDDZ256rmkz:
9492
0
  case VPANDDZ256rr:
9493
0
  case VPANDDZ256rrk:
9494
0
  case VPANDDZ256rrkz:
9495
0
  case VPANDDZrm:
9496
0
  case VPANDDZrmb:
9497
0
  case VPANDDZrmbk:
9498
0
  case VPANDDZrmbkz:
9499
0
  case VPANDDZrmk:
9500
0
  case VPANDDZrmkz:
9501
0
  case VPANDDZrr:
9502
0
  case VPANDDZrrk:
9503
0
  case VPANDDZrrkz:
9504
0
    return true;
9505
0
  }
9506
0
  return false;
9507
0
}
9508
9509
0
bool isPMINSW(unsigned Opcode) {
9510
0
  switch (Opcode) {
9511
0
  case MMX_PMINSWrm:
9512
0
  case MMX_PMINSWrr:
9513
0
  case PMINSWrm:
9514
0
  case PMINSWrr:
9515
0
    return true;
9516
0
  }
9517
0
  return false;
9518
0
}
9519
9520
0
bool isSTAC(unsigned Opcode) {
9521
0
  return Opcode == STAC;
9522
0
}
9523
9524
0
bool isVFMSUB213PS(unsigned Opcode) {
9525
0
  switch (Opcode) {
9526
0
  case VFMSUB213PSYm:
9527
0
  case VFMSUB213PSYr:
9528
0
  case VFMSUB213PSZ128m:
9529
0
  case VFMSUB213PSZ128mb:
9530
0
  case VFMSUB213PSZ128mbk:
9531
0
  case VFMSUB213PSZ128mbkz:
9532
0
  case VFMSUB213PSZ128mk:
9533
0
  case VFMSUB213PSZ128mkz:
9534
0
  case VFMSUB213PSZ128r:
9535
0
  case VFMSUB213PSZ128rk:
9536
0
  case VFMSUB213PSZ128rkz:
9537
0
  case VFMSUB213PSZ256m:
9538
0
  case VFMSUB213PSZ256mb:
9539
0
  case VFMSUB213PSZ256mbk:
9540
0
  case VFMSUB213PSZ256mbkz:
9541
0
  case VFMSUB213PSZ256mk:
9542
0
  case VFMSUB213PSZ256mkz:
9543
0
  case VFMSUB213PSZ256r:
9544
0
  case VFMSUB213PSZ256rk:
9545
0
  case VFMSUB213PSZ256rkz:
9546
0
  case VFMSUB213PSZm:
9547
0
  case VFMSUB213PSZmb:
9548
0
  case VFMSUB213PSZmbk:
9549
0
  case VFMSUB213PSZmbkz:
9550
0
  case VFMSUB213PSZmk:
9551
0
  case VFMSUB213PSZmkz:
9552
0
  case VFMSUB213PSZr:
9553
0
  case VFMSUB213PSZrb:
9554
0
  case VFMSUB213PSZrbk:
9555
0
  case VFMSUB213PSZrbkz:
9556
0
  case VFMSUB213PSZrk:
9557
0
  case VFMSUB213PSZrkz:
9558
0
  case VFMSUB213PSm:
9559
0
  case VFMSUB213PSr:
9560
0
    return true;
9561
0
  }
9562
0
  return false;
9563
0
}
9564
9565
0
bool isPOPAL(unsigned Opcode) {
9566
0
  return Opcode == POPA32;
9567
0
}
9568
9569
0
bool isVCVTPS2UQQ(unsigned Opcode) {
9570
0
  switch (Opcode) {
9571
0
  case VCVTPS2UQQZ128rm:
9572
0
  case VCVTPS2UQQZ128rmb:
9573
0
  case VCVTPS2UQQZ128rmbk:
9574
0
  case VCVTPS2UQQZ128rmbkz:
9575
0
  case VCVTPS2UQQZ128rmk:
9576
0
  case VCVTPS2UQQZ128rmkz:
9577
0
  case VCVTPS2UQQZ128rr:
9578
0
  case VCVTPS2UQQZ128rrk:
9579
0
  case VCVTPS2UQQZ128rrkz:
9580
0
  case VCVTPS2UQQZ256rm:
9581
0
  case VCVTPS2UQQZ256rmb:
9582
0
  case VCVTPS2UQQZ256rmbk:
9583
0
  case VCVTPS2UQQZ256rmbkz:
9584
0
  case VCVTPS2UQQZ256rmk:
9585
0
  case VCVTPS2UQQZ256rmkz:
9586
0
  case VCVTPS2UQQZ256rr:
9587
0
  case VCVTPS2UQQZ256rrk:
9588
0
  case VCVTPS2UQQZ256rrkz:
9589
0
  case VCVTPS2UQQZrm:
9590
0
  case VCVTPS2UQQZrmb:
9591
0
  case VCVTPS2UQQZrmbk:
9592
0
  case VCVTPS2UQQZrmbkz:
9593
0
  case VCVTPS2UQQZrmk:
9594
0
  case VCVTPS2UQQZrmkz:
9595
0
  case VCVTPS2UQQZrr:
9596
0
  case VCVTPS2UQQZrrb:
9597
0
  case VCVTPS2UQQZrrbk:
9598
0
  case VCVTPS2UQQZrrbkz:
9599
0
  case VCVTPS2UQQZrrk:
9600
0
  case VCVTPS2UQQZrrkz:
9601
0
    return true;
9602
0
  }
9603
0
  return false;
9604
0
}
9605
9606
0
bool isRDRAND(unsigned Opcode) {
9607
0
  switch (Opcode) {
9608
0
  case RDRAND16r:
9609
0
  case RDRAND32r:
9610
0
  case RDRAND64r:
9611
0
    return true;
9612
0
  }
9613
0
  return false;
9614
0
}
9615
9616
253k
bool isJCC(unsigned Opcode) {
9617
253k
  switch (Opcode) {
9618
230k
  case JCC_1:
9619
230k
  case JCC_2:
9620
230k
  case JCC_4:
9621
230k
    return true;
9622
253k
  }
9623
23.3k
  return false;
9624
253k
}
9625
9626
0
bool isVPMINSQ(unsigned Opcode) {
9627
0
  switch (Opcode) {
9628
0
  case VPMINSQZ128rm:
9629
0
  case VPMINSQZ128rmb:
9630
0
  case VPMINSQZ128rmbk:
9631
0
  case VPMINSQZ128rmbkz:
9632
0
  case VPMINSQZ128rmk:
9633
0
  case VPMINSQZ128rmkz:
9634
0
  case VPMINSQZ128rr:
9635
0
  case VPMINSQZ128rrk:
9636
0
  case VPMINSQZ128rrkz:
9637
0
  case VPMINSQZ256rm:
9638
0
  case VPMINSQZ256rmb:
9639
0
  case VPMINSQZ256rmbk:
9640
0
  case VPMINSQZ256rmbkz:
9641
0
  case VPMINSQZ256rmk:
9642
0
  case VPMINSQZ256rmkz:
9643
0
  case VPMINSQZ256rr:
9644
0
  case VPMINSQZ256rrk:
9645
0
  case VPMINSQZ256rrkz:
9646
0
  case VPMINSQZrm:
9647
0
  case VPMINSQZrmb:
9648
0
  case VPMINSQZrmbk:
9649
0
  case VPMINSQZrmbkz:
9650
0
  case VPMINSQZrmk:
9651
0
  case VPMINSQZrmkz:
9652
0
  case VPMINSQZrr:
9653
0
  case VPMINSQZrrk:
9654
0
  case VPMINSQZrrkz:
9655
0
    return true;
9656
0
  }
9657
0
  return false;
9658
0
}
9659
9660
0
bool isVADDSD(unsigned Opcode) {
9661
0
  switch (Opcode) {
9662
0
  case VADDSDZrm_Int:
9663
0
  case VADDSDZrm_Intk:
9664
0
  case VADDSDZrm_Intkz:
9665
0
  case VADDSDZrr_Int:
9666
0
  case VADDSDZrr_Intk:
9667
0
  case VADDSDZrr_Intkz:
9668
0
  case VADDSDZrrb_Int:
9669
0
  case VADDSDZrrb_Intk:
9670
0
  case VADDSDZrrb_Intkz:
9671
0
  case VADDSDrm_Int:
9672
0
  case VADDSDrr_Int:
9673
0
    return true;
9674
0
  }
9675
0
  return false;
9676
0
}
9677
9678
0
bool isDPPS(unsigned Opcode) {
9679
0
  switch (Opcode) {
9680
0
  case DPPSrmi:
9681
0
  case DPPSrri:
9682
0
    return true;
9683
0
  }
9684
0
  return false;
9685
0
}
9686
9687
0
bool isPINSRQ(unsigned Opcode) {
9688
0
  switch (Opcode) {
9689
0
  case PINSRQrm:
9690
0
  case PINSRQrr:
9691
0
    return true;
9692
0
  }
9693
0
  return false;
9694
0
}
9695
9696
0
bool isVUCOMISS(unsigned Opcode) {
9697
0
  switch (Opcode) {
9698
0
  case VUCOMISSZrm:
9699
0
  case VUCOMISSZrr:
9700
0
  case VUCOMISSZrrb:
9701
0
  case VUCOMISSrm:
9702
0
  case VUCOMISSrr:
9703
0
    return true;
9704
0
  }
9705
0
  return false;
9706
0
}
9707
9708
0
bool isVPDPWSUD(unsigned Opcode) {
9709
0
  switch (Opcode) {
9710
0
  case VPDPWSUDYrm:
9711
0
  case VPDPWSUDYrr:
9712
0
  case VPDPWSUDrm:
9713
0
  case VPDPWSUDrr:
9714
0
    return true;
9715
0
  }
9716
0
  return false;
9717
0
}
9718
9719
0
bool isKANDNW(unsigned Opcode) {
9720
0
  return Opcode == KANDNWrr;
9721
0
}
9722
9723
0
bool isAOR(unsigned Opcode) {
9724
0
  switch (Opcode) {
9725
0
  case AOR32mr:
9726
0
  case AOR64mr:
9727
0
    return true;
9728
0
  }
9729
0
  return false;
9730
0
}
9731
9732
0
bool isPMAXUB(unsigned Opcode) {
9733
0
  switch (Opcode) {
9734
0
  case MMX_PMAXUBrm:
9735
0
  case MMX_PMAXUBrr:
9736
0
  case PMAXUBrm:
9737
0
  case PMAXUBrr:
9738
0
    return true;
9739
0
  }
9740
0
  return false;
9741
0
}
9742
9743
0
bool isANDNPD(unsigned Opcode) {
9744
0
  switch (Opcode) {
9745
0
  case ANDNPDrm:
9746
0
  case ANDNPDrr:
9747
0
    return true;
9748
0
  }
9749
0
  return false;
9750
0
}
9751
9752
0
bool isINVPCID(unsigned Opcode) {
9753
0
  switch (Opcode) {
9754
0
  case INVPCID32:
9755
0
  case INVPCID64:
9756
0
  case INVPCID64_EVEX:
9757
0
    return true;
9758
0
  }
9759
0
  return false;
9760
0
}
9761
9762
0
bool isRDGSBASE(unsigned Opcode) {
9763
0
  switch (Opcode) {
9764
0
  case RDGSBASE:
9765
0
  case RDGSBASE64:
9766
0
    return true;
9767
0
  }
9768
0
  return false;
9769
0
}
9770
9771
0
bool isVPMOVSQD(unsigned Opcode) {
9772
0
  switch (Opcode) {
9773
0
  case VPMOVSQDZ128mr:
9774
0
  case VPMOVSQDZ128mrk:
9775
0
  case VPMOVSQDZ128rr:
9776
0
  case VPMOVSQDZ128rrk:
9777
0
  case VPMOVSQDZ128rrkz:
9778
0
  case VPMOVSQDZ256mr:
9779
0
  case VPMOVSQDZ256mrk:
9780
0
  case VPMOVSQDZ256rr:
9781
0
  case VPMOVSQDZ256rrk:
9782
0
  case VPMOVSQDZ256rrkz:
9783
0
  case VPMOVSQDZmr:
9784
0
  case VPMOVSQDZmrk:
9785
0
  case VPMOVSQDZrr:
9786
0
  case VPMOVSQDZrrk:
9787
0
  case VPMOVSQDZrrkz:
9788
0
    return true;
9789
0
  }
9790
0
  return false;
9791
0
}
9792
9793
0
bool isBT(unsigned Opcode) {
9794
0
  switch (Opcode) {
9795
0
  case BT16mi8:
9796
0
  case BT16mr:
9797
0
  case BT16ri8:
9798
0
  case BT16rr:
9799
0
  case BT32mi8:
9800
0
  case BT32mr:
9801
0
  case BT32ri8:
9802
0
  case BT32rr:
9803
0
  case BT64mi8:
9804
0
  case BT64mr:
9805
0
  case BT64ri8:
9806
0
  case BT64rr:
9807
0
    return true;
9808
0
  }
9809
0
  return false;
9810
0
}
9811
9812
0
bool isVPROLVQ(unsigned Opcode) {
9813
0
  switch (Opcode) {
9814
0
  case VPROLVQZ128rm:
9815
0
  case VPROLVQZ128rmb:
9816
0
  case VPROLVQZ128rmbk:
9817
0
  case VPROLVQZ128rmbkz:
9818
0
  case VPROLVQZ128rmk:
9819
0
  case VPROLVQZ128rmkz:
9820
0
  case VPROLVQZ128rr:
9821
0
  case VPROLVQZ128rrk:
9822
0
  case VPROLVQZ128rrkz:
9823
0
  case VPROLVQZ256rm:
9824
0
  case VPROLVQZ256rmb:
9825
0
  case VPROLVQZ256rmbk:
9826
0
  case VPROLVQZ256rmbkz:
9827
0
  case VPROLVQZ256rmk:
9828
0
  case VPROLVQZ256rmkz:
9829
0
  case VPROLVQZ256rr:
9830
0
  case VPROLVQZ256rrk:
9831
0
  case VPROLVQZ256rrkz:
9832
0
  case VPROLVQZrm:
9833
0
  case VPROLVQZrmb:
9834
0
  case VPROLVQZrmbk:
9835
0
  case VPROLVQZrmbkz:
9836
0
  case VPROLVQZrmk:
9837
0
  case VPROLVQZrmkz:
9838
0
  case VPROLVQZrr:
9839
0
  case VPROLVQZrrk:
9840
0
  case VPROLVQZrrkz:
9841
0
    return true;
9842
0
  }
9843
0
  return false;
9844
0
}
9845
9846
0
bool isVFMADDSUB132PD(unsigned Opcode) {
9847
0
  switch (Opcode) {
9848
0
  case VFMADDSUB132PDYm:
9849
0
  case VFMADDSUB132PDYr:
9850
0
  case VFMADDSUB132PDZ128m:
9851
0
  case VFMADDSUB132PDZ128mb:
9852
0
  case VFMADDSUB132PDZ128mbk:
9853
0
  case VFMADDSUB132PDZ128mbkz:
9854
0
  case VFMADDSUB132PDZ128mk:
9855
0
  case VFMADDSUB132PDZ128mkz:
9856
0
  case VFMADDSUB132PDZ128r:
9857
0
  case VFMADDSUB132PDZ128rk:
9858
0
  case VFMADDSUB132PDZ128rkz:
9859
0
  case VFMADDSUB132PDZ256m:
9860
0
  case VFMADDSUB132PDZ256mb:
9861
0
  case VFMADDSUB132PDZ256mbk:
9862
0
  case VFMADDSUB132PDZ256mbkz:
9863
0
  case VFMADDSUB132PDZ256mk:
9864
0
  case VFMADDSUB132PDZ256mkz:
9865
0
  case VFMADDSUB132PDZ256r:
9866
0
  case VFMADDSUB132PDZ256rk:
9867
0
  case VFMADDSUB132PDZ256rkz:
9868
0
  case VFMADDSUB132PDZm:
9869
0
  case VFMADDSUB132PDZmb:
9870
0
  case VFMADDSUB132PDZmbk:
9871
0
  case VFMADDSUB132PDZmbkz:
9872
0
  case VFMADDSUB132PDZmk:
9873
0
  case VFMADDSUB132PDZmkz:
9874
0
  case VFMADDSUB132PDZr:
9875
0
  case VFMADDSUB132PDZrb:
9876
0
  case VFMADDSUB132PDZrbk:
9877
0
  case VFMADDSUB132PDZrbkz:
9878
0
  case VFMADDSUB132PDZrk:
9879
0
  case VFMADDSUB132PDZrkz:
9880
0
  case VFMADDSUB132PDm:
9881
0
  case VFMADDSUB132PDr:
9882
0
    return true;
9883
0
  }
9884
0
  return false;
9885
0
}
9886
9887
0
bool isRORX(unsigned Opcode) {
9888
0
  switch (Opcode) {
9889
0
  case RORX32mi:
9890
0
  case RORX32mi_EVEX:
9891
0
  case RORX32ri:
9892
0
  case RORX32ri_EVEX:
9893
0
  case RORX64mi:
9894
0
  case RORX64mi_EVEX:
9895
0
  case RORX64ri:
9896
0
  case RORX64ri_EVEX:
9897
0
    return true;
9898
0
  }
9899
0
  return false;
9900
0
}
9901
9902
0
bool isPADDUSW(unsigned Opcode) {
9903
0
  switch (Opcode) {
9904
0
  case MMX_PADDUSWrm:
9905
0
  case MMX_PADDUSWrr:
9906
0
  case PADDUSWrm:
9907
0
  case PADDUSWrr:
9908
0
    return true;
9909
0
  }
9910
0
  return false;
9911
0
}
9912
9913
0
bool isPFNACC(unsigned Opcode) {
9914
0
  switch (Opcode) {
9915
0
  case PFNACCrm:
9916
0
  case PFNACCrr:
9917
0
    return true;
9918
0
  }
9919
0
  return false;
9920
0
}
9921
9922
5
bool isAND(unsigned Opcode) {
9923
5
  switch (Opcode) {
9924
0
  case AND16i16:
9925
0
  case AND16mi:
9926
0
  case AND16mi8:
9927
0
  case AND16mi8_EVEX:
9928
0
  case AND16mi8_ND:
9929
0
  case AND16mi8_NF:
9930
0
  case AND16mi8_NF_ND:
9931
0
  case AND16mi_EVEX:
9932
0
  case AND16mi_ND:
9933
0
  case AND16mi_NF:
9934
0
  case AND16mi_NF_ND:
9935
0
  case AND16mr:
9936
0
  case AND16mr_EVEX:
9937
0
  case AND16mr_ND:
9938
0
  case AND16mr_NF:
9939
0
  case AND16mr_NF_ND:
9940
0
  case AND16ri:
9941
0
  case AND16ri8:
9942
0
  case AND16ri8_EVEX:
9943
0
  case AND16ri8_ND:
9944
0
  case AND16ri8_NF:
9945
0
  case AND16ri8_NF_ND:
9946
0
  case AND16ri_EVEX:
9947
0
  case AND16ri_ND:
9948
0
  case AND16ri_NF:
9949
0
  case AND16ri_NF_ND:
9950
0
  case AND16rm:
9951
0
  case AND16rm_EVEX:
9952
0
  case AND16rm_ND:
9953
0
  case AND16rm_NF:
9954
0
  case AND16rm_NF_ND:
9955
0
  case AND16rr:
9956
0
  case AND16rr_EVEX:
9957
0
  case AND16rr_EVEX_REV:
9958
0
  case AND16rr_ND:
9959
0
  case AND16rr_ND_REV:
9960
0
  case AND16rr_NF:
9961
0
  case AND16rr_NF_ND:
9962
0
  case AND16rr_NF_ND_REV:
9963
0
  case AND16rr_NF_REV:
9964
0
  case AND16rr_REV:
9965
0
  case AND32i32:
9966
0
  case AND32mi:
9967
0
  case AND32mi8:
9968
0
  case AND32mi8_EVEX:
9969
0
  case AND32mi8_ND:
9970
0
  case AND32mi8_NF:
9971
0
  case AND32mi8_NF_ND:
9972
0
  case AND32mi_EVEX:
9973
0
  case AND32mi_ND:
9974
0
  case AND32mi_NF:
9975
0
  case AND32mi_NF_ND:
9976
0
  case AND32mr:
9977
0
  case AND32mr_EVEX:
9978
0
  case AND32mr_ND:
9979
0
  case AND32mr_NF:
9980
0
  case AND32mr_NF_ND:
9981
0
  case AND32ri:
9982
0
  case AND32ri8:
9983
0
  case AND32ri8_EVEX:
9984
0
  case AND32ri8_ND:
9985
0
  case AND32ri8_NF:
9986
0
  case AND32ri8_NF_ND:
9987
0
  case AND32ri_EVEX:
9988
0
  case AND32ri_ND:
9989
0
  case AND32ri_NF:
9990
0
  case AND32ri_NF_ND:
9991
0
  case AND32rm:
9992
0
  case AND32rm_EVEX:
9993
0
  case AND32rm_ND:
9994
0
  case AND32rm_NF:
9995
0
  case AND32rm_NF_ND:
9996
0
  case AND32rr:
9997
0
  case AND32rr_EVEX:
9998
0
  case AND32rr_EVEX_REV:
9999
0
  case AND32rr_ND:
10000
0
  case AND32rr_ND_REV:
10001
0
  case AND32rr_NF:
10002
0
  case AND32rr_NF_ND:
10003
0
  case AND32rr_NF_ND_REV:
10004
0
  case AND32rr_NF_REV:
10005
0
  case AND32rr_REV:
10006
0
  case AND64i32:
10007
0
  case AND64mi32:
10008
0
  case AND64mi32_EVEX:
10009
0
  case AND64mi32_ND:
10010
0
  case AND64mi32_NF:
10011
0
  case AND64mi32_NF_ND:
10012
0
  case AND64mi8:
10013
0
  case AND64mi8_EVEX:
10014
0
  case AND64mi8_ND:
10015
0
  case AND64mi8_NF:
10016
0
  case AND64mi8_NF_ND:
10017
0
  case AND64mr:
10018
0
  case AND64mr_EVEX:
10019
0
  case AND64mr_ND:
10020
0
  case AND64mr_NF:
10021
0
  case AND64mr_NF_ND:
10022
0
  case AND64ri32:
10023
0
  case AND64ri32_EVEX:
10024
0
  case AND64ri32_ND:
10025
0
  case AND64ri32_NF:
10026
0
  case AND64ri32_NF_ND:
10027
0
  case AND64ri8:
10028
0
  case AND64ri8_EVEX:
10029
0
  case AND64ri8_ND:
10030
0
  case AND64ri8_NF:
10031
0
  case AND64ri8_NF_ND:
10032
0
  case AND64rm:
10033
0
  case AND64rm_EVEX:
10034
0
  case AND64rm_ND:
10035
0
  case AND64rm_NF:
10036
0
  case AND64rm_NF_ND:
10037
0
  case AND64rr:
10038
0
  case AND64rr_EVEX:
10039
0
  case AND64rr_EVEX_REV:
10040
0
  case AND64rr_ND:
10041
0
  case AND64rr_ND_REV:
10042
0
  case AND64rr_NF:
10043
0
  case AND64rr_NF_ND:
10044
0
  case AND64rr_NF_ND_REV:
10045
0
  case AND64rr_NF_REV:
10046
0
  case AND64rr_REV:
10047
0
  case AND8i8:
10048
0
  case AND8mi:
10049
0
  case AND8mi8:
10050
0
  case AND8mi_EVEX:
10051
0
  case AND8mi_ND:
10052
0
  case AND8mi_NF:
10053
0
  case AND8mi_NF_ND:
10054
0
  case AND8mr:
10055
0
  case AND8mr_EVEX:
10056
0
  case AND8mr_ND:
10057
0
  case AND8mr_NF:
10058
0
  case AND8mr_NF_ND:
10059
0
  case AND8ri:
10060
0
  case AND8ri8:
10061
0
  case AND8ri_EVEX:
10062
0
  case AND8ri_ND:
10063
0
  case AND8ri_NF:
10064
0
  case AND8ri_NF_ND:
10065
0
  case AND8rm:
10066
0
  case AND8rm_EVEX:
10067
0
  case AND8rm_ND:
10068
0
  case AND8rm_NF:
10069
0
  case AND8rm_NF_ND:
10070
0
  case AND8rr:
10071
0
  case AND8rr_EVEX:
10072
0
  case AND8rr_EVEX_REV:
10073
0
  case AND8rr_ND:
10074
0
  case AND8rr_ND_REV:
10075
0
  case AND8rr_NF:
10076
0
  case AND8rr_NF_ND:
10077
0
  case AND8rr_NF_ND_REV:
10078
0
  case AND8rr_NF_REV:
10079
0
  case AND8rr_REV:
10080
0
    return true;
10081
5
  }
10082
5
  return false;
10083
5
}
10084
10085
0
bool isPSLLQ(unsigned Opcode) {
10086
0
  switch (Opcode) {
10087
0
  case MMX_PSLLQri:
10088
0
  case MMX_PSLLQrm:
10089
0
  case MMX_PSLLQrr:
10090
0
  case PSLLQri:
10091
0
  case PSLLQrm:
10092
0
  case PSLLQrr:
10093
0
    return true;
10094
0
  }
10095
0
  return false;
10096
0
}
10097
10098
0
bool isVFMSUB132PH(unsigned Opcode) {
10099
0
  switch (Opcode) {
10100
0
  case VFMSUB132PHZ128m:
10101
0
  case VFMSUB132PHZ128mb:
10102
0
  case VFMSUB132PHZ128mbk:
10103
0
  case VFMSUB132PHZ128mbkz:
10104
0
  case VFMSUB132PHZ128mk:
10105
0
  case VFMSUB132PHZ128mkz:
10106
0
  case VFMSUB132PHZ128r:
10107
0
  case VFMSUB132PHZ128rk:
10108
0
  case VFMSUB132PHZ128rkz:
10109
0
  case VFMSUB132PHZ256m:
10110
0
  case VFMSUB132PHZ256mb:
10111
0
  case VFMSUB132PHZ256mbk:
10112
0
  case VFMSUB132PHZ256mbkz:
10113
0
  case VFMSUB132PHZ256mk:
10114
0
  case VFMSUB132PHZ256mkz:
10115
0
  case VFMSUB132PHZ256r:
10116
0
  case VFMSUB132PHZ256rk:
10117
0
  case VFMSUB132PHZ256rkz:
10118
0
  case VFMSUB132PHZm:
10119
0
  case VFMSUB132PHZmb:
10120
0
  case VFMSUB132PHZmbk:
10121
0
  case VFMSUB132PHZmbkz:
10122
0
  case VFMSUB132PHZmk:
10123
0
  case VFMSUB132PHZmkz:
10124
0
  case VFMSUB132PHZr:
10125
0
  case VFMSUB132PHZrb:
10126
0
  case VFMSUB132PHZrbk:
10127
0
  case VFMSUB132PHZrbkz:
10128
0
  case VFMSUB132PHZrk:
10129
0
  case VFMSUB132PHZrkz:
10130
0
    return true;
10131
0
  }
10132
0
  return false;
10133
0
}
10134
10135
0
bool isXSAVE(unsigned Opcode) {
10136
0
  return Opcode == XSAVE;
10137
0
}
10138
10139
0
bool isKNOTQ(unsigned Opcode) {
10140
0
  return Opcode == KNOTQrr;
10141
0
}
10142
10143
0
bool isXTEST(unsigned Opcode) {
10144
0
  return Opcode == XTEST;
10145
0
}
10146
10147
0
bool isVINSERTPS(unsigned Opcode) {
10148
0
  switch (Opcode) {
10149
0
  case VINSERTPSZrm:
10150
0
  case VINSERTPSZrr:
10151
0
  case VINSERTPSrm:
10152
0
  case VINSERTPSrr:
10153
0
    return true;
10154
0
  }
10155
0
  return false;
10156
0
}
10157
10158
0
bool isXSAVEOPT(unsigned Opcode) {
10159
0
  return Opcode == XSAVEOPT;
10160
0
}
10161
10162
0
bool isLDS(unsigned Opcode) {
10163
0
  switch (Opcode) {
10164
0
  case LDS16rm:
10165
0
  case LDS32rm:
10166
0
    return true;
10167
0
  }
10168
0
  return false;
10169
0
}
10170
10171
0
bool isVFMADDSUB213PD(unsigned Opcode) {
10172
0
  switch (Opcode) {
10173
0
  case VFMADDSUB213PDYm:
10174
0
  case VFMADDSUB213PDYr:
10175
0
  case VFMADDSUB213PDZ128m:
10176
0
  case VFMADDSUB213PDZ128mb:
10177
0
  case VFMADDSUB213PDZ128mbk:
10178
0
  case VFMADDSUB213PDZ128mbkz:
10179
0
  case VFMADDSUB213PDZ128mk:
10180
0
  case VFMADDSUB213PDZ128mkz:
10181
0
  case VFMADDSUB213PDZ128r:
10182
0
  case VFMADDSUB213PDZ128rk:
10183
0
  case VFMADDSUB213PDZ128rkz:
10184
0
  case VFMADDSUB213PDZ256m:
10185
0
  case VFMADDSUB213PDZ256mb:
10186
0
  case VFMADDSUB213PDZ256mbk:
10187
0
  case VFMADDSUB213PDZ256mbkz:
10188
0
  case VFMADDSUB213PDZ256mk:
10189
0
  case VFMADDSUB213PDZ256mkz:
10190
0
  case VFMADDSUB213PDZ256r:
10191
0
  case VFMADDSUB213PDZ256rk:
10192
0
  case VFMADDSUB213PDZ256rkz:
10193
0
  case VFMADDSUB213PDZm:
10194
0
  case VFMADDSUB213PDZmb:
10195
0
  case VFMADDSUB213PDZmbk:
10196
0
  case VFMADDSUB213PDZmbkz:
10197
0
  case VFMADDSUB213PDZmk:
10198
0
  case VFMADDSUB213PDZmkz:
10199
0
  case VFMADDSUB213PDZr:
10200
0
  case VFMADDSUB213PDZrb:
10201
0
  case VFMADDSUB213PDZrbk:
10202
0
  case VFMADDSUB213PDZrbkz:
10203
0
  case VFMADDSUB213PDZrk:
10204
0
  case VFMADDSUB213PDZrkz:
10205
0
  case VFMADDSUB213PDm:
10206
0
  case VFMADDSUB213PDr:
10207
0
    return true;
10208
0
  }
10209
0
  return false;
10210
0
}
10211
10212
0
bool isVINSERTF32X4(unsigned Opcode) {
10213
0
  switch (Opcode) {
10214
0
  case VINSERTF32x4Z256rm:
10215
0
  case VINSERTF32x4Z256rmk:
10216
0
  case VINSERTF32x4Z256rmkz:
10217
0
  case VINSERTF32x4Z256rr:
10218
0
  case VINSERTF32x4Z256rrk:
10219
0
  case VINSERTF32x4Z256rrkz:
10220
0
  case VINSERTF32x4Zrm:
10221
0
  case VINSERTF32x4Zrmk:
10222
0
  case VINSERTF32x4Zrmkz:
10223
0
  case VINSERTF32x4Zrr:
10224
0
  case VINSERTF32x4Zrrk:
10225
0
  case VINSERTF32x4Zrrkz:
10226
0
    return true;
10227
0
  }
10228
0
  return false;
10229
0
}
10230
10231
0
bool isVRSQRTPS(unsigned Opcode) {
10232
0
  switch (Opcode) {
10233
0
  case VRSQRTPSYm:
10234
0
  case VRSQRTPSYr:
10235
0
  case VRSQRTPSm:
10236
0
  case VRSQRTPSr:
10237
0
    return true;
10238
0
  }
10239
0
  return false;
10240
0
}
10241
10242
0
bool isVSUBPH(unsigned Opcode) {
10243
0
  switch (Opcode) {
10244
0
  case VSUBPHZ128rm:
10245
0
  case VSUBPHZ128rmb:
10246
0
  case VSUBPHZ128rmbk:
10247
0
  case VSUBPHZ128rmbkz:
10248
0
  case VSUBPHZ128rmk:
10249
0
  case VSUBPHZ128rmkz:
10250
0
  case VSUBPHZ128rr:
10251
0
  case VSUBPHZ128rrk:
10252
0
  case VSUBPHZ128rrkz:
10253
0
  case VSUBPHZ256rm:
10254
0
  case VSUBPHZ256rmb:
10255
0
  case VSUBPHZ256rmbk:
10256
0
  case VSUBPHZ256rmbkz:
10257
0
  case VSUBPHZ256rmk:
10258
0
  case VSUBPHZ256rmkz:
10259
0
  case VSUBPHZ256rr:
10260
0
  case VSUBPHZ256rrk:
10261
0
  case VSUBPHZ256rrkz:
10262
0
  case VSUBPHZrm:
10263
0
  case VSUBPHZrmb:
10264
0
  case VSUBPHZrmbk:
10265
0
  case VSUBPHZrmbkz:
10266
0
  case VSUBPHZrmk:
10267
0
  case VSUBPHZrmkz:
10268
0
  case VSUBPHZrr:
10269
0
  case VSUBPHZrrb:
10270
0
  case VSUBPHZrrbk:
10271
0
  case VSUBPHZrrbkz:
10272
0
  case VSUBPHZrrk:
10273
0
  case VSUBPHZrrkz:
10274
0
    return true;
10275
0
  }
10276
0
  return false;
10277
0
}
10278
10279
0
bool isPMOVSXBW(unsigned Opcode) {
10280
0
  switch (Opcode) {
10281
0
  case PMOVSXBWrm:
10282
0
  case PMOVSXBWrr:
10283
0
    return true;
10284
0
  }
10285
0
  return false;
10286
0
}
10287
10288
0
bool isVPSRLDQ(unsigned Opcode) {
10289
0
  switch (Opcode) {
10290
0
  case VPSRLDQYri:
10291
0
  case VPSRLDQZ128mi:
10292
0
  case VPSRLDQZ128ri:
10293
0
  case VPSRLDQZ256mi:
10294
0
  case VPSRLDQZ256ri:
10295
0
  case VPSRLDQZmi:
10296
0
  case VPSRLDQZri:
10297
0
  case VPSRLDQri:
10298
0
    return true;
10299
0
  }
10300
0
  return false;
10301
0
}
10302
10303
0
bool isADC(unsigned Opcode) {
10304
0
  switch (Opcode) {
10305
0
  case ADC16i16:
10306
0
  case ADC16mi:
10307
0
  case ADC16mi8:
10308
0
  case ADC16mi8_EVEX:
10309
0
  case ADC16mi8_ND:
10310
0
  case ADC16mi_EVEX:
10311
0
  case ADC16mi_ND:
10312
0
  case ADC16mr:
10313
0
  case ADC16mr_EVEX:
10314
0
  case ADC16mr_ND:
10315
0
  case ADC16ri:
10316
0
  case ADC16ri8:
10317
0
  case ADC16ri8_EVEX:
10318
0
  case ADC16ri8_ND:
10319
0
  case ADC16ri_EVEX:
10320
0
  case ADC16ri_ND:
10321
0
  case ADC16rm:
10322
0
  case ADC16rm_EVEX:
10323
0
  case ADC16rm_ND:
10324
0
  case ADC16rr:
10325
0
  case ADC16rr_EVEX:
10326
0
  case ADC16rr_EVEX_REV:
10327
0
  case ADC16rr_ND:
10328
0
  case ADC16rr_ND_REV:
10329
0
  case ADC16rr_REV:
10330
0
  case ADC32i32:
10331
0
  case ADC32mi:
10332
0
  case ADC32mi8:
10333
0
  case ADC32mi8_EVEX:
10334
0
  case ADC32mi8_ND:
10335
0
  case ADC32mi_EVEX:
10336
0
  case ADC32mi_ND:
10337
0
  case ADC32mr:
10338
0
  case ADC32mr_EVEX:
10339
0
  case ADC32mr_ND:
10340
0
  case ADC32ri:
10341
0
  case ADC32ri8:
10342
0
  case ADC32ri8_EVEX:
10343
0
  case ADC32ri8_ND:
10344
0
  case ADC32ri_EVEX:
10345
0
  case ADC32ri_ND:
10346
0
  case ADC32rm:
10347
0
  case ADC32rm_EVEX:
10348
0
  case ADC32rm_ND:
10349
0
  case ADC32rr:
10350
0
  case ADC32rr_EVEX:
10351
0
  case ADC32rr_EVEX_REV:
10352
0
  case ADC32rr_ND:
10353
0
  case ADC32rr_ND_REV:
10354
0
  case ADC32rr_REV:
10355
0
  case ADC64i32:
10356
0
  case ADC64mi32:
10357
0
  case ADC64mi32_EVEX:
10358
0
  case ADC64mi32_ND:
10359
0
  case ADC64mi8:
10360
0
  case ADC64mi8_EVEX:
10361
0
  case ADC64mi8_ND:
10362
0
  case ADC64mr:
10363
0
  case ADC64mr_EVEX:
10364
0
  case ADC64mr_ND:
10365
0
  case ADC64ri32:
10366
0
  case ADC64ri32_EVEX:
10367
0
  case ADC64ri32_ND:
10368
0
  case ADC64ri8:
10369
0
  case ADC64ri8_EVEX:
10370
0
  case ADC64ri8_ND:
10371
0
  case ADC64rm:
10372
0
  case ADC64rm_EVEX:
10373
0
  case ADC64rm_ND:
10374
0
  case ADC64rr:
10375
0
  case ADC64rr_EVEX:
10376
0
  case ADC64rr_EVEX_REV:
10377
0
  case ADC64rr_ND:
10378
0
  case ADC64rr_ND_REV:
10379
0
  case ADC64rr_REV:
10380
0
  case ADC8i8:
10381
0
  case ADC8mi:
10382
0
  case ADC8mi8:
10383
0
  case ADC8mi_EVEX:
10384
0
  case ADC8mi_ND:
10385
0
  case ADC8mr:
10386
0
  case ADC8mr_EVEX:
10387
0
  case ADC8mr_ND:
10388
0
  case ADC8ri:
10389
0
  case ADC8ri8:
10390
0
  case ADC8ri_EVEX:
10391
0
  case ADC8ri_ND:
10392
0
  case ADC8rm:
10393
0
  case ADC8rm_EVEX:
10394
0
  case ADC8rm_ND:
10395
0
  case ADC8rr:
10396
0
  case ADC8rr_EVEX:
10397
0
  case ADC8rr_EVEX_REV:
10398
0
  case ADC8rr_ND:
10399
0
  case ADC8rr_ND_REV:
10400
0
  case ADC8rr_REV:
10401
0
    return true;
10402
0
  }
10403
0
  return false;
10404
0
}
10405
10406
0
bool isPHADDD(unsigned Opcode) {
10407
0
  switch (Opcode) {
10408
0
  case MMX_PHADDDrm:
10409
0
  case MMX_PHADDDrr:
10410
0
  case PHADDDrm:
10411
0
  case PHADDDrr:
10412
0
    return true;
10413
0
  }
10414
0
  return false;
10415
0
}
10416
10417
0
bool isVMINPH(unsigned Opcode) {
10418
0
  switch (Opcode) {
10419
0
  case VMINPHZ128rm:
10420
0
  case VMINPHZ128rmb:
10421
0
  case VMINPHZ128rmbk:
10422
0
  case VMINPHZ128rmbkz:
10423
0
  case VMINPHZ128rmk:
10424
0
  case VMINPHZ128rmkz:
10425
0
  case VMINPHZ128rr:
10426
0
  case VMINPHZ128rrk:
10427
0
  case VMINPHZ128rrkz:
10428
0
  case VMINPHZ256rm:
10429
0
  case VMINPHZ256rmb:
10430
0
  case VMINPHZ256rmbk:
10431
0
  case VMINPHZ256rmbkz:
10432
0
  case VMINPHZ256rmk:
10433
0
  case VMINPHZ256rmkz:
10434
0
  case VMINPHZ256rr:
10435
0
  case VMINPHZ256rrk:
10436
0
  case VMINPHZ256rrkz:
10437
0
  case VMINPHZrm:
10438
0
  case VMINPHZrmb:
10439
0
  case VMINPHZrmbk:
10440
0
  case VMINPHZrmbkz:
10441
0
  case VMINPHZrmk:
10442
0
  case VMINPHZrmkz:
10443
0
  case VMINPHZrr:
10444
0
  case VMINPHZrrb:
10445
0
  case VMINPHZrrbk:
10446
0
  case VMINPHZrrbkz:
10447
0
  case VMINPHZrrk:
10448
0
  case VMINPHZrrkz:
10449
0
    return true;
10450
0
  }
10451
0
  return false;
10452
0
}
10453
10454
0
bool isVMINSD(unsigned Opcode) {
10455
0
  switch (Opcode) {
10456
0
  case VMINSDZrm_Int:
10457
0
  case VMINSDZrm_Intk:
10458
0
  case VMINSDZrm_Intkz:
10459
0
  case VMINSDZrr_Int:
10460
0
  case VMINSDZrr_Intk:
10461
0
  case VMINSDZrr_Intkz:
10462
0
  case VMINSDZrrb_Int:
10463
0
  case VMINSDZrrb_Intk:
10464
0
  case VMINSDZrrb_Intkz:
10465
0
  case VMINSDrm_Int:
10466
0
  case VMINSDrr_Int:
10467
0
    return true;
10468
0
  }
10469
0
  return false;
10470
0
}
10471
10472
0
bool isVROUNDPD(unsigned Opcode) {
10473
0
  switch (Opcode) {
10474
0
  case VROUNDPDYm:
10475
0
  case VROUNDPDYr:
10476
0
  case VROUNDPDm:
10477
0
  case VROUNDPDr:
10478
0
    return true;
10479
0
  }
10480
0
  return false;
10481
0
}
10482
10483
0
bool isVFCMADDCPH(unsigned Opcode) {
10484
0
  switch (Opcode) {
10485
0
  case VFCMADDCPHZ128m:
10486
0
  case VFCMADDCPHZ128mb:
10487
0
  case VFCMADDCPHZ128mbk:
10488
0
  case VFCMADDCPHZ128mbkz:
10489
0
  case VFCMADDCPHZ128mk:
10490
0
  case VFCMADDCPHZ128mkz:
10491
0
  case VFCMADDCPHZ128r:
10492
0
  case VFCMADDCPHZ128rk:
10493
0
  case VFCMADDCPHZ128rkz:
10494
0
  case VFCMADDCPHZ256m:
10495
0
  case VFCMADDCPHZ256mb:
10496
0
  case VFCMADDCPHZ256mbk:
10497
0
  case VFCMADDCPHZ256mbkz:
10498
0
  case VFCMADDCPHZ256mk:
10499
0
  case VFCMADDCPHZ256mkz:
10500
0
  case VFCMADDCPHZ256r:
10501
0
  case VFCMADDCPHZ256rk:
10502
0
  case VFCMADDCPHZ256rkz:
10503
0
  case VFCMADDCPHZm:
10504
0
  case VFCMADDCPHZmb:
10505
0
  case VFCMADDCPHZmbk:
10506
0
  case VFCMADDCPHZmbkz:
10507
0
  case VFCMADDCPHZmk:
10508
0
  case VFCMADDCPHZmkz:
10509
0
  case VFCMADDCPHZr:
10510
0
  case VFCMADDCPHZrb:
10511
0
  case VFCMADDCPHZrbk:
10512
0
  case VFCMADDCPHZrbkz:
10513
0
  case VFCMADDCPHZrk:
10514
0
  case VFCMADDCPHZrkz:
10515
0
    return true;
10516
0
  }
10517
0
  return false;
10518
0
}
10519
10520
0
bool isINCSSPQ(unsigned Opcode) {
10521
0
  return Opcode == INCSSPQ;
10522
0
}
10523
10524
0
bool isVPUNPCKLDQ(unsigned Opcode) {
10525
0
  switch (Opcode) {
10526
0
  case VPUNPCKLDQYrm:
10527
0
  case VPUNPCKLDQYrr:
10528
0
  case VPUNPCKLDQZ128rm:
10529
0
  case VPUNPCKLDQZ128rmb:
10530
0
  case VPUNPCKLDQZ128rmbk:
10531
0
  case VPUNPCKLDQZ128rmbkz:
10532
0
  case VPUNPCKLDQZ128rmk:
10533
0
  case VPUNPCKLDQZ128rmkz:
10534
0
  case VPUNPCKLDQZ128rr:
10535
0
  case VPUNPCKLDQZ128rrk:
10536
0
  case VPUNPCKLDQZ128rrkz:
10537
0
  case VPUNPCKLDQZ256rm:
10538
0
  case VPUNPCKLDQZ256rmb:
10539
0
  case VPUNPCKLDQZ256rmbk:
10540
0
  case VPUNPCKLDQZ256rmbkz:
10541
0
  case VPUNPCKLDQZ256rmk:
10542
0
  case VPUNPCKLDQZ256rmkz:
10543
0
  case VPUNPCKLDQZ256rr:
10544
0
  case VPUNPCKLDQZ256rrk:
10545
0
  case VPUNPCKLDQZ256rrkz:
10546
0
  case VPUNPCKLDQZrm:
10547
0
  case VPUNPCKLDQZrmb:
10548
0
  case VPUNPCKLDQZrmbk:
10549
0
  case VPUNPCKLDQZrmbkz:
10550
0
  case VPUNPCKLDQZrmk:
10551
0
  case VPUNPCKLDQZrmkz:
10552
0
  case VPUNPCKLDQZrr:
10553
0
  case VPUNPCKLDQZrrk:
10554
0
  case VPUNPCKLDQZrrkz:
10555
0
  case VPUNPCKLDQrm:
10556
0
  case VPUNPCKLDQrr:
10557
0
    return true;
10558
0
  }
10559
0
  return false;
10560
0
}
10561
10562
0
bool isVMINSH(unsigned Opcode) {
10563
0
  switch (Opcode) {
10564
0
  case VMINSHZrm_Int:
10565
0
  case VMINSHZrm_Intk:
10566
0
  case VMINSHZrm_Intkz:
10567
0
  case VMINSHZrr_Int:
10568
0
  case VMINSHZrr_Intk:
10569
0
  case VMINSHZrr_Intkz:
10570
0
  case VMINSHZrrb_Int:
10571
0
  case VMINSHZrrb_Intk:
10572
0
  case VMINSHZrrb_Intkz:
10573
0
    return true;
10574
0
  }
10575
0
  return false;
10576
0
}
10577
10578
0
bool isINSERTQ(unsigned Opcode) {
10579
0
  switch (Opcode) {
10580
0
  case INSERTQ:
10581
0
  case INSERTQI:
10582
0
    return true;
10583
0
  }
10584
0
  return false;
10585
0
}
10586
10587
0
bool isBLCI(unsigned Opcode) {
10588
0
  switch (Opcode) {
10589
0
  case BLCI32rm:
10590
0
  case BLCI32rr:
10591
0
  case BLCI64rm:
10592
0
  case BLCI64rr:
10593
0
    return true;
10594
0
  }
10595
0
  return false;
10596
0
}
10597
10598
0
bool isHLT(unsigned Opcode) {
10599
0
  return Opcode == HLT;
10600
0
}
10601
10602
0
bool isVPCOMUW(unsigned Opcode) {
10603
0
  switch (Opcode) {
10604
0
  case VPCOMUWmi:
10605
0
  case VPCOMUWri:
10606
0
    return true;
10607
0
  }
10608
0
  return false;
10609
0
}
10610
10611
0
bool isVPMOVSXDQ(unsigned Opcode) {
10612
0
  switch (Opcode) {
10613
0
  case VPMOVSXDQYrm:
10614
0
  case VPMOVSXDQYrr:
10615
0
  case VPMOVSXDQZ128rm:
10616
0
  case VPMOVSXDQZ128rmk:
10617
0
  case VPMOVSXDQZ128rmkz:
10618
0
  case VPMOVSXDQZ128rr:
10619
0
  case VPMOVSXDQZ128rrk:
10620
0
  case VPMOVSXDQZ128rrkz:
10621
0
  case VPMOVSXDQZ256rm:
10622
0
  case VPMOVSXDQZ256rmk:
10623
0
  case VPMOVSXDQZ256rmkz:
10624
0
  case VPMOVSXDQZ256rr:
10625
0
  case VPMOVSXDQZ256rrk:
10626
0
  case VPMOVSXDQZ256rrkz:
10627
0
  case VPMOVSXDQZrm:
10628
0
  case VPMOVSXDQZrmk:
10629
0
  case VPMOVSXDQZrmkz:
10630
0
  case VPMOVSXDQZrr:
10631
0
  case VPMOVSXDQZrrk:
10632
0
  case VPMOVSXDQZrrkz:
10633
0
  case VPMOVSXDQrm:
10634
0
  case VPMOVSXDQrr:
10635
0
    return true;
10636
0
  }
10637
0
  return false;
10638
0
}
10639
10640
0
bool isVFNMSUB231PS(unsigned Opcode) {
10641
0
  switch (Opcode) {
10642
0
  case VFNMSUB231PSYm:
10643
0
  case VFNMSUB231PSYr:
10644
0
  case VFNMSUB231PSZ128m:
10645
0
  case VFNMSUB231PSZ128mb:
10646
0
  case VFNMSUB231PSZ128mbk:
10647
0
  case VFNMSUB231PSZ128mbkz:
10648
0
  case VFNMSUB231PSZ128mk:
10649
0
  case VFNMSUB231PSZ128mkz:
10650
0
  case VFNMSUB231PSZ128r:
10651
0
  case VFNMSUB231PSZ128rk:
10652
0
  case VFNMSUB231PSZ128rkz:
10653
0
  case VFNMSUB231PSZ256m:
10654
0
  case VFNMSUB231PSZ256mb:
10655
0
  case VFNMSUB231PSZ256mbk:
10656
0
  case VFNMSUB231PSZ256mbkz:
10657
0
  case VFNMSUB231PSZ256mk:
10658
0
  case VFNMSUB231PSZ256mkz:
10659
0
  case VFNMSUB231PSZ256r:
10660
0
  case VFNMSUB231PSZ256rk:
10661
0
  case VFNMSUB231PSZ256rkz:
10662
0
  case VFNMSUB231PSZm:
10663
0
  case VFNMSUB231PSZmb:
10664
0
  case VFNMSUB231PSZmbk:
10665
0
  case VFNMSUB231PSZmbkz:
10666
0
  case VFNMSUB231PSZmk:
10667
0
  case VFNMSUB231PSZmkz:
10668
0
  case VFNMSUB231PSZr:
10669
0
  case VFNMSUB231PSZrb:
10670
0
  case VFNMSUB231PSZrbk:
10671
0
  case VFNMSUB231PSZrbkz:
10672
0
  case VFNMSUB231PSZrk:
10673
0
  case VFNMSUB231PSZrkz:
10674
0
  case VFNMSUB231PSm:
10675
0
  case VFNMSUB231PSr:
10676
0
    return true;
10677
0
  }
10678
0
  return false;
10679
0
}
10680
10681
0
bool isVFNMSUB213SH(unsigned Opcode) {
10682
0
  switch (Opcode) {
10683
0
  case VFNMSUB213SHZm_Int:
10684
0
  case VFNMSUB213SHZm_Intk:
10685
0
  case VFNMSUB213SHZm_Intkz:
10686
0
  case VFNMSUB213SHZr_Int:
10687
0
  case VFNMSUB213SHZr_Intk:
10688
0
  case VFNMSUB213SHZr_Intkz:
10689
0
  case VFNMSUB213SHZrb_Int:
10690
0
  case VFNMSUB213SHZrb_Intk:
10691
0
  case VFNMSUB213SHZrb_Intkz:
10692
0
    return true;
10693
0
  }
10694
0
  return false;
10695
0
}
10696
10697
0
bool isVCVTTPD2UQQ(unsigned Opcode) {
10698
0
  switch (Opcode) {
10699
0
  case VCVTTPD2UQQZ128rm:
10700
0
  case VCVTTPD2UQQZ128rmb:
10701
0
  case VCVTTPD2UQQZ128rmbk:
10702
0
  case VCVTTPD2UQQZ128rmbkz:
10703
0
  case VCVTTPD2UQQZ128rmk:
10704
0
  case VCVTTPD2UQQZ128rmkz:
10705
0
  case VCVTTPD2UQQZ128rr:
10706
0
  case VCVTTPD2UQQZ128rrk:
10707
0
  case VCVTTPD2UQQZ128rrkz:
10708
0
  case VCVTTPD2UQQZ256rm:
10709
0
  case VCVTTPD2UQQZ256rmb:
10710
0
  case VCVTTPD2UQQZ256rmbk:
10711
0
  case VCVTTPD2UQQZ256rmbkz:
10712
0
  case VCVTTPD2UQQZ256rmk:
10713
0
  case VCVTTPD2UQQZ256rmkz:
10714
0
  case VCVTTPD2UQQZ256rr:
10715
0
  case VCVTTPD2UQQZ256rrk:
10716
0
  case VCVTTPD2UQQZ256rrkz:
10717
0
  case VCVTTPD2UQQZrm:
10718
0
  case VCVTTPD2UQQZrmb:
10719
0
  case VCVTTPD2UQQZrmbk:
10720
0
  case VCVTTPD2UQQZrmbkz:
10721
0
  case VCVTTPD2UQQZrmk:
10722
0
  case VCVTTPD2UQQZrmkz:
10723
0
  case VCVTTPD2UQQZrr:
10724
0
  case VCVTTPD2UQQZrrb:
10725
0
  case VCVTTPD2UQQZrrbk:
10726
0
  case VCVTTPD2UQQZrrbkz:
10727
0
  case VCVTTPD2UQQZrrk:
10728
0
  case VCVTTPD2UQQZrrkz:
10729
0
    return true;
10730
0
  }
10731
0
  return false;
10732
0
}
10733
10734
0
bool isSQRTSS(unsigned Opcode) {
10735
0
  switch (Opcode) {
10736
0
  case SQRTSSm_Int:
10737
0
  case SQRTSSr_Int:
10738
0
    return true;
10739
0
  }
10740
0
  return false;
10741
0
}
10742
10743
0
bool isIMUL(unsigned Opcode) {
10744
0
  switch (Opcode) {
10745
0
  case IMUL16m:
10746
0
  case IMUL16m_EVEX:
10747
0
  case IMUL16m_NF:
10748
0
  case IMUL16r:
10749
0
  case IMUL16r_EVEX:
10750
0
  case IMUL16r_NF:
10751
0
  case IMUL16rm:
10752
0
  case IMUL16rm_EVEX:
10753
0
  case IMUL16rm_ND:
10754
0
  case IMUL16rm_NF:
10755
0
  case IMUL16rm_NF_ND:
10756
0
  case IMUL16rmi:
10757
0
  case IMUL16rmi8:
10758
0
  case IMUL16rmi8_EVEX:
10759
0
  case IMUL16rmi8_NF:
10760
0
  case IMUL16rmi_EVEX:
10761
0
  case IMUL16rmi_NF:
10762
0
  case IMUL16rr:
10763
0
  case IMUL16rr_EVEX:
10764
0
  case IMUL16rr_ND:
10765
0
  case IMUL16rr_NF:
10766
0
  case IMUL16rr_NF_ND:
10767
0
  case IMUL16rri:
10768
0
  case IMUL16rri8:
10769
0
  case IMUL16rri8_EVEX:
10770
0
  case IMUL16rri8_NF:
10771
0
  case IMUL16rri_EVEX:
10772
0
  case IMUL16rri_NF:
10773
0
  case IMUL32m:
10774
0
  case IMUL32m_EVEX:
10775
0
  case IMUL32m_NF:
10776
0
  case IMUL32r:
10777
0
  case IMUL32r_EVEX:
10778
0
  case IMUL32r_NF:
10779
0
  case IMUL32rm:
10780
0
  case IMUL32rm_EVEX:
10781
0
  case IMUL32rm_ND:
10782
0
  case IMUL32rm_NF:
10783
0
  case IMUL32rm_NF_ND:
10784
0
  case IMUL32rmi:
10785
0
  case IMUL32rmi8:
10786
0
  case IMUL32rmi8_EVEX:
10787
0
  case IMUL32rmi8_NF:
10788
0
  case IMUL32rmi_EVEX:
10789
0
  case IMUL32rmi_NF:
10790
0
  case IMUL32rr:
10791
0
  case IMUL32rr_EVEX:
10792
0
  case IMUL32rr_ND:
10793
0
  case IMUL32rr_NF:
10794
0
  case IMUL32rr_NF_ND:
10795
0
  case IMUL32rri:
10796
0
  case IMUL32rri8:
10797
0
  case IMUL32rri8_EVEX:
10798
0
  case IMUL32rri8_NF:
10799
0
  case IMUL32rri_EVEX:
10800
0
  case IMUL32rri_NF:
10801
0
  case IMUL64m:
10802
0
  case IMUL64m_EVEX:
10803
0
  case IMUL64m_NF:
10804
0
  case IMUL64r:
10805
0
  case IMUL64r_EVEX:
10806
0
  case IMUL64r_NF:
10807
0
  case IMUL64rm:
10808
0
  case IMUL64rm_EVEX:
10809
0
  case IMUL64rm_ND:
10810
0
  case IMUL64rm_NF:
10811
0
  case IMUL64rm_NF_ND:
10812
0
  case IMUL64rmi32:
10813
0
  case IMUL64rmi32_EVEX:
10814
0
  case IMUL64rmi32_NF:
10815
0
  case IMUL64rmi8:
10816
0
  case IMUL64rmi8_EVEX:
10817
0
  case IMUL64rmi8_NF:
10818
0
  case IMUL64rr:
10819
0
  case IMUL64rr_EVEX:
10820
0
  case IMUL64rr_ND:
10821
0
  case IMUL64rr_NF:
10822
0
  case IMUL64rr_NF_ND:
10823
0
  case IMUL64rri32:
10824
0
  case IMUL64rri32_EVEX:
10825
0
  case IMUL64rri32_NF:
10826
0
  case IMUL64rri8:
10827
0
  case IMUL64rri8_EVEX:
10828
0
  case IMUL64rri8_NF:
10829
0
  case IMUL8m:
10830
0
  case IMUL8m_EVEX:
10831
0
  case IMUL8m_NF:
10832
0
  case IMUL8r:
10833
0
  case IMUL8r_EVEX:
10834
0
  case IMUL8r_NF:
10835
0
    return true;
10836
0
  }
10837
0
  return false;
10838
0
}
10839
10840
0
bool isVCVTSS2SI(unsigned Opcode) {
10841
0
  switch (Opcode) {
10842
0
  case VCVTSS2SI64Zrm_Int:
10843
0
  case VCVTSS2SI64Zrr_Int:
10844
0
  case VCVTSS2SI64Zrrb_Int:
10845
0
  case VCVTSS2SI64rm_Int:
10846
0
  case VCVTSS2SI64rr_Int:
10847
0
  case VCVTSS2SIZrm_Int:
10848
0
  case VCVTSS2SIZrr_Int:
10849
0
  case VCVTSS2SIZrrb_Int:
10850
0
  case VCVTSS2SIrm_Int:
10851
0
  case VCVTSS2SIrr_Int:
10852
0
    return true;
10853
0
  }
10854
0
  return false;
10855
0
}
10856
10857
0
bool isPUSHAW(unsigned Opcode) {
10858
0
  return Opcode == PUSHA16;
10859
0
}
10860
10861
0
bool isSTOSD(unsigned Opcode) {
10862
0
  return Opcode == STOSL;
10863
0
}
10864
10865
0
bool isPSRLDQ(unsigned Opcode) {
10866
0
  return Opcode == PSRLDQri;
10867
0
}
10868
10869
0
bool isVSCATTERQPS(unsigned Opcode) {
10870
0
  switch (Opcode) {
10871
0
  case VSCATTERQPSZ128mr:
10872
0
  case VSCATTERQPSZ256mr:
10873
0
  case VSCATTERQPSZmr:
10874
0
    return true;
10875
0
  }
10876
0
  return false;
10877
0
}
10878
10879
0
bool isFIDIV(unsigned Opcode) {
10880
0
  switch (Opcode) {
10881
0
  case DIV_FI16m:
10882
0
  case DIV_FI32m:
10883
0
    return true;
10884
0
  }
10885
0
  return false;
10886
0
}
10887
10888
0
bool isVFMSUB213PD(unsigned Opcode) {
10889
0
  switch (Opcode) {
10890
0
  case VFMSUB213PDYm:
10891
0
  case VFMSUB213PDYr:
10892
0
  case VFMSUB213PDZ128m:
10893
0
  case VFMSUB213PDZ128mb:
10894
0
  case VFMSUB213PDZ128mbk:
10895
0
  case VFMSUB213PDZ128mbkz:
10896
0
  case VFMSUB213PDZ128mk:
10897
0
  case VFMSUB213PDZ128mkz:
10898
0
  case VFMSUB213PDZ128r:
10899
0
  case VFMSUB213PDZ128rk:
10900
0
  case VFMSUB213PDZ128rkz:
10901
0
  case VFMSUB213PDZ256m:
10902
0
  case VFMSUB213PDZ256mb:
10903
0
  case VFMSUB213PDZ256mbk:
10904
0
  case VFMSUB213PDZ256mbkz:
10905
0
  case VFMSUB213PDZ256mk:
10906
0
  case VFMSUB213PDZ256mkz:
10907
0
  case VFMSUB213PDZ256r:
10908
0
  case VFMSUB213PDZ256rk:
10909
0
  case VFMSUB213PDZ256rkz:
10910
0
  case VFMSUB213PDZm:
10911
0
  case VFMSUB213PDZmb:
10912
0
  case VFMSUB213PDZmbk:
10913
0
  case VFMSUB213PDZmbkz:
10914
0
  case VFMSUB213PDZmk:
10915
0
  case VFMSUB213PDZmkz:
10916
0
  case VFMSUB213PDZr:
10917
0
  case VFMSUB213PDZrb:
10918
0
  case VFMSUB213PDZrbk:
10919
0
  case VFMSUB213PDZrbkz:
10920
0
  case VFMSUB213PDZrk:
10921
0
  case VFMSUB213PDZrkz:
10922
0
  case VFMSUB213PDm:
10923
0
  case VFMSUB213PDr:
10924
0
    return true;
10925
0
  }
10926
0
  return false;
10927
0
}
10928
10929
0
bool isVFMADDSUB231PH(unsigned Opcode) {
10930
0
  switch (Opcode) {
10931
0
  case VFMADDSUB231PHZ128m:
10932
0
  case VFMADDSUB231PHZ128mb:
10933
0
  case VFMADDSUB231PHZ128mbk:
10934
0
  case VFMADDSUB231PHZ128mbkz:
10935
0
  case VFMADDSUB231PHZ128mk:
10936
0
  case VFMADDSUB231PHZ128mkz:
10937
0
  case VFMADDSUB231PHZ128r:
10938
0
  case VFMADDSUB231PHZ128rk:
10939
0
  case VFMADDSUB231PHZ128rkz:
10940
0
  case VFMADDSUB231PHZ256m:
10941
0
  case VFMADDSUB231PHZ256mb:
10942
0
  case VFMADDSUB231PHZ256mbk:
10943
0
  case VFMADDSUB231PHZ256mbkz:
10944
0
  case VFMADDSUB231PHZ256mk:
10945
0
  case VFMADDSUB231PHZ256mkz:
10946
0
  case VFMADDSUB231PHZ256r:
10947
0
  case VFMADDSUB231PHZ256rk:
10948
0
  case VFMADDSUB231PHZ256rkz:
10949
0
  case VFMADDSUB231PHZm:
10950
0
  case VFMADDSUB231PHZmb:
10951
0
  case VFMADDSUB231PHZmbk:
10952
0
  case VFMADDSUB231PHZmbkz:
10953
0
  case VFMADDSUB231PHZmk:
10954
0
  case VFMADDSUB231PHZmkz:
10955
0
  case VFMADDSUB231PHZr:
10956
0
  case VFMADDSUB231PHZrb:
10957
0
  case VFMADDSUB231PHZrbk:
10958
0
  case VFMADDSUB231PHZrbkz:
10959
0
  case VFMADDSUB231PHZrk:
10960
0
  case VFMADDSUB231PHZrkz:
10961
0
    return true;
10962
0
  }
10963
0
  return false;
10964
0
}
10965
10966
0
bool isTDCALL(unsigned Opcode) {
10967
0
  return Opcode == TDCALL;
10968
0
}
10969
10970
0
bool isPVALIDATE(unsigned Opcode) {
10971
0
  switch (Opcode) {
10972
0
  case PVALIDATE32:
10973
0
  case PVALIDATE64:
10974
0
    return true;
10975
0
  }
10976
0
  return false;
10977
0
}
10978
10979
0
bool isVPSHUFLW(unsigned Opcode) {
10980
0
  switch (Opcode) {
10981
0
  case VPSHUFLWYmi:
10982
0
  case VPSHUFLWYri:
10983
0
  case VPSHUFLWZ128mi:
10984
0
  case VPSHUFLWZ128mik:
10985
0
  case VPSHUFLWZ128mikz:
10986
0
  case VPSHUFLWZ128ri:
10987
0
  case VPSHUFLWZ128rik:
10988
0
  case VPSHUFLWZ128rikz:
10989
0
  case VPSHUFLWZ256mi:
10990
0
  case VPSHUFLWZ256mik:
10991
0
  case VPSHUFLWZ256mikz:
10992
0
  case VPSHUFLWZ256ri:
10993
0
  case VPSHUFLWZ256rik:
10994
0
  case VPSHUFLWZ256rikz:
10995
0
  case VPSHUFLWZmi:
10996
0
  case VPSHUFLWZmik:
10997
0
  case VPSHUFLWZmikz:
10998
0
  case VPSHUFLWZri:
10999
0
  case VPSHUFLWZrik:
11000
0
  case VPSHUFLWZrikz:
11001
0
  case VPSHUFLWmi:
11002
0
  case VPSHUFLWri:
11003
0
    return true;
11004
0
  }
11005
0
  return false;
11006
0
}
11007
11008
0
bool isPCLMULQDQ(unsigned Opcode) {
11009
0
  switch (Opcode) {
11010
0
  case PCLMULQDQrm:
11011
0
  case PCLMULQDQrr:
11012
0
    return true;
11013
0
  }
11014
0
  return false;
11015
0
}
11016
11017
0
bool isCMPXCHG8B(unsigned Opcode) {
11018
0
  return Opcode == CMPXCHG8B;
11019
0
}
11020
11021
0
bool isVPMOVM2B(unsigned Opcode) {
11022
0
  switch (Opcode) {
11023
0
  case VPMOVM2BZ128rr:
11024
0
  case VPMOVM2BZ256rr:
11025
0
  case VPMOVM2BZrr:
11026
0
    return true;
11027
0
  }
11028
0
  return false;
11029
0
}
11030
11031
0
bool isVCVTUDQ2PH(unsigned Opcode) {
11032
0
  switch (Opcode) {
11033
0
  case VCVTUDQ2PHZ128rm:
11034
0
  case VCVTUDQ2PHZ128rmb:
11035
0
  case VCVTUDQ2PHZ128rmbk:
11036
0
  case VCVTUDQ2PHZ128rmbkz:
11037
0
  case VCVTUDQ2PHZ128rmk:
11038
0
  case VCVTUDQ2PHZ128rmkz:
11039
0
  case VCVTUDQ2PHZ128rr:
11040
0
  case VCVTUDQ2PHZ128rrk:
11041
0
  case VCVTUDQ2PHZ128rrkz:
11042
0
  case VCVTUDQ2PHZ256rm:
11043
0
  case VCVTUDQ2PHZ256rmb:
11044
0
  case VCVTUDQ2PHZ256rmbk:
11045
0
  case VCVTUDQ2PHZ256rmbkz:
11046
0
  case VCVTUDQ2PHZ256rmk:
11047
0
  case VCVTUDQ2PHZ256rmkz:
11048
0
  case VCVTUDQ2PHZ256rr:
11049
0
  case VCVTUDQ2PHZ256rrk:
11050
0
  case VCVTUDQ2PHZ256rrkz:
11051
0
  case VCVTUDQ2PHZrm:
11052
0
  case VCVTUDQ2PHZrmb:
11053
0
  case VCVTUDQ2PHZrmbk:
11054
0
  case VCVTUDQ2PHZrmbkz:
11055
0
  case VCVTUDQ2PHZrmk:
11056
0
  case VCVTUDQ2PHZrmkz:
11057
0
  case VCVTUDQ2PHZrr:
11058
0
  case VCVTUDQ2PHZrrb:
11059
0
  case VCVTUDQ2PHZrrbk:
11060
0
  case VCVTUDQ2PHZrrbkz:
11061
0
  case VCVTUDQ2PHZrrk:
11062
0
  case VCVTUDQ2PHZrrkz:
11063
0
    return true;
11064
0
  }
11065
0
  return false;
11066
0
}
11067
11068
0
bool isPEXTRQ(unsigned Opcode) {
11069
0
  switch (Opcode) {
11070
0
  case PEXTRQmr:
11071
0
  case PEXTRQrr:
11072
0
    return true;
11073
0
  }
11074
0
  return false;
11075
0
}
11076
11077
0
bool isXCRYPTCTR(unsigned Opcode) {
11078
0
  return Opcode == XCRYPTCTR;
11079
0
}
11080
11081
0
bool isVREDUCEPH(unsigned Opcode) {
11082
0
  switch (Opcode) {
11083
0
  case VREDUCEPHZ128rmbi:
11084
0
  case VREDUCEPHZ128rmbik:
11085
0
  case VREDUCEPHZ128rmbikz:
11086
0
  case VREDUCEPHZ128rmi:
11087
0
  case VREDUCEPHZ128rmik:
11088
0
  case VREDUCEPHZ128rmikz:
11089
0
  case VREDUCEPHZ128rri:
11090
0
  case VREDUCEPHZ128rrik:
11091
0
  case VREDUCEPHZ128rrikz:
11092
0
  case VREDUCEPHZ256rmbi:
11093
0
  case VREDUCEPHZ256rmbik:
11094
0
  case VREDUCEPHZ256rmbikz:
11095
0
  case VREDUCEPHZ256rmi:
11096
0
  case VREDUCEPHZ256rmik:
11097
0
  case VREDUCEPHZ256rmikz:
11098
0
  case VREDUCEPHZ256rri:
11099
0
  case VREDUCEPHZ256rrik:
11100
0
  case VREDUCEPHZ256rrikz:
11101
0
  case VREDUCEPHZrmbi:
11102
0
  case VREDUCEPHZrmbik:
11103
0
  case VREDUCEPHZrmbikz:
11104
0
  case VREDUCEPHZrmi:
11105
0
  case VREDUCEPHZrmik:
11106
0
  case VREDUCEPHZrmikz:
11107
0
  case VREDUCEPHZrri:
11108
0
  case VREDUCEPHZrrib:
11109
0
  case VREDUCEPHZrribk:
11110
0
  case VREDUCEPHZrribkz:
11111
0
  case VREDUCEPHZrrik:
11112
0
  case VREDUCEPHZrrikz:
11113
0
    return true;
11114
0
  }
11115
0
  return false;
11116
0
}
11117
11118
0
bool isUCOMISD(unsigned Opcode) {
11119
0
  switch (Opcode) {
11120
0
  case UCOMISDrm:
11121
0
  case UCOMISDrr:
11122
0
    return true;
11123
0
  }
11124
0
  return false;
11125
0
}
11126
11127
0
bool isOUTSD(unsigned Opcode) {
11128
0
  return Opcode == OUTSL;
11129
0
}
11130
11131
0
bool isSUBSS(unsigned Opcode) {
11132
0
  switch (Opcode) {
11133
0
  case SUBSSrm_Int:
11134
0
  case SUBSSrr_Int:
11135
0
    return true;
11136
0
  }
11137
0
  return false;
11138
0
}
11139
11140
0
bool isVFMSUBPS(unsigned Opcode) {
11141
0
  switch (Opcode) {
11142
0
  case VFMSUBPS4Ymr:
11143
0
  case VFMSUBPS4Yrm:
11144
0
  case VFMSUBPS4Yrr:
11145
0
  case VFMSUBPS4Yrr_REV:
11146
0
  case VFMSUBPS4mr:
11147
0
  case VFMSUBPS4rm:
11148
0
  case VFMSUBPS4rr:
11149
0
  case VFMSUBPS4rr_REV:
11150
0
    return true;
11151
0
  }
11152
0
  return false;
11153
0
}
11154
11155
0
bool isVPBLENDW(unsigned Opcode) {
11156
0
  switch (Opcode) {
11157
0
  case VPBLENDWYrmi:
11158
0
  case VPBLENDWYrri:
11159
0
  case VPBLENDWrmi:
11160
0
  case VPBLENDWrri:
11161
0
    return true;
11162
0
  }
11163
0
  return false;
11164
0
}
11165
11166
0
bool isBZHI(unsigned Opcode) {
11167
0
  switch (Opcode) {
11168
0
  case BZHI32rm:
11169
0
  case BZHI32rm_EVEX:
11170
0
  case BZHI32rr:
11171
0
  case BZHI32rr_EVEX:
11172
0
  case BZHI64rm:
11173
0
  case BZHI64rm_EVEX:
11174
0
  case BZHI64rr:
11175
0
  case BZHI64rr_EVEX:
11176
0
    return true;
11177
0
  }
11178
0
  return false;
11179
0
}
11180
11181
0
bool isVPRORVD(unsigned Opcode) {
11182
0
  switch (Opcode) {
11183
0
  case VPRORVDZ128rm:
11184
0
  case VPRORVDZ128rmb:
11185
0
  case VPRORVDZ128rmbk:
11186
0
  case VPRORVDZ128rmbkz:
11187
0
  case VPRORVDZ128rmk:
11188
0
  case VPRORVDZ128rmkz:
11189
0
  case VPRORVDZ128rr:
11190
0
  case VPRORVDZ128rrk:
11191
0
  case VPRORVDZ128rrkz:
11192
0
  case VPRORVDZ256rm:
11193
0
  case VPRORVDZ256rmb:
11194
0
  case VPRORVDZ256rmbk:
11195
0
  case VPRORVDZ256rmbkz:
11196
0
  case VPRORVDZ256rmk:
11197
0
  case VPRORVDZ256rmkz:
11198
0
  case VPRORVDZ256rr:
11199
0
  case VPRORVDZ256rrk:
11200
0
  case VPRORVDZ256rrkz:
11201
0
  case VPRORVDZrm:
11202
0
  case VPRORVDZrmb:
11203
0
  case VPRORVDZrmbk:
11204
0
  case VPRORVDZrmbkz:
11205
0
  case VPRORVDZrmk:
11206
0
  case VPRORVDZrmkz:
11207
0
  case VPRORVDZrr:
11208
0
  case VPRORVDZrrk:
11209
0
  case VPRORVDZrrkz:
11210
0
    return true;
11211
0
  }
11212
0
  return false;
11213
0
}
11214
11215
0
bool isRMPQUERY(unsigned Opcode) {
11216
0
  return Opcode == RMPQUERY;
11217
0
}
11218
11219
0
bool isVPEXPANDB(unsigned Opcode) {
11220
0
  switch (Opcode) {
11221
0
  case VPEXPANDBZ128rm:
11222
0
  case VPEXPANDBZ128rmk:
11223
0
  case VPEXPANDBZ128rmkz:
11224
0
  case VPEXPANDBZ128rr:
11225
0
  case VPEXPANDBZ128rrk:
11226
0
  case VPEXPANDBZ128rrkz:
11227
0
  case VPEXPANDBZ256rm:
11228
0
  case VPEXPANDBZ256rmk:
11229
0
  case VPEXPANDBZ256rmkz:
11230
0
  case VPEXPANDBZ256rr:
11231
0
  case VPEXPANDBZ256rrk:
11232
0
  case VPEXPANDBZ256rrkz:
11233
0
  case VPEXPANDBZrm:
11234
0
  case VPEXPANDBZrmk:
11235
0
  case VPEXPANDBZrmkz:
11236
0
  case VPEXPANDBZrr:
11237
0
  case VPEXPANDBZrrk:
11238
0
  case VPEXPANDBZrrkz:
11239
0
    return true;
11240
0
  }
11241
0
  return false;
11242
0
}
11243
11244
0
bool isVPSCATTERDQ(unsigned Opcode) {
11245
0
  switch (Opcode) {
11246
0
  case VPSCATTERDQZ128mr:
11247
0
  case VPSCATTERDQZ256mr:
11248
0
  case VPSCATTERDQZmr:
11249
0
    return true;
11250
0
  }
11251
0
  return false;
11252
0
}
11253
11254
0
bool isPSMASH(unsigned Opcode) {
11255
0
  return Opcode == PSMASH;
11256
0
}
11257
11258
0
bool isVPSHLDQ(unsigned Opcode) {
11259
0
  switch (Opcode) {
11260
0
  case VPSHLDQZ128rmbi:
11261
0
  case VPSHLDQZ128rmbik:
11262
0
  case VPSHLDQZ128rmbikz:
11263
0
  case VPSHLDQZ128rmi:
11264
0
  case VPSHLDQZ128rmik:
11265
0
  case VPSHLDQZ128rmikz:
11266
0
  case VPSHLDQZ128rri:
11267
0
  case VPSHLDQZ128rrik:
11268
0
  case VPSHLDQZ128rrikz:
11269
0
  case VPSHLDQZ256rmbi:
11270
0
  case VPSHLDQZ256rmbik:
11271
0
  case VPSHLDQZ256rmbikz:
11272
0
  case VPSHLDQZ256rmi:
11273
0
  case VPSHLDQZ256rmik:
11274
0
  case VPSHLDQZ256rmikz:
11275
0
  case VPSHLDQZ256rri:
11276
0
  case VPSHLDQZ256rrik:
11277
0
  case VPSHLDQZ256rrikz:
11278
0
  case VPSHLDQZrmbi:
11279
0
  case VPSHLDQZrmbik:
11280
0
  case VPSHLDQZrmbikz:
11281
0
  case VPSHLDQZrmi:
11282
0
  case VPSHLDQZrmik:
11283
0
  case VPSHLDQZrmikz:
11284
0
  case VPSHLDQZrri:
11285
0
  case VPSHLDQZrrik:
11286
0
  case VPSHLDQZrrikz:
11287
0
    return true;
11288
0
  }
11289
0
  return false;
11290
0
}
11291
11292
0
bool isVSCATTERPF1DPD(unsigned Opcode) {
11293
0
  return Opcode == VSCATTERPF1DPDm;
11294
0
}
11295
11296
0
bool isMONTMUL(unsigned Opcode) {
11297
0
  return Opcode == MONTMUL;
11298
0
}
11299
11300
0
bool isVCVTPH2UQQ(unsigned Opcode) {
11301
0
  switch (Opcode) {
11302
0
  case VCVTPH2UQQZ128rm:
11303
0
  case VCVTPH2UQQZ128rmb:
11304
0
  case VCVTPH2UQQZ128rmbk:
11305
0
  case VCVTPH2UQQZ128rmbkz:
11306
0
  case VCVTPH2UQQZ128rmk:
11307
0
  case VCVTPH2UQQZ128rmkz:
11308
0
  case VCVTPH2UQQZ128rr:
11309
0
  case VCVTPH2UQQZ128rrk:
11310
0
  case VCVTPH2UQQZ128rrkz:
11311
0
  case VCVTPH2UQQZ256rm:
11312
0
  case VCVTPH2UQQZ256rmb:
11313
0
  case VCVTPH2UQQZ256rmbk:
11314
0
  case VCVTPH2UQQZ256rmbkz:
11315
0
  case VCVTPH2UQQZ256rmk:
11316
0
  case VCVTPH2UQQZ256rmkz:
11317
0
  case VCVTPH2UQQZ256rr:
11318
0
  case VCVTPH2UQQZ256rrk:
11319
0
  case VCVTPH2UQQZ256rrkz:
11320
0
  case VCVTPH2UQQZrm:
11321
0
  case VCVTPH2UQQZrmb:
11322
0
  case VCVTPH2UQQZrmbk:
11323
0
  case VCVTPH2UQQZrmbkz:
11324
0
  case VCVTPH2UQQZrmk:
11325
0
  case VCVTPH2UQQZrmkz:
11326
0
  case VCVTPH2UQQZrr:
11327
0
  case VCVTPH2UQQZrrb:
11328
0
  case VCVTPH2UQQZrrbk:
11329
0
  case VCVTPH2UQQZrrbkz:
11330
0
  case VCVTPH2UQQZrrk:
11331
0
  case VCVTPH2UQQZrrkz:
11332
0
    return true;
11333
0
  }
11334
0
  return false;
11335
0
}
11336
11337
0
bool isPSLLD(unsigned Opcode) {
11338
0
  switch (Opcode) {
11339
0
  case MMX_PSLLDri:
11340
0
  case MMX_PSLLDrm:
11341
0
  case MMX_PSLLDrr:
11342
0
  case PSLLDri:
11343
0
  case PSLLDrm:
11344
0
  case PSLLDrr:
11345
0
    return true;
11346
0
  }
11347
0
  return false;
11348
0
}
11349
11350
0
bool isSAR(unsigned Opcode) {
11351
0
  switch (Opcode) {
11352
0
  case SAR16m1:
11353
0
  case SAR16mCL:
11354
0
  case SAR16mi:
11355
0
  case SAR16r1:
11356
0
  case SAR16rCL:
11357
0
  case SAR16ri:
11358
0
  case SAR32m1:
11359
0
  case SAR32mCL:
11360
0
  case SAR32mi:
11361
0
  case SAR32r1:
11362
0
  case SAR32rCL:
11363
0
  case SAR32ri:
11364
0
  case SAR64m1:
11365
0
  case SAR64mCL:
11366
0
  case SAR64mi:
11367
0
  case SAR64r1:
11368
0
  case SAR64rCL:
11369
0
  case SAR64ri:
11370
0
  case SAR8m1:
11371
0
  case SAR8mCL:
11372
0
  case SAR8mi:
11373
0
  case SAR8r1:
11374
0
  case SAR8rCL:
11375
0
  case SAR8ri:
11376
0
    return true;
11377
0
  }
11378
0
  return false;
11379
0
}
11380
11381
0
bool isLDTILECFG(unsigned Opcode) {
11382
0
  switch (Opcode) {
11383
0
  case LDTILECFG:
11384
0
  case LDTILECFG_EVEX:
11385
0
    return true;
11386
0
  }
11387
0
  return false;
11388
0
}
11389
11390
0
bool isPMINUB(unsigned Opcode) {
11391
0
  switch (Opcode) {
11392
0
  case MMX_PMINUBrm:
11393
0
  case MMX_PMINUBrr:
11394
0
  case PMINUBrm:
11395
0
  case PMINUBrr:
11396
0
    return true;
11397
0
  }
11398
0
  return false;
11399
0
}
11400
11401
0
bool isVCVTNEEBF162PS(unsigned Opcode) {
11402
0
  switch (Opcode) {
11403
0
  case VCVTNEEBF162PSYrm:
11404
0
  case VCVTNEEBF162PSrm:
11405
0
    return true;
11406
0
  }
11407
0
  return false;
11408
0
}
11409
11410
0
bool isMOVDIR64B(unsigned Opcode) {
11411
0
  switch (Opcode) {
11412
0
  case MOVDIR64B16:
11413
0
  case MOVDIR64B32:
11414
0
  case MOVDIR64B32_EVEX:
11415
0
  case MOVDIR64B64:
11416
0
  case MOVDIR64B64_EVEX:
11417
0
    return true;
11418
0
  }
11419
0
  return false;
11420
0
}
11421
11422
0
bool isSTR(unsigned Opcode) {
11423
0
  switch (Opcode) {
11424
0
  case STR16r:
11425
0
  case STR32r:
11426
0
  case STR64r:
11427
0
  case STRm:
11428
0
    return true;
11429
0
  }
11430
0
  return false;
11431
0
}
11432
11433
0
bool isKANDNQ(unsigned Opcode) {
11434
0
  return Opcode == KANDNQrr;
11435
0
}
11436
11437
0
bool isBSF(unsigned Opcode) {
11438
0
  switch (Opcode) {
11439
0
  case BSF16rm:
11440
0
  case BSF16rr:
11441
0
  case BSF32rm:
11442
0
  case BSF32rr:
11443
0
  case BSF64rm:
11444
0
  case BSF64rr:
11445
0
    return true;
11446
0
  }
11447
0
  return false;
11448
0
}
11449
11450
0
bool isVPDPBUUDS(unsigned Opcode) {
11451
0
  switch (Opcode) {
11452
0
  case VPDPBUUDSYrm:
11453
0
  case VPDPBUUDSYrr:
11454
0
  case VPDPBUUDSrm:
11455
0
  case VPDPBUUDSrr:
11456
0
    return true;
11457
0
  }
11458
0
  return false;
11459
0
}
11460
11461
0
bool isINCSSPD(unsigned Opcode) {
11462
0
  return Opcode == INCSSPD;
11463
0
}
11464
11465
0
bool isSQRTPS(unsigned Opcode) {
11466
0
  switch (Opcode) {
11467
0
  case SQRTPSm:
11468
0
  case SQRTPSr:
11469
0
    return true;
11470
0
  }
11471
0
  return false;
11472
0
}
11473
11474
0
bool isCMPXCHG(unsigned Opcode) {
11475
0
  switch (Opcode) {
11476
0
  case CMPXCHG16rm:
11477
0
  case CMPXCHG16rr:
11478
0
  case CMPXCHG32rm:
11479
0
  case CMPXCHG32rr:
11480
0
  case CMPXCHG64rm:
11481
0
  case CMPXCHG64rr:
11482
0
  case CMPXCHG8rm:
11483
0
  case CMPXCHG8rr:
11484
0
    return true;
11485
0
  }
11486
0
  return false;
11487
0
}
11488
11489
0
bool isVPSIGNW(unsigned Opcode) {
11490
0
  switch (Opcode) {
11491
0
  case VPSIGNWYrm:
11492
0
  case VPSIGNWYrr:
11493
0
  case VPSIGNWrm:
11494
0
  case VPSIGNWrr:
11495
0
    return true;
11496
0
  }
11497
0
  return false;
11498
0
}
11499
11500
0
bool isLES(unsigned Opcode) {
11501
0
  switch (Opcode) {
11502
0
  case LES16rm:
11503
0
  case LES32rm:
11504
0
    return true;
11505
0
  }
11506
0
  return false;
11507
0
}
11508
11509
0
bool isCVTSS2SI(unsigned Opcode) {
11510
0
  switch (Opcode) {
11511
0
  case CVTSS2SI64rm_Int:
11512
0
  case CVTSS2SI64rr_Int:
11513
0
  case CVTSS2SIrm_Int:
11514
0
  case CVTSS2SIrr_Int:
11515
0
    return true;
11516
0
  }
11517
0
  return false;
11518
0
}
11519
11520
0
bool isVPMOVUSWB(unsigned Opcode) {
11521
0
  switch (Opcode) {
11522
0
  case VPMOVUSWBZ128mr:
11523
0
  case VPMOVUSWBZ128mrk:
11524
0
  case VPMOVUSWBZ128rr:
11525
0
  case VPMOVUSWBZ128rrk:
11526
0
  case VPMOVUSWBZ128rrkz:
11527
0
  case VPMOVUSWBZ256mr:
11528
0
  case VPMOVUSWBZ256mrk:
11529
0
  case VPMOVUSWBZ256rr:
11530
0
  case VPMOVUSWBZ256rrk:
11531
0
  case VPMOVUSWBZ256rrkz:
11532
0
  case VPMOVUSWBZmr:
11533
0
  case VPMOVUSWBZmrk:
11534
0
  case VPMOVUSWBZrr:
11535
0
  case VPMOVUSWBZrrk:
11536
0
  case VPMOVUSWBZrrkz:
11537
0
    return true;
11538
0
  }
11539
0
  return false;
11540
0
}
11541
11542
0
bool isFCOMPI(unsigned Opcode) {
11543
0
  return Opcode == COM_FIPr;
11544
0
}
11545
11546
0
bool isPUNPCKHWD(unsigned Opcode) {
11547
0
  switch (Opcode) {
11548
0
  case MMX_PUNPCKHWDrm:
11549
0
  case MMX_PUNPCKHWDrr:
11550
0
  case PUNPCKHWDrm:
11551
0
  case PUNPCKHWDrr:
11552
0
    return true;
11553
0
  }
11554
0
  return false;
11555
0
}
11556
11557
0
bool isPFACC(unsigned Opcode) {
11558
0
  switch (Opcode) {
11559
0
  case PFACCrm:
11560
0
  case PFACCrr:
11561
0
    return true;
11562
0
  }
11563
0
  return false;
11564
0
}
11565
11566
0
bool isVPTESTNMW(unsigned Opcode) {
11567
0
  switch (Opcode) {
11568
0
  case VPTESTNMWZ128rm:
11569
0
  case VPTESTNMWZ128rmk:
11570
0
  case VPTESTNMWZ128rr:
11571
0
  case VPTESTNMWZ128rrk:
11572
0
  case VPTESTNMWZ256rm:
11573
0
  case VPTESTNMWZ256rmk:
11574
0
  case VPTESTNMWZ256rr:
11575
0
  case VPTESTNMWZ256rrk:
11576
0
  case VPTESTNMWZrm:
11577
0
  case VPTESTNMWZrmk:
11578
0
  case VPTESTNMWZrr:
11579
0
  case VPTESTNMWZrrk:
11580
0
    return true;
11581
0
  }
11582
0
  return false;
11583
0
}
11584
11585
0
bool isVPMULDQ(unsigned Opcode) {
11586
0
  switch (Opcode) {
11587
0
  case VPMULDQYrm:
11588
0
  case VPMULDQYrr:
11589
0
  case VPMULDQZ128rm:
11590
0
  case VPMULDQZ128rmb:
11591
0
  case VPMULDQZ128rmbk:
11592
0
  case VPMULDQZ128rmbkz:
11593
0
  case VPMULDQZ128rmk:
11594
0
  case VPMULDQZ128rmkz:
11595
0
  case VPMULDQZ128rr:
11596
0
  case VPMULDQZ128rrk:
11597
0
  case VPMULDQZ128rrkz:
11598
0
  case VPMULDQZ256rm:
11599
0
  case VPMULDQZ256rmb:
11600
0
  case VPMULDQZ256rmbk:
11601
0
  case VPMULDQZ256rmbkz:
11602
0
  case VPMULDQZ256rmk:
11603
0
  case VPMULDQZ256rmkz:
11604
0
  case VPMULDQZ256rr:
11605
0
  case VPMULDQZ256rrk:
11606
0
  case VPMULDQZ256rrkz:
11607
0
  case VPMULDQZrm:
11608
0
  case VPMULDQZrmb:
11609
0
  case VPMULDQZrmbk:
11610
0
  case VPMULDQZrmbkz:
11611
0
  case VPMULDQZrmk:
11612
0
  case VPMULDQZrmkz:
11613
0
  case VPMULDQZrr:
11614
0
  case VPMULDQZrrk:
11615
0
  case VPMULDQZrrkz:
11616
0
  case VPMULDQrm:
11617
0
  case VPMULDQrr:
11618
0
    return true;
11619
0
  }
11620
0
  return false;
11621
0
}
11622
11623
0
bool isSHRX(unsigned Opcode) {
11624
0
  switch (Opcode) {
11625
0
  case SHRX32rm:
11626
0
  case SHRX32rm_EVEX:
11627
0
  case SHRX32rr:
11628
0
  case SHRX32rr_EVEX:
11629
0
  case SHRX64rm:
11630
0
  case SHRX64rm_EVEX:
11631
0
  case SHRX64rr:
11632
0
  case SHRX64rr_EVEX:
11633
0
    return true;
11634
0
  }
11635
0
  return false;
11636
0
}
11637
11638
0
bool isKXORQ(unsigned Opcode) {
11639
0
  return Opcode == KXORQrr;
11640
0
}
11641
11642
0
bool isVGETEXPSD(unsigned Opcode) {
11643
0
  switch (Opcode) {
11644
0
  case VGETEXPSDZm:
11645
0
  case VGETEXPSDZmk:
11646
0
  case VGETEXPSDZmkz:
11647
0
  case VGETEXPSDZr:
11648
0
  case VGETEXPSDZrb:
11649
0
  case VGETEXPSDZrbk:
11650
0
  case VGETEXPSDZrbkz:
11651
0
  case VGETEXPSDZrk:
11652
0
  case VGETEXPSDZrkz:
11653
0
    return true;
11654
0
  }
11655
0
  return false;
11656
0
}
11657
11658
0
bool isV4FNMADDPS(unsigned Opcode) {
11659
0
  switch (Opcode) {
11660
0
  case V4FNMADDPSrm:
11661
0
  case V4FNMADDPSrmk:
11662
0
  case V4FNMADDPSrmkz:
11663
0
    return true;
11664
0
  }
11665
0
  return false;
11666
0
}
11667
11668
0
bool isVFNMSUB231SD(unsigned Opcode) {
11669
0
  switch (Opcode) {
11670
0
  case VFNMSUB231SDZm_Int:
11671
0
  case VFNMSUB231SDZm_Intk:
11672
0
  case VFNMSUB231SDZm_Intkz:
11673
0
  case VFNMSUB231SDZr_Int:
11674
0
  case VFNMSUB231SDZr_Intk:
11675
0
  case VFNMSUB231SDZr_Intkz:
11676
0
  case VFNMSUB231SDZrb_Int:
11677
0
  case VFNMSUB231SDZrb_Intk:
11678
0
  case VFNMSUB231SDZrb_Intkz:
11679
0
  case VFNMSUB231SDm_Int:
11680
0
  case VFNMSUB231SDr_Int:
11681
0
    return true;
11682
0
  }
11683
0
  return false;
11684
0
}
11685
11686
0
bool isVPSHLD(unsigned Opcode) {
11687
0
  switch (Opcode) {
11688
0
  case VPSHLDmr:
11689
0
  case VPSHLDrm:
11690
0
  case VPSHLDrr:
11691
0
  case VPSHLDrr_REV:
11692
0
    return true;
11693
0
  }
11694
0
  return false;
11695
0
}
11696
11697
0
bool isPAVGB(unsigned Opcode) {
11698
0
  switch (Opcode) {
11699
0
  case MMX_PAVGBrm:
11700
0
  case MMX_PAVGBrr:
11701
0
  case PAVGBrm:
11702
0
  case PAVGBrr:
11703
0
    return true;
11704
0
  }
11705
0
  return false;
11706
0
}
11707
11708
0
bool isPMOVZXBD(unsigned Opcode) {
11709
0
  switch (Opcode) {
11710
0
  case PMOVZXBDrm:
11711
0
  case PMOVZXBDrr:
11712
0
    return true;
11713
0
  }
11714
0
  return false;
11715
0
}
11716
11717
0
bool isKORTESTW(unsigned Opcode) {
11718
0
  return Opcode == KORTESTWrr;
11719
0
}
11720
11721
0
bool isVSHUFPS(unsigned Opcode) {
11722
0
  switch (Opcode) {
11723
0
  case VSHUFPSYrmi:
11724
0
  case VSHUFPSYrri:
11725
0
  case VSHUFPSZ128rmbi:
11726
0
  case VSHUFPSZ128rmbik:
11727
0
  case VSHUFPSZ128rmbikz:
11728
0
  case VSHUFPSZ128rmi:
11729
0
  case VSHUFPSZ128rmik:
11730
0
  case VSHUFPSZ128rmikz:
11731
0
  case VSHUFPSZ128rri:
11732
0
  case VSHUFPSZ128rrik:
11733
0
  case VSHUFPSZ128rrikz:
11734
0
  case VSHUFPSZ256rmbi:
11735
0
  case VSHUFPSZ256rmbik:
11736
0
  case VSHUFPSZ256rmbikz:
11737
0
  case VSHUFPSZ256rmi:
11738
0
  case VSHUFPSZ256rmik:
11739
0
  case VSHUFPSZ256rmikz:
11740
0
  case VSHUFPSZ256rri:
11741
0
  case VSHUFPSZ256rrik:
11742
0
  case VSHUFPSZ256rrikz:
11743
0
  case VSHUFPSZrmbi:
11744
0
  case VSHUFPSZrmbik:
11745
0
  case VSHUFPSZrmbikz:
11746
0
  case VSHUFPSZrmi:
11747
0
  case VSHUFPSZrmik:
11748
0
  case VSHUFPSZrmikz:
11749
0
  case VSHUFPSZrri:
11750
0
  case VSHUFPSZrrik:
11751
0
  case VSHUFPSZrrikz:
11752
0
  case VSHUFPSrmi:
11753
0
  case VSHUFPSrri:
11754
0
    return true;
11755
0
  }
11756
0
  return false;
11757
0
}
11758
11759
0
bool isAESENCWIDE128KL(unsigned Opcode) {
11760
0
  return Opcode == AESENCWIDE128KL;
11761
0
}
11762
11763
0
bool isVPXORD(unsigned Opcode) {
11764
0
  switch (Opcode) {
11765
0
  case VPXORDZ128rm:
11766
0
  case VPXORDZ128rmb:
11767
0
  case VPXORDZ128rmbk:
11768
0
  case VPXORDZ128rmbkz:
11769
0
  case VPXORDZ128rmk:
11770
0
  case VPXORDZ128rmkz:
11771
0
  case VPXORDZ128rr:
11772
0
  case VPXORDZ128rrk:
11773
0
  case VPXORDZ128rrkz:
11774
0
  case VPXORDZ256rm:
11775
0
  case VPXORDZ256rmb:
11776
0
  case VPXORDZ256rmbk:
11777
0
  case VPXORDZ256rmbkz:
11778
0
  case VPXORDZ256rmk:
11779
0
  case VPXORDZ256rmkz:
11780
0
  case VPXORDZ256rr:
11781
0
  case VPXORDZ256rrk:
11782
0
  case VPXORDZ256rrkz:
11783
0
  case VPXORDZrm:
11784
0
  case VPXORDZrmb:
11785
0
  case VPXORDZrmbk:
11786
0
  case VPXORDZrmbkz:
11787
0
  case VPXORDZrmk:
11788
0
  case VPXORDZrmkz:
11789
0
  case VPXORDZrr:
11790
0
  case VPXORDZrrk:
11791
0
  case VPXORDZrrkz:
11792
0
    return true;
11793
0
  }
11794
0
  return false;
11795
0
}
11796
11797
0
bool isVPSHAW(unsigned Opcode) {
11798
0
  switch (Opcode) {
11799
0
  case VPSHAWmr:
11800
0
  case VPSHAWrm:
11801
0
  case VPSHAWrr:
11802
0
  case VPSHAWrr_REV:
11803
0
    return true;
11804
0
  }
11805
0
  return false;
11806
0
}
11807
11808
0
bool isVPERMT2B(unsigned Opcode) {
11809
0
  switch (Opcode) {
11810
0
  case VPERMT2BZ128rm:
11811
0
  case VPERMT2BZ128rmk:
11812
0
  case VPERMT2BZ128rmkz:
11813
0
  case VPERMT2BZ128rr:
11814
0
  case VPERMT2BZ128rrk:
11815
0
  case VPERMT2BZ128rrkz:
11816
0
  case VPERMT2BZ256rm:
11817
0
  case VPERMT2BZ256rmk:
11818
0
  case VPERMT2BZ256rmkz:
11819
0
  case VPERMT2BZ256rr:
11820
0
  case VPERMT2BZ256rrk:
11821
0
  case VPERMT2BZ256rrkz:
11822
0
  case VPERMT2BZrm:
11823
0
  case VPERMT2BZrmk:
11824
0
  case VPERMT2BZrmkz:
11825
0
  case VPERMT2BZrr:
11826
0
  case VPERMT2BZrrk:
11827
0
  case VPERMT2BZrrkz:
11828
0
    return true;
11829
0
  }
11830
0
  return false;
11831
0
}
11832
11833
0
bool isVFMADD213PD(unsigned Opcode) {
11834
0
  switch (Opcode) {
11835
0
  case VFMADD213PDYm:
11836
0
  case VFMADD213PDYr:
11837
0
  case VFMADD213PDZ128m:
11838
0
  case VFMADD213PDZ128mb:
11839
0
  case VFMADD213PDZ128mbk:
11840
0
  case VFMADD213PDZ128mbkz:
11841
0
  case VFMADD213PDZ128mk:
11842
0
  case VFMADD213PDZ128mkz:
11843
0
  case VFMADD213PDZ128r:
11844
0
  case VFMADD213PDZ128rk:
11845
0
  case VFMADD213PDZ128rkz:
11846
0
  case VFMADD213PDZ256m:
11847
0
  case VFMADD213PDZ256mb:
11848
0
  case VFMADD213PDZ256mbk:
11849
0
  case VFMADD213PDZ256mbkz:
11850
0
  case VFMADD213PDZ256mk:
11851
0
  case VFMADD213PDZ256mkz:
11852
0
  case VFMADD213PDZ256r:
11853
0
  case VFMADD213PDZ256rk:
11854
0
  case VFMADD213PDZ256rkz:
11855
0
  case VFMADD213PDZm:
11856
0
  case VFMADD213PDZmb:
11857
0
  case VFMADD213PDZmbk:
11858
0
  case VFMADD213PDZmbkz:
11859
0
  case VFMADD213PDZmk:
11860
0
  case VFMADD213PDZmkz:
11861
0
  case VFMADD213PDZr:
11862
0
  case VFMADD213PDZrb:
11863
0
  case VFMADD213PDZrbk:
11864
0
  case VFMADD213PDZrbkz:
11865
0
  case VFMADD213PDZrk:
11866
0
  case VFMADD213PDZrkz:
11867
0
  case VFMADD213PDm:
11868
0
  case VFMADD213PDr:
11869
0
    return true;
11870
0
  }
11871
0
  return false;
11872
0
}
11873
11874
0
bool isVPGATHERQD(unsigned Opcode) {
11875
0
  switch (Opcode) {
11876
0
  case VPGATHERQDYrm:
11877
0
  case VPGATHERQDZ128rm:
11878
0
  case VPGATHERQDZ256rm:
11879
0
  case VPGATHERQDZrm:
11880
0
  case VPGATHERQDrm:
11881
0
    return true;
11882
0
  }
11883
0
  return false;
11884
0
}
11885
11886
0
bool isVPCMPGTW(unsigned Opcode) {
11887
0
  switch (Opcode) {
11888
0
  case VPCMPGTWYrm:
11889
0
  case VPCMPGTWYrr:
11890
0
  case VPCMPGTWZ128rm:
11891
0
  case VPCMPGTWZ128rmk:
11892
0
  case VPCMPGTWZ128rr:
11893
0
  case VPCMPGTWZ128rrk:
11894
0
  case VPCMPGTWZ256rm:
11895
0
  case VPCMPGTWZ256rmk:
11896
0
  case VPCMPGTWZ256rr:
11897
0
  case VPCMPGTWZ256rrk:
11898
0
  case VPCMPGTWZrm:
11899
0
  case VPCMPGTWZrmk:
11900
0
  case VPCMPGTWZrr:
11901
0
  case VPCMPGTWZrrk:
11902
0
  case VPCMPGTWrm:
11903
0
  case VPCMPGTWrr:
11904
0
    return true;
11905
0
  }
11906
0
  return false;
11907
0
}
11908
11909
0
bool isVGETMANTSH(unsigned Opcode) {
11910
0
  switch (Opcode) {
11911
0
  case VGETMANTSHZrmi:
11912
0
  case VGETMANTSHZrmik:
11913
0
  case VGETMANTSHZrmikz:
11914
0
  case VGETMANTSHZrri:
11915
0
  case VGETMANTSHZrrib:
11916
0
  case VGETMANTSHZrribk:
11917
0
  case VGETMANTSHZrribkz:
11918
0
  case VGETMANTSHZrrik:
11919
0
  case VGETMANTSHZrrikz:
11920
0
    return true;
11921
0
  }
11922
0
  return false;
11923
0
}
11924
11925
0
bool isVANDPS(unsigned Opcode) {
11926
0
  switch (Opcode) {
11927
0
  case VANDPSYrm:
11928
0
  case VANDPSYrr:
11929
0
  case VANDPSZ128rm:
11930
0
  case VANDPSZ128rmb:
11931
0
  case VANDPSZ128rmbk:
11932
0
  case VANDPSZ128rmbkz:
11933
0
  case VANDPSZ128rmk:
11934
0
  case VANDPSZ128rmkz:
11935
0
  case VANDPSZ128rr:
11936
0
  case VANDPSZ128rrk:
11937
0
  case VANDPSZ128rrkz:
11938
0
  case VANDPSZ256rm:
11939
0
  case VANDPSZ256rmb:
11940
0
  case VANDPSZ256rmbk:
11941
0
  case VANDPSZ256rmbkz:
11942
0
  case VANDPSZ256rmk:
11943
0
  case VANDPSZ256rmkz:
11944
0
  case VANDPSZ256rr:
11945
0
  case VANDPSZ256rrk:
11946
0
  case VANDPSZ256rrkz:
11947
0
  case VANDPSZrm:
11948
0
  case VANDPSZrmb:
11949
0
  case VANDPSZrmbk:
11950
0
  case VANDPSZrmbkz:
11951
0
  case VANDPSZrmk:
11952
0
  case VANDPSZrmkz:
11953
0
  case VANDPSZrr:
11954
0
  case VANDPSZrrk:
11955
0
  case VANDPSZrrkz:
11956
0
  case VANDPSrm:
11957
0
  case VANDPSrr:
11958
0
    return true;
11959
0
  }
11960
0
  return false;
11961
0
}
11962
11963
0
bool isVDIVPS(unsigned Opcode) {
11964
0
  switch (Opcode) {
11965
0
  case VDIVPSYrm:
11966
0
  case VDIVPSYrr:
11967
0
  case VDIVPSZ128rm:
11968
0
  case VDIVPSZ128rmb:
11969
0
  case VDIVPSZ128rmbk:
11970
0
  case VDIVPSZ128rmbkz:
11971
0
  case VDIVPSZ128rmk:
11972
0
  case VDIVPSZ128rmkz:
11973
0
  case VDIVPSZ128rr:
11974
0
  case VDIVPSZ128rrk:
11975
0
  case VDIVPSZ128rrkz:
11976
0
  case VDIVPSZ256rm:
11977
0
  case VDIVPSZ256rmb:
11978
0
  case VDIVPSZ256rmbk:
11979
0
  case VDIVPSZ256rmbkz:
11980
0
  case VDIVPSZ256rmk:
11981
0
  case VDIVPSZ256rmkz:
11982
0
  case VDIVPSZ256rr:
11983
0
  case VDIVPSZ256rrk:
11984
0
  case VDIVPSZ256rrkz:
11985
0
  case VDIVPSZrm:
11986
0
  case VDIVPSZrmb:
11987
0
  case VDIVPSZrmbk:
11988
0
  case VDIVPSZrmbkz:
11989
0
  case VDIVPSZrmk:
11990
0
  case VDIVPSZrmkz:
11991
0
  case VDIVPSZrr:
11992
0
  case VDIVPSZrrb:
11993
0
  case VDIVPSZrrbk:
11994
0
  case VDIVPSZrrbkz:
11995
0
  case VDIVPSZrrk:
11996
0
  case VDIVPSZrrkz:
11997
0
  case VDIVPSrm:
11998
0
  case VDIVPSrr:
11999
0
    return true;
12000
0
  }
12001
0
  return false;
12002
0
}
12003
12004
0
bool isVANDNPS(unsigned Opcode) {
12005
0
  switch (Opcode) {
12006
0
  case VANDNPSYrm:
12007
0
  case VANDNPSYrr:
12008
0
  case VANDNPSZ128rm:
12009
0
  case VANDNPSZ128rmb:
12010
0
  case VANDNPSZ128rmbk:
12011
0
  case VANDNPSZ128rmbkz:
12012
0
  case VANDNPSZ128rmk:
12013
0
  case VANDNPSZ128rmkz:
12014
0
  case VANDNPSZ128rr:
12015
0
  case VANDNPSZ128rrk:
12016
0
  case VANDNPSZ128rrkz:
12017
0
  case VANDNPSZ256rm:
12018
0
  case VANDNPSZ256rmb:
12019
0
  case VANDNPSZ256rmbk:
12020
0
  case VANDNPSZ256rmbkz:
12021
0
  case VANDNPSZ256rmk:
12022
0
  case VANDNPSZ256rmkz:
12023
0
  case VANDNPSZ256rr:
12024
0
  case VANDNPSZ256rrk:
12025
0
  case VANDNPSZ256rrkz:
12026
0
  case VANDNPSZrm:
12027
0
  case VANDNPSZrmb:
12028
0
  case VANDNPSZrmbk:
12029
0
  case VANDNPSZrmbkz:
12030
0
  case VANDNPSZrmk:
12031
0
  case VANDNPSZrmkz:
12032
0
  case VANDNPSZrr:
12033
0
  case VANDNPSZrrk:
12034
0
  case VANDNPSZrrkz:
12035
0
  case VANDNPSrm:
12036
0
  case VANDNPSrr:
12037
0
    return true;
12038
0
  }
12039
0
  return false;
12040
0
}
12041
12042
0
bool isVPBROADCASTW(unsigned Opcode) {
12043
0
  switch (Opcode) {
12044
0
  case VPBROADCASTWYrm:
12045
0
  case VPBROADCASTWYrr:
12046
0
  case VPBROADCASTWZ128rm:
12047
0
  case VPBROADCASTWZ128rmk:
12048
0
  case VPBROADCASTWZ128rmkz:
12049
0
  case VPBROADCASTWZ128rr:
12050
0
  case VPBROADCASTWZ128rrk:
12051
0
  case VPBROADCASTWZ128rrkz:
12052
0
  case VPBROADCASTWZ256rm:
12053
0
  case VPBROADCASTWZ256rmk:
12054
0
  case VPBROADCASTWZ256rmkz:
12055
0
  case VPBROADCASTWZ256rr:
12056
0
  case VPBROADCASTWZ256rrk:
12057
0
  case VPBROADCASTWZ256rrkz:
12058
0
  case VPBROADCASTWZrm:
12059
0
  case VPBROADCASTWZrmk:
12060
0
  case VPBROADCASTWZrmkz:
12061
0
  case VPBROADCASTWZrr:
12062
0
  case VPBROADCASTWZrrk:
12063
0
  case VPBROADCASTWZrrkz:
12064
0
  case VPBROADCASTWrZ128rr:
12065
0
  case VPBROADCASTWrZ128rrk:
12066
0
  case VPBROADCASTWrZ128rrkz:
12067
0
  case VPBROADCASTWrZ256rr:
12068
0
  case VPBROADCASTWrZ256rrk:
12069
0
  case VPBROADCASTWrZ256rrkz:
12070
0
  case VPBROADCASTWrZrr:
12071
0
  case VPBROADCASTWrZrrk:
12072
0
  case VPBROADCASTWrZrrkz:
12073
0
  case VPBROADCASTWrm:
12074
0
  case VPBROADCASTWrr:
12075
0
    return true;
12076
0
  }
12077
0
  return false;
12078
0
}
12079
12080
0
bool isFLDL2T(unsigned Opcode) {
12081
0
  return Opcode == FLDL2T;
12082
0
}
12083
12084
0
bool isVPERMB(unsigned Opcode) {
12085
0
  switch (Opcode) {
12086
0
  case VPERMBZ128rm:
12087
0
  case VPERMBZ128rmk:
12088
0
  case VPERMBZ128rmkz:
12089
0
  case VPERMBZ128rr:
12090
0
  case VPERMBZ128rrk:
12091
0
  case VPERMBZ128rrkz:
12092
0
  case VPERMBZ256rm:
12093
0
  case VPERMBZ256rmk:
12094
0
  case VPERMBZ256rmkz:
12095
0
  case VPERMBZ256rr:
12096
0
  case VPERMBZ256rrk:
12097
0
  case VPERMBZ256rrkz:
12098
0
  case VPERMBZrm:
12099
0
  case VPERMBZrmk:
12100
0
  case VPERMBZrmkz:
12101
0
  case VPERMBZrr:
12102
0
  case VPERMBZrrk:
12103
0
  case VPERMBZrrkz:
12104
0
    return true;
12105
0
  }
12106
0
  return false;
12107
0
}
12108
12109
0
bool isFCMOVNBE(unsigned Opcode) {
12110
0
  return Opcode == CMOVNBE_F;
12111
0
}
12112
12113
0
bool isVCVTTPH2W(unsigned Opcode) {
12114
0
  switch (Opcode) {
12115
0
  case VCVTTPH2WZ128rm:
12116
0
  case VCVTTPH2WZ128rmb:
12117
0
  case VCVTTPH2WZ128rmbk:
12118
0
  case VCVTTPH2WZ128rmbkz:
12119
0
  case VCVTTPH2WZ128rmk:
12120
0
  case VCVTTPH2WZ128rmkz:
12121
0
  case VCVTTPH2WZ128rr:
12122
0
  case VCVTTPH2WZ128rrk:
12123
0
  case VCVTTPH2WZ128rrkz:
12124
0
  case VCVTTPH2WZ256rm:
12125
0
  case VCVTTPH2WZ256rmb:
12126
0
  case VCVTTPH2WZ256rmbk:
12127
0
  case VCVTTPH2WZ256rmbkz:
12128
0
  case VCVTTPH2WZ256rmk:
12129
0
  case VCVTTPH2WZ256rmkz:
12130
0
  case VCVTTPH2WZ256rr:
12131
0
  case VCVTTPH2WZ256rrk:
12132
0
  case VCVTTPH2WZ256rrkz:
12133
0
  case VCVTTPH2WZrm:
12134
0
  case VCVTTPH2WZrmb:
12135
0
  case VCVTTPH2WZrmbk:
12136
0
  case VCVTTPH2WZrmbkz:
12137
0
  case VCVTTPH2WZrmk:
12138
0
  case VCVTTPH2WZrmkz:
12139
0
  case VCVTTPH2WZrr:
12140
0
  case VCVTTPH2WZrrb:
12141
0
  case VCVTTPH2WZrrbk:
12142
0
  case VCVTTPH2WZrrbkz:
12143
0
  case VCVTTPH2WZrrk:
12144
0
  case VCVTTPH2WZrrkz:
12145
0
    return true;
12146
0
  }
12147
0
  return false;
12148
0
}
12149
12150
0
bool isPMOVZXBQ(unsigned Opcode) {
12151
0
  switch (Opcode) {
12152
0
  case PMOVZXBQrm:
12153
0
  case PMOVZXBQrr:
12154
0
    return true;
12155
0
  }
12156
0
  return false;
12157
0
}
12158
12159
0
bool isPF2ID(unsigned Opcode) {
12160
0
  switch (Opcode) {
12161
0
  case PF2IDrm:
12162
0
  case PF2IDrr:
12163
0
    return true;
12164
0
  }
12165
0
  return false;
12166
0
}
12167
12168
0
bool isVFNMADD132PD(unsigned Opcode) {
12169
0
  switch (Opcode) {
12170
0
  case VFNMADD132PDYm:
12171
0
  case VFNMADD132PDYr:
12172
0
  case VFNMADD132PDZ128m:
12173
0
  case VFNMADD132PDZ128mb:
12174
0
  case VFNMADD132PDZ128mbk:
12175
0
  case VFNMADD132PDZ128mbkz:
12176
0
  case VFNMADD132PDZ128mk:
12177
0
  case VFNMADD132PDZ128mkz:
12178
0
  case VFNMADD132PDZ128r:
12179
0
  case VFNMADD132PDZ128rk:
12180
0
  case VFNMADD132PDZ128rkz:
12181
0
  case VFNMADD132PDZ256m:
12182
0
  case VFNMADD132PDZ256mb:
12183
0
  case VFNMADD132PDZ256mbk:
12184
0
  case VFNMADD132PDZ256mbkz:
12185
0
  case VFNMADD132PDZ256mk:
12186
0
  case VFNMADD132PDZ256mkz:
12187
0
  case VFNMADD132PDZ256r:
12188
0
  case VFNMADD132PDZ256rk:
12189
0
  case VFNMADD132PDZ256rkz:
12190
0
  case VFNMADD132PDZm:
12191
0
  case VFNMADD132PDZmb:
12192
0
  case VFNMADD132PDZmbk:
12193
0
  case VFNMADD132PDZmbkz:
12194
0
  case VFNMADD132PDZmk:
12195
0
  case VFNMADD132PDZmkz:
12196
0
  case VFNMADD132PDZr:
12197
0
  case VFNMADD132PDZrb:
12198
0
  case VFNMADD132PDZrbk:
12199
0
  case VFNMADD132PDZrbkz:
12200
0
  case VFNMADD132PDZrk:
12201
0
  case VFNMADD132PDZrkz:
12202
0
  case VFNMADD132PDm:
12203
0
  case VFNMADD132PDr:
12204
0
    return true;
12205
0
  }
12206
0
  return false;
12207
0
}
12208
12209
0
bool isPMULHRSW(unsigned Opcode) {
12210
0
  switch (Opcode) {
12211
0
  case MMX_PMULHRSWrm:
12212
0
  case MMX_PMULHRSWrr:
12213
0
  case PMULHRSWrm:
12214
0
  case PMULHRSWrr:
12215
0
    return true;
12216
0
  }
12217
0
  return false;
12218
0
}
12219
12220
0
bool isKADDD(unsigned Opcode) {
12221
0
  return Opcode == KADDDrr;
12222
0
}
12223
12224
0
bool isVFNMSUB132SH(unsigned Opcode) {
12225
0
  switch (Opcode) {
12226
0
  case VFNMSUB132SHZm_Int:
12227
0
  case VFNMSUB132SHZm_Intk:
12228
0
  case VFNMSUB132SHZm_Intkz:
12229
0
  case VFNMSUB132SHZr_Int:
12230
0
  case VFNMSUB132SHZr_Intk:
12231
0
  case VFNMSUB132SHZr_Intkz:
12232
0
  case VFNMSUB132SHZrb_Int:
12233
0
  case VFNMSUB132SHZrb_Intk:
12234
0
  case VFNMSUB132SHZrb_Intkz:
12235
0
    return true;
12236
0
  }
12237
0
  return false;
12238
0
}
12239
12240
0
bool isUIRET(unsigned Opcode) {
12241
0
  return Opcode == UIRET;
12242
0
}
12243
12244
0
bool isBSR(unsigned Opcode) {
12245
0
  switch (Opcode) {
12246
0
  case BSR16rm:
12247
0
  case BSR16rr:
12248
0
  case BSR32rm:
12249
0
  case BSR32rr:
12250
0
  case BSR64rm:
12251
0
  case BSR64rr:
12252
0
    return true;
12253
0
  }
12254
0
  return false;
12255
0
}
12256
12257
0
bool isPCMPEQQ(unsigned Opcode) {
12258
0
  switch (Opcode) {
12259
0
  case PCMPEQQrm:
12260
0
  case PCMPEQQrr:
12261
0
    return true;
12262
0
  }
12263
0
  return false;
12264
0
}
12265
12266
0
bool isCDQ(unsigned Opcode) {
12267
0
  return Opcode == CDQ;
12268
0
}
12269
12270
0
bool isPMAXSW(unsigned Opcode) {
12271
0
  switch (Opcode) {
12272
0
  case MMX_PMAXSWrm:
12273
0
  case MMX_PMAXSWrr:
12274
0
  case PMAXSWrm:
12275
0
  case PMAXSWrr:
12276
0
    return true;
12277
0
  }
12278
0
  return false;
12279
0
}
12280
12281
0
bool isSIDTD(unsigned Opcode) {
12282
0
  return Opcode == SIDT32m;
12283
0
}
12284
12285
0
bool isVCVTPS2PHX(unsigned Opcode) {
12286
0
  switch (Opcode) {
12287
0
  case VCVTPS2PHXZ128rm:
12288
0
  case VCVTPS2PHXZ128rmb:
12289
0
  case VCVTPS2PHXZ128rmbk:
12290
0
  case VCVTPS2PHXZ128rmbkz:
12291
0
  case VCVTPS2PHXZ128rmk:
12292
0
  case VCVTPS2PHXZ128rmkz:
12293
0
  case VCVTPS2PHXZ128rr:
12294
0
  case VCVTPS2PHXZ128rrk:
12295
0
  case VCVTPS2PHXZ128rrkz:
12296
0
  case VCVTPS2PHXZ256rm:
12297
0
  case VCVTPS2PHXZ256rmb:
12298
0
  case VCVTPS2PHXZ256rmbk:
12299
0
  case VCVTPS2PHXZ256rmbkz:
12300
0
  case VCVTPS2PHXZ256rmk:
12301
0
  case VCVTPS2PHXZ256rmkz:
12302
0
  case VCVTPS2PHXZ256rr:
12303
0
  case VCVTPS2PHXZ256rrk:
12304
0
  case VCVTPS2PHXZ256rrkz:
12305
0
  case VCVTPS2PHXZrm:
12306
0
  case VCVTPS2PHXZrmb:
12307
0
  case VCVTPS2PHXZrmbk:
12308
0
  case VCVTPS2PHXZrmbkz:
12309
0
  case VCVTPS2PHXZrmk:
12310
0
  case VCVTPS2PHXZrmkz:
12311
0
  case VCVTPS2PHXZrr:
12312
0
  case VCVTPS2PHXZrrb:
12313
0
  case VCVTPS2PHXZrrbk:
12314
0
  case VCVTPS2PHXZrrbkz:
12315
0
  case VCVTPS2PHXZrrk:
12316
0
  case VCVTPS2PHXZrrkz:
12317
0
    return true;
12318
0
  }
12319
0
  return false;
12320
0
}
12321
12322
0
bool isVPSLLVQ(unsigned Opcode) {
12323
0
  switch (Opcode) {
12324
0
  case VPSLLVQYrm:
12325
0
  case VPSLLVQYrr:
12326
0
  case VPSLLVQZ128rm:
12327
0
  case VPSLLVQZ128rmb:
12328
0
  case VPSLLVQZ128rmbk:
12329
0
  case VPSLLVQZ128rmbkz:
12330
0
  case VPSLLVQZ128rmk:
12331
0
  case VPSLLVQZ128rmkz:
12332
0
  case VPSLLVQZ128rr:
12333
0
  case VPSLLVQZ128rrk:
12334
0
  case VPSLLVQZ128rrkz:
12335
0
  case VPSLLVQZ256rm:
12336
0
  case VPSLLVQZ256rmb:
12337
0
  case VPSLLVQZ256rmbk:
12338
0
  case VPSLLVQZ256rmbkz:
12339
0
  case VPSLLVQZ256rmk:
12340
0
  case VPSLLVQZ256rmkz:
12341
0
  case VPSLLVQZ256rr:
12342
0
  case VPSLLVQZ256rrk:
12343
0
  case VPSLLVQZ256rrkz:
12344
0
  case VPSLLVQZrm:
12345
0
  case VPSLLVQZrmb:
12346
0
  case VPSLLVQZrmbk:
12347
0
  case VPSLLVQZrmbkz:
12348
0
  case VPSLLVQZrmk:
12349
0
  case VPSLLVQZrmkz:
12350
0
  case VPSLLVQZrr:
12351
0
  case VPSLLVQZrrk:
12352
0
  case VPSLLVQZrrkz:
12353
0
  case VPSLLVQrm:
12354
0
  case VPSLLVQrr:
12355
0
    return true;
12356
0
  }
12357
0
  return false;
12358
0
}
12359
12360
0
bool isMOVQ(unsigned Opcode) {
12361
0
  switch (Opcode) {
12362
0
  case MMX_MOVD64from64mr:
12363
0
  case MMX_MOVD64from64rr:
12364
0
  case MMX_MOVD64to64rm:
12365
0
  case MMX_MOVD64to64rr:
12366
0
  case MMX_MOVQ64mr:
12367
0
  case MMX_MOVQ64rm:
12368
0
  case MMX_MOVQ64rr:
12369
0
  case MMX_MOVQ64rr_REV:
12370
0
  case MOV64toPQIrm:
12371
0
  case MOV64toPQIrr:
12372
0
  case MOVPQI2QImr:
12373
0
  case MOVPQI2QIrr:
12374
0
  case MOVPQIto64mr:
12375
0
  case MOVPQIto64rr:
12376
0
  case MOVQI2PQIrm:
12377
0
  case MOVZPQILo2PQIrr:
12378
0
    return true;
12379
0
  }
12380
0
  return false;
12381
0
}
12382
12383
0
bool isPREFETCH(unsigned Opcode) {
12384
0
  return Opcode == PREFETCH;
12385
0
}
12386
12387
0
bool isCLRSSBSY(unsigned Opcode) {
12388
0
  return Opcode == CLRSSBSY;
12389
0
}
12390
12391
0
bool isPSHUFW(unsigned Opcode) {
12392
0
  switch (Opcode) {
12393
0
  case MMX_PSHUFWmi:
12394
0
  case MMX_PSHUFWri:
12395
0
    return true;
12396
0
  }
12397
0
  return false;
12398
0
}
12399
12400
0
bool isVPDPWSUDS(unsigned Opcode) {
12401
0
  switch (Opcode) {
12402
0
  case VPDPWSUDSYrm:
12403
0
  case VPDPWSUDSYrr:
12404
0
  case VPDPWSUDSrm:
12405
0
  case VPDPWSUDSrr:
12406
0
    return true;
12407
0
  }
12408
0
  return false;
12409
0
}
12410
12411
0
bool isVPMOVSXBQ(unsigned Opcode) {
12412
0
  switch (Opcode) {
12413
0
  case VPMOVSXBQYrm:
12414
0
  case VPMOVSXBQYrr:
12415
0
  case VPMOVSXBQZ128rm:
12416
0
  case VPMOVSXBQZ128rmk:
12417
0
  case VPMOVSXBQZ128rmkz:
12418
0
  case VPMOVSXBQZ128rr:
12419
0
  case VPMOVSXBQZ128rrk:
12420
0
  case VPMOVSXBQZ128rrkz:
12421
0
  case VPMOVSXBQZ256rm:
12422
0
  case VPMOVSXBQZ256rmk:
12423
0
  case VPMOVSXBQZ256rmkz:
12424
0
  case VPMOVSXBQZ256rr:
12425
0
  case VPMOVSXBQZ256rrk:
12426
0
  case VPMOVSXBQZ256rrkz:
12427
0
  case VPMOVSXBQZrm:
12428
0
  case VPMOVSXBQZrmk:
12429
0
  case VPMOVSXBQZrmkz:
12430
0
  case VPMOVSXBQZrr:
12431
0
  case VPMOVSXBQZrrk:
12432
0
  case VPMOVSXBQZrrkz:
12433
0
  case VPMOVSXBQrm:
12434
0
  case VPMOVSXBQrr:
12435
0
    return true;
12436
0
  }
12437
0
  return false;
12438
0
}
12439
12440
0
bool isFICOMP(unsigned Opcode) {
12441
0
  switch (Opcode) {
12442
0
  case FICOMP16m:
12443
0
  case FICOMP32m:
12444
0
    return true;
12445
0
  }
12446
0
  return false;
12447
0
}
12448
12449
0
bool isVLDMXCSR(unsigned Opcode) {
12450
0
  return Opcode == VLDMXCSR;
12451
0
}
12452
12453
0
bool isVPSUBUSW(unsigned Opcode) {
12454
0
  switch (Opcode) {
12455
0
  case VPSUBUSWYrm:
12456
0
  case VPSUBUSWYrr:
12457
0
  case VPSUBUSWZ128rm:
12458
0
  case VPSUBUSWZ128rmk:
12459
0
  case VPSUBUSWZ128rmkz:
12460
0
  case VPSUBUSWZ128rr:
12461
0
  case VPSUBUSWZ128rrk:
12462
0
  case VPSUBUSWZ128rrkz:
12463
0
  case VPSUBUSWZ256rm:
12464
0
  case VPSUBUSWZ256rmk:
12465
0
  case VPSUBUSWZ256rmkz:
12466
0
  case VPSUBUSWZ256rr:
12467
0
  case VPSUBUSWZ256rrk:
12468
0
  case VPSUBUSWZ256rrkz:
12469
0
  case VPSUBUSWZrm:
12470
0
  case VPSUBUSWZrmk:
12471
0
  case VPSUBUSWZrmkz:
12472
0
  case VPSUBUSWZrr:
12473
0
  case VPSUBUSWZrrk:
12474
0
  case VPSUBUSWZrrkz:
12475
0
  case VPSUBUSWrm:
12476
0
  case VPSUBUSWrr:
12477
0
    return true;
12478
0
  }
12479
0
  return false;
12480
0
}
12481
12482
0
bool isVFNMSUB132SS(unsigned Opcode) {
12483
0
  switch (Opcode) {
12484
0
  case VFNMSUB132SSZm_Int:
12485
0
  case VFNMSUB132SSZm_Intk:
12486
0
  case VFNMSUB132SSZm_Intkz:
12487
0
  case VFNMSUB132SSZr_Int:
12488
0
  case VFNMSUB132SSZr_Intk:
12489
0
  case VFNMSUB132SSZr_Intkz:
12490
0
  case VFNMSUB132SSZrb_Int:
12491
0
  case VFNMSUB132SSZrb_Intk:
12492
0
  case VFNMSUB132SSZrb_Intkz:
12493
0
  case VFNMSUB132SSm_Int:
12494
0
  case VFNMSUB132SSr_Int:
12495
0
    return true;
12496
0
  }
12497
0
  return false;
12498
0
}
12499
12500
0
bool isRETF(unsigned Opcode) {
12501
0
  switch (Opcode) {
12502
0
  case LRET16:
12503
0
  case LRET32:
12504
0
  case LRETI16:
12505
0
  case LRETI32:
12506
0
    return true;
12507
0
  }
12508
0
  return false;
12509
0
}
12510
12511
0
bool isKMOVQ(unsigned Opcode) {
12512
0
  switch (Opcode) {
12513
0
  case KMOVQkk:
12514
0
  case KMOVQkk_EVEX:
12515
0
  case KMOVQkm:
12516
0
  case KMOVQkm_EVEX:
12517
0
  case KMOVQkr:
12518
0
  case KMOVQkr_EVEX:
12519
0
  case KMOVQmk:
12520
0
  case KMOVQmk_EVEX:
12521
0
  case KMOVQrk:
12522
0
  case KMOVQrk_EVEX:
12523
0
    return true;
12524
0
  }
12525
0
  return false;
12526
0
}
12527
12528
0
bool isVPADDUSW(unsigned Opcode) {
12529
0
  switch (Opcode) {
12530
0
  case VPADDUSWYrm:
12531
0
  case VPADDUSWYrr:
12532
0
  case VPADDUSWZ128rm:
12533
0
  case VPADDUSWZ128rmk:
12534
0
  case VPADDUSWZ128rmkz:
12535
0
  case VPADDUSWZ128rr:
12536
0
  case VPADDUSWZ128rrk:
12537
0
  case VPADDUSWZ128rrkz:
12538
0
  case VPADDUSWZ256rm:
12539
0
  case VPADDUSWZ256rmk:
12540
0
  case VPADDUSWZ256rmkz:
12541
0
  case VPADDUSWZ256rr:
12542
0
  case VPADDUSWZ256rrk:
12543
0
  case VPADDUSWZ256rrkz:
12544
0
  case VPADDUSWZrm:
12545
0
  case VPADDUSWZrmk:
12546
0
  case VPADDUSWZrmkz:
12547
0
  case VPADDUSWZrr:
12548
0
  case VPADDUSWZrrk:
12549
0
  case VPADDUSWZrrkz:
12550
0
  case VPADDUSWrm:
12551
0
  case VPADDUSWrr:
12552
0
    return true;
12553
0
  }
12554
0
  return false;
12555
0
}
12556
12557
0
bool isPACKSSDW(unsigned Opcode) {
12558
0
  switch (Opcode) {
12559
0
  case MMX_PACKSSDWrm:
12560
0
  case MMX_PACKSSDWrr:
12561
0
  case PACKSSDWrm:
12562
0
  case PACKSSDWrr:
12563
0
    return true;
12564
0
  }
12565
0
  return false;
12566
0
}
12567
12568
0
bool isUMONITOR(unsigned Opcode) {
12569
0
  switch (Opcode) {
12570
0
  case UMONITOR16:
12571
0
  case UMONITOR32:
12572
0
  case UMONITOR64:
12573
0
    return true;
12574
0
  }
12575
0
  return false;
12576
0
}
12577
12578
0
bool isENQCMDS(unsigned Opcode) {
12579
0
  switch (Opcode) {
12580
0
  case ENQCMDS16:
12581
0
  case ENQCMDS32:
12582
0
  case ENQCMDS64:
12583
0
    return true;
12584
0
  }
12585
0
  return false;
12586
0
}
12587
12588
0
bool isVPMAXSQ(unsigned Opcode) {
12589
0
  switch (Opcode) {
12590
0
  case VPMAXSQZ128rm:
12591
0
  case VPMAXSQZ128rmb:
12592
0
  case VPMAXSQZ128rmbk:
12593
0
  case VPMAXSQZ128rmbkz:
12594
0
  case VPMAXSQZ128rmk:
12595
0
  case VPMAXSQZ128rmkz:
12596
0
  case VPMAXSQZ128rr:
12597
0
  case VPMAXSQZ128rrk:
12598
0
  case VPMAXSQZ128rrkz:
12599
0
  case VPMAXSQZ256rm:
12600
0
  case VPMAXSQZ256rmb:
12601
0
  case VPMAXSQZ256rmbk:
12602
0
  case VPMAXSQZ256rmbkz:
12603
0
  case VPMAXSQZ256rmk:
12604
0
  case VPMAXSQZ256rmkz:
12605
0
  case VPMAXSQZ256rr:
12606
0
  case VPMAXSQZ256rrk:
12607
0
  case VPMAXSQZ256rrkz:
12608
0
  case VPMAXSQZrm:
12609
0
  case VPMAXSQZrmb:
12610
0
  case VPMAXSQZrmbk:
12611
0
  case VPMAXSQZrmbkz:
12612
0
  case VPMAXSQZrmk:
12613
0
  case VPMAXSQZrmkz:
12614
0
  case VPMAXSQZrr:
12615
0
  case VPMAXSQZrrk:
12616
0
  case VPMAXSQZrrkz:
12617
0
    return true;
12618
0
  }
12619
0
  return false;
12620
0
}
12621
12622
0
bool isVPERMT2Q(unsigned Opcode) {
12623
0
  switch (Opcode) {
12624
0
  case VPERMT2QZ128rm:
12625
0
  case VPERMT2QZ128rmb:
12626
0
  case VPERMT2QZ128rmbk:
12627
0
  case VPERMT2QZ128rmbkz:
12628
0
  case VPERMT2QZ128rmk:
12629
0
  case VPERMT2QZ128rmkz:
12630
0
  case VPERMT2QZ128rr:
12631
0
  case VPERMT2QZ128rrk:
12632
0
  case VPERMT2QZ128rrkz:
12633
0
  case VPERMT2QZ256rm:
12634
0
  case VPERMT2QZ256rmb:
12635
0
  case VPERMT2QZ256rmbk:
12636
0
  case VPERMT2QZ256rmbkz:
12637
0
  case VPERMT2QZ256rmk:
12638
0
  case VPERMT2QZ256rmkz:
12639
0
  case VPERMT2QZ256rr:
12640
0
  case VPERMT2QZ256rrk:
12641
0
  case VPERMT2QZ256rrkz:
12642
0
  case VPERMT2QZrm:
12643
0
  case VPERMT2QZrmb:
12644
0
  case VPERMT2QZrmbk:
12645
0
  case VPERMT2QZrmbkz:
12646
0
  case VPERMT2QZrmk:
12647
0
  case VPERMT2QZrmkz:
12648
0
  case VPERMT2QZrr:
12649
0
  case VPERMT2QZrrk:
12650
0
  case VPERMT2QZrrkz:
12651
0
    return true;
12652
0
  }
12653
0
  return false;
12654
0
}
12655
12656
0
bool isFDECSTP(unsigned Opcode) {
12657
0
  return Opcode == FDECSTP;
12658
0
}
12659
12660
0
bool isVPTESTMQ(unsigned Opcode) {
12661
0
  switch (Opcode) {
12662
0
  case VPTESTMQZ128rm:
12663
0
  case VPTESTMQZ128rmb:
12664
0
  case VPTESTMQZ128rmbk:
12665
0
  case VPTESTMQZ128rmk:
12666
0
  case VPTESTMQZ128rr:
12667
0
  case VPTESTMQZ128rrk:
12668
0
  case VPTESTMQZ256rm:
12669
0
  case VPTESTMQZ256rmb:
12670
0
  case VPTESTMQZ256rmbk:
12671
0
  case VPTESTMQZ256rmk:
12672
0
  case VPTESTMQZ256rr:
12673
0
  case VPTESTMQZ256rrk:
12674
0
  case VPTESTMQZrm:
12675
0
  case VPTESTMQZrmb:
12676
0
  case VPTESTMQZrmbk:
12677
0
  case VPTESTMQZrmk:
12678
0
  case VPTESTMQZrr:
12679
0
  case VPTESTMQZrrk:
12680
0
    return true;
12681
0
  }
12682
0
  return false;
12683
0
}
12684
12685
0
bool isVRCP14PD(unsigned Opcode) {
12686
0
  switch (Opcode) {
12687
0
  case VRCP14PDZ128m:
12688
0
  case VRCP14PDZ128mb:
12689
0
  case VRCP14PDZ128mbk:
12690
0
  case VRCP14PDZ128mbkz:
12691
0
  case VRCP14PDZ128mk:
12692
0
  case VRCP14PDZ128mkz:
12693
0
  case VRCP14PDZ128r:
12694
0
  case VRCP14PDZ128rk:
12695
0
  case VRCP14PDZ128rkz:
12696
0
  case VRCP14PDZ256m:
12697
0
  case VRCP14PDZ256mb:
12698
0
  case VRCP14PDZ256mbk:
12699
0
  case VRCP14PDZ256mbkz:
12700
0
  case VRCP14PDZ256mk:
12701
0
  case VRCP14PDZ256mkz:
12702
0
  case VRCP14PDZ256r:
12703
0
  case VRCP14PDZ256rk:
12704
0
  case VRCP14PDZ256rkz:
12705
0
  case VRCP14PDZm:
12706
0
  case VRCP14PDZmb:
12707
0
  case VRCP14PDZmbk:
12708
0
  case VRCP14PDZmbkz:
12709
0
  case VRCP14PDZmk:
12710
0
  case VRCP14PDZmkz:
12711
0
  case VRCP14PDZr:
12712
0
  case VRCP14PDZrk:
12713
0
  case VRCP14PDZrkz:
12714
0
    return true;
12715
0
  }
12716
0
  return false;
12717
0
}
12718
12719
0
bool isARPL(unsigned Opcode) {
12720
0
  switch (Opcode) {
12721
0
  case ARPL16mr:
12722
0
  case ARPL16rr:
12723
0
    return true;
12724
0
  }
12725
0
  return false;
12726
0
}
12727
12728
0
bool isVFMSUB213SD(unsigned Opcode) {
12729
0
  switch (Opcode) {
12730
0
  case VFMSUB213SDZm_Int:
12731
0
  case VFMSUB213SDZm_Intk:
12732
0
  case VFMSUB213SDZm_Intkz:
12733
0
  case VFMSUB213SDZr_Int:
12734
0
  case VFMSUB213SDZr_Intk:
12735
0
  case VFMSUB213SDZr_Intkz:
12736
0
  case VFMSUB213SDZrb_Int:
12737
0
  case VFMSUB213SDZrb_Intk:
12738
0
  case VFMSUB213SDZrb_Intkz:
12739
0
  case VFMSUB213SDm_Int:
12740
0
  case VFMSUB213SDr_Int:
12741
0
    return true;
12742
0
  }
12743
0
  return false;
12744
0
}
12745
12746
0
bool isJMPABS(unsigned Opcode) {
12747
0
  return Opcode == JMPABS64i;
12748
0
}
12749
12750
0
bool isVUNPCKHPS(unsigned Opcode) {
12751
0
  switch (Opcode) {
12752
0
  case VUNPCKHPSYrm:
12753
0
  case VUNPCKHPSYrr:
12754
0
  case VUNPCKHPSZ128rm:
12755
0
  case VUNPCKHPSZ128rmb:
12756
0
  case VUNPCKHPSZ128rmbk:
12757
0
  case VUNPCKHPSZ128rmbkz:
12758
0
  case VUNPCKHPSZ128rmk:
12759
0
  case VUNPCKHPSZ128rmkz:
12760
0
  case VUNPCKHPSZ128rr:
12761
0
  case VUNPCKHPSZ128rrk:
12762
0
  case VUNPCKHPSZ128rrkz:
12763
0
  case VUNPCKHPSZ256rm:
12764
0
  case VUNPCKHPSZ256rmb:
12765
0
  case VUNPCKHPSZ256rmbk:
12766
0
  case VUNPCKHPSZ256rmbkz:
12767
0
  case VUNPCKHPSZ256rmk:
12768
0
  case VUNPCKHPSZ256rmkz:
12769
0
  case VUNPCKHPSZ256rr:
12770
0
  case VUNPCKHPSZ256rrk:
12771
0
  case VUNPCKHPSZ256rrkz:
12772
0
  case VUNPCKHPSZrm:
12773
0
  case VUNPCKHPSZrmb:
12774
0
  case VUNPCKHPSZrmbk:
12775
0
  case VUNPCKHPSZrmbkz:
12776
0
  case VUNPCKHPSZrmk:
12777
0
  case VUNPCKHPSZrmkz:
12778
0
  case VUNPCKHPSZrr:
12779
0
  case VUNPCKHPSZrrk:
12780
0
  case VUNPCKHPSZrrkz:
12781
0
  case VUNPCKHPSrm:
12782
0
  case VUNPCKHPSrr:
12783
0
    return true;
12784
0
  }
12785
0
  return false;
12786
0
}
12787
12788
0
bool isVFNMADDSS(unsigned Opcode) {
12789
0
  switch (Opcode) {
12790
0
  case VFNMADDSS4mr:
12791
0
  case VFNMADDSS4rm:
12792
0
  case VFNMADDSS4rr:
12793
0
  case VFNMADDSS4rr_REV:
12794
0
    return true;
12795
0
  }
12796
0
  return false;
12797
0
}
12798
12799
0
bool isSIDT(unsigned Opcode) {
12800
0
  return Opcode == SIDT64m;
12801
0
}
12802
12803
0
bool isVPCMPGTB(unsigned Opcode) {
12804
0
  switch (Opcode) {
12805
0
  case VPCMPGTBYrm:
12806
0
  case VPCMPGTBYrr:
12807
0
  case VPCMPGTBZ128rm:
12808
0
  case VPCMPGTBZ128rmk:
12809
0
  case VPCMPGTBZ128rr:
12810
0
  case VPCMPGTBZ128rrk:
12811
0
  case VPCMPGTBZ256rm:
12812
0
  case VPCMPGTBZ256rmk:
12813
0
  case VPCMPGTBZ256rr:
12814
0
  case VPCMPGTBZ256rrk:
12815
0
  case VPCMPGTBZrm:
12816
0
  case VPCMPGTBZrmk:
12817
0
  case VPCMPGTBZrr:
12818
0
  case VPCMPGTBZrrk:
12819
0
  case VPCMPGTBrm:
12820
0
  case VPCMPGTBrr:
12821
0
    return true;
12822
0
  }
12823
0
  return false;
12824
0
}
12825
12826
0
bool isVPRORD(unsigned Opcode) {
12827
0
  switch (Opcode) {
12828
0
  case VPRORDZ128mbi:
12829
0
  case VPRORDZ128mbik:
12830
0
  case VPRORDZ128mbikz:
12831
0
  case VPRORDZ128mi:
12832
0
  case VPRORDZ128mik:
12833
0
  case VPRORDZ128mikz:
12834
0
  case VPRORDZ128ri:
12835
0
  case VPRORDZ128rik:
12836
0
  case VPRORDZ128rikz:
12837
0
  case VPRORDZ256mbi:
12838
0
  case VPRORDZ256mbik:
12839
0
  case VPRORDZ256mbikz:
12840
0
  case VPRORDZ256mi:
12841
0
  case VPRORDZ256mik:
12842
0
  case VPRORDZ256mikz:
12843
0
  case VPRORDZ256ri:
12844
0
  case VPRORDZ256rik:
12845
0
  case VPRORDZ256rikz:
12846
0
  case VPRORDZmbi:
12847
0
  case VPRORDZmbik:
12848
0
  case VPRORDZmbikz:
12849
0
  case VPRORDZmi:
12850
0
  case VPRORDZmik:
12851
0
  case VPRORDZmikz:
12852
0
  case VPRORDZri:
12853
0
  case VPRORDZrik:
12854
0
  case VPRORDZrikz:
12855
0
    return true;
12856
0
  }
12857
0
  return false;
12858
0
}
12859
12860
0
bool isVSUBSS(unsigned Opcode) {
12861
0
  switch (Opcode) {
12862
0
  case VSUBSSZrm_Int:
12863
0
  case VSUBSSZrm_Intk:
12864
0
  case VSUBSSZrm_Intkz:
12865
0
  case VSUBSSZrr_Int:
12866
0
  case VSUBSSZrr_Intk:
12867
0
  case VSUBSSZrr_Intkz:
12868
0
  case VSUBSSZrrb_Int:
12869
0
  case VSUBSSZrrb_Intk:
12870
0
  case VSUBSSZrrb_Intkz:
12871
0
  case VSUBSSrm_Int:
12872
0
  case VSUBSSrr_Int:
12873
0
    return true;
12874
0
  }
12875
0
  return false;
12876
0
}
12877
12878
0
bool isPUSHFQ(unsigned Opcode) {
12879
0
  return Opcode == PUSHF64;
12880
0
}
12881
12882
0
bool isVPCLMULQDQ(unsigned Opcode) {
12883
0
  switch (Opcode) {
12884
0
  case VPCLMULQDQYrm:
12885
0
  case VPCLMULQDQYrr:
12886
0
  case VPCLMULQDQZ128rm:
12887
0
  case VPCLMULQDQZ128rr:
12888
0
  case VPCLMULQDQZ256rm:
12889
0
  case VPCLMULQDQZ256rr:
12890
0
  case VPCLMULQDQZrm:
12891
0
  case VPCLMULQDQZrr:
12892
0
  case VPCLMULQDQrm:
12893
0
  case VPCLMULQDQrr:
12894
0
    return true;
12895
0
  }
12896
0
  return false;
12897
0
}
12898
12899
0
bool isVPADDUSB(unsigned Opcode) {
12900
0
  switch (Opcode) {
12901
0
  case VPADDUSBYrm:
12902
0
  case VPADDUSBYrr:
12903
0
  case VPADDUSBZ128rm:
12904
0
  case VPADDUSBZ128rmk:
12905
0
  case VPADDUSBZ128rmkz:
12906
0
  case VPADDUSBZ128rr:
12907
0
  case VPADDUSBZ128rrk:
12908
0
  case VPADDUSBZ128rrkz:
12909
0
  case VPADDUSBZ256rm:
12910
0
  case VPADDUSBZ256rmk:
12911
0
  case VPADDUSBZ256rmkz:
12912
0
  case VPADDUSBZ256rr:
12913
0
  case VPADDUSBZ256rrk:
12914
0
  case VPADDUSBZ256rrkz:
12915
0
  case VPADDUSBZrm:
12916
0
  case VPADDUSBZrmk:
12917
0
  case VPADDUSBZrmkz:
12918
0
  case VPADDUSBZrr:
12919
0
  case VPADDUSBZrrk:
12920
0
  case VPADDUSBZrrkz:
12921
0
  case VPADDUSBrm:
12922
0
  case VPADDUSBrr:
12923
0
    return true;
12924
0
  }
12925
0
  return false;
12926
0
}
12927
12928
0
bool isVPCMPD(unsigned Opcode) {
12929
0
  switch (Opcode) {
12930
0
  case VPCMPDZ128rmi:
12931
0
  case VPCMPDZ128rmib:
12932
0
  case VPCMPDZ128rmibk:
12933
0
  case VPCMPDZ128rmik:
12934
0
  case VPCMPDZ128rri:
12935
0
  case VPCMPDZ128rrik:
12936
0
  case VPCMPDZ256rmi:
12937
0
  case VPCMPDZ256rmib:
12938
0
  case VPCMPDZ256rmibk:
12939
0
  case VPCMPDZ256rmik:
12940
0
  case VPCMPDZ256rri:
12941
0
  case VPCMPDZ256rrik:
12942
0
  case VPCMPDZrmi:
12943
0
  case VPCMPDZrmib:
12944
0
  case VPCMPDZrmibk:
12945
0
  case VPCMPDZrmik:
12946
0
  case VPCMPDZrri:
12947
0
  case VPCMPDZrrik:
12948
0
    return true;
12949
0
  }
12950
0
  return false;
12951
0
}
12952
12953
0
bool isMOVSD(unsigned Opcode) {
12954
0
  switch (Opcode) {
12955
0
  case MOVSDmr:
12956
0
  case MOVSDrm:
12957
0
  case MOVSDrr:
12958
0
  case MOVSDrr_REV:
12959
0
  case MOVSL:
12960
0
    return true;
12961
0
  }
12962
0
  return false;
12963
0
}
12964
12965
0
bool isPSUBUSW(unsigned Opcode) {
12966
0
  switch (Opcode) {
12967
0
  case MMX_PSUBUSWrm:
12968
0
  case MMX_PSUBUSWrr:
12969
0
  case PSUBUSWrm:
12970
0
  case PSUBUSWrr:
12971
0
    return true;
12972
0
  }
12973
0
  return false;
12974
0
}
12975
12976
0
bool isVFMSUBADD132PS(unsigned Opcode) {
12977
0
  switch (Opcode) {
12978
0
  case VFMSUBADD132PSYm:
12979
0
  case VFMSUBADD132PSYr:
12980
0
  case VFMSUBADD132PSZ128m:
12981
0
  case VFMSUBADD132PSZ128mb:
12982
0
  case VFMSUBADD132PSZ128mbk:
12983
0
  case VFMSUBADD132PSZ128mbkz:
12984
0
  case VFMSUBADD132PSZ128mk:
12985
0
  case VFMSUBADD132PSZ128mkz:
12986
0
  case VFMSUBADD132PSZ128r:
12987
0
  case VFMSUBADD132PSZ128rk:
12988
0
  case VFMSUBADD132PSZ128rkz:
12989
0
  case VFMSUBADD132PSZ256m:
12990
0
  case VFMSUBADD132PSZ256mb:
12991
0
  case VFMSUBADD132PSZ256mbk:
12992
0
  case VFMSUBADD132PSZ256mbkz:
12993
0
  case VFMSUBADD132PSZ256mk:
12994
0
  case VFMSUBADD132PSZ256mkz:
12995
0
  case VFMSUBADD132PSZ256r:
12996
0
  case VFMSUBADD132PSZ256rk:
12997
0
  case VFMSUBADD132PSZ256rkz:
12998
0
  case VFMSUBADD132PSZm:
12999
0
  case VFMSUBADD132PSZmb:
13000
0
  case VFMSUBADD132PSZmbk:
13001
0
  case VFMSUBADD132PSZmbkz:
13002
0
  case VFMSUBADD132PSZmk:
13003
0
  case VFMSUBADD132PSZmkz:
13004
0
  case VFMSUBADD132PSZr:
13005
0
  case VFMSUBADD132PSZrb:
13006
0
  case VFMSUBADD132PSZrbk:
13007
0
  case VFMSUBADD132PSZrbkz:
13008
0
  case VFMSUBADD132PSZrk:
13009
0
  case VFMSUBADD132PSZrkz:
13010
0
  case VFMSUBADD132PSm:
13011
0
  case VFMSUBADD132PSr:
13012
0
    return true;
13013
0
  }
13014
0
  return false;
13015
0
}
13016
13017
0
bool isMOVMSKPS(unsigned Opcode) {
13018
0
  return Opcode == MOVMSKPSrr;
13019
0
}
13020
13021
0
bool isVFIXUPIMMSS(unsigned Opcode) {
13022
0
  switch (Opcode) {
13023
0
  case VFIXUPIMMSSZrmi:
13024
0
  case VFIXUPIMMSSZrmik:
13025
0
  case VFIXUPIMMSSZrmikz:
13026
0
  case VFIXUPIMMSSZrri:
13027
0
  case VFIXUPIMMSSZrrib:
13028
0
  case VFIXUPIMMSSZrribk:
13029
0
  case VFIXUPIMMSSZrribkz:
13030
0
  case VFIXUPIMMSSZrrik:
13031
0
  case VFIXUPIMMSSZrrikz:
13032
0
    return true;
13033
0
  }
13034
0
  return false;
13035
0
}
13036
13037
0
bool isMFENCE(unsigned Opcode) {
13038
0
  return Opcode == MFENCE;
13039
0
}
13040
13041
0
bool isFTST(unsigned Opcode) {
13042
0
  return Opcode == TST_F;
13043
0
}
13044
13045
0
bool isVPMADDWD(unsigned Opcode) {
13046
0
  switch (Opcode) {
13047
0
  case VPMADDWDYrm:
13048
0
  case VPMADDWDYrr:
13049
0
  case VPMADDWDZ128rm:
13050
0
  case VPMADDWDZ128rmk:
13051
0
  case VPMADDWDZ128rmkz:
13052
0
  case VPMADDWDZ128rr:
13053
0
  case VPMADDWDZ128rrk:
13054
0
  case VPMADDWDZ128rrkz:
13055
0
  case VPMADDWDZ256rm:
13056
0
  case VPMADDWDZ256rmk:
13057
0
  case VPMADDWDZ256rmkz:
13058
0
  case VPMADDWDZ256rr:
13059
0
  case VPMADDWDZ256rrk:
13060
0
  case VPMADDWDZ256rrkz:
13061
0
  case VPMADDWDZrm:
13062
0
  case VPMADDWDZrmk:
13063
0
  case VPMADDWDZrmkz:
13064
0
  case VPMADDWDZrr:
13065
0
  case VPMADDWDZrrk:
13066
0
  case VPMADDWDZrrkz:
13067
0
  case VPMADDWDrm:
13068
0
  case VPMADDWDrr:
13069
0
    return true;
13070
0
  }
13071
0
  return false;
13072
0
}
13073
13074
0
bool isPOP(unsigned Opcode) {
13075
0
  switch (Opcode) {
13076
0
  case POP16r:
13077
0
  case POP16rmm:
13078
0
  case POP16rmr:
13079
0
  case POP32r:
13080
0
  case POP32rmm:
13081
0
  case POP32rmr:
13082
0
  case POP64r:
13083
0
  case POP64rmm:
13084
0
  case POP64rmr:
13085
0
  case POPDS16:
13086
0
  case POPDS32:
13087
0
  case POPES16:
13088
0
  case POPES32:
13089
0
  case POPFS16:
13090
0
  case POPFS32:
13091
0
  case POPFS64:
13092
0
  case POPGS16:
13093
0
  case POPGS32:
13094
0
  case POPGS64:
13095
0
  case POPSS16:
13096
0
  case POPSS32:
13097
0
    return true;
13098
0
  }
13099
0
  return false;
13100
0
}
13101
13102
0
bool isPSUBW(unsigned Opcode) {
13103
0
  switch (Opcode) {
13104
0
  case MMX_PSUBWrm:
13105
0
  case MMX_PSUBWrr:
13106
0
  case PSUBWrm:
13107
0
  case PSUBWrr:
13108
0
    return true;
13109
0
  }
13110
0
  return false;
13111
0
}
13112
13113
0
bool isBSWAP(unsigned Opcode) {
13114
0
  switch (Opcode) {
13115
0
  case BSWAP16r_BAD:
13116
0
  case BSWAP32r:
13117
0
  case BSWAP64r:
13118
0
    return true;
13119
0
  }
13120
0
  return false;
13121
0
}
13122
13123
0
bool isPFMIN(unsigned Opcode) {
13124
0
  switch (Opcode) {
13125
0
  case PFMINrm:
13126
0
  case PFMINrr:
13127
0
    return true;
13128
0
  }
13129
0
  return false;
13130
0
}
13131
13132
0
bool isVFPCLASSPD(unsigned Opcode) {
13133
0
  switch (Opcode) {
13134
0
  case VFPCLASSPDZ128rm:
13135
0
  case VFPCLASSPDZ128rmb:
13136
0
  case VFPCLASSPDZ128rmbk:
13137
0
  case VFPCLASSPDZ128rmk:
13138
0
  case VFPCLASSPDZ128rr:
13139
0
  case VFPCLASSPDZ128rrk:
13140
0
  case VFPCLASSPDZ256rm:
13141
0
  case VFPCLASSPDZ256rmb:
13142
0
  case VFPCLASSPDZ256rmbk:
13143
0
  case VFPCLASSPDZ256rmk:
13144
0
  case VFPCLASSPDZ256rr:
13145
0
  case VFPCLASSPDZ256rrk:
13146
0
  case VFPCLASSPDZrm:
13147
0
  case VFPCLASSPDZrmb:
13148
0
  case VFPCLASSPDZrmbk:
13149
0
  case VFPCLASSPDZrmk:
13150
0
  case VFPCLASSPDZrr:
13151
0
  case VFPCLASSPDZrrk:
13152
0
    return true;
13153
0
  }
13154
0
  return false;
13155
0
}
13156
13157
0
bool isVPSHRDVD(unsigned Opcode) {
13158
0
  switch (Opcode) {
13159
0
  case VPSHRDVDZ128m:
13160
0
  case VPSHRDVDZ128mb:
13161
0
  case VPSHRDVDZ128mbk:
13162
0
  case VPSHRDVDZ128mbkz:
13163
0
  case VPSHRDVDZ128mk:
13164
0
  case VPSHRDVDZ128mkz:
13165
0
  case VPSHRDVDZ128r:
13166
0
  case VPSHRDVDZ128rk:
13167
0
  case VPSHRDVDZ128rkz:
13168
0
  case VPSHRDVDZ256m:
13169
0
  case VPSHRDVDZ256mb:
13170
0
  case VPSHRDVDZ256mbk:
13171
0
  case VPSHRDVDZ256mbkz:
13172
0
  case VPSHRDVDZ256mk:
13173
0
  case VPSHRDVDZ256mkz:
13174
0
  case VPSHRDVDZ256r:
13175
0
  case VPSHRDVDZ256rk:
13176
0
  case VPSHRDVDZ256rkz:
13177
0
  case VPSHRDVDZm:
13178
0
  case VPSHRDVDZmb:
13179
0
  case VPSHRDVDZmbk:
13180
0
  case VPSHRDVDZmbkz:
13181
0
  case VPSHRDVDZmk:
13182
0
  case VPSHRDVDZmkz:
13183
0
  case VPSHRDVDZr:
13184
0
  case VPSHRDVDZrk:
13185
0
  case VPSHRDVDZrkz:
13186
0
    return true;
13187
0
  }
13188
0
  return false;
13189
0
}
13190
13191
0
bool isPADDW(unsigned Opcode) {
13192
0
  switch (Opcode) {
13193
0
  case MMX_PADDWrm:
13194
0
  case MMX_PADDWrr:
13195
0
  case PADDWrm:
13196
0
  case PADDWrr:
13197
0
    return true;
13198
0
  }
13199
0
  return false;
13200
0
}
13201
13202
0
bool isCVTSI2SD(unsigned Opcode) {
13203
0
  switch (Opcode) {
13204
0
  case CVTSI2SDrm_Int:
13205
0
  case CVTSI2SDrr_Int:
13206
0
  case CVTSI642SDrm_Int:
13207
0
  case CVTSI642SDrr_Int:
13208
0
    return true;
13209
0
  }
13210
0
  return false;
13211
0
}
13212
13213
0
bool isENQCMD(unsigned Opcode) {
13214
0
  switch (Opcode) {
13215
0
  case ENQCMD16:
13216
0
  case ENQCMD32:
13217
0
  case ENQCMD64:
13218
0
    return true;
13219
0
  }
13220
0
  return false;
13221
0
}
13222
13223
0
bool isXSHA1(unsigned Opcode) {
13224
0
  return Opcode == XSHA1;
13225
0
}
13226
13227
0
bool isVFNMADD132SD(unsigned Opcode) {
13228
0
  switch (Opcode) {
13229
0
  case VFNMADD132SDZm_Int:
13230
0
  case VFNMADD132SDZm_Intk:
13231
0
  case VFNMADD132SDZm_Intkz:
13232
0
  case VFNMADD132SDZr_Int:
13233
0
  case VFNMADD132SDZr_Intk:
13234
0
  case VFNMADD132SDZr_Intkz:
13235
0
  case VFNMADD132SDZrb_Int:
13236
0
  case VFNMADD132SDZrb_Intk:
13237
0
  case VFNMADD132SDZrb_Intkz:
13238
0
  case VFNMADD132SDm_Int:
13239
0
  case VFNMADD132SDr_Int:
13240
0
    return true;
13241
0
  }
13242
0
  return false;
13243
0
}
13244
13245
0
bool isMOVZX(unsigned Opcode) {
13246
0
  switch (Opcode) {
13247
0
  case MOVZX16rm16:
13248
0
  case MOVZX16rm8:
13249
0
  case MOVZX16rr16:
13250
0
  case MOVZX16rr8:
13251
0
  case MOVZX32rm16:
13252
0
  case MOVZX32rm8:
13253
0
  case MOVZX32rr16:
13254
0
  case MOVZX32rr8:
13255
0
  case MOVZX64rm16:
13256
0
  case MOVZX64rm8:
13257
0
  case MOVZX64rr16:
13258
0
  case MOVZX64rr8:
13259
0
    return true;
13260
0
  }
13261
0
  return false;
13262
0
}
13263
13264
0
bool isVFIXUPIMMSD(unsigned Opcode) {
13265
0
  switch (Opcode) {
13266
0
  case VFIXUPIMMSDZrmi:
13267
0
  case VFIXUPIMMSDZrmik:
13268
0
  case VFIXUPIMMSDZrmikz:
13269
0
  case VFIXUPIMMSDZrri:
13270
0
  case VFIXUPIMMSDZrrib:
13271
0
  case VFIXUPIMMSDZrribk:
13272
0
  case VFIXUPIMMSDZrribkz:
13273
0
  case VFIXUPIMMSDZrrik:
13274
0
  case VFIXUPIMMSDZrrikz:
13275
0
    return true;
13276
0
  }
13277
0
  return false;
13278
0
}
13279
13280
0
bool isINVD(unsigned Opcode) {
13281
0
  return Opcode == INVD;
13282
0
}
13283
13284
0
bool isVFIXUPIMMPS(unsigned Opcode) {
13285
0
  switch (Opcode) {
13286
0
  case VFIXUPIMMPSZ128rmbi:
13287
0
  case VFIXUPIMMPSZ128rmbik:
13288
0
  case VFIXUPIMMPSZ128rmbikz:
13289
0
  case VFIXUPIMMPSZ128rmi:
13290
0
  case VFIXUPIMMPSZ128rmik:
13291
0
  case VFIXUPIMMPSZ128rmikz:
13292
0
  case VFIXUPIMMPSZ128rri:
13293
0
  case VFIXUPIMMPSZ128rrik:
13294
0
  case VFIXUPIMMPSZ128rrikz:
13295
0
  case VFIXUPIMMPSZ256rmbi:
13296
0
  case VFIXUPIMMPSZ256rmbik:
13297
0
  case VFIXUPIMMPSZ256rmbikz:
13298
0
  case VFIXUPIMMPSZ256rmi:
13299
0
  case VFIXUPIMMPSZ256rmik:
13300
0
  case VFIXUPIMMPSZ256rmikz:
13301
0
  case VFIXUPIMMPSZ256rri:
13302
0
  case VFIXUPIMMPSZ256rrik:
13303
0
  case VFIXUPIMMPSZ256rrikz:
13304
0
  case VFIXUPIMMPSZrmbi:
13305
0
  case VFIXUPIMMPSZrmbik:
13306
0
  case VFIXUPIMMPSZrmbikz:
13307
0
  case VFIXUPIMMPSZrmi:
13308
0
  case VFIXUPIMMPSZrmik:
13309
0
  case VFIXUPIMMPSZrmikz:
13310
0
  case VFIXUPIMMPSZrri:
13311
0
  case VFIXUPIMMPSZrrib:
13312
0
  case VFIXUPIMMPSZrribk:
13313
0
  case VFIXUPIMMPSZrribkz:
13314
0
  case VFIXUPIMMPSZrrik:
13315
0
  case VFIXUPIMMPSZrrikz:
13316
0
    return true;
13317
0
  }
13318
0
  return false;
13319
0
}
13320
13321
0
bool isMOVDQU(unsigned Opcode) {
13322
0
  switch (Opcode) {
13323
0
  case MOVDQUmr:
13324
0
  case MOVDQUrm:
13325
0
  case MOVDQUrr:
13326
0
  case MOVDQUrr_REV:
13327
0
    return true;
13328
0
  }
13329
0
  return false;
13330
0
}
13331
13332
0
bool isVFPCLASSPS(unsigned Opcode) {
13333
0
  switch (Opcode) {
13334
0
  case VFPCLASSPSZ128rm:
13335
0
  case VFPCLASSPSZ128rmb:
13336
0
  case VFPCLASSPSZ128rmbk:
13337
0
  case VFPCLASSPSZ128rmk:
13338
0
  case VFPCLASSPSZ128rr:
13339
0
  case VFPCLASSPSZ128rrk:
13340
0
  case VFPCLASSPSZ256rm:
13341
0
  case VFPCLASSPSZ256rmb:
13342
0
  case VFPCLASSPSZ256rmbk:
13343
0
  case VFPCLASSPSZ256rmk:
13344
0
  case VFPCLASSPSZ256rr:
13345
0
  case VFPCLASSPSZ256rrk:
13346
0
  case VFPCLASSPSZrm:
13347
0
  case VFPCLASSPSZrmb:
13348
0
  case VFPCLASSPSZrmbk:
13349
0
  case VFPCLASSPSZrmk:
13350
0
  case VFPCLASSPSZrr:
13351
0
  case VFPCLASSPSZrrk:
13352
0
    return true;
13353
0
  }
13354
0
  return false;
13355
0
}
13356
13357
0
bool isMOVSQ(unsigned Opcode) {
13358
0
  return Opcode == MOVSQ;
13359
0
}
13360
13361
0
bool isAESDECWIDE128KL(unsigned Opcode) {
13362
0
  return Opcode == AESDECWIDE128KL;
13363
0
}
13364
13365
0
bool isROUNDSS(unsigned Opcode) {
13366
0
  switch (Opcode) {
13367
0
  case ROUNDSSm_Int:
13368
0
  case ROUNDSSr_Int:
13369
0
    return true;
13370
0
  }
13371
0
  return false;
13372
0
}
13373
13374
0
bool isVPERMILPS(unsigned Opcode) {
13375
0
  switch (Opcode) {
13376
0
  case VPERMILPSYmi:
13377
0
  case VPERMILPSYri:
13378
0
  case VPERMILPSYrm:
13379
0
  case VPERMILPSYrr:
13380
0
  case VPERMILPSZ128mbi:
13381
0
  case VPERMILPSZ128mbik:
13382
0
  case VPERMILPSZ128mbikz:
13383
0
  case VPERMILPSZ128mi:
13384
0
  case VPERMILPSZ128mik:
13385
0
  case VPERMILPSZ128mikz:
13386
0
  case VPERMILPSZ128ri:
13387
0
  case VPERMILPSZ128rik:
13388
0
  case VPERMILPSZ128rikz:
13389
0
  case VPERMILPSZ128rm:
13390
0
  case VPERMILPSZ128rmb:
13391
0
  case VPERMILPSZ128rmbk:
13392
0
  case VPERMILPSZ128rmbkz:
13393
0
  case VPERMILPSZ128rmk:
13394
0
  case VPERMILPSZ128rmkz:
13395
0
  case VPERMILPSZ128rr:
13396
0
  case VPERMILPSZ128rrk:
13397
0
  case VPERMILPSZ128rrkz:
13398
0
  case VPERMILPSZ256mbi:
13399
0
  case VPERMILPSZ256mbik:
13400
0
  case VPERMILPSZ256mbikz:
13401
0
  case VPERMILPSZ256mi:
13402
0
  case VPERMILPSZ256mik:
13403
0
  case VPERMILPSZ256mikz:
13404
0
  case VPERMILPSZ256ri:
13405
0
  case VPERMILPSZ256rik:
13406
0
  case VPERMILPSZ256rikz:
13407
0
  case VPERMILPSZ256rm:
13408
0
  case VPERMILPSZ256rmb:
13409
0
  case VPERMILPSZ256rmbk:
13410
0
  case VPERMILPSZ256rmbkz:
13411
0
  case VPERMILPSZ256rmk:
13412
0
  case VPERMILPSZ256rmkz:
13413
0
  case VPERMILPSZ256rr:
13414
0
  case VPERMILPSZ256rrk:
13415
0
  case VPERMILPSZ256rrkz:
13416
0
  case VPERMILPSZmbi:
13417
0
  case VPERMILPSZmbik:
13418
0
  case VPERMILPSZmbikz:
13419
0
  case VPERMILPSZmi:
13420
0
  case VPERMILPSZmik:
13421
0
  case VPERMILPSZmikz:
13422
0
  case VPERMILPSZri:
13423
0
  case VPERMILPSZrik:
13424
0
  case VPERMILPSZrikz:
13425
0
  case VPERMILPSZrm:
13426
0
  case VPERMILPSZrmb:
13427
0
  case VPERMILPSZrmbk:
13428
0
  case VPERMILPSZrmbkz:
13429
0
  case VPERMILPSZrmk:
13430
0
  case VPERMILPSZrmkz:
13431
0
  case VPERMILPSZrr:
13432
0
  case VPERMILPSZrrk:
13433
0
  case VPERMILPSZrrkz:
13434
0
  case VPERMILPSmi:
13435
0
  case VPERMILPSri:
13436
0
  case VPERMILPSrm:
13437
0
  case VPERMILPSrr:
13438
0
    return true;
13439
0
  }
13440
0
  return false;
13441
0
}
13442
13443
0
bool isVPMOVW2M(unsigned Opcode) {
13444
0
  switch (Opcode) {
13445
0
  case VPMOVW2MZ128rr:
13446
0
  case VPMOVW2MZ256rr:
13447
0
  case VPMOVW2MZrr:
13448
0
    return true;
13449
0
  }
13450
0
  return false;
13451
0
}
13452
13453
0
bool isVMULSD(unsigned Opcode) {
13454
0
  switch (Opcode) {
13455
0
  case VMULSDZrm_Int:
13456
0
  case VMULSDZrm_Intk:
13457
0
  case VMULSDZrm_Intkz:
13458
0
  case VMULSDZrr_Int:
13459
0
  case VMULSDZrr_Intk:
13460
0
  case VMULSDZrr_Intkz:
13461
0
  case VMULSDZrrb_Int:
13462
0
  case VMULSDZrrb_Intk:
13463
0
  case VMULSDZrrb_Intkz:
13464
0
  case VMULSDrm_Int:
13465
0
  case VMULSDrr_Int:
13466
0
    return true;
13467
0
  }
13468
0
  return false;
13469
0
}
13470
13471
0
bool isVPERMI2W(unsigned Opcode) {
13472
0
  switch (Opcode) {
13473
0
  case VPERMI2WZ128rm:
13474
0
  case VPERMI2WZ128rmk:
13475
0
  case VPERMI2WZ128rmkz:
13476
0
  case VPERMI2WZ128rr:
13477
0
  case VPERMI2WZ128rrk:
13478
0
  case VPERMI2WZ128rrkz:
13479
0
  case VPERMI2WZ256rm:
13480
0
  case VPERMI2WZ256rmk:
13481
0
  case VPERMI2WZ256rmkz:
13482
0
  case VPERMI2WZ256rr:
13483
0
  case VPERMI2WZ256rrk:
13484
0
  case VPERMI2WZ256rrkz:
13485
0
  case VPERMI2WZrm:
13486
0
  case VPERMI2WZrmk:
13487
0
  case VPERMI2WZrmkz:
13488
0
  case VPERMI2WZrr:
13489
0
  case VPERMI2WZrrk:
13490
0
  case VPERMI2WZrrkz:
13491
0
    return true;
13492
0
  }
13493
0
  return false;
13494
0
}
13495
13496
0
bool isVPSHUFB(unsigned Opcode) {
13497
0
  switch (Opcode) {
13498
0
  case VPSHUFBYrm:
13499
0
  case VPSHUFBYrr:
13500
0
  case VPSHUFBZ128rm:
13501
0
  case VPSHUFBZ128rmk:
13502
0
  case VPSHUFBZ128rmkz:
13503
0
  case VPSHUFBZ128rr:
13504
0
  case VPSHUFBZ128rrk:
13505
0
  case VPSHUFBZ128rrkz:
13506
0
  case VPSHUFBZ256rm:
13507
0
  case VPSHUFBZ256rmk:
13508
0
  case VPSHUFBZ256rmkz:
13509
0
  case VPSHUFBZ256rr:
13510
0
  case VPSHUFBZ256rrk:
13511
0
  case VPSHUFBZ256rrkz:
13512
0
  case VPSHUFBZrm:
13513
0
  case VPSHUFBZrmk:
13514
0
  case VPSHUFBZrmkz:
13515
0
  case VPSHUFBZrr:
13516
0
  case VPSHUFBZrrk:
13517
0
  case VPSHUFBZrrkz:
13518
0
  case VPSHUFBrm:
13519
0
  case VPSHUFBrr:
13520
0
    return true;
13521
0
  }
13522
0
  return false;
13523
0
}
13524
13525
0
bool isFST(unsigned Opcode) {
13526
0
  switch (Opcode) {
13527
0
  case ST_F32m:
13528
0
  case ST_F64m:
13529
0
  case ST_Frr:
13530
0
    return true;
13531
0
  }
13532
0
  return false;
13533
0
}
13534
13535
0
bool isVPHSUBW(unsigned Opcode) {
13536
0
  switch (Opcode) {
13537
0
  case VPHSUBWYrm:
13538
0
  case VPHSUBWYrr:
13539
0
  case VPHSUBWrm:
13540
0
  case VPHSUBWrr:
13541
0
    return true;
13542
0
  }
13543
0
  return false;
13544
0
}
13545
13546
0
bool isVREDUCESS(unsigned Opcode) {
13547
0
  switch (Opcode) {
13548
0
  case VREDUCESSZrmi:
13549
0
  case VREDUCESSZrmik:
13550
0
  case VREDUCESSZrmikz:
13551
0
  case VREDUCESSZrri:
13552
0
  case VREDUCESSZrrib:
13553
0
  case VREDUCESSZrribk:
13554
0
  case VREDUCESSZrribkz:
13555
0
  case VREDUCESSZrrik:
13556
0
  case VREDUCESSZrrikz:
13557
0
    return true;
13558
0
  }
13559
0
  return false;
13560
0
}
13561
13562
0
bool isFRNDINT(unsigned Opcode) {
13563
0
  return Opcode == FRNDINT;
13564
0
}
13565
13566
0
bool isSHR(unsigned Opcode) {
13567
0
  switch (Opcode) {
13568
0
  case SHR16m1:
13569
0
  case SHR16mCL:
13570
0
  case SHR16mi:
13571
0
  case SHR16r1:
13572
0
  case SHR16rCL:
13573
0
  case SHR16ri:
13574
0
  case SHR32m1:
13575
0
  case SHR32mCL:
13576
0
  case SHR32mi:
13577
0
  case SHR32r1:
13578
0
  case SHR32rCL:
13579
0
  case SHR32ri:
13580
0
  case SHR64m1:
13581
0
  case SHR64mCL:
13582
0
  case SHR64mi:
13583
0
  case SHR64r1:
13584
0
  case SHR64rCL:
13585
0
  case SHR64ri:
13586
0
  case SHR8m1:
13587
0
  case SHR8mCL:
13588
0
  case SHR8mi:
13589
0
  case SHR8r1:
13590
0
  case SHR8rCL:
13591
0
  case SHR8ri:
13592
0
    return true;
13593
0
  }
13594
0
  return false;
13595
0
}
13596
13597
0
bool isLOOPNE(unsigned Opcode) {
13598
0
  return Opcode == LOOPNE;
13599
0
}
13600
13601
0
bool isVCVTTPH2UQQ(unsigned Opcode) {
13602
0
  switch (Opcode) {
13603
0
  case VCVTTPH2UQQZ128rm:
13604
0
  case VCVTTPH2UQQZ128rmb:
13605
0
  case VCVTTPH2UQQZ128rmbk:
13606
0
  case VCVTTPH2UQQZ128rmbkz:
13607
0
  case VCVTTPH2UQQZ128rmk:
13608
0
  case VCVTTPH2UQQZ128rmkz:
13609
0
  case VCVTTPH2UQQZ128rr:
13610
0
  case VCVTTPH2UQQZ128rrk:
13611
0
  case VCVTTPH2UQQZ128rrkz:
13612
0
  case VCVTTPH2UQQZ256rm:
13613
0
  case VCVTTPH2UQQZ256rmb:
13614
0
  case VCVTTPH2UQQZ256rmbk:
13615
0
  case VCVTTPH2UQQZ256rmbkz:
13616
0
  case VCVTTPH2UQQZ256rmk:
13617
0
  case VCVTTPH2UQQZ256rmkz:
13618
0
  case VCVTTPH2UQQZ256rr:
13619
0
  case VCVTTPH2UQQZ256rrk:
13620
0
  case VCVTTPH2UQQZ256rrkz:
13621
0
  case VCVTTPH2UQQZrm:
13622
0
  case VCVTTPH2UQQZrmb:
13623
0
  case VCVTTPH2UQQZrmbk:
13624
0
  case VCVTTPH2UQQZrmbkz:
13625
0
  case VCVTTPH2UQQZrmk:
13626
0
  case VCVTTPH2UQQZrmkz:
13627
0
  case VCVTTPH2UQQZrr:
13628
0
  case VCVTTPH2UQQZrrb:
13629
0
  case VCVTTPH2UQQZrrbk:
13630
0
  case VCVTTPH2UQQZrrbkz:
13631
0
  case VCVTTPH2UQQZrrk:
13632
0
  case VCVTTPH2UQQZrrkz:
13633
0
    return true;
13634
0
  }
13635
0
  return false;
13636
0
}
13637
13638
0
bool isSHA1NEXTE(unsigned Opcode) {
13639
0
  switch (Opcode) {
13640
0
  case SHA1NEXTErm:
13641
0
  case SHA1NEXTErm_EVEX:
13642
0
  case SHA1NEXTErr:
13643
0
  case SHA1NEXTErr_EVEX:
13644
0
    return true;
13645
0
  }
13646
0
  return false;
13647
0
}
13648
13649
0
bool isVFMADD132SD(unsigned Opcode) {
13650
0
  switch (Opcode) {
13651
0
  case VFMADD132SDZm_Int:
13652
0
  case VFMADD132SDZm_Intk:
13653
0
  case VFMADD132SDZm_Intkz:
13654
0
  case VFMADD132SDZr_Int:
13655
0
  case VFMADD132SDZr_Intk:
13656
0
  case VFMADD132SDZr_Intkz:
13657
0
  case VFMADD132SDZrb_Int:
13658
0
  case VFMADD132SDZrb_Intk:
13659
0
  case VFMADD132SDZrb_Intkz:
13660
0
  case VFMADD132SDm_Int:
13661
0
  case VFMADD132SDr_Int:
13662
0
    return true;
13663
0
  }
13664
0
  return false;
13665
0
}
13666
13667
0
bool isPSRAW(unsigned Opcode) {
13668
0
  switch (Opcode) {
13669
0
  case MMX_PSRAWri:
13670
0
  case MMX_PSRAWrm:
13671
0
  case MMX_PSRAWrr:
13672
0
  case PSRAWri:
13673
0
  case PSRAWrm:
13674
0
  case PSRAWrr:
13675
0
    return true;
13676
0
  }
13677
0
  return false;
13678
0
}
13679
13680
0
bool isVPBROADCASTQ(unsigned Opcode) {
13681
0
  switch (Opcode) {
13682
0
  case VPBROADCASTQYrm:
13683
0
  case VPBROADCASTQYrr:
13684
0
  case VPBROADCASTQZ128rm:
13685
0
  case VPBROADCASTQZ128rmk:
13686
0
  case VPBROADCASTQZ128rmkz:
13687
0
  case VPBROADCASTQZ128rr:
13688
0
  case VPBROADCASTQZ128rrk:
13689
0
  case VPBROADCASTQZ128rrkz:
13690
0
  case VPBROADCASTQZ256rm:
13691
0
  case VPBROADCASTQZ256rmk:
13692
0
  case VPBROADCASTQZ256rmkz:
13693
0
  case VPBROADCASTQZ256rr:
13694
0
  case VPBROADCASTQZ256rrk:
13695
0
  case VPBROADCASTQZ256rrkz:
13696
0
  case VPBROADCASTQZrm:
13697
0
  case VPBROADCASTQZrmk:
13698
0
  case VPBROADCASTQZrmkz:
13699
0
  case VPBROADCASTQZrr:
13700
0
  case VPBROADCASTQZrrk:
13701
0
  case VPBROADCASTQZrrkz:
13702
0
  case VPBROADCASTQrZ128rr:
13703
0
  case VPBROADCASTQrZ128rrk:
13704
0
  case VPBROADCASTQrZ128rrkz:
13705
0
  case VPBROADCASTQrZ256rr:
13706
0
  case VPBROADCASTQrZ256rrk:
13707
0
  case VPBROADCASTQrZ256rrkz:
13708
0
  case VPBROADCASTQrZrr:
13709
0
  case VPBROADCASTQrZrrk:
13710
0
  case VPBROADCASTQrZrrkz:
13711
0
  case VPBROADCASTQrm:
13712
0
  case VPBROADCASTQrr:
13713
0
    return true;
13714
0
  }
13715
0
  return false;
13716
0
}
13717
13718
0
bool isCLC(unsigned Opcode) {
13719
0
  return Opcode == CLC;
13720
0
}
13721
13722
0
bool isPOPAW(unsigned Opcode) {
13723
0
  return Opcode == POPA16;
13724
0
}
13725
13726
0
bool isTCMMIMFP16PS(unsigned Opcode) {
13727
0
  return Opcode == TCMMIMFP16PS;
13728
0
}
13729
13730
0
bool isVCVTTPS2UQQ(unsigned Opcode) {
13731
0
  switch (Opcode) {
13732
0
  case VCVTTPS2UQQZ128rm:
13733
0
  case VCVTTPS2UQQZ128rmb:
13734
0
  case VCVTTPS2UQQZ128rmbk:
13735
0
  case VCVTTPS2UQQZ128rmbkz:
13736
0
  case VCVTTPS2UQQZ128rmk:
13737
0
  case VCVTTPS2UQQZ128rmkz:
13738
0
  case VCVTTPS2UQQZ128rr:
13739
0
  case VCVTTPS2UQQZ128rrk:
13740
0
  case VCVTTPS2UQQZ128rrkz:
13741
0
  case VCVTTPS2UQQZ256rm:
13742
0
  case VCVTTPS2UQQZ256rmb:
13743
0
  case VCVTTPS2UQQZ256rmbk:
13744
0
  case VCVTTPS2UQQZ256rmbkz:
13745
0
  case VCVTTPS2UQQZ256rmk:
13746
0
  case VCVTTPS2UQQZ256rmkz:
13747
0
  case VCVTTPS2UQQZ256rr:
13748
0
  case VCVTTPS2UQQZ256rrk:
13749
0
  case VCVTTPS2UQQZ256rrkz:
13750
0
  case VCVTTPS2UQQZrm:
13751
0
  case VCVTTPS2UQQZrmb:
13752
0
  case VCVTTPS2UQQZrmbk:
13753
0
  case VCVTTPS2UQQZrmbkz:
13754
0
  case VCVTTPS2UQQZrmk:
13755
0
  case VCVTTPS2UQQZrmkz:
13756
0
  case VCVTTPS2UQQZrr:
13757
0
  case VCVTTPS2UQQZrrb:
13758
0
  case VCVTTPS2UQQZrrbk:
13759
0
  case VCVTTPS2UQQZrrbkz:
13760
0
  case VCVTTPS2UQQZrrk:
13761
0
  case VCVTTPS2UQQZrrkz:
13762
0
    return true;
13763
0
  }
13764
0
  return false;
13765
0
}
13766
13767
0
bool isVCVTQQ2PH(unsigned Opcode) {
13768
0
  switch (Opcode) {
13769
0
  case VCVTQQ2PHZ128rm:
13770
0
  case VCVTQQ2PHZ128rmb:
13771
0
  case VCVTQQ2PHZ128rmbk:
13772
0
  case VCVTQQ2PHZ128rmbkz:
13773
0
  case VCVTQQ2PHZ128rmk:
13774
0
  case VCVTQQ2PHZ128rmkz:
13775
0
  case VCVTQQ2PHZ128rr:
13776
0
  case VCVTQQ2PHZ128rrk:
13777
0
  case VCVTQQ2PHZ128rrkz:
13778
0
  case VCVTQQ2PHZ256rm:
13779
0
  case VCVTQQ2PHZ256rmb:
13780
0
  case VCVTQQ2PHZ256rmbk:
13781
0
  case VCVTQQ2PHZ256rmbkz:
13782
0
  case VCVTQQ2PHZ256rmk:
13783
0
  case VCVTQQ2PHZ256rmkz:
13784
0
  case VCVTQQ2PHZ256rr:
13785
0
  case VCVTQQ2PHZ256rrk:
13786
0
  case VCVTQQ2PHZ256rrkz:
13787
0
  case VCVTQQ2PHZrm:
13788
0
  case VCVTQQ2PHZrmb:
13789
0
  case VCVTQQ2PHZrmbk:
13790
0
  case VCVTQQ2PHZrmbkz:
13791
0
  case VCVTQQ2PHZrmk:
13792
0
  case VCVTQQ2PHZrmkz:
13793
0
  case VCVTQQ2PHZrr:
13794
0
  case VCVTQQ2PHZrrb:
13795
0
  case VCVTQQ2PHZrrbk:
13796
0
  case VCVTQQ2PHZrrbkz:
13797
0
  case VCVTQQ2PHZrrk:
13798
0
  case VCVTQQ2PHZrrkz:
13799
0
    return true;
13800
0
  }
13801
0
  return false;
13802
0
}
13803
13804
0
bool isVMOVUPD(unsigned Opcode) {
13805
0
  switch (Opcode) {
13806
0
  case VMOVUPDYmr:
13807
0
  case VMOVUPDYrm:
13808
0
  case VMOVUPDYrr:
13809
0
  case VMOVUPDYrr_REV:
13810
0
  case VMOVUPDZ128mr:
13811
0
  case VMOVUPDZ128mrk:
13812
0
  case VMOVUPDZ128rm:
13813
0
  case VMOVUPDZ128rmk:
13814
0
  case VMOVUPDZ128rmkz:
13815
0
  case VMOVUPDZ128rr:
13816
0
  case VMOVUPDZ128rr_REV:
13817
0
  case VMOVUPDZ128rrk:
13818
0
  case VMOVUPDZ128rrk_REV:
13819
0
  case VMOVUPDZ128rrkz:
13820
0
  case VMOVUPDZ128rrkz_REV:
13821
0
  case VMOVUPDZ256mr:
13822
0
  case VMOVUPDZ256mrk:
13823
0
  case VMOVUPDZ256rm:
13824
0
  case VMOVUPDZ256rmk:
13825
0
  case VMOVUPDZ256rmkz:
13826
0
  case VMOVUPDZ256rr:
13827
0
  case VMOVUPDZ256rr_REV:
13828
0
  case VMOVUPDZ256rrk:
13829
0
  case VMOVUPDZ256rrk_REV:
13830
0
  case VMOVUPDZ256rrkz:
13831
0
  case VMOVUPDZ256rrkz_REV:
13832
0
  case VMOVUPDZmr:
13833
0
  case VMOVUPDZmrk:
13834
0
  case VMOVUPDZrm:
13835
0
  case VMOVUPDZrmk:
13836
0
  case VMOVUPDZrmkz:
13837
0
  case VMOVUPDZrr:
13838
0
  case VMOVUPDZrr_REV:
13839
0
  case VMOVUPDZrrk:
13840
0
  case VMOVUPDZrrk_REV:
13841
0
  case VMOVUPDZrrkz:
13842
0
  case VMOVUPDZrrkz_REV:
13843
0
  case VMOVUPDmr:
13844
0
  case VMOVUPDrm:
13845
0
  case VMOVUPDrr:
13846
0
  case VMOVUPDrr_REV:
13847
0
    return true;
13848
0
  }
13849
0
  return false;
13850
0
}
13851
13852
0
bool isFPTAN(unsigned Opcode) {
13853
0
  return Opcode == FPTAN;
13854
0
}
13855
13856
0
bool isVMASKMOVPD(unsigned Opcode) {
13857
0
  switch (Opcode) {
13858
0
  case VMASKMOVPDYmr:
13859
0
  case VMASKMOVPDYrm:
13860
0
  case VMASKMOVPDmr:
13861
0
  case VMASKMOVPDrm:
13862
0
    return true;
13863
0
  }
13864
0
  return false;
13865
0
}
13866
13867
0
bool isVMOVLHPS(unsigned Opcode) {
13868
0
  switch (Opcode) {
13869
0
  case VMOVLHPSZrr:
13870
0
  case VMOVLHPSrr:
13871
0
    return true;
13872
0
  }
13873
0
  return false;
13874
0
}
13875
13876
0
bool isAESKEYGENASSIST(unsigned Opcode) {
13877
0
  switch (Opcode) {
13878
0
  case AESKEYGENASSIST128rm:
13879
0
  case AESKEYGENASSIST128rr:
13880
0
    return true;
13881
0
  }
13882
0
  return false;
13883
0
}
13884
13885
0
bool isXSAVEOPT64(unsigned Opcode) {
13886
0
  return Opcode == XSAVEOPT64;
13887
0
}
13888
13889
0
bool isXSAVEC(unsigned Opcode) {
13890
0
  return Opcode == XSAVEC;
13891
0
}
13892
13893
0
bool isVPLZCNTQ(unsigned Opcode) {
13894
0
  switch (Opcode) {
13895
0
  case VPLZCNTQZ128rm:
13896
0
  case VPLZCNTQZ128rmb:
13897
0
  case VPLZCNTQZ128rmbk:
13898
0
  case VPLZCNTQZ128rmbkz:
13899
0
  case VPLZCNTQZ128rmk:
13900
0
  case VPLZCNTQZ128rmkz:
13901
0
  case VPLZCNTQZ128rr:
13902
0
  case VPLZCNTQZ128rrk:
13903
0
  case VPLZCNTQZ128rrkz:
13904
0
  case VPLZCNTQZ256rm:
13905
0
  case VPLZCNTQZ256rmb:
13906
0
  case VPLZCNTQZ256rmbk:
13907
0
  case VPLZCNTQZ256rmbkz:
13908
0
  case VPLZCNTQZ256rmk:
13909
0
  case VPLZCNTQZ256rmkz:
13910
0
  case VPLZCNTQZ256rr:
13911
0
  case VPLZCNTQZ256rrk:
13912
0
  case VPLZCNTQZ256rrkz:
13913
0
  case VPLZCNTQZrm:
13914
0
  case VPLZCNTQZrmb:
13915
0
  case VPLZCNTQZrmbk:
13916
0
  case VPLZCNTQZrmbkz:
13917
0
  case VPLZCNTQZrmk:
13918
0
  case VPLZCNTQZrmkz:
13919
0
  case VPLZCNTQZrr:
13920
0
  case VPLZCNTQZrrk:
13921
0
  case VPLZCNTQZrrkz:
13922
0
    return true;
13923
0
  }
13924
0
  return false;
13925
0
}
13926
13927
0
bool isVPSUBW(unsigned Opcode) {
13928
0
  switch (Opcode) {
13929
0
  case VPSUBWYrm:
13930
0
  case VPSUBWYrr:
13931
0
  case VPSUBWZ128rm:
13932
0
  case VPSUBWZ128rmk:
13933
0
  case VPSUBWZ128rmkz:
13934
0
  case VPSUBWZ128rr:
13935
0
  case VPSUBWZ128rrk:
13936
0
  case VPSUBWZ128rrkz:
13937
0
  case VPSUBWZ256rm:
13938
0
  case VPSUBWZ256rmk:
13939
0
  case VPSUBWZ256rmkz:
13940
0
  case VPSUBWZ256rr:
13941
0
  case VPSUBWZ256rrk:
13942
0
  case VPSUBWZ256rrkz:
13943
0
  case VPSUBWZrm:
13944
0
  case VPSUBWZrmk:
13945
0
  case VPSUBWZrmkz:
13946
0
  case VPSUBWZrr:
13947
0
  case VPSUBWZrrk:
13948
0
  case VPSUBWZrrkz:
13949
0
  case VPSUBWrm:
13950
0
  case VPSUBWrr:
13951
0
    return true;
13952
0
  }
13953
0
  return false;
13954
0
}
13955
13956
0
bool isVFMSUBADD213PH(unsigned Opcode) {
13957
0
  switch (Opcode) {
13958
0
  case VFMSUBADD213PHZ128m:
13959
0
  case VFMSUBADD213PHZ128mb:
13960
0
  case VFMSUBADD213PHZ128mbk:
13961
0
  case VFMSUBADD213PHZ128mbkz:
13962
0
  case VFMSUBADD213PHZ128mk:
13963
0
  case VFMSUBADD213PHZ128mkz:
13964
0
  case VFMSUBADD213PHZ128r:
13965
0
  case VFMSUBADD213PHZ128rk:
13966
0
  case VFMSUBADD213PHZ128rkz:
13967
0
  case VFMSUBADD213PHZ256m:
13968
0
  case VFMSUBADD213PHZ256mb:
13969
0
  case VFMSUBADD213PHZ256mbk:
13970
0
  case VFMSUBADD213PHZ256mbkz:
13971
0
  case VFMSUBADD213PHZ256mk:
13972
0
  case VFMSUBADD213PHZ256mkz:
13973
0
  case VFMSUBADD213PHZ256r:
13974
0
  case VFMSUBADD213PHZ256rk:
13975
0
  case VFMSUBADD213PHZ256rkz:
13976
0
  case VFMSUBADD213PHZm:
13977
0
  case VFMSUBADD213PHZmb:
13978
0
  case VFMSUBADD213PHZmbk:
13979
0
  case VFMSUBADD213PHZmbkz:
13980
0
  case VFMSUBADD213PHZmk:
13981
0
  case VFMSUBADD213PHZmkz:
13982
0
  case VFMSUBADD213PHZr:
13983
0
  case VFMSUBADD213PHZrb:
13984
0
  case VFMSUBADD213PHZrbk:
13985
0
  case VFMSUBADD213PHZrbkz:
13986
0
  case VFMSUBADD213PHZrk:
13987
0
  case VFMSUBADD213PHZrkz:
13988
0
    return true;
13989
0
  }
13990
0
  return false;
13991
0
}
13992
13993
0
bool isVFMADDSUBPD(unsigned Opcode) {
13994
0
  switch (Opcode) {
13995
0
  case VFMADDSUBPD4Ymr:
13996
0
  case VFMADDSUBPD4Yrm:
13997
0
  case VFMADDSUBPD4Yrr:
13998
0
  case VFMADDSUBPD4Yrr_REV:
13999
0
  case VFMADDSUBPD4mr:
14000
0
  case VFMADDSUBPD4rm:
14001
0
  case VFMADDSUBPD4rr:
14002
0
  case VFMADDSUBPD4rr_REV:
14003
0
    return true;
14004
0
  }
14005
0
  return false;
14006
0
}
14007
14008
0
bool isVPMINSW(unsigned Opcode) {
14009
0
  switch (Opcode) {
14010
0
  case VPMINSWYrm:
14011
0
  case VPMINSWYrr:
14012
0
  case VPMINSWZ128rm:
14013
0
  case VPMINSWZ128rmk:
14014
0
  case VPMINSWZ128rmkz:
14015
0
  case VPMINSWZ128rr:
14016
0
  case VPMINSWZ128rrk:
14017
0
  case VPMINSWZ128rrkz:
14018
0
  case VPMINSWZ256rm:
14019
0
  case VPMINSWZ256rmk:
14020
0
  case VPMINSWZ256rmkz:
14021
0
  case VPMINSWZ256rr:
14022
0
  case VPMINSWZ256rrk:
14023
0
  case VPMINSWZ256rrkz:
14024
0
  case VPMINSWZrm:
14025
0
  case VPMINSWZrmk:
14026
0
  case VPMINSWZrmkz:
14027
0
  case VPMINSWZrr:
14028
0
  case VPMINSWZrrk:
14029
0
  case VPMINSWZrrkz:
14030
0
  case VPMINSWrm:
14031
0
  case VPMINSWrr:
14032
0
    return true;
14033
0
  }
14034
0
  return false;
14035
0
}
14036
14037
0
bool isVFNMSUB132PS(unsigned Opcode) {
14038
0
  switch (Opcode) {
14039
0
  case VFNMSUB132PSYm:
14040
0
  case VFNMSUB132PSYr:
14041
0
  case VFNMSUB132PSZ128m:
14042
0
  case VFNMSUB132PSZ128mb:
14043
0
  case VFNMSUB132PSZ128mbk:
14044
0
  case VFNMSUB132PSZ128mbkz:
14045
0
  case VFNMSUB132PSZ128mk:
14046
0
  case VFNMSUB132PSZ128mkz:
14047
0
  case VFNMSUB132PSZ128r:
14048
0
  case VFNMSUB132PSZ128rk:
14049
0
  case VFNMSUB132PSZ128rkz:
14050
0
  case VFNMSUB132PSZ256m:
14051
0
  case VFNMSUB132PSZ256mb:
14052
0
  case VFNMSUB132PSZ256mbk:
14053
0
  case VFNMSUB132PSZ256mbkz:
14054
0
  case VFNMSUB132PSZ256mk:
14055
0
  case VFNMSUB132PSZ256mkz:
14056
0
  case VFNMSUB132PSZ256r:
14057
0
  case VFNMSUB132PSZ256rk:
14058
0
  case VFNMSUB132PSZ256rkz:
14059
0
  case VFNMSUB132PSZm:
14060
0
  case VFNMSUB132PSZmb:
14061
0
  case VFNMSUB132PSZmbk:
14062
0
  case VFNMSUB132PSZmbkz:
14063
0
  case VFNMSUB132PSZmk:
14064
0
  case VFNMSUB132PSZmkz:
14065
0
  case VFNMSUB132PSZr:
14066
0
  case VFNMSUB132PSZrb:
14067
0
  case VFNMSUB132PSZrbk:
14068
0
  case VFNMSUB132PSZrbkz:
14069
0
  case VFNMSUB132PSZrk:
14070
0
  case VFNMSUB132PSZrkz:
14071
0
  case VFNMSUB132PSm:
14072
0
  case VFNMSUB132PSr:
14073
0
    return true;
14074
0
  }
14075
0
  return false;
14076
0
}
14077
14078
0
bool isVMOVAPS(unsigned Opcode) {
14079
0
  switch (Opcode) {
14080
0
  case VMOVAPSYmr:
14081
0
  case VMOVAPSYrm:
14082
0
  case VMOVAPSYrr:
14083
0
  case VMOVAPSYrr_REV:
14084
0
  case VMOVAPSZ128mr:
14085
0
  case VMOVAPSZ128mrk:
14086
0
  case VMOVAPSZ128rm:
14087
0
  case VMOVAPSZ128rmk:
14088
0
  case VMOVAPSZ128rmkz:
14089
0
  case VMOVAPSZ128rr:
14090
0
  case VMOVAPSZ128rr_REV:
14091
0
  case VMOVAPSZ128rrk:
14092
0
  case VMOVAPSZ128rrk_REV:
14093
0
  case VMOVAPSZ128rrkz:
14094
0
  case VMOVAPSZ128rrkz_REV:
14095
0
  case VMOVAPSZ256mr:
14096
0
  case VMOVAPSZ256mrk:
14097
0
  case VMOVAPSZ256rm:
14098
0
  case VMOVAPSZ256rmk:
14099
0
  case VMOVAPSZ256rmkz:
14100
0
  case VMOVAPSZ256rr:
14101
0
  case VMOVAPSZ256rr_REV:
14102
0
  case VMOVAPSZ256rrk:
14103
0
  case VMOVAPSZ256rrk_REV:
14104
0
  case VMOVAPSZ256rrkz:
14105
0
  case VMOVAPSZ256rrkz_REV:
14106
0
  case VMOVAPSZmr:
14107
0
  case VMOVAPSZmrk:
14108
0
  case VMOVAPSZrm:
14109
0
  case VMOVAPSZrmk:
14110
0
  case VMOVAPSZrmkz:
14111
0
  case VMOVAPSZrr:
14112
0
  case VMOVAPSZrr_REV:
14113
0
  case VMOVAPSZrrk:
14114
0
  case VMOVAPSZrrk_REV:
14115
0
  case VMOVAPSZrrkz:
14116
0
  case VMOVAPSZrrkz_REV:
14117
0
  case VMOVAPSmr:
14118
0
  case VMOVAPSrm:
14119
0
  case VMOVAPSrr:
14120
0
  case VMOVAPSrr_REV:
14121
0
    return true;
14122
0
  }
14123
0
  return false;
14124
0
}
14125
14126
0
bool isVPEXTRQ(unsigned Opcode) {
14127
0
  switch (Opcode) {
14128
0
  case VPEXTRQZmr:
14129
0
  case VPEXTRQZrr:
14130
0
  case VPEXTRQmr:
14131
0
  case VPEXTRQrr:
14132
0
    return true;
14133
0
  }
14134
0
  return false;
14135
0
}
14136
14137
0
bool isVSCALEFSH(unsigned Opcode) {
14138
0
  switch (Opcode) {
14139
0
  case VSCALEFSHZrm:
14140
0
  case VSCALEFSHZrmk:
14141
0
  case VSCALEFSHZrmkz:
14142
0
  case VSCALEFSHZrr:
14143
0
  case VSCALEFSHZrrb_Int:
14144
0
  case VSCALEFSHZrrb_Intk:
14145
0
  case VSCALEFSHZrrb_Intkz:
14146
0
  case VSCALEFSHZrrk:
14147
0
  case VSCALEFSHZrrkz:
14148
0
    return true;
14149
0
  }
14150
0
  return false;
14151
0
}
14152
14153
0
bool isVCVTPD2PS(unsigned Opcode) {
14154
0
  switch (Opcode) {
14155
0
  case VCVTPD2PSYrm:
14156
0
  case VCVTPD2PSYrr:
14157
0
  case VCVTPD2PSZ128rm:
14158
0
  case VCVTPD2PSZ128rmb:
14159
0
  case VCVTPD2PSZ128rmbk:
14160
0
  case VCVTPD2PSZ128rmbkz:
14161
0
  case VCVTPD2PSZ128rmk:
14162
0
  case VCVTPD2PSZ128rmkz:
14163
0
  case VCVTPD2PSZ128rr:
14164
0
  case VCVTPD2PSZ128rrk:
14165
0
  case VCVTPD2PSZ128rrkz:
14166
0
  case VCVTPD2PSZ256rm:
14167
0
  case VCVTPD2PSZ256rmb:
14168
0
  case VCVTPD2PSZ256rmbk:
14169
0
  case VCVTPD2PSZ256rmbkz:
14170
0
  case VCVTPD2PSZ256rmk:
14171
0
  case VCVTPD2PSZ256rmkz:
14172
0
  case VCVTPD2PSZ256rr:
14173
0
  case VCVTPD2PSZ256rrk:
14174
0
  case VCVTPD2PSZ256rrkz:
14175
0
  case VCVTPD2PSZrm:
14176
0
  case VCVTPD2PSZrmb:
14177
0
  case VCVTPD2PSZrmbk:
14178
0
  case VCVTPD2PSZrmbkz:
14179
0
  case VCVTPD2PSZrmk:
14180
0
  case VCVTPD2PSZrmkz:
14181
0
  case VCVTPD2PSZrr:
14182
0
  case VCVTPD2PSZrrb:
14183
0
  case VCVTPD2PSZrrbk:
14184
0
  case VCVTPD2PSZrrbkz:
14185
0
  case VCVTPD2PSZrrk:
14186
0
  case VCVTPD2PSZrrkz:
14187
0
  case VCVTPD2PSrm:
14188
0
  case VCVTPD2PSrr:
14189
0
    return true;
14190
0
  }
14191
0
  return false;
14192
0
}
14193
14194
0
bool isCLGI(unsigned Opcode) {
14195
0
  return Opcode == CLGI;
14196
0
}
14197
14198
0
bool isVAESDEC(unsigned Opcode) {
14199
0
  switch (Opcode) {
14200
0
  case VAESDECYrm:
14201
0
  case VAESDECYrr:
14202
0
  case VAESDECZ128rm:
14203
0
  case VAESDECZ128rr:
14204
0
  case VAESDECZ256rm:
14205
0
  case VAESDECZ256rr:
14206
0
  case VAESDECZrm:
14207
0
  case VAESDECZrr:
14208
0
  case VAESDECrm:
14209
0
  case VAESDECrr:
14210
0
    return true;
14211
0
  }
14212
0
  return false;
14213
0
}
14214
14215
0
bool isPFMUL(unsigned Opcode) {
14216
0
  switch (Opcode) {
14217
0
  case PFMULrm:
14218
0
  case PFMULrr:
14219
0
    return true;
14220
0
  }
14221
0
  return false;
14222
0
}
14223
14224
0
bool isMOVDIRI(unsigned Opcode) {
14225
0
  switch (Opcode) {
14226
0
  case MOVDIRI32:
14227
0
  case MOVDIRI32_EVEX:
14228
0
  case MOVDIRI64:
14229
0
  case MOVDIRI64_EVEX:
14230
0
    return true;
14231
0
  }
14232
0
  return false;
14233
0
}
14234
14235
0
bool isSHUFPS(unsigned Opcode) {
14236
0
  switch (Opcode) {
14237
0
  case SHUFPSrmi:
14238
0
  case SHUFPSrri:
14239
0
    return true;
14240
0
  }
14241
0
  return false;
14242
0
}
14243
14244
0
bool isVFNMSUB231SS(unsigned Opcode) {
14245
0
  switch (Opcode) {
14246
0
  case VFNMSUB231SSZm_Int:
14247
0
  case VFNMSUB231SSZm_Intk:
14248
0
  case VFNMSUB231SSZm_Intkz:
14249
0
  case VFNMSUB231SSZr_Int:
14250
0
  case VFNMSUB231SSZr_Intk:
14251
0
  case VFNMSUB231SSZr_Intkz:
14252
0
  case VFNMSUB231SSZrb_Int:
14253
0
  case VFNMSUB231SSZrb_Intk:
14254
0
  case VFNMSUB231SSZrb_Intkz:
14255
0
  case VFNMSUB231SSm_Int:
14256
0
  case VFNMSUB231SSr_Int:
14257
0
    return true;
14258
0
  }
14259
0
  return false;
14260
0
}
14261
14262
0
bool isVMWRITE(unsigned Opcode) {
14263
0
  switch (Opcode) {
14264
0
  case VMWRITE32rm:
14265
0
  case VMWRITE32rr:
14266
0
  case VMWRITE64rm:
14267
0
  case VMWRITE64rr:
14268
0
    return true;
14269
0
  }
14270
0
  return false;
14271
0
}
14272
14273
0
bool isVINSERTF128(unsigned Opcode) {
14274
0
  switch (Opcode) {
14275
0
  case VINSERTF128rm:
14276
0
  case VINSERTF128rr:
14277
0
    return true;
14278
0
  }
14279
0
  return false;
14280
0
}
14281
14282
0
bool isFISUBR(unsigned Opcode) {
14283
0
  switch (Opcode) {
14284
0
  case SUBR_FI16m:
14285
0
  case SUBR_FI32m:
14286
0
    return true;
14287
0
  }
14288
0
  return false;
14289
0
}
14290
14291
0
bool isVINSERTI32X4(unsigned Opcode) {
14292
0
  switch (Opcode) {
14293
0
  case VINSERTI32x4Z256rm:
14294
0
  case VINSERTI32x4Z256rmk:
14295
0
  case VINSERTI32x4Z256rmkz:
14296
0
  case VINSERTI32x4Z256rr:
14297
0
  case VINSERTI32x4Z256rrk:
14298
0
  case VINSERTI32x4Z256rrkz:
14299
0
  case VINSERTI32x4Zrm:
14300
0
  case VINSERTI32x4Zrmk:
14301
0
  case VINSERTI32x4Zrmkz:
14302
0
  case VINSERTI32x4Zrr:
14303
0
  case VINSERTI32x4Zrrk:
14304
0
  case VINSERTI32x4Zrrkz:
14305
0
    return true;
14306
0
  }
14307
0
  return false;
14308
0
}
14309
14310
0
bool isVPSLLDQ(unsigned Opcode) {
14311
0
  switch (Opcode) {
14312
0
  case VPSLLDQYri:
14313
0
  case VPSLLDQZ128mi:
14314
0
  case VPSLLDQZ128ri:
14315
0
  case VPSLLDQZ256mi:
14316
0
  case VPSLLDQZ256ri:
14317
0
  case VPSLLDQZmi:
14318
0
  case VPSLLDQZri:
14319
0
  case VPSLLDQri:
14320
0
    return true;
14321
0
  }
14322
0
  return false;
14323
0
}
14324
14325
0
bool isPOPCNT(unsigned Opcode) {
14326
0
  switch (Opcode) {
14327
0
  case POPCNT16rm:
14328
0
  case POPCNT16rr:
14329
0
  case POPCNT32rm:
14330
0
  case POPCNT32rr:
14331
0
  case POPCNT64rm:
14332
0
  case POPCNT64rr:
14333
0
    return true;
14334
0
  }
14335
0
  return false;
14336
0
}
14337
14338
0
bool isVXORPD(unsigned Opcode) {
14339
0
  switch (Opcode) {
14340
0
  case VXORPDYrm:
14341
0
  case VXORPDYrr:
14342
0
  case VXORPDZ128rm:
14343
0
  case VXORPDZ128rmb:
14344
0
  case VXORPDZ128rmbk:
14345
0
  case VXORPDZ128rmbkz:
14346
0
  case VXORPDZ128rmk:
14347
0
  case VXORPDZ128rmkz:
14348
0
  case VXORPDZ128rr:
14349
0
  case VXORPDZ128rrk:
14350
0
  case VXORPDZ128rrkz:
14351
0
  case VXORPDZ256rm:
14352
0
  case VXORPDZ256rmb:
14353
0
  case VXORPDZ256rmbk:
14354
0
  case VXORPDZ256rmbkz:
14355
0
  case VXORPDZ256rmk:
14356
0
  case VXORPDZ256rmkz:
14357
0
  case VXORPDZ256rr:
14358
0
  case VXORPDZ256rrk:
14359
0
  case VXORPDZ256rrkz:
14360
0
  case VXORPDZrm:
14361
0
  case VXORPDZrmb:
14362
0
  case VXORPDZrmbk:
14363
0
  case VXORPDZrmbkz:
14364
0
  case VXORPDZrmk:
14365
0
  case VXORPDZrmkz:
14366
0
  case VXORPDZrr:
14367
0
  case VXORPDZrrk:
14368
0
  case VXORPDZrrkz:
14369
0
  case VXORPDrm:
14370
0
  case VXORPDrr:
14371
0
    return true;
14372
0
  }
14373
0
  return false;
14374
0
}
14375
14376
0
bool isXLATB(unsigned Opcode) {
14377
0
  return Opcode == XLAT;
14378
0
}
14379
14380
0
bool isDIV(unsigned Opcode) {
14381
0
  switch (Opcode) {
14382
0
  case DIV16m:
14383
0
  case DIV16m_EVEX:
14384
0
  case DIV16m_NF:
14385
0
  case DIV16r:
14386
0
  case DIV16r_EVEX:
14387
0
  case DIV16r_NF:
14388
0
  case DIV32m:
14389
0
  case DIV32m_EVEX:
14390
0
  case DIV32m_NF:
14391
0
  case DIV32r:
14392
0
  case DIV32r_EVEX:
14393
0
  case DIV32r_NF:
14394
0
  case DIV64m:
14395
0
  case DIV64m_EVEX:
14396
0
  case DIV64m_NF:
14397
0
  case DIV64r:
14398
0
  case DIV64r_EVEX:
14399
0
  case DIV64r_NF:
14400
0
  case DIV8m:
14401
0
  case DIV8m_EVEX:
14402
0
  case DIV8m_NF:
14403
0
  case DIV8r:
14404
0
  case DIV8r_EVEX:
14405
0
  case DIV8r_NF:
14406
0
    return true;
14407
0
  }
14408
0
  return false;
14409
0
}
14410
14411
0
bool isVPSHLDVQ(unsigned Opcode) {
14412
0
  switch (Opcode) {
14413
0
  case VPSHLDVQZ128m:
14414
0
  case VPSHLDVQZ128mb:
14415
0
  case VPSHLDVQZ128mbk:
14416
0
  case VPSHLDVQZ128mbkz:
14417
0
  case VPSHLDVQZ128mk:
14418
0
  case VPSHLDVQZ128mkz:
14419
0
  case VPSHLDVQZ128r:
14420
0
  case VPSHLDVQZ128rk:
14421
0
  case VPSHLDVQZ128rkz:
14422
0
  case VPSHLDVQZ256m:
14423
0
  case VPSHLDVQZ256mb:
14424
0
  case VPSHLDVQZ256mbk:
14425
0
  case VPSHLDVQZ256mbkz:
14426
0
  case VPSHLDVQZ256mk:
14427
0
  case VPSHLDVQZ256mkz:
14428
0
  case VPSHLDVQZ256r:
14429
0
  case VPSHLDVQZ256rk:
14430
0
  case VPSHLDVQZ256rkz:
14431
0
  case VPSHLDVQZm:
14432
0
  case VPSHLDVQZmb:
14433
0
  case VPSHLDVQZmbk:
14434
0
  case VPSHLDVQZmbkz:
14435
0
  case VPSHLDVQZmk:
14436
0
  case VPSHLDVQZmkz:
14437
0
  case VPSHLDVQZr:
14438
0
  case VPSHLDVQZrk:
14439
0
  case VPSHLDVQZrkz:
14440
0
    return true;
14441
0
  }
14442
0
  return false;
14443
0
}
14444
14445
0
bool isMOVDDUP(unsigned Opcode) {
14446
0
  switch (Opcode) {
14447
0
  case MOVDDUPrm:
14448
0
  case MOVDDUPrr:
14449
0
    return true;
14450
0
  }
14451
0
  return false;
14452
0
}
14453
14454
0
bool isVMOVDQU64(unsigned Opcode) {
14455
0
  switch (Opcode) {
14456
0
  case VMOVDQU64Z128mr:
14457
0
  case VMOVDQU64Z128mrk:
14458
0
  case VMOVDQU64Z128rm:
14459
0
  case VMOVDQU64Z128rmk:
14460
0
  case VMOVDQU64Z128rmkz:
14461
0
  case VMOVDQU64Z128rr:
14462
0
  case VMOVDQU64Z128rr_REV:
14463
0
  case VMOVDQU64Z128rrk:
14464
0
  case VMOVDQU64Z128rrk_REV:
14465
0
  case VMOVDQU64Z128rrkz:
14466
0
  case VMOVDQU64Z128rrkz_REV:
14467
0
  case VMOVDQU64Z256mr:
14468
0
  case VMOVDQU64Z256mrk:
14469
0
  case VMOVDQU64Z256rm:
14470
0
  case VMOVDQU64Z256rmk:
14471
0
  case VMOVDQU64Z256rmkz:
14472
0
  case VMOVDQU64Z256rr:
14473
0
  case VMOVDQU64Z256rr_REV:
14474
0
  case VMOVDQU64Z256rrk:
14475
0
  case VMOVDQU64Z256rrk_REV:
14476
0
  case VMOVDQU64Z256rrkz:
14477
0
  case VMOVDQU64Z256rrkz_REV:
14478
0
  case VMOVDQU64Zmr:
14479
0
  case VMOVDQU64Zmrk:
14480
0
  case VMOVDQU64Zrm:
14481
0
  case VMOVDQU64Zrmk:
14482
0
  case VMOVDQU64Zrmkz:
14483
0
  case VMOVDQU64Zrr:
14484
0
  case VMOVDQU64Zrr_REV:
14485
0
  case VMOVDQU64Zrrk:
14486
0
  case VMOVDQU64Zrrk_REV:
14487
0
  case VMOVDQU64Zrrkz:
14488
0
  case VMOVDQU64Zrrkz_REV:
14489
0
    return true;
14490
0
  }
14491
0
  return false;
14492
0
}
14493
14494
0
bool isVPCOMPRESSQ(unsigned Opcode) {
14495
0
  switch (Opcode) {
14496
0
  case VPCOMPRESSQZ128mr:
14497
0
  case VPCOMPRESSQZ128mrk:
14498
0
  case VPCOMPRESSQZ128rr:
14499
0
  case VPCOMPRESSQZ128rrk:
14500
0
  case VPCOMPRESSQZ128rrkz:
14501
0
  case VPCOMPRESSQZ256mr:
14502
0
  case VPCOMPRESSQZ256mrk:
14503
0
  case VPCOMPRESSQZ256rr:
14504
0
  case VPCOMPRESSQZ256rrk:
14505
0
  case VPCOMPRESSQZ256rrkz:
14506
0
  case VPCOMPRESSQZmr:
14507
0
  case VPCOMPRESSQZmrk:
14508
0
  case VPCOMPRESSQZrr:
14509
0
  case VPCOMPRESSQZrrk:
14510
0
  case VPCOMPRESSQZrrkz:
14511
0
    return true;
14512
0
  }
14513
0
  return false;
14514
0
}
14515
14516
0
bool isVFMSUBADD132PD(unsigned Opcode) {
14517
0
  switch (Opcode) {
14518
0
  case VFMSUBADD132PDYm:
14519
0
  case VFMSUBADD132PDYr:
14520
0
  case VFMSUBADD132PDZ128m:
14521
0
  case VFMSUBADD132PDZ128mb:
14522
0
  case VFMSUBADD132PDZ128mbk:
14523
0
  case VFMSUBADD132PDZ128mbkz:
14524
0
  case VFMSUBADD132PDZ128mk:
14525
0
  case VFMSUBADD132PDZ128mkz:
14526
0
  case VFMSUBADD132PDZ128r:
14527
0
  case VFMSUBADD132PDZ128rk:
14528
0
  case VFMSUBADD132PDZ128rkz:
14529
0
  case VFMSUBADD132PDZ256m:
14530
0
  case VFMSUBADD132PDZ256mb:
14531
0
  case VFMSUBADD132PDZ256mbk:
14532
0
  case VFMSUBADD132PDZ256mbkz:
14533
0
  case VFMSUBADD132PDZ256mk:
14534
0
  case VFMSUBADD132PDZ256mkz:
14535
0
  case VFMSUBADD132PDZ256r:
14536
0
  case VFMSUBADD132PDZ256rk:
14537
0
  case VFMSUBADD132PDZ256rkz:
14538
0
  case VFMSUBADD132PDZm:
14539
0
  case VFMSUBADD132PDZmb:
14540
0
  case VFMSUBADD132PDZmbk:
14541
0
  case VFMSUBADD132PDZmbkz:
14542
0
  case VFMSUBADD132PDZmk:
14543
0
  case VFMSUBADD132PDZmkz:
14544
0
  case VFMSUBADD132PDZr:
14545
0
  case VFMSUBADD132PDZrb:
14546
0
  case VFMSUBADD132PDZrbk:
14547
0
  case VFMSUBADD132PDZrbkz:
14548
0
  case VFMSUBADD132PDZrk:
14549
0
  case VFMSUBADD132PDZrkz:
14550
0
  case VFMSUBADD132PDm:
14551
0
  case VFMSUBADD132PDr:
14552
0
    return true;
14553
0
  }
14554
0
  return false;
14555
0
}
14556
14557
0
bool isADDSD(unsigned Opcode) {
14558
0
  switch (Opcode) {
14559
0
  case ADDSDrm_Int:
14560
0
  case ADDSDrr_Int:
14561
0
    return true;
14562
0
  }
14563
0
  return false;
14564
0
}
14565
14566
0
bool isBLENDPD(unsigned Opcode) {
14567
0
  switch (Opcode) {
14568
0
  case BLENDPDrmi:
14569
0
  case BLENDPDrri:
14570
0
    return true;
14571
0
  }
14572
0
  return false;
14573
0
}
14574
14575
0
bool isVPERMILPD(unsigned Opcode) {
14576
0
  switch (Opcode) {
14577
0
  case VPERMILPDYmi:
14578
0
  case VPERMILPDYri:
14579
0
  case VPERMILPDYrm:
14580
0
  case VPERMILPDYrr:
14581
0
  case VPERMILPDZ128mbi:
14582
0
  case VPERMILPDZ128mbik:
14583
0
  case VPERMILPDZ128mbikz:
14584
0
  case VPERMILPDZ128mi:
14585
0
  case VPERMILPDZ128mik:
14586
0
  case VPERMILPDZ128mikz:
14587
0
  case VPERMILPDZ128ri:
14588
0
  case VPERMILPDZ128rik:
14589
0
  case VPERMILPDZ128rikz:
14590
0
  case VPERMILPDZ128rm:
14591
0
  case VPERMILPDZ128rmb:
14592
0
  case VPERMILPDZ128rmbk:
14593
0
  case VPERMILPDZ128rmbkz:
14594
0
  case VPERMILPDZ128rmk:
14595
0
  case VPERMILPDZ128rmkz:
14596
0
  case VPERMILPDZ128rr:
14597
0
  case VPERMILPDZ128rrk:
14598
0
  case VPERMILPDZ128rrkz:
14599
0
  case VPERMILPDZ256mbi:
14600
0
  case VPERMILPDZ256mbik:
14601
0
  case VPERMILPDZ256mbikz:
14602
0
  case VPERMILPDZ256mi:
14603
0
  case VPERMILPDZ256mik:
14604
0
  case VPERMILPDZ256mikz:
14605
0
  case VPERMILPDZ256ri:
14606
0
  case VPERMILPDZ256rik:
14607
0
  case VPERMILPDZ256rikz:
14608
0
  case VPERMILPDZ256rm:
14609
0
  case VPERMILPDZ256rmb:
14610
0
  case VPERMILPDZ256rmbk:
14611
0
  case VPERMILPDZ256rmbkz:
14612
0
  case VPERMILPDZ256rmk:
14613
0
  case VPERMILPDZ256rmkz:
14614
0
  case VPERMILPDZ256rr:
14615
0
  case VPERMILPDZ256rrk:
14616
0
  case VPERMILPDZ256rrkz:
14617
0
  case VPERMILPDZmbi:
14618
0
  case VPERMILPDZmbik:
14619
0
  case VPERMILPDZmbikz:
14620
0
  case VPERMILPDZmi:
14621
0
  case VPERMILPDZmik:
14622
0
  case VPERMILPDZmikz:
14623
0
  case VPERMILPDZri:
14624
0
  case VPERMILPDZrik:
14625
0
  case VPERMILPDZrikz:
14626
0
  case VPERMILPDZrm:
14627
0
  case VPERMILPDZrmb:
14628
0
  case VPERMILPDZrmbk:
14629
0
  case VPERMILPDZrmbkz:
14630
0
  case VPERMILPDZrmk:
14631
0
  case VPERMILPDZrmkz:
14632
0
  case VPERMILPDZrr:
14633
0
  case VPERMILPDZrrk:
14634
0
  case VPERMILPDZrrkz:
14635
0
  case VPERMILPDmi:
14636
0
  case VPERMILPDri:
14637
0
  case VPERMILPDrm:
14638
0
  case VPERMILPDrr:
14639
0
    return true;
14640
0
  }
14641
0
  return false;
14642
0
}
14643
14644
0
bool isPMADDUBSW(unsigned Opcode) {
14645
0
  switch (Opcode) {
14646
0
  case MMX_PMADDUBSWrm:
14647
0
  case MMX_PMADDUBSWrr:
14648
0
  case PMADDUBSWrm:
14649
0
  case PMADDUBSWrr:
14650
0
    return true;
14651
0
  }
14652
0
  return false;
14653
0
}
14654
14655
0
bool isPOPFD(unsigned Opcode) {
14656
0
  return Opcode == POPF32;
14657
0
}
14658
14659
0
bool isCMPSW(unsigned Opcode) {
14660
0
  return Opcode == CMPSW;
14661
0
}
14662
14663
0
bool isLDMXCSR(unsigned Opcode) {
14664
0
  return Opcode == LDMXCSR;
14665
0
}
14666
14667
0
bool isVMULPS(unsigned Opcode) {
14668
0
  switch (Opcode) {
14669
0
  case VMULPSYrm:
14670
0
  case VMULPSYrr:
14671
0
  case VMULPSZ128rm:
14672
0
  case VMULPSZ128rmb:
14673
0
  case VMULPSZ128rmbk:
14674
0
  case VMULPSZ128rmbkz:
14675
0
  case VMULPSZ128rmk:
14676
0
  case VMULPSZ128rmkz:
14677
0
  case VMULPSZ128rr:
14678
0
  case VMULPSZ128rrk:
14679
0
  case VMULPSZ128rrkz:
14680
0
  case VMULPSZ256rm:
14681
0
  case VMULPSZ256rmb:
14682
0
  case VMULPSZ256rmbk:
14683
0
  case VMULPSZ256rmbkz:
14684
0
  case VMULPSZ256rmk:
14685
0
  case VMULPSZ256rmkz:
14686
0
  case VMULPSZ256rr:
14687
0
  case VMULPSZ256rrk:
14688
0
  case VMULPSZ256rrkz:
14689
0
  case VMULPSZrm:
14690
0
  case VMULPSZrmb:
14691
0
  case VMULPSZrmbk:
14692
0
  case VMULPSZrmbkz:
14693
0
  case VMULPSZrmk:
14694
0
  case VMULPSZrmkz:
14695
0
  case VMULPSZrr:
14696
0
  case VMULPSZrrb:
14697
0
  case VMULPSZrrbk:
14698
0
  case VMULPSZrrbkz:
14699
0
  case VMULPSZrrk:
14700
0
  case VMULPSZrrkz:
14701
0
  case VMULPSrm:
14702
0
  case VMULPSrr:
14703
0
    return true;
14704
0
  }
14705
0
  return false;
14706
0
}
14707
14708
0
bool isVROUNDSD(unsigned Opcode) {
14709
0
  switch (Opcode) {
14710
0
  case VROUNDSDm_Int:
14711
0
  case VROUNDSDr_Int:
14712
0
    return true;
14713
0
  }
14714
0
  return false;
14715
0
}
14716
14717
0
bool isVFMADD132PD(unsigned Opcode) {
14718
0
  switch (Opcode) {
14719
0
  case VFMADD132PDYm:
14720
0
  case VFMADD132PDYr:
14721
0
  case VFMADD132PDZ128m:
14722
0
  case VFMADD132PDZ128mb:
14723
0
  case VFMADD132PDZ128mbk:
14724
0
  case VFMADD132PDZ128mbkz:
14725
0
  case VFMADD132PDZ128mk:
14726
0
  case VFMADD132PDZ128mkz:
14727
0
  case VFMADD132PDZ128r:
14728
0
  case VFMADD132PDZ128rk:
14729
0
  case VFMADD132PDZ128rkz:
14730
0
  case VFMADD132PDZ256m:
14731
0
  case VFMADD132PDZ256mb:
14732
0
  case VFMADD132PDZ256mbk:
14733
0
  case VFMADD132PDZ256mbkz:
14734
0
  case VFMADD132PDZ256mk:
14735
0
  case VFMADD132PDZ256mkz:
14736
0
  case VFMADD132PDZ256r:
14737
0
  case VFMADD132PDZ256rk:
14738
0
  case VFMADD132PDZ256rkz:
14739
0
  case VFMADD132PDZm:
14740
0
  case VFMADD132PDZmb:
14741
0
  case VFMADD132PDZmbk:
14742
0
  case VFMADD132PDZmbkz:
14743
0
  case VFMADD132PDZmk:
14744
0
  case VFMADD132PDZmkz:
14745
0
  case VFMADD132PDZr:
14746
0
  case VFMADD132PDZrb:
14747
0
  case VFMADD132PDZrbk:
14748
0
  case VFMADD132PDZrbkz:
14749
0
  case VFMADD132PDZrk:
14750
0
  case VFMADD132PDZrkz:
14751
0
  case VFMADD132PDm:
14752
0
  case VFMADD132PDr:
14753
0
    return true;
14754
0
  }
14755
0
  return false;
14756
0
}
14757
14758
0
bool isVPANDQ(unsigned Opcode) {
14759
0
  switch (Opcode) {
14760
0
  case VPANDQZ128rm:
14761
0
  case VPANDQZ128rmb:
14762
0
  case VPANDQZ128rmbk:
14763
0
  case VPANDQZ128rmbkz:
14764
0
  case VPANDQZ128rmk:
14765
0
  case VPANDQZ128rmkz:
14766
0
  case VPANDQZ128rr:
14767
0
  case VPANDQZ128rrk:
14768
0
  case VPANDQZ128rrkz:
14769
0
  case VPANDQZ256rm:
14770
0
  case VPANDQZ256rmb:
14771
0
  case VPANDQZ256rmbk:
14772
0
  case VPANDQZ256rmbkz:
14773
0
  case VPANDQZ256rmk:
14774
0
  case VPANDQZ256rmkz:
14775
0
  case VPANDQZ256rr:
14776
0
  case VPANDQZ256rrk:
14777
0
  case VPANDQZ256rrkz:
14778
0
  case VPANDQZrm:
14779
0
  case VPANDQZrmb:
14780
0
  case VPANDQZrmbk:
14781
0
  case VPANDQZrmbkz:
14782
0
  case VPANDQZrmk:
14783
0
  case VPANDQZrmkz:
14784
0
  case VPANDQZrr:
14785
0
  case VPANDQZrrk:
14786
0
  case VPANDQZrrkz:
14787
0
    return true;
14788
0
  }
14789
0
  return false;
14790
0
}
14791
14792
0
bool isVPSRAQ(unsigned Opcode) {
14793
0
  switch (Opcode) {
14794
0
  case VPSRAQZ128mbi:
14795
0
  case VPSRAQZ128mbik:
14796
0
  case VPSRAQZ128mbikz:
14797
0
  case VPSRAQZ128mi:
14798
0
  case VPSRAQZ128mik:
14799
0
  case VPSRAQZ128mikz:
14800
0
  case VPSRAQZ128ri:
14801
0
  case VPSRAQZ128rik:
14802
0
  case VPSRAQZ128rikz:
14803
0
  case VPSRAQZ128rm:
14804
0
  case VPSRAQZ128rmk:
14805
0
  case VPSRAQZ128rmkz:
14806
0
  case VPSRAQZ128rr:
14807
0
  case VPSRAQZ128rrk:
14808
0
  case VPSRAQZ128rrkz:
14809
0
  case VPSRAQZ256mbi:
14810
0
  case VPSRAQZ256mbik:
14811
0
  case VPSRAQZ256mbikz:
14812
0
  case VPSRAQZ256mi:
14813
0
  case VPSRAQZ256mik:
14814
0
  case VPSRAQZ256mikz:
14815
0
  case VPSRAQZ256ri:
14816
0
  case VPSRAQZ256rik:
14817
0
  case VPSRAQZ256rikz:
14818
0
  case VPSRAQZ256rm:
14819
0
  case VPSRAQZ256rmk:
14820
0
  case VPSRAQZ256rmkz:
14821
0
  case VPSRAQZ256rr:
14822
0
  case VPSRAQZ256rrk:
14823
0
  case VPSRAQZ256rrkz:
14824
0
  case VPSRAQZmbi:
14825
0
  case VPSRAQZmbik:
14826
0
  case VPSRAQZmbikz:
14827
0
  case VPSRAQZmi:
14828
0
  case VPSRAQZmik:
14829
0
  case VPSRAQZmikz:
14830
0
  case VPSRAQZri:
14831
0
  case VPSRAQZrik:
14832
0
  case VPSRAQZrikz:
14833
0
  case VPSRAQZrm:
14834
0
  case VPSRAQZrmk:
14835
0
  case VPSRAQZrmkz:
14836
0
  case VPSRAQZrr:
14837
0
  case VPSRAQZrrk:
14838
0
  case VPSRAQZrrkz:
14839
0
    return true;
14840
0
  }
14841
0
  return false;
14842
0
}
14843
14844
0
bool isVCOMISD(unsigned Opcode) {
14845
0
  switch (Opcode) {
14846
0
  case VCOMISDZrm:
14847
0
  case VCOMISDZrr:
14848
0
  case VCOMISDZrrb:
14849
0
  case VCOMISDrm:
14850
0
  case VCOMISDrr:
14851
0
    return true;
14852
0
  }
14853
0
  return false;
14854
0
}
14855
14856
0
bool isFFREEP(unsigned Opcode) {
14857
0
  return Opcode == FFREEP;
14858
0
}
14859
14860
0
bool isVFNMADD213PD(unsigned Opcode) {
14861
0
  switch (Opcode) {
14862
0
  case VFNMADD213PDYm:
14863
0
  case VFNMADD213PDYr:
14864
0
  case VFNMADD213PDZ128m:
14865
0
  case VFNMADD213PDZ128mb:
14866
0
  case VFNMADD213PDZ128mbk:
14867
0
  case VFNMADD213PDZ128mbkz:
14868
0
  case VFNMADD213PDZ128mk:
14869
0
  case VFNMADD213PDZ128mkz:
14870
0
  case VFNMADD213PDZ128r:
14871
0
  case VFNMADD213PDZ128rk:
14872
0
  case VFNMADD213PDZ128rkz:
14873
0
  case VFNMADD213PDZ256m:
14874
0
  case VFNMADD213PDZ256mb:
14875
0
  case VFNMADD213PDZ256mbk:
14876
0
  case VFNMADD213PDZ256mbkz:
14877
0
  case VFNMADD213PDZ256mk:
14878
0
  case VFNMADD213PDZ256mkz:
14879
0
  case VFNMADD213PDZ256r:
14880
0
  case VFNMADD213PDZ256rk:
14881
0
  case VFNMADD213PDZ256rkz:
14882
0
  case VFNMADD213PDZm:
14883
0
  case VFNMADD213PDZmb:
14884
0
  case VFNMADD213PDZmbk:
14885
0
  case VFNMADD213PDZmbkz:
14886
0
  case VFNMADD213PDZmk:
14887
0
  case VFNMADD213PDZmkz:
14888
0
  case VFNMADD213PDZr:
14889
0
  case VFNMADD213PDZrb:
14890
0
  case VFNMADD213PDZrbk:
14891
0
  case VFNMADD213PDZrbkz:
14892
0
  case VFNMADD213PDZrk:
14893
0
  case VFNMADD213PDZrkz:
14894
0
  case VFNMADD213PDm:
14895
0
  case VFNMADD213PDr:
14896
0
    return true;
14897
0
  }
14898
0
  return false;
14899
0
}
14900
14901
0
bool isVCMPPD(unsigned Opcode) {
14902
0
  switch (Opcode) {
14903
0
  case VCMPPDYrmi:
14904
0
  case VCMPPDYrri:
14905
0
  case VCMPPDZ128rmbi:
14906
0
  case VCMPPDZ128rmbik:
14907
0
  case VCMPPDZ128rmi:
14908
0
  case VCMPPDZ128rmik:
14909
0
  case VCMPPDZ128rri:
14910
0
  case VCMPPDZ128rrik:
14911
0
  case VCMPPDZ256rmbi:
14912
0
  case VCMPPDZ256rmbik:
14913
0
  case VCMPPDZ256rmi:
14914
0
  case VCMPPDZ256rmik:
14915
0
  case VCMPPDZ256rri:
14916
0
  case VCMPPDZ256rrik:
14917
0
  case VCMPPDZrmbi:
14918
0
  case VCMPPDZrmbik:
14919
0
  case VCMPPDZrmi:
14920
0
  case VCMPPDZrmik:
14921
0
  case VCMPPDZrri:
14922
0
  case VCMPPDZrrib:
14923
0
  case VCMPPDZrribk:
14924
0
  case VCMPPDZrrik:
14925
0
  case VCMPPDrmi:
14926
0
  case VCMPPDrri:
14927
0
    return true;
14928
0
  }
14929
0
  return false;
14930
0
}
14931
14932
0
bool isVFNMSUB132PH(unsigned Opcode) {
14933
0
  switch (Opcode) {
14934
0
  case VFNMSUB132PHZ128m:
14935
0
  case VFNMSUB132PHZ128mb:
14936
0
  case VFNMSUB132PHZ128mbk:
14937
0
  case VFNMSUB132PHZ128mbkz:
14938
0
  case VFNMSUB132PHZ128mk:
14939
0
  case VFNMSUB132PHZ128mkz:
14940
0
  case VFNMSUB132PHZ128r:
14941
0
  case VFNMSUB132PHZ128rk:
14942
0
  case VFNMSUB132PHZ128rkz:
14943
0
  case VFNMSUB132PHZ256m:
14944
0
  case VFNMSUB132PHZ256mb:
14945
0
  case VFNMSUB132PHZ256mbk:
14946
0
  case VFNMSUB132PHZ256mbkz:
14947
0
  case VFNMSUB132PHZ256mk:
14948
0
  case VFNMSUB132PHZ256mkz:
14949
0
  case VFNMSUB132PHZ256r:
14950
0
  case VFNMSUB132PHZ256rk:
14951
0
  case VFNMSUB132PHZ256rkz:
14952
0
  case VFNMSUB132PHZm:
14953
0
  case VFNMSUB132PHZmb:
14954
0
  case VFNMSUB132PHZmbk:
14955
0
  case VFNMSUB132PHZmbkz:
14956
0
  case VFNMSUB132PHZmk:
14957
0
  case VFNMSUB132PHZmkz:
14958
0
  case VFNMSUB132PHZr:
14959
0
  case VFNMSUB132PHZrb:
14960
0
  case VFNMSUB132PHZrbk:
14961
0
  case VFNMSUB132PHZrbkz:
14962
0
  case VFNMSUB132PHZrk:
14963
0
  case VFNMSUB132PHZrkz:
14964
0
    return true;
14965
0
  }
14966
0
  return false;
14967
0
}
14968
14969
0
bool isVPHADDBW(unsigned Opcode) {
14970
0
  switch (Opcode) {
14971
0
  case VPHADDBWrm:
14972
0
  case VPHADDBWrr:
14973
0
    return true;
14974
0
  }
14975
0
  return false;
14976
0
}
14977
14978
0
bool isVPPERM(unsigned Opcode) {
14979
0
  switch (Opcode) {
14980
0
  case VPPERMrmr:
14981
0
  case VPPERMrrm:
14982
0
  case VPPERMrrr:
14983
0
  case VPPERMrrr_REV:
14984
0
    return true;
14985
0
  }
14986
0
  return false;
14987
0
}
14988
14989
0
bool isVCVTPS2PD(unsigned Opcode) {
14990
0
  switch (Opcode) {
14991
0
  case VCVTPS2PDYrm:
14992
0
  case VCVTPS2PDYrr:
14993
0
  case VCVTPS2PDZ128rm:
14994
0
  case VCVTPS2PDZ128rmb:
14995
0
  case VCVTPS2PDZ128rmbk:
14996
0
  case VCVTPS2PDZ128rmbkz:
14997
0
  case VCVTPS2PDZ128rmk:
14998
0
  case VCVTPS2PDZ128rmkz:
14999
0
  case VCVTPS2PDZ128rr:
15000
0
  case VCVTPS2PDZ128rrk:
15001
0
  case VCVTPS2PDZ128rrkz:
15002
0
  case VCVTPS2PDZ256rm:
15003
0
  case VCVTPS2PDZ256rmb:
15004
0
  case VCVTPS2PDZ256rmbk:
15005
0
  case VCVTPS2PDZ256rmbkz:
15006
0
  case VCVTPS2PDZ256rmk:
15007
0
  case VCVTPS2PDZ256rmkz:
15008
0
  case VCVTPS2PDZ256rr:
15009
0
  case VCVTPS2PDZ256rrk:
15010
0
  case VCVTPS2PDZ256rrkz:
15011
0
  case VCVTPS2PDZrm:
15012
0
  case VCVTPS2PDZrmb:
15013
0
  case VCVTPS2PDZrmbk:
15014
0
  case VCVTPS2PDZrmbkz:
15015
0
  case VCVTPS2PDZrmk:
15016
0
  case VCVTPS2PDZrmkz:
15017
0
  case VCVTPS2PDZrr:
15018
0
  case VCVTPS2PDZrrb:
15019
0
  case VCVTPS2PDZrrbk:
15020
0
  case VCVTPS2PDZrrbkz:
15021
0
  case VCVTPS2PDZrrk:
15022
0
  case VCVTPS2PDZrrkz:
15023
0
  case VCVTPS2PDrm:
15024
0
  case VCVTPS2PDrr:
15025
0
    return true;
15026
0
  }
15027
0
  return false;
15028
0
}
15029
15030
0
bool isCBW(unsigned Opcode) {
15031
0
  return Opcode == CBW;
15032
0
}
15033
15034
0
bool isVMOVUPS(unsigned Opcode) {
15035
0
  switch (Opcode) {
15036
0
  case VMOVUPSYmr:
15037
0
  case VMOVUPSYrm:
15038
0
  case VMOVUPSYrr:
15039
0
  case VMOVUPSYrr_REV:
15040
0
  case VMOVUPSZ128mr:
15041
0
  case VMOVUPSZ128mrk:
15042
0
  case VMOVUPSZ128rm:
15043
0
  case VMOVUPSZ128rmk:
15044
0
  case VMOVUPSZ128rmkz:
15045
0
  case VMOVUPSZ128rr:
15046
0
  case VMOVUPSZ128rr_REV:
15047
0
  case VMOVUPSZ128rrk:
15048
0
  case VMOVUPSZ128rrk_REV:
15049
0
  case VMOVUPSZ128rrkz:
15050
0
  case VMOVUPSZ128rrkz_REV:
15051
0
  case VMOVUPSZ256mr:
15052
0
  case VMOVUPSZ256mrk:
15053
0
  case VMOVUPSZ256rm:
15054
0
  case VMOVUPSZ256rmk:
15055
0
  case VMOVUPSZ256rmkz:
15056
0
  case VMOVUPSZ256rr:
15057
0
  case VMOVUPSZ256rr_REV:
15058
0
  case VMOVUPSZ256rrk:
15059
0
  case VMOVUPSZ256rrk_REV:
15060
0
  case VMOVUPSZ256rrkz:
15061
0
  case VMOVUPSZ256rrkz_REV:
15062
0
  case VMOVUPSZmr:
15063
0
  case VMOVUPSZmrk:
15064
0
  case VMOVUPSZrm:
15065
0
  case VMOVUPSZrmk:
15066
0
  case VMOVUPSZrmkz:
15067
0
  case VMOVUPSZrr:
15068
0
  case VMOVUPSZrr_REV:
15069
0
  case VMOVUPSZrrk:
15070
0
  case VMOVUPSZrrk_REV:
15071
0
  case VMOVUPSZrrkz:
15072
0
  case VMOVUPSZrrkz_REV:
15073
0
  case VMOVUPSmr:
15074
0
  case VMOVUPSrm:
15075
0
  case VMOVUPSrr:
15076
0
  case VMOVUPSrr_REV:
15077
0
    return true;
15078
0
  }
15079
0
  return false;
15080
0
}
15081
15082
0
bool isVPMAXUQ(unsigned Opcode) {
15083
0
  switch (Opcode) {
15084
0
  case VPMAXUQZ128rm:
15085
0
  case VPMAXUQZ128rmb:
15086
0
  case VPMAXUQZ128rmbk:
15087
0
  case VPMAXUQZ128rmbkz:
15088
0
  case VPMAXUQZ128rmk:
15089
0
  case VPMAXUQZ128rmkz:
15090
0
  case VPMAXUQZ128rr:
15091
0
  case VPMAXUQZ128rrk:
15092
0
  case VPMAXUQZ128rrkz:
15093
0
  case VPMAXUQZ256rm:
15094
0
  case VPMAXUQZ256rmb:
15095
0
  case VPMAXUQZ256rmbk:
15096
0
  case VPMAXUQZ256rmbkz:
15097
0
  case VPMAXUQZ256rmk:
15098
0
  case VPMAXUQZ256rmkz:
15099
0
  case VPMAXUQZ256rr:
15100
0
  case VPMAXUQZ256rrk:
15101
0
  case VPMAXUQZ256rrkz:
15102
0
  case VPMAXUQZrm:
15103
0
  case VPMAXUQZrmb:
15104
0
  case VPMAXUQZrmbk:
15105
0
  case VPMAXUQZrmbkz:
15106
0
  case VPMAXUQZrmk:
15107
0
  case VPMAXUQZrmkz:
15108
0
  case VPMAXUQZrr:
15109
0
  case VPMAXUQZrrk:
15110
0
  case VPMAXUQZrrkz:
15111
0
    return true;
15112
0
  }
15113
0
  return false;
15114
0
}
15115
15116
0
bool isWRSSQ(unsigned Opcode) {
15117
0
  switch (Opcode) {
15118
0
  case WRSSQ:
15119
0
  case WRSSQ_EVEX:
15120
0
    return true;
15121
0
  }
15122
0
  return false;
15123
0
}
15124
15125
0
bool isPACKUSDW(unsigned Opcode) {
15126
0
  switch (Opcode) {
15127
0
  case PACKUSDWrm:
15128
0
  case PACKUSDWrr:
15129
0
    return true;
15130
0
  }
15131
0
  return false;
15132
0
}
15133
15134
0
bool isXBEGIN(unsigned Opcode) {
15135
0
  switch (Opcode) {
15136
0
  case XBEGIN_2:
15137
0
  case XBEGIN_4:
15138
0
    return true;
15139
0
  }
15140
0
  return false;
15141
0
}
15142
15143
0
bool isVCVTPD2UQQ(unsigned Opcode) {
15144
0
  switch (Opcode) {
15145
0
  case VCVTPD2UQQZ128rm:
15146
0
  case VCVTPD2UQQZ128rmb:
15147
0
  case VCVTPD2UQQZ128rmbk:
15148
0
  case VCVTPD2UQQZ128rmbkz:
15149
0
  case VCVTPD2UQQZ128rmk:
15150
0
  case VCVTPD2UQQZ128rmkz:
15151
0
  case VCVTPD2UQQZ128rr:
15152
0
  case VCVTPD2UQQZ128rrk:
15153
0
  case VCVTPD2UQQZ128rrkz:
15154
0
  case VCVTPD2UQQZ256rm:
15155
0
  case VCVTPD2UQQZ256rmb:
15156
0
  case VCVTPD2UQQZ256rmbk:
15157
0
  case VCVTPD2UQQZ256rmbkz:
15158
0
  case VCVTPD2UQQZ256rmk:
15159
0
  case VCVTPD2UQQZ256rmkz:
15160
0
  case VCVTPD2UQQZ256rr:
15161
0
  case VCVTPD2UQQZ256rrk:
15162
0
  case VCVTPD2UQQZ256rrkz:
15163
0
  case VCVTPD2UQQZrm:
15164
0
  case VCVTPD2UQQZrmb:
15165
0
  case VCVTPD2UQQZrmbk:
15166
0
  case VCVTPD2UQQZrmbkz:
15167
0
  case VCVTPD2UQQZrmk:
15168
0
  case VCVTPD2UQQZrmkz:
15169
0
  case VCVTPD2UQQZrr:
15170
0
  case VCVTPD2UQQZrrb:
15171
0
  case VCVTPD2UQQZrrbk:
15172
0
  case VCVTPD2UQQZrrbkz:
15173
0
  case VCVTPD2UQQZrrk:
15174
0
  case VCVTPD2UQQZrrkz:
15175
0
    return true;
15176
0
  }
15177
0
  return false;
15178
0
}
15179
15180
0
bool isFCMOVB(unsigned Opcode) {
15181
0
  return Opcode == CMOVB_F;
15182
0
}
15183
15184
0
bool isNOP(unsigned Opcode) {
15185
0
  switch (Opcode) {
15186
0
  case NOOP:
15187
0
  case NOOPL:
15188
0
  case NOOPLr:
15189
0
  case NOOPQ:
15190
0
  case NOOPQr:
15191
0
  case NOOPW:
15192
0
  case NOOPWr:
15193
0
    return true;
15194
0
  }
15195
0
  return false;
15196
0
}
15197
15198
0
bool isVPABSQ(unsigned Opcode) {
15199
0
  switch (Opcode) {
15200
0
  case VPABSQZ128rm:
15201
0
  case VPABSQZ128rmb:
15202
0
  case VPABSQZ128rmbk:
15203
0
  case VPABSQZ128rmbkz:
15204
0
  case VPABSQZ128rmk:
15205
0
  case VPABSQZ128rmkz:
15206
0
  case VPABSQZ128rr:
15207
0
  case VPABSQZ128rrk:
15208
0
  case VPABSQZ128rrkz:
15209
0
  case VPABSQZ256rm:
15210
0
  case VPABSQZ256rmb:
15211
0
  case VPABSQZ256rmbk:
15212
0
  case VPABSQZ256rmbkz:
15213
0
  case VPABSQZ256rmk:
15214
0
  case VPABSQZ256rmkz:
15215
0
  case VPABSQZ256rr:
15216
0
  case VPABSQZ256rrk:
15217
0
  case VPABSQZ256rrkz:
15218
0
  case VPABSQZrm:
15219
0
  case VPABSQZrmb:
15220
0
  case VPABSQZrmbk:
15221
0
  case VPABSQZrmbkz:
15222
0
  case VPABSQZrmk:
15223
0
  case VPABSQZrmkz:
15224
0
  case VPABSQZrr:
15225
0
  case VPABSQZrrk:
15226
0
  case VPABSQZrrkz:
15227
0
    return true;
15228
0
  }
15229
0
  return false;
15230
0
}
15231
15232
0
bool isVTESTPS(unsigned Opcode) {
15233
0
  switch (Opcode) {
15234
0
  case VTESTPSYrm:
15235
0
  case VTESTPSYrr:
15236
0
  case VTESTPSrm:
15237
0
  case VTESTPSrr:
15238
0
    return true;
15239
0
  }
15240
0
  return false;
15241
0
}
15242
15243
0
bool isPHSUBW(unsigned Opcode) {
15244
0
  switch (Opcode) {
15245
0
  case MMX_PHSUBWrm:
15246
0
  case MMX_PHSUBWrr:
15247
0
  case PHSUBWrm:
15248
0
  case PHSUBWrr:
15249
0
    return true;
15250
0
  }
15251
0
  return false;
15252
0
}
15253
15254
0
bool isPUSH2P(unsigned Opcode) {
15255
0
  return Opcode == PUSH2P;
15256
0
}
15257
15258
0
bool isFISTTP(unsigned Opcode) {
15259
0
  switch (Opcode) {
15260
0
  case ISTT_FP16m:
15261
0
  case ISTT_FP32m:
15262
0
  case ISTT_FP64m:
15263
0
    return true;
15264
0
  }
15265
0
  return false;
15266
0
}
15267
15268
0
bool isPCMPESTRM(unsigned Opcode) {
15269
0
  switch (Opcode) {
15270
0
  case PCMPESTRMrm:
15271
0
  case PCMPESTRMrr:
15272
0
    return true;
15273
0
  }
15274
0
  return false;
15275
0
}
15276
15277
0
bool isVPINSRD(unsigned Opcode) {
15278
0
  switch (Opcode) {
15279
0
  case VPINSRDZrm:
15280
0
  case VPINSRDZrr:
15281
0
  case VPINSRDrm:
15282
0
  case VPINSRDrr:
15283
0
    return true;
15284
0
  }
15285
0
  return false;
15286
0
}
15287
15288
0
bool isVFNMSUB213PS(unsigned Opcode) {
15289
0
  switch (Opcode) {
15290
0
  case VFNMSUB213PSYm:
15291
0
  case VFNMSUB213PSYr:
15292
0
  case VFNMSUB213PSZ128m:
15293
0
  case VFNMSUB213PSZ128mb:
15294
0
  case VFNMSUB213PSZ128mbk:
15295
0
  case VFNMSUB213PSZ128mbkz:
15296
0
  case VFNMSUB213PSZ128mk:
15297
0
  case VFNMSUB213PSZ128mkz:
15298
0
  case VFNMSUB213PSZ128r:
15299
0
  case VFNMSUB213PSZ128rk:
15300
0
  case VFNMSUB213PSZ128rkz:
15301
0
  case VFNMSUB213PSZ256m:
15302
0
  case VFNMSUB213PSZ256mb:
15303
0
  case VFNMSUB213PSZ256mbk:
15304
0
  case VFNMSUB213PSZ256mbkz:
15305
0
  case VFNMSUB213PSZ256mk:
15306
0
  case VFNMSUB213PSZ256mkz:
15307
0
  case VFNMSUB213PSZ256r:
15308
0
  case VFNMSUB213PSZ256rk:
15309
0
  case VFNMSUB213PSZ256rkz:
15310
0
  case VFNMSUB213PSZm:
15311
0
  case VFNMSUB213PSZmb:
15312
0
  case VFNMSUB213PSZmbk:
15313
0
  case VFNMSUB213PSZmbkz:
15314
0
  case VFNMSUB213PSZmk:
15315
0
  case VFNMSUB213PSZmkz:
15316
0
  case VFNMSUB213PSZr:
15317
0
  case VFNMSUB213PSZrb:
15318
0
  case VFNMSUB213PSZrbk:
15319
0
  case VFNMSUB213PSZrbkz:
15320
0
  case VFNMSUB213PSZrk:
15321
0
  case VFNMSUB213PSZrkz:
15322
0
  case VFNMSUB213PSm:
15323
0
  case VFNMSUB213PSr:
15324
0
    return true;
15325
0
  }
15326
0
  return false;
15327
0
}
15328
15329
0
bool isPHSUBD(unsigned Opcode) {
15330
0
  switch (Opcode) {
15331
0
  case MMX_PHSUBDrm:
15332
0
  case MMX_PHSUBDrr:
15333
0
  case PHSUBDrm:
15334
0
  case PHSUBDrr:
15335
0
    return true;
15336
0
  }
15337
0
  return false;
15338
0
}
15339
15340
0
bool isSLDT(unsigned Opcode) {
15341
0
  switch (Opcode) {
15342
0
  case SLDT16m:
15343
0
  case SLDT16r:
15344
0
  case SLDT32r:
15345
0
  case SLDT64r:
15346
0
    return true;
15347
0
  }
15348
0
  return false;
15349
0
}
15350
15351
0
bool isVPMINSD(unsigned Opcode) {
15352
0
  switch (Opcode) {
15353
0
  case VPMINSDYrm:
15354
0
  case VPMINSDYrr:
15355
0
  case VPMINSDZ128rm:
15356
0
  case VPMINSDZ128rmb:
15357
0
  case VPMINSDZ128rmbk:
15358
0
  case VPMINSDZ128rmbkz:
15359
0
  case VPMINSDZ128rmk:
15360
0
  case VPMINSDZ128rmkz:
15361
0
  case VPMINSDZ128rr:
15362
0
  case VPMINSDZ128rrk:
15363
0
  case VPMINSDZ128rrkz:
15364
0
  case VPMINSDZ256rm:
15365
0
  case VPMINSDZ256rmb:
15366
0
  case VPMINSDZ256rmbk:
15367
0
  case VPMINSDZ256rmbkz:
15368
0
  case VPMINSDZ256rmk:
15369
0
  case VPMINSDZ256rmkz:
15370
0
  case VPMINSDZ256rr:
15371
0
  case VPMINSDZ256rrk:
15372
0
  case VPMINSDZ256rrkz:
15373
0
  case VPMINSDZrm:
15374
0
  case VPMINSDZrmb:
15375
0
  case VPMINSDZrmbk:
15376
0
  case VPMINSDZrmbkz:
15377
0
  case VPMINSDZrmk:
15378
0
  case VPMINSDZrmkz:
15379
0
  case VPMINSDZrr:
15380
0
  case VPMINSDZrrk:
15381
0
  case VPMINSDZrrkz:
15382
0
  case VPMINSDrm:
15383
0
  case VPMINSDrr:
15384
0
    return true;
15385
0
  }
15386
0
  return false;
15387
0
}
15388
15389
0
bool isVHADDPS(unsigned Opcode) {
15390
0
  switch (Opcode) {
15391
0
  case VHADDPSYrm:
15392
0
  case VHADDPSYrr:
15393
0
  case VHADDPSrm:
15394
0
  case VHADDPSrr:
15395
0
    return true;
15396
0
  }
15397
0
  return false;
15398
0
}
15399
15400
0
bool isVMOVNTDQ(unsigned Opcode) {
15401
0
  switch (Opcode) {
15402
0
  case VMOVNTDQYmr:
15403
0
  case VMOVNTDQZ128mr:
15404
0
  case VMOVNTDQZ256mr:
15405
0
  case VMOVNTDQZmr:
15406
0
  case VMOVNTDQmr:
15407
0
    return true;
15408
0
  }
15409
0
  return false;
15410
0
}
15411
15412
0
bool isVFRCZSD(unsigned Opcode) {
15413
0
  switch (Opcode) {
15414
0
  case VFRCZSDrm:
15415
0
  case VFRCZSDrr:
15416
0
    return true;
15417
0
  }
15418
0
  return false;
15419
0
}
15420
15421
0
bool isVPTESTMW(unsigned Opcode) {
15422
0
  switch (Opcode) {
15423
0
  case VPTESTMWZ128rm:
15424
0
  case VPTESTMWZ128rmk:
15425
0
  case VPTESTMWZ128rr:
15426
0
  case VPTESTMWZ128rrk:
15427
0
  case VPTESTMWZ256rm:
15428
0
  case VPTESTMWZ256rmk:
15429
0
  case VPTESTMWZ256rr:
15430
0
  case VPTESTMWZ256rrk:
15431
0
  case VPTESTMWZrm:
15432
0
  case VPTESTMWZrmk:
15433
0
  case VPTESTMWZrr:
15434
0
  case VPTESTMWZrrk:
15435
0
    return true;
15436
0
  }
15437
0
  return false;
15438
0
}
15439
15440
0
bool isVPMOVZXWD(unsigned Opcode) {
15441
0
  switch (Opcode) {
15442
0
  case VPMOVZXWDYrm:
15443
0
  case VPMOVZXWDYrr:
15444
0
  case VPMOVZXWDZ128rm:
15445
0
  case VPMOVZXWDZ128rmk:
15446
0
  case VPMOVZXWDZ128rmkz:
15447
0
  case VPMOVZXWDZ128rr:
15448
0
  case VPMOVZXWDZ128rrk:
15449
0
  case VPMOVZXWDZ128rrkz:
15450
0
  case VPMOVZXWDZ256rm:
15451
0
  case VPMOVZXWDZ256rmk:
15452
0
  case VPMOVZXWDZ256rmkz:
15453
0
  case VPMOVZXWDZ256rr:
15454
0
  case VPMOVZXWDZ256rrk:
15455
0
  case VPMOVZXWDZ256rrkz:
15456
0
  case VPMOVZXWDZrm:
15457
0
  case VPMOVZXWDZrmk:
15458
0
  case VPMOVZXWDZrmkz:
15459
0
  case VPMOVZXWDZrr:
15460
0
  case VPMOVZXWDZrrk:
15461
0
  case VPMOVZXWDZrrkz:
15462
0
  case VPMOVZXWDrm:
15463
0
  case VPMOVZXWDrr:
15464
0
    return true;
15465
0
  }
15466
0
  return false;
15467
0
}
15468
15469
0
bool isPSADBW(unsigned Opcode) {
15470
0
  switch (Opcode) {
15471
0
  case MMX_PSADBWrm:
15472
0
  case MMX_PSADBWrr:
15473
0
  case PSADBWrm:
15474
0
  case PSADBWrr:
15475
0
    return true;
15476
0
  }
15477
0
  return false;
15478
0
}
15479
15480
0
bool isVCVTSD2SI(unsigned Opcode) {
15481
0
  switch (Opcode) {
15482
0
  case VCVTSD2SI64Zrm_Int:
15483
0
  case VCVTSD2SI64Zrr_Int:
15484
0
  case VCVTSD2SI64Zrrb_Int:
15485
0
  case VCVTSD2SI64rm_Int:
15486
0
  case VCVTSD2SI64rr_Int:
15487
0
  case VCVTSD2SIZrm_Int:
15488
0
  case VCVTSD2SIZrr_Int:
15489
0
  case VCVTSD2SIZrrb_Int:
15490
0
  case VCVTSD2SIrm_Int:
15491
0
  case VCVTSD2SIrr_Int:
15492
0
    return true;
15493
0
  }
15494
0
  return false;
15495
0
}
15496
15497
0
bool isVMAXPH(unsigned Opcode) {
15498
0
  switch (Opcode) {
15499
0
  case VMAXPHZ128rm:
15500
0
  case VMAXPHZ128rmb:
15501
0
  case VMAXPHZ128rmbk:
15502
0
  case VMAXPHZ128rmbkz:
15503
0
  case VMAXPHZ128rmk:
15504
0
  case VMAXPHZ128rmkz:
15505
0
  case VMAXPHZ128rr:
15506
0
  case VMAXPHZ128rrk:
15507
0
  case VMAXPHZ128rrkz:
15508
0
  case VMAXPHZ256rm:
15509
0
  case VMAXPHZ256rmb:
15510
0
  case VMAXPHZ256rmbk:
15511
0
  case VMAXPHZ256rmbkz:
15512
0
  case VMAXPHZ256rmk:
15513
0
  case VMAXPHZ256rmkz:
15514
0
  case VMAXPHZ256rr:
15515
0
  case VMAXPHZ256rrk:
15516
0
  case VMAXPHZ256rrkz:
15517
0
  case VMAXPHZrm:
15518
0
  case VMAXPHZrmb:
15519
0
  case VMAXPHZrmbk:
15520
0
  case VMAXPHZrmbkz:
15521
0
  case VMAXPHZrmk:
15522
0
  case VMAXPHZrmkz:
15523
0
  case VMAXPHZrr:
15524
0
  case VMAXPHZrrb:
15525
0
  case VMAXPHZrrbk:
15526
0
  case VMAXPHZrrbkz:
15527
0
  case VMAXPHZrrk:
15528
0
  case VMAXPHZrrkz:
15529
0
    return true;
15530
0
  }
15531
0
  return false;
15532
0
}
15533
15534
0
bool isLODSB(unsigned Opcode) {
15535
0
  return Opcode == LODSB;
15536
0
}
15537
15538
0
bool isPHMINPOSUW(unsigned Opcode) {
15539
0
  switch (Opcode) {
15540
0
  case PHMINPOSUWrm:
15541
0
  case PHMINPOSUWrr:
15542
0
    return true;
15543
0
  }
15544
0
  return false;
15545
0
}
15546
15547
0
bool isVPROLVD(unsigned Opcode) {
15548
0
  switch (Opcode) {
15549
0
  case VPROLVDZ128rm:
15550
0
  case VPROLVDZ128rmb:
15551
0
  case VPROLVDZ128rmbk:
15552
0
  case VPROLVDZ128rmbkz:
15553
0
  case VPROLVDZ128rmk:
15554
0
  case VPROLVDZ128rmkz:
15555
0
  case VPROLVDZ128rr:
15556
0
  case VPROLVDZ128rrk:
15557
0
  case VPROLVDZ128rrkz:
15558
0
  case VPROLVDZ256rm:
15559
0
  case VPROLVDZ256rmb:
15560
0
  case VPROLVDZ256rmbk:
15561
0
  case VPROLVDZ256rmbkz:
15562
0
  case VPROLVDZ256rmk:
15563
0
  case VPROLVDZ256rmkz:
15564
0
  case VPROLVDZ256rr:
15565
0
  case VPROLVDZ256rrk:
15566
0
  case VPROLVDZ256rrkz:
15567
0
  case VPROLVDZrm:
15568
0
  case VPROLVDZrmb:
15569
0
  case VPROLVDZrmbk:
15570
0
  case VPROLVDZrmbkz:
15571
0
  case VPROLVDZrmk:
15572
0
  case VPROLVDZrmkz:
15573
0
  case VPROLVDZrr:
15574
0
  case VPROLVDZrrk:
15575
0
  case VPROLVDZrrkz:
15576
0
    return true;
15577
0
  }
15578
0
  return false;
15579
0
}
15580
15581
0
bool isWRFSBASE(unsigned Opcode) {
15582
0
  switch (Opcode) {
15583
0
  case WRFSBASE:
15584
0
  case WRFSBASE64:
15585
0
    return true;
15586
0
  }
15587
0
  return false;
15588
0
}
15589
15590
0
bool isVRSQRT14PS(unsigned Opcode) {
15591
0
  switch (Opcode) {
15592
0
  case VRSQRT14PSZ128m:
15593
0
  case VRSQRT14PSZ128mb:
15594
0
  case VRSQRT14PSZ128mbk:
15595
0
  case VRSQRT14PSZ128mbkz:
15596
0
  case VRSQRT14PSZ128mk:
15597
0
  case VRSQRT14PSZ128mkz:
15598
0
  case VRSQRT14PSZ128r:
15599
0
  case VRSQRT14PSZ128rk:
15600
0
  case VRSQRT14PSZ128rkz:
15601
0
  case VRSQRT14PSZ256m:
15602
0
  case VRSQRT14PSZ256mb:
15603
0
  case VRSQRT14PSZ256mbk:
15604
0
  case VRSQRT14PSZ256mbkz:
15605
0
  case VRSQRT14PSZ256mk:
15606
0
  case VRSQRT14PSZ256mkz:
15607
0
  case VRSQRT14PSZ256r:
15608
0
  case VRSQRT14PSZ256rk:
15609
0
  case VRSQRT14PSZ256rkz:
15610
0
  case VRSQRT14PSZm:
15611
0
  case VRSQRT14PSZmb:
15612
0
  case VRSQRT14PSZmbk:
15613
0
  case VRSQRT14PSZmbkz:
15614
0
  case VRSQRT14PSZmk:
15615
0
  case VRSQRT14PSZmkz:
15616
0
  case VRSQRT14PSZr:
15617
0
  case VRSQRT14PSZrk:
15618
0
  case VRSQRT14PSZrkz:
15619
0
    return true;
15620
0
  }
15621
0
  return false;
15622
0
}
15623
15624
0
bool isVPHSUBDQ(unsigned Opcode) {
15625
0
  switch (Opcode) {
15626
0
  case VPHSUBDQrm:
15627
0
  case VPHSUBDQrr:
15628
0
    return true;
15629
0
  }
15630
0
  return false;
15631
0
}
15632
15633
0
bool isIRETD(unsigned Opcode) {
15634
0
  return Opcode == IRET32;
15635
0
}
15636
15637
0
bool isCVTSI2SS(unsigned Opcode) {
15638
0
  switch (Opcode) {
15639
0
  case CVTSI2SSrm_Int:
15640
0
  case CVTSI2SSrr_Int:
15641
0
  case CVTSI642SSrm_Int:
15642
0
  case CVTSI642SSrr_Int:
15643
0
    return true;
15644
0
  }
15645
0
  return false;
15646
0
}
15647
15648
0
bool isVPMULHRSW(unsigned Opcode) {
15649
0
  switch (Opcode) {
15650
0
  case VPMULHRSWYrm:
15651
0
  case VPMULHRSWYrr:
15652
0
  case VPMULHRSWZ128rm:
15653
0
  case VPMULHRSWZ128rmk:
15654
0
  case VPMULHRSWZ128rmkz:
15655
0
  case VPMULHRSWZ128rr:
15656
0
  case VPMULHRSWZ128rrk:
15657
0
  case VPMULHRSWZ128rrkz:
15658
0
  case VPMULHRSWZ256rm:
15659
0
  case VPMULHRSWZ256rmk:
15660
0
  case VPMULHRSWZ256rmkz:
15661
0
  case VPMULHRSWZ256rr:
15662
0
  case VPMULHRSWZ256rrk:
15663
0
  case VPMULHRSWZ256rrkz:
15664
0
  case VPMULHRSWZrm:
15665
0
  case VPMULHRSWZrmk:
15666
0
  case VPMULHRSWZrmkz:
15667
0
  case VPMULHRSWZrr:
15668
0
  case VPMULHRSWZrrk:
15669
0
  case VPMULHRSWZrrkz:
15670
0
  case VPMULHRSWrm:
15671
0
  case VPMULHRSWrr:
15672
0
    return true;
15673
0
  }
15674
0
  return false;
15675
0
}
15676
15677
0
bool isPI2FD(unsigned Opcode) {
15678
0
  switch (Opcode) {
15679
0
  case PI2FDrm:
15680
0
  case PI2FDrr:
15681
0
    return true;
15682
0
  }
15683
0
  return false;
15684
0
}
15685
15686
0
bool isGF2P8AFFINEQB(unsigned Opcode) {
15687
0
  switch (Opcode) {
15688
0
  case GF2P8AFFINEQBrmi:
15689
0
  case GF2P8AFFINEQBrri:
15690
0
    return true;
15691
0
  }
15692
0
  return false;
15693
0
}
15694
15695
0
bool isPAND(unsigned Opcode) {
15696
0
  switch (Opcode) {
15697
0
  case MMX_PANDrm:
15698
0
  case MMX_PANDrr:
15699
0
  case PANDrm:
15700
0
  case PANDrr:
15701
0
    return true;
15702
0
  }
15703
0
  return false;
15704
0
}
15705
15706
0
bool isVFNMSUB231SH(unsigned Opcode) {
15707
0
  switch (Opcode) {
15708
0
  case VFNMSUB231SHZm_Int:
15709
0
  case VFNMSUB231SHZm_Intk:
15710
0
  case VFNMSUB231SHZm_Intkz:
15711
0
  case VFNMSUB231SHZr_Int:
15712
0
  case VFNMSUB231SHZr_Intk:
15713
0
  case VFNMSUB231SHZr_Intkz:
15714
0
  case VFNMSUB231SHZrb_Int:
15715
0
  case VFNMSUB231SHZrb_Intk:
15716
0
  case VFNMSUB231SHZrb_Intkz:
15717
0
    return true;
15718
0
  }
15719
0
  return false;
15720
0
}
15721
15722
0
bool isVMOVHLPS(unsigned Opcode) {
15723
0
  switch (Opcode) {
15724
0
  case VMOVHLPSZrr:
15725
0
  case VMOVHLPSrr:
15726
0
    return true;
15727
0
  }
15728
0
  return false;
15729
0
}
15730
15731
0
bool isPEXTRB(unsigned Opcode) {
15732
0
  switch (Opcode) {
15733
0
  case PEXTRBmr:
15734
0
  case PEXTRBrr:
15735
0
    return true;
15736
0
  }
15737
0
  return false;
15738
0
}
15739
15740
0
bool isKNOTD(unsigned Opcode) {
15741
0
  return Opcode == KNOTDrr;
15742
0
}
15743
15744
0
bool isVPUNPCKLQDQ(unsigned Opcode) {
15745
0
  switch (Opcode) {
15746
0
  case VPUNPCKLQDQYrm:
15747
0
  case VPUNPCKLQDQYrr:
15748
0
  case VPUNPCKLQDQZ128rm:
15749
0
  case VPUNPCKLQDQZ128rmb:
15750
0
  case VPUNPCKLQDQZ128rmbk:
15751
0
  case VPUNPCKLQDQZ128rmbkz:
15752
0
  case VPUNPCKLQDQZ128rmk:
15753
0
  case VPUNPCKLQDQZ128rmkz:
15754
0
  case VPUNPCKLQDQZ128rr:
15755
0
  case VPUNPCKLQDQZ128rrk:
15756
0
  case VPUNPCKLQDQZ128rrkz:
15757
0
  case VPUNPCKLQDQZ256rm:
15758
0
  case VPUNPCKLQDQZ256rmb:
15759
0
  case VPUNPCKLQDQZ256rmbk:
15760
0
  case VPUNPCKLQDQZ256rmbkz:
15761
0
  case VPUNPCKLQDQZ256rmk:
15762
0
  case VPUNPCKLQDQZ256rmkz:
15763
0
  case VPUNPCKLQDQZ256rr:
15764
0
  case VPUNPCKLQDQZ256rrk:
15765
0
  case VPUNPCKLQDQZ256rrkz:
15766
0
  case VPUNPCKLQDQZrm:
15767
0
  case VPUNPCKLQDQZrmb:
15768
0
  case VPUNPCKLQDQZrmbk:
15769
0
  case VPUNPCKLQDQZrmbkz:
15770
0
  case VPUNPCKLQDQZrmk:
15771
0
  case VPUNPCKLQDQZrmkz:
15772
0
  case VPUNPCKLQDQZrr:
15773
0
  case VPUNPCKLQDQZrrk:
15774
0
  case VPUNPCKLQDQZrrkz:
15775
0
  case VPUNPCKLQDQrm:
15776
0
  case VPUNPCKLQDQrr:
15777
0
    return true;
15778
0
  }
15779
0
  return false;
15780
0
}
15781
15782
0
bool isVMMCALL(unsigned Opcode) {
15783
0
  return Opcode == VMMCALL;
15784
0
}
15785
15786
0
bool isVCVTSH2SS(unsigned Opcode) {
15787
0
  switch (Opcode) {
15788
0
  case VCVTSH2SSZrm_Int:
15789
0
  case VCVTSH2SSZrm_Intk:
15790
0
  case VCVTSH2SSZrm_Intkz:
15791
0
  case VCVTSH2SSZrr_Int:
15792
0
  case VCVTSH2SSZrr_Intk:
15793
0
  case VCVTSH2SSZrr_Intkz:
15794
0
  case VCVTSH2SSZrrb_Int:
15795
0
  case VCVTSH2SSZrrb_Intk:
15796
0
  case VCVTSH2SSZrrb_Intkz:
15797
0
    return true;
15798
0
  }
15799
0
  return false;
15800
0
}
15801
15802
0
bool isVPERMIL2PS(unsigned Opcode) {
15803
0
  switch (Opcode) {
15804
0
  case VPERMIL2PSYmr:
15805
0
  case VPERMIL2PSYrm:
15806
0
  case VPERMIL2PSYrr:
15807
0
  case VPERMIL2PSYrr_REV:
15808
0
  case VPERMIL2PSmr:
15809
0
  case VPERMIL2PSrm:
15810
0
  case VPERMIL2PSrr:
15811
0
  case VPERMIL2PSrr_REV:
15812
0
    return true;
15813
0
  }
15814
0
  return false;
15815
0
}
15816
15817
0
bool isVPCMPGTD(unsigned Opcode) {
15818
0
  switch (Opcode) {
15819
0
  case VPCMPGTDYrm:
15820
0
  case VPCMPGTDYrr:
15821
0
  case VPCMPGTDZ128rm:
15822
0
  case VPCMPGTDZ128rmb:
15823
0
  case VPCMPGTDZ128rmbk:
15824
0
  case VPCMPGTDZ128rmk:
15825
0
  case VPCMPGTDZ128rr:
15826
0
  case VPCMPGTDZ128rrk:
15827
0
  case VPCMPGTDZ256rm:
15828
0
  case VPCMPGTDZ256rmb:
15829
0
  case VPCMPGTDZ256rmbk:
15830
0
  case VPCMPGTDZ256rmk:
15831
0
  case VPCMPGTDZ256rr:
15832
0
  case VPCMPGTDZ256rrk:
15833
0
  case VPCMPGTDZrm:
15834
0
  case VPCMPGTDZrmb:
15835
0
  case VPCMPGTDZrmbk:
15836
0
  case VPCMPGTDZrmk:
15837
0
  case VPCMPGTDZrr:
15838
0
  case VPCMPGTDZrrk:
15839
0
  case VPCMPGTDrm:
15840
0
  case VPCMPGTDrr:
15841
0
    return true;
15842
0
  }
15843
0
  return false;
15844
0
}
15845
15846
0
bool isCMPXCHG16B(unsigned Opcode) {
15847
0
  return Opcode == CMPXCHG16B;
15848
0
}
15849
15850
0
bool isVZEROUPPER(unsigned Opcode) {
15851
0
  return Opcode == VZEROUPPER;
15852
0
}
15853
15854
0
bool isMOVAPS(unsigned Opcode) {
15855
0
  switch (Opcode) {
15856
0
  case MOVAPSmr:
15857
0
  case MOVAPSrm:
15858
0
  case MOVAPSrr:
15859
0
  case MOVAPSrr_REV:
15860
0
    return true;
15861
0
  }
15862
0
  return false;
15863
0
}
15864
15865
0
bool isVPCMPW(unsigned Opcode) {
15866
0
  switch (Opcode) {
15867
0
  case VPCMPWZ128rmi:
15868
0
  case VPCMPWZ128rmik:
15869
0
  case VPCMPWZ128rri:
15870
0
  case VPCMPWZ128rrik:
15871
0
  case VPCMPWZ256rmi:
15872
0
  case VPCMPWZ256rmik:
15873
0
  case VPCMPWZ256rri:
15874
0
  case VPCMPWZ256rrik:
15875
0
  case VPCMPWZrmi:
15876
0
  case VPCMPWZrmik:
15877
0
  case VPCMPWZrri:
15878
0
  case VPCMPWZrrik:
15879
0
    return true;
15880
0
  }
15881
0
  return false;
15882
0
}
15883
15884
0
bool isFUCOMPP(unsigned Opcode) {
15885
0
  return Opcode == UCOM_FPPr;
15886
0
}
15887
15888
0
bool isXSETBV(unsigned Opcode) {
15889
0
  return Opcode == XSETBV;
15890
0
}
15891
15892
0
bool isSLWPCB(unsigned Opcode) {
15893
0
  switch (Opcode) {
15894
0
  case SLWPCB:
15895
0
  case SLWPCB64:
15896
0
    return true;
15897
0
  }
15898
0
  return false;
15899
0
}
15900
15901
0
bool isSCASW(unsigned Opcode) {
15902
0
  return Opcode == SCASW;
15903
0
}
15904
15905
0
bool isFCMOVNE(unsigned Opcode) {
15906
0
  return Opcode == CMOVNE_F;
15907
0
}
15908
15909
0
bool isPBNDKB(unsigned Opcode) {
15910
0
  return Opcode == PBNDKB;
15911
0
}
15912
15913
0
bool isVPMULLD(unsigned Opcode) {
15914
0
  switch (Opcode) {
15915
0
  case VPMULLDYrm:
15916
0
  case VPMULLDYrr:
15917
0
  case VPMULLDZ128rm:
15918
0
  case VPMULLDZ128rmb:
15919
0
  case VPMULLDZ128rmbk:
15920
0
  case VPMULLDZ128rmbkz:
15921
0
  case VPMULLDZ128rmk:
15922
0
  case VPMULLDZ128rmkz:
15923
0
  case VPMULLDZ128rr:
15924
0
  case VPMULLDZ128rrk:
15925
0
  case VPMULLDZ128rrkz:
15926
0
  case VPMULLDZ256rm:
15927
0
  case VPMULLDZ256rmb:
15928
0
  case VPMULLDZ256rmbk:
15929
0
  case VPMULLDZ256rmbkz:
15930
0
  case VPMULLDZ256rmk:
15931
0
  case VPMULLDZ256rmkz:
15932
0
  case VPMULLDZ256rr:
15933
0
  case VPMULLDZ256rrk:
15934
0
  case VPMULLDZ256rrkz:
15935
0
  case VPMULLDZrm:
15936
0
  case VPMULLDZrmb:
15937
0
  case VPMULLDZrmbk:
15938
0
  case VPMULLDZrmbkz:
15939
0
  case VPMULLDZrmk:
15940
0
  case VPMULLDZrmkz:
15941
0
  case VPMULLDZrr:
15942
0
  case VPMULLDZrrk:
15943
0
  case VPMULLDZrrkz:
15944
0
  case VPMULLDrm:
15945
0
  case VPMULLDrr:
15946
0
    return true;
15947
0
  }
15948
0
  return false;
15949
0
}
15950
15951
0
bool isVP4DPWSSDS(unsigned Opcode) {
15952
0
  switch (Opcode) {
15953
0
  case VP4DPWSSDSrm:
15954
0
  case VP4DPWSSDSrmk:
15955
0
  case VP4DPWSSDSrmkz:
15956
0
    return true;
15957
0
  }
15958
0
  return false;
15959
0
}
15960
15961
0
bool isPINSRW(unsigned Opcode) {
15962
0
  switch (Opcode) {
15963
0
  case MMX_PINSRWrm:
15964
0
  case MMX_PINSRWrr:
15965
0
  case PINSRWrm:
15966
0
  case PINSRWrr:
15967
0
    return true;
15968
0
  }
15969
0
  return false;
15970
0
}
15971
15972
0
bool isVCVTSI2SH(unsigned Opcode) {
15973
0
  switch (Opcode) {
15974
0
  case VCVTSI2SHZrm_Int:
15975
0
  case VCVTSI2SHZrr_Int:
15976
0
  case VCVTSI2SHZrrb_Int:
15977
0
  case VCVTSI642SHZrm_Int:
15978
0
  case VCVTSI642SHZrr_Int:
15979
0
  case VCVTSI642SHZrrb_Int:
15980
0
    return true;
15981
0
  }
15982
0
  return false;
15983
0
}
15984
15985
0
bool isVINSERTF32X8(unsigned Opcode) {
15986
0
  switch (Opcode) {
15987
0
  case VINSERTF32x8Zrm:
15988
0
  case VINSERTF32x8Zrmk:
15989
0
  case VINSERTF32x8Zrmkz:
15990
0
  case VINSERTF32x8Zrr:
15991
0
  case VINSERTF32x8Zrrk:
15992
0
  case VINSERTF32x8Zrrkz:
15993
0
    return true;
15994
0
  }
15995
0
  return false;
15996
0
}
15997
15998
0
bool isKSHIFTLB(unsigned Opcode) {
15999
0
  return Opcode == KSHIFTLBri;
16000
0
}
16001
16002
0
bool isSEAMOPS(unsigned Opcode) {
16003
0
  return Opcode == SEAMOPS;
16004
0
}
16005
16006
0
bool isVPMULUDQ(unsigned Opcode) {
16007
0
  switch (Opcode) {
16008
0
  case VPMULUDQYrm:
16009
0
  case VPMULUDQYrr:
16010
0
  case VPMULUDQZ128rm:
16011
0
  case VPMULUDQZ128rmb:
16012
0
  case VPMULUDQZ128rmbk:
16013
0
  case VPMULUDQZ128rmbkz:
16014
0
  case VPMULUDQZ128rmk:
16015
0
  case VPMULUDQZ128rmkz:
16016
0
  case VPMULUDQZ128rr:
16017
0
  case VPMULUDQZ128rrk:
16018
0
  case VPMULUDQZ128rrkz:
16019
0
  case VPMULUDQZ256rm:
16020
0
  case VPMULUDQZ256rmb:
16021
0
  case VPMULUDQZ256rmbk:
16022
0
  case VPMULUDQZ256rmbkz:
16023
0
  case VPMULUDQZ256rmk:
16024
0
  case VPMULUDQZ256rmkz:
16025
0
  case VPMULUDQZ256rr:
16026
0
  case VPMULUDQZ256rrk:
16027
0
  case VPMULUDQZ256rrkz:
16028
0
  case VPMULUDQZrm:
16029
0
  case VPMULUDQZrmb:
16030
0
  case VPMULUDQZrmbk:
16031
0
  case VPMULUDQZrmbkz:
16032
0
  case VPMULUDQZrmk:
16033
0
  case VPMULUDQZrmkz:
16034
0
  case VPMULUDQZrr:
16035
0
  case VPMULUDQZrrk:
16036
0
  case VPMULUDQZrrkz:
16037
0
  case VPMULUDQrm:
16038
0
  case VPMULUDQrr:
16039
0
    return true;
16040
0
  }
16041
0
  return false;
16042
0
}
16043
16044
0
bool isVPMOVSQB(unsigned Opcode) {
16045
0
  switch (Opcode) {
16046
0
  case VPMOVSQBZ128mr:
16047
0
  case VPMOVSQBZ128mrk:
16048
0
  case VPMOVSQBZ128rr:
16049
0
  case VPMOVSQBZ128rrk:
16050
0
  case VPMOVSQBZ128rrkz:
16051
0
  case VPMOVSQBZ256mr:
16052
0
  case VPMOVSQBZ256mrk:
16053
0
  case VPMOVSQBZ256rr:
16054
0
  case VPMOVSQBZ256rrk:
16055
0
  case VPMOVSQBZ256rrkz:
16056
0
  case VPMOVSQBZmr:
16057
0
  case VPMOVSQBZmrk:
16058
0
  case VPMOVSQBZrr:
16059
0
  case VPMOVSQBZrrk:
16060
0
  case VPMOVSQBZrrkz:
16061
0
    return true;
16062
0
  }
16063
0
  return false;
16064
0
}
16065
16066
0
bool isVPTESTMD(unsigned Opcode) {
16067
0
  switch (Opcode) {
16068
0
  case VPTESTMDZ128rm:
16069
0
  case VPTESTMDZ128rmb:
16070
0
  case VPTESTMDZ128rmbk:
16071
0
  case VPTESTMDZ128rmk:
16072
0
  case VPTESTMDZ128rr:
16073
0
  case VPTESTMDZ128rrk:
16074
0
  case VPTESTMDZ256rm:
16075
0
  case VPTESTMDZ256rmb:
16076
0
  case VPTESTMDZ256rmbk:
16077
0
  case VPTESTMDZ256rmk:
16078
0
  case VPTESTMDZ256rr:
16079
0
  case VPTESTMDZ256rrk:
16080
0
  case VPTESTMDZrm:
16081
0
  case VPTESTMDZrmb:
16082
0
  case VPTESTMDZrmbk:
16083
0
  case VPTESTMDZrmk:
16084
0
  case VPTESTMDZrr:
16085
0
  case VPTESTMDZrrk:
16086
0
    return true;
16087
0
  }
16088
0
  return false;
16089
0
}
16090
16091
0
bool isVPHADDDQ(unsigned Opcode) {
16092
0
  switch (Opcode) {
16093
0
  case VPHADDDQrm:
16094
0
  case VPHADDDQrr:
16095
0
    return true;
16096
0
  }
16097
0
  return false;
16098
0
}
16099
16100
0
bool isKUNPCKDQ(unsigned Opcode) {
16101
0
  return Opcode == KUNPCKDQrr;
16102
0
}
16103
16104
0
bool isT1MSKC(unsigned Opcode) {
16105
0
  switch (Opcode) {
16106
0
  case T1MSKC32rm:
16107
0
  case T1MSKC32rr:
16108
0
  case T1MSKC64rm:
16109
0
  case T1MSKC64rr:
16110
0
    return true;
16111
0
  }
16112
0
  return false;
16113
0
}
16114
16115
0
bool isVPCOMB(unsigned Opcode) {
16116
0
  switch (Opcode) {
16117
0
  case VPCOMBmi:
16118
0
  case VPCOMBri:
16119
0
    return true;
16120
0
  }
16121
0
  return false;
16122
0
}
16123
16124
0
bool isVBLENDPS(unsigned Opcode) {
16125
0
  switch (Opcode) {
16126
0
  case VBLENDPSYrmi:
16127
0
  case VBLENDPSYrri:
16128
0
  case VBLENDPSrmi:
16129
0
  case VBLENDPSrri:
16130
0
    return true;
16131
0
  }
16132
0
  return false;
16133
0
}
16134
16135
0
bool isPTWRITE(unsigned Opcode) {
16136
0
  switch (Opcode) {
16137
0
  case PTWRITE64m:
16138
0
  case PTWRITE64r:
16139
0
  case PTWRITEm:
16140
0
  case PTWRITEr:
16141
0
    return true;
16142
0
  }
16143
0
  return false;
16144
0
}
16145
16146
0
bool isCVTPS2PI(unsigned Opcode) {
16147
0
  switch (Opcode) {
16148
0
  case MMX_CVTPS2PIrm:
16149
0
  case MMX_CVTPS2PIrr:
16150
0
    return true;
16151
0
  }
16152
0
  return false;
16153
0
}
16154
16155
0
bool isVPROTD(unsigned Opcode) {
16156
0
  switch (Opcode) {
16157
0
  case VPROTDmi:
16158
0
  case VPROTDmr:
16159
0
  case VPROTDri:
16160
0
  case VPROTDrm:
16161
0
  case VPROTDrr:
16162
0
  case VPROTDrr_REV:
16163
0
    return true;
16164
0
  }
16165
0
  return false;
16166
0
}
16167
16168
0
bool isCALL(unsigned Opcode) {
16169
0
  switch (Opcode) {
16170
0
  case CALL16m:
16171
0
  case CALL16r:
16172
0
  case CALL32m:
16173
0
  case CALL32r:
16174
0
  case CALL64m:
16175
0
  case CALL64pcrel32:
16176
0
  case CALL64r:
16177
0
  case CALLpcrel16:
16178
0
  case CALLpcrel32:
16179
0
  case FARCALL32m:
16180
0
    return true;
16181
0
  }
16182
0
  return false;
16183
0
}
16184
16185
0
bool isVPERMPS(unsigned Opcode) {
16186
0
  switch (Opcode) {
16187
0
  case VPERMPSYrm:
16188
0
  case VPERMPSYrr:
16189
0
  case VPERMPSZ256rm:
16190
0
  case VPERMPSZ256rmb:
16191
0
  case VPERMPSZ256rmbk:
16192
0
  case VPERMPSZ256rmbkz:
16193
0
  case VPERMPSZ256rmk:
16194
0
  case VPERMPSZ256rmkz:
16195
0
  case VPERMPSZ256rr:
16196
0
  case VPERMPSZ256rrk:
16197
0
  case VPERMPSZ256rrkz:
16198
0
  case VPERMPSZrm:
16199
0
  case VPERMPSZrmb:
16200
0
  case VPERMPSZrmbk:
16201
0
  case VPERMPSZrmbkz:
16202
0
  case VPERMPSZrmk:
16203
0
  case VPERMPSZrmkz:
16204
0
  case VPERMPSZrr:
16205
0
  case VPERMPSZrrk:
16206
0
  case VPERMPSZrrkz:
16207
0
    return true;
16208
0
  }
16209
0
  return false;
16210
0
}
16211
16212
0
bool isVPSHUFBITQMB(unsigned Opcode) {
16213
0
  switch (Opcode) {
16214
0
  case VPSHUFBITQMBZ128rm:
16215
0
  case VPSHUFBITQMBZ128rmk:
16216
0
  case VPSHUFBITQMBZ128rr:
16217
0
  case VPSHUFBITQMBZ128rrk:
16218
0
  case VPSHUFBITQMBZ256rm:
16219
0
  case VPSHUFBITQMBZ256rmk:
16220
0
  case VPSHUFBITQMBZ256rr:
16221
0
  case VPSHUFBITQMBZ256rrk:
16222
0
  case VPSHUFBITQMBZrm:
16223
0
  case VPSHUFBITQMBZrmk:
16224
0
  case VPSHUFBITQMBZrr:
16225
0
  case VPSHUFBITQMBZrrk:
16226
0
    return true;
16227
0
  }
16228
0
  return false;
16229
0
}
16230
16231
0
bool isVMOVSLDUP(unsigned Opcode) {
16232
0
  switch (Opcode) {
16233
0
  case VMOVSLDUPYrm:
16234
0
  case VMOVSLDUPYrr:
16235
0
  case VMOVSLDUPZ128rm:
16236
0
  case VMOVSLDUPZ128rmk:
16237
0
  case VMOVSLDUPZ128rmkz:
16238
0
  case VMOVSLDUPZ128rr:
16239
0
  case VMOVSLDUPZ128rrk:
16240
0
  case VMOVSLDUPZ128rrkz:
16241
0
  case VMOVSLDUPZ256rm:
16242
0
  case VMOVSLDUPZ256rmk:
16243
0
  case VMOVSLDUPZ256rmkz:
16244
0
  case VMOVSLDUPZ256rr:
16245
0
  case VMOVSLDUPZ256rrk:
16246
0
  case VMOVSLDUPZ256rrkz:
16247
0
  case VMOVSLDUPZrm:
16248
0
  case VMOVSLDUPZrmk:
16249
0
  case VMOVSLDUPZrmkz:
16250
0
  case VMOVSLDUPZrr:
16251
0
  case VMOVSLDUPZrrk:
16252
0
  case VMOVSLDUPZrrkz:
16253
0
  case VMOVSLDUPrm:
16254
0
  case VMOVSLDUPrr:
16255
0
    return true;
16256
0
  }
16257
0
  return false;
16258
0
}
16259
16260
0
bool isINVLPGA(unsigned Opcode) {
16261
0
  switch (Opcode) {
16262
0
  case INVLPGA32:
16263
0
  case INVLPGA64:
16264
0
    return true;
16265
0
  }
16266
0
  return false;
16267
0
}
16268
16269
0
bool isVCVTPH2QQ(unsigned Opcode) {
16270
0
  switch (Opcode) {
16271
0
  case VCVTPH2QQZ128rm:
16272
0
  case VCVTPH2QQZ128rmb:
16273
0
  case VCVTPH2QQZ128rmbk:
16274
0
  case VCVTPH2QQZ128rmbkz:
16275
0
  case VCVTPH2QQZ128rmk:
16276
0
  case VCVTPH2QQZ128rmkz:
16277
0
  case VCVTPH2QQZ128rr:
16278
0
  case VCVTPH2QQZ128rrk:
16279
0
  case VCVTPH2QQZ128rrkz:
16280
0
  case VCVTPH2QQZ256rm:
16281
0
  case VCVTPH2QQZ256rmb:
16282
0
  case VCVTPH2QQZ256rmbk:
16283
0
  case VCVTPH2QQZ256rmbkz:
16284
0
  case VCVTPH2QQZ256rmk:
16285
0
  case VCVTPH2QQZ256rmkz:
16286
0
  case VCVTPH2QQZ256rr:
16287
0
  case VCVTPH2QQZ256rrk:
16288
0
  case VCVTPH2QQZ256rrkz:
16289
0
  case VCVTPH2QQZrm:
16290
0
  case VCVTPH2QQZrmb:
16291
0
  case VCVTPH2QQZrmbk:
16292
0
  case VCVTPH2QQZrmbkz:
16293
0
  case VCVTPH2QQZrmk:
16294
0
  case VCVTPH2QQZrmkz:
16295
0
  case VCVTPH2QQZrr:
16296
0
  case VCVTPH2QQZrrb:
16297
0
  case VCVTPH2QQZrrbk:
16298
0
  case VCVTPH2QQZrrbkz:
16299
0
  case VCVTPH2QQZrrk:
16300
0
  case VCVTPH2QQZrrkz:
16301
0
    return true;
16302
0
  }
16303
0
  return false;
16304
0
}
16305
16306
0
bool isADD(unsigned Opcode) {
16307
0
  switch (Opcode) {
16308
0
  case ADD16i16:
16309
0
  case ADD16mi:
16310
0
  case ADD16mi8:
16311
0
  case ADD16mi8_EVEX:
16312
0
  case ADD16mi8_ND:
16313
0
  case ADD16mi8_NF:
16314
0
  case ADD16mi8_NF_ND:
16315
0
  case ADD16mi_EVEX:
16316
0
  case ADD16mi_ND:
16317
0
  case ADD16mi_NF:
16318
0
  case ADD16mi_NF_ND:
16319
0
  case ADD16mr:
16320
0
  case ADD16mr_EVEX:
16321
0
  case ADD16mr_ND:
16322
0
  case ADD16mr_NF:
16323
0
  case ADD16mr_NF_ND:
16324
0
  case ADD16ri:
16325
0
  case ADD16ri8:
16326
0
  case ADD16ri8_EVEX:
16327
0
  case ADD16ri8_ND:
16328
0
  case ADD16ri8_NF:
16329
0
  case ADD16ri8_NF_ND:
16330
0
  case ADD16ri_EVEX:
16331
0
  case ADD16ri_ND:
16332
0
  case ADD16ri_NF:
16333
0
  case ADD16ri_NF_ND:
16334
0
  case ADD16rm:
16335
0
  case ADD16rm_EVEX:
16336
0
  case ADD16rm_ND:
16337
0
  case ADD16rm_NF:
16338
0
  case ADD16rm_NF_ND:
16339
0
  case ADD16rr:
16340
0
  case ADD16rr_EVEX:
16341
0
  case ADD16rr_EVEX_REV:
16342
0
  case ADD16rr_ND:
16343
0
  case ADD16rr_ND_REV:
16344
0
  case ADD16rr_NF:
16345
0
  case ADD16rr_NF_ND:
16346
0
  case ADD16rr_NF_ND_REV:
16347
0
  case ADD16rr_NF_REV:
16348
0
  case ADD16rr_REV:
16349
0
  case ADD32i32:
16350
0
  case ADD32mi:
16351
0
  case ADD32mi8:
16352
0
  case ADD32mi8_EVEX:
16353
0
  case ADD32mi8_ND:
16354
0
  case ADD32mi8_NF:
16355
0
  case ADD32mi8_NF_ND:
16356
0
  case ADD32mi_EVEX:
16357
0
  case ADD32mi_ND:
16358
0
  case ADD32mi_NF:
16359
0
  case ADD32mi_NF_ND:
16360
0
  case ADD32mr:
16361
0
  case ADD32mr_EVEX:
16362
0
  case ADD32mr_ND:
16363
0
  case ADD32mr_NF:
16364
0
  case ADD32mr_NF_ND:
16365
0
  case ADD32ri:
16366
0
  case ADD32ri8:
16367
0
  case ADD32ri8_EVEX:
16368
0
  case ADD32ri8_ND:
16369
0
  case ADD32ri8_NF:
16370
0
  case ADD32ri8_NF_ND:
16371
0
  case ADD32ri_EVEX:
16372
0
  case ADD32ri_ND:
16373
0
  case ADD32ri_NF:
16374
0
  case ADD32ri_NF_ND:
16375
0
  case ADD32rm:
16376
0
  case ADD32rm_EVEX:
16377
0
  case ADD32rm_ND:
16378
0
  case ADD32rm_NF:
16379
0
  case ADD32rm_NF_ND:
16380
0
  case ADD32rr:
16381
0
  case ADD32rr_EVEX:
16382
0
  case ADD32rr_EVEX_REV:
16383
0
  case ADD32rr_ND:
16384
0
  case ADD32rr_ND_REV:
16385
0
  case ADD32rr_NF:
16386
0
  case ADD32rr_NF_ND:
16387
0
  case ADD32rr_NF_ND_REV:
16388
0
  case ADD32rr_NF_REV:
16389
0
  case ADD32rr_REV:
16390
0
  case ADD64i32:
16391
0
  case ADD64mi32:
16392
0
  case ADD64mi32_EVEX:
16393
0
  case ADD64mi32_ND:
16394
0
  case ADD64mi32_NF:
16395
0
  case ADD64mi32_NF_ND:
16396
0
  case ADD64mi8:
16397
0
  case ADD64mi8_EVEX:
16398
0
  case ADD64mi8_ND:
16399
0
  case ADD64mi8_NF:
16400
0
  case ADD64mi8_NF_ND:
16401
0
  case ADD64mr:
16402
0
  case ADD64mr_EVEX:
16403
0
  case ADD64mr_ND:
16404
0
  case ADD64mr_NF:
16405
0
  case ADD64mr_NF_ND:
16406
0
  case ADD64ri32:
16407
0
  case ADD64ri32_EVEX:
16408
0
  case ADD64ri32_ND:
16409
0
  case ADD64ri32_NF:
16410
0
  case ADD64ri32_NF_ND:
16411
0
  case ADD64ri8:
16412
0
  case ADD64ri8_EVEX:
16413
0
  case ADD64ri8_ND:
16414
0
  case ADD64ri8_NF:
16415
0
  case ADD64ri8_NF_ND:
16416
0
  case ADD64rm:
16417
0
  case ADD64rm_EVEX:
16418
0
  case ADD64rm_ND:
16419
0
  case ADD64rm_NF:
16420
0
  case ADD64rm_NF_ND:
16421
0
  case ADD64rr:
16422
0
  case ADD64rr_EVEX:
16423
0
  case ADD64rr_EVEX_REV:
16424
0
  case ADD64rr_ND:
16425
0
  case ADD64rr_ND_REV:
16426
0
  case ADD64rr_NF:
16427
0
  case ADD64rr_NF_ND:
16428
0
  case ADD64rr_NF_ND_REV:
16429
0
  case ADD64rr_NF_REV:
16430
0
  case ADD64rr_REV:
16431
0
  case ADD8i8:
16432
0
  case ADD8mi:
16433
0
  case ADD8mi8:
16434
0
  case ADD8mi_EVEX:
16435
0
  case ADD8mi_ND:
16436
0
  case ADD8mi_NF:
16437
0
  case ADD8mi_NF_ND:
16438
0
  case ADD8mr:
16439
0
  case ADD8mr_EVEX:
16440
0
  case ADD8mr_ND:
16441
0
  case ADD8mr_NF:
16442
0
  case ADD8mr_NF_ND:
16443
0
  case ADD8ri:
16444
0
  case ADD8ri8:
16445
0
  case ADD8ri_EVEX:
16446
0
  case ADD8ri_ND:
16447
0
  case ADD8ri_NF:
16448
0
  case ADD8ri_NF_ND:
16449
0
  case ADD8rm:
16450
0
  case ADD8rm_EVEX:
16451
0
  case ADD8rm_ND:
16452
0
  case ADD8rm_NF:
16453
0
  case ADD8rm_NF_ND:
16454
0
  case ADD8rr:
16455
0
  case ADD8rr_EVEX:
16456
0
  case ADD8rr_EVEX_REV:
16457
0
  case ADD8rr_ND:
16458
0
  case ADD8rr_ND_REV:
16459
0
  case ADD8rr_NF:
16460
0
  case ADD8rr_NF_ND:
16461
0
  case ADD8rr_NF_ND_REV:
16462
0
  case ADD8rr_NF_REV:
16463
0
  case ADD8rr_REV:
16464
0
    return true;
16465
0
  }
16466
0
  return false;
16467
0
}
16468
16469
0
bool isPSUBSW(unsigned Opcode) {
16470
0
  switch (Opcode) {
16471
0
  case MMX_PSUBSWrm:
16472
0
  case MMX_PSUBSWrr:
16473
0
  case PSUBSWrm:
16474
0
  case PSUBSWrr:
16475
0
    return true;
16476
0
  }
16477
0
  return false;
16478
0
}
16479
16480
0
bool isSIDTW(unsigned Opcode) {
16481
0
  return Opcode == SIDT16m;
16482
0
}
16483
16484
0
bool isVFNMADD231PH(unsigned Opcode) {
16485
0
  switch (Opcode) {
16486
0
  case VFNMADD231PHZ128m:
16487
0
  case VFNMADD231PHZ128mb:
16488
0
  case VFNMADD231PHZ128mbk:
16489
0
  case VFNMADD231PHZ128mbkz:
16490
0
  case VFNMADD231PHZ128mk:
16491
0
  case VFNMADD231PHZ128mkz:
16492
0
  case VFNMADD231PHZ128r:
16493
0
  case VFNMADD231PHZ128rk:
16494
0
  case VFNMADD231PHZ128rkz:
16495
0
  case VFNMADD231PHZ256m:
16496
0
  case VFNMADD231PHZ256mb:
16497
0
  case VFNMADD231PHZ256mbk:
16498
0
  case VFNMADD231PHZ256mbkz:
16499
0
  case VFNMADD231PHZ256mk:
16500
0
  case VFNMADD231PHZ256mkz:
16501
0
  case VFNMADD231PHZ256r:
16502
0
  case VFNMADD231PHZ256rk:
16503
0
  case VFNMADD231PHZ256rkz:
16504
0
  case VFNMADD231PHZm:
16505
0
  case VFNMADD231PHZmb:
16506
0
  case VFNMADD231PHZmbk:
16507
0
  case VFNMADD231PHZmbkz:
16508
0
  case VFNMADD231PHZmk:
16509
0
  case VFNMADD231PHZmkz:
16510
0
  case VFNMADD231PHZr:
16511
0
  case VFNMADD231PHZrb:
16512
0
  case VFNMADD231PHZrbk:
16513
0
  case VFNMADD231PHZrbkz:
16514
0
  case VFNMADD231PHZrk:
16515
0
  case VFNMADD231PHZrkz:
16516
0
    return true;
16517
0
  }
16518
0
  return false;
16519
0
}
16520
16521
0
bool isVEXTRACTF64X2(unsigned Opcode) {
16522
0
  switch (Opcode) {
16523
0
  case VEXTRACTF64x2Z256mr:
16524
0
  case VEXTRACTF64x2Z256mrk:
16525
0
  case VEXTRACTF64x2Z256rr:
16526
0
  case VEXTRACTF64x2Z256rrk:
16527
0
  case VEXTRACTF64x2Z256rrkz:
16528
0
  case VEXTRACTF64x2Zmr:
16529
0
  case VEXTRACTF64x2Zmrk:
16530
0
  case VEXTRACTF64x2Zrr:
16531
0
  case VEXTRACTF64x2Zrrk:
16532
0
  case VEXTRACTF64x2Zrrkz:
16533
0
    return true;
16534
0
  }
16535
0
  return false;
16536
0
}
16537
16538
0
bool isFCOMI(unsigned Opcode) {
16539
0
  return Opcode == COM_FIr;
16540
0
}
16541
16542
0
bool isRSM(unsigned Opcode) {
16543
0
  return Opcode == RSM;
16544
0
}
16545
16546
0
bool isVPCOMUD(unsigned Opcode) {
16547
0
  switch (Opcode) {
16548
0
  case VPCOMUDmi:
16549
0
  case VPCOMUDri:
16550
0
    return true;
16551
0
  }
16552
0
  return false;
16553
0
}
16554
16555
0
bool isVPMOVZXBQ(unsigned Opcode) {
16556
0
  switch (Opcode) {
16557
0
  case VPMOVZXBQYrm:
16558
0
  case VPMOVZXBQYrr:
16559
0
  case VPMOVZXBQZ128rm:
16560
0
  case VPMOVZXBQZ128rmk:
16561
0
  case VPMOVZXBQZ128rmkz:
16562
0
  case VPMOVZXBQZ128rr:
16563
0
  case VPMOVZXBQZ128rrk:
16564
0
  case VPMOVZXBQZ128rrkz:
16565
0
  case VPMOVZXBQZ256rm:
16566
0
  case VPMOVZXBQZ256rmk:
16567
0
  case VPMOVZXBQZ256rmkz:
16568
0
  case VPMOVZXBQZ256rr:
16569
0
  case VPMOVZXBQZ256rrk:
16570
0
  case VPMOVZXBQZ256rrkz:
16571
0
  case VPMOVZXBQZrm:
16572
0
  case VPMOVZXBQZrmk:
16573
0
  case VPMOVZXBQZrmkz:
16574
0
  case VPMOVZXBQZrr:
16575
0
  case VPMOVZXBQZrrk:
16576
0
  case VPMOVZXBQZrrkz:
16577
0
  case VPMOVZXBQrm:
16578
0
  case VPMOVZXBQrr:
16579
0
    return true;
16580
0
  }
16581
0
  return false;
16582
0
}
16583
16584
0
bool isUWRMSR(unsigned Opcode) {
16585
0
  switch (Opcode) {
16586
0
  case UWRMSRir:
16587
0
  case UWRMSRrr:
16588
0
    return true;
16589
0
  }
16590
0
  return false;
16591
0
}
16592
16593
0
bool isLGS(unsigned Opcode) {
16594
0
  switch (Opcode) {
16595
0
  case LGS16rm:
16596
0
  case LGS32rm:
16597
0
  case LGS64rm:
16598
0
    return true;
16599
0
  }
16600
0
  return false;
16601
0
}
16602
16603
0
bool isVMOVNTPD(unsigned Opcode) {
16604
0
  switch (Opcode) {
16605
0
  case VMOVNTPDYmr:
16606
0
  case VMOVNTPDZ128mr:
16607
0
  case VMOVNTPDZ256mr:
16608
0
  case VMOVNTPDZmr:
16609
0
  case VMOVNTPDmr:
16610
0
    return true;
16611
0
  }
16612
0
  return false;
16613
0
}
16614
16615
0
bool isRDPRU(unsigned Opcode) {
16616
0
  return Opcode == RDPRU;
16617
0
}
16618
16619
0
bool isVPUNPCKHBW(unsigned Opcode) {
16620
0
  switch (Opcode) {
16621
0
  case VPUNPCKHBWYrm:
16622
0
  case VPUNPCKHBWYrr:
16623
0
  case VPUNPCKHBWZ128rm:
16624
0
  case VPUNPCKHBWZ128rmk:
16625
0
  case VPUNPCKHBWZ128rmkz:
16626
0
  case VPUNPCKHBWZ128rr:
16627
0
  case VPUNPCKHBWZ128rrk:
16628
0
  case VPUNPCKHBWZ128rrkz:
16629
0
  case VPUNPCKHBWZ256rm:
16630
0
  case VPUNPCKHBWZ256rmk:
16631
0
  case VPUNPCKHBWZ256rmkz:
16632
0
  case VPUNPCKHBWZ256rr:
16633
0
  case VPUNPCKHBWZ256rrk:
16634
0
  case VPUNPCKHBWZ256rrkz:
16635
0
  case VPUNPCKHBWZrm:
16636
0
  case VPUNPCKHBWZrmk:
16637
0
  case VPUNPCKHBWZrmkz:
16638
0
  case VPUNPCKHBWZrr:
16639
0
  case VPUNPCKHBWZrrk:
16640
0
  case VPUNPCKHBWZrrkz:
16641
0
  case VPUNPCKHBWrm:
16642
0
  case VPUNPCKHBWrr:
16643
0
    return true;
16644
0
  }
16645
0
  return false;
16646
0
}
16647
16648
0
bool isANDN(unsigned Opcode) {
16649
0
  switch (Opcode) {
16650
0
  case ANDN32rm:
16651
0
  case ANDN32rm_EVEX:
16652
0
  case ANDN32rr:
16653
0
  case ANDN32rr_EVEX:
16654
0
  case ANDN64rm:
16655
0
  case ANDN64rm_EVEX:
16656
0
  case ANDN64rr:
16657
0
  case ANDN64rr_EVEX:
16658
0
    return true;
16659
0
  }
16660
0
  return false;
16661
0
}
16662
16663
0
bool isVCVTTPH2UW(unsigned Opcode) {
16664
0
  switch (Opcode) {
16665
0
  case VCVTTPH2UWZ128rm:
16666
0
  case VCVTTPH2UWZ128rmb:
16667
0
  case VCVTTPH2UWZ128rmbk:
16668
0
  case VCVTTPH2UWZ128rmbkz:
16669
0
  case VCVTTPH2UWZ128rmk:
16670
0
  case VCVTTPH2UWZ128rmkz:
16671
0
  case VCVTTPH2UWZ128rr:
16672
0
  case VCVTTPH2UWZ128rrk:
16673
0
  case VCVTTPH2UWZ128rrkz:
16674
0
  case VCVTTPH2UWZ256rm:
16675
0
  case VCVTTPH2UWZ256rmb:
16676
0
  case VCVTTPH2UWZ256rmbk:
16677
0
  case VCVTTPH2UWZ256rmbkz:
16678
0
  case VCVTTPH2UWZ256rmk:
16679
0
  case VCVTTPH2UWZ256rmkz:
16680
0
  case VCVTTPH2UWZ256rr:
16681
0
  case VCVTTPH2UWZ256rrk:
16682
0
  case VCVTTPH2UWZ256rrkz:
16683
0
  case VCVTTPH2UWZrm:
16684
0
  case VCVTTPH2UWZrmb:
16685
0
  case VCVTTPH2UWZrmbk:
16686
0
  case VCVTTPH2UWZrmbkz:
16687
0
  case VCVTTPH2UWZrmk:
16688
0
  case VCVTTPH2UWZrmkz:
16689
0
  case VCVTTPH2UWZrr:
16690
0
  case VCVTTPH2UWZrrb:
16691
0
  case VCVTTPH2UWZrrbk:
16692
0
  case VCVTTPH2UWZrrbkz:
16693
0
  case VCVTTPH2UWZrrk:
16694
0
  case VCVTTPH2UWZrrkz:
16695
0
    return true;
16696
0
  }
16697
0
  return false;
16698
0
}
16699
16700
0
bool isVMFUNC(unsigned Opcode) {
16701
0
  return Opcode == VMFUNC;
16702
0
}
16703
16704
0
bool isFIMUL(unsigned Opcode) {
16705
0
  switch (Opcode) {
16706
0
  case MUL_FI16m:
16707
0
  case MUL_FI32m:
16708
0
    return true;
16709
0
  }
16710
0
  return false;
16711
0
}
16712
16713
0
bool isBLCFILL(unsigned Opcode) {
16714
0
  switch (Opcode) {
16715
0
  case BLCFILL32rm:
16716
0
  case BLCFILL32rr:
16717
0
  case BLCFILL64rm:
16718
0
  case BLCFILL64rr:
16719
0
    return true;
16720
0
  }
16721
0
  return false;
16722
0
}
16723
16724
0
bool isVGATHERPF0DPS(unsigned Opcode) {
16725
0
  return Opcode == VGATHERPF0DPSm;
16726
0
}
16727
16728
0
bool isVFMSUBADD231PS(unsigned Opcode) {
16729
0
  switch (Opcode) {
16730
0
  case VFMSUBADD231PSYm:
16731
0
  case VFMSUBADD231PSYr:
16732
0
  case VFMSUBADD231PSZ128m:
16733
0
  case VFMSUBADD231PSZ128mb:
16734
0
  case VFMSUBADD231PSZ128mbk:
16735
0
  case VFMSUBADD231PSZ128mbkz:
16736
0
  case VFMSUBADD231PSZ128mk:
16737
0
  case VFMSUBADD231PSZ128mkz:
16738
0
  case VFMSUBADD231PSZ128r:
16739
0
  case VFMSUBADD231PSZ128rk:
16740
0
  case VFMSUBADD231PSZ128rkz:
16741
0
  case VFMSUBADD231PSZ256m:
16742
0
  case VFMSUBADD231PSZ256mb:
16743
0
  case VFMSUBADD231PSZ256mbk:
16744
0
  case VFMSUBADD231PSZ256mbkz:
16745
0
  case VFMSUBADD231PSZ256mk:
16746
0
  case VFMSUBADD231PSZ256mkz:
16747
0
  case VFMSUBADD231PSZ256r:
16748
0
  case VFMSUBADD231PSZ256rk:
16749
0
  case VFMSUBADD231PSZ256rkz:
16750
0
  case VFMSUBADD231PSZm:
16751
0
  case VFMSUBADD231PSZmb:
16752
0
  case VFMSUBADD231PSZmbk:
16753
0
  case VFMSUBADD231PSZmbkz:
16754
0
  case VFMSUBADD231PSZmk:
16755
0
  case VFMSUBADD231PSZmkz:
16756
0
  case VFMSUBADD231PSZr:
16757
0
  case VFMSUBADD231PSZrb:
16758
0
  case VFMSUBADD231PSZrbk:
16759
0
  case VFMSUBADD231PSZrbkz:
16760
0
  case VFMSUBADD231PSZrk:
16761
0
  case VFMSUBADD231PSZrkz:
16762
0
  case VFMSUBADD231PSm:
16763
0
  case VFMSUBADD231PSr:
16764
0
    return true;
16765
0
  }
16766
0
  return false;
16767
0
}
16768
16769
0
bool isVREDUCESD(unsigned Opcode) {
16770
0
  switch (Opcode) {
16771
0
  case VREDUCESDZrmi:
16772
0
  case VREDUCESDZrmik:
16773
0
  case VREDUCESDZrmikz:
16774
0
  case VREDUCESDZrri:
16775
0
  case VREDUCESDZrrib:
16776
0
  case VREDUCESDZrribk:
16777
0
  case VREDUCESDZrribkz:
16778
0
  case VREDUCESDZrrik:
16779
0
  case VREDUCESDZrrikz:
16780
0
    return true;
16781
0
  }
16782
0
  return false;
16783
0
}
16784
16785
0
bool isVXORPS(unsigned Opcode) {
16786
0
  switch (Opcode) {
16787
0
  case VXORPSYrm:
16788
0
  case VXORPSYrr:
16789
0
  case VXORPSZ128rm:
16790
0
  case VXORPSZ128rmb:
16791
0
  case VXORPSZ128rmbk:
16792
0
  case VXORPSZ128rmbkz:
16793
0
  case VXORPSZ128rmk:
16794
0
  case VXORPSZ128rmkz:
16795
0
  case VXORPSZ128rr:
16796
0
  case VXORPSZ128rrk:
16797
0
  case VXORPSZ128rrkz:
16798
0
  case VXORPSZ256rm:
16799
0
  case VXORPSZ256rmb:
16800
0
  case VXORPSZ256rmbk:
16801
0
  case VXORPSZ256rmbkz:
16802
0
  case VXORPSZ256rmk:
16803
0
  case VXORPSZ256rmkz:
16804
0
  case VXORPSZ256rr:
16805
0
  case VXORPSZ256rrk:
16806
0
  case VXORPSZ256rrkz:
16807
0
  case VXORPSZrm:
16808
0
  case VXORPSZrmb:
16809
0
  case VXORPSZrmbk:
16810
0
  case VXORPSZrmbkz:
16811
0
  case VXORPSZrmk:
16812
0
  case VXORPSZrmkz:
16813
0
  case VXORPSZrr:
16814
0
  case VXORPSZrrk:
16815
0
  case VXORPSZrrkz:
16816
0
  case VXORPSrm:
16817
0
  case VXORPSrr:
16818
0
    return true;
16819
0
  }
16820
0
  return false;
16821
0
}
16822
16823
0
bool isPSWAPD(unsigned Opcode) {
16824
0
  switch (Opcode) {
16825
0
  case PSWAPDrm:
16826
0
  case PSWAPDrr:
16827
0
    return true;
16828
0
  }
16829
0
  return false;
16830
0
}
16831
16832
0
bool isPMAXSD(unsigned Opcode) {
16833
0
  switch (Opcode) {
16834
0
  case PMAXSDrm:
16835
0
  case PMAXSDrr:
16836
0
    return true;
16837
0
  }
16838
0
  return false;
16839
0
}
16840
16841
0
bool isVCMPSS(unsigned Opcode) {
16842
0
  switch (Opcode) {
16843
0
  case VCMPSSZrm_Int:
16844
0
  case VCMPSSZrm_Intk:
16845
0
  case VCMPSSZrr_Int:
16846
0
  case VCMPSSZrr_Intk:
16847
0
  case VCMPSSZrrb_Int:
16848
0
  case VCMPSSZrrb_Intk:
16849
0
  case VCMPSSrm_Int:
16850
0
  case VCMPSSrr_Int:
16851
0
    return true;
16852
0
  }
16853
0
  return false;
16854
0
}
16855
16856
0
bool isEXTRACTPS(unsigned Opcode) {
16857
0
  switch (Opcode) {
16858
0
  case EXTRACTPSmr:
16859
0
  case EXTRACTPSrr:
16860
0
    return true;
16861
0
  }
16862
0
  return false;
16863
0
}
16864
16865
0
bool isVPMOVZXBD(unsigned Opcode) {
16866
0
  switch (Opcode) {
16867
0
  case VPMOVZXBDYrm:
16868
0
  case VPMOVZXBDYrr:
16869
0
  case VPMOVZXBDZ128rm:
16870
0
  case VPMOVZXBDZ128rmk:
16871
0
  case VPMOVZXBDZ128rmkz:
16872
0
  case VPMOVZXBDZ128rr:
16873
0
  case VPMOVZXBDZ128rrk:
16874
0
  case VPMOVZXBDZ128rrkz:
16875
0
  case VPMOVZXBDZ256rm:
16876
0
  case VPMOVZXBDZ256rmk:
16877
0
  case VPMOVZXBDZ256rmkz:
16878
0
  case VPMOVZXBDZ256rr:
16879
0
  case VPMOVZXBDZ256rrk:
16880
0
  case VPMOVZXBDZ256rrkz:
16881
0
  case VPMOVZXBDZrm:
16882
0
  case VPMOVZXBDZrmk:
16883
0
  case VPMOVZXBDZrmkz:
16884
0
  case VPMOVZXBDZrr:
16885
0
  case VPMOVZXBDZrrk:
16886
0
  case VPMOVZXBDZrrkz:
16887
0
  case VPMOVZXBDrm:
16888
0
  case VPMOVZXBDrr:
16889
0
    return true;
16890
0
  }
16891
0
  return false;
16892
0
}
16893
16894
0
bool isOUTSW(unsigned Opcode) {
16895
0
  return Opcode == OUTSW;
16896
0
}
16897
16898
0
bool isKORTESTB(unsigned Opcode) {
16899
0
  return Opcode == KORTESTBrr;
16900
0
}
16901
16902
0
bool isVREDUCEPS(unsigned Opcode) {
16903
0
  switch (Opcode) {
16904
0
  case VREDUCEPSZ128rmbi:
16905
0
  case VREDUCEPSZ128rmbik:
16906
0
  case VREDUCEPSZ128rmbikz:
16907
0
  case VREDUCEPSZ128rmi:
16908
0
  case VREDUCEPSZ128rmik:
16909
0
  case VREDUCEPSZ128rmikz:
16910
0
  case VREDUCEPSZ128rri:
16911
0
  case VREDUCEPSZ128rrik:
16912
0
  case VREDUCEPSZ128rrikz:
16913
0
  case VREDUCEPSZ256rmbi:
16914
0
  case VREDUCEPSZ256rmbik:
16915
0
  case VREDUCEPSZ256rmbikz:
16916
0
  case VREDUCEPSZ256rmi:
16917
0
  case VREDUCEPSZ256rmik:
16918
0
  case VREDUCEPSZ256rmikz:
16919
0
  case VREDUCEPSZ256rri:
16920
0
  case VREDUCEPSZ256rrik:
16921
0
  case VREDUCEPSZ256rrikz:
16922
0
  case VREDUCEPSZrmbi:
16923
0
  case VREDUCEPSZrmbik:
16924
0
  case VREDUCEPSZrmbikz:
16925
0
  case VREDUCEPSZrmi:
16926
0
  case VREDUCEPSZrmik:
16927
0
  case VREDUCEPSZrmikz:
16928
0
  case VREDUCEPSZrri:
16929
0
  case VREDUCEPSZrrib:
16930
0
  case VREDUCEPSZrribk:
16931
0
  case VREDUCEPSZrribkz:
16932
0
  case VREDUCEPSZrrik:
16933
0
  case VREDUCEPSZrrikz:
16934
0
    return true;
16935
0
  }
16936
0
  return false;
16937
0
}
16938
16939
0
bool isPEXTRW(unsigned Opcode) {
16940
0
  switch (Opcode) {
16941
0
  case MMX_PEXTRWrr:
16942
0
  case PEXTRWmr:
16943
0
  case PEXTRWrr:
16944
0
  case PEXTRWrr_REV:
16945
0
    return true;
16946
0
  }
16947
0
  return false;
16948
0
}
16949
16950
0
bool isFNINIT(unsigned Opcode) {
16951
0
  return Opcode == FNINIT;
16952
0
}
16953
16954
0
bool isROL(unsigned Opcode) {
16955
0
  switch (Opcode) {
16956
0
  case ROL16m1:
16957
0
  case ROL16mCL:
16958
0
  case ROL16mi:
16959
0
  case ROL16r1:
16960
0
  case ROL16rCL:
16961
0
  case ROL16ri:
16962
0
  case ROL32m1:
16963
0
  case ROL32mCL:
16964
0
  case ROL32mi:
16965
0
  case ROL32r1:
16966
0
  case ROL32rCL:
16967
0
  case ROL32ri:
16968
0
  case ROL64m1:
16969
0
  case ROL64mCL:
16970
0
  case ROL64mi:
16971
0
  case ROL64r1:
16972
0
  case ROL64rCL:
16973
0
  case ROL64ri:
16974
0
  case ROL8m1:
16975
0
  case ROL8mCL:
16976
0
  case ROL8mi:
16977
0
  case ROL8r1:
16978
0
  case ROL8rCL:
16979
0
  case ROL8ri:
16980
0
    return true;
16981
0
  }
16982
0
  return false;
16983
0
}
16984
16985
0
bool isVCVTPS2QQ(unsigned Opcode) {
16986
0
  switch (Opcode) {
16987
0
  case VCVTPS2QQZ128rm:
16988
0
  case VCVTPS2QQZ128rmb:
16989
0
  case VCVTPS2QQZ128rmbk:
16990
0
  case VCVTPS2QQZ128rmbkz:
16991
0
  case VCVTPS2QQZ128rmk:
16992
0
  case VCVTPS2QQZ128rmkz:
16993
0
  case VCVTPS2QQZ128rr:
16994
0
  case VCVTPS2QQZ128rrk:
16995
0
  case VCVTPS2QQZ128rrkz:
16996
0
  case VCVTPS2QQZ256rm:
16997
0
  case VCVTPS2QQZ256rmb:
16998
0
  case VCVTPS2QQZ256rmbk:
16999
0
  case VCVTPS2QQZ256rmbkz:
17000
0
  case VCVTPS2QQZ256rmk:
17001
0
  case VCVTPS2QQZ256rmkz:
17002
0
  case VCVTPS2QQZ256rr:
17003
0
  case VCVTPS2QQZ256rrk:
17004
0
  case VCVTPS2QQZ256rrkz:
17005
0
  case VCVTPS2QQZrm:
17006
0
  case VCVTPS2QQZrmb:
17007
0
  case VCVTPS2QQZrmbk:
17008
0
  case VCVTPS2QQZrmbkz:
17009
0
  case VCVTPS2QQZrmk:
17010
0
  case VCVTPS2QQZrmkz:
17011
0
  case VCVTPS2QQZrr:
17012
0
  case VCVTPS2QQZrrb:
17013
0
  case VCVTPS2QQZrrbk:
17014
0
  case VCVTPS2QQZrrbkz:
17015
0
  case VCVTPS2QQZrrk:
17016
0
  case VCVTPS2QQZrrkz:
17017
0
    return true;
17018
0
  }
17019
0
  return false;
17020
0
}
17021
17022
0
bool isVGETMANTPH(unsigned Opcode) {
17023
0
  switch (Opcode) {
17024
0
  case VGETMANTPHZ128rmbi:
17025
0
  case VGETMANTPHZ128rmbik:
17026
0
  case VGETMANTPHZ128rmbikz:
17027
0
  case VGETMANTPHZ128rmi:
17028
0
  case VGETMANTPHZ128rmik:
17029
0
  case VGETMANTPHZ128rmikz:
17030
0
  case VGETMANTPHZ128rri:
17031
0
  case VGETMANTPHZ128rrik:
17032
0
  case VGETMANTPHZ128rrikz:
17033
0
  case VGETMANTPHZ256rmbi:
17034
0
  case VGETMANTPHZ256rmbik:
17035
0
  case VGETMANTPHZ256rmbikz:
17036
0
  case VGETMANTPHZ256rmi:
17037
0
  case VGETMANTPHZ256rmik:
17038
0
  case VGETMANTPHZ256rmikz:
17039
0
  case VGETMANTPHZ256rri:
17040
0
  case VGETMANTPHZ256rrik:
17041
0
  case VGETMANTPHZ256rrikz:
17042
0
  case VGETMANTPHZrmbi:
17043
0
  case VGETMANTPHZrmbik:
17044
0
  case VGETMANTPHZrmbikz:
17045
0
  case VGETMANTPHZrmi:
17046
0
  case VGETMANTPHZrmik:
17047
0
  case VGETMANTPHZrmikz:
17048
0
  case VGETMANTPHZrri:
17049
0
  case VGETMANTPHZrrib:
17050
0
  case VGETMANTPHZrribk:
17051
0
  case VGETMANTPHZrribkz:
17052
0
  case VGETMANTPHZrrik:
17053
0
  case VGETMANTPHZrrikz:
17054
0
    return true;
17055
0
  }
17056
0
  return false;
17057
0
}
17058
17059
0
bool isPUNPCKLDQ(unsigned Opcode) {
17060
0
  switch (Opcode) {
17061
0
  case MMX_PUNPCKLDQrm:
17062
0
  case MMX_PUNPCKLDQrr:
17063
0
  case PUNPCKLDQrm:
17064
0
  case PUNPCKLDQrr:
17065
0
    return true;
17066
0
  }
17067
0
  return false;
17068
0
}
17069
17070
0
bool isPADDD(unsigned Opcode) {
17071
0
  switch (Opcode) {
17072
0
  case MMX_PADDDrm:
17073
0
  case MMX_PADDDrr:
17074
0
  case PADDDrm:
17075
0
  case PADDDrr:
17076
0
    return true;
17077
0
  }
17078
0
  return false;
17079
0
}
17080
17081
0
bool isVPSLLD(unsigned Opcode) {
17082
0
  switch (Opcode) {
17083
0
  case VPSLLDYri:
17084
0
  case VPSLLDYrm:
17085
0
  case VPSLLDYrr:
17086
0
  case VPSLLDZ128mbi:
17087
0
  case VPSLLDZ128mbik:
17088
0
  case VPSLLDZ128mbikz:
17089
0
  case VPSLLDZ128mi:
17090
0
  case VPSLLDZ128mik:
17091
0
  case VPSLLDZ128mikz:
17092
0
  case VPSLLDZ128ri:
17093
0
  case VPSLLDZ128rik:
17094
0
  case VPSLLDZ128rikz:
17095
0
  case VPSLLDZ128rm:
17096
0
  case VPSLLDZ128rmk:
17097
0
  case VPSLLDZ128rmkz:
17098
0
  case VPSLLDZ128rr:
17099
0
  case VPSLLDZ128rrk:
17100
0
  case VPSLLDZ128rrkz:
17101
0
  case VPSLLDZ256mbi:
17102
0
  case VPSLLDZ256mbik:
17103
0
  case VPSLLDZ256mbikz:
17104
0
  case VPSLLDZ256mi:
17105
0
  case VPSLLDZ256mik:
17106
0
  case VPSLLDZ256mikz:
17107
0
  case VPSLLDZ256ri:
17108
0
  case VPSLLDZ256rik:
17109
0
  case VPSLLDZ256rikz:
17110
0
  case VPSLLDZ256rm:
17111
0
  case VPSLLDZ256rmk:
17112
0
  case VPSLLDZ256rmkz:
17113
0
  case VPSLLDZ256rr:
17114
0
  case VPSLLDZ256rrk:
17115
0
  case VPSLLDZ256rrkz:
17116
0
  case VPSLLDZmbi:
17117
0
  case VPSLLDZmbik:
17118
0
  case VPSLLDZmbikz:
17119
0
  case VPSLLDZmi:
17120
0
  case VPSLLDZmik:
17121
0
  case VPSLLDZmikz:
17122
0
  case VPSLLDZri:
17123
0
  case VPSLLDZrik:
17124
0
  case VPSLLDZrikz:
17125
0
  case VPSLLDZrm:
17126
0
  case VPSLLDZrmk:
17127
0
  case VPSLLDZrmkz:
17128
0
  case VPSLLDZrr:
17129
0
  case VPSLLDZrrk:
17130
0
  case VPSLLDZrrkz:
17131
0
  case VPSLLDri:
17132
0
  case VPSLLDrm:
17133
0
  case VPSLLDrr:
17134
0
    return true;
17135
0
  }
17136
0
  return false;
17137
0
}
17138
17139
0
bool isPFCMPGE(unsigned Opcode) {
17140
0
  switch (Opcode) {
17141
0
  case PFCMPGErm:
17142
0
  case PFCMPGErr:
17143
0
    return true;
17144
0
  }
17145
0
  return false;
17146
0
}
17147
17148
0
bool isVPMOVM2D(unsigned Opcode) {
17149
0
  switch (Opcode) {
17150
0
  case VPMOVM2DZ128rr:
17151
0
  case VPMOVM2DZ256rr:
17152
0
  case VPMOVM2DZrr:
17153
0
    return true;
17154
0
  }
17155
0
  return false;
17156
0
}
17157
17158
0
bool isVHSUBPS(unsigned Opcode) {
17159
0
  switch (Opcode) {
17160
0
  case VHSUBPSYrm:
17161
0
  case VHSUBPSYrr:
17162
0
  case VHSUBPSrm:
17163
0
  case VHSUBPSrr:
17164
0
    return true;
17165
0
  }
17166
0
  return false;
17167
0
}
17168
17169
0
bool isENDBR32(unsigned Opcode) {
17170
0
  return Opcode == ENDBR32;
17171
0
}
17172
17173
0
bool isMOVSXD(unsigned Opcode) {
17174
0
  switch (Opcode) {
17175
0
  case MOVSX16rm32:
17176
0
  case MOVSX16rr32:
17177
0
  case MOVSX32rm32:
17178
0
  case MOVSX32rr32:
17179
0
  case MOVSX64rm32:
17180
0
  case MOVSX64rr32:
17181
0
    return true;
17182
0
  }
17183
0
  return false;
17184
0
}
17185
17186
0
bool isPSIGND(unsigned Opcode) {
17187
0
  switch (Opcode) {
17188
0
  case MMX_PSIGNDrm:
17189
0
  case MMX_PSIGNDrr:
17190
0
  case PSIGNDrm:
17191
0
  case PSIGNDrr:
17192
0
    return true;
17193
0
  }
17194
0
  return false;
17195
0
}
17196
17197
0
bool isVPTEST(unsigned Opcode) {
17198
0
  switch (Opcode) {
17199
0
  case VPTESTYrm:
17200
0
  case VPTESTYrr:
17201
0
  case VPTESTrm:
17202
0
  case VPTESTrr:
17203
0
    return true;
17204
0
  }
17205
0
  return false;
17206
0
}
17207
17208
0
bool isVPDPWUSD(unsigned Opcode) {
17209
0
  switch (Opcode) {
17210
0
  case VPDPWUSDYrm:
17211
0
  case VPDPWUSDYrr:
17212
0
  case VPDPWUSDrm:
17213
0
  case VPDPWUSDrr:
17214
0
    return true;
17215
0
  }
17216
0
  return false;
17217
0
}
17218
17219
0
bool isHSUBPD(unsigned Opcode) {
17220
0
  switch (Opcode) {
17221
0
  case HSUBPDrm:
17222
0
  case HSUBPDrr:
17223
0
    return true;
17224
0
  }
17225
0
  return false;
17226
0
}
17227
17228
0
bool isADCX(unsigned Opcode) {
17229
0
  switch (Opcode) {
17230
0
  case ADCX32rm:
17231
0
  case ADCX32rm_EVEX:
17232
0
  case ADCX32rm_ND:
17233
0
  case ADCX32rr:
17234
0
  case ADCX32rr_EVEX:
17235
0
  case ADCX32rr_ND:
17236
0
  case ADCX64rm:
17237
0
  case ADCX64rm_EVEX:
17238
0
  case ADCX64rm_ND:
17239
0
  case ADCX64rr:
17240
0
  case ADCX64rr_EVEX:
17241
0
  case ADCX64rr_ND:
17242
0
    return true;
17243
0
  }
17244
0
  return false;
17245
0
}
17246
17247
0
bool isCVTTPD2PI(unsigned Opcode) {
17248
0
  switch (Opcode) {
17249
0
  case MMX_CVTTPD2PIrm:
17250
0
  case MMX_CVTTPD2PIrr:
17251
0
    return true;
17252
0
  }
17253
0
  return false;
17254
0
}
17255
17256
0
bool isPDEP(unsigned Opcode) {
17257
0
  switch (Opcode) {
17258
0
  case PDEP32rm:
17259
0
  case PDEP32rm_EVEX:
17260
0
  case PDEP32rr:
17261
0
  case PDEP32rr_EVEX:
17262
0
  case PDEP64rm:
17263
0
  case PDEP64rm_EVEX:
17264
0
  case PDEP64rr:
17265
0
  case PDEP64rr_EVEX:
17266
0
    return true;
17267
0
  }
17268
0
  return false;
17269
0
}
17270
17271
0
bool isTDPBUSD(unsigned Opcode) {
17272
0
  return Opcode == TDPBUSD;
17273
0
}
17274
17275
0
bool isVBROADCASTI32X4(unsigned Opcode) {
17276
0
  switch (Opcode) {
17277
0
  case VBROADCASTI32X4Z256rm:
17278
0
  case VBROADCASTI32X4Z256rmk:
17279
0
  case VBROADCASTI32X4Z256rmkz:
17280
0
  case VBROADCASTI32X4rm:
17281
0
  case VBROADCASTI32X4rmk:
17282
0
  case VBROADCASTI32X4rmkz:
17283
0
    return true;
17284
0
  }
17285
0
  return false;
17286
0
}
17287
17288
0
bool isVCVTPH2UDQ(unsigned Opcode) {
17289
0
  switch (Opcode) {
17290
0
  case VCVTPH2UDQZ128rm:
17291
0
  case VCVTPH2UDQZ128rmb:
17292
0
  case VCVTPH2UDQZ128rmbk:
17293
0
  case VCVTPH2UDQZ128rmbkz:
17294
0
  case VCVTPH2UDQZ128rmk:
17295
0
  case VCVTPH2UDQZ128rmkz:
17296
0
  case VCVTPH2UDQZ128rr:
17297
0
  case VCVTPH2UDQZ128rrk:
17298
0
  case VCVTPH2UDQZ128rrkz:
17299
0
  case VCVTPH2UDQZ256rm:
17300
0
  case VCVTPH2UDQZ256rmb:
17301
0
  case VCVTPH2UDQZ256rmbk:
17302
0
  case VCVTPH2UDQZ256rmbkz:
17303
0
  case VCVTPH2UDQZ256rmk:
17304
0
  case VCVTPH2UDQZ256rmkz:
17305
0
  case VCVTPH2UDQZ256rr:
17306
0
  case VCVTPH2UDQZ256rrk:
17307
0
  case VCVTPH2UDQZ256rrkz:
17308
0
  case VCVTPH2UDQZrm:
17309
0
  case VCVTPH2UDQZrmb:
17310
0
  case VCVTPH2UDQZrmbk:
17311
0
  case VCVTPH2UDQZrmbkz:
17312
0
  case VCVTPH2UDQZrmk:
17313
0
  case VCVTPH2UDQZrmkz:
17314
0
  case VCVTPH2UDQZrr:
17315
0
  case VCVTPH2UDQZrrb:
17316
0
  case VCVTPH2UDQZrrbk:
17317
0
  case VCVTPH2UDQZrrbkz:
17318
0
  case VCVTPH2UDQZrrk:
17319
0
  case VCVTPH2UDQZrrkz:
17320
0
    return true;
17321
0
  }
17322
0
  return false;
17323
0
}
17324
17325
0
bool isVPHADDW(unsigned Opcode) {
17326
0
  switch (Opcode) {
17327
0
  case VPHADDWYrm:
17328
0
  case VPHADDWYrr:
17329
0
  case VPHADDWrm:
17330
0
  case VPHADDWrr:
17331
0
    return true;
17332
0
  }
17333
0
  return false;
17334
0
}
17335
17336
0
bool isFLDL2E(unsigned Opcode) {
17337
0
  return Opcode == FLDL2E;
17338
0
}
17339
17340
0
bool isCLZERO(unsigned Opcode) {
17341
0
  switch (Opcode) {
17342
0
  case CLZERO32r:
17343
0
  case CLZERO64r:
17344
0
    return true;
17345
0
  }
17346
0
  return false;
17347
0
}
17348
17349
0
bool isPBLENDW(unsigned Opcode) {
17350
0
  switch (Opcode) {
17351
0
  case PBLENDWrmi:
17352
0
  case PBLENDWrri:
17353
0
    return true;
17354
0
  }
17355
0
  return false;
17356
0
}
17357
17358
0
bool isVCVTSH2USI(unsigned Opcode) {
17359
0
  switch (Opcode) {
17360
0
  case VCVTSH2USI64Zrm_Int:
17361
0
  case VCVTSH2USI64Zrr_Int:
17362
0
  case VCVTSH2USI64Zrrb_Int:
17363
0
  case VCVTSH2USIZrm_Int:
17364
0
  case VCVTSH2USIZrr_Int:
17365
0
  case VCVTSH2USIZrrb_Int:
17366
0
    return true;
17367
0
  }
17368
0
  return false;
17369
0
}
17370
17371
0
bool isVANDPD(unsigned Opcode) {
17372
0
  switch (Opcode) {
17373
0
  case VANDPDYrm:
17374
0
  case VANDPDYrr:
17375
0
  case VANDPDZ128rm:
17376
0
  case VANDPDZ128rmb:
17377
0
  case VANDPDZ128rmbk:
17378
0
  case VANDPDZ128rmbkz:
17379
0
  case VANDPDZ128rmk:
17380
0
  case VANDPDZ128rmkz:
17381
0
  case VANDPDZ128rr:
17382
0
  case VANDPDZ128rrk:
17383
0
  case VANDPDZ128rrkz:
17384
0
  case VANDPDZ256rm:
17385
0
  case VANDPDZ256rmb:
17386
0
  case VANDPDZ256rmbk:
17387
0
  case VANDPDZ256rmbkz:
17388
0
  case VANDPDZ256rmk:
17389
0
  case VANDPDZ256rmkz:
17390
0
  case VANDPDZ256rr:
17391
0
  case VANDPDZ256rrk:
17392
0
  case VANDPDZ256rrkz:
17393
0
  case VANDPDZrm:
17394
0
  case VANDPDZrmb:
17395
0
  case VANDPDZrmbk:
17396
0
  case VANDPDZrmbkz:
17397
0
  case VANDPDZrmk:
17398
0
  case VANDPDZrmkz:
17399
0
  case VANDPDZrr:
17400
0
  case VANDPDZrrk:
17401
0
  case VANDPDZrrkz:
17402
0
  case VANDPDrm:
17403
0
  case VANDPDrr:
17404
0
    return true;
17405
0
  }
17406
0
  return false;
17407
0
}
17408
17409
0
bool isBEXTR(unsigned Opcode) {
17410
0
  switch (Opcode) {
17411
0
  case BEXTR32rm:
17412
0
  case BEXTR32rm_EVEX:
17413
0
  case BEXTR32rr:
17414
0
  case BEXTR32rr_EVEX:
17415
0
  case BEXTR64rm:
17416
0
  case BEXTR64rm_EVEX:
17417
0
  case BEXTR64rr:
17418
0
  case BEXTR64rr_EVEX:
17419
0
  case BEXTRI32mi:
17420
0
  case BEXTRI32ri:
17421
0
  case BEXTRI64mi:
17422
0
  case BEXTRI64ri:
17423
0
    return true;
17424
0
  }
17425
0
  return false;
17426
0
}
17427
17428
0
bool isSTD(unsigned Opcode) {
17429
0
  return Opcode == STD;
17430
0
}
17431
17432
0
bool isVAESKEYGENASSIST(unsigned Opcode) {
17433
0
  switch (Opcode) {
17434
0
  case VAESKEYGENASSIST128rm:
17435
0
  case VAESKEYGENASSIST128rr:
17436
0
    return true;
17437
0
  }
17438
0
  return false;
17439
0
}
17440
17441
0
bool isCMPSD(unsigned Opcode) {
17442
0
  switch (Opcode) {
17443
0
  case CMPSDrm_Int:
17444
0
  case CMPSDrr_Int:
17445
0
  case CMPSL:
17446
0
    return true;
17447
0
  }
17448
0
  return false;
17449
0
}
17450
17451
0
bool isMOVSS(unsigned Opcode) {
17452
0
  switch (Opcode) {
17453
0
  case MOVSSmr:
17454
0
  case MOVSSrm:
17455
0
  case MOVSSrr:
17456
0
  case MOVSSrr_REV:
17457
0
    return true;
17458
0
  }
17459
0
  return false;
17460
0
}
17461
17462
0
bool isVCVTUQQ2PD(unsigned Opcode) {
17463
0
  switch (Opcode) {
17464
0
  case VCVTUQQ2PDZ128rm:
17465
0
  case VCVTUQQ2PDZ128rmb:
17466
0
  case VCVTUQQ2PDZ128rmbk:
17467
0
  case VCVTUQQ2PDZ128rmbkz:
17468
0
  case VCVTUQQ2PDZ128rmk:
17469
0
  case VCVTUQQ2PDZ128rmkz:
17470
0
  case VCVTUQQ2PDZ128rr:
17471
0
  case VCVTUQQ2PDZ128rrk:
17472
0
  case VCVTUQQ2PDZ128rrkz:
17473
0
  case VCVTUQQ2PDZ256rm:
17474
0
  case VCVTUQQ2PDZ256rmb:
17475
0
  case VCVTUQQ2PDZ256rmbk:
17476
0
  case VCVTUQQ2PDZ256rmbkz:
17477
0
  case VCVTUQQ2PDZ256rmk:
17478
0
  case VCVTUQQ2PDZ256rmkz:
17479
0
  case VCVTUQQ2PDZ256rr:
17480
0
  case VCVTUQQ2PDZ256rrk:
17481
0
  case VCVTUQQ2PDZ256rrkz:
17482
0
  case VCVTUQQ2PDZrm:
17483
0
  case VCVTUQQ2PDZrmb:
17484
0
  case VCVTUQQ2PDZrmbk:
17485
0
  case VCVTUQQ2PDZrmbkz:
17486
0
  case VCVTUQQ2PDZrmk:
17487
0
  case VCVTUQQ2PDZrmkz:
17488
0
  case VCVTUQQ2PDZrr:
17489
0
  case VCVTUQQ2PDZrrb:
17490
0
  case VCVTUQQ2PDZrrbk:
17491
0
  case VCVTUQQ2PDZrrbkz:
17492
0
  case VCVTUQQ2PDZrrk:
17493
0
  case VCVTUQQ2PDZrrkz:
17494
0
    return true;
17495
0
  }
17496
0
  return false;
17497
0
}
17498
17499
0
bool isVEXTRACTI32X4(unsigned Opcode) {
17500
0
  switch (Opcode) {
17501
0
  case VEXTRACTI32x4Z256mr:
17502
0
  case VEXTRACTI32x4Z256mrk:
17503
0
  case VEXTRACTI32x4Z256rr:
17504
0
  case VEXTRACTI32x4Z256rrk:
17505
0
  case VEXTRACTI32x4Z256rrkz:
17506
0
  case VEXTRACTI32x4Zmr:
17507
0
  case VEXTRACTI32x4Zmrk:
17508
0
  case VEXTRACTI32x4Zrr:
17509
0
  case VEXTRACTI32x4Zrrk:
17510
0
  case VEXTRACTI32x4Zrrkz:
17511
0
    return true;
17512
0
  }
17513
0
  return false;
17514
0
}
17515
17516
0
bool isFLDCW(unsigned Opcode) {
17517
0
  return Opcode == FLDCW16m;
17518
0
}
17519
17520
0
bool isINSW(unsigned Opcode) {
17521
0
  return Opcode == INSW;
17522
0
}
17523
17524
0
bool isRDPID(unsigned Opcode) {
17525
0
  switch (Opcode) {
17526
0
  case RDPID32:
17527
0
  case RDPID64:
17528
0
    return true;
17529
0
  }
17530
0
  return false;
17531
0
}
17532
17533
0
bool isKANDQ(unsigned Opcode) {
17534
0
  return Opcode == KANDQrr;
17535
0
}
17536
17537
0
bool isV4FMADDPS(unsigned Opcode) {
17538
0
  switch (Opcode) {
17539
0
  case V4FMADDPSrm:
17540
0
  case V4FMADDPSrmk:
17541
0
  case V4FMADDPSrmkz:
17542
0
    return true;
17543
0
  }
17544
0
  return false;
17545
0
}
17546
17547
0
bool isPMOVZXWQ(unsigned Opcode) {
17548
0
  switch (Opcode) {
17549
0
  case PMOVZXWQrm:
17550
0
  case PMOVZXWQrr:
17551
0
    return true;
17552
0
  }
17553
0
  return false;
17554
0
}
17555
17556
0
bool isVFPCLASSSD(unsigned Opcode) {
17557
0
  switch (Opcode) {
17558
0
  case VFPCLASSSDZrm:
17559
0
  case VFPCLASSSDZrmk:
17560
0
  case VFPCLASSSDZrr:
17561
0
  case VFPCLASSSDZrrk:
17562
0
    return true;
17563
0
  }
17564
0
  return false;
17565
0
}
17566
17567
0
bool isBLENDPS(unsigned Opcode) {
17568
0
  switch (Opcode) {
17569
0
  case BLENDPSrmi:
17570
0
  case BLENDPSrri:
17571
0
    return true;
17572
0
  }
17573
0
  return false;
17574
0
}
17575
17576
0
bool isVPACKSSDW(unsigned Opcode) {
17577
0
  switch (Opcode) {
17578
0
  case VPACKSSDWYrm:
17579
0
  case VPACKSSDWYrr:
17580
0
  case VPACKSSDWZ128rm:
17581
0
  case VPACKSSDWZ128rmb:
17582
0
  case VPACKSSDWZ128rmbk:
17583
0
  case VPACKSSDWZ128rmbkz:
17584
0
  case VPACKSSDWZ128rmk:
17585
0
  case VPACKSSDWZ128rmkz:
17586
0
  case VPACKSSDWZ128rr:
17587
0
  case VPACKSSDWZ128rrk:
17588
0
  case VPACKSSDWZ128rrkz:
17589
0
  case VPACKSSDWZ256rm:
17590
0
  case VPACKSSDWZ256rmb:
17591
0
  case VPACKSSDWZ256rmbk:
17592
0
  case VPACKSSDWZ256rmbkz:
17593
0
  case VPACKSSDWZ256rmk:
17594
0
  case VPACKSSDWZ256rmkz:
17595
0
  case VPACKSSDWZ256rr:
17596
0
  case VPACKSSDWZ256rrk:
17597
0
  case VPACKSSDWZ256rrkz:
17598
0
  case VPACKSSDWZrm:
17599
0
  case VPACKSSDWZrmb:
17600
0
  case VPACKSSDWZrmbk:
17601
0
  case VPACKSSDWZrmbkz:
17602
0
  case VPACKSSDWZrmk:
17603
0
  case VPACKSSDWZrmkz:
17604
0
  case VPACKSSDWZrr:
17605
0
  case VPACKSSDWZrrk:
17606
0
  case VPACKSSDWZrrkz:
17607
0
  case VPACKSSDWrm:
17608
0
  case VPACKSSDWrr:
17609
0
    return true;
17610
0
  }
17611
0
  return false;
17612
0
}
17613
17614
0
bool isVPINSRW(unsigned Opcode) {
17615
0
  switch (Opcode) {
17616
0
  case VPINSRWZrm:
17617
0
  case VPINSRWZrr:
17618
0
  case VPINSRWrm:
17619
0
  case VPINSRWrr:
17620
0
    return true;
17621
0
  }
17622
0
  return false;
17623
0
}
17624
17625
0
bool isFXAM(unsigned Opcode) {
17626
0
  return Opcode == XAM_F;
17627
0
}
17628
17629
0
bool isVPHSUBBW(unsigned Opcode) {
17630
0
  switch (Opcode) {
17631
0
  case VPHSUBBWrm:
17632
0
  case VPHSUBBWrr:
17633
0
    return true;
17634
0
  }
17635
0
  return false;
17636
0
}
17637
17638
0
bool isVSHUFF64X2(unsigned Opcode) {
17639
0
  switch (Opcode) {
17640
0
  case VSHUFF64X2Z256rmbi:
17641
0
  case VSHUFF64X2Z256rmbik:
17642
0
  case VSHUFF64X2Z256rmbikz:
17643
0
  case VSHUFF64X2Z256rmi:
17644
0
  case VSHUFF64X2Z256rmik:
17645
0
  case VSHUFF64X2Z256rmikz:
17646
0
  case VSHUFF64X2Z256rri:
17647
0
  case VSHUFF64X2Z256rrik:
17648
0
  case VSHUFF64X2Z256rrikz:
17649
0
  case VSHUFF64X2Zrmbi:
17650
0
  case VSHUFF64X2Zrmbik:
17651
0
  case VSHUFF64X2Zrmbikz:
17652
0
  case VSHUFF64X2Zrmi:
17653
0
  case VSHUFF64X2Zrmik:
17654
0
  case VSHUFF64X2Zrmikz:
17655
0
  case VSHUFF64X2Zrri:
17656
0
  case VSHUFF64X2Zrrik:
17657
0
  case VSHUFF64X2Zrrikz:
17658
0
    return true;
17659
0
  }
17660
0
  return false;
17661
0
}
17662
17663
0
bool isVPACKUSWB(unsigned Opcode) {
17664
0
  switch (Opcode) {
17665
0
  case VPACKUSWBYrm:
17666
0
  case VPACKUSWBYrr:
17667
0
  case VPACKUSWBZ128rm:
17668
0
  case VPACKUSWBZ128rmk:
17669
0
  case VPACKUSWBZ128rmkz:
17670
0
  case VPACKUSWBZ128rr:
17671
0
  case VPACKUSWBZ128rrk:
17672
0
  case VPACKUSWBZ128rrkz:
17673
0
  case VPACKUSWBZ256rm:
17674
0
  case VPACKUSWBZ256rmk:
17675
0
  case VPACKUSWBZ256rmkz:
17676
0
  case VPACKUSWBZ256rr:
17677
0
  case VPACKUSWBZ256rrk:
17678
0
  case VPACKUSWBZ256rrkz:
17679
0
  case VPACKUSWBZrm:
17680
0
  case VPACKUSWBZrmk:
17681
0
  case VPACKUSWBZrmkz:
17682
0
  case VPACKUSWBZrr:
17683
0
  case VPACKUSWBZrrk:
17684
0
  case VPACKUSWBZrrkz:
17685
0
  case VPACKUSWBrm:
17686
0
  case VPACKUSWBrr:
17687
0
    return true;
17688
0
  }
17689
0
  return false;
17690
0
}
17691
17692
0
bool isVRSQRT28SS(unsigned Opcode) {
17693
0
  switch (Opcode) {
17694
0
  case VRSQRT28SSZm:
17695
0
  case VRSQRT28SSZmk:
17696
0
  case VRSQRT28SSZmkz:
17697
0
  case VRSQRT28SSZr:
17698
0
  case VRSQRT28SSZrb:
17699
0
  case VRSQRT28SSZrbk:
17700
0
  case VRSQRT28SSZrbkz:
17701
0
  case VRSQRT28SSZrk:
17702
0
  case VRSQRT28SSZrkz:
17703
0
    return true;
17704
0
  }
17705
0
  return false;
17706
0
}
17707
17708
0
bool isGETSEC(unsigned Opcode) {
17709
0
  return Opcode == GETSEC;
17710
0
}
17711
17712
0
bool isVEXTRACTF64X4(unsigned Opcode) {
17713
0
  switch (Opcode) {
17714
0
  case VEXTRACTF64x4Zmr:
17715
0
  case VEXTRACTF64x4Zmrk:
17716
0
  case VEXTRACTF64x4Zrr:
17717
0
  case VEXTRACTF64x4Zrrk:
17718
0
  case VEXTRACTF64x4Zrrkz:
17719
0
    return true;
17720
0
  }
17721
0
  return false;
17722
0
}
17723
17724
0
bool isBLSR(unsigned Opcode) {
17725
0
  switch (Opcode) {
17726
0
  case BLSR32rm:
17727
0
  case BLSR32rm_EVEX:
17728
0
  case BLSR32rr:
17729
0
  case BLSR32rr_EVEX:
17730
0
  case BLSR64rm:
17731
0
  case BLSR64rm_EVEX:
17732
0
  case BLSR64rr:
17733
0
  case BLSR64rr_EVEX:
17734
0
    return true;
17735
0
  }
17736
0
  return false;
17737
0
}
17738
17739
0
bool isFILD(unsigned Opcode) {
17740
0
  switch (Opcode) {
17741
0
  case ILD_F16m:
17742
0
  case ILD_F32m:
17743
0
  case ILD_F64m:
17744
0
    return true;
17745
0
  }
17746
0
  return false;
17747
0
}
17748
17749
0
bool isRETFQ(unsigned Opcode) {
17750
0
  switch (Opcode) {
17751
0
  case LRET64:
17752
0
  case LRETI64:
17753
0
    return true;
17754
0
  }
17755
0
  return false;
17756
0
}
17757
17758
0
bool isVADDSS(unsigned Opcode) {
17759
0
  switch (Opcode) {
17760
0
  case VADDSSZrm_Int:
17761
0
  case VADDSSZrm_Intk:
17762
0
  case VADDSSZrm_Intkz:
17763
0
  case VADDSSZrr_Int:
17764
0
  case VADDSSZrr_Intk:
17765
0
  case VADDSSZrr_Intkz:
17766
0
  case VADDSSZrrb_Int:
17767
0
  case VADDSSZrrb_Intk:
17768
0
  case VADDSSZrrb_Intkz:
17769
0
  case VADDSSrm_Int:
17770
0
  case VADDSSrr_Int:
17771
0
    return true;
17772
0
  }
17773
0
  return false;
17774
0
}
17775
17776
0
bool isCOMISS(unsigned Opcode) {
17777
0
  switch (Opcode) {
17778
0
  case COMISSrm:
17779
0
  case COMISSrr:
17780
0
    return true;
17781
0
  }
17782
0
  return false;
17783
0
}
17784
17785
0
bool isCLI(unsigned Opcode) {
17786
0
  return Opcode == CLI;
17787
0
}
17788
17789
0
bool isVERW(unsigned Opcode) {
17790
0
  switch (Opcode) {
17791
0
  case VERWm:
17792
0
  case VERWr:
17793
0
    return true;
17794
0
  }
17795
0
  return false;
17796
0
}
17797
17798
0
bool isBTC(unsigned Opcode) {
17799
0
  switch (Opcode) {
17800
0
  case BTC16mi8:
17801
0
  case BTC16mr:
17802
0
  case BTC16ri8:
17803
0
  case BTC16rr:
17804
0
  case BTC32mi8:
17805
0
  case BTC32mr:
17806
0
  case BTC32ri8:
17807
0
  case BTC32rr:
17808
0
  case BTC64mi8:
17809
0
  case BTC64mr:
17810
0
  case BTC64ri8:
17811
0
  case BTC64rr:
17812
0
    return true;
17813
0
  }
17814
0
  return false;
17815
0
}
17816
17817
0
bool isVPHADDUBQ(unsigned Opcode) {
17818
0
  switch (Opcode) {
17819
0
  case VPHADDUBQrm:
17820
0
  case VPHADDUBQrr:
17821
0
    return true;
17822
0
  }
17823
0
  return false;
17824
0
}
17825
17826
0
bool isVPORQ(unsigned Opcode) {
17827
0
  switch (Opcode) {
17828
0
  case VPORQZ128rm:
17829
0
  case VPORQZ128rmb:
17830
0
  case VPORQZ128rmbk:
17831
0
  case VPORQZ128rmbkz:
17832
0
  case VPORQZ128rmk:
17833
0
  case VPORQZ128rmkz:
17834
0
  case VPORQZ128rr:
17835
0
  case VPORQZ128rrk:
17836
0
  case VPORQZ128rrkz:
17837
0
  case VPORQZ256rm:
17838
0
  case VPORQZ256rmb:
17839
0
  case VPORQZ256rmbk:
17840
0
  case VPORQZ256rmbkz:
17841
0
  case VPORQZ256rmk:
17842
0
  case VPORQZ256rmkz:
17843
0
  case VPORQZ256rr:
17844
0
  case VPORQZ256rrk:
17845
0
  case VPORQZ256rrkz:
17846
0
  case VPORQZrm:
17847
0
  case VPORQZrmb:
17848
0
  case VPORQZrmbk:
17849
0
  case VPORQZrmbkz:
17850
0
  case VPORQZrmk:
17851
0
  case VPORQZrmkz:
17852
0
  case VPORQZrr:
17853
0
  case VPORQZrrk:
17854
0
  case VPORQZrrkz:
17855
0
    return true;
17856
0
  }
17857
0
  return false;
17858
0
}
17859
17860
0
bool isORPD(unsigned Opcode) {
17861
0
  switch (Opcode) {
17862
0
  case ORPDrm:
17863
0
  case ORPDrr:
17864
0
    return true;
17865
0
  }
17866
0
  return false;
17867
0
}
17868
17869
0
bool isVMOVSS(unsigned Opcode) {
17870
0
  switch (Opcode) {
17871
0
  case VMOVSSZmr:
17872
0
  case VMOVSSZmrk:
17873
0
  case VMOVSSZrm:
17874
0
  case VMOVSSZrmk:
17875
0
  case VMOVSSZrmkz:
17876
0
  case VMOVSSZrr:
17877
0
  case VMOVSSZrr_REV:
17878
0
  case VMOVSSZrrk:
17879
0
  case VMOVSSZrrk_REV:
17880
0
  case VMOVSSZrrkz:
17881
0
  case VMOVSSZrrkz_REV:
17882
0
  case VMOVSSmr:
17883
0
  case VMOVSSrm:
17884
0
  case VMOVSSrr:
17885
0
  case VMOVSSrr_REV:
17886
0
    return true;
17887
0
  }
17888
0
  return false;
17889
0
}
17890
17891
0
bool isVPSUBD(unsigned Opcode) {
17892
0
  switch (Opcode) {
17893
0
  case VPSUBDYrm:
17894
0
  case VPSUBDYrr:
17895
0
  case VPSUBDZ128rm:
17896
0
  case VPSUBDZ128rmb:
17897
0
  case VPSUBDZ128rmbk:
17898
0
  case VPSUBDZ128rmbkz:
17899
0
  case VPSUBDZ128rmk:
17900
0
  case VPSUBDZ128rmkz:
17901
0
  case VPSUBDZ128rr:
17902
0
  case VPSUBDZ128rrk:
17903
0
  case VPSUBDZ128rrkz:
17904
0
  case VPSUBDZ256rm:
17905
0
  case VPSUBDZ256rmb:
17906
0
  case VPSUBDZ256rmbk:
17907
0
  case VPSUBDZ256rmbkz:
17908
0
  case VPSUBDZ256rmk:
17909
0
  case VPSUBDZ256rmkz:
17910
0
  case VPSUBDZ256rr:
17911
0
  case VPSUBDZ256rrk:
17912
0
  case VPSUBDZ256rrkz:
17913
0
  case VPSUBDZrm:
17914
0
  case VPSUBDZrmb:
17915
0
  case VPSUBDZrmbk:
17916
0
  case VPSUBDZrmbkz:
17917
0
  case VPSUBDZrmk:
17918
0
  case VPSUBDZrmkz:
17919
0
  case VPSUBDZrr:
17920
0
  case VPSUBDZrrk:
17921
0
  case VPSUBDZrrkz:
17922
0
  case VPSUBDrm:
17923
0
  case VPSUBDrr:
17924
0
    return true;
17925
0
  }
17926
0
  return false;
17927
0
}
17928
17929
0
bool isVGATHERPF1QPD(unsigned Opcode) {
17930
0
  return Opcode == VGATHERPF1QPDm;
17931
0
}
17932
17933
0
bool isENCODEKEY256(unsigned Opcode) {
17934
0
  return Opcode == ENCODEKEY256;
17935
0
}
17936
17937
0
bool isGF2P8AFFINEINVQB(unsigned Opcode) {
17938
0
  switch (Opcode) {
17939
0
  case GF2P8AFFINEINVQBrmi:
17940
0
  case GF2P8AFFINEINVQBrri:
17941
0
    return true;
17942
0
  }
17943
0
  return false;
17944
0
}
17945
17946
0
bool isXRSTOR64(unsigned Opcode) {
17947
0
  return Opcode == XRSTOR64;
17948
0
}
17949
17950
0
bool isKANDW(unsigned Opcode) {
17951
0
  return Opcode == KANDWrr;
17952
0
}
17953
17954
0
bool isLODSQ(unsigned Opcode) {
17955
0
  return Opcode == LODSQ;
17956
0
}
17957
17958
0
bool isVSUBSH(unsigned Opcode) {
17959
0
  switch (Opcode) {
17960
0
  case VSUBSHZrm_Int:
17961
0
  case VSUBSHZrm_Intk:
17962
0
  case VSUBSHZrm_Intkz:
17963
0
  case VSUBSHZrr_Int:
17964
0
  case VSUBSHZrr_Intk:
17965
0
  case VSUBSHZrr_Intkz:
17966
0
  case VSUBSHZrrb_Int:
17967
0
  case VSUBSHZrrb_Intk:
17968
0
  case VSUBSHZrrb_Intkz:
17969
0
    return true;
17970
0
  }
17971
0
  return false;
17972
0
}
17973
17974
0
bool isLSS(unsigned Opcode) {
17975
0
  switch (Opcode) {
17976
0
  case LSS16rm:
17977
0
  case LSS32rm:
17978
0
  case LSS64rm:
17979
0
    return true;
17980
0
  }
17981
0
  return false;
17982
0
}
17983
17984
0
bool isPMOVSXBQ(unsigned Opcode) {
17985
0
  switch (Opcode) {
17986
0
  case PMOVSXBQrm:
17987
0
  case PMOVSXBQrr:
17988
0
    return true;
17989
0
  }
17990
0
  return false;
17991
0
}
17992
17993
0
bool isVCMPSH(unsigned Opcode) {
17994
0
  switch (Opcode) {
17995
0
  case VCMPSHZrm_Int:
17996
0
  case VCMPSHZrm_Intk:
17997
0
  case VCMPSHZrr_Int:
17998
0
  case VCMPSHZrr_Intk:
17999
0
  case VCMPSHZrrb_Int:
18000
0
  case VCMPSHZrrb_Intk:
18001
0
    return true;
18002
0
  }
18003
0
  return false;
18004
0
}
18005
18006
0
bool isVFMADD132PS(unsigned Opcode) {
18007
0
  switch (Opcode) {
18008
0
  case VFMADD132PSYm:
18009
0
  case VFMADD132PSYr:
18010
0
  case VFMADD132PSZ128m:
18011
0
  case VFMADD132PSZ128mb:
18012
0
  case VFMADD132PSZ128mbk:
18013
0
  case VFMADD132PSZ128mbkz:
18014
0
  case VFMADD132PSZ128mk:
18015
0
  case VFMADD132PSZ128mkz:
18016
0
  case VFMADD132PSZ128r:
18017
0
  case VFMADD132PSZ128rk:
18018
0
  case VFMADD132PSZ128rkz:
18019
0
  case VFMADD132PSZ256m:
18020
0
  case VFMADD132PSZ256mb:
18021
0
  case VFMADD132PSZ256mbk:
18022
0
  case VFMADD132PSZ256mbkz:
18023
0
  case VFMADD132PSZ256mk:
18024
0
  case VFMADD132PSZ256mkz:
18025
0
  case VFMADD132PSZ256r:
18026
0
  case VFMADD132PSZ256rk:
18027
0
  case VFMADD132PSZ256rkz:
18028
0
  case VFMADD132PSZm:
18029
0
  case VFMADD132PSZmb:
18030
0
  case VFMADD132PSZmbk:
18031
0
  case VFMADD132PSZmbkz:
18032
0
  case VFMADD132PSZmk:
18033
0
  case VFMADD132PSZmkz:
18034
0
  case VFMADD132PSZr:
18035
0
  case VFMADD132PSZrb:
18036
0
  case VFMADD132PSZrbk:
18037
0
  case VFMADD132PSZrbkz:
18038
0
  case VFMADD132PSZrk:
18039
0
  case VFMADD132PSZrkz:
18040
0
  case VFMADD132PSm:
18041
0
  case VFMADD132PSr:
18042
0
    return true;
18043
0
  }
18044
0
  return false;
18045
0
}
18046
18047
0
bool isVPACKSSWB(unsigned Opcode) {
18048
0
  switch (Opcode) {
18049
0
  case VPACKSSWBYrm:
18050
0
  case VPACKSSWBYrr:
18051
0
  case VPACKSSWBZ128rm:
18052
0
  case VPACKSSWBZ128rmk:
18053
0
  case VPACKSSWBZ128rmkz:
18054
0
  case VPACKSSWBZ128rr:
18055
0
  case VPACKSSWBZ128rrk:
18056
0
  case VPACKSSWBZ128rrkz:
18057
0
  case VPACKSSWBZ256rm:
18058
0
  case VPACKSSWBZ256rmk:
18059
0
  case VPACKSSWBZ256rmkz:
18060
0
  case VPACKSSWBZ256rr:
18061
0
  case VPACKSSWBZ256rrk:
18062
0
  case VPACKSSWBZ256rrkz:
18063
0
  case VPACKSSWBZrm:
18064
0
  case VPACKSSWBZrmk:
18065
0
  case VPACKSSWBZrmkz:
18066
0
  case VPACKSSWBZrr:
18067
0
  case VPACKSSWBZrrk:
18068
0
  case VPACKSSWBZrrkz:
18069
0
  case VPACKSSWBrm:
18070
0
  case VPACKSSWBrr:
18071
0
    return true;
18072
0
  }
18073
0
  return false;
18074
0
}
18075
18076
0
bool isPCMPGTQ(unsigned Opcode) {
18077
0
  switch (Opcode) {
18078
0
  case PCMPGTQrm:
18079
0
  case PCMPGTQrr:
18080
0
    return true;
18081
0
  }
18082
0
  return false;
18083
0
}
18084
18085
0
bool isVFMADD132SH(unsigned Opcode) {
18086
0
  switch (Opcode) {
18087
0
  case VFMADD132SHZm_Int:
18088
0
  case VFMADD132SHZm_Intk:
18089
0
  case VFMADD132SHZm_Intkz:
18090
0
  case VFMADD132SHZr_Int:
18091
0
  case VFMADD132SHZr_Intk:
18092
0
  case VFMADD132SHZr_Intkz:
18093
0
  case VFMADD132SHZrb_Int:
18094
0
  case VFMADD132SHZrb_Intk:
18095
0
  case VFMADD132SHZrb_Intkz:
18096
0
    return true;
18097
0
  }
18098
0
  return false;
18099
0
}
18100
18101
0
bool isVCVTUQQ2PH(unsigned Opcode) {
18102
0
  switch (Opcode) {
18103
0
  case VCVTUQQ2PHZ128rm:
18104
0
  case VCVTUQQ2PHZ128rmb:
18105
0
  case VCVTUQQ2PHZ128rmbk:
18106
0
  case VCVTUQQ2PHZ128rmbkz:
18107
0
  case VCVTUQQ2PHZ128rmk:
18108
0
  case VCVTUQQ2PHZ128rmkz:
18109
0
  case VCVTUQQ2PHZ128rr:
18110
0
  case VCVTUQQ2PHZ128rrk:
18111
0
  case VCVTUQQ2PHZ128rrkz:
18112
0
  case VCVTUQQ2PHZ256rm:
18113
0
  case VCVTUQQ2PHZ256rmb:
18114
0
  case VCVTUQQ2PHZ256rmbk:
18115
0
  case VCVTUQQ2PHZ256rmbkz:
18116
0
  case VCVTUQQ2PHZ256rmk:
18117
0
  case VCVTUQQ2PHZ256rmkz:
18118
0
  case VCVTUQQ2PHZ256rr:
18119
0
  case VCVTUQQ2PHZ256rrk:
18120
0
  case VCVTUQQ2PHZ256rrkz:
18121
0
  case VCVTUQQ2PHZrm:
18122
0
  case VCVTUQQ2PHZrmb:
18123
0
  case VCVTUQQ2PHZrmbk:
18124
0
  case VCVTUQQ2PHZrmbkz:
18125
0
  case VCVTUQQ2PHZrmk:
18126
0
  case VCVTUQQ2PHZrmkz:
18127
0
  case VCVTUQQ2PHZrr:
18128
0
  case VCVTUQQ2PHZrrb:
18129
0
  case VCVTUQQ2PHZrrbk:
18130
0
  case VCVTUQQ2PHZrrbkz:
18131
0
  case VCVTUQQ2PHZrrk:
18132
0
  case VCVTUQQ2PHZrrkz:
18133
0
    return true;
18134
0
  }
18135
0
  return false;
18136
0
}
18137
18138
0
bool isVCVTQQ2PS(unsigned Opcode) {
18139
0
  switch (Opcode) {
18140
0
  case VCVTQQ2PSZ128rm:
18141
0
  case VCVTQQ2PSZ128rmb:
18142
0
  case VCVTQQ2PSZ128rmbk:
18143
0
  case VCVTQQ2PSZ128rmbkz:
18144
0
  case VCVTQQ2PSZ128rmk:
18145
0
  case VCVTQQ2PSZ128rmkz:
18146
0
  case VCVTQQ2PSZ128rr:
18147
0
  case VCVTQQ2PSZ128rrk:
18148
0
  case VCVTQQ2PSZ128rrkz:
18149
0
  case VCVTQQ2PSZ256rm:
18150
0
  case VCVTQQ2PSZ256rmb:
18151
0
  case VCVTQQ2PSZ256rmbk:
18152
0
  case VCVTQQ2PSZ256rmbkz:
18153
0
  case VCVTQQ2PSZ256rmk:
18154
0
  case VCVTQQ2PSZ256rmkz:
18155
0
  case VCVTQQ2PSZ256rr:
18156
0
  case VCVTQQ2PSZ256rrk:
18157
0
  case VCVTQQ2PSZ256rrkz:
18158
0
  case VCVTQQ2PSZrm:
18159
0
  case VCVTQQ2PSZrmb:
18160
0
  case VCVTQQ2PSZrmbk:
18161
0
  case VCVTQQ2PSZrmbkz:
18162
0
  case VCVTQQ2PSZrmk:
18163
0
  case VCVTQQ2PSZrmkz:
18164
0
  case VCVTQQ2PSZrr:
18165
0
  case VCVTQQ2PSZrrb:
18166
0
  case VCVTQQ2PSZrrbk:
18167
0
  case VCVTQQ2PSZrrbkz:
18168
0
  case VCVTQQ2PSZrrk:
18169
0
  case VCVTQQ2PSZrrkz:
18170
0
    return true;
18171
0
  }
18172
0
  return false;
18173
0
}
18174
18175
0
bool isVCVTTSS2USI(unsigned Opcode) {
18176
0
  switch (Opcode) {
18177
0
  case VCVTTSS2USI64Zrm_Int:
18178
0
  case VCVTTSS2USI64Zrr_Int:
18179
0
  case VCVTTSS2USI64Zrrb_Int:
18180
0
  case VCVTTSS2USIZrm_Int:
18181
0
  case VCVTTSS2USIZrr_Int:
18182
0
  case VCVTTSS2USIZrrb_Int:
18183
0
    return true;
18184
0
  }
18185
0
  return false;
18186
0
}
18187
18188
0
bool isVPMOVM2Q(unsigned Opcode) {
18189
0
  switch (Opcode) {
18190
0
  case VPMOVM2QZ128rr:
18191
0
  case VPMOVM2QZ256rr:
18192
0
  case VPMOVM2QZrr:
18193
0
    return true;
18194
0
  }
18195
0
  return false;
18196
0
}
18197
18198
0
bool isVMOVD(unsigned Opcode) {
18199
0
  switch (Opcode) {
18200
0
  case VMOVDI2PDIZrm:
18201
0
  case VMOVDI2PDIZrr:
18202
0
  case VMOVDI2PDIrm:
18203
0
  case VMOVDI2PDIrr:
18204
0
  case VMOVPDI2DIZmr:
18205
0
  case VMOVPDI2DIZrr:
18206
0
  case VMOVPDI2DImr:
18207
0
  case VMOVPDI2DIrr:
18208
0
    return true;
18209
0
  }
18210
0
  return false;
18211
0
}
18212
18213
0
bool isVFPCLASSPH(unsigned Opcode) {
18214
0
  switch (Opcode) {
18215
0
  case VFPCLASSPHZ128rm:
18216
0
  case VFPCLASSPHZ128rmb:
18217
0
  case VFPCLASSPHZ128rmbk:
18218
0
  case VFPCLASSPHZ128rmk:
18219
0
  case VFPCLASSPHZ128rr:
18220
0
  case VFPCLASSPHZ128rrk:
18221
0
  case VFPCLASSPHZ256rm:
18222
0
  case VFPCLASSPHZ256rmb:
18223
0
  case VFPCLASSPHZ256rmbk:
18224
0
  case VFPCLASSPHZ256rmk:
18225
0
  case VFPCLASSPHZ256rr:
18226
0
  case VFPCLASSPHZ256rrk:
18227
0
  case VFPCLASSPHZrm:
18228
0
  case VFPCLASSPHZrmb:
18229
0
  case VFPCLASSPHZrmbk:
18230
0
  case VFPCLASSPHZrmk:
18231
0
  case VFPCLASSPHZrr:
18232
0
  case VFPCLASSPHZrrk:
18233
0
    return true;
18234
0
  }
18235
0
  return false;
18236
0
}
18237
18238
0
bool isVCVTSS2SH(unsigned Opcode) {
18239
0
  switch (Opcode) {
18240
0
  case VCVTSS2SHZrm_Int:
18241
0
  case VCVTSS2SHZrm_Intk:
18242
0
  case VCVTSS2SHZrm_Intkz:
18243
0
  case VCVTSS2SHZrr_Int:
18244
0
  case VCVTSS2SHZrr_Intk:
18245
0
  case VCVTSS2SHZrr_Intkz:
18246
0
  case VCVTSS2SHZrrb_Int:
18247
0
  case VCVTSS2SHZrrb_Intk:
18248
0
  case VCVTSS2SHZrrb_Intkz:
18249
0
    return true;
18250
0
  }
18251
0
  return false;
18252
0
}
18253
18254
0
bool isSCASB(unsigned Opcode) {
18255
0
  return Opcode == SCASB;
18256
0
}
18257
18258
0
bool isPSRLD(unsigned Opcode) {
18259
0
  switch (Opcode) {
18260
0
  case MMX_PSRLDri:
18261
0
  case MMX_PSRLDrm:
18262
0
  case MMX_PSRLDrr:
18263
0
  case PSRLDri:
18264
0
  case PSRLDrm:
18265
0
  case PSRLDrr:
18266
0
    return true;
18267
0
  }
18268
0
  return false;
18269
0
}
18270
18271
0
bool isVADDPH(unsigned Opcode) {
18272
0
  switch (Opcode) {
18273
0
  case VADDPHZ128rm:
18274
0
  case VADDPHZ128rmb:
18275
0
  case VADDPHZ128rmbk:
18276
0
  case VADDPHZ128rmbkz:
18277
0
  case VADDPHZ128rmk:
18278
0
  case VADDPHZ128rmkz:
18279
0
  case VADDPHZ128rr:
18280
0
  case VADDPHZ128rrk:
18281
0
  case VADDPHZ128rrkz:
18282
0
  case VADDPHZ256rm:
18283
0
  case VADDPHZ256rmb:
18284
0
  case VADDPHZ256rmbk:
18285
0
  case VADDPHZ256rmbkz:
18286
0
  case VADDPHZ256rmk:
18287
0
  case VADDPHZ256rmkz:
18288
0
  case VADDPHZ256rr:
18289
0
  case VADDPHZ256rrk:
18290
0
  case VADDPHZ256rrkz:
18291
0
  case VADDPHZrm:
18292
0
  case VADDPHZrmb:
18293
0
  case VADDPHZrmbk:
18294
0
  case VADDPHZrmbkz:
18295
0
  case VADDPHZrmk:
18296
0
  case VADDPHZrmkz:
18297
0
  case VADDPHZrr:
18298
0
  case VADDPHZrrb:
18299
0
  case VADDPHZrrbk:
18300
0
  case VADDPHZrrbkz:
18301
0
  case VADDPHZrrk:
18302
0
  case VADDPHZrrkz:
18303
0
    return true;
18304
0
  }
18305
0
  return false;
18306
0
}
18307
18308
0
bool isFSUB(unsigned Opcode) {
18309
0
  switch (Opcode) {
18310
0
  case SUB_F32m:
18311
0
  case SUB_F64m:
18312
0
  case SUB_FST0r:
18313
0
  case SUB_FrST0:
18314
0
    return true;
18315
0
  }
18316
0
  return false;
18317
0
}
18318
18319
0
bool isVEXTRACTI64X2(unsigned Opcode) {
18320
0
  switch (Opcode) {
18321
0
  case VEXTRACTI64x2Z256mr:
18322
0
  case VEXTRACTI64x2Z256mrk:
18323
0
  case VEXTRACTI64x2Z256rr:
18324
0
  case VEXTRACTI64x2Z256rrk:
18325
0
  case VEXTRACTI64x2Z256rrkz:
18326
0
  case VEXTRACTI64x2Zmr:
18327
0
  case VEXTRACTI64x2Zmrk:
18328
0
  case VEXTRACTI64x2Zrr:
18329
0
  case VEXTRACTI64x2Zrrk:
18330
0
  case VEXTRACTI64x2Zrrkz:
18331
0
    return true;
18332
0
  }
18333
0
  return false;
18334
0
}
18335
18336
0
bool isPMINUW(unsigned Opcode) {
18337
0
  switch (Opcode) {
18338
0
  case PMINUWrm:
18339
0
  case PMINUWrr:
18340
0
    return true;
18341
0
  }
18342
0
  return false;
18343
0
}
18344
18345
0
bool isPSUBSB(unsigned Opcode) {
18346
0
  switch (Opcode) {
18347
0
  case MMX_PSUBSBrm:
18348
0
  case MMX_PSUBSBrr:
18349
0
  case PSUBSBrm:
18350
0
  case PSUBSBrr:
18351
0
    return true;
18352
0
  }
18353
0
  return false;
18354
0
}
18355
18356
0
bool isVPSHLDD(unsigned Opcode) {
18357
0
  switch (Opcode) {
18358
0
  case VPSHLDDZ128rmbi:
18359
0
  case VPSHLDDZ128rmbik:
18360
0
  case VPSHLDDZ128rmbikz:
18361
0
  case VPSHLDDZ128rmi:
18362
0
  case VPSHLDDZ128rmik:
18363
0
  case VPSHLDDZ128rmikz:
18364
0
  case VPSHLDDZ128rri:
18365
0
  case VPSHLDDZ128rrik:
18366
0
  case VPSHLDDZ128rrikz:
18367
0
  case VPSHLDDZ256rmbi:
18368
0
  case VPSHLDDZ256rmbik:
18369
0
  case VPSHLDDZ256rmbikz:
18370
0
  case VPSHLDDZ256rmi:
18371
0
  case VPSHLDDZ256rmik:
18372
0
  case VPSHLDDZ256rmikz:
18373
0
  case VPSHLDDZ256rri:
18374
0
  case VPSHLDDZ256rrik:
18375
0
  case VPSHLDDZ256rrikz:
18376
0
  case VPSHLDDZrmbi:
18377
0
  case VPSHLDDZrmbik:
18378
0
  case VPSHLDDZrmbikz:
18379
0
  case VPSHLDDZrmi:
18380
0
  case VPSHLDDZrmik:
18381
0
  case VPSHLDDZrmikz:
18382
0
  case VPSHLDDZrri:
18383
0
  case VPSHLDDZrrik:
18384
0
  case VPSHLDDZrrikz:
18385
0
    return true;
18386
0
  }
18387
0
  return false;
18388
0
}
18389
18390
0
bool isVPCMPEQD(unsigned Opcode) {
18391
0
  switch (Opcode) {
18392
0
  case VPCMPEQDYrm:
18393
0
  case VPCMPEQDYrr:
18394
0
  case VPCMPEQDZ128rm:
18395
0
  case VPCMPEQDZ128rmb:
18396
0
  case VPCMPEQDZ128rmbk:
18397
0
  case VPCMPEQDZ128rmk:
18398
0
  case VPCMPEQDZ128rr:
18399
0
  case VPCMPEQDZ128rrk:
18400
0
  case VPCMPEQDZ256rm:
18401
0
  case VPCMPEQDZ256rmb:
18402
0
  case VPCMPEQDZ256rmbk:
18403
0
  case VPCMPEQDZ256rmk:
18404
0
  case VPCMPEQDZ256rr:
18405
0
  case VPCMPEQDZ256rrk:
18406
0
  case VPCMPEQDZrm:
18407
0
  case VPCMPEQDZrmb:
18408
0
  case VPCMPEQDZrmbk:
18409
0
  case VPCMPEQDZrmk:
18410
0
  case VPCMPEQDZrr:
18411
0
  case VPCMPEQDZrrk:
18412
0
  case VPCMPEQDrm:
18413
0
  case VPCMPEQDrr:
18414
0
    return true;
18415
0
  }
18416
0
  return false;
18417
0
}
18418
18419
0
bool isVPSCATTERQD(unsigned Opcode) {
18420
0
  switch (Opcode) {
18421
0
  case VPSCATTERQDZ128mr:
18422
0
  case VPSCATTERQDZ256mr:
18423
0
  case VPSCATTERQDZmr:
18424
0
    return true;
18425
0
  }
18426
0
  return false;
18427
0
}
18428
18429
0
bool isKXNORB(unsigned Opcode) {
18430
0
  return Opcode == KXNORBrr;
18431
0
}
18432
18433
0
bool isCMPCC(unsigned Opcode) {
18434
0
  switch (Opcode) {
18435
0
  case CMPCCXADDmr32:
18436
0
  case CMPCCXADDmr32_EVEX:
18437
0
  case CMPCCXADDmr64:
18438
0
  case CMPCCXADDmr64_EVEX:
18439
0
    return true;
18440
0
  }
18441
0
  return false;
18442
0
}
18443
18444
0
bool isMASKMOVQ(unsigned Opcode) {
18445
0
  switch (Opcode) {
18446
0
  case MMX_MASKMOVQ:
18447
0
  case MMX_MASKMOVQ64:
18448
0
    return true;
18449
0
  }
18450
0
  return false;
18451
0
}
18452
18453
0
bool isLDDQU(unsigned Opcode) {
18454
0
  return Opcode == LDDQUrm;
18455
0
}
18456
18457
0
bool isPABSW(unsigned Opcode) {
18458
0
  switch (Opcode) {
18459
0
  case MMX_PABSWrm:
18460
0
  case MMX_PABSWrr:
18461
0
  case PABSWrm:
18462
0
  case PABSWrr:
18463
0
    return true;
18464
0
  }
18465
0
  return false;
18466
0
}
18467
18468
0
bool isVPROLD(unsigned Opcode) {
18469
0
  switch (Opcode) {
18470
0
  case VPROLDZ128mbi:
18471
0
  case VPROLDZ128mbik:
18472
0
  case VPROLDZ128mbikz:
18473
0
  case VPROLDZ128mi:
18474
0
  case VPROLDZ128mik:
18475
0
  case VPROLDZ128mikz:
18476
0
  case VPROLDZ128ri:
18477
0
  case VPROLDZ128rik:
18478
0
  case VPROLDZ128rikz:
18479
0
  case VPROLDZ256mbi:
18480
0
  case VPROLDZ256mbik:
18481
0
  case VPROLDZ256mbikz:
18482
0
  case VPROLDZ256mi:
18483
0
  case VPROLDZ256mik:
18484
0
  case VPROLDZ256mikz:
18485
0
  case VPROLDZ256ri:
18486
0
  case VPROLDZ256rik:
18487
0
  case VPROLDZ256rikz:
18488
0
  case VPROLDZmbi:
18489
0
  case VPROLDZmbik:
18490
0
  case VPROLDZmbikz:
18491
0
  case VPROLDZmi:
18492
0
  case VPROLDZmik:
18493
0
  case VPROLDZmikz:
18494
0
  case VPROLDZri:
18495
0
  case VPROLDZrik:
18496
0
  case VPROLDZrikz:
18497
0
    return true;
18498
0
  }
18499
0
  return false;
18500
0
}
18501
18502
0
bool isVSCATTERDPD(unsigned Opcode) {
18503
0
  switch (Opcode) {
18504
0
  case VSCATTERDPDZ128mr:
18505
0
  case VSCATTERDPDZ256mr:
18506
0
  case VSCATTERDPDZmr:
18507
0
    return true;
18508
0
  }
18509
0
  return false;
18510
0
}
18511
18512
0
bool isVPCOMQ(unsigned Opcode) {
18513
0
  switch (Opcode) {
18514
0
  case VPCOMQmi:
18515
0
  case VPCOMQri:
18516
0
    return true;
18517
0
  }
18518
0
  return false;
18519
0
}
18520
18521
0
bool isFXRSTOR(unsigned Opcode) {
18522
0
  return Opcode == FXRSTOR;
18523
0
}
18524
18525
0
bool isVPCMPUW(unsigned Opcode) {
18526
0
  switch (Opcode) {
18527
0
  case VPCMPUWZ128rmi:
18528
0
  case VPCMPUWZ128rmik:
18529
0
  case VPCMPUWZ128rri:
18530
0
  case VPCMPUWZ128rrik:
18531
0
  case VPCMPUWZ256rmi:
18532
0
  case VPCMPUWZ256rmik:
18533
0
  case VPCMPUWZ256rri:
18534
0
  case VPCMPUWZ256rrik:
18535
0
  case VPCMPUWZrmi:
18536
0
  case VPCMPUWZrmik:
18537
0
  case VPCMPUWZrri:
18538
0
  case VPCMPUWZrrik:
18539
0
    return true;
18540
0
  }
18541
0
  return false;
18542
0
}
18543
18544
0
bool isWBINVD(unsigned Opcode) {
18545
0
  return Opcode == WBINVD;
18546
0
}
18547
18548
0
bool isVCVTTPD2UDQ(unsigned Opcode) {
18549
0
  switch (Opcode) {
18550
0
  case VCVTTPD2UDQZ128rm:
18551
0
  case VCVTTPD2UDQZ128rmb:
18552
0
  case VCVTTPD2UDQZ128rmbk:
18553
0
  case VCVTTPD2UDQZ128rmbkz:
18554
0
  case VCVTTPD2UDQZ128rmk:
18555
0
  case VCVTTPD2UDQZ128rmkz:
18556
0
  case VCVTTPD2UDQZ128rr:
18557
0
  case VCVTTPD2UDQZ128rrk:
18558
0
  case VCVTTPD2UDQZ128rrkz:
18559
0
  case VCVTTPD2UDQZ256rm:
18560
0
  case VCVTTPD2UDQZ256rmb:
18561
0
  case VCVTTPD2UDQZ256rmbk:
18562
0
  case VCVTTPD2UDQZ256rmbkz:
18563
0
  case VCVTTPD2UDQZ256rmk:
18564
0
  case VCVTTPD2UDQZ256rmkz:
18565
0
  case VCVTTPD2UDQZ256rr:
18566
0
  case VCVTTPD2UDQZ256rrk:
18567
0
  case VCVTTPD2UDQZ256rrkz:
18568
0
  case VCVTTPD2UDQZrm:
18569
0
  case VCVTTPD2UDQZrmb:
18570
0
  case VCVTTPD2UDQZrmbk:
18571
0
  case VCVTTPD2UDQZrmbkz:
18572
0
  case VCVTTPD2UDQZrmk:
18573
0
  case VCVTTPD2UDQZrmkz:
18574
0
  case VCVTTPD2UDQZrr:
18575
0
  case VCVTTPD2UDQZrrb:
18576
0
  case VCVTTPD2UDQZrrbk:
18577
0
  case VCVTTPD2UDQZrrbkz:
18578
0
  case VCVTTPD2UDQZrrk:
18579
0
  case VCVTTPD2UDQZrrkz:
18580
0
    return true;
18581
0
  }
18582
0
  return false;
18583
0
}
18584
18585
0
bool isPFRCPIT2(unsigned Opcode) {
18586
0
  switch (Opcode) {
18587
0
  case PFRCPIT2rm:
18588
0
  case PFRCPIT2rr:
18589
0
    return true;
18590
0
  }
18591
0
  return false;
18592
0
}
18593
18594
0
bool isVPERMT2W(unsigned Opcode) {
18595
0
  switch (Opcode) {
18596
0
  case VPERMT2WZ128rm:
18597
0
  case VPERMT2WZ128rmk:
18598
0
  case VPERMT2WZ128rmkz:
18599
0
  case VPERMT2WZ128rr:
18600
0
  case VPERMT2WZ128rrk:
18601
0
  case VPERMT2WZ128rrkz:
18602
0
  case VPERMT2WZ256rm:
18603
0
  case VPERMT2WZ256rmk:
18604
0
  case VPERMT2WZ256rmkz:
18605
0
  case VPERMT2WZ256rr:
18606
0
  case VPERMT2WZ256rrk:
18607
0
  case VPERMT2WZ256rrkz:
18608
0
  case VPERMT2WZrm:
18609
0
  case VPERMT2WZrmk:
18610
0
  case VPERMT2WZrmkz:
18611
0
  case VPERMT2WZrr:
18612
0
  case VPERMT2WZrrk:
18613
0
  case VPERMT2WZrrkz:
18614
0
    return true;
18615
0
  }
18616
0
  return false;
18617
0
}
18618
18619
0
bool isVEXTRACTF32X4(unsigned Opcode) {
18620
0
  switch (Opcode) {
18621
0
  case VEXTRACTF32x4Z256mr:
18622
0
  case VEXTRACTF32x4Z256mrk:
18623
0
  case VEXTRACTF32x4Z256rr:
18624
0
  case VEXTRACTF32x4Z256rrk:
18625
0
  case VEXTRACTF32x4Z256rrkz:
18626
0
  case VEXTRACTF32x4Zmr:
18627
0
  case VEXTRACTF32x4Zmrk:
18628
0
  case VEXTRACTF32x4Zrr:
18629
0
  case VEXTRACTF32x4Zrrk:
18630
0
  case VEXTRACTF32x4Zrrkz:
18631
0
    return true;
18632
0
  }
18633
0
  return false;
18634
0
}
18635
18636
0
bool isVGATHERPF0DPD(unsigned Opcode) {
18637
0
  return Opcode == VGATHERPF0DPDm;
18638
0
}
18639
18640
0
bool isVBROADCASTF32X2(unsigned Opcode) {
18641
0
  switch (Opcode) {
18642
0
  case VBROADCASTF32X2Z256rm:
18643
0
  case VBROADCASTF32X2Z256rmk:
18644
0
  case VBROADCASTF32X2Z256rmkz:
18645
0
  case VBROADCASTF32X2Z256rr:
18646
0
  case VBROADCASTF32X2Z256rrk:
18647
0
  case VBROADCASTF32X2Z256rrkz:
18648
0
  case VBROADCASTF32X2Zrm:
18649
0
  case VBROADCASTF32X2Zrmk:
18650
0
  case VBROADCASTF32X2Zrmkz:
18651
0
  case VBROADCASTF32X2Zrr:
18652
0
  case VBROADCASTF32X2Zrrk:
18653
0
  case VBROADCASTF32X2Zrrkz:
18654
0
    return true;
18655
0
  }
18656
0
  return false;
18657
0
}
18658
18659
0
bool isVRCP14SD(unsigned Opcode) {
18660
0
  switch (Opcode) {
18661
0
  case VRCP14SDZrm:
18662
0
  case VRCP14SDZrmk:
18663
0
  case VRCP14SDZrmkz:
18664
0
  case VRCP14SDZrr:
18665
0
  case VRCP14SDZrrk:
18666
0
  case VRCP14SDZrrkz:
18667
0
    return true;
18668
0
  }
18669
0
  return false;
18670
0
}
18671
18672
0
bool isPABSD(unsigned Opcode) {
18673
0
  switch (Opcode) {
18674
0
  case MMX_PABSDrm:
18675
0
  case MMX_PABSDrr:
18676
0
  case PABSDrm:
18677
0
  case PABSDrr:
18678
0
    return true;
18679
0
  }
18680
0
  return false;
18681
0
}
18682
18683
0
bool isLAHF(unsigned Opcode) {
18684
0
  return Opcode == LAHF;
18685
0
}
18686
18687
0
bool isPINSRB(unsigned Opcode) {
18688
0
  switch (Opcode) {
18689
0
  case PINSRBrm:
18690
0
  case PINSRBrr:
18691
0
    return true;
18692
0
  }
18693
0
  return false;
18694
0
}
18695
18696
0
bool isSKINIT(unsigned Opcode) {
18697
0
  return Opcode == SKINIT;
18698
0
}
18699
18700
0
bool isENTER(unsigned Opcode) {
18701
0
  return Opcode == ENTER;
18702
0
}
18703
18704
0
bool isVCVTSI2SS(unsigned Opcode) {
18705
0
  switch (Opcode) {
18706
0
  case VCVTSI2SSZrm_Int:
18707
0
  case VCVTSI2SSZrr_Int:
18708
0
  case VCVTSI2SSZrrb_Int:
18709
0
  case VCVTSI2SSrm_Int:
18710
0
  case VCVTSI2SSrr_Int:
18711
0
  case VCVTSI642SSZrm_Int:
18712
0
  case VCVTSI642SSZrr_Int:
18713
0
  case VCVTSI642SSZrrb_Int:
18714
0
  case VCVTSI642SSrm_Int:
18715
0
  case VCVTSI642SSrr_Int:
18716
0
    return true;
18717
0
  }
18718
0
  return false;
18719
0
}
18720
18721
0
bool isVFMADD231PD(unsigned Opcode) {
18722
0
  switch (Opcode) {
18723
0
  case VFMADD231PDYm:
18724
0
  case VFMADD231PDYr:
18725
0
  case VFMADD231PDZ128m:
18726
0
  case VFMADD231PDZ128mb:
18727
0
  case VFMADD231PDZ128mbk:
18728
0
  case VFMADD231PDZ128mbkz:
18729
0
  case VFMADD231PDZ128mk:
18730
0
  case VFMADD231PDZ128mkz:
18731
0
  case VFMADD231PDZ128r:
18732
0
  case VFMADD231PDZ128rk:
18733
0
  case VFMADD231PDZ128rkz:
18734
0
  case VFMADD231PDZ256m:
18735
0
  case VFMADD231PDZ256mb:
18736
0
  case VFMADD231PDZ256mbk:
18737
0
  case VFMADD231PDZ256mbkz:
18738
0
  case VFMADD231PDZ256mk:
18739
0
  case VFMADD231PDZ256mkz:
18740
0
  case VFMADD231PDZ256r:
18741
0
  case VFMADD231PDZ256rk:
18742
0
  case VFMADD231PDZ256rkz:
18743
0
  case VFMADD231PDZm:
18744
0
  case VFMADD231PDZmb:
18745
0
  case VFMADD231PDZmbk:
18746
0
  case VFMADD231PDZmbkz:
18747
0
  case VFMADD231PDZmk:
18748
0
  case VFMADD231PDZmkz:
18749
0
  case VFMADD231PDZr:
18750
0
  case VFMADD231PDZrb:
18751
0
  case VFMADD231PDZrbk:
18752
0
  case VFMADD231PDZrbkz:
18753
0
  case VFMADD231PDZrk:
18754
0
  case VFMADD231PDZrkz:
18755
0
  case VFMADD231PDm:
18756
0
  case VFMADD231PDr:
18757
0
    return true;
18758
0
  }
18759
0
  return false;
18760
0
}
18761
18762
0
bool isLOADIWKEY(unsigned Opcode) {
18763
0
  return Opcode == LOADIWKEY;
18764
0
}
18765
18766
0
bool isVMOVNTDQA(unsigned Opcode) {
18767
0
  switch (Opcode) {
18768
0
  case VMOVNTDQAYrm:
18769
0
  case VMOVNTDQAZ128rm:
18770
0
  case VMOVNTDQAZ256rm:
18771
0
  case VMOVNTDQAZrm:
18772
0
  case VMOVNTDQArm:
18773
0
    return true;
18774
0
  }
18775
0
  return false;
18776
0
}
18777
18778
0
bool isVPERMT2PS(unsigned Opcode) {
18779
0
  switch (Opcode) {
18780
0
  case VPERMT2PSZ128rm:
18781
0
  case VPERMT2PSZ128rmb:
18782
0
  case VPERMT2PSZ128rmbk:
18783
0
  case VPERMT2PSZ128rmbkz:
18784
0
  case VPERMT2PSZ128rmk:
18785
0
  case VPERMT2PSZ128rmkz:
18786
0
  case VPERMT2PSZ128rr:
18787
0
  case VPERMT2PSZ128rrk:
18788
0
  case VPERMT2PSZ128rrkz:
18789
0
  case VPERMT2PSZ256rm:
18790
0
  case VPERMT2PSZ256rmb:
18791
0
  case VPERMT2PSZ256rmbk:
18792
0
  case VPERMT2PSZ256rmbkz:
18793
0
  case VPERMT2PSZ256rmk:
18794
0
  case VPERMT2PSZ256rmkz:
18795
0
  case VPERMT2PSZ256rr:
18796
0
  case VPERMT2PSZ256rrk:
18797
0
  case VPERMT2PSZ256rrkz:
18798
0
  case VPERMT2PSZrm:
18799
0
  case VPERMT2PSZrmb:
18800
0
  case VPERMT2PSZrmbk:
18801
0
  case VPERMT2PSZrmbkz:
18802
0
  case VPERMT2PSZrmk:
18803
0
  case VPERMT2PSZrmkz:
18804
0
  case VPERMT2PSZrr:
18805
0
  case VPERMT2PSZrrk:
18806
0
  case VPERMT2PSZrrkz:
18807
0
    return true;
18808
0
  }
18809
0
  return false;
18810
0
}
18811
18812
0
bool isPUSHF(unsigned Opcode) {
18813
0
  return Opcode == PUSHF16;
18814
0
}
18815
18816
0
bool isMPSADBW(unsigned Opcode) {
18817
0
  switch (Opcode) {
18818
0
  case MPSADBWrmi:
18819
0
  case MPSADBWrri:
18820
0
    return true;
18821
0
  }
18822
0
  return false;
18823
0
}
18824
18825
0
bool isVRSQRT14SS(unsigned Opcode) {
18826
0
  switch (Opcode) {
18827
0
  case VRSQRT14SSZrm:
18828
0
  case VRSQRT14SSZrmk:
18829
0
  case VRSQRT14SSZrmkz:
18830
0
  case VRSQRT14SSZrr:
18831
0
  case VRSQRT14SSZrrk:
18832
0
  case VRSQRT14SSZrrkz:
18833
0
    return true;
18834
0
  }
18835
0
  return false;
18836
0
}
18837
18838
0
bool isVCVTDQ2PD(unsigned Opcode) {
18839
0
  switch (Opcode) {
18840
0
  case VCVTDQ2PDYrm:
18841
0
  case VCVTDQ2PDYrr:
18842
0
  case VCVTDQ2PDZ128rm:
18843
0
  case VCVTDQ2PDZ128rmb:
18844
0
  case VCVTDQ2PDZ128rmbk:
18845
0
  case VCVTDQ2PDZ128rmbkz:
18846
0
  case VCVTDQ2PDZ128rmk:
18847
0
  case VCVTDQ2PDZ128rmkz:
18848
0
  case VCVTDQ2PDZ128rr:
18849
0
  case VCVTDQ2PDZ128rrk:
18850
0
  case VCVTDQ2PDZ128rrkz:
18851
0
  case VCVTDQ2PDZ256rm:
18852
0
  case VCVTDQ2PDZ256rmb:
18853
0
  case VCVTDQ2PDZ256rmbk:
18854
0
  case VCVTDQ2PDZ256rmbkz:
18855
0
  case VCVTDQ2PDZ256rmk:
18856
0
  case VCVTDQ2PDZ256rmkz:
18857
0
  case VCVTDQ2PDZ256rr:
18858
0
  case VCVTDQ2PDZ256rrk:
18859
0
  case VCVTDQ2PDZ256rrkz:
18860
0
  case VCVTDQ2PDZrm:
18861
0
  case VCVTDQ2PDZrmb:
18862
0
  case VCVTDQ2PDZrmbk:
18863
0
  case VCVTDQ2PDZrmbkz:
18864
0
  case VCVTDQ2PDZrmk:
18865
0
  case VCVTDQ2PDZrmkz:
18866
0
  case VCVTDQ2PDZrr:
18867
0
  case VCVTDQ2PDZrrk:
18868
0
  case VCVTDQ2PDZrrkz:
18869
0
  case VCVTDQ2PDrm:
18870
0
  case VCVTDQ2PDrr:
18871
0
    return true;
18872
0
  }
18873
0
  return false;
18874
0
}
18875
18876
0
bool isVORPS(unsigned Opcode) {
18877
0
  switch (Opcode) {
18878
0
  case VORPSYrm:
18879
0
  case VORPSYrr:
18880
0
  case VORPSZ128rm:
18881
0
  case VORPSZ128rmb:
18882
0
  case VORPSZ128rmbk:
18883
0
  case VORPSZ128rmbkz:
18884
0
  case VORPSZ128rmk:
18885
0
  case VORPSZ128rmkz:
18886
0
  case VORPSZ128rr:
18887
0
  case VORPSZ128rrk:
18888
0
  case VORPSZ128rrkz:
18889
0
  case VORPSZ256rm:
18890
0
  case VORPSZ256rmb:
18891
0
  case VORPSZ256rmbk:
18892
0
  case VORPSZ256rmbkz:
18893
0
  case VORPSZ256rmk:
18894
0
  case VORPSZ256rmkz:
18895
0
  case VORPSZ256rr:
18896
0
  case VORPSZ256rrk:
18897
0
  case VORPSZ256rrkz:
18898
0
  case VORPSZrm:
18899
0
  case VORPSZrmb:
18900
0
  case VORPSZrmbk:
18901
0
  case VORPSZrmbkz:
18902
0
  case VORPSZrmk:
18903
0
  case VORPSZrmkz:
18904
0
  case VORPSZrr:
18905
0
  case VORPSZrrk:
18906
0
  case VORPSZrrkz:
18907
0
  case VORPSrm:
18908
0
  case VORPSrr:
18909
0
    return true;
18910
0
  }
18911
0
  return false;
18912
0
}
18913
18914
0
bool isVPEXPANDQ(unsigned Opcode) {
18915
0
  switch (Opcode) {
18916
0
  case VPEXPANDQZ128rm:
18917
0
  case VPEXPANDQZ128rmk:
18918
0
  case VPEXPANDQZ128rmkz:
18919
0
  case VPEXPANDQZ128rr:
18920
0
  case VPEXPANDQZ128rrk:
18921
0
  case VPEXPANDQZ128rrkz:
18922
0
  case VPEXPANDQZ256rm:
18923
0
  case VPEXPANDQZ256rmk:
18924
0
  case VPEXPANDQZ256rmkz:
18925
0
  case VPEXPANDQZ256rr:
18926
0
  case VPEXPANDQZ256rrk:
18927
0
  case VPEXPANDQZ256rrkz:
18928
0
  case VPEXPANDQZrm:
18929
0
  case VPEXPANDQZrmk:
18930
0
  case VPEXPANDQZrmkz:
18931
0
  case VPEXPANDQZrr:
18932
0
  case VPEXPANDQZrrk:
18933
0
  case VPEXPANDQZrrkz:
18934
0
    return true;
18935
0
  }
18936
0
  return false;
18937
0
}
18938
18939
0
bool isVPSHRDD(unsigned Opcode) {
18940
0
  switch (Opcode) {
18941
0
  case VPSHRDDZ128rmbi:
18942
0
  case VPSHRDDZ128rmbik:
18943
0
  case VPSHRDDZ128rmbikz:
18944
0
  case VPSHRDDZ128rmi:
18945
0
  case VPSHRDDZ128rmik:
18946
0
  case VPSHRDDZ128rmikz:
18947
0
  case VPSHRDDZ128rri:
18948
0
  case VPSHRDDZ128rrik:
18949
0
  case VPSHRDDZ128rrikz:
18950
0
  case VPSHRDDZ256rmbi:
18951
0
  case VPSHRDDZ256rmbik:
18952
0
  case VPSHRDDZ256rmbikz:
18953
0
  case VPSHRDDZ256rmi:
18954
0
  case VPSHRDDZ256rmik:
18955
0
  case VPSHRDDZ256rmikz:
18956
0
  case VPSHRDDZ256rri:
18957
0
  case VPSHRDDZ256rrik:
18958
0
  case VPSHRDDZ256rrikz:
18959
0
  case VPSHRDDZrmbi:
18960
0
  case VPSHRDDZrmbik:
18961
0
  case VPSHRDDZrmbikz:
18962
0
  case VPSHRDDZrmi:
18963
0
  case VPSHRDDZrmik:
18964
0
  case VPSHRDDZrmikz:
18965
0
  case VPSHRDDZrri:
18966
0
  case VPSHRDDZrrik:
18967
0
  case VPSHRDDZrrikz:
18968
0
    return true;
18969
0
  }
18970
0
  return false;
18971
0
}
18972
18973
0
bool isTDPBSSD(unsigned Opcode) {
18974
0
  return Opcode == TDPBSSD;
18975
0
}
18976
18977
0
bool isTESTUI(unsigned Opcode) {
18978
0
  return Opcode == TESTUI;
18979
0
}
18980
18981
0
bool isVFMADDPD(unsigned Opcode) {
18982
0
  switch (Opcode) {
18983
0
  case VFMADDPD4Ymr:
18984
0
  case VFMADDPD4Yrm:
18985
0
  case VFMADDPD4Yrr:
18986
0
  case VFMADDPD4Yrr_REV:
18987
0
  case VFMADDPD4mr:
18988
0
  case VFMADDPD4rm:
18989
0
  case VFMADDPD4rr:
18990
0
  case VFMADDPD4rr_REV:
18991
0
    return true;
18992
0
  }
18993
0
  return false;
18994
0
}
18995
18996
0
bool isVPANDND(unsigned Opcode) {
18997
0
  switch (Opcode) {
18998
0
  case VPANDNDZ128rm:
18999
0
  case VPANDNDZ128rmb:
19000
0
  case VPANDNDZ128rmbk:
19001
0
  case VPANDNDZ128rmbkz:
19002
0
  case VPANDNDZ128rmk:
19003
0
  case VPANDNDZ128rmkz:
19004
0
  case VPANDNDZ128rr:
19005
0
  case VPANDNDZ128rrk:
19006
0
  case VPANDNDZ128rrkz:
19007
0
  case VPANDNDZ256rm:
19008
0
  case VPANDNDZ256rmb:
19009
0
  case VPANDNDZ256rmbk:
19010
0
  case VPANDNDZ256rmbkz:
19011
0
  case VPANDNDZ256rmk:
19012
0
  case VPANDNDZ256rmkz:
19013
0
  case VPANDNDZ256rr:
19014
0
  case VPANDNDZ256rrk:
19015
0
  case VPANDNDZ256rrkz:
19016
0
  case VPANDNDZrm:
19017
0
  case VPANDNDZrmb:
19018
0
  case VPANDNDZrmbk:
19019
0
  case VPANDNDZrmbkz:
19020
0
  case VPANDNDZrmk:
19021
0
  case VPANDNDZrmkz:
19022
0
  case VPANDNDZrr:
19023
0
  case VPANDNDZrrk:
19024
0
  case VPANDNDZrrkz:
19025
0
    return true;
19026
0
  }
19027
0
  return false;
19028
0
}
19029
19030
0
bool isVPMOVSDB(unsigned Opcode) {
19031
0
  switch (Opcode) {
19032
0
  case VPMOVSDBZ128mr:
19033
0
  case VPMOVSDBZ128mrk:
19034
0
  case VPMOVSDBZ128rr:
19035
0
  case VPMOVSDBZ128rrk:
19036
0
  case VPMOVSDBZ128rrkz:
19037
0
  case VPMOVSDBZ256mr:
19038
0
  case VPMOVSDBZ256mrk:
19039
0
  case VPMOVSDBZ256rr:
19040
0
  case VPMOVSDBZ256rrk:
19041
0
  case VPMOVSDBZ256rrkz:
19042
0
  case VPMOVSDBZmr:
19043
0
  case VPMOVSDBZmrk:
19044
0
  case VPMOVSDBZrr:
19045
0
  case VPMOVSDBZrrk:
19046
0
  case VPMOVSDBZrrkz:
19047
0
    return true;
19048
0
  }
19049
0
  return false;
19050
0
}
19051
19052
0
bool isVPBROADCASTB(unsigned Opcode) {
19053
0
  switch (Opcode) {
19054
0
  case VPBROADCASTBYrm:
19055
0
  case VPBROADCASTBYrr:
19056
0
  case VPBROADCASTBZ128rm:
19057
0
  case VPBROADCASTBZ128rmk:
19058
0
  case VPBROADCASTBZ128rmkz:
19059
0
  case VPBROADCASTBZ128rr:
19060
0
  case VPBROADCASTBZ128rrk:
19061
0
  case VPBROADCASTBZ128rrkz:
19062
0
  case VPBROADCASTBZ256rm:
19063
0
  case VPBROADCASTBZ256rmk:
19064
0
  case VPBROADCASTBZ256rmkz:
19065
0
  case VPBROADCASTBZ256rr:
19066
0
  case VPBROADCASTBZ256rrk:
19067
0
  case VPBROADCASTBZ256rrkz:
19068
0
  case VPBROADCASTBZrm:
19069
0
  case VPBROADCASTBZrmk:
19070
0
  case VPBROADCASTBZrmkz:
19071
0
  case VPBROADCASTBZrr:
19072
0
  case VPBROADCASTBZrrk:
19073
0
  case VPBROADCASTBZrrkz:
19074
0
  case VPBROADCASTBrZ128rr:
19075
0
  case VPBROADCASTBrZ128rrk:
19076
0
  case VPBROADCASTBrZ128rrkz:
19077
0
  case VPBROADCASTBrZ256rr:
19078
0
  case VPBROADCASTBrZ256rrk:
19079
0
  case VPBROADCASTBrZ256rrkz:
19080
0
  case VPBROADCASTBrZrr:
19081
0
  case VPBROADCASTBrZrrk:
19082
0
  case VPBROADCASTBrZrrkz:
19083
0
  case VPBROADCASTBrm:
19084
0
  case VPBROADCASTBrr:
19085
0
    return true;
19086
0
  }
19087
0
  return false;
19088
0
}
19089
19090
0
bool isCVTPI2PD(unsigned Opcode) {
19091
0
  switch (Opcode) {
19092
0
  case MMX_CVTPI2PDrm:
19093
0
  case MMX_CVTPI2PDrr:
19094
0
    return true;
19095
0
  }
19096
0
  return false;
19097
0
}
19098
19099
0
bool isVPERMI2B(unsigned Opcode) {
19100
0
  switch (Opcode) {
19101
0
  case VPERMI2BZ128rm:
19102
0
  case VPERMI2BZ128rmk:
19103
0
  case VPERMI2BZ128rmkz:
19104
0
  case VPERMI2BZ128rr:
19105
0
  case VPERMI2BZ128rrk:
19106
0
  case VPERMI2BZ128rrkz:
19107
0
  case VPERMI2BZ256rm:
19108
0
  case VPERMI2BZ256rmk:
19109
0
  case VPERMI2BZ256rmkz:
19110
0
  case VPERMI2BZ256rr:
19111
0
  case VPERMI2BZ256rrk:
19112
0
  case VPERMI2BZ256rrkz:
19113
0
  case VPERMI2BZrm:
19114
0
  case VPERMI2BZrmk:
19115
0
  case VPERMI2BZrmkz:
19116
0
  case VPERMI2BZrr:
19117
0
  case VPERMI2BZrrk:
19118
0
  case VPERMI2BZrrkz:
19119
0
    return true;
19120
0
  }
19121
0
  return false;
19122
0
}
19123
19124
0
bool isVPMINSB(unsigned Opcode) {
19125
0
  switch (Opcode) {
19126
0
  case VPMINSBYrm:
19127
0
  case VPMINSBYrr:
19128
0
  case VPMINSBZ128rm:
19129
0
  case VPMINSBZ128rmk:
19130
0
  case VPMINSBZ128rmkz:
19131
0
  case VPMINSBZ128rr:
19132
0
  case VPMINSBZ128rrk:
19133
0
  case VPMINSBZ128rrkz:
19134
0
  case VPMINSBZ256rm:
19135
0
  case VPMINSBZ256rmk:
19136
0
  case VPMINSBZ256rmkz:
19137
0
  case VPMINSBZ256rr:
19138
0
  case VPMINSBZ256rrk:
19139
0
  case VPMINSBZ256rrkz:
19140
0
  case VPMINSBZrm:
19141
0
  case VPMINSBZrmk:
19142
0
  case VPMINSBZrmkz:
19143
0
  case VPMINSBZrr:
19144
0
  case VPMINSBZrrk:
19145
0
  case VPMINSBZrrkz:
19146
0
  case VPMINSBrm:
19147
0
  case VPMINSBrr:
19148
0
    return true;
19149
0
  }
19150
0
  return false;
19151
0
}
19152
19153
0
bool isLAR(unsigned Opcode) {
19154
0
  switch (Opcode) {
19155
0
  case LAR16rm:
19156
0
  case LAR16rr:
19157
0
  case LAR32rm:
19158
0
  case LAR32rr:
19159
0
  case LAR64rm:
19160
0
  case LAR64rr:
19161
0
    return true;
19162
0
  }
19163
0
  return false;
19164
0
}
19165
19166
0
bool isINVLPGB(unsigned Opcode) {
19167
0
  switch (Opcode) {
19168
0
  case INVLPGB32:
19169
0
  case INVLPGB64:
19170
0
    return true;
19171
0
  }
19172
0
  return false;
19173
0
}
19174
19175
0
bool isTLBSYNC(unsigned Opcode) {
19176
0
  return Opcode == TLBSYNC;
19177
0
}
19178
19179
0
bool isFDIVP(unsigned Opcode) {
19180
0
  return Opcode == DIV_FPrST0;
19181
0
}
19182
19183
0
bool isVPSRLW(unsigned Opcode) {
19184
0
  switch (Opcode) {
19185
0
  case VPSRLWYri:
19186
0
  case VPSRLWYrm:
19187
0
  case VPSRLWYrr:
19188
0
  case VPSRLWZ128mi:
19189
0
  case VPSRLWZ128mik:
19190
0
  case VPSRLWZ128mikz:
19191
0
  case VPSRLWZ128ri:
19192
0
  case VPSRLWZ128rik:
19193
0
  case VPSRLWZ128rikz:
19194
0
  case VPSRLWZ128rm:
19195
0
  case VPSRLWZ128rmk:
19196
0
  case VPSRLWZ128rmkz:
19197
0
  case VPSRLWZ128rr:
19198
0
  case VPSRLWZ128rrk:
19199
0
  case VPSRLWZ128rrkz:
19200
0
  case VPSRLWZ256mi:
19201
0
  case VPSRLWZ256mik:
19202
0
  case VPSRLWZ256mikz:
19203
0
  case VPSRLWZ256ri:
19204
0
  case VPSRLWZ256rik:
19205
0
  case VPSRLWZ256rikz:
19206
0
  case VPSRLWZ256rm:
19207
0
  case VPSRLWZ256rmk:
19208
0
  case VPSRLWZ256rmkz:
19209
0
  case VPSRLWZ256rr:
19210
0
  case VPSRLWZ256rrk:
19211
0
  case VPSRLWZ256rrkz:
19212
0
  case VPSRLWZmi:
19213
0
  case VPSRLWZmik:
19214
0
  case VPSRLWZmikz:
19215
0
  case VPSRLWZri:
19216
0
  case VPSRLWZrik:
19217
0
  case VPSRLWZrikz:
19218
0
  case VPSRLWZrm:
19219
0
  case VPSRLWZrmk:
19220
0
  case VPSRLWZrmkz:
19221
0
  case VPSRLWZrr:
19222
0
  case VPSRLWZrrk:
19223
0
  case VPSRLWZrrkz:
19224
0
  case VPSRLWri:
19225
0
  case VPSRLWrm:
19226
0
  case VPSRLWrr:
19227
0
    return true;
19228
0
  }
19229
0
  return false;
19230
0
}
19231
19232
0
bool isVRCP28SS(unsigned Opcode) {
19233
0
  switch (Opcode) {
19234
0
  case VRCP28SSZm:
19235
0
  case VRCP28SSZmk:
19236
0
  case VRCP28SSZmkz:
19237
0
  case VRCP28SSZr:
19238
0
  case VRCP28SSZrb:
19239
0
  case VRCP28SSZrbk:
19240
0
  case VRCP28SSZrbkz:
19241
0
  case VRCP28SSZrk:
19242
0
  case VRCP28SSZrkz:
19243
0
    return true;
19244
0
  }
19245
0
  return false;
19246
0
}
19247
19248
0
bool isVMOVHPS(unsigned Opcode) {
19249
0
  switch (Opcode) {
19250
0
  case VMOVHPSZ128mr:
19251
0
  case VMOVHPSZ128rm:
19252
0
  case VMOVHPSmr:
19253
0
  case VMOVHPSrm:
19254
0
    return true;
19255
0
  }
19256
0
  return false;
19257
0
}
19258
19259
0
bool isVPMACSSDD(unsigned Opcode) {
19260
0
  switch (Opcode) {
19261
0
  case VPMACSSDDrm:
19262
0
  case VPMACSSDDrr:
19263
0
    return true;
19264
0
  }
19265
0
  return false;
19266
0
}
19267
19268
0
bool isPEXT(unsigned Opcode) {
19269
0
  switch (Opcode) {
19270
0
  case PEXT32rm:
19271
0
  case PEXT32rm_EVEX:
19272
0
  case PEXT32rr:
19273
0
  case PEXT32rr_EVEX:
19274
0
  case PEXT64rm:
19275
0
  case PEXT64rm_EVEX:
19276
0
  case PEXT64rr:
19277
0
  case PEXT64rr_EVEX:
19278
0
    return true;
19279
0
  }
19280
0
  return false;
19281
0
}
19282
19283
0
bool isVRSQRT14SD(unsigned Opcode) {
19284
0
  switch (Opcode) {
19285
0
  case VRSQRT14SDZrm:
19286
0
  case VRSQRT14SDZrmk:
19287
0
  case VRSQRT14SDZrmkz:
19288
0
  case VRSQRT14SDZrr:
19289
0
  case VRSQRT14SDZrrk:
19290
0
  case VRSQRT14SDZrrkz:
19291
0
    return true;
19292
0
  }
19293
0
  return false;
19294
0
}
19295
19296
0
bool isVPDPWSSD(unsigned Opcode) {
19297
0
  switch (Opcode) {
19298
0
  case VPDPWSSDYrm:
19299
0
  case VPDPWSSDYrr:
19300
0
  case VPDPWSSDZ128m:
19301
0
  case VPDPWSSDZ128mb:
19302
0
  case VPDPWSSDZ128mbk:
19303
0
  case VPDPWSSDZ128mbkz:
19304
0
  case VPDPWSSDZ128mk:
19305
0
  case VPDPWSSDZ128mkz:
19306
0
  case VPDPWSSDZ128r:
19307
0
  case VPDPWSSDZ128rk:
19308
0
  case VPDPWSSDZ128rkz:
19309
0
  case VPDPWSSDZ256m:
19310
0
  case VPDPWSSDZ256mb:
19311
0
  case VPDPWSSDZ256mbk:
19312
0
  case VPDPWSSDZ256mbkz:
19313
0
  case VPDPWSSDZ256mk:
19314
0
  case VPDPWSSDZ256mkz:
19315
0
  case VPDPWSSDZ256r:
19316
0
  case VPDPWSSDZ256rk:
19317
0
  case VPDPWSSDZ256rkz:
19318
0
  case VPDPWSSDZm:
19319
0
  case VPDPWSSDZmb:
19320
0
  case VPDPWSSDZmbk:
19321
0
  case VPDPWSSDZmbkz:
19322
0
  case VPDPWSSDZmk:
19323
0
  case VPDPWSSDZmkz:
19324
0
  case VPDPWSSDZr:
19325
0
  case VPDPWSSDZrk:
19326
0
  case VPDPWSSDZrkz:
19327
0
  case VPDPWSSDrm:
19328
0
  case VPDPWSSDrr:
19329
0
    return true;
19330
0
  }
19331
0
  return false;
19332
0
}
19333
19334
0
bool isVFMSUB231SD(unsigned Opcode) {
19335
0
  switch (Opcode) {
19336
0
  case VFMSUB231SDZm_Int:
19337
0
  case VFMSUB231SDZm_Intk:
19338
0
  case VFMSUB231SDZm_Intkz:
19339
0
  case VFMSUB231SDZr_Int:
19340
0
  case VFMSUB231SDZr_Intk:
19341
0
  case VFMSUB231SDZr_Intkz:
19342
0
  case VFMSUB231SDZrb_Int:
19343
0
  case VFMSUB231SDZrb_Intk:
19344
0
  case VFMSUB231SDZrb_Intkz:
19345
0
  case VFMSUB231SDm_Int:
19346
0
  case VFMSUB231SDr_Int:
19347
0
    return true;
19348
0
  }
19349
0
  return false;
19350
0
}
19351
19352
0
bool isVPMOVZXWQ(unsigned Opcode) {
19353
0
  switch (Opcode) {
19354
0
  case VPMOVZXWQYrm:
19355
0
  case VPMOVZXWQYrr:
19356
0
  case VPMOVZXWQZ128rm:
19357
0
  case VPMOVZXWQZ128rmk:
19358
0
  case VPMOVZXWQZ128rmkz:
19359
0
  case VPMOVZXWQZ128rr:
19360
0
  case VPMOVZXWQZ128rrk:
19361
0
  case VPMOVZXWQZ128rrkz:
19362
0
  case VPMOVZXWQZ256rm:
19363
0
  case VPMOVZXWQZ256rmk:
19364
0
  case VPMOVZXWQZ256rmkz:
19365
0
  case VPMOVZXWQZ256rr:
19366
0
  case VPMOVZXWQZ256rrk:
19367
0
  case VPMOVZXWQZ256rrkz:
19368
0
  case VPMOVZXWQZrm:
19369
0
  case VPMOVZXWQZrmk:
19370
0
  case VPMOVZXWQZrmkz:
19371
0
  case VPMOVZXWQZrr:
19372
0
  case VPMOVZXWQZrrk:
19373
0
  case VPMOVZXWQZrrkz:
19374
0
  case VPMOVZXWQrm:
19375
0
  case VPMOVZXWQrr:
19376
0
    return true;
19377
0
  }
19378
0
  return false;
19379
0
}
19380
19381
0
bool isVMOVDQA(unsigned Opcode) {
19382
0
  switch (Opcode) {
19383
0
  case VMOVDQAYmr:
19384
0
  case VMOVDQAYrm:
19385
0
  case VMOVDQAYrr:
19386
0
  case VMOVDQAYrr_REV:
19387
0
  case VMOVDQAmr:
19388
0
  case VMOVDQArm:
19389
0
  case VMOVDQArr:
19390
0
  case VMOVDQArr_REV:
19391
0
    return true;
19392
0
  }
19393
0
  return false;
19394
0
}
19395
19396
0
bool isVFNMSUB213SD(unsigned Opcode) {
19397
0
  switch (Opcode) {
19398
0
  case VFNMSUB213SDZm_Int:
19399
0
  case VFNMSUB213SDZm_Intk:
19400
0
  case VFNMSUB213SDZm_Intkz:
19401
0
  case VFNMSUB213SDZr_Int:
19402
0
  case VFNMSUB213SDZr_Intk:
19403
0
  case VFNMSUB213SDZr_Intkz:
19404
0
  case VFNMSUB213SDZrb_Int:
19405
0
  case VFNMSUB213SDZrb_Intk:
19406
0
  case VFNMSUB213SDZrb_Intkz:
19407
0
  case VFNMSUB213SDm_Int:
19408
0
  case VFNMSUB213SDr_Int:
19409
0
    return true;
19410
0
  }
19411
0
  return false;
19412
0
}
19413
19414
0
bool isVMINPS(unsigned Opcode) {
19415
0
  switch (Opcode) {
19416
0
  case VMINPSYrm:
19417
0
  case VMINPSYrr:
19418
0
  case VMINPSZ128rm:
19419
0
  case VMINPSZ128rmb:
19420
0
  case VMINPSZ128rmbk:
19421
0
  case VMINPSZ128rmbkz:
19422
0
  case VMINPSZ128rmk:
19423
0
  case VMINPSZ128rmkz:
19424
0
  case VMINPSZ128rr:
19425
0
  case VMINPSZ128rrk:
19426
0
  case VMINPSZ128rrkz:
19427
0
  case VMINPSZ256rm:
19428
0
  case VMINPSZ256rmb:
19429
0
  case VMINPSZ256rmbk:
19430
0
  case VMINPSZ256rmbkz:
19431
0
  case VMINPSZ256rmk:
19432
0
  case VMINPSZ256rmkz:
19433
0
  case VMINPSZ256rr:
19434
0
  case VMINPSZ256rrk:
19435
0
  case VMINPSZ256rrkz:
19436
0
  case VMINPSZrm:
19437
0
  case VMINPSZrmb:
19438
0
  case VMINPSZrmbk:
19439
0
  case VMINPSZrmbkz:
19440
0
  case VMINPSZrmk:
19441
0
  case VMINPSZrmkz:
19442
0
  case VMINPSZrr:
19443
0
  case VMINPSZrrb:
19444
0
  case VMINPSZrrbk:
19445
0
  case VMINPSZrrbkz:
19446
0
  case VMINPSZrrk:
19447
0
  case VMINPSZrrkz:
19448
0
  case VMINPSrm:
19449
0
  case VMINPSrr:
19450
0
    return true;
19451
0
  }
19452
0
  return false;
19453
0
}
19454
19455
0
bool isVFMSUB231PS(unsigned Opcode) {
19456
0
  switch (Opcode) {
19457
0
  case VFMSUB231PSYm:
19458
0
  case VFMSUB231PSYr:
19459
0
  case VFMSUB231PSZ128m:
19460
0
  case VFMSUB231PSZ128mb:
19461
0
  case VFMSUB231PSZ128mbk:
19462
0
  case VFMSUB231PSZ128mbkz:
19463
0
  case VFMSUB231PSZ128mk:
19464
0
  case VFMSUB231PSZ128mkz:
19465
0
  case VFMSUB231PSZ128r:
19466
0
  case VFMSUB231PSZ128rk:
19467
0
  case VFMSUB231PSZ128rkz:
19468
0
  case VFMSUB231PSZ256m:
19469
0
  case VFMSUB231PSZ256mb:
19470
0
  case VFMSUB231PSZ256mbk:
19471
0
  case VFMSUB231PSZ256mbkz:
19472
0
  case VFMSUB231PSZ256mk:
19473
0
  case VFMSUB231PSZ256mkz:
19474
0
  case VFMSUB231PSZ256r:
19475
0
  case VFMSUB231PSZ256rk:
19476
0
  case VFMSUB231PSZ256rkz:
19477
0
  case VFMSUB231PSZm:
19478
0
  case VFMSUB231PSZmb:
19479
0
  case VFMSUB231PSZmbk:
19480
0
  case VFMSUB231PSZmbkz:
19481
0
  case VFMSUB231PSZmk:
19482
0
  case VFMSUB231PSZmkz:
19483
0
  case VFMSUB231PSZr:
19484
0
  case VFMSUB231PSZrb:
19485
0
  case VFMSUB231PSZrbk:
19486
0
  case VFMSUB231PSZrbkz:
19487
0
  case VFMSUB231PSZrk:
19488
0
  case VFMSUB231PSZrkz:
19489
0
  case VFMSUB231PSm:
19490
0
  case VFMSUB231PSr:
19491
0
    return true;
19492
0
  }
19493
0
  return false;
19494
0
}
19495
19496
0
bool isVPCOMPRESSB(unsigned Opcode) {
19497
0
  switch (Opcode) {
19498
0
  case VPCOMPRESSBZ128mr:
19499
0
  case VPCOMPRESSBZ128mrk:
19500
0
  case VPCOMPRESSBZ128rr:
19501
0
  case VPCOMPRESSBZ128rrk:
19502
0
  case VPCOMPRESSBZ128rrkz:
19503
0
  case VPCOMPRESSBZ256mr:
19504
0
  case VPCOMPRESSBZ256mrk:
19505
0
  case VPCOMPRESSBZ256rr:
19506
0
  case VPCOMPRESSBZ256rrk:
19507
0
  case VPCOMPRESSBZ256rrkz:
19508
0
  case VPCOMPRESSBZmr:
19509
0
  case VPCOMPRESSBZmrk:
19510
0
  case VPCOMPRESSBZrr:
19511
0
  case VPCOMPRESSBZrrk:
19512
0
  case VPCOMPRESSBZrrkz:
19513
0
    return true;
19514
0
  }
19515
0
  return false;
19516
0
}
19517
19518
0
bool isVPCMPEQQ(unsigned Opcode) {
19519
0
  switch (Opcode) {
19520
0
  case VPCMPEQQYrm:
19521
0
  case VPCMPEQQYrr:
19522
0
  case VPCMPEQQZ128rm:
19523
0
  case VPCMPEQQZ128rmb:
19524
0
  case VPCMPEQQZ128rmbk:
19525
0
  case VPCMPEQQZ128rmk:
19526
0
  case VPCMPEQQZ128rr:
19527
0
  case VPCMPEQQZ128rrk:
19528
0
  case VPCMPEQQZ256rm:
19529
0
  case VPCMPEQQZ256rmb:
19530
0
  case VPCMPEQQZ256rmbk:
19531
0
  case VPCMPEQQZ256rmk:
19532
0
  case VPCMPEQQZ256rr:
19533
0
  case VPCMPEQQZ256rrk:
19534
0
  case VPCMPEQQZrm:
19535
0
  case VPCMPEQQZrmb:
19536
0
  case VPCMPEQQZrmbk:
19537
0
  case VPCMPEQQZrmk:
19538
0
  case VPCMPEQQZrr:
19539
0
  case VPCMPEQQZrrk:
19540
0
  case VPCMPEQQrm:
19541
0
  case VPCMPEQQrr:
19542
0
    return true;
19543
0
  }
19544
0
  return false;
19545
0
}
19546
19547
0
bool isVRCPSS(unsigned Opcode) {
19548
0
  switch (Opcode) {
19549
0
  case VRCPSSm_Int:
19550
0
  case VRCPSSr_Int:
19551
0
    return true;
19552
0
  }
19553
0
  return false;
19554
0
}
19555
19556
0
bool isVSCATTERPF1DPS(unsigned Opcode) {
19557
0
  return Opcode == VSCATTERPF1DPSm;
19558
0
}
19559
19560
0
bool isVPHADDUBW(unsigned Opcode) {
19561
0
  switch (Opcode) {
19562
0
  case VPHADDUBWrm:
19563
0
  case VPHADDUBWrr:
19564
0
    return true;
19565
0
  }
19566
0
  return false;
19567
0
}
19568
19569
0
bool isXORPD(unsigned Opcode) {
19570
0
  switch (Opcode) {
19571
0
  case XORPDrm:
19572
0
  case XORPDrr:
19573
0
    return true;
19574
0
  }
19575
0
  return false;
19576
0
}
19577
19578
0
bool isVPSCATTERQQ(unsigned Opcode) {
19579
0
  switch (Opcode) {
19580
0
  case VPSCATTERQQZ128mr:
19581
0
  case VPSCATTERQQZ256mr:
19582
0
  case VPSCATTERQQZmr:
19583
0
    return true;
19584
0
  }
19585
0
  return false;
19586
0
}
19587
19588
0
bool isVCVTW2PH(unsigned Opcode) {
19589
0
  switch (Opcode) {
19590
0
  case VCVTW2PHZ128rm:
19591
0
  case VCVTW2PHZ128rmb:
19592
0
  case VCVTW2PHZ128rmbk:
19593
0
  case VCVTW2PHZ128rmbkz:
19594
0
  case VCVTW2PHZ128rmk:
19595
0
  case VCVTW2PHZ128rmkz:
19596
0
  case VCVTW2PHZ128rr:
19597
0
  case VCVTW2PHZ128rrk:
19598
0
  case VCVTW2PHZ128rrkz:
19599
0
  case VCVTW2PHZ256rm:
19600
0
  case VCVTW2PHZ256rmb:
19601
0
  case VCVTW2PHZ256rmbk:
19602
0
  case VCVTW2PHZ256rmbkz:
19603
0
  case VCVTW2PHZ256rmk:
19604
0
  case VCVTW2PHZ256rmkz:
19605
0
  case VCVTW2PHZ256rr:
19606
0
  case VCVTW2PHZ256rrk:
19607
0
  case VCVTW2PHZ256rrkz:
19608
0
  case VCVTW2PHZrm:
19609
0
  case VCVTW2PHZrmb:
19610
0
  case VCVTW2PHZrmbk:
19611
0
  case VCVTW2PHZrmbkz:
19612
0
  case VCVTW2PHZrmk:
19613
0
  case VCVTW2PHZrmkz:
19614
0
  case VCVTW2PHZrr:
19615
0
  case VCVTW2PHZrrb:
19616
0
  case VCVTW2PHZrrbk:
19617
0
  case VCVTW2PHZrrbkz:
19618
0
  case VCVTW2PHZrrk:
19619
0
  case VCVTW2PHZrrkz:
19620
0
    return true;
19621
0
  }
19622
0
  return false;
19623
0
}
19624
19625
0
bool isVFMADDCPH(unsigned Opcode) {
19626
0
  switch (Opcode) {
19627
0
  case VFMADDCPHZ128m:
19628
0
  case VFMADDCPHZ128mb:
19629
0
  case VFMADDCPHZ128mbk:
19630
0
  case VFMADDCPHZ128mbkz:
19631
0
  case VFMADDCPHZ128mk:
19632
0
  case VFMADDCPHZ128mkz:
19633
0
  case VFMADDCPHZ128r:
19634
0
  case VFMADDCPHZ128rk:
19635
0
  case VFMADDCPHZ128rkz:
19636
0
  case VFMADDCPHZ256m:
19637
0
  case VFMADDCPHZ256mb:
19638
0
  case VFMADDCPHZ256mbk:
19639
0
  case VFMADDCPHZ256mbkz:
19640
0
  case VFMADDCPHZ256mk:
19641
0
  case VFMADDCPHZ256mkz:
19642
0
  case VFMADDCPHZ256r:
19643
0
  case VFMADDCPHZ256rk:
19644
0
  case VFMADDCPHZ256rkz:
19645
0
  case VFMADDCPHZm:
19646
0
  case VFMADDCPHZmb:
19647
0
  case VFMADDCPHZmbk:
19648
0
  case VFMADDCPHZmbkz:
19649
0
  case VFMADDCPHZmk:
19650
0
  case VFMADDCPHZmkz:
19651
0
  case VFMADDCPHZr:
19652
0
  case VFMADDCPHZrb:
19653
0
  case VFMADDCPHZrbk:
19654
0
  case VFMADDCPHZrbkz:
19655
0
  case VFMADDCPHZrk:
19656
0
  case VFMADDCPHZrkz:
19657
0
    return true;
19658
0
  }
19659
0
  return false;
19660
0
}
19661
19662
0
bool isVSUBPD(unsigned Opcode) {
19663
0
  switch (Opcode) {
19664
0
  case VSUBPDYrm:
19665
0
  case VSUBPDYrr:
19666
0
  case VSUBPDZ128rm:
19667
0
  case VSUBPDZ128rmb:
19668
0
  case VSUBPDZ128rmbk:
19669
0
  case VSUBPDZ128rmbkz:
19670
0
  case VSUBPDZ128rmk:
19671
0
  case VSUBPDZ128rmkz:
19672
0
  case VSUBPDZ128rr:
19673
0
  case VSUBPDZ128rrk:
19674
0
  case VSUBPDZ128rrkz:
19675
0
  case VSUBPDZ256rm:
19676
0
  case VSUBPDZ256rmb:
19677
0
  case VSUBPDZ256rmbk:
19678
0
  case VSUBPDZ256rmbkz:
19679
0
  case VSUBPDZ256rmk:
19680
0
  case VSUBPDZ256rmkz:
19681
0
  case VSUBPDZ256rr:
19682
0
  case VSUBPDZ256rrk:
19683
0
  case VSUBPDZ256rrkz:
19684
0
  case VSUBPDZrm:
19685
0
  case VSUBPDZrmb:
19686
0
  case VSUBPDZrmbk:
19687
0
  case VSUBPDZrmbkz:
19688
0
  case VSUBPDZrmk:
19689
0
  case VSUBPDZrmkz:
19690
0
  case VSUBPDZrr:
19691
0
  case VSUBPDZrrb:
19692
0
  case VSUBPDZrrbk:
19693
0
  case VSUBPDZrrbkz:
19694
0
  case VSUBPDZrrk:
19695
0
  case VSUBPDZrrkz:
19696
0
  case VSUBPDrm:
19697
0
  case VSUBPDrr:
19698
0
    return true;
19699
0
  }
19700
0
  return false;
19701
0
}
19702
19703
0
bool isVPACKUSDW(unsigned Opcode) {
19704
0
  switch (Opcode) {
19705
0
  case VPACKUSDWYrm:
19706
0
  case VPACKUSDWYrr:
19707
0
  case VPACKUSDWZ128rm:
19708
0
  case VPACKUSDWZ128rmb:
19709
0
  case VPACKUSDWZ128rmbk:
19710
0
  case VPACKUSDWZ128rmbkz:
19711
0
  case VPACKUSDWZ128rmk:
19712
0
  case VPACKUSDWZ128rmkz:
19713
0
  case VPACKUSDWZ128rr:
19714
0
  case VPACKUSDWZ128rrk:
19715
0
  case VPACKUSDWZ128rrkz:
19716
0
  case VPACKUSDWZ256rm:
19717
0
  case VPACKUSDWZ256rmb:
19718
0
  case VPACKUSDWZ256rmbk:
19719
0
  case VPACKUSDWZ256rmbkz:
19720
0
  case VPACKUSDWZ256rmk:
19721
0
  case VPACKUSDWZ256rmkz:
19722
0
  case VPACKUSDWZ256rr:
19723
0
  case VPACKUSDWZ256rrk:
19724
0
  case VPACKUSDWZ256rrkz:
19725
0
  case VPACKUSDWZrm:
19726
0
  case VPACKUSDWZrmb:
19727
0
  case VPACKUSDWZrmbk:
19728
0
  case VPACKUSDWZrmbkz:
19729
0
  case VPACKUSDWZrmk:
19730
0
  case VPACKUSDWZrmkz:
19731
0
  case VPACKUSDWZrr:
19732
0
  case VPACKUSDWZrrk:
19733
0
  case VPACKUSDWZrrkz:
19734
0
  case VPACKUSDWrm:
19735
0
  case VPACKUSDWrr:
19736
0
    return true;
19737
0
  }
19738
0
  return false;
19739
0
}
19740
19741
0
bool isVSCALEFSS(unsigned Opcode) {
19742
0
  switch (Opcode) {
19743
0
  case VSCALEFSSZrm:
19744
0
  case VSCALEFSSZrmk:
19745
0
  case VSCALEFSSZrmkz:
19746
0
  case VSCALEFSSZrr:
19747
0
  case VSCALEFSSZrrb_Int:
19748
0
  case VSCALEFSSZrrb_Intk:
19749
0
  case VSCALEFSSZrrb_Intkz:
19750
0
  case VSCALEFSSZrrk:
19751
0
  case VSCALEFSSZrrkz:
19752
0
    return true;
19753
0
  }
19754
0
  return false;
19755
0
}
19756
19757
0
bool isAESIMC(unsigned Opcode) {
19758
0
  switch (Opcode) {
19759
0
  case AESIMCrm:
19760
0
  case AESIMCrr:
19761
0
    return true;
19762
0
  }
19763
0
  return false;
19764
0
}
19765
19766
0
bool isVRCP28PS(unsigned Opcode) {
19767
0
  switch (Opcode) {
19768
0
  case VRCP28PSZm:
19769
0
  case VRCP28PSZmb:
19770
0
  case VRCP28PSZmbk:
19771
0
  case VRCP28PSZmbkz:
19772
0
  case VRCP28PSZmk:
19773
0
  case VRCP28PSZmkz:
19774
0
  case VRCP28PSZr:
19775
0
  case VRCP28PSZrb:
19776
0
  case VRCP28PSZrbk:
19777
0
  case VRCP28PSZrbkz:
19778
0
  case VRCP28PSZrk:
19779
0
  case VRCP28PSZrkz:
19780
0
    return true;
19781
0
  }
19782
0
  return false;
19783
0
}
19784
19785
0
bool isAAND(unsigned Opcode) {
19786
0
  switch (Opcode) {
19787
0
  case AAND32mr:
19788
0
  case AAND64mr:
19789
0
    return true;
19790
0
  }
19791
0
  return false;
19792
0
}
19793
19794
0
bool isDAA(unsigned Opcode) {
19795
0
  return Opcode == DAA;
19796
0
}
19797
19798
0
bool isVCVTPD2UDQ(unsigned Opcode) {
19799
0
  switch (Opcode) {
19800
0
  case VCVTPD2UDQZ128rm:
19801
0
  case VCVTPD2UDQZ128rmb:
19802
0
  case VCVTPD2UDQZ128rmbk:
19803
0
  case VCVTPD2UDQZ128rmbkz:
19804
0
  case VCVTPD2UDQZ128rmk:
19805
0
  case VCVTPD2UDQZ128rmkz:
19806
0
  case VCVTPD2UDQZ128rr:
19807
0
  case VCVTPD2UDQZ128rrk:
19808
0
  case VCVTPD2UDQZ128rrkz:
19809
0
  case VCVTPD2UDQZ256rm:
19810
0
  case VCVTPD2UDQZ256rmb:
19811
0
  case VCVTPD2UDQZ256rmbk:
19812
0
  case VCVTPD2UDQZ256rmbkz:
19813
0
  case VCVTPD2UDQZ256rmk:
19814
0
  case VCVTPD2UDQZ256rmkz:
19815
0
  case VCVTPD2UDQZ256rr:
19816
0
  case VCVTPD2UDQZ256rrk:
19817
0
  case VCVTPD2UDQZ256rrkz:
19818
0
  case VCVTPD2UDQZrm:
19819
0
  case VCVTPD2UDQZrmb:
19820
0
  case VCVTPD2UDQZrmbk:
19821
0
  case VCVTPD2UDQZrmbkz:
19822
0
  case VCVTPD2UDQZrmk:
19823
0
  case VCVTPD2UDQZrmkz:
19824
0
  case VCVTPD2UDQZrr:
19825
0
  case VCVTPD2UDQZrrb:
19826
0
  case VCVTPD2UDQZrrbk:
19827
0
  case VCVTPD2UDQZrrbkz:
19828
0
  case VCVTPD2UDQZrrk:
19829
0
  case VCVTPD2UDQZrrkz:
19830
0
    return true;
19831
0
  }
19832
0
  return false;
19833
0
}
19834
19835
0
bool isKTESTW(unsigned Opcode) {
19836
0
  return Opcode == KTESTWrr;
19837
0
}
19838
19839
0
bool isVPADDQ(unsigned Opcode) {
19840
0
  switch (Opcode) {
19841
0
  case VPADDQYrm:
19842
0
  case VPADDQYrr:
19843
0
  case VPADDQZ128rm:
19844
0
  case VPADDQZ128rmb:
19845
0
  case VPADDQZ128rmbk:
19846
0
  case VPADDQZ128rmbkz:
19847
0
  case VPADDQZ128rmk:
19848
0
  case VPADDQZ128rmkz:
19849
0
  case VPADDQZ128rr:
19850
0
  case VPADDQZ128rrk:
19851
0
  case VPADDQZ128rrkz:
19852
0
  case VPADDQZ256rm:
19853
0
  case VPADDQZ256rmb:
19854
0
  case VPADDQZ256rmbk:
19855
0
  case VPADDQZ256rmbkz:
19856
0
  case VPADDQZ256rmk:
19857
0
  case VPADDQZ256rmkz:
19858
0
  case VPADDQZ256rr:
19859
0
  case VPADDQZ256rrk:
19860
0
  case VPADDQZ256rrkz:
19861
0
  case VPADDQZrm:
19862
0
  case VPADDQZrmb:
19863
0
  case VPADDQZrmbk:
19864
0
  case VPADDQZrmbkz:
19865
0
  case VPADDQZrmk:
19866
0
  case VPADDQZrmkz:
19867
0
  case VPADDQZrr:
19868
0
  case VPADDQZrrk:
19869
0
  case VPADDQZrrkz:
19870
0
  case VPADDQrm:
19871
0
  case VPADDQrr:
19872
0
    return true;
19873
0
  }
19874
0
  return false;
19875
0
}
19876
19877
0
bool isPALIGNR(unsigned Opcode) {
19878
0
  switch (Opcode) {
19879
0
  case MMX_PALIGNRrmi:
19880
0
  case MMX_PALIGNRrri:
19881
0
  case PALIGNRrmi:
19882
0
  case PALIGNRrri:
19883
0
    return true;
19884
0
  }
19885
0
  return false;
19886
0
}
19887
19888
0
bool isPMAXUW(unsigned Opcode) {
19889
0
  switch (Opcode) {
19890
0
  case PMAXUWrm:
19891
0
  case PMAXUWrr:
19892
0
    return true;
19893
0
  }
19894
0
  return false;
19895
0
}
19896
19897
0
bool isVFMADDSD(unsigned Opcode) {
19898
0
  switch (Opcode) {
19899
0
  case VFMADDSD4mr:
19900
0
  case VFMADDSD4rm:
19901
0
  case VFMADDSD4rr:
19902
0
  case VFMADDSD4rr_REV:
19903
0
    return true;
19904
0
  }
19905
0
  return false;
19906
0
}
19907
19908
0
bool isPFMAX(unsigned Opcode) {
19909
0
  switch (Opcode) {
19910
0
  case PFMAXrm:
19911
0
  case PFMAXrr:
19912
0
    return true;
19913
0
  }
19914
0
  return false;
19915
0
}
19916
19917
0
bool isVPOR(unsigned Opcode) {
19918
0
  switch (Opcode) {
19919
0
  case VPORYrm:
19920
0
  case VPORYrr:
19921
0
  case VPORrm:
19922
0
  case VPORrr:
19923
0
    return true;
19924
0
  }
19925
0
  return false;
19926
0
}
19927
19928
0
bool isVPSUBB(unsigned Opcode) {
19929
0
  switch (Opcode) {
19930
0
  case VPSUBBYrm:
19931
0
  case VPSUBBYrr:
19932
0
  case VPSUBBZ128rm:
19933
0
  case VPSUBBZ128rmk:
19934
0
  case VPSUBBZ128rmkz:
19935
0
  case VPSUBBZ128rr:
19936
0
  case VPSUBBZ128rrk:
19937
0
  case VPSUBBZ128rrkz:
19938
0
  case VPSUBBZ256rm:
19939
0
  case VPSUBBZ256rmk:
19940
0
  case VPSUBBZ256rmkz:
19941
0
  case VPSUBBZ256rr:
19942
0
  case VPSUBBZ256rrk:
19943
0
  case VPSUBBZ256rrkz:
19944
0
  case VPSUBBZrm:
19945
0
  case VPSUBBZrmk:
19946
0
  case VPSUBBZrmkz:
19947
0
  case VPSUBBZrr:
19948
0
  case VPSUBBZrrk:
19949
0
  case VPSUBBZrrkz:
19950
0
  case VPSUBBrm:
19951
0
  case VPSUBBrr:
19952
0
    return true;
19953
0
  }
19954
0
  return false;
19955
0
}
19956
19957
0
bool isVPAVGB(unsigned Opcode) {
19958
0
  switch (Opcode) {
19959
0
  case VPAVGBYrm:
19960
0
  case VPAVGBYrr:
19961
0
  case VPAVGBZ128rm:
19962
0
  case VPAVGBZ128rmk:
19963
0
  case VPAVGBZ128rmkz:
19964
0
  case VPAVGBZ128rr:
19965
0
  case VPAVGBZ128rrk:
19966
0
  case VPAVGBZ128rrkz:
19967
0
  case VPAVGBZ256rm:
19968
0
  case VPAVGBZ256rmk:
19969
0
  case VPAVGBZ256rmkz:
19970
0
  case VPAVGBZ256rr:
19971
0
  case VPAVGBZ256rrk:
19972
0
  case VPAVGBZ256rrkz:
19973
0
  case VPAVGBZrm:
19974
0
  case VPAVGBZrmk:
19975
0
  case VPAVGBZrmkz:
19976
0
  case VPAVGBZrr:
19977
0
  case VPAVGBZrrk:
19978
0
  case VPAVGBZrrkz:
19979
0
  case VPAVGBrm:
19980
0
  case VPAVGBrr:
19981
0
    return true;
19982
0
  }
19983
0
  return false;
19984
0
}
19985
19986
0
bool isINSB(unsigned Opcode) {
19987
0
  return Opcode == INSB;
19988
0
}
19989
19990
0
bool isFYL2X(unsigned Opcode) {
19991
0
  return Opcode == FYL2X;
19992
0
}
19993
19994
0
bool isVFNMSUB132PD(unsigned Opcode) {
19995
0
  switch (Opcode) {
19996
0
  case VFNMSUB132PDYm:
19997
0
  case VFNMSUB132PDYr:
19998
0
  case VFNMSUB132PDZ128m:
19999
0
  case VFNMSUB132PDZ128mb:
20000
0
  case VFNMSUB132PDZ128mbk:
20001
0
  case VFNMSUB132PDZ128mbkz:
20002
0
  case VFNMSUB132PDZ128mk:
20003
0
  case VFNMSUB132PDZ128mkz:
20004
0
  case VFNMSUB132PDZ128r:
20005
0
  case VFNMSUB132PDZ128rk:
20006
0
  case VFNMSUB132PDZ128rkz:
20007
0
  case VFNMSUB132PDZ256m:
20008
0
  case VFNMSUB132PDZ256mb:
20009
0
  case VFNMSUB132PDZ256mbk:
20010
0
  case VFNMSUB132PDZ256mbkz:
20011
0
  case VFNMSUB132PDZ256mk:
20012
0
  case VFNMSUB132PDZ256mkz:
20013
0
  case VFNMSUB132PDZ256r:
20014
0
  case VFNMSUB132PDZ256rk:
20015
0
  case VFNMSUB132PDZ256rkz:
20016
0
  case VFNMSUB132PDZm:
20017
0
  case VFNMSUB132PDZmb:
20018
0
  case VFNMSUB132PDZmbk:
20019
0
  case VFNMSUB132PDZmbkz:
20020
0
  case VFNMSUB132PDZmk:
20021
0
  case VFNMSUB132PDZmkz:
20022
0
  case VFNMSUB132PDZr:
20023
0
  case VFNMSUB132PDZrb:
20024
0
  case VFNMSUB132PDZrbk:
20025
0
  case VFNMSUB132PDZrbkz:
20026
0
  case VFNMSUB132PDZrk:
20027
0
  case VFNMSUB132PDZrkz:
20028
0
  case VFNMSUB132PDm:
20029
0
  case VFNMSUB132PDr:
20030
0
    return true;
20031
0
  }
20032
0
  return false;
20033
0
}
20034
20035
0
bool isVFNMSUBPS(unsigned Opcode) {
20036
0
  switch (Opcode) {
20037
0
  case VFNMSUBPS4Ymr:
20038
0
  case VFNMSUBPS4Yrm:
20039
0
  case VFNMSUBPS4Yrr:
20040
0
  case VFNMSUBPS4Yrr_REV:
20041
0
  case VFNMSUBPS4mr:
20042
0
  case VFNMSUBPS4rm:
20043
0
  case VFNMSUBPS4rr:
20044
0
  case VFNMSUBPS4rr_REV:
20045
0
    return true;
20046
0
  }
20047
0
  return false;
20048
0
}
20049
20050
0
bool isVFMADD231PS(unsigned Opcode) {
20051
0
  switch (Opcode) {
20052
0
  case VFMADD231PSYm:
20053
0
  case VFMADD231PSYr:
20054
0
  case VFMADD231PSZ128m:
20055
0
  case VFMADD231PSZ128mb:
20056
0
  case VFMADD231PSZ128mbk:
20057
0
  case VFMADD231PSZ128mbkz:
20058
0
  case VFMADD231PSZ128mk:
20059
0
  case VFMADD231PSZ128mkz:
20060
0
  case VFMADD231PSZ128r:
20061
0
  case VFMADD231PSZ128rk:
20062
0
  case VFMADD231PSZ128rkz:
20063
0
  case VFMADD231PSZ256m:
20064
0
  case VFMADD231PSZ256mb:
20065
0
  case VFMADD231PSZ256mbk:
20066
0
  case VFMADD231PSZ256mbkz:
20067
0
  case VFMADD231PSZ256mk:
20068
0
  case VFMADD231PSZ256mkz:
20069
0
  case VFMADD231PSZ256r:
20070
0
  case VFMADD231PSZ256rk:
20071
0
  case VFMADD231PSZ256rkz:
20072
0
  case VFMADD231PSZm:
20073
0
  case VFMADD231PSZmb:
20074
0
  case VFMADD231PSZmbk:
20075
0
  case VFMADD231PSZmbkz:
20076
0
  case VFMADD231PSZmk:
20077
0
  case VFMADD231PSZmkz:
20078
0
  case VFMADD231PSZr:
20079
0
  case VFMADD231PSZrb:
20080
0
  case VFMADD231PSZrbk:
20081
0
  case VFMADD231PSZrbkz:
20082
0
  case VFMADD231PSZrk:
20083
0
  case VFMADD231PSZrkz:
20084
0
  case VFMADD231PSm:
20085
0
  case VFMADD231PSr:
20086
0
    return true;
20087
0
  }
20088
0
  return false;
20089
0
}
20090
20091
0
bool isVCVTTSS2SI(unsigned Opcode) {
20092
0
  switch (Opcode) {
20093
0
  case VCVTTSS2SI64Zrm_Int:
20094
0
  case VCVTTSS2SI64Zrr_Int:
20095
0
  case VCVTTSS2SI64Zrrb_Int:
20096
0
  case VCVTTSS2SI64rm_Int:
20097
0
  case VCVTTSS2SI64rr_Int:
20098
0
  case VCVTTSS2SIZrm_Int:
20099
0
  case VCVTTSS2SIZrr_Int:
20100
0
  case VCVTTSS2SIZrrb_Int:
20101
0
  case VCVTTSS2SIrm_Int:
20102
0
  case VCVTTSS2SIrr_Int:
20103
0
    return true;
20104
0
  }
20105
0
  return false;
20106
0
}
20107
20108
0
bool isTCMMRLFP16PS(unsigned Opcode) {
20109
0
  return Opcode == TCMMRLFP16PS;
20110
0
}
20111
20112
0
bool isFCOMPP(unsigned Opcode) {
20113
0
  return Opcode == FCOMPP;
20114
0
}
20115
20116
0
bool isMOVD(unsigned Opcode) {
20117
0
  switch (Opcode) {
20118
0
  case MMX_MOVD64grr:
20119
0
  case MMX_MOVD64mr:
20120
0
  case MMX_MOVD64rm:
20121
0
  case MMX_MOVD64rr:
20122
0
  case MOVDI2PDIrm:
20123
0
  case MOVDI2PDIrr:
20124
0
  case MOVPDI2DImr:
20125
0
  case MOVPDI2DIrr:
20126
0
    return true;
20127
0
  }
20128
0
  return false;
20129
0
}
20130
20131
0
bool isMOVBE(unsigned Opcode) {
20132
0
  switch (Opcode) {
20133
0
  case MOVBE16mr:
20134
0
  case MOVBE16rm:
20135
0
  case MOVBE32mr:
20136
0
  case MOVBE32rm:
20137
0
  case MOVBE64mr:
20138
0
  case MOVBE64rm:
20139
0
    return true;
20140
0
  }
20141
0
  return false;
20142
0
}
20143
20144
0
bool isVP2INTERSECTD(unsigned Opcode) {
20145
0
  switch (Opcode) {
20146
0
  case VP2INTERSECTDZ128rm:
20147
0
  case VP2INTERSECTDZ128rmb:
20148
0
  case VP2INTERSECTDZ128rr:
20149
0
  case VP2INTERSECTDZ256rm:
20150
0
  case VP2INTERSECTDZ256rmb:
20151
0
  case VP2INTERSECTDZ256rr:
20152
0
  case VP2INTERSECTDZrm:
20153
0
  case VP2INTERSECTDZrmb:
20154
0
  case VP2INTERSECTDZrr:
20155
0
    return true;
20156
0
  }
20157
0
  return false;
20158
0
}
20159
20160
0
bool isVPMULLQ(unsigned Opcode) {
20161
0
  switch (Opcode) {
20162
0
  case VPMULLQZ128rm:
20163
0
  case VPMULLQZ128rmb:
20164
0
  case VPMULLQZ128rmbk:
20165
0
  case VPMULLQZ128rmbkz:
20166
0
  case VPMULLQZ128rmk:
20167
0
  case VPMULLQZ128rmkz:
20168
0
  case VPMULLQZ128rr:
20169
0
  case VPMULLQZ128rrk:
20170
0
  case VPMULLQZ128rrkz:
20171
0
  case VPMULLQZ256rm:
20172
0
  case VPMULLQZ256rmb:
20173
0
  case VPMULLQZ256rmbk:
20174
0
  case VPMULLQZ256rmbkz:
20175
0
  case VPMULLQZ256rmk:
20176
0
  case VPMULLQZ256rmkz:
20177
0
  case VPMULLQZ256rr:
20178
0
  case VPMULLQZ256rrk:
20179
0
  case VPMULLQZ256rrkz:
20180
0
  case VPMULLQZrm:
20181
0
  case VPMULLQZrmb:
20182
0
  case VPMULLQZrmbk:
20183
0
  case VPMULLQZrmbkz:
20184
0
  case VPMULLQZrmk:
20185
0
  case VPMULLQZrmkz:
20186
0
  case VPMULLQZrr:
20187
0
  case VPMULLQZrrk:
20188
0
  case VPMULLQZrrkz:
20189
0
    return true;
20190
0
  }
20191
0
  return false;
20192
0
}
20193
20194
0
bool isVSCALEFPS(unsigned Opcode) {
20195
0
  switch (Opcode) {
20196
0
  case VSCALEFPSZ128rm:
20197
0
  case VSCALEFPSZ128rmb:
20198
0
  case VSCALEFPSZ128rmbk:
20199
0
  case VSCALEFPSZ128rmbkz:
20200
0
  case VSCALEFPSZ128rmk:
20201
0
  case VSCALEFPSZ128rmkz:
20202
0
  case VSCALEFPSZ128rr:
20203
0
  case VSCALEFPSZ128rrk:
20204
0
  case VSCALEFPSZ128rrkz:
20205
0
  case VSCALEFPSZ256rm:
20206
0
  case VSCALEFPSZ256rmb:
20207
0
  case VSCALEFPSZ256rmbk:
20208
0
  case VSCALEFPSZ256rmbkz:
20209
0
  case VSCALEFPSZ256rmk:
20210
0
  case VSCALEFPSZ256rmkz:
20211
0
  case VSCALEFPSZ256rr:
20212
0
  case VSCALEFPSZ256rrk:
20213
0
  case VSCALEFPSZ256rrkz:
20214
0
  case VSCALEFPSZrm:
20215
0
  case VSCALEFPSZrmb:
20216
0
  case VSCALEFPSZrmbk:
20217
0
  case VSCALEFPSZrmbkz:
20218
0
  case VSCALEFPSZrmk:
20219
0
  case VSCALEFPSZrmkz:
20220
0
  case VSCALEFPSZrr:
20221
0
  case VSCALEFPSZrrb:
20222
0
  case VSCALEFPSZrrbk:
20223
0
  case VSCALEFPSZrrbkz:
20224
0
  case VSCALEFPSZrrk:
20225
0
  case VSCALEFPSZrrkz:
20226
0
    return true;
20227
0
  }
20228
0
  return false;
20229
0
}
20230
20231
0
bool isVPMACSDQH(unsigned Opcode) {
20232
0
  switch (Opcode) {
20233
0
  case VPMACSDQHrm:
20234
0
  case VPMACSDQHrr:
20235
0
    return true;
20236
0
  }
20237
0
  return false;
20238
0
}
20239
20240
0
bool isVPTESTNMD(unsigned Opcode) {
20241
0
  switch (Opcode) {
20242
0
  case VPTESTNMDZ128rm:
20243
0
  case VPTESTNMDZ128rmb:
20244
0
  case VPTESTNMDZ128rmbk:
20245
0
  case VPTESTNMDZ128rmk:
20246
0
  case VPTESTNMDZ128rr:
20247
0
  case VPTESTNMDZ128rrk:
20248
0
  case VPTESTNMDZ256rm:
20249
0
  case VPTESTNMDZ256rmb:
20250
0
  case VPTESTNMDZ256rmbk:
20251
0
  case VPTESTNMDZ256rmk:
20252
0
  case VPTESTNMDZ256rr:
20253
0
  case VPTESTNMDZ256rrk:
20254
0
  case VPTESTNMDZrm:
20255
0
  case VPTESTNMDZrmb:
20256
0
  case VPTESTNMDZrmbk:
20257
0
  case VPTESTNMDZrmk:
20258
0
  case VPTESTNMDZrr:
20259
0
  case VPTESTNMDZrrk:
20260
0
    return true;
20261
0
  }
20262
0
  return false;
20263
0
}
20264
20265
0
bool isFCOMP(unsigned Opcode) {
20266
0
  switch (Opcode) {
20267
0
  case COMP_FST0r:
20268
0
  case FCOMP32m:
20269
0
  case FCOMP64m:
20270
0
    return true;
20271
0
  }
20272
0
  return false;
20273
0
}
20274
20275
0
bool isPREFETCHWT1(unsigned Opcode) {
20276
0
  return Opcode == PREFETCHWT1;
20277
0
}
20278
20279
0
bool isVCMPSD(unsigned Opcode) {
20280
0
  switch (Opcode) {
20281
0
  case VCMPSDZrm_Int:
20282
0
  case VCMPSDZrm_Intk:
20283
0
  case VCMPSDZrr_Int:
20284
0
  case VCMPSDZrr_Intk:
20285
0
  case VCMPSDZrrb_Int:
20286
0
  case VCMPSDZrrb_Intk:
20287
0
  case VCMPSDrm_Int:
20288
0
  case VCMPSDrr_Int:
20289
0
    return true;
20290
0
  }
20291
0
  return false;
20292
0
}
20293
20294
0
bool isSGDTD(unsigned Opcode) {
20295
0
  return Opcode == SGDT32m;
20296
0
}
20297
20298
0
bool isWRUSSD(unsigned Opcode) {
20299
0
  switch (Opcode) {
20300
0
  case WRUSSD:
20301
0
  case WRUSSD_EVEX:
20302
0
    return true;
20303
0
  }
20304
0
  return false;
20305
0
}
20306
20307
0
bool isFSUBP(unsigned Opcode) {
20308
0
  return Opcode == SUB_FPrST0;
20309
0
}
20310
20311
0
bool isVUNPCKLPS(unsigned Opcode) {
20312
0
  switch (Opcode) {
20313
0
  case VUNPCKLPSYrm:
20314
0
  case VUNPCKLPSYrr:
20315
0
  case VUNPCKLPSZ128rm:
20316
0
  case VUNPCKLPSZ128rmb:
20317
0
  case VUNPCKLPSZ128rmbk:
20318
0
  case VUNPCKLPSZ128rmbkz:
20319
0
  case VUNPCKLPSZ128rmk:
20320
0
  case VUNPCKLPSZ128rmkz:
20321
0
  case VUNPCKLPSZ128rr:
20322
0
  case VUNPCKLPSZ128rrk:
20323
0
  case VUNPCKLPSZ128rrkz:
20324
0
  case VUNPCKLPSZ256rm:
20325
0
  case VUNPCKLPSZ256rmb:
20326
0
  case VUNPCKLPSZ256rmbk:
20327
0
  case VUNPCKLPSZ256rmbkz:
20328
0
  case VUNPCKLPSZ256rmk:
20329
0
  case VUNPCKLPSZ256rmkz:
20330
0
  case VUNPCKLPSZ256rr:
20331
0
  case VUNPCKLPSZ256rrk:
20332
0
  case VUNPCKLPSZ256rrkz:
20333
0
  case VUNPCKLPSZrm:
20334
0
  case VUNPCKLPSZrmb:
20335
0
  case VUNPCKLPSZrmbk:
20336
0
  case VUNPCKLPSZrmbkz:
20337
0
  case VUNPCKLPSZrmk:
20338
0
  case VUNPCKLPSZrmkz:
20339
0
  case VUNPCKLPSZrr:
20340
0
  case VUNPCKLPSZrrk:
20341
0
  case VUNPCKLPSZrrkz:
20342
0
  case VUNPCKLPSrm:
20343
0
  case VUNPCKLPSrr:
20344
0
    return true;
20345
0
  }
20346
0
  return false;
20347
0
}
20348
20349
0
bool isVFNMSUB213SS(unsigned Opcode) {
20350
0
  switch (Opcode) {
20351
0
  case VFNMSUB213SSZm_Int:
20352
0
  case VFNMSUB213SSZm_Intk:
20353
0
  case VFNMSUB213SSZm_Intkz:
20354
0
  case VFNMSUB213SSZr_Int:
20355
0
  case VFNMSUB213SSZr_Intk:
20356
0
  case VFNMSUB213SSZr_Intkz:
20357
0
  case VFNMSUB213SSZrb_Int:
20358
0
  case VFNMSUB213SSZrb_Intk:
20359
0
  case VFNMSUB213SSZrb_Intkz:
20360
0
  case VFNMSUB213SSm_Int:
20361
0
  case VFNMSUB213SSr_Int:
20362
0
    return true;
20363
0
  }
20364
0
  return false;
20365
0
}
20366
20367
0
bool isROUNDPD(unsigned Opcode) {
20368
0
  switch (Opcode) {
20369
0
  case ROUNDPDm:
20370
0
  case ROUNDPDr:
20371
0
    return true;
20372
0
  }
20373
0
  return false;
20374
0
}
20375
20376
0
bool isVPMAXSW(unsigned Opcode) {
20377
0
  switch (Opcode) {
20378
0
  case VPMAXSWYrm:
20379
0
  case VPMAXSWYrr:
20380
0
  case VPMAXSWZ128rm:
20381
0
  case VPMAXSWZ128rmk:
20382
0
  case VPMAXSWZ128rmkz:
20383
0
  case VPMAXSWZ128rr:
20384
0
  case VPMAXSWZ128rrk:
20385
0
  case VPMAXSWZ128rrkz:
20386
0
  case VPMAXSWZ256rm:
20387
0
  case VPMAXSWZ256rmk:
20388
0
  case VPMAXSWZ256rmkz:
20389
0
  case VPMAXSWZ256rr:
20390
0
  case VPMAXSWZ256rrk:
20391
0
  case VPMAXSWZ256rrkz:
20392
0
  case VPMAXSWZrm:
20393
0
  case VPMAXSWZrmk:
20394
0
  case VPMAXSWZrmkz:
20395
0
  case VPMAXSWZrr:
20396
0
  case VPMAXSWZrrk:
20397
0
  case VPMAXSWZrrkz:
20398
0
  case VPMAXSWrm:
20399
0
  case VPMAXSWrr:
20400
0
    return true;
20401
0
  }
20402
0
  return false;
20403
0
}
20404
20405
0
bool isVCVTTPH2DQ(unsigned Opcode) {
20406
0
  switch (Opcode) {
20407
0
  case VCVTTPH2DQZ128rm:
20408
0
  case VCVTTPH2DQZ128rmb:
20409
0
  case VCVTTPH2DQZ128rmbk:
20410
0
  case VCVTTPH2DQZ128rmbkz:
20411
0
  case VCVTTPH2DQZ128rmk:
20412
0
  case VCVTTPH2DQZ128rmkz:
20413
0
  case VCVTTPH2DQZ128rr:
20414
0
  case VCVTTPH2DQZ128rrk:
20415
0
  case VCVTTPH2DQZ128rrkz:
20416
0
  case VCVTTPH2DQZ256rm:
20417
0
  case VCVTTPH2DQZ256rmb:
20418
0
  case VCVTTPH2DQZ256rmbk:
20419
0
  case VCVTTPH2DQZ256rmbkz:
20420
0
  case VCVTTPH2DQZ256rmk:
20421
0
  case VCVTTPH2DQZ256rmkz:
20422
0
  case VCVTTPH2DQZ256rr:
20423
0
  case VCVTTPH2DQZ256rrk:
20424
0
  case VCVTTPH2DQZ256rrkz:
20425
0
  case VCVTTPH2DQZrm:
20426
0
  case VCVTTPH2DQZrmb:
20427
0
  case VCVTTPH2DQZrmbk:
20428
0
  case VCVTTPH2DQZrmbkz:
20429
0
  case VCVTTPH2DQZrmk:
20430
0
  case VCVTTPH2DQZrmkz:
20431
0
  case VCVTTPH2DQZrr:
20432
0
  case VCVTTPH2DQZrrb:
20433
0
  case VCVTTPH2DQZrrbk:
20434
0
  case VCVTTPH2DQZrrbkz:
20435
0
  case VCVTTPH2DQZrrk:
20436
0
  case VCVTTPH2DQZrrkz:
20437
0
    return true;
20438
0
  }
20439
0
  return false;
20440
0
}
20441
20442
0
bool isVPUNPCKLWD(unsigned Opcode) {
20443
0
  switch (Opcode) {
20444
0
  case VPUNPCKLWDYrm:
20445
0
  case VPUNPCKLWDYrr:
20446
0
  case VPUNPCKLWDZ128rm:
20447
0
  case VPUNPCKLWDZ128rmk:
20448
0
  case VPUNPCKLWDZ128rmkz:
20449
0
  case VPUNPCKLWDZ128rr:
20450
0
  case VPUNPCKLWDZ128rrk:
20451
0
  case VPUNPCKLWDZ128rrkz:
20452
0
  case VPUNPCKLWDZ256rm:
20453
0
  case VPUNPCKLWDZ256rmk:
20454
0
  case VPUNPCKLWDZ256rmkz:
20455
0
  case VPUNPCKLWDZ256rr:
20456
0
  case VPUNPCKLWDZ256rrk:
20457
0
  case VPUNPCKLWDZ256rrkz:
20458
0
  case VPUNPCKLWDZrm:
20459
0
  case VPUNPCKLWDZrmk:
20460
0
  case VPUNPCKLWDZrmkz:
20461
0
  case VPUNPCKLWDZrr:
20462
0
  case VPUNPCKLWDZrrk:
20463
0
  case VPUNPCKLWDZrrkz:
20464
0
  case VPUNPCKLWDrm:
20465
0
  case VPUNPCKLWDrr:
20466
0
    return true;
20467
0
  }
20468
0
  return false;
20469
0
}
20470
20471
0
bool isKSHIFTLD(unsigned Opcode) {
20472
0
  return Opcode == KSHIFTLDri;
20473
0
}
20474
20475
0
bool isVFMADD231SD(unsigned Opcode) {
20476
0
  switch (Opcode) {
20477
0
  case VFMADD231SDZm_Int:
20478
0
  case VFMADD231SDZm_Intk:
20479
0
  case VFMADD231SDZm_Intkz:
20480
0
  case VFMADD231SDZr_Int:
20481
0
  case VFMADD231SDZr_Intk:
20482
0
  case VFMADD231SDZr_Intkz:
20483
0
  case VFMADD231SDZrb_Int:
20484
0
  case VFMADD231SDZrb_Intk:
20485
0
  case VFMADD231SDZrb_Intkz:
20486
0
  case VFMADD231SDm_Int:
20487
0
  case VFMADD231SDr_Int:
20488
0
    return true;
20489
0
  }
20490
0
  return false;
20491
0
}
20492
20493
0
bool isADDPS(unsigned Opcode) {
20494
0
  switch (Opcode) {
20495
0
  case ADDPSrm:
20496
0
  case ADDPSrr:
20497
0
    return true;
20498
0
  }
20499
0
  return false;
20500
0
}
20501
20502
0
bool isVPSLLVD(unsigned Opcode) {
20503
0
  switch (Opcode) {
20504
0
  case VPSLLVDYrm:
20505
0
  case VPSLLVDYrr:
20506
0
  case VPSLLVDZ128rm:
20507
0
  case VPSLLVDZ128rmb:
20508
0
  case VPSLLVDZ128rmbk:
20509
0
  case VPSLLVDZ128rmbkz:
20510
0
  case VPSLLVDZ128rmk:
20511
0
  case VPSLLVDZ128rmkz:
20512
0
  case VPSLLVDZ128rr:
20513
0
  case VPSLLVDZ128rrk:
20514
0
  case VPSLLVDZ128rrkz:
20515
0
  case VPSLLVDZ256rm:
20516
0
  case VPSLLVDZ256rmb:
20517
0
  case VPSLLVDZ256rmbk:
20518
0
  case VPSLLVDZ256rmbkz:
20519
0
  case VPSLLVDZ256rmk:
20520
0
  case VPSLLVDZ256rmkz:
20521
0
  case VPSLLVDZ256rr:
20522
0
  case VPSLLVDZ256rrk:
20523
0
  case VPSLLVDZ256rrkz:
20524
0
  case VPSLLVDZrm:
20525
0
  case VPSLLVDZrmb:
20526
0
  case VPSLLVDZrmbk:
20527
0
  case VPSLLVDZrmbkz:
20528
0
  case VPSLLVDZrmk:
20529
0
  case VPSLLVDZrmkz:
20530
0
  case VPSLLVDZrr:
20531
0
  case VPSLLVDZrrk:
20532
0
  case VPSLLVDZrrkz:
20533
0
  case VPSLLVDrm:
20534
0
  case VPSLLVDrr:
20535
0
    return true;
20536
0
  }
20537
0
  return false;
20538
0
}
20539
20540
0
bool isVFNMADD132SH(unsigned Opcode) {
20541
0
  switch (Opcode) {
20542
0
  case VFNMADD132SHZm_Int:
20543
0
  case VFNMADD132SHZm_Intk:
20544
0
  case VFNMADD132SHZm_Intkz:
20545
0
  case VFNMADD132SHZr_Int:
20546
0
  case VFNMADD132SHZr_Intk:
20547
0
  case VFNMADD132SHZr_Intkz:
20548
0
  case VFNMADD132SHZrb_Int:
20549
0
  case VFNMADD132SHZrb_Intk:
20550
0
  case VFNMADD132SHZrb_Intkz:
20551
0
    return true;
20552
0
  }
20553
0
  return false;
20554
0
}
20555
20556
0
bool isVMOVNTPS(unsigned Opcode) {
20557
0
  switch (Opcode) {
20558
0
  case VMOVNTPSYmr:
20559
0
  case VMOVNTPSZ128mr:
20560
0
  case VMOVNTPSZ256mr:
20561
0
  case VMOVNTPSZmr:
20562
0
  case VMOVNTPSmr:
20563
0
    return true;
20564
0
  }
20565
0
  return false;
20566
0
}
20567
20568
0
bool isVCVTPD2DQ(unsigned Opcode) {
20569
0
  switch (Opcode) {
20570
0
  case VCVTPD2DQYrm:
20571
0
  case VCVTPD2DQYrr:
20572
0
  case VCVTPD2DQZ128rm:
20573
0
  case VCVTPD2DQZ128rmb:
20574
0
  case VCVTPD2DQZ128rmbk:
20575
0
  case VCVTPD2DQZ128rmbkz:
20576
0
  case VCVTPD2DQZ128rmk:
20577
0
  case VCVTPD2DQZ128rmkz:
20578
0
  case VCVTPD2DQZ128rr:
20579
0
  case VCVTPD2DQZ128rrk:
20580
0
  case VCVTPD2DQZ128rrkz:
20581
0
  case VCVTPD2DQZ256rm:
20582
0
  case VCVTPD2DQZ256rmb:
20583
0
  case VCVTPD2DQZ256rmbk:
20584
0
  case VCVTPD2DQZ256rmbkz:
20585
0
  case VCVTPD2DQZ256rmk:
20586
0
  case VCVTPD2DQZ256rmkz:
20587
0
  case VCVTPD2DQZ256rr:
20588
0
  case VCVTPD2DQZ256rrk:
20589
0
  case VCVTPD2DQZ256rrkz:
20590
0
  case VCVTPD2DQZrm:
20591
0
  case VCVTPD2DQZrmb:
20592
0
  case VCVTPD2DQZrmbk:
20593
0
  case VCVTPD2DQZrmbkz:
20594
0
  case VCVTPD2DQZrmk:
20595
0
  case VCVTPD2DQZrmkz:
20596
0
  case VCVTPD2DQZrr:
20597
0
  case VCVTPD2DQZrrb:
20598
0
  case VCVTPD2DQZrrbk:
20599
0
  case VCVTPD2DQZrrbkz:
20600
0
  case VCVTPD2DQZrrk:
20601
0
  case VCVTPD2DQZrrkz:
20602
0
  case VCVTPD2DQrm:
20603
0
  case VCVTPD2DQrr:
20604
0
    return true;
20605
0
  }
20606
0
  return false;
20607
0
}
20608
20609
0
bool isVPXOR(unsigned Opcode) {
20610
0
  switch (Opcode) {
20611
0
  case VPXORYrm:
20612
0
  case VPXORYrr:
20613
0
  case VPXORrm:
20614
0
  case VPXORrr:
20615
0
    return true;
20616
0
  }
20617
0
  return false;
20618
0
}
20619
20620
0
bool isSTMXCSR(unsigned Opcode) {
20621
0
  return Opcode == STMXCSR;
20622
0
}
20623
20624
0
bool isVRCP14SS(unsigned Opcode) {
20625
0
  switch (Opcode) {
20626
0
  case VRCP14SSZrm:
20627
0
  case VRCP14SSZrmk:
20628
0
  case VRCP14SSZrmkz:
20629
0
  case VRCP14SSZrr:
20630
0
  case VRCP14SSZrrk:
20631
0
  case VRCP14SSZrrkz:
20632
0
    return true;
20633
0
  }
20634
0
  return false;
20635
0
}
20636
20637
0
bool isUD2(unsigned Opcode) {
20638
0
  return Opcode == TRAP;
20639
0
}
20640
20641
0
bool isVPOPCNTW(unsigned Opcode) {
20642
0
  switch (Opcode) {
20643
0
  case VPOPCNTWZ128rm:
20644
0
  case VPOPCNTWZ128rmk:
20645
0
  case VPOPCNTWZ128rmkz:
20646
0
  case VPOPCNTWZ128rr:
20647
0
  case VPOPCNTWZ128rrk:
20648
0
  case VPOPCNTWZ128rrkz:
20649
0
  case VPOPCNTWZ256rm:
20650
0
  case VPOPCNTWZ256rmk:
20651
0
  case VPOPCNTWZ256rmkz:
20652
0
  case VPOPCNTWZ256rr:
20653
0
  case VPOPCNTWZ256rrk:
20654
0
  case VPOPCNTWZ256rrkz:
20655
0
  case VPOPCNTWZrm:
20656
0
  case VPOPCNTWZrmk:
20657
0
  case VPOPCNTWZrmkz:
20658
0
  case VPOPCNTWZrr:
20659
0
  case VPOPCNTWZrrk:
20660
0
  case VPOPCNTWZrrkz:
20661
0
    return true;
20662
0
  }
20663
0
  return false;
20664
0
}
20665
20666
0
bool isVRSQRTSH(unsigned Opcode) {
20667
0
  switch (Opcode) {
20668
0
  case VRSQRTSHZrm:
20669
0
  case VRSQRTSHZrmk:
20670
0
  case VRSQRTSHZrmkz:
20671
0
  case VRSQRTSHZrr:
20672
0
  case VRSQRTSHZrrk:
20673
0
  case VRSQRTSHZrrkz:
20674
0
    return true;
20675
0
  }
20676
0
  return false;
20677
0
}
20678
20679
0
bool isVSCATTERPF0DPD(unsigned Opcode) {
20680
0
  return Opcode == VSCATTERPF0DPDm;
20681
0
}
20682
20683
0
bool isVFMADDPS(unsigned Opcode) {
20684
0
  switch (Opcode) {
20685
0
  case VFMADDPS4Ymr:
20686
0
  case VFMADDPS4Yrm:
20687
0
  case VFMADDPS4Yrr:
20688
0
  case VFMADDPS4Yrr_REV:
20689
0
  case VFMADDPS4mr:
20690
0
  case VFMADDPS4rm:
20691
0
  case VFMADDPS4rr:
20692
0
  case VFMADDPS4rr_REV:
20693
0
    return true;
20694
0
  }
20695
0
  return false;
20696
0
}
20697
20698
0
bool isXSAVEC64(unsigned Opcode) {
20699
0
  return Opcode == XSAVEC64;
20700
0
}
20701
20702
0
bool isVPMADDUBSW(unsigned Opcode) {
20703
0
  switch (Opcode) {
20704
0
  case VPMADDUBSWYrm:
20705
0
  case VPMADDUBSWYrr:
20706
0
  case VPMADDUBSWZ128rm:
20707
0
  case VPMADDUBSWZ128rmk:
20708
0
  case VPMADDUBSWZ128rmkz:
20709
0
  case VPMADDUBSWZ128rr:
20710
0
  case VPMADDUBSWZ128rrk:
20711
0
  case VPMADDUBSWZ128rrkz:
20712
0
  case VPMADDUBSWZ256rm:
20713
0
  case VPMADDUBSWZ256rmk:
20714
0
  case VPMADDUBSWZ256rmkz:
20715
0
  case VPMADDUBSWZ256rr:
20716
0
  case VPMADDUBSWZ256rrk:
20717
0
  case VPMADDUBSWZ256rrkz:
20718
0
  case VPMADDUBSWZrm:
20719
0
  case VPMADDUBSWZrmk:
20720
0
  case VPMADDUBSWZrmkz:
20721
0
  case VPMADDUBSWZrr:
20722
0
  case VPMADDUBSWZrrk:
20723
0
  case VPMADDUBSWZrrkz:
20724
0
  case VPMADDUBSWrm:
20725
0
  case VPMADDUBSWrr:
20726
0
    return true;
20727
0
  }
20728
0
  return false;
20729
0
}
20730
20731
0
bool isVPMOVZXDQ(unsigned Opcode) {
20732
0
  switch (Opcode) {
20733
0
  case VPMOVZXDQYrm:
20734
0
  case VPMOVZXDQYrr:
20735
0
  case VPMOVZXDQZ128rm:
20736
0
  case VPMOVZXDQZ128rmk:
20737
0
  case VPMOVZXDQZ128rmkz:
20738
0
  case VPMOVZXDQZ128rr:
20739
0
  case VPMOVZXDQZ128rrk:
20740
0
  case VPMOVZXDQZ128rrkz:
20741
0
  case VPMOVZXDQZ256rm:
20742
0
  case VPMOVZXDQZ256rmk:
20743
0
  case VPMOVZXDQZ256rmkz:
20744
0
  case VPMOVZXDQZ256rr:
20745
0
  case VPMOVZXDQZ256rrk:
20746
0
  case VPMOVZXDQZ256rrkz:
20747
0
  case VPMOVZXDQZrm:
20748
0
  case VPMOVZXDQZrmk:
20749
0
  case VPMOVZXDQZrmkz:
20750
0
  case VPMOVZXDQZrr:
20751
0
  case VPMOVZXDQZrrk:
20752
0
  case VPMOVZXDQZrrkz:
20753
0
  case VPMOVZXDQrm:
20754
0
  case VPMOVZXDQrr:
20755
0
    return true;
20756
0
  }
20757
0
  return false;
20758
0
}
20759
20760
0
bool isVRCP14PS(unsigned Opcode) {
20761
0
  switch (Opcode) {
20762
0
  case VRCP14PSZ128m:
20763
0
  case VRCP14PSZ128mb:
20764
0
  case VRCP14PSZ128mbk:
20765
0
  case VRCP14PSZ128mbkz:
20766
0
  case VRCP14PSZ128mk:
20767
0
  case VRCP14PSZ128mkz:
20768
0
  case VRCP14PSZ128r:
20769
0
  case VRCP14PSZ128rk:
20770
0
  case VRCP14PSZ128rkz:
20771
0
  case VRCP14PSZ256m:
20772
0
  case VRCP14PSZ256mb:
20773
0
  case VRCP14PSZ256mbk:
20774
0
  case VRCP14PSZ256mbkz:
20775
0
  case VRCP14PSZ256mk:
20776
0
  case VRCP14PSZ256mkz:
20777
0
  case VRCP14PSZ256r:
20778
0
  case VRCP14PSZ256rk:
20779
0
  case VRCP14PSZ256rkz:
20780
0
  case VRCP14PSZm:
20781
0
  case VRCP14PSZmb:
20782
0
  case VRCP14PSZmbk:
20783
0
  case VRCP14PSZmbkz:
20784
0
  case VRCP14PSZmk:
20785
0
  case VRCP14PSZmkz:
20786
0
  case VRCP14PSZr:
20787
0
  case VRCP14PSZrk:
20788
0
  case VRCP14PSZrkz:
20789
0
    return true;
20790
0
  }
20791
0
  return false;
20792
0
}
20793
20794
0
bool isVSQRTSH(unsigned Opcode) {
20795
0
  switch (Opcode) {
20796
0
  case VSQRTSHZm_Int:
20797
0
  case VSQRTSHZm_Intk:
20798
0
  case VSQRTSHZm_Intkz:
20799
0
  case VSQRTSHZr_Int:
20800
0
  case VSQRTSHZr_Intk:
20801
0
  case VSQRTSHZr_Intkz:
20802
0
  case VSQRTSHZrb_Int:
20803
0
  case VSQRTSHZrb_Intk:
20804
0
  case VSQRTSHZrb_Intkz:
20805
0
    return true;
20806
0
  }
20807
0
  return false;
20808
0
}
20809
20810
0
bool isLOOP(unsigned Opcode) {
20811
0
  return Opcode == LOOP;
20812
0
}
20813
20814
0
bool isSTUI(unsigned Opcode) {
20815
0
  return Opcode == STUI;
20816
0
}
20817
20818
0
bool isVCVTTPS2UDQ(unsigned Opcode) {
20819
0
  switch (Opcode) {
20820
0
  case VCVTTPS2UDQZ128rm:
20821
0
  case VCVTTPS2UDQZ128rmb:
20822
0
  case VCVTTPS2UDQZ128rmbk:
20823
0
  case VCVTTPS2UDQZ128rmbkz:
20824
0
  case VCVTTPS2UDQZ128rmk:
20825
0
  case VCVTTPS2UDQZ128rmkz:
20826
0
  case VCVTTPS2UDQZ128rr:
20827
0
  case VCVTTPS2UDQZ128rrk:
20828
0
  case VCVTTPS2UDQZ128rrkz:
20829
0
  case VCVTTPS2UDQZ256rm:
20830
0
  case VCVTTPS2UDQZ256rmb:
20831
0
  case VCVTTPS2UDQZ256rmbk:
20832
0
  case VCVTTPS2UDQZ256rmbkz:
20833
0
  case VCVTTPS2UDQZ256rmk:
20834
0
  case VCVTTPS2UDQZ256rmkz:
20835
0
  case VCVTTPS2UDQZ256rr:
20836
0
  case VCVTTPS2UDQZ256rrk:
20837
0
  case VCVTTPS2UDQZ256rrkz:
20838
0
  case VCVTTPS2UDQZrm:
20839
0
  case VCVTTPS2UDQZrmb:
20840
0
  case VCVTTPS2UDQZrmbk:
20841
0
  case VCVTTPS2UDQZrmbkz:
20842
0
  case VCVTTPS2UDQZrmk:
20843
0
  case VCVTTPS2UDQZrmkz:
20844
0
  case VCVTTPS2UDQZrr:
20845
0
  case VCVTTPS2UDQZrrb:
20846
0
  case VCVTTPS2UDQZrrbk:
20847
0
  case VCVTTPS2UDQZrrbkz:
20848
0
  case VCVTTPS2UDQZrrk:
20849
0
  case VCVTTPS2UDQZrrkz:
20850
0
    return true;
20851
0
  }
20852
0
  return false;
20853
0
}
20854
20855
0
bool isVCOMPRESSPS(unsigned Opcode) {
20856
0
  switch (Opcode) {
20857
0
  case VCOMPRESSPSZ128mr:
20858
0
  case VCOMPRESSPSZ128mrk:
20859
0
  case VCOMPRESSPSZ128rr:
20860
0
  case VCOMPRESSPSZ128rrk:
20861
0
  case VCOMPRESSPSZ128rrkz:
20862
0
  case VCOMPRESSPSZ256mr:
20863
0
  case VCOMPRESSPSZ256mrk:
20864
0
  case VCOMPRESSPSZ256rr:
20865
0
  case VCOMPRESSPSZ256rrk:
20866
0
  case VCOMPRESSPSZ256rrkz:
20867
0
  case VCOMPRESSPSZmr:
20868
0
  case VCOMPRESSPSZmrk:
20869
0
  case VCOMPRESSPSZrr:
20870
0
  case VCOMPRESSPSZrrk:
20871
0
  case VCOMPRESSPSZrrkz:
20872
0
    return true;
20873
0
  }
20874
0
  return false;
20875
0
}
20876
20877
0
bool isXABORT(unsigned Opcode) {
20878
0
  return Opcode == XABORT;
20879
0
}
20880
20881
0
bool isVPADDW(unsigned Opcode) {
20882
0
  switch (Opcode) {
20883
0
  case VPADDWYrm:
20884
0
  case VPADDWYrr:
20885
0
  case VPADDWZ128rm:
20886
0
  case VPADDWZ128rmk:
20887
0
  case VPADDWZ128rmkz:
20888
0
  case VPADDWZ128rr:
20889
0
  case VPADDWZ128rrk:
20890
0
  case VPADDWZ128rrkz:
20891
0
  case VPADDWZ256rm:
20892
0
  case VPADDWZ256rmk:
20893
0
  case VPADDWZ256rmkz:
20894
0
  case VPADDWZ256rr:
20895
0
  case VPADDWZ256rrk:
20896
0
  case VPADDWZ256rrkz:
20897
0
  case VPADDWZrm:
20898
0
  case VPADDWZrmk:
20899
0
  case VPADDWZrmkz:
20900
0
  case VPADDWZrr:
20901
0
  case VPADDWZrrk:
20902
0
  case VPADDWZrrkz:
20903
0
  case VPADDWrm:
20904
0
  case VPADDWrr:
20905
0
    return true;
20906
0
  }
20907
0
  return false;
20908
0
}
20909
20910
0
bool isVPSIGND(unsigned Opcode) {
20911
0
  switch (Opcode) {
20912
0
  case VPSIGNDYrm:
20913
0
  case VPSIGNDYrr:
20914
0
  case VPSIGNDrm:
20915
0
  case VPSIGNDrr:
20916
0
    return true;
20917
0
  }
20918
0
  return false;
20919
0
}
20920
20921
0
bool isVRNDSCALEPS(unsigned Opcode) {
20922
0
  switch (Opcode) {
20923
0
  case VRNDSCALEPSZ128rmbi:
20924
0
  case VRNDSCALEPSZ128rmbik:
20925
0
  case VRNDSCALEPSZ128rmbikz:
20926
0
  case VRNDSCALEPSZ128rmi:
20927
0
  case VRNDSCALEPSZ128rmik:
20928
0
  case VRNDSCALEPSZ128rmikz:
20929
0
  case VRNDSCALEPSZ128rri:
20930
0
  case VRNDSCALEPSZ128rrik:
20931
0
  case VRNDSCALEPSZ128rrikz:
20932
0
  case VRNDSCALEPSZ256rmbi:
20933
0
  case VRNDSCALEPSZ256rmbik:
20934
0
  case VRNDSCALEPSZ256rmbikz:
20935
0
  case VRNDSCALEPSZ256rmi:
20936
0
  case VRNDSCALEPSZ256rmik:
20937
0
  case VRNDSCALEPSZ256rmikz:
20938
0
  case VRNDSCALEPSZ256rri:
20939
0
  case VRNDSCALEPSZ256rrik:
20940
0
  case VRNDSCALEPSZ256rrikz:
20941
0
  case VRNDSCALEPSZrmbi:
20942
0
  case VRNDSCALEPSZrmbik:
20943
0
  case VRNDSCALEPSZrmbikz:
20944
0
  case VRNDSCALEPSZrmi:
20945
0
  case VRNDSCALEPSZrmik:
20946
0
  case VRNDSCALEPSZrmikz:
20947
0
  case VRNDSCALEPSZrri:
20948
0
  case VRNDSCALEPSZrrib:
20949
0
  case VRNDSCALEPSZrribk:
20950
0
  case VRNDSCALEPSZrribkz:
20951
0
  case VRNDSCALEPSZrrik:
20952
0
  case VRNDSCALEPSZrrikz:
20953
0
    return true;
20954
0
  }
20955
0
  return false;
20956
0
}
20957
20958
0
bool isVPHADDUWD(unsigned Opcode) {
20959
0
  switch (Opcode) {
20960
0
  case VPHADDUWDrm:
20961
0
  case VPHADDUWDrr:
20962
0
    return true;
20963
0
  }
20964
0
  return false;
20965
0
}
20966
20967
0
bool isVDBPSADBW(unsigned Opcode) {
20968
0
  switch (Opcode) {
20969
0
  case VDBPSADBWZ128rmi:
20970
0
  case VDBPSADBWZ128rmik:
20971
0
  case VDBPSADBWZ128rmikz:
20972
0
  case VDBPSADBWZ128rri:
20973
0
  case VDBPSADBWZ128rrik:
20974
0
  case VDBPSADBWZ128rrikz:
20975
0
  case VDBPSADBWZ256rmi:
20976
0
  case VDBPSADBWZ256rmik:
20977
0
  case VDBPSADBWZ256rmikz:
20978
0
  case VDBPSADBWZ256rri:
20979
0
  case VDBPSADBWZ256rrik:
20980
0
  case VDBPSADBWZ256rrikz:
20981
0
  case VDBPSADBWZrmi:
20982
0
  case VDBPSADBWZrmik:
20983
0
  case VDBPSADBWZrmikz:
20984
0
  case VDBPSADBWZrri:
20985
0
  case VDBPSADBWZrrik:
20986
0
  case VDBPSADBWZrrikz:
20987
0
    return true;
20988
0
  }
20989
0
  return false;
20990
0
}
20991
20992
0
bool isPSLLW(unsigned Opcode) {
20993
0
  switch (Opcode) {
20994
0
  case MMX_PSLLWri:
20995
0
  case MMX_PSLLWrm:
20996
0
  case MMX_PSLLWrr:
20997
0
  case PSLLWri:
20998
0
  case PSLLWrm:
20999
0
  case PSLLWrr:
21000
0
    return true;
21001
0
  }
21002
0
  return false;
21003
0
}
21004
21005
0
bool isVPMOVQD(unsigned Opcode) {
21006
0
  switch (Opcode) {
21007
0
  case VPMOVQDZ128mr:
21008
0
  case VPMOVQDZ128mrk:
21009
0
  case VPMOVQDZ128rr:
21010
0
  case VPMOVQDZ128rrk:
21011
0
  case VPMOVQDZ128rrkz:
21012
0
  case VPMOVQDZ256mr:
21013
0
  case VPMOVQDZ256mrk:
21014
0
  case VPMOVQDZ256rr:
21015
0
  case VPMOVQDZ256rrk:
21016
0
  case VPMOVQDZ256rrkz:
21017
0
  case VPMOVQDZmr:
21018
0
  case VPMOVQDZmrk:
21019
0
  case VPMOVQDZrr:
21020
0
  case VPMOVQDZrrk:
21021
0
  case VPMOVQDZrrkz:
21022
0
    return true;
21023
0
  }
21024
0
  return false;
21025
0
}
21026
21027
0
bool isVINSERTI64X4(unsigned Opcode) {
21028
0
  switch (Opcode) {
21029
0
  case VINSERTI64x4Zrm:
21030
0
  case VINSERTI64x4Zrmk:
21031
0
  case VINSERTI64x4Zrmkz:
21032
0
  case VINSERTI64x4Zrr:
21033
0
  case VINSERTI64x4Zrrk:
21034
0
  case VINSERTI64x4Zrrkz:
21035
0
    return true;
21036
0
  }
21037
0
  return false;
21038
0
}
21039
21040
0
bool isVPERMI2PS(unsigned Opcode) {
21041
0
  switch (Opcode) {
21042
0
  case VPERMI2PSZ128rm:
21043
0
  case VPERMI2PSZ128rmb:
21044
0
  case VPERMI2PSZ128rmbk:
21045
0
  case VPERMI2PSZ128rmbkz:
21046
0
  case VPERMI2PSZ128rmk:
21047
0
  case VPERMI2PSZ128rmkz:
21048
0
  case VPERMI2PSZ128rr:
21049
0
  case VPERMI2PSZ128rrk:
21050
0
  case VPERMI2PSZ128rrkz:
21051
0
  case VPERMI2PSZ256rm:
21052
0
  case VPERMI2PSZ256rmb:
21053
0
  case VPERMI2PSZ256rmbk:
21054
0
  case VPERMI2PSZ256rmbkz:
21055
0
  case VPERMI2PSZ256rmk:
21056
0
  case VPERMI2PSZ256rmkz:
21057
0
  case VPERMI2PSZ256rr:
21058
0
  case VPERMI2PSZ256rrk:
21059
0
  case VPERMI2PSZ256rrkz:
21060
0
  case VPERMI2PSZrm:
21061
0
  case VPERMI2PSZrmb:
21062
0
  case VPERMI2PSZrmbk:
21063
0
  case VPERMI2PSZrmbkz:
21064
0
  case VPERMI2PSZrmk:
21065
0
  case VPERMI2PSZrmkz:
21066
0
  case VPERMI2PSZrr:
21067
0
  case VPERMI2PSZrrk:
21068
0
  case VPERMI2PSZrrkz:
21069
0
    return true;
21070
0
  }
21071
0
  return false;
21072
0
}
21073
21074
0
bool isVMULPH(unsigned Opcode) {
21075
0
  switch (Opcode) {
21076
0
  case VMULPHZ128rm:
21077
0
  case VMULPHZ128rmb:
21078
0
  case VMULPHZ128rmbk:
21079
0
  case VMULPHZ128rmbkz:
21080
0
  case VMULPHZ128rmk:
21081
0
  case VMULPHZ128rmkz:
21082
0
  case VMULPHZ128rr:
21083
0
  case VMULPHZ128rrk:
21084
0
  case VMULPHZ128rrkz:
21085
0
  case VMULPHZ256rm:
21086
0
  case VMULPHZ256rmb:
21087
0
  case VMULPHZ256rmbk:
21088
0
  case VMULPHZ256rmbkz:
21089
0
  case VMULPHZ256rmk:
21090
0
  case VMULPHZ256rmkz:
21091
0
  case VMULPHZ256rr:
21092
0
  case VMULPHZ256rrk:
21093
0
  case VMULPHZ256rrkz:
21094
0
  case VMULPHZrm:
21095
0
  case VMULPHZrmb:
21096
0
  case VMULPHZrmbk:
21097
0
  case VMULPHZrmbkz:
21098
0
  case VMULPHZrmk:
21099
0
  case VMULPHZrmkz:
21100
0
  case VMULPHZrr:
21101
0
  case VMULPHZrrb:
21102
0
  case VMULPHZrrbk:
21103
0
  case VMULPHZrrbkz:
21104
0
  case VMULPHZrrk:
21105
0
  case VMULPHZrrkz:
21106
0
    return true;
21107
0
  }
21108
0
  return false;
21109
0
}
21110
21111
0
bool isVPCMPUQ(unsigned Opcode) {
21112
0
  switch (Opcode) {
21113
0
  case VPCMPUQZ128rmi:
21114
0
  case VPCMPUQZ128rmib:
21115
0
  case VPCMPUQZ128rmibk:
21116
0
  case VPCMPUQZ128rmik:
21117
0
  case VPCMPUQZ128rri:
21118
0
  case VPCMPUQZ128rrik:
21119
0
  case VPCMPUQZ256rmi:
21120
0
  case VPCMPUQZ256rmib:
21121
0
  case VPCMPUQZ256rmibk:
21122
0
  case VPCMPUQZ256rmik:
21123
0
  case VPCMPUQZ256rri:
21124
0
  case VPCMPUQZ256rrik:
21125
0
  case VPCMPUQZrmi:
21126
0
  case VPCMPUQZrmib:
21127
0
  case VPCMPUQZrmibk:
21128
0
  case VPCMPUQZrmik:
21129
0
  case VPCMPUQZrri:
21130
0
  case VPCMPUQZrrik:
21131
0
    return true;
21132
0
  }
21133
0
  return false;
21134
0
}
21135
21136
0
bool isVCVTUSI2SD(unsigned Opcode) {
21137
0
  switch (Opcode) {
21138
0
  case VCVTUSI2SDZrm_Int:
21139
0
  case VCVTUSI2SDZrr_Int:
21140
0
  case VCVTUSI642SDZrm_Int:
21141
0
  case VCVTUSI642SDZrr_Int:
21142
0
  case VCVTUSI642SDZrrb_Int:
21143
0
    return true;
21144
0
  }
21145
0
  return false;
21146
0
}
21147
21148
0
bool isKXNORW(unsigned Opcode) {
21149
0
  return Opcode == KXNORWrr;
21150
0
}
21151
21152
0
bool isBLCIC(unsigned Opcode) {
21153
0
  switch (Opcode) {
21154
0
  case BLCIC32rm:
21155
0
  case BLCIC32rr:
21156
0
  case BLCIC64rm:
21157
0
  case BLCIC64rr:
21158
0
    return true;
21159
0
  }
21160
0
  return false;
21161
0
}
21162
21163
0
bool isVFNMADD213SD(unsigned Opcode) {
21164
0
  switch (Opcode) {
21165
0
  case VFNMADD213SDZm_Int:
21166
0
  case VFNMADD213SDZm_Intk:
21167
0
  case VFNMADD213SDZm_Intkz:
21168
0
  case VFNMADD213SDZr_Int:
21169
0
  case VFNMADD213SDZr_Intk:
21170
0
  case VFNMADD213SDZr_Intkz:
21171
0
  case VFNMADD213SDZrb_Int:
21172
0
  case VFNMADD213SDZrb_Intk:
21173
0
  case VFNMADD213SDZrb_Intkz:
21174
0
  case VFNMADD213SDm_Int:
21175
0
  case VFNMADD213SDr_Int:
21176
0
    return true;
21177
0
  }
21178
0
  return false;
21179
0
}
21180
21181
0
bool isVPMACSWW(unsigned Opcode) {
21182
0
  switch (Opcode) {
21183
0
  case VPMACSWWrm:
21184
0
  case VPMACSWWrr:
21185
0
    return true;
21186
0
  }
21187
0
  return false;
21188
0
}
21189
21190
0
bool isVMOVLPS(unsigned Opcode) {
21191
0
  switch (Opcode) {
21192
0
  case VMOVLPSZ128mr:
21193
0
  case VMOVLPSZ128rm:
21194
0
  case VMOVLPSmr:
21195
0
  case VMOVLPSrm:
21196
0
    return true;
21197
0
  }
21198
0
  return false;
21199
0
}
21200
21201
0
bool isPCONFIG(unsigned Opcode) {
21202
0
  return Opcode == PCONFIG;
21203
0
}
21204
21205
0
bool isPANDN(unsigned Opcode) {
21206
0
  switch (Opcode) {
21207
0
  case MMX_PANDNrm:
21208
0
  case MMX_PANDNrr:
21209
0
  case PANDNrm:
21210
0
  case PANDNrr:
21211
0
    return true;
21212
0
  }
21213
0
  return false;
21214
0
}
21215
21216
0
bool isVGETEXPPD(unsigned Opcode) {
21217
0
  switch (Opcode) {
21218
0
  case VGETEXPPDZ128m:
21219
0
  case VGETEXPPDZ128mb:
21220
0
  case VGETEXPPDZ128mbk:
21221
0
  case VGETEXPPDZ128mbkz:
21222
0
  case VGETEXPPDZ128mk:
21223
0
  case VGETEXPPDZ128mkz:
21224
0
  case VGETEXPPDZ128r:
21225
0
  case VGETEXPPDZ128rk:
21226
0
  case VGETEXPPDZ128rkz:
21227
0
  case VGETEXPPDZ256m:
21228
0
  case VGETEXPPDZ256mb:
21229
0
  case VGETEXPPDZ256mbk:
21230
0
  case VGETEXPPDZ256mbkz:
21231
0
  case VGETEXPPDZ256mk:
21232
0
  case VGETEXPPDZ256mkz:
21233
0
  case VGETEXPPDZ256r:
21234
0
  case VGETEXPPDZ256rk:
21235
0
  case VGETEXPPDZ256rkz:
21236
0
  case VGETEXPPDZm:
21237
0
  case VGETEXPPDZmb:
21238
0
  case VGETEXPPDZmbk:
21239
0
  case VGETEXPPDZmbkz:
21240
0
  case VGETEXPPDZmk:
21241
0
  case VGETEXPPDZmkz:
21242
0
  case VGETEXPPDZr:
21243
0
  case VGETEXPPDZrb:
21244
0
  case VGETEXPPDZrbk:
21245
0
  case VGETEXPPDZrbkz:
21246
0
  case VGETEXPPDZrk:
21247
0
  case VGETEXPPDZrkz:
21248
0
    return true;
21249
0
  }
21250
0
  return false;
21251
0
}
21252
21253
0
bool isVPSRLVQ(unsigned Opcode) {
21254
0
  switch (Opcode) {
21255
0
  case VPSRLVQYrm:
21256
0
  case VPSRLVQYrr:
21257
0
  case VPSRLVQZ128rm:
21258
0
  case VPSRLVQZ128rmb:
21259
0
  case VPSRLVQZ128rmbk:
21260
0
  case VPSRLVQZ128rmbkz:
21261
0
  case VPSRLVQZ128rmk:
21262
0
  case VPSRLVQZ128rmkz:
21263
0
  case VPSRLVQZ128rr:
21264
0
  case VPSRLVQZ128rrk:
21265
0
  case VPSRLVQZ128rrkz:
21266
0
  case VPSRLVQZ256rm:
21267
0
  case VPSRLVQZ256rmb:
21268
0
  case VPSRLVQZ256rmbk:
21269
0
  case VPSRLVQZ256rmbkz:
21270
0
  case VPSRLVQZ256rmk:
21271
0
  case VPSRLVQZ256rmkz:
21272
0
  case VPSRLVQZ256rr:
21273
0
  case VPSRLVQZ256rrk:
21274
0
  case VPSRLVQZ256rrkz:
21275
0
  case VPSRLVQZrm:
21276
0
  case VPSRLVQZrmb:
21277
0
  case VPSRLVQZrmbk:
21278
0
  case VPSRLVQZrmbkz:
21279
0
  case VPSRLVQZrmk:
21280
0
  case VPSRLVQZrmkz:
21281
0
  case VPSRLVQZrr:
21282
0
  case VPSRLVQZrrk:
21283
0
  case VPSRLVQZrrkz:
21284
0
  case VPSRLVQrm:
21285
0
  case VPSRLVQrr:
21286
0
    return true;
21287
0
  }
21288
0
  return false;
21289
0
}
21290
21291
0
bool isUD1(unsigned Opcode) {
21292
0
  switch (Opcode) {
21293
0
  case UD1Lm:
21294
0
  case UD1Lr:
21295
0
  case UD1Qm:
21296
0
  case UD1Qr:
21297
0
  case UD1Wm:
21298
0
  case UD1Wr:
21299
0
    return true;
21300
0
  }
21301
0
  return false;
21302
0
}
21303
21304
0
bool isPMAXSB(unsigned Opcode) {
21305
0
  switch (Opcode) {
21306
0
  case PMAXSBrm:
21307
0
  case PMAXSBrr:
21308
0
    return true;
21309
0
  }
21310
0
  return false;
21311
0
}
21312
21313
0
bool isVPROLQ(unsigned Opcode) {
21314
0
  switch (Opcode) {
21315
0
  case VPROLQZ128mbi:
21316
0
  case VPROLQZ128mbik:
21317
0
  case VPROLQZ128mbikz:
21318
0
  case VPROLQZ128mi:
21319
0
  case VPROLQZ128mik:
21320
0
  case VPROLQZ128mikz:
21321
0
  case VPROLQZ128ri:
21322
0
  case VPROLQZ128rik:
21323
0
  case VPROLQZ128rikz:
21324
0
  case VPROLQZ256mbi:
21325
0
  case VPROLQZ256mbik:
21326
0
  case VPROLQZ256mbikz:
21327
0
  case VPROLQZ256mi:
21328
0
  case VPROLQZ256mik:
21329
0
  case VPROLQZ256mikz:
21330
0
  case VPROLQZ256ri:
21331
0
  case VPROLQZ256rik:
21332
0
  case VPROLQZ256rikz:
21333
0
  case VPROLQZmbi:
21334
0
  case VPROLQZmbik:
21335
0
  case VPROLQZmbikz:
21336
0
  case VPROLQZmi:
21337
0
  case VPROLQZmik:
21338
0
  case VPROLQZmikz:
21339
0
  case VPROLQZri:
21340
0
  case VPROLQZrik:
21341
0
  case VPROLQZrikz:
21342
0
    return true;
21343
0
  }
21344
0
  return false;
21345
0
}
21346
21347
0
bool isVSCATTERPF1QPD(unsigned Opcode) {
21348
0
  return Opcode == VSCATTERPF1QPDm;
21349
0
}
21350
21351
0
bool isVPSRLD(unsigned Opcode) {
21352
0
  switch (Opcode) {
21353
0
  case VPSRLDYri:
21354
0
  case VPSRLDYrm:
21355
0
  case VPSRLDYrr:
21356
0
  case VPSRLDZ128mbi:
21357
0
  case VPSRLDZ128mbik:
21358
0
  case VPSRLDZ128mbikz:
21359
0
  case VPSRLDZ128mi:
21360
0
  case VPSRLDZ128mik:
21361
0
  case VPSRLDZ128mikz:
21362
0
  case VPSRLDZ128ri:
21363
0
  case VPSRLDZ128rik:
21364
0
  case VPSRLDZ128rikz:
21365
0
  case VPSRLDZ128rm:
21366
0
  case VPSRLDZ128rmk:
21367
0
  case VPSRLDZ128rmkz:
21368
0
  case VPSRLDZ128rr:
21369
0
  case VPSRLDZ128rrk:
21370
0
  case VPSRLDZ128rrkz:
21371
0
  case VPSRLDZ256mbi:
21372
0
  case VPSRLDZ256mbik:
21373
0
  case VPSRLDZ256mbikz:
21374
0
  case VPSRLDZ256mi:
21375
0
  case VPSRLDZ256mik:
21376
0
  case VPSRLDZ256mikz:
21377
0
  case VPSRLDZ256ri:
21378
0
  case VPSRLDZ256rik:
21379
0
  case VPSRLDZ256rikz:
21380
0
  case VPSRLDZ256rm:
21381
0
  case VPSRLDZ256rmk:
21382
0
  case VPSRLDZ256rmkz:
21383
0
  case VPSRLDZ256rr:
21384
0
  case VPSRLDZ256rrk:
21385
0
  case VPSRLDZ256rrkz:
21386
0
  case VPSRLDZmbi:
21387
0
  case VPSRLDZmbik:
21388
0
  case VPSRLDZmbikz:
21389
0
  case VPSRLDZmi:
21390
0
  case VPSRLDZmik:
21391
0
  case VPSRLDZmikz:
21392
0
  case VPSRLDZri:
21393
0
  case VPSRLDZrik:
21394
0
  case VPSRLDZrikz:
21395
0
  case VPSRLDZrm:
21396
0
  case VPSRLDZrmk:
21397
0
  case VPSRLDZrmkz:
21398
0
  case VPSRLDZrr:
21399
0
  case VPSRLDZrrk:
21400
0
  case VPSRLDZrrkz:
21401
0
  case VPSRLDri:
21402
0
  case VPSRLDrm:
21403
0
  case VPSRLDrr:
21404
0
    return true;
21405
0
  }
21406
0
  return false;
21407
0
}
21408
21409
0
bool isINT3(unsigned Opcode) {
21410
0
  return Opcode == INT3;
21411
0
}
21412
21413
0
bool isXRSTORS64(unsigned Opcode) {
21414
0
  return Opcode == XRSTORS64;
21415
0
}
21416
21417
0
bool isCVTSD2SI(unsigned Opcode) {
21418
0
  switch (Opcode) {
21419
0
  case CVTSD2SI64rm_Int:
21420
0
  case CVTSD2SI64rr_Int:
21421
0
  case CVTSD2SIrm_Int:
21422
0
  case CVTSD2SIrr_Int:
21423
0
    return true;
21424
0
  }
21425
0
  return false;
21426
0
}
21427
21428
0
bool isVMAXSS(unsigned Opcode) {
21429
0
  switch (Opcode) {
21430
0
  case VMAXSSZrm_Int:
21431
0
  case VMAXSSZrm_Intk:
21432
0
  case VMAXSSZrm_Intkz:
21433
0
  case VMAXSSZrr_Int:
21434
0
  case VMAXSSZrr_Intk:
21435
0
  case VMAXSSZrr_Intkz:
21436
0
  case VMAXSSZrrb_Int:
21437
0
  case VMAXSSZrrb_Intk:
21438
0
  case VMAXSSZrrb_Intkz:
21439
0
  case VMAXSSrm_Int:
21440
0
  case VMAXSSrr_Int:
21441
0
    return true;
21442
0
  }
21443
0
  return false;
21444
0
}
21445
21446
0
bool isVPMINUB(unsigned Opcode) {
21447
0
  switch (Opcode) {
21448
0
  case VPMINUBYrm:
21449
0
  case VPMINUBYrr:
21450
0
  case VPMINUBZ128rm:
21451
0
  case VPMINUBZ128rmk:
21452
0
  case VPMINUBZ128rmkz:
21453
0
  case VPMINUBZ128rr:
21454
0
  case VPMINUBZ128rrk:
21455
0
  case VPMINUBZ128rrkz:
21456
0
  case VPMINUBZ256rm:
21457
0
  case VPMINUBZ256rmk:
21458
0
  case VPMINUBZ256rmkz:
21459
0
  case VPMINUBZ256rr:
21460
0
  case VPMINUBZ256rrk:
21461
0
  case VPMINUBZ256rrkz:
21462
0
  case VPMINUBZrm:
21463
0
  case VPMINUBZrmk:
21464
0
  case VPMINUBZrmkz:
21465
0
  case VPMINUBZrr:
21466
0
  case VPMINUBZrrk:
21467
0
  case VPMINUBZrrkz:
21468
0
  case VPMINUBrm:
21469
0
  case VPMINUBrr:
21470
0
    return true;
21471
0
  }
21472
0
  return false;
21473
0
}
21474
21475
0
bool isKXNORQ(unsigned Opcode) {
21476
0
  return Opcode == KXNORQrr;
21477
0
}
21478
21479
0
bool isFLD(unsigned Opcode) {
21480
0
  switch (Opcode) {
21481
0
  case LD_F32m:
21482
0
  case LD_F64m:
21483
0
  case LD_F80m:
21484
0
  case LD_Frr:
21485
0
    return true;
21486
0
  }
21487
0
  return false;
21488
0
}
21489
21490
0
bool isVSHUFI32X4(unsigned Opcode) {
21491
0
  switch (Opcode) {
21492
0
  case VSHUFI32X4Z256rmbi:
21493
0
  case VSHUFI32X4Z256rmbik:
21494
0
  case VSHUFI32X4Z256rmbikz:
21495
0
  case VSHUFI32X4Z256rmi:
21496
0
  case VSHUFI32X4Z256rmik:
21497
0
  case VSHUFI32X4Z256rmikz:
21498
0
  case VSHUFI32X4Z256rri:
21499
0
  case VSHUFI32X4Z256rrik:
21500
0
  case VSHUFI32X4Z256rrikz:
21501
0
  case VSHUFI32X4Zrmbi:
21502
0
  case VSHUFI32X4Zrmbik:
21503
0
  case VSHUFI32X4Zrmbikz:
21504
0
  case VSHUFI32X4Zrmi:
21505
0
  case VSHUFI32X4Zrmik:
21506
0
  case VSHUFI32X4Zrmikz:
21507
0
  case VSHUFI32X4Zrri:
21508
0
  case VSHUFI32X4Zrrik:
21509
0
  case VSHUFI32X4Zrrikz:
21510
0
    return true;
21511
0
  }
21512
0
  return false;
21513
0
}
21514
21515
0
bool isSAHF(unsigned Opcode) {
21516
0
  return Opcode == SAHF;
21517
0
}
21518
21519
0
bool isPFRSQRT(unsigned Opcode) {
21520
0
  switch (Opcode) {
21521
0
  case PFRSQRTrm:
21522
0
  case PFRSQRTrr:
21523
0
    return true;
21524
0
  }
21525
0
  return false;
21526
0
}
21527
21528
0
bool isSHRD(unsigned Opcode) {
21529
0
  switch (Opcode) {
21530
0
  case SHRD16mrCL:
21531
0
  case SHRD16mri8:
21532
0
  case SHRD16rrCL:
21533
0
  case SHRD16rri8:
21534
0
  case SHRD32mrCL:
21535
0
  case SHRD32mri8:
21536
0
  case SHRD32rrCL:
21537
0
  case SHRD32rri8:
21538
0
  case SHRD64mrCL:
21539
0
  case SHRD64mri8:
21540
0
  case SHRD64rrCL:
21541
0
  case SHRD64rri8:
21542
0
    return true;
21543
0
  }
21544
0
  return false;
21545
0
}
21546
21547
0
bool isSYSEXIT(unsigned Opcode) {
21548
0
  return Opcode == SYSEXIT;
21549
0
}
21550
21551
0
bool isXSAVE64(unsigned Opcode) {
21552
0
  return Opcode == XSAVE64;
21553
0
}
21554
21555
0
bool isVPMAXSD(unsigned Opcode) {
21556
0
  switch (Opcode) {
21557
0
  case VPMAXSDYrm:
21558
0
  case VPMAXSDYrr:
21559
0
  case VPMAXSDZ128rm:
21560
0
  case VPMAXSDZ128rmb:
21561
0
  case VPMAXSDZ128rmbk:
21562
0
  case VPMAXSDZ128rmbkz:
21563
0
  case VPMAXSDZ128rmk:
21564
0
  case VPMAXSDZ128rmkz:
21565
0
  case VPMAXSDZ128rr:
21566
0
  case VPMAXSDZ128rrk:
21567
0
  case VPMAXSDZ128rrkz:
21568
0
  case VPMAXSDZ256rm:
21569
0
  case VPMAXSDZ256rmb:
21570
0
  case VPMAXSDZ256rmbk:
21571
0
  case VPMAXSDZ256rmbkz:
21572
0
  case VPMAXSDZ256rmk:
21573
0
  case VPMAXSDZ256rmkz:
21574
0
  case VPMAXSDZ256rr:
21575
0
  case VPMAXSDZ256rrk:
21576
0
  case VPMAXSDZ256rrkz:
21577
0
  case VPMAXSDZrm:
21578
0
  case VPMAXSDZrmb:
21579
0
  case VPMAXSDZrmbk:
21580
0
  case VPMAXSDZrmbkz:
21581
0
  case VPMAXSDZrmk:
21582
0
  case VPMAXSDZrmkz:
21583
0
  case VPMAXSDZrr:
21584
0
  case VPMAXSDZrrk:
21585
0
  case VPMAXSDZrrkz:
21586
0
  case VPMAXSDrm:
21587
0
  case VPMAXSDrr:
21588
0
    return true;
21589
0
  }
21590
0
  return false;
21591
0
}
21592
21593
0
bool isCVTTSD2SI(unsigned Opcode) {
21594
0
  switch (Opcode) {
21595
0
  case CVTTSD2SI64rm_Int:
21596
0
  case CVTTSD2SI64rr_Int:
21597
0
  case CVTTSD2SIrm_Int:
21598
0
  case CVTTSD2SIrr_Int:
21599
0
    return true;
21600
0
  }
21601
0
  return false;
21602
0
}
21603
21604
0
bool isPMOVMSKB(unsigned Opcode) {
21605
0
  switch (Opcode) {
21606
0
  case MMX_PMOVMSKBrr:
21607
0
  case PMOVMSKBrr:
21608
0
    return true;
21609
0
  }
21610
0
  return false;
21611
0
}
21612
21613
0
bool isVRANGEPS(unsigned Opcode) {
21614
0
  switch (Opcode) {
21615
0
  case VRANGEPSZ128rmbi:
21616
0
  case VRANGEPSZ128rmbik:
21617
0
  case VRANGEPSZ128rmbikz:
21618
0
  case VRANGEPSZ128rmi:
21619
0
  case VRANGEPSZ128rmik:
21620
0
  case VRANGEPSZ128rmikz:
21621
0
  case VRANGEPSZ128rri:
21622
0
  case VRANGEPSZ128rrik:
21623
0
  case VRANGEPSZ128rrikz:
21624
0
  case VRANGEPSZ256rmbi:
21625
0
  case VRANGEPSZ256rmbik:
21626
0
  case VRANGEPSZ256rmbikz:
21627
0
  case VRANGEPSZ256rmi:
21628
0
  case VRANGEPSZ256rmik:
21629
0
  case VRANGEPSZ256rmikz:
21630
0
  case VRANGEPSZ256rri:
21631
0
  case VRANGEPSZ256rrik:
21632
0
  case VRANGEPSZ256rrikz:
21633
0
  case VRANGEPSZrmbi:
21634
0
  case VRANGEPSZrmbik:
21635
0
  case VRANGEPSZrmbikz:
21636
0
  case VRANGEPSZrmi:
21637
0
  case VRANGEPSZrmik:
21638
0
  case VRANGEPSZrmikz:
21639
0
  case VRANGEPSZrri:
21640
0
  case VRANGEPSZrrib:
21641
0
  case VRANGEPSZrribk:
21642
0
  case VRANGEPSZrribkz:
21643
0
  case VRANGEPSZrrik:
21644
0
  case VRANGEPSZrrikz:
21645
0
    return true;
21646
0
  }
21647
0
  return false;
21648
0
}
21649
21650
0
bool isVADDSUBPS(unsigned Opcode) {
21651
0
  switch (Opcode) {
21652
0
  case VADDSUBPSYrm:
21653
0
  case VADDSUBPSYrr:
21654
0
  case VADDSUBPSrm:
21655
0
  case VADDSUBPSrr:
21656
0
    return true;
21657
0
  }
21658
0
  return false;
21659
0
}
21660
21661
0
bool isVBROADCASTI128(unsigned Opcode) {
21662
0
  return Opcode == VBROADCASTI128rm;
21663
0
}
21664
21665
0
bool isPADDUSB(unsigned Opcode) {
21666
0
  switch (Opcode) {
21667
0
  case MMX_PADDUSBrm:
21668
0
  case MMX_PADDUSBrr:
21669
0
  case PADDUSBrm:
21670
0
  case PADDUSBrr:
21671
0
    return true;
21672
0
  }
21673
0
  return false;
21674
0
}
21675
21676
0
bool isENCODEKEY128(unsigned Opcode) {
21677
0
  return Opcode == ENCODEKEY128;
21678
0
}
21679
21680
0
bool isOR(unsigned Opcode) {
21681
0
  switch (Opcode) {
21682
0
  case OR16i16:
21683
0
  case OR16mi:
21684
0
  case OR16mi8:
21685
0
  case OR16mi8_EVEX:
21686
0
  case OR16mi8_ND:
21687
0
  case OR16mi8_NF:
21688
0
  case OR16mi8_NF_ND:
21689
0
  case OR16mi_EVEX:
21690
0
  case OR16mi_ND:
21691
0
  case OR16mi_NF:
21692
0
  case OR16mi_NF_ND:
21693
0
  case OR16mr:
21694
0
  case OR16mr_EVEX:
21695
0
  case OR16mr_ND:
21696
0
  case OR16mr_NF:
21697
0
  case OR16mr_NF_ND:
21698
0
  case OR16ri:
21699
0
  case OR16ri8:
21700
0
  case OR16ri8_EVEX:
21701
0
  case OR16ri8_ND:
21702
0
  case OR16ri8_NF:
21703
0
  case OR16ri8_NF_ND:
21704
0
  case OR16ri_EVEX:
21705
0
  case OR16ri_ND:
21706
0
  case OR16ri_NF:
21707
0
  case OR16ri_NF_ND:
21708
0
  case OR16rm:
21709
0
  case OR16rm_EVEX:
21710
0
  case OR16rm_ND:
21711
0
  case OR16rm_NF:
21712
0
  case OR16rm_NF_ND:
21713
0
  case OR16rr:
21714
0
  case OR16rr_EVEX:
21715
0
  case OR16rr_EVEX_REV:
21716
0
  case OR16rr_ND:
21717
0
  case OR16rr_ND_REV:
21718
0
  case OR16rr_NF:
21719
0
  case OR16rr_NF_ND:
21720
0
  case OR16rr_NF_ND_REV:
21721
0
  case OR16rr_NF_REV:
21722
0
  case OR16rr_REV:
21723
0
  case OR32i32:
21724
0
  case OR32mi:
21725
0
  case OR32mi8:
21726
0
  case OR32mi8_EVEX:
21727
0
  case OR32mi8_ND:
21728
0
  case OR32mi8_NF:
21729
0
  case OR32mi8_NF_ND:
21730
0
  case OR32mi_EVEX:
21731
0
  case OR32mi_ND:
21732
0
  case OR32mi_NF:
21733
0
  case OR32mi_NF_ND:
21734
0
  case OR32mr:
21735
0
  case OR32mr_EVEX:
21736
0
  case OR32mr_ND:
21737
0
  case OR32mr_NF:
21738
0
  case OR32mr_NF_ND:
21739
0
  case OR32ri:
21740
0
  case OR32ri8:
21741
0
  case OR32ri8_EVEX:
21742
0
  case OR32ri8_ND:
21743
0
  case OR32ri8_NF:
21744
0
  case OR32ri8_NF_ND:
21745
0
  case OR32ri_EVEX:
21746
0
  case OR32ri_ND:
21747
0
  case OR32ri_NF:
21748
0
  case OR32ri_NF_ND:
21749
0
  case OR32rm:
21750
0
  case OR32rm_EVEX:
21751
0
  case OR32rm_ND:
21752
0
  case OR32rm_NF:
21753
0
  case OR32rm_NF_ND:
21754
0
  case OR32rr:
21755
0
  case OR32rr_EVEX:
21756
0
  case OR32rr_EVEX_REV:
21757
0
  case OR32rr_ND:
21758
0
  case OR32rr_ND_REV:
21759
0
  case OR32rr_NF:
21760
0
  case OR32rr_NF_ND:
21761
0
  case OR32rr_NF_ND_REV:
21762
0
  case OR32rr_NF_REV:
21763
0
  case OR32rr_REV:
21764
0
  case OR64i32:
21765
0
  case OR64mi32:
21766
0
  case OR64mi32_EVEX:
21767
0
  case OR64mi32_ND:
21768
0
  case OR64mi32_NF:
21769
0
  case OR64mi32_NF_ND:
21770
0
  case OR64mi8:
21771
0
  case OR64mi8_EVEX:
21772
0
  case OR64mi8_ND:
21773
0
  case OR64mi8_NF:
21774
0
  case OR64mi8_NF_ND:
21775
0
  case OR64mr:
21776
0
  case OR64mr_EVEX:
21777
0
  case OR64mr_ND:
21778
0
  case OR64mr_NF:
21779
0
  case OR64mr_NF_ND:
21780
0
  case OR64ri32:
21781
0
  case OR64ri32_EVEX:
21782
0
  case OR64ri32_ND:
21783
0
  case OR64ri32_NF:
21784
0
  case OR64ri32_NF_ND:
21785
0
  case OR64ri8:
21786
0
  case OR64ri8_EVEX:
21787
0
  case OR64ri8_ND:
21788
0
  case OR64ri8_NF:
21789
0
  case OR64ri8_NF_ND:
21790
0
  case OR64rm:
21791
0
  case OR64rm_EVEX:
21792
0
  case OR64rm_ND:
21793
0
  case OR64rm_NF:
21794
0
  case OR64rm_NF_ND:
21795
0
  case OR64rr:
21796
0
  case OR64rr_EVEX:
21797
0
  case OR64rr_EVEX_REV:
21798
0
  case OR64rr_ND:
21799
0
  case OR64rr_ND_REV:
21800
0
  case OR64rr_NF:
21801
0
  case OR64rr_NF_ND:
21802
0
  case OR64rr_NF_ND_REV:
21803
0
  case OR64rr_NF_REV:
21804
0
  case OR64rr_REV:
21805
0
  case OR8i8:
21806
0
  case OR8mi:
21807
0
  case OR8mi8:
21808
0
  case OR8mi_EVEX:
21809
0
  case OR8mi_ND:
21810
0
  case OR8mi_NF:
21811
0
  case OR8mi_NF_ND:
21812
0
  case OR8mr:
21813
0
  case OR8mr_EVEX:
21814
0
  case OR8mr_ND:
21815
0
  case OR8mr_NF:
21816
0
  case OR8mr_NF_ND:
21817
0
  case OR8ri:
21818
0
  case OR8ri8:
21819
0
  case OR8ri_EVEX:
21820
0
  case OR8ri_ND:
21821
0
  case OR8ri_NF:
21822
0
  case OR8ri_NF_ND:
21823
0
  case OR8rm:
21824
0
  case OR8rm_EVEX:
21825
0
  case OR8rm_ND:
21826
0
  case OR8rm_NF:
21827
0
  case OR8rm_NF_ND:
21828
0
  case OR8rr:
21829
0
  case OR8rr_EVEX:
21830
0
  case OR8rr_EVEX_REV:
21831
0
  case OR8rr_ND:
21832
0
  case OR8rr_ND_REV:
21833
0
  case OR8rr_NF:
21834
0
  case OR8rr_NF_ND:
21835
0
  case OR8rr_NF_ND_REV:
21836
0
  case OR8rr_NF_REV:
21837
0
  case OR8rr_REV:
21838
0
    return true;
21839
0
  }
21840
0
  return false;
21841
0
}
21842
21843
0
bool isSTOSW(unsigned Opcode) {
21844
0
  return Opcode == STOSW;
21845
0
}
21846
21847
0
bool isPAVGW(unsigned Opcode) {
21848
0
  switch (Opcode) {
21849
0
  case MMX_PAVGWrm:
21850
0
  case MMX_PAVGWrr:
21851
0
  case PAVGWrm:
21852
0
  case PAVGWrr:
21853
0
    return true;
21854
0
  }
21855
0
  return false;
21856
0
}
21857
21858
0
bool isVCVTPD2PH(unsigned Opcode) {
21859
0
  switch (Opcode) {
21860
0
  case VCVTPD2PHZ128rm:
21861
0
  case VCVTPD2PHZ128rmb:
21862
0
  case VCVTPD2PHZ128rmbk:
21863
0
  case VCVTPD2PHZ128rmbkz:
21864
0
  case VCVTPD2PHZ128rmk:
21865
0
  case VCVTPD2PHZ128rmkz:
21866
0
  case VCVTPD2PHZ128rr:
21867
0
  case VCVTPD2PHZ128rrk:
21868
0
  case VCVTPD2PHZ128rrkz:
21869
0
  case VCVTPD2PHZ256rm:
21870
0
  case VCVTPD2PHZ256rmb:
21871
0
  case VCVTPD2PHZ256rmbk:
21872
0
  case VCVTPD2PHZ256rmbkz:
21873
0
  case VCVTPD2PHZ256rmk:
21874
0
  case VCVTPD2PHZ256rmkz:
21875
0
  case VCVTPD2PHZ256rr:
21876
0
  case VCVTPD2PHZ256rrk:
21877
0
  case VCVTPD2PHZ256rrkz:
21878
0
  case VCVTPD2PHZrm:
21879
0
  case VCVTPD2PHZrmb:
21880
0
  case VCVTPD2PHZrmbk:
21881
0
  case VCVTPD2PHZrmbkz:
21882
0
  case VCVTPD2PHZrmk:
21883
0
  case VCVTPD2PHZrmkz:
21884
0
  case VCVTPD2PHZrr:
21885
0
  case VCVTPD2PHZrrb:
21886
0
  case VCVTPD2PHZrrbk:
21887
0
  case VCVTPD2PHZrrbkz:
21888
0
  case VCVTPD2PHZrrk:
21889
0
  case VCVTPD2PHZrrkz:
21890
0
    return true;
21891
0
  }
21892
0
  return false;
21893
0
}
21894
21895
0
bool isSHLX(unsigned Opcode) {
21896
0
  switch (Opcode) {
21897
0
  case SHLX32rm:
21898
0
  case SHLX32rm_EVEX:
21899
0
  case SHLX32rr:
21900
0
  case SHLX32rr_EVEX:
21901
0
  case SHLX64rm:
21902
0
  case SHLX64rm_EVEX:
21903
0
  case SHLX64rr:
21904
0
  case SHLX64rr_EVEX:
21905
0
    return true;
21906
0
  }
21907
0
  return false;
21908
0
}
21909
21910
0
bool isVCVTSH2SD(unsigned Opcode) {
21911
0
  switch (Opcode) {
21912
0
  case VCVTSH2SDZrm_Int:
21913
0
  case VCVTSH2SDZrm_Intk:
21914
0
  case VCVTSH2SDZrm_Intkz:
21915
0
  case VCVTSH2SDZrr_Int:
21916
0
  case VCVTSH2SDZrr_Intk:
21917
0
  case VCVTSH2SDZrr_Intkz:
21918
0
  case VCVTSH2SDZrrb_Int:
21919
0
  case VCVTSH2SDZrrb_Intk:
21920
0
  case VCVTSH2SDZrrb_Intkz:
21921
0
    return true;
21922
0
  }
21923
0
  return false;
21924
0
}
21925
21926
0
bool isVFMADD231SS(unsigned Opcode) {
21927
0
  switch (Opcode) {
21928
0
  case VFMADD231SSZm_Int:
21929
0
  case VFMADD231SSZm_Intk:
21930
0
  case VFMADD231SSZm_Intkz:
21931
0
  case VFMADD231SSZr_Int:
21932
0
  case VFMADD231SSZr_Intk:
21933
0
  case VFMADD231SSZr_Intkz:
21934
0
  case VFMADD231SSZrb_Int:
21935
0
  case VFMADD231SSZrb_Intk:
21936
0
  case VFMADD231SSZrb_Intkz:
21937
0
  case VFMADD231SSm_Int:
21938
0
  case VFMADD231SSr_Int:
21939
0
    return true;
21940
0
  }
21941
0
  return false;
21942
0
}
21943
21944
0
bool isMOVNTSD(unsigned Opcode) {
21945
0
  return Opcode == MOVNTSD;
21946
0
}
21947
21948
0
bool isFLDPI(unsigned Opcode) {
21949
0
  return Opcode == FLDPI;
21950
0
}
21951
21952
0
bool isVCVTUSI2SS(unsigned Opcode) {
21953
0
  switch (Opcode) {
21954
0
  case VCVTUSI2SSZrm_Int:
21955
0
  case VCVTUSI2SSZrr_Int:
21956
0
  case VCVTUSI2SSZrrb_Int:
21957
0
  case VCVTUSI642SSZrm_Int:
21958
0
  case VCVTUSI642SSZrr_Int:
21959
0
  case VCVTUSI642SSZrrb_Int:
21960
0
    return true;
21961
0
  }
21962
0
  return false;
21963
0
}
21964
21965
0
bool isPMOVSXBD(unsigned Opcode) {
21966
0
  switch (Opcode) {
21967
0
  case PMOVSXBDrm:
21968
0
  case PMOVSXBDrr:
21969
0
    return true;
21970
0
  }
21971
0
  return false;
21972
0
}
21973
21974
0
bool isVPRORVQ(unsigned Opcode) {
21975
0
  switch (Opcode) {
21976
0
  case VPRORVQZ128rm:
21977
0
  case VPRORVQZ128rmb:
21978
0
  case VPRORVQZ128rmbk:
21979
0
  case VPRORVQZ128rmbkz:
21980
0
  case VPRORVQZ128rmk:
21981
0
  case VPRORVQZ128rmkz:
21982
0
  case VPRORVQZ128rr:
21983
0
  case VPRORVQZ128rrk:
21984
0
  case VPRORVQZ128rrkz:
21985
0
  case VPRORVQZ256rm:
21986
0
  case VPRORVQZ256rmb:
21987
0
  case VPRORVQZ256rmbk:
21988
0
  case VPRORVQZ256rmbkz:
21989
0
  case VPRORVQZ256rmk:
21990
0
  case VPRORVQZ256rmkz:
21991
0
  case VPRORVQZ256rr:
21992
0
  case VPRORVQZ256rrk:
21993
0
  case VPRORVQZ256rrkz:
21994
0
  case VPRORVQZrm:
21995
0
  case VPRORVQZrmb:
21996
0
  case VPRORVQZrmbk:
21997
0
  case VPRORVQZrmbkz:
21998
0
  case VPRORVQZrmk:
21999
0
  case VPRORVQZrmkz:
22000
0
  case VPRORVQZrr:
22001
0
  case VPRORVQZrrk:
22002
0
  case VPRORVQZrrkz:
22003
0
    return true;
22004
0
  }
22005
0
  return false;
22006
0
}
22007
22008
0
bool isVPERMT2D(unsigned Opcode) {
22009
0
  switch (Opcode) {
22010
0
  case VPERMT2DZ128rm:
22011
0
  case VPERMT2DZ128rmb:
22012
0
  case VPERMT2DZ128rmbk:
22013
0
  case VPERMT2DZ128rmbkz:
22014
0
  case VPERMT2DZ128rmk:
22015
0
  case VPERMT2DZ128rmkz:
22016
0
  case VPERMT2DZ128rr:
22017
0
  case VPERMT2DZ128rrk:
22018
0
  case VPERMT2DZ128rrkz:
22019
0
  case VPERMT2DZ256rm:
22020
0
  case VPERMT2DZ256rmb:
22021
0
  case VPERMT2DZ256rmbk:
22022
0
  case VPERMT2DZ256rmbkz:
22023
0
  case VPERMT2DZ256rmk:
22024
0
  case VPERMT2DZ256rmkz:
22025
0
  case VPERMT2DZ256rr:
22026
0
  case VPERMT2DZ256rrk:
22027
0
  case VPERMT2DZ256rrkz:
22028
0
  case VPERMT2DZrm:
22029
0
  case VPERMT2DZrmb:
22030
0
  case VPERMT2DZrmbk:
22031
0
  case VPERMT2DZrmbkz:
22032
0
  case VPERMT2DZrmk:
22033
0
  case VPERMT2DZrmkz:
22034
0
  case VPERMT2DZrr:
22035
0
  case VPERMT2DZrrk:
22036
0
  case VPERMT2DZrrkz:
22037
0
    return true;
22038
0
  }
22039
0
  return false;
22040
0
}
22041
22042
0
bool isADDSS(unsigned Opcode) {
22043
0
  switch (Opcode) {
22044
0
  case ADDSSrm_Int:
22045
0
  case ADDSSrr_Int:
22046
0
    return true;
22047
0
  }
22048
0
  return false;
22049
0
}
22050
22051
0
bool isAADD(unsigned Opcode) {
22052
0
  switch (Opcode) {
22053
0
  case AADD32mr:
22054
0
  case AADD64mr:
22055
0
    return true;
22056
0
  }
22057
0
  return false;
22058
0
}
22059
22060
0
bool isVPSRLVW(unsigned Opcode) {
22061
0
  switch (Opcode) {
22062
0
  case VPSRLVWZ128rm:
22063
0
  case VPSRLVWZ128rmk:
22064
0
  case VPSRLVWZ128rmkz:
22065
0
  case VPSRLVWZ128rr:
22066
0
  case VPSRLVWZ128rrk:
22067
0
  case VPSRLVWZ128rrkz:
22068
0
  case VPSRLVWZ256rm:
22069
0
  case VPSRLVWZ256rmk:
22070
0
  case VPSRLVWZ256rmkz:
22071
0
  case VPSRLVWZ256rr:
22072
0
  case VPSRLVWZ256rrk:
22073
0
  case VPSRLVWZ256rrkz:
22074
0
  case VPSRLVWZrm:
22075
0
  case VPSRLVWZrmk:
22076
0
  case VPSRLVWZrmkz:
22077
0
  case VPSRLVWZrr:
22078
0
  case VPSRLVWZrrk:
22079
0
  case VPSRLVWZrrkz:
22080
0
    return true;
22081
0
  }
22082
0
  return false;
22083
0
}
22084
22085
0
bool isVRSQRTPH(unsigned Opcode) {
22086
0
  switch (Opcode) {
22087
0
  case VRSQRTPHZ128m:
22088
0
  case VRSQRTPHZ128mb:
22089
0
  case VRSQRTPHZ128mbk:
22090
0
  case VRSQRTPHZ128mbkz:
22091
0
  case VRSQRTPHZ128mk:
22092
0
  case VRSQRTPHZ128mkz:
22093
0
  case VRSQRTPHZ128r:
22094
0
  case VRSQRTPHZ128rk:
22095
0
  case VRSQRTPHZ128rkz:
22096
0
  case VRSQRTPHZ256m:
22097
0
  case VRSQRTPHZ256mb:
22098
0
  case VRSQRTPHZ256mbk:
22099
0
  case VRSQRTPHZ256mbkz:
22100
0
  case VRSQRTPHZ256mk:
22101
0
  case VRSQRTPHZ256mkz:
22102
0
  case VRSQRTPHZ256r:
22103
0
  case VRSQRTPHZ256rk:
22104
0
  case VRSQRTPHZ256rkz:
22105
0
  case VRSQRTPHZm:
22106
0
  case VRSQRTPHZmb:
22107
0
  case VRSQRTPHZmbk:
22108
0
  case VRSQRTPHZmbkz:
22109
0
  case VRSQRTPHZmk:
22110
0
  case VRSQRTPHZmkz:
22111
0
  case VRSQRTPHZr:
22112
0
  case VRSQRTPHZrk:
22113
0
  case VRSQRTPHZrkz:
22114
0
    return true;
22115
0
  }
22116
0
  return false;
22117
0
}
22118
22119
0
bool isVLDDQU(unsigned Opcode) {
22120
0
  switch (Opcode) {
22121
0
  case VLDDQUYrm:
22122
0
  case VLDDQUrm:
22123
0
    return true;
22124
0
  }
22125
0
  return false;
22126
0
}
22127
22128
0
bool isKMOVD(unsigned Opcode) {
22129
0
  switch (Opcode) {
22130
0
  case KMOVDkk:
22131
0
  case KMOVDkk_EVEX:
22132
0
  case KMOVDkm:
22133
0
  case KMOVDkm_EVEX:
22134
0
  case KMOVDkr:
22135
0
  case KMOVDkr_EVEX:
22136
0
  case KMOVDmk:
22137
0
  case KMOVDmk_EVEX:
22138
0
  case KMOVDrk:
22139
0
  case KMOVDrk_EVEX:
22140
0
    return true;
22141
0
  }
22142
0
  return false;
22143
0
}
22144
22145
0
bool isENCLV(unsigned Opcode) {
22146
0
  return Opcode == ENCLV;
22147
0
}
22148
22149
0
bool isENCLU(unsigned Opcode) {
22150
0
  return Opcode == ENCLU;
22151
0
}
22152
22153
0
bool isPREFETCHT1(unsigned Opcode) {
22154
0
  return Opcode == PREFETCHT1;
22155
0
}
22156
22157
0
bool isRSQRTPS(unsigned Opcode) {
22158
0
  switch (Opcode) {
22159
0
  case RSQRTPSm:
22160
0
  case RSQRTPSr:
22161
0
    return true;
22162
0
  }
22163
0
  return false;
22164
0
}
22165
22166
0
bool isVCVTTSH2USI(unsigned Opcode) {
22167
0
  switch (Opcode) {
22168
0
  case VCVTTSH2USI64Zrm_Int:
22169
0
  case VCVTTSH2USI64Zrr_Int:
22170
0
  case VCVTTSH2USI64Zrrb_Int:
22171
0
  case VCVTTSH2USIZrm_Int:
22172
0
  case VCVTTSH2USIZrr_Int:
22173
0
  case VCVTTSH2USIZrrb_Int:
22174
0
    return true;
22175
0
  }
22176
0
  return false;
22177
0
}
22178
22179
0
bool isPADDB(unsigned Opcode) {
22180
0
  switch (Opcode) {
22181
0
  case MMX_PADDBrm:
22182
0
  case MMX_PADDBrr:
22183
0
  case PADDBrm:
22184
0
  case PADDBrr:
22185
0
    return true;
22186
0
  }
22187
0
  return false;
22188
0
}
22189
22190
0
bool isVMASKMOVDQU(unsigned Opcode) {
22191
0
  return Opcode == VMASKMOVDQU64;
22192
0
}
22193
22194
0
bool isPUNPCKLBW(unsigned Opcode) {
22195
0
  switch (Opcode) {
22196
0
  case MMX_PUNPCKLBWrm:
22197
0
  case MMX_PUNPCKLBWrr:
22198
0
  case PUNPCKLBWrm:
22199
0
  case PUNPCKLBWrr:
22200
0
    return true;
22201
0
  }
22202
0
  return false;
22203
0
}
22204
22205
0
bool isMOV(unsigned Opcode) {
22206
0
  switch (Opcode) {
22207
0
  case MOV16ao16:
22208
0
  case MOV16ao32:
22209
0
  case MOV16mi:
22210
0
  case MOV16mr:
22211
0
  case MOV16ms:
22212
0
  case MOV16o16a:
22213
0
  case MOV16o32a:
22214
0
  case MOV16ri:
22215
0
  case MOV16ri_alt:
22216
0
  case MOV16rm:
22217
0
  case MOV16rr:
22218
0
  case MOV16rr_REV:
22219
0
  case MOV16rs:
22220
0
  case MOV16sm:
22221
0
  case MOV16sr:
22222
0
  case MOV32ao16:
22223
0
  case MOV32ao32:
22224
0
  case MOV32cr:
22225
0
  case MOV32dr:
22226
0
  case MOV32mi:
22227
0
  case MOV32mr:
22228
0
  case MOV32o16a:
22229
0
  case MOV32o32a:
22230
0
  case MOV32rc:
22231
0
  case MOV32rd:
22232
0
  case MOV32ri:
22233
0
  case MOV32ri_alt:
22234
0
  case MOV32rm:
22235
0
  case MOV32rr:
22236
0
  case MOV32rr_REV:
22237
0
  case MOV32rs:
22238
0
  case MOV32sr:
22239
0
  case MOV64ao32:
22240
0
  case MOV64cr:
22241
0
  case MOV64dr:
22242
0
  case MOV64mi32:
22243
0
  case MOV64mr:
22244
0
  case MOV64o32a:
22245
0
  case MOV64rc:
22246
0
  case MOV64rd:
22247
0
  case MOV64ri32:
22248
0
  case MOV64rm:
22249
0
  case MOV64rr:
22250
0
  case MOV64rr_REV:
22251
0
  case MOV64rs:
22252
0
  case MOV64sr:
22253
0
  case MOV8ao16:
22254
0
  case MOV8ao32:
22255
0
  case MOV8mi:
22256
0
  case MOV8mr:
22257
0
  case MOV8o16a:
22258
0
  case MOV8o32a:
22259
0
  case MOV8ri:
22260
0
  case MOV8ri_alt:
22261
0
  case MOV8rm:
22262
0
  case MOV8rr:
22263
0
  case MOV8rr_REV:
22264
0
    return true;
22265
0
  }
22266
0
  return false;
22267
0
}
22268
22269
0
bool isMUL(unsigned Opcode) {
22270
0
  switch (Opcode) {
22271
0
  case MUL16m:
22272
0
  case MUL16m_EVEX:
22273
0
  case MUL16m_NF:
22274
0
  case MUL16r:
22275
0
  case MUL16r_EVEX:
22276
0
  case MUL16r_NF:
22277
0
  case MUL32m:
22278
0
  case MUL32m_EVEX:
22279
0
  case MUL32m_NF:
22280
0
  case MUL32r:
22281
0
  case MUL32r_EVEX:
22282
0
  case MUL32r_NF:
22283
0
  case MUL64m:
22284
0
  case MUL64m_EVEX:
22285
0
  case MUL64m_NF:
22286
0
  case MUL64r:
22287
0
  case MUL64r_EVEX:
22288
0
  case MUL64r_NF:
22289
0
  case MUL8m:
22290
0
  case MUL8m_EVEX:
22291
0
  case MUL8m_NF:
22292
0
  case MUL8r:
22293
0
  case MUL8r_EVEX:
22294
0
  case MUL8r_NF:
22295
0
    return true;
22296
0
  }
22297
0
  return false;
22298
0
}
22299
22300
0
bool isRCL(unsigned Opcode) {
22301
0
  switch (Opcode) {
22302
0
  case RCL16m1:
22303
0
  case RCL16mCL:
22304
0
  case RCL16mi:
22305
0
  case RCL16r1:
22306
0
  case RCL16rCL:
22307
0
  case RCL16ri:
22308
0
  case RCL32m1:
22309
0
  case RCL32mCL:
22310
0
  case RCL32mi:
22311
0
  case RCL32r1:
22312
0
  case RCL32rCL:
22313
0
  case RCL32ri:
22314
0
  case RCL64m1:
22315
0
  case RCL64mCL:
22316
0
  case RCL64mi:
22317
0
  case RCL64r1:
22318
0
  case RCL64rCL:
22319
0
  case RCL64ri:
22320
0
  case RCL8m1:
22321
0
  case RCL8mCL:
22322
0
  case RCL8mi:
22323
0
  case RCL8r1:
22324
0
  case RCL8rCL:
22325
0
  case RCL8ri:
22326
0
    return true;
22327
0
  }
22328
0
  return false;
22329
0
}
22330
22331
0
bool isVRCPSH(unsigned Opcode) {
22332
0
  switch (Opcode) {
22333
0
  case VRCPSHZrm:
22334
0
  case VRCPSHZrmk:
22335
0
  case VRCPSHZrmkz:
22336
0
  case VRCPSHZrr:
22337
0
  case VRCPSHZrrk:
22338
0
  case VRCPSHZrrkz:
22339
0
    return true;
22340
0
  }
22341
0
  return false;
22342
0
}
22343
22344
0
bool isPFCMPEQ(unsigned Opcode) {
22345
0
  switch (Opcode) {
22346
0
  case PFCMPEQrm:
22347
0
  case PFCMPEQrr:
22348
0
    return true;
22349
0
  }
22350
0
  return false;
22351
0
}
22352
22353
0
bool isMONITOR(unsigned Opcode) {
22354
0
  switch (Opcode) {
22355
0
  case MONITOR32rrr:
22356
0
  case MONITOR64rrr:
22357
0
    return true;
22358
0
  }
22359
0
  return false;
22360
0
}
22361
22362
0
bool isFDIVR(unsigned Opcode) {
22363
0
  switch (Opcode) {
22364
0
  case DIVR_F32m:
22365
0
  case DIVR_F64m:
22366
0
  case DIVR_FST0r:
22367
0
  case DIVR_FrST0:
22368
0
    return true;
22369
0
  }
22370
0
  return false;
22371
0
}
22372
22373
0
bool isPMINSD(unsigned Opcode) {
22374
0
  switch (Opcode) {
22375
0
  case PMINSDrm:
22376
0
  case PMINSDrr:
22377
0
    return true;
22378
0
  }
22379
0
  return false;
22380
0
}
22381
22382
0
bool isPFRCP(unsigned Opcode) {
22383
0
  switch (Opcode) {
22384
0
  case PFRCPrm:
22385
0
  case PFRCPrr:
22386
0
    return true;
22387
0
  }
22388
0
  return false;
22389
0
}
22390
22391
0
bool isKTESTQ(unsigned Opcode) {
22392
0
  return Opcode == KTESTQrr;
22393
0
}
22394
22395
0
bool isVCVTTPD2DQ(unsigned Opcode) {
22396
0
  switch (Opcode) {
22397
0
  case VCVTTPD2DQYrm:
22398
0
  case VCVTTPD2DQYrr:
22399
0
  case VCVTTPD2DQZ128rm:
22400
0
  case VCVTTPD2DQZ128rmb:
22401
0
  case VCVTTPD2DQZ128rmbk:
22402
0
  case VCVTTPD2DQZ128rmbkz:
22403
0
  case VCVTTPD2DQZ128rmk:
22404
0
  case VCVTTPD2DQZ128rmkz:
22405
0
  case VCVTTPD2DQZ128rr:
22406
0
  case VCVTTPD2DQZ128rrk:
22407
0
  case VCVTTPD2DQZ128rrkz:
22408
0
  case VCVTTPD2DQZ256rm:
22409
0
  case VCVTTPD2DQZ256rmb:
22410
0
  case VCVTTPD2DQZ256rmbk:
22411
0
  case VCVTTPD2DQZ256rmbkz:
22412
0
  case VCVTTPD2DQZ256rmk:
22413
0
  case VCVTTPD2DQZ256rmkz:
22414
0
  case VCVTTPD2DQZ256rr:
22415
0
  case VCVTTPD2DQZ256rrk:
22416
0
  case VCVTTPD2DQZ256rrkz:
22417
0
  case VCVTTPD2DQZrm:
22418
0
  case VCVTTPD2DQZrmb:
22419
0
  case VCVTTPD2DQZrmbk:
22420
0
  case VCVTTPD2DQZrmbkz:
22421
0
  case VCVTTPD2DQZrmk:
22422
0
  case VCVTTPD2DQZrmkz:
22423
0
  case VCVTTPD2DQZrr:
22424
0
  case VCVTTPD2DQZrrb:
22425
0
  case VCVTTPD2DQZrrbk:
22426
0
  case VCVTTPD2DQZrrbkz:
22427
0
  case VCVTTPD2DQZrrk:
22428
0
  case VCVTTPD2DQZrrkz:
22429
0
  case VCVTTPD2DQrm:
22430
0
  case VCVTTPD2DQrr:
22431
0
    return true;
22432
0
  }
22433
0
  return false;
22434
0
}
22435
22436
0
bool isVSHUFF32X4(unsigned Opcode) {
22437
0
  switch (Opcode) {
22438
0
  case VSHUFF32X4Z256rmbi:
22439
0
  case VSHUFF32X4Z256rmbik:
22440
0
  case VSHUFF32X4Z256rmbikz:
22441
0
  case VSHUFF32X4Z256rmi:
22442
0
  case VSHUFF32X4Z256rmik:
22443
0
  case VSHUFF32X4Z256rmikz:
22444
0
  case VSHUFF32X4Z256rri:
22445
0
  case VSHUFF32X4Z256rrik:
22446
0
  case VSHUFF32X4Z256rrikz:
22447
0
  case VSHUFF32X4Zrmbi:
22448
0
  case VSHUFF32X4Zrmbik:
22449
0
  case VSHUFF32X4Zrmbikz:
22450
0
  case VSHUFF32X4Zrmi:
22451
0
  case VSHUFF32X4Zrmik:
22452
0
  case VSHUFF32X4Zrmikz:
22453
0
  case VSHUFF32X4Zrri:
22454
0
  case VSHUFF32X4Zrrik:
22455
0
  case VSHUFF32X4Zrrikz:
22456
0
    return true;
22457
0
  }
22458
0
  return false;
22459
0
}
22460
22461
0
bool isVPSLLVW(unsigned Opcode) {
22462
0
  switch (Opcode) {
22463
0
  case VPSLLVWZ128rm:
22464
0
  case VPSLLVWZ128rmk:
22465
0
  case VPSLLVWZ128rmkz:
22466
0
  case VPSLLVWZ128rr:
22467
0
  case VPSLLVWZ128rrk:
22468
0
  case VPSLLVWZ128rrkz:
22469
0
  case VPSLLVWZ256rm:
22470
0
  case VPSLLVWZ256rmk:
22471
0
  case VPSLLVWZ256rmkz:
22472
0
  case VPSLLVWZ256rr:
22473
0
  case VPSLLVWZ256rrk:
22474
0
  case VPSLLVWZ256rrkz:
22475
0
  case VPSLLVWZrm:
22476
0
  case VPSLLVWZrmk:
22477
0
  case VPSLLVWZrmkz:
22478
0
  case VPSLLVWZrr:
22479
0
  case VPSLLVWZrrk:
22480
0
  case VPSLLVWZrrkz:
22481
0
    return true;
22482
0
  }
22483
0
  return false;
22484
0
}
22485
22486
0
bool isTDPBSUD(unsigned Opcode) {
22487
0
  return Opcode == TDPBSUD;
22488
0
}
22489
22490
0
bool isVPMINUQ(unsigned Opcode) {
22491
0
  switch (Opcode) {
22492
0
  case VPMINUQZ128rm:
22493
0
  case VPMINUQZ128rmb:
22494
0
  case VPMINUQZ128rmbk:
22495
0
  case VPMINUQZ128rmbkz:
22496
0
  case VPMINUQZ128rmk:
22497
0
  case VPMINUQZ128rmkz:
22498
0
  case VPMINUQZ128rr:
22499
0
  case VPMINUQZ128rrk:
22500
0
  case VPMINUQZ128rrkz:
22501
0
  case VPMINUQZ256rm:
22502
0
  case VPMINUQZ256rmb:
22503
0
  case VPMINUQZ256rmbk:
22504
0
  case VPMINUQZ256rmbkz:
22505
0
  case VPMINUQZ256rmk:
22506
0
  case VPMINUQZ256rmkz:
22507
0
  case VPMINUQZ256rr:
22508
0
  case VPMINUQZ256rrk:
22509
0
  case VPMINUQZ256rrkz:
22510
0
  case VPMINUQZrm:
22511
0
  case VPMINUQZrmb:
22512
0
  case VPMINUQZrmbk:
22513
0
  case VPMINUQZrmbkz:
22514
0
  case VPMINUQZrmk:
22515
0
  case VPMINUQZrmkz:
22516
0
  case VPMINUQZrr:
22517
0
  case VPMINUQZrrk:
22518
0
  case VPMINUQZrrkz:
22519
0
    return true;
22520
0
  }
22521
0
  return false;
22522
0
}
22523
22524
0
bool isFIADD(unsigned Opcode) {
22525
0
  switch (Opcode) {
22526
0
  case ADD_FI16m:
22527
0
  case ADD_FI32m:
22528
0
    return true;
22529
0
  }
22530
0
  return false;
22531
0
}
22532
22533
0
bool isFCMOVNU(unsigned Opcode) {
22534
0
  return Opcode == CMOVNP_F;
22535
0
}
22536
22537
0
bool isVHSUBPD(unsigned Opcode) {
22538
0
  switch (Opcode) {
22539
0
  case VHSUBPDYrm:
22540
0
  case VHSUBPDYrr:
22541
0
  case VHSUBPDrm:
22542
0
  case VHSUBPDrr:
22543
0
    return true;
22544
0
  }
22545
0
  return false;
22546
0
}
22547
22548
0
bool isKSHIFTRQ(unsigned Opcode) {
22549
0
  return Opcode == KSHIFTRQri;
22550
0
}
22551
22552
0
bool isMOVUPS(unsigned Opcode) {
22553
0
  switch (Opcode) {
22554
0
  case MOVUPSmr:
22555
0
  case MOVUPSrm:
22556
0
  case MOVUPSrr:
22557
0
  case MOVUPSrr_REV:
22558
0
    return true;
22559
0
  }
22560
0
  return false;
22561
0
}
22562
22563
0
bool isVMCALL(unsigned Opcode) {
22564
0
  return Opcode == VMCALL;
22565
0
}
22566
22567
0
bool isXADD(unsigned Opcode) {
22568
0
  switch (Opcode) {
22569
0
  case XADD16rm:
22570
0
  case XADD16rr:
22571
0
  case XADD32rm:
22572
0
  case XADD32rr:
22573
0
  case XADD64rm:
22574
0
  case XADD64rr:
22575
0
  case XADD8rm:
22576
0
  case XADD8rr:
22577
0
    return true;
22578
0
  }
22579
0
  return false;
22580
0
}
22581
22582
0
bool isXRSTOR(unsigned Opcode) {
22583
0
  return Opcode == XRSTOR;
22584
0
}
22585
22586
0
bool isVGATHERPF1DPD(unsigned Opcode) {
22587
0
  return Opcode == VGATHERPF1DPDm;
22588
0
}
22589
22590
0
bool isRCR(unsigned Opcode) {
22591
0
  switch (Opcode) {
22592
0
  case RCR16m1:
22593
0
  case RCR16mCL:
22594
0
  case RCR16mi:
22595
0
  case RCR16r1:
22596
0
  case RCR16rCL:
22597
0
  case RCR16ri:
22598
0
  case RCR32m1:
22599
0
  case RCR32mCL:
22600
0
  case RCR32mi:
22601
0
  case RCR32r1:
22602
0
  case RCR32rCL:
22603
0
  case RCR32ri:
22604
0
  case RCR64m1:
22605
0
  case RCR64mCL:
22606
0
  case RCR64mi:
22607
0
  case RCR64r1:
22608
0
  case RCR64rCL:
22609
0
  case RCR64ri:
22610
0
  case RCR8m1:
22611
0
  case RCR8mCL:
22612
0
  case RCR8mi:
22613
0
  case RCR8r1:
22614
0
  case RCR8rCL:
22615
0
  case RCR8ri:
22616
0
    return true;
22617
0
  }
22618
0
  return false;
22619
0
}
22620
22621
0
bool isFNSTCW(unsigned Opcode) {
22622
0
  return Opcode == FNSTCW16m;
22623
0
}
22624
22625
0
bool isVPMOVSDW(unsigned Opcode) {
22626
0
  switch (Opcode) {
22627
0
  case VPMOVSDWZ128mr:
22628
0
  case VPMOVSDWZ128mrk:
22629
0
  case VPMOVSDWZ128rr:
22630
0
  case VPMOVSDWZ128rrk:
22631
0
  case VPMOVSDWZ128rrkz:
22632
0
  case VPMOVSDWZ256mr:
22633
0
  case VPMOVSDWZ256mrk:
22634
0
  case VPMOVSDWZ256rr:
22635
0
  case VPMOVSDWZ256rrk:
22636
0
  case VPMOVSDWZ256rrkz:
22637
0
  case VPMOVSDWZmr:
22638
0
  case VPMOVSDWZmrk:
22639
0
  case VPMOVSDWZrr:
22640
0
  case VPMOVSDWZrrk:
22641
0
  case VPMOVSDWZrrkz:
22642
0
    return true;
22643
0
  }
22644
0
  return false;
22645
0
}
22646
22647
0
bool isVFMSUB132SH(unsigned Opcode) {
22648
0
  switch (Opcode) {
22649
0
  case VFMSUB132SHZm_Int:
22650
0
  case VFMSUB132SHZm_Intk:
22651
0
  case VFMSUB132SHZm_Intkz:
22652
0
  case VFMSUB132SHZr_Int:
22653
0
  case VFMSUB132SHZr_Intk:
22654
0
  case VFMSUB132SHZr_Intkz:
22655
0
  case VFMSUB132SHZrb_Int:
22656
0
  case VFMSUB132SHZrb_Intk:
22657
0
  case VFMSUB132SHZrb_Intkz:
22658
0
    return true;
22659
0
  }
22660
0
  return false;
22661
0
}
22662
22663
0
bool isVPCONFLICTQ(unsigned Opcode) {
22664
0
  switch (Opcode) {
22665
0
  case VPCONFLICTQZ128rm:
22666
0
  case VPCONFLICTQZ128rmb:
22667
0
  case VPCONFLICTQZ128rmbk:
22668
0
  case VPCONFLICTQZ128rmbkz:
22669
0
  case VPCONFLICTQZ128rmk:
22670
0
  case VPCONFLICTQZ128rmkz:
22671
0
  case VPCONFLICTQZ128rr:
22672
0
  case VPCONFLICTQZ128rrk:
22673
0
  case VPCONFLICTQZ128rrkz:
22674
0
  case VPCONFLICTQZ256rm:
22675
0
  case VPCONFLICTQZ256rmb:
22676
0
  case VPCONFLICTQZ256rmbk:
22677
0
  case VPCONFLICTQZ256rmbkz:
22678
0
  case VPCONFLICTQZ256rmk:
22679
0
  case VPCONFLICTQZ256rmkz:
22680
0
  case VPCONFLICTQZ256rr:
22681
0
  case VPCONFLICTQZ256rrk:
22682
0
  case VPCONFLICTQZ256rrkz:
22683
0
  case VPCONFLICTQZrm:
22684
0
  case VPCONFLICTQZrmb:
22685
0
  case VPCONFLICTQZrmbk:
22686
0
  case VPCONFLICTQZrmbkz:
22687
0
  case VPCONFLICTQZrmk:
22688
0
  case VPCONFLICTQZrmkz:
22689
0
  case VPCONFLICTQZrr:
22690
0
  case VPCONFLICTQZrrk:
22691
0
  case VPCONFLICTQZrrkz:
22692
0
    return true;
22693
0
  }
22694
0
  return false;
22695
0
}
22696
22697
0
bool isSWAPGS(unsigned Opcode) {
22698
0
  return Opcode == SWAPGS;
22699
0
}
22700
22701
0
bool isVPMOVQ2M(unsigned Opcode) {
22702
0
  switch (Opcode) {
22703
0
  case VPMOVQ2MZ128rr:
22704
0
  case VPMOVQ2MZ256rr:
22705
0
  case VPMOVQ2MZrr:
22706
0
    return true;
22707
0
  }
22708
0
  return false;
22709
0
}
22710
22711
0
bool isVPSRAVW(unsigned Opcode) {
22712
0
  switch (Opcode) {
22713
0
  case VPSRAVWZ128rm:
22714
0
  case VPSRAVWZ128rmk:
22715
0
  case VPSRAVWZ128rmkz:
22716
0
  case VPSRAVWZ128rr:
22717
0
  case VPSRAVWZ128rrk:
22718
0
  case VPSRAVWZ128rrkz:
22719
0
  case VPSRAVWZ256rm:
22720
0
  case VPSRAVWZ256rmk:
22721
0
  case VPSRAVWZ256rmkz:
22722
0
  case VPSRAVWZ256rr:
22723
0
  case VPSRAVWZ256rrk:
22724
0
  case VPSRAVWZ256rrkz:
22725
0
  case VPSRAVWZrm:
22726
0
  case VPSRAVWZrmk:
22727
0
  case VPSRAVWZrmkz:
22728
0
  case VPSRAVWZrr:
22729
0
  case VPSRAVWZrrk:
22730
0
  case VPSRAVWZrrkz:
22731
0
    return true;
22732
0
  }
22733
0
  return false;
22734
0
}
22735
22736
0
bool isMOVDQA(unsigned Opcode) {
22737
0
  switch (Opcode) {
22738
0
  case MOVDQAmr:
22739
0
  case MOVDQArm:
22740
0
  case MOVDQArr:
22741
0
  case MOVDQArr_REV:
22742
0
    return true;
22743
0
  }
22744
0
  return false;
22745
0
}
22746
22747
0
bool isDIVSD(unsigned Opcode) {
22748
0
  switch (Opcode) {
22749
0
  case DIVSDrm_Int:
22750
0
  case DIVSDrr_Int:
22751
0
    return true;
22752
0
  }
22753
0
  return false;
22754
0
}
22755
22756
0
bool isPCMPGTB(unsigned Opcode) {
22757
0
  switch (Opcode) {
22758
0
  case MMX_PCMPGTBrm:
22759
0
  case MMX_PCMPGTBrr:
22760
0
  case PCMPGTBrm:
22761
0
  case PCMPGTBrr:
22762
0
    return true;
22763
0
  }
22764
0
  return false;
22765
0
}
22766
22767
0
bool isSHA256MSG2(unsigned Opcode) {
22768
0
  switch (Opcode) {
22769
0
  case SHA256MSG2rm:
22770
0
  case SHA256MSG2rm_EVEX:
22771
0
  case SHA256MSG2rr:
22772
0
  case SHA256MSG2rr_EVEX:
22773
0
    return true;
22774
0
  }
22775
0
  return false;
22776
0
}
22777
22778
0
bool isKXORW(unsigned Opcode) {
22779
0
  return Opcode == KXORWrr;
22780
0
}
22781
22782
0
bool isLIDTW(unsigned Opcode) {
22783
0
  return Opcode == LIDT16m;
22784
0
}
22785
22786
0
bool isPMULHW(unsigned Opcode) {
22787
0
  switch (Opcode) {
22788
0
  case MMX_PMULHWrm:
22789
0
  case MMX_PMULHWrr:
22790
0
  case PMULHWrm:
22791
0
  case PMULHWrr:
22792
0
    return true;
22793
0
  }
22794
0
  return false;
22795
0
}
22796
22797
0
bool isVAESENCLAST(unsigned Opcode) {
22798
0
  switch (Opcode) {
22799
0
  case VAESENCLASTYrm:
22800
0
  case VAESENCLASTYrr:
22801
0
  case VAESENCLASTZ128rm:
22802
0
  case VAESENCLASTZ128rr:
22803
0
  case VAESENCLASTZ256rm:
22804
0
  case VAESENCLASTZ256rr:
22805
0
  case VAESENCLASTZrm:
22806
0
  case VAESENCLASTZrr:
22807
0
  case VAESENCLASTrm:
22808
0
  case VAESENCLASTrr:
22809
0
    return true;
22810
0
  }
22811
0
  return false;
22812
0
}
22813
22814
0
bool isVINSERTI32X8(unsigned Opcode) {
22815
0
  switch (Opcode) {
22816
0
  case VINSERTI32x8Zrm:
22817
0
  case VINSERTI32x8Zrmk:
22818
0
  case VINSERTI32x8Zrmkz:
22819
0
  case VINSERTI32x8Zrr:
22820
0
  case VINSERTI32x8Zrrk:
22821
0
  case VINSERTI32x8Zrrkz:
22822
0
    return true;
22823
0
  }
22824
0
  return false;
22825
0
}
22826
22827
0
bool isVRCPPS(unsigned Opcode) {
22828
0
  switch (Opcode) {
22829
0
  case VRCPPSYm:
22830
0
  case VRCPPSYr:
22831
0
  case VRCPPSm:
22832
0
  case VRCPPSr:
22833
0
    return true;
22834
0
  }
22835
0
  return false;
22836
0
}
22837
22838
0
bool isVGATHERQPS(unsigned Opcode) {
22839
0
  switch (Opcode) {
22840
0
  case VGATHERQPSYrm:
22841
0
  case VGATHERQPSZ128rm:
22842
0
  case VGATHERQPSZ256rm:
22843
0
  case VGATHERQPSZrm:
22844
0
  case VGATHERQPSrm:
22845
0
    return true;
22846
0
  }
22847
0
  return false;
22848
0
}
22849
22850
0
bool isPMADDWD(unsigned Opcode) {
22851
0
  switch (Opcode) {
22852
0
  case MMX_PMADDWDrm:
22853
0
  case MMX_PMADDWDrr:
22854
0
  case PMADDWDrm:
22855
0
  case PMADDWDrr:
22856
0
    return true;
22857
0
  }
22858
0
  return false;
22859
0
}
22860
22861
0
bool isUCOMISS(unsigned Opcode) {
22862
0
  switch (Opcode) {
22863
0
  case UCOMISSrm:
22864
0
  case UCOMISSrr:
22865
0
    return true;
22866
0
  }
22867
0
  return false;
22868
0
}
22869
22870
0
bool isXGETBV(unsigned Opcode) {
22871
0
  return Opcode == XGETBV;
22872
0
}
22873
22874
0
bool isVCVTPD2QQ(unsigned Opcode) {
22875
0
  switch (Opcode) {
22876
0
  case VCVTPD2QQZ128rm:
22877
0
  case VCVTPD2QQZ128rmb:
22878
0
  case VCVTPD2QQZ128rmbk:
22879
0
  case VCVTPD2QQZ128rmbkz:
22880
0
  case VCVTPD2QQZ128rmk:
22881
0
  case VCVTPD2QQZ128rmkz:
22882
0
  case VCVTPD2QQZ128rr:
22883
0
  case VCVTPD2QQZ128rrk:
22884
0
  case VCVTPD2QQZ128rrkz:
22885
0
  case VCVTPD2QQZ256rm:
22886
0
  case VCVTPD2QQZ256rmb:
22887
0
  case VCVTPD2QQZ256rmbk:
22888
0
  case VCVTPD2QQZ256rmbkz:
22889
0
  case VCVTPD2QQZ256rmk:
22890
0
  case VCVTPD2QQZ256rmkz:
22891
0
  case VCVTPD2QQZ256rr:
22892
0
  case VCVTPD2QQZ256rrk:
22893
0
  case VCVTPD2QQZ256rrkz:
22894
0
  case VCVTPD2QQZrm:
22895
0
  case VCVTPD2QQZrmb:
22896
0
  case VCVTPD2QQZrmbk:
22897
0
  case VCVTPD2QQZrmbkz:
22898
0
  case VCVTPD2QQZrmk:
22899
0
  case VCVTPD2QQZrmkz:
22900
0
  case VCVTPD2QQZrr:
22901
0
  case VCVTPD2QQZrrb:
22902
0
  case VCVTPD2QQZrrbk:
22903
0
  case VCVTPD2QQZrrbkz:
22904
0
  case VCVTPD2QQZrrk:
22905
0
  case VCVTPD2QQZrrkz:
22906
0
    return true;
22907
0
  }
22908
0
  return false;
22909
0
}
22910
22911
0
bool isVGETEXPPS(unsigned Opcode) {
22912
0
  switch (Opcode) {
22913
0
  case VGETEXPPSZ128m:
22914
0
  case VGETEXPPSZ128mb:
22915
0
  case VGETEXPPSZ128mbk:
22916
0
  case VGETEXPPSZ128mbkz:
22917
0
  case VGETEXPPSZ128mk:
22918
0
  case VGETEXPPSZ128mkz:
22919
0
  case VGETEXPPSZ128r:
22920
0
  case VGETEXPPSZ128rk:
22921
0
  case VGETEXPPSZ128rkz:
22922
0
  case VGETEXPPSZ256m:
22923
0
  case VGETEXPPSZ256mb:
22924
0
  case VGETEXPPSZ256mbk:
22925
0
  case VGETEXPPSZ256mbkz:
22926
0
  case VGETEXPPSZ256mk:
22927
0
  case VGETEXPPSZ256mkz:
22928
0
  case VGETEXPPSZ256r:
22929
0
  case VGETEXPPSZ256rk:
22930
0
  case VGETEXPPSZ256rkz:
22931
0
  case VGETEXPPSZm:
22932
0
  case VGETEXPPSZmb:
22933
0
  case VGETEXPPSZmbk:
22934
0
  case VGETEXPPSZmbkz:
22935
0
  case VGETEXPPSZmk:
22936
0
  case VGETEXPPSZmkz:
22937
0
  case VGETEXPPSZr:
22938
0
  case VGETEXPPSZrb:
22939
0
  case VGETEXPPSZrbk:
22940
0
  case VGETEXPPSZrbkz:
22941
0
  case VGETEXPPSZrk:
22942
0
  case VGETEXPPSZrkz:
22943
0
    return true;
22944
0
  }
22945
0
  return false;
22946
0
}
22947
22948
0
bool isFISTP(unsigned Opcode) {
22949
0
  switch (Opcode) {
22950
0
  case IST_FP16m:
22951
0
  case IST_FP32m:
22952
0
  case IST_FP64m:
22953
0
    return true;
22954
0
  }
22955
0
  return false;
22956
0
}
22957
22958
0
bool isVINSERTF64X4(unsigned Opcode) {
22959
0
  switch (Opcode) {
22960
0
  case VINSERTF64x4Zrm:
22961
0
  case VINSERTF64x4Zrmk:
22962
0
  case VINSERTF64x4Zrmkz:
22963
0
  case VINSERTF64x4Zrr:
22964
0
  case VINSERTF64x4Zrrk:
22965
0
  case VINSERTF64x4Zrrkz:
22966
0
    return true;
22967
0
  }
22968
0
  return false;
22969
0
}
22970
22971
0
bool isVMOVDQU16(unsigned Opcode) {
22972
0
  switch (Opcode) {
22973
0
  case VMOVDQU16Z128mr:
22974
0
  case VMOVDQU16Z128mrk:
22975
0
  case VMOVDQU16Z128rm:
22976
0
  case VMOVDQU16Z128rmk:
22977
0
  case VMOVDQU16Z128rmkz:
22978
0
  case VMOVDQU16Z128rr:
22979
0
  case VMOVDQU16Z128rr_REV:
22980
0
  case VMOVDQU16Z128rrk:
22981
0
  case VMOVDQU16Z128rrk_REV:
22982
0
  case VMOVDQU16Z128rrkz:
22983
0
  case VMOVDQU16Z128rrkz_REV:
22984
0
  case VMOVDQU16Z256mr:
22985
0
  case VMOVDQU16Z256mrk:
22986
0
  case VMOVDQU16Z256rm:
22987
0
  case VMOVDQU16Z256rmk:
22988
0
  case VMOVDQU16Z256rmkz:
22989
0
  case VMOVDQU16Z256rr:
22990
0
  case VMOVDQU16Z256rr_REV:
22991
0
  case VMOVDQU16Z256rrk:
22992
0
  case VMOVDQU16Z256rrk_REV:
22993
0
  case VMOVDQU16Z256rrkz:
22994
0
  case VMOVDQU16Z256rrkz_REV:
22995
0
  case VMOVDQU16Zmr:
22996
0
  case VMOVDQU16Zmrk:
22997
0
  case VMOVDQU16Zrm:
22998
0
  case VMOVDQU16Zrmk:
22999
0
  case VMOVDQU16Zrmkz:
23000
0
  case VMOVDQU16Zrr:
23001
0
  case VMOVDQU16Zrr_REV:
23002
0
  case VMOVDQU16Zrrk:
23003
0
  case VMOVDQU16Zrrk_REV:
23004
0
  case VMOVDQU16Zrrkz:
23005
0
  case VMOVDQU16Zrrkz_REV:
23006
0
    return true;
23007
0
  }
23008
0
  return false;
23009
0
}
23010
23011
0
bool isVFMADD132PH(unsigned Opcode) {
23012
0
  switch (Opcode) {
23013
0
  case VFMADD132PHZ128m:
23014
0
  case VFMADD132PHZ128mb:
23015
0
  case VFMADD132PHZ128mbk:
23016
0
  case VFMADD132PHZ128mbkz:
23017
0
  case VFMADD132PHZ128mk:
23018
0
  case VFMADD132PHZ128mkz:
23019
0
  case VFMADD132PHZ128r:
23020
0
  case VFMADD132PHZ128rk:
23021
0
  case VFMADD132PHZ128rkz:
23022
0
  case VFMADD132PHZ256m:
23023
0
  case VFMADD132PHZ256mb:
23024
0
  case VFMADD132PHZ256mbk:
23025
0
  case VFMADD132PHZ256mbkz:
23026
0
  case VFMADD132PHZ256mk:
23027
0
  case VFMADD132PHZ256mkz:
23028
0
  case VFMADD132PHZ256r:
23029
0
  case VFMADD132PHZ256rk:
23030
0
  case VFMADD132PHZ256rkz:
23031
0
  case VFMADD132PHZm:
23032
0
  case VFMADD132PHZmb:
23033
0
  case VFMADD132PHZmbk:
23034
0
  case VFMADD132PHZmbkz:
23035
0
  case VFMADD132PHZmk:
23036
0
  case VFMADD132PHZmkz:
23037
0
  case VFMADD132PHZr:
23038
0
  case VFMADD132PHZrb:
23039
0
  case VFMADD132PHZrbk:
23040
0
  case VFMADD132PHZrbkz:
23041
0
  case VFMADD132PHZrk:
23042
0
  case VFMADD132PHZrkz:
23043
0
    return true;
23044
0
  }
23045
0
  return false;
23046
0
}
23047
23048
0
bool isVFMSUBADD213PS(unsigned Opcode) {
23049
0
  switch (Opcode) {
23050
0
  case VFMSUBADD213PSYm:
23051
0
  case VFMSUBADD213PSYr:
23052
0
  case VFMSUBADD213PSZ128m:
23053
0
  case VFMSUBADD213PSZ128mb:
23054
0
  case VFMSUBADD213PSZ128mbk:
23055
0
  case VFMSUBADD213PSZ128mbkz:
23056
0
  case VFMSUBADD213PSZ128mk:
23057
0
  case VFMSUBADD213PSZ128mkz:
23058
0
  case VFMSUBADD213PSZ128r:
23059
0
  case VFMSUBADD213PSZ128rk:
23060
0
  case VFMSUBADD213PSZ128rkz:
23061
0
  case VFMSUBADD213PSZ256m:
23062
0
  case VFMSUBADD213PSZ256mb:
23063
0
  case VFMSUBADD213PSZ256mbk:
23064
0
  case VFMSUBADD213PSZ256mbkz:
23065
0
  case VFMSUBADD213PSZ256mk:
23066
0
  case VFMSUBADD213PSZ256mkz:
23067
0
  case VFMSUBADD213PSZ256r:
23068
0
  case VFMSUBADD213PSZ256rk:
23069
0
  case VFMSUBADD213PSZ256rkz:
23070
0
  case VFMSUBADD213PSZm:
23071
0
  case VFMSUBADD213PSZmb:
23072
0
  case VFMSUBADD213PSZmbk:
23073
0
  case VFMSUBADD213PSZmbkz:
23074
0
  case VFMSUBADD213PSZmk:
23075
0
  case VFMSUBADD213PSZmkz:
23076
0
  case VFMSUBADD213PSZr:
23077
0
  case VFMSUBADD213PSZrb:
23078
0
  case VFMSUBADD213PSZrbk:
23079
0
  case VFMSUBADD213PSZrbkz:
23080
0
  case VFMSUBADD213PSZrk:
23081
0
  case VFMSUBADD213PSZrkz:
23082
0
  case VFMSUBADD213PSm:
23083
0
  case VFMSUBADD213PSr:
23084
0
    return true;
23085
0
  }
23086
0
  return false;
23087
0
}
23088
23089
0
bool isVMOVDQU32(unsigned Opcode) {
23090
0
  switch (Opcode) {
23091
0
  case VMOVDQU32Z128mr:
23092
0
  case VMOVDQU32Z128mrk:
23093
0
  case VMOVDQU32Z128rm:
23094
0
  case VMOVDQU32Z128rmk:
23095
0
  case VMOVDQU32Z128rmkz:
23096
0
  case VMOVDQU32Z128rr:
23097
0
  case VMOVDQU32Z128rr_REV:
23098
0
  case VMOVDQU32Z128rrk:
23099
0
  case VMOVDQU32Z128rrk_REV:
23100
0
  case VMOVDQU32Z128rrkz:
23101
0
  case VMOVDQU32Z128rrkz_REV:
23102
0
  case VMOVDQU32Z256mr:
23103
0
  case VMOVDQU32Z256mrk:
23104
0
  case VMOVDQU32Z256rm:
23105
0
  case VMOVDQU32Z256rmk:
23106
0
  case VMOVDQU32Z256rmkz:
23107
0
  case VMOVDQU32Z256rr:
23108
0
  case VMOVDQU32Z256rr_REV:
23109
0
  case VMOVDQU32Z256rrk:
23110
0
  case VMOVDQU32Z256rrk_REV:
23111
0
  case VMOVDQU32Z256rrkz:
23112
0
  case VMOVDQU32Z256rrkz_REV:
23113
0
  case VMOVDQU32Zmr:
23114
0
  case VMOVDQU32Zmrk:
23115
0
  case VMOVDQU32Zrm:
23116
0
  case VMOVDQU32Zrmk:
23117
0
  case VMOVDQU32Zrmkz:
23118
0
  case VMOVDQU32Zrr:
23119
0
  case VMOVDQU32Zrr_REV:
23120
0
  case VMOVDQU32Zrrk:
23121
0
  case VMOVDQU32Zrrk_REV:
23122
0
  case VMOVDQU32Zrrkz:
23123
0
  case VMOVDQU32Zrrkz_REV:
23124
0
    return true;
23125
0
  }
23126
0
  return false;
23127
0
}
23128
23129
0
bool isFUCOM(unsigned Opcode) {
23130
0
  return Opcode == UCOM_Fr;
23131
0
}
23132
23133
0
bool isHADDPS(unsigned Opcode) {
23134
0
  switch (Opcode) {
23135
0
  case HADDPSrm:
23136
0
  case HADDPSrr:
23137
0
    return true;
23138
0
  }
23139
0
  return false;
23140
0
}
23141
23142
0
bool isCMP(unsigned Opcode) {
23143
0
  switch (Opcode) {
23144
0
  case CMP16i16:
23145
0
  case CMP16mi:
23146
0
  case CMP16mi8:
23147
0
  case CMP16mr:
23148
0
  case CMP16ri:
23149
0
  case CMP16ri8:
23150
0
  case CMP16rm:
23151
0
  case CMP16rr:
23152
0
  case CMP16rr_REV:
23153
0
  case CMP32i32:
23154
0
  case CMP32mi:
23155
0
  case CMP32mi8:
23156
0
  case CMP32mr:
23157
0
  case CMP32ri:
23158
0
  case CMP32ri8:
23159
0
  case CMP32rm:
23160
0
  case CMP32rr:
23161
0
  case CMP32rr_REV:
23162
0
  case CMP64i32:
23163
0
  case CMP64mi32:
23164
0
  case CMP64mi8:
23165
0
  case CMP64mr:
23166
0
  case CMP64ri32:
23167
0
  case CMP64ri8:
23168
0
  case CMP64rm:
23169
0
  case CMP64rr:
23170
0
  case CMP64rr_REV:
23171
0
  case CMP8i8:
23172
0
  case CMP8mi:
23173
0
  case CMP8mi8:
23174
0
  case CMP8mr:
23175
0
  case CMP8ri:
23176
0
  case CMP8ri8:
23177
0
  case CMP8rm:
23178
0
  case CMP8rr:
23179
0
  case CMP8rr_REV:
23180
0
    return true;
23181
0
  }
23182
0
  return false;
23183
0
}
23184
23185
0
bool isCVTTPS2PI(unsigned Opcode) {
23186
0
  switch (Opcode) {
23187
0
  case MMX_CVTTPS2PIrm:
23188
0
  case MMX_CVTTPS2PIrr:
23189
0
    return true;
23190
0
  }
23191
0
  return false;
23192
0
}
23193
23194
0
bool isIRETQ(unsigned Opcode) {
23195
0
  return Opcode == IRET64;
23196
0
}
23197
23198
0
bool isPF2IW(unsigned Opcode) {
23199
0
  switch (Opcode) {
23200
0
  case PF2IWrm:
23201
0
  case PF2IWrr:
23202
0
    return true;
23203
0
  }
23204
0
  return false;
23205
0
}
23206
23207
0
bool isPSHUFD(unsigned Opcode) {
23208
0
  switch (Opcode) {
23209
0
  case PSHUFDmi:
23210
0
  case PSHUFDri:
23211
0
    return true;
23212
0
  }
23213
0
  return false;
23214
0
}
23215
23216
0
bool isVDPPD(unsigned Opcode) {
23217
0
  switch (Opcode) {
23218
0
  case VDPPDrmi:
23219
0
  case VDPPDrri:
23220
0
    return true;
23221
0
  }
23222
0
  return false;
23223
0
}
23224
23225
0
bool isPSHUFHW(unsigned Opcode) {
23226
0
  switch (Opcode) {
23227
0
  case PSHUFHWmi:
23228
0
  case PSHUFHWri:
23229
0
    return true;
23230
0
  }
23231
0
  return false;
23232
0
}
23233
23234
0
bool isRMPADJUST(unsigned Opcode) {
23235
0
  return Opcode == RMPADJUST;
23236
0
}
23237
23238
0
bool isPI2FW(unsigned Opcode) {
23239
0
  switch (Opcode) {
23240
0
  case PI2FWrm:
23241
0
  case PI2FWrr:
23242
0
    return true;
23243
0
  }
23244
0
  return false;
23245
0
}
23246
23247
0
bool isVCVTTPH2QQ(unsigned Opcode) {
23248
0
  switch (Opcode) {
23249
0
  case VCVTTPH2QQZ128rm:
23250
0
  case VCVTTPH2QQZ128rmb:
23251
0
  case VCVTTPH2QQZ128rmbk:
23252
0
  case VCVTTPH2QQZ128rmbkz:
23253
0
  case VCVTTPH2QQZ128rmk:
23254
0
  case VCVTTPH2QQZ128rmkz:
23255
0
  case VCVTTPH2QQZ128rr:
23256
0
  case VCVTTPH2QQZ128rrk:
23257
0
  case VCVTTPH2QQZ128rrkz:
23258
0
  case VCVTTPH2QQZ256rm:
23259
0
  case VCVTTPH2QQZ256rmb:
23260
0
  case VCVTTPH2QQZ256rmbk:
23261
0
  case VCVTTPH2QQZ256rmbkz:
23262
0
  case VCVTTPH2QQZ256rmk:
23263
0
  case VCVTTPH2QQZ256rmkz:
23264
0
  case VCVTTPH2QQZ256rr:
23265
0
  case VCVTTPH2QQZ256rrk:
23266
0
  case VCVTTPH2QQZ256rrkz:
23267
0
  case VCVTTPH2QQZrm:
23268
0
  case VCVTTPH2QQZrmb:
23269
0
  case VCVTTPH2QQZrmbk:
23270
0
  case VCVTTPH2QQZrmbkz:
23271
0
  case VCVTTPH2QQZrmk:
23272
0
  case VCVTTPH2QQZrmkz:
23273
0
  case VCVTTPH2QQZrr:
23274
0
  case VCVTTPH2QQZrrb:
23275
0
  case VCVTTPH2QQZrrbk:
23276
0
  case VCVTTPH2QQZrrbkz:
23277
0
  case VCVTTPH2QQZrrk:
23278
0
  case VCVTTPH2QQZrrkz:
23279
0
    return true;
23280
0
  }
23281
0
  return false;
23282
0
}
23283
23284
0
bool isDIVPD(unsigned Opcode) {
23285
0
  switch (Opcode) {
23286
0
  case DIVPDrm:
23287
0
  case DIVPDrr:
23288
0
    return true;
23289
0
  }
23290
0
  return false;
23291
0
}
23292
23293
0
bool isCLFLUSH(unsigned Opcode) {
23294
0
  return Opcode == CLFLUSH;
23295
0
}
23296
23297
0
bool isVPMINUW(unsigned Opcode) {
23298
0
  switch (Opcode) {
23299
0
  case VPMINUWYrm:
23300
0
  case VPMINUWYrr:
23301
0
  case VPMINUWZ128rm:
23302
0
  case VPMINUWZ128rmk:
23303
0
  case VPMINUWZ128rmkz:
23304
0
  case VPMINUWZ128rr:
23305
0
  case VPMINUWZ128rrk:
23306
0
  case VPMINUWZ128rrkz:
23307
0
  case VPMINUWZ256rm:
23308
0
  case VPMINUWZ256rmk:
23309
0
  case VPMINUWZ256rmkz:
23310
0
  case VPMINUWZ256rr:
23311
0
  case VPMINUWZ256rrk:
23312
0
  case VPMINUWZ256rrkz:
23313
0
  case VPMINUWZrm:
23314
0
  case VPMINUWZrmk:
23315
0
  case VPMINUWZrmkz:
23316
0
  case VPMINUWZrr:
23317
0
  case VPMINUWZrrk:
23318
0
  case VPMINUWZrrkz:
23319
0
  case VPMINUWrm:
23320
0
  case VPMINUWrr:
23321
0
    return true;
23322
0
  }
23323
0
  return false;
23324
0
}
23325
23326
0
bool isIN(unsigned Opcode) {
23327
0
  switch (Opcode) {
23328
0
  case IN16ri:
23329
0
  case IN16rr:
23330
0
  case IN32ri:
23331
0
  case IN32rr:
23332
0
  case IN8ri:
23333
0
  case IN8rr:
23334
0
    return true;
23335
0
  }
23336
0
  return false;
23337
0
}
23338
23339
0
bool isWRPKRU(unsigned Opcode) {
23340
0
  return Opcode == WRPKRUr;
23341
0
}
23342
23343
0
bool isINSERTPS(unsigned Opcode) {
23344
0
  switch (Opcode) {
23345
0
  case INSERTPSrm:
23346
0
  case INSERTPSrr:
23347
0
    return true;
23348
0
  }
23349
0
  return false;
23350
0
}
23351
23352
0
bool isAAM(unsigned Opcode) {
23353
0
  return Opcode == AAM8i8;
23354
0
}
23355
23356
0
bool isVPHADDUDQ(unsigned Opcode) {
23357
0
  switch (Opcode) {
23358
0
  case VPHADDUDQrm:
23359
0
  case VPHADDUDQrr:
23360
0
    return true;
23361
0
  }
23362
0
  return false;
23363
0
}
23364
23365
0
bool isVSHA512MSG1(unsigned Opcode) {
23366
0
  return Opcode == VSHA512MSG1rr;
23367
0
}
23368
23369
0
bool isDIVPS(unsigned Opcode) {
23370
0
  switch (Opcode) {
23371
0
  case DIVPSrm:
23372
0
  case DIVPSrr:
23373
0
    return true;
23374
0
  }
23375
0
  return false;
23376
0
}
23377
23378
0
bool isKNOTB(unsigned Opcode) {
23379
0
  return Opcode == KNOTBrr;
23380
0
}
23381
23382
0
bool isBLSFILL(unsigned Opcode) {
23383
0
  switch (Opcode) {
23384
0
  case BLSFILL32rm:
23385
0
  case BLSFILL32rr:
23386
0
  case BLSFILL64rm:
23387
0
  case BLSFILL64rr:
23388
0
    return true;
23389
0
  }
23390
0
  return false;
23391
0
}
23392
23393
0
bool isVPCMPGTQ(unsigned Opcode) {
23394
0
  switch (Opcode) {
23395
0
  case VPCMPGTQYrm:
23396
0
  case VPCMPGTQYrr:
23397
0
  case VPCMPGTQZ128rm:
23398
0
  case VPCMPGTQZ128rmb:
23399
0
  case VPCMPGTQZ128rmbk:
23400
0
  case VPCMPGTQZ128rmk:
23401
0
  case VPCMPGTQZ128rr:
23402
0
  case VPCMPGTQZ128rrk:
23403
0
  case VPCMPGTQZ256rm:
23404
0
  case VPCMPGTQZ256rmb:
23405
0
  case VPCMPGTQZ256rmbk:
23406
0
  case VPCMPGTQZ256rmk:
23407
0
  case VPCMPGTQZ256rr:
23408
0
  case VPCMPGTQZ256rrk:
23409
0
  case VPCMPGTQZrm:
23410
0
  case VPCMPGTQZrmb:
23411
0
  case VPCMPGTQZrmbk:
23412
0
  case VPCMPGTQZrmk:
23413
0
  case VPCMPGTQZrr:
23414
0
  case VPCMPGTQZrrk:
23415
0
  case VPCMPGTQrm:
23416
0
  case VPCMPGTQrr:
23417
0
    return true;
23418
0
  }
23419
0
  return false;
23420
0
}
23421
23422
0
bool isMINSD(unsigned Opcode) {
23423
0
  switch (Opcode) {
23424
0
  case MINSDrm_Int:
23425
0
  case MINSDrr_Int:
23426
0
    return true;
23427
0
  }
23428
0
  return false;
23429
0
}
23430
23431
0
bool isFPREM(unsigned Opcode) {
23432
0
  return Opcode == FPREM;
23433
0
}
23434
23435
0
bool isVPUNPCKHQDQ(unsigned Opcode) {
23436
0
  switch (Opcode) {
23437
0
  case VPUNPCKHQDQYrm:
23438
0
  case VPUNPCKHQDQYrr:
23439
0
  case VPUNPCKHQDQZ128rm:
23440
0
  case VPUNPCKHQDQZ128rmb:
23441
0
  case VPUNPCKHQDQZ128rmbk:
23442
0
  case VPUNPCKHQDQZ128rmbkz:
23443
0
  case VPUNPCKHQDQZ128rmk:
23444
0
  case VPUNPCKHQDQZ128rmkz:
23445
0
  case VPUNPCKHQDQZ128rr:
23446
0
  case VPUNPCKHQDQZ128rrk:
23447
0
  case VPUNPCKHQDQZ128rrkz:
23448
0
  case VPUNPCKHQDQZ256rm:
23449
0
  case VPUNPCKHQDQZ256rmb:
23450
0
  case VPUNPCKHQDQZ256rmbk:
23451
0
  case VPUNPCKHQDQZ256rmbkz:
23452
0
  case VPUNPCKHQDQZ256rmk:
23453
0
  case VPUNPCKHQDQZ256rmkz:
23454
0
  case VPUNPCKHQDQZ256rr:
23455
0
  case VPUNPCKHQDQZ256rrk:
23456
0
  case VPUNPCKHQDQZ256rrkz:
23457
0
  case VPUNPCKHQDQZrm:
23458
0
  case VPUNPCKHQDQZrmb:
23459
0
  case VPUNPCKHQDQZrmbk:
23460
0
  case VPUNPCKHQDQZrmbkz:
23461
0
  case VPUNPCKHQDQZrmk:
23462
0
  case VPUNPCKHQDQZrmkz:
23463
0
  case VPUNPCKHQDQZrr:
23464
0
  case VPUNPCKHQDQZrrk:
23465
0
  case VPUNPCKHQDQZrrkz:
23466
0
  case VPUNPCKHQDQrm:
23467
0
  case VPUNPCKHQDQrr:
23468
0
    return true;
23469
0
  }
23470
0
  return false;
23471
0
}
23472
23473
0
bool isMINPD(unsigned Opcode) {
23474
0
  switch (Opcode) {
23475
0
  case MINPDrm:
23476
0
  case MINPDrr:
23477
0
    return true;
23478
0
  }
23479
0
  return false;
23480
0
}
23481
23482
0
bool isVCVTTPD2QQ(unsigned Opcode) {
23483
0
  switch (Opcode) {
23484
0
  case VCVTTPD2QQZ128rm:
23485
0
  case VCVTTPD2QQZ128rmb:
23486
0
  case VCVTTPD2QQZ128rmbk:
23487
0
  case VCVTTPD2QQZ128rmbkz:
23488
0
  case VCVTTPD2QQZ128rmk:
23489
0
  case VCVTTPD2QQZ128rmkz:
23490
0
  case VCVTTPD2QQZ128rr:
23491
0
  case VCVTTPD2QQZ128rrk:
23492
0
  case VCVTTPD2QQZ128rrkz:
23493
0
  case VCVTTPD2QQZ256rm:
23494
0
  case VCVTTPD2QQZ256rmb:
23495
0
  case VCVTTPD2QQZ256rmbk:
23496
0
  case VCVTTPD2QQZ256rmbkz:
23497
0
  case VCVTTPD2QQZ256rmk:
23498
0
  case VCVTTPD2QQZ256rmkz:
23499
0
  case VCVTTPD2QQZ256rr:
23500
0
  case VCVTTPD2QQZ256rrk:
23501
0
  case VCVTTPD2QQZ256rrkz:
23502
0
  case VCVTTPD2QQZrm:
23503
0
  case VCVTTPD2QQZrmb:
23504
0
  case VCVTTPD2QQZrmbk:
23505
0
  case VCVTTPD2QQZrmbkz:
23506
0
  case VCVTTPD2QQZrmk:
23507
0
  case VCVTTPD2QQZrmkz:
23508
0
  case VCVTTPD2QQZrr:
23509
0
  case VCVTTPD2QQZrrb:
23510
0
  case VCVTTPD2QQZrrbk:
23511
0
  case VCVTTPD2QQZrrbkz:
23512
0
  case VCVTTPD2QQZrrk:
23513
0
  case VCVTTPD2QQZrrkz:
23514
0
    return true;
23515
0
  }
23516
0
  return false;
23517
0
}
23518
23519
0
bool isVFMSUBPD(unsigned Opcode) {
23520
0
  switch (Opcode) {
23521
0
  case VFMSUBPD4Ymr:
23522
0
  case VFMSUBPD4Yrm:
23523
0
  case VFMSUBPD4Yrr:
23524
0
  case VFMSUBPD4Yrr_REV:
23525
0
  case VFMSUBPD4mr:
23526
0
  case VFMSUBPD4rm:
23527
0
  case VFMSUBPD4rr:
23528
0
  case VFMSUBPD4rr_REV:
23529
0
    return true;
23530
0
  }
23531
0
  return false;
23532
0
}
23533
23534
0
bool isV4FMADDSS(unsigned Opcode) {
23535
0
  switch (Opcode) {
23536
0
  case V4FMADDSSrm:
23537
0
  case V4FMADDSSrmk:
23538
0
  case V4FMADDSSrmkz:
23539
0
    return true;
23540
0
  }
23541
0
  return false;
23542
0
}
23543
23544
0
bool isCPUID(unsigned Opcode) {
23545
0
  return Opcode == CPUID;
23546
0
}
23547
23548
2.57k
bool isSETCC(unsigned Opcode) {
23549
2.57k
  switch (Opcode) {
23550
63
  case SETCCm:
23551
186
  case SETCCr:
23552
186
    return true;
23553
2.57k
  }
23554
2.39k
  return false;
23555
2.57k
}
23556
23557
0
bool isVPDPWUUD(unsigned Opcode) {
23558
0
  switch (Opcode) {
23559
0
  case VPDPWUUDYrm:
23560
0
  case VPDPWUUDYrr:
23561
0
  case VPDPWUUDrm:
23562
0
  case VPDPWUUDrr:
23563
0
    return true;
23564
0
  }
23565
0
  return false;
23566
0
}
23567
23568
0
bool isPMOVSXDQ(unsigned Opcode) {
23569
0
  switch (Opcode) {
23570
0
  case PMOVSXDQrm:
23571
0
  case PMOVSXDQrr:
23572
0
    return true;
23573
0
  }
23574
0
  return false;
23575
0
}
23576
23577
0
bool isMWAIT(unsigned Opcode) {
23578
0
  return Opcode == MWAITrr;
23579
0
}
23580
23581
0
bool isVPEXTRB(unsigned Opcode) {
23582
0
  switch (Opcode) {
23583
0
  case VPEXTRBZmr:
23584
0
  case VPEXTRBZrr:
23585
0
  case VPEXTRBmr:
23586
0
  case VPEXTRBrr:
23587
0
    return true;
23588
0
  }
23589
0
  return false;
23590
0
}
23591
23592
0
bool isINVVPID(unsigned Opcode) {
23593
0
  switch (Opcode) {
23594
0
  case INVVPID32:
23595
0
  case INVVPID64:
23596
0
  case INVVPID64_EVEX:
23597
0
    return true;
23598
0
  }
23599
0
  return false;
23600
0
}
23601
23602
0
bool isVPSHUFD(unsigned Opcode) {
23603
0
  switch (Opcode) {
23604
0
  case VPSHUFDYmi:
23605
0
  case VPSHUFDYri:
23606
0
  case VPSHUFDZ128mbi:
23607
0
  case VPSHUFDZ128mbik:
23608
0
  case VPSHUFDZ128mbikz:
23609
0
  case VPSHUFDZ128mi:
23610
0
  case VPSHUFDZ128mik:
23611
0
  case VPSHUFDZ128mikz:
23612
0
  case VPSHUFDZ128ri:
23613
0
  case VPSHUFDZ128rik:
23614
0
  case VPSHUFDZ128rikz:
23615
0
  case VPSHUFDZ256mbi:
23616
0
  case VPSHUFDZ256mbik:
23617
0
  case VPSHUFDZ256mbikz:
23618
0
  case VPSHUFDZ256mi:
23619
0
  case VPSHUFDZ256mik:
23620
0
  case VPSHUFDZ256mikz:
23621
0
  case VPSHUFDZ256ri:
23622
0
  case VPSHUFDZ256rik:
23623
0
  case VPSHUFDZ256rikz:
23624
0
  case VPSHUFDZmbi:
23625
0
  case VPSHUFDZmbik:
23626
0
  case VPSHUFDZmbikz:
23627
0
  case VPSHUFDZmi:
23628
0
  case VPSHUFDZmik:
23629
0
  case VPSHUFDZmikz:
23630
0
  case VPSHUFDZri:
23631
0
  case VPSHUFDZrik:
23632
0
  case VPSHUFDZrikz:
23633
0
  case VPSHUFDmi:
23634
0
  case VPSHUFDri:
23635
0
    return true;
23636
0
  }
23637
0
  return false;
23638
0
}
23639
23640
0
bool isMOVLPS(unsigned Opcode) {
23641
0
  switch (Opcode) {
23642
0
  case MOVLPSmr:
23643
0
  case MOVLPSrm:
23644
0
    return true;
23645
0
  }
23646
0
  return false;
23647
0
}
23648
23649
0
bool isVBLENDMPS(unsigned Opcode) {
23650
0
  switch (Opcode) {
23651
0
  case VBLENDMPSZ128rm:
23652
0
  case VBLENDMPSZ128rmb:
23653
0
  case VBLENDMPSZ128rmbk:
23654
0
  case VBLENDMPSZ128rmbkz:
23655
0
  case VBLENDMPSZ128rmk:
23656
0
  case VBLENDMPSZ128rmkz:
23657
0
  case VBLENDMPSZ128rr:
23658
0
  case VBLENDMPSZ128rrk:
23659
0
  case VBLENDMPSZ128rrkz:
23660
0
  case VBLENDMPSZ256rm:
23661
0
  case VBLENDMPSZ256rmb:
23662
0
  case VBLENDMPSZ256rmbk:
23663
0
  case VBLENDMPSZ256rmbkz:
23664
0
  case VBLENDMPSZ256rmk:
23665
0
  case VBLENDMPSZ256rmkz:
23666
0
  case VBLENDMPSZ256rr:
23667
0
  case VBLENDMPSZ256rrk:
23668
0
  case VBLENDMPSZ256rrkz:
23669
0
  case VBLENDMPSZrm:
23670
0
  case VBLENDMPSZrmb:
23671
0
  case VBLENDMPSZrmbk:
23672
0
  case VBLENDMPSZrmbkz:
23673
0
  case VBLENDMPSZrmk:
23674
0
  case VBLENDMPSZrmkz:
23675
0
  case VBLENDMPSZrr:
23676
0
  case VBLENDMPSZrrk:
23677
0
  case VBLENDMPSZrrkz:
23678
0
    return true;
23679
0
  }
23680
0
  return false;
23681
0
}
23682
23683
0
bool isPMULLW(unsigned Opcode) {
23684
0
  switch (Opcode) {
23685
0
  case MMX_PMULLWrm:
23686
0
  case MMX_PMULLWrr:
23687
0
  case PMULLWrm:
23688
0
  case PMULLWrr:
23689
0
    return true;
23690
0
  }
23691
0
  return false;
23692
0
}
23693
23694
0
bool isVCVTSH2SI(unsigned Opcode) {
23695
0
  switch (Opcode) {
23696
0
  case VCVTSH2SI64Zrm_Int:
23697
0
  case VCVTSH2SI64Zrr_Int:
23698
0
  case VCVTSH2SI64Zrrb_Int:
23699
0
  case VCVTSH2SIZrm_Int:
23700
0
  case VCVTSH2SIZrr_Int:
23701
0
  case VCVTSH2SIZrrb_Int:
23702
0
    return true;
23703
0
  }
23704
0
  return false;
23705
0
}
23706
23707
0
bool isVPMOVSXWQ(unsigned Opcode) {
23708
0
  switch (Opcode) {
23709
0
  case VPMOVSXWQYrm:
23710
0
  case VPMOVSXWQYrr:
23711
0
  case VPMOVSXWQZ128rm:
23712
0
  case VPMOVSXWQZ128rmk:
23713
0
  case VPMOVSXWQZ128rmkz:
23714
0
  case VPMOVSXWQZ128rr:
23715
0
  case VPMOVSXWQZ128rrk:
23716
0
  case VPMOVSXWQZ128rrkz:
23717
0
  case VPMOVSXWQZ256rm:
23718
0
  case VPMOVSXWQZ256rmk:
23719
0
  case VPMOVSXWQZ256rmkz:
23720
0
  case VPMOVSXWQZ256rr:
23721
0
  case VPMOVSXWQZ256rrk:
23722
0
  case VPMOVSXWQZ256rrkz:
23723
0
  case VPMOVSXWQZrm:
23724
0
  case VPMOVSXWQZrmk:
23725
0
  case VPMOVSXWQZrmkz:
23726
0
  case VPMOVSXWQZrr:
23727
0
  case VPMOVSXWQZrrk:
23728
0
  case VPMOVSXWQZrrkz:
23729
0
  case VPMOVSXWQrm:
23730
0
  case VPMOVSXWQrr:
23731
0
    return true;
23732
0
  }
23733
0
  return false;
23734
0
}
23735
23736
0
bool isFNSTENV(unsigned Opcode) {
23737
0
  return Opcode == FSTENVm;
23738
0
}
23739
23740
0
bool isVPERMI2PD(unsigned Opcode) {
23741
0
  switch (Opcode) {
23742
0
  case VPERMI2PDZ128rm:
23743
0
  case VPERMI2PDZ128rmb:
23744
0
  case VPERMI2PDZ128rmbk:
23745
0
  case VPERMI2PDZ128rmbkz:
23746
0
  case VPERMI2PDZ128rmk:
23747
0
  case VPERMI2PDZ128rmkz:
23748
0
  case VPERMI2PDZ128rr:
23749
0
  case VPERMI2PDZ128rrk:
23750
0
  case VPERMI2PDZ128rrkz:
23751
0
  case VPERMI2PDZ256rm:
23752
0
  case VPERMI2PDZ256rmb:
23753
0
  case VPERMI2PDZ256rmbk:
23754
0
  case VPERMI2PDZ256rmbkz:
23755
0
  case VPERMI2PDZ256rmk:
23756
0
  case VPERMI2PDZ256rmkz:
23757
0
  case VPERMI2PDZ256rr:
23758
0
  case VPERMI2PDZ256rrk:
23759
0
  case VPERMI2PDZ256rrkz:
23760
0
  case VPERMI2PDZrm:
23761
0
  case VPERMI2PDZrmb:
23762
0
  case VPERMI2PDZrmbk:
23763
0
  case VPERMI2PDZrmbkz:
23764
0
  case VPERMI2PDZrmk:
23765
0
  case VPERMI2PDZrmkz:
23766
0
  case VPERMI2PDZrr:
23767
0
  case VPERMI2PDZrrk:
23768
0
  case VPERMI2PDZrrkz:
23769
0
    return true;
23770
0
  }
23771
0
  return false;
23772
0
}
23773
23774
0
bool isMAXSS(unsigned Opcode) {
23775
0
  switch (Opcode) {
23776
0
  case MAXSSrm_Int:
23777
0
  case MAXSSrr_Int:
23778
0
    return true;
23779
0
  }
23780
0
  return false;
23781
0
}
23782
23783
0
bool isCWDE(unsigned Opcode) {
23784
0
  return Opcode == CWDE;
23785
0
}
23786
23787
0
bool isVBROADCASTI32X8(unsigned Opcode) {
23788
0
  switch (Opcode) {
23789
0
  case VBROADCASTI32X8rm:
23790
0
  case VBROADCASTI32X8rmk:
23791
0
  case VBROADCASTI32X8rmkz:
23792
0
    return true;
23793
0
  }
23794
0
  return false;
23795
0
}
23796
23797
0
bool isINT(unsigned Opcode) {
23798
0
  return Opcode == INT;
23799
0
}
23800
23801
0
bool isENCLS(unsigned Opcode) {
23802
0
  return Opcode == ENCLS;
23803
0
}
23804
23805
0
bool isMOVNTQ(unsigned Opcode) {
23806
0
  return Opcode == MMX_MOVNTQmr;
23807
0
}
23808
23809
0
bool isVDIVSH(unsigned Opcode) {
23810
0
  switch (Opcode) {
23811
0
  case VDIVSHZrm_Int:
23812
0
  case VDIVSHZrm_Intk:
23813
0
  case VDIVSHZrm_Intkz:
23814
0
  case VDIVSHZrr_Int:
23815
0
  case VDIVSHZrr_Intk:
23816
0
  case VDIVSHZrr_Intkz:
23817
0
  case VDIVSHZrrb_Int:
23818
0
  case VDIVSHZrrb_Intk:
23819
0
  case VDIVSHZrrb_Intkz:
23820
0
    return true;
23821
0
  }
23822
0
  return false;
23823
0
}
23824
23825
0
bool isMOVHLPS(unsigned Opcode) {
23826
0
  return Opcode == MOVHLPSrr;
23827
0
}
23828
23829
0
bool isVPMASKMOVD(unsigned Opcode) {
23830
0
  switch (Opcode) {
23831
0
  case VPMASKMOVDYmr:
23832
0
  case VPMASKMOVDYrm:
23833
0
  case VPMASKMOVDmr:
23834
0
  case VPMASKMOVDrm:
23835
0
    return true;
23836
0
  }
23837
0
  return false;
23838
0
}
23839
23840
0
bool isVMOVSD(unsigned Opcode) {
23841
0
  switch (Opcode) {
23842
0
  case VMOVSDZmr:
23843
0
  case VMOVSDZmrk:
23844
0
  case VMOVSDZrm:
23845
0
  case VMOVSDZrmk:
23846
0
  case VMOVSDZrmkz:
23847
0
  case VMOVSDZrr:
23848
0
  case VMOVSDZrr_REV:
23849
0
  case VMOVSDZrrk:
23850
0
  case VMOVSDZrrk_REV:
23851
0
  case VMOVSDZrrkz:
23852
0
  case VMOVSDZrrkz_REV:
23853
0
  case VMOVSDmr:
23854
0
  case VMOVSDrm:
23855
0
  case VMOVSDrr:
23856
0
  case VMOVSDrr_REV:
23857
0
    return true;
23858
0
  }
23859
0
  return false;
23860
0
}
23861
23862
0
bool isVPMINUD(unsigned Opcode) {
23863
0
  switch (Opcode) {
23864
0
  case VPMINUDYrm:
23865
0
  case VPMINUDYrr:
23866
0
  case VPMINUDZ128rm:
23867
0
  case VPMINUDZ128rmb:
23868
0
  case VPMINUDZ128rmbk:
23869
0
  case VPMINUDZ128rmbkz:
23870
0
  case VPMINUDZ128rmk:
23871
0
  case VPMINUDZ128rmkz:
23872
0
  case VPMINUDZ128rr:
23873
0
  case VPMINUDZ128rrk:
23874
0
  case VPMINUDZ128rrkz:
23875
0
  case VPMINUDZ256rm:
23876
0
  case VPMINUDZ256rmb:
23877
0
  case VPMINUDZ256rmbk:
23878
0
  case VPMINUDZ256rmbkz:
23879
0
  case VPMINUDZ256rmk:
23880
0
  case VPMINUDZ256rmkz:
23881
0
  case VPMINUDZ256rr:
23882
0
  case VPMINUDZ256rrk:
23883
0
  case VPMINUDZ256rrkz:
23884
0
  case VPMINUDZrm:
23885
0
  case VPMINUDZrmb:
23886
0
  case VPMINUDZrmbk:
23887
0
  case VPMINUDZrmbkz:
23888
0
  case VPMINUDZrmk:
23889
0
  case VPMINUDZrmkz:
23890
0
  case VPMINUDZrr:
23891
0
  case VPMINUDZrrk:
23892
0
  case VPMINUDZrrkz:
23893
0
  case VPMINUDrm:
23894
0
  case VPMINUDrr:
23895
0
    return true;
23896
0
  }
23897
0
  return false;
23898
0
}
23899
23900
0
bool isVPCMPISTRM(unsigned Opcode) {
23901
0
  switch (Opcode) {
23902
0
  case VPCMPISTRMrm:
23903
0
  case VPCMPISTRMrr:
23904
0
    return true;
23905
0
  }
23906
0
  return false;
23907
0
}
23908
23909
0
bool isVGETMANTSD(unsigned Opcode) {
23910
0
  switch (Opcode) {
23911
0
  case VGETMANTSDZrmi:
23912
0
  case VGETMANTSDZrmik:
23913
0
  case VGETMANTSDZrmikz:
23914
0
  case VGETMANTSDZrri:
23915
0
  case VGETMANTSDZrrib:
23916
0
  case VGETMANTSDZrribk:
23917
0
  case VGETMANTSDZrribkz:
23918
0
  case VGETMANTSDZrrik:
23919
0
  case VGETMANTSDZrrikz:
23920
0
    return true;
23921
0
  }
23922
0
  return false;
23923
0
}
23924
23925
0
bool isKSHIFTRW(unsigned Opcode) {
23926
0
  return Opcode == KSHIFTRWri;
23927
0
}
23928
23929
0
bool isAESDECLAST(unsigned Opcode) {
23930
0
  switch (Opcode) {
23931
0
  case AESDECLASTrm:
23932
0
  case AESDECLASTrr:
23933
0
    return true;
23934
0
  }
23935
0
  return false;
23936
0
}
23937
23938
0
bool isVPTESTMB(unsigned Opcode) {
23939
0
  switch (Opcode) {
23940
0
  case VPTESTMBZ128rm:
23941
0
  case VPTESTMBZ128rmk:
23942
0
  case VPTESTMBZ128rr:
23943
0
  case VPTESTMBZ128rrk:
23944
0
  case VPTESTMBZ256rm:
23945
0
  case VPTESTMBZ256rmk:
23946
0
  case VPTESTMBZ256rr:
23947
0
  case VPTESTMBZ256rrk:
23948
0
  case VPTESTMBZrm:
23949
0
  case VPTESTMBZrmk:
23950
0
  case VPTESTMBZrr:
23951
0
  case VPTESTMBZrrk:
23952
0
    return true;
23953
0
  }
23954
0
  return false;
23955
0
}
23956
23957
0
bool isVMPTRST(unsigned Opcode) {
23958
0
  return Opcode == VMPTRSTm;
23959
0
}
23960
23961
0
bool isLLDT(unsigned Opcode) {
23962
0
  switch (Opcode) {
23963
0
  case LLDT16m:
23964
0
  case LLDT16r:
23965
0
    return true;
23966
0
  }
23967
0
  return false;
23968
0
}
23969
23970
0
bool isMOVSB(unsigned Opcode) {
23971
0
  return Opcode == MOVSB;
23972
0
}
23973
23974
0
bool isTILELOADD(unsigned Opcode) {
23975
0
  switch (Opcode) {
23976
0
  case TILELOADD:
23977
0
  case TILELOADD_EVEX:
23978
0
    return true;
23979
0
  }
23980
0
  return false;
23981
0
}
23982
23983
0
bool isKTESTB(unsigned Opcode) {
23984
0
  return Opcode == KTESTBrr;
23985
0
}
23986
23987
0
bool isMOVUPD(unsigned Opcode) {
23988
0
  switch (Opcode) {
23989
0
  case MOVUPDmr:
23990
0
  case MOVUPDrm:
23991
0
  case MOVUPDrr:
23992
0
  case MOVUPDrr_REV:
23993
0
    return true;
23994
0
  }
23995
0
  return false;
23996
0
}
23997
23998
0
bool isSGDTW(unsigned Opcode) {
23999
0
  return Opcode == SGDT16m;
24000
0
}
24001
24002
0
bool isDIVSS(unsigned Opcode) {
24003
0
  switch (Opcode) {
24004
0
  case DIVSSrm_Int:
24005
0
  case DIVSSrr_Int:
24006
0
    return true;
24007
0
  }
24008
0
  return false;
24009
0
}
24010
24011
0
bool isPUNPCKHQDQ(unsigned Opcode) {
24012
0
  switch (Opcode) {
24013
0
  case PUNPCKHQDQrm:
24014
0
  case PUNPCKHQDQrr:
24015
0
    return true;
24016
0
  }
24017
0
  return false;
24018
0
}
24019
24020
0
bool isVFMADD213SD(unsigned Opcode) {
24021
0
  switch (Opcode) {
24022
0
  case VFMADD213SDZm_Int:
24023
0
  case VFMADD213SDZm_Intk:
24024
0
  case VFMADD213SDZm_Intkz:
24025
0
  case VFMADD213SDZr_Int:
24026
0
  case VFMADD213SDZr_Intk:
24027
0
  case VFMADD213SDZr_Intkz:
24028
0
  case VFMADD213SDZrb_Int:
24029
0
  case VFMADD213SDZrb_Intk:
24030
0
  case VFMADD213SDZrb_Intkz:
24031
0
  case VFMADD213SDm_Int:
24032
0
  case VFMADD213SDr_Int:
24033
0
    return true;
24034
0
  }
24035
0
  return false;
24036
0
}
24037
24038
0
bool isKXORD(unsigned Opcode) {
24039
0
  return Opcode == KXORDrr;
24040
0
}
24041
24042
0
bool isVPMOVB2M(unsigned Opcode) {
24043
0
  switch (Opcode) {
24044
0
  case VPMOVB2MZ128rr:
24045
0
  case VPMOVB2MZ256rr:
24046
0
  case VPMOVB2MZrr:
24047
0
    return true;
24048
0
  }
24049
0
  return false;
24050
0
}
24051
24052
0
bool isVMREAD(unsigned Opcode) {
24053
0
  switch (Opcode) {
24054
0
  case VMREAD32mr:
24055
0
  case VMREAD32rr:
24056
0
  case VMREAD64mr:
24057
0
  case VMREAD64rr:
24058
0
    return true;
24059
0
  }
24060
0
  return false;
24061
0
}
24062
24063
0
bool isVPDPWSSDS(unsigned Opcode) {
24064
0
  switch (Opcode) {
24065
0
  case VPDPWSSDSYrm:
24066
0
  case VPDPWSSDSYrr:
24067
0
  case VPDPWSSDSZ128m:
24068
0
  case VPDPWSSDSZ128mb:
24069
0
  case VPDPWSSDSZ128mbk:
24070
0
  case VPDPWSSDSZ128mbkz:
24071
0
  case VPDPWSSDSZ128mk:
24072
0
  case VPDPWSSDSZ128mkz:
24073
0
  case VPDPWSSDSZ128r:
24074
0
  case VPDPWSSDSZ128rk:
24075
0
  case VPDPWSSDSZ128rkz:
24076
0
  case VPDPWSSDSZ256m:
24077
0
  case VPDPWSSDSZ256mb:
24078
0
  case VPDPWSSDSZ256mbk:
24079
0
  case VPDPWSSDSZ256mbkz:
24080
0
  case VPDPWSSDSZ256mk:
24081
0
  case VPDPWSSDSZ256mkz:
24082
0
  case VPDPWSSDSZ256r:
24083
0
  case VPDPWSSDSZ256rk:
24084
0
  case VPDPWSSDSZ256rkz:
24085
0
  case VPDPWSSDSZm:
24086
0
  case VPDPWSSDSZmb:
24087
0
  case VPDPWSSDSZmbk:
24088
0
  case VPDPWSSDSZmbkz:
24089
0
  case VPDPWSSDSZmk:
24090
0
  case VPDPWSSDSZmkz:
24091
0
  case VPDPWSSDSZr:
24092
0
  case VPDPWSSDSZrk:
24093
0
  case VPDPWSSDSZrkz:
24094
0
  case VPDPWSSDSrm:
24095
0
  case VPDPWSSDSrr:
24096
0
    return true;
24097
0
  }
24098
0
  return false;
24099
0
}
24100
24101
0
bool isTILERELEASE(unsigned Opcode) {
24102
0
  return Opcode == TILERELEASE;
24103
0
}
24104
24105
0
bool isCLFLUSHOPT(unsigned Opcode) {
24106
0
  return Opcode == CLFLUSHOPT;
24107
0
}
24108
24109
0
bool isDAS(unsigned Opcode) {
24110
0
  return Opcode == DAS;
24111
0
}
24112
24113
0
bool isVSCALEFPH(unsigned Opcode) {
24114
0
  switch (Opcode) {
24115
0
  case VSCALEFPHZ128rm:
24116
0
  case VSCALEFPHZ128rmb:
24117
0
  case VSCALEFPHZ128rmbk:
24118
0
  case VSCALEFPHZ128rmbkz:
24119
0
  case VSCALEFPHZ128rmk:
24120
0
  case VSCALEFPHZ128rmkz:
24121
0
  case VSCALEFPHZ128rr:
24122
0
  case VSCALEFPHZ128rrk:
24123
0
  case VSCALEFPHZ128rrkz:
24124
0
  case VSCALEFPHZ256rm:
24125
0
  case VSCALEFPHZ256rmb:
24126
0
  case VSCALEFPHZ256rmbk:
24127
0
  case VSCALEFPHZ256rmbkz:
24128
0
  case VSCALEFPHZ256rmk:
24129
0
  case VSCALEFPHZ256rmkz:
24130
0
  case VSCALEFPHZ256rr:
24131
0
  case VSCALEFPHZ256rrk:
24132
0
  case VSCALEFPHZ256rrkz:
24133
0
  case VSCALEFPHZrm:
24134
0
  case VSCALEFPHZrmb:
24135
0
  case VSCALEFPHZrmbk:
24136
0
  case VSCALEFPHZrmbkz:
24137
0
  case VSCALEFPHZrmk:
24138
0
  case VSCALEFPHZrmkz:
24139
0
  case VSCALEFPHZrr:
24140
0
  case VSCALEFPHZrrb:
24141
0
  case VSCALEFPHZrrbk:
24142
0
  case VSCALEFPHZrrbkz:
24143
0
  case VSCALEFPHZrrk:
24144
0
  case VSCALEFPHZrrkz:
24145
0
    return true;
24146
0
  }
24147
0
  return false;
24148
0
}
24149
24150
0
bool isVSUBSD(unsigned Opcode) {
24151
0
  switch (Opcode) {
24152
0
  case VSUBSDZrm_Int:
24153
0
  case VSUBSDZrm_Intk:
24154
0
  case VSUBSDZrm_Intkz:
24155
0
  case VSUBSDZrr_Int:
24156
0
  case VSUBSDZrr_Intk:
24157
0
  case VSUBSDZrr_Intkz:
24158
0
  case VSUBSDZrrb_Int:
24159
0
  case VSUBSDZrrb_Intk:
24160
0
  case VSUBSDZrrb_Intkz:
24161
0
  case VSUBSDrm_Int:
24162
0
  case VSUBSDrr_Int:
24163
0
    return true;
24164
0
  }
24165
0
  return false;
24166
0
}
24167
24168
0
bool isVCOMISS(unsigned Opcode) {
24169
0
  switch (Opcode) {
24170
0
  case VCOMISSZrm:
24171
0
  case VCOMISSZrr:
24172
0
  case VCOMISSZrrb:
24173
0
  case VCOMISSrm:
24174
0
  case VCOMISSrr:
24175
0
    return true;
24176
0
  }
24177
0
  return false;
24178
0
}
24179
24180
0
bool isORPS(unsigned Opcode) {
24181
0
  switch (Opcode) {
24182
0
  case ORPSrm:
24183
0
  case ORPSrr:
24184
0
    return true;
24185
0
  }
24186
0
  return false;
24187
0
}
24188
24189
0
bool isTDPFP16PS(unsigned Opcode) {
24190
0
  return Opcode == TDPFP16PS;
24191
0
}
24192
24193
0
bool isVMAXPD(unsigned Opcode) {
24194
0
  switch (Opcode) {
24195
0
  case VMAXPDYrm:
24196
0
  case VMAXPDYrr:
24197
0
  case VMAXPDZ128rm:
24198
0
  case VMAXPDZ128rmb:
24199
0
  case VMAXPDZ128rmbk:
24200
0
  case VMAXPDZ128rmbkz:
24201
0
  case VMAXPDZ128rmk:
24202
0
  case VMAXPDZ128rmkz:
24203
0
  case VMAXPDZ128rr:
24204
0
  case VMAXPDZ128rrk:
24205
0
  case VMAXPDZ128rrkz:
24206
0
  case VMAXPDZ256rm:
24207
0
  case VMAXPDZ256rmb:
24208
0
  case VMAXPDZ256rmbk:
24209
0
  case VMAXPDZ256rmbkz:
24210
0
  case VMAXPDZ256rmk:
24211
0
  case VMAXPDZ256rmkz:
24212
0
  case VMAXPDZ256rr:
24213
0
  case VMAXPDZ256rrk:
24214
0
  case VMAXPDZ256rrkz:
24215
0
  case VMAXPDZrm:
24216
0
  case VMAXPDZrmb:
24217
0
  case VMAXPDZrmbk:
24218
0
  case VMAXPDZrmbkz:
24219
0
  case VMAXPDZrmk:
24220
0
  case VMAXPDZrmkz:
24221
0
  case VMAXPDZrr:
24222
0
  case VMAXPDZrrb:
24223
0
  case VMAXPDZrrbk:
24224
0
  case VMAXPDZrrbkz:
24225
0
  case VMAXPDZrrk:
24226
0
  case VMAXPDZrrkz:
24227
0
  case VMAXPDrm:
24228
0
  case VMAXPDrr:
24229
0
    return true;
24230
0
  }
24231
0
  return false;
24232
0
}
24233
24234
0
bool isVPMOVWB(unsigned Opcode) {
24235
0
  switch (Opcode) {
24236
0
  case VPMOVWBZ128mr:
24237
0
  case VPMOVWBZ128mrk:
24238
0
  case VPMOVWBZ128rr:
24239
0
  case VPMOVWBZ128rrk:
24240
0
  case VPMOVWBZ128rrkz:
24241
0
  case VPMOVWBZ256mr:
24242
0
  case VPMOVWBZ256mrk:
24243
0
  case VPMOVWBZ256rr:
24244
0
  case VPMOVWBZ256rrk:
24245
0
  case VPMOVWBZ256rrkz:
24246
0
  case VPMOVWBZmr:
24247
0
  case VPMOVWBZmrk:
24248
0
  case VPMOVWBZrr:
24249
0
  case VPMOVWBZrrk:
24250
0
  case VPMOVWBZrrkz:
24251
0
    return true;
24252
0
  }
24253
0
  return false;
24254
0
}
24255
24256
0
bool isVEXP2PS(unsigned Opcode) {
24257
0
  switch (Opcode) {
24258
0
  case VEXP2PSZm:
24259
0
  case VEXP2PSZmb:
24260
0
  case VEXP2PSZmbk:
24261
0
  case VEXP2PSZmbkz:
24262
0
  case VEXP2PSZmk:
24263
0
  case VEXP2PSZmkz:
24264
0
  case VEXP2PSZr:
24265
0
  case VEXP2PSZrb:
24266
0
  case VEXP2PSZrbk:
24267
0
  case VEXP2PSZrbkz:
24268
0
  case VEXP2PSZrk:
24269
0
  case VEXP2PSZrkz:
24270
0
    return true;
24271
0
  }
24272
0
  return false;
24273
0
}
24274
24275
0
bool isVPGATHERDQ(unsigned Opcode) {
24276
0
  switch (Opcode) {
24277
0
  case VPGATHERDQYrm:
24278
0
  case VPGATHERDQZ128rm:
24279
0
  case VPGATHERDQZ256rm:
24280
0
  case VPGATHERDQZrm:
24281
0
  case VPGATHERDQrm:
24282
0
    return true;
24283
0
  }
24284
0
  return false;
24285
0
}
24286
24287
0
bool isVPSRAVQ(unsigned Opcode) {
24288
0
  switch (Opcode) {
24289
0
  case VPSRAVQZ128rm:
24290
0
  case VPSRAVQZ128rmb:
24291
0
  case VPSRAVQZ128rmbk:
24292
0
  case VPSRAVQZ128rmbkz:
24293
0
  case VPSRAVQZ128rmk:
24294
0
  case VPSRAVQZ128rmkz:
24295
0
  case VPSRAVQZ128rr:
24296
0
  case VPSRAVQZ128rrk:
24297
0
  case VPSRAVQZ128rrkz:
24298
0
  case VPSRAVQZ256rm:
24299
0
  case VPSRAVQZ256rmb:
24300
0
  case VPSRAVQZ256rmbk:
24301
0
  case VPSRAVQZ256rmbkz:
24302
0
  case VPSRAVQZ256rmk:
24303
0
  case VPSRAVQZ256rmkz:
24304
0
  case VPSRAVQZ256rr:
24305
0
  case VPSRAVQZ256rrk:
24306
0
  case VPSRAVQZ256rrkz:
24307
0
  case VPSRAVQZrm:
24308
0
  case VPSRAVQZrmb:
24309
0
  case VPSRAVQZrmbk:
24310
0
  case VPSRAVQZrmbkz:
24311
0
  case VPSRAVQZrmk:
24312
0
  case VPSRAVQZrmkz:
24313
0
  case VPSRAVQZrr:
24314
0
  case VPSRAVQZrrk:
24315
0
  case VPSRAVQZrrkz:
24316
0
    return true;
24317
0
  }
24318
0
  return false;
24319
0
}
24320
24321
0
bool isPCMPISTRI(unsigned Opcode) {
24322
0
  switch (Opcode) {
24323
0
  case PCMPISTRIrm:
24324
0
  case PCMPISTRIrr:
24325
0
    return true;
24326
0
  }
24327
0
  return false;
24328
0
}
24329
24330
0
bool isVFMSUB231PD(unsigned Opcode) {
24331
0
  switch (Opcode) {
24332
0
  case VFMSUB231PDYm:
24333
0
  case VFMSUB231PDYr:
24334
0
  case VFMSUB231PDZ128m:
24335
0
  case VFMSUB231PDZ128mb:
24336
0
  case VFMSUB231PDZ128mbk:
24337
0
  case VFMSUB231PDZ128mbkz:
24338
0
  case VFMSUB231PDZ128mk:
24339
0
  case VFMSUB231PDZ128mkz:
24340
0
  case VFMSUB231PDZ128r:
24341
0
  case VFMSUB231PDZ128rk:
24342
0
  case VFMSUB231PDZ128rkz:
24343
0
  case VFMSUB231PDZ256m:
24344
0
  case VFMSUB231PDZ256mb:
24345
0
  case VFMSUB231PDZ256mbk:
24346
0
  case VFMSUB231PDZ256mbkz:
24347
0
  case VFMSUB231PDZ256mk:
24348
0
  case VFMSUB231PDZ256mkz:
24349
0
  case VFMSUB231PDZ256r:
24350
0
  case VFMSUB231PDZ256rk:
24351
0
  case VFMSUB231PDZ256rkz:
24352
0
  case VFMSUB231PDZm:
24353
0
  case VFMSUB231PDZmb:
24354
0
  case VFMSUB231PDZmbk:
24355
0
  case VFMSUB231PDZmbkz:
24356
0
  case VFMSUB231PDZmk:
24357
0
  case VFMSUB231PDZmkz:
24358
0
  case VFMSUB231PDZr:
24359
0
  case VFMSUB231PDZrb:
24360
0
  case VFMSUB231PDZrbk:
24361
0
  case VFMSUB231PDZrbkz:
24362
0
  case VFMSUB231PDZrk:
24363
0
  case VFMSUB231PDZrkz:
24364
0
  case VFMSUB231PDm:
24365
0
  case VFMSUB231PDr:
24366
0
    return true;
24367
0
  }
24368
0
  return false;
24369
0
}
24370
24371
0
bool isRDMSR(unsigned Opcode) {
24372
0
  return Opcode == RDMSR;
24373
0
}
24374
24375
0
bool isKORTESTD(unsigned Opcode) {
24376
0
  return Opcode == KORTESTDrr;
24377
0
}
24378
24379
0
bool isVPBLENDMW(unsigned Opcode) {
24380
0
  switch (Opcode) {
24381
0
  case VPBLENDMWZ128rm:
24382
0
  case VPBLENDMWZ128rmk:
24383
0
  case VPBLENDMWZ128rmkz:
24384
0
  case VPBLENDMWZ128rr:
24385
0
  case VPBLENDMWZ128rrk:
24386
0
  case VPBLENDMWZ128rrkz:
24387
0
  case VPBLENDMWZ256rm:
24388
0
  case VPBLENDMWZ256rmk:
24389
0
  case VPBLENDMWZ256rmkz:
24390
0
  case VPBLENDMWZ256rr:
24391
0
  case VPBLENDMWZ256rrk:
24392
0
  case VPBLENDMWZ256rrkz:
24393
0
  case VPBLENDMWZrm:
24394
0
  case VPBLENDMWZrmk:
24395
0
  case VPBLENDMWZrmkz:
24396
0
  case VPBLENDMWZrr:
24397
0
  case VPBLENDMWZrrk:
24398
0
  case VPBLENDMWZrrkz:
24399
0
    return true;
24400
0
  }
24401
0
  return false;
24402
0
}
24403
24404
0
bool isPSHUFB(unsigned Opcode) {
24405
0
  switch (Opcode) {
24406
0
  case MMX_PSHUFBrm:
24407
0
  case MMX_PSHUFBrr:
24408
0
  case PSHUFBrm:
24409
0
  case PSHUFBrr:
24410
0
    return true;
24411
0
  }
24412
0
  return false;
24413
0
}
24414
24415
0
bool isVDPBF16PS(unsigned Opcode) {
24416
0
  switch (Opcode) {
24417
0
  case VDPBF16PSZ128m:
24418
0
  case VDPBF16PSZ128mb:
24419
0
  case VDPBF16PSZ128mbk:
24420
0
  case VDPBF16PSZ128mbkz:
24421
0
  case VDPBF16PSZ128mk:
24422
0
  case VDPBF16PSZ128mkz:
24423
0
  case VDPBF16PSZ128r:
24424
0
  case VDPBF16PSZ128rk:
24425
0
  case VDPBF16PSZ128rkz:
24426
0
  case VDPBF16PSZ256m:
24427
0
  case VDPBF16PSZ256mb:
24428
0
  case VDPBF16PSZ256mbk:
24429
0
  case VDPBF16PSZ256mbkz:
24430
0
  case VDPBF16PSZ256mk:
24431
0
  case VDPBF16PSZ256mkz:
24432
0
  case VDPBF16PSZ256r:
24433
0
  case VDPBF16PSZ256rk:
24434
0
  case VDPBF16PSZ256rkz:
24435
0
  case VDPBF16PSZm:
24436
0
  case VDPBF16PSZmb:
24437
0
  case VDPBF16PSZmbk:
24438
0
  case VDPBF16PSZmbkz:
24439
0
  case VDPBF16PSZmk:
24440
0
  case VDPBF16PSZmkz:
24441
0
  case VDPBF16PSZr:
24442
0
  case VDPBF16PSZrk:
24443
0
  case VDPBF16PSZrkz:
24444
0
    return true;
24445
0
  }
24446
0
  return false;
24447
0
}
24448
24449
0
bool isTDPBF16PS(unsigned Opcode) {
24450
0
  return Opcode == TDPBF16PS;
24451
0
}
24452
24453
0
bool isFCMOVE(unsigned Opcode) {
24454
0
  return Opcode == CMOVE_F;
24455
0
}
24456
24457
0
bool isCMPSS(unsigned Opcode) {
24458
0
  switch (Opcode) {
24459
0
  case CMPSSrm_Int:
24460
0
  case CMPSSrr_Int:
24461
0
    return true;
24462
0
  }
24463
0
  return false;
24464
0
}
24465
24466
0
bool isMASKMOVDQU(unsigned Opcode) {
24467
0
  switch (Opcode) {
24468
0
  case MASKMOVDQU:
24469
0
  case MASKMOVDQU64:
24470
0
    return true;
24471
0
  }
24472
0
  return false;
24473
0
}
24474
24475
0
bool isVPDPWUSDS(unsigned Opcode) {
24476
0
  switch (Opcode) {
24477
0
  case VPDPWUSDSYrm:
24478
0
  case VPDPWUSDSYrr:
24479
0
  case VPDPWUSDSrm:
24480
0
  case VPDPWUSDSrr:
24481
0
    return true;
24482
0
  }
24483
0
  return false;
24484
0
}
24485
24486
0
bool isSARX(unsigned Opcode) {
24487
0
  switch (Opcode) {
24488
0
  case SARX32rm:
24489
0
  case SARX32rm_EVEX:
24490
0
  case SARX32rr:
24491
0
  case SARX32rr_EVEX:
24492
0
  case SARX64rm:
24493
0
  case SARX64rm_EVEX:
24494
0
  case SARX64rr:
24495
0
  case SARX64rr_EVEX:
24496
0
    return true;
24497
0
  }
24498
0
  return false;
24499
0
}
24500
24501
0
bool isSGDT(unsigned Opcode) {
24502
0
  return Opcode == SGDT64m;
24503
0
}
24504
24505
0
bool isVFMULCPH(unsigned Opcode) {
24506
0
  switch (Opcode) {
24507
0
  case VFMULCPHZ128rm:
24508
0
  case VFMULCPHZ128rmb:
24509
0
  case VFMULCPHZ128rmbk:
24510
0
  case VFMULCPHZ128rmbkz:
24511
0
  case VFMULCPHZ128rmk:
24512
0
  case VFMULCPHZ128rmkz:
24513
0
  case VFMULCPHZ128rr:
24514
0
  case VFMULCPHZ128rrk:
24515
0
  case VFMULCPHZ128rrkz:
24516
0
  case VFMULCPHZ256rm:
24517
0
  case VFMULCPHZ256rmb:
24518
0
  case VFMULCPHZ256rmbk:
24519
0
  case VFMULCPHZ256rmbkz:
24520
0
  case VFMULCPHZ256rmk:
24521
0
  case VFMULCPHZ256rmkz:
24522
0
  case VFMULCPHZ256rr:
24523
0
  case VFMULCPHZ256rrk:
24524
0
  case VFMULCPHZ256rrkz:
24525
0
  case VFMULCPHZrm:
24526
0
  case VFMULCPHZrmb:
24527
0
  case VFMULCPHZrmbk:
24528
0
  case VFMULCPHZrmbkz:
24529
0
  case VFMULCPHZrmk:
24530
0
  case VFMULCPHZrmkz:
24531
0
  case VFMULCPHZrr:
24532
0
  case VFMULCPHZrrb:
24533
0
  case VFMULCPHZrrbk:
24534
0
  case VFMULCPHZrrbkz:
24535
0
  case VFMULCPHZrrk:
24536
0
  case VFMULCPHZrrkz:
24537
0
    return true;
24538
0
  }
24539
0
  return false;
24540
0
}
24541
24542
0
bool isURDMSR(unsigned Opcode) {
24543
0
  switch (Opcode) {
24544
0
  case URDMSRri:
24545
0
  case URDMSRrr:
24546
0
    return true;
24547
0
  }
24548
0
  return false;
24549
0
}
24550
24551
0
bool isKUNPCKWD(unsigned Opcode) {
24552
0
  return Opcode == KUNPCKWDrr;
24553
0
}
24554
24555
0
bool isCVTPS2PD(unsigned Opcode) {
24556
0
  switch (Opcode) {
24557
0
  case CVTPS2PDrm:
24558
0
  case CVTPS2PDrr:
24559
0
    return true;
24560
0
  }
24561
0
  return false;
24562
0
}
24563
24564
0
bool isFBSTP(unsigned Opcode) {
24565
0
  return Opcode == FBSTPm;
24566
0
}
24567
24568
0
bool isPSUBQ(unsigned Opcode) {
24569
0
  switch (Opcode) {
24570
0
  case MMX_PSUBQrm:
24571
0
  case MMX_PSUBQrr:
24572
0
  case PSUBQrm:
24573
0
  case PSUBQrr:
24574
0
    return true;
24575
0
  }
24576
0
  return false;
24577
0
}
24578
24579
0
bool isFXSAVE64(unsigned Opcode) {
24580
0
  return Opcode == FXSAVE64;
24581
0
}
24582
24583
0
bool isKMOVW(unsigned Opcode) {
24584
0
  switch (Opcode) {
24585
0
  case KMOVWkk:
24586
0
  case KMOVWkk_EVEX:
24587
0
  case KMOVWkm:
24588
0
  case KMOVWkm_EVEX:
24589
0
  case KMOVWkr:
24590
0
  case KMOVWkr_EVEX:
24591
0
  case KMOVWmk:
24592
0
  case KMOVWmk_EVEX:
24593
0
  case KMOVWrk:
24594
0
  case KMOVWrk_EVEX:
24595
0
    return true;
24596
0
  }
24597
0
  return false;
24598
0
}
24599
24600
0
bool isBTS(unsigned Opcode) {
24601
0
  switch (Opcode) {
24602
0
  case BTS16mi8:
24603
0
  case BTS16mr:
24604
0
  case BTS16ri8:
24605
0
  case BTS16rr:
24606
0
  case BTS32mi8:
24607
0
  case BTS32mr:
24608
0
  case BTS32ri8:
24609
0
  case BTS32rr:
24610
0
  case BTS64mi8:
24611
0
  case BTS64mr:
24612
0
  case BTS64ri8:
24613
0
  case BTS64rr:
24614
0
    return true;
24615
0
  }
24616
0
  return false;
24617
0
}
24618
24619
0
bool isVPHADDBQ(unsigned Opcode) {
24620
0
  switch (Opcode) {
24621
0
  case VPHADDBQrm:
24622
0
  case VPHADDBQrr:
24623
0
    return true;
24624
0
  }
24625
0
  return false;
24626
0
}
24627
24628
0
bool isFRSTOR(unsigned Opcode) {
24629
0
  return Opcode == FRSTORm;
24630
0
}
24631
24632
0
bool isVFMSUB132PD(unsigned Opcode) {
24633
0
  switch (Opcode) {
24634
0
  case VFMSUB132PDYm:
24635
0
  case VFMSUB132PDYr:
24636
0
  case VFMSUB132PDZ128m:
24637
0
  case VFMSUB132PDZ128mb:
24638
0
  case VFMSUB132PDZ128mbk:
24639
0
  case VFMSUB132PDZ128mbkz:
24640
0
  case VFMSUB132PDZ128mk:
24641
0
  case VFMSUB132PDZ128mkz:
24642
0
  case VFMSUB132PDZ128r:
24643
0
  case VFMSUB132PDZ128rk:
24644
0
  case VFMSUB132PDZ128rkz:
24645
0
  case VFMSUB132PDZ256m:
24646
0
  case VFMSUB132PDZ256mb:
24647
0
  case VFMSUB132PDZ256mbk:
24648
0
  case VFMSUB132PDZ256mbkz:
24649
0
  case VFMSUB132PDZ256mk:
24650
0
  case VFMSUB132PDZ256mkz:
24651
0
  case VFMSUB132PDZ256r:
24652
0
  case VFMSUB132PDZ256rk:
24653
0
  case VFMSUB132PDZ256rkz:
24654
0
  case VFMSUB132PDZm:
24655
0
  case VFMSUB132PDZmb:
24656
0
  case VFMSUB132PDZmbk:
24657
0
  case VFMSUB132PDZmbkz:
24658
0
  case VFMSUB132PDZmk:
24659
0
  case VFMSUB132PDZmkz:
24660
0
  case VFMSUB132PDZr:
24661
0
  case VFMSUB132PDZrb:
24662
0
  case VFMSUB132PDZrbk:
24663
0
  case VFMSUB132PDZrbkz:
24664
0
  case VFMSUB132PDZrk:
24665
0
  case VFMSUB132PDZrkz:
24666
0
  case VFMSUB132PDm:
24667
0
  case VFMSUB132PDr:
24668
0
    return true;
24669
0
  }
24670
0
  return false;
24671
0
}
24672
24673
0
bool isPMULLD(unsigned Opcode) {
24674
0
  switch (Opcode) {
24675
0
  case PMULLDrm:
24676
0
  case PMULLDrr:
24677
0
    return true;
24678
0
  }
24679
0
  return false;
24680
0
}
24681
24682
0
bool isSHA1MSG2(unsigned Opcode) {
24683
0
  switch (Opcode) {
24684
0
  case SHA1MSG2rm:
24685
0
  case SHA1MSG2rm_EVEX:
24686
0
  case SHA1MSG2rr:
24687
0
  case SHA1MSG2rr_EVEX:
24688
0
    return true;
24689
0
  }
24690
0
  return false;
24691
0
}
24692
24693
0
bool isJECXZ(unsigned Opcode) {
24694
0
  return Opcode == JECXZ;
24695
0
}
24696
24697
0
bool isVCVTUDQ2PS(unsigned Opcode) {
24698
0
  switch (Opcode) {
24699
0
  case VCVTUDQ2PSZ128rm:
24700
0
  case VCVTUDQ2PSZ128rmb:
24701
0
  case VCVTUDQ2PSZ128rmbk:
24702
0
  case VCVTUDQ2PSZ128rmbkz:
24703
0
  case VCVTUDQ2PSZ128rmk:
24704
0
  case VCVTUDQ2PSZ128rmkz:
24705
0
  case VCVTUDQ2PSZ128rr:
24706
0
  case VCVTUDQ2PSZ128rrk:
24707
0
  case VCVTUDQ2PSZ128rrkz:
24708
0
  case VCVTUDQ2PSZ256rm:
24709
0
  case VCVTUDQ2PSZ256rmb:
24710
0
  case VCVTUDQ2PSZ256rmbk:
24711
0
  case VCVTUDQ2PSZ256rmbkz:
24712
0
  case VCVTUDQ2PSZ256rmk:
24713
0
  case VCVTUDQ2PSZ256rmkz:
24714
0
  case VCVTUDQ2PSZ256rr:
24715
0
  case VCVTUDQ2PSZ256rrk:
24716
0
  case VCVTUDQ2PSZ256rrkz:
24717
0
  case VCVTUDQ2PSZrm:
24718
0
  case VCVTUDQ2PSZrmb:
24719
0
  case VCVTUDQ2PSZrmbk:
24720
0
  case VCVTUDQ2PSZrmbkz:
24721
0
  case VCVTUDQ2PSZrmk:
24722
0
  case VCVTUDQ2PSZrmkz:
24723
0
  case VCVTUDQ2PSZrr:
24724
0
  case VCVTUDQ2PSZrrb:
24725
0
  case VCVTUDQ2PSZrrbk:
24726
0
  case VCVTUDQ2PSZrrbkz:
24727
0
  case VCVTUDQ2PSZrrk:
24728
0
  case VCVTUDQ2PSZrrkz:
24729
0
    return true;
24730
0
  }
24731
0
  return false;
24732
0
}
24733
24734
0
bool isAESENC(unsigned Opcode) {
24735
0
  switch (Opcode) {
24736
0
  case AESENCrm:
24737
0
  case AESENCrr:
24738
0
    return true;
24739
0
  }
24740
0
  return false;
24741
0
}
24742
24743
0
bool isPSIGNW(unsigned Opcode) {
24744
0
  switch (Opcode) {
24745
0
  case MMX_PSIGNWrm:
24746
0
  case MMX_PSIGNWrr:
24747
0
  case PSIGNWrm:
24748
0
  case PSIGNWrr:
24749
0
    return true;
24750
0
  }
24751
0
  return false;
24752
0
}
24753
24754
0
bool isUNPCKLPD(unsigned Opcode) {
24755
0
  switch (Opcode) {
24756
0
  case UNPCKLPDrm:
24757
0
  case UNPCKLPDrr:
24758
0
    return true;
24759
0
  }
24760
0
  return false;
24761
0
}
24762
24763
0
bool isPUSHP(unsigned Opcode) {
24764
0
  return Opcode == PUSHP64r;
24765
0
}
24766
24767
0
bool isBLSI(unsigned Opcode) {
24768
0
  switch (Opcode) {
24769
0
  case BLSI32rm:
24770
0
  case BLSI32rm_EVEX:
24771
0
  case BLSI32rr:
24772
0
  case BLSI32rr_EVEX:
24773
0
  case BLSI64rm:
24774
0
  case BLSI64rm_EVEX:
24775
0
  case BLSI64rr:
24776
0
  case BLSI64rr_EVEX:
24777
0
    return true;
24778
0
  }
24779
0
  return false;
24780
0
}
24781
24782
0
bool isVPTESTNMB(unsigned Opcode) {
24783
0
  switch (Opcode) {
24784
0
  case VPTESTNMBZ128rm:
24785
0
  case VPTESTNMBZ128rmk:
24786
0
  case VPTESTNMBZ128rr:
24787
0
  case VPTESTNMBZ128rrk:
24788
0
  case VPTESTNMBZ256rm:
24789
0
  case VPTESTNMBZ256rmk:
24790
0
  case VPTESTNMBZ256rr:
24791
0
  case VPTESTNMBZ256rrk:
24792
0
  case VPTESTNMBZrm:
24793
0
  case VPTESTNMBZrmk:
24794
0
  case VPTESTNMBZrr:
24795
0
  case VPTESTNMBZrrk:
24796
0
    return true;
24797
0
  }
24798
0
  return false;
24799
0
}
24800
24801
0
bool isWRUSSQ(unsigned Opcode) {
24802
0
  switch (Opcode) {
24803
0
  case WRUSSQ:
24804
0
  case WRUSSQ_EVEX:
24805
0
    return true;
24806
0
  }
24807
0
  return false;
24808
0
}
24809
24810
0
bool isVGF2P8MULB(unsigned Opcode) {
24811
0
  switch (Opcode) {
24812
0
  case VGF2P8MULBYrm:
24813
0
  case VGF2P8MULBYrr:
24814
0
  case VGF2P8MULBZ128rm:
24815
0
  case VGF2P8MULBZ128rmk:
24816
0
  case VGF2P8MULBZ128rmkz:
24817
0
  case VGF2P8MULBZ128rr:
24818
0
  case VGF2P8MULBZ128rrk:
24819
0
  case VGF2P8MULBZ128rrkz:
24820
0
  case VGF2P8MULBZ256rm:
24821
0
  case VGF2P8MULBZ256rmk:
24822
0
  case VGF2P8MULBZ256rmkz:
24823
0
  case VGF2P8MULBZ256rr:
24824
0
  case VGF2P8MULBZ256rrk:
24825
0
  case VGF2P8MULBZ256rrkz:
24826
0
  case VGF2P8MULBZrm:
24827
0
  case VGF2P8MULBZrmk:
24828
0
  case VGF2P8MULBZrmkz:
24829
0
  case VGF2P8MULBZrr:
24830
0
  case VGF2P8MULBZrrk:
24831
0
  case VGF2P8MULBZrrkz:
24832
0
  case VGF2P8MULBrm:
24833
0
  case VGF2P8MULBrr:
24834
0
    return true;
24835
0
  }
24836
0
  return false;
24837
0
}
24838
24839
0
bool isVPUNPCKLBW(unsigned Opcode) {
24840
0
  switch (Opcode) {
24841
0
  case VPUNPCKLBWYrm:
24842
0
  case VPUNPCKLBWYrr:
24843
0
  case VPUNPCKLBWZ128rm:
24844
0
  case VPUNPCKLBWZ128rmk:
24845
0
  case VPUNPCKLBWZ128rmkz:
24846
0
  case VPUNPCKLBWZ128rr:
24847
0
  case VPUNPCKLBWZ128rrk:
24848
0
  case VPUNPCKLBWZ128rrkz:
24849
0
  case VPUNPCKLBWZ256rm:
24850
0
  case VPUNPCKLBWZ256rmk:
24851
0
  case VPUNPCKLBWZ256rmkz:
24852
0
  case VPUNPCKLBWZ256rr:
24853
0
  case VPUNPCKLBWZ256rrk:
24854
0
  case VPUNPCKLBWZ256rrkz:
24855
0
  case VPUNPCKLBWZrm:
24856
0
  case VPUNPCKLBWZrmk:
24857
0
  case VPUNPCKLBWZrmkz:
24858
0
  case VPUNPCKLBWZrr:
24859
0
  case VPUNPCKLBWZrrk:
24860
0
  case VPUNPCKLBWZrrkz:
24861
0
  case VPUNPCKLBWrm:
24862
0
  case VPUNPCKLBWrr:
24863
0
    return true;
24864
0
  }
24865
0
  return false;
24866
0
}
24867
24868
0
bool isVRANGESD(unsigned Opcode) {
24869
0
  switch (Opcode) {
24870
0
  case VRANGESDZrmi:
24871
0
  case VRANGESDZrmik:
24872
0
  case VRANGESDZrmikz:
24873
0
  case VRANGESDZrri:
24874
0
  case VRANGESDZrrib:
24875
0
  case VRANGESDZrribk:
24876
0
  case VRANGESDZrribkz:
24877
0
  case VRANGESDZrrik:
24878
0
  case VRANGESDZrrikz:
24879
0
    return true;
24880
0
  }
24881
0
  return false;
24882
0
}
24883
24884
0
bool isCLD(unsigned Opcode) {
24885
0
  return Opcode == CLD;
24886
0
}
24887
24888
0
bool isVSCALEFPD(unsigned Opcode) {
24889
0
  switch (Opcode) {
24890
0
  case VSCALEFPDZ128rm:
24891
0
  case VSCALEFPDZ128rmb:
24892
0
  case VSCALEFPDZ128rmbk:
24893
0
  case VSCALEFPDZ128rmbkz:
24894
0
  case VSCALEFPDZ128rmk:
24895
0
  case VSCALEFPDZ128rmkz:
24896
0
  case VSCALEFPDZ128rr:
24897
0
  case VSCALEFPDZ128rrk:
24898
0
  case VSCALEFPDZ128rrkz:
24899
0
  case VSCALEFPDZ256rm:
24900
0
  case VSCALEFPDZ256rmb:
24901
0
  case VSCALEFPDZ256rmbk:
24902
0
  case VSCALEFPDZ256rmbkz:
24903
0
  case VSCALEFPDZ256rmk:
24904
0
  case VSCALEFPDZ256rmkz:
24905
0
  case VSCALEFPDZ256rr:
24906
0
  case VSCALEFPDZ256rrk:
24907
0
  case VSCALEFPDZ256rrkz:
24908
0
  case VSCALEFPDZrm:
24909
0
  case VSCALEFPDZrmb:
24910
0
  case VSCALEFPDZrmbk:
24911
0
  case VSCALEFPDZrmbkz:
24912
0
  case VSCALEFPDZrmk:
24913
0
  case VSCALEFPDZrmkz:
24914
0
  case VSCALEFPDZrr:
24915
0
  case VSCALEFPDZrrb:
24916
0
  case VSCALEFPDZrrbk:
24917
0
  case VSCALEFPDZrrbkz:
24918
0
  case VSCALEFPDZrrk:
24919
0
  case VSCALEFPDZrrkz:
24920
0
    return true;
24921
0
  }
24922
0
  return false;
24923
0
}
24924
24925
0
bool isVPERMQ(unsigned Opcode) {
24926
0
  switch (Opcode) {
24927
0
  case VPERMQYmi:
24928
0
  case VPERMQYri:
24929
0
  case VPERMQZ256mbi:
24930
0
  case VPERMQZ256mbik:
24931
0
  case VPERMQZ256mbikz:
24932
0
  case VPERMQZ256mi:
24933
0
  case VPERMQZ256mik:
24934
0
  case VPERMQZ256mikz:
24935
0
  case VPERMQZ256ri:
24936
0
  case VPERMQZ256rik:
24937
0
  case VPERMQZ256rikz:
24938
0
  case VPERMQZ256rm:
24939
0
  case VPERMQZ256rmb:
24940
0
  case VPERMQZ256rmbk:
24941
0
  case VPERMQZ256rmbkz:
24942
0
  case VPERMQZ256rmk:
24943
0
  case VPERMQZ256rmkz:
24944
0
  case VPERMQZ256rr:
24945
0
  case VPERMQZ256rrk:
24946
0
  case VPERMQZ256rrkz:
24947
0
  case VPERMQZmbi:
24948
0
  case VPERMQZmbik:
24949
0
  case VPERMQZmbikz:
24950
0
  case VPERMQZmi:
24951
0
  case VPERMQZmik:
24952
0
  case VPERMQZmikz:
24953
0
  case VPERMQZri:
24954
0
  case VPERMQZrik:
24955
0
  case VPERMQZrikz:
24956
0
  case VPERMQZrm:
24957
0
  case VPERMQZrmb:
24958
0
  case VPERMQZrmbk:
24959
0
  case VPERMQZrmbkz:
24960
0
  case VPERMQZrmk:
24961
0
  case VPERMQZrmkz:
24962
0
  case VPERMQZrr:
24963
0
  case VPERMQZrrk:
24964
0
  case VPERMQZrrkz:
24965
0
    return true;
24966
0
  }
24967
0
  return false;
24968
0
}
24969
24970
0
bool isVPSHLDVW(unsigned Opcode) {
24971
0
  switch (Opcode) {
24972
0
  case VPSHLDVWZ128m:
24973
0
  case VPSHLDVWZ128mk:
24974
0
  case VPSHLDVWZ128mkz:
24975
0
  case VPSHLDVWZ128r:
24976
0
  case VPSHLDVWZ128rk:
24977
0
  case VPSHLDVWZ128rkz:
24978
0
  case VPSHLDVWZ256m:
24979
0
  case VPSHLDVWZ256mk:
24980
0
  case VPSHLDVWZ256mkz:
24981
0
  case VPSHLDVWZ256r:
24982
0
  case VPSHLDVWZ256rk:
24983
0
  case VPSHLDVWZ256rkz:
24984
0
  case VPSHLDVWZm:
24985
0
  case VPSHLDVWZmk:
24986
0
  case VPSHLDVWZmkz:
24987
0
  case VPSHLDVWZr:
24988
0
  case VPSHLDVWZrk:
24989
0
  case VPSHLDVWZrkz:
24990
0
    return true;
24991
0
  }
24992
0
  return false;
24993
0
}
24994
24995
0
bool isROR(unsigned Opcode) {
24996
0
  switch (Opcode) {
24997
0
  case ROR16m1:
24998
0
  case ROR16mCL:
24999
0
  case ROR16mi:
25000
0
  case ROR16r1:
25001
0
  case ROR16rCL:
25002
0
  case ROR16ri:
25003
0
  case ROR32m1:
25004
0
  case ROR32mCL:
25005
0
  case ROR32mi:
25006
0
  case ROR32r1:
25007
0
  case ROR32rCL:
25008
0
  case ROR32ri:
25009
0
  case ROR64m1:
25010
0
  case ROR64mCL:
25011
0
  case ROR64mi:
25012
0
  case ROR64r1:
25013
0
  case ROR64rCL:
25014
0
  case ROR64ri:
25015
0
  case ROR8m1:
25016
0
  case ROR8mCL:
25017
0
  case ROR8mi:
25018
0
  case ROR8r1:
25019
0
  case ROR8rCL:
25020
0
  case ROR8ri:
25021
0
    return true;
25022
0
  }
25023
0
  return false;
25024
0
}
25025
25026
0
bool isVFMADDSUB132PH(unsigned Opcode) {
25027
0
  switch (Opcode) {
25028
0
  case VFMADDSUB132PHZ128m:
25029
0
  case VFMADDSUB132PHZ128mb:
25030
0
  case VFMADDSUB132PHZ128mbk:
25031
0
  case VFMADDSUB132PHZ128mbkz:
25032
0
  case VFMADDSUB132PHZ128mk:
25033
0
  case VFMADDSUB132PHZ128mkz:
25034
0
  case VFMADDSUB132PHZ128r:
25035
0
  case VFMADDSUB132PHZ128rk:
25036
0
  case VFMADDSUB132PHZ128rkz:
25037
0
  case VFMADDSUB132PHZ256m:
25038
0
  case VFMADDSUB132PHZ256mb:
25039
0
  case VFMADDSUB132PHZ256mbk:
25040
0
  case VFMADDSUB132PHZ256mbkz:
25041
0
  case VFMADDSUB132PHZ256mk:
25042
0
  case VFMADDSUB132PHZ256mkz:
25043
0
  case VFMADDSUB132PHZ256r:
25044
0
  case VFMADDSUB132PHZ256rk:
25045
0
  case VFMADDSUB132PHZ256rkz:
25046
0
  case VFMADDSUB132PHZm:
25047
0
  case VFMADDSUB132PHZmb:
25048
0
  case VFMADDSUB132PHZmbk:
25049
0
  case VFMADDSUB132PHZmbkz:
25050
0
  case VFMADDSUB132PHZmk:
25051
0
  case VFMADDSUB132PHZmkz:
25052
0
  case VFMADDSUB132PHZr:
25053
0
  case VFMADDSUB132PHZrb:
25054
0
  case VFMADDSUB132PHZrbk:
25055
0
  case VFMADDSUB132PHZrbkz:
25056
0
  case VFMADDSUB132PHZrk:
25057
0
  case VFMADDSUB132PHZrkz:
25058
0
    return true;
25059
0
  }
25060
0
  return false;
25061
0
}
25062
25063
0
bool isDEC(unsigned Opcode) {
25064
0
  switch (Opcode) {
25065
0
  case DEC16m:
25066
0
  case DEC16m_EVEX:
25067
0
  case DEC16m_ND:
25068
0
  case DEC16m_NF:
25069
0
  case DEC16m_NF_ND:
25070
0
  case DEC16r:
25071
0
  case DEC16r_EVEX:
25072
0
  case DEC16r_ND:
25073
0
  case DEC16r_NF:
25074
0
  case DEC16r_NF_ND:
25075
0
  case DEC16r_alt:
25076
0
  case DEC32m:
25077
0
  case DEC32m_EVEX:
25078
0
  case DEC32m_ND:
25079
0
  case DEC32m_NF:
25080
0
  case DEC32m_NF_ND:
25081
0
  case DEC32r:
25082
0
  case DEC32r_EVEX:
25083
0
  case DEC32r_ND:
25084
0
  case DEC32r_NF:
25085
0
  case DEC32r_NF_ND:
25086
0
  case DEC32r_alt:
25087
0
  case DEC64m:
25088
0
  case DEC64m_EVEX:
25089
0
  case DEC64m_ND:
25090
0
  case DEC64m_NF:
25091
0
  case DEC64m_NF_ND:
25092
0
  case DEC64r:
25093
0
  case DEC64r_EVEX:
25094
0
  case DEC64r_ND:
25095
0
  case DEC64r_NF:
25096
0
  case DEC64r_NF_ND:
25097
0
  case DEC8m:
25098
0
  case DEC8m_EVEX:
25099
0
  case DEC8m_ND:
25100
0
  case DEC8m_NF:
25101
0
  case DEC8m_NF_ND:
25102
0
  case DEC8r:
25103
0
  case DEC8r_EVEX:
25104
0
  case DEC8r_ND:
25105
0
  case DEC8r_NF:
25106
0
  case DEC8r_NF_ND:
25107
0
    return true;
25108
0
  }
25109
0
  return false;
25110
0
}
25111
25112
0
bool isVGETEXPSH(unsigned Opcode) {
25113
0
  switch (Opcode) {
25114
0
  case VGETEXPSHZm:
25115
0
  case VGETEXPSHZmk:
25116
0
  case VGETEXPSHZmkz:
25117
0
  case VGETEXPSHZr:
25118
0
  case VGETEXPSHZrb:
25119
0
  case VGETEXPSHZrbk:
25120
0
  case VGETEXPSHZrbkz:
25121
0
  case VGETEXPSHZrk:
25122
0
  case VGETEXPSHZrkz:
25123
0
    return true;
25124
0
  }
25125
0
  return false;
25126
0
}
25127
25128
0
bool isAESDEC(unsigned Opcode) {
25129
0
  switch (Opcode) {
25130
0
  case AESDECrm:
25131
0
  case AESDECrr:
25132
0
    return true;
25133
0
  }
25134
0
  return false;
25135
0
}
25136
25137
0
bool isKORD(unsigned Opcode) {
25138
0
  return Opcode == KORDrr;
25139
0
}
25140
25141
0
bool isVPMULHW(unsigned Opcode) {
25142
0
  switch (Opcode) {
25143
0
  case VPMULHWYrm:
25144
0
  case VPMULHWYrr:
25145
0
  case VPMULHWZ128rm:
25146
0
  case VPMULHWZ128rmk:
25147
0
  case VPMULHWZ128rmkz:
25148
0
  case VPMULHWZ128rr:
25149
0
  case VPMULHWZ128rrk:
25150
0
  case VPMULHWZ128rrkz:
25151
0
  case VPMULHWZ256rm:
25152
0
  case VPMULHWZ256rmk:
25153
0
  case VPMULHWZ256rmkz:
25154
0
  case VPMULHWZ256rr:
25155
0
  case VPMULHWZ256rrk:
25156
0
  case VPMULHWZ256rrkz:
25157
0
  case VPMULHWZrm:
25158
0
  case VPMULHWZrmk:
25159
0
  case VPMULHWZrmkz:
25160
0
  case VPMULHWZrr:
25161
0
  case VPMULHWZrrk:
25162
0
  case VPMULHWZrrkz:
25163
0
  case VPMULHWrm:
25164
0
  case VPMULHWrr:
25165
0
    return true;
25166
0
  }
25167
0
  return false;
25168
0
}
25169
25170
0
bool isTILELOADDT1(unsigned Opcode) {
25171
0
  switch (Opcode) {
25172
0
  case TILELOADDT1:
25173
0
  case TILELOADDT1_EVEX:
25174
0
    return true;
25175
0
  }
25176
0
  return false;
25177
0
}
25178
25179
0
bool isVMASKMOVPS(unsigned Opcode) {
25180
0
  switch (Opcode) {
25181
0
  case VMASKMOVPSYmr:
25182
0
  case VMASKMOVPSYrm:
25183
0
  case VMASKMOVPSmr:
25184
0
  case VMASKMOVPSrm:
25185
0
    return true;
25186
0
  }
25187
0
  return false;
25188
0
}
25189
25190
0
bool isPMOVZXDQ(unsigned Opcode) {
25191
0
  switch (Opcode) {
25192
0
  case PMOVZXDQrm:
25193
0
  case PMOVZXDQrr:
25194
0
    return true;
25195
0
  }
25196
0
  return false;
25197
0
}
25198
25199
0
bool isVCVTPS2PH(unsigned Opcode) {
25200
0
  switch (Opcode) {
25201
0
  case VCVTPS2PHYmr:
25202
0
  case VCVTPS2PHYrr:
25203
0
  case VCVTPS2PHZ128mr:
25204
0
  case VCVTPS2PHZ128mrk:
25205
0
  case VCVTPS2PHZ128rr:
25206
0
  case VCVTPS2PHZ128rrk:
25207
0
  case VCVTPS2PHZ128rrkz:
25208
0
  case VCVTPS2PHZ256mr:
25209
0
  case VCVTPS2PHZ256mrk:
25210
0
  case VCVTPS2PHZ256rr:
25211
0
  case VCVTPS2PHZ256rrk:
25212
0
  case VCVTPS2PHZ256rrkz:
25213
0
  case VCVTPS2PHZmr:
25214
0
  case VCVTPS2PHZmrk:
25215
0
  case VCVTPS2PHZrr:
25216
0
  case VCVTPS2PHZrrb:
25217
0
  case VCVTPS2PHZrrbk:
25218
0
  case VCVTPS2PHZrrbkz:
25219
0
  case VCVTPS2PHZrrk:
25220
0
  case VCVTPS2PHZrrkz:
25221
0
  case VCVTPS2PHmr:
25222
0
  case VCVTPS2PHrr:
25223
0
    return true;
25224
0
  }
25225
0
  return false;
25226
0
}
25227
25228
0
bool isCVTDQ2PD(unsigned Opcode) {
25229
0
  switch (Opcode) {
25230
0
  case CVTDQ2PDrm:
25231
0
  case CVTDQ2PDrr:
25232
0
    return true;
25233
0
  }
25234
0
  return false;
25235
0
}
25236
25237
0
bool isVCVTSD2SS(unsigned Opcode) {
25238
0
  switch (Opcode) {
25239
0
  case VCVTSD2SSZrm_Int:
25240
0
  case VCVTSD2SSZrm_Intk:
25241
0
  case VCVTSD2SSZrm_Intkz:
25242
0
  case VCVTSD2SSZrr_Int:
25243
0
  case VCVTSD2SSZrr_Intk:
25244
0
  case VCVTSD2SSZrr_Intkz:
25245
0
  case VCVTSD2SSZrrb_Int:
25246
0
  case VCVTSD2SSZrrb_Intk:
25247
0
  case VCVTSD2SSZrrb_Intkz:
25248
0
  case VCVTSD2SSrm_Int:
25249
0
  case VCVTSD2SSrr_Int:
25250
0
    return true;
25251
0
  }
25252
0
  return false;
25253
0
}
25254
25255
0
bool isVFMSUB213PH(unsigned Opcode) {
25256
0
  switch (Opcode) {
25257
0
  case VFMSUB213PHZ128m:
25258
0
  case VFMSUB213PHZ128mb:
25259
0
  case VFMSUB213PHZ128mbk:
25260
0
  case VFMSUB213PHZ128mbkz:
25261
0
  case VFMSUB213PHZ128mk:
25262
0
  case VFMSUB213PHZ128mkz:
25263
0
  case VFMSUB213PHZ128r:
25264
0
  case VFMSUB213PHZ128rk:
25265
0
  case VFMSUB213PHZ128rkz:
25266
0
  case VFMSUB213PHZ256m:
25267
0
  case VFMSUB213PHZ256mb:
25268
0
  case VFMSUB213PHZ256mbk:
25269
0
  case VFMSUB213PHZ256mbkz:
25270
0
  case VFMSUB213PHZ256mk:
25271
0
  case VFMSUB213PHZ256mkz:
25272
0
  case VFMSUB213PHZ256r:
25273
0
  case VFMSUB213PHZ256rk:
25274
0
  case VFMSUB213PHZ256rkz:
25275
0
  case VFMSUB213PHZm:
25276
0
  case VFMSUB213PHZmb:
25277
0
  case VFMSUB213PHZmbk:
25278
0
  case VFMSUB213PHZmbkz:
25279
0
  case VFMSUB213PHZmk:
25280
0
  case VFMSUB213PHZmkz:
25281
0
  case VFMSUB213PHZr:
25282
0
  case VFMSUB213PHZrb:
25283
0
  case VFMSUB213PHZrbk:
25284
0
  case VFMSUB213PHZrbkz:
25285
0
  case VFMSUB213PHZrk:
25286
0
  case VFMSUB213PHZrkz:
25287
0
    return true;
25288
0
  }
25289
0
  return false;
25290
0
}
25291
25292
0
bool isVPROTB(unsigned Opcode) {
25293
0
  switch (Opcode) {
25294
0
  case VPROTBmi:
25295
0
  case VPROTBmr:
25296
0
  case VPROTBri:
25297
0
  case VPROTBrm:
25298
0
  case VPROTBrr:
25299
0
  case VPROTBrr_REV:
25300
0
    return true;
25301
0
  }
25302
0
  return false;
25303
0
}
25304
25305
0
bool isPINSRD(unsigned Opcode) {
25306
0
  switch (Opcode) {
25307
0
  case PINSRDrm:
25308
0
  case PINSRDrr:
25309
0
    return true;
25310
0
  }
25311
0
  return false;
25312
0
}
25313
25314
0
bool isVMXON(unsigned Opcode) {
25315
0
  return Opcode == VMXON;
25316
0
}
25317
25318
0
bool isVFCMULCSH(unsigned Opcode) {
25319
0
  switch (Opcode) {
25320
0
  case VFCMULCSHZrm:
25321
0
  case VFCMULCSHZrmk:
25322
0
  case VFCMULCSHZrmkz:
25323
0
  case VFCMULCSHZrr:
25324
0
  case VFCMULCSHZrrb:
25325
0
  case VFCMULCSHZrrbk:
25326
0
  case VFCMULCSHZrrbkz:
25327
0
  case VFCMULCSHZrrk:
25328
0
  case VFCMULCSHZrrkz:
25329
0
    return true;
25330
0
  }
25331
0
  return false;
25332
0
}
25333
25334
0
bool isVFMULCSH(unsigned Opcode) {
25335
0
  switch (Opcode) {
25336
0
  case VFMULCSHZrm:
25337
0
  case VFMULCSHZrmk:
25338
0
  case VFMULCSHZrmkz:
25339
0
  case VFMULCSHZrr:
25340
0
  case VFMULCSHZrrb:
25341
0
  case VFMULCSHZrrbk:
25342
0
  case VFMULCSHZrrbkz:
25343
0
  case VFMULCSHZrrk:
25344
0
  case VFMULCSHZrrkz:
25345
0
    return true;
25346
0
  }
25347
0
  return false;
25348
0
}
25349
25350
0
bool isVRANGEPD(unsigned Opcode) {
25351
0
  switch (Opcode) {
25352
0
  case VRANGEPDZ128rmbi:
25353
0
  case VRANGEPDZ128rmbik:
25354
0
  case VRANGEPDZ128rmbikz:
25355
0
  case VRANGEPDZ128rmi:
25356
0
  case VRANGEPDZ128rmik:
25357
0
  case VRANGEPDZ128rmikz:
25358
0
  case VRANGEPDZ128rri:
25359
0
  case VRANGEPDZ128rrik:
25360
0
  case VRANGEPDZ128rrikz:
25361
0
  case VRANGEPDZ256rmbi:
25362
0
  case VRANGEPDZ256rmbik:
25363
0
  case VRANGEPDZ256rmbikz:
25364
0
  case VRANGEPDZ256rmi:
25365
0
  case VRANGEPDZ256rmik:
25366
0
  case VRANGEPDZ256rmikz:
25367
0
  case VRANGEPDZ256rri:
25368
0
  case VRANGEPDZ256rrik:
25369
0
  case VRANGEPDZ256rrikz:
25370
0
  case VRANGEPDZrmbi:
25371
0
  case VRANGEPDZrmbik:
25372
0
  case VRANGEPDZrmbikz:
25373
0
  case VRANGEPDZrmi:
25374
0
  case VRANGEPDZrmik:
25375
0
  case VRANGEPDZrmikz:
25376
0
  case VRANGEPDZrri:
25377
0
  case VRANGEPDZrrib:
25378
0
  case VRANGEPDZrribk:
25379
0
  case VRANGEPDZrribkz:
25380
0
  case VRANGEPDZrrik:
25381
0
  case VRANGEPDZrrikz:
25382
0
    return true;
25383
0
  }
25384
0
  return false;
25385
0
}
25386
25387
0
bool isCMC(unsigned Opcode) {
25388
0
  return Opcode == CMC;
25389
0
}
25390
25391
0
bool isSHA256MSG1(unsigned Opcode) {
25392
0
  switch (Opcode) {
25393
0
  case SHA256MSG1rm:
25394
0
  case SHA256MSG1rm_EVEX:
25395
0
  case SHA256MSG1rr:
25396
0
  case SHA256MSG1rr_EVEX:
25397
0
    return true;
25398
0
  }
25399
0
  return false;
25400
0
}
25401
25402
0
bool isFLD1(unsigned Opcode) {
25403
0
  return Opcode == LD_F1;
25404
0
}
25405
25406
0
bool isCMPPS(unsigned Opcode) {
25407
0
  switch (Opcode) {
25408
0
  case CMPPSrmi:
25409
0
  case CMPPSrri:
25410
0
    return true;
25411
0
  }
25412
0
  return false;
25413
0
}
25414
25415
0
bool isVPAVGW(unsigned Opcode) {
25416
0
  switch (Opcode) {
25417
0
  case VPAVGWYrm:
25418
0
  case VPAVGWYrr:
25419
0
  case VPAVGWZ128rm:
25420
0
  case VPAVGWZ128rmk:
25421
0
  case VPAVGWZ128rmkz:
25422
0
  case VPAVGWZ128rr:
25423
0
  case VPAVGWZ128rrk:
25424
0
  case VPAVGWZ128rrkz:
25425
0
  case VPAVGWZ256rm:
25426
0
  case VPAVGWZ256rmk:
25427
0
  case VPAVGWZ256rmkz:
25428
0
  case VPAVGWZ256rr:
25429
0
  case VPAVGWZ256rrk:
25430
0
  case VPAVGWZ256rrkz:
25431
0
  case VPAVGWZrm:
25432
0
  case VPAVGWZrmk:
25433
0
  case VPAVGWZrmkz:
25434
0
  case VPAVGWZrr:
25435
0
  case VPAVGWZrrk:
25436
0
  case VPAVGWZrrkz:
25437
0
  case VPAVGWrm:
25438
0
  case VPAVGWrr:
25439
0
    return true;
25440
0
  }
25441
0
  return false;
25442
0
}
25443
25444
0
bool isVFMADD213SH(unsigned Opcode) {
25445
0
  switch (Opcode) {
25446
0
  case VFMADD213SHZm_Int:
25447
0
  case VFMADD213SHZm_Intk:
25448
0
  case VFMADD213SHZm_Intkz:
25449
0
  case VFMADD213SHZr_Int:
25450
0
  case VFMADD213SHZr_Intk:
25451
0
  case VFMADD213SHZr_Intkz:
25452
0
  case VFMADD213SHZrb_Int:
25453
0
  case VFMADD213SHZrb_Intk:
25454
0
  case VFMADD213SHZrb_Intkz:
25455
0
    return true;
25456
0
  }
25457
0
  return false;
25458
0
}
25459
25460
0
bool isVPINSRQ(unsigned Opcode) {
25461
0
  switch (Opcode) {
25462
0
  case VPINSRQZrm:
25463
0
  case VPINSRQZrr:
25464
0
  case VPINSRQrm:
25465
0
  case VPINSRQrr:
25466
0
    return true;
25467
0
  }
25468
0
  return false;
25469
0
}
25470
25471
0
bool isMOVABS(unsigned Opcode) {
25472
0
  switch (Opcode) {
25473
0
  case MOV16ao64:
25474
0
  case MOV16o64a:
25475
0
  case MOV32ao64:
25476
0
  case MOV32o64a:
25477
0
  case MOV64ao64:
25478
0
  case MOV64o64a:
25479
0
  case MOV64ri:
25480
0
  case MOV8ao64:
25481
0
  case MOV8o64a:
25482
0
    return true;
25483
0
  }
25484
0
  return false;
25485
0
}
25486
25487
0
bool isVPSHAQ(unsigned Opcode) {
25488
0
  switch (Opcode) {
25489
0
  case VPSHAQmr:
25490
0
  case VPSHAQrm:
25491
0
  case VPSHAQrr:
25492
0
  case VPSHAQrr_REV:
25493
0
    return true;
25494
0
  }
25495
0
  return false;
25496
0
}
25497
25498
0
bool isRDTSCP(unsigned Opcode) {
25499
0
  return Opcode == RDTSCP;
25500
0
}
25501
25502
0
bool isVFNMADD231SS(unsigned Opcode) {
25503
0
  switch (Opcode) {
25504
0
  case VFNMADD231SSZm_Int:
25505
0
  case VFNMADD231SSZm_Intk:
25506
0
  case VFNMADD231SSZm_Intkz:
25507
0
  case VFNMADD231SSZr_Int:
25508
0
  case VFNMADD231SSZr_Intk:
25509
0
  case VFNMADD231SSZr_Intkz:
25510
0
  case VFNMADD231SSZrb_Int:
25511
0
  case VFNMADD231SSZrb_Intk:
25512
0
  case VFNMADD231SSZrb_Intkz:
25513
0
  case VFNMADD231SSm_Int:
25514
0
  case VFNMADD231SSr_Int:
25515
0
    return true;
25516
0
  }
25517
0
  return false;
25518
0
}
25519
25520
0
bool isTEST(unsigned Opcode) {
25521
0
  switch (Opcode) {
25522
0
  case TEST16i16:
25523
0
  case TEST16mi:
25524
0
  case TEST16mr:
25525
0
  case TEST16ri:
25526
0
  case TEST16rr:
25527
0
  case TEST32i32:
25528
0
  case TEST32mi:
25529
0
  case TEST32mr:
25530
0
  case TEST32ri:
25531
0
  case TEST32rr:
25532
0
  case TEST64i32:
25533
0
  case TEST64mi32:
25534
0
  case TEST64mr:
25535
0
  case TEST64ri32:
25536
0
  case TEST64rr:
25537
0
  case TEST8i8:
25538
0
  case TEST8mi:
25539
0
  case TEST8mr:
25540
0
  case TEST8ri:
25541
0
  case TEST8rr:
25542
0
    return true;
25543
0
  }
25544
0
  return false;
25545
0
}
25546
25547
0
bool isVPERMD(unsigned Opcode) {
25548
0
  switch (Opcode) {
25549
0
  case VPERMDYrm:
25550
0
  case VPERMDYrr:
25551
0
  case VPERMDZ256rm:
25552
0
  case VPERMDZ256rmb:
25553
0
  case VPERMDZ256rmbk:
25554
0
  case VPERMDZ256rmbkz:
25555
0
  case VPERMDZ256rmk:
25556
0
  case VPERMDZ256rmkz:
25557
0
  case VPERMDZ256rr:
25558
0
  case VPERMDZ256rrk:
25559
0
  case VPERMDZ256rrkz:
25560
0
  case VPERMDZrm:
25561
0
  case VPERMDZrmb:
25562
0
  case VPERMDZrmbk:
25563
0
  case VPERMDZrmbkz:
25564
0
  case VPERMDZrmk:
25565
0
  case VPERMDZrmkz:
25566
0
  case VPERMDZrr:
25567
0
  case VPERMDZrrk:
25568
0
  case VPERMDZrrkz:
25569
0
    return true;
25570
0
  }
25571
0
  return false;
25572
0
}
25573
25574
0
bool isVBCSTNESH2PS(unsigned Opcode) {
25575
0
  switch (Opcode) {
25576
0
  case VBCSTNESH2PSYrm:
25577
0
  case VBCSTNESH2PSrm:
25578
0
    return true;
25579
0
  }
25580
0
  return false;
25581
0
}
25582
25583
0
bool isVGATHERPF0QPD(unsigned Opcode) {
25584
0
  return Opcode == VGATHERPF0QPDm;
25585
0
}
25586
25587
0
bool isVPERM2I128(unsigned Opcode) {
25588
0
  switch (Opcode) {
25589
0
  case VPERM2I128rm:
25590
0
  case VPERM2I128rr:
25591
0
    return true;
25592
0
  }
25593
0
  return false;
25594
0
}
25595
25596
0
bool isVMPSADBW(unsigned Opcode) {
25597
0
  switch (Opcode) {
25598
0
  case VMPSADBWYrmi:
25599
0
  case VMPSADBWYrri:
25600
0
  case VMPSADBWrmi:
25601
0
  case VMPSADBWrri:
25602
0
    return true;
25603
0
  }
25604
0
  return false;
25605
0
}
25606
25607
0
bool isVFNMSUB231PD(unsigned Opcode) {
25608
0
  switch (Opcode) {
25609
0
  case VFNMSUB231PDYm:
25610
0
  case VFNMSUB231PDYr:
25611
0
  case VFNMSUB231PDZ128m:
25612
0
  case VFNMSUB231PDZ128mb:
25613
0
  case VFNMSUB231PDZ128mbk:
25614
0
  case VFNMSUB231PDZ128mbkz:
25615
0
  case VFNMSUB231PDZ128mk:
25616
0
  case VFNMSUB231PDZ128mkz:
25617
0
  case VFNMSUB231PDZ128r:
25618
0
  case VFNMSUB231PDZ128rk:
25619
0
  case VFNMSUB231PDZ128rkz:
25620
0
  case VFNMSUB231PDZ256m:
25621
0
  case VFNMSUB231PDZ256mb:
25622
0
  case VFNMSUB231PDZ256mbk:
25623
0
  case VFNMSUB231PDZ256mbkz:
25624
0
  case VFNMSUB231PDZ256mk:
25625
0
  case VFNMSUB231PDZ256mkz:
25626
0
  case VFNMSUB231PDZ256r:
25627
0
  case VFNMSUB231PDZ256rk:
25628
0
  case VFNMSUB231PDZ256rkz:
25629
0
  case VFNMSUB231PDZm:
25630
0
  case VFNMSUB231PDZmb:
25631
0
  case VFNMSUB231PDZmbk:
25632
0
  case VFNMSUB231PDZmbkz:
25633
0
  case VFNMSUB231PDZmk:
25634
0
  case VFNMSUB231PDZmkz:
25635
0
  case VFNMSUB231PDZr:
25636
0
  case VFNMSUB231PDZrb:
25637
0
  case VFNMSUB231PDZrbk:
25638
0
  case VFNMSUB231PDZrbkz:
25639
0
  case VFNMSUB231PDZrk:
25640
0
  case VFNMSUB231PDZrkz:
25641
0
  case VFNMSUB231PDm:
25642
0
  case VFNMSUB231PDr:
25643
0
    return true;
25644
0
  }
25645
0
  return false;
25646
0
}
25647
25648
0
bool isPADDSB(unsigned Opcode) {
25649
0
  switch (Opcode) {
25650
0
  case MMX_PADDSBrm:
25651
0
  case MMX_PADDSBrr:
25652
0
  case PADDSBrm:
25653
0
  case PADDSBrr:
25654
0
    return true;
25655
0
  }
25656
0
  return false;
25657
0
}
25658
25659
0
bool isMWAITX(unsigned Opcode) {
25660
0
  return Opcode == MWAITXrrr;
25661
0
}
25662
25663
0
bool isMONITORX(unsigned Opcode) {
25664
0
  switch (Opcode) {
25665
0
  case MONITORX32rrr:
25666
0
  case MONITORX64rrr:
25667
0
    return true;
25668
0
  }
25669
0
  return false;
25670
0
}
25671
25672
0
bool isVPEXPANDD(unsigned Opcode) {
25673
0
  switch (Opcode) {
25674
0
  case VPEXPANDDZ128rm:
25675
0
  case VPEXPANDDZ128rmk:
25676
0
  case VPEXPANDDZ128rmkz:
25677
0
  case VPEXPANDDZ128rr:
25678
0
  case VPEXPANDDZ128rrk:
25679
0
  case VPEXPANDDZ128rrkz:
25680
0
  case VPEXPANDDZ256rm:
25681
0
  case VPEXPANDDZ256rmk:
25682
0
  case VPEXPANDDZ256rmkz:
25683
0
  case VPEXPANDDZ256rr:
25684
0
  case VPEXPANDDZ256rrk:
25685
0
  case VPEXPANDDZ256rrkz:
25686
0
  case VPEXPANDDZrm:
25687
0
  case VPEXPANDDZrmk:
25688
0
  case VPEXPANDDZrmkz:
25689
0
  case VPEXPANDDZrr:
25690
0
  case VPEXPANDDZrrk:
25691
0
  case VPEXPANDDZrrkz:
25692
0
    return true;
25693
0
  }
25694
0
  return false;
25695
0
}
25696
25697
0
bool isVFRCZPD(unsigned Opcode) {
25698
0
  switch (Opcode) {
25699
0
  case VFRCZPDYrm:
25700
0
  case VFRCZPDYrr:
25701
0
  case VFRCZPDrm:
25702
0
  case VFRCZPDrr:
25703
0
    return true;
25704
0
  }
25705
0
  return false;
25706
0
}
25707
25708
0
bool isVRCPPH(unsigned Opcode) {
25709
0
  switch (Opcode) {
25710
0
  case VRCPPHZ128m:
25711
0
  case VRCPPHZ128mb:
25712
0
  case VRCPPHZ128mbk:
25713
0
  case VRCPPHZ128mbkz:
25714
0
  case VRCPPHZ128mk:
25715
0
  case VRCPPHZ128mkz:
25716
0
  case VRCPPHZ128r:
25717
0
  case VRCPPHZ128rk:
25718
0
  case VRCPPHZ128rkz:
25719
0
  case VRCPPHZ256m:
25720
0
  case VRCPPHZ256mb:
25721
0
  case VRCPPHZ256mbk:
25722
0
  case VRCPPHZ256mbkz:
25723
0
  case VRCPPHZ256mk:
25724
0
  case VRCPPHZ256mkz:
25725
0
  case VRCPPHZ256r:
25726
0
  case VRCPPHZ256rk:
25727
0
  case VRCPPHZ256rkz:
25728
0
  case VRCPPHZm:
25729
0
  case VRCPPHZmb:
25730
0
  case VRCPPHZmbk:
25731
0
  case VRCPPHZmbkz:
25732
0
  case VRCPPHZmk:
25733
0
  case VRCPPHZmkz:
25734
0
  case VRCPPHZr:
25735
0
  case VRCPPHZrk:
25736
0
  case VRCPPHZrkz:
25737
0
    return true;
25738
0
  }
25739
0
  return false;
25740
0
}
25741
25742
0
bool isFEMMS(unsigned Opcode) {
25743
0
  return Opcode == FEMMS;
25744
0
}
25745
25746
0
bool isVSCATTERQPD(unsigned Opcode) {
25747
0
  switch (Opcode) {
25748
0
  case VSCATTERQPDZ128mr:
25749
0
  case VSCATTERQPDZ256mr:
25750
0
  case VSCATTERQPDZmr:
25751
0
    return true;
25752
0
  }
25753
0
  return false;
25754
0
}
25755
25756
0
bool isVMOVW(unsigned Opcode) {
25757
0
  switch (Opcode) {
25758
0
  case VMOVSH2Wrr:
25759
0
  case VMOVSHtoW64rr:
25760
0
  case VMOVW2SHrr:
25761
0
  case VMOVW64toSHrr:
25762
0
  case VMOVWmr:
25763
0
  case VMOVWrm:
25764
0
    return true;
25765
0
  }
25766
0
  return false;
25767
0
}
25768
25769
0
bool isVPBROADCASTD(unsigned Opcode) {
25770
0
  switch (Opcode) {
25771
0
  case VPBROADCASTDYrm:
25772
0
  case VPBROADCASTDYrr:
25773
0
  case VPBROADCASTDZ128rm:
25774
0
  case VPBROADCASTDZ128rmk:
25775
0
  case VPBROADCASTDZ128rmkz:
25776
0
  case VPBROADCASTDZ128rr:
25777
0
  case VPBROADCASTDZ128rrk:
25778
0
  case VPBROADCASTDZ128rrkz:
25779
0
  case VPBROADCASTDZ256rm:
25780
0
  case VPBROADCASTDZ256rmk:
25781
0
  case VPBROADCASTDZ256rmkz:
25782
0
  case VPBROADCASTDZ256rr:
25783
0
  case VPBROADCASTDZ256rrk:
25784
0
  case VPBROADCASTDZ256rrkz:
25785
0
  case VPBROADCASTDZrm:
25786
0
  case VPBROADCASTDZrmk:
25787
0
  case VPBROADCASTDZrmkz:
25788
0
  case VPBROADCASTDZrr:
25789
0
  case VPBROADCASTDZrrk:
25790
0
  case VPBROADCASTDZrrkz:
25791
0
  case VPBROADCASTDrZ128rr:
25792
0
  case VPBROADCASTDrZ128rrk:
25793
0
  case VPBROADCASTDrZ128rrkz:
25794
0
  case VPBROADCASTDrZ256rr:
25795
0
  case VPBROADCASTDrZ256rrk:
25796
0
  case VPBROADCASTDrZ256rrkz:
25797
0
  case VPBROADCASTDrZrr:
25798
0
  case VPBROADCASTDrZrrk:
25799
0
  case VPBROADCASTDrZrrkz:
25800
0
  case VPBROADCASTDrm:
25801
0
  case VPBROADCASTDrr:
25802
0
    return true;
25803
0
  }
25804
0
  return false;
25805
0
}
25806
25807
0
bool isSTOSB(unsigned Opcode) {
25808
0
  return Opcode == STOSB;
25809
0
}
25810
25811
0
bool isFUCOMI(unsigned Opcode) {
25812
0
  return Opcode == UCOM_FIr;
25813
0
}
25814
25815
0
bool isVBROADCASTI64X4(unsigned Opcode) {
25816
0
  switch (Opcode) {
25817
0
  case VBROADCASTI64X4rm:
25818
0
  case VBROADCASTI64X4rmk:
25819
0
  case VBROADCASTI64X4rmkz:
25820
0
    return true;
25821
0
  }
25822
0
  return false;
25823
0
}
25824
25825
0
bool isFCMOVU(unsigned Opcode) {
25826
0
  return Opcode == CMOVP_F;
25827
0
}
25828
25829
0
bool isPSHUFLW(unsigned Opcode) {
25830
0
  switch (Opcode) {
25831
0
  case PSHUFLWmi:
25832
0
  case PSHUFLWri:
25833
0
    return true;
25834
0
  }
25835
0
  return false;
25836
0
}
25837
25838
0
bool isCVTPI2PS(unsigned Opcode) {
25839
0
  switch (Opcode) {
25840
0
  case MMX_CVTPI2PSrm:
25841
0
  case MMX_CVTPI2PSrr:
25842
0
    return true;
25843
0
  }
25844
0
  return false;
25845
0
}
25846
25847
0
bool isVFMADD231SH(unsigned Opcode) {
25848
0
  switch (Opcode) {
25849
0
  case VFMADD231SHZm_Int:
25850
0
  case VFMADD231SHZm_Intk:
25851
0
  case VFMADD231SHZm_Intkz:
25852
0
  case VFMADD231SHZr_Int:
25853
0
  case VFMADD231SHZr_Intk:
25854
0
  case VFMADD231SHZr_Intkz:
25855
0
  case VFMADD231SHZrb_Int:
25856
0
  case VFMADD231SHZrb_Intk:
25857
0
  case VFMADD231SHZrb_Intkz:
25858
0
    return true;
25859
0
  }
25860
0
  return false;
25861
0
}
25862
25863
0
bool isSYSCALL(unsigned Opcode) {
25864
0
  return Opcode == SYSCALL;
25865
0
}
25866
25867
0
bool isVPOPCNTB(unsigned Opcode) {
25868
0
  switch (Opcode) {
25869
0
  case VPOPCNTBZ128rm:
25870
0
  case VPOPCNTBZ128rmk:
25871
0
  case VPOPCNTBZ128rmkz:
25872
0
  case VPOPCNTBZ128rr:
25873
0
  case VPOPCNTBZ128rrk:
25874
0
  case VPOPCNTBZ128rrkz:
25875
0
  case VPOPCNTBZ256rm:
25876
0
  case VPOPCNTBZ256rmk:
25877
0
  case VPOPCNTBZ256rmkz:
25878
0
  case VPOPCNTBZ256rr:
25879
0
  case VPOPCNTBZ256rrk:
25880
0
  case VPOPCNTBZ256rrkz:
25881
0
  case VPOPCNTBZrm:
25882
0
  case VPOPCNTBZrmk:
25883
0
  case VPOPCNTBZrmkz:
25884
0
  case VPOPCNTBZrr:
25885
0
  case VPOPCNTBZrrk:
25886
0
  case VPOPCNTBZrrkz:
25887
0
    return true;
25888
0
  }
25889
0
  return false;
25890
0
}
25891
25892
0
bool isPMOVZXBW(unsigned Opcode) {
25893
0
  switch (Opcode) {
25894
0
  case PMOVZXBWrm:
25895
0
  case PMOVZXBWrr:
25896
0
    return true;
25897
0
  }
25898
0
  return false;
25899
0
}
25900
25901
0
bool isVCVTDQ2PS(unsigned Opcode) {
25902
0
  switch (Opcode) {
25903
0
  case VCVTDQ2PSYrm:
25904
0
  case VCVTDQ2PSYrr:
25905
0
  case VCVTDQ2PSZ128rm:
25906
0
  case VCVTDQ2PSZ128rmb:
25907
0
  case VCVTDQ2PSZ128rmbk:
25908
0
  case VCVTDQ2PSZ128rmbkz:
25909
0
  case VCVTDQ2PSZ128rmk:
25910
0
  case VCVTDQ2PSZ128rmkz:
25911
0
  case VCVTDQ2PSZ128rr:
25912
0
  case VCVTDQ2PSZ128rrk:
25913
0
  case VCVTDQ2PSZ128rrkz:
25914
0
  case VCVTDQ2PSZ256rm:
25915
0
  case VCVTDQ2PSZ256rmb:
25916
0
  case VCVTDQ2PSZ256rmbk:
25917
0
  case VCVTDQ2PSZ256rmbkz:
25918
0
  case VCVTDQ2PSZ256rmk:
25919
0
  case VCVTDQ2PSZ256rmkz:
25920
0
  case VCVTDQ2PSZ256rr:
25921
0
  case VCVTDQ2PSZ256rrk:
25922
0
  case VCVTDQ2PSZ256rrkz:
25923
0
  case VCVTDQ2PSZrm:
25924
0
  case VCVTDQ2PSZrmb:
25925
0
  case VCVTDQ2PSZrmbk:
25926
0
  case VCVTDQ2PSZrmbkz:
25927
0
  case VCVTDQ2PSZrmk:
25928
0
  case VCVTDQ2PSZrmkz:
25929
0
  case VCVTDQ2PSZrr:
25930
0
  case VCVTDQ2PSZrrb:
25931
0
  case VCVTDQ2PSZrrbk:
25932
0
  case VCVTDQ2PSZrrbkz:
25933
0
  case VCVTDQ2PSZrrk:
25934
0
  case VCVTDQ2PSZrrkz:
25935
0
  case VCVTDQ2PSrm:
25936
0
  case VCVTDQ2PSrr:
25937
0
    return true;
25938
0
  }
25939
0
  return false;
25940
0
}
25941
25942
0
bool isPSUBD(unsigned Opcode) {
25943
0
  switch (Opcode) {
25944
0
  case MMX_PSUBDrm:
25945
0
  case MMX_PSUBDrr:
25946
0
  case PSUBDrm:
25947
0
  case PSUBDrr:
25948
0
    return true;
25949
0
  }
25950
0
  return false;
25951
0
}
25952
25953
0
bool isVPCMPEQW(unsigned Opcode) {
25954
0
  switch (Opcode) {
25955
0
  case VPCMPEQWYrm:
25956
0
  case VPCMPEQWYrr:
25957
0
  case VPCMPEQWZ128rm:
25958
0
  case VPCMPEQWZ128rmk:
25959
0
  case VPCMPEQWZ128rr:
25960
0
  case VPCMPEQWZ128rrk:
25961
0
  case VPCMPEQWZ256rm:
25962
0
  case VPCMPEQWZ256rmk:
25963
0
  case VPCMPEQWZ256rr:
25964
0
  case VPCMPEQWZ256rrk:
25965
0
  case VPCMPEQWZrm:
25966
0
  case VPCMPEQWZrmk:
25967
0
  case VPCMPEQWZrr:
25968
0
  case VPCMPEQWZrrk:
25969
0
  case VPCMPEQWrm:
25970
0
  case VPCMPEQWrr:
25971
0
    return true;
25972
0
  }
25973
0
  return false;
25974
0
}
25975
25976
0
bool isMOVSW(unsigned Opcode) {
25977
0
  return Opcode == MOVSW;
25978
0
}
25979
25980
0
bool isVSM3RNDS2(unsigned Opcode) {
25981
0
  switch (Opcode) {
25982
0
  case VSM3RNDS2rm:
25983
0
  case VSM3RNDS2rr:
25984
0
    return true;
25985
0
  }
25986
0
  return false;
25987
0
}
25988
25989
0
bool isVPMOVUSQD(unsigned Opcode) {
25990
0
  switch (Opcode) {
25991
0
  case VPMOVUSQDZ128mr:
25992
0
  case VPMOVUSQDZ128mrk:
25993
0
  case VPMOVUSQDZ128rr:
25994
0
  case VPMOVUSQDZ128rrk:
25995
0
  case VPMOVUSQDZ128rrkz:
25996
0
  case VPMOVUSQDZ256mr:
25997
0
  case VPMOVUSQDZ256mrk:
25998
0
  case VPMOVUSQDZ256rr:
25999
0
  case VPMOVUSQDZ256rrk:
26000
0
  case VPMOVUSQDZ256rrkz:
26001
0
  case VPMOVUSQDZmr:
26002
0
  case VPMOVUSQDZmrk:
26003
0
  case VPMOVUSQDZrr:
26004
0
  case VPMOVUSQDZrrk:
26005
0
  case VPMOVUSQDZrrkz:
26006
0
    return true;
26007
0
  }
26008
0
  return false;
26009
0
}
26010
26011
0
bool isCVTTPD2DQ(unsigned Opcode) {
26012
0
  switch (Opcode) {
26013
0
  case CVTTPD2DQrm:
26014
0
  case CVTTPD2DQrr:
26015
0
    return true;
26016
0
  }
26017
0
  return false;
26018
0
}
26019
26020
0
bool isVPEXPANDW(unsigned Opcode) {
26021
0
  switch (Opcode) {
26022
0
  case VPEXPANDWZ128rm:
26023
0
  case VPEXPANDWZ128rmk:
26024
0
  case VPEXPANDWZ128rmkz:
26025
0
  case VPEXPANDWZ128rr:
26026
0
  case VPEXPANDWZ128rrk:
26027
0
  case VPEXPANDWZ128rrkz:
26028
0
  case VPEXPANDWZ256rm:
26029
0
  case VPEXPANDWZ256rmk:
26030
0
  case VPEXPANDWZ256rmkz:
26031
0
  case VPEXPANDWZ256rr:
26032
0
  case VPEXPANDWZ256rrk:
26033
0
  case VPEXPANDWZ256rrkz:
26034
0
  case VPEXPANDWZrm:
26035
0
  case VPEXPANDWZrmk:
26036
0
  case VPEXPANDWZrmkz:
26037
0
  case VPEXPANDWZrr:
26038
0
  case VPEXPANDWZrrk:
26039
0
  case VPEXPANDWZrrkz:
26040
0
    return true;
26041
0
  }
26042
0
  return false;
26043
0
}
26044
26045
0
bool isVUCOMISH(unsigned Opcode) {
26046
0
  switch (Opcode) {
26047
0
  case VUCOMISHZrm:
26048
0
  case VUCOMISHZrr:
26049
0
  case VUCOMISHZrrb:
26050
0
    return true;
26051
0
  }
26052
0
  return false;
26053
0
}
26054
26055
0
bool isVZEROALL(unsigned Opcode) {
26056
0
  return Opcode == VZEROALL;
26057
0
}
26058
26059
0
bool isVPAND(unsigned Opcode) {
26060
0
  switch (Opcode) {
26061
0
  case VPANDYrm:
26062
0
  case VPANDYrr:
26063
0
  case VPANDrm:
26064
0
  case VPANDrr:
26065
0
    return true;
26066
0
  }
26067
0
  return false;
26068
0
}
26069
26070
0
bool isPMULDQ(unsigned Opcode) {
26071
0
  switch (Opcode) {
26072
0
  case PMULDQrm:
26073
0
  case PMULDQrr:
26074
0
    return true;
26075
0
  }
26076
0
  return false;
26077
0
}
26078
26079
0
bool isVPSHUFHW(unsigned Opcode) {
26080
0
  switch (Opcode) {
26081
0
  case VPSHUFHWYmi:
26082
0
  case VPSHUFHWYri:
26083
0
  case VPSHUFHWZ128mi:
26084
0
  case VPSHUFHWZ128mik:
26085
0
  case VPSHUFHWZ128mikz:
26086
0
  case VPSHUFHWZ128ri:
26087
0
  case VPSHUFHWZ128rik:
26088
0
  case VPSHUFHWZ128rikz:
26089
0
  case VPSHUFHWZ256mi:
26090
0
  case VPSHUFHWZ256mik:
26091
0
  case VPSHUFHWZ256mikz:
26092
0
  case VPSHUFHWZ256ri:
26093
0
  case VPSHUFHWZ256rik:
26094
0
  case VPSHUFHWZ256rikz:
26095
0
  case VPSHUFHWZmi:
26096
0
  case VPSHUFHWZmik:
26097
0
  case VPSHUFHWZmikz:
26098
0
  case VPSHUFHWZri:
26099
0
  case VPSHUFHWZrik:
26100
0
  case VPSHUFHWZrikz:
26101
0
  case VPSHUFHWmi:
26102
0
  case VPSHUFHWri:
26103
0
    return true;
26104
0
  }
26105
0
  return false;
26106
0
}
26107
26108
0
bool isVPALIGNR(unsigned Opcode) {
26109
0
  switch (Opcode) {
26110
0
  case VPALIGNRYrmi:
26111
0
  case VPALIGNRYrri:
26112
0
  case VPALIGNRZ128rmi:
26113
0
  case VPALIGNRZ128rmik:
26114
0
  case VPALIGNRZ128rmikz:
26115
0
  case VPALIGNRZ128rri:
26116
0
  case VPALIGNRZ128rrik:
26117
0
  case VPALIGNRZ128rrikz:
26118
0
  case VPALIGNRZ256rmi:
26119
0
  case VPALIGNRZ256rmik:
26120
0
  case VPALIGNRZ256rmikz:
26121
0
  case VPALIGNRZ256rri:
26122
0
  case VPALIGNRZ256rrik:
26123
0
  case VPALIGNRZ256rrikz:
26124
0
  case VPALIGNRZrmi:
26125
0
  case VPALIGNRZrmik:
26126
0
  case VPALIGNRZrmikz:
26127
0
  case VPALIGNRZrri:
26128
0
  case VPALIGNRZrrik:
26129
0
  case VPALIGNRZrrikz:
26130
0
  case VPALIGNRrmi:
26131
0
  case VPALIGNRrri:
26132
0
    return true;
26133
0
  }
26134
0
  return false;
26135
0
}
26136
26137
0
bool isSQRTSD(unsigned Opcode) {
26138
0
  switch (Opcode) {
26139
0
  case SQRTSDm_Int:
26140
0
  case SQRTSDr_Int:
26141
0
    return true;
26142
0
  }
26143
0
  return false;
26144
0
}
26145
26146
0
bool isVCVTTPH2UDQ(unsigned Opcode) {
26147
0
  switch (Opcode) {
26148
0
  case VCVTTPH2UDQZ128rm:
26149
0
  case VCVTTPH2UDQZ128rmb:
26150
0
  case VCVTTPH2UDQZ128rmbk:
26151
0
  case VCVTTPH2UDQZ128rmbkz:
26152
0
  case VCVTTPH2UDQZ128rmk:
26153
0
  case VCVTTPH2UDQZ128rmkz:
26154
0
  case VCVTTPH2UDQZ128rr:
26155
0
  case VCVTTPH2UDQZ128rrk:
26156
0
  case VCVTTPH2UDQZ128rrkz:
26157
0
  case VCVTTPH2UDQZ256rm:
26158
0
  case VCVTTPH2UDQZ256rmb:
26159
0
  case VCVTTPH2UDQZ256rmbk:
26160
0
  case VCVTTPH2UDQZ256rmbkz:
26161
0
  case VCVTTPH2UDQZ256rmk:
26162
0
  case VCVTTPH2UDQZ256rmkz:
26163
0
  case VCVTTPH2UDQZ256rr:
26164
0
  case VCVTTPH2UDQZ256rrk:
26165
0
  case VCVTTPH2UDQZ256rrkz:
26166
0
  case VCVTTPH2UDQZrm:
26167
0
  case VCVTTPH2UDQZrmb:
26168
0
  case VCVTTPH2UDQZrmbk:
26169
0
  case VCVTTPH2UDQZrmbkz:
26170
0
  case VCVTTPH2UDQZrmk:
26171
0
  case VCVTTPH2UDQZrmkz:
26172
0
  case VCVTTPH2UDQZrr:
26173
0
  case VCVTTPH2UDQZrrb:
26174
0
  case VCVTTPH2UDQZrrbk:
26175
0
  case VCVTTPH2UDQZrrbkz:
26176
0
  case VCVTTPH2UDQZrrk:
26177
0
  case VCVTTPH2UDQZrrkz:
26178
0
    return true;
26179
0
  }
26180
0
  return false;
26181
0
}
26182
26183
0
bool isVGETEXPPH(unsigned Opcode) {
26184
0
  switch (Opcode) {
26185
0
  case VGETEXPPHZ128m:
26186
0
  case VGETEXPPHZ128mb:
26187
0
  case VGETEXPPHZ128mbk:
26188
0
  case VGETEXPPHZ128mbkz:
26189
0
  case VGETEXPPHZ128mk:
26190
0
  case VGETEXPPHZ128mkz:
26191
0
  case VGETEXPPHZ128r:
26192
0
  case VGETEXPPHZ128rk:
26193
0
  case VGETEXPPHZ128rkz:
26194
0
  case VGETEXPPHZ256m:
26195
0
  case VGETEXPPHZ256mb:
26196
0
  case VGETEXPPHZ256mbk:
26197
0
  case VGETEXPPHZ256mbkz:
26198
0
  case VGETEXPPHZ256mk:
26199
0
  case VGETEXPPHZ256mkz:
26200
0
  case VGETEXPPHZ256r:
26201
0
  case VGETEXPPHZ256rk:
26202
0
  case VGETEXPPHZ256rkz:
26203
0
  case VGETEXPPHZm:
26204
0
  case VGETEXPPHZmb:
26205
0
  case VGETEXPPHZmbk:
26206
0
  case VGETEXPPHZmbkz:
26207
0
  case VGETEXPPHZmk:
26208
0
  case VGETEXPPHZmkz:
26209
0
  case VGETEXPPHZr:
26210
0
  case VGETEXPPHZrb:
26211
0
  case VGETEXPPHZrbk:
26212
0
  case VGETEXPPHZrbkz:
26213
0
  case VGETEXPPHZrk:
26214
0
  case VGETEXPPHZrkz:
26215
0
    return true;
26216
0
  }
26217
0
  return false;
26218
0
}
26219
26220
0
bool isADDPD(unsigned Opcode) {
26221
0
  switch (Opcode) {
26222
0
  case ADDPDrm:
26223
0
  case ADDPDrr:
26224
0
    return true;
26225
0
  }
26226
0
  return false;
26227
0
}
26228
26229
0
bool isVFNMADDPD(unsigned Opcode) {
26230
0
  switch (Opcode) {
26231
0
  case VFNMADDPD4Ymr:
26232
0
  case VFNMADDPD4Yrm:
26233
0
  case VFNMADDPD4Yrr:
26234
0
  case VFNMADDPD4Yrr_REV:
26235
0
  case VFNMADDPD4mr:
26236
0
  case VFNMADDPD4rm:
26237
0
  case VFNMADDPD4rr:
26238
0
  case VFNMADDPD4rr_REV:
26239
0
    return true;
26240
0
  }
26241
0
  return false;
26242
0
}
26243
26244
0
bool isSTTILECFG(unsigned Opcode) {
26245
0
  switch (Opcode) {
26246
0
  case STTILECFG:
26247
0
  case STTILECFG_EVEX:
26248
0
    return true;
26249
0
  }
26250
0
  return false;
26251
0
}
26252
26253
0
bool isVMINPD(unsigned Opcode) {
26254
0
  switch (Opcode) {
26255
0
  case VMINPDYrm:
26256
0
  case VMINPDYrr:
26257
0
  case VMINPDZ128rm:
26258
0
  case VMINPDZ128rmb:
26259
0
  case VMINPDZ128rmbk:
26260
0
  case VMINPDZ128rmbkz:
26261
0
  case VMINPDZ128rmk:
26262
0
  case VMINPDZ128rmkz:
26263
0
  case VMINPDZ128rr:
26264
0
  case VMINPDZ128rrk:
26265
0
  case VMINPDZ128rrkz:
26266
0
  case VMINPDZ256rm:
26267
0
  case VMINPDZ256rmb:
26268
0
  case VMINPDZ256rmbk:
26269
0
  case VMINPDZ256rmbkz:
26270
0
  case VMINPDZ256rmk:
26271
0
  case VMINPDZ256rmkz:
26272
0
  case VMINPDZ256rr:
26273
0
  case VMINPDZ256rrk:
26274
0
  case VMINPDZ256rrkz:
26275
0
  case VMINPDZrm:
26276
0
  case VMINPDZrmb:
26277
0
  case VMINPDZrmbk:
26278
0
  case VMINPDZrmbkz:
26279
0
  case VMINPDZrmk:
26280
0
  case VMINPDZrmkz:
26281
0
  case VMINPDZrr:
26282
0
  case VMINPDZrrb:
26283
0
  case VMINPDZrrbk:
26284
0
  case VMINPDZrrbkz:
26285
0
  case VMINPDZrrk:
26286
0
  case VMINPDZrrkz:
26287
0
  case VMINPDrm:
26288
0
  case VMINPDrr:
26289
0
    return true;
26290
0
  }
26291
0
  return false;
26292
0
}
26293
26294
0
bool isSHA1RNDS4(unsigned Opcode) {
26295
0
  switch (Opcode) {
26296
0
  case SHA1RNDS4rmi:
26297
0
  case SHA1RNDS4rmi_EVEX:
26298
0
  case SHA1RNDS4rri:
26299
0
  case SHA1RNDS4rri_EVEX:
26300
0
    return true;
26301
0
  }
26302
0
  return false;
26303
0
}
26304
26305
0
bool isPBLENDVB(unsigned Opcode) {
26306
0
  switch (Opcode) {
26307
0
  case PBLENDVBrm0:
26308
0
  case PBLENDVBrr0:
26309
0
    return true;
26310
0
  }
26311
0
  return false;
26312
0
}
26313
26314
0
bool isVBROADCASTF128(unsigned Opcode) {
26315
0
  return Opcode == VBROADCASTF128rm;
26316
0
}
26317
26318
0
bool isVPSHRDQ(unsigned Opcode) {
26319
0
  switch (Opcode) {
26320
0
  case VPSHRDQZ128rmbi:
26321
0
  case VPSHRDQZ128rmbik:
26322
0
  case VPSHRDQZ128rmbikz:
26323
0
  case VPSHRDQZ128rmi:
26324
0
  case VPSHRDQZ128rmik:
26325
0
  case VPSHRDQZ128rmikz:
26326
0
  case VPSHRDQZ128rri:
26327
0
  case VPSHRDQZ128rrik:
26328
0
  case VPSHRDQZ128rrikz:
26329
0
  case VPSHRDQZ256rmbi:
26330
0
  case VPSHRDQZ256rmbik:
26331
0
  case VPSHRDQZ256rmbikz:
26332
0
  case VPSHRDQZ256rmi:
26333
0
  case VPSHRDQZ256rmik:
26334
0
  case VPSHRDQZ256rmikz:
26335
0
  case VPSHRDQZ256rri:
26336
0
  case VPSHRDQZ256rrik:
26337
0
  case VPSHRDQZ256rrikz:
26338
0
  case VPSHRDQZrmbi:
26339
0
  case VPSHRDQZrmbik:
26340
0
  case VPSHRDQZrmbikz:
26341
0
  case VPSHRDQZrmi:
26342
0
  case VPSHRDQZrmik:
26343
0
  case VPSHRDQZrmikz:
26344
0
  case VPSHRDQZrri:
26345
0
  case VPSHRDQZrrik:
26346
0
  case VPSHRDQZrrikz:
26347
0
    return true;
26348
0
  }
26349
0
  return false;
26350
0
}
26351
26352
0
bool isVAESIMC(unsigned Opcode) {
26353
0
  switch (Opcode) {
26354
0
  case VAESIMCrm:
26355
0
  case VAESIMCrr:
26356
0
    return true;
26357
0
  }
26358
0
  return false;
26359
0
}
26360
26361
0
bool isCOMISD(unsigned Opcode) {
26362
0
  switch (Opcode) {
26363
0
  case COMISDrm:
26364
0
  case COMISDrr:
26365
0
    return true;
26366
0
  }
26367
0
  return false;
26368
0
}
26369
26370
0
bool isVMOVSH(unsigned Opcode) {
26371
0
  switch (Opcode) {
26372
0
  case VMOVSHZmr:
26373
0
  case VMOVSHZmrk:
26374
0
  case VMOVSHZrm:
26375
0
  case VMOVSHZrmk:
26376
0
  case VMOVSHZrmkz:
26377
0
  case VMOVSHZrr:
26378
0
  case VMOVSHZrr_REV:
26379
0
  case VMOVSHZrrk:
26380
0
  case VMOVSHZrrk_REV:
26381
0
  case VMOVSHZrrkz:
26382
0
  case VMOVSHZrrkz_REV:
26383
0
    return true;
26384
0
  }
26385
0
  return false;
26386
0
}
26387
26388
0
bool isPFSUBR(unsigned Opcode) {
26389
0
  switch (Opcode) {
26390
0
  case PFSUBRrm:
26391
0
  case PFSUBRrr:
26392
0
    return true;
26393
0
  }
26394
0
  return false;
26395
0
}
26396
26397
0
bool isRDSSPD(unsigned Opcode) {
26398
0
  return Opcode == RDSSPD;
26399
0
}
26400
26401
0
bool isWAIT(unsigned Opcode) {
26402
0
  return Opcode == WAIT;
26403
0
}
26404
26405
0
bool isVFPCLASSSS(unsigned Opcode) {
26406
0
  switch (Opcode) {
26407
0
  case VFPCLASSSSZrm:
26408
0
  case VFPCLASSSSZrmk:
26409
0
  case VFPCLASSSSZrr:
26410
0
  case VFPCLASSSSZrrk:
26411
0
    return true;
26412
0
  }
26413
0
  return false;
26414
0
}
26415
26416
0
bool isPCMPGTD(unsigned Opcode) {
26417
0
  switch (Opcode) {
26418
0
  case MMX_PCMPGTDrm:
26419
0
  case MMX_PCMPGTDrr:
26420
0
  case PCMPGTDrm:
26421
0
  case PCMPGTDrr:
26422
0
    return true;
26423
0
  }
26424
0
  return false;
26425
0
}
26426
26427
0
bool isVGATHERPF0QPS(unsigned Opcode) {
26428
0
  return Opcode == VGATHERPF0QPSm;
26429
0
}
26430
26431
0
bool isBLENDVPS(unsigned Opcode) {
26432
0
  switch (Opcode) {
26433
0
  case BLENDVPSrm0:
26434
0
  case BLENDVPSrr0:
26435
0
    return true;
26436
0
  }
26437
0
  return false;
26438
0
}
26439
26440
0
bool isVBROADCASTF32X4(unsigned Opcode) {
26441
0
  switch (Opcode) {
26442
0
  case VBROADCASTF32X4Z256rm:
26443
0
  case VBROADCASTF32X4Z256rmk:
26444
0
  case VBROADCASTF32X4Z256rmkz:
26445
0
  case VBROADCASTF32X4rm:
26446
0
  case VBROADCASTF32X4rmk:
26447
0
  case VBROADCASTF32X4rmkz:
26448
0
    return true;
26449
0
  }
26450
0
  return false;
26451
0
}
26452
26453
0
bool isVPMADD52LUQ(unsigned Opcode) {
26454
0
  switch (Opcode) {
26455
0
  case VPMADD52LUQYrm:
26456
0
  case VPMADD52LUQYrr:
26457
0
  case VPMADD52LUQZ128m:
26458
0
  case VPMADD52LUQZ128mb:
26459
0
  case VPMADD52LUQZ128mbk:
26460
0
  case VPMADD52LUQZ128mbkz:
26461
0
  case VPMADD52LUQZ128mk:
26462
0
  case VPMADD52LUQZ128mkz:
26463
0
  case VPMADD52LUQZ128r:
26464
0
  case VPMADD52LUQZ128rk:
26465
0
  case VPMADD52LUQZ128rkz:
26466
0
  case VPMADD52LUQZ256m:
26467
0
  case VPMADD52LUQZ256mb:
26468
0
  case VPMADD52LUQZ256mbk:
26469
0
  case VPMADD52LUQZ256mbkz:
26470
0
  case VPMADD52LUQZ256mk:
26471
0
  case VPMADD52LUQZ256mkz:
26472
0
  case VPMADD52LUQZ256r:
26473
0
  case VPMADD52LUQZ256rk:
26474
0
  case VPMADD52LUQZ256rkz:
26475
0
  case VPMADD52LUQZm:
26476
0
  case VPMADD52LUQZmb:
26477
0
  case VPMADD52LUQZmbk:
26478
0
  case VPMADD52LUQZmbkz:
26479
0
  case VPMADD52LUQZmk:
26480
0
  case VPMADD52LUQZmkz:
26481
0
  case VPMADD52LUQZr:
26482
0
  case VPMADD52LUQZrk:
26483
0
  case VPMADD52LUQZrkz:
26484
0
  case VPMADD52LUQrm:
26485
0
  case VPMADD52LUQrr:
26486
0
    return true;
26487
0
  }
26488
0
  return false;
26489
0
}
26490
26491
0
bool isVMOVLPD(unsigned Opcode) {
26492
0
  switch (Opcode) {
26493
0
  case VMOVLPDZ128mr:
26494
0
  case VMOVLPDZ128rm:
26495
0
  case VMOVLPDmr:
26496
0
  case VMOVLPDrm:
26497
0
    return true;
26498
0
  }
26499
0
  return false;
26500
0
}
26501
26502
0
bool isVMOVQ(unsigned Opcode) {
26503
0
  switch (Opcode) {
26504
0
  case VMOV64toPQIZrm:
26505
0
  case VMOV64toPQIZrr:
26506
0
  case VMOV64toPQIrm:
26507
0
  case VMOV64toPQIrr:
26508
0
  case VMOVPQI2QIZmr:
26509
0
  case VMOVPQI2QIZrr:
26510
0
  case VMOVPQI2QImr:
26511
0
  case VMOVPQI2QIrr:
26512
0
  case VMOVPQIto64Zmr:
26513
0
  case VMOVPQIto64Zrr:
26514
0
  case VMOVPQIto64mr:
26515
0
  case VMOVPQIto64rr:
26516
0
  case VMOVQI2PQIZrm:
26517
0
  case VMOVQI2PQIrm:
26518
0
  case VMOVZPQILo2PQIZrr:
26519
0
  case VMOVZPQILo2PQIrr:
26520
0
    return true;
26521
0
  }
26522
0
  return false;
26523
0
}
26524
26525
0
bool isVMOVDQU(unsigned Opcode) {
26526
0
  switch (Opcode) {
26527
0
  case VMOVDQUYmr:
26528
0
  case VMOVDQUYrm:
26529
0
  case VMOVDQUYrr:
26530
0
  case VMOVDQUYrr_REV:
26531
0
  case VMOVDQUmr:
26532
0
  case VMOVDQUrm:
26533
0
  case VMOVDQUrr:
26534
0
  case VMOVDQUrr_REV:
26535
0
    return true;
26536
0
  }
26537
0
  return false;
26538
0
}
26539
26540
0
bool isAESENC128KL(unsigned Opcode) {
26541
0
  return Opcode == AESENC128KL;
26542
0
}
26543
26544
0
bool isVFMADDSUB231PS(unsigned Opcode) {
26545
0
  switch (Opcode) {
26546
0
  case VFMADDSUB231PSYm:
26547
0
  case VFMADDSUB231PSYr:
26548
0
  case VFMADDSUB231PSZ128m:
26549
0
  case VFMADDSUB231PSZ128mb:
26550
0
  case VFMADDSUB231PSZ128mbk:
26551
0
  case VFMADDSUB231PSZ128mbkz:
26552
0
  case VFMADDSUB231PSZ128mk:
26553
0
  case VFMADDSUB231PSZ128mkz:
26554
0
  case VFMADDSUB231PSZ128r:
26555
0
  case VFMADDSUB231PSZ128rk:
26556
0
  case VFMADDSUB231PSZ128rkz:
26557
0
  case VFMADDSUB231PSZ256m:
26558
0
  case VFMADDSUB231PSZ256mb:
26559
0
  case VFMADDSUB231PSZ256mbk:
26560
0
  case VFMADDSUB231PSZ256mbkz:
26561
0
  case VFMADDSUB231PSZ256mk:
26562
0
  case VFMADDSUB231PSZ256mkz:
26563
0
  case VFMADDSUB231PSZ256r:
26564
0
  case VFMADDSUB231PSZ256rk:
26565
0
  case VFMADDSUB231PSZ256rkz:
26566
0
  case VFMADDSUB231PSZm:
26567
0
  case VFMADDSUB231PSZmb:
26568
0
  case VFMADDSUB231PSZmbk:
26569
0
  case VFMADDSUB231PSZmbkz:
26570
0
  case VFMADDSUB231PSZmk:
26571
0
  case VFMADDSUB231PSZmkz:
26572
0
  case VFMADDSUB231PSZr:
26573
0
  case VFMADDSUB231PSZrb:
26574
0
  case VFMADDSUB231PSZrbk:
26575
0
  case VFMADDSUB231PSZrbkz:
26576
0
  case VFMADDSUB231PSZrk:
26577
0
  case VFMADDSUB231PSZrkz:
26578
0
  case VFMADDSUB231PSm:
26579
0
  case VFMADDSUB231PSr:
26580
0
    return true;
26581
0
  }
26582
0
  return false;
26583
0
}
26584
26585
0
bool isVFNMSUB213PD(unsigned Opcode) {
26586
0
  switch (Opcode) {
26587
0
  case VFNMSUB213PDYm:
26588
0
  case VFNMSUB213PDYr:
26589
0
  case VFNMSUB213PDZ128m:
26590
0
  case VFNMSUB213PDZ128mb:
26591
0
  case VFNMSUB213PDZ128mbk:
26592
0
  case VFNMSUB213PDZ128mbkz:
26593
0
  case VFNMSUB213PDZ128mk:
26594
0
  case VFNMSUB213PDZ128mkz:
26595
0
  case VFNMSUB213PDZ128r:
26596
0
  case VFNMSUB213PDZ128rk:
26597
0
  case VFNMSUB213PDZ128rkz:
26598
0
  case VFNMSUB213PDZ256m:
26599
0
  case VFNMSUB213PDZ256mb:
26600
0
  case VFNMSUB213PDZ256mbk:
26601
0
  case VFNMSUB213PDZ256mbkz:
26602
0
  case VFNMSUB213PDZ256mk:
26603
0
  case VFNMSUB213PDZ256mkz:
26604
0
  case VFNMSUB213PDZ256r:
26605
0
  case VFNMSUB213PDZ256rk:
26606
0
  case VFNMSUB213PDZ256rkz:
26607
0
  case VFNMSUB213PDZm:
26608
0
  case VFNMSUB213PDZmb:
26609
0
  case VFNMSUB213PDZmbk:
26610
0
  case VFNMSUB213PDZmbkz:
26611
0
  case VFNMSUB213PDZmk:
26612
0
  case VFNMSUB213PDZmkz:
26613
0
  case VFNMSUB213PDZr:
26614
0
  case VFNMSUB213PDZrb:
26615
0
  case VFNMSUB213PDZrbk:
26616
0
  case VFNMSUB213PDZrbkz:
26617
0
  case VFNMSUB213PDZrk:
26618
0
  case VFNMSUB213PDZrkz:
26619
0
  case VFNMSUB213PDm:
26620
0
  case VFNMSUB213PDr:
26621
0
    return true;
26622
0
  }
26623
0
  return false;
26624
0
}
26625
26626
0
bool isVPCONFLICTD(unsigned Opcode) {
26627
0
  switch (Opcode) {
26628
0
  case VPCONFLICTDZ128rm:
26629
0
  case VPCONFLICTDZ128rmb:
26630
0
  case VPCONFLICTDZ128rmbk:
26631
0
  case VPCONFLICTDZ128rmbkz:
26632
0
  case VPCONFLICTDZ128rmk:
26633
0
  case VPCONFLICTDZ128rmkz:
26634
0
  case VPCONFLICTDZ128rr:
26635
0
  case VPCONFLICTDZ128rrk:
26636
0
  case VPCONFLICTDZ128rrkz:
26637
0
  case VPCONFLICTDZ256rm:
26638
0
  case VPCONFLICTDZ256rmb:
26639
0
  case VPCONFLICTDZ256rmbk:
26640
0
  case VPCONFLICTDZ256rmbkz:
26641
0
  case VPCONFLICTDZ256rmk:
26642
0
  case VPCONFLICTDZ256rmkz:
26643
0
  case VPCONFLICTDZ256rr:
26644
0
  case VPCONFLICTDZ256rrk:
26645
0
  case VPCONFLICTDZ256rrkz:
26646
0
  case VPCONFLICTDZrm:
26647
0
  case VPCONFLICTDZrmb:
26648
0
  case VPCONFLICTDZrmbk:
26649
0
  case VPCONFLICTDZrmbkz:
26650
0
  case VPCONFLICTDZrmk:
26651
0
  case VPCONFLICTDZrmkz:
26652
0
  case VPCONFLICTDZrr:
26653
0
  case VPCONFLICTDZrrk:
26654
0
  case VPCONFLICTDZrrkz:
26655
0
    return true;
26656
0
  }
26657
0
  return false;
26658
0
}
26659
26660
0
bool isVFMADDSUB213PH(unsigned Opcode) {
26661
0
  switch (Opcode) {
26662
0
  case VFMADDSUB213PHZ128m:
26663
0
  case VFMADDSUB213PHZ128mb:
26664
0
  case VFMADDSUB213PHZ128mbk:
26665
0
  case VFMADDSUB213PHZ128mbkz:
26666
0
  case VFMADDSUB213PHZ128mk:
26667
0
  case VFMADDSUB213PHZ128mkz:
26668
0
  case VFMADDSUB213PHZ128r:
26669
0
  case VFMADDSUB213PHZ128rk:
26670
0
  case VFMADDSUB213PHZ128rkz:
26671
0
  case VFMADDSUB213PHZ256m:
26672
0
  case VFMADDSUB213PHZ256mb:
26673
0
  case VFMADDSUB213PHZ256mbk:
26674
0
  case VFMADDSUB213PHZ256mbkz:
26675
0
  case VFMADDSUB213PHZ256mk:
26676
0
  case VFMADDSUB213PHZ256mkz:
26677
0
  case VFMADDSUB213PHZ256r:
26678
0
  case VFMADDSUB213PHZ256rk:
26679
0
  case VFMADDSUB213PHZ256rkz:
26680
0
  case VFMADDSUB213PHZm:
26681
0
  case VFMADDSUB213PHZmb:
26682
0
  case VFMADDSUB213PHZmbk:
26683
0
  case VFMADDSUB213PHZmbkz:
26684
0
  case VFMADDSUB213PHZmk:
26685
0
  case VFMADDSUB213PHZmkz:
26686
0
  case VFMADDSUB213PHZr:
26687
0
  case VFMADDSUB213PHZrb:
26688
0
  case VFMADDSUB213PHZrbk:
26689
0
  case VFMADDSUB213PHZrbkz:
26690
0
  case VFMADDSUB213PHZrk:
26691
0
  case VFMADDSUB213PHZrkz:
26692
0
    return true;
26693
0
  }
26694
0
  return false;
26695
0
}
26696
26697
0
bool isVPHSUBSW(unsigned Opcode) {
26698
0
  switch (Opcode) {
26699
0
  case VPHSUBSWYrm:
26700
0
  case VPHSUBSWYrr:
26701
0
  case VPHSUBSWrm:
26702
0
  case VPHSUBSWrr:
26703
0
    return true;
26704
0
  }
26705
0
  return false;
26706
0
}
26707
26708
0
bool isPUNPCKHDQ(unsigned Opcode) {
26709
0
  switch (Opcode) {
26710
0
  case MMX_PUNPCKHDQrm:
26711
0
  case MMX_PUNPCKHDQrr:
26712
0
  case PUNPCKHDQrm:
26713
0
  case PUNPCKHDQrr:
26714
0
    return true;
26715
0
  }
26716
0
  return false;
26717
0
}
26718
26719
0
bool isVSHUFI64X2(unsigned Opcode) {
26720
0
  switch (Opcode) {
26721
0
  case VSHUFI64X2Z256rmbi:
26722
0
  case VSHUFI64X2Z256rmbik:
26723
0
  case VSHUFI64X2Z256rmbikz:
26724
0
  case VSHUFI64X2Z256rmi:
26725
0
  case VSHUFI64X2Z256rmik:
26726
0
  case VSHUFI64X2Z256rmikz:
26727
0
  case VSHUFI64X2Z256rri:
26728
0
  case VSHUFI64X2Z256rrik:
26729
0
  case VSHUFI64X2Z256rrikz:
26730
0
  case VSHUFI64X2Zrmbi:
26731
0
  case VSHUFI64X2Zrmbik:
26732
0
  case VSHUFI64X2Zrmbikz:
26733
0
  case VSHUFI64X2Zrmi:
26734
0
  case VSHUFI64X2Zrmik:
26735
0
  case VSHUFI64X2Zrmikz:
26736
0
  case VSHUFI64X2Zrri:
26737
0
  case VSHUFI64X2Zrrik:
26738
0
  case VSHUFI64X2Zrrikz:
26739
0
    return true;
26740
0
  }
26741
0
  return false;
26742
0
}
26743
26744
0
bool isVFMSUBSD(unsigned Opcode) {
26745
0
  switch (Opcode) {
26746
0
  case VFMSUBSD4mr:
26747
0
  case VFMSUBSD4rm:
26748
0
  case VFMSUBSD4rr:
26749
0
  case VFMSUBSD4rr_REV:
26750
0
    return true;
26751
0
  }
26752
0
  return false;
26753
0
}
26754
26755
0
bool isVPORD(unsigned Opcode) {
26756
0
  switch (Opcode) {
26757
0
  case VPORDZ128rm:
26758
0
  case VPORDZ128rmb:
26759
0
  case VPORDZ128rmbk:
26760
0
  case VPORDZ128rmbkz:
26761
0
  case VPORDZ128rmk:
26762
0
  case VPORDZ128rmkz:
26763
0
  case VPORDZ128rr:
26764
0
  case VPORDZ128rrk:
26765
0
  case VPORDZ128rrkz:
26766
0
  case VPORDZ256rm:
26767
0
  case VPORDZ256rmb:
26768
0
  case VPORDZ256rmbk:
26769
0
  case VPORDZ256rmbkz:
26770
0
  case VPORDZ256rmk:
26771
0
  case VPORDZ256rmkz:
26772
0
  case VPORDZ256rr:
26773
0
  case VPORDZ256rrk:
26774
0
  case VPORDZ256rrkz:
26775
0
  case VPORDZrm:
26776
0
  case VPORDZrmb:
26777
0
  case VPORDZrmbk:
26778
0
  case VPORDZrmbkz:
26779
0
  case VPORDZrmk:
26780
0
  case VPORDZrmkz:
26781
0
  case VPORDZrr:
26782
0
  case VPORDZrrk:
26783
0
  case VPORDZrrkz:
26784
0
    return true;
26785
0
  }
26786
0
  return false;
26787
0
}
26788
26789
0
bool isRCPPS(unsigned Opcode) {
26790
0
  switch (Opcode) {
26791
0
  case RCPPSm:
26792
0
  case RCPPSr:
26793
0
    return true;
26794
0
  }
26795
0
  return false;
26796
0
}
26797
26798
0
bool isVEXTRACTI128(unsigned Opcode) {
26799
0
  switch (Opcode) {
26800
0
  case VEXTRACTI128mr:
26801
0
  case VEXTRACTI128rr:
26802
0
    return true;
26803
0
  }
26804
0
  return false;
26805
0
}
26806
26807
0
bool isVPSHRDVW(unsigned Opcode) {
26808
0
  switch (Opcode) {
26809
0
  case VPSHRDVWZ128m:
26810
0
  case VPSHRDVWZ128mk:
26811
0
  case VPSHRDVWZ128mkz:
26812
0
  case VPSHRDVWZ128r:
26813
0
  case VPSHRDVWZ128rk:
26814
0
  case VPSHRDVWZ128rkz:
26815
0
  case VPSHRDVWZ256m:
26816
0
  case VPSHRDVWZ256mk:
26817
0
  case VPSHRDVWZ256mkz:
26818
0
  case VPSHRDVWZ256r:
26819
0
  case VPSHRDVWZ256rk:
26820
0
  case VPSHRDVWZ256rkz:
26821
0
  case VPSHRDVWZm:
26822
0
  case VPSHRDVWZmk:
26823
0
  case VPSHRDVWZmkz:
26824
0
  case VPSHRDVWZr:
26825
0
  case VPSHRDVWZrk:
26826
0
  case VPSHRDVWZrkz:
26827
0
    return true;
26828
0
  }
26829
0
  return false;
26830
0
}
26831
26832
0
bool isVUNPCKLPD(unsigned Opcode) {
26833
0
  switch (Opcode) {
26834
0
  case VUNPCKLPDYrm:
26835
0
  case VUNPCKLPDYrr:
26836
0
  case VUNPCKLPDZ128rm:
26837
0
  case VUNPCKLPDZ128rmb:
26838
0
  case VUNPCKLPDZ128rmbk:
26839
0
  case VUNPCKLPDZ128rmbkz:
26840
0
  case VUNPCKLPDZ128rmk:
26841
0
  case VUNPCKLPDZ128rmkz:
26842
0
  case VUNPCKLPDZ128rr:
26843
0
  case VUNPCKLPDZ128rrk:
26844
0
  case VUNPCKLPDZ128rrkz:
26845
0
  case VUNPCKLPDZ256rm:
26846
0
  case VUNPCKLPDZ256rmb:
26847
0
  case VUNPCKLPDZ256rmbk:
26848
0
  case VUNPCKLPDZ256rmbkz:
26849
0
  case VUNPCKLPDZ256rmk:
26850
0
  case VUNPCKLPDZ256rmkz:
26851
0
  case VUNPCKLPDZ256rr:
26852
0
  case VUNPCKLPDZ256rrk:
26853
0
  case VUNPCKLPDZ256rrkz:
26854
0
  case VUNPCKLPDZrm:
26855
0
  case VUNPCKLPDZrmb:
26856
0
  case VUNPCKLPDZrmbk:
26857
0
  case VUNPCKLPDZrmbkz:
26858
0
  case VUNPCKLPDZrmk:
26859
0
  case VUNPCKLPDZrmkz:
26860
0
  case VUNPCKLPDZrr:
26861
0
  case VUNPCKLPDZrrk:
26862
0
  case VUNPCKLPDZrrkz:
26863
0
  case VUNPCKLPDrm:
26864
0
  case VUNPCKLPDrr:
26865
0
    return true;
26866
0
  }
26867
0
  return false;
26868
0
}
26869
26870
0
bool isVPSRAVD(unsigned Opcode) {
26871
0
  switch (Opcode) {
26872
0
  case VPSRAVDYrm:
26873
0
  case VPSRAVDYrr:
26874
0
  case VPSRAVDZ128rm:
26875
0
  case VPSRAVDZ128rmb:
26876
0
  case VPSRAVDZ128rmbk:
26877
0
  case VPSRAVDZ128rmbkz:
26878
0
  case VPSRAVDZ128rmk:
26879
0
  case VPSRAVDZ128rmkz:
26880
0
  case VPSRAVDZ128rr:
26881
0
  case VPSRAVDZ128rrk:
26882
0
  case VPSRAVDZ128rrkz:
26883
0
  case VPSRAVDZ256rm:
26884
0
  case VPSRAVDZ256rmb:
26885
0
  case VPSRAVDZ256rmbk:
26886
0
  case VPSRAVDZ256rmbkz:
26887
0
  case VPSRAVDZ256rmk:
26888
0
  case VPSRAVDZ256rmkz:
26889
0
  case VPSRAVDZ256rr:
26890
0
  case VPSRAVDZ256rrk:
26891
0
  case VPSRAVDZ256rrkz:
26892
0
  case VPSRAVDZrm:
26893
0
  case VPSRAVDZrmb:
26894
0
  case VPSRAVDZrmbk:
26895
0
  case VPSRAVDZrmbkz:
26896
0
  case VPSRAVDZrmk:
26897
0
  case VPSRAVDZrmkz:
26898
0
  case VPSRAVDZrr:
26899
0
  case VPSRAVDZrrk:
26900
0
  case VPSRAVDZrrkz:
26901
0
  case VPSRAVDrm:
26902
0
  case VPSRAVDrr:
26903
0
    return true;
26904
0
  }
26905
0
  return false;
26906
0
}
26907
26908
0
bool isVMULSH(unsigned Opcode) {
26909
0
  switch (Opcode) {
26910
0
  case VMULSHZrm_Int:
26911
0
  case VMULSHZrm_Intk:
26912
0
  case VMULSHZrm_Intkz:
26913
0
  case VMULSHZrr_Int:
26914
0
  case VMULSHZrr_Intk:
26915
0
  case VMULSHZrr_Intkz:
26916
0
  case VMULSHZrrb_Int:
26917
0
  case VMULSHZrrb_Intk:
26918
0
  case VMULSHZrrb_Intkz:
26919
0
    return true;
26920
0
  }
26921
0
  return false;
26922
0
}
26923
26924
0
bool isMOVNTSS(unsigned Opcode) {
26925
0
  return Opcode == MOVNTSS;
26926
0
}
26927
26928
0
bool isSTI(unsigned Opcode) {
26929
0
  return Opcode == STI;
26930
0
}
26931
26932
0
bool isVSM4RNDS4(unsigned Opcode) {
26933
0
  switch (Opcode) {
26934
0
  case VSM4RNDS4Yrm:
26935
0
  case VSM4RNDS4Yrr:
26936
0
  case VSM4RNDS4rm:
26937
0
  case VSM4RNDS4rr:
26938
0
    return true;
26939
0
  }
26940
0
  return false;
26941
0
}
26942
26943
0
bool isVMCLEAR(unsigned Opcode) {
26944
0
  return Opcode == VMCLEARm;
26945
0
}
26946
26947
0
bool isVPMADD52HUQ(unsigned Opcode) {
26948
0
  switch (Opcode) {
26949
0
  case VPMADD52HUQYrm:
26950
0
  case VPMADD52HUQYrr:
26951
0
  case VPMADD52HUQZ128m:
26952
0
  case VPMADD52HUQZ128mb:
26953
0
  case VPMADD52HUQZ128mbk:
26954
0
  case VPMADD52HUQZ128mbkz:
26955
0
  case VPMADD52HUQZ128mk:
26956
0
  case VPMADD52HUQZ128mkz:
26957
0
  case VPMADD52HUQZ128r:
26958
0
  case VPMADD52HUQZ128rk:
26959
0
  case VPMADD52HUQZ128rkz:
26960
0
  case VPMADD52HUQZ256m:
26961
0
  case VPMADD52HUQZ256mb:
26962
0
  case VPMADD52HUQZ256mbk:
26963
0
  case VPMADD52HUQZ256mbkz:
26964
0
  case VPMADD52HUQZ256mk:
26965
0
  case VPMADD52HUQZ256mkz:
26966
0
  case VPMADD52HUQZ256r:
26967
0
  case VPMADD52HUQZ256rk:
26968
0
  case VPMADD52HUQZ256rkz:
26969
0
  case VPMADD52HUQZm:
26970
0
  case VPMADD52HUQZmb:
26971
0
  case VPMADD52HUQZmbk:
26972
0
  case VPMADD52HUQZmbkz:
26973
0
  case VPMADD52HUQZmk:
26974
0
  case VPMADD52HUQZmkz:
26975
0
  case VPMADD52HUQZr:
26976
0
  case VPMADD52HUQZrk:
26977
0
  case VPMADD52HUQZrkz:
26978
0
  case VPMADD52HUQrm:
26979
0
  case VPMADD52HUQrr:
26980
0
    return true;
26981
0
  }
26982
0
  return false;
26983
0
}
26984
26985
0
bool isLIDT(unsigned Opcode) {
26986
0
  return Opcode == LIDT64m;
26987
0
}
26988
26989
0
bool isPUSH2(unsigned Opcode) {
26990
0
  return Opcode == PUSH2;
26991
0
}
26992
26993
0
bool isRDPKRU(unsigned Opcode) {
26994
0
  return Opcode == RDPKRUr;
26995
0
}
26996
26997
0
bool isVPCMPB(unsigned Opcode) {
26998
0
  switch (Opcode) {
26999
0
  case VPCMPBZ128rmi:
27000
0
  case VPCMPBZ128rmik:
27001
0
  case VPCMPBZ128rri:
27002
0
  case VPCMPBZ128rrik:
27003
0
  case VPCMPBZ256rmi:
27004
0
  case VPCMPBZ256rmik:
27005
0
  case VPCMPBZ256rri:
27006
0
  case VPCMPBZ256rrik:
27007
0
  case VPCMPBZrmi:
27008
0
  case VPCMPBZrmik:
27009
0
  case VPCMPBZrri:
27010
0
  case VPCMPBZrrik:
27011
0
    return true;
27012
0
  }
27013
0
  return false;
27014
0
}
27015
27016
0
bool isFINCSTP(unsigned Opcode) {
27017
0
  return Opcode == FINCSTP;
27018
0
}
27019
27020
0
bool isKORQ(unsigned Opcode) {
27021
0
  return Opcode == KORQrr;
27022
0
}
27023
27024
0
bool isXCRYPTCBC(unsigned Opcode) {
27025
0
  return Opcode == XCRYPTCBC;
27026
0
}
27027
27028
0
bool isRDPMC(unsigned Opcode) {
27029
0
  return Opcode == RDPMC;
27030
0
}
27031
27032
0
bool isMOVMSKPD(unsigned Opcode) {
27033
0
  return Opcode == MOVMSKPDrr;
27034
0
}
27035
27036
0
bool isVFMSUB231SH(unsigned Opcode) {
27037
0
  switch (Opcode) {
27038
0
  case VFMSUB231SHZm_Int:
27039
0
  case VFMSUB231SHZm_Intk:
27040
0
  case VFMSUB231SHZm_Intkz:
27041
0
  case VFMSUB231SHZr_Int:
27042
0
  case VFMSUB231SHZr_Intk:
27043
0
  case VFMSUB231SHZr_Intkz:
27044
0
  case VFMSUB231SHZrb_Int:
27045
0
  case VFMSUB231SHZrb_Intk:
27046
0
  case VFMSUB231SHZrb_Intkz:
27047
0
    return true;
27048
0
  }
27049
0
  return false;
27050
0
}
27051
27052
0
bool isVEXTRACTF128(unsigned Opcode) {
27053
0
  switch (Opcode) {
27054
0
  case VEXTRACTF128mr:
27055
0
  case VEXTRACTF128rr:
27056
0
    return true;
27057
0
  }
27058
0
  return false;
27059
0
}
27060
27061
0
bool isVPSHLB(unsigned Opcode) {
27062
0
  switch (Opcode) {
27063
0
  case VPSHLBmr:
27064
0
  case VPSHLBrm:
27065
0
  case VPSHLBrr:
27066
0
  case VPSHLBrr_REV:
27067
0
    return true;
27068
0
  }
27069
0
  return false;
27070
0
}
27071
27072
0
bool isXSAVES64(unsigned Opcode) {
27073
0
  return Opcode == XSAVES64;
27074
0
}
27075
27076
0
bool isSHL(unsigned Opcode) {
27077
0
  switch (Opcode) {
27078
0
  case SHL16m1:
27079
0
  case SHL16mCL:
27080
0
  case SHL16mi:
27081
0
  case SHL16r1:
27082
0
  case SHL16rCL:
27083
0
  case SHL16ri:
27084
0
  case SHL32m1:
27085
0
  case SHL32mCL:
27086
0
  case SHL32mi:
27087
0
  case SHL32r1:
27088
0
  case SHL32rCL:
27089
0
  case SHL32ri:
27090
0
  case SHL64m1:
27091
0
  case SHL64mCL:
27092
0
  case SHL64mi:
27093
0
  case SHL64r1:
27094
0
  case SHL64rCL:
27095
0
  case SHL64ri:
27096
0
  case SHL8m1:
27097
0
  case SHL8mCL:
27098
0
  case SHL8mi:
27099
0
  case SHL8r1:
27100
0
  case SHL8rCL:
27101
0
  case SHL8ri:
27102
0
    return true;
27103
0
  }
27104
0
  return false;
27105
0
}
27106
27107
0
bool isAXOR(unsigned Opcode) {
27108
0
  switch (Opcode) {
27109
0
  case AXOR32mr:
27110
0
  case AXOR64mr:
27111
0
    return true;
27112
0
  }
27113
0
  return false;
27114
0
}
27115
27116
0
bool isVINSERTI64X2(unsigned Opcode) {
27117
0
  switch (Opcode) {
27118
0
  case VINSERTI64x2Z256rm:
27119
0
  case VINSERTI64x2Z256rmk:
27120
0
  case VINSERTI64x2Z256rmkz:
27121
0
  case VINSERTI64x2Z256rr:
27122
0
  case VINSERTI64x2Z256rrk:
27123
0
  case VINSERTI64x2Z256rrkz:
27124
0
  case VINSERTI64x2Zrm:
27125
0
  case VINSERTI64x2Zrmk:
27126
0
  case VINSERTI64x2Zrmkz:
27127
0
  case VINSERTI64x2Zrr:
27128
0
  case VINSERTI64x2Zrrk:
27129
0
  case VINSERTI64x2Zrrkz:
27130
0
    return true;
27131
0
  }
27132
0
  return false;
27133
0
}
27134
27135
0
bool isSYSRETQ(unsigned Opcode) {
27136
0
  return Opcode == SYSRET64;
27137
0
}
27138
27139
0
bool isVSCATTERPF0QPD(unsigned Opcode) {
27140
0
  return Opcode == VSCATTERPF0QPDm;
27141
0
}
27142
27143
0
bool isVFMSUB213SH(unsigned Opcode) {
27144
0
  switch (Opcode) {
27145
0
  case VFMSUB213SHZm_Int:
27146
0
  case VFMSUB213SHZm_Intk:
27147
0
  case VFMSUB213SHZm_Intkz:
27148
0
  case VFMSUB213SHZr_Int:
27149
0
  case VFMSUB213SHZr_Intk:
27150
0
  case VFMSUB213SHZr_Intkz:
27151
0
  case VFMSUB213SHZrb_Int:
27152
0
  case VFMSUB213SHZrb_Intk:
27153
0
  case VFMSUB213SHZrb_Intkz:
27154
0
    return true;
27155
0
  }
27156
0
  return false;
27157
0
}
27158
27159
0
bool isVPMOVQW(unsigned Opcode) {
27160
0
  switch (Opcode) {
27161
0
  case VPMOVQWZ128mr:
27162
0
  case VPMOVQWZ128mrk:
27163
0
  case VPMOVQWZ128rr:
27164
0
  case VPMOVQWZ128rrk:
27165
0
  case VPMOVQWZ128rrkz:
27166
0
  case VPMOVQWZ256mr:
27167
0
  case VPMOVQWZ256mrk:
27168
0
  case VPMOVQWZ256rr:
27169
0
  case VPMOVQWZ256rrk:
27170
0
  case VPMOVQWZ256rrkz:
27171
0
  case VPMOVQWZmr:
27172
0
  case VPMOVQWZmrk:
27173
0
  case VPMOVQWZrr:
27174
0
  case VPMOVQWZrrk:
27175
0
  case VPMOVQWZrrkz:
27176
0
    return true;
27177
0
  }
27178
0
  return false;
27179
0
}
27180
27181
0
bool isVREDUCEPD(unsigned Opcode) {
27182
0
  switch (Opcode) {
27183
0
  case VREDUCEPDZ128rmbi:
27184
0
  case VREDUCEPDZ128rmbik:
27185
0
  case VREDUCEPDZ128rmbikz:
27186
0
  case VREDUCEPDZ128rmi:
27187
0
  case VREDUCEPDZ128rmik:
27188
0
  case VREDUCEPDZ128rmikz:
27189
0
  case VREDUCEPDZ128rri:
27190
0
  case VREDUCEPDZ128rrik:
27191
0
  case VREDUCEPDZ128rrikz:
27192
0
  case VREDUCEPDZ256rmbi:
27193
0
  case VREDUCEPDZ256rmbik:
27194
0
  case VREDUCEPDZ256rmbikz:
27195
0
  case VREDUCEPDZ256rmi:
27196
0
  case VREDUCEPDZ256rmik:
27197
0
  case VREDUCEPDZ256rmikz:
27198
0
  case VREDUCEPDZ256rri:
27199
0
  case VREDUCEPDZ256rrik:
27200
0
  case VREDUCEPDZ256rrikz:
27201
0
  case VREDUCEPDZrmbi:
27202
0
  case VREDUCEPDZrmbik:
27203
0
  case VREDUCEPDZrmbikz:
27204
0
  case VREDUCEPDZrmi:
27205
0
  case VREDUCEPDZrmik:
27206
0
  case VREDUCEPDZrmikz:
27207
0
  case VREDUCEPDZrri:
27208
0
  case VREDUCEPDZrrib:
27209
0
  case VREDUCEPDZrribk:
27210
0
  case VREDUCEPDZrribkz:
27211
0
  case VREDUCEPDZrrik:
27212
0
  case VREDUCEPDZrrikz:
27213
0
    return true;
27214
0
  }
27215
0
  return false;
27216
0
}
27217
27218
0
bool isNOT(unsigned Opcode) {
27219
0
  switch (Opcode) {
27220
0
  case NOT16m:
27221
0
  case NOT16m_EVEX:
27222
0
  case NOT16m_ND:
27223
0
  case NOT16r:
27224
0
  case NOT16r_EVEX:
27225
0
  case NOT16r_ND:
27226
0
  case NOT32m:
27227
0
  case NOT32m_EVEX:
27228
0
  case NOT32m_ND:
27229
0
  case NOT32r:
27230
0
  case NOT32r_EVEX:
27231
0
  case NOT32r_ND:
27232
0
  case NOT64m:
27233
0
  case NOT64m_EVEX:
27234
0
  case NOT64m_ND:
27235
0
  case NOT64r:
27236
0
  case NOT64r_EVEX:
27237
0
  case NOT64r_ND:
27238
0
  case NOT8m:
27239
0
  case NOT8m_EVEX:
27240
0
  case NOT8m_ND:
27241
0
  case NOT8r:
27242
0
  case NOT8r_EVEX:
27243
0
  case NOT8r_ND:
27244
0
    return true;
27245
0
  }
27246
0
  return false;
27247
0
}
27248
27249
0
bool isLWPINS(unsigned Opcode) {
27250
0
  switch (Opcode) {
27251
0
  case LWPINS32rmi:
27252
0
  case LWPINS32rri:
27253
0
  case LWPINS64rmi:
27254
0
  case LWPINS64rri:
27255
0
    return true;
27256
0
  }
27257
0
  return false;
27258
0
}
27259
27260
0
bool isVSCATTERDPS(unsigned Opcode) {
27261
0
  switch (Opcode) {
27262
0
  case VSCATTERDPSZ128mr:
27263
0
  case VSCATTERDPSZ256mr:
27264
0
  case VSCATTERDPSZmr:
27265
0
    return true;
27266
0
  }
27267
0
  return false;
27268
0
}
27269
27270
0
bool isVPMOVM2W(unsigned Opcode) {
27271
0
  switch (Opcode) {
27272
0
  case VPMOVM2WZ128rr:
27273
0
  case VPMOVM2WZ256rr:
27274
0
  case VPMOVM2WZrr:
27275
0
    return true;
27276
0
  }
27277
0
  return false;
27278
0
}
27279
27280
0
bool isVFNMADD132PS(unsigned Opcode) {
27281
0
  switch (Opcode) {
27282
0
  case VFNMADD132PSYm:
27283
0
  case VFNMADD132PSYr:
27284
0
  case VFNMADD132PSZ128m:
27285
0
  case VFNMADD132PSZ128mb:
27286
0
  case VFNMADD132PSZ128mbk:
27287
0
  case VFNMADD132PSZ128mbkz:
27288
0
  case VFNMADD132PSZ128mk:
27289
0
  case VFNMADD132PSZ128mkz:
27290
0
  case VFNMADD132PSZ128r:
27291
0
  case VFNMADD132PSZ128rk:
27292
0
  case VFNMADD132PSZ128rkz:
27293
0
  case VFNMADD132PSZ256m:
27294
0
  case VFNMADD132PSZ256mb:
27295
0
  case VFNMADD132PSZ256mbk:
27296
0
  case VFNMADD132PSZ256mbkz:
27297
0
  case VFNMADD132PSZ256mk:
27298
0
  case VFNMADD132PSZ256mkz:
27299
0
  case VFNMADD132PSZ256r:
27300
0
  case VFNMADD132PSZ256rk:
27301
0
  case VFNMADD132PSZ256rkz:
27302
0
  case VFNMADD132PSZm:
27303
0
  case VFNMADD132PSZmb:
27304
0
  case VFNMADD132PSZmbk:
27305
0
  case VFNMADD132PSZmbkz:
27306
0
  case VFNMADD132PSZmk:
27307
0
  case VFNMADD132PSZmkz:
27308
0
  case VFNMADD132PSZr:
27309
0
  case VFNMADD132PSZrb:
27310
0
  case VFNMADD132PSZrbk:
27311
0
  case VFNMADD132PSZrbkz:
27312
0
  case VFNMADD132PSZrk:
27313
0
  case VFNMADD132PSZrkz:
27314
0
  case VFNMADD132PSm:
27315
0
  case VFNMADD132PSr:
27316
0
    return true;
27317
0
  }
27318
0
  return false;
27319
0
}
27320
27321
0
bool isMOVNTPS(unsigned Opcode) {
27322
0
  return Opcode == MOVNTPSmr;
27323
0
}
27324
27325
0
bool isVRSQRTSS(unsigned Opcode) {
27326
0
  switch (Opcode) {
27327
0
  case VRSQRTSSm_Int:
27328
0
  case VRSQRTSSr_Int:
27329
0
    return true;
27330
0
  }
27331
0
  return false;
27332
0
}
27333
27334
0
bool isKMOVB(unsigned Opcode) {
27335
0
  switch (Opcode) {
27336
0
  case KMOVBkk:
27337
0
  case KMOVBkk_EVEX:
27338
0
  case KMOVBkm:
27339
0
  case KMOVBkm_EVEX:
27340
0
  case KMOVBkr:
27341
0
  case KMOVBkr_EVEX:
27342
0
  case KMOVBmk:
27343
0
  case KMOVBmk_EVEX:
27344
0
  case KMOVBrk:
27345
0
  case KMOVBrk_EVEX:
27346
0
    return true;
27347
0
  }
27348
0
  return false;
27349
0
}
27350
27351
0
bool isCVTSD2SS(unsigned Opcode) {
27352
0
  switch (Opcode) {
27353
0
  case CVTSD2SSrm_Int:
27354
0
  case CVTSD2SSrr_Int:
27355
0
    return true;
27356
0
  }
27357
0
  return false;
27358
0
}
27359
27360
0
bool isVBROADCASTF64X2(unsigned Opcode) {
27361
0
  switch (Opcode) {
27362
0
  case VBROADCASTF64X2Z128rm:
27363
0
  case VBROADCASTF64X2Z128rmk:
27364
0
  case VBROADCASTF64X2Z128rmkz:
27365
0
  case VBROADCASTF64X2rm:
27366
0
  case VBROADCASTF64X2rmk:
27367
0
  case VBROADCASTF64X2rmkz:
27368
0
    return true;
27369
0
  }
27370
0
  return false;
27371
0
}
27372
27373
0
bool isMOVNTPD(unsigned Opcode) {
27374
0
  return Opcode == MOVNTPDmr;
27375
0
}
27376
27377
0
bool isMAXSD(unsigned Opcode) {
27378
0
  switch (Opcode) {
27379
0
  case MAXSDrm_Int:
27380
0
  case MAXSDrr_Int:
27381
0
    return true;
27382
0
  }
27383
0
  return false;
27384
0
}
27385
27386
0
bool isCMPPD(unsigned Opcode) {
27387
0
  switch (Opcode) {
27388
0
  case CMPPDrmi:
27389
0
  case CMPPDrri:
27390
0
    return true;
27391
0
  }
27392
0
  return false;
27393
0
}
27394
27395
0
bool isVPCMPESTRM(unsigned Opcode) {
27396
0
  switch (Opcode) {
27397
0
  case VPCMPESTRMrm:
27398
0
  case VPCMPESTRMrr:
27399
0
    return true;
27400
0
  }
27401
0
  return false;
27402
0
}
27403
27404
0
bool isVFMSUB132PS(unsigned Opcode) {
27405
0
  switch (Opcode) {
27406
0
  case VFMSUB132PSYm:
27407
0
  case VFMSUB132PSYr:
27408
0
  case VFMSUB132PSZ128m:
27409
0
  case VFMSUB132PSZ128mb:
27410
0
  case VFMSUB132PSZ128mbk:
27411
0
  case VFMSUB132PSZ128mbkz:
27412
0
  case VFMSUB132PSZ128mk:
27413
0
  case VFMSUB132PSZ128mkz:
27414
0
  case VFMSUB132PSZ128r:
27415
0
  case VFMSUB132PSZ128rk:
27416
0
  case VFMSUB132PSZ128rkz:
27417
0
  case VFMSUB132PSZ256m:
27418
0
  case VFMSUB132PSZ256mb:
27419
0
  case VFMSUB132PSZ256mbk:
27420
0
  case VFMSUB132PSZ256mbkz:
27421
0
  case VFMSUB132PSZ256mk:
27422
0
  case VFMSUB132PSZ256mkz:
27423
0
  case VFMSUB132PSZ256r:
27424
0
  case VFMSUB132PSZ256rk:
27425
0
  case VFMSUB132PSZ256rkz:
27426
0
  case VFMSUB132PSZm:
27427
0
  case VFMSUB132PSZmb:
27428
0
  case VFMSUB132PSZmbk:
27429
0
  case VFMSUB132PSZmbkz:
27430
0
  case VFMSUB132PSZmk:
27431
0
  case VFMSUB132PSZmkz:
27432
0
  case VFMSUB132PSZr:
27433
0
  case VFMSUB132PSZrb:
27434
0
  case VFMSUB132PSZrbk:
27435
0
  case VFMSUB132PSZrbkz:
27436
0
  case VFMSUB132PSZrk:
27437
0
  case VFMSUB132PSZrkz:
27438
0
  case VFMSUB132PSm:
27439
0
  case VFMSUB132PSr:
27440
0
    return true;
27441
0
  }
27442
0
  return false;
27443
0
}
27444
27445
0
bool isVCOMISH(unsigned Opcode) {
27446
0
  switch (Opcode) {
27447
0
  case VCOMISHZrm:
27448
0
  case VCOMISHZrr:
27449
0
  case VCOMISHZrrb:
27450
0
    return true;
27451
0
  }
27452
0
  return false;
27453
0
}
27454
27455
0
bool isF2XM1(unsigned Opcode) {
27456
0
  return Opcode == F2XM1;
27457
0
}
27458
27459
0
bool isSQRTPD(unsigned Opcode) {
27460
0
  switch (Opcode) {
27461
0
  case SQRTPDm:
27462
0
  case SQRTPDr:
27463
0
    return true;
27464
0
  }
27465
0
  return false;
27466
0
}
27467
27468
0
bool isVFMSUBADDPS(unsigned Opcode) {
27469
0
  switch (Opcode) {
27470
0
  case VFMSUBADDPS4Ymr:
27471
0
  case VFMSUBADDPS4Yrm:
27472
0
  case VFMSUBADDPS4Yrr:
27473
0
  case VFMSUBADDPS4Yrr_REV:
27474
0
  case VFMSUBADDPS4mr:
27475
0
  case VFMSUBADDPS4rm:
27476
0
  case VFMSUBADDPS4rr:
27477
0
  case VFMSUBADDPS4rr_REV:
27478
0
    return true;
27479
0
  }
27480
0
  return false;
27481
0
}
27482
27483
0
bool isFXTRACT(unsigned Opcode) {
27484
0
  return Opcode == FXTRACT;
27485
0
}
27486
27487
0
bool isVP4DPWSSD(unsigned Opcode) {
27488
0
  switch (Opcode) {
27489
0
  case VP4DPWSSDrm:
27490
0
  case VP4DPWSSDrmk:
27491
0
  case VP4DPWSSDrmkz:
27492
0
    return true;
27493
0
  }
27494
0
  return false;
27495
0
}
27496
27497
0
bool isVFMSUBADDPD(unsigned Opcode) {
27498
0
  switch (Opcode) {
27499
0
  case VFMSUBADDPD4Ymr:
27500
0
  case VFMSUBADDPD4Yrm:
27501
0
  case VFMSUBADDPD4Yrr:
27502
0
  case VFMSUBADDPD4Yrr_REV:
27503
0
  case VFMSUBADDPD4mr:
27504
0
  case VFMSUBADDPD4rm:
27505
0
  case VFMSUBADDPD4rr:
27506
0
  case VFMSUBADDPD4rr_REV:
27507
0
    return true;
27508
0
  }
27509
0
  return false;
27510
0
}
27511
27512
0
bool isVBCSTNEBF162PS(unsigned Opcode) {
27513
0
  switch (Opcode) {
27514
0
  case VBCSTNEBF162PSYrm:
27515
0
  case VBCSTNEBF162PSrm:
27516
0
    return true;
27517
0
  }
27518
0
  return false;
27519
0
}
27520
27521
0
bool isVPGATHERQQ(unsigned Opcode) {
27522
0
  switch (Opcode) {
27523
0
  case VPGATHERQQYrm:
27524
0
  case VPGATHERQQZ128rm:
27525
0
  case VPGATHERQQZ256rm:
27526
0
  case VPGATHERQQZrm:
27527
0
  case VPGATHERQQrm:
27528
0
    return true;
27529
0
  }
27530
0
  return false;
27531
0
}
27532
27533
0
bool isPCMPEQB(unsigned Opcode) {
27534
0
  switch (Opcode) {
27535
0
  case MMX_PCMPEQBrm:
27536
0
  case MMX_PCMPEQBrr:
27537
0
  case PCMPEQBrm:
27538
0
  case PCMPEQBrr:
27539
0
    return true;
27540
0
  }
27541
0
  return false;
27542
0
}
27543
27544
0
bool isTILESTORED(unsigned Opcode) {
27545
0
  switch (Opcode) {
27546
0
  case TILESTORED:
27547
0
  case TILESTORED_EVEX:
27548
0
    return true;
27549
0
  }
27550
0
  return false;
27551
0
}
27552
27553
0
bool isBLSMSK(unsigned Opcode) {
27554
0
  switch (Opcode) {
27555
0
  case BLSMSK32rm:
27556
0
  case BLSMSK32rm_EVEX:
27557
0
  case BLSMSK32rr:
27558
0
  case BLSMSK32rr_EVEX:
27559
0
  case BLSMSK64rm:
27560
0
  case BLSMSK64rm_EVEX:
27561
0
  case BLSMSK64rr:
27562
0
  case BLSMSK64rr_EVEX:
27563
0
    return true;
27564
0
  }
27565
0
  return false;
27566
0
}
27567
27568
0
bool isVCVTTPS2DQ(unsigned Opcode) {
27569
0
  switch (Opcode) {
27570
0
  case VCVTTPS2DQYrm:
27571
0
  case VCVTTPS2DQYrr:
27572
0
  case VCVTTPS2DQZ128rm:
27573
0
  case VCVTTPS2DQZ128rmb:
27574
0
  case VCVTTPS2DQZ128rmbk:
27575
0
  case VCVTTPS2DQZ128rmbkz:
27576
0
  case VCVTTPS2DQZ128rmk:
27577
0
  case VCVTTPS2DQZ128rmkz:
27578
0
  case VCVTTPS2DQZ128rr:
27579
0
  case VCVTTPS2DQZ128rrk:
27580
0
  case VCVTTPS2DQZ128rrkz:
27581
0
  case VCVTTPS2DQZ256rm:
27582
0
  case VCVTTPS2DQZ256rmb:
27583
0
  case VCVTTPS2DQZ256rmbk:
27584
0
  case VCVTTPS2DQZ256rmbkz:
27585
0
  case VCVTTPS2DQZ256rmk:
27586
0
  case VCVTTPS2DQZ256rmkz:
27587
0
  case VCVTTPS2DQZ256rr:
27588
0
  case VCVTTPS2DQZ256rrk:
27589
0
  case VCVTTPS2DQZ256rrkz:
27590
0
  case VCVTTPS2DQZrm:
27591
0
  case VCVTTPS2DQZrmb:
27592
0
  case VCVTTPS2DQZrmbk:
27593
0
  case VCVTTPS2DQZrmbkz:
27594
0
  case VCVTTPS2DQZrmk:
27595
0
  case VCVTTPS2DQZrmkz:
27596
0
  case VCVTTPS2DQZrr:
27597
0
  case VCVTTPS2DQZrrb:
27598
0
  case VCVTTPS2DQZrrbk:
27599
0
  case VCVTTPS2DQZrrbkz:
27600
0
  case VCVTTPS2DQZrrk:
27601
0
  case VCVTTPS2DQZrrkz:
27602
0
  case VCVTTPS2DQrm:
27603
0
  case VCVTTPS2DQrr:
27604
0
    return true;
27605
0
  }
27606
0
  return false;
27607
0
}
27608
27609
0
bool isVRNDSCALEPD(unsigned Opcode) {
27610
0
  switch (Opcode) {
27611
0
  case VRNDSCALEPDZ128rmbi:
27612
0
  case VRNDSCALEPDZ128rmbik:
27613
0
  case VRNDSCALEPDZ128rmbikz:
27614
0
  case VRNDSCALEPDZ128rmi:
27615
0
  case VRNDSCALEPDZ128rmik:
27616
0
  case VRNDSCALEPDZ128rmikz:
27617
0
  case VRNDSCALEPDZ128rri:
27618
0
  case VRNDSCALEPDZ128rrik:
27619
0
  case VRNDSCALEPDZ128rrikz:
27620
0
  case VRNDSCALEPDZ256rmbi:
27621
0
  case VRNDSCALEPDZ256rmbik:
27622
0
  case VRNDSCALEPDZ256rmbikz:
27623
0
  case VRNDSCALEPDZ256rmi:
27624
0
  case VRNDSCALEPDZ256rmik:
27625
0
  case VRNDSCALEPDZ256rmikz:
27626
0
  case VRNDSCALEPDZ256rri:
27627
0
  case VRNDSCALEPDZ256rrik:
27628
0
  case VRNDSCALEPDZ256rrikz:
27629
0
  case VRNDSCALEPDZrmbi:
27630
0
  case VRNDSCALEPDZrmbik:
27631
0
  case VRNDSCALEPDZrmbikz:
27632
0
  case VRNDSCALEPDZrmi:
27633
0
  case VRNDSCALEPDZrmik:
27634
0
  case VRNDSCALEPDZrmikz:
27635
0
  case VRNDSCALEPDZrri:
27636
0
  case VRNDSCALEPDZrrib:
27637
0
  case VRNDSCALEPDZrribk:
27638
0
  case VRNDSCALEPDZrribkz:
27639
0
  case VRNDSCALEPDZrrik:
27640
0
  case VRNDSCALEPDZrrikz:
27641
0
    return true;
27642
0
  }
27643
0
  return false;
27644
0
}
27645
27646
0
bool isVMLOAD(unsigned Opcode) {
27647
0
  switch (Opcode) {
27648
0
  case VMLOAD32:
27649
0
  case VMLOAD64:
27650
0
    return true;
27651
0
  }
27652
0
  return false;
27653
0
}
27654
27655
0
bool isVPTERNLOGQ(unsigned Opcode) {
27656
0
  switch (Opcode) {
27657
0
  case VPTERNLOGQZ128rmbi:
27658
0
  case VPTERNLOGQZ128rmbik:
27659
0
  case VPTERNLOGQZ128rmbikz:
27660
0
  case VPTERNLOGQZ128rmi:
27661
0
  case VPTERNLOGQZ128rmik:
27662
0
  case VPTERNLOGQZ128rmikz:
27663
0
  case VPTERNLOGQZ128rri:
27664
0
  case VPTERNLOGQZ128rrik:
27665
0
  case VPTERNLOGQZ128rrikz:
27666
0
  case VPTERNLOGQZ256rmbi:
27667
0
  case VPTERNLOGQZ256rmbik:
27668
0
  case VPTERNLOGQZ256rmbikz:
27669
0
  case VPTERNLOGQZ256rmi:
27670
0
  case VPTERNLOGQZ256rmik:
27671
0
  case VPTERNLOGQZ256rmikz:
27672
0
  case VPTERNLOGQZ256rri:
27673
0
  case VPTERNLOGQZ256rrik:
27674
0
  case VPTERNLOGQZ256rrikz:
27675
0
  case VPTERNLOGQZrmbi:
27676
0
  case VPTERNLOGQZrmbik:
27677
0
  case VPTERNLOGQZrmbikz:
27678
0
  case VPTERNLOGQZrmi:
27679
0
  case VPTERNLOGQZrmik:
27680
0
  case VPTERNLOGQZrmikz:
27681
0
  case VPTERNLOGQZrri:
27682
0
  case VPTERNLOGQZrrik:
27683
0
  case VPTERNLOGQZrrikz:
27684
0
    return true;
27685
0
  }
27686
0
  return false;
27687
0
}
27688
27689
0
bool isKXNORD(unsigned Opcode) {
27690
0
  return Opcode == KXNORDrr;
27691
0
}
27692
27693
0
bool isFXSAVE(unsigned Opcode) {
27694
0
  return Opcode == FXSAVE;
27695
0
}
27696
27697
0
bool isVUNPCKHPD(unsigned Opcode) {
27698
0
  switch (Opcode) {
27699
0
  case VUNPCKHPDYrm:
27700
0
  case VUNPCKHPDYrr:
27701
0
  case VUNPCKHPDZ128rm:
27702
0
  case VUNPCKHPDZ128rmb:
27703
0
  case VUNPCKHPDZ128rmbk:
27704
0
  case VUNPCKHPDZ128rmbkz:
27705
0
  case VUNPCKHPDZ128rmk:
27706
0
  case VUNPCKHPDZ128rmkz:
27707
0
  case VUNPCKHPDZ128rr:
27708
0
  case VUNPCKHPDZ128rrk:
27709
0
  case VUNPCKHPDZ128rrkz:
27710
0
  case VUNPCKHPDZ256rm:
27711
0
  case VUNPCKHPDZ256rmb:
27712
0
  case VUNPCKHPDZ256rmbk:
27713
0
  case VUNPCKHPDZ256rmbkz:
27714
0
  case VUNPCKHPDZ256rmk:
27715
0
  case VUNPCKHPDZ256rmkz:
27716
0
  case VUNPCKHPDZ256rr:
27717
0
  case VUNPCKHPDZ256rrk:
27718
0
  case VUNPCKHPDZ256rrkz:
27719
0
  case VUNPCKHPDZrm:
27720
0
  case VUNPCKHPDZrmb:
27721
0
  case VUNPCKHPDZrmbk:
27722
0
  case VUNPCKHPDZrmbkz:
27723
0
  case VUNPCKHPDZrmk:
27724
0
  case VUNPCKHPDZrmkz:
27725
0
  case VUNPCKHPDZrr:
27726
0
  case VUNPCKHPDZrrk:
27727
0
  case VUNPCKHPDZrrkz:
27728
0
  case VUNPCKHPDrm:
27729
0
  case VUNPCKHPDrr:
27730
0
    return true;
27731
0
  }
27732
0
  return false;
27733
0
}
27734
27735
0
bool isCVTPS2DQ(unsigned Opcode) {
27736
0
  switch (Opcode) {
27737
0
  case CVTPS2DQrm:
27738
0
  case CVTPS2DQrr:
27739
0
    return true;
27740
0
  }
27741
0
  return false;
27742
0
}
27743
27744
0
bool isVFMSUB213SS(unsigned Opcode) {
27745
0
  switch (Opcode) {
27746
0
  case VFMSUB213SSZm_Int:
27747
0
  case VFMSUB213SSZm_Intk:
27748
0
  case VFMSUB213SSZm_Intkz:
27749
0
  case VFMSUB213SSZr_Int:
27750
0
  case VFMSUB213SSZr_Intk:
27751
0
  case VFMSUB213SSZr_Intkz:
27752
0
  case VFMSUB213SSZrb_Int:
27753
0
  case VFMSUB213SSZrb_Intk:
27754
0
  case VFMSUB213SSZrb_Intkz:
27755
0
  case VFMSUB213SSm_Int:
27756
0
  case VFMSUB213SSr_Int:
27757
0
    return true;
27758
0
  }
27759
0
  return false;
27760
0
}
27761
27762
0
bool isVPOPCNTD(unsigned Opcode) {
27763
0
  switch (Opcode) {
27764
0
  case VPOPCNTDZ128rm:
27765
0
  case VPOPCNTDZ128rmb:
27766
0
  case VPOPCNTDZ128rmbk:
27767
0
  case VPOPCNTDZ128rmbkz:
27768
0
  case VPOPCNTDZ128rmk:
27769
0
  case VPOPCNTDZ128rmkz:
27770
0
  case VPOPCNTDZ128rr:
27771
0
  case VPOPCNTDZ128rrk:
27772
0
  case VPOPCNTDZ128rrkz:
27773
0
  case VPOPCNTDZ256rm:
27774
0
  case VPOPCNTDZ256rmb:
27775
0
  case VPOPCNTDZ256rmbk:
27776
0
  case VPOPCNTDZ256rmbkz:
27777
0
  case VPOPCNTDZ256rmk:
27778
0
  case VPOPCNTDZ256rmkz:
27779
0
  case VPOPCNTDZ256rr:
27780
0
  case VPOPCNTDZ256rrk:
27781
0
  case VPOPCNTDZ256rrkz:
27782
0
  case VPOPCNTDZrm:
27783
0
  case VPOPCNTDZrmb:
27784
0
  case VPOPCNTDZrmbk:
27785
0
  case VPOPCNTDZrmbkz:
27786
0
  case VPOPCNTDZrmk:
27787
0
  case VPOPCNTDZrmkz:
27788
0
  case VPOPCNTDZrr:
27789
0
  case VPOPCNTDZrrk:
27790
0
  case VPOPCNTDZrrkz:
27791
0
    return true;
27792
0
  }
27793
0
  return false;
27794
0
}
27795
27796
0
bool isSALC(unsigned Opcode) {
27797
0
  return Opcode == SALC;
27798
0
}
27799
27800
0
bool isV4FNMADDSS(unsigned Opcode) {
27801
0
  switch (Opcode) {
27802
0
  case V4FNMADDSSrm:
27803
0
  case V4FNMADDSSrmk:
27804
0
  case V4FNMADDSSrmkz:
27805
0
    return true;
27806
0
  }
27807
0
  return false;
27808
0
}
27809
27810
0
bool isXCRYPTOFB(unsigned Opcode) {
27811
0
  return Opcode == XCRYPTOFB;
27812
0
}
27813
27814
0
bool isVORPD(unsigned Opcode) {
27815
0
  switch (Opcode) {
27816
0
  case VORPDYrm:
27817
0
  case VORPDYrr:
27818
0
  case VORPDZ128rm:
27819
0
  case VORPDZ128rmb:
27820
0
  case VORPDZ128rmbk:
27821
0
  case VORPDZ128rmbkz:
27822
0
  case VORPDZ128rmk:
27823
0
  case VORPDZ128rmkz:
27824
0
  case VORPDZ128rr:
27825
0
  case VORPDZ128rrk:
27826
0
  case VORPDZ128rrkz:
27827
0
  case VORPDZ256rm:
27828
0
  case VORPDZ256rmb:
27829
0
  case VORPDZ256rmbk:
27830
0
  case VORPDZ256rmbkz:
27831
0
  case VORPDZ256rmk:
27832
0
  case VORPDZ256rmkz:
27833
0
  case VORPDZ256rr:
27834
0
  case VORPDZ256rrk:
27835
0
  case VORPDZ256rrkz:
27836
0
  case VORPDZrm:
27837
0
  case VORPDZrmb:
27838
0
  case VORPDZrmbk:
27839
0
  case VORPDZrmbkz:
27840
0
  case VORPDZrmk:
27841
0
  case VORPDZrmkz:
27842
0
  case VORPDZrr:
27843
0
  case VORPDZrrk:
27844
0
  case VORPDZrrkz:
27845
0
  case VORPDrm:
27846
0
  case VORPDrr:
27847
0
    return true;
27848
0
  }
27849
0
  return false;
27850
0
}
27851
27852
0
bool isLSL(unsigned Opcode) {
27853
0
  switch (Opcode) {
27854
0
  case LSL16rm:
27855
0
  case LSL16rr:
27856
0
  case LSL32rm:
27857
0
  case LSL32rr:
27858
0
  case LSL64rm:
27859
0
  case LSL64rr:
27860
0
    return true;
27861
0
  }
27862
0
  return false;
27863
0
}
27864
27865
0
bool isXCRYPTCFB(unsigned Opcode) {
27866
0
  return Opcode == XCRYPTCFB;
27867
0
}
27868
27869
0
bool isVGETEXPSS(unsigned Opcode) {
27870
0
  switch (Opcode) {
27871
0
  case VGETEXPSSZm:
27872
0
  case VGETEXPSSZmk:
27873
0
  case VGETEXPSSZmkz:
27874
0
  case VGETEXPSSZr:
27875
0
  case VGETEXPSSZrb:
27876
0
  case VGETEXPSSZrbk:
27877
0
  case VGETEXPSSZrbkz:
27878
0
  case VGETEXPSSZrk:
27879
0
  case VGETEXPSSZrkz:
27880
0
    return true;
27881
0
  }
27882
0
  return false;
27883
0
}
27884
27885
0
bool isPSLLDQ(unsigned Opcode) {
27886
0
  return Opcode == PSLLDQri;
27887
0
}
27888
27889
0
bool isVPDPBUUD(unsigned Opcode) {
27890
0
  switch (Opcode) {
27891
0
  case VPDPBUUDYrm:
27892
0
  case VPDPBUUDYrr:
27893
0
  case VPDPBUUDrm:
27894
0
  case VPDPBUUDrr:
27895
0
    return true;
27896
0
  }
27897
0
  return false;
27898
0
}
27899
27900
0
bool isVMXOFF(unsigned Opcode) {
27901
0
  return Opcode == VMXOFF;
27902
0
}
27903
27904
0
bool isBLSIC(unsigned Opcode) {
27905
0
  switch (Opcode) {
27906
0
  case BLSIC32rm:
27907
0
  case BLSIC32rr:
27908
0
  case BLSIC64rm:
27909
0
  case BLSIC64rr:
27910
0
    return true;
27911
0
  }
27912
0
  return false;
27913
0
}
27914
27915
0
bool isMOVLHPS(unsigned Opcode) {
27916
0
  return Opcode == MOVLHPSrr;
27917
0
}
27918
27919
0
bool isVFNMSUBSD(unsigned Opcode) {
27920
0
  switch (Opcode) {
27921
0
  case VFNMSUBSD4mr:
27922
0
  case VFNMSUBSD4rm:
27923
0
  case VFNMSUBSD4rr:
27924
0
  case VFNMSUBSD4rr_REV:
27925
0
    return true;
27926
0
  }
27927
0
  return false;
27928
0
}
27929
27930
0
bool isVFPCLASSSH(unsigned Opcode) {
27931
0
  switch (Opcode) {
27932
0
  case VFPCLASSSHZrm:
27933
0
  case VFPCLASSSHZrmk:
27934
0
  case VFPCLASSSHZrr:
27935
0
  case VFPCLASSSHZrrk:
27936
0
    return true;
27937
0
  }
27938
0
  return false;
27939
0
}
27940
27941
0
bool isVPSHLQ(unsigned Opcode) {
27942
0
  switch (Opcode) {
27943
0
  case VPSHLQmr:
27944
0
  case VPSHLQrm:
27945
0
  case VPSHLQrr:
27946
0
  case VPSHLQrr_REV:
27947
0
    return true;
27948
0
  }
27949
0
  return false;
27950
0
}
27951
27952
0
bool isVROUNDPS(unsigned Opcode) {
27953
0
  switch (Opcode) {
27954
0
  case VROUNDPSYm:
27955
0
  case VROUNDPSYr:
27956
0
  case VROUNDPSm:
27957
0
  case VROUNDPSr:
27958
0
    return true;
27959
0
  }
27960
0
  return false;
27961
0
}
27962
27963
0
bool isVSCATTERPF0QPS(unsigned Opcode) {
27964
0
  return Opcode == VSCATTERPF0QPSm;
27965
0
}
27966
27967
0
bool isVPERMI2D(unsigned Opcode) {
27968
0
  switch (Opcode) {
27969
0
  case VPERMI2DZ128rm:
27970
0
  case VPERMI2DZ128rmb:
27971
0
  case VPERMI2DZ128rmbk:
27972
0
  case VPERMI2DZ128rmbkz:
27973
0
  case VPERMI2DZ128rmk:
27974
0
  case VPERMI2DZ128rmkz:
27975
0
  case VPERMI2DZ128rr:
27976
0
  case VPERMI2DZ128rrk:
27977
0
  case VPERMI2DZ128rrkz:
27978
0
  case VPERMI2DZ256rm:
27979
0
  case VPERMI2DZ256rmb:
27980
0
  case VPERMI2DZ256rmbk:
27981
0
  case VPERMI2DZ256rmbkz:
27982
0
  case VPERMI2DZ256rmk:
27983
0
  case VPERMI2DZ256rmkz:
27984
0
  case VPERMI2DZ256rr:
27985
0
  case VPERMI2DZ256rrk:
27986
0
  case VPERMI2DZ256rrkz:
27987
0
  case VPERMI2DZrm:
27988
0
  case VPERMI2DZrmb:
27989
0
  case VPERMI2DZrmbk:
27990
0
  case VPERMI2DZrmbkz:
27991
0
  case VPERMI2DZrmk:
27992
0
  case VPERMI2DZrmkz:
27993
0
  case VPERMI2DZrr:
27994
0
  case VPERMI2DZrrk:
27995
0
  case VPERMI2DZrrkz:
27996
0
    return true;
27997
0
  }
27998
0
  return false;
27999
0
}
28000
28001
0
bool isFUCOMP(unsigned Opcode) {
28002
0
  return Opcode == UCOM_FPr;
28003
0
}
28004
28005
0
bool isVCVTTPS2QQ(unsigned Opcode) {
28006
0
  switch (Opcode) {
28007
0
  case VCVTTPS2QQZ128rm:
28008
0
  case VCVTTPS2QQZ128rmb:
28009
0
  case VCVTTPS2QQZ128rmbk:
28010
0
  case VCVTTPS2QQZ128rmbkz:
28011
0
  case VCVTTPS2QQZ128rmk:
28012
0
  case VCVTTPS2QQZ128rmkz:
28013
0
  case VCVTTPS2QQZ128rr:
28014
0
  case VCVTTPS2QQZ128rrk:
28015
0
  case VCVTTPS2QQZ128rrkz:
28016
0
  case VCVTTPS2QQZ256rm:
28017
0
  case VCVTTPS2QQZ256rmb:
28018
0
  case VCVTTPS2QQZ256rmbk:
28019
0
  case VCVTTPS2QQZ256rmbkz:
28020
0
  case VCVTTPS2QQZ256rmk:
28021
0
  case VCVTTPS2QQZ256rmkz:
28022
0
  case VCVTTPS2QQZ256rr:
28023
0
  case VCVTTPS2QQZ256rrk:
28024
0
  case VCVTTPS2QQZ256rrkz:
28025
0
  case VCVTTPS2QQZrm:
28026
0
  case VCVTTPS2QQZrmb:
28027
0
  case VCVTTPS2QQZrmbk:
28028
0
  case VCVTTPS2QQZrmbkz:
28029
0
  case VCVTTPS2QQZrmk:
28030
0
  case VCVTTPS2QQZrmkz:
28031
0
  case VCVTTPS2QQZrr:
28032
0
  case VCVTTPS2QQZrrb:
28033
0
  case VCVTTPS2QQZrrbk:
28034
0
  case VCVTTPS2QQZrrbkz:
28035
0
  case VCVTTPS2QQZrrk:
28036
0
  case VCVTTPS2QQZrrkz:
28037
0
    return true;
28038
0
  }
28039
0
  return false;
28040
0
}
28041
28042
0
bool isPUSHFD(unsigned Opcode) {
28043
0
  return Opcode == PUSHF32;
28044
0
}
28045
28046
0
bool isKORB(unsigned Opcode) {
28047
0
  return Opcode == KORBrr;
28048
0
}
28049
28050
0
bool isVRCP28PD(unsigned Opcode) {
28051
0
  switch (Opcode) {
28052
0
  case VRCP28PDZm:
28053
0
  case VRCP28PDZmb:
28054
0
  case VRCP28PDZmbk:
28055
0
  case VRCP28PDZmbkz:
28056
0
  case VRCP28PDZmk:
28057
0
  case VRCP28PDZmkz:
28058
0
  case VRCP28PDZr:
28059
0
  case VRCP28PDZrb:
28060
0
  case VRCP28PDZrbk:
28061
0
  case VRCP28PDZrbkz:
28062
0
  case VRCP28PDZrk:
28063
0
  case VRCP28PDZrkz:
28064
0
    return true;
28065
0
  }
28066
0
  return false;
28067
0
}
28068
28069
0
bool isVPABSD(unsigned Opcode) {
28070
0
  switch (Opcode) {
28071
0
  case VPABSDYrm:
28072
0
  case VPABSDYrr:
28073
0
  case VPABSDZ128rm:
28074
0
  case VPABSDZ128rmb:
28075
0
  case VPABSDZ128rmbk:
28076
0
  case VPABSDZ128rmbkz:
28077
0
  case VPABSDZ128rmk:
28078
0
  case VPABSDZ128rmkz:
28079
0
  case VPABSDZ128rr:
28080
0
  case VPABSDZ128rrk:
28081
0
  case VPABSDZ128rrkz:
28082
0
  case VPABSDZ256rm:
28083
0
  case VPABSDZ256rmb:
28084
0
  case VPABSDZ256rmbk:
28085
0
  case VPABSDZ256rmbkz:
28086
0
  case VPABSDZ256rmk:
28087
0
  case VPABSDZ256rmkz:
28088
0
  case VPABSDZ256rr:
28089
0
  case VPABSDZ256rrk:
28090
0
  case VPABSDZ256rrkz:
28091
0
  case VPABSDZrm:
28092
0
  case VPABSDZrmb:
28093
0
  case VPABSDZrmbk:
28094
0
  case VPABSDZrmbkz:
28095
0
  case VPABSDZrmk:
28096
0
  case VPABSDZrmkz:
28097
0
  case VPABSDZrr:
28098
0
  case VPABSDZrrk:
28099
0
  case VPABSDZrrkz:
28100
0
  case VPABSDrm:
28101
0
  case VPABSDrr:
28102
0
    return true;
28103
0
  }
28104
0
  return false;
28105
0
}
28106
28107
0
bool isVROUNDSS(unsigned Opcode) {
28108
0
  switch (Opcode) {
28109
0
  case VROUNDSSm_Int:
28110
0
  case VROUNDSSr_Int:
28111
0
    return true;
28112
0
  }
28113
0
  return false;
28114
0
}
28115
28116
0
bool isVCVTSD2USI(unsigned Opcode) {
28117
0
  switch (Opcode) {
28118
0
  case VCVTSD2USI64Zrm_Int:
28119
0
  case VCVTSD2USI64Zrr_Int:
28120
0
  case VCVTSD2USI64Zrrb_Int:
28121
0
  case VCVTSD2USIZrm_Int:
28122
0
  case VCVTSD2USIZrr_Int:
28123
0
  case VCVTSD2USIZrrb_Int:
28124
0
    return true;
28125
0
  }
28126
0
  return false;
28127
0
}
28128
28129
0
bool isVPERMPD(unsigned Opcode) {
28130
0
  switch (Opcode) {
28131
0
  case VPERMPDYmi:
28132
0
  case VPERMPDYri:
28133
0
  case VPERMPDZ256mbi:
28134
0
  case VPERMPDZ256mbik:
28135
0
  case VPERMPDZ256mbikz:
28136
0
  case VPERMPDZ256mi:
28137
0
  case VPERMPDZ256mik:
28138
0
  case VPERMPDZ256mikz:
28139
0
  case VPERMPDZ256ri:
28140
0
  case VPERMPDZ256rik:
28141
0
  case VPERMPDZ256rikz:
28142
0
  case VPERMPDZ256rm:
28143
0
  case VPERMPDZ256rmb:
28144
0
  case VPERMPDZ256rmbk:
28145
0
  case VPERMPDZ256rmbkz:
28146
0
  case VPERMPDZ256rmk:
28147
0
  case VPERMPDZ256rmkz:
28148
0
  case VPERMPDZ256rr:
28149
0
  case VPERMPDZ256rrk:
28150
0
  case VPERMPDZ256rrkz:
28151
0
  case VPERMPDZmbi:
28152
0
  case VPERMPDZmbik:
28153
0
  case VPERMPDZmbikz:
28154
0
  case VPERMPDZmi:
28155
0
  case VPERMPDZmik:
28156
0
  case VPERMPDZmikz:
28157
0
  case VPERMPDZri:
28158
0
  case VPERMPDZrik:
28159
0
  case VPERMPDZrikz:
28160
0
  case VPERMPDZrm:
28161
0
  case VPERMPDZrmb:
28162
0
  case VPERMPDZrmbk:
28163
0
  case VPERMPDZrmbkz:
28164
0
  case VPERMPDZrmk:
28165
0
  case VPERMPDZrmkz:
28166
0
  case VPERMPDZrr:
28167
0
  case VPERMPDZrrk:
28168
0
  case VPERMPDZrrkz:
28169
0
    return true;
28170
0
  }
28171
0
  return false;
28172
0
}
28173
28174
0
bool isPMAXUD(unsigned Opcode) {
28175
0
  switch (Opcode) {
28176
0
  case PMAXUDrm:
28177
0
  case PMAXUDrr:
28178
0
    return true;
28179
0
  }
28180
0
  return false;
28181
0
}
28182
28183
0
bool isVPMULHUW(unsigned Opcode) {
28184
0
  switch (Opcode) {
28185
0
  case VPMULHUWYrm:
28186
0
  case VPMULHUWYrr:
28187
0
  case VPMULHUWZ128rm:
28188
0
  case VPMULHUWZ128rmk:
28189
0
  case VPMULHUWZ128rmkz:
28190
0
  case VPMULHUWZ128rr:
28191
0
  case VPMULHUWZ128rrk:
28192
0
  case VPMULHUWZ128rrkz:
28193
0
  case VPMULHUWZ256rm:
28194
0
  case VPMULHUWZ256rmk:
28195
0
  case VPMULHUWZ256rmkz:
28196
0
  case VPMULHUWZ256rr:
28197
0
  case VPMULHUWZ256rrk:
28198
0
  case VPMULHUWZ256rrkz:
28199
0
  case VPMULHUWZrm:
28200
0
  case VPMULHUWZrmk:
28201
0
  case VPMULHUWZrmkz:
28202
0
  case VPMULHUWZrr:
28203
0
  case VPMULHUWZrrk:
28204
0
  case VPMULHUWZrrkz:
28205
0
  case VPMULHUWrm:
28206
0
  case VPMULHUWrr:
28207
0
    return true;
28208
0
  }
28209
0
  return false;
28210
0
}
28211
28212
0
bool isVPABSB(unsigned Opcode) {
28213
0
  switch (Opcode) {
28214
0
  case VPABSBYrm:
28215
0
  case VPABSBYrr:
28216
0
  case VPABSBZ128rm:
28217
0
  case VPABSBZ128rmk:
28218
0
  case VPABSBZ128rmkz:
28219
0
  case VPABSBZ128rr:
28220
0
  case VPABSBZ128rrk:
28221
0
  case VPABSBZ128rrkz:
28222
0
  case VPABSBZ256rm:
28223
0
  case VPABSBZ256rmk:
28224
0
  case VPABSBZ256rmkz:
28225
0
  case VPABSBZ256rr:
28226
0
  case VPABSBZ256rrk:
28227
0
  case VPABSBZ256rrkz:
28228
0
  case VPABSBZrm:
28229
0
  case VPABSBZrmk:
28230
0
  case VPABSBZrmkz:
28231
0
  case VPABSBZrr:
28232
0
  case VPABSBZrrk:
28233
0
  case VPABSBZrrkz:
28234
0
  case VPABSBrm:
28235
0
  case VPABSBrr:
28236
0
    return true;
28237
0
  }
28238
0
  return false;
28239
0
}
28240
28241
0
bool isFCHS(unsigned Opcode) {
28242
0
  return Opcode == CHS_F;
28243
0
}
28244
28245
0
bool isVPBLENDMB(unsigned Opcode) {
28246
0
  switch (Opcode) {
28247
0
  case VPBLENDMBZ128rm:
28248
0
  case VPBLENDMBZ128rmk:
28249
0
  case VPBLENDMBZ128rmkz:
28250
0
  case VPBLENDMBZ128rr:
28251
0
  case VPBLENDMBZ128rrk:
28252
0
  case VPBLENDMBZ128rrkz:
28253
0
  case VPBLENDMBZ256rm:
28254
0
  case VPBLENDMBZ256rmk:
28255
0
  case VPBLENDMBZ256rmkz:
28256
0
  case VPBLENDMBZ256rr:
28257
0
  case VPBLENDMBZ256rrk:
28258
0
  case VPBLENDMBZ256rrkz:
28259
0
  case VPBLENDMBZrm:
28260
0
  case VPBLENDMBZrmk:
28261
0
  case VPBLENDMBZrmkz:
28262
0
  case VPBLENDMBZrr:
28263
0
  case VPBLENDMBZrrk:
28264
0
  case VPBLENDMBZrrkz:
28265
0
    return true;
28266
0
  }
28267
0
  return false;
28268
0
}
28269
28270
0
bool isVGETMANTSS(unsigned Opcode) {
28271
0
  switch (Opcode) {
28272
0
  case VGETMANTSSZrmi:
28273
0
  case VGETMANTSSZrmik:
28274
0
  case VGETMANTSSZrmikz:
28275
0
  case VGETMANTSSZrri:
28276
0
  case VGETMANTSSZrrib:
28277
0
  case VGETMANTSSZrribk:
28278
0
  case VGETMANTSSZrribkz:
28279
0
  case VGETMANTSSZrrik:
28280
0
  case VGETMANTSSZrrikz:
28281
0
    return true;
28282
0
  }
28283
0
  return false;
28284
0
}
28285
28286
0
bool isVPSLLW(unsigned Opcode) {
28287
0
  switch (Opcode) {
28288
0
  case VPSLLWYri:
28289
0
  case VPSLLWYrm:
28290
0
  case VPSLLWYrr:
28291
0
  case VPSLLWZ128mi:
28292
0
  case VPSLLWZ128mik:
28293
0
  case VPSLLWZ128mikz:
28294
0
  case VPSLLWZ128ri:
28295
0
  case VPSLLWZ128rik:
28296
0
  case VPSLLWZ128rikz:
28297
0
  case VPSLLWZ128rm:
28298
0
  case VPSLLWZ128rmk:
28299
0
  case VPSLLWZ128rmkz:
28300
0
  case VPSLLWZ128rr:
28301
0
  case VPSLLWZ128rrk:
28302
0
  case VPSLLWZ128rrkz:
28303
0
  case VPSLLWZ256mi:
28304
0
  case VPSLLWZ256mik:
28305
0
  case VPSLLWZ256mikz:
28306
0
  case VPSLLWZ256ri:
28307
0
  case VPSLLWZ256rik:
28308
0
  case VPSLLWZ256rikz:
28309
0
  case VPSLLWZ256rm:
28310
0
  case VPSLLWZ256rmk:
28311
0
  case VPSLLWZ256rmkz:
28312
0
  case VPSLLWZ256rr:
28313
0
  case VPSLLWZ256rrk:
28314
0
  case VPSLLWZ256rrkz:
28315
0
  case VPSLLWZmi:
28316
0
  case VPSLLWZmik:
28317
0
  case VPSLLWZmikz:
28318
0
  case VPSLLWZri:
28319
0
  case VPSLLWZrik:
28320
0
  case VPSLLWZrikz:
28321
0
  case VPSLLWZrm:
28322
0
  case VPSLLWZrmk:
28323
0
  case VPSLLWZrmkz:
28324
0
  case VPSLLWZrr:
28325
0
  case VPSLLWZrrk:
28326
0
  case VPSLLWZrrkz:
28327
0
  case VPSLLWri:
28328
0
  case VPSLLWrm:
28329
0
  case VPSLLWrr:
28330
0
    return true;
28331
0
  }
28332
0
  return false;
28333
0
}
28334
28335
0
bool isVDIVPD(unsigned Opcode) {
28336
0
  switch (Opcode) {
28337
0
  case VDIVPDYrm:
28338
0
  case VDIVPDYrr:
28339
0
  case VDIVPDZ128rm:
28340
0
  case VDIVPDZ128rmb:
28341
0
  case VDIVPDZ128rmbk:
28342
0
  case VDIVPDZ128rmbkz:
28343
0
  case VDIVPDZ128rmk:
28344
0
  case VDIVPDZ128rmkz:
28345
0
  case VDIVPDZ128rr:
28346
0
  case VDIVPDZ128rrk:
28347
0
  case VDIVPDZ128rrkz:
28348
0
  case VDIVPDZ256rm:
28349
0
  case VDIVPDZ256rmb:
28350
0
  case VDIVPDZ256rmbk:
28351
0
  case VDIVPDZ256rmbkz:
28352
0
  case VDIVPDZ256rmk:
28353
0
  case VDIVPDZ256rmkz:
28354
0
  case VDIVPDZ256rr:
28355
0
  case VDIVPDZ256rrk:
28356
0
  case VDIVPDZ256rrkz:
28357
0
  case VDIVPDZrm:
28358
0
  case VDIVPDZrmb:
28359
0
  case VDIVPDZrmbk:
28360
0
  case VDIVPDZrmbkz:
28361
0
  case VDIVPDZrmk:
28362
0
  case VDIVPDZrmkz:
28363
0
  case VDIVPDZrr:
28364
0
  case VDIVPDZrrb:
28365
0
  case VDIVPDZrrbk:
28366
0
  case VDIVPDZrrbkz:
28367
0
  case VDIVPDZrrk:
28368
0
  case VDIVPDZrrkz:
28369
0
  case VDIVPDrm:
28370
0
  case VDIVPDrr:
28371
0
    return true;
28372
0
  }
28373
0
  return false;
28374
0
}
28375
28376
0
bool isBLCMSK(unsigned Opcode) {
28377
0
  switch (Opcode) {
28378
0
  case BLCMSK32rm:
28379
0
  case BLCMSK32rr:
28380
0
  case BLCMSK64rm:
28381
0
  case BLCMSK64rr:
28382
0
    return true;
28383
0
  }
28384
0
  return false;
28385
0
}
28386
28387
0
bool isFDIV(unsigned Opcode) {
28388
0
  switch (Opcode) {
28389
0
  case DIV_F32m:
28390
0
  case DIV_F64m:
28391
0
  case DIV_FST0r:
28392
0
  case DIV_FrST0:
28393
0
    return true;
28394
0
  }
28395
0
  return false;
28396
0
}
28397
28398
0
bool isRSQRTSS(unsigned Opcode) {
28399
0
  switch (Opcode) {
28400
0
  case RSQRTSSm_Int:
28401
0
  case RSQRTSSr_Int:
28402
0
    return true;
28403
0
  }
28404
0
  return false;
28405
0
}
28406
28407
0
bool isPOR(unsigned Opcode) {
28408
0
  switch (Opcode) {
28409
0
  case MMX_PORrm:
28410
0
  case MMX_PORrr:
28411
0
  case PORrm:
28412
0
  case PORrr:
28413
0
    return true;
28414
0
  }
28415
0
  return false;
28416
0
}
28417
28418
0
bool isVMOVDQA32(unsigned Opcode) {
28419
0
  switch (Opcode) {
28420
0
  case VMOVDQA32Z128mr:
28421
0
  case VMOVDQA32Z128mrk:
28422
0
  case VMOVDQA32Z128rm:
28423
0
  case VMOVDQA32Z128rmk:
28424
0
  case VMOVDQA32Z128rmkz:
28425
0
  case VMOVDQA32Z128rr:
28426
0
  case VMOVDQA32Z128rr_REV:
28427
0
  case VMOVDQA32Z128rrk:
28428
0
  case VMOVDQA32Z128rrk_REV:
28429
0
  case VMOVDQA32Z128rrkz:
28430
0
  case VMOVDQA32Z128rrkz_REV:
28431
0
  case VMOVDQA32Z256mr:
28432
0
  case VMOVDQA32Z256mrk:
28433
0
  case VMOVDQA32Z256rm:
28434
0
  case VMOVDQA32Z256rmk:
28435
0
  case VMOVDQA32Z256rmkz:
28436
0
  case VMOVDQA32Z256rr:
28437
0
  case VMOVDQA32Z256rr_REV:
28438
0
  case VMOVDQA32Z256rrk:
28439
0
  case VMOVDQA32Z256rrk_REV:
28440
0
  case VMOVDQA32Z256rrkz:
28441
0
  case VMOVDQA32Z256rrkz_REV:
28442
0
  case VMOVDQA32Zmr:
28443
0
  case VMOVDQA32Zmrk:
28444
0
  case VMOVDQA32Zrm:
28445
0
  case VMOVDQA32Zrmk:
28446
0
  case VMOVDQA32Zrmkz:
28447
0
  case VMOVDQA32Zrr:
28448
0
  case VMOVDQA32Zrr_REV:
28449
0
  case VMOVDQA32Zrrk:
28450
0
  case VMOVDQA32Zrrk_REV:
28451
0
  case VMOVDQA32Zrrkz:
28452
0
  case VMOVDQA32Zrrkz_REV:
28453
0
    return true;
28454
0
  }
28455
0
  return false;
28456
0
}
28457
28458
0
bool isVPHADDUWQ(unsigned Opcode) {
28459
0
  switch (Opcode) {
28460
0
  case VPHADDUWQrm:
28461
0
  case VPHADDUWQrr:
28462
0
    return true;
28463
0
  }
28464
0
  return false;
28465
0
}
28466
28467
0
bool isPSRAD(unsigned Opcode) {
28468
0
  switch (Opcode) {
28469
0
  case MMX_PSRADri:
28470
0
  case MMX_PSRADrm:
28471
0
  case MMX_PSRADrr:
28472
0
  case PSRADri:
28473
0
  case PSRADrm:
28474
0
  case PSRADrr:
28475
0
    return true;
28476
0
  }
28477
0
  return false;
28478
0
}
28479
28480
0
bool isPREFETCHW(unsigned Opcode) {
28481
0
  return Opcode == PREFETCHW;
28482
0
}
28483
28484
0
bool isFIDIVR(unsigned Opcode) {
28485
0
  switch (Opcode) {
28486
0
  case DIVR_FI16m:
28487
0
  case DIVR_FI32m:
28488
0
    return true;
28489
0
  }
28490
0
  return false;
28491
0
}
28492
28493
0
bool isMOVHPS(unsigned Opcode) {
28494
0
  switch (Opcode) {
28495
0
  case MOVHPSmr:
28496
0
  case MOVHPSrm:
28497
0
    return true;
28498
0
  }
28499
0
  return false;
28500
0
}
28501
28502
0
bool isVFNMSUB231PH(unsigned Opcode) {
28503
0
  switch (Opcode) {
28504
0
  case VFNMSUB231PHZ128m:
28505
0
  case VFNMSUB231PHZ128mb:
28506
0
  case VFNMSUB231PHZ128mbk:
28507
0
  case VFNMSUB231PHZ128mbkz:
28508
0
  case VFNMSUB231PHZ128mk:
28509
0
  case VFNMSUB231PHZ128mkz:
28510
0
  case VFNMSUB231PHZ128r:
28511
0
  case VFNMSUB231PHZ128rk:
28512
0
  case VFNMSUB231PHZ128rkz:
28513
0
  case VFNMSUB231PHZ256m:
28514
0
  case VFNMSUB231PHZ256mb:
28515
0
  case VFNMSUB231PHZ256mbk:
28516
0
  case VFNMSUB231PHZ256mbkz:
28517
0
  case VFNMSUB231PHZ256mk:
28518
0
  case VFNMSUB231PHZ256mkz:
28519
0
  case VFNMSUB231PHZ256r:
28520
0
  case VFNMSUB231PHZ256rk:
28521
0
  case VFNMSUB231PHZ256rkz:
28522
0
  case VFNMSUB231PHZm:
28523
0
  case VFNMSUB231PHZmb:
28524
0
  case VFNMSUB231PHZmbk:
28525
0
  case VFNMSUB231PHZmbkz:
28526
0
  case VFNMSUB231PHZmk:
28527
0
  case VFNMSUB231PHZmkz:
28528
0
  case VFNMSUB231PHZr:
28529
0
  case VFNMSUB231PHZrb:
28530
0
  case VFNMSUB231PHZrbk:
28531
0
  case VFNMSUB231PHZrbkz:
28532
0
  case VFNMSUB231PHZrk:
28533
0
  case VFNMSUB231PHZrkz:
28534
0
    return true;
28535
0
  }
28536
0
  return false;
28537
0
}
28538
28539
0
bool isUNPCKLPS(unsigned Opcode) {
28540
0
  switch (Opcode) {
28541
0
  case UNPCKLPSrm:
28542
0
  case UNPCKLPSrr:
28543
0
    return true;
28544
0
  }
28545
0
  return false;
28546
0
}
28547
28548
0
bool isVPSIGNB(unsigned Opcode) {
28549
0
  switch (Opcode) {
28550
0
  case VPSIGNBYrm:
28551
0
  case VPSIGNBYrr:
28552
0
  case VPSIGNBrm:
28553
0
  case VPSIGNBrr:
28554
0
    return true;
28555
0
  }
28556
0
  return false;
28557
0
}
28558
28559
0
bool isSAVEPREVSSP(unsigned Opcode) {
28560
0
  return Opcode == SAVEPREVSSP;
28561
0
}
28562
28563
0
bool isVSCALEFSD(unsigned Opcode) {
28564
0
  switch (Opcode) {
28565
0
  case VSCALEFSDZrm:
28566
0
  case VSCALEFSDZrmk:
28567
0
  case VSCALEFSDZrmkz:
28568
0
  case VSCALEFSDZrr:
28569
0
  case VSCALEFSDZrrb_Int:
28570
0
  case VSCALEFSDZrrb_Intk:
28571
0
  case VSCALEFSDZrrb_Intkz:
28572
0
  case VSCALEFSDZrrk:
28573
0
  case VSCALEFSDZrrkz:
28574
0
    return true;
28575
0
  }
28576
0
  return false;
28577
0
}
28578
28579
0
bool isFSIN(unsigned Opcode) {
28580
0
  return Opcode == FSIN;
28581
0
}
28582
28583
0
bool isSCASQ(unsigned Opcode) {
28584
0
  return Opcode == SCASQ;
28585
0
}
28586
28587
0
bool isPCMPGTW(unsigned Opcode) {
28588
0
  switch (Opcode) {
28589
0
  case MMX_PCMPGTWrm:
28590
0
  case MMX_PCMPGTWrr:
28591
0
  case PCMPGTWrm:
28592
0
  case PCMPGTWrr:
28593
0
    return true;
28594
0
  }
28595
0
  return false;
28596
0
}
28597
28598
0
bool isMULX(unsigned Opcode) {
28599
0
  switch (Opcode) {
28600
0
  case MULX32rm:
28601
0
  case MULX32rm_EVEX:
28602
0
  case MULX32rr:
28603
0
  case MULX32rr_EVEX:
28604
0
  case MULX64rm:
28605
0
  case MULX64rm_EVEX:
28606
0
  case MULX64rr:
28607
0
  case MULX64rr_EVEX:
28608
0
    return true;
28609
0
  }
28610
0
  return false;
28611
0
}
28612
28613
0
bool isVPMAXUW(unsigned Opcode) {
28614
0
  switch (Opcode) {
28615
0
  case VPMAXUWYrm:
28616
0
  case VPMAXUWYrr:
28617
0
  case VPMAXUWZ128rm:
28618
0
  case VPMAXUWZ128rmk:
28619
0
  case VPMAXUWZ128rmkz:
28620
0
  case VPMAXUWZ128rr:
28621
0
  case VPMAXUWZ128rrk:
28622
0
  case VPMAXUWZ128rrkz:
28623
0
  case VPMAXUWZ256rm:
28624
0
  case VPMAXUWZ256rmk:
28625
0
  case VPMAXUWZ256rmkz:
28626
0
  case VPMAXUWZ256rr:
28627
0
  case VPMAXUWZ256rrk:
28628
0
  case VPMAXUWZ256rrkz:
28629
0
  case VPMAXUWZrm:
28630
0
  case VPMAXUWZrmk:
28631
0
  case VPMAXUWZrmkz:
28632
0
  case VPMAXUWZrr:
28633
0
  case VPMAXUWZrrk:
28634
0
  case VPMAXUWZrrkz:
28635
0
  case VPMAXUWrm:
28636
0
  case VPMAXUWrr:
28637
0
    return true;
28638
0
  }
28639
0
  return false;
28640
0
}
28641
28642
0
bool isPAUSE(unsigned Opcode) {
28643
0
  return Opcode == PAUSE;
28644
0
}
28645
28646
0
bool isMOVQ2DQ(unsigned Opcode) {
28647
0
  return Opcode == MMX_MOVQ2DQrr;
28648
0
}
28649
28650
0
bool isVPSUBQ(unsigned Opcode) {
28651
0
  switch (Opcode) {
28652
0
  case VPSUBQYrm:
28653
0
  case VPSUBQYrr:
28654
0
  case VPSUBQZ128rm:
28655
0
  case VPSUBQZ128rmb:
28656
0
  case VPSUBQZ128rmbk:
28657
0
  case VPSUBQZ128rmbkz:
28658
0
  case VPSUBQZ128rmk:
28659
0
  case VPSUBQZ128rmkz:
28660
0
  case VPSUBQZ128rr:
28661
0
  case VPSUBQZ128rrk:
28662
0
  case VPSUBQZ128rrkz:
28663
0
  case VPSUBQZ256rm:
28664
0
  case VPSUBQZ256rmb:
28665
0
  case VPSUBQZ256rmbk:
28666
0
  case VPSUBQZ256rmbkz:
28667
0
  case VPSUBQZ256rmk:
28668
0
  case VPSUBQZ256rmkz:
28669
0
  case VPSUBQZ256rr:
28670
0
  case VPSUBQZ256rrk:
28671
0
  case VPSUBQZ256rrkz:
28672
0
  case VPSUBQZrm:
28673
0
  case VPSUBQZrmb:
28674
0
  case VPSUBQZrmbk:
28675
0
  case VPSUBQZrmbkz:
28676
0
  case VPSUBQZrmk:
28677
0
  case VPSUBQZrmkz:
28678
0
  case VPSUBQZrr:
28679
0
  case VPSUBQZrrk:
28680
0
  case VPSUBQZrrkz:
28681
0
  case VPSUBQrm:
28682
0
  case VPSUBQrr:
28683
0
    return true;
28684
0
  }
28685
0
  return false;
28686
0
}
28687
28688
0
bool isVPABSW(unsigned Opcode) {
28689
0
  switch (Opcode) {
28690
0
  case VPABSWYrm:
28691
0
  case VPABSWYrr:
28692
0
  case VPABSWZ128rm:
28693
0
  case VPABSWZ128rmk:
28694
0
  case VPABSWZ128rmkz:
28695
0
  case VPABSWZ128rr:
28696
0
  case VPABSWZ128rrk:
28697
0
  case VPABSWZ128rrkz:
28698
0
  case VPABSWZ256rm:
28699
0
  case VPABSWZ256rmk:
28700
0
  case VPABSWZ256rmkz:
28701
0
  case VPABSWZ256rr:
28702
0
  case VPABSWZ256rrk:
28703
0
  case VPABSWZ256rrkz:
28704
0
  case VPABSWZrm:
28705
0
  case VPABSWZrmk:
28706
0
  case VPABSWZrmkz:
28707
0
  case VPABSWZrr:
28708
0
  case VPABSWZrrk:
28709
0
  case VPABSWZrrkz:
28710
0
  case VPABSWrm:
28711
0
  case VPABSWrr:
28712
0
    return true;
28713
0
  }
28714
0
  return false;
28715
0
}
28716
28717
0
bool isVPCOMPRESSD(unsigned Opcode) {
28718
0
  switch (Opcode) {
28719
0
  case VPCOMPRESSDZ128mr:
28720
0
  case VPCOMPRESSDZ128mrk:
28721
0
  case VPCOMPRESSDZ128rr:
28722
0
  case VPCOMPRESSDZ128rrk:
28723
0
  case VPCOMPRESSDZ128rrkz:
28724
0
  case VPCOMPRESSDZ256mr:
28725
0
  case VPCOMPRESSDZ256mrk:
28726
0
  case VPCOMPRESSDZ256rr:
28727
0
  case VPCOMPRESSDZ256rrk:
28728
0
  case VPCOMPRESSDZ256rrkz:
28729
0
  case VPCOMPRESSDZmr:
28730
0
  case VPCOMPRESSDZmrk:
28731
0
  case VPCOMPRESSDZrr:
28732
0
  case VPCOMPRESSDZrrk:
28733
0
  case VPCOMPRESSDZrrkz:
28734
0
    return true;
28735
0
  }
28736
0
  return false;
28737
0
}
28738
28739
0
bool isVPMOVUSQW(unsigned Opcode) {
28740
0
  switch (Opcode) {
28741
0
  case VPMOVUSQWZ128mr:
28742
0
  case VPMOVUSQWZ128mrk:
28743
0
  case VPMOVUSQWZ128rr:
28744
0
  case VPMOVUSQWZ128rrk:
28745
0
  case VPMOVUSQWZ128rrkz:
28746
0
  case VPMOVUSQWZ256mr:
28747
0
  case VPMOVUSQWZ256mrk:
28748
0
  case VPMOVUSQWZ256rr:
28749
0
  case VPMOVUSQWZ256rrk:
28750
0
  case VPMOVUSQWZ256rrkz:
28751
0
  case VPMOVUSQWZmr:
28752
0
  case VPMOVUSQWZmrk:
28753
0
  case VPMOVUSQWZrr:
28754
0
  case VPMOVUSQWZrrk:
28755
0
  case VPMOVUSQWZrrkz:
28756
0
    return true;
28757
0
  }
28758
0
  return false;
28759
0
}
28760
28761
0
bool isBLENDVPD(unsigned Opcode) {
28762
0
  switch (Opcode) {
28763
0
  case BLENDVPDrm0:
28764
0
  case BLENDVPDrr0:
28765
0
    return true;
28766
0
  }
28767
0
  return false;
28768
0
}
28769
28770
0
bool isVPMOVQB(unsigned Opcode) {
28771
0
  switch (Opcode) {
28772
0
  case VPMOVQBZ128mr:
28773
0
  case VPMOVQBZ128mrk:
28774
0
  case VPMOVQBZ128rr:
28775
0
  case VPMOVQBZ128rrk:
28776
0
  case VPMOVQBZ128rrkz:
28777
0
  case VPMOVQBZ256mr:
28778
0
  case VPMOVQBZ256mrk:
28779
0
  case VPMOVQBZ256rr:
28780
0
  case VPMOVQBZ256rrk:
28781
0
  case VPMOVQBZ256rrkz:
28782
0
  case VPMOVQBZmr:
28783
0
  case VPMOVQBZmrk:
28784
0
  case VPMOVQBZrr:
28785
0
  case VPMOVQBZrrk:
28786
0
  case VPMOVQBZrrkz:
28787
0
    return true;
28788
0
  }
28789
0
  return false;
28790
0
}
28791
28792
0
bool isVBLENDVPS(unsigned Opcode) {
28793
0
  switch (Opcode) {
28794
0
  case VBLENDVPSYrm:
28795
0
  case VBLENDVPSYrr:
28796
0
  case VBLENDVPSrm:
28797
0
  case VBLENDVPSrr:
28798
0
    return true;
28799
0
  }
28800
0
  return false;
28801
0
}
28802
28803
0
bool isKSHIFTLQ(unsigned Opcode) {
28804
0
  return Opcode == KSHIFTLQri;
28805
0
}
28806
28807
0
bool isPMOVSXWD(unsigned Opcode) {
28808
0
  switch (Opcode) {
28809
0
  case PMOVSXWDrm:
28810
0
  case PMOVSXWDrr:
28811
0
    return true;
28812
0
  }
28813
0
  return false;
28814
0
}
28815
28816
0
bool isPHSUBSW(unsigned Opcode) {
28817
0
  switch (Opcode) {
28818
0
  case MMX_PHSUBSWrm:
28819
0
  case MMX_PHSUBSWrr:
28820
0
  case PHSUBSWrm:
28821
0
  case PHSUBSWrr:
28822
0
    return true;
28823
0
  }
28824
0
  return false;
28825
0
}
28826
28827
0
bool isPSRLQ(unsigned Opcode) {
28828
0
  switch (Opcode) {
28829
0
  case MMX_PSRLQri:
28830
0
  case MMX_PSRLQrm:
28831
0
  case MMX_PSRLQrr:
28832
0
  case PSRLQri:
28833
0
  case PSRLQrm:
28834
0
  case PSRLQrr:
28835
0
    return true;
28836
0
  }
28837
0
  return false;
28838
0
}
28839
28840
0
bool isVCVTPH2DQ(unsigned Opcode) {
28841
0
  switch (Opcode) {
28842
0
  case VCVTPH2DQZ128rm:
28843
0
  case VCVTPH2DQZ128rmb:
28844
0
  case VCVTPH2DQZ128rmbk:
28845
0
  case VCVTPH2DQZ128rmbkz:
28846
0
  case VCVTPH2DQZ128rmk:
28847
0
  case VCVTPH2DQZ128rmkz:
28848
0
  case VCVTPH2DQZ128rr:
28849
0
  case VCVTPH2DQZ128rrk:
28850
0
  case VCVTPH2DQZ128rrkz:
28851
0
  case VCVTPH2DQZ256rm:
28852
0
  case VCVTPH2DQZ256rmb:
28853
0
  case VCVTPH2DQZ256rmbk:
28854
0
  case VCVTPH2DQZ256rmbkz:
28855
0
  case VCVTPH2DQZ256rmk:
28856
0
  case VCVTPH2DQZ256rmkz:
28857
0
  case VCVTPH2DQZ256rr:
28858
0
  case VCVTPH2DQZ256rrk:
28859
0
  case VCVTPH2DQZ256rrkz:
28860
0
  case VCVTPH2DQZrm:
28861
0
  case VCVTPH2DQZrmb:
28862
0
  case VCVTPH2DQZrmbk:
28863
0
  case VCVTPH2DQZrmbkz:
28864
0
  case VCVTPH2DQZrmk:
28865
0
  case VCVTPH2DQZrmkz:
28866
0
  case VCVTPH2DQZrr:
28867
0
  case VCVTPH2DQZrrb:
28868
0
  case VCVTPH2DQZrrbk:
28869
0
  case VCVTPH2DQZrrbkz:
28870
0
  case VCVTPH2DQZrrk:
28871
0
  case VCVTPH2DQZrrkz:
28872
0
    return true;
28873
0
  }
28874
0
  return false;
28875
0
}
28876
28877
0
bool isFISUB(unsigned Opcode) {
28878
0
  switch (Opcode) {
28879
0
  case SUB_FI16m:
28880
0
  case SUB_FI32m:
28881
0
    return true;
28882
0
  }
28883
0
  return false;
28884
0
}
28885
28886
0
bool isVCVTPS2UDQ(unsigned Opcode) {
28887
0
  switch (Opcode) {
28888
0
  case VCVTPS2UDQZ128rm:
28889
0
  case VCVTPS2UDQZ128rmb:
28890
0
  case VCVTPS2UDQZ128rmbk:
28891
0
  case VCVTPS2UDQZ128rmbkz:
28892
0
  case VCVTPS2UDQZ128rmk:
28893
0
  case VCVTPS2UDQZ128rmkz:
28894
0
  case VCVTPS2UDQZ128rr:
28895
0
  case VCVTPS2UDQZ128rrk:
28896
0
  case VCVTPS2UDQZ128rrkz:
28897
0
  case VCVTPS2UDQZ256rm:
28898
0
  case VCVTPS2UDQZ256rmb:
28899
0
  case VCVTPS2UDQZ256rmbk:
28900
0
  case VCVTPS2UDQZ256rmbkz:
28901
0
  case VCVTPS2UDQZ256rmk:
28902
0
  case VCVTPS2UDQZ256rmkz:
28903
0
  case VCVTPS2UDQZ256rr:
28904
0
  case VCVTPS2UDQZ256rrk:
28905
0
  case VCVTPS2UDQZ256rrkz:
28906
0
  case VCVTPS2UDQZrm:
28907
0
  case VCVTPS2UDQZrmb:
28908
0
  case VCVTPS2UDQZrmbk:
28909
0
  case VCVTPS2UDQZrmbkz:
28910
0
  case VCVTPS2UDQZrmk:
28911
0
  case VCVTPS2UDQZrmkz:
28912
0
  case VCVTPS2UDQZrr:
28913
0
  case VCVTPS2UDQZrrb:
28914
0
  case VCVTPS2UDQZrrbk:
28915
0
  case VCVTPS2UDQZrrbkz:
28916
0
  case VCVTPS2UDQZrrk:
28917
0
  case VCVTPS2UDQZrrkz:
28918
0
    return true;
28919
0
  }
28920
0
  return false;
28921
0
}
28922
28923
0
bool isVMOVDDUP(unsigned Opcode) {
28924
0
  switch (Opcode) {
28925
0
  case VMOVDDUPYrm:
28926
0
  case VMOVDDUPYrr:
28927
0
  case VMOVDDUPZ128rm:
28928
0
  case VMOVDDUPZ128rmk:
28929
0
  case VMOVDDUPZ128rmkz:
28930
0
  case VMOVDDUPZ128rr:
28931
0
  case VMOVDDUPZ128rrk:
28932
0
  case VMOVDDUPZ128rrkz:
28933
0
  case VMOVDDUPZ256rm:
28934
0
  case VMOVDDUPZ256rmk:
28935
0
  case VMOVDDUPZ256rmkz:
28936
0
  case VMOVDDUPZ256rr:
28937
0
  case VMOVDDUPZ256rrk:
28938
0
  case VMOVDDUPZ256rrkz:
28939
0
  case VMOVDDUPZrm:
28940
0
  case VMOVDDUPZrmk:
28941
0
  case VMOVDDUPZrmkz:
28942
0
  case VMOVDDUPZrr:
28943
0
  case VMOVDDUPZrrk:
28944
0
  case VMOVDDUPZrrkz:
28945
0
  case VMOVDDUPrm:
28946
0
  case VMOVDDUPrr:
28947
0
    return true;
28948
0
  }
28949
0
  return false;
28950
0
}
28951
28952
0
bool isPCMPEQD(unsigned Opcode) {
28953
0
  switch (Opcode) {
28954
0
  case MMX_PCMPEQDrm:
28955
0
  case MMX_PCMPEQDrr:
28956
0
  case PCMPEQDrm:
28957
0
  case PCMPEQDrr:
28958
0
    return true;
28959
0
  }
28960
0
  return false;
28961
0
}
28962
28963
0
bool isVRSQRT28SD(unsigned Opcode) {
28964
0
  switch (Opcode) {
28965
0
  case VRSQRT28SDZm:
28966
0
  case VRSQRT28SDZmk:
28967
0
  case VRSQRT28SDZmkz:
28968
0
  case VRSQRT28SDZr:
28969
0
  case VRSQRT28SDZrb:
28970
0
  case VRSQRT28SDZrbk:
28971
0
  case VRSQRT28SDZrbkz:
28972
0
  case VRSQRT28SDZrk:
28973
0
  case VRSQRT28SDZrkz:
28974
0
    return true;
28975
0
  }
28976
0
  return false;
28977
0
}
28978
28979
0
bool isLODSW(unsigned Opcode) {
28980
0
  return Opcode == LODSW;
28981
0
}
28982
28983
0
bool isVPOPCNTQ(unsigned Opcode) {
28984
0
  switch (Opcode) {
28985
0
  case VPOPCNTQZ128rm:
28986
0
  case VPOPCNTQZ128rmb:
28987
0
  case VPOPCNTQZ128rmbk:
28988
0
  case VPOPCNTQZ128rmbkz:
28989
0
  case VPOPCNTQZ128rmk:
28990
0
  case VPOPCNTQZ128rmkz:
28991
0
  case VPOPCNTQZ128rr:
28992
0
  case VPOPCNTQZ128rrk:
28993
0
  case VPOPCNTQZ128rrkz:
28994
0
  case VPOPCNTQZ256rm:
28995
0
  case VPOPCNTQZ256rmb:
28996
0
  case VPOPCNTQZ256rmbk:
28997
0
  case VPOPCNTQZ256rmbkz:
28998
0
  case VPOPCNTQZ256rmk:
28999
0
  case VPOPCNTQZ256rmkz:
29000
0
  case VPOPCNTQZ256rr:
29001
0
  case VPOPCNTQZ256rrk:
29002
0
  case VPOPCNTQZ256rrkz:
29003
0
  case VPOPCNTQZrm:
29004
0
  case VPOPCNTQZrmb:
29005
0
  case VPOPCNTQZrmbk:
29006
0
  case VPOPCNTQZrmbkz:
29007
0
  case VPOPCNTQZrmk:
29008
0
  case VPOPCNTQZrmkz:
29009
0
  case VPOPCNTQZrr:
29010
0
  case VPOPCNTQZrrk:
29011
0
  case VPOPCNTQZrrkz:
29012
0
    return true;
29013
0
  }
29014
0
  return false;
29015
0
}
29016
29017
0
bool isKSHIFTRB(unsigned Opcode) {
29018
0
  return Opcode == KSHIFTRBri;
29019
0
}
29020
29021
0
bool isVFNMADDPS(unsigned Opcode) {
29022
0
  switch (Opcode) {
29023
0
  case VFNMADDPS4Ymr:
29024
0
  case VFNMADDPS4Yrm:
29025
0
  case VFNMADDPS4Yrr:
29026
0
  case VFNMADDPS4Yrr_REV:
29027
0
  case VFNMADDPS4mr:
29028
0
  case VFNMADDPS4rm:
29029
0
  case VFNMADDPS4rr:
29030
0
  case VFNMADDPS4rr_REV:
29031
0
    return true;
29032
0
  }
29033
0
  return false;
29034
0
}
29035
29036
0
bool isFXRSTOR64(unsigned Opcode) {
29037
0
  return Opcode == FXRSTOR64;
29038
0
}
29039
29040
0
bool isVFMSUBADD213PD(unsigned Opcode) {
29041
0
  switch (Opcode) {
29042
0
  case VFMSUBADD213PDYm:
29043
0
  case VFMSUBADD213PDYr:
29044
0
  case VFMSUBADD213PDZ128m:
29045
0
  case VFMSUBADD213PDZ128mb:
29046
0
  case VFMSUBADD213PDZ128mbk:
29047
0
  case VFMSUBADD213PDZ128mbkz:
29048
0
  case VFMSUBADD213PDZ128mk:
29049
0
  case VFMSUBADD213PDZ128mkz:
29050
0
  case VFMSUBADD213PDZ128r:
29051
0
  case VFMSUBADD213PDZ128rk:
29052
0
  case VFMSUBADD213PDZ128rkz:
29053
0
  case VFMSUBADD213PDZ256m:
29054
0
  case VFMSUBADD213PDZ256mb:
29055
0
  case VFMSUBADD213PDZ256mbk:
29056
0
  case VFMSUBADD213PDZ256mbkz:
29057
0
  case VFMSUBADD213PDZ256mk:
29058
0
  case VFMSUBADD213PDZ256mkz:
29059
0
  case VFMSUBADD213PDZ256r:
29060
0
  case VFMSUBADD213PDZ256rk:
29061
0
  case VFMSUBADD213PDZ256rkz:
29062
0
  case VFMSUBADD213PDZm:
29063
0
  case VFMSUBADD213PDZmb:
29064
0
  case VFMSUBADD213PDZmbk:
29065
0
  case VFMSUBADD213PDZmbkz:
29066
0
  case VFMSUBADD213PDZmk:
29067
0
  case VFMSUBADD213PDZmkz:
29068
0
  case VFMSUBADD213PDZr:
29069
0
  case VFMSUBADD213PDZrb:
29070
0
  case VFMSUBADD213PDZrbk:
29071
0
  case VFMSUBADD213PDZrbkz:
29072
0
  case VFMSUBADD213PDZrk:
29073
0
  case VFMSUBADD213PDZrkz:
29074
0
  case VFMSUBADD213PDm:
29075
0
  case VFMSUBADD213PDr:
29076
0
    return true;
29077
0
  }
29078
0
  return false;
29079
0
}
29080
29081
0
bool isVSQRTPH(unsigned Opcode) {
29082
0
  switch (Opcode) {
29083
0
  case VSQRTPHZ128m:
29084
0
  case VSQRTPHZ128mb:
29085
0
  case VSQRTPHZ128mbk:
29086
0
  case VSQRTPHZ128mbkz:
29087
0
  case VSQRTPHZ128mk:
29088
0
  case VSQRTPHZ128mkz:
29089
0
  case VSQRTPHZ128r:
29090
0
  case VSQRTPHZ128rk:
29091
0
  case VSQRTPHZ128rkz:
29092
0
  case VSQRTPHZ256m:
29093
0
  case VSQRTPHZ256mb:
29094
0
  case VSQRTPHZ256mbk:
29095
0
  case VSQRTPHZ256mbkz:
29096
0
  case VSQRTPHZ256mk:
29097
0
  case VSQRTPHZ256mkz:
29098
0
  case VSQRTPHZ256r:
29099
0
  case VSQRTPHZ256rk:
29100
0
  case VSQRTPHZ256rkz:
29101
0
  case VSQRTPHZm:
29102
0
  case VSQRTPHZmb:
29103
0
  case VSQRTPHZmbk:
29104
0
  case VSQRTPHZmbkz:
29105
0
  case VSQRTPHZmk:
29106
0
  case VSQRTPHZmkz:
29107
0
  case VSQRTPHZr:
29108
0
  case VSQRTPHZrb:
29109
0
  case VSQRTPHZrbk:
29110
0
  case VSQRTPHZrbkz:
29111
0
  case VSQRTPHZrk:
29112
0
  case VSQRTPHZrkz:
29113
0
    return true;
29114
0
  }
29115
0
  return false;
29116
0
}
29117
29118
0
bool isPOPF(unsigned Opcode) {
29119
0
  return Opcode == POPF16;
29120
0
}
29121
29122
0
bool isVPSUBUSB(unsigned Opcode) {
29123
0
  switch (Opcode) {
29124
0
  case VPSUBUSBYrm:
29125
0
  case VPSUBUSBYrr:
29126
0
  case VPSUBUSBZ128rm:
29127
0
  case VPSUBUSBZ128rmk:
29128
0
  case VPSUBUSBZ128rmkz:
29129
0
  case VPSUBUSBZ128rr:
29130
0
  case VPSUBUSBZ128rrk:
29131
0
  case VPSUBUSBZ128rrkz:
29132
0
  case VPSUBUSBZ256rm:
29133
0
  case VPSUBUSBZ256rmk:
29134
0
  case VPSUBUSBZ256rmkz:
29135
0
  case VPSUBUSBZ256rr:
29136
0
  case VPSUBUSBZ256rrk:
29137
0
  case VPSUBUSBZ256rrkz:
29138
0
  case VPSUBUSBZrm:
29139
0
  case VPSUBUSBZrmk:
29140
0
  case VPSUBUSBZrmkz:
29141
0
  case VPSUBUSBZrr:
29142
0
  case VPSUBUSBZrrk:
29143
0
  case VPSUBUSBZrrkz:
29144
0
  case VPSUBUSBrm:
29145
0
  case VPSUBUSBrr:
29146
0
    return true;
29147
0
  }
29148
0
  return false;
29149
0
}
29150
29151
0
bool isPREFETCHIT1(unsigned Opcode) {
29152
0
  return Opcode == PREFETCHIT1;
29153
0
}
29154
29155
0
bool isVPADDSW(unsigned Opcode) {
29156
0
  switch (Opcode) {
29157
0
  case VPADDSWYrm:
29158
0
  case VPADDSWYrr:
29159
0
  case VPADDSWZ128rm:
29160
0
  case VPADDSWZ128rmk:
29161
0
  case VPADDSWZ128rmkz:
29162
0
  case VPADDSWZ128rr:
29163
0
  case VPADDSWZ128rrk:
29164
0
  case VPADDSWZ128rrkz:
29165
0
  case VPADDSWZ256rm:
29166
0
  case VPADDSWZ256rmk:
29167
0
  case VPADDSWZ256rmkz:
29168
0
  case VPADDSWZ256rr:
29169
0
  case VPADDSWZ256rrk:
29170
0
  case VPADDSWZ256rrkz:
29171
0
  case VPADDSWZrm:
29172
0
  case VPADDSWZrmk:
29173
0
  case VPADDSWZrmkz:
29174
0
  case VPADDSWZrr:
29175
0
  case VPADDSWZrrk:
29176
0
  case VPADDSWZrrkz:
29177
0
  case VPADDSWrm:
29178
0
  case VPADDSWrr:
29179
0
    return true;
29180
0
  }
29181
0
  return false;
29182
0
}
29183
29184
0
bool isVADDSUBPD(unsigned Opcode) {
29185
0
  switch (Opcode) {
29186
0
  case VADDSUBPDYrm:
29187
0
  case VADDSUBPDYrr:
29188
0
  case VADDSUBPDrm:
29189
0
  case VADDSUBPDrr:
29190
0
    return true;
29191
0
  }
29192
0
  return false;
29193
0
}
29194
29195
0
bool isKANDD(unsigned Opcode) {
29196
0
  return Opcode == KANDDrr;
29197
0
}
29198
29199
0
bool isOUTSB(unsigned Opcode) {
29200
0
  return Opcode == OUTSB;
29201
0
}
29202
29203
0
bool isFNSTSW(unsigned Opcode) {
29204
0
  switch (Opcode) {
29205
0
  case FNSTSW16r:
29206
0
  case FNSTSWm:
29207
0
    return true;
29208
0
  }
29209
0
  return false;
29210
0
}
29211
29212
0
bool isPMINSB(unsigned Opcode) {
29213
0
  switch (Opcode) {
29214
0
  case PMINSBrm:
29215
0
  case PMINSBrr:
29216
0
    return true;
29217
0
  }
29218
0
  return false;
29219
0
}
29220
29221
#endif // GET_X86_MNEMONIC_TABLES_CPP
29222
29223
} // end namespace X86
29224
} // end namespace llvm