Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/X86/X86GenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace X86 {
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enum : unsigned {
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  InvalidRegBankID = ~0u,
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  GPRRegBankID = 0,
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  VECRRegBankID = 1,
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  NumRegisterBanks,
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};
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} // end namespace X86
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static const RegisterBank *RegBanks[];
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  static const unsigned Sizes[];
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protected:
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  X86GenRegisterBankInfo(unsigned HwMode = 0);
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace X86 {
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const uint32_t GPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (X86::GR8RegClassID - 0)) |
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    (1u << (X86::GR16RegClassID - 0)) |
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    (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
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    (1u << (X86::GR8_NOREX2RegClassID - 0)) |
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    (1u << (X86::GR16_NOREX2RegClassID - 0)) |
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    (1u << (X86::GR8_NOREXRegClassID - 0)) |
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    (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
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    (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
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    (1u << (X86::GR16_NOREXRegClassID - 0)) |
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    (1u << (X86::GR16_ABCDRegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 32)) |
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    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 32)) |
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    (1u << (X86::GR32RegClassID - 32)) |
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    (1u << (X86::GR32_NOSPRegClassID - 32)) |
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    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID - 32)) |
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    (1u << (X86::GR32_NOREX2RegClassID - 32)) |
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    (1u << (X86::GR32_NOREX2_NOSPRegClassID - 32)) |
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    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) |
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    (1u << (X86::GR32_NOREXRegClassID - 32)) |
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    (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
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    (1u << (X86::GR32_ABCDRegClassID - 32)) |
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    (1u << (X86::GR32_TCRegClassID - 32)) |
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    (1u << (X86::GR32_ABCD_and_GR32_TCRegClassID - 32)) |
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    (1u << (X86::GR32_ADRegClassID - 32)) |
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    (1u << (X86::GR32_ArgRefRegClassID - 32)) |
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    (1u << (X86::GR32_DCRegClassID - 32)) |
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    (1u << (X86::GR32_AD_and_GR32_ArgRefRegClassID - 32)) |
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    (1u << (X86::GR32_CBRegClassID - 32)) |
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    (1u << (X86::GR32_SIDIRegClassID - 32)) |
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    (1u << (X86::GR32_BSIRegClassID - 32)) |
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    (1u << (X86::GR32_DIBPRegClassID - 32)) |
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    (1u << (X86::GR32_ABCD_and_GR32_BSIRegClassID - 32)) |
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    (1u << (X86::GR32_BPSPRegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (X86::GR64RegClassID - 64)) |
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    (1u << (X86::GR64_with_sub_8bitRegClassID - 64)) |
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    (1u << (X86::GR64_NOSPRegClassID - 64)) |
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    (1u << (X86::GR64_NOREX2_NOSPRegClassID - 64)) |
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    (1u << (X86::GR64PLTSafeRegClassID - 64)) |
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    (1u << (X86::GR64PLTSafe_and_GR64_TCRegClassID - 64)) |
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    (1u << (X86::GR32_ArgRef_and_GR32_CBRegClassID - 64)) |
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    (1u << (X86::GR32_BSI_and_GR32_SIDIRegClassID - 64)) |
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    (1u << (X86::GR32_DIBP_and_GR32_SIDIRegClassID - 64)) |
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    (1u << (X86::GR64_NOREX_NOSPRegClassID - 64)) |
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    (1u << (X86::GR32_BPSP_and_GR32_DIBPRegClassID - 64)) |
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    (1u << (X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID - 64)) |
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    (1u << (X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID - 64)) |
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    (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID - 64)) |
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    (1u << (X86::GR64_TC_with_sub_8bitRegClassID - 64)) |
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    (1u << (X86::GR32_BPSP_and_GR32_TCRegClassID - 64)) |
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    (1u << (X86::GR64_TCW64_with_sub_8bitRegClassID - 64)) |
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    (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
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    (1u << (X86::GR64_NOREX2RegClassID - 64)) |
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    (1u << (X86::GR64_TCRegClassID - 64)) |
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    (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) |
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    (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) |
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    (1u << (X86::GR64_NOREXRegClassID - 64)) |
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    (1u << (X86::GR64_TCW64RegClassID - 64)) |
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    0,
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    // 96-127
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    (1u << (X86::GR64PLTSafe_and_GR64_TCW64RegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID - 96)) |
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    (1u << (X86::GR64_ADRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID - 96)) |
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    (1u << (X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID - 96)) |
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    (1u << (X86::GR64_ABCDRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_CBRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID - 96)) |
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    (1u << (X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID - 96)) |
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    (1u << (X86::GR64_ArgRef_and_GR64_TCRegClassID - 96)) |
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    (1u << (X86::GR64_ArgRefRegClassID - 96)) |
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    (1u << (X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID - 96)) |
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    (1u << (X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 96)) |
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID - 96)) |
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    (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 96)) |
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    (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 96)) |
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    (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 96)) |
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    0,
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    // 128-159
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    0,
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};
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const uint32_t VECRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (X86::FR16XRegClassID - 0)) |
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    (1u << (X86::FR16RegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (X86::FR32XRegClassID - 32)) |
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    (1u << (X86::FR32RegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (X86::FR64XRegClassID - 64)) |
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    (1u << (X86::FR64RegClassID - 64)) |
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    0,
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    // 96-127
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    (1u << (X86::VR128XRegClassID - 96)) |
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    0,
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    // 128-159
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    (1u << (X86::VR512RegClassID - 128)) |
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    (1u << (X86::VR256XRegClassID - 128)) |
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    (1u << (X86::VR512_0_15RegClassID - 128)) |
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    (1u << (X86::VR128RegClassID - 128)) |
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    (1u << (X86::VR256RegClassID - 128)) |
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    0,
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};
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constexpr RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 134);
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constexpr RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 134);
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} // end namespace X86
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const RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
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    &X86::GPRRegBank,
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    &X86::VECRRegBank,
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};
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const unsigned X86GenRegisterBankInfo::Sizes[] = {
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    // Mode = 0 (Default)
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    64,
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    512,
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};
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X86GenRegisterBankInfo::X86GenRegisterBankInfo(unsigned HwMode)
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    : RegisterBankInfo(RegBanks, X86::NumRegisterBanks, Sizes, HwMode) {
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  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  for (auto RB : enumerate(RegBanks))
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    assert(RB.index() == RB.value()->getID() && "Index != ID");
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#endif // NDEBUG
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}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL