//===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

//

// This file defines the AVR specific subclass of TargetMachine.

//

//===----------------------------------------------------------------------===//

#include "AVRTargetMachine.h"

#include "llvm/CodeGen/Passes.h"

#include "llvm/CodeGen/TargetPassConfig.h"

#include "llvm/IR/Module.h"

#include "llvm/MC/TargetRegistry.h"

#include "AVR.h"

#include "AVRMachineFunctionInfo.h"

#include "AVRTargetObjectFile.h"

#include "MCTargetDesc/AVRMCTargetDesc.h"

#include "TargetInfo/AVRTargetInfo.h"

#include <optional>

namespace llvm {

static const char *AVRDataLayout =

    "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";

/// Processes a CPU name.

static StringRef getCPU(StringRef CPU) {

  if (CPU.empty() || CPU == "generic") {

    return "avr2";

  }

  return CPU;

}

static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {

  return RM.value_or(Reloc::Static);

}

AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,

                                   StringRef CPU, StringRef FS,

                                   const TargetOptions &Options,

                                   std::optional<Reloc::Model> RM,

                                   std::optional<CodeModel::Model> CM,

                                   CodeGenOptLevel OL, bool JIT)

    : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,

                        getEffectiveRelocModel(RM),

                        getEffectiveCodeModel(CM, CodeModel::Small), OL),

      SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) {

  this->TLOF = std::make_unique<AVRTargetObjectFile>();

  initAsmInfo();

}

namespace {

/// AVR Code Generator Pass Configuration Options.

class AVRPassConfig : public TargetPassConfig {

public:

  AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)

      : TargetPassConfig(TM, PM) {}

  AVRTargetMachine &getAVRTargetMachine() const {

    return getTM<AVRTargetMachine>();

  }

  void addIRPasses() override;

  bool addInstSelector() override;

  void addPreSched2() override;

  void addPreEmitPass() override;

};

} // namespace

TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {

  return new AVRPassConfig(*this, PM);

}

void AVRPassConfig::addIRPasses() {

  // Expand instructions like

  //   %result = shl i32 %n, %amount

  // to a loop so that library calls are avoided.

  addPass(createAVRShiftExpandPass());

  TargetPassConfig::addIRPasses();

}

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() {

  // Register the target.

  RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());

  auto &PR = *PassRegistry::getPassRegistry();

  initializeAVRExpandPseudoPass(PR);

  initializeAVRShiftExpandPass(PR);

  initializeAVRDAGToDAGISelPass(PR);

}

const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {

  return &SubTarget;

}

const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {

  return &SubTarget;

}

MachineFunctionInfo *AVRTargetMachine::createMachineFunctionInfo(

    BumpPtrAllocator &Allocator, const Function &F,

    const TargetSubtargetInfo *STI) const {

  return AVRMachineFunctionInfo::create<AVRMachineFunctionInfo>(Allocator, F,

                                                                STI);

}

//===----------------------------------------------------------------------===//

// Pass Pipeline Configuration

//===----------------------------------------------------------------------===//

bool AVRPassConfig::addInstSelector() {

  // Install an instruction selector.

  addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));

  // Create the frame analyzer pass used by the PEI pass.

  addPass(createAVRFrameAnalyzerPass());

  return false;

}

void AVRPassConfig::addPreSched2() {

  addPass(createAVRExpandPseudoPass());

}

void AVRPassConfig::addPreEmitPass() {

  // Must run branch selection immediately preceding the asm printer.

  addPass(&BranchRelaxationPassID);

}

} // end of namespace llvm