Coverage for /pythoncovmergedfiles/medio/medio/usr/local/lib/python3.8/site-packages/archinfo/arch_aarch64.py: 93%

1from .arch import Arch, register_arch, Endness, Register 

2from .tls import TLSArchInfo 

3 

4try: 

5 import capstone as _capstone 

6except ImportError: 

7 _capstone = None 

8 

9try: 

10 import keystone as _keystone 

11except ImportError: 

12 _keystone = None 

13 

14try: 

15 import unicorn as _unicorn 

16except ImportError: 

17 _unicorn = None 

18 

19 

20class ArchAArch64(Arch): 

21 def __init__(self, endness=Endness.LE): 

22 super().__init__(endness) 

23 if endness == Endness.BE: 

24 self.ida_processor = "armb" 

25 self.function_prologs = set() 

26 self.function_epilogs = set() 

27 

28 bits = 64 

29 vex_arch = "VexArchARM64" 

30 name = "AARCH64" 

31 qemu_name = "aarch64" 

32 ida_processor = "arm" 

33 linux_name = "aarch64" 

34 triplet = "aarch64-linux-gnueabihf" 

35 max_inst_bytes = 4 

36 ret_offset = 16 

37 vex_conditional_helpers = True 

38 syscall_num_offset = 80 

39 call_pushes_ret = False 

40 stack_change = -8 

41 memory_endness = Endness.LE 

42 register_endness = Endness.LE 

43 instruction_endness = Endness.LE 

44 sizeof = {"short": 16, "int": 32, "long": 64, "long long": 64} 

45 if _capstone: 

46 cs_arch = _capstone.CS_ARCH_ARM64 

47 cs_mode = _capstone.CS_MODE_LITTLE_ENDIAN 

48 if _keystone: 

49 ks_arch = _keystone.KS_ARCH_ARM64 

50 ks_mode = _keystone.KS_MODE_LITTLE_ENDIAN 

51 uc_arch = _unicorn.UC_ARCH_ARM64 if _unicorn else None 

52 uc_mode = _unicorn.UC_MODE_LITTLE_ENDIAN if _unicorn else None 

53 uc_const = _unicorn.arm64_const if _unicorn else None 

54 uc_prefix = "UC_ARM64_" if _unicorn else None 

55 initial_sp = 0x7FFFFFFFFFF0000 

56 

57 ret_instruction = b"\xC0\x03\x5F\xD6" # ret 

58 nop_instruction = b"\x1F\x20\x03\xD5" # nop 

59 function_prologs = set() 

60 function_epilogs = set() 

61 instruction_alignment = 4 

62 register_list = [ 

63 Register( 

64 name="x0", 

65 size=8, 

66 subregisters=[("w0", 0, 4)], 

67 alias_names=("r0",), 

68 general_purpose=True, 

69 argument=True, 

70 linux_entry_value="ld_destructor", 

71 ), 

72 Register( 

73 name="x1", size=8, subregisters=[("w1", 0, 4)], alias_names=("r1",), general_purpose=True, argument=True 

74 ), 

75 Register( 

76 name="x2", size=8, subregisters=[("w2", 0, 4)], alias_names=("r2",), general_purpose=True, argument=True 

77 ), 

78 Register( 

79 name="x3", size=8, subregisters=[("w3", 0, 4)], alias_names=("r3",), general_purpose=True, argument=True 

80 ), 

81 Register( 

82 name="x4", size=8, subregisters=[("w4", 0, 4)], alias_names=("r4",), general_purpose=True, argument=True 

83 ), 

84 Register( 

85 name="x5", size=8, subregisters=[("w5", 0, 4)], alias_names=("r5",), general_purpose=True, argument=True 

86 ), 

87 Register( 

88 name="x6", size=8, subregisters=[("w6", 0, 4)], alias_names=("r6",), general_purpose=True, argument=True 

89 ), 

90 Register(name="x7", size=8, subregisters=[("w7", 0, 4)], alias_names=("r7",), general_purpose=True), 

91 Register(name="x8", size=8, subregisters=[("w8", 0, 4)], alias_names=("r8",), general_purpose=True), 

92 Register(name="x9", size=8, subregisters=[("w9", 0, 4)], alias_names=("r9",), general_purpose=True), 

93 Register(name="x10", size=8, subregisters=[("w10", 0, 4)], alias_names=("r10",), general_purpose=True), 

94 Register(name="x11", size=8, subregisters=[("w11", 0, 4)], alias_names=("r11",), general_purpose=True), 

95 Register(name="x12", size=8, subregisters=[("w12", 0, 4)], alias_names=("r12",), general_purpose=True), 

96 Register(name="x13", size=8, subregisters=[("w13", 0, 4)], alias_names=("r13",), general_purpose=True), 

97 Register(name="x14", size=8, subregisters=[("w14", 0, 4)], alias_names=("r14",), general_purpose=True), 

98 Register(name="x15", size=8, subregisters=[("w15", 0, 4)], alias_names=("r15",), general_purpose=True), 

99 Register(name="x16", size=8, subregisters=[("w16", 0, 4)], alias_names=("r16", "ip0"), general_purpose=True), 

100 Register(name="x17", size=8, subregisters=[("w17", 0, 4)], alias_names=("r17", "ip1"), general_purpose=True), 

101 Register(name="x18", size=8, subregisters=[("w18", 0, 4)], alias_names=("r18",), general_purpose=True), 

102 Register(name="x19", size=8, subregisters=[("w19", 0, 4)], alias_names=("r19",), general_purpose=True), 

103 Register(name="x20", size=8, subregisters=[("w20", 0, 4)], alias_names=("r20",), general_purpose=True), 

104 Register(name="x21", size=8, subregisters=[("w21", 0, 4)], alias_names=("r21",), general_purpose=True), 

105 Register(name="x22", size=8, subregisters=[("w22", 0, 4)], alias_names=("r22",), general_purpose=True), 

106 Register(name="x23", size=8, subregisters=[("w23", 0, 4)], alias_names=("r23",), general_purpose=True), 

107 Register(name="x24", size=8, subregisters=[("w24", 0, 4)], alias_names=("r24",), general_purpose=True), 

108 Register(name="x25", size=8, subregisters=[("w25", 0, 4)], alias_names=("r25",), general_purpose=True), 

109 Register(name="x26", size=8, subregisters=[("w26", 0, 4)], alias_names=("r26",), general_purpose=True), 

110 Register(name="x27", size=8, subregisters=[("w27", 0, 4)], alias_names=("r27",), general_purpose=True), 

111 Register(name="x28", size=8, subregisters=[("w28", 0, 4)], alias_names=("r28",), general_purpose=True), 

112 Register( 

113 name="x29", size=8, subregisters=[("w29", 0, 4)], alias_names=("r29", "fp", "bp"), general_purpose=True 

114 ), 

115 Register(name="x30", size=8, subregisters=[("w30", 0, 4)], alias_names=("r30", "lr"), general_purpose=True), 

116 Register( 

117 name="xsp", 

118 size=8, 

119 subregisters=[("wsp", 0, 4)], 

120 alias_names=("sp",), 

121 general_purpose=True, 

122 default_value=(initial_sp, True, "global"), 

123 ), 

124 Register(name="pc", size=8, alias_names=("ip",)), 

125 Register(name="cc_op", size=8, artificial=True), 

126 Register(name="cc_dep1", size=8, artificial=True), 

127 Register(name="cc_dep2", size=8, artificial=True), 

128 Register(name="cc_ndep", size=8, artificial=True), 

129 Register(name="tpidr_el0", size=8), 

130 Register( 

131 name="q0", 

132 size=16, 

133 subregisters=[("d0", 0, 8), ("s0", 0, 4), ("h0", 0, 2), ("b0", 0, 1)], 

134 alias_names=("v0",), 

135 floating_point=True, 

136 vector=True, 

137 ), 

138 Register( 

139 name="q1", 

140 size=16, 

141 subregisters=[("d1", 0, 8), ("s1", 0, 4), ("h1", 0, 2), ("b1", 0, 1)], 

142 alias_names=("v1",), 

143 floating_point=True, 

144 vector=True, 

145 ), 

146 Register( 

147 name="q2", 

148 size=16, 

149 subregisters=[("d2", 0, 8), ("s2", 0, 4), ("h2", 0, 2), ("b2", 0, 1)], 

150 alias_names=("v2",), 

151 floating_point=True, 

152 vector=True, 

153 ), 

154 Register( 

155 name="q3", 

156 size=16, 

157 subregisters=[("d3", 0, 8), ("s3", 0, 4), ("h3", 0, 2), ("b3", 0, 1)], 

158 alias_names=("v3",), 

159 floating_point=True, 

160 vector=True, 

161 ), 

162 Register( 

163 name="q4", 

164 size=16, 

165 subregisters=[("d4", 0, 8), ("s4", 0, 4), ("h4", 0, 2), ("b4", 0, 1)], 

166 alias_names=("v4",), 

167 floating_point=True, 

168 vector=True, 

169 ), 

170 Register( 

171 name="q5", 

172 size=16, 

173 subregisters=[("d5", 0, 8), ("s5", 0, 4), ("h5", 0, 2), ("b5", 0, 1)], 

174 alias_names=("v5",), 

175 floating_point=True, 

176 vector=True, 

177 ), 

178 Register( 

179 name="q6", 

180 size=16, 

181 subregisters=[("d6", 0, 8), ("s6", 0, 4), ("h6", 0, 2), ("b6", 0, 1)], 

182 alias_names=("v6",), 

183 floating_point=True, 

184 vector=True, 

185 ), 

186 Register( 

187 name="q7", 

188 size=16, 

189 subregisters=[("d7", 0, 8), ("s7", 0, 4), ("h7", 0, 2), ("b7", 0, 1)], 

190 alias_names=("v7",), 

191 floating_point=True, 

192 vector=True, 

193 ), 

194 Register( 

195 name="q8", 

196 size=16, 

197 subregisters=[("d8", 0, 8), ("s8", 0, 4), ("h8", 0, 2), ("b8", 0, 1)], 

198 alias_names=("v8",), 

199 floating_point=True, 

200 vector=True, 

201 ), 

202 Register( 

203 name="q9", 

204 size=16, 

205 subregisters=[("d9", 0, 8), ("s9", 0, 4), ("h9", 0, 2), ("b9", 0, 1)], 

206 alias_names=("v9",), 

207 floating_point=True, 

208 vector=True, 

209 ), 

210 Register( 

211 name="q10", 

212 size=16, 

213 subregisters=[("d10", 0, 8), ("s10", 0, 4), ("h10", 0, 2), ("b10", 0, 1)], 

214 alias_names=("v10",), 

215 floating_point=True, 

216 vector=True, 

217 ), 

218 Register( 

219 name="q11", 

220 size=16, 

221 subregisters=[("d11", 0, 8), ("s11", 0, 4), ("h11", 0, 2), ("b11", 0, 1)], 

222 alias_names=("v11",), 

223 floating_point=True, 

224 vector=True, 

225 ), 

226 Register( 

227 name="q12", 

228 size=16, 

229 subregisters=[("d12", 0, 8), ("s12", 0, 4), ("h12", 0, 2), ("b12", 0, 1)], 

230 alias_names=("v12",), 

231 floating_point=True, 

232 vector=True, 

233 ), 

234 Register( 

235 name="q13", 

236 size=16, 

237 subregisters=[("d13", 0, 8), ("s13", 0, 4), ("h13", 0, 2), ("b13", 0, 1)], 

238 alias_names=("v13",), 

239 floating_point=True, 

240 vector=True, 

241 ), 

242 Register( 

243 name="q14", 

244 size=16, 

245 subregisters=[("d14", 0, 8), ("s14", 0, 4), ("h14", 0, 2), ("b14", 0, 1)], 

246 alias_names=("v14",), 

247 floating_point=True, 

248 vector=True, 

249 ), 

250 Register( 

251 name="q15", 

252 size=16, 

253 subregisters=[("d15", 0, 8), ("s15", 0, 4), ("h15", 0, 2), ("b15", 0, 1)], 

254 alias_names=("v15",), 

255 floating_point=True, 

256 vector=True, 

257 ), 

258 Register( 

259 name="q16", 

260 size=16, 

261 subregisters=[("d16", 0, 8), ("s16", 0, 4), ("h16", 0, 2), ("b16", 0, 1)], 

262 alias_names=("v16",), 

263 floating_point=True, 

264 vector=True, 

265 ), 

266 Register( 

267 name="q17", 

268 size=16, 

269 subregisters=[("d17", 0, 8), ("s17", 0, 4), ("h17", 0, 2), ("b17", 0, 1)], 

270 alias_names=("v17",), 

271 floating_point=True, 

272 vector=True, 

273 ), 

274 Register( 

275 name="q18", 

276 size=16, 

277 subregisters=[("d18", 0, 8), ("s18", 0, 4), ("h18", 0, 2), ("b18", 0, 1)], 

278 alias_names=("v18",), 

279 floating_point=True, 

280 vector=True, 

281 ), 

282 Register( 

283 name="q19", 

284 size=16, 

285 subregisters=[("d19", 0, 8), ("s19", 0, 4), ("h19", 0, 2), ("b19", 0, 1)], 

286 alias_names=("v19",), 

287 floating_point=True, 

288 vector=True, 

289 ), 

290 Register( 

291 name="q20", 

292 size=16, 

293 subregisters=[("d20", 0, 8), ("s20", 0, 4), ("h20", 0, 2), ("b20", 0, 1)], 

294 alias_names=("v20",), 

295 floating_point=True, 

296 vector=True, 

297 ), 

298 Register( 

299 name="q21", 

300 size=16, 

301 subregisters=[("d21", 0, 8), ("s21", 0, 4), ("h21", 0, 2), ("b21", 0, 1)], 

302 alias_names=("v21",), 

303 floating_point=True, 

304 vector=True, 

305 ), 

306 Register( 

307 name="q22", 

308 size=16, 

309 subregisters=[("d22", 0, 8), ("s22", 0, 4), ("h22", 0, 2), ("b22", 0, 1)], 

310 alias_names=("v22",), 

311 floating_point=True, 

312 vector=True, 

313 ), 

314 Register( 

315 name="q23", 

316 size=16, 

317 subregisters=[("d23", 0, 8), ("s23", 0, 4), ("h23", 0, 2), ("b23", 0, 1)], 

318 alias_names=("v23",), 

319 floating_point=True, 

320 vector=True, 

321 ), 

322 Register( 

323 name="q24", 

324 size=16, 

325 subregisters=[("d24", 0, 8), ("s24", 0, 4), ("h24", 0, 2), ("b24", 0, 1)], 

326 alias_names=("v24",), 

327 floating_point=True, 

328 vector=True, 

329 ), 

330 Register( 

331 name="q25", 

332 size=16, 

333 subregisters=[("d25", 0, 8), ("s25", 0, 4), ("h25", 0, 2), ("b25", 0, 1)], 

334 alias_names=("v25",), 

335 floating_point=True, 

336 vector=True, 

337 ), 

338 Register( 

339 name="q26", 

340 size=16, 

341 subregisters=[("d26", 0, 8), ("s26", 0, 4), ("h26", 0, 2), ("b26", 0, 1)], 

342 alias_names=("v26",), 

343 floating_point=True, 

344 vector=True, 

345 ), 

346 Register( 

347 name="q27", 

348 size=16, 

349 subregisters=[("d27", 0, 8), ("s27", 0, 4), ("h27", 0, 2), ("b27", 0, 1)], 

350 alias_names=("v27",), 

351 floating_point=True, 

352 vector=True, 

353 ), 

354 Register( 

355 name="q28", 

356 size=16, 

357 subregisters=[("d28", 0, 8), ("s28", 0, 4), ("h28", 0, 2), ("b28", 0, 1)], 

358 alias_names=("v28",), 

359 floating_point=True, 

360 vector=True, 

361 ), 

362 Register( 

363 name="q29", 

364 size=16, 

365 subregisters=[("d29", 0, 8), ("s29", 0, 4), ("h29", 0, 2), ("b29", 0, 1)], 

366 alias_names=("v29",), 

367 floating_point=True, 

368 vector=True, 

369 ), 

370 Register( 

371 name="q30", 

372 size=16, 

373 subregisters=[("d30", 0, 8), ("s30", 0, 4), ("h30", 0, 2), ("b30", 0, 1)], 

374 alias_names=("v30",), 

375 floating_point=True, 

376 vector=True, 

377 ), 

378 Register( 

379 name="q31", 

380 size=16, 

381 subregisters=[("d31", 0, 8), ("s31", 0, 4), ("h31", 0, 2), ("b31", 0, 1)], 

382 alias_names=("v31",), 

383 floating_point=True, 

384 vector=True, 

385 ), 

386 Register(name="qcflag", size=16, floating_point=True), 

387 Register(name="emnote", size=4, artificial=True), 

388 Register(name="cmstart", size=8), 

389 Register(name="cmlen", size=8), 

390 Register(name="nraddr", size=8), 

391 Register(name="ip_at_syscall", size=8, artificial=True), 

392 Register(name="fpcr", size=4, floating_point=True, default_value=(initial_sp, True, "global")), 

393 ] 

394 

395 got_section_name = ".got" 

396 ld_linux_name = "ld-linux-aarch64.so.1" 

397 elf_tls = TLSArchInfo(1, 32, [], [0], [], 0, 0) 

398 dwarf_registers = [ 

399 "x0", 

400 "x1", 

401 "x2", 

402 "x3", 

403 "x4", 

404 "x5", 

405 "x6", 

406 "x7", 

407 "x8", 

408 "x9", 

409 "x10", 

410 "x11", 

411 "x12", 

412 "x13", 

413 "x14", 

414 "x15", 

415 "x16", 

416 "x17", 

417 "x18", 

418 "x19", 

419 "x20", 

420 "x21", 

421 "x22", 

422 "x23", 

423 "x24", 

424 "x25", 

425 "x26", 

426 "x27", 

427 "x28", 

428 "x29", 

429 "x30", 

430 "sp", 

431 "<none>", 

432 "ELR_mode", 

433 "RA_SIGN_STATE", 

434 "<none>", 

435 "<none>", 

436 "<none>", 

437 "<none>", 

438 "<none>", 

439 "<none>", 

440 "<none>", 

441 "<none>", 

442 "<none>", 

443 "<none>", 

444 "<none>", 

445 "VG", 

446 "FFR", 

447 "p0", 

448 "p1", 

449 "p2", 

450 "p3", 

451 "p4", 

452 "p5", 

453 "p6", 

454 "p7", 

455 "p8", 

456 "p9", 

457 "p10", 

458 "p11", 

459 "p12", 

460 "p13", 

461 "p14", 

462 "p15", 

463 "v0", 

464 "v1", 

465 "v2", 

466 "v3", 

467 "v4", 

468 "v5", 

469 "v6", 

470 "v7", 

471 "v8", 

472 "v9", 

473 "v10", 

474 "v11", 

475 "v12", 

476 "v13", 

477 "v14", 

478 "v15", 

479 "v16", 

480 "v17", 

481 "v18", 

482 "v19", 

483 "v20", 

484 "v21", 

485 "v22", 

486 "v23", 

487 "v24", 

488 "v25", 

489 "v26", 

490 "v27", 

491 "v28", 

492 "v29", 

493 "v30", 

494 "v31", 

495 "z0", 

496 "z1", 

497 "z2", 

498 "z3", 

499 "z4", 

500 "z5", 

501 "z6", 

502 "z7", 

503 "z8", 

504 "z9", 

505 "z10", 

506 "z11", 

507 "z12", 

508 "z13", 

509 "z14", 

510 "z15", 

511 "z16", 

512 "z17", 

513 "z18", 

514 "z19", 

515 "z20", 

516 "z21", 

517 "z22", 

518 "z23", 

519 "z24", 

520 "z25", 

521 "z26", 

522 "z27", 

523 "z28", 

524 "z29", 

525 "z30", 

526 "z31", 

527 ] 

528 

529 

530register_arch([r".*arm64.*|.*aarch64*"], 64, "any", ArchAArch64)