Coverage for /pythoncovmergedfiles/medio/medio/usr/local/lib/python3.8/site-packages/archinfo/arch_avr.py: 99%
125 statements
« prev ^ index » next coverage.py v7.3.1, created at 2023-09-25 06:15 +0000
« prev ^ index » next coverage.py v7.3.1, created at 2023-09-25 06:15 +0000
1from .arch import Arch, register_arch, Endness
2from .archerror import ArchError
3from .tls import TLSArchInfo
6class ArchAVR8(Arch):
7 bits = 32
8 vex_arch = None
9 name = "AVR8"
10 qemu_name = "avr"
11 linux_name = "avr" # ???
12 triplet = "avr-linux-gnu" # ???
13 max_inst_bytes = 4
14 instruction_alignment = 2
15 elf_tls = TLSArchInfo(1, 8, [], [0], [], 0, 0) # ???
17 def __init__(self, endness=Endness.LE):
18 if endness != Endness.LE:
19 raise ArchError("Arch AVR8 must be little endian")
20 super().__init__(endness)
22 # IO Registers are mapped into the register file starting at 0x20
23 # Any instruction that references an IO register by numer should just add this.
24 self.ioreg_offset = 0x20
25 # Instructions and data are in different memory in AVR
26 # Translate data address into the address space by adding this
27 self.data_offset = 0x10000000
29 self.registers = {}
30 self.registers.update({"r%d" % i: (i, 1) for i in range(0, 32)})
31 self.registers.update({"R%d_R%d" % (i + 1, i): (i, 2) for i in range(0, 32, 2)})
33 self.registers["W"] = (24, 2)
34 self.registers["X"] = (26, 2)
35 self.registers["Y"] = (28, 2)
36 self.registers["Z"] = (30, 2)
38 self.registers["WL"] = (24, 1)
39 self.registers["WH"] = (25, 1)
40 self.registers["XL"] = (26, 1)
41 self.registers["XH"] = (27, 1)
42 self.registers["YL"] = (28, 1)
43 self.registers["YH"] = (29, 1)
44 self.registers["ZL"] = (30, 1)
45 self.registers["ZH"] = (31, 1)
47 self.registers["EEDR"] = (0x40, 1)
48 self.registers["EEARL"] = (0x41, 1)
49 self.registers["EEARH"] = (0x42, 1)
50 self.registers["GTCCR"] = (0x43, 1)
51 self.registers["TCCR0A"] = (0x44, 1)
52 self.registers["TCCR0B"] = (0x45, 1)
53 self.registers["TCNT0"] = (0x46, 1)
54 self.registers["OCR0A"] = (0x47, 1)
55 self.registers["OCR0B"] = (0x48, 1)
56 self.registers["IO_0x29"] = (0x49, 1)
57 self.registers["GPIOR1"] = (0x4A, 1)
58 self.registers["GPIOR2"] = (0x4B, 1)
59 self.registers["SPCR"] = (0x4C, 1)
60 self.registers["SPSR"] = (0x4D, 1)
61 self.registers["SPDR"] = (0x4E, 1)
62 self.registers["IO_0x2f"] = (0x4F, 1)
63 self.registers["ACSR"] = (0x50, 1)
64 self.registers["IO_0x31"] = (0x51, 1)
65 self.registers["IO_0x32"] = (0x52, 1)
66 self.registers["SMCR"] = (0x53, 1)
67 self.registers["MCUSR"] = (0x54, 1)
68 self.registers["MCUCR"] = (0x55, 1)
69 self.registers["IO_0x36"] = (0x56, 1)
70 self.registers["SPMCSR"] = (0x57, 1)
71 self.registers["RAMPD"] = (0x58, 1)
72 self.registers["RAMPX"] = (0x59, 1)
73 self.registers["RAMPY"] = (0x5A, 1)
74 self.registers["RAMPZ"] = (0x5B, 1)
75 self.registers["EIND"] = (0x5C, 1)
77 self.registers["SP"] = (0x5D, 2)
78 self.registers["SPL"] = (0x5D, 1)
79 self.registers["SPH"] = (0x5E, 1)
81 self.registers["SREG"] = (0x5F, 1)
83 self.registers["WDTCSR"] = (0x60, 1)
84 self.registers["CLKPR"] = (0x61, 1)
85 self.registers["PRR"] = (0x64, 1)
86 self.registers["OSCCAL"] = (0x66, 1)
87 self.registers["PCICR"] = (0x68, 1)
88 self.registers["EICRA"] = (0x69, 1)
89 self.registers["PCMSK0"] = (0x6B, 1)
90 self.registers["PCMSK2"] = (0x6D, 1)
91 self.registers["PCMSK1"] = (0x6C, 1)
92 self.registers["TIMSK0"] = (0x6E, 1)
93 self.registers["TIMSK1"] = (0x6F, 1)
94 self.registers["TIMSK2"] = (0x70, 1)
95 self.registers["ADCL"] = (0x78, 1)
96 self.registers["ADCH"] = (0x79, 1)
97 self.registers["ADCSRA"] = (0x7A, 1)
98 self.registers["ADCSRB"] = (0x7B, 1)
99 self.registers["ADMUX"] = (0x7C, 1)
100 self.registers["DIDR0"] = (0x7E, 1)
101 self.registers["DIDR1"] = (0x7F, 1)
102 self.registers["TCCR1A"] = (0x80, 1)
103 self.registers["TCCR1B"] = (0x81, 1)
104 self.registers["TCCR1C"] = (0x82, 1)
105 self.registers["TCNT1H"] = (0x85, 1)
106 self.registers["TCNT1L"] = (0x84, 1)
107 self.registers["ICR1H"] = (0x87, 1)
108 self.registers["ICR1L"] = (0x86, 1)
109 self.registers["OCR1AH"] = (0x89, 1)
110 self.registers["OCR1AL"] = (0x88, 1)
111 self.registers["OCR1BH"] = (0x8B, 1)
112 self.registers["OCR1BL"] = (0x8A, 1)
113 self.registers["TCCR2A"] = (0xB0, 1)
114 self.registers["TCCR2B"] = (0xB1, 1)
115 self.registers["TCNT2"] = (0xB2, 1)
116 self.registers["OCR2A"] = (0xB3, 1)
117 self.registers["OCR2B"] = (0xB4, 1)
118 self.registers["ASSR"] = (0xB6, 1)
119 self.registers["TWBR"] = (0xB8, 1)
120 self.registers["TWSR"] = (0xB9, 1)
121 self.registers["TWAR"] = (0xBA, 1)
122 self.registers["TWDR"] = (0xBB, 1)
123 self.registers["TWCR"] = (0xBC, 1)
124 self.registers["TWAMR"] = (0xBD, 1)
125 self.registers["UCSR0A"] = (0xC0, 1)
126 self.registers["UCSR0B"] = (0xC1, 1)
127 self.registers["UCSR0C"] = (0xC2, 1)
128 self.registers["UBRR0H"] = (0xC5, 1)
129 self.registers["UBRR0L"] = (0xC4, 1)
130 self.registers["UDR0"] = (0xC6, 1)
132 self.registers["pc"] = (0x80000000, 2)
133 self.registers["ip"] = (0x80000000, 2)
134 self.registers["sp"] = self.registers["SP"]
136 self.register_names = {}
137 self.register_names.update({i: "r%d" % i for i in range(0, 32)})
138 self.register_names[self.registers["pc"][0]] = "pc"
139 self.register_names[self.registers["sp"][0]] = "sp"
141 self.ip_offset = self.registers["pc"][0]
142 self.sp_offset = self.registers["sp"][0]
145register_arch([r".*avr"], 32, Endness.LE, ArchAVR8)