Coverage for /pythoncovmergedfiles/medio/medio/usr/local/lib/python3.8/site-packages/archinfo/arch_s390x.py: 86%
51 statements
« prev ^ index » next coverage.py v7.3.1, created at 2023-09-25 06:15 +0000
1try:
2 import capstone as _capstone
3except ImportError:
4 _capstone = None
6try:
7 import keystone as _keystone
8except ImportError:
9 _keystone = None
11try:
12 import pyvex as _pyvex
13except ImportError:
14 _pyvex = None
16from .arch import Arch, register_arch, Endness, Register
17from .archerror import ArchError
18from .tls import TLSArchInfo
21class ArchS390X(Arch):
22 def __init__(self, endness=Endness.BE):
23 super().__init__(endness)
24 if endness != Endness.BE:
25 raise ArchError("Arch s390x must be big endian")
26 self.argument_register_positions = (
27 {
28 self.registers["r2"][0]: 0,
29 self.registers["r3"][0]: 1,
30 self.registers["r4"][0]: 2,
31 self.registers["r5"][0]: 3,
32 self.registers["r6"][0]: 4,
33 # fp registers
34 self.registers["f0"][0]: 0,
35 self.registers["f2"][0]: 1,
36 self.registers["f4"][0]: 2,
37 self.registers["f6"][0]: 3,
38 }
39 if _pyvex is not None
40 else None
41 )
43 bits = 64
44 vex_arch = "VexArchS390X" # enum VexArch
45 name = "S390X"
46 qemu_name = "s390x" # target/s390x
47 triplet = "s390x-linux-gnu"
48 linux_name = "s390" # arch/s390
49 max_inst_bytes = 6
50 ret_offset = 584 # offsetof(VexGuestS390XState, guest_r2)
51 syscall_num_offset = 576 # offsetof(VexGuestS390XState, guest_r1)
52 call_pushes_ret = False
53 stack_change = -8
54 initial_sp = 0x40000000000
55 sizeof = {"short": 16, "int": 32, "long": 64, "long long": 64}
56 if _capstone:
57 cs_arch = _capstone.CS_ARCH_SYSZ
58 cs_mode = _capstone.CS_MODE_BIG_ENDIAN
59 if _keystone:
60 ks_arch = _keystone.KS_ARCH_SYSTEMZ
61 ks_mode = _keystone.KS_MODE_BIG_ENDIAN
62 ret_instruction = b"\x07\xf4" # br %r14
63 nop_instruction = b"\x07\x07" # nopr %r7
64 instruction_alignment = 2
65 register_list = [
66 Register(name="ia", size=8, alias_names=("ip", "pc")),
67 Register(name="r0", size=8, general_purpose=True),
68 Register(name="r1", size=8, general_purpose=True, subregisters=[("r1_32", 4, 4)]),
69 Register(name="r2", size=8, general_purpose=True, argument=True, subregisters=[("r2_32", 4, 4)]),
70 Register(
71 name="r3",
72 size=8,
73 general_purpose=True,
74 argument=True,
75 linux_entry_value="argc",
76 subregisters=[("r3_32", 4, 4)],
77 ),
78 Register(
79 name="r4",
80 size=8,
81 general_purpose=True,
82 argument=True,
83 linux_entry_value="argv",
84 subregisters=[("r4_32", 4, 4)],
85 ),
86 Register(
87 name="r5",
88 size=8,
89 general_purpose=True,
90 argument=True,
91 linux_entry_value="envp",
92 subregisters=[("r5_32", 4, 4)],
93 ),
94 Register(
95 name="r6", size=8, general_purpose=True, argument=True, persistent=True, subregisters=[("r6_32", 4, 4)]
96 ),
97 Register(name="r7", size=8, general_purpose=True, persistent=True, subregisters=[("r7_32", 4, 4)]),
98 Register(name="r8", size=8, general_purpose=True, persistent=True, subregisters=[("r8_32", 4, 4)]),
99 Register(name="r9", size=8, general_purpose=True, persistent=True, subregisters=[("r9_32", 4, 4)]),
100 Register(name="r10", size=8, general_purpose=True, persistent=True, subregisters=[("r10_32", 4, 4)]),
101 Register(
102 name="r11",
103 size=8,
104 alias_names=("bp",),
105 general_purpose=True,
106 persistent=True,
107 subregisters=[("r11_32", 4, 4)],
108 ),
109 Register(name="r12", size=8, general_purpose=True, persistent=True, subregisters=[("r12_32", 4, 4)]),
110 Register(name="r13", size=8, general_purpose=True, persistent=True, subregisters=[("r13_32", 4, 4)]),
111 # Strictly speaking, there is no fixed link register on s390x.
112 # However, %r14 is almost always used for that, so mark it as such.
113 # Situations when that's not the case (e.g. brasl %r0,X)
114 # can still be handled explicitly.
115 Register(name="r14", size=8, general_purpose=True, alias_names=("lr",)),
116 Register(
117 name="r15",
118 size=8,
119 alias_names=("sp",),
120 general_purpose=True,
121 persistent=True,
122 default_value=(initial_sp, True, "global"),
123 ),
124 Register(name="v0", size=16, subregisters=[("f0", 0, 8)], floating_point=True),
125 Register(name="v1", size=16, subregisters=[("f1", 0, 8)], floating_point=True),
126 Register(name="v2", size=16, subregisters=[("f2", 0, 8)], floating_point=True),
127 Register(name="v3", size=16, subregisters=[("f3", 0, 8)], floating_point=True),
128 Register(name="v4", size=16, subregisters=[("f4", 0, 8)], floating_point=True),
129 Register(name="v5", size=16, subregisters=[("f5", 0, 8)], floating_point=True),
130 Register(name="v6", size=16, subregisters=[("f6", 0, 8)], floating_point=True),
131 Register(name="v7", size=16, subregisters=[("f7", 0, 8)], floating_point=True),
132 Register(name="v8", size=16, subregisters=[("f8", 0, 8)], floating_point=True),
133 Register(name="v9", size=16, subregisters=[("f9", 0, 8)], floating_point=True),
134 Register(name="v10", size=16, subregisters=[("f10", 0, 8)], floating_point=True),
135 Register(name="v11", size=16, subregisters=[("f11", 0, 8)], floating_point=True),
136 Register(name="v12", size=16, subregisters=[("f12", 0, 8)], floating_point=True),
137 Register(name="v13", size=16, subregisters=[("f13", 0, 8)], floating_point=True),
138 Register(name="v14", size=16, subregisters=[("f14", 0, 8)], floating_point=True),
139 Register(name="v15", size=16, subregisters=[("f15", 0, 8)], floating_point=True),
140 Register(name="v16", size=16, vector=True),
141 Register(name="v17", size=16, vector=True),
142 Register(name="v18", size=16, vector=True),
143 Register(name="v19", size=16, vector=True),
144 Register(name="v20", size=16, vector=True),
145 Register(name="v21", size=16, vector=True),
146 Register(name="v22", size=16, vector=True),
147 Register(name="v23", size=16, vector=True),
148 Register(name="v24", size=16, vector=True),
149 Register(name="v25", size=16, vector=True),
150 Register(name="v26", size=16, vector=True),
151 Register(name="v27", size=16, vector=True),
152 Register(name="v28", size=16, vector=True),
153 Register(name="v29", size=16, vector=True),
154 Register(name="v30", size=16, vector=True),
155 Register(name="v31", size=16, vector=True),
156 Register(name="a0", size=4),
157 Register(name="a1", size=4),
158 Register(name="a2", size=4),
159 Register(name="a3", size=4),
160 Register(name="a4", size=4),
161 Register(name="a5", size=4),
162 Register(name="a6", size=4),
163 Register(name="a7", size=4),
164 Register(name="a8", size=4),
165 Register(name="a9", size=4),
166 Register(name="a10", size=4),
167 Register(name="a11", size=4),
168 Register(name="a12", size=4),
169 Register(name="a13", size=4),
170 Register(name="a14", size=4),
171 Register(name="a15", size=4),
172 Register(name="nraddr", size=8),
173 Register(name="cmstart", size=8),
174 Register(name="cmlen", size=8),
175 Register(name="ip_at_syscall", size=8, artificial=True),
176 Register(name="emnote", size=4, artificial=True),
177 ]
179 function_prologs = {
180 rb"\xeb.[\xf0-\xff]..\x24", # stmg %r1,%r3,d2(%r15)
181 }
182 function_epilogs = {
183 rb"\x07\xf4", # br %r14
184 }
186 got_section_name = ".got"
187 ld_linux_name = "ld64.so.1"
188 elf_tls = TLSArchInfo(
189 variant=2, # 3.4.7 @ https://www.uclibc.org/docs/tls.pdf
190 tcbhead_size=64, # sizeof(tcbhead_t)
191 head_offsets=[0], # offsetof(tcbhead_t, tcb)
192 dtv_offsets=[8], # offsetof(tcbhead_t, dtv)
193 pthread_offsets=[16], # offsetof(tcbhead_t, self)
194 tp_offset=0,
195 dtv_entry_offset=0,
196 )
198 dwarf_registers = [
199 "v0",
200 "v1",
201 "v2",
202 "v3",
203 "v4",
204 "v5",
205 "v6",
206 "v7",
207 "v8",
208 "v9",
209 "v10",
210 "v11",
211 "v12",
212 "v13",
213 "v14",
214 "v15",
215 "v16",
216 "v17",
217 "v18",
218 "v19",
219 "v20",
220 "v21",
221 "v22",
222 "v23",
223 "v24",
224 "v25",
225 "v26",
226 "v27",
227 "v28",
228 "v29",
229 "v30",
230 "v31",
231 "cr0",
232 "cr1",
233 "cr2",
234 "cr3",
235 "cr4",
236 "cr5",
237 "cr6",
238 "cr7",
239 "cr8",
240 "cr9",
241 "cr10",
242 "cr11",
243 "cr12",
244 "cr13",
245 "cr14",
246 "cr15",
247 "ar0",
248 "ar1",
249 "ar2",
250 "ar3",
251 "ar4",
252 "ar5",
253 "ar6",
254 "ar7",
255 "ar8",
256 "ar9",
257 "ar10",
258 "ar11",
259 "ar12",
260 "ar13",
261 "ar14",
262 "ar15",
263 "psw_mask",
264 "psw_address",
265 ]
268register_arch(["s390"], 64, Endness.BE, ArchS390X)