Coverage for /pythoncovmergedfiles/medio/medio/usr/local/lib/python3.8/site-packages/pyvex/enums.py: 88%

1from typing import List 

2 

3from .native import ffi, pvc 

4from .utils import stable_hash 

5 

6 

7class VEXObject: 

8 """ 

9 The base class for Vex types. 

10 """ 

11 

12 __slots__: List[str] = [] 

13 

14 def __eq__(self, other): 

15 if not isinstance(other, type(self)): 

16 return False 

17 # compare values in slots 

18 for slot in self.__slots__: 

19 if getattr(self, slot) != getattr(other, slot): 

20 return False 

21 return True 

22 

23 def __hash__(self): 

24 values = [getattr(self, slot) for slot in self.__slots__] 

25 for i in range(len(values)): 

26 if isinstance(values[i], list): 

27 values[i] = tuple(values[i]) 

28 return stable_hash(tuple([type(self)] + values)) 

29 

30 

31class IRCallee(VEXObject): 

32 """ 

33 Describes a helper function to call. 

34 """ 

35 

36 __slots__ = ["regparms", "name", "mcx_mask"] 

37 

38 def __init__(self, regparms, name, mcx_mask): 

39 VEXObject.__init__(self) 

40 self.regparms = regparms 

41 self.name = name 

42 self.mcx_mask = mcx_mask 

43 

44 def __str__(self): 

45 return str(self.name) 

46 

47 @staticmethod 

48 def _from_c(c_callee): 

49 return IRCallee( 

50 c_callee.regparms, 

51 ffi.string(c_callee.name).decode(), 

52 # NO. #int(ffi.cast("unsigned long long", c_callee.addr)), 

53 c_callee.mcx_mask, 

54 ) 

55 

56 @staticmethod 

57 def _to_c(callee): # pylint: disable=unused-argument 

58 raise Exception( 

59 "This doesn't work! Please invent a way to get the correct address for the named function from pyvex_c." 

60 ) 

61 # c_callee = pvc.mkIRCallee(callee.regparms, 

62 # callee.name.encode(), 

63 # ffi.cast("void *", callee.addr)) 

64 # c_callee.mcx_mask = callee.mcx_mask 

65 # return c_callee 

66 

67 

68class IRRegArray(VEXObject): 

69 """ 

70 A section of the guest state that we want te be able to index at run time, so as to be able to describe indexed or 

71 rotating register files on the guest. 

72 

73 :ivar int base: The offset into the state that this array starts 

74 :ivar str elemTy: The types of the elements in this array, as VEX enum strings 

75 :ivar int nElems: The number of elements in this array 

76 """ 

77 

78 __slots__ = ["base", "elemTy", "nElems"] 

79 

80 def __init__(self, base, elemTy, nElems): 

81 VEXObject.__init__(self) 

82 self.base = base 

83 self.elemTy = elemTy 

84 self.nElems = nElems 

85 

86 def __str__(self): 

87 return "%s:%sx%d" % (self.base, self.elemTy[4:], self.nElems) 

88 

89 @staticmethod 

90 def _from_c(c_arr): 

91 return IRRegArray(c_arr.base, ints_to_enums[c_arr.elemTy], c_arr.nElems) 

92 

93 @staticmethod 

94 def _to_c(arr): 

95 return pvc.mkIRRegArray(arr.base, get_int_from_enum(arr.elemTy), arr.nElems) 

96 

97 

98ints_to_enums = {} 

99enums_to_ints = {} 

100irop_enums_to_ints = {} 

101will_be_overwritten = ["Ircr_GT", "Ircr_LT"] 

102 

103 

104def get_enum_from_int(i): 

105 return ints_to_enums[i] 

106 

107 

108def get_int_from_enum(e): 

109 return enums_to_ints[e] 

110 

111 

112def _add_enum(s, i=None): # TODO get rid of this 

113 if i is None: 

114 while _add_enum.counter in ints_to_enums: 

115 _add_enum.counter += 1 

116 i = _add_enum.counter 

117 _add_enum.counter += 1 # Update for the next iteration 

118 if i in ints_to_enums: 

119 if ints_to_enums[i] not in will_be_overwritten: 

120 raise ValueError("Enum with intkey %d already present" % i) 

121 enums_to_ints[s] = i 

122 ints_to_enums[i] = s 

123 if s.startswith("Iop_"): 

124 irop_enums_to_ints[s] = i 

125 

126 

127_add_enum.counter = 0 

128 

129for attr in dir(pvc): 

130 if attr[0] in "ABCDEFGHIJKLMNOPQRSTUVWXYZ" and hasattr(pvc, attr) and isinstance(getattr(pvc, attr), int): 

131 _add_enum(attr, getattr(pvc, attr)) 

132 

133 

134def vex_endness_from_string(endness_str): 

135 return getattr(pvc, endness_str) 

136 

137 

138def default_vex_archinfo(): 

139 return { 

140 "hwcaps": 0, 

141 "endness": vex_endness_from_string("VexEndnessLE"), 

142 "ppc_icache_line_szB": 0, 

143 "ppc_dcbz_szB": 0, 

144 "ppc_dcbzl_szB": 0, 

145 "arm64_dMinLine_lg2_szB": 0, 

146 "arm64_iMinLine_lg2_szB": 0, 

147 "hwcache_info": { 

148 "num_levels": 0, 

149 "num_caches": 0, 

150 "caches": None, 

151 "icaches_maintain_coherence": True, 

152 }, 

153 "x86_cr0": 0xFFFFFFFF, 

154 }