Coverage for /pythoncovmergedfiles/medio/medio/usr/local/lib/python3.9/dist-packages/pyvex/arches.py: 96%

1from typing import Dict, List, Tuple 

2 

3from ._register_info import REGISTER_OFFSETS 

4from .enums import default_vex_archinfo, vex_endness_from_string 

5from .types import Register 

6from .vex_ffi import guest_offsets 

7 

8 

9class PyvexArch: 

10 """ 

11 An architecture definition for use with pyvex - usable version. 

12 """ 

13 

14 def __init__(self, name: str, bits: int, memory_endness: str, instruction_endness: str = "Iend_BE"): 

15 self.name = name 

16 self.bits = bits 

17 self.memory_endness = memory_endness 

18 self.instruction_endness = instruction_endness 

19 self.byte_width = 8 

20 self.register_list: List[Register] = [] 

21 self.registers: Dict[str, Tuple[int, int]] = {} 

22 self.vex_arch = { 

23 "X86": "VexArchX86", 

24 "AMD64": "VexArchAMD64", 

25 "ARM": "VexArchARM", 

26 "ARM64": "VexArchARM64", 

27 "PPC32": "VexArchPPC32", 

28 "PPC64": "VexArchPPC64", 

29 "S390X": "VexArchS390X", 

30 "MIPS32": "VexArchMIPS32", 

31 "MIPS64": "VexArchMIPS64", 

32 "RISCV64": "VexArchRISCV64", 

33 }[name] 

34 self.ip_offset = guest_offsets[ 

35 ( 

36 self.vex_name_small, 

37 { 

38 "X86": "eip", 

39 "AMD64": "rip", 

40 "ARM": "r15t", 

41 "ARM64": "pc", 

42 "PPC32": "cia", 

43 "PPC64": "cia", 

44 "S390X": "ia", 

45 "MIPS32": "pc", 

46 "MIPS64": "pc", 

47 "RISCV64": "pc", 

48 }[name], 

49 ) 

50 ] 

51 self.vex_archinfo = default_vex_archinfo() 

52 if memory_endness == "Iend_BE": 

53 self.vex_archinfo["endness"] = vex_endness_from_string("VexEndnessBE") 

54 

55 def __repr__(self): 

56 return f"<PyvexArch {self.name}>" 

57 

58 @property 

59 def vex_name_small(self): 

60 return self.vex_arch[7:].lower() 

61 

62 def translate_register_name(self, offset, size=None): # pylint: disable=unused-argument 

63 for (arch, reg), offset2 in guest_offsets.items(): 

64 if arch == self.vex_name_small and offset2 == offset: 

65 return reg 

66 for (arch, reg), offset2 in REGISTER_OFFSETS.items(): 

67 if arch == self.vex_name_small and offset2 == offset: 

68 return reg 

69 return str(offset) 

70 

71 def get_register_offset(self, name: str) -> int: 

72 arch_reg_tuple = (self.vex_name_small, name) 

73 if arch_reg_tuple in guest_offsets: 

74 return guest_offsets[arch_reg_tuple] 

75 elif arch_reg_tuple in REGISTER_OFFSETS: 

76 return REGISTER_OFFSETS[arch_reg_tuple] 

77 else: 

78 raise KeyError(f"Unknown register {name} for architecture {self.name}") 

79 

80 

81ARCH_X86 = PyvexArch("X86", 32, "Iend_LE") 

82ARCH_AMD64 = PyvexArch("AMD64", 64, "Iend_LE") 

83ARCH_ARM_LE = PyvexArch("ARM", 32, "Iend_LE", instruction_endness="Iend_LE") 

84ARCH_ARM_BE_LE = PyvexArch("ARM", 32, "Iend_BE", instruction_endness="Iend_LE") 

85ARCH_ARM_BE = PyvexArch("ARM", 32, "Iend_LE") 

86ARCH_ARM64_LE = PyvexArch("ARM64", 64, "Iend_LE", instruction_endness="Iend_LE") 

87ARCH_ARM64_BE = PyvexArch("ARM64", 64, "Iend_BE") 

88ARCH_PPC32 = PyvexArch("PPC32", 32, "Iend_BE") 

89ARCH_PPC64_BE = PyvexArch("PPC64", 64, "Iend_BE") 

90ARCH_PPC64_LE = PyvexArch("PPC64", 64, "Iend_LE") 

91ARCH_S390X = PyvexArch("S390X", 64, "Iend_BE") 

92ARCH_MIPS32_BE = PyvexArch("MIPS32", 32, "Iend_BE") 

93ARCH_MIPS32_LE = PyvexArch("MIPS32", 32, "Iend_LE") 

94ARCH_MIPS64_BE = PyvexArch("MIPS64", 64, "Iend_BE") 

95ARCH_MIPS64_LE = PyvexArch("MIPS64", 64, "Iend_LE") 

96ARCH_RISCV64_LE = PyvexArch("RISCV64", 64, "Iend_LE", instruction_endness="Iend_LE")