Coverage for /pythoncovmergedfiles/medio/medio/usr/local/lib/python3.11/site-packages/pyvex/arches.py: 96%

1from ._register_info import REGISTER_OFFSETS 

2from .enums import default_vex_archinfo, vex_endness_from_string 

3from .types import Register 

4from .vex_ffi import guest_offsets 

5 

6 

7class PyvexArch: 

8 """ 

9 An architecture definition for use with pyvex - usable version. 

10 """ 

11 

12 def __init__(self, name: str, bits: int, memory_endness: str, instruction_endness: str = "Iend_BE"): 

13 self.name = name 

14 self.bits = bits 

15 self.memory_endness = memory_endness 

16 self.instruction_endness = instruction_endness 

17 self.byte_width = 8 

18 self.register_list: list[Register] = [] 

19 self.registers: dict[str, tuple[int, int]] = {} 

20 self.vex_arch = { 

21 "X86": "VexArchX86", 

22 "AMD64": "VexArchAMD64", 

23 "ARM": "VexArchARM", 

24 "ARM64": "VexArchARM64", 

25 "PPC32": "VexArchPPC32", 

26 "PPC64": "VexArchPPC64", 

27 "S390X": "VexArchS390X", 

28 "MIPS32": "VexArchMIPS32", 

29 "MIPS64": "VexArchMIPS64", 

30 "RISCV64": "VexArchRISCV64", 

31 }[name] 

32 self.ip_offset = guest_offsets[ 

33 ( 

34 self.vex_name_small, 

35 { 

36 "X86": "eip", 

37 "AMD64": "rip", 

38 "ARM": "r15t", 

39 "ARM64": "pc", 

40 "PPC32": "cia", 

41 "PPC64": "cia", 

42 "S390X": "ia", 

43 "MIPS32": "pc", 

44 "MIPS64": "pc", 

45 "RISCV64": "pc", 

46 }[name], 

47 ) 

48 ] 

49 self.vex_archinfo = default_vex_archinfo() 

50 if memory_endness == "Iend_BE": 

51 self.vex_archinfo["endness"] = vex_endness_from_string("VexEndnessBE") 

52 

53 def __repr__(self): 

54 return f"<PyvexArch {self.name}>" 

55 

56 @property 

57 def vex_name_small(self): 

58 return self.vex_arch[7:].lower() 

59 

60 def translate_register_name(self, offset, size=None): # pylint: disable=unused-argument 

61 for (arch, reg), offset2 in guest_offsets.items(): 

62 if arch == self.vex_name_small and offset2 == offset: 

63 return reg 

64 for (arch, reg), offset2 in REGISTER_OFFSETS.items(): 

65 if arch == self.vex_name_small and offset2 == offset: 

66 return reg 

67 return str(offset) 

68 

69 def get_register_offset(self, name: str) -> int: 

70 arch_reg_tuple = (self.vex_name_small, name) 

71 if arch_reg_tuple in guest_offsets: 

72 return guest_offsets[arch_reg_tuple] 

73 elif arch_reg_tuple in REGISTER_OFFSETS: 

74 return REGISTER_OFFSETS[arch_reg_tuple] 

75 else: 

76 raise KeyError(f"Unknown register {name} for architecture {self.name}") 

77 

78 

79ARCH_X86 = PyvexArch("X86", 32, "Iend_LE") 

80ARCH_AMD64 = PyvexArch("AMD64", 64, "Iend_LE") 

81ARCH_ARM_LE = PyvexArch("ARM", 32, "Iend_LE", instruction_endness="Iend_LE") 

82ARCH_ARM_BE_LE = PyvexArch("ARM", 32, "Iend_BE", instruction_endness="Iend_LE") 

83ARCH_ARM_BE = PyvexArch("ARM", 32, "Iend_LE") 

84ARCH_ARM64_LE = PyvexArch("ARM64", 64, "Iend_LE", instruction_endness="Iend_LE") 

85ARCH_ARM64_BE = PyvexArch("ARM64", 64, "Iend_BE") 

86ARCH_PPC32 = PyvexArch("PPC32", 32, "Iend_BE") 

87ARCH_PPC64_BE = PyvexArch("PPC64", 64, "Iend_BE") 

88ARCH_PPC64_LE = PyvexArch("PPC64", 64, "Iend_LE") 

89ARCH_S390X = PyvexArch("S390X", 64, "Iend_BE") 

90ARCH_MIPS32_BE = PyvexArch("MIPS32", 32, "Iend_BE") 

91ARCH_MIPS32_LE = PyvexArch("MIPS32", 32, "Iend_LE") 

92ARCH_MIPS64_BE = PyvexArch("MIPS64", 64, "Iend_BE") 

93ARCH_MIPS64_LE = PyvexArch("MIPS64", 64, "Iend_LE") 

94ARCH_RISCV64_LE = PyvexArch("RISCV64", 64, "Iend_LE", instruction_endness="Iend_LE")