SerializerIntrinsics_a64

Source file "jnr/a64asm/SerializerIntrinsics_a64.java" was not found during generation of report.

Element	Missed Instructions	Cov.	Missed Branches	Cov.	Missed	Cxty	Missed	Lines	Missed	Methods
Total	1,687 of 1,687	0%	6 of 6	0%	260	260	517	517	257	257
mov(Register, Register)		0%		0%	3	3	4	4	1	1
mov(Register, Immediate)		0%		0%	2	2	4	4	1	1
stxp(Register, Register, Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
add(Register, Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
add(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
add(Register, Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
adds(Register, Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
adds(Register, Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
adds(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
and(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
ands(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
bfi(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
bfm(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
bfxil(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
bic(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
bics(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
ccmn(Register, Immediate, Immediate, Conditions)		0%		n/a	1	1	2	2	1	1
ccmn(Register, Register, Immediate, Conditions)		0%		n/a	1	1	2	2	1	1
ccmp(Register, Immediate, Immediate, Conditions)		0%		n/a	1	1	2	2	1	1
ccmp(Register, Register, Immediate, Conditions)		0%		n/a	1	1	2	2	1	1
csel(Register, Register, Register, Conditions)		0%		n/a	1	1	2	2	1	1
csinc(Register, Register, Register, Conditions)		0%		n/a	1	1	2	2	1	1
csinv(Register, Register, Register, Conditions)		0%		n/a	1	1	2	2	1	1
csneg(Register, Register, Register, Conditions)		0%		n/a	1	1	2	2	1	1
eon(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
eor(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
extr(Register, Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
ldnp(Register, Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
ldpsw(Register, Register, Mem, Immediate)		0%		n/a	1	1	2	2	1	1
madd(Register, Register, Register, Register)		0%		n/a	1	1	2	2	1	1
msub(Register, Register, Register, Register)		0%		n/a	1	1	2	2	1	1
orn(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
orr(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
prfm(PRFOP_ENUM, Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
sbfiz(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
sbfm(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
sbfx(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
smaddl(Register, Register, Register, Register)		0%		n/a	1	1	2	2	1	1
smsubl(Register, Register, Register, Register)		0%		n/a	1	1	2	2	1	1
stlxp(Register, Register, Register, Mem)		0%		n/a	1	1	2	2	1	1
str(Register, Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
strb(Register, Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
strh(Register, Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
sub(Register, Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
sub(Register, Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
sub(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
subs(Register, Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
subs(Register, Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
subs(Register, Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
ubfiz(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
ubfm(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
ubfx(Register, Register, Immediate, Immediate)		0%		n/a	1	1	2	2	1	1
umaddl(Register, Register, Register, Register)		0%		n/a	1	1	2	2	1	1
umsubl(Register, Register, Register, Register)		0%		n/a	1	1	2	2	1	1
adc(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
adcs(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
and(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
ands(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
asr(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
asr(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
asrv(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
cinc(Register, Register, Conditions)		0%		n/a	1	1	2	2	1	1
cinv(Register, Register, Conditions)		0%		n/a	1	1	2	2	1	1
cmn(Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
cmn(Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
cmn(Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
cmp(Register, Register, Ext)		0%		n/a	1	1	2	2	1	1
cmp(Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
cmp(Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
cneg(Register, Register, Conditions)		0%		n/a	1	1	2	2	1	1
eor(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
ldp(Register, Register, Post_index)		0%		n/a	1	1	2	2	1	1
ldp(Register, Register, Pre_index)		0%		n/a	1	1	2	2	1	1
ldp(Register, Register, Offset)		0%		n/a	1	1	2	2	1	1
ldpsw(Register, Register, Pre_index)		0%		n/a	1	1	2	2	1	1
ldpsw(Register, Register, Offset)		0%		n/a	1	1	2	2	1	1
ldrb(Register, Mem, Immediate)		0%		n/a	1	1	2	2	1	1
ldrh(Register, Mem, Immediate)		0%		n/a	1	1	2	2	1	1
ldrsb(Register, Mem, Immediate)		0%		n/a	1	1	2	2	1	1
ldrsh(Register, Mem, Immediate)		0%		n/a	1	1	2	2	1	1
ldrsw(Register, Mem, Immediate)		0%		n/a	1	1	2	2	1	1
lsl(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
lsl(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
lslv(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
lsr(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
lsr(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
lsrv(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
mneg(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
movk(Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
movn(Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
movz(Register, Immediate, Shift)		0%		n/a	1	1	2	2	1	1
mul(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
mvn(Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
neg(Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
negs(Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
orr(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
prfm(PRFOP_ENUM, Register, Immediate)		0%		n/a	1	1	2	2	1	1
prfum(PRFOP_ENUM, Register, Immediate)		0%		n/a	1	1	2	2	1	1
ror(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
ror(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
rorv(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
sbc(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
sbcs(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
sdiv(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
smnegl(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
smulh(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
smull(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
stlrb(Register, Register, Immediate)		0%		n/a	1	1	2	2	1	1
stlxr(Register, Register, Mem)		0%		n/a	1	1	2	2	1	1
stlxrb(Register, Register, Mem)		0%		n/a	1	1	2	2	1	1
stlxrh(Register, Register, Mem)		0%		n/a	1	1	2	2	1	1
stnp(Register, Register, Mem)		0%		n/a	1	1	2	2	1	1
stp(Register, Register, Post_index)		0%		n/a	1	1	2	2	1	1
stp(Register, Register, Pre_index)		0%		n/a	1	1	2	2	1	1
stp(Register, Register, Offset)		0%		n/a	1	1	2	2	1	1
stxr(Register, Register, Offset)		0%		n/a	1	1	2	2	1	1
stxrb(Register, Register, Offset)		0%		n/a	1	1	2	2	1	1
stxrh(Register, Register, Offset)		0%		n/a	1	1	2	2	1	1
tbnz(Register, Immediate, Label)		0%		n/a	1	1	2	2	1	1
tbz(Register, Immediate, Label)		0%		n/a	1	1	2	2	1	1
tst(Register, Register, Shift)		0%		n/a	1	1	2	2	1	1
udiv(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
umnegl(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
umulh(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
umull(Register, Register, Register)		0%		n/a	1	1	2	2	1	1
adr(Register, Label)		0%		n/a	1	1	2	2	1	1
adrp(Register, Label)		0%		n/a	1	1	2	2	1	1
cbnz(Register, Label)		0%		n/a	1	1	2	2	1	1
cbz(Register, Label)		0%		n/a	1	1	2	2	1	1
cls(Register, Register)		0%		n/a	1	1	2	2	1	1
clz(Register, Register)		0%		n/a	1	1	2	2	1	1
cset(Register, Conditions)		0%		n/a	1	1	2	2	1	1
csetm(Register, Conditions)		0%		n/a	1	1	2	2	1	1
dc(Register, Register)		0%		n/a	1	1	2	2	1	1
ic(Register, Register)		0%		n/a	1	1	2	2	1	1
ldar(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldarb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldarh(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldaxp(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldaxr(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldaxrb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldaxrh(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldr(Register, Post_index)		0%		n/a	1	1	2	2	1	1
ldr(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
ldr(Register, Offset)		0%		n/a	1	1	2	2	1	1
ldr(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldrb(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
ldrb(Register, Offset)		0%		n/a	1	1	2	2	1	1
ldrb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldrh(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
ldrh(Register, Offset)		0%		n/a	1	1	2	2	1	1
ldrh(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldrsb(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
ldrsb(Register, Offset)		0%		n/a	1	1	2	2	1	1
ldrsb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldrsh(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
ldrsh(Register, Offset)		0%		n/a	1	1	2	2	1	1
ldrsh(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldrsw(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
ldrsw(Register, Offset)		0%		n/a	1	1	2	2	1	1
ldrsw(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldtr(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldtrb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldtrh(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldtrsb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldtrsh(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldtrsw(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldur(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldurb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldurh(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldursb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldursh(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldursw(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldxp(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldxr(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldxrb(Register, Mem)		0%		n/a	1	1	2	2	1	1
ldxrh(Register, Mem)		0%		n/a	1	1	2	2	1	1
mov(Register, Shift)		0%		n/a	1	1	2	2	1	1
mrs(Register, Register)		0%		n/a	1	1	2	2	1	1
msr(Register, Immediate)		0%		n/a	1	1	2	2	1	1
msr(SysRegister, Register)		0%		n/a	1	1	2	2	1	1
ngc(Register, Register)		0%		n/a	1	1	2	2	1	1
ngcs(Register, Register)		0%		n/a	1	1	2	2	1	1
prfm(PRFOP_ENUM, Immediate)		0%		n/a	1	1	2	2	1	1
rbit(Register, Register)		0%		n/a	1	1	2	2	1	1
rev(Register, Register)		0%		n/a	1	1	2	2	1	1
rev16(Register, Register)		0%		n/a	1	1	2	2	1	1
rev32(Register, Register)		0%		n/a	1	1	2	2	1	1
stlr(Register, Mem)		0%		n/a	1	1	2	2	1	1
stlrh(Register, Mem)		0%		n/a	1	1	2	2	1	1
str(Register, Post_index)		0%		n/a	1	1	2	2	1	1
str(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
str(Register, Offset)		0%		n/a	1	1	2	2	1	1
strb(Register, Post_index)		0%		n/a	1	1	2	2	1	1
strb(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
strb(Register, Offset)		0%		n/a	1	1	2	2	1	1
strh(Register, Post_index)		0%		n/a	1	1	2	2	1	1
strh(Register, Pre_index)		0%		n/a	1	1	2	2	1	1
strh(Register, Offset)		0%		n/a	1	1	2	2	1	1
sttr(Register, Offset)		0%		n/a	1	1	2	2	1	1
sttrb(Register, Offset)		0%		n/a	1	1	2	2	1	1
sttrh(Register, Offset)		0%		n/a	1	1	2	2	1	1
stur(Register, Offset)		0%		n/a	1	1	2	2	1	1
sturb(Register, Offset)		0%		n/a	1	1	2	2	1	1
sturh(Register, Offset)		0%		n/a	1	1	2	2	1	1
sxtb(Register, Register)		0%		n/a	1	1	2	2	1	1
sxth(Register, Register)		0%		n/a	1	1	2	2	1	1
sxtw(Register, Register)		0%		n/a	1	1	2	2	1	1
tst(Register, Immediate)		0%		n/a	1	1	2	2	1	1
uxtb(Register, Register)		0%		n/a	1	1	2	2	1	1
uxth(Register, Register)		0%		n/a	1	1	2	2	1	1
uxtw(Register, Register)		0%		n/a	1	1	2	2	1	1
b(Immediate)		0%		n/a	1	1	2	2	1	1
bcc(Immediate)		0%		n/a	1	1	2	2	1	1
bcs(Immediate)		0%		n/a	1	1	2	2	1	1
beq(Immediate)		0%		n/a	1	1	2	2	1	1
bge(Immediate)		0%		n/a	1	1	2	2	1	1
bgt(Immediate)		0%		n/a	1	1	2	2	1	1
bhi(Immediate)		0%		n/a	1	1	2	2	1	1
bhs(Immediate)		0%		n/a	1	1	2	2	1	1
bl(Immediate)		0%		n/a	1	1	2	2	1	1
ble(Immediate)		0%		n/a	1	1	2	2	1	1
blo(Immediate)		0%		n/a	1	1	2	2	1	1
blr(Register)		0%		n/a	1	1	2	2	1	1
bls(Immediate)		0%		n/a	1	1	2	2	1	1
blt(Immediate)		0%		n/a	1	1	2	2	1	1
bmi(Immediate)		0%		n/a	1	1	2	2	1	1
bne(Immediate)		0%		n/a	1	1	2	2	1	1
bpl(Immediate)		0%		n/a	1	1	2	2	1	1
br(Register)		0%		n/a	1	1	2	2	1	1
brk(Immediate)		0%		n/a	1	1	2	2	1	1
bvc(Immediate)		0%		n/a	1	1	2	2	1	1
bvs(Immediate)		0%		n/a	1	1	2	2	1	1
clrex(Immediate)		0%		n/a	1	1	2	2	1	1
dcps1(Immediate)		0%		n/a	1	1	2	2	1	1
dcps2(Immediate)		0%		n/a	1	1	2	2	1	1
dcps3(Immediate)		0%		n/a	1	1	2	2	1	1
dmb(Immediate)		0%		n/a	1	1	2	2	1	1
dsb(Immediate)		0%		n/a	1	1	2	2	1	1
hint(Immediate)		0%		n/a	1	1	2	2	1	1
hlt(Immediate)		0%		n/a	1	1	2	2	1	1
hvc(Immediate)		0%		n/a	1	1	2	2	1	1
isb(Immediate)		0%		n/a	1	1	2	2	1	1
ldr(Register, Immediate)		0%		n/a	1	1	2	2	1	1
ldrsw(Register, Label)		0%		n/a	1	1	2	2	1	1
ret(Register)		0%		n/a	1	1	2	2	1	1
smc(Immediate)		0%		n/a	1	1	2	2	1	1
svc(Immediate)		0%		n/a	1	1	2	2	1	1
drps()		0%		n/a	1	1	2	2	1	1
eret()		0%		n/a	1	1	2	2	1	1
nop()		0%		n/a	1	1	2	2	1	1
sev()		0%		n/a	1	1	2	2	1	1
sevl()		0%		n/a	1	1	2	2	1	1
wfe()		0%		n/a	1	1	2	2	1	1
wfi()		0%		n/a	1	1	2	2	1	1
yield()		0%		n/a	1	1	2	2	1	1
SerializerIntrinsics_a64()		0%		n/a	1	1	1	1	1	1