/rust/registry/src/index.crates.io-1949cf8c6b5b557f/blake2-0.10.6/src/simd/simdop.rs
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1 | | // Copyright 2015 blake2-rfc Developers |
2 | | // |
3 | | // Licensed under the Apache License, Version 2.0, <LICENSE-APACHE or |
4 | | // http://apache.org/licenses/LICENSE-2.0> or the MIT license <LICENSE-MIT or |
5 | | // http://opensource.org/licenses/MIT>, at your option. This file may not be |
6 | | // copied, modified, or distributed except according to those terms. |
7 | | |
8 | | #[cfg(feature = "simd")] |
9 | | use crate::simd::simdint; |
10 | | use crate::simd::simdty::{u32x4, u64x4}; |
11 | | |
12 | | use core::ops::{Add, BitXor, Shl, Shr}; |
13 | | |
14 | | macro_rules! impl_ops { |
15 | | ($vec:ident) => { |
16 | | impl Add for $vec { |
17 | | type Output = Self; |
18 | | |
19 | | #[cfg(feature = "simd")] |
20 | | #[inline(always)] |
21 | | fn add(self, rhs: Self) -> Self::Output { |
22 | | unsafe { simdint::simd_add(self, rhs) } |
23 | | } |
24 | | |
25 | | #[cfg(not(feature = "simd"))] |
26 | | #[inline(always)] |
27 | 0 | fn add(self, rhs: Self) -> Self::Output { |
28 | 0 | $vec::new( |
29 | 0 | self.0.wrapping_add(rhs.0), |
30 | 0 | self.1.wrapping_add(rhs.1), |
31 | 0 | self.2.wrapping_add(rhs.2), |
32 | 0 | self.3.wrapping_add(rhs.3), |
33 | | ) |
34 | 0 | } Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as core::ops::arith::Add>::add Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as core::ops::arith::Add>::add |
35 | | } |
36 | | |
37 | | impl BitXor for $vec { |
38 | | type Output = Self; |
39 | | |
40 | | #[cfg(feature = "simd")] |
41 | | #[inline(always)] |
42 | | fn bitxor(self, rhs: Self) -> Self::Output { |
43 | | unsafe { simdint::simd_xor(self, rhs) } |
44 | | } |
45 | | |
46 | | #[cfg(not(feature = "simd"))] |
47 | | #[inline(always)] |
48 | 0 | fn bitxor(self, rhs: Self) -> Self::Output { |
49 | 0 | $vec::new( |
50 | 0 | self.0 ^ rhs.0, |
51 | 0 | self.1 ^ rhs.1, |
52 | 0 | self.2 ^ rhs.2, |
53 | 0 | self.3 ^ rhs.3, |
54 | | ) |
55 | 0 | } Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as core::ops::bit::BitXor>::bitxor Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as core::ops::bit::BitXor>::bitxor |
56 | | } |
57 | | |
58 | | impl Shl<$vec> for $vec { |
59 | | type Output = Self; |
60 | | |
61 | | #[cfg(feature = "simd")] |
62 | | #[inline(always)] |
63 | | fn shl(self, rhs: Self) -> Self::Output { |
64 | | unsafe { simdint::simd_shl(self, rhs) } |
65 | | } |
66 | | |
67 | | #[cfg(not(feature = "simd"))] |
68 | | #[inline(always)] |
69 | 0 | fn shl(self, rhs: Self) -> Self::Output { |
70 | 0 | $vec::new( |
71 | 0 | self.0 << rhs.0, |
72 | 0 | self.1 << rhs.1, |
73 | 0 | self.2 << rhs.2, |
74 | 0 | self.3 << rhs.3, |
75 | | ) |
76 | 0 | } Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as core::ops::bit::Shl>::shl Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as core::ops::bit::Shl>::shl |
77 | | } |
78 | | |
79 | | impl Shr<$vec> for $vec { |
80 | | type Output = Self; |
81 | | |
82 | | #[cfg(feature = "simd")] |
83 | | #[inline(always)] |
84 | | fn shr(self, rhs: Self) -> Self::Output { |
85 | | unsafe { simdint::simd_shr(self, rhs) } |
86 | | } |
87 | | |
88 | | #[cfg(not(feature = "simd"))] |
89 | | #[inline(always)] |
90 | 0 | fn shr(self, rhs: Self) -> Self::Output { |
91 | 0 | $vec::new( |
92 | 0 | self.0 >> rhs.0, |
93 | 0 | self.1 >> rhs.1, |
94 | 0 | self.2 >> rhs.2, |
95 | 0 | self.3 >> rhs.3, |
96 | | ) |
97 | 0 | } Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as core::ops::bit::Shr>::shr Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as core::ops::bit::Shr>::shr |
98 | | } |
99 | | }; |
100 | | } |
101 | | |
102 | | impl_ops!(u32x4); |
103 | | impl_ops!(u64x4); |