/rust/registry/src/index.crates.io-1949cf8c6b5b557f/blake2-0.10.6/src/simd.rs

Source
// Copyright 2015 blake2-rfc Developers
//
// Licensed under the Apache License, Version 2.0, <LICENSE-APACHE or
// http://apache.org/licenses/LICENSE-2.0> or the MIT license <LICENSE-MIT or
// http://opensource.org/licenses/MIT>, at your option. This file may not be
// copied, modified, or distributed except according to those terms.

mod simd_opt;
mod simdint;
mod simdop;
mod simdty;

pub use self::simdty::{u32x4, u64x4};

pub trait Vector4<T>: Copy {
    fn gather(src: &[T], i0: usize, i1: usize, i2: usize, i3: usize) -> Self;

    #[allow(clippy::wrong_self_convention)]
    fn from_le(self) -> Self;
    fn to_le(self) -> Self;

    fn wrapping_add(self, rhs: Self) -> Self;

    fn rotate_right_const(self, n: u32) -> Self;

    fn shuffle_left_1(self) -> Self;
    fn shuffle_left_2(self) -> Self;
    fn shuffle_left_3(self) -> Self;

    #[inline(always)]
    fn shuffle_right_1(self) -> Self {
        self.shuffle_left_3()
    }
    #[inline(always)]
    fn shuffle_right_2(self) -> Self {
        self.shuffle_left_2()
    }
    #[inline(always)]
    fn shuffle_right_3(self) -> Self {
        self.shuffle_left_1()
    }
}

macro_rules! impl_vector4 {
    ($vec:ident, $word:ident) => {
        impl Vector4<$word> for $vec {
            #[inline(always)]
            fn gather(src: &[$word], i0: usize, i1: usize, i2: usize, i3: usize) -> Self {
                $vec::new(src[i0], src[i1], src[i2], src[i3])
            }

            #[cfg(target_endian = "little")]
            #[inline(always)]
            fn from_le(self) -> Self {
                self
            }

            #[cfg(not(target_endian = "little"))]
            #[inline(always)]
            fn from_le(self) -> Self {
                $vec::new(
                    $word::from_le(self.0),
                    $word::from_le(self.1),
                    $word::from_le(self.2),
                    $word::from_le(self.3),
                )
            }

            #[cfg(target_endian = "little")]
            #[inline(always)]
            fn to_le(self) -> Self {
                self
            }

            #[cfg(not(target_endian = "little"))]
            #[inline(always)]
            fn to_le(self) -> Self {
                $vec::new(
                    self.0.to_le(),
                    self.1.to_le(),
                    self.2.to_le(),
                    self.3.to_le(),
                )
            }

            #[inline(always)]
            fn wrapping_add(self, rhs: Self) -> Self {
                self + rhs
            }

            #[inline(always)]
            fn rotate_right_const(self, n: u32) -> Self {
                simd_opt::$vec::rotate_right_const(self, n)
            }

            #[cfg(feature = "simd")]
            #[inline(always)]
            fn shuffle_left_1(self) -> Self {
                use crate::simd::simdint::simd_shuffle4;
                const IDX: [u32; 4] = [1, 2, 3, 0];
                unsafe { simd_shuffle4(self, self, IDX) }
            }

            #[cfg(not(feature = "simd"))]
            #[inline(always)]
            fn shuffle_left_1(self) -> Self {
                $vec::new(self.1, self.2, self.3, self.0)
            }

            #[cfg(feature = "simd")]
            #[inline(always)]
            fn shuffle_left_2(self) -> Self {
                use crate::simd::simdint::simd_shuffle4;
                const IDX: [u32; 4] = [2, 3, 0, 1];
                unsafe { simd_shuffle4(self, self, IDX) }
            }

            #[cfg(not(feature = "simd"))]
            #[inline(always)]
            fn shuffle_left_2(self) -> Self {
                $vec::new(self.2, self.3, self.0, self.1)
            }

            #[cfg(feature = "simd")]
            #[inline(always)]
            fn shuffle_left_3(self) -> Self {
                use crate::simd::simdint::simd_shuffle4;
                const IDX: [u32; 4] = [3, 0, 1, 2];
                unsafe { simd_shuffle4(self, self, IDX) }
            }

            #[cfg(not(feature = "simd"))]
            #[inline(always)]
            fn shuffle_left_3(self) -> Self {
                $vec::new(self.3, self.0, self.1, self.2)
            }
        }
    };
}

impl_vector4!(u32x4, u32);
impl_vector4!(u64x4, u64);

Line	Count	Source
1		// Copyright 2015 blake2-rfc Developers
2		//
3		// Licensed under the Apache License, Version 2.0, <LICENSE-APACHE or
4		// http://apache.org/licenses/LICENSE-2.0> or the MIT license <LICENSE-MIT or
5		// http://opensource.org/licenses/MIT>, at your option. This file may not be
6		// copied, modified, or distributed except according to those terms.
7
8		mod simd_opt;
9		mod simdint;
10		mod simdop;
11		mod simdty;
12
13		pub use self::simdty::{u32x4, u64x4};
14
15		pub trait Vector4<T>: Copy {
16		fn gather(src: &[T], i0: usize, i1: usize, i2: usize, i3: usize) -> Self;
17
18		#[allow(clippy::wrong_self_convention)]
19		fn from_le(self) -> Self;
20		fn to_le(self) -> Self;
21
22		fn wrapping_add(self, rhs: Self) -> Self;
23
24		fn rotate_right_const(self, n: u32) -> Self;
25
26		fn shuffle_left_1(self) -> Self;
27		fn shuffle_left_2(self) -> Self;
28		fn shuffle_left_3(self) -> Self;
29
30		#[inline(always)]
31	0	fn shuffle_right_1(self) -> Self {
32	0	self.shuffle_left_3()
33	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::shuffle_right_1 Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::shuffle_right_1
34		#[inline(always)]
35	0	fn shuffle_right_2(self) -> Self {
36	0	self.shuffle_left_2()
37	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::shuffle_right_2 Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::shuffle_right_2
38		#[inline(always)]
39	0	fn shuffle_right_3(self) -> Self {
40	0	self.shuffle_left_1()
41	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::shuffle_right_3 Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::shuffle_right_3
42		}
43
44		macro_rules! impl_vector4 {
45		($vec:ident, $word:ident) => {
46		impl Vector4<$word> for $vec {
47		#[inline(always)]
48	0	fn gather(src: &[$word], i0: usize, i1: usize, i2: usize, i3: usize) -> Self {
49	0	$vec::new(src[i0], src[i1], src[i2], src[i3])
50	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::gather Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::gather
51
52		#[cfg(target_endian = "little")]
53		#[inline(always)]
54	0	fn from_le(self) -> Self {
55	0	self
56	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::from_le Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::from_le
57
58		#[cfg(not(target_endian = "little"))]
59		#[inline(always)]
60		fn from_le(self) -> Self {
61		$vec::new(
62		$word::from_le(self.0),
63		$word::from_le(self.1),
64		$word::from_le(self.2),
65		$word::from_le(self.3),
66		)
67		}
68
69		#[cfg(target_endian = "little")]
70		#[inline(always)]
71	0	fn to_le(self) -> Self {
72	0	self
73	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::to_le Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::to_le
74
75		#[cfg(not(target_endian = "little"))]
76		#[inline(always)]
77		fn to_le(self) -> Self {
78		$vec::new(
79		self.0.to_le(),
80		self.1.to_le(),
81		self.2.to_le(),
82		self.3.to_le(),
83		)
84		}
85
86		#[inline(always)]
87	0	fn wrapping_add(self, rhs: Self) -> Self {
88	0	self + rhs
89	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::wrapping_add Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::wrapping_add
90
91		#[inline(always)]
92	0	fn rotate_right_const(self, n: u32) -> Self {
93	0	simd_opt::$vec::rotate_right_const(self, n)
94	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::rotate_right_const Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::rotate_right_const
95
96		#[cfg(feature = "simd")]
97		#[inline(always)]
98		fn shuffle_left_1(self) -> Self {
99		use crate::simd::simdint::simd_shuffle4;
100		const IDX: [u32; 4] = [1, 2, 3, 0];
101		unsafe { simd_shuffle4(self, self, IDX) }
102		}
103
104		#[cfg(not(feature = "simd"))]
105		#[inline(always)]
106	0	fn shuffle_left_1(self) -> Self {
107	0	$vec::new(self.1, self.2, self.3, self.0)
108	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::shuffle_left_1 Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::shuffle_left_1
109
110		#[cfg(feature = "simd")]
111		#[inline(always)]
112		fn shuffle_left_2(self) -> Self {
113		use crate::simd::simdint::simd_shuffle4;
114		const IDX: [u32; 4] = [2, 3, 0, 1];
115		unsafe { simd_shuffle4(self, self, IDX) }
116		}
117
118		#[cfg(not(feature = "simd"))]
119		#[inline(always)]
120	0	fn shuffle_left_2(self) -> Self {
121	0	$vec::new(self.2, self.3, self.0, self.1)
122	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::shuffle_left_2 Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::shuffle_left_2
123
124		#[cfg(feature = "simd")]
125		#[inline(always)]
126		fn shuffle_left_3(self) -> Self {
127		use crate::simd::simdint::simd_shuffle4;
128		const IDX: [u32; 4] = [3, 0, 1, 2];
129		unsafe { simd_shuffle4(self, self, IDX) }
130		}
131
132		#[cfg(not(feature = "simd"))]
133		#[inline(always)]
134	0	fn shuffle_left_3(self) -> Self {
135	0	$vec::new(self.3, self.0, self.1, self.2)
136	0	} Unexecuted instantiation: <blake2::simd::simdty::Simd4<u32> as blake2::simd::Vector4<u32>>::shuffle_left_3 Unexecuted instantiation: <blake2::simd::simdty::Simd4<u64> as blake2::simd::Vector4<u64>>::shuffle_left_3
137		}
138		};
139		}
140
141		impl_vector4!(u32x4, u32);
142		impl_vector4!(u64x4, u64);

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Created: 2026-03-31 07:09