Coverage Report

Created: 2023-04-25 07:07

/rust/registry/src/index.crates.io-6f17d22bba15001f/capstone-0.9.0/src/arch/riscv.rs
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//! Contains riscv-specific types
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use core::convert::From;
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use core::{cmp, fmt, slice};
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// XXX todo(tmfink): create rusty versions
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pub use capstone_sys::riscv_insn_group as RiscVInsnGroup;
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pub use capstone_sys::riscv_insn as RiscVInsn;
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pub use capstone_sys::riscv_reg as RiscVReg;
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use capstone_sys::{cs_riscv, cs_riscv_op, riscv_op_mem, riscv_op_type};
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pub use crate::arch::arch_builder::riscv::*;
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use crate::arch::DetailsArchInsn;
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use crate::instruction::{RegId, RegIdInt};
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/// Contains RISCV-specific details for an instruction
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pub struct RiscVInsnDetail<'a>(pub(crate) &'a cs_riscv);
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impl_PartialEq_repr_fields!(RiscVInsnDetail<'a> [ 'a ];
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    operands
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);
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/// RISCV operand
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#[derive(Clone, Debug, Eq, PartialEq)]
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pub enum RiscVOperand {
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    /// Register
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    Reg(RegId),
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    /// Immediate
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    Imm(i64),
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    /// Memory
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    Mem(RiscVOpMem),
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    /// Invalid
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    Invalid,
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}
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impl Default for RiscVOperand {
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    fn default() -> Self {
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        RiscVOperand::Invalid
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    }
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}
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/// RISCV memory operand
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#[derive(Debug, Copy, Clone)]
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pub struct RiscVOpMem(pub(crate) riscv_op_mem);
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impl RiscVOpMem {
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    /// Base register
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    pub fn base(&self) -> RegId {
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        RegId(self.0.base as RegIdInt)
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    }
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    /// Disp value
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    pub fn disp(&self) -> i64 {
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        self.0.disp
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    }
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}
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impl_PartialEq_repr_fields!(RiscVOpMem;
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    base, disp
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);
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impl cmp::Eq for RiscVOpMem {}
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impl<'a> From<&'a cs_riscv_op> for RiscVOperand {
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    fn from(insn: &cs_riscv_op) -> RiscVOperand {
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        match insn.type_ {
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            riscv_op_type::RISCV_OP_REG => {
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                RiscVOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
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            }
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            riscv_op_type::RISCV_OP_IMM => RiscVOperand::Imm(unsafe { insn.__bindgen_anon_1.imm }),
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            riscv_op_type::RISCV_OP_MEM => {
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                RiscVOperand::Mem(RiscVOpMem(unsafe { insn.__bindgen_anon_1.mem }))
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            }
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            riscv_op_type::RISCV_OP_INVALID => RiscVOperand::Invalid,
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        }
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    }
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}
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def_arch_details_struct!(
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    InsnDetail = RiscVInsnDetail;
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    Operand = RiscVOperand;
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    OperandIterator = RiscVOperandIterator;
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    OperandIteratorLife = RiscVOperandIterator<'a>;
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    [ pub struct RiscVOperandIterator<'a>(slice::Iter<'a, cs_riscv_op>); ]
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    cs_arch_op = cs_riscv_op;
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    cs_arch = cs_riscv;
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);