/rust/registry/src/index.crates.io-6f17d22bba15001f/capstone-0.9.0/src/arch/riscv.rs
Line | Count | Source (jump to first uncovered line) |
1 | | //! Contains riscv-specific types |
2 | | |
3 | | use core::convert::From; |
4 | | use core::{cmp, fmt, slice}; |
5 | | |
6 | | // XXX todo(tmfink): create rusty versions |
7 | | pub use capstone_sys::riscv_insn_group as RiscVInsnGroup; |
8 | | pub use capstone_sys::riscv_insn as RiscVInsn; |
9 | | pub use capstone_sys::riscv_reg as RiscVReg; |
10 | | use capstone_sys::{cs_riscv, cs_riscv_op, riscv_op_mem, riscv_op_type}; |
11 | | |
12 | | pub use crate::arch::arch_builder::riscv::*; |
13 | | use crate::arch::DetailsArchInsn; |
14 | | use crate::instruction::{RegId, RegIdInt}; |
15 | | |
16 | | /// Contains RISCV-specific details for an instruction |
17 | | pub struct RiscVInsnDetail<'a>(pub(crate) &'a cs_riscv); |
18 | | |
19 | | impl_PartialEq_repr_fields!(RiscVInsnDetail<'a> [ 'a ]; |
20 | | operands |
21 | | ); |
22 | | |
23 | | /// RISCV operand |
24 | 0 | #[derive(Clone, Debug, Eq, PartialEq)] |
25 | | pub enum RiscVOperand { |
26 | | /// Register |
27 | | Reg(RegId), |
28 | | |
29 | | /// Immediate |
30 | | Imm(i64), |
31 | | |
32 | | /// Memory |
33 | | Mem(RiscVOpMem), |
34 | | |
35 | | /// Invalid |
36 | | Invalid, |
37 | | } |
38 | | |
39 | | impl Default for RiscVOperand { |
40 | 0 | fn default() -> Self { |
41 | 0 | RiscVOperand::Invalid |
42 | 0 | } |
43 | | } |
44 | | |
45 | | /// RISCV memory operand |
46 | 0 | #[derive(Debug, Copy, Clone)] |
47 | | pub struct RiscVOpMem(pub(crate) riscv_op_mem); |
48 | | |
49 | | impl RiscVOpMem { |
50 | | /// Base register |
51 | 0 | pub fn base(&self) -> RegId { |
52 | 0 | RegId(self.0.base as RegIdInt) |
53 | 0 | } |
54 | | |
55 | | /// Disp value |
56 | 0 | pub fn disp(&self) -> i64 { |
57 | 0 | self.0.disp |
58 | 0 | } |
59 | | } |
60 | | |
61 | | impl_PartialEq_repr_fields!(RiscVOpMem; |
62 | | base, disp |
63 | | ); |
64 | | |
65 | | impl cmp::Eq for RiscVOpMem {} |
66 | | |
67 | | impl<'a> From<&'a cs_riscv_op> for RiscVOperand { |
68 | 0 | fn from(insn: &cs_riscv_op) -> RiscVOperand { |
69 | 0 | match insn.type_ { |
70 | | riscv_op_type::RISCV_OP_REG => { |
71 | 0 | RiscVOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt)) |
72 | | } |
73 | 0 | riscv_op_type::RISCV_OP_IMM => RiscVOperand::Imm(unsafe { insn.__bindgen_anon_1.imm }), |
74 | | riscv_op_type::RISCV_OP_MEM => { |
75 | 0 | RiscVOperand::Mem(RiscVOpMem(unsafe { insn.__bindgen_anon_1.mem })) |
76 | | } |
77 | 0 | riscv_op_type::RISCV_OP_INVALID => RiscVOperand::Invalid, |
78 | | } |
79 | 0 | } |
80 | | } |
81 | | |
82 | 0 | def_arch_details_struct!( |
83 | 0 | InsnDetail = RiscVInsnDetail; |
84 | 0 | Operand = RiscVOperand; |
85 | 0 | OperandIterator = RiscVOperandIterator; |
86 | 0 | OperandIteratorLife = RiscVOperandIterator<'a>; |
87 | 0 | [ pub struct RiscVOperandIterator<'a>(slice::Iter<'a, cs_riscv_op>); ] |
88 | 0 | cs_arch_op = cs_riscv_op; |
89 | 0 | cs_arch = cs_riscv; |
90 | 0 | ); |