/* automatically generated by rust-bindgen */

pub type va_list = __builtin_va_list;

pub type __int8_t = libc::c_schar;

pub type __uint8_t = libc::c_uchar;

pub type __int16_t = libc::c_short;

pub type __uint16_t = libc::c_ushort;

pub type __int32_t = libc::c_int;

pub type __uint32_t = libc::c_uint;

pub type __int64_t = libc::c_long;

pub type __uint64_t = libc::c_ulong;

pub type csh = usize;

#[repr(u32)]

#[doc = " Architecture type"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub enum cs_arch {

    #[doc = "< ARM architecture (including Thumb, Thumb-2)"]

    CS_ARCH_ARM = 0,

    #[doc = "< ARM-64, also called AArch64"]

    CS_ARCH_ARM64 = 1,

    #[doc = "< Mips architecture"]

    CS_ARCH_MIPS = 2,

    #[doc = "< X86 architecture (including x86 & x86-64)"]

    CS_ARCH_X86 = 3,

    #[doc = "< PowerPC architecture"]

    CS_ARCH_PPC = 4,

    #[doc = "< Sparc architecture"]

    CS_ARCH_SPARC = 5,

    #[doc = "< SystemZ architecture"]

    CS_ARCH_SYSZ = 6,

    #[doc = "< XCore architecture"]

    CS_ARCH_XCORE = 7,

    #[doc = "< 68K architecture"]

    CS_ARCH_M68K = 8,

    #[doc = "< TMS320C64x architecture"]

    CS_ARCH_TMS320C64X = 9,

    #[doc = "< 680X architecture"]

    CS_ARCH_M680X = 10,

    #[doc = "< Ethereum architecture"]

    CS_ARCH_EVM = 11,

    #[doc = "< MOS65XX architecture (including MOS6502)"]

    CS_ARCH_MOS65XX = 12,

    #[doc = "< WebAssembly architecture"]

    CS_ARCH_WASM = 13,

    #[doc = "< Berkeley Packet Filter architecture (including eBPF)"]

    CS_ARCH_BPF = 14,

    #[doc = "< RISCV architecture"]

    CS_ARCH_RISCV = 15,

    CS_ARCH_MAX = 16,

    CS_ARCH_ALL = 65535,

}

#[doc = "< little-endian mode (default mode)"]

pub const CS_MODE_LITTLE_ENDIAN: cs_mode = cs_mode(0);

#[doc = "< 32-bit ARM"]

pub const CS_MODE_ARM: cs_mode = cs_mode(0);

#[doc = "< 16-bit mode (X86)"]

pub const CS_MODE_16: cs_mode = cs_mode(2);

#[doc = "< 32-bit mode (X86)"]

pub const CS_MODE_32: cs_mode = cs_mode(4);

#[doc = "< 64-bit mode (X86, PPC)"]

pub const CS_MODE_64: cs_mode = cs_mode(8);

#[doc = "< ARM's Thumb mode, including Thumb-2"]

pub const CS_MODE_THUMB: cs_mode = cs_mode(16);

#[doc = "< ARM's Cortex-M series"]

pub const CS_MODE_MCLASS: cs_mode = cs_mode(32);

#[doc = "< ARMv8 A32 encodings for ARM"]

pub const CS_MODE_V8: cs_mode = cs_mode(64);

#[doc = "< MicroMips mode (MIPS)"]

pub const CS_MODE_MICRO: cs_mode = cs_mode(16);

#[doc = "< Mips III ISA"]

pub const CS_MODE_MIPS3: cs_mode = cs_mode(32);

#[doc = "< Mips32r6 ISA"]

pub const CS_MODE_MIPS32R6: cs_mode = cs_mode(64);

#[doc = "< Mips II ISA"]

pub const CS_MODE_MIPS2: cs_mode = cs_mode(128);

#[doc = "< SparcV9 mode (Sparc)"]

pub const CS_MODE_V9: cs_mode = cs_mode(16);

#[doc = "< Quad Processing eXtensions mode (PPC)"]

pub const CS_MODE_QPX: cs_mode = cs_mode(16);

#[doc = "< Signal Processing Engine mode (PPC)"]

pub const CS_MODE_SPE: cs_mode = cs_mode(32);

#[doc = "< Book-E mode (PPC)"]

pub const CS_MODE_BOOKE: cs_mode = cs_mode(64);

#[doc = "< M68K 68000 mode"]

pub const CS_MODE_M68K_000: cs_mode = cs_mode(2);

#[doc = "< M68K 68010 mode"]

pub const CS_MODE_M68K_010: cs_mode = cs_mode(4);

#[doc = "< M68K 68020 mode"]

pub const CS_MODE_M68K_020: cs_mode = cs_mode(8);

#[doc = "< M68K 68030 mode"]

pub const CS_MODE_M68K_030: cs_mode = cs_mode(16);

#[doc = "< M68K 68040 mode"]

pub const CS_MODE_M68K_040: cs_mode = cs_mode(32);

#[doc = "< M68K 68060 mode"]

pub const CS_MODE_M68K_060: cs_mode = cs_mode(64);

#[doc = "< big-endian mode"]

pub const CS_MODE_BIG_ENDIAN: cs_mode = cs_mode(-2147483648);

#[doc = "< Mips32 ISA (Mips)"]

pub const CS_MODE_MIPS32: cs_mode = cs_mode(4);

#[doc = "< Mips64 ISA (Mips)"]

pub const CS_MODE_MIPS64: cs_mode = cs_mode(8);

#[doc = "< M680X Hitachi 6301,6303 mode"]

pub const CS_MODE_M680X_6301: cs_mode = cs_mode(2);

#[doc = "< M680X Hitachi 6309 mode"]

pub const CS_MODE_M680X_6309: cs_mode = cs_mode(4);

#[doc = "< M680X Motorola 6800,6802 mode"]

pub const CS_MODE_M680X_6800: cs_mode = cs_mode(8);

#[doc = "< M680X Motorola 6801,6803 mode"]

pub const CS_MODE_M680X_6801: cs_mode = cs_mode(16);

#[doc = "< M680X Motorola/Freescale 6805 mode"]

pub const CS_MODE_M680X_6805: cs_mode = cs_mode(32);

#[doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"]

pub const CS_MODE_M680X_6808: cs_mode = cs_mode(64);

#[doc = "< M680X Motorola 6809 mode"]

pub const CS_MODE_M680X_6809: cs_mode = cs_mode(128);

#[doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"]

pub const CS_MODE_M680X_6811: cs_mode = cs_mode(256);

#[doc = "< M680X Motorola/Freescale/NXP CPU12"]

#[doc = "< used on M68HC12/HCS12"]

pub const CS_MODE_M680X_CPU12: cs_mode = cs_mode(512);

#[doc = "< M680X Freescale/NXP HCS08 mode"]

pub const CS_MODE_M680X_HCS08: cs_mode = cs_mode(1024);

#[doc = "< Classic BPF mode (default)"]

pub const CS_MODE_BPF_CLASSIC: cs_mode = cs_mode(0);

#[doc = "< Extended BPF mode"]

pub const CS_MODE_BPF_EXTENDED: cs_mode = cs_mode(1);

#[doc = "< RISCV RV32G"]

pub const CS_MODE_RISCV32: cs_mode = cs_mode(1);

#[doc = "< RISCV RV64G"]

pub const CS_MODE_RISCV64: cs_mode = cs_mode(2);

#[doc = "< RISCV compressed instructure mode"]

pub const CS_MODE_RISCVC: cs_mode = cs_mode(4);

#[doc = "< MOS65XXX MOS 6502"]

pub const CS_MODE_MOS65XX_6502: cs_mode = cs_mode(2);

#[doc = "< MOS65XXX WDC 65c02"]

pub const CS_MODE_MOS65XX_65C02: cs_mode = cs_mode(4);

#[doc = "< MOS65XXX WDC W65c02"]

pub const CS_MODE_MOS65XX_W65C02: cs_mode = cs_mode(8);

#[doc = "< MOS65XXX WDC 65816, 8-bit m/x"]

pub const CS_MODE_MOS65XX_65816: cs_mode = cs_mode(16);

#[doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"]

pub const CS_MODE_MOS65XX_65816_LONG_M: cs_mode = cs_mode(32);

#[doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"]

pub const CS_MODE_MOS65XX_65816_LONG_X: cs_mode = cs_mode(64);

pub const CS_MODE_MOS65XX_65816_LONG_MX: cs_mode = cs_mode(96);

impl ::core::ops::BitOr<cs_mode> for cs_mode {

    type Output = Self;

    #[inline]

    fn bitor(self, other: Self) -> Self {

        cs_mode(self.0 | other.0)

    }

Unexecuted instantiation: <capstone_sys::cs_mode as core::ops::bit::BitOr>::bitor

Unexecuted instantiation: <capstone_sys::cs_mode as core::ops::bit::BitOr>::bitor

}

impl ::core::ops::BitOrAssign for cs_mode {

    #[inline]

    fn bitor_assign(&mut self, rhs: cs_mode) {

        self.0 |= rhs.0;

    }

}

impl ::core::ops::BitAnd<cs_mode> for cs_mode {

    type Output = Self;

    #[inline]

    fn bitand(self, other: Self) -> Self {

        cs_mode(self.0 & other.0)

    }

}

impl ::core::ops::BitAndAssign for cs_mode {

    #[inline]

    fn bitand_assign(&mut self, rhs: cs_mode) {

        self.0 &= rhs.0;

    }

}

#[repr(C)]

#[doc = " Mode type"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub struct cs_mode(pub i32);

pub type cs_malloc_t =

    ::core::option::Option<unsafe extern "C" fn(size: usize) -> *mut libc::c_void>;

pub type cs_calloc_t =

    ::core::option::Option<unsafe extern "C" fn(nmemb: usize, size: usize) -> *mut libc::c_void>;

pub type cs_realloc_t = ::core::option::Option<

    unsafe extern "C" fn(ptr: *mut libc::c_void, size: usize) -> *mut libc::c_void,

>;

pub type cs_free_t = ::core::option::Option<unsafe extern "C" fn(ptr: *mut libc::c_void)>;

pub type cs_vsnprintf_t = ::core::option::Option<

    unsafe extern "C" fn(

        str: *mut libc::c_char,

        size: usize,

        format: *const libc::c_char,

        ap: *mut __va_list_tag,

    ) -> libc::c_int,

>;

#[doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()"]

#[doc = " By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."]

#[repr(C)]

#[derive(Debug, Copy)]

pub struct cs_opt_mem {

    pub malloc: cs_malloc_t,

    pub calloc: cs_calloc_t,

    pub realloc: cs_realloc_t,

    pub free: cs_free_t,

    pub vsnprintf: cs_vsnprintf_t,

}

impl Clone for cs_opt_mem {

    fn clone(&self) -> Self {

        *self

    }

}

#[doc = " Customize mnemonic for instructions with alternative name."]

#[doc = " To reset existing customized instruction to its default mnemonic,"]

#[doc = " call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value"]

#[doc = " for @mnemonic."]

#[repr(C)]

#[derive(Debug, Copy)]

pub struct cs_opt_mnem {

    #[doc = " ID of instruction to be customized."]

    pub id: libc::c_uint,

    #[doc = " Customized instruction mnemonic."]

    pub mnemonic: *const libc::c_char,

}

impl Clone for cs_opt_mnem {

    fn clone(&self) -> Self {

        *self

    }

}

#[repr(u32)]

#[doc = " Runtime option for the disassembled engine"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub enum cs_opt_type {

    #[doc = "< No option specified"]

    CS_OPT_INVALID = 0,

    #[doc = "< Assembly output syntax"]

    CS_OPT_SYNTAX = 1,

    #[doc = "< Break down instruction structure into details"]

    CS_OPT_DETAIL = 2,

    #[doc = "< Change engine's mode at run-time"]

    CS_OPT_MODE = 3,

    #[doc = "< User-defined dynamic memory related functions"]

    CS_OPT_MEM = 4,

    #[doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."]

    CS_OPT_SKIPDATA = 5,

    #[doc = "< Setup user-defined function for SKIPDATA option"]

    CS_OPT_SKIPDATA_SETUP = 6,

    #[doc = "< Customize instruction mnemonic"]

    CS_OPT_MNEMONIC = 7,

    #[doc = "< print immediate operands in unsigned form"]

    CS_OPT_UNSIGNED = 8,

}

pub mod cs_opt_value {

    #[doc = " Runtime option value (associated with option type above)"]

    pub type Type = u32;

    #[doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."]

    pub const CS_OPT_OFF: Type = 0;

    #[doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."]

    pub const CS_OPT_ON: Type = 3;

    #[doc = "< Default asm syntax (CS_OPT_SYNTAX)."]

    pub const CS_OPT_SYNTAX_DEFAULT: Type = 0;

    #[doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."]

    pub const CS_OPT_SYNTAX_INTEL: Type = 1;

    #[doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."]

    pub const CS_OPT_SYNTAX_ATT: Type = 2;

    #[doc = "< Prints register name with only number (CS_OPT_SYNTAX)"]

    pub const CS_OPT_SYNTAX_NOREGNAME: Type = 3;

    #[doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."]

    pub const CS_OPT_SYNTAX_MASM: Type = 4;

    #[doc = "< MOS65XX use $ as hex prefix"]

    pub const CS_OPT_SYNTAX_MOTOROLA: Type = 5;

}

#[repr(u32)]

#[doc = " Common instruction operand types - to be consistent across all architectures."]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub enum cs_op_type {

    #[doc = "< uninitialized/invalid operand."]

    CS_OP_INVALID = 0,

    #[doc = "< Register operand."]

    CS_OP_REG = 1,

    #[doc = "< Immediate operand."]

    CS_OP_IMM = 2,

    #[doc = "< Memory operand."]

    CS_OP_MEM = 3,

    #[doc = "< Floating-Point operand."]

    CS_OP_FP = 4,

}

#[doc = "< Uninitialized/invalid access type."]

pub const CS_AC_INVALID: cs_ac_type = cs_ac_type(0);

#[doc = "< Operand read from memory or register."]

pub const CS_AC_READ: cs_ac_type = cs_ac_type(1);

#[doc = "< Operand write to memory or register."]

pub const CS_AC_WRITE: cs_ac_type = cs_ac_type(2);

impl ::core::ops::BitOr<cs_ac_type> for cs_ac_type {

    type Output = Self;

    #[inline]

    fn bitor(self, other: Self) -> Self {

        cs_ac_type(self.0 | other.0)

    }

Unexecuted instantiation: <capstone_sys::cs_ac_type as core::ops::bit::BitOr>::bitor

Unexecuted instantiation: <capstone_sys::cs_ac_type as core::ops::bit::BitOr>::bitor

}

impl ::core::ops::BitOrAssign for cs_ac_type {

    #[inline]

    fn bitor_assign(&mut self, rhs: cs_ac_type) {

        self.0 |= rhs.0;

    }

}

impl ::core::ops::BitAnd<cs_ac_type> for cs_ac_type {

    type Output = Self;

    #[inline]

    fn bitand(self, other: Self) -> Self {

        cs_ac_type(self.0 & other.0)

    }

Unexecuted instantiation: <capstone_sys::cs_ac_type as core::ops::bit::BitAnd>::bitand

Unexecuted instantiation: <capstone_sys::cs_ac_type as core::ops::bit::BitAnd>::bitand

}

impl ::core::ops::BitAndAssign for cs_ac_type {

    #[inline]

    fn bitand_assign(&mut self, rhs: cs_ac_type) {

        self.0 &= rhs.0;

    }

}

#[repr(C)]

#[doc = " Common instruction operand access types - to be consistent across all architectures."]

#[doc = " It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub struct cs_ac_type(pub u32);

pub mod cs_group_type {

    #[doc = " Common instruction groups - to be consistent across all architectures."]

    pub type Type = u32;

    #[doc = "< uninitialized/invalid group."]

    pub const CS_GRP_INVALID: Type = 0;

    #[doc = "< all jump instructions (conditional+direct+indirect jumps)"]

    pub const CS_GRP_JUMP: Type = 1;

    #[doc = "< all call instructions"]

    pub const CS_GRP_CALL: Type = 2;

    #[doc = "< all return instructions"]

    pub const CS_GRP_RET: Type = 3;

    #[doc = "< all interrupt instructions (int+syscall)"]

    pub const CS_GRP_INT: Type = 4;

    #[doc = "< all interrupt return instructions"]

    pub const CS_GRP_IRET: Type = 5;

    #[doc = "< all privileged instructions"]

    pub const CS_GRP_PRIVILEGE: Type = 6;

    #[doc = "< all relative branching instructions"]

    pub const CS_GRP_BRANCH_RELATIVE: Type = 7;

}

#[doc = "User-defined callback function for SKIPDATA option."]

#[doc = "See tests/test_skipdata.c for sample code demonstrating this API."]

#[doc = ""]

#[doc = "@code: the input buffer containing code to be disassembled."]

#[doc = "This is the same buffer passed to cs_disasm()."]

#[doc = "@code_size: size (in bytes) of the above @code buffer."]

#[doc = "@offset: the position of the currently-examining byte in the input"]

#[doc = "buffer @code mentioned above."]

#[doc = "@user_data: user-data passed to cs_option() via @user_data field in"]

#[doc = "cs_opt_skipdata struct below."]

#[doc = ""]

#[doc = "@return: return number of bytes to skip, or 0 to immediately stop disassembling."]

pub type cs_skipdata_cb_t = ::core::option::Option<

    unsafe extern "C" fn(

        code: *const u8,

        code_size: usize,

        offset: usize,

        user_data: *mut libc::c_void,

    ) -> usize,

>;

#[doc = " User-customized setup for SKIPDATA option"]

#[repr(C)]

#[derive(Debug, Copy)]

pub struct cs_opt_skipdata {

    #[doc = " Capstone considers data to skip as special \"instructions\"."]

    #[doc = " User can specify the string for this instruction's \"mnemonic\" here."]

    #[doc = " By default (if @mnemonic is NULL), Capstone use \".byte\"."]

    pub mnemonic: *const libc::c_char,

    #[doc = " User-defined callback function to be called when Capstone hits data."]

    #[doc = " If the returned value from this callback is positive (>0), Capstone"]

    #[doc = " will skip exactly that number of bytes & continue. Otherwise, if"]

    #[doc = " the callback returns 0, Capstone stops disassembling and returns"]

    #[doc = " immediately from cs_disasm()"]

    #[doc = " NOTE: if this callback pointer is NULL, Capstone would skip a number"]

    #[doc = " of bytes depending on architectures, as following:"]

    #[doc = " Arm:     2 bytes (Thumb mode) or 4 bytes."]

    #[doc = " Arm64:   4 bytes."]

    #[doc = " Mips:    4 bytes."]

    #[doc = " M680x:   1 byte."]

    #[doc = " PowerPC: 4 bytes."]

    #[doc = " Sparc:   4 bytes."]

    #[doc = " SystemZ: 2 bytes."]

    #[doc = " X86:     1 bytes."]

    #[doc = " XCore:   2 bytes."]

    #[doc = " EVM:     1 bytes."]

    #[doc = " RISCV:   4 bytes."]

    #[doc = " WASM:    1 bytes."]

    #[doc = " MOS65XX: 1 bytes."]

    #[doc = " BPF:     8 bytes."]

    pub callback: cs_skipdata_cb_t,

    #[doc = " User-defined data to be passed to @callback function pointer."]

    pub user_data: *mut libc::c_void,

}

impl Clone for cs_opt_skipdata {

    fn clone(&self) -> Self {

        *self

    }

}

#[repr(u32)]

#[doc = " ARM shift type"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub enum arm_shifter {

    ARM_SFT_INVALID = 0,

    #[doc = "< shift with immediate const"]

    ARM_SFT_ASR = 1,

    #[doc = "< shift with immediate const"]

    ARM_SFT_LSL = 2,

    #[doc = "< shift with immediate const"]

    ARM_SFT_LSR = 3,

    #[doc = "< shift with immediate const"]

    ARM_SFT_ROR = 4,

    #[doc = "< shift with immediate const"]

    ARM_SFT_RRX = 5,

    #[doc = "< shift with register"]

    ARM_SFT_ASR_REG = 6,

    #[doc = "< shift with register"]

    ARM_SFT_LSL_REG = 7,

    #[doc = "< shift with register"]

    ARM_SFT_LSR_REG = 8,

    #[doc = "< shift with register"]

    ARM_SFT_ROR_REG = 9,

    #[doc = "< shift with register"]

    ARM_SFT_RRX_REG = 10,

}

#[repr(u32)]

#[doc = " ARM condition code"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

Unexecuted instantiation: <capstone_sys::arm_cc as core::cmp::PartialEq>::eq

Unexecuted instantiation: <capstone_sys::arm_cc as core::cmp::PartialEq>::eq

pub enum arm_cc {

    ARM_CC_INVALID = 0,

    #[doc = "< Equal                      Equal"]

    ARM_CC_EQ = 1,

    #[doc = "< Not equal                  Not equal, or unordered"]

    ARM_CC_NE = 2,

    #[doc = "< Carry set                  >, ==, or unordered"]

    ARM_CC_HS = 3,

    #[doc = "< Carry clear                Less than"]

    ARM_CC_LO = 4,

    #[doc = "< Minus, negative            Less than"]

    ARM_CC_MI = 5,

    #[doc = "< Plus, positive or zero     >, ==, or unordered"]

    ARM_CC_PL = 6,

    #[doc = "< Overflow                   Unordered"]

    ARM_CC_VS = 7,

    #[doc = "< No overflow                Not unordered"]

    ARM_CC_VC = 8,

    #[doc = "< Unsigned higher            Greater than, or unordered"]

    ARM_CC_HI = 9,

    #[doc = "< Unsigned lower or same     Less than or equal"]

    ARM_CC_LS = 10,

    #[doc = "< Greater than or equal      Greater than or equal"]

    ARM_CC_GE = 11,

    #[doc = "< Less than                  Less than, or unordered"]

    ARM_CC_LT = 12,

    #[doc = "< Greater than               Greater than"]

    ARM_CC_GT = 13,

    #[doc = "< Less than or equal         <, ==, or unordered"]

    ARM_CC_LE = 14,

    #[doc = "< Always (unconditional)     Always (unconditional)"]

    ARM_CC_AL = 15,

}

#[repr(u32)]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub enum arm_sysreg {

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_INVALID = 0,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_C = 1,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_X = 2,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_S = 4,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_F = 8,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_CPSR_C = 16,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_CPSR_X = 32,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_CPSR_S = 64,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_CPSR_F = 128,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_APSR = 256,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_APSR_G = 257,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_APSR_NZCVQ = 258,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_APSR_NZCVQG = 259,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_IAPSR = 260,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_IAPSR_G = 261,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_IAPSR_NZCVQG = 262,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_IAPSR_NZCVQ = 263,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_EAPSR = 264,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_EAPSR_G = 265,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_EAPSR_NZCVQG = 266,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_EAPSR_NZCVQ = 267,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_XPSR = 268,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_XPSR_G = 269,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_XPSR_NZCVQG = 270,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_XPSR_NZCVQ = 271,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_IPSR = 272,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_EPSR = 273,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_IEPSR = 274,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_MSP = 275,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_PSP = 276,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_PRIMASK = 277,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_BASEPRI = 278,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_BASEPRI_MAX = 279,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_FAULTMASK = 280,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_CONTROL = 281,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_MSPLIM = 282,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_PSPLIM = 283,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_MSP_NS = 284,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_PSP_NS = 285,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_MSPLIM_NS = 286,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_PSPLIM_NS = 287,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_PRIMASK_NS = 288,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_BASEPRI_NS = 289,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_FAULTMASK_NS = 290,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_CONTROL_NS = 291,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_NS = 292,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R8_USR = 293,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R9_USR = 294,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R10_USR = 295,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R11_USR = 296,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R12_USR = 297,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_USR = 298,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_LR_USR = 299,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R8_FIQ = 300,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R9_FIQ = 301,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R10_FIQ = 302,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R11_FIQ = 303,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_R12_FIQ = 304,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_FIQ = 305,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_LR_FIQ = 306,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_LR_IRQ = 307,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_IRQ = 308,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_LR_SVC = 309,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_SVC = 310,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_LR_ABT = 311,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_ABT = 312,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_LR_UND = 313,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_UND = 314,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_LR_MON = 315,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_MON = 316,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_ELR_HYP = 317,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SP_HYP = 318,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_FIQ = 319,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_IRQ = 320,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_SVC = 321,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_ABT = 322,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_UND = 323,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_MON = 324,

    #[doc = " Special registers for MSR"]

    ARM_SYSREG_SPSR_HYP = 325,

}

#[repr(u32)]

#[doc = " The memory barrier constants map directly to the 4-bit encoding of"]

#[doc = " the option field for Memory Barrier operations."]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

Unexecuted instantiation: <capstone_sys::arm_mem_barrier as core::cmp::PartialEq>::eq

Unexecuted instantiation: <capstone_sys::arm_mem_barrier as core::cmp::PartialEq>::eq

pub enum arm_mem_barrier {

    ARM_MB_INVALID = 0,

    ARM_MB_RESERVED_0 = 1,

    ARM_MB_OSHLD = 2,

    ARM_MB_OSHST = 3,

    ARM_MB_OSH = 4,

    ARM_MB_RESERVED_4 = 5,

    ARM_MB_NSHLD = 6,

    ARM_MB_NSHST = 7,

    ARM_MB_NSH = 8,

    ARM_MB_RESERVED_8 = 9,

    ARM_MB_ISHLD = 10,

    ARM_MB_ISHST = 11,

    ARM_MB_ISH = 12,

    ARM_MB_RESERVED_12 = 13,

    ARM_MB_LD = 14,

    ARM_MB_ST = 15,

    ARM_MB_SY = 16,

}

#[repr(u32)]

#[doc = " Operand type for instruction's operands"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub enum arm_op_type {

    #[doc = "< = CS_OP_INVALID (Uninitialized)."]

    ARM_OP_INVALID = 0,

    #[doc = "< = CS_OP_REG (Register operand)."]

    ARM_OP_REG = 1,

    #[doc = "< = CS_OP_IMM (Immediate operand)."]

    ARM_OP_IMM = 2,

    #[doc = "< = CS_OP_MEM (Memory operand)."]

    ARM_OP_MEM = 3,

    #[doc = "< = CS_OP_FP (Floating-Point operand)."]

    ARM_OP_FP = 4,

    #[doc = "< C-Immediate (coprocessor registers)"]

    ARM_OP_CIMM = 64,

    #[doc = "< P-Immediate (coprocessor registers)"]

    ARM_OP_PIMM = 65,

    #[doc = "< operand for SETEND instruction"]

    ARM_OP_SETEND = 66,

    #[doc = "< MSR/MRS special register operand"]

    ARM_OP_SYSREG = 67,

}

#[repr(u32)]

#[doc = " Operand type for SETEND instruction"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

Unexecuted instantiation: <capstone_sys::arm_setend_type as core::cmp::PartialEq>::eq

Unexecuted instantiation: <capstone_sys::arm_setend_type as core::cmp::PartialEq>::eq

pub enum arm_setend_type {

    #[doc = "< Uninitialized."]

    ARM_SETEND_INVALID = 0,

    #[doc = "< BE operand."]

    ARM_SETEND_BE = 1,

    #[doc = "< LE operand"]

    ARM_SETEND_LE = 2,

}

#[repr(u32)]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

Unexecuted instantiation: <capstone_sys::arm_cpsmode_type as core::cmp::PartialEq>::eq

Unexecuted instantiation: <capstone_sys::arm_cpsmode_type as core::cmp::PartialEq>::eq

pub enum arm_cpsmode_type {

    ARM_CPSMODE_INVALID = 0,

    ARM_CPSMODE_IE = 2,

    ARM_CPSMODE_ID = 3,

}

#[repr(u32)]

#[doc = " Operand type for SETEND instruction"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

Unexecuted instantiation: <capstone_sys::arm_cpsflag_type as core::cmp::PartialEq>::eq

Unexecuted instantiation: <capstone_sys::arm_cpsflag_type as core::cmp::PartialEq>::eq

pub enum arm_cpsflag_type {

    ARM_CPSFLAG_INVALID = 0,

    ARM_CPSFLAG_F = 1,

    ARM_CPSFLAG_I = 2,

    ARM_CPSFLAG_A = 4,

    #[doc = "< no flag"]

    ARM_CPSFLAG_NONE = 16,

}

#[repr(u32)]

#[doc = " Data type for elements of vector instructions."]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

Unexecuted instantiation: <capstone_sys::arm_vectordata_type as core::cmp::PartialEq>::eq

Unexecuted instantiation: <capstone_sys::arm_vectordata_type as core::cmp::PartialEq>::eq

pub enum arm_vectordata_type {

    ARM_VECTORDATA_INVALID = 0,

    ARM_VECTORDATA_I8 = 1,

    ARM_VECTORDATA_I16 = 2,

    ARM_VECTORDATA_I32 = 3,

    ARM_VECTORDATA_I64 = 4,

    ARM_VECTORDATA_S8 = 5,

    ARM_VECTORDATA_S16 = 6,

    ARM_VECTORDATA_S32 = 7,

    ARM_VECTORDATA_S64 = 8,

    ARM_VECTORDATA_U8 = 9,

    ARM_VECTORDATA_U16 = 10,

    ARM_VECTORDATA_U32 = 11,

    ARM_VECTORDATA_U64 = 12,

    ARM_VECTORDATA_P8 = 13,

    ARM_VECTORDATA_F16 = 14,

    ARM_VECTORDATA_F32 = 15,

    ARM_VECTORDATA_F64 = 16,

    ARM_VECTORDATA_F16F64 = 17,

    ARM_VECTORDATA_F64F16 = 18,

    ARM_VECTORDATA_F32F16 = 19,

    ARM_VECTORDATA_F16F32 = 20,

    ARM_VECTORDATA_F64F32 = 21,

    ARM_VECTORDATA_F32F64 = 22,

    ARM_VECTORDATA_S32F32 = 23,

    ARM_VECTORDATA_U32F32 = 24,

    ARM_VECTORDATA_F32S32 = 25,

    ARM_VECTORDATA_F32U32 = 26,

    ARM_VECTORDATA_F64S16 = 27,

    ARM_VECTORDATA_F32S16 = 28,

    ARM_VECTORDATA_F64S32 = 29,

    ARM_VECTORDATA_S16F64 = 30,

    ARM_VECTORDATA_S16F32 = 31,

    ARM_VECTORDATA_S32F64 = 32,

    ARM_VECTORDATA_U16F64 = 33,

    ARM_VECTORDATA_U16F32 = 34,

    ARM_VECTORDATA_U32F64 = 35,

    ARM_VECTORDATA_F64U16 = 36,

    ARM_VECTORDATA_F32U16 = 37,

    ARM_VECTORDATA_F64U32 = 38,

    ARM_VECTORDATA_F16U16 = 39,

    ARM_VECTORDATA_U16F16 = 40,

    ARM_VECTORDATA_F16U32 = 41,

    ARM_VECTORDATA_U32F16 = 42,

}

pub mod arm_reg {

    #[doc = " ARM registers"]

    pub type Type = u32;

    pub const ARM_REG_INVALID: Type = 0;

    pub const ARM_REG_APSR: Type = 1;

    pub const ARM_REG_APSR_NZCV: Type = 2;

    pub const ARM_REG_CPSR: Type = 3;

    pub const ARM_REG_FPEXC: Type = 4;

    pub const ARM_REG_FPINST: Type = 5;

    pub const ARM_REG_FPSCR: Type = 6;

    pub const ARM_REG_FPSCR_NZCV: Type = 7;

    pub const ARM_REG_FPSID: Type = 8;

    pub const ARM_REG_ITSTATE: Type = 9;

    pub const ARM_REG_LR: Type = 10;

    pub const ARM_REG_PC: Type = 11;

    pub const ARM_REG_SP: Type = 12;

    pub const ARM_REG_SPSR: Type = 13;

    pub const ARM_REG_D0: Type = 14;

    pub const ARM_REG_D1: Type = 15;

    pub const ARM_REG_D2: Type = 16;

    pub const ARM_REG_D3: Type = 17;

    pub const ARM_REG_D4: Type = 18;

    pub const ARM_REG_D5: Type = 19;

    pub const ARM_REG_D6: Type = 20;

    pub const ARM_REG_D7: Type = 21;

    pub const ARM_REG_D8: Type = 22;

    pub const ARM_REG_D9: Type = 23;

    pub const ARM_REG_D10: Type = 24;

    pub const ARM_REG_D11: Type = 25;

    pub const ARM_REG_D12: Type = 26;

    pub const ARM_REG_D13: Type = 27;

    pub const ARM_REG_D14: Type = 28;

    pub const ARM_REG_D15: Type = 29;

    pub const ARM_REG_D16: Type = 30;

    pub const ARM_REG_D17: Type = 31;

    pub const ARM_REG_D18: Type = 32;

    pub const ARM_REG_D19: Type = 33;

    pub const ARM_REG_D20: Type = 34;

    pub const ARM_REG_D21: Type = 35;

    pub const ARM_REG_D22: Type = 36;

    pub const ARM_REG_D23: Type = 37;

    pub const ARM_REG_D24: Type = 38;

    pub const ARM_REG_D25: Type = 39;

    pub const ARM_REG_D26: Type = 40;

    pub const ARM_REG_D27: Type = 41;

    pub const ARM_REG_D28: Type = 42;

    pub const ARM_REG_D29: Type = 43;

    pub const ARM_REG_D30: Type = 44;

    pub const ARM_REG_D31: Type = 45;

    pub const ARM_REG_FPINST2: Type = 46;

    pub const ARM_REG_MVFR0: Type = 47;

    pub const ARM_REG_MVFR1: Type = 48;

    pub const ARM_REG_MVFR2: Type = 49;

    pub const ARM_REG_Q0: Type = 50;

    pub const ARM_REG_Q1: Type = 51;

    pub const ARM_REG_Q2: Type = 52;

    pub const ARM_REG_Q3: Type = 53;

    pub const ARM_REG_Q4: Type = 54;

    pub const ARM_REG_Q5: Type = 55;

    pub const ARM_REG_Q6: Type = 56;

    pub const ARM_REG_Q7: Type = 57;

    pub const ARM_REG_Q8: Type = 58;

    pub const ARM_REG_Q9: Type = 59;

    pub const ARM_REG_Q10: Type = 60;

    pub const ARM_REG_Q11: Type = 61;

    pub const ARM_REG_Q12: Type = 62;

    pub const ARM_REG_Q13: Type = 63;

    pub const ARM_REG_Q14: Type = 64;

    pub const ARM_REG_Q15: Type = 65;

    pub const ARM_REG_R0: Type = 66;

    pub const ARM_REG_R1: Type = 67;

    pub const ARM_REG_R2: Type = 68;

    pub const ARM_REG_R3: Type = 69;

    pub const ARM_REG_R4: Type = 70;

    pub const ARM_REG_R5: Type = 71;

    pub const ARM_REG_R6: Type = 72;

    pub const ARM_REG_R7: Type = 73;

    pub const ARM_REG_R8: Type = 74;

    pub const ARM_REG_R9: Type = 75;

    pub const ARM_REG_R10: Type = 76;

    pub const ARM_REG_R11: Type = 77;

    pub const ARM_REG_R12: Type = 78;

    pub const ARM_REG_S0: Type = 79;

    pub const ARM_REG_S1: Type = 80;

    pub const ARM_REG_S2: Type = 81;

    pub const ARM_REG_S3: Type = 82;

    pub const ARM_REG_S4: Type = 83;

    pub const ARM_REG_S5: Type = 84;

    pub const ARM_REG_S6: Type = 85;

    pub const ARM_REG_S7: Type = 86;

    pub const ARM_REG_S8: Type = 87;

    pub const ARM_REG_S9: Type = 88;

    pub const ARM_REG_S10: Type = 89;

    pub const ARM_REG_S11: Type = 90;

    pub const ARM_REG_S12: Type = 91;

    pub const ARM_REG_S13: Type = 92;

    pub const ARM_REG_S14: Type = 93;

    pub const ARM_REG_S15: Type = 94;

    pub const ARM_REG_S16: Type = 95;

    pub const ARM_REG_S17: Type = 96;

    pub const ARM_REG_S18: Type = 97;

    pub const ARM_REG_S19: Type = 98;

    pub const ARM_REG_S20: Type = 99;

    pub const ARM_REG_S21: Type = 100;

    pub const ARM_REG_S22: Type = 101;

    pub const ARM_REG_S23: Type = 102;

    pub const ARM_REG_S24: Type = 103;

    pub const ARM_REG_S25: Type = 104;

    pub const ARM_REG_S26: Type = 105;

    pub const ARM_REG_S27: Type = 106;

    pub const ARM_REG_S28: Type = 107;

    pub const ARM_REG_S29: Type = 108;

    pub const ARM_REG_S30: Type = 109;

    pub const ARM_REG_S31: Type = 110;

    pub const ARM_REG_ENDING: Type = 111;

    pub const ARM_REG_R13: Type = 12;

    pub const ARM_REG_R14: Type = 10;

    pub const ARM_REG_R15: Type = 11;

    pub const ARM_REG_SB: Type = 75;

    pub const ARM_REG_SL: Type = 76;

    pub const ARM_REG_FP: Type = 77;

    pub const ARM_REG_IP: Type = 78;

}

#[doc = " Instruction's operand referring to memory"]

#[doc = " This is associated with ARM_OP_MEM operand type above"]

#[repr(C)]

#[derive(Debug, Copy)]

pub struct arm_op_mem {

    #[doc = "< base register"]

    pub base: arm_reg::Type,

    #[doc = "< index register"]

    pub index: arm_reg::Type,

    #[doc = "< scale for index register (can be 1, or -1)"]

    pub scale: libc::c_int,

    #[doc = "< displacement/offset value"]

    pub disp: libc::c_int,

    #[doc = " left-shift on index register, or 0 if irrelevant"]

    #[doc = " NOTE: this value can also be fetched via operand.shift.value"]

    pub lshift: libc::c_int,

}

impl Clone for arm_op_mem {

    fn clone(&self) -> Self {

        *self

    }

}

#[doc = " Instruction operand"]

#[repr(C)]

#[derive(Copy)]

pub struct cs_arm_op {

    #[doc = "< Vector Index for some vector operands (or -1 if irrelevant)"]

    pub vector_index: libc::c_int,

    pub shift: cs_arm_op__bindgen_ty_1,

    #[doc = "< operand type"]

    pub type_: arm_op_type,

    pub __bindgen_anon_1: cs_arm_op__bindgen_ty_2,

    #[doc = " in some instructions, an operand can be subtracted or added to"]

    #[doc = " the base register,"]

    #[doc = " if TRUE, this operand is subtracted. otherwise, it is added."]

    pub subtracted: bool,

    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)"]

    #[doc = " This field is combined of cs_ac_type."]

    #[doc = " NOTE: this field is irrelevant if engine is compiled in DIET mode."]

    pub access: u8,

    #[doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"]

    pub neon_lane: i8,

}

#[repr(C)]

#[derive(Debug, Copy)]

pub struct cs_arm_op__bindgen_ty_1 {

    pub type_: arm_shifter,

    pub value: libc::c_uint,

}

impl Clone for cs_arm_op__bindgen_ty_1 {

    fn clone(&self) -> Self {

        *self

    }

}

#[repr(C)]

#[derive(Copy)]

pub union cs_arm_op__bindgen_ty_2 {

    #[doc = "< register value for REG/SYSREG operand"]

    pub reg: libc::c_int,

    #[doc = "< immediate value for C-IMM, P-IMM or IMM operand"]

    pub imm: i32,

    #[doc = "< floating point value for FP operand"]

    pub fp: f64,

    #[doc = "< base/index/scale/disp value for MEM operand"]

    pub mem: arm_op_mem,

    #[doc = "< SETEND instruction's operand type"]

    pub setend: arm_setend_type,

    _bindgen_union_align: [u64; 3usize],

}

impl Clone for cs_arm_op__bindgen_ty_2 {

    fn clone(&self) -> Self {

        *self

    }

}

impl ::core::fmt::Debug for cs_arm_op__bindgen_ty_2 {

    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {

        write!(f, "cs_arm_op__bindgen_ty_2 {{ union }}")

    }

}

impl Clone for cs_arm_op {

    fn clone(&self) -> Self {

        *self

    }

}

impl ::core::fmt::Debug for cs_arm_op {

    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {

        write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane)

    }

}

#[doc = " Instruction structure"]

#[repr(C)]

#[derive(Copy)]

pub struct cs_arm {

    #[doc = "< User-mode registers to be loaded (for LDM/STM instructions)"]

    pub usermode: bool,

    #[doc = "< Scalar size for vector instructions"]

    pub vector_size: libc::c_int,

    #[doc = "< Data type for elements of vector instructions"]

    pub vector_data: arm_vectordata_type,

    #[doc = "< CPS mode for CPS instruction"]

    pub cps_mode: arm_cpsmode_type,

    #[doc = "< CPS mode for CPS instruction"]

    pub cps_flag: arm_cpsflag_type,

    #[doc = "< conditional code for this insn"]

    pub cc: arm_cc,

    #[doc = "< does this insn update flags?"]

    pub update_flags: bool,

    #[doc = "< does this insn write-back?"]

    pub writeback: bool,

    #[doc = "< Option for some memory barrier instructions"]

    pub mem_barrier: arm_mem_barrier,

    #[doc = " Number of operands of this instruction,"]

    #[doc = " or 0 when instruction has no operand."]

    pub op_count: u8,

    #[doc = "< operands for this instruction."]

    pub operands: [cs_arm_op; 36usize],

}

impl Clone for cs_arm {

    fn clone(&self) -> Self {

        *self

    }

}

impl ::core::fmt::Debug for cs_arm {

    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {

        write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: [...] }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . mem_barrier , self . op_count)

    }

}

#[repr(u32)]

#[doc = " ARM instruction"]

#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]

pub enum arm_insn {

    ARM_INS_INVALID = 0,

    ARM_INS_ADC = 1,

    ARM_INS_ADD = 2,

    ARM_INS_ADDW = 3,

    ARM_INS_ADR = 4,

    ARM_INS_AESD = 5,

    ARM_INS_AESE = 6,

    ARM_INS_AESIMC = 7,

    ARM_INS_AESMC = 8,

    ARM_INS_AND = 9,

    ARM_INS_ASR = 10,

    ARM_INS_B = 11,

    ARM_INS_BFC = 12,

    ARM_INS_BFI = 13,

    ARM_INS_BIC = 14,

    ARM_INS_BKPT = 15,

    ARM_INS_BL = 16,

    ARM_INS_BLX = 17,

    ARM_INS_BLXNS = 18,

    ARM_INS_BX = 19,

    ARM_INS_BXJ = 20,

    ARM_INS_BXNS = 21,

    ARM_INS_CBNZ = 22,

    ARM_INS_CBZ = 23,

    ARM_INS_CDP = 24,

    ARM_INS_CDP2 = 25,

    ARM_INS_CLREX = 26,

    ARM_INS_CLZ = 27,

    ARM_INS_CMN = 28,

    ARM_INS_CMP = 29,

    ARM_INS_CPS = 30,

    ARM_INS_CRC32B = 31,

    ARM_INS_CRC32CB = 32,

    ARM_INS_CRC32CH = 33,

    ARM_INS_CRC32CW = 34,

    ARM_INS_CRC32H = 35,

    ARM_INS_CRC32W = 36,

    ARM_INS_CSDB = 37,

    ARM_INS_DBG = 38,

    ARM_INS_DCPS1 = 39,

    ARM_INS_DCPS2 = 40,

    ARM_INS_DCPS3 = 41,

    ARM_INS_DFB = 42,

    ARM_INS_DMB = 43,

    ARM_INS_DSB = 44,

    ARM_INS_EOR = 45,

    ARM_INS_ERET = 46,

    ARM_INS_ESB = 47,

    ARM_INS_FADDD = 48,

    ARM_INS_FADDS = 49,

    ARM_INS_FCMPZD = 50,

    ARM_INS_FCMPZS = 51,

    ARM_INS_FCONSTD = 52,

    ARM_INS_FCONSTS = 53,

    ARM_INS_FLDMDBX = 54,

    ARM_INS_FLDMIAX = 55,

    ARM_INS_FMDHR = 56,

    ARM_INS_FMDLR = 57,

    ARM_INS_FMSTAT = 58,

    ARM_INS_FSTMDBX = 59,

    ARM_INS_FSTMIAX = 60,

    ARM_INS_FSUBD = 61,

    ARM_INS_FSUBS = 62,

    ARM_INS_HINT = 63,

    ARM_INS_HLT = 64,

    ARM_INS_HVC = 65,

    ARM_INS_ISB = 66,

    ARM_INS_IT = 67,

    ARM_INS_LDA = 68,

    ARM_INS_LDAB = 69,

    ARM_INS_LDAEX = 70,

    ARM_INS_LDAEXB = 71,

    ARM_INS_LDAEXD = 72,

    ARM_INS_LDAEXH = 73,

    ARM_INS_LDAH = 74,

    ARM_INS_LDC = 75,

    ARM_INS_LDC2 = 76,

    ARM_INS_LDC2L = 77,

    ARM_INS_LDCL = 78,

    ARM_INS_LDM = 79,

    ARM_INS_LDMDA = 80,

    ARM_INS_LDMDB = 81,

    ARM_INS_LDMIB = 82,

    ARM_INS_LDR = 83,

    ARM_INS_LDRB = 84,

    ARM_INS_LDRBT = 85,

    ARM_INS_LDRD = 86,

    ARM_INS_LDREX = 87,

    ARM_INS_LDREXB = 88,

    ARM_INS_LDREXD = 89,

    ARM_INS_LDREXH = 90,

    ARM_INS_LDRH = 91,

    ARM_INS_LDRHT = 92,

    ARM_INS_LDRSB = 93,

    ARM_INS_LDRSBT = 94,

    ARM_INS_LDRSH = 95,

    ARM_INS_LDRSHT = 96,

    ARM_INS_LDRT = 97,

    ARM_INS_LSL = 98,

    ARM_INS_LSR = 99,

    ARM_INS_MCR = 100,

    ARM_INS_MCR2 = 101,

    ARM_INS_MCRR = 102,

    ARM_INS_MCRR2 = 103,