Coverage Report

Created: 2025-12-04 07:01

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/wasmtime/target/debug/build/capstone-sys-fcdbf9c5ea3d46c6/out/capstone.rs
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1
/* automatically generated by rust-bindgen 0.69.4 */
2
3
pub type va_list = __builtin_va_list;
4
pub type csh = usize;
5
#[repr(u32)]
6
#[doc = " Architecture type"]
7
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
8
pub enum cs_arch {
9
    #[doc = "< ARM architecture (including Thumb, Thumb-2)"]
10
    CS_ARCH_ARM = 0,
11
    #[doc = "< ARM-64, also called AArch64"]
12
    CS_ARCH_ARM64 = 1,
13
    #[doc = "< Mips architecture"]
14
    CS_ARCH_MIPS = 2,
15
    #[doc = "< X86 architecture (including x86 & x86-64)"]
16
    CS_ARCH_X86 = 3,
17
    #[doc = "< PowerPC architecture"]
18
    CS_ARCH_PPC = 4,
19
    #[doc = "< Sparc architecture"]
20
    CS_ARCH_SPARC = 5,
21
    #[doc = "< SystemZ architecture"]
22
    CS_ARCH_SYSZ = 6,
23
    #[doc = "< XCore architecture"]
24
    CS_ARCH_XCORE = 7,
25
    #[doc = "< 68K architecture"]
26
    CS_ARCH_M68K = 8,
27
    #[doc = "< TMS320C64x architecture"]
28
    CS_ARCH_TMS320C64X = 9,
29
    #[doc = "< 680X architecture"]
30
    CS_ARCH_M680X = 10,
31
    #[doc = "< Ethereum architecture"]
32
    CS_ARCH_EVM = 11,
33
    #[doc = "< MOS65XX architecture (including MOS6502)"]
34
    CS_ARCH_MOS65XX = 12,
35
    #[doc = "< WebAssembly architecture"]
36
    CS_ARCH_WASM = 13,
37
    #[doc = "< Berkeley Packet Filter architecture (including eBPF)"]
38
    CS_ARCH_BPF = 14,
39
    #[doc = "< RISCV architecture"]
40
    CS_ARCH_RISCV = 15,
41
    CS_ARCH_MAX = 16,
42
    CS_ARCH_ALL = 65535,
43
}
44
impl cs_mode {
45
    #[doc = "< little-endian mode (default mode)"]
46
    pub const CS_MODE_LITTLE_ENDIAN: cs_mode = cs_mode(0);
47
}
48
impl cs_mode {
49
    #[doc = "< 32-bit ARM"]
50
    pub const CS_MODE_ARM: cs_mode = cs_mode(0);
51
}
52
impl cs_mode {
53
    #[doc = "< 16-bit mode (X86)"]
54
    pub const CS_MODE_16: cs_mode = cs_mode(2);
55
}
56
impl cs_mode {
57
    #[doc = "< 32-bit mode (X86)"]
58
    pub const CS_MODE_32: cs_mode = cs_mode(4);
59
}
60
impl cs_mode {
61
    #[doc = "< 64-bit mode (X86, PPC)"]
62
    pub const CS_MODE_64: cs_mode = cs_mode(8);
63
}
64
impl cs_mode {
65
    #[doc = "< ARM's Thumb mode, including Thumb-2"]
66
    pub const CS_MODE_THUMB: cs_mode = cs_mode(16);
67
}
68
impl cs_mode {
69
    #[doc = "< ARM's Cortex-M series"]
70
    pub const CS_MODE_MCLASS: cs_mode = cs_mode(32);
71
}
72
impl cs_mode {
73
    #[doc = "< ARMv8 A32 encodings for ARM"]
74
    pub const CS_MODE_V8: cs_mode = cs_mode(64);
75
}
76
impl cs_mode {
77
    #[doc = "< MicroMips mode (MIPS)"]
78
    pub const CS_MODE_MICRO: cs_mode = cs_mode(16);
79
}
80
impl cs_mode {
81
    #[doc = "< Mips III ISA"]
82
    pub const CS_MODE_MIPS3: cs_mode = cs_mode(32);
83
}
84
impl cs_mode {
85
    #[doc = "< Mips32r6 ISA"]
86
    pub const CS_MODE_MIPS32R6: cs_mode = cs_mode(64);
87
}
88
impl cs_mode {
89
    #[doc = "< Mips II ISA"]
90
    pub const CS_MODE_MIPS2: cs_mode = cs_mode(128);
91
}
92
impl cs_mode {
93
    #[doc = "< SparcV9 mode (Sparc)"]
94
    pub const CS_MODE_V9: cs_mode = cs_mode(16);
95
}
96
impl cs_mode {
97
    #[doc = "< Quad Processing eXtensions mode (PPC)"]
98
    pub const CS_MODE_QPX: cs_mode = cs_mode(16);
99
}
100
impl cs_mode {
101
    #[doc = "< Signal Processing Engine mode (PPC)"]
102
    pub const CS_MODE_SPE: cs_mode = cs_mode(32);
103
}
104
impl cs_mode {
105
    #[doc = "< Book-E mode (PPC)"]
106
    pub const CS_MODE_BOOKE: cs_mode = cs_mode(64);
107
}
108
impl cs_mode {
109
    #[doc = "< M68K 68000 mode"]
110
    pub const CS_MODE_M68K_000: cs_mode = cs_mode(2);
111
}
112
impl cs_mode {
113
    #[doc = "< M68K 68010 mode"]
114
    pub const CS_MODE_M68K_010: cs_mode = cs_mode(4);
115
}
116
impl cs_mode {
117
    #[doc = "< M68K 68020 mode"]
118
    pub const CS_MODE_M68K_020: cs_mode = cs_mode(8);
119
}
120
impl cs_mode {
121
    #[doc = "< M68K 68030 mode"]
122
    pub const CS_MODE_M68K_030: cs_mode = cs_mode(16);
123
}
124
impl cs_mode {
125
    #[doc = "< M68K 68040 mode"]
126
    pub const CS_MODE_M68K_040: cs_mode = cs_mode(32);
127
}
128
impl cs_mode {
129
    #[doc = "< M68K 68060 mode"]
130
    pub const CS_MODE_M68K_060: cs_mode = cs_mode(64);
131
}
132
impl cs_mode {
133
    #[doc = "< big-endian mode"]
134
    pub const CS_MODE_BIG_ENDIAN: cs_mode = cs_mode(2147483648);
135
}
136
impl cs_mode {
137
    #[doc = "< Mips32 ISA (Mips)"]
138
    pub const CS_MODE_MIPS32: cs_mode = cs_mode(4);
139
}
140
impl cs_mode {
141
    #[doc = "< Mips64 ISA (Mips)"]
142
    pub const CS_MODE_MIPS64: cs_mode = cs_mode(8);
143
}
144
impl cs_mode {
145
    #[doc = "< M680X Hitachi 6301,6303 mode"]
146
    pub const CS_MODE_M680X_6301: cs_mode = cs_mode(2);
147
}
148
impl cs_mode {
149
    #[doc = "< M680X Hitachi 6309 mode"]
150
    pub const CS_MODE_M680X_6309: cs_mode = cs_mode(4);
151
}
152
impl cs_mode {
153
    #[doc = "< M680X Motorola 6800,6802 mode"]
154
    pub const CS_MODE_M680X_6800: cs_mode = cs_mode(8);
155
}
156
impl cs_mode {
157
    #[doc = "< M680X Motorola 6801,6803 mode"]
158
    pub const CS_MODE_M680X_6801: cs_mode = cs_mode(16);
159
}
160
impl cs_mode {
161
    #[doc = "< M680X Motorola/Freescale 6805 mode"]
162
    pub const CS_MODE_M680X_6805: cs_mode = cs_mode(32);
163
}
164
impl cs_mode {
165
    #[doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"]
166
    pub const CS_MODE_M680X_6808: cs_mode = cs_mode(64);
167
}
168
impl cs_mode {
169
    #[doc = "< M680X Motorola 6809 mode"]
170
    pub const CS_MODE_M680X_6809: cs_mode = cs_mode(128);
171
}
172
impl cs_mode {
173
    #[doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"]
174
    pub const CS_MODE_M680X_6811: cs_mode = cs_mode(256);
175
}
176
impl cs_mode {
177
    #[doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"]
178
    pub const CS_MODE_M680X_CPU12: cs_mode = cs_mode(512);
179
}
180
impl cs_mode {
181
    #[doc = "< M680X Freescale/NXP HCS08 mode"]
182
    pub const CS_MODE_M680X_HCS08: cs_mode = cs_mode(1024);
183
}
184
impl cs_mode {
185
    #[doc = "< Classic BPF mode (default)"]
186
    pub const CS_MODE_BPF_CLASSIC: cs_mode = cs_mode(0);
187
}
188
impl cs_mode {
189
    #[doc = "< Extended BPF mode"]
190
    pub const CS_MODE_BPF_EXTENDED: cs_mode = cs_mode(1);
191
}
192
impl cs_mode {
193
    #[doc = "< RISCV RV32G"]
194
    pub const CS_MODE_RISCV32: cs_mode = cs_mode(1);
195
}
196
impl cs_mode {
197
    #[doc = "< RISCV RV64G"]
198
    pub const CS_MODE_RISCV64: cs_mode = cs_mode(2);
199
}
200
impl cs_mode {
201
    #[doc = "< RISCV compressed instructure mode"]
202
    pub const CS_MODE_RISCVC: cs_mode = cs_mode(4);
203
}
204
impl cs_mode {
205
    #[doc = "< MOS65XXX MOS 6502"]
206
    pub const CS_MODE_MOS65XX_6502: cs_mode = cs_mode(2);
207
}
208
impl cs_mode {
209
    #[doc = "< MOS65XXX WDC 65c02"]
210
    pub const CS_MODE_MOS65XX_65C02: cs_mode = cs_mode(4);
211
}
212
impl cs_mode {
213
    #[doc = "< MOS65XXX WDC W65c02"]
214
    pub const CS_MODE_MOS65XX_W65C02: cs_mode = cs_mode(8);
215
}
216
impl cs_mode {
217
    #[doc = "< MOS65XXX WDC 65816, 8-bit m/x"]
218
    pub const CS_MODE_MOS65XX_65816: cs_mode = cs_mode(16);
219
}
220
impl cs_mode {
221
    #[doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"]
222
    pub const CS_MODE_MOS65XX_65816_LONG_M: cs_mode = cs_mode(32);
223
}
224
impl cs_mode {
225
    #[doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"]
226
    pub const CS_MODE_MOS65XX_65816_LONG_X: cs_mode = cs_mode(64);
227
}
228
impl cs_mode {
229
    pub const CS_MODE_MOS65XX_65816_LONG_MX: cs_mode = cs_mode(96);
230
}
231
impl ::core::ops::BitOr<cs_mode> for cs_mode {
232
    type Output = Self;
233
    #[inline]
234
18.4k
    fn bitor(self, other: Self) -> Self {
235
18.4k
        cs_mode(self.0 | other.0)
236
18.4k
    }
<capstone_sys::cs_mode as core::ops::bit::BitOr>::bitor
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234
18.4k
    fn bitor(self, other: Self) -> Self {
235
18.4k
        cs_mode(self.0 | other.0)
236
18.4k
    }
Unexecuted instantiation: <capstone_sys::cs_mode as core::ops::bit::BitOr>::bitor
237
}
238
impl ::core::ops::BitOrAssign for cs_mode {
239
    #[inline]
240
0
    fn bitor_assign(&mut self, rhs: cs_mode) {
241
0
        self.0 |= rhs.0;
242
0
    }
243
}
244
impl ::core::ops::BitAnd<cs_mode> for cs_mode {
245
    type Output = Self;
246
    #[inline]
247
0
    fn bitand(self, other: Self) -> Self {
248
0
        cs_mode(self.0 & other.0)
249
0
    }
250
}
251
impl ::core::ops::BitAndAssign for cs_mode {
252
    #[inline]
253
0
    fn bitand_assign(&mut self, rhs: cs_mode) {
254
0
        self.0 &= rhs.0;
255
0
    }
256
}
257
#[repr(transparent)]
258
#[doc = " Mode type"]
259
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
260
pub struct cs_mode(pub libc::c_uint);
261
pub type cs_malloc_t =
262
    ::core::option::Option<unsafe extern "C" fn(size: usize) -> *mut libc::c_void>;
263
pub type cs_calloc_t =
264
    ::core::option::Option<unsafe extern "C" fn(nmemb: usize, size: usize) -> *mut libc::c_void>;
265
pub type cs_realloc_t = ::core::option::Option<
266
    unsafe extern "C" fn(ptr: *mut libc::c_void, size: usize) -> *mut libc::c_void,
267
>;
268
pub type cs_free_t = ::core::option::Option<unsafe extern "C" fn(ptr: *mut libc::c_void)>;
269
pub type cs_vsnprintf_t = ::core::option::Option<
270
    unsafe extern "C" fn(
271
        str_: *mut libc::c_char,
272
        size: usize,
273
        format: *const libc::c_char,
274
        ap: *mut __va_list_tag,
275
    ) -> libc::c_int,
276
>;
277
#[doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."]
278
#[repr(C)]
279
#[derive(Debug, Copy, Clone)]
280
pub struct cs_opt_mem {
281
    pub malloc: cs_malloc_t,
282
    pub calloc: cs_calloc_t,
283
    pub realloc: cs_realloc_t,
284
    pub free: cs_free_t,
285
    pub vsnprintf: cs_vsnprintf_t,
286
}
287
#[doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."]
288
#[repr(C)]
289
#[derive(Debug, Copy, Clone)]
290
pub struct cs_opt_mnem {
291
    #[doc = " ID of instruction to be customized."]
292
    pub id: libc::c_uint,
293
    #[doc = " Customized instruction mnemonic."]
294
    pub mnemonic: *const libc::c_char,
295
}
296
#[repr(u32)]
297
#[doc = " Runtime option for the disassembled engine"]
298
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
299
pub enum cs_opt_type {
300
    #[doc = "< No option specified"]
301
    CS_OPT_INVALID = 0,
302
    #[doc = "< Assembly output syntax"]
303
    CS_OPT_SYNTAX = 1,
304
    #[doc = "< Break down instruction structure into details"]
305
    CS_OPT_DETAIL = 2,
306
    #[doc = "< Change engine's mode at run-time"]
307
    CS_OPT_MODE = 3,
308
    #[doc = "< User-defined dynamic memory related functions"]
309
    CS_OPT_MEM = 4,
310
    #[doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."]
311
    CS_OPT_SKIPDATA = 5,
312
    #[doc = "< Setup user-defined function for SKIPDATA option"]
313
    CS_OPT_SKIPDATA_SETUP = 6,
314
    #[doc = "< Customize instruction mnemonic"]
315
    CS_OPT_MNEMONIC = 7,
316
    #[doc = "< print immediate operands in unsigned form"]
317
    CS_OPT_UNSIGNED = 8,
318
}
319
pub mod cs_opt_value {
320
    #[doc = " Runtime option value (associated with option type above)"]
321
    pub type Type = libc::c_uint;
322
    #[doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."]
323
    pub const CS_OPT_OFF: Type = 0;
324
    #[doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."]
325
    pub const CS_OPT_ON: Type = 3;
326
    #[doc = "< Default asm syntax (CS_OPT_SYNTAX)."]
327
    pub const CS_OPT_SYNTAX_DEFAULT: Type = 0;
328
    #[doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."]
329
    pub const CS_OPT_SYNTAX_INTEL: Type = 1;
330
    #[doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."]
331
    pub const CS_OPT_SYNTAX_ATT: Type = 2;
332
    #[doc = "< Prints register name with only number (CS_OPT_SYNTAX)"]
333
    pub const CS_OPT_SYNTAX_NOREGNAME: Type = 3;
334
    #[doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."]
335
    pub const CS_OPT_SYNTAX_MASM: Type = 4;
336
    #[doc = "< MOS65XX use $ as hex prefix"]
337
    pub const CS_OPT_SYNTAX_MOTOROLA: Type = 5;
338
}
339
#[repr(u32)]
340
#[doc = " Common instruction operand types - to be consistent across all architectures."]
341
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
342
pub enum cs_op_type {
343
    #[doc = "< uninitialized/invalid operand."]
344
    CS_OP_INVALID = 0,
345
    #[doc = "< Register operand."]
346
    CS_OP_REG = 1,
347
    #[doc = "< Immediate operand."]
348
    CS_OP_IMM = 2,
349
    #[doc = "< Memory operand."]
350
    CS_OP_MEM = 3,
351
    #[doc = "< Floating-Point operand."]
352
    CS_OP_FP = 4,
353
}
354
impl cs_ac_type {
355
    #[doc = "< Uninitialized/invalid access type."]
356
    pub const CS_AC_INVALID: cs_ac_type = cs_ac_type(0);
357
}
358
impl cs_ac_type {
359
    #[doc = "< Operand read from memory or register."]
360
    pub const CS_AC_READ: cs_ac_type = cs_ac_type(1);
361
}
362
impl cs_ac_type {
363
    #[doc = "< Operand write to memory or register."]
364
    pub const CS_AC_WRITE: cs_ac_type = cs_ac_type(2);
365
}
366
impl ::core::ops::BitOr<cs_ac_type> for cs_ac_type {
367
    type Output = Self;
368
    #[inline]
369
0
    fn bitor(self, other: Self) -> Self {
370
0
        cs_ac_type(self.0 | other.0)
371
0
    }
Unexecuted instantiation: <capstone_sys::cs_ac_type as core::ops::bit::BitOr>::bitor
Unexecuted instantiation: <capstone_sys::cs_ac_type as core::ops::bit::BitOr>::bitor
372
}
373
impl ::core::ops::BitOrAssign for cs_ac_type {
374
    #[inline]
375
0
    fn bitor_assign(&mut self, rhs: cs_ac_type) {
376
0
        self.0 |= rhs.0;
377
0
    }
378
}
379
impl ::core::ops::BitAnd<cs_ac_type> for cs_ac_type {
380
    type Output = Self;
381
    #[inline]
382
0
    fn bitand(self, other: Self) -> Self {
383
0
        cs_ac_type(self.0 & other.0)
384
0
    }
Unexecuted instantiation: <capstone_sys::cs_ac_type as core::ops::bit::BitAnd>::bitand
Unexecuted instantiation: <capstone_sys::cs_ac_type as core::ops::bit::BitAnd>::bitand
385
}
386
impl ::core::ops::BitAndAssign for cs_ac_type {
387
    #[inline]
388
0
    fn bitand_assign(&mut self, rhs: cs_ac_type) {
389
0
        self.0 &= rhs.0;
390
0
    }
391
}
392
#[repr(transparent)]
393
#[doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"]
394
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
395
pub struct cs_ac_type(pub libc::c_uint);
396
pub mod cs_group_type {
397
    #[doc = " Common instruction groups - to be consistent across all architectures."]
398
    pub type Type = libc::c_uint;
399
    #[doc = "< uninitialized/invalid group."]
400
    pub const CS_GRP_INVALID: Type = 0;
401
    #[doc = "< all jump instructions (conditional+direct+indirect jumps)"]
402
    pub const CS_GRP_JUMP: Type = 1;
403
    #[doc = "< all call instructions"]
404
    pub const CS_GRP_CALL: Type = 2;
405
    #[doc = "< all return instructions"]
406
    pub const CS_GRP_RET: Type = 3;
407
    #[doc = "< all interrupt instructions (int+syscall)"]
408
    pub const CS_GRP_INT: Type = 4;
409
    #[doc = "< all interrupt return instructions"]
410
    pub const CS_GRP_IRET: Type = 5;
411
    #[doc = "< all privileged instructions"]
412
    pub const CS_GRP_PRIVILEGE: Type = 6;
413
    #[doc = "< all relative branching instructions"]
414
    pub const CS_GRP_BRANCH_RELATIVE: Type = 7;
415
}
416
#[doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."]
417
pub type cs_skipdata_cb_t = ::core::option::Option<
418
    unsafe extern "C" fn(
419
        code: *const u8,
420
        code_size: usize,
421
        offset: usize,
422
        user_data: *mut libc::c_void,
423
    ) -> usize,
424
>;
425
#[doc = " User-customized setup for SKIPDATA option"]
426
#[repr(C)]
427
#[derive(Debug, Copy, Clone)]
428
pub struct cs_opt_skipdata {
429
    #[doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."]
430
    pub mnemonic: *const libc::c_char,
431
    #[doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes."]
432
    pub callback: cs_skipdata_cb_t,
433
    #[doc = " User-defined data to be passed to @callback function pointer."]
434
    pub user_data: *mut libc::c_void,
435
}
436
#[repr(u32)]
437
#[doc = " ARM shift type"]
438
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
439
pub enum arm_shifter {
440
    ARM_SFT_INVALID = 0,
441
    #[doc = "< shift with immediate const"]
442
    ARM_SFT_ASR = 1,
443
    #[doc = "< shift with immediate const"]
444
    ARM_SFT_LSL = 2,
445
    #[doc = "< shift with immediate const"]
446
    ARM_SFT_LSR = 3,
447
    #[doc = "< shift with immediate const"]
448
    ARM_SFT_ROR = 4,
449
    #[doc = "< shift with immediate const"]
450
    ARM_SFT_RRX = 5,
451
    #[doc = "< shift with register"]
452
    ARM_SFT_ASR_REG = 6,
453
    #[doc = "< shift with register"]
454
    ARM_SFT_LSL_REG = 7,
455
    #[doc = "< shift with register"]
456
    ARM_SFT_LSR_REG = 8,
457
    #[doc = "< shift with register"]
458
    ARM_SFT_ROR_REG = 9,
459
    #[doc = "< shift with register"]
460
    ARM_SFT_RRX_REG = 10,
461
}
462
#[repr(u32)]
463
#[doc = " ARM condition code"]
464
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
465
pub enum arm_cc {
466
    ARM_CC_INVALID = 0,
467
    #[doc = "< Equal                      Equal"]
468
    ARM_CC_EQ = 1,
469
    #[doc = "< Not equal                  Not equal, or unordered"]
470
    ARM_CC_NE = 2,
471
    #[doc = "< Carry set                  >, ==, or unordered"]
472
    ARM_CC_HS = 3,
473
    #[doc = "< Carry clear                Less than"]
474
    ARM_CC_LO = 4,
475
    #[doc = "< Minus, negative            Less than"]
476
    ARM_CC_MI = 5,
477
    #[doc = "< Plus, positive or zero     >, ==, or unordered"]
478
    ARM_CC_PL = 6,
479
    #[doc = "< Overflow                   Unordered"]
480
    ARM_CC_VS = 7,
481
    #[doc = "< No overflow                Not unordered"]
482
    ARM_CC_VC = 8,
483
    #[doc = "< Unsigned higher            Greater than, or unordered"]
484
    ARM_CC_HI = 9,
485
    #[doc = "< Unsigned lower or same     Less than or equal"]
486
    ARM_CC_LS = 10,
487
    #[doc = "< Greater than or equal      Greater than or equal"]
488
    ARM_CC_GE = 11,
489
    #[doc = "< Less than                  Less than, or unordered"]
490
    ARM_CC_LT = 12,
491
    #[doc = "< Greater than               Greater than"]
492
    ARM_CC_GT = 13,
493
    #[doc = "< Less than or equal         <, ==, or unordered"]
494
    ARM_CC_LE = 14,
495
    #[doc = "< Always (unconditional)     Always (unconditional)"]
496
    ARM_CC_AL = 15,
497
}
498
#[repr(u32)]
499
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
500
pub enum arm_sysreg {
501
    #[doc = " Special registers for MSR"]
502
    ARM_SYSREG_INVALID = 0,
503
    #[doc = " Special registers for MSR"]
504
    ARM_SYSREG_SPSR_C = 1,
505
    #[doc = " Special registers for MSR"]
506
    ARM_SYSREG_SPSR_X = 2,
507
    #[doc = " Special registers for MSR"]
508
    ARM_SYSREG_SPSR_S = 4,
509
    #[doc = " Special registers for MSR"]
510
    ARM_SYSREG_SPSR_F = 8,
511
    #[doc = " Special registers for MSR"]
512
    ARM_SYSREG_CPSR_C = 16,
513
    #[doc = " Special registers for MSR"]
514
    ARM_SYSREG_CPSR_X = 32,
515
    #[doc = " Special registers for MSR"]
516
    ARM_SYSREG_CPSR_S = 64,
517
    #[doc = " Special registers for MSR"]
518
    ARM_SYSREG_CPSR_F = 128,
519
    #[doc = " Special registers for MSR"]
520
    ARM_SYSREG_APSR = 256,
521
    #[doc = " Special registers for MSR"]
522
    ARM_SYSREG_APSR_G = 257,
523
    #[doc = " Special registers for MSR"]
524
    ARM_SYSREG_APSR_NZCVQ = 258,
525
    #[doc = " Special registers for MSR"]
526
    ARM_SYSREG_APSR_NZCVQG = 259,
527
    #[doc = " Special registers for MSR"]
528
    ARM_SYSREG_IAPSR = 260,
529
    #[doc = " Special registers for MSR"]
530
    ARM_SYSREG_IAPSR_G = 261,
531
    #[doc = " Special registers for MSR"]
532
    ARM_SYSREG_IAPSR_NZCVQG = 262,
533
    #[doc = " Special registers for MSR"]
534
    ARM_SYSREG_IAPSR_NZCVQ = 263,
535
    #[doc = " Special registers for MSR"]
536
    ARM_SYSREG_EAPSR = 264,
537
    #[doc = " Special registers for MSR"]
538
    ARM_SYSREG_EAPSR_G = 265,
539
    #[doc = " Special registers for MSR"]
540
    ARM_SYSREG_EAPSR_NZCVQG = 266,
541
    #[doc = " Special registers for MSR"]
542
    ARM_SYSREG_EAPSR_NZCVQ = 267,
543
    #[doc = " Special registers for MSR"]
544
    ARM_SYSREG_XPSR = 268,
545
    #[doc = " Special registers for MSR"]
546
    ARM_SYSREG_XPSR_G = 269,
547
    #[doc = " Special registers for MSR"]
548
    ARM_SYSREG_XPSR_NZCVQG = 270,
549
    #[doc = " Special registers for MSR"]
550
    ARM_SYSREG_XPSR_NZCVQ = 271,
551
    #[doc = " Special registers for MSR"]
552
    ARM_SYSREG_IPSR = 272,
553
    #[doc = " Special registers for MSR"]
554
    ARM_SYSREG_EPSR = 273,
555
    #[doc = " Special registers for MSR"]
556
    ARM_SYSREG_IEPSR = 274,
557
    #[doc = " Special registers for MSR"]
558
    ARM_SYSREG_MSP = 275,
559
    #[doc = " Special registers for MSR"]
560
    ARM_SYSREG_PSP = 276,
561
    #[doc = " Special registers for MSR"]
562
    ARM_SYSREG_PRIMASK = 277,
563
    #[doc = " Special registers for MSR"]
564
    ARM_SYSREG_BASEPRI = 278,
565
    #[doc = " Special registers for MSR"]
566
    ARM_SYSREG_BASEPRI_MAX = 279,
567
    #[doc = " Special registers for MSR"]
568
    ARM_SYSREG_FAULTMASK = 280,
569
    #[doc = " Special registers for MSR"]
570
    ARM_SYSREG_CONTROL = 281,
571
    #[doc = " Special registers for MSR"]
572
    ARM_SYSREG_MSPLIM = 282,
573
    #[doc = " Special registers for MSR"]
574
    ARM_SYSREG_PSPLIM = 283,
575
    #[doc = " Special registers for MSR"]
576
    ARM_SYSREG_MSP_NS = 284,
577
    #[doc = " Special registers for MSR"]
578
    ARM_SYSREG_PSP_NS = 285,
579
    #[doc = " Special registers for MSR"]
580
    ARM_SYSREG_MSPLIM_NS = 286,
581
    #[doc = " Special registers for MSR"]
582
    ARM_SYSREG_PSPLIM_NS = 287,
583
    #[doc = " Special registers for MSR"]
584
    ARM_SYSREG_PRIMASK_NS = 288,
585
    #[doc = " Special registers for MSR"]
586
    ARM_SYSREG_BASEPRI_NS = 289,
587
    #[doc = " Special registers for MSR"]
588
    ARM_SYSREG_FAULTMASK_NS = 290,
589
    #[doc = " Special registers for MSR"]
590
    ARM_SYSREG_CONTROL_NS = 291,
591
    #[doc = " Special registers for MSR"]
592
    ARM_SYSREG_SP_NS = 292,
593
    #[doc = " Special registers for MSR"]
594
    ARM_SYSREG_R8_USR = 293,
595
    #[doc = " Special registers for MSR"]
596
    ARM_SYSREG_R9_USR = 294,
597
    #[doc = " Special registers for MSR"]
598
    ARM_SYSREG_R10_USR = 295,
599
    #[doc = " Special registers for MSR"]
600
    ARM_SYSREG_R11_USR = 296,
601
    #[doc = " Special registers for MSR"]
602
    ARM_SYSREG_R12_USR = 297,
603
    #[doc = " Special registers for MSR"]
604
    ARM_SYSREG_SP_USR = 298,
605
    #[doc = " Special registers for MSR"]
606
    ARM_SYSREG_LR_USR = 299,
607
    #[doc = " Special registers for MSR"]
608
    ARM_SYSREG_R8_FIQ = 300,
609
    #[doc = " Special registers for MSR"]
610
    ARM_SYSREG_R9_FIQ = 301,
611
    #[doc = " Special registers for MSR"]
612
    ARM_SYSREG_R10_FIQ = 302,
613
    #[doc = " Special registers for MSR"]
614
    ARM_SYSREG_R11_FIQ = 303,
615
    #[doc = " Special registers for MSR"]
616
    ARM_SYSREG_R12_FIQ = 304,
617
    #[doc = " Special registers for MSR"]
618
    ARM_SYSREG_SP_FIQ = 305,
619
    #[doc = " Special registers for MSR"]
620
    ARM_SYSREG_LR_FIQ = 306,
621
    #[doc = " Special registers for MSR"]
622
    ARM_SYSREG_LR_IRQ = 307,
623
    #[doc = " Special registers for MSR"]
624
    ARM_SYSREG_SP_IRQ = 308,
625
    #[doc = " Special registers for MSR"]
626
    ARM_SYSREG_LR_SVC = 309,
627
    #[doc = " Special registers for MSR"]
628
    ARM_SYSREG_SP_SVC = 310,
629
    #[doc = " Special registers for MSR"]
630
    ARM_SYSREG_LR_ABT = 311,
631
    #[doc = " Special registers for MSR"]
632
    ARM_SYSREG_SP_ABT = 312,
633
    #[doc = " Special registers for MSR"]
634
    ARM_SYSREG_LR_UND = 313,
635
    #[doc = " Special registers for MSR"]
636
    ARM_SYSREG_SP_UND = 314,
637
    #[doc = " Special registers for MSR"]
638
    ARM_SYSREG_LR_MON = 315,
639
    #[doc = " Special registers for MSR"]
640
    ARM_SYSREG_SP_MON = 316,
641
    #[doc = " Special registers for MSR"]
642
    ARM_SYSREG_ELR_HYP = 317,
643
    #[doc = " Special registers for MSR"]
644
    ARM_SYSREG_SP_HYP = 318,
645
    #[doc = " Special registers for MSR"]
646
    ARM_SYSREG_SPSR_FIQ = 319,
647
    #[doc = " Special registers for MSR"]
648
    ARM_SYSREG_SPSR_IRQ = 320,
649
    #[doc = " Special registers for MSR"]
650
    ARM_SYSREG_SPSR_SVC = 321,
651
    #[doc = " Special registers for MSR"]
652
    ARM_SYSREG_SPSR_ABT = 322,
653
    #[doc = " Special registers for MSR"]
654
    ARM_SYSREG_SPSR_UND = 323,
655
    #[doc = " Special registers for MSR"]
656
    ARM_SYSREG_SPSR_MON = 324,
657
    #[doc = " Special registers for MSR"]
658
    ARM_SYSREG_SPSR_HYP = 325,
659
}
660
#[repr(u32)]
661
#[doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."]
662
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
663
pub enum arm_mem_barrier {
664
    ARM_MB_INVALID = 0,
665
    ARM_MB_RESERVED_0 = 1,
666
    ARM_MB_OSHLD = 2,
667
    ARM_MB_OSHST = 3,
668
    ARM_MB_OSH = 4,
669
    ARM_MB_RESERVED_4 = 5,
670
    ARM_MB_NSHLD = 6,
671
    ARM_MB_NSHST = 7,
672
    ARM_MB_NSH = 8,
673
    ARM_MB_RESERVED_8 = 9,
674
    ARM_MB_ISHLD = 10,
675
    ARM_MB_ISHST = 11,
676
    ARM_MB_ISH = 12,
677
    ARM_MB_RESERVED_12 = 13,
678
    ARM_MB_LD = 14,
679
    ARM_MB_ST = 15,
680
    ARM_MB_SY = 16,
681
}
682
#[repr(u32)]
683
#[doc = " Operand type for instruction's operands"]
684
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
685
pub enum arm_op_type {
686
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
687
    ARM_OP_INVALID = 0,
688
    #[doc = "< = CS_OP_REG (Register operand)."]
689
    ARM_OP_REG = 1,
690
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
691
    ARM_OP_IMM = 2,
692
    #[doc = "< = CS_OP_MEM (Memory operand)."]
693
    ARM_OP_MEM = 3,
694
    #[doc = "< = CS_OP_FP (Floating-Point operand)."]
695
    ARM_OP_FP = 4,
696
    #[doc = "< C-Immediate (coprocessor registers)"]
697
    ARM_OP_CIMM = 64,
698
    #[doc = "< P-Immediate (coprocessor registers)"]
699
    ARM_OP_PIMM = 65,
700
    #[doc = "< operand for SETEND instruction"]
701
    ARM_OP_SETEND = 66,
702
    #[doc = "< MSR/MRS special register operand"]
703
    ARM_OP_SYSREG = 67,
704
}
705
#[repr(u32)]
706
#[doc = " Operand type for SETEND instruction"]
707
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
708
pub enum arm_setend_type {
709
    #[doc = "< Uninitialized."]
710
    ARM_SETEND_INVALID = 0,
711
    #[doc = "< BE operand."]
712
    ARM_SETEND_BE = 1,
713
    #[doc = "< LE operand"]
714
    ARM_SETEND_LE = 2,
715
}
716
#[repr(u32)]
717
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
718
pub enum arm_cpsmode_type {
719
    ARM_CPSMODE_INVALID = 0,
720
    ARM_CPSMODE_IE = 2,
721
    ARM_CPSMODE_ID = 3,
722
}
723
#[repr(u32)]
724
#[doc = " Operand type for SETEND instruction"]
725
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
726
pub enum arm_cpsflag_type {
727
    ARM_CPSFLAG_INVALID = 0,
728
    ARM_CPSFLAG_F = 1,
729
    ARM_CPSFLAG_I = 2,
730
    ARM_CPSFLAG_A = 4,
731
    #[doc = "< no flag"]
732
    ARM_CPSFLAG_NONE = 16,
733
}
734
#[repr(u32)]
735
#[doc = " Data type for elements of vector instructions."]
736
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
737
pub enum arm_vectordata_type {
738
    ARM_VECTORDATA_INVALID = 0,
739
    ARM_VECTORDATA_I8 = 1,
740
    ARM_VECTORDATA_I16 = 2,
741
    ARM_VECTORDATA_I32 = 3,
742
    ARM_VECTORDATA_I64 = 4,
743
    ARM_VECTORDATA_S8 = 5,
744
    ARM_VECTORDATA_S16 = 6,
745
    ARM_VECTORDATA_S32 = 7,
746
    ARM_VECTORDATA_S64 = 8,
747
    ARM_VECTORDATA_U8 = 9,
748
    ARM_VECTORDATA_U16 = 10,
749
    ARM_VECTORDATA_U32 = 11,
750
    ARM_VECTORDATA_U64 = 12,
751
    ARM_VECTORDATA_P8 = 13,
752
    ARM_VECTORDATA_F16 = 14,
753
    ARM_VECTORDATA_F32 = 15,
754
    ARM_VECTORDATA_F64 = 16,
755
    ARM_VECTORDATA_F16F64 = 17,
756
    ARM_VECTORDATA_F64F16 = 18,
757
    ARM_VECTORDATA_F32F16 = 19,
758
    ARM_VECTORDATA_F16F32 = 20,
759
    ARM_VECTORDATA_F64F32 = 21,
760
    ARM_VECTORDATA_F32F64 = 22,
761
    ARM_VECTORDATA_S32F32 = 23,
762
    ARM_VECTORDATA_U32F32 = 24,
763
    ARM_VECTORDATA_F32S32 = 25,
764
    ARM_VECTORDATA_F32U32 = 26,
765
    ARM_VECTORDATA_F64S16 = 27,
766
    ARM_VECTORDATA_F32S16 = 28,
767
    ARM_VECTORDATA_F64S32 = 29,
768
    ARM_VECTORDATA_S16F64 = 30,
769
    ARM_VECTORDATA_S16F32 = 31,
770
    ARM_VECTORDATA_S32F64 = 32,
771
    ARM_VECTORDATA_U16F64 = 33,
772
    ARM_VECTORDATA_U16F32 = 34,
773
    ARM_VECTORDATA_U32F64 = 35,
774
    ARM_VECTORDATA_F64U16 = 36,
775
    ARM_VECTORDATA_F32U16 = 37,
776
    ARM_VECTORDATA_F64U32 = 38,
777
    ARM_VECTORDATA_F16U16 = 39,
778
    ARM_VECTORDATA_U16F16 = 40,
779
    ARM_VECTORDATA_F16U32 = 41,
780
    ARM_VECTORDATA_U32F16 = 42,
781
}
782
pub mod arm_reg {
783
    #[doc = " ARM registers"]
784
    pub type Type = libc::c_uint;
785
    pub const ARM_REG_INVALID: Type = 0;
786
    pub const ARM_REG_APSR: Type = 1;
787
    pub const ARM_REG_APSR_NZCV: Type = 2;
788
    pub const ARM_REG_CPSR: Type = 3;
789
    pub const ARM_REG_FPEXC: Type = 4;
790
    pub const ARM_REG_FPINST: Type = 5;
791
    pub const ARM_REG_FPSCR: Type = 6;
792
    pub const ARM_REG_FPSCR_NZCV: Type = 7;
793
    pub const ARM_REG_FPSID: Type = 8;
794
    pub const ARM_REG_ITSTATE: Type = 9;
795
    pub const ARM_REG_LR: Type = 10;
796
    pub const ARM_REG_PC: Type = 11;
797
    pub const ARM_REG_SP: Type = 12;
798
    pub const ARM_REG_SPSR: Type = 13;
799
    pub const ARM_REG_D0: Type = 14;
800
    pub const ARM_REG_D1: Type = 15;
801
    pub const ARM_REG_D2: Type = 16;
802
    pub const ARM_REG_D3: Type = 17;
803
    pub const ARM_REG_D4: Type = 18;
804
    pub const ARM_REG_D5: Type = 19;
805
    pub const ARM_REG_D6: Type = 20;
806
    pub const ARM_REG_D7: Type = 21;
807
    pub const ARM_REG_D8: Type = 22;
808
    pub const ARM_REG_D9: Type = 23;
809
    pub const ARM_REG_D10: Type = 24;
810
    pub const ARM_REG_D11: Type = 25;
811
    pub const ARM_REG_D12: Type = 26;
812
    pub const ARM_REG_D13: Type = 27;
813
    pub const ARM_REG_D14: Type = 28;
814
    pub const ARM_REG_D15: Type = 29;
815
    pub const ARM_REG_D16: Type = 30;
816
    pub const ARM_REG_D17: Type = 31;
817
    pub const ARM_REG_D18: Type = 32;
818
    pub const ARM_REG_D19: Type = 33;
819
    pub const ARM_REG_D20: Type = 34;
820
    pub const ARM_REG_D21: Type = 35;
821
    pub const ARM_REG_D22: Type = 36;
822
    pub const ARM_REG_D23: Type = 37;
823
    pub const ARM_REG_D24: Type = 38;
824
    pub const ARM_REG_D25: Type = 39;
825
    pub const ARM_REG_D26: Type = 40;
826
    pub const ARM_REG_D27: Type = 41;
827
    pub const ARM_REG_D28: Type = 42;
828
    pub const ARM_REG_D29: Type = 43;
829
    pub const ARM_REG_D30: Type = 44;
830
    pub const ARM_REG_D31: Type = 45;
831
    pub const ARM_REG_FPINST2: Type = 46;
832
    pub const ARM_REG_MVFR0: Type = 47;
833
    pub const ARM_REG_MVFR1: Type = 48;
834
    pub const ARM_REG_MVFR2: Type = 49;
835
    pub const ARM_REG_Q0: Type = 50;
836
    pub const ARM_REG_Q1: Type = 51;
837
    pub const ARM_REG_Q2: Type = 52;
838
    pub const ARM_REG_Q3: Type = 53;
839
    pub const ARM_REG_Q4: Type = 54;
840
    pub const ARM_REG_Q5: Type = 55;
841
    pub const ARM_REG_Q6: Type = 56;
842
    pub const ARM_REG_Q7: Type = 57;
843
    pub const ARM_REG_Q8: Type = 58;
844
    pub const ARM_REG_Q9: Type = 59;
845
    pub const ARM_REG_Q10: Type = 60;
846
    pub const ARM_REG_Q11: Type = 61;
847
    pub const ARM_REG_Q12: Type = 62;
848
    pub const ARM_REG_Q13: Type = 63;
849
    pub const ARM_REG_Q14: Type = 64;
850
    pub const ARM_REG_Q15: Type = 65;
851
    pub const ARM_REG_R0: Type = 66;
852
    pub const ARM_REG_R1: Type = 67;
853
    pub const ARM_REG_R2: Type = 68;
854
    pub const ARM_REG_R3: Type = 69;
855
    pub const ARM_REG_R4: Type = 70;
856
    pub const ARM_REG_R5: Type = 71;
857
    pub const ARM_REG_R6: Type = 72;
858
    pub const ARM_REG_R7: Type = 73;
859
    pub const ARM_REG_R8: Type = 74;
860
    pub const ARM_REG_R9: Type = 75;
861
    pub const ARM_REG_R10: Type = 76;
862
    pub const ARM_REG_R11: Type = 77;
863
    pub const ARM_REG_R12: Type = 78;
864
    pub const ARM_REG_S0: Type = 79;
865
    pub const ARM_REG_S1: Type = 80;
866
    pub const ARM_REG_S2: Type = 81;
867
    pub const ARM_REG_S3: Type = 82;
868
    pub const ARM_REG_S4: Type = 83;
869
    pub const ARM_REG_S5: Type = 84;
870
    pub const ARM_REG_S6: Type = 85;
871
    pub const ARM_REG_S7: Type = 86;
872
    pub const ARM_REG_S8: Type = 87;
873
    pub const ARM_REG_S9: Type = 88;
874
    pub const ARM_REG_S10: Type = 89;
875
    pub const ARM_REG_S11: Type = 90;
876
    pub const ARM_REG_S12: Type = 91;
877
    pub const ARM_REG_S13: Type = 92;
878
    pub const ARM_REG_S14: Type = 93;
879
    pub const ARM_REG_S15: Type = 94;
880
    pub const ARM_REG_S16: Type = 95;
881
    pub const ARM_REG_S17: Type = 96;
882
    pub const ARM_REG_S18: Type = 97;
883
    pub const ARM_REG_S19: Type = 98;
884
    pub const ARM_REG_S20: Type = 99;
885
    pub const ARM_REG_S21: Type = 100;
886
    pub const ARM_REG_S22: Type = 101;
887
    pub const ARM_REG_S23: Type = 102;
888
    pub const ARM_REG_S24: Type = 103;
889
    pub const ARM_REG_S25: Type = 104;
890
    pub const ARM_REG_S26: Type = 105;
891
    pub const ARM_REG_S27: Type = 106;
892
    pub const ARM_REG_S28: Type = 107;
893
    pub const ARM_REG_S29: Type = 108;
894
    pub const ARM_REG_S30: Type = 109;
895
    pub const ARM_REG_S31: Type = 110;
896
    pub const ARM_REG_ENDING: Type = 111;
897
    pub const ARM_REG_R13: Type = 12;
898
    pub const ARM_REG_R14: Type = 10;
899
    pub const ARM_REG_R15: Type = 11;
900
    pub const ARM_REG_SB: Type = 75;
901
    pub const ARM_REG_SL: Type = 76;
902
    pub const ARM_REG_FP: Type = 77;
903
    pub const ARM_REG_IP: Type = 78;
904
}
905
#[doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"]
906
#[repr(C)]
907
#[derive(Debug, Copy, Clone)]
908
pub struct arm_op_mem {
909
    #[doc = "< base register"]
910
    pub base: arm_reg::Type,
911
    #[doc = "< index register"]
912
    pub index: arm_reg::Type,
913
    #[doc = "< scale for index register (can be 1, or -1)"]
914
    pub scale: libc::c_int,
915
    #[doc = "< displacement/offset value"]
916
    pub disp: libc::c_int,
917
    #[doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"]
918
    pub lshift: libc::c_int,
919
}
920
#[doc = " Instruction operand"]
921
#[repr(C)]
922
#[derive(Copy, Clone)]
923
pub struct cs_arm_op {
924
    #[doc = "< Vector Index for some vector operands (or -1 if irrelevant)"]
925
    pub vector_index: libc::c_int,
926
    pub shift: cs_arm_op__bindgen_ty_1,
927
    #[doc = "< operand type"]
928
    pub type_: arm_op_type,
929
    pub __bindgen_anon_1: cs_arm_op__bindgen_ty_2,
930
    #[doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."]
931
    pub subtracted: bool,
932
    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."]
933
    pub access: u8,
934
    #[doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"]
935
    pub neon_lane: i8,
936
}
937
#[repr(C)]
938
#[derive(Debug, Copy, Clone)]
939
pub struct cs_arm_op__bindgen_ty_1 {
940
    pub type_: arm_shifter,
941
    pub value: libc::c_uint,
942
}
943
#[repr(C)]
944
#[derive(Copy, Clone)]
945
pub union cs_arm_op__bindgen_ty_2 {
946
    #[doc = "< register value for REG/SYSREG operand"]
947
    pub reg: libc::c_int,
948
    #[doc = "< immediate value for C-IMM, P-IMM or IMM operand"]
949
    pub imm: i32,
950
    #[doc = "< floating point value for FP operand"]
951
    pub fp: f64,
952
    #[doc = "< base/index/scale/disp value for MEM operand"]
953
    pub mem: arm_op_mem,
954
    #[doc = "< SETEND instruction's operand type"]
955
    pub setend: arm_setend_type,
956
}
957
impl ::core::fmt::Debug for cs_arm_op__bindgen_ty_2 {
958
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
959
0
        write!(f, "cs_arm_op__bindgen_ty_2 {{ union }}")
960
0
    }
961
}
962
impl ::core::fmt::Debug for cs_arm_op {
963
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
964
0
        write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted)
965
0
    }
966
}
967
#[doc = " Instruction structure"]
968
#[repr(C)]
969
#[derive(Copy, Clone)]
970
pub struct cs_arm {
971
    #[doc = "< User-mode registers to be loaded (for LDM/STM instructions)"]
972
    pub usermode: bool,
973
    #[doc = "< Scalar size for vector instructions"]
974
    pub vector_size: libc::c_int,
975
    #[doc = "< Data type for elements of vector instructions"]
976
    pub vector_data: arm_vectordata_type,
977
    #[doc = "< CPS mode for CPS instruction"]
978
    pub cps_mode: arm_cpsmode_type,
979
    #[doc = "< CPS mode for CPS instruction"]
980
    pub cps_flag: arm_cpsflag_type,
981
    #[doc = "< conditional code for this insn"]
982
    pub cc: arm_cc,
983
    #[doc = "< does this insn update flags?"]
984
    pub update_flags: bool,
985
    #[doc = "< does this insn write-back?"]
986
    pub writeback: bool,
987
    #[doc = "< Option for some memory barrier instructions"]
988
    pub mem_barrier: arm_mem_barrier,
989
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
990
    pub op_count: u8,
991
    #[doc = "< operands for this instruction."]
992
    pub operands: [cs_arm_op; 36usize],
993
}
994
impl ::core::fmt::Debug for cs_arm {
995
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
996
0
        write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, mem_barrier: {:?}, operands: [...] }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . mem_barrier)
997
0
    }
998
}
999
#[repr(u32)]
1000
#[doc = " ARM instruction"]
1001
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
1002
pub enum arm_insn {
1003
    ARM_INS_INVALID = 0,
1004
    ARM_INS_ADC = 1,
1005
    ARM_INS_ADD = 2,
1006
    ARM_INS_ADDW = 3,
1007
    ARM_INS_ADR = 4,
1008
    ARM_INS_AESD = 5,
1009
    ARM_INS_AESE = 6,
1010
    ARM_INS_AESIMC = 7,
1011
    ARM_INS_AESMC = 8,
1012
    ARM_INS_AND = 9,
1013
    ARM_INS_ASR = 10,
1014
    ARM_INS_B = 11,
1015
    ARM_INS_BFC = 12,
1016
    ARM_INS_BFI = 13,
1017
    ARM_INS_BIC = 14,
1018
    ARM_INS_BKPT = 15,
1019
    ARM_INS_BL = 16,
1020
    ARM_INS_BLX = 17,
1021
    ARM_INS_BLXNS = 18,
1022
    ARM_INS_BX = 19,
1023
    ARM_INS_BXJ = 20,
1024
    ARM_INS_BXNS = 21,
1025
    ARM_INS_CBNZ = 22,
1026
    ARM_INS_CBZ = 23,
1027
    ARM_INS_CDP = 24,
1028
    ARM_INS_CDP2 = 25,
1029
    ARM_INS_CLREX = 26,
1030
    ARM_INS_CLZ = 27,
1031
    ARM_INS_CMN = 28,
1032
    ARM_INS_CMP = 29,
1033
    ARM_INS_CPS = 30,
1034
    ARM_INS_CRC32B = 31,
1035
    ARM_INS_CRC32CB = 32,
1036
    ARM_INS_CRC32CH = 33,
1037
    ARM_INS_CRC32CW = 34,
1038
    ARM_INS_CRC32H = 35,
1039
    ARM_INS_CRC32W = 36,
1040
    ARM_INS_CSDB = 37,
1041
    ARM_INS_DBG = 38,
1042
    ARM_INS_DCPS1 = 39,
1043
    ARM_INS_DCPS2 = 40,
1044
    ARM_INS_DCPS3 = 41,
1045
    ARM_INS_DFB = 42,
1046
    ARM_INS_DMB = 43,
1047
    ARM_INS_DSB = 44,
1048
    ARM_INS_EOR = 45,
1049
    ARM_INS_ERET = 46,
1050
    ARM_INS_ESB = 47,
1051
    ARM_INS_FADDD = 48,
1052
    ARM_INS_FADDS = 49,
1053
    ARM_INS_FCMPZD = 50,
1054
    ARM_INS_FCMPZS = 51,
1055
    ARM_INS_FCONSTD = 52,
1056
    ARM_INS_FCONSTS = 53,
1057
    ARM_INS_FLDMDBX = 54,
1058
    ARM_INS_FLDMIAX = 55,
1059
    ARM_INS_FMDHR = 56,
1060
    ARM_INS_FMDLR = 57,
1061
    ARM_INS_FMSTAT = 58,
1062
    ARM_INS_FSTMDBX = 59,
1063
    ARM_INS_FSTMIAX = 60,
1064
    ARM_INS_FSUBD = 61,
1065
    ARM_INS_FSUBS = 62,
1066
    ARM_INS_HINT = 63,
1067
    ARM_INS_HLT = 64,
1068
    ARM_INS_HVC = 65,
1069
    ARM_INS_ISB = 66,
1070
    ARM_INS_IT = 67,
1071
    ARM_INS_LDA = 68,
1072
    ARM_INS_LDAB = 69,
1073
    ARM_INS_LDAEX = 70,
1074
    ARM_INS_LDAEXB = 71,
1075
    ARM_INS_LDAEXD = 72,
1076
    ARM_INS_LDAEXH = 73,
1077
    ARM_INS_LDAH = 74,
1078
    ARM_INS_LDC = 75,
1079
    ARM_INS_LDC2 = 76,
1080
    ARM_INS_LDC2L = 77,
1081
    ARM_INS_LDCL = 78,
1082
    ARM_INS_LDM = 79,
1083
    ARM_INS_LDMDA = 80,
1084
    ARM_INS_LDMDB = 81,
1085
    ARM_INS_LDMIB = 82,
1086
    ARM_INS_LDR = 83,
1087
    ARM_INS_LDRB = 84,
1088
    ARM_INS_LDRBT = 85,
1089
    ARM_INS_LDRD = 86,
1090
    ARM_INS_LDREX = 87,
1091
    ARM_INS_LDREXB = 88,
1092
    ARM_INS_LDREXD = 89,
1093
    ARM_INS_LDREXH = 90,
1094
    ARM_INS_LDRH = 91,
1095
    ARM_INS_LDRHT = 92,
1096
    ARM_INS_LDRSB = 93,
1097
    ARM_INS_LDRSBT = 94,
1098
    ARM_INS_LDRSH = 95,
1099
    ARM_INS_LDRSHT = 96,
1100
    ARM_INS_LDRT = 97,
1101
    ARM_INS_LSL = 98,
1102
    ARM_INS_LSR = 99,
1103
    ARM_INS_MCR = 100,
1104
    ARM_INS_MCR2 = 101,
1105
    ARM_INS_MCRR = 102,
1106
    ARM_INS_MCRR2 = 103,
1107
    ARM_INS_MLA = 104,
1108
    ARM_INS_MLS = 105,
1109
    ARM_INS_MOV = 106,
1110
    ARM_INS_MOVS = 107,
1111
    ARM_INS_MOVT = 108,
1112
    ARM_INS_MOVW = 109,
1113
    ARM_INS_MRC = 110,
1114
    ARM_INS_MRC2 = 111,
1115
    ARM_INS_MRRC = 112,
1116
    ARM_INS_MRRC2 = 113,
1117
    ARM_INS_MRS = 114,
1118
    ARM_INS_MSR = 115,
1119
    ARM_INS_MUL = 116,
1120
    ARM_INS_MVN = 117,
1121
    ARM_INS_NEG = 118,
1122
    ARM_INS_NOP = 119,
1123
    ARM_INS_ORN = 120,
1124
    ARM_INS_ORR = 121,
1125
    ARM_INS_PKHBT = 122,
1126
    ARM_INS_PKHTB = 123,
1127
    ARM_INS_PLD = 124,
1128
    ARM_INS_PLDW = 125,
1129
    ARM_INS_PLI = 126,
1130
    ARM_INS_POP = 127,
1131
    ARM_INS_PUSH = 128,
1132
    ARM_INS_QADD = 129,
1133
    ARM_INS_QADD16 = 130,
1134
    ARM_INS_QADD8 = 131,
1135
    ARM_INS_QASX = 132,
1136
    ARM_INS_QDADD = 133,
1137
    ARM_INS_QDSUB = 134,
1138
    ARM_INS_QSAX = 135,
1139
    ARM_INS_QSUB = 136,
1140
    ARM_INS_QSUB16 = 137,
1141
    ARM_INS_QSUB8 = 138,
1142
    ARM_INS_RBIT = 139,
1143
    ARM_INS_REV = 140,
1144
    ARM_INS_REV16 = 141,
1145
    ARM_INS_REVSH = 142,
1146
    ARM_INS_RFEDA = 143,
1147
    ARM_INS_RFEDB = 144,
1148
    ARM_INS_RFEIA = 145,
1149
    ARM_INS_RFEIB = 146,
1150
    ARM_INS_ROR = 147,
1151
    ARM_INS_RRX = 148,
1152
    ARM_INS_RSB = 149,
1153
    ARM_INS_RSC = 150,
1154
    ARM_INS_SADD16 = 151,
1155
    ARM_INS_SADD8 = 152,
1156
    ARM_INS_SASX = 153,
1157
    ARM_INS_SBC = 154,
1158
    ARM_INS_SBFX = 155,
1159
    ARM_INS_SDIV = 156,
1160
    ARM_INS_SEL = 157,
1161
    ARM_INS_SETEND = 158,
1162
    ARM_INS_SETPAN = 159,
1163
    ARM_INS_SEV = 160,
1164
    ARM_INS_SEVL = 161,
1165
    ARM_INS_SG = 162,
1166
    ARM_INS_SHA1C = 163,
1167
    ARM_INS_SHA1H = 164,
1168
    ARM_INS_SHA1M = 165,
1169
    ARM_INS_SHA1P = 166,
1170
    ARM_INS_SHA1SU0 = 167,
1171
    ARM_INS_SHA1SU1 = 168,
1172
    ARM_INS_SHA256H = 169,
1173
    ARM_INS_SHA256H2 = 170,
1174
    ARM_INS_SHA256SU0 = 171,
1175
    ARM_INS_SHA256SU1 = 172,
1176
    ARM_INS_SHADD16 = 173,
1177
    ARM_INS_SHADD8 = 174,
1178
    ARM_INS_SHASX = 175,
1179
    ARM_INS_SHSAX = 176,
1180
    ARM_INS_SHSUB16 = 177,
1181
    ARM_INS_SHSUB8 = 178,
1182
    ARM_INS_SMC = 179,
1183
    ARM_INS_SMLABB = 180,
1184
    ARM_INS_SMLABT = 181,
1185
    ARM_INS_SMLAD = 182,
1186
    ARM_INS_SMLADX = 183,
1187
    ARM_INS_SMLAL = 184,
1188
    ARM_INS_SMLALBB = 185,
1189
    ARM_INS_SMLALBT = 186,
1190
    ARM_INS_SMLALD = 187,
1191
    ARM_INS_SMLALDX = 188,
1192
    ARM_INS_SMLALTB = 189,
1193
    ARM_INS_SMLALTT = 190,
1194
    ARM_INS_SMLATB = 191,
1195
    ARM_INS_SMLATT = 192,
1196
    ARM_INS_SMLAWB = 193,
1197
    ARM_INS_SMLAWT = 194,
1198
    ARM_INS_SMLSD = 195,
1199
    ARM_INS_SMLSDX = 196,
1200
    ARM_INS_SMLSLD = 197,
1201
    ARM_INS_SMLSLDX = 198,
1202
    ARM_INS_SMMLA = 199,
1203
    ARM_INS_SMMLAR = 200,
1204
    ARM_INS_SMMLS = 201,
1205
    ARM_INS_SMMLSR = 202,
1206
    ARM_INS_SMMUL = 203,
1207
    ARM_INS_SMMULR = 204,
1208
    ARM_INS_SMUAD = 205,
1209
    ARM_INS_SMUADX = 206,
1210
    ARM_INS_SMULBB = 207,
1211
    ARM_INS_SMULBT = 208,
1212
    ARM_INS_SMULL = 209,
1213
    ARM_INS_SMULTB = 210,
1214
    ARM_INS_SMULTT = 211,
1215
    ARM_INS_SMULWB = 212,
1216
    ARM_INS_SMULWT = 213,
1217
    ARM_INS_SMUSD = 214,
1218
    ARM_INS_SMUSDX = 215,
1219
    ARM_INS_SRSDA = 216,
1220
    ARM_INS_SRSDB = 217,
1221
    ARM_INS_SRSIA = 218,
1222
    ARM_INS_SRSIB = 219,
1223
    ARM_INS_SSAT = 220,
1224
    ARM_INS_SSAT16 = 221,
1225
    ARM_INS_SSAX = 222,
1226
    ARM_INS_SSUB16 = 223,
1227
    ARM_INS_SSUB8 = 224,
1228
    ARM_INS_STC = 225,
1229
    ARM_INS_STC2 = 226,
1230
    ARM_INS_STC2L = 227,
1231
    ARM_INS_STCL = 228,
1232
    ARM_INS_STL = 229,
1233
    ARM_INS_STLB = 230,
1234
    ARM_INS_STLEX = 231,
1235
    ARM_INS_STLEXB = 232,
1236
    ARM_INS_STLEXD = 233,
1237
    ARM_INS_STLEXH = 234,
1238
    ARM_INS_STLH = 235,
1239
    ARM_INS_STM = 236,
1240
    ARM_INS_STMDA = 237,
1241
    ARM_INS_STMDB = 238,
1242
    ARM_INS_STMIB = 239,
1243
    ARM_INS_STR = 240,
1244
    ARM_INS_STRB = 241,
1245
    ARM_INS_STRBT = 242,
1246
    ARM_INS_STRD = 243,
1247
    ARM_INS_STREX = 244,
1248
    ARM_INS_STREXB = 245,
1249
    ARM_INS_STREXD = 246,
1250
    ARM_INS_STREXH = 247,
1251
    ARM_INS_STRH = 248,
1252
    ARM_INS_STRHT = 249,
1253
    ARM_INS_STRT = 250,
1254
    ARM_INS_SUB = 251,
1255
    ARM_INS_SUBS = 252,
1256
    ARM_INS_SUBW = 253,
1257
    ARM_INS_SVC = 254,
1258
    ARM_INS_SWP = 255,
1259
    ARM_INS_SWPB = 256,
1260
    ARM_INS_SXTAB = 257,
1261
    ARM_INS_SXTAB16 = 258,
1262
    ARM_INS_SXTAH = 259,
1263
    ARM_INS_SXTB = 260,
1264
    ARM_INS_SXTB16 = 261,
1265
    ARM_INS_SXTH = 262,
1266
    ARM_INS_TBB = 263,
1267
    ARM_INS_TBH = 264,
1268
    ARM_INS_TEQ = 265,
1269
    ARM_INS_TRAP = 266,
1270
    ARM_INS_TSB = 267,
1271
    ARM_INS_TST = 268,
1272
    ARM_INS_TT = 269,
1273
    ARM_INS_TTA = 270,
1274
    ARM_INS_TTAT = 271,
1275
    ARM_INS_TTT = 272,
1276
    ARM_INS_UADD16 = 273,
1277
    ARM_INS_UADD8 = 274,
1278
    ARM_INS_UASX = 275,
1279
    ARM_INS_UBFX = 276,
1280
    ARM_INS_UDF = 277,
1281
    ARM_INS_UDIV = 278,
1282
    ARM_INS_UHADD16 = 279,
1283
    ARM_INS_UHADD8 = 280,
1284
    ARM_INS_UHASX = 281,
1285
    ARM_INS_UHSAX = 282,
1286
    ARM_INS_UHSUB16 = 283,
1287
    ARM_INS_UHSUB8 = 284,
1288
    ARM_INS_UMAAL = 285,
1289
    ARM_INS_UMLAL = 286,
1290
    ARM_INS_UMULL = 287,
1291
    ARM_INS_UQADD16 = 288,
1292
    ARM_INS_UQADD8 = 289,
1293
    ARM_INS_UQASX = 290,
1294
    ARM_INS_UQSAX = 291,
1295
    ARM_INS_UQSUB16 = 292,
1296
    ARM_INS_UQSUB8 = 293,
1297
    ARM_INS_USAD8 = 294,
1298
    ARM_INS_USADA8 = 295,
1299
    ARM_INS_USAT = 296,
1300
    ARM_INS_USAT16 = 297,
1301
    ARM_INS_USAX = 298,
1302
    ARM_INS_USUB16 = 299,
1303
    ARM_INS_USUB8 = 300,
1304
    ARM_INS_UXTAB = 301,
1305
    ARM_INS_UXTAB16 = 302,
1306
    ARM_INS_UXTAH = 303,
1307
    ARM_INS_UXTB = 304,
1308
    ARM_INS_UXTB16 = 305,
1309
    ARM_INS_UXTH = 306,
1310
    ARM_INS_VABA = 307,
1311
    ARM_INS_VABAL = 308,
1312
    ARM_INS_VABD = 309,
1313
    ARM_INS_VABDL = 310,
1314
    ARM_INS_VABS = 311,
1315
    ARM_INS_VACGE = 312,
1316
    ARM_INS_VACGT = 313,
1317
    ARM_INS_VACLE = 314,
1318
    ARM_INS_VACLT = 315,
1319
    ARM_INS_VADD = 316,
1320
    ARM_INS_VADDHN = 317,
1321
    ARM_INS_VADDL = 318,
1322
    ARM_INS_VADDW = 319,
1323
    ARM_INS_VAND = 320,
1324
    ARM_INS_VBIC = 321,
1325
    ARM_INS_VBIF = 322,
1326
    ARM_INS_VBIT = 323,
1327
    ARM_INS_VBSL = 324,
1328
    ARM_INS_VCADD = 325,
1329
    ARM_INS_VCEQ = 326,
1330
    ARM_INS_VCGE = 327,
1331
    ARM_INS_VCGT = 328,
1332
    ARM_INS_VCLE = 329,
1333
    ARM_INS_VCLS = 330,
1334
    ARM_INS_VCLT = 331,
1335
    ARM_INS_VCLZ = 332,
1336
    ARM_INS_VCMLA = 333,
1337
    ARM_INS_VCMP = 334,
1338
    ARM_INS_VCMPE = 335,
1339
    ARM_INS_VCNT = 336,
1340
    ARM_INS_VCVT = 337,
1341
    ARM_INS_VCVTA = 338,
1342
    ARM_INS_VCVTB = 339,
1343
    ARM_INS_VCVTM = 340,
1344
    ARM_INS_VCVTN = 341,
1345
    ARM_INS_VCVTP = 342,
1346
    ARM_INS_VCVTR = 343,
1347
    ARM_INS_VCVTT = 344,
1348
    ARM_INS_VDIV = 345,
1349
    ARM_INS_VDUP = 346,
1350
    ARM_INS_VEOR = 347,
1351
    ARM_INS_VEXT = 348,
1352
    ARM_INS_VFMA = 349,
1353
    ARM_INS_VFMS = 350,
1354
    ARM_INS_VFNMA = 351,
1355
    ARM_INS_VFNMS = 352,
1356
    ARM_INS_VHADD = 353,
1357
    ARM_INS_VHSUB = 354,
1358
    ARM_INS_VINS = 355,
1359
    ARM_INS_VJCVT = 356,
1360
    ARM_INS_VLD1 = 357,
1361
    ARM_INS_VLD2 = 358,
1362
    ARM_INS_VLD3 = 359,
1363
    ARM_INS_VLD4 = 360,
1364
    ARM_INS_VLDMDB = 361,
1365
    ARM_INS_VLDMIA = 362,
1366
    ARM_INS_VLDR = 363,
1367
    ARM_INS_VLLDM = 364,
1368
    ARM_INS_VLSTM = 365,
1369
    ARM_INS_VMAX = 366,
1370
    ARM_INS_VMAXNM = 367,
1371
    ARM_INS_VMIN = 368,
1372
    ARM_INS_VMINNM = 369,
1373
    ARM_INS_VMLA = 370,
1374
    ARM_INS_VMLAL = 371,
1375
    ARM_INS_VMLS = 372,
1376
    ARM_INS_VMLSL = 373,
1377
    ARM_INS_VMOV = 374,
1378
    ARM_INS_VMOVL = 375,
1379
    ARM_INS_VMOVN = 376,
1380
    ARM_INS_VMOVX = 377,
1381
    ARM_INS_VMRS = 378,
1382
    ARM_INS_VMSR = 379,
1383
    ARM_INS_VMUL = 380,
1384
    ARM_INS_VMULL = 381,
1385
    ARM_INS_VMVN = 382,
1386
    ARM_INS_VNEG = 383,
1387
    ARM_INS_VNMLA = 384,
1388
    ARM_INS_VNMLS = 385,
1389
    ARM_INS_VNMUL = 386,
1390
    ARM_INS_VORN = 387,
1391
    ARM_INS_VORR = 388,
1392
    ARM_INS_VPADAL = 389,
1393
    ARM_INS_VPADD = 390,
1394
    ARM_INS_VPADDL = 391,
1395
    ARM_INS_VPMAX = 392,
1396
    ARM_INS_VPMIN = 393,
1397
    ARM_INS_VPOP = 394,
1398
    ARM_INS_VPUSH = 395,
1399
    ARM_INS_VQABS = 396,
1400
    ARM_INS_VQADD = 397,
1401
    ARM_INS_VQDMLAL = 398,
1402
    ARM_INS_VQDMLSL = 399,
1403
    ARM_INS_VQDMULH = 400,
1404
    ARM_INS_VQDMULL = 401,
1405
    ARM_INS_VQMOVN = 402,
1406
    ARM_INS_VQMOVUN = 403,
1407
    ARM_INS_VQNEG = 404,
1408
    ARM_INS_VQRDMLAH = 405,
1409
    ARM_INS_VQRDMLSH = 406,
1410
    ARM_INS_VQRDMULH = 407,
1411
    ARM_INS_VQRSHL = 408,
1412
    ARM_INS_VQRSHRN = 409,
1413
    ARM_INS_VQRSHRUN = 410,
1414
    ARM_INS_VQSHL = 411,
1415
    ARM_INS_VQSHLU = 412,
1416
    ARM_INS_VQSHRN = 413,
1417
    ARM_INS_VQSHRUN = 414,
1418
    ARM_INS_VQSUB = 415,
1419
    ARM_INS_VRADDHN = 416,
1420
    ARM_INS_VRECPE = 417,
1421
    ARM_INS_VRECPS = 418,
1422
    ARM_INS_VREV16 = 419,
1423
    ARM_INS_VREV32 = 420,
1424
    ARM_INS_VREV64 = 421,
1425
    ARM_INS_VRHADD = 422,
1426
    ARM_INS_VRINTA = 423,
1427
    ARM_INS_VRINTM = 424,
1428
    ARM_INS_VRINTN = 425,
1429
    ARM_INS_VRINTP = 426,
1430
    ARM_INS_VRINTR = 427,
1431
    ARM_INS_VRINTX = 428,
1432
    ARM_INS_VRINTZ = 429,
1433
    ARM_INS_VRSHL = 430,
1434
    ARM_INS_VRSHR = 431,
1435
    ARM_INS_VRSHRN = 432,
1436
    ARM_INS_VRSQRTE = 433,
1437
    ARM_INS_VRSQRTS = 434,
1438
    ARM_INS_VRSRA = 435,
1439
    ARM_INS_VRSUBHN = 436,
1440
    ARM_INS_VSDOT = 437,
1441
    ARM_INS_VSELEQ = 438,
1442
    ARM_INS_VSELGE = 439,
1443
    ARM_INS_VSELGT = 440,
1444
    ARM_INS_VSELVS = 441,
1445
    ARM_INS_VSHL = 442,
1446
    ARM_INS_VSHLL = 443,
1447
    ARM_INS_VSHR = 444,
1448
    ARM_INS_VSHRN = 445,
1449
    ARM_INS_VSLI = 446,
1450
    ARM_INS_VSQRT = 447,
1451
    ARM_INS_VSRA = 448,
1452
    ARM_INS_VSRI = 449,
1453
    ARM_INS_VST1 = 450,
1454
    ARM_INS_VST2 = 451,
1455
    ARM_INS_VST3 = 452,
1456
    ARM_INS_VST4 = 453,
1457
    ARM_INS_VSTMDB = 454,
1458
    ARM_INS_VSTMIA = 455,
1459
    ARM_INS_VSTR = 456,
1460
    ARM_INS_VSUB = 457,
1461
    ARM_INS_VSUBHN = 458,
1462
    ARM_INS_VSUBL = 459,
1463
    ARM_INS_VSUBW = 460,
1464
    ARM_INS_VSWP = 461,
1465
    ARM_INS_VTBL = 462,
1466
    ARM_INS_VTBX = 463,
1467
    ARM_INS_VTRN = 464,
1468
    ARM_INS_VTST = 465,
1469
    ARM_INS_VUDOT = 466,
1470
    ARM_INS_VUZP = 467,
1471
    ARM_INS_VZIP = 468,
1472
    ARM_INS_WFE = 469,
1473
    ARM_INS_WFI = 470,
1474
    ARM_INS_YIELD = 471,
1475
    ARM_INS_ENDING = 472,
1476
}
1477
pub mod arm_insn_group {
1478
    #[doc = " Group of ARM instructions"]
1479
    pub type Type = libc::c_uint;
1480
    #[doc = "< = CS_GRP_INVALID"]
1481
    pub const ARM_GRP_INVALID: Type = 0;
1482
    #[doc = "< = CS_GRP_JUMP"]
1483
    pub const ARM_GRP_JUMP: Type = 1;
1484
    #[doc = "< = CS_GRP_CALL"]
1485
    pub const ARM_GRP_CALL: Type = 2;
1486
    #[doc = "< = CS_GRP_INT"]
1487
    pub const ARM_GRP_INT: Type = 4;
1488
    #[doc = "< = CS_GRP_PRIVILEGE"]
1489
    pub const ARM_GRP_PRIVILEGE: Type = 6;
1490
    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
1491
    pub const ARM_GRP_BRANCH_RELATIVE: Type = 7;
1492
    pub const ARM_GRP_CRYPTO: Type = 128;
1493
    pub const ARM_GRP_DATABARRIER: Type = 129;
1494
    pub const ARM_GRP_DIVIDE: Type = 130;
1495
    pub const ARM_GRP_FPARMV8: Type = 131;
1496
    pub const ARM_GRP_MULTPRO: Type = 132;
1497
    pub const ARM_GRP_NEON: Type = 133;
1498
    pub const ARM_GRP_T2EXTRACTPACK: Type = 134;
1499
    pub const ARM_GRP_THUMB2DSP: Type = 135;
1500
    pub const ARM_GRP_TRUSTZONE: Type = 136;
1501
    pub const ARM_GRP_V4T: Type = 137;
1502
    pub const ARM_GRP_V5T: Type = 138;
1503
    pub const ARM_GRP_V5TE: Type = 139;
1504
    pub const ARM_GRP_V6: Type = 140;
1505
    pub const ARM_GRP_V6T2: Type = 141;
1506
    pub const ARM_GRP_V7: Type = 142;
1507
    pub const ARM_GRP_V8: Type = 143;
1508
    pub const ARM_GRP_VFP2: Type = 144;
1509
    pub const ARM_GRP_VFP3: Type = 145;
1510
    pub const ARM_GRP_VFP4: Type = 146;
1511
    pub const ARM_GRP_ARM: Type = 147;
1512
    pub const ARM_GRP_MCLASS: Type = 148;
1513
    pub const ARM_GRP_NOTMCLASS: Type = 149;
1514
    pub const ARM_GRP_THUMB: Type = 150;
1515
    pub const ARM_GRP_THUMB1ONLY: Type = 151;
1516
    pub const ARM_GRP_THUMB2: Type = 152;
1517
    pub const ARM_GRP_PREV8: Type = 153;
1518
    pub const ARM_GRP_FPVMLX: Type = 154;
1519
    pub const ARM_GRP_MULOPS: Type = 155;
1520
    pub const ARM_GRP_CRC: Type = 156;
1521
    pub const ARM_GRP_DPVFP: Type = 157;
1522
    pub const ARM_GRP_V6M: Type = 158;
1523
    pub const ARM_GRP_VIRTUALIZATION: Type = 159;
1524
    pub const ARM_GRP_ENDING: Type = 160;
1525
}
1526
#[repr(u32)]
1527
#[doc = " ARM64 shift type"]
1528
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
1529
pub enum arm64_shifter {
1530
    ARM64_SFT_INVALID = 0,
1531
    ARM64_SFT_LSL = 1,
1532
    ARM64_SFT_MSL = 2,
1533
    ARM64_SFT_LSR = 3,
1534
    ARM64_SFT_ASR = 4,
1535
    ARM64_SFT_ROR = 5,
1536
}
1537
#[repr(u32)]
1538
#[doc = " ARM64 extender type"]
1539
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
1540
pub enum arm64_extender {
1541
    ARM64_EXT_INVALID = 0,
1542
    ARM64_EXT_UXTB = 1,
1543
    ARM64_EXT_UXTH = 2,
1544
    ARM64_EXT_UXTW = 3,
1545
    ARM64_EXT_UXTX = 4,
1546
    ARM64_EXT_SXTB = 5,
1547
    ARM64_EXT_SXTH = 6,
1548
    ARM64_EXT_SXTW = 7,
1549
    ARM64_EXT_SXTX = 8,
1550
}
1551
#[repr(u32)]
1552
#[doc = " ARM64 condition code"]
1553
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
1554
pub enum arm64_cc {
1555
    ARM64_CC_INVALID = 0,
1556
    #[doc = "< Equal"]
1557
    ARM64_CC_EQ = 1,
1558
    #[doc = "< Not equal:                 Not equal, or unordered"]
1559
    ARM64_CC_NE = 2,
1560
    #[doc = "< Unsigned higher or same:   >, ==, or unordered"]
1561
    ARM64_CC_HS = 3,
1562
    #[doc = "< Unsigned lower or same:    Less than"]
1563
    ARM64_CC_LO = 4,
1564
    #[doc = "< Minus, negative:           Less than"]
1565
    ARM64_CC_MI = 5,
1566
    #[doc = "< Plus, positive or zero:    >, ==, or unordered"]
1567
    ARM64_CC_PL = 6,
1568
    #[doc = "< Overflow:                  Unordered"]
1569
    ARM64_CC_VS = 7,
1570
    #[doc = "< No overflow:               Ordered"]
1571
    ARM64_CC_VC = 8,
1572
    #[doc = "< Unsigned higher:           Greater than, or unordered"]
1573
    ARM64_CC_HI = 9,
1574
    #[doc = "< Unsigned lower or same:    Less than or equal"]
1575
    ARM64_CC_LS = 10,
1576
    #[doc = "< Greater than or equal:     Greater than or equal"]
1577
    ARM64_CC_GE = 11,
1578
    #[doc = "< Less than:                 Less than, or unordered"]
1579
    ARM64_CC_LT = 12,
1580
    #[doc = "< Signed greater than:       Greater than"]
1581
    ARM64_CC_GT = 13,
1582
    #[doc = "< Signed less than or equal: <, ==, or unordered"]
1583
    ARM64_CC_LE = 14,
1584
    #[doc = "< Always (unconditional):    Always (unconditional)"]
1585
    ARM64_CC_AL = 15,
1586
    #[doc = "< Always (unconditional):   Always (unconditional)"]
1587
    ARM64_CC_NV = 16,
1588
}
1589
impl arm64_sysreg {
1590
    pub const ARM64_SYSREG_DBGDTRTX_EL0: arm64_sysreg = arm64_sysreg::ARM64_SYSREG_DBGDTRRX_EL0;
1591
}
1592
#[repr(u32)]
1593
#[doc = " System registers"]
1594
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
1595
pub enum arm64_sysreg {
1596
    ARM64_SYSREG_INVALID = 0,
1597
    ARM64_SYSREG_MDCCSR_EL0 = 38920,
1598
    ARM64_SYSREG_DBGDTRRX_EL0 = 38952,
1599
    ARM64_SYSREG_MDRAR_EL1 = 32896,
1600
    ARM64_SYSREG_OSLSR_EL1 = 32908,
1601
    ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782,
1602
    ARM64_SYSREG_PMCEID0_EL0 = 56550,
1603
    ARM64_SYSREG_PMCEID1_EL0 = 56551,
1604
    ARM64_SYSREG_MIDR_EL1 = 49152,
1605
    ARM64_SYSREG_CCSIDR_EL1 = 51200,
1606
    ARM64_SYSREG_CCSIDR2_EL1 = 51202,
1607
    ARM64_SYSREG_CLIDR_EL1 = 51201,
1608
    ARM64_SYSREG_CTR_EL0 = 55297,
1609
    ARM64_SYSREG_MPIDR_EL1 = 49157,
1610
    ARM64_SYSREG_REVIDR_EL1 = 49158,
1611
    ARM64_SYSREG_AIDR_EL1 = 51207,
1612
    ARM64_SYSREG_DCZID_EL0 = 55303,
1613
    ARM64_SYSREG_ID_PFR0_EL1 = 49160,
1614
    ARM64_SYSREG_ID_PFR1_EL1 = 49161,
1615
    ARM64_SYSREG_ID_DFR0_EL1 = 49162,
1616
    ARM64_SYSREG_ID_AFR0_EL1 = 49163,
1617
    ARM64_SYSREG_ID_MMFR0_EL1 = 49164,
1618
    ARM64_SYSREG_ID_MMFR1_EL1 = 49165,
1619
    ARM64_SYSREG_ID_MMFR2_EL1 = 49166,
1620
    ARM64_SYSREG_ID_MMFR3_EL1 = 49167,
1621
    ARM64_SYSREG_ID_ISAR0_EL1 = 49168,
1622
    ARM64_SYSREG_ID_ISAR1_EL1 = 49169,
1623
    ARM64_SYSREG_ID_ISAR2_EL1 = 49170,
1624
    ARM64_SYSREG_ID_ISAR3_EL1 = 49171,
1625
    ARM64_SYSREG_ID_ISAR4_EL1 = 49172,
1626
    ARM64_SYSREG_ID_ISAR5_EL1 = 49173,
1627
    ARM64_SYSREG_ID_ISAR6_EL1 = 49175,
1628
    ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184,
1629
    ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185,
1630
    ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192,
1631
    ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193,
1632
    ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196,
1633
    ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197,
1634
    ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200,
1635
    ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201,
1636
    ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208,
1637
    ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209,
1638
    ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210,
1639
    ARM64_SYSREG_MVFR0_EL1 = 49176,
1640
    ARM64_SYSREG_MVFR1_EL1 = 49177,
1641
    ARM64_SYSREG_MVFR2_EL1 = 49178,
1642
    ARM64_SYSREG_RVBAR_EL1 = 50689,
1643
    ARM64_SYSREG_RVBAR_EL2 = 58881,
1644
    ARM64_SYSREG_RVBAR_EL3 = 62977,
1645
    ARM64_SYSREG_ISR_EL1 = 50696,
1646
    ARM64_SYSREG_CNTPCT_EL0 = 57089,
1647
    ARM64_SYSREG_CNTVCT_EL0 = 57090,
1648
    ARM64_SYSREG_ID_MMFR4_EL1 = 49174,
1649
    ARM64_SYSREG_TRCSTATR = 34840,
1650
    ARM64_SYSREG_TRCIDR8 = 34822,
1651
    ARM64_SYSREG_TRCIDR9 = 34830,
1652
    ARM64_SYSREG_TRCIDR10 = 34838,
1653
    ARM64_SYSREG_TRCIDR11 = 34846,
1654
    ARM64_SYSREG_TRCIDR12 = 34854,
1655
    ARM64_SYSREG_TRCIDR13 = 34862,
1656
    ARM64_SYSREG_TRCIDR0 = 34887,
1657
    ARM64_SYSREG_TRCIDR1 = 34895,
1658
    ARM64_SYSREG_TRCIDR2 = 34903,
1659
    ARM64_SYSREG_TRCIDR3 = 34911,
1660
    ARM64_SYSREG_TRCIDR4 = 34919,
1661
    ARM64_SYSREG_TRCIDR5 = 34927,
1662
    ARM64_SYSREG_TRCIDR6 = 34935,
1663
    ARM64_SYSREG_TRCIDR7 = 34943,
1664
    ARM64_SYSREG_TRCOSLSR = 34956,
1665
    ARM64_SYSREG_TRCPDSR = 34988,
1666
    ARM64_SYSREG_TRCDEVAFF0 = 35798,
1667
    ARM64_SYSREG_TRCDEVAFF1 = 35806,
1668
    ARM64_SYSREG_TRCLSR = 35822,
1669
    ARM64_SYSREG_TRCAUTHSTATUS = 35830,
1670
    ARM64_SYSREG_TRCDEVARCH = 35838,
1671
    ARM64_SYSREG_TRCDEVID = 35735,
1672
    ARM64_SYSREG_TRCDEVTYPE = 35743,
1673
    ARM64_SYSREG_TRCPIDR4 = 35751,
1674
    ARM64_SYSREG_TRCPIDR5 = 35759,
1675
    ARM64_SYSREG_TRCPIDR6 = 35767,
1676
    ARM64_SYSREG_TRCPIDR7 = 35775,
1677
    ARM64_SYSREG_TRCPIDR0 = 35783,
1678
    ARM64_SYSREG_TRCPIDR1 = 35791,
1679
    ARM64_SYSREG_TRCPIDR2 = 35799,
1680
    ARM64_SYSREG_TRCPIDR3 = 35807,
1681
    ARM64_SYSREG_TRCCIDR0 = 35815,
1682
    ARM64_SYSREG_TRCCIDR1 = 35823,
1683
    ARM64_SYSREG_TRCCIDR2 = 35831,
1684
    ARM64_SYSREG_TRCCIDR3 = 35839,
1685
    ARM64_SYSREG_ICC_IAR1_EL1 = 50784,
1686
    ARM64_SYSREG_ICC_IAR0_EL1 = 50752,
1687
    ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786,
1688
    ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754,
1689
    ARM64_SYSREG_ICC_RPR_EL1 = 50779,
1690
    ARM64_SYSREG_ICH_VTR_EL2 = 58969,
1691
    ARM64_SYSREG_ICH_EISR_EL2 = 58971,
1692
    ARM64_SYSREG_ICH_ELRSR_EL2 = 58973,
1693
    ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188,
1694
    ARM64_SYSREG_LORID_EL1 = 50471,
1695
    ARM64_SYSREG_ERRIDR_EL1 = 49816,
1696
    ARM64_SYSREG_ERXFR_EL1 = 49824,
1697
    ARM64_SYSREG_OSLAR_EL1 = 32900,
1698
    ARM64_SYSREG_PMSWINC_EL0 = 56548,
1699
    ARM64_SYSREG_TRCOSLAR = 34948,
1700
    ARM64_SYSREG_TRCLAR = 35814,
1701
    ARM64_SYSREG_ICC_EOIR1_EL1 = 50785,
1702
    ARM64_SYSREG_ICC_EOIR0_EL1 = 50753,
1703
    ARM64_SYSREG_ICC_DIR_EL1 = 50777,
1704
    ARM64_SYSREG_ICC_SGI1R_EL1 = 50781,
1705
    ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782,
1706
    ARM64_SYSREG_ICC_SGI0R_EL1 = 50783,
1707
    ARM64_SYSREG_OSDTRRX_EL1 = 32770,
1708
    ARM64_SYSREG_OSDTRTX_EL1 = 32794,
1709
    ARM64_SYSREG_TEECR32_EL1 = 36864,
1710
    ARM64_SYSREG_MDCCINT_EL1 = 32784,
1711
    ARM64_SYSREG_MDSCR_EL1 = 32786,
1712
    ARM64_SYSREG_DBGDTR_EL0 = 38944,
1713
    ARM64_SYSREG_OSECCR_EL1 = 32818,
1714
    ARM64_SYSREG_DBGVCR32_EL2 = 41016,
1715
    ARM64_SYSREG_DBGBVR0_EL1 = 32772,
1716
    ARM64_SYSREG_DBGBVR1_EL1 = 32780,
1717
    ARM64_SYSREG_DBGBVR2_EL1 = 32788,
1718
    ARM64_SYSREG_DBGBVR3_EL1 = 32796,
1719
    ARM64_SYSREG_DBGBVR4_EL1 = 32804,
1720
    ARM64_SYSREG_DBGBVR5_EL1 = 32812,
1721
    ARM64_SYSREG_DBGBVR6_EL1 = 32820,
1722
    ARM64_SYSREG_DBGBVR7_EL1 = 32828,
1723
    ARM64_SYSREG_DBGBVR8_EL1 = 32836,
1724
    ARM64_SYSREG_DBGBVR9_EL1 = 32844,
1725
    ARM64_SYSREG_DBGBVR10_EL1 = 32852,
1726
    ARM64_SYSREG_DBGBVR11_EL1 = 32860,
1727
    ARM64_SYSREG_DBGBVR12_EL1 = 32868,
1728
    ARM64_SYSREG_DBGBVR13_EL1 = 32876,
1729
    ARM64_SYSREG_DBGBVR14_EL1 = 32884,
1730
    ARM64_SYSREG_DBGBVR15_EL1 = 32892,
1731
    ARM64_SYSREG_DBGBCR0_EL1 = 32773,
1732
    ARM64_SYSREG_DBGBCR1_EL1 = 32781,
1733
    ARM64_SYSREG_DBGBCR2_EL1 = 32789,
1734
    ARM64_SYSREG_DBGBCR3_EL1 = 32797,
1735
    ARM64_SYSREG_DBGBCR4_EL1 = 32805,
1736
    ARM64_SYSREG_DBGBCR5_EL1 = 32813,
1737
    ARM64_SYSREG_DBGBCR6_EL1 = 32821,
1738
    ARM64_SYSREG_DBGBCR7_EL1 = 32829,
1739
    ARM64_SYSREG_DBGBCR8_EL1 = 32837,
1740
    ARM64_SYSREG_DBGBCR9_EL1 = 32845,
1741
    ARM64_SYSREG_DBGBCR10_EL1 = 32853,
1742
    ARM64_SYSREG_DBGBCR11_EL1 = 32861,
1743
    ARM64_SYSREG_DBGBCR12_EL1 = 32869,
1744
    ARM64_SYSREG_DBGBCR13_EL1 = 32877,
1745
    ARM64_SYSREG_DBGBCR14_EL1 = 32885,
1746
    ARM64_SYSREG_DBGBCR15_EL1 = 32893,
1747
    ARM64_SYSREG_DBGWVR0_EL1 = 32774,
1748
    ARM64_SYSREG_DBGWVR1_EL1 = 32782,
1749
    ARM64_SYSREG_DBGWVR2_EL1 = 32790,
1750
    ARM64_SYSREG_DBGWVR3_EL1 = 32798,
1751
    ARM64_SYSREG_DBGWVR4_EL1 = 32806,
1752
    ARM64_SYSREG_DBGWVR5_EL1 = 32814,
1753
    ARM64_SYSREG_DBGWVR6_EL1 = 32822,
1754
    ARM64_SYSREG_DBGWVR7_EL1 = 32830,
1755
    ARM64_SYSREG_DBGWVR8_EL1 = 32838,
1756
    ARM64_SYSREG_DBGWVR9_EL1 = 32846,
1757
    ARM64_SYSREG_DBGWVR10_EL1 = 32854,
1758
    ARM64_SYSREG_DBGWVR11_EL1 = 32862,
1759
    ARM64_SYSREG_DBGWVR12_EL1 = 32870,
1760
    ARM64_SYSREG_DBGWVR13_EL1 = 32878,
1761
    ARM64_SYSREG_DBGWVR14_EL1 = 32886,
1762
    ARM64_SYSREG_DBGWVR15_EL1 = 32894,
1763
    ARM64_SYSREG_DBGWCR0_EL1 = 32775,
1764
    ARM64_SYSREG_DBGWCR1_EL1 = 32783,
1765
    ARM64_SYSREG_DBGWCR2_EL1 = 32791,
1766
    ARM64_SYSREG_DBGWCR3_EL1 = 32799,
1767
    ARM64_SYSREG_DBGWCR4_EL1 = 32807,
1768
    ARM64_SYSREG_DBGWCR5_EL1 = 32815,
1769
    ARM64_SYSREG_DBGWCR6_EL1 = 32823,
1770
    ARM64_SYSREG_DBGWCR7_EL1 = 32831,
1771
    ARM64_SYSREG_DBGWCR8_EL1 = 32839,
1772
    ARM64_SYSREG_DBGWCR9_EL1 = 32847,
1773
    ARM64_SYSREG_DBGWCR10_EL1 = 32855,
1774
    ARM64_SYSREG_DBGWCR11_EL1 = 32863,
1775
    ARM64_SYSREG_DBGWCR12_EL1 = 32871,
1776
    ARM64_SYSREG_DBGWCR13_EL1 = 32879,
1777
    ARM64_SYSREG_DBGWCR14_EL1 = 32887,
1778
    ARM64_SYSREG_DBGWCR15_EL1 = 32895,
1779
    ARM64_SYSREG_TEEHBR32_EL1 = 36992,
1780
    ARM64_SYSREG_OSDLR_EL1 = 32924,
1781
    ARM64_SYSREG_DBGPRCR_EL1 = 32932,
1782
    ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734,
1783
    ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742,
1784
    ARM64_SYSREG_CSSELR_EL1 = 53248,
1785
    ARM64_SYSREG_VPIDR_EL2 = 57344,
1786
    ARM64_SYSREG_VMPIDR_EL2 = 57349,
1787
    ARM64_SYSREG_CPACR_EL1 = 49282,
1788
    ARM64_SYSREG_SCTLR_EL1 = 49280,
1789
    ARM64_SYSREG_SCTLR_EL2 = 57472,
1790
    ARM64_SYSREG_SCTLR_EL3 = 61568,
1791
    ARM64_SYSREG_ACTLR_EL1 = 49281,
1792
    ARM64_SYSREG_ACTLR_EL2 = 57473,
1793
    ARM64_SYSREG_ACTLR_EL3 = 61569,
1794
    ARM64_SYSREG_HCR_EL2 = 57480,
1795
    ARM64_SYSREG_SCR_EL3 = 61576,
1796
    ARM64_SYSREG_MDCR_EL2 = 57481,
1797
    ARM64_SYSREG_SDER32_EL3 = 61577,
1798
    ARM64_SYSREG_CPTR_EL2 = 57482,
1799
    ARM64_SYSREG_CPTR_EL3 = 61578,
1800
    ARM64_SYSREG_HSTR_EL2 = 57483,
1801
    ARM64_SYSREG_HACR_EL2 = 57487,
1802
    ARM64_SYSREG_MDCR_EL3 = 61593,
1803
    ARM64_SYSREG_TTBR0_EL1 = 49408,
1804
    ARM64_SYSREG_TTBR0_EL2 = 57600,
1805
    ARM64_SYSREG_TTBR0_EL3 = 61696,
1806
    ARM64_SYSREG_TTBR1_EL1 = 49409,
1807
    ARM64_SYSREG_TCR_EL1 = 49410,
1808
    ARM64_SYSREG_TCR_EL2 = 57602,
1809
    ARM64_SYSREG_TCR_EL3 = 61698,
1810
    ARM64_SYSREG_VTTBR_EL2 = 57608,
1811
    ARM64_SYSREG_VTCR_EL2 = 57610,
1812
    ARM64_SYSREG_DACR32_EL2 = 57728,
1813
    ARM64_SYSREG_SPSR_EL1 = 49664,
1814
    ARM64_SYSREG_SPSR_EL2 = 57856,
1815
    ARM64_SYSREG_SPSR_EL3 = 61952,
1816
    ARM64_SYSREG_ELR_EL1 = 49665,
1817
    ARM64_SYSREG_ELR_EL2 = 57857,
1818
    ARM64_SYSREG_ELR_EL3 = 61953,
1819
    ARM64_SYSREG_SP_EL0 = 49672,
1820
    ARM64_SYSREG_SP_EL1 = 57864,
1821
    ARM64_SYSREG_SP_EL2 = 61960,
1822
    ARM64_SYSREG_SPSEL = 49680,
1823
    ARM64_SYSREG_NZCV = 55824,
1824
    ARM64_SYSREG_DAIF = 55825,
1825
    ARM64_SYSREG_CURRENTEL = 49682,
1826
    ARM64_SYSREG_SPSR_IRQ = 57880,
1827
    ARM64_SYSREG_SPSR_ABT = 57881,
1828
    ARM64_SYSREG_SPSR_UND = 57882,
1829
    ARM64_SYSREG_SPSR_FIQ = 57883,
1830
    ARM64_SYSREG_FPCR = 55840,
1831
    ARM64_SYSREG_FPSR = 55841,
1832
    ARM64_SYSREG_DSPSR_EL0 = 55848,
1833
    ARM64_SYSREG_DLR_EL0 = 55849,
1834
    ARM64_SYSREG_IFSR32_EL2 = 57985,
1835
    ARM64_SYSREG_AFSR0_EL1 = 49800,
1836
    ARM64_SYSREG_AFSR0_EL2 = 57992,
1837
    ARM64_SYSREG_AFSR0_EL3 = 62088,
1838
    ARM64_SYSREG_AFSR1_EL1 = 49801,
1839
    ARM64_SYSREG_AFSR1_EL2 = 57993,
1840
    ARM64_SYSREG_AFSR1_EL3 = 62089,
1841
    ARM64_SYSREG_ESR_EL1 = 49808,
1842
    ARM64_SYSREG_ESR_EL2 = 58000,
1843
    ARM64_SYSREG_ESR_EL3 = 62096,
1844
    ARM64_SYSREG_FPEXC32_EL2 = 58008,
1845
    ARM64_SYSREG_FAR_EL1 = 49920,
1846
    ARM64_SYSREG_FAR_EL2 = 58112,
1847
    ARM64_SYSREG_FAR_EL3 = 62208,
1848
    ARM64_SYSREG_HPFAR_EL2 = 58116,
1849
    ARM64_SYSREG_PAR_EL1 = 50080,
1850
    ARM64_SYSREG_PMCR_EL0 = 56544,
1851
    ARM64_SYSREG_PMCNTENSET_EL0 = 56545,
1852
    ARM64_SYSREG_PMCNTENCLR_EL0 = 56546,
1853
    ARM64_SYSREG_PMOVSCLR_EL0 = 56547,
1854
    ARM64_SYSREG_PMSELR_EL0 = 56549,
1855
    ARM64_SYSREG_PMCCNTR_EL0 = 56552,
1856
    ARM64_SYSREG_PMXEVTYPER_EL0 = 56553,
1857
    ARM64_SYSREG_PMXEVCNTR_EL0 = 56554,
1858
    ARM64_SYSREG_PMUSERENR_EL0 = 56560,
1859
    ARM64_SYSREG_PMINTENSET_EL1 = 50417,
1860
    ARM64_SYSREG_PMINTENCLR_EL1 = 50418,
1861
    ARM64_SYSREG_PMOVSSET_EL0 = 56563,
1862
    ARM64_SYSREG_MAIR_EL1 = 50448,
1863
    ARM64_SYSREG_MAIR_EL2 = 58640,
1864
    ARM64_SYSREG_MAIR_EL3 = 62736,
1865
    ARM64_SYSREG_AMAIR_EL1 = 50456,
1866
    ARM64_SYSREG_AMAIR_EL2 = 58648,
1867
    ARM64_SYSREG_AMAIR_EL3 = 62744,
1868
    ARM64_SYSREG_VBAR_EL1 = 50688,
1869
    ARM64_SYSREG_VBAR_EL2 = 58880,
1870
    ARM64_SYSREG_VBAR_EL3 = 62976,
1871
    ARM64_SYSREG_RMR_EL1 = 50690,
1872
    ARM64_SYSREG_RMR_EL2 = 58882,
1873
    ARM64_SYSREG_RMR_EL3 = 62978,
1874
    ARM64_SYSREG_CONTEXTIDR_EL1 = 50817,
1875
    ARM64_SYSREG_TPIDR_EL0 = 56962,
1876
    ARM64_SYSREG_TPIDR_EL2 = 59010,
1877
    ARM64_SYSREG_TPIDR_EL3 = 63106,
1878
    ARM64_SYSREG_TPIDRRO_EL0 = 56963,
1879
    ARM64_SYSREG_TPIDR_EL1 = 50820,
1880
    ARM64_SYSREG_CNTFRQ_EL0 = 57088,
1881
    ARM64_SYSREG_CNTVOFF_EL2 = 59139,
1882
    ARM64_SYSREG_CNTKCTL_EL1 = 50952,
1883
    ARM64_SYSREG_CNTHCTL_EL2 = 59144,
1884
    ARM64_SYSREG_CNTP_TVAL_EL0 = 57104,
1885
    ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152,
1886
    ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296,
1887
    ARM64_SYSREG_CNTP_CTL_EL0 = 57105,
1888
    ARM64_SYSREG_CNTHP_CTL_EL2 = 59153,
1889
    ARM64_SYSREG_CNTPS_CTL_EL1 = 65297,
1890
    ARM64_SYSREG_CNTP_CVAL_EL0 = 57106,
1891
    ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154,
1892
    ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298,
1893
    ARM64_SYSREG_CNTV_TVAL_EL0 = 57112,
1894
    ARM64_SYSREG_CNTV_CTL_EL0 = 57113,
1895
    ARM64_SYSREG_CNTV_CVAL_EL0 = 57114,
1896
    ARM64_SYSREG_PMEVCNTR0_EL0 = 57152,
1897
    ARM64_SYSREG_PMEVCNTR1_EL0 = 57153,
1898
    ARM64_SYSREG_PMEVCNTR2_EL0 = 57154,
1899
    ARM64_SYSREG_PMEVCNTR3_EL0 = 57155,
1900
    ARM64_SYSREG_PMEVCNTR4_EL0 = 57156,
1901
    ARM64_SYSREG_PMEVCNTR5_EL0 = 57157,
1902
    ARM64_SYSREG_PMEVCNTR6_EL0 = 57158,
1903
    ARM64_SYSREG_PMEVCNTR7_EL0 = 57159,
1904
    ARM64_SYSREG_PMEVCNTR8_EL0 = 57160,
1905
    ARM64_SYSREG_PMEVCNTR9_EL0 = 57161,
1906
    ARM64_SYSREG_PMEVCNTR10_EL0 = 57162,
1907
    ARM64_SYSREG_PMEVCNTR11_EL0 = 57163,
1908
    ARM64_SYSREG_PMEVCNTR12_EL0 = 57164,
1909
    ARM64_SYSREG_PMEVCNTR13_EL0 = 57165,
1910
    ARM64_SYSREG_PMEVCNTR14_EL0 = 57166,
1911
    ARM64_SYSREG_PMEVCNTR15_EL0 = 57167,
1912
    ARM64_SYSREG_PMEVCNTR16_EL0 = 57168,
1913
    ARM64_SYSREG_PMEVCNTR17_EL0 = 57169,
1914
    ARM64_SYSREG_PMEVCNTR18_EL0 = 57170,
1915
    ARM64_SYSREG_PMEVCNTR19_EL0 = 57171,
1916
    ARM64_SYSREG_PMEVCNTR20_EL0 = 57172,
1917
    ARM64_SYSREG_PMEVCNTR21_EL0 = 57173,
1918
    ARM64_SYSREG_PMEVCNTR22_EL0 = 57174,
1919
    ARM64_SYSREG_PMEVCNTR23_EL0 = 57175,
1920
    ARM64_SYSREG_PMEVCNTR24_EL0 = 57176,
1921
    ARM64_SYSREG_PMEVCNTR25_EL0 = 57177,
1922
    ARM64_SYSREG_PMEVCNTR26_EL0 = 57178,
1923
    ARM64_SYSREG_PMEVCNTR27_EL0 = 57179,
1924
    ARM64_SYSREG_PMEVCNTR28_EL0 = 57180,
1925
    ARM64_SYSREG_PMEVCNTR29_EL0 = 57181,
1926
    ARM64_SYSREG_PMEVCNTR30_EL0 = 57182,
1927
    ARM64_SYSREG_PMCCFILTR_EL0 = 57215,
1928
    ARM64_SYSREG_PMEVTYPER0_EL0 = 57184,
1929
    ARM64_SYSREG_PMEVTYPER1_EL0 = 57185,
1930
    ARM64_SYSREG_PMEVTYPER2_EL0 = 57186,
1931
    ARM64_SYSREG_PMEVTYPER3_EL0 = 57187,
1932
    ARM64_SYSREG_PMEVTYPER4_EL0 = 57188,
1933
    ARM64_SYSREG_PMEVTYPER5_EL0 = 57189,
1934
    ARM64_SYSREG_PMEVTYPER6_EL0 = 57190,
1935
    ARM64_SYSREG_PMEVTYPER7_EL0 = 57191,
1936
    ARM64_SYSREG_PMEVTYPER8_EL0 = 57192,
1937
    ARM64_SYSREG_PMEVTYPER9_EL0 = 57193,
1938
    ARM64_SYSREG_PMEVTYPER10_EL0 = 57194,
1939
    ARM64_SYSREG_PMEVTYPER11_EL0 = 57195,
1940
    ARM64_SYSREG_PMEVTYPER12_EL0 = 57196,
1941
    ARM64_SYSREG_PMEVTYPER13_EL0 = 57197,
1942
    ARM64_SYSREG_PMEVTYPER14_EL0 = 57198,
1943
    ARM64_SYSREG_PMEVTYPER15_EL0 = 57199,
1944
    ARM64_SYSREG_PMEVTYPER16_EL0 = 57200,
1945
    ARM64_SYSREG_PMEVTYPER17_EL0 = 57201,
1946
    ARM64_SYSREG_PMEVTYPER18_EL0 = 57202,
1947
    ARM64_SYSREG_PMEVTYPER19_EL0 = 57203,
1948
    ARM64_SYSREG_PMEVTYPER20_EL0 = 57204,
1949
    ARM64_SYSREG_PMEVTYPER21_EL0 = 57205,
1950
    ARM64_SYSREG_PMEVTYPER22_EL0 = 57206,
1951
    ARM64_SYSREG_PMEVTYPER23_EL0 = 57207,
1952
    ARM64_SYSREG_PMEVTYPER24_EL0 = 57208,
1953
    ARM64_SYSREG_PMEVTYPER25_EL0 = 57209,
1954
    ARM64_SYSREG_PMEVTYPER26_EL0 = 57210,
1955
    ARM64_SYSREG_PMEVTYPER27_EL0 = 57211,
1956
    ARM64_SYSREG_PMEVTYPER28_EL0 = 57212,
1957
    ARM64_SYSREG_PMEVTYPER29_EL0 = 57213,
1958
    ARM64_SYSREG_PMEVTYPER30_EL0 = 57214,
1959
    ARM64_SYSREG_TRCPRGCTLR = 34824,
1960
    ARM64_SYSREG_TRCPROCSELR = 34832,
1961
    ARM64_SYSREG_TRCCONFIGR = 34848,
1962
    ARM64_SYSREG_TRCAUXCTLR = 34864,
1963
    ARM64_SYSREG_TRCEVENTCTL0R = 34880,
1964
    ARM64_SYSREG_TRCEVENTCTL1R = 34888,
1965
    ARM64_SYSREG_TRCSTALLCTLR = 34904,
1966
    ARM64_SYSREG_TRCTSCTLR = 34912,
1967
    ARM64_SYSREG_TRCSYNCPR = 34920,
1968
    ARM64_SYSREG_TRCCCCTLR = 34928,
1969
    ARM64_SYSREG_TRCBBCTLR = 34936,
1970
    ARM64_SYSREG_TRCTRACEIDR = 34817,
1971
    ARM64_SYSREG_TRCQCTLR = 34825,
1972
    ARM64_SYSREG_TRCVICTLR = 34818,
1973
    ARM64_SYSREG_TRCVIIECTLR = 34826,
1974
    ARM64_SYSREG_TRCVISSCTLR = 34834,
1975
    ARM64_SYSREG_TRCVIPCSSCTLR = 34842,
1976
    ARM64_SYSREG_TRCVDCTLR = 34882,
1977
    ARM64_SYSREG_TRCVDSACCTLR = 34890,
1978
    ARM64_SYSREG_TRCVDARCCTLR = 34898,
1979
    ARM64_SYSREG_TRCSEQEVR0 = 34820,
1980
    ARM64_SYSREG_TRCSEQEVR1 = 34828,
1981
    ARM64_SYSREG_TRCSEQEVR2 = 34836,
1982
    ARM64_SYSREG_TRCSEQRSTEVR = 34868,
1983
    ARM64_SYSREG_TRCSEQSTR = 34876,
1984
    ARM64_SYSREG_TRCEXTINSELR = 34884,
1985
    ARM64_SYSREG_TRCCNTRLDVR0 = 34821,
1986
    ARM64_SYSREG_TRCCNTRLDVR1 = 34829,
1987
    ARM64_SYSREG_TRCCNTRLDVR2 = 34837,
1988
    ARM64_SYSREG_TRCCNTRLDVR3 = 34845,
1989
    ARM64_SYSREG_TRCCNTCTLR0 = 34853,
1990
    ARM64_SYSREG_TRCCNTCTLR1 = 34861,
1991
    ARM64_SYSREG_TRCCNTCTLR2 = 34869,
1992
    ARM64_SYSREG_TRCCNTCTLR3 = 34877,
1993
    ARM64_SYSREG_TRCCNTVR0 = 34885,
1994
    ARM64_SYSREG_TRCCNTVR1 = 34893,
1995
    ARM64_SYSREG_TRCCNTVR2 = 34901,
1996
    ARM64_SYSREG_TRCCNTVR3 = 34909,
1997
    ARM64_SYSREG_TRCIMSPEC0 = 34823,
1998
    ARM64_SYSREG_TRCIMSPEC1 = 34831,
1999
    ARM64_SYSREG_TRCIMSPEC2 = 34839,
2000
    ARM64_SYSREG_TRCIMSPEC3 = 34847,
2001
    ARM64_SYSREG_TRCIMSPEC4 = 34855,
2002
    ARM64_SYSREG_TRCIMSPEC5 = 34863,
2003
    ARM64_SYSREG_TRCIMSPEC6 = 34871,
2004
    ARM64_SYSREG_TRCIMSPEC7 = 34879,
2005
    ARM64_SYSREG_TRCRSCTLR2 = 34960,
2006
    ARM64_SYSREG_TRCRSCTLR3 = 34968,
2007
    ARM64_SYSREG_TRCRSCTLR4 = 34976,
2008
    ARM64_SYSREG_TRCRSCTLR5 = 34984,
2009
    ARM64_SYSREG_TRCRSCTLR6 = 34992,
2010
    ARM64_SYSREG_TRCRSCTLR7 = 35000,
2011
    ARM64_SYSREG_TRCRSCTLR8 = 35008,
2012
    ARM64_SYSREG_TRCRSCTLR9 = 35016,
2013
    ARM64_SYSREG_TRCRSCTLR10 = 35024,
2014
    ARM64_SYSREG_TRCRSCTLR11 = 35032,
2015
    ARM64_SYSREG_TRCRSCTLR12 = 35040,
2016
    ARM64_SYSREG_TRCRSCTLR13 = 35048,
2017
    ARM64_SYSREG_TRCRSCTLR14 = 35056,
2018
    ARM64_SYSREG_TRCRSCTLR15 = 35064,
2019
    ARM64_SYSREG_TRCRSCTLR16 = 34945,
2020
    ARM64_SYSREG_TRCRSCTLR17 = 34953,
2021
    ARM64_SYSREG_TRCRSCTLR18 = 34961,
2022
    ARM64_SYSREG_TRCRSCTLR19 = 34969,
2023
    ARM64_SYSREG_TRCRSCTLR20 = 34977,
2024
    ARM64_SYSREG_TRCRSCTLR21 = 34985,
2025
    ARM64_SYSREG_TRCRSCTLR22 = 34993,
2026
    ARM64_SYSREG_TRCRSCTLR23 = 35001,
2027
    ARM64_SYSREG_TRCRSCTLR24 = 35009,
2028
    ARM64_SYSREG_TRCRSCTLR25 = 35017,
2029
    ARM64_SYSREG_TRCRSCTLR26 = 35025,
2030
    ARM64_SYSREG_TRCRSCTLR27 = 35033,
2031
    ARM64_SYSREG_TRCRSCTLR28 = 35041,
2032
    ARM64_SYSREG_TRCRSCTLR29 = 35049,
2033
    ARM64_SYSREG_TRCRSCTLR30 = 35057,
2034
    ARM64_SYSREG_TRCRSCTLR31 = 35065,
2035
    ARM64_SYSREG_TRCSSCCR0 = 34946,
2036
    ARM64_SYSREG_TRCSSCCR1 = 34954,
2037
    ARM64_SYSREG_TRCSSCCR2 = 34962,
2038
    ARM64_SYSREG_TRCSSCCR3 = 34970,
2039
    ARM64_SYSREG_TRCSSCCR4 = 34978,
2040
    ARM64_SYSREG_TRCSSCCR5 = 34986,
2041
    ARM64_SYSREG_TRCSSCCR6 = 34994,
2042
    ARM64_SYSREG_TRCSSCCR7 = 35002,
2043
    ARM64_SYSREG_TRCSSCSR0 = 35010,
2044
    ARM64_SYSREG_TRCSSCSR1 = 35018,
2045
    ARM64_SYSREG_TRCSSCSR2 = 35026,
2046
    ARM64_SYSREG_TRCSSCSR3 = 35034,
2047
    ARM64_SYSREG_TRCSSCSR4 = 35042,
2048
    ARM64_SYSREG_TRCSSCSR5 = 35050,
2049
    ARM64_SYSREG_TRCSSCSR6 = 35058,
2050
    ARM64_SYSREG_TRCSSCSR7 = 35066,
2051
    ARM64_SYSREG_TRCSSPCICR0 = 34947,
2052
    ARM64_SYSREG_TRCSSPCICR1 = 34955,
2053
    ARM64_SYSREG_TRCSSPCICR2 = 34963,
2054
    ARM64_SYSREG_TRCSSPCICR3 = 34971,
2055
    ARM64_SYSREG_TRCSSPCICR4 = 34979,
2056
    ARM64_SYSREG_TRCSSPCICR5 = 34987,
2057
    ARM64_SYSREG_TRCSSPCICR6 = 34995,
2058
    ARM64_SYSREG_TRCSSPCICR7 = 35003,
2059
    ARM64_SYSREG_TRCPDCR = 34980,
2060
    ARM64_SYSREG_TRCACVR0 = 35072,
2061
    ARM64_SYSREG_TRCACVR1 = 35088,
2062
    ARM64_SYSREG_TRCACVR2 = 35104,
2063
    ARM64_SYSREG_TRCACVR3 = 35120,
2064
    ARM64_SYSREG_TRCACVR4 = 35136,
2065
    ARM64_SYSREG_TRCACVR5 = 35152,
2066
    ARM64_SYSREG_TRCACVR6 = 35168,
2067
    ARM64_SYSREG_TRCACVR7 = 35184,
2068
    ARM64_SYSREG_TRCACVR8 = 35073,
2069
    ARM64_SYSREG_TRCACVR9 = 35089,
2070
    ARM64_SYSREG_TRCACVR10 = 35105,
2071
    ARM64_SYSREG_TRCACVR11 = 35121,
2072
    ARM64_SYSREG_TRCACVR12 = 35137,
2073
    ARM64_SYSREG_TRCACVR13 = 35153,
2074
    ARM64_SYSREG_TRCACVR14 = 35169,
2075
    ARM64_SYSREG_TRCACVR15 = 35185,
2076
    ARM64_SYSREG_TRCACATR0 = 35074,
2077
    ARM64_SYSREG_TRCACATR1 = 35090,
2078
    ARM64_SYSREG_TRCACATR2 = 35106,
2079
    ARM64_SYSREG_TRCACATR3 = 35122,
2080
    ARM64_SYSREG_TRCACATR4 = 35138,
2081
    ARM64_SYSREG_TRCACATR5 = 35154,
2082
    ARM64_SYSREG_TRCACATR6 = 35170,
2083
    ARM64_SYSREG_TRCACATR7 = 35186,
2084
    ARM64_SYSREG_TRCACATR8 = 35075,
2085
    ARM64_SYSREG_TRCACATR9 = 35091,
2086
    ARM64_SYSREG_TRCACATR10 = 35107,
2087
    ARM64_SYSREG_TRCACATR11 = 35123,
2088
    ARM64_SYSREG_TRCACATR12 = 35139,
2089
    ARM64_SYSREG_TRCACATR13 = 35155,
2090
    ARM64_SYSREG_TRCACATR14 = 35171,
2091
    ARM64_SYSREG_TRCACATR15 = 35187,
2092
    ARM64_SYSREG_TRCDVCVR0 = 35076,
2093
    ARM64_SYSREG_TRCDVCVR1 = 35108,
2094
    ARM64_SYSREG_TRCDVCVR2 = 35140,
2095
    ARM64_SYSREG_TRCDVCVR3 = 35172,
2096
    ARM64_SYSREG_TRCDVCVR4 = 35077,
2097
    ARM64_SYSREG_TRCDVCVR5 = 35109,
2098
    ARM64_SYSREG_TRCDVCVR6 = 35141,
2099
    ARM64_SYSREG_TRCDVCVR7 = 35173,
2100
    ARM64_SYSREG_TRCDVCMR0 = 35078,
2101
    ARM64_SYSREG_TRCDVCMR1 = 35110,
2102
    ARM64_SYSREG_TRCDVCMR2 = 35142,
2103
    ARM64_SYSREG_TRCDVCMR3 = 35174,
2104
    ARM64_SYSREG_TRCDVCMR4 = 35079,
2105
    ARM64_SYSREG_TRCDVCMR5 = 35111,
2106
    ARM64_SYSREG_TRCDVCMR6 = 35143,
2107
    ARM64_SYSREG_TRCDVCMR7 = 35175,
2108
    ARM64_SYSREG_TRCCIDCVR0 = 35200,
2109
    ARM64_SYSREG_TRCCIDCVR1 = 35216,
2110
    ARM64_SYSREG_TRCCIDCVR2 = 35232,
2111
    ARM64_SYSREG_TRCCIDCVR3 = 35248,
2112
    ARM64_SYSREG_TRCCIDCVR4 = 35264,
2113
    ARM64_SYSREG_TRCCIDCVR5 = 35280,
2114
    ARM64_SYSREG_TRCCIDCVR6 = 35296,
2115
    ARM64_SYSREG_TRCCIDCVR7 = 35312,
2116
    ARM64_SYSREG_TRCVMIDCVR0 = 35201,
2117
    ARM64_SYSREG_TRCVMIDCVR1 = 35217,
2118
    ARM64_SYSREG_TRCVMIDCVR2 = 35233,
2119
    ARM64_SYSREG_TRCVMIDCVR3 = 35249,
2120
    ARM64_SYSREG_TRCVMIDCVR4 = 35265,
2121
    ARM64_SYSREG_TRCVMIDCVR5 = 35281,
2122
    ARM64_SYSREG_TRCVMIDCVR6 = 35297,
2123
    ARM64_SYSREG_TRCVMIDCVR7 = 35313,
2124
    ARM64_SYSREG_TRCCIDCCTLR0 = 35202,
2125
    ARM64_SYSREG_TRCCIDCCTLR1 = 35210,
2126
    ARM64_SYSREG_TRCVMIDCCTLR0 = 35218,
2127
    ARM64_SYSREG_TRCVMIDCCTLR1 = 35226,
2128
    ARM64_SYSREG_TRCITCTRL = 35716,
2129
    ARM64_SYSREG_TRCCLAIMSET = 35782,
2130
    ARM64_SYSREG_TRCCLAIMCLR = 35790,
2131
    ARM64_SYSREG_ICC_BPR1_EL1 = 50787,
2132
    ARM64_SYSREG_ICC_BPR0_EL1 = 50755,
2133
    ARM64_SYSREG_ICC_PMR_EL1 = 49712,
2134
    ARM64_SYSREG_ICC_CTLR_EL1 = 50788,
2135
    ARM64_SYSREG_ICC_CTLR_EL3 = 63076,
2136
    ARM64_SYSREG_ICC_SRE_EL1 = 50789,
2137
    ARM64_SYSREG_ICC_SRE_EL2 = 58957,
2138
    ARM64_SYSREG_ICC_SRE_EL3 = 63077,
2139
    ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790,
2140
    ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791,
2141
    ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079,
2142
    ARM64_SYSREG_ICC_SEIEN_EL1 = 50792,
2143
    ARM64_SYSREG_ICC_AP0R0_EL1 = 50756,
2144
    ARM64_SYSREG_ICC_AP0R1_EL1 = 50757,
2145
    ARM64_SYSREG_ICC_AP0R2_EL1 = 50758,
2146
    ARM64_SYSREG_ICC_AP0R3_EL1 = 50759,
2147
    ARM64_SYSREG_ICC_AP1R0_EL1 = 50760,
2148
    ARM64_SYSREG_ICC_AP1R1_EL1 = 50761,
2149
    ARM64_SYSREG_ICC_AP1R2_EL1 = 50762,
2150
    ARM64_SYSREG_ICC_AP1R3_EL1 = 50763,
2151
    ARM64_SYSREG_ICH_AP0R0_EL2 = 58944,
2152
    ARM64_SYSREG_ICH_AP0R1_EL2 = 58945,
2153
    ARM64_SYSREG_ICH_AP0R2_EL2 = 58946,
2154
    ARM64_SYSREG_ICH_AP0R3_EL2 = 58947,
2155
    ARM64_SYSREG_ICH_AP1R0_EL2 = 58952,
2156
    ARM64_SYSREG_ICH_AP1R1_EL2 = 58953,
2157
    ARM64_SYSREG_ICH_AP1R2_EL2 = 58954,
2158
    ARM64_SYSREG_ICH_AP1R3_EL2 = 58955,
2159
    ARM64_SYSREG_ICH_HCR_EL2 = 58968,
2160
    ARM64_SYSREG_ICH_MISR_EL2 = 58970,
2161
    ARM64_SYSREG_ICH_VMCR_EL2 = 58975,
2162
    ARM64_SYSREG_ICH_VSEIR_EL2 = 58956,
2163
    ARM64_SYSREG_ICH_LR0_EL2 = 58976,
2164
    ARM64_SYSREG_ICH_LR1_EL2 = 58977,
2165
    ARM64_SYSREG_ICH_LR2_EL2 = 58978,
2166
    ARM64_SYSREG_ICH_LR3_EL2 = 58979,
2167
    ARM64_SYSREG_ICH_LR4_EL2 = 58980,
2168
    ARM64_SYSREG_ICH_LR5_EL2 = 58981,
2169
    ARM64_SYSREG_ICH_LR6_EL2 = 58982,
2170
    ARM64_SYSREG_ICH_LR7_EL2 = 58983,
2171
    ARM64_SYSREG_ICH_LR8_EL2 = 58984,
2172
    ARM64_SYSREG_ICH_LR9_EL2 = 58985,
2173
    ARM64_SYSREG_ICH_LR10_EL2 = 58986,
2174
    ARM64_SYSREG_ICH_LR11_EL2 = 58987,
2175
    ARM64_SYSREG_ICH_LR12_EL2 = 58988,
2176
    ARM64_SYSREG_ICH_LR13_EL2 = 58989,
2177
    ARM64_SYSREG_ICH_LR14_EL2 = 58990,
2178
    ARM64_SYSREG_ICH_LR15_EL2 = 58991,
2179
    ARM64_SYSREG_PAN = 49683,
2180
    ARM64_SYSREG_LORSA_EL1 = 50464,
2181
    ARM64_SYSREG_LOREA_EL1 = 50465,
2182
    ARM64_SYSREG_LORN_EL1 = 50466,
2183
    ARM64_SYSREG_LORC_EL1 = 50467,
2184
    ARM64_SYSREG_TTBR1_EL2 = 57601,
2185
    ARM64_SYSREG_CONTEXTIDR_EL2 = 59009,
2186
    ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160,
2187
    ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162,
2188
    ARM64_SYSREG_CNTHV_CTL_EL2 = 59161,
2189
    ARM64_SYSREG_SCTLR_EL12 = 59520,
2190
    ARM64_SYSREG_CPACR_EL12 = 59522,
2191
    ARM64_SYSREG_TTBR0_EL12 = 59648,
2192
    ARM64_SYSREG_TTBR1_EL12 = 59649,
2193
    ARM64_SYSREG_TCR_EL12 = 59650,
2194
    ARM64_SYSREG_AFSR0_EL12 = 60040,
2195
    ARM64_SYSREG_AFSR1_EL12 = 60041,
2196
    ARM64_SYSREG_ESR_EL12 = 60048,
2197
    ARM64_SYSREG_FAR_EL12 = 60160,
2198
    ARM64_SYSREG_MAIR_EL12 = 60688,
2199
    ARM64_SYSREG_AMAIR_EL12 = 60696,
2200
    ARM64_SYSREG_VBAR_EL12 = 60928,
2201
    ARM64_SYSREG_CONTEXTIDR_EL12 = 61057,
2202
    ARM64_SYSREG_CNTKCTL_EL12 = 61192,
2203
    ARM64_SYSREG_CNTP_TVAL_EL02 = 61200,
2204
    ARM64_SYSREG_CNTP_CTL_EL02 = 61201,
2205
    ARM64_SYSREG_CNTP_CVAL_EL02 = 61202,
2206
    ARM64_SYSREG_CNTV_TVAL_EL02 = 61208,
2207
    ARM64_SYSREG_CNTV_CTL_EL02 = 61209,
2208
    ARM64_SYSREG_CNTV_CVAL_EL02 = 61210,
2209
    ARM64_SYSREG_SPSR_EL12 = 59904,
2210
    ARM64_SYSREG_ELR_EL12 = 59905,
2211
    ARM64_SYSREG_UAO = 49684,
2212
    ARM64_SYSREG_PMBLIMITR_EL1 = 50384,
2213
    ARM64_SYSREG_PMBPTR_EL1 = 50385,
2214
    ARM64_SYSREG_PMBSR_EL1 = 50387,
2215
    ARM64_SYSREG_PMBIDR_EL1 = 50391,
2216
    ARM64_SYSREG_PMSCR_EL2 = 58568,
2217
    ARM64_SYSREG_PMSCR_EL12 = 60616,
2218
    ARM64_SYSREG_PMSCR_EL1 = 50376,
2219
    ARM64_SYSREG_PMSICR_EL1 = 50378,
2220
    ARM64_SYSREG_PMSIRR_EL1 = 50379,
2221
    ARM64_SYSREG_PMSFCR_EL1 = 50380,
2222
    ARM64_SYSREG_PMSEVFR_EL1 = 50381,
2223
    ARM64_SYSREG_PMSLATFR_EL1 = 50382,
2224
    ARM64_SYSREG_PMSIDR_EL1 = 50383,
2225
    ARM64_SYSREG_ERRSELR_EL1 = 49817,
2226
    ARM64_SYSREG_ERXCTLR_EL1 = 49825,
2227
    ARM64_SYSREG_ERXSTATUS_EL1 = 49826,
2228
    ARM64_SYSREG_ERXADDR_EL1 = 49827,
2229
    ARM64_SYSREG_ERXMISC0_EL1 = 49832,
2230
    ARM64_SYSREG_ERXMISC1_EL1 = 49833,
2231
    ARM64_SYSREG_DISR_EL1 = 50697,
2232
    ARM64_SYSREG_VDISR_EL2 = 58889,
2233
    ARM64_SYSREG_VSESR_EL2 = 58003,
2234
    ARM64_SYSREG_APIAKEYLO_EL1 = 49416,
2235
    ARM64_SYSREG_APIAKEYHI_EL1 = 49417,
2236
    ARM64_SYSREG_APIBKEYLO_EL1 = 49418,
2237
    ARM64_SYSREG_APIBKEYHI_EL1 = 49419,
2238
    ARM64_SYSREG_APDAKEYLO_EL1 = 49424,
2239
    ARM64_SYSREG_APDAKEYHI_EL1 = 49425,
2240
    ARM64_SYSREG_APDBKEYLO_EL1 = 49426,
2241
    ARM64_SYSREG_APDBKEYHI_EL1 = 49427,
2242
    ARM64_SYSREG_APGAKEYLO_EL1 = 49432,
2243
    ARM64_SYSREG_APGAKEYHI_EL1 = 49433,
2244
    ARM64_SYSREG_VSTCR_EL2 = 57650,
2245
    ARM64_SYSREG_VSTTBR_EL2 = 57648,
2246
    ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168,
2247
    ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170,
2248
    ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169,
2249
    ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176,
2250
    ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178,
2251
    ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177,
2252
    ARM64_SYSREG_SDER32_EL2 = 57497,
2253
    ARM64_SYSREG_ERXPFGCTL_EL1 = 49829,
2254
    ARM64_SYSREG_ERXPFGCDN_EL1 = 49830,
2255
    ARM64_SYSREG_ERXTS_EL1 = 49839,
2256
    ARM64_SYSREG_ERXMISC2_EL1 = 49834,
2257
    ARM64_SYSREG_ERXMISC3_EL1 = 49835,
2258
    ARM64_SYSREG_ERXPFGF_EL1 = 49828,
2259
    ARM64_SYSREG_MPAM0_EL1 = 50473,
2260
    ARM64_SYSREG_MPAM1_EL1 = 50472,
2261
    ARM64_SYSREG_MPAM2_EL2 = 58664,
2262
    ARM64_SYSREG_MPAM3_EL3 = 62760,
2263
    ARM64_SYSREG_MPAM1_EL12 = 60712,
2264
    ARM64_SYSREG_MPAMHCR_EL2 = 58656,
2265
    ARM64_SYSREG_MPAMVPMV_EL2 = 58657,
2266
    ARM64_SYSREG_MPAMVPM0_EL2 = 58672,
2267
    ARM64_SYSREG_MPAMVPM1_EL2 = 58673,
2268
    ARM64_SYSREG_MPAMVPM2_EL2 = 58674,
2269
    ARM64_SYSREG_MPAMVPM3_EL2 = 58675,
2270
    ARM64_SYSREG_MPAMVPM4_EL2 = 58676,
2271
    ARM64_SYSREG_MPAMVPM5_EL2 = 58677,
2272
    ARM64_SYSREG_MPAMVPM6_EL2 = 58678,
2273
    ARM64_SYSREG_MPAMVPM7_EL2 = 58679,
2274
    ARM64_SYSREG_MPAMIDR_EL1 = 50468,
2275
    ARM64_SYSREG_AMCR_EL0 = 56976,
2276
    ARM64_SYSREG_AMCFGR_EL0 = 56977,
2277
    ARM64_SYSREG_AMCGCR_EL0 = 56978,
2278
    ARM64_SYSREG_AMUSERENR_EL0 = 56979,
2279
    ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980,
2280
    ARM64_SYSREG_AMCNTENSET0_EL0 = 56981,
2281
    ARM64_SYSREG_AMEVCNTR00_EL0 = 56992,
2282
    ARM64_SYSREG_AMEVCNTR01_EL0 = 56993,
2283
    ARM64_SYSREG_AMEVCNTR02_EL0 = 56994,
2284
    ARM64_SYSREG_AMEVCNTR03_EL0 = 56995,
2285
    ARM64_SYSREG_AMEVTYPER00_EL0 = 57008,
2286
    ARM64_SYSREG_AMEVTYPER01_EL0 = 57009,
2287
    ARM64_SYSREG_AMEVTYPER02_EL0 = 57010,
2288
    ARM64_SYSREG_AMEVTYPER03_EL0 = 57011,
2289
    ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984,
2290
    ARM64_SYSREG_AMCNTENSET1_EL0 = 56985,
2291
    ARM64_SYSREG_AMEVCNTR10_EL0 = 57056,
2292
    ARM64_SYSREG_AMEVCNTR11_EL0 = 57057,
2293
    ARM64_SYSREG_AMEVCNTR12_EL0 = 57058,
2294
    ARM64_SYSREG_AMEVCNTR13_EL0 = 57059,
2295
    ARM64_SYSREG_AMEVCNTR14_EL0 = 57060,
2296
    ARM64_SYSREG_AMEVCNTR15_EL0 = 57061,
2297
    ARM64_SYSREG_AMEVCNTR16_EL0 = 57062,
2298
    ARM64_SYSREG_AMEVCNTR17_EL0 = 57063,
2299
    ARM64_SYSREG_AMEVCNTR18_EL0 = 57064,
2300
    ARM64_SYSREG_AMEVCNTR19_EL0 = 57065,
2301
    ARM64_SYSREG_AMEVCNTR110_EL0 = 57066,
2302
    ARM64_SYSREG_AMEVCNTR111_EL0 = 57067,
2303
    ARM64_SYSREG_AMEVCNTR112_EL0 = 57068,
2304
    ARM64_SYSREG_AMEVCNTR113_EL0 = 57069,
2305
    ARM64_SYSREG_AMEVCNTR114_EL0 = 57070,
2306
    ARM64_SYSREG_AMEVCNTR115_EL0 = 57071,
2307
    ARM64_SYSREG_AMEVTYPER10_EL0 = 57072,
2308
    ARM64_SYSREG_AMEVTYPER11_EL0 = 57073,
2309
    ARM64_SYSREG_AMEVTYPER12_EL0 = 57074,
2310
    ARM64_SYSREG_AMEVTYPER13_EL0 = 57075,
2311
    ARM64_SYSREG_AMEVTYPER14_EL0 = 57076,
2312
    ARM64_SYSREG_AMEVTYPER15_EL0 = 57077,
2313
    ARM64_SYSREG_AMEVTYPER16_EL0 = 57078,
2314
    ARM64_SYSREG_AMEVTYPER17_EL0 = 57079,
2315
    ARM64_SYSREG_AMEVTYPER18_EL0 = 57080,
2316
    ARM64_SYSREG_AMEVTYPER19_EL0 = 57081,
2317
    ARM64_SYSREG_AMEVTYPER110_EL0 = 57082,
2318
    ARM64_SYSREG_AMEVTYPER111_EL0 = 57083,
2319
    ARM64_SYSREG_AMEVTYPER112_EL0 = 57084,
2320
    ARM64_SYSREG_AMEVTYPER113_EL0 = 57085,
2321
    ARM64_SYSREG_AMEVTYPER114_EL0 = 57086,
2322
    ARM64_SYSREG_AMEVTYPER115_EL0 = 57087,
2323
    ARM64_SYSREG_TRFCR_EL1 = 49297,
2324
    ARM64_SYSREG_TRFCR_EL2 = 57489,
2325
    ARM64_SYSREG_TRFCR_EL12 = 59537,
2326
    ARM64_SYSREG_DIT = 55829,
2327
    ARM64_SYSREG_VNCR_EL2 = 57616,
2328
    ARM64_SYSREG_ZCR_EL1 = 49296,
2329
    ARM64_SYSREG_ZCR_EL2 = 57488,
2330
    ARM64_SYSREG_ZCR_EL3 = 61584,
2331
    ARM64_SYSREG_ZCR_EL12 = 59536,
2332
    ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424,
2333
}
2334
#[repr(u32)]
2335
#[doc = " System PState Field (MSR instruction)"]
2336
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2337
pub enum arm64_pstate {
2338
    ARM64_PSTATE_INVALID = 0,
2339
    ARM64_PSTATE_SPSEL = 5,
2340
    ARM64_PSTATE_DAIFSET = 30,
2341
    ARM64_PSTATE_DAIFCLR = 31,
2342
    ARM64_PSTATE_PAN = 4,
2343
    ARM64_PSTATE_UAO = 3,
2344
    ARM64_PSTATE_DIT = 26,
2345
}
2346
#[repr(u32)]
2347
#[doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"]
2348
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2349
pub enum arm64_vas {
2350
    ARM64_VAS_INVALID = 0,
2351
    ARM64_VAS_16B = 1,
2352
    ARM64_VAS_8B = 2,
2353
    ARM64_VAS_4B = 3,
2354
    ARM64_VAS_1B = 4,
2355
    ARM64_VAS_8H = 5,
2356
    ARM64_VAS_4H = 6,
2357
    ARM64_VAS_2H = 7,
2358
    ARM64_VAS_1H = 8,
2359
    ARM64_VAS_4S = 9,
2360
    ARM64_VAS_2S = 10,
2361
    ARM64_VAS_1S = 11,
2362
    ARM64_VAS_2D = 12,
2363
    ARM64_VAS_1D = 13,
2364
    ARM64_VAS_1Q = 14,
2365
}
2366
#[repr(u32)]
2367
#[doc = " Memory barrier operands"]
2368
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2369
pub enum arm64_barrier_op {
2370
    ARM64_BARRIER_INVALID = 0,
2371
    ARM64_BARRIER_OSHLD = 1,
2372
    ARM64_BARRIER_OSHST = 2,
2373
    ARM64_BARRIER_OSH = 3,
2374
    ARM64_BARRIER_NSHLD = 5,
2375
    ARM64_BARRIER_NSHST = 6,
2376
    ARM64_BARRIER_NSH = 7,
2377
    ARM64_BARRIER_ISHLD = 9,
2378
    ARM64_BARRIER_ISHST = 10,
2379
    ARM64_BARRIER_ISH = 11,
2380
    ARM64_BARRIER_LD = 13,
2381
    ARM64_BARRIER_ST = 14,
2382
    ARM64_BARRIER_SY = 15,
2383
}
2384
#[repr(u32)]
2385
#[doc = " Operand type for instruction's operands"]
2386
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2387
pub enum arm64_op_type {
2388
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
2389
    ARM64_OP_INVALID = 0,
2390
    #[doc = "< = CS_OP_REG (Register operand)."]
2391
    ARM64_OP_REG = 1,
2392
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
2393
    ARM64_OP_IMM = 2,
2394
    #[doc = "< = CS_OP_MEM (Memory operand)."]
2395
    ARM64_OP_MEM = 3,
2396
    #[doc = "< = CS_OP_FP (Floating-Point operand)."]
2397
    ARM64_OP_FP = 4,
2398
    #[doc = "< C-Immediate"]
2399
    ARM64_OP_CIMM = 64,
2400
    #[doc = "< MRS register operand."]
2401
    ARM64_OP_REG_MRS = 65,
2402
    #[doc = "< MSR register operand."]
2403
    ARM64_OP_REG_MSR = 66,
2404
    #[doc = "< PState operand."]
2405
    ARM64_OP_PSTATE = 67,
2406
    #[doc = "< SYS operand for IC/DC/AT/TLBI instructions."]
2407
    ARM64_OP_SYS = 68,
2408
    #[doc = "< Prefetch operand (PRFM)."]
2409
    ARM64_OP_PREFETCH = 69,
2410
    #[doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."]
2411
    ARM64_OP_BARRIER = 70,
2412
}
2413
#[repr(u32)]
2414
#[doc = " SYS operands (IC/DC/AC/TLBI)"]
2415
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2416
pub enum arm64_sys_op {
2417
    ARM64_SYS_INVALID = 0,
2418
    #[doc = " TLBI operations"]
2419
    ARM64_TLBI_IPAS2E1IS = 1,
2420
    #[doc = " TLBI operations"]
2421
    ARM64_TLBI_IPAS2LE1IS = 2,
2422
    #[doc = " TLBI operations"]
2423
    ARM64_TLBI_VMALLE1IS = 3,
2424
    #[doc = " TLBI operations"]
2425
    ARM64_TLBI_ALLE2IS = 4,
2426
    #[doc = " TLBI operations"]
2427
    ARM64_TLBI_ALLE3IS = 5,
2428
    #[doc = " TLBI operations"]
2429
    ARM64_TLBI_VAE1IS = 6,
2430
    #[doc = " TLBI operations"]
2431
    ARM64_TLBI_VAE2IS = 7,
2432
    #[doc = " TLBI operations"]
2433
    ARM64_TLBI_VAE3IS = 8,
2434
    #[doc = " TLBI operations"]
2435
    ARM64_TLBI_ASIDE1IS = 9,
2436
    #[doc = " TLBI operations"]
2437
    ARM64_TLBI_VAAE1IS = 10,
2438
    #[doc = " TLBI operations"]
2439
    ARM64_TLBI_ALLE1IS = 11,
2440
    #[doc = " TLBI operations"]
2441
    ARM64_TLBI_VALE1IS = 12,
2442
    #[doc = " TLBI operations"]
2443
    ARM64_TLBI_VALE2IS = 13,
2444
    #[doc = " TLBI operations"]
2445
    ARM64_TLBI_VALE3IS = 14,
2446
    #[doc = " TLBI operations"]
2447
    ARM64_TLBI_VMALLS12E1IS = 15,
2448
    #[doc = " TLBI operations"]
2449
    ARM64_TLBI_VAALE1IS = 16,
2450
    #[doc = " TLBI operations"]
2451
    ARM64_TLBI_IPAS2E1 = 17,
2452
    #[doc = " TLBI operations"]
2453
    ARM64_TLBI_IPAS2LE1 = 18,
2454
    #[doc = " TLBI operations"]
2455
    ARM64_TLBI_VMALLE1 = 19,
2456
    #[doc = " TLBI operations"]
2457
    ARM64_TLBI_ALLE2 = 20,
2458
    #[doc = " TLBI operations"]
2459
    ARM64_TLBI_ALLE3 = 21,
2460
    #[doc = " TLBI operations"]
2461
    ARM64_TLBI_VAE1 = 22,
2462
    #[doc = " TLBI operations"]
2463
    ARM64_TLBI_VAE2 = 23,
2464
    #[doc = " TLBI operations"]
2465
    ARM64_TLBI_VAE3 = 24,
2466
    #[doc = " TLBI operations"]
2467
    ARM64_TLBI_ASIDE1 = 25,
2468
    #[doc = " TLBI operations"]
2469
    ARM64_TLBI_VAAE1 = 26,
2470
    #[doc = " TLBI operations"]
2471
    ARM64_TLBI_ALLE1 = 27,
2472
    #[doc = " TLBI operations"]
2473
    ARM64_TLBI_VALE1 = 28,
2474
    #[doc = " TLBI operations"]
2475
    ARM64_TLBI_VALE2 = 29,
2476
    #[doc = " TLBI operations"]
2477
    ARM64_TLBI_VALE3 = 30,
2478
    #[doc = " TLBI operations"]
2479
    ARM64_TLBI_VMALLS12E1 = 31,
2480
    #[doc = " TLBI operations"]
2481
    ARM64_TLBI_VAALE1 = 32,
2482
    #[doc = " TLBI operations"]
2483
    ARM64_TLBI_VMALLE1OS = 33,
2484
    #[doc = " TLBI operations"]
2485
    ARM64_TLBI_VAE1OS = 34,
2486
    #[doc = " TLBI operations"]
2487
    ARM64_TLBI_ASIDE1OS = 35,
2488
    #[doc = " TLBI operations"]
2489
    ARM64_TLBI_VAAE1OS = 36,
2490
    #[doc = " TLBI operations"]
2491
    ARM64_TLBI_VALE1OS = 37,
2492
    #[doc = " TLBI operations"]
2493
    ARM64_TLBI_VAALE1OS = 38,
2494
    #[doc = " TLBI operations"]
2495
    ARM64_TLBI_IPAS2E1OS = 39,
2496
    #[doc = " TLBI operations"]
2497
    ARM64_TLBI_IPAS2LE1OS = 40,
2498
    #[doc = " TLBI operations"]
2499
    ARM64_TLBI_VAE2OS = 41,
2500
    #[doc = " TLBI operations"]
2501
    ARM64_TLBI_VALE2OS = 42,
2502
    #[doc = " TLBI operations"]
2503
    ARM64_TLBI_VMALLS12E1OS = 43,
2504
    #[doc = " TLBI operations"]
2505
    ARM64_TLBI_VAE3OS = 44,
2506
    #[doc = " TLBI operations"]
2507
    ARM64_TLBI_VALE3OS = 45,
2508
    #[doc = " TLBI operations"]
2509
    ARM64_TLBI_ALLE2OS = 46,
2510
    #[doc = " TLBI operations"]
2511
    ARM64_TLBI_ALLE1OS = 47,
2512
    #[doc = " TLBI operations"]
2513
    ARM64_TLBI_ALLE3OS = 48,
2514
    #[doc = " TLBI operations"]
2515
    ARM64_TLBI_RVAE1 = 49,
2516
    #[doc = " TLBI operations"]
2517
    ARM64_TLBI_RVAAE1 = 50,
2518
    #[doc = " TLBI operations"]
2519
    ARM64_TLBI_RVALE1 = 51,
2520
    #[doc = " TLBI operations"]
2521
    ARM64_TLBI_RVAALE1 = 52,
2522
    #[doc = " TLBI operations"]
2523
    ARM64_TLBI_RVAE1IS = 53,
2524
    #[doc = " TLBI operations"]
2525
    ARM64_TLBI_RVAAE1IS = 54,
2526
    #[doc = " TLBI operations"]
2527
    ARM64_TLBI_RVALE1IS = 55,
2528
    #[doc = " TLBI operations"]
2529
    ARM64_TLBI_RVAALE1IS = 56,
2530
    #[doc = " TLBI operations"]
2531
    ARM64_TLBI_RVAE1OS = 57,
2532
    #[doc = " TLBI operations"]
2533
    ARM64_TLBI_RVAAE1OS = 58,
2534
    #[doc = " TLBI operations"]
2535
    ARM64_TLBI_RVALE1OS = 59,
2536
    #[doc = " TLBI operations"]
2537
    ARM64_TLBI_RVAALE1OS = 60,
2538
    #[doc = " TLBI operations"]
2539
    ARM64_TLBI_RIPAS2E1IS = 61,
2540
    #[doc = " TLBI operations"]
2541
    ARM64_TLBI_RIPAS2LE1IS = 62,
2542
    #[doc = " TLBI operations"]
2543
    ARM64_TLBI_RIPAS2E1 = 63,
2544
    #[doc = " TLBI operations"]
2545
    ARM64_TLBI_RIPAS2LE1 = 64,
2546
    #[doc = " TLBI operations"]
2547
    ARM64_TLBI_RIPAS2E1OS = 65,
2548
    #[doc = " TLBI operations"]
2549
    ARM64_TLBI_RIPAS2LE1OS = 66,
2550
    #[doc = " TLBI operations"]
2551
    ARM64_TLBI_RVAE2 = 67,
2552
    #[doc = " TLBI operations"]
2553
    ARM64_TLBI_RVALE2 = 68,
2554
    #[doc = " TLBI operations"]
2555
    ARM64_TLBI_RVAE2IS = 69,
2556
    #[doc = " TLBI operations"]
2557
    ARM64_TLBI_RVALE2IS = 70,
2558
    #[doc = " TLBI operations"]
2559
    ARM64_TLBI_RVAE2OS = 71,
2560
    #[doc = " TLBI operations"]
2561
    ARM64_TLBI_RVALE2OS = 72,
2562
    #[doc = " TLBI operations"]
2563
    ARM64_TLBI_RVAE3 = 73,
2564
    #[doc = " TLBI operations"]
2565
    ARM64_TLBI_RVALE3 = 74,
2566
    #[doc = " TLBI operations"]
2567
    ARM64_TLBI_RVAE3IS = 75,
2568
    #[doc = " TLBI operations"]
2569
    ARM64_TLBI_RVALE3IS = 76,
2570
    #[doc = " TLBI operations"]
2571
    ARM64_TLBI_RVAE3OS = 77,
2572
    #[doc = " TLBI operations"]
2573
    ARM64_TLBI_RVALE3OS = 78,
2574
    #[doc = " AT operations"]
2575
    ARM64_AT_S1E1R = 79,
2576
    #[doc = " AT operations"]
2577
    ARM64_AT_S1E2R = 80,
2578
    #[doc = " AT operations"]
2579
    ARM64_AT_S1E3R = 81,
2580
    #[doc = " AT operations"]
2581
    ARM64_AT_S1E1W = 82,
2582
    #[doc = " AT operations"]
2583
    ARM64_AT_S1E2W = 83,
2584
    #[doc = " AT operations"]
2585
    ARM64_AT_S1E3W = 84,
2586
    #[doc = " AT operations"]
2587
    ARM64_AT_S1E0R = 85,
2588
    #[doc = " AT operations"]
2589
    ARM64_AT_S1E0W = 86,
2590
    #[doc = " AT operations"]
2591
    ARM64_AT_S12E1R = 87,
2592
    #[doc = " AT operations"]
2593
    ARM64_AT_S12E1W = 88,
2594
    #[doc = " AT operations"]
2595
    ARM64_AT_S12E0R = 89,
2596
    #[doc = " AT operations"]
2597
    ARM64_AT_S12E0W = 90,
2598
    #[doc = " AT operations"]
2599
    ARM64_AT_S1E1RP = 91,
2600
    #[doc = " AT operations"]
2601
    ARM64_AT_S1E1WP = 92,
2602
    #[doc = " DC operations"]
2603
    ARM64_DC_ZVA = 93,
2604
    #[doc = " DC operations"]
2605
    ARM64_DC_IVAC = 94,
2606
    #[doc = " DC operations"]
2607
    ARM64_DC_ISW = 95,
2608
    #[doc = " DC operations"]
2609
    ARM64_DC_CVAC = 96,
2610
    #[doc = " DC operations"]
2611
    ARM64_DC_CSW = 97,
2612
    #[doc = " DC operations"]
2613
    ARM64_DC_CVAU = 98,
2614
    #[doc = " DC operations"]
2615
    ARM64_DC_CIVAC = 99,
2616
    #[doc = " DC operations"]
2617
    ARM64_DC_CISW = 100,
2618
    #[doc = " DC operations"]
2619
    ARM64_DC_CVAP = 101,
2620
    #[doc = " IC operations"]
2621
    ARM64_IC_IALLUIS = 102,
2622
    #[doc = " IC operations"]
2623
    ARM64_IC_IALLU = 103,
2624
    #[doc = " IC operations"]
2625
    ARM64_IC_IVAU = 104,
2626
}
2627
#[repr(u32)]
2628
#[doc = " Prefetch operations (PRFM)"]
2629
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2630
pub enum arm64_prefetch_op {
2631
    ARM64_PRFM_INVALID = 0,
2632
    ARM64_PRFM_PLDL1KEEP = 1,
2633
    ARM64_PRFM_PLDL1STRM = 2,
2634
    ARM64_PRFM_PLDL2KEEP = 3,
2635
    ARM64_PRFM_PLDL2STRM = 4,
2636
    ARM64_PRFM_PLDL3KEEP = 5,
2637
    ARM64_PRFM_PLDL3STRM = 6,
2638
    ARM64_PRFM_PLIL1KEEP = 9,
2639
    ARM64_PRFM_PLIL1STRM = 10,
2640
    ARM64_PRFM_PLIL2KEEP = 11,
2641
    ARM64_PRFM_PLIL2STRM = 12,
2642
    ARM64_PRFM_PLIL3KEEP = 13,
2643
    ARM64_PRFM_PLIL3STRM = 14,
2644
    ARM64_PRFM_PSTL1KEEP = 17,
2645
    ARM64_PRFM_PSTL1STRM = 18,
2646
    ARM64_PRFM_PSTL2KEEP = 19,
2647
    ARM64_PRFM_PSTL2STRM = 20,
2648
    ARM64_PRFM_PSTL3KEEP = 21,
2649
    ARM64_PRFM_PSTL3STRM = 22,
2650
}
2651
pub mod arm64_reg {
2652
    #[doc = " ARM64 registers"]
2653
    pub type Type = libc::c_uint;
2654
    pub const ARM64_REG_INVALID: Type = 0;
2655
    pub const ARM64_REG_FFR: Type = 1;
2656
    pub const ARM64_REG_FP: Type = 2;
2657
    pub const ARM64_REG_LR: Type = 3;
2658
    pub const ARM64_REG_NZCV: Type = 4;
2659
    pub const ARM64_REG_SP: Type = 5;
2660
    pub const ARM64_REG_WSP: Type = 6;
2661
    pub const ARM64_REG_WZR: Type = 7;
2662
    pub const ARM64_REG_XZR: Type = 8;
2663
    pub const ARM64_REG_B0: Type = 9;
2664
    pub const ARM64_REG_B1: Type = 10;
2665
    pub const ARM64_REG_B2: Type = 11;
2666
    pub const ARM64_REG_B3: Type = 12;
2667
    pub const ARM64_REG_B4: Type = 13;
2668
    pub const ARM64_REG_B5: Type = 14;
2669
    pub const ARM64_REG_B6: Type = 15;
2670
    pub const ARM64_REG_B7: Type = 16;
2671
    pub const ARM64_REG_B8: Type = 17;
2672
    pub const ARM64_REG_B9: Type = 18;
2673
    pub const ARM64_REG_B10: Type = 19;
2674
    pub const ARM64_REG_B11: Type = 20;
2675
    pub const ARM64_REG_B12: Type = 21;
2676
    pub const ARM64_REG_B13: Type = 22;
2677
    pub const ARM64_REG_B14: Type = 23;
2678
    pub const ARM64_REG_B15: Type = 24;
2679
    pub const ARM64_REG_B16: Type = 25;
2680
    pub const ARM64_REG_B17: Type = 26;
2681
    pub const ARM64_REG_B18: Type = 27;
2682
    pub const ARM64_REG_B19: Type = 28;
2683
    pub const ARM64_REG_B20: Type = 29;
2684
    pub const ARM64_REG_B21: Type = 30;
2685
    pub const ARM64_REG_B22: Type = 31;
2686
    pub const ARM64_REG_B23: Type = 32;
2687
    pub const ARM64_REG_B24: Type = 33;
2688
    pub const ARM64_REG_B25: Type = 34;
2689
    pub const ARM64_REG_B26: Type = 35;
2690
    pub const ARM64_REG_B27: Type = 36;
2691
    pub const ARM64_REG_B28: Type = 37;
2692
    pub const ARM64_REG_B29: Type = 38;
2693
    pub const ARM64_REG_B30: Type = 39;
2694
    pub const ARM64_REG_B31: Type = 40;
2695
    pub const ARM64_REG_D0: Type = 41;
2696
    pub const ARM64_REG_D1: Type = 42;
2697
    pub const ARM64_REG_D2: Type = 43;
2698
    pub const ARM64_REG_D3: Type = 44;
2699
    pub const ARM64_REG_D4: Type = 45;
2700
    pub const ARM64_REG_D5: Type = 46;
2701
    pub const ARM64_REG_D6: Type = 47;
2702
    pub const ARM64_REG_D7: Type = 48;
2703
    pub const ARM64_REG_D8: Type = 49;
2704
    pub const ARM64_REG_D9: Type = 50;
2705
    pub const ARM64_REG_D10: Type = 51;
2706
    pub const ARM64_REG_D11: Type = 52;
2707
    pub const ARM64_REG_D12: Type = 53;
2708
    pub const ARM64_REG_D13: Type = 54;
2709
    pub const ARM64_REG_D14: Type = 55;
2710
    pub const ARM64_REG_D15: Type = 56;
2711
    pub const ARM64_REG_D16: Type = 57;
2712
    pub const ARM64_REG_D17: Type = 58;
2713
    pub const ARM64_REG_D18: Type = 59;
2714
    pub const ARM64_REG_D19: Type = 60;
2715
    pub const ARM64_REG_D20: Type = 61;
2716
    pub const ARM64_REG_D21: Type = 62;
2717
    pub const ARM64_REG_D22: Type = 63;
2718
    pub const ARM64_REG_D23: Type = 64;
2719
    pub const ARM64_REG_D24: Type = 65;
2720
    pub const ARM64_REG_D25: Type = 66;
2721
    pub const ARM64_REG_D26: Type = 67;
2722
    pub const ARM64_REG_D27: Type = 68;
2723
    pub const ARM64_REG_D28: Type = 69;
2724
    pub const ARM64_REG_D29: Type = 70;
2725
    pub const ARM64_REG_D30: Type = 71;
2726
    pub const ARM64_REG_D31: Type = 72;
2727
    pub const ARM64_REG_H0: Type = 73;
2728
    pub const ARM64_REG_H1: Type = 74;
2729
    pub const ARM64_REG_H2: Type = 75;
2730
    pub const ARM64_REG_H3: Type = 76;
2731
    pub const ARM64_REG_H4: Type = 77;
2732
    pub const ARM64_REG_H5: Type = 78;
2733
    pub const ARM64_REG_H6: Type = 79;
2734
    pub const ARM64_REG_H7: Type = 80;
2735
    pub const ARM64_REG_H8: Type = 81;
2736
    pub const ARM64_REG_H9: Type = 82;
2737
    pub const ARM64_REG_H10: Type = 83;
2738
    pub const ARM64_REG_H11: Type = 84;
2739
    pub const ARM64_REG_H12: Type = 85;
2740
    pub const ARM64_REG_H13: Type = 86;
2741
    pub const ARM64_REG_H14: Type = 87;
2742
    pub const ARM64_REG_H15: Type = 88;
2743
    pub const ARM64_REG_H16: Type = 89;
2744
    pub const ARM64_REG_H17: Type = 90;
2745
    pub const ARM64_REG_H18: Type = 91;
2746
    pub const ARM64_REG_H19: Type = 92;
2747
    pub const ARM64_REG_H20: Type = 93;
2748
    pub const ARM64_REG_H21: Type = 94;
2749
    pub const ARM64_REG_H22: Type = 95;
2750
    pub const ARM64_REG_H23: Type = 96;
2751
    pub const ARM64_REG_H24: Type = 97;
2752
    pub const ARM64_REG_H25: Type = 98;
2753
    pub const ARM64_REG_H26: Type = 99;
2754
    pub const ARM64_REG_H27: Type = 100;
2755
    pub const ARM64_REG_H28: Type = 101;
2756
    pub const ARM64_REG_H29: Type = 102;
2757
    pub const ARM64_REG_H30: Type = 103;
2758
    pub const ARM64_REG_H31: Type = 104;
2759
    pub const ARM64_REG_P0: Type = 105;
2760
    pub const ARM64_REG_P1: Type = 106;
2761
    pub const ARM64_REG_P2: Type = 107;
2762
    pub const ARM64_REG_P3: Type = 108;
2763
    pub const ARM64_REG_P4: Type = 109;
2764
    pub const ARM64_REG_P5: Type = 110;
2765
    pub const ARM64_REG_P6: Type = 111;
2766
    pub const ARM64_REG_P7: Type = 112;
2767
    pub const ARM64_REG_P8: Type = 113;
2768
    pub const ARM64_REG_P9: Type = 114;
2769
    pub const ARM64_REG_P10: Type = 115;
2770
    pub const ARM64_REG_P11: Type = 116;
2771
    pub const ARM64_REG_P12: Type = 117;
2772
    pub const ARM64_REG_P13: Type = 118;
2773
    pub const ARM64_REG_P14: Type = 119;
2774
    pub const ARM64_REG_P15: Type = 120;
2775
    pub const ARM64_REG_Q0: Type = 121;
2776
    pub const ARM64_REG_Q1: Type = 122;
2777
    pub const ARM64_REG_Q2: Type = 123;
2778
    pub const ARM64_REG_Q3: Type = 124;
2779
    pub const ARM64_REG_Q4: Type = 125;
2780
    pub const ARM64_REG_Q5: Type = 126;
2781
    pub const ARM64_REG_Q6: Type = 127;
2782
    pub const ARM64_REG_Q7: Type = 128;
2783
    pub const ARM64_REG_Q8: Type = 129;
2784
    pub const ARM64_REG_Q9: Type = 130;
2785
    pub const ARM64_REG_Q10: Type = 131;
2786
    pub const ARM64_REG_Q11: Type = 132;
2787
    pub const ARM64_REG_Q12: Type = 133;
2788
    pub const ARM64_REG_Q13: Type = 134;
2789
    pub const ARM64_REG_Q14: Type = 135;
2790
    pub const ARM64_REG_Q15: Type = 136;
2791
    pub const ARM64_REG_Q16: Type = 137;
2792
    pub const ARM64_REG_Q17: Type = 138;
2793
    pub const ARM64_REG_Q18: Type = 139;
2794
    pub const ARM64_REG_Q19: Type = 140;
2795
    pub const ARM64_REG_Q20: Type = 141;
2796
    pub const ARM64_REG_Q21: Type = 142;
2797
    pub const ARM64_REG_Q22: Type = 143;
2798
    pub const ARM64_REG_Q23: Type = 144;
2799
    pub const ARM64_REG_Q24: Type = 145;
2800
    pub const ARM64_REG_Q25: Type = 146;
2801
    pub const ARM64_REG_Q26: Type = 147;
2802
    pub const ARM64_REG_Q27: Type = 148;
2803
    pub const ARM64_REG_Q28: Type = 149;
2804
    pub const ARM64_REG_Q29: Type = 150;
2805
    pub const ARM64_REG_Q30: Type = 151;
2806
    pub const ARM64_REG_Q31: Type = 152;
2807
    pub const ARM64_REG_S0: Type = 153;
2808
    pub const ARM64_REG_S1: Type = 154;
2809
    pub const ARM64_REG_S2: Type = 155;
2810
    pub const ARM64_REG_S3: Type = 156;
2811
    pub const ARM64_REG_S4: Type = 157;
2812
    pub const ARM64_REG_S5: Type = 158;
2813
    pub const ARM64_REG_S6: Type = 159;
2814
    pub const ARM64_REG_S7: Type = 160;
2815
    pub const ARM64_REG_S8: Type = 161;
2816
    pub const ARM64_REG_S9: Type = 162;
2817
    pub const ARM64_REG_S10: Type = 163;
2818
    pub const ARM64_REG_S11: Type = 164;
2819
    pub const ARM64_REG_S12: Type = 165;
2820
    pub const ARM64_REG_S13: Type = 166;
2821
    pub const ARM64_REG_S14: Type = 167;
2822
    pub const ARM64_REG_S15: Type = 168;
2823
    pub const ARM64_REG_S16: Type = 169;
2824
    pub const ARM64_REG_S17: Type = 170;
2825
    pub const ARM64_REG_S18: Type = 171;
2826
    pub const ARM64_REG_S19: Type = 172;
2827
    pub const ARM64_REG_S20: Type = 173;
2828
    pub const ARM64_REG_S21: Type = 174;
2829
    pub const ARM64_REG_S22: Type = 175;
2830
    pub const ARM64_REG_S23: Type = 176;
2831
    pub const ARM64_REG_S24: Type = 177;
2832
    pub const ARM64_REG_S25: Type = 178;
2833
    pub const ARM64_REG_S26: Type = 179;
2834
    pub const ARM64_REG_S27: Type = 180;
2835
    pub const ARM64_REG_S28: Type = 181;
2836
    pub const ARM64_REG_S29: Type = 182;
2837
    pub const ARM64_REG_S30: Type = 183;
2838
    pub const ARM64_REG_S31: Type = 184;
2839
    pub const ARM64_REG_W0: Type = 185;
2840
    pub const ARM64_REG_W1: Type = 186;
2841
    pub const ARM64_REG_W2: Type = 187;
2842
    pub const ARM64_REG_W3: Type = 188;
2843
    pub const ARM64_REG_W4: Type = 189;
2844
    pub const ARM64_REG_W5: Type = 190;
2845
    pub const ARM64_REG_W6: Type = 191;
2846
    pub const ARM64_REG_W7: Type = 192;
2847
    pub const ARM64_REG_W8: Type = 193;
2848
    pub const ARM64_REG_W9: Type = 194;
2849
    pub const ARM64_REG_W10: Type = 195;
2850
    pub const ARM64_REG_W11: Type = 196;
2851
    pub const ARM64_REG_W12: Type = 197;
2852
    pub const ARM64_REG_W13: Type = 198;
2853
    pub const ARM64_REG_W14: Type = 199;
2854
    pub const ARM64_REG_W15: Type = 200;
2855
    pub const ARM64_REG_W16: Type = 201;
2856
    pub const ARM64_REG_W17: Type = 202;
2857
    pub const ARM64_REG_W18: Type = 203;
2858
    pub const ARM64_REG_W19: Type = 204;
2859
    pub const ARM64_REG_W20: Type = 205;
2860
    pub const ARM64_REG_W21: Type = 206;
2861
    pub const ARM64_REG_W22: Type = 207;
2862
    pub const ARM64_REG_W23: Type = 208;
2863
    pub const ARM64_REG_W24: Type = 209;
2864
    pub const ARM64_REG_W25: Type = 210;
2865
    pub const ARM64_REG_W26: Type = 211;
2866
    pub const ARM64_REG_W27: Type = 212;
2867
    pub const ARM64_REG_W28: Type = 213;
2868
    pub const ARM64_REG_W29: Type = 214;
2869
    pub const ARM64_REG_W30: Type = 215;
2870
    pub const ARM64_REG_X0: Type = 216;
2871
    pub const ARM64_REG_X1: Type = 217;
2872
    pub const ARM64_REG_X2: Type = 218;
2873
    pub const ARM64_REG_X3: Type = 219;
2874
    pub const ARM64_REG_X4: Type = 220;
2875
    pub const ARM64_REG_X5: Type = 221;
2876
    pub const ARM64_REG_X6: Type = 222;
2877
    pub const ARM64_REG_X7: Type = 223;
2878
    pub const ARM64_REG_X8: Type = 224;
2879
    pub const ARM64_REG_X9: Type = 225;
2880
    pub const ARM64_REG_X10: Type = 226;
2881
    pub const ARM64_REG_X11: Type = 227;
2882
    pub const ARM64_REG_X12: Type = 228;
2883
    pub const ARM64_REG_X13: Type = 229;
2884
    pub const ARM64_REG_X14: Type = 230;
2885
    pub const ARM64_REG_X15: Type = 231;
2886
    pub const ARM64_REG_X16: Type = 232;
2887
    pub const ARM64_REG_X17: Type = 233;
2888
    pub const ARM64_REG_X18: Type = 234;
2889
    pub const ARM64_REG_X19: Type = 235;
2890
    pub const ARM64_REG_X20: Type = 236;
2891
    pub const ARM64_REG_X21: Type = 237;
2892
    pub const ARM64_REG_X22: Type = 238;
2893
    pub const ARM64_REG_X23: Type = 239;
2894
    pub const ARM64_REG_X24: Type = 240;
2895
    pub const ARM64_REG_X25: Type = 241;
2896
    pub const ARM64_REG_X26: Type = 242;
2897
    pub const ARM64_REG_X27: Type = 243;
2898
    pub const ARM64_REG_X28: Type = 244;
2899
    pub const ARM64_REG_Z0: Type = 245;
2900
    pub const ARM64_REG_Z1: Type = 246;
2901
    pub const ARM64_REG_Z2: Type = 247;
2902
    pub const ARM64_REG_Z3: Type = 248;
2903
    pub const ARM64_REG_Z4: Type = 249;
2904
    pub const ARM64_REG_Z5: Type = 250;
2905
    pub const ARM64_REG_Z6: Type = 251;
2906
    pub const ARM64_REG_Z7: Type = 252;
2907
    pub const ARM64_REG_Z8: Type = 253;
2908
    pub const ARM64_REG_Z9: Type = 254;
2909
    pub const ARM64_REG_Z10: Type = 255;
2910
    pub const ARM64_REG_Z11: Type = 256;
2911
    pub const ARM64_REG_Z12: Type = 257;
2912
    pub const ARM64_REG_Z13: Type = 258;
2913
    pub const ARM64_REG_Z14: Type = 259;
2914
    pub const ARM64_REG_Z15: Type = 260;
2915
    pub const ARM64_REG_Z16: Type = 261;
2916
    pub const ARM64_REG_Z17: Type = 262;
2917
    pub const ARM64_REG_Z18: Type = 263;
2918
    pub const ARM64_REG_Z19: Type = 264;
2919
    pub const ARM64_REG_Z20: Type = 265;
2920
    pub const ARM64_REG_Z21: Type = 266;
2921
    pub const ARM64_REG_Z22: Type = 267;
2922
    pub const ARM64_REG_Z23: Type = 268;
2923
    pub const ARM64_REG_Z24: Type = 269;
2924
    pub const ARM64_REG_Z25: Type = 270;
2925
    pub const ARM64_REG_Z26: Type = 271;
2926
    pub const ARM64_REG_Z27: Type = 272;
2927
    pub const ARM64_REG_Z28: Type = 273;
2928
    pub const ARM64_REG_Z29: Type = 274;
2929
    pub const ARM64_REG_Z30: Type = 275;
2930
    pub const ARM64_REG_Z31: Type = 276;
2931
    pub const ARM64_REG_V0: Type = 277;
2932
    pub const ARM64_REG_V1: Type = 278;
2933
    pub const ARM64_REG_V2: Type = 279;
2934
    pub const ARM64_REG_V3: Type = 280;
2935
    pub const ARM64_REG_V4: Type = 281;
2936
    pub const ARM64_REG_V5: Type = 282;
2937
    pub const ARM64_REG_V6: Type = 283;
2938
    pub const ARM64_REG_V7: Type = 284;
2939
    pub const ARM64_REG_V8: Type = 285;
2940
    pub const ARM64_REG_V9: Type = 286;
2941
    pub const ARM64_REG_V10: Type = 287;
2942
    pub const ARM64_REG_V11: Type = 288;
2943
    pub const ARM64_REG_V12: Type = 289;
2944
    pub const ARM64_REG_V13: Type = 290;
2945
    pub const ARM64_REG_V14: Type = 291;
2946
    pub const ARM64_REG_V15: Type = 292;
2947
    pub const ARM64_REG_V16: Type = 293;
2948
    pub const ARM64_REG_V17: Type = 294;
2949
    pub const ARM64_REG_V18: Type = 295;
2950
    pub const ARM64_REG_V19: Type = 296;
2951
    pub const ARM64_REG_V20: Type = 297;
2952
    pub const ARM64_REG_V21: Type = 298;
2953
    pub const ARM64_REG_V22: Type = 299;
2954
    pub const ARM64_REG_V23: Type = 300;
2955
    pub const ARM64_REG_V24: Type = 301;
2956
    pub const ARM64_REG_V25: Type = 302;
2957
    pub const ARM64_REG_V26: Type = 303;
2958
    pub const ARM64_REG_V27: Type = 304;
2959
    pub const ARM64_REG_V28: Type = 305;
2960
    pub const ARM64_REG_V29: Type = 306;
2961
    pub const ARM64_REG_V30: Type = 307;
2962
    pub const ARM64_REG_V31: Type = 308;
2963
    pub const ARM64_REG_ENDING: Type = 309;
2964
    pub const ARM64_REG_IP0: Type = 232;
2965
    pub const ARM64_REG_IP1: Type = 233;
2966
    pub const ARM64_REG_X29: Type = 2;
2967
    pub const ARM64_REG_X30: Type = 3;
2968
}
2969
#[doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"]
2970
#[repr(C)]
2971
#[derive(Debug, Copy, Clone)]
2972
pub struct arm64_op_mem {
2973
    #[doc = "< base register"]
2974
    pub base: arm64_reg::Type,
2975
    #[doc = "< index register"]
2976
    pub index: arm64_reg::Type,
2977
    #[doc = "< displacement/offset value"]
2978
    pub disp: i32,
2979
}
2980
#[doc = " Instruction operand"]
2981
#[repr(C)]
2982
#[derive(Copy, Clone)]
2983
pub struct cs_arm64_op {
2984
    #[doc = "< Vector Index for some vector operands (or -1 if irrelevant)"]
2985
    pub vector_index: libc::c_int,
2986
    #[doc = "< Vector Arrangement Specifier"]
2987
    pub vas: arm64_vas,
2988
    pub shift: cs_arm64_op__bindgen_ty_1,
2989
    #[doc = "< extender type of this operand"]
2990
    pub ext: arm64_extender,
2991
    #[doc = "< operand type"]
2992
    pub type_: arm64_op_type,
2993
    pub __bindgen_anon_1: cs_arm64_op__bindgen_ty_2,
2994
    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."]
2995
    pub access: u8,
2996
}
2997
#[repr(C)]
2998
#[derive(Debug, Copy, Clone)]
2999
pub struct cs_arm64_op__bindgen_ty_1 {
3000
    #[doc = "< shifter type of this operand"]
3001
    pub type_: arm64_shifter,
3002
    #[doc = "< shifter value of this operand"]
3003
    pub value: libc::c_uint,
3004
}
3005
#[repr(C)]
3006
#[derive(Copy, Clone)]
3007
pub union cs_arm64_op__bindgen_ty_2 {
3008
    #[doc = "< register value for REG operand"]
3009
    pub reg: arm64_reg::Type,
3010
    #[doc = "< immediate value, or index for C-IMM or IMM operand"]
3011
    pub imm: i64,
3012
    #[doc = "< floating point value for FP operand"]
3013
    pub fp: f64,
3014
    #[doc = "< base/index/scale/disp value for MEM operand"]
3015
    pub mem: arm64_op_mem,
3016
    #[doc = "< PState field of MSR instruction."]
3017
    pub pstate: arm64_pstate,
3018
    #[doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)"]
3019
    pub sys: arm64_sys_op,
3020
    #[doc = "< PRFM operation."]
3021
    pub prefetch: arm64_prefetch_op,
3022
    #[doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."]
3023
    pub barrier: arm64_barrier_op,
3024
}
3025
impl ::core::fmt::Debug for cs_arm64_op__bindgen_ty_2 {
3026
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
3027
0
        write!(f, "cs_arm64_op__bindgen_ty_2 {{ union }}")
3028
0
    }
3029
}
3030
impl ::core::fmt::Debug for cs_arm64_op {
3031
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
3032
0
        write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, __bindgen_anon_1: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . __bindgen_anon_1)
3033
0
    }
3034
}
3035
#[doc = " Instruction structure"]
3036
#[repr(C)]
3037
#[derive(Copy, Clone)]
3038
pub struct cs_arm64 {
3039
    #[doc = "< conditional code for this insn"]
3040
    pub cc: arm64_cc,
3041
    #[doc = "< does this insn update flags?"]
3042
    pub update_flags: bool,
3043
    #[doc = "< does this insn request writeback? 'True' means 'yes'"]
3044
    pub writeback: bool,
3045
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
3046
    pub op_count: u8,
3047
    #[doc = "< operands for this instruction."]
3048
    pub operands: [cs_arm64_op; 8usize],
3049
}
3050
impl ::core::fmt::Debug for cs_arm64 {
3051
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
3052
0
        write!(
3053
0
            f,
3054
0
            "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, operands: {:?} }}",
3055
            self.cc, self.update_flags, self.writeback, self.operands
3056
        )
3057
0
    }
3058
}
3059
#[repr(u32)]
3060
#[doc = " ARM64 instruction"]
3061
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
3062
pub enum arm64_insn {
3063
    ARM64_INS_INVALID = 0,
3064
    ARM64_INS_ABS = 1,
3065
    ARM64_INS_ADC = 2,
3066
    ARM64_INS_ADCS = 3,
3067
    ARM64_INS_ADD = 4,
3068
    ARM64_INS_ADDHN = 5,
3069
    ARM64_INS_ADDHN2 = 6,
3070
    ARM64_INS_ADDP = 7,
3071
    ARM64_INS_ADDPL = 8,
3072
    ARM64_INS_ADDS = 9,
3073
    ARM64_INS_ADDV = 10,
3074
    ARM64_INS_ADDVL = 11,
3075
    ARM64_INS_ADR = 12,
3076
    ARM64_INS_ADRP = 13,
3077
    ARM64_INS_AESD = 14,
3078
    ARM64_INS_AESE = 15,
3079
    ARM64_INS_AESIMC = 16,
3080
    ARM64_INS_AESMC = 17,
3081
    ARM64_INS_AND = 18,
3082
    ARM64_INS_ANDS = 19,
3083
    ARM64_INS_ANDV = 20,
3084
    ARM64_INS_ASR = 21,
3085
    ARM64_INS_ASRD = 22,
3086
    ARM64_INS_ASRR = 23,
3087
    ARM64_INS_ASRV = 24,
3088
    ARM64_INS_AUTDA = 25,
3089
    ARM64_INS_AUTDB = 26,
3090
    ARM64_INS_AUTDZA = 27,
3091
    ARM64_INS_AUTDZB = 28,
3092
    ARM64_INS_AUTIA = 29,
3093
    ARM64_INS_AUTIA1716 = 30,
3094
    ARM64_INS_AUTIASP = 31,
3095
    ARM64_INS_AUTIAZ = 32,
3096
    ARM64_INS_AUTIB = 33,
3097
    ARM64_INS_AUTIB1716 = 34,
3098
    ARM64_INS_AUTIBSP = 35,
3099
    ARM64_INS_AUTIBZ = 36,
3100
    ARM64_INS_AUTIZA = 37,
3101
    ARM64_INS_AUTIZB = 38,
3102
    ARM64_INS_B = 39,
3103
    ARM64_INS_BCAX = 40,
3104
    ARM64_INS_BFM = 41,
3105
    ARM64_INS_BIC = 42,
3106
    ARM64_INS_BICS = 43,
3107
    ARM64_INS_BIF = 44,
3108
    ARM64_INS_BIT = 45,
3109
    ARM64_INS_BL = 46,
3110
    ARM64_INS_BLR = 47,
3111
    ARM64_INS_BLRAA = 48,
3112
    ARM64_INS_BLRAAZ = 49,
3113
    ARM64_INS_BLRAB = 50,
3114
    ARM64_INS_BLRABZ = 51,
3115
    ARM64_INS_BR = 52,
3116
    ARM64_INS_BRAA = 53,
3117
    ARM64_INS_BRAAZ = 54,
3118
    ARM64_INS_BRAB = 55,
3119
    ARM64_INS_BRABZ = 56,
3120
    ARM64_INS_BRK = 57,
3121
    ARM64_INS_BRKA = 58,
3122
    ARM64_INS_BRKAS = 59,
3123
    ARM64_INS_BRKB = 60,
3124
    ARM64_INS_BRKBS = 61,
3125
    ARM64_INS_BRKN = 62,
3126
    ARM64_INS_BRKNS = 63,
3127
    ARM64_INS_BRKPA = 64,
3128
    ARM64_INS_BRKPAS = 65,
3129
    ARM64_INS_BRKPB = 66,
3130
    ARM64_INS_BRKPBS = 67,
3131
    ARM64_INS_BSL = 68,
3132
    ARM64_INS_CAS = 69,
3133
    ARM64_INS_CASA = 70,
3134
    ARM64_INS_CASAB = 71,
3135
    ARM64_INS_CASAH = 72,
3136
    ARM64_INS_CASAL = 73,
3137
    ARM64_INS_CASALB = 74,
3138
    ARM64_INS_CASALH = 75,
3139
    ARM64_INS_CASB = 76,
3140
    ARM64_INS_CASH = 77,
3141
    ARM64_INS_CASL = 78,
3142
    ARM64_INS_CASLB = 79,
3143
    ARM64_INS_CASLH = 80,
3144
    ARM64_INS_CASP = 81,
3145
    ARM64_INS_CASPA = 82,
3146
    ARM64_INS_CASPAL = 83,
3147
    ARM64_INS_CASPL = 84,
3148
    ARM64_INS_CBNZ = 85,
3149
    ARM64_INS_CBZ = 86,
3150
    ARM64_INS_CCMN = 87,
3151
    ARM64_INS_CCMP = 88,
3152
    ARM64_INS_CFINV = 89,
3153
    ARM64_INS_CINC = 90,
3154
    ARM64_INS_CINV = 91,
3155
    ARM64_INS_CLASTA = 92,
3156
    ARM64_INS_CLASTB = 93,
3157
    ARM64_INS_CLREX = 94,
3158
    ARM64_INS_CLS = 95,
3159
    ARM64_INS_CLZ = 96,
3160
    ARM64_INS_CMEQ = 97,
3161
    ARM64_INS_CMGE = 98,
3162
    ARM64_INS_CMGT = 99,
3163
    ARM64_INS_CMHI = 100,
3164
    ARM64_INS_CMHS = 101,
3165
    ARM64_INS_CMLE = 102,
3166
    ARM64_INS_CMLO = 103,
3167
    ARM64_INS_CMLS = 104,
3168
    ARM64_INS_CMLT = 105,
3169
    ARM64_INS_CMN = 106,
3170
    ARM64_INS_CMP = 107,
3171
    ARM64_INS_CMPEQ = 108,
3172
    ARM64_INS_CMPGE = 109,
3173
    ARM64_INS_CMPGT = 110,
3174
    ARM64_INS_CMPHI = 111,
3175
    ARM64_INS_CMPHS = 112,
3176
    ARM64_INS_CMPLE = 113,
3177
    ARM64_INS_CMPLO = 114,
3178
    ARM64_INS_CMPLS = 115,
3179
    ARM64_INS_CMPLT = 116,
3180
    ARM64_INS_CMPNE = 117,
3181
    ARM64_INS_CMTST = 118,
3182
    ARM64_INS_CNEG = 119,
3183
    ARM64_INS_CNOT = 120,
3184
    ARM64_INS_CNT = 121,
3185
    ARM64_INS_CNTB = 122,
3186
    ARM64_INS_CNTD = 123,
3187
    ARM64_INS_CNTH = 124,
3188
    ARM64_INS_CNTP = 125,
3189
    ARM64_INS_CNTW = 126,
3190
    ARM64_INS_COMPACT = 127,
3191
    ARM64_INS_CPY = 128,
3192
    ARM64_INS_CRC32B = 129,
3193
    ARM64_INS_CRC32CB = 130,
3194
    ARM64_INS_CRC32CH = 131,
3195
    ARM64_INS_CRC32CW = 132,
3196
    ARM64_INS_CRC32CX = 133,
3197
    ARM64_INS_CRC32H = 134,
3198
    ARM64_INS_CRC32W = 135,
3199
    ARM64_INS_CRC32X = 136,
3200
    ARM64_INS_CSDB = 137,
3201
    ARM64_INS_CSEL = 138,
3202
    ARM64_INS_CSET = 139,
3203
    ARM64_INS_CSETM = 140,
3204
    ARM64_INS_CSINC = 141,
3205
    ARM64_INS_CSINV = 142,
3206
    ARM64_INS_CSNEG = 143,
3207
    ARM64_INS_CTERMEQ = 144,
3208
    ARM64_INS_CTERMNE = 145,
3209
    ARM64_INS_DCPS1 = 146,
3210
    ARM64_INS_DCPS2 = 147,
3211
    ARM64_INS_DCPS3 = 148,
3212
    ARM64_INS_DECB = 149,
3213
    ARM64_INS_DECD = 150,
3214
    ARM64_INS_DECH = 151,
3215
    ARM64_INS_DECP = 152,
3216
    ARM64_INS_DECW = 153,
3217
    ARM64_INS_DMB = 154,
3218
    ARM64_INS_DRPS = 155,
3219
    ARM64_INS_DSB = 156,
3220
    ARM64_INS_DUP = 157,
3221
    ARM64_INS_DUPM = 158,
3222
    ARM64_INS_EON = 159,
3223
    ARM64_INS_EOR = 160,
3224
    ARM64_INS_EOR3 = 161,
3225
    ARM64_INS_EORS = 162,
3226
    ARM64_INS_EORV = 163,
3227
    ARM64_INS_ERET = 164,
3228
    ARM64_INS_ERETAA = 165,
3229
    ARM64_INS_ERETAB = 166,
3230
    ARM64_INS_ESB = 167,
3231
    ARM64_INS_EXT = 168,
3232
    ARM64_INS_EXTR = 169,
3233
    ARM64_INS_FABD = 170,
3234
    ARM64_INS_FABS = 171,
3235
    ARM64_INS_FACGE = 172,
3236
    ARM64_INS_FACGT = 173,
3237
    ARM64_INS_FACLE = 174,
3238
    ARM64_INS_FACLT = 175,
3239
    ARM64_INS_FADD = 176,
3240
    ARM64_INS_FADDA = 177,
3241
    ARM64_INS_FADDP = 178,
3242
    ARM64_INS_FADDV = 179,
3243
    ARM64_INS_FCADD = 180,
3244
    ARM64_INS_FCCMP = 181,
3245
    ARM64_INS_FCCMPE = 182,
3246
    ARM64_INS_FCMEQ = 183,
3247
    ARM64_INS_FCMGE = 184,
3248
    ARM64_INS_FCMGT = 185,
3249
    ARM64_INS_FCMLA = 186,
3250
    ARM64_INS_FCMLE = 187,
3251
    ARM64_INS_FCMLT = 188,
3252
    ARM64_INS_FCMNE = 189,
3253
    ARM64_INS_FCMP = 190,
3254
    ARM64_INS_FCMPE = 191,
3255
    ARM64_INS_FCMUO = 192,
3256
    ARM64_INS_FCPY = 193,
3257
    ARM64_INS_FCSEL = 194,
3258
    ARM64_INS_FCVT = 195,
3259
    ARM64_INS_FCVTAS = 196,
3260
    ARM64_INS_FCVTAU = 197,
3261
    ARM64_INS_FCVTL = 198,
3262
    ARM64_INS_FCVTL2 = 199,
3263
    ARM64_INS_FCVTMS = 200,
3264
    ARM64_INS_FCVTMU = 201,
3265
    ARM64_INS_FCVTN = 202,
3266
    ARM64_INS_FCVTN2 = 203,
3267
    ARM64_INS_FCVTNS = 204,
3268
    ARM64_INS_FCVTNU = 205,
3269
    ARM64_INS_FCVTPS = 206,
3270
    ARM64_INS_FCVTPU = 207,
3271
    ARM64_INS_FCVTXN = 208,
3272
    ARM64_INS_FCVTXN2 = 209,
3273
    ARM64_INS_FCVTZS = 210,
3274
    ARM64_INS_FCVTZU = 211,
3275
    ARM64_INS_FDIV = 212,
3276
    ARM64_INS_FDIVR = 213,
3277
    ARM64_INS_FDUP = 214,
3278
    ARM64_INS_FEXPA = 215,
3279
    ARM64_INS_FJCVTZS = 216,
3280
    ARM64_INS_FMAD = 217,
3281
    ARM64_INS_FMADD = 218,
3282
    ARM64_INS_FMAX = 219,
3283
    ARM64_INS_FMAXNM = 220,
3284
    ARM64_INS_FMAXNMP = 221,
3285
    ARM64_INS_FMAXNMV = 222,
3286
    ARM64_INS_FMAXP = 223,
3287
    ARM64_INS_FMAXV = 224,
3288
    ARM64_INS_FMIN = 225,
3289
    ARM64_INS_FMINNM = 226,
3290
    ARM64_INS_FMINNMP = 227,
3291
    ARM64_INS_FMINNMV = 228,
3292
    ARM64_INS_FMINP = 229,
3293
    ARM64_INS_FMINV = 230,
3294
    ARM64_INS_FMLA = 231,
3295
    ARM64_INS_FMLS = 232,
3296
    ARM64_INS_FMOV = 233,
3297
    ARM64_INS_FMSB = 234,
3298
    ARM64_INS_FMSUB = 235,
3299
    ARM64_INS_FMUL = 236,
3300
    ARM64_INS_FMULX = 237,
3301
    ARM64_INS_FNEG = 238,
3302
    ARM64_INS_FNMAD = 239,
3303
    ARM64_INS_FNMADD = 240,
3304
    ARM64_INS_FNMLA = 241,
3305
    ARM64_INS_FNMLS = 242,
3306
    ARM64_INS_FNMSB = 243,
3307
    ARM64_INS_FNMSUB = 244,
3308
    ARM64_INS_FNMUL = 245,
3309
    ARM64_INS_FRECPE = 246,
3310
    ARM64_INS_FRECPS = 247,
3311
    ARM64_INS_FRECPX = 248,
3312
    ARM64_INS_FRINTA = 249,
3313
    ARM64_INS_FRINTI = 250,
3314
    ARM64_INS_FRINTM = 251,
3315
    ARM64_INS_FRINTN = 252,
3316
    ARM64_INS_FRINTP = 253,
3317
    ARM64_INS_FRINTX = 254,
3318
    ARM64_INS_FRINTZ = 255,
3319
    ARM64_INS_FRSQRTE = 256,
3320
    ARM64_INS_FRSQRTS = 257,
3321
    ARM64_INS_FSCALE = 258,
3322
    ARM64_INS_FSQRT = 259,
3323
    ARM64_INS_FSUB = 260,
3324
    ARM64_INS_FSUBR = 261,
3325
    ARM64_INS_FTMAD = 262,
3326
    ARM64_INS_FTSMUL = 263,
3327
    ARM64_INS_FTSSEL = 264,
3328
    ARM64_INS_HINT = 265,
3329
    ARM64_INS_HLT = 266,
3330
    ARM64_INS_HVC = 267,
3331
    ARM64_INS_INCB = 268,
3332
    ARM64_INS_INCD = 269,
3333
    ARM64_INS_INCH = 270,
3334
    ARM64_INS_INCP = 271,
3335
    ARM64_INS_INCW = 272,
3336
    ARM64_INS_INDEX = 273,
3337
    ARM64_INS_INS = 274,
3338
    ARM64_INS_INSR = 275,
3339
    ARM64_INS_ISB = 276,
3340
    ARM64_INS_LASTA = 277,
3341
    ARM64_INS_LASTB = 278,
3342
    ARM64_INS_LD1 = 279,
3343
    ARM64_INS_LD1B = 280,
3344
    ARM64_INS_LD1D = 281,
3345
    ARM64_INS_LD1H = 282,
3346
    ARM64_INS_LD1R = 283,
3347
    ARM64_INS_LD1RB = 284,
3348
    ARM64_INS_LD1RD = 285,
3349
    ARM64_INS_LD1RH = 286,
3350
    ARM64_INS_LD1RQB = 287,
3351
    ARM64_INS_LD1RQD = 288,
3352
    ARM64_INS_LD1RQH = 289,
3353
    ARM64_INS_LD1RQW = 290,
3354
    ARM64_INS_LD1RSB = 291,
3355
    ARM64_INS_LD1RSH = 292,
3356
    ARM64_INS_LD1RSW = 293,
3357
    ARM64_INS_LD1RW = 294,
3358
    ARM64_INS_LD1SB = 295,
3359
    ARM64_INS_LD1SH = 296,
3360
    ARM64_INS_LD1SW = 297,
3361
    ARM64_INS_LD1W = 298,
3362
    ARM64_INS_LD2 = 299,
3363
    ARM64_INS_LD2B = 300,
3364
    ARM64_INS_LD2D = 301,
3365
    ARM64_INS_LD2H = 302,
3366
    ARM64_INS_LD2R = 303,
3367
    ARM64_INS_LD2W = 304,
3368
    ARM64_INS_LD3 = 305,
3369
    ARM64_INS_LD3B = 306,
3370
    ARM64_INS_LD3D = 307,
3371
    ARM64_INS_LD3H = 308,
3372
    ARM64_INS_LD3R = 309,
3373
    ARM64_INS_LD3W = 310,
3374
    ARM64_INS_LD4 = 311,
3375
    ARM64_INS_LD4B = 312,
3376
    ARM64_INS_LD4D = 313,
3377
    ARM64_INS_LD4H = 314,
3378
    ARM64_INS_LD4R = 315,
3379
    ARM64_INS_LD4W = 316,
3380
    ARM64_INS_LDADD = 317,
3381
    ARM64_INS_LDADDA = 318,
3382
    ARM64_INS_LDADDAB = 319,
3383
    ARM64_INS_LDADDAH = 320,
3384
    ARM64_INS_LDADDAL = 321,
3385
    ARM64_INS_LDADDALB = 322,
3386
    ARM64_INS_LDADDALH = 323,
3387
    ARM64_INS_LDADDB = 324,
3388
    ARM64_INS_LDADDH = 325,
3389
    ARM64_INS_LDADDL = 326,
3390
    ARM64_INS_LDADDLB = 327,
3391
    ARM64_INS_LDADDLH = 328,
3392
    ARM64_INS_LDAPR = 329,
3393
    ARM64_INS_LDAPRB = 330,
3394
    ARM64_INS_LDAPRH = 331,
3395
    ARM64_INS_LDAPUR = 332,
3396
    ARM64_INS_LDAPURB = 333,
3397
    ARM64_INS_LDAPURH = 334,
3398
    ARM64_INS_LDAPURSB = 335,
3399
    ARM64_INS_LDAPURSH = 336,
3400
    ARM64_INS_LDAPURSW = 337,
3401
    ARM64_INS_LDAR = 338,
3402
    ARM64_INS_LDARB = 339,
3403
    ARM64_INS_LDARH = 340,
3404
    ARM64_INS_LDAXP = 341,
3405
    ARM64_INS_LDAXR = 342,
3406
    ARM64_INS_LDAXRB = 343,
3407
    ARM64_INS_LDAXRH = 344,
3408
    ARM64_INS_LDCLR = 345,
3409
    ARM64_INS_LDCLRA = 346,
3410
    ARM64_INS_LDCLRAB = 347,
3411
    ARM64_INS_LDCLRAH = 348,
3412
    ARM64_INS_LDCLRAL = 349,
3413
    ARM64_INS_LDCLRALB = 350,
3414
    ARM64_INS_LDCLRALH = 351,
3415
    ARM64_INS_LDCLRB = 352,
3416
    ARM64_INS_LDCLRH = 353,
3417
    ARM64_INS_LDCLRL = 354,
3418
    ARM64_INS_LDCLRLB = 355,
3419
    ARM64_INS_LDCLRLH = 356,
3420
    ARM64_INS_LDEOR = 357,
3421
    ARM64_INS_LDEORA = 358,
3422
    ARM64_INS_LDEORAB = 359,
3423
    ARM64_INS_LDEORAH = 360,
3424
    ARM64_INS_LDEORAL = 361,
3425
    ARM64_INS_LDEORALB = 362,
3426
    ARM64_INS_LDEORALH = 363,
3427
    ARM64_INS_LDEORB = 364,
3428
    ARM64_INS_LDEORH = 365,
3429
    ARM64_INS_LDEORL = 366,
3430
    ARM64_INS_LDEORLB = 367,
3431
    ARM64_INS_LDEORLH = 368,
3432
    ARM64_INS_LDFF1B = 369,
3433
    ARM64_INS_LDFF1D = 370,
3434
    ARM64_INS_LDFF1H = 371,
3435
    ARM64_INS_LDFF1SB = 372,
3436
    ARM64_INS_LDFF1SH = 373,
3437
    ARM64_INS_LDFF1SW = 374,
3438
    ARM64_INS_LDFF1W = 375,
3439
    ARM64_INS_LDLAR = 376,
3440
    ARM64_INS_LDLARB = 377,
3441
    ARM64_INS_LDLARH = 378,
3442
    ARM64_INS_LDNF1B = 379,
3443
    ARM64_INS_LDNF1D = 380,
3444
    ARM64_INS_LDNF1H = 381,
3445
    ARM64_INS_LDNF1SB = 382,
3446
    ARM64_INS_LDNF1SH = 383,
3447
    ARM64_INS_LDNF1SW = 384,
3448
    ARM64_INS_LDNF1W = 385,
3449
    ARM64_INS_LDNP = 386,
3450
    ARM64_INS_LDNT1B = 387,
3451
    ARM64_INS_LDNT1D = 388,
3452
    ARM64_INS_LDNT1H = 389,
3453
    ARM64_INS_LDNT1W = 390,
3454
    ARM64_INS_LDP = 391,
3455
    ARM64_INS_LDPSW = 392,
3456
    ARM64_INS_LDR = 393,
3457
    ARM64_INS_LDRAA = 394,
3458
    ARM64_INS_LDRAB = 395,
3459
    ARM64_INS_LDRB = 396,
3460
    ARM64_INS_LDRH = 397,
3461
    ARM64_INS_LDRSB = 398,
3462
    ARM64_INS_LDRSH = 399,
3463
    ARM64_INS_LDRSW = 400,
3464
    ARM64_INS_LDSET = 401,
3465
    ARM64_INS_LDSETA = 402,
3466
    ARM64_INS_LDSETAB = 403,
3467
    ARM64_INS_LDSETAH = 404,
3468
    ARM64_INS_LDSETAL = 405,
3469
    ARM64_INS_LDSETALB = 406,
3470
    ARM64_INS_LDSETALH = 407,
3471
    ARM64_INS_LDSETB = 408,
3472
    ARM64_INS_LDSETH = 409,
3473
    ARM64_INS_LDSETL = 410,
3474
    ARM64_INS_LDSETLB = 411,
3475
    ARM64_INS_LDSETLH = 412,
3476
    ARM64_INS_LDSMAX = 413,
3477
    ARM64_INS_LDSMAXA = 414,
3478
    ARM64_INS_LDSMAXAB = 415,
3479
    ARM64_INS_LDSMAXAH = 416,
3480
    ARM64_INS_LDSMAXAL = 417,
3481
    ARM64_INS_LDSMAXALB = 418,
3482
    ARM64_INS_LDSMAXALH = 419,
3483
    ARM64_INS_LDSMAXB = 420,
3484
    ARM64_INS_LDSMAXH = 421,
3485
    ARM64_INS_LDSMAXL = 422,
3486
    ARM64_INS_LDSMAXLB = 423,
3487
    ARM64_INS_LDSMAXLH = 424,
3488
    ARM64_INS_LDSMIN = 425,
3489
    ARM64_INS_LDSMINA = 426,
3490
    ARM64_INS_LDSMINAB = 427,
3491
    ARM64_INS_LDSMINAH = 428,
3492
    ARM64_INS_LDSMINAL = 429,
3493
    ARM64_INS_LDSMINALB = 430,
3494
    ARM64_INS_LDSMINALH = 431,
3495
    ARM64_INS_LDSMINB = 432,
3496
    ARM64_INS_LDSMINH = 433,
3497
    ARM64_INS_LDSMINL = 434,
3498
    ARM64_INS_LDSMINLB = 435,
3499
    ARM64_INS_LDSMINLH = 436,
3500
    ARM64_INS_LDTR = 437,
3501
    ARM64_INS_LDTRB = 438,
3502
    ARM64_INS_LDTRH = 439,
3503
    ARM64_INS_LDTRSB = 440,
3504
    ARM64_INS_LDTRSH = 441,
3505
    ARM64_INS_LDTRSW = 442,
3506
    ARM64_INS_LDUMAX = 443,
3507
    ARM64_INS_LDUMAXA = 444,
3508
    ARM64_INS_LDUMAXAB = 445,
3509
    ARM64_INS_LDUMAXAH = 446,
3510
    ARM64_INS_LDUMAXAL = 447,
3511
    ARM64_INS_LDUMAXALB = 448,
3512
    ARM64_INS_LDUMAXALH = 449,
3513
    ARM64_INS_LDUMAXB = 450,
3514
    ARM64_INS_LDUMAXH = 451,
3515
    ARM64_INS_LDUMAXL = 452,
3516
    ARM64_INS_LDUMAXLB = 453,
3517
    ARM64_INS_LDUMAXLH = 454,
3518
    ARM64_INS_LDUMIN = 455,
3519
    ARM64_INS_LDUMINA = 456,
3520
    ARM64_INS_LDUMINAB = 457,
3521
    ARM64_INS_LDUMINAH = 458,
3522
    ARM64_INS_LDUMINAL = 459,
3523
    ARM64_INS_LDUMINALB = 460,
3524
    ARM64_INS_LDUMINALH = 461,
3525
    ARM64_INS_LDUMINB = 462,
3526
    ARM64_INS_LDUMINH = 463,
3527
    ARM64_INS_LDUMINL = 464,
3528
    ARM64_INS_LDUMINLB = 465,
3529
    ARM64_INS_LDUMINLH = 466,
3530
    ARM64_INS_LDUR = 467,
3531
    ARM64_INS_LDURB = 468,
3532
    ARM64_INS_LDURH = 469,
3533
    ARM64_INS_LDURSB = 470,
3534
    ARM64_INS_LDURSH = 471,
3535
    ARM64_INS_LDURSW = 472,
3536
    ARM64_INS_LDXP = 473,
3537
    ARM64_INS_LDXR = 474,
3538
    ARM64_INS_LDXRB = 475,
3539
    ARM64_INS_LDXRH = 476,
3540
    ARM64_INS_LSL = 477,
3541
    ARM64_INS_LSLR = 478,
3542
    ARM64_INS_LSLV = 479,
3543
    ARM64_INS_LSR = 480,
3544
    ARM64_INS_LSRR = 481,
3545
    ARM64_INS_LSRV = 482,
3546
    ARM64_INS_MAD = 483,
3547
    ARM64_INS_MADD = 484,
3548
    ARM64_INS_MLA = 485,
3549
    ARM64_INS_MLS = 486,
3550
    ARM64_INS_MNEG = 487,
3551
    ARM64_INS_MOV = 488,
3552
    ARM64_INS_MOVI = 489,
3553
    ARM64_INS_MOVK = 490,
3554
    ARM64_INS_MOVN = 491,
3555
    ARM64_INS_MOVPRFX = 492,
3556
    ARM64_INS_MOVS = 493,
3557
    ARM64_INS_MOVZ = 494,
3558
    ARM64_INS_MRS = 495,
3559
    ARM64_INS_MSB = 496,
3560
    ARM64_INS_MSR = 497,
3561
    ARM64_INS_MSUB = 498,
3562
    ARM64_INS_MUL = 499,
3563
    ARM64_INS_MVN = 500,
3564
    ARM64_INS_MVNI = 501,
3565
    ARM64_INS_NAND = 502,
3566
    ARM64_INS_NANDS = 503,
3567
    ARM64_INS_NEG = 504,
3568
    ARM64_INS_NEGS = 505,
3569
    ARM64_INS_NGC = 506,
3570
    ARM64_INS_NGCS = 507,
3571
    ARM64_INS_NOP = 508,
3572
    ARM64_INS_NOR = 509,
3573
    ARM64_INS_NORS = 510,
3574
    ARM64_INS_NOT = 511,
3575
    ARM64_INS_NOTS = 512,
3576
    ARM64_INS_ORN = 513,
3577
    ARM64_INS_ORNS = 514,
3578
    ARM64_INS_ORR = 515,
3579
    ARM64_INS_ORRS = 516,
3580
    ARM64_INS_ORV = 517,
3581
    ARM64_INS_PACDA = 518,
3582
    ARM64_INS_PACDB = 519,
3583
    ARM64_INS_PACDZA = 520,
3584
    ARM64_INS_PACDZB = 521,
3585
    ARM64_INS_PACGA = 522,
3586
    ARM64_INS_PACIA = 523,
3587
    ARM64_INS_PACIA1716 = 524,
3588
    ARM64_INS_PACIASP = 525,
3589
    ARM64_INS_PACIAZ = 526,
3590
    ARM64_INS_PACIB = 527,
3591
    ARM64_INS_PACIB1716 = 528,
3592
    ARM64_INS_PACIBSP = 529,
3593
    ARM64_INS_PACIBZ = 530,
3594
    ARM64_INS_PACIZA = 531,
3595
    ARM64_INS_PACIZB = 532,
3596
    ARM64_INS_PFALSE = 533,
3597
    ARM64_INS_PFIRST = 534,
3598
    ARM64_INS_PMUL = 535,
3599
    ARM64_INS_PMULL = 536,
3600
    ARM64_INS_PMULL2 = 537,
3601
    ARM64_INS_PNEXT = 538,
3602
    ARM64_INS_PRFB = 539,
3603
    ARM64_INS_PRFD = 540,
3604
    ARM64_INS_PRFH = 541,
3605
    ARM64_INS_PRFM = 542,
3606
    ARM64_INS_PRFUM = 543,
3607
    ARM64_INS_PRFW = 544,
3608
    ARM64_INS_PSB = 545,
3609
    ARM64_INS_PTEST = 546,
3610
    ARM64_INS_PTRUE = 547,
3611
    ARM64_INS_PTRUES = 548,
3612
    ARM64_INS_PUNPKHI = 549,
3613
    ARM64_INS_PUNPKLO = 550,
3614
    ARM64_INS_RADDHN = 551,
3615
    ARM64_INS_RADDHN2 = 552,
3616
    ARM64_INS_RAX1 = 553,
3617
    ARM64_INS_RBIT = 554,
3618
    ARM64_INS_RDFFR = 555,
3619
    ARM64_INS_RDFFRS = 556,
3620
    ARM64_INS_RDVL = 557,
3621
    ARM64_INS_RET = 558,
3622
    ARM64_INS_RETAA = 559,
3623
    ARM64_INS_RETAB = 560,
3624
    ARM64_INS_REV = 561,
3625
    ARM64_INS_REV16 = 562,
3626
    ARM64_INS_REV32 = 563,
3627
    ARM64_INS_REV64 = 564,
3628
    ARM64_INS_REVB = 565,
3629
    ARM64_INS_REVH = 566,
3630
    ARM64_INS_REVW = 567,
3631
    ARM64_INS_RMIF = 568,
3632
    ARM64_INS_ROR = 569,
3633
    ARM64_INS_RORV = 570,
3634
    ARM64_INS_RSHRN = 571,
3635
    ARM64_INS_RSHRN2 = 572,
3636
    ARM64_INS_RSUBHN = 573,
3637
    ARM64_INS_RSUBHN2 = 574,
3638
    ARM64_INS_SABA = 575,
3639
    ARM64_INS_SABAL = 576,
3640
    ARM64_INS_SABAL2 = 577,
3641
    ARM64_INS_SABD = 578,
3642
    ARM64_INS_SABDL = 579,
3643
    ARM64_INS_SABDL2 = 580,
3644
    ARM64_INS_SADALP = 581,
3645
    ARM64_INS_SADDL = 582,
3646
    ARM64_INS_SADDL2 = 583,
3647
    ARM64_INS_SADDLP = 584,
3648
    ARM64_INS_SADDLV = 585,
3649
    ARM64_INS_SADDV = 586,
3650
    ARM64_INS_SADDW = 587,
3651
    ARM64_INS_SADDW2 = 588,
3652
    ARM64_INS_SBC = 589,
3653
    ARM64_INS_SBCS = 590,
3654
    ARM64_INS_SBFM = 591,
3655
    ARM64_INS_SCVTF = 592,
3656
    ARM64_INS_SDIV = 593,
3657
    ARM64_INS_SDIVR = 594,
3658
    ARM64_INS_SDOT = 595,
3659
    ARM64_INS_SEL = 596,
3660
    ARM64_INS_SETF16 = 597,
3661
    ARM64_INS_SETF8 = 598,
3662
    ARM64_INS_SETFFR = 599,
3663
    ARM64_INS_SEV = 600,
3664
    ARM64_INS_SEVL = 601,
3665
    ARM64_INS_SHA1C = 602,
3666
    ARM64_INS_SHA1H = 603,
3667
    ARM64_INS_SHA1M = 604,
3668
    ARM64_INS_SHA1P = 605,
3669
    ARM64_INS_SHA1SU0 = 606,
3670
    ARM64_INS_SHA1SU1 = 607,
3671
    ARM64_INS_SHA256H = 608,
3672
    ARM64_INS_SHA256H2 = 609,
3673
    ARM64_INS_SHA256SU0 = 610,
3674
    ARM64_INS_SHA256SU1 = 611,
3675
    ARM64_INS_SHA512H = 612,
3676
    ARM64_INS_SHA512H2 = 613,
3677
    ARM64_INS_SHA512SU0 = 614,
3678
    ARM64_INS_SHA512SU1 = 615,
3679
    ARM64_INS_SHADD = 616,
3680
    ARM64_INS_SHL = 617,
3681
    ARM64_INS_SHLL = 618,
3682
    ARM64_INS_SHLL2 = 619,
3683
    ARM64_INS_SHRN = 620,
3684
    ARM64_INS_SHRN2 = 621,
3685
    ARM64_INS_SHSUB = 622,
3686
    ARM64_INS_SLI = 623,
3687
    ARM64_INS_SM3PARTW1 = 624,
3688
    ARM64_INS_SM3PARTW2 = 625,
3689
    ARM64_INS_SM3SS1 = 626,
3690
    ARM64_INS_SM3TT1A = 627,
3691
    ARM64_INS_SM3TT1B = 628,
3692
    ARM64_INS_SM3TT2A = 629,
3693
    ARM64_INS_SM3TT2B = 630,
3694
    ARM64_INS_SM4E = 631,
3695
    ARM64_INS_SM4EKEY = 632,
3696
    ARM64_INS_SMADDL = 633,
3697
    ARM64_INS_SMAX = 634,
3698
    ARM64_INS_SMAXP = 635,
3699
    ARM64_INS_SMAXV = 636,
3700
    ARM64_INS_SMC = 637,
3701
    ARM64_INS_SMIN = 638,
3702
    ARM64_INS_SMINP = 639,
3703
    ARM64_INS_SMINV = 640,
3704
    ARM64_INS_SMLAL = 641,
3705
    ARM64_INS_SMLAL2 = 642,
3706
    ARM64_INS_SMLSL = 643,
3707
    ARM64_INS_SMLSL2 = 644,
3708
    ARM64_INS_SMNEGL = 645,
3709
    ARM64_INS_SMOV = 646,
3710
    ARM64_INS_SMSUBL = 647,
3711
    ARM64_INS_SMULH = 648,
3712
    ARM64_INS_SMULL = 649,
3713
    ARM64_INS_SMULL2 = 650,
3714
    ARM64_INS_SPLICE = 651,
3715
    ARM64_INS_SQABS = 652,
3716
    ARM64_INS_SQADD = 653,
3717
    ARM64_INS_SQDECB = 654,
3718
    ARM64_INS_SQDECD = 655,
3719
    ARM64_INS_SQDECH = 656,
3720
    ARM64_INS_SQDECP = 657,
3721
    ARM64_INS_SQDECW = 658,
3722
    ARM64_INS_SQDMLAL = 659,
3723
    ARM64_INS_SQDMLAL2 = 660,
3724
    ARM64_INS_SQDMLSL = 661,
3725
    ARM64_INS_SQDMLSL2 = 662,
3726
    ARM64_INS_SQDMULH = 663,
3727
    ARM64_INS_SQDMULL = 664,
3728
    ARM64_INS_SQDMULL2 = 665,
3729
    ARM64_INS_SQINCB = 666,
3730
    ARM64_INS_SQINCD = 667,
3731
    ARM64_INS_SQINCH = 668,
3732
    ARM64_INS_SQINCP = 669,
3733
    ARM64_INS_SQINCW = 670,
3734
    ARM64_INS_SQNEG = 671,
3735
    ARM64_INS_SQRDMLAH = 672,
3736
    ARM64_INS_SQRDMLSH = 673,
3737
    ARM64_INS_SQRDMULH = 674,
3738
    ARM64_INS_SQRSHL = 675,
3739
    ARM64_INS_SQRSHRN = 676,
3740
    ARM64_INS_SQRSHRN2 = 677,
3741
    ARM64_INS_SQRSHRUN = 678,
3742
    ARM64_INS_SQRSHRUN2 = 679,
3743
    ARM64_INS_SQSHL = 680,
3744
    ARM64_INS_SQSHLU = 681,
3745
    ARM64_INS_SQSHRN = 682,
3746
    ARM64_INS_SQSHRN2 = 683,
3747
    ARM64_INS_SQSHRUN = 684,
3748
    ARM64_INS_SQSHRUN2 = 685,
3749
    ARM64_INS_SQSUB = 686,
3750
    ARM64_INS_SQXTN = 687,
3751
    ARM64_INS_SQXTN2 = 688,
3752
    ARM64_INS_SQXTUN = 689,
3753
    ARM64_INS_SQXTUN2 = 690,
3754
    ARM64_INS_SRHADD = 691,
3755
    ARM64_INS_SRI = 692,
3756
    ARM64_INS_SRSHL = 693,
3757
    ARM64_INS_SRSHR = 694,
3758
    ARM64_INS_SRSRA = 695,
3759
    ARM64_INS_SSHL = 696,
3760
    ARM64_INS_SSHLL = 697,
3761
    ARM64_INS_SSHLL2 = 698,
3762
    ARM64_INS_SSHR = 699,
3763
    ARM64_INS_SSRA = 700,
3764
    ARM64_INS_SSUBL = 701,
3765
    ARM64_INS_SSUBL2 = 702,
3766
    ARM64_INS_SSUBW = 703,
3767
    ARM64_INS_SSUBW2 = 704,
3768
    ARM64_INS_ST1 = 705,
3769
    ARM64_INS_ST1B = 706,
3770
    ARM64_INS_ST1D = 707,
3771
    ARM64_INS_ST1H = 708,
3772
    ARM64_INS_ST1W = 709,
3773
    ARM64_INS_ST2 = 710,
3774
    ARM64_INS_ST2B = 711,
3775
    ARM64_INS_ST2D = 712,
3776
    ARM64_INS_ST2H = 713,
3777
    ARM64_INS_ST2W = 714,
3778
    ARM64_INS_ST3 = 715,
3779
    ARM64_INS_ST3B = 716,
3780
    ARM64_INS_ST3D = 717,
3781
    ARM64_INS_ST3H = 718,
3782
    ARM64_INS_ST3W = 719,
3783
    ARM64_INS_ST4 = 720,
3784
    ARM64_INS_ST4B = 721,
3785
    ARM64_INS_ST4D = 722,
3786
    ARM64_INS_ST4H = 723,
3787
    ARM64_INS_ST4W = 724,
3788
    ARM64_INS_STADD = 725,
3789
    ARM64_INS_STADDB = 726,
3790
    ARM64_INS_STADDH = 727,
3791
    ARM64_INS_STADDL = 728,
3792
    ARM64_INS_STADDLB = 729,
3793
    ARM64_INS_STADDLH = 730,
3794
    ARM64_INS_STCLR = 731,
3795
    ARM64_INS_STCLRB = 732,
3796
    ARM64_INS_STCLRH = 733,
3797
    ARM64_INS_STCLRL = 734,
3798
    ARM64_INS_STCLRLB = 735,
3799
    ARM64_INS_STCLRLH = 736,
3800
    ARM64_INS_STEOR = 737,
3801
    ARM64_INS_STEORB = 738,
3802
    ARM64_INS_STEORH = 739,
3803
    ARM64_INS_STEORL = 740,
3804
    ARM64_INS_STEORLB = 741,
3805
    ARM64_INS_STEORLH = 742,
3806
    ARM64_INS_STLLR = 743,
3807
    ARM64_INS_STLLRB = 744,
3808
    ARM64_INS_STLLRH = 745,
3809
    ARM64_INS_STLR = 746,
3810
    ARM64_INS_STLRB = 747,
3811
    ARM64_INS_STLRH = 748,
3812
    ARM64_INS_STLUR = 749,
3813
    ARM64_INS_STLURB = 750,
3814
    ARM64_INS_STLURH = 751,
3815
    ARM64_INS_STLXP = 752,
3816
    ARM64_INS_STLXR = 753,
3817
    ARM64_INS_STLXRB = 754,
3818
    ARM64_INS_STLXRH = 755,
3819
    ARM64_INS_STNP = 756,
3820
    ARM64_INS_STNT1B = 757,
3821
    ARM64_INS_STNT1D = 758,
3822
    ARM64_INS_STNT1H = 759,
3823
    ARM64_INS_STNT1W = 760,
3824
    ARM64_INS_STP = 761,
3825
    ARM64_INS_STR = 762,
3826
    ARM64_INS_STRB = 763,
3827
    ARM64_INS_STRH = 764,
3828
    ARM64_INS_STSET = 765,
3829
    ARM64_INS_STSETB = 766,
3830
    ARM64_INS_STSETH = 767,
3831
    ARM64_INS_STSETL = 768,
3832
    ARM64_INS_STSETLB = 769,
3833
    ARM64_INS_STSETLH = 770,
3834
    ARM64_INS_STSMAX = 771,
3835
    ARM64_INS_STSMAXB = 772,
3836
    ARM64_INS_STSMAXH = 773,
3837
    ARM64_INS_STSMAXL = 774,
3838
    ARM64_INS_STSMAXLB = 775,
3839
    ARM64_INS_STSMAXLH = 776,
3840
    ARM64_INS_STSMIN = 777,
3841
    ARM64_INS_STSMINB = 778,
3842
    ARM64_INS_STSMINH = 779,
3843
    ARM64_INS_STSMINL = 780,
3844
    ARM64_INS_STSMINLB = 781,
3845
    ARM64_INS_STSMINLH = 782,
3846
    ARM64_INS_STTR = 783,
3847
    ARM64_INS_STTRB = 784,
3848
    ARM64_INS_STTRH = 785,
3849
    ARM64_INS_STUMAX = 786,
3850
    ARM64_INS_STUMAXB = 787,
3851
    ARM64_INS_STUMAXH = 788,
3852
    ARM64_INS_STUMAXL = 789,
3853
    ARM64_INS_STUMAXLB = 790,
3854
    ARM64_INS_STUMAXLH = 791,
3855
    ARM64_INS_STUMIN = 792,
3856
    ARM64_INS_STUMINB = 793,
3857
    ARM64_INS_STUMINH = 794,
3858
    ARM64_INS_STUMINL = 795,
3859
    ARM64_INS_STUMINLB = 796,
3860
    ARM64_INS_STUMINLH = 797,
3861
    ARM64_INS_STUR = 798,
3862
    ARM64_INS_STURB = 799,
3863
    ARM64_INS_STURH = 800,
3864
    ARM64_INS_STXP = 801,
3865
    ARM64_INS_STXR = 802,
3866
    ARM64_INS_STXRB = 803,
3867
    ARM64_INS_STXRH = 804,
3868
    ARM64_INS_SUB = 805,
3869
    ARM64_INS_SUBHN = 806,
3870
    ARM64_INS_SUBHN2 = 807,
3871
    ARM64_INS_SUBR = 808,
3872
    ARM64_INS_SUBS = 809,
3873
    ARM64_INS_SUNPKHI = 810,
3874
    ARM64_INS_SUNPKLO = 811,
3875
    ARM64_INS_SUQADD = 812,
3876
    ARM64_INS_SVC = 813,
3877
    ARM64_INS_SWP = 814,
3878
    ARM64_INS_SWPA = 815,
3879
    ARM64_INS_SWPAB = 816,
3880
    ARM64_INS_SWPAH = 817,
3881
    ARM64_INS_SWPAL = 818,
3882
    ARM64_INS_SWPALB = 819,
3883
    ARM64_INS_SWPALH = 820,
3884
    ARM64_INS_SWPB = 821,
3885
    ARM64_INS_SWPH = 822,
3886
    ARM64_INS_SWPL = 823,
3887
    ARM64_INS_SWPLB = 824,
3888
    ARM64_INS_SWPLH = 825,
3889
    ARM64_INS_SXTB = 826,
3890
    ARM64_INS_SXTH = 827,
3891
    ARM64_INS_SXTL = 828,
3892
    ARM64_INS_SXTL2 = 829,
3893
    ARM64_INS_SXTW = 830,
3894
    ARM64_INS_SYS = 831,
3895
    ARM64_INS_SYSL = 832,
3896
    ARM64_INS_TBL = 833,
3897
    ARM64_INS_TBNZ = 834,
3898
    ARM64_INS_TBX = 835,
3899
    ARM64_INS_TBZ = 836,
3900
    ARM64_INS_TRN1 = 837,
3901
    ARM64_INS_TRN2 = 838,
3902
    ARM64_INS_TSB = 839,
3903
    ARM64_INS_TST = 840,
3904
    ARM64_INS_UABA = 841,
3905
    ARM64_INS_UABAL = 842,
3906
    ARM64_INS_UABAL2 = 843,
3907
    ARM64_INS_UABD = 844,
3908
    ARM64_INS_UABDL = 845,
3909
    ARM64_INS_UABDL2 = 846,
3910
    ARM64_INS_UADALP = 847,
3911
    ARM64_INS_UADDL = 848,
3912
    ARM64_INS_UADDL2 = 849,
3913
    ARM64_INS_UADDLP = 850,
3914
    ARM64_INS_UADDLV = 851,
3915
    ARM64_INS_UADDV = 852,
3916
    ARM64_INS_UADDW = 853,
3917
    ARM64_INS_UADDW2 = 854,
3918
    ARM64_INS_UBFM = 855,
3919
    ARM64_INS_UCVTF = 856,
3920
    ARM64_INS_UDIV = 857,
3921
    ARM64_INS_UDIVR = 858,
3922
    ARM64_INS_UDOT = 859,
3923
    ARM64_INS_UHADD = 860,
3924
    ARM64_INS_UHSUB = 861,
3925
    ARM64_INS_UMADDL = 862,
3926
    ARM64_INS_UMAX = 863,
3927
    ARM64_INS_UMAXP = 864,
3928
    ARM64_INS_UMAXV = 865,
3929
    ARM64_INS_UMIN = 866,
3930
    ARM64_INS_UMINP = 867,
3931
    ARM64_INS_UMINV = 868,
3932
    ARM64_INS_UMLAL = 869,
3933
    ARM64_INS_UMLAL2 = 870,
3934
    ARM64_INS_UMLSL = 871,
3935
    ARM64_INS_UMLSL2 = 872,
3936
    ARM64_INS_UMNEGL = 873,
3937
    ARM64_INS_UMOV = 874,
3938
    ARM64_INS_UMSUBL = 875,
3939
    ARM64_INS_UMULH = 876,
3940
    ARM64_INS_UMULL = 877,
3941
    ARM64_INS_UMULL2 = 878,
3942
    ARM64_INS_UQADD = 879,
3943
    ARM64_INS_UQDECB = 880,
3944
    ARM64_INS_UQDECD = 881,
3945
    ARM64_INS_UQDECH = 882,
3946
    ARM64_INS_UQDECP = 883,
3947
    ARM64_INS_UQDECW = 884,
3948
    ARM64_INS_UQINCB = 885,
3949
    ARM64_INS_UQINCD = 886,
3950
    ARM64_INS_UQINCH = 887,
3951
    ARM64_INS_UQINCP = 888,
3952
    ARM64_INS_UQINCW = 889,
3953
    ARM64_INS_UQRSHL = 890,
3954
    ARM64_INS_UQRSHRN = 891,
3955
    ARM64_INS_UQRSHRN2 = 892,
3956
    ARM64_INS_UQSHL = 893,
3957
    ARM64_INS_UQSHRN = 894,
3958
    ARM64_INS_UQSHRN2 = 895,
3959
    ARM64_INS_UQSUB = 896,
3960
    ARM64_INS_UQXTN = 897,
3961
    ARM64_INS_UQXTN2 = 898,
3962
    ARM64_INS_URECPE = 899,
3963
    ARM64_INS_URHADD = 900,
3964
    ARM64_INS_URSHL = 901,
3965
    ARM64_INS_URSHR = 902,
3966
    ARM64_INS_URSQRTE = 903,
3967
    ARM64_INS_URSRA = 904,
3968
    ARM64_INS_USHL = 905,
3969
    ARM64_INS_USHLL = 906,
3970
    ARM64_INS_USHLL2 = 907,
3971
    ARM64_INS_USHR = 908,
3972
    ARM64_INS_USQADD = 909,
3973
    ARM64_INS_USRA = 910,
3974
    ARM64_INS_USUBL = 911,
3975
    ARM64_INS_USUBL2 = 912,
3976
    ARM64_INS_USUBW = 913,
3977
    ARM64_INS_USUBW2 = 914,
3978
    ARM64_INS_UUNPKHI = 915,
3979
    ARM64_INS_UUNPKLO = 916,
3980
    ARM64_INS_UXTB = 917,
3981
    ARM64_INS_UXTH = 918,
3982
    ARM64_INS_UXTL = 919,
3983
    ARM64_INS_UXTL2 = 920,
3984
    ARM64_INS_UXTW = 921,
3985
    ARM64_INS_UZP1 = 922,
3986
    ARM64_INS_UZP2 = 923,
3987
    ARM64_INS_WFE = 924,
3988
    ARM64_INS_WFI = 925,
3989
    ARM64_INS_WHILELE = 926,
3990
    ARM64_INS_WHILELO = 927,
3991
    ARM64_INS_WHILELS = 928,
3992
    ARM64_INS_WHILELT = 929,
3993
    ARM64_INS_WRFFR = 930,
3994
    ARM64_INS_XAR = 931,
3995
    ARM64_INS_XPACD = 932,
3996
    ARM64_INS_XPACI = 933,
3997
    ARM64_INS_XPACLRI = 934,
3998
    ARM64_INS_XTN = 935,
3999
    ARM64_INS_XTN2 = 936,
4000
    ARM64_INS_YIELD = 937,
4001
    ARM64_INS_ZIP1 = 938,
4002
    ARM64_INS_ZIP2 = 939,
4003
    ARM64_INS_SBFIZ = 940,
4004
    ARM64_INS_UBFIZ = 941,
4005
    ARM64_INS_SBFX = 942,
4006
    ARM64_INS_UBFX = 943,
4007
    ARM64_INS_BFI = 944,
4008
    ARM64_INS_BFXIL = 945,
4009
    ARM64_INS_IC = 946,
4010
    ARM64_INS_DC = 947,
4011
    ARM64_INS_AT = 948,
4012
    ARM64_INS_TLBI = 949,
4013
    ARM64_INS_ENDING = 950,
4014
}
4015
pub mod arm64_insn_group {
4016
    #[doc = " Group of ARM64 instructions"]
4017
    pub type Type = libc::c_uint;
4018
    #[doc = "< = CS_GRP_INVALID"]
4019
    pub const ARM64_GRP_INVALID: Type = 0;
4020
    #[doc = "< = CS_GRP_JUMP"]
4021
    pub const ARM64_GRP_JUMP: Type = 1;
4022
    pub const ARM64_GRP_CALL: Type = 2;
4023
    pub const ARM64_GRP_RET: Type = 3;
4024
    pub const ARM64_GRP_INT: Type = 4;
4025
    #[doc = "< = CS_GRP_PRIVILEGE"]
4026
    pub const ARM64_GRP_PRIVILEGE: Type = 6;
4027
    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
4028
    pub const ARM64_GRP_BRANCH_RELATIVE: Type = 7;
4029
    pub const ARM64_GRP_PAC: Type = 8;
4030
    pub const ARM64_GRP_CRYPTO: Type = 128;
4031
    pub const ARM64_GRP_FPARMV8: Type = 129;
4032
    pub const ARM64_GRP_NEON: Type = 130;
4033
    pub const ARM64_GRP_CRC: Type = 131;
4034
    pub const ARM64_GRP_AES: Type = 132;
4035
    pub const ARM64_GRP_DOTPROD: Type = 133;
4036
    pub const ARM64_GRP_FULLFP16: Type = 134;
4037
    pub const ARM64_GRP_LSE: Type = 135;
4038
    pub const ARM64_GRP_RCPC: Type = 136;
4039
    pub const ARM64_GRP_RDM: Type = 137;
4040
    pub const ARM64_GRP_SHA2: Type = 138;
4041
    pub const ARM64_GRP_SHA3: Type = 139;
4042
    pub const ARM64_GRP_SM4: Type = 140;
4043
    pub const ARM64_GRP_SVE: Type = 141;
4044
    pub const ARM64_GRP_V8_1A: Type = 142;
4045
    pub const ARM64_GRP_V8_3A: Type = 143;
4046
    pub const ARM64_GRP_V8_4A: Type = 144;
4047
    pub const ARM64_GRP_ENDING: Type = 145;
4048
}
4049
pub mod m68k_reg {
4050
    #[doc = " M68K registers and special registers"]
4051
    pub type Type = libc::c_uint;
4052
    pub const M68K_REG_INVALID: Type = 0;
4053
    pub const M68K_REG_D0: Type = 1;
4054
    pub const M68K_REG_D1: Type = 2;
4055
    pub const M68K_REG_D2: Type = 3;
4056
    pub const M68K_REG_D3: Type = 4;
4057
    pub const M68K_REG_D4: Type = 5;
4058
    pub const M68K_REG_D5: Type = 6;
4059
    pub const M68K_REG_D6: Type = 7;
4060
    pub const M68K_REG_D7: Type = 8;
4061
    pub const M68K_REG_A0: Type = 9;
4062
    pub const M68K_REG_A1: Type = 10;
4063
    pub const M68K_REG_A2: Type = 11;
4064
    pub const M68K_REG_A3: Type = 12;
4065
    pub const M68K_REG_A4: Type = 13;
4066
    pub const M68K_REG_A5: Type = 14;
4067
    pub const M68K_REG_A6: Type = 15;
4068
    pub const M68K_REG_A7: Type = 16;
4069
    pub const M68K_REG_FP0: Type = 17;
4070
    pub const M68K_REG_FP1: Type = 18;
4071
    pub const M68K_REG_FP2: Type = 19;
4072
    pub const M68K_REG_FP3: Type = 20;
4073
    pub const M68K_REG_FP4: Type = 21;
4074
    pub const M68K_REG_FP5: Type = 22;
4075
    pub const M68K_REG_FP6: Type = 23;
4076
    pub const M68K_REG_FP7: Type = 24;
4077
    pub const M68K_REG_PC: Type = 25;
4078
    pub const M68K_REG_SR: Type = 26;
4079
    pub const M68K_REG_CCR: Type = 27;
4080
    pub const M68K_REG_SFC: Type = 28;
4081
    pub const M68K_REG_DFC: Type = 29;
4082
    pub const M68K_REG_USP: Type = 30;
4083
    pub const M68K_REG_VBR: Type = 31;
4084
    pub const M68K_REG_CACR: Type = 32;
4085
    pub const M68K_REG_CAAR: Type = 33;
4086
    pub const M68K_REG_MSP: Type = 34;
4087
    pub const M68K_REG_ISP: Type = 35;
4088
    pub const M68K_REG_TC: Type = 36;
4089
    pub const M68K_REG_ITT0: Type = 37;
4090
    pub const M68K_REG_ITT1: Type = 38;
4091
    pub const M68K_REG_DTT0: Type = 39;
4092
    pub const M68K_REG_DTT1: Type = 40;
4093
    pub const M68K_REG_MMUSR: Type = 41;
4094
    pub const M68K_REG_URP: Type = 42;
4095
    pub const M68K_REG_SRP: Type = 43;
4096
    pub const M68K_REG_FPCR: Type = 44;
4097
    pub const M68K_REG_FPSR: Type = 45;
4098
    pub const M68K_REG_FPIAR: Type = 46;
4099
    pub const M68K_REG_ENDING: Type = 47;
4100
}
4101
#[repr(u32)]
4102
#[doc = " M68K Addressing Modes"]
4103
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4104
pub enum m68k_address_mode {
4105
    #[doc = "< No address mode."]
4106
    M68K_AM_NONE = 0,
4107
    #[doc = "< Register Direct - Data"]
4108
    M68K_AM_REG_DIRECT_DATA = 1,
4109
    #[doc = "< Register Direct - Address"]
4110
    M68K_AM_REG_DIRECT_ADDR = 2,
4111
    #[doc = "< Register Indirect - Address"]
4112
    M68K_AM_REGI_ADDR = 3,
4113
    #[doc = "< Register Indirect - Address with Postincrement"]
4114
    M68K_AM_REGI_ADDR_POST_INC = 4,
4115
    #[doc = "< Register Indirect - Address with Predecrement"]
4116
    M68K_AM_REGI_ADDR_PRE_DEC = 5,
4117
    #[doc = "< Register Indirect - Address with Displacement"]
4118
    M68K_AM_REGI_ADDR_DISP = 6,
4119
    #[doc = "< Address Register Indirect With Index- 8-bit displacement"]
4120
    M68K_AM_AREGI_INDEX_8_BIT_DISP = 7,
4121
    #[doc = "< Address Register Indirect With Index- Base displacement"]
4122
    M68K_AM_AREGI_INDEX_BASE_DISP = 8,
4123
    #[doc = "< Memory indirect - Postindex"]
4124
    M68K_AM_MEMI_POST_INDEX = 9,
4125
    #[doc = "< Memory indirect - Preindex"]
4126
    M68K_AM_MEMI_PRE_INDEX = 10,
4127
    #[doc = "< Program Counter Indirect - with Displacement"]
4128
    M68K_AM_PCI_DISP = 11,
4129
    #[doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"]
4130
    M68K_AM_PCI_INDEX_8_BIT_DISP = 12,
4131
    #[doc = "< Program Counter Indirect with Index - with Base Displacement"]
4132
    M68K_AM_PCI_INDEX_BASE_DISP = 13,
4133
    #[doc = "< Program Counter Memory Indirect - Postindexed"]
4134
    M68K_AM_PC_MEMI_POST_INDEX = 14,
4135
    #[doc = "< Program Counter Memory Indirect - Preindexed"]
4136
    M68K_AM_PC_MEMI_PRE_INDEX = 15,
4137
    #[doc = "< Absolute Data Addressing  - Short"]
4138
    M68K_AM_ABSOLUTE_DATA_SHORT = 16,
4139
    #[doc = "< Absolute Data Addressing  - Long"]
4140
    M68K_AM_ABSOLUTE_DATA_LONG = 17,
4141
    #[doc = "< Immediate value"]
4142
    M68K_AM_IMMEDIATE = 18,
4143
    #[doc = "< Address as displacement from (PC+2) used by branches"]
4144
    M68K_AM_BRANCH_DISPLACEMENT = 19,
4145
}
4146
#[repr(u32)]
4147
#[doc = " Operand type for instruction's operands"]
4148
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4149
pub enum m68k_op_type {
4150
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
4151
    M68K_OP_INVALID = 0,
4152
    #[doc = "< = CS_OP_REG (Register operand)."]
4153
    M68K_OP_REG = 1,
4154
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
4155
    M68K_OP_IMM = 2,
4156
    #[doc = "< = CS_OP_MEM (Memory operand)."]
4157
    M68K_OP_MEM = 3,
4158
    #[doc = "< single precision Floating-Point operand"]
4159
    M68K_OP_FP_SINGLE = 4,
4160
    #[doc = "< double precision Floating-Point operand"]
4161
    M68K_OP_FP_DOUBLE = 5,
4162
    #[doc = "< Register bits move"]
4163
    M68K_OP_REG_BITS = 6,
4164
    #[doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"]
4165
    M68K_OP_REG_PAIR = 7,
4166
    #[doc = "< Branch displacement"]
4167
    M68K_OP_BR_DISP = 8,
4168
}
4169
#[doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"]
4170
#[repr(C)]
4171
#[derive(Debug, Copy, Clone)]
4172
pub struct m68k_op_mem {
4173
    #[doc = "< base register (or M68K_REG_INVALID if irrelevant)"]
4174
    pub base_reg: m68k_reg::Type,
4175
    #[doc = "< index register (or M68K_REG_INVALID if irrelevant)"]
4176
    pub index_reg: m68k_reg::Type,
4177
    #[doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"]
4178
    pub in_base_reg: m68k_reg::Type,
4179
    #[doc = "< indirect displacement"]
4180
    pub in_disp: u32,
4181
    #[doc = "< other displacement"]
4182
    pub out_disp: u32,
4183
    #[doc = "< displacement value"]
4184
    pub disp: i16,
4185
    #[doc = "< scale for index register"]
4186
    pub scale: u8,
4187
    #[doc = "< set to true if the two values below should be used"]
4188
    pub bitfield: u8,
4189
    #[doc = "< used for bf* instructions"]
4190
    pub width: u8,
4191
    #[doc = "< used for bf* instructions"]
4192
    pub offset: u8,
4193
    #[doc = "< 0 = w, 1 = l"]
4194
    pub index_size: u8,
4195
}
4196
#[repr(u32)]
4197
#[doc = " Operand type for instruction's operands"]
4198
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4199
pub enum m68k_op_br_disp_size {
4200
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
4201
    M68K_OP_BR_DISP_SIZE_INVALID = 0,
4202
    #[doc = "< signed 8-bit displacement"]
4203
    M68K_OP_BR_DISP_SIZE_BYTE = 1,
4204
    #[doc = "< signed 16-bit displacement"]
4205
    M68K_OP_BR_DISP_SIZE_WORD = 2,
4206
    #[doc = "< signed 32-bit displacement"]
4207
    M68K_OP_BR_DISP_SIZE_LONG = 4,
4208
}
4209
#[repr(C)]
4210
#[derive(Debug, Copy, Clone)]
4211
pub struct m68k_op_br_disp {
4212
    #[doc = "< displacement value"]
4213
    pub disp: i32,
4214
    #[doc = "< Size from m68k_op_br_disp_size type above"]
4215
    pub disp_size: u8,
4216
}
4217
#[doc = " Register pair in one operand."]
4218
#[repr(C)]
4219
#[derive(Debug, Copy, Clone)]
4220
pub struct cs_m68k_op_reg_pair {
4221
    pub reg_0: m68k_reg::Type,
4222
    pub reg_1: m68k_reg::Type,
4223
}
4224
#[doc = " Instruction operand"]
4225
#[repr(C)]
4226
#[derive(Copy, Clone)]
4227
pub struct cs_m68k_op {
4228
    pub __bindgen_anon_1: cs_m68k_op__bindgen_ty_1,
4229
    #[doc = "< data when operand is targeting memory"]
4230
    pub mem: m68k_op_mem,
4231
    #[doc = "< data when operand is a branch displacement"]
4232
    pub br_disp: m68k_op_br_disp,
4233
    #[doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"]
4234
    pub register_bits: u32,
4235
    pub type_: m68k_op_type,
4236
    #[doc = "< M68K addressing mode for this op"]
4237
    pub address_mode: m68k_address_mode,
4238
}
4239
#[repr(C)]
4240
#[derive(Copy, Clone)]
4241
pub union cs_m68k_op__bindgen_ty_1 {
4242
    #[doc = "< immediate value for IMM operand"]
4243
    pub imm: u64,
4244
    #[doc = "< double imm"]
4245
    pub dimm: f64,
4246
    #[doc = "< float imm"]
4247
    pub simm: f32,
4248
    #[doc = "< register value for REG operand"]
4249
    pub reg: m68k_reg::Type,
4250
    #[doc = "< register pair in one operand"]
4251
    pub reg_pair: cs_m68k_op_reg_pair,
4252
}
4253
impl ::core::fmt::Debug for cs_m68k_op__bindgen_ty_1 {
4254
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
4255
0
        write!(f, "cs_m68k_op__bindgen_ty_1 {{ union }}")
4256
0
    }
4257
}
4258
impl ::core::fmt::Debug for cs_m68k_op {
4259
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
4260
0
        write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . type_ , self . address_mode)
4261
0
    }
4262
}
4263
#[repr(u32)]
4264
#[doc = " Operation size of the CPU instructions"]
4265
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4266
pub enum m68k_cpu_size {
4267
    #[doc = "< unsized or unspecified"]
4268
    M68K_CPU_SIZE_NONE = 0,
4269
    #[doc = "< 1 byte in size"]
4270
    M68K_CPU_SIZE_BYTE = 1,
4271
    #[doc = "< 2 bytes in size"]
4272
    M68K_CPU_SIZE_WORD = 2,
4273
    #[doc = "< 4 bytes in size"]
4274
    M68K_CPU_SIZE_LONG = 4,
4275
}
4276
#[repr(u32)]
4277
#[doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"]
4278
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4279
pub enum m68k_fpu_size {
4280
    #[doc = "< unsized like fsave/frestore"]
4281
    M68K_FPU_SIZE_NONE = 0,
4282
    #[doc = "< 4 byte in size (single float)"]
4283
    M68K_FPU_SIZE_SINGLE = 4,
4284
    #[doc = "< 8 byte in size (double)"]
4285
    M68K_FPU_SIZE_DOUBLE = 8,
4286
    #[doc = "< 12 byte in size (extended real format)"]
4287
    M68K_FPU_SIZE_EXTENDED = 12,
4288
}
4289
#[repr(u32)]
4290
#[doc = " Type of size that is being used for the current instruction"]
4291
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4292
pub enum m68k_size_type {
4293
    M68K_SIZE_TYPE_INVALID = 0,
4294
    M68K_SIZE_TYPE_CPU = 1,
4295
    M68K_SIZE_TYPE_FPU = 2,
4296
}
4297
#[doc = " Operation size of the current instruction (NOT the actually size of instruction)"]
4298
#[repr(C)]
4299
#[derive(Copy, Clone)]
4300
pub struct m68k_op_size {
4301
    pub type_: m68k_size_type,
4302
    pub __bindgen_anon_1: m68k_op_size__bindgen_ty_1,
4303
}
4304
#[repr(C)]
4305
#[derive(Copy, Clone)]
4306
pub union m68k_op_size__bindgen_ty_1 {
4307
    pub cpu_size: m68k_cpu_size,
4308
    pub fpu_size: m68k_fpu_size,
4309
}
4310
impl ::core::fmt::Debug for m68k_op_size__bindgen_ty_1 {
4311
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
4312
0
        write!(f, "m68k_op_size__bindgen_ty_1 {{ union }}")
4313
0
    }
4314
}
4315
impl ::core::fmt::Debug for m68k_op_size {
4316
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
4317
0
        write!(
4318
0
            f,
4319
0
            "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}",
4320
            self.type_, self.__bindgen_anon_1
4321
        )
4322
0
    }
4323
}
4324
#[doc = " The M68K instruction and it's operands"]
4325
#[repr(C)]
4326
#[derive(Copy, Clone)]
4327
pub struct cs_m68k {
4328
    #[doc = "< operands for this instruction."]
4329
    pub operands: [cs_m68k_op; 4usize],
4330
    #[doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"]
4331
    pub op_size: m68k_op_size,
4332
    #[doc = "< number of operands for the instruction"]
4333
    pub op_count: u8,
4334
}
4335
impl ::core::fmt::Debug for cs_m68k {
4336
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
4337
0
        write!(
4338
0
            f,
4339
0
            "cs_m68k {{ operands: {:?}, op_size: {:?} }}",
4340
            self.operands, self.op_size
4341
        )
4342
0
    }
4343
}
4344
#[repr(u32)]
4345
#[doc = " M68K instruction"]
4346
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4347
pub enum m68k_insn {
4348
    M68K_INS_INVALID = 0,
4349
    M68K_INS_ABCD = 1,
4350
    M68K_INS_ADD = 2,
4351
    M68K_INS_ADDA = 3,
4352
    M68K_INS_ADDI = 4,
4353
    M68K_INS_ADDQ = 5,
4354
    M68K_INS_ADDX = 6,
4355
    M68K_INS_AND = 7,
4356
    M68K_INS_ANDI = 8,
4357
    M68K_INS_ASL = 9,
4358
    M68K_INS_ASR = 10,
4359
    M68K_INS_BHS = 11,
4360
    M68K_INS_BLO = 12,
4361
    M68K_INS_BHI = 13,
4362
    M68K_INS_BLS = 14,
4363
    M68K_INS_BCC = 15,
4364
    M68K_INS_BCS = 16,
4365
    M68K_INS_BNE = 17,
4366
    M68K_INS_BEQ = 18,
4367
    M68K_INS_BVC = 19,
4368
    M68K_INS_BVS = 20,
4369
    M68K_INS_BPL = 21,
4370
    M68K_INS_BMI = 22,
4371
    M68K_INS_BGE = 23,
4372
    M68K_INS_BLT = 24,
4373
    M68K_INS_BGT = 25,
4374
    M68K_INS_BLE = 26,
4375
    M68K_INS_BRA = 27,
4376
    M68K_INS_BSR = 28,
4377
    M68K_INS_BCHG = 29,
4378
    M68K_INS_BCLR = 30,
4379
    M68K_INS_BSET = 31,
4380
    M68K_INS_BTST = 32,
4381
    M68K_INS_BFCHG = 33,
4382
    M68K_INS_BFCLR = 34,
4383
    M68K_INS_BFEXTS = 35,
4384
    M68K_INS_BFEXTU = 36,
4385
    M68K_INS_BFFFO = 37,
4386
    M68K_INS_BFINS = 38,
4387
    M68K_INS_BFSET = 39,
4388
    M68K_INS_BFTST = 40,
4389
    M68K_INS_BKPT = 41,
4390
    M68K_INS_CALLM = 42,
4391
    M68K_INS_CAS = 43,
4392
    M68K_INS_CAS2 = 44,
4393
    M68K_INS_CHK = 45,
4394
    M68K_INS_CHK2 = 46,
4395
    M68K_INS_CLR = 47,
4396
    M68K_INS_CMP = 48,
4397
    M68K_INS_CMPA = 49,
4398
    M68K_INS_CMPI = 50,
4399
    M68K_INS_CMPM = 51,
4400
    M68K_INS_CMP2 = 52,
4401
    M68K_INS_CINVL = 53,
4402
    M68K_INS_CINVP = 54,
4403
    M68K_INS_CINVA = 55,
4404
    M68K_INS_CPUSHL = 56,
4405
    M68K_INS_CPUSHP = 57,
4406
    M68K_INS_CPUSHA = 58,
4407
    M68K_INS_DBT = 59,
4408
    M68K_INS_DBF = 60,
4409
    M68K_INS_DBHI = 61,
4410
    M68K_INS_DBLS = 62,
4411
    M68K_INS_DBCC = 63,
4412
    M68K_INS_DBCS = 64,
4413
    M68K_INS_DBNE = 65,
4414
    M68K_INS_DBEQ = 66,
4415
    M68K_INS_DBVC = 67,
4416
    M68K_INS_DBVS = 68,
4417
    M68K_INS_DBPL = 69,
4418
    M68K_INS_DBMI = 70,
4419
    M68K_INS_DBGE = 71,
4420
    M68K_INS_DBLT = 72,
4421
    M68K_INS_DBGT = 73,
4422
    M68K_INS_DBLE = 74,
4423
    M68K_INS_DBRA = 75,
4424
    M68K_INS_DIVS = 76,
4425
    M68K_INS_DIVSL = 77,
4426
    M68K_INS_DIVU = 78,
4427
    M68K_INS_DIVUL = 79,
4428
    M68K_INS_EOR = 80,
4429
    M68K_INS_EORI = 81,
4430
    M68K_INS_EXG = 82,
4431
    M68K_INS_EXT = 83,
4432
    M68K_INS_EXTB = 84,
4433
    M68K_INS_FABS = 85,
4434
    M68K_INS_FSABS = 86,
4435
    M68K_INS_FDABS = 87,
4436
    M68K_INS_FACOS = 88,
4437
    M68K_INS_FADD = 89,
4438
    M68K_INS_FSADD = 90,
4439
    M68K_INS_FDADD = 91,
4440
    M68K_INS_FASIN = 92,
4441
    M68K_INS_FATAN = 93,
4442
    M68K_INS_FATANH = 94,
4443
    M68K_INS_FBF = 95,
4444
    M68K_INS_FBEQ = 96,
4445
    M68K_INS_FBOGT = 97,
4446
    M68K_INS_FBOGE = 98,
4447
    M68K_INS_FBOLT = 99,
4448
    M68K_INS_FBOLE = 100,
4449
    M68K_INS_FBOGL = 101,
4450
    M68K_INS_FBOR = 102,
4451
    M68K_INS_FBUN = 103,
4452
    M68K_INS_FBUEQ = 104,
4453
    M68K_INS_FBUGT = 105,
4454
    M68K_INS_FBUGE = 106,
4455
    M68K_INS_FBULT = 107,
4456
    M68K_INS_FBULE = 108,
4457
    M68K_INS_FBNE = 109,
4458
    M68K_INS_FBT = 110,
4459
    M68K_INS_FBSF = 111,
4460
    M68K_INS_FBSEQ = 112,
4461
    M68K_INS_FBGT = 113,
4462
    M68K_INS_FBGE = 114,
4463
    M68K_INS_FBLT = 115,
4464
    M68K_INS_FBLE = 116,
4465
    M68K_INS_FBGL = 117,
4466
    M68K_INS_FBGLE = 118,
4467
    M68K_INS_FBNGLE = 119,
4468
    M68K_INS_FBNGL = 120,
4469
    M68K_INS_FBNLE = 121,
4470
    M68K_INS_FBNLT = 122,
4471
    M68K_INS_FBNGE = 123,
4472
    M68K_INS_FBNGT = 124,
4473
    M68K_INS_FBSNE = 125,
4474
    M68K_INS_FBST = 126,
4475
    M68K_INS_FCMP = 127,
4476
    M68K_INS_FCOS = 128,
4477
    M68K_INS_FCOSH = 129,
4478
    M68K_INS_FDBF = 130,
4479
    M68K_INS_FDBEQ = 131,
4480
    M68K_INS_FDBOGT = 132,
4481
    M68K_INS_FDBOGE = 133,
4482
    M68K_INS_FDBOLT = 134,
4483
    M68K_INS_FDBOLE = 135,
4484
    M68K_INS_FDBOGL = 136,
4485
    M68K_INS_FDBOR = 137,
4486
    M68K_INS_FDBUN = 138,
4487
    M68K_INS_FDBUEQ = 139,
4488
    M68K_INS_FDBUGT = 140,
4489
    M68K_INS_FDBUGE = 141,
4490
    M68K_INS_FDBULT = 142,
4491
    M68K_INS_FDBULE = 143,
4492
    M68K_INS_FDBNE = 144,
4493
    M68K_INS_FDBT = 145,
4494
    M68K_INS_FDBSF = 146,
4495
    M68K_INS_FDBSEQ = 147,
4496
    M68K_INS_FDBGT = 148,
4497
    M68K_INS_FDBGE = 149,
4498
    M68K_INS_FDBLT = 150,
4499
    M68K_INS_FDBLE = 151,
4500
    M68K_INS_FDBGL = 152,
4501
    M68K_INS_FDBGLE = 153,
4502
    M68K_INS_FDBNGLE = 154,
4503
    M68K_INS_FDBNGL = 155,
4504
    M68K_INS_FDBNLE = 156,
4505
    M68K_INS_FDBNLT = 157,
4506
    M68K_INS_FDBNGE = 158,
4507
    M68K_INS_FDBNGT = 159,
4508
    M68K_INS_FDBSNE = 160,
4509
    M68K_INS_FDBST = 161,
4510
    M68K_INS_FDIV = 162,
4511
    M68K_INS_FSDIV = 163,
4512
    M68K_INS_FDDIV = 164,
4513
    M68K_INS_FETOX = 165,
4514
    M68K_INS_FETOXM1 = 166,
4515
    M68K_INS_FGETEXP = 167,
4516
    M68K_INS_FGETMAN = 168,
4517
    M68K_INS_FINT = 169,
4518
    M68K_INS_FINTRZ = 170,
4519
    M68K_INS_FLOG10 = 171,
4520
    M68K_INS_FLOG2 = 172,
4521
    M68K_INS_FLOGN = 173,
4522
    M68K_INS_FLOGNP1 = 174,
4523
    M68K_INS_FMOD = 175,
4524
    M68K_INS_FMOVE = 176,
4525
    M68K_INS_FSMOVE = 177,
4526
    M68K_INS_FDMOVE = 178,
4527
    M68K_INS_FMOVECR = 179,
4528
    M68K_INS_FMOVEM = 180,
4529
    M68K_INS_FMUL = 181,
4530
    M68K_INS_FSMUL = 182,
4531
    M68K_INS_FDMUL = 183,
4532
    M68K_INS_FNEG = 184,
4533
    M68K_INS_FSNEG = 185,
4534
    M68K_INS_FDNEG = 186,
4535
    M68K_INS_FNOP = 187,
4536
    M68K_INS_FREM = 188,
4537
    M68K_INS_FRESTORE = 189,
4538
    M68K_INS_FSAVE = 190,
4539
    M68K_INS_FSCALE = 191,
4540
    M68K_INS_FSGLDIV = 192,
4541
    M68K_INS_FSGLMUL = 193,
4542
    M68K_INS_FSIN = 194,
4543
    M68K_INS_FSINCOS = 195,
4544
    M68K_INS_FSINH = 196,
4545
    M68K_INS_FSQRT = 197,
4546
    M68K_INS_FSSQRT = 198,
4547
    M68K_INS_FDSQRT = 199,
4548
    M68K_INS_FSF = 200,
4549
    M68K_INS_FSBEQ = 201,
4550
    M68K_INS_FSOGT = 202,
4551
    M68K_INS_FSOGE = 203,
4552
    M68K_INS_FSOLT = 204,
4553
    M68K_INS_FSOLE = 205,
4554
    M68K_INS_FSOGL = 206,
4555
    M68K_INS_FSOR = 207,
4556
    M68K_INS_FSUN = 208,
4557
    M68K_INS_FSUEQ = 209,
4558
    M68K_INS_FSUGT = 210,
4559
    M68K_INS_FSUGE = 211,
4560
    M68K_INS_FSULT = 212,
4561
    M68K_INS_FSULE = 213,
4562
    M68K_INS_FSNE = 214,
4563
    M68K_INS_FST = 215,
4564
    M68K_INS_FSSF = 216,
4565
    M68K_INS_FSSEQ = 217,
4566
    M68K_INS_FSGT = 218,
4567
    M68K_INS_FSGE = 219,
4568
    M68K_INS_FSLT = 220,
4569
    M68K_INS_FSLE = 221,
4570
    M68K_INS_FSGL = 222,
4571
    M68K_INS_FSGLE = 223,
4572
    M68K_INS_FSNGLE = 224,
4573
    M68K_INS_FSNGL = 225,
4574
    M68K_INS_FSNLE = 226,
4575
    M68K_INS_FSNLT = 227,
4576
    M68K_INS_FSNGE = 228,
4577
    M68K_INS_FSNGT = 229,
4578
    M68K_INS_FSSNE = 230,
4579
    M68K_INS_FSST = 231,
4580
    M68K_INS_FSUB = 232,
4581
    M68K_INS_FSSUB = 233,
4582
    M68K_INS_FDSUB = 234,
4583
    M68K_INS_FTAN = 235,
4584
    M68K_INS_FTANH = 236,
4585
    M68K_INS_FTENTOX = 237,
4586
    M68K_INS_FTRAPF = 238,
4587
    M68K_INS_FTRAPEQ = 239,
4588
    M68K_INS_FTRAPOGT = 240,
4589
    M68K_INS_FTRAPOGE = 241,
4590
    M68K_INS_FTRAPOLT = 242,
4591
    M68K_INS_FTRAPOLE = 243,
4592
    M68K_INS_FTRAPOGL = 244,
4593
    M68K_INS_FTRAPOR = 245,
4594
    M68K_INS_FTRAPUN = 246,
4595
    M68K_INS_FTRAPUEQ = 247,
4596
    M68K_INS_FTRAPUGT = 248,
4597
    M68K_INS_FTRAPUGE = 249,
4598
    M68K_INS_FTRAPULT = 250,
4599
    M68K_INS_FTRAPULE = 251,
4600
    M68K_INS_FTRAPNE = 252,
4601
    M68K_INS_FTRAPT = 253,
4602
    M68K_INS_FTRAPSF = 254,
4603
    M68K_INS_FTRAPSEQ = 255,
4604
    M68K_INS_FTRAPGT = 256,
4605
    M68K_INS_FTRAPGE = 257,
4606
    M68K_INS_FTRAPLT = 258,
4607
    M68K_INS_FTRAPLE = 259,
4608
    M68K_INS_FTRAPGL = 260,
4609
    M68K_INS_FTRAPGLE = 261,
4610
    M68K_INS_FTRAPNGLE = 262,
4611
    M68K_INS_FTRAPNGL = 263,
4612
    M68K_INS_FTRAPNLE = 264,
4613
    M68K_INS_FTRAPNLT = 265,
4614
    M68K_INS_FTRAPNGE = 266,
4615
    M68K_INS_FTRAPNGT = 267,
4616
    M68K_INS_FTRAPSNE = 268,
4617
    M68K_INS_FTRAPST = 269,
4618
    M68K_INS_FTST = 270,
4619
    M68K_INS_FTWOTOX = 271,
4620
    M68K_INS_HALT = 272,
4621
    M68K_INS_ILLEGAL = 273,
4622
    M68K_INS_JMP = 274,
4623
    M68K_INS_JSR = 275,
4624
    M68K_INS_LEA = 276,
4625
    M68K_INS_LINK = 277,
4626
    M68K_INS_LPSTOP = 278,
4627
    M68K_INS_LSL = 279,
4628
    M68K_INS_LSR = 280,
4629
    M68K_INS_MOVE = 281,
4630
    M68K_INS_MOVEA = 282,
4631
    M68K_INS_MOVEC = 283,
4632
    M68K_INS_MOVEM = 284,
4633
    M68K_INS_MOVEP = 285,
4634
    M68K_INS_MOVEQ = 286,
4635
    M68K_INS_MOVES = 287,
4636
    M68K_INS_MOVE16 = 288,
4637
    M68K_INS_MULS = 289,
4638
    M68K_INS_MULU = 290,
4639
    M68K_INS_NBCD = 291,
4640
    M68K_INS_NEG = 292,
4641
    M68K_INS_NEGX = 293,
4642
    M68K_INS_NOP = 294,
4643
    M68K_INS_NOT = 295,
4644
    M68K_INS_OR = 296,
4645
    M68K_INS_ORI = 297,
4646
    M68K_INS_PACK = 298,
4647
    M68K_INS_PEA = 299,
4648
    M68K_INS_PFLUSH = 300,
4649
    M68K_INS_PFLUSHA = 301,
4650
    M68K_INS_PFLUSHAN = 302,
4651
    M68K_INS_PFLUSHN = 303,
4652
    M68K_INS_PLOADR = 304,
4653
    M68K_INS_PLOADW = 305,
4654
    M68K_INS_PLPAR = 306,
4655
    M68K_INS_PLPAW = 307,
4656
    M68K_INS_PMOVE = 308,
4657
    M68K_INS_PMOVEFD = 309,
4658
    M68K_INS_PTESTR = 310,
4659
    M68K_INS_PTESTW = 311,
4660
    M68K_INS_PULSE = 312,
4661
    M68K_INS_REMS = 313,
4662
    M68K_INS_REMU = 314,
4663
    M68K_INS_RESET = 315,
4664
    M68K_INS_ROL = 316,
4665
    M68K_INS_ROR = 317,
4666
    M68K_INS_ROXL = 318,
4667
    M68K_INS_ROXR = 319,
4668
    M68K_INS_RTD = 320,
4669
    M68K_INS_RTE = 321,
4670
    M68K_INS_RTM = 322,
4671
    M68K_INS_RTR = 323,
4672
    M68K_INS_RTS = 324,
4673
    M68K_INS_SBCD = 325,
4674
    M68K_INS_ST = 326,
4675
    M68K_INS_SF = 327,
4676
    M68K_INS_SHI = 328,
4677
    M68K_INS_SLS = 329,
4678
    M68K_INS_SCC = 330,
4679
    M68K_INS_SHS = 331,
4680
    M68K_INS_SCS = 332,
4681
    M68K_INS_SLO = 333,
4682
    M68K_INS_SNE = 334,
4683
    M68K_INS_SEQ = 335,
4684
    M68K_INS_SVC = 336,
4685
    M68K_INS_SVS = 337,
4686
    M68K_INS_SPL = 338,
4687
    M68K_INS_SMI = 339,
4688
    M68K_INS_SGE = 340,
4689
    M68K_INS_SLT = 341,
4690
    M68K_INS_SGT = 342,
4691
    M68K_INS_SLE = 343,
4692
    M68K_INS_STOP = 344,
4693
    M68K_INS_SUB = 345,
4694
    M68K_INS_SUBA = 346,
4695
    M68K_INS_SUBI = 347,
4696
    M68K_INS_SUBQ = 348,
4697
    M68K_INS_SUBX = 349,
4698
    M68K_INS_SWAP = 350,
4699
    M68K_INS_TAS = 351,
4700
    M68K_INS_TRAP = 352,
4701
    M68K_INS_TRAPV = 353,
4702
    M68K_INS_TRAPT = 354,
4703
    M68K_INS_TRAPF = 355,
4704
    M68K_INS_TRAPHI = 356,
4705
    M68K_INS_TRAPLS = 357,
4706
    M68K_INS_TRAPCC = 358,
4707
    M68K_INS_TRAPHS = 359,
4708
    M68K_INS_TRAPCS = 360,
4709
    M68K_INS_TRAPLO = 361,
4710
    M68K_INS_TRAPNE = 362,
4711
    M68K_INS_TRAPEQ = 363,
4712
    M68K_INS_TRAPVC = 364,
4713
    M68K_INS_TRAPVS = 365,
4714
    M68K_INS_TRAPPL = 366,
4715
    M68K_INS_TRAPMI = 367,
4716
    M68K_INS_TRAPGE = 368,
4717
    M68K_INS_TRAPLT = 369,
4718
    M68K_INS_TRAPGT = 370,
4719
    M68K_INS_TRAPLE = 371,
4720
    M68K_INS_TST = 372,
4721
    M68K_INS_UNLK = 373,
4722
    M68K_INS_UNPK = 374,
4723
    M68K_INS_ENDING = 375,
4724
}
4725
#[repr(u32)]
4726
#[doc = " Group of M68K instructions"]
4727
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4728
pub enum m68k_group_type {
4729
    #[doc = "< CS_GRUP_INVALID"]
4730
    M68K_GRP_INVALID = 0,
4731
    #[doc = "< = CS_GRP_JUMP"]
4732
    M68K_GRP_JUMP = 1,
4733
    #[doc = "< = CS_GRP_RET"]
4734
    M68K_GRP_RET = 3,
4735
    #[doc = "< = CS_GRP_IRET"]
4736
    M68K_GRP_IRET = 5,
4737
    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
4738
    M68K_GRP_BRANCH_RELATIVE = 7,
4739
    M68K_GRP_ENDING = 8,
4740
}
4741
#[repr(u32)]
4742
#[doc = " Operand type for instruction's operands"]
4743
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4744
pub enum mips_op_type {
4745
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
4746
    MIPS_OP_INVALID = 0,
4747
    #[doc = "< = CS_OP_REG (Register operand)."]
4748
    MIPS_OP_REG = 1,
4749
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
4750
    MIPS_OP_IMM = 2,
4751
    #[doc = "< = CS_OP_MEM (Memory operand)."]
4752
    MIPS_OP_MEM = 3,
4753
}
4754
pub mod mips_reg {
4755
    #[doc = " MIPS registers"]
4756
    pub type Type = libc::c_uint;
4757
    pub const MIPS_REG_INVALID: Type = 0;
4758
    pub const MIPS_REG_PC: Type = 1;
4759
    pub const MIPS_REG_0: Type = 2;
4760
    pub const MIPS_REG_1: Type = 3;
4761
    pub const MIPS_REG_2: Type = 4;
4762
    pub const MIPS_REG_3: Type = 5;
4763
    pub const MIPS_REG_4: Type = 6;
4764
    pub const MIPS_REG_5: Type = 7;
4765
    pub const MIPS_REG_6: Type = 8;
4766
    pub const MIPS_REG_7: Type = 9;
4767
    pub const MIPS_REG_8: Type = 10;
4768
    pub const MIPS_REG_9: Type = 11;
4769
    pub const MIPS_REG_10: Type = 12;
4770
    pub const MIPS_REG_11: Type = 13;
4771
    pub const MIPS_REG_12: Type = 14;
4772
    pub const MIPS_REG_13: Type = 15;
4773
    pub const MIPS_REG_14: Type = 16;
4774
    pub const MIPS_REG_15: Type = 17;
4775
    pub const MIPS_REG_16: Type = 18;
4776
    pub const MIPS_REG_17: Type = 19;
4777
    pub const MIPS_REG_18: Type = 20;
4778
    pub const MIPS_REG_19: Type = 21;
4779
    pub const MIPS_REG_20: Type = 22;
4780
    pub const MIPS_REG_21: Type = 23;
4781
    pub const MIPS_REG_22: Type = 24;
4782
    pub const MIPS_REG_23: Type = 25;
4783
    pub const MIPS_REG_24: Type = 26;
4784
    pub const MIPS_REG_25: Type = 27;
4785
    pub const MIPS_REG_26: Type = 28;
4786
    pub const MIPS_REG_27: Type = 29;
4787
    pub const MIPS_REG_28: Type = 30;
4788
    pub const MIPS_REG_29: Type = 31;
4789
    pub const MIPS_REG_30: Type = 32;
4790
    pub const MIPS_REG_31: Type = 33;
4791
    pub const MIPS_REG_DSPCCOND: Type = 34;
4792
    pub const MIPS_REG_DSPCARRY: Type = 35;
4793
    pub const MIPS_REG_DSPEFI: Type = 36;
4794
    pub const MIPS_REG_DSPOUTFLAG: Type = 37;
4795
    pub const MIPS_REG_DSPOUTFLAG16_19: Type = 38;
4796
    pub const MIPS_REG_DSPOUTFLAG20: Type = 39;
4797
    pub const MIPS_REG_DSPOUTFLAG21: Type = 40;
4798
    pub const MIPS_REG_DSPOUTFLAG22: Type = 41;
4799
    pub const MIPS_REG_DSPOUTFLAG23: Type = 42;
4800
    pub const MIPS_REG_DSPPOS: Type = 43;
4801
    pub const MIPS_REG_DSPSCOUNT: Type = 44;
4802
    pub const MIPS_REG_AC0: Type = 45;
4803
    pub const MIPS_REG_AC1: Type = 46;
4804
    pub const MIPS_REG_AC2: Type = 47;
4805
    pub const MIPS_REG_AC3: Type = 48;
4806
    pub const MIPS_REG_CC0: Type = 49;
4807
    pub const MIPS_REG_CC1: Type = 50;
4808
    pub const MIPS_REG_CC2: Type = 51;
4809
    pub const MIPS_REG_CC3: Type = 52;
4810
    pub const MIPS_REG_CC4: Type = 53;
4811
    pub const MIPS_REG_CC5: Type = 54;
4812
    pub const MIPS_REG_CC6: Type = 55;
4813
    pub const MIPS_REG_CC7: Type = 56;
4814
    pub const MIPS_REG_F0: Type = 57;
4815
    pub const MIPS_REG_F1: Type = 58;
4816
    pub const MIPS_REG_F2: Type = 59;
4817
    pub const MIPS_REG_F3: Type = 60;
4818
    pub const MIPS_REG_F4: Type = 61;
4819
    pub const MIPS_REG_F5: Type = 62;
4820
    pub const MIPS_REG_F6: Type = 63;
4821
    pub const MIPS_REG_F7: Type = 64;
4822
    pub const MIPS_REG_F8: Type = 65;
4823
    pub const MIPS_REG_F9: Type = 66;
4824
    pub const MIPS_REG_F10: Type = 67;
4825
    pub const MIPS_REG_F11: Type = 68;
4826
    pub const MIPS_REG_F12: Type = 69;
4827
    pub const MIPS_REG_F13: Type = 70;
4828
    pub const MIPS_REG_F14: Type = 71;
4829
    pub const MIPS_REG_F15: Type = 72;
4830
    pub const MIPS_REG_F16: Type = 73;
4831
    pub const MIPS_REG_F17: Type = 74;
4832
    pub const MIPS_REG_F18: Type = 75;
4833
    pub const MIPS_REG_F19: Type = 76;
4834
    pub const MIPS_REG_F20: Type = 77;
4835
    pub const MIPS_REG_F21: Type = 78;
4836
    pub const MIPS_REG_F22: Type = 79;
4837
    pub const MIPS_REG_F23: Type = 80;
4838
    pub const MIPS_REG_F24: Type = 81;
4839
    pub const MIPS_REG_F25: Type = 82;
4840
    pub const MIPS_REG_F26: Type = 83;
4841
    pub const MIPS_REG_F27: Type = 84;
4842
    pub const MIPS_REG_F28: Type = 85;
4843
    pub const MIPS_REG_F29: Type = 86;
4844
    pub const MIPS_REG_F30: Type = 87;
4845
    pub const MIPS_REG_F31: Type = 88;
4846
    pub const MIPS_REG_FCC0: Type = 89;
4847
    pub const MIPS_REG_FCC1: Type = 90;
4848
    pub const MIPS_REG_FCC2: Type = 91;
4849
    pub const MIPS_REG_FCC3: Type = 92;
4850
    pub const MIPS_REG_FCC4: Type = 93;
4851
    pub const MIPS_REG_FCC5: Type = 94;
4852
    pub const MIPS_REG_FCC6: Type = 95;
4853
    pub const MIPS_REG_FCC7: Type = 96;
4854
    pub const MIPS_REG_W0: Type = 97;
4855
    pub const MIPS_REG_W1: Type = 98;
4856
    pub const MIPS_REG_W2: Type = 99;
4857
    pub const MIPS_REG_W3: Type = 100;
4858
    pub const MIPS_REG_W4: Type = 101;
4859
    pub const MIPS_REG_W5: Type = 102;
4860
    pub const MIPS_REG_W6: Type = 103;
4861
    pub const MIPS_REG_W7: Type = 104;
4862
    pub const MIPS_REG_W8: Type = 105;
4863
    pub const MIPS_REG_W9: Type = 106;
4864
    pub const MIPS_REG_W10: Type = 107;
4865
    pub const MIPS_REG_W11: Type = 108;
4866
    pub const MIPS_REG_W12: Type = 109;
4867
    pub const MIPS_REG_W13: Type = 110;
4868
    pub const MIPS_REG_W14: Type = 111;
4869
    pub const MIPS_REG_W15: Type = 112;
4870
    pub const MIPS_REG_W16: Type = 113;
4871
    pub const MIPS_REG_W17: Type = 114;
4872
    pub const MIPS_REG_W18: Type = 115;
4873
    pub const MIPS_REG_W19: Type = 116;
4874
    pub const MIPS_REG_W20: Type = 117;
4875
    pub const MIPS_REG_W21: Type = 118;
4876
    pub const MIPS_REG_W22: Type = 119;
4877
    pub const MIPS_REG_W23: Type = 120;
4878
    pub const MIPS_REG_W24: Type = 121;
4879
    pub const MIPS_REG_W25: Type = 122;
4880
    pub const MIPS_REG_W26: Type = 123;
4881
    pub const MIPS_REG_W27: Type = 124;
4882
    pub const MIPS_REG_W28: Type = 125;
4883
    pub const MIPS_REG_W29: Type = 126;
4884
    pub const MIPS_REG_W30: Type = 127;
4885
    pub const MIPS_REG_W31: Type = 128;
4886
    pub const MIPS_REG_HI: Type = 129;
4887
    pub const MIPS_REG_LO: Type = 130;
4888
    pub const MIPS_REG_P0: Type = 131;
4889
    pub const MIPS_REG_P1: Type = 132;
4890
    pub const MIPS_REG_P2: Type = 133;
4891
    pub const MIPS_REG_MPL0: Type = 134;
4892
    pub const MIPS_REG_MPL1: Type = 135;
4893
    pub const MIPS_REG_MPL2: Type = 136;
4894
    pub const MIPS_REG_ENDING: Type = 137;
4895
    pub const MIPS_REG_ZERO: Type = 2;
4896
    pub const MIPS_REG_AT: Type = 3;
4897
    pub const MIPS_REG_V0: Type = 4;
4898
    pub const MIPS_REG_V1: Type = 5;
4899
    pub const MIPS_REG_A0: Type = 6;
4900
    pub const MIPS_REG_A1: Type = 7;
4901
    pub const MIPS_REG_A2: Type = 8;
4902
    pub const MIPS_REG_A3: Type = 9;
4903
    pub const MIPS_REG_T0: Type = 10;
4904
    pub const MIPS_REG_T1: Type = 11;
4905
    pub const MIPS_REG_T2: Type = 12;
4906
    pub const MIPS_REG_T3: Type = 13;
4907
    pub const MIPS_REG_T4: Type = 14;
4908
    pub const MIPS_REG_T5: Type = 15;
4909
    pub const MIPS_REG_T6: Type = 16;
4910
    pub const MIPS_REG_T7: Type = 17;
4911
    pub const MIPS_REG_S0: Type = 18;
4912
    pub const MIPS_REG_S1: Type = 19;
4913
    pub const MIPS_REG_S2: Type = 20;
4914
    pub const MIPS_REG_S3: Type = 21;
4915
    pub const MIPS_REG_S4: Type = 22;
4916
    pub const MIPS_REG_S5: Type = 23;
4917
    pub const MIPS_REG_S6: Type = 24;
4918
    pub const MIPS_REG_S7: Type = 25;
4919
    pub const MIPS_REG_T8: Type = 26;
4920
    pub const MIPS_REG_T9: Type = 27;
4921
    pub const MIPS_REG_K0: Type = 28;
4922
    pub const MIPS_REG_K1: Type = 29;
4923
    pub const MIPS_REG_GP: Type = 30;
4924
    pub const MIPS_REG_SP: Type = 31;
4925
    pub const MIPS_REG_FP: Type = 32;
4926
    pub const MIPS_REG_S8: Type = 32;
4927
    pub const MIPS_REG_RA: Type = 33;
4928
    pub const MIPS_REG_HI0: Type = 45;
4929
    pub const MIPS_REG_HI1: Type = 46;
4930
    pub const MIPS_REG_HI2: Type = 47;
4931
    pub const MIPS_REG_HI3: Type = 48;
4932
    pub const MIPS_REG_LO0: Type = 45;
4933
    pub const MIPS_REG_LO1: Type = 46;
4934
    pub const MIPS_REG_LO2: Type = 47;
4935
    pub const MIPS_REG_LO3: Type = 48;
4936
}
4937
#[doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"]
4938
#[repr(C)]
4939
#[derive(Debug, Copy, Clone)]
4940
pub struct mips_op_mem {
4941
    #[doc = "< base register"]
4942
    pub base: mips_reg::Type,
4943
    #[doc = "< displacement/offset value"]
4944
    pub disp: i64,
4945
}
4946
#[doc = " Instruction operand"]
4947
#[repr(C)]
4948
#[derive(Copy, Clone)]
4949
pub struct cs_mips_op {
4950
    #[doc = "< operand type"]
4951
    pub type_: mips_op_type,
4952
    pub __bindgen_anon_1: cs_mips_op__bindgen_ty_1,
4953
}
4954
#[repr(C)]
4955
#[derive(Copy, Clone)]
4956
pub union cs_mips_op__bindgen_ty_1 {
4957
    #[doc = "< register id for REG operand"]
4958
    pub reg: mips_reg::Type,
4959
    #[doc = "< immediate value for IMM operand"]
4960
    pub imm: i64,
4961
    #[doc = "< base/index/scale/disp value for MEM operand"]
4962
    pub mem: mips_op_mem,
4963
}
4964
impl ::core::fmt::Debug for cs_mips_op__bindgen_ty_1 {
4965
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
4966
0
        write!(f, "cs_mips_op__bindgen_ty_1 {{ union }}")
4967
0
    }
4968
}
4969
impl ::core::fmt::Debug for cs_mips_op {
4970
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
4971
0
        write!(
4972
0
            f,
4973
0
            "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
4974
            self.type_, self.__bindgen_anon_1
4975
        )
4976
0
    }
4977
}
4978
#[doc = " Instruction structure"]
4979
#[repr(C)]
4980
#[derive(Copy, Clone)]
4981
pub struct cs_mips {
4982
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
4983
    pub op_count: u8,
4984
    #[doc = "< operands for this instruction."]
4985
    pub operands: [cs_mips_op; 10usize],
4986
}
4987
impl ::core::fmt::Debug for cs_mips {
4988
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
4989
0
        write!(f, "cs_mips {{ operands: {:?} }}", self.operands)
4990
0
    }
4991
}
4992
#[repr(u32)]
4993
#[doc = " MIPS instruction"]
4994
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
4995
pub enum mips_insn {
4996
    MIPS_INS_INVALID = 0,
4997
    MIPS_INS_ABSQ_S = 1,
4998
    MIPS_INS_ADD = 2,
4999
    MIPS_INS_ADDIUPC = 3,
5000
    MIPS_INS_ADDIUR1SP = 4,
5001
    MIPS_INS_ADDIUR2 = 5,
5002
    MIPS_INS_ADDIUS5 = 6,
5003
    MIPS_INS_ADDIUSP = 7,
5004
    MIPS_INS_ADDQH = 8,
5005
    MIPS_INS_ADDQH_R = 9,
5006
    MIPS_INS_ADDQ = 10,
5007
    MIPS_INS_ADDQ_S = 11,
5008
    MIPS_INS_ADDSC = 12,
5009
    MIPS_INS_ADDS_A = 13,
5010
    MIPS_INS_ADDS_S = 14,
5011
    MIPS_INS_ADDS_U = 15,
5012
    MIPS_INS_ADDU16 = 16,
5013
    MIPS_INS_ADDUH = 17,
5014
    MIPS_INS_ADDUH_R = 18,
5015
    MIPS_INS_ADDU = 19,
5016
    MIPS_INS_ADDU_S = 20,
5017
    MIPS_INS_ADDVI = 21,
5018
    MIPS_INS_ADDV = 22,
5019
    MIPS_INS_ADDWC = 23,
5020
    MIPS_INS_ADD_A = 24,
5021
    MIPS_INS_ADDI = 25,
5022
    MIPS_INS_ADDIU = 26,
5023
    MIPS_INS_ALIGN = 27,
5024
    MIPS_INS_ALUIPC = 28,
5025
    MIPS_INS_AND = 29,
5026
    MIPS_INS_AND16 = 30,
5027
    MIPS_INS_ANDI16 = 31,
5028
    MIPS_INS_ANDI = 32,
5029
    MIPS_INS_APPEND = 33,
5030
    MIPS_INS_ASUB_S = 34,
5031
    MIPS_INS_ASUB_U = 35,
5032
    MIPS_INS_AUI = 36,
5033
    MIPS_INS_AUIPC = 37,
5034
    MIPS_INS_AVER_S = 38,
5035
    MIPS_INS_AVER_U = 39,
5036
    MIPS_INS_AVE_S = 40,
5037
    MIPS_INS_AVE_U = 41,
5038
    MIPS_INS_B16 = 42,
5039
    MIPS_INS_BADDU = 43,
5040
    MIPS_INS_BAL = 44,
5041
    MIPS_INS_BALC = 45,
5042
    MIPS_INS_BALIGN = 46,
5043
    MIPS_INS_BBIT0 = 47,
5044
    MIPS_INS_BBIT032 = 48,
5045
    MIPS_INS_BBIT1 = 49,
5046
    MIPS_INS_BBIT132 = 50,
5047
    MIPS_INS_BC = 51,
5048
    MIPS_INS_BC0F = 52,
5049
    MIPS_INS_BC0FL = 53,
5050
    MIPS_INS_BC0T = 54,
5051
    MIPS_INS_BC0TL = 55,
5052
    MIPS_INS_BC1EQZ = 56,
5053
    MIPS_INS_BC1F = 57,
5054
    MIPS_INS_BC1FL = 58,
5055
    MIPS_INS_BC1NEZ = 59,
5056
    MIPS_INS_BC1T = 60,
5057
    MIPS_INS_BC1TL = 61,
5058
    MIPS_INS_BC2EQZ = 62,
5059
    MIPS_INS_BC2F = 63,
5060
    MIPS_INS_BC2FL = 64,
5061
    MIPS_INS_BC2NEZ = 65,
5062
    MIPS_INS_BC2T = 66,
5063
    MIPS_INS_BC2TL = 67,
5064
    MIPS_INS_BC3F = 68,
5065
    MIPS_INS_BC3FL = 69,
5066
    MIPS_INS_BC3T = 70,
5067
    MIPS_INS_BC3TL = 71,
5068
    MIPS_INS_BCLRI = 72,
5069
    MIPS_INS_BCLR = 73,
5070
    MIPS_INS_BEQ = 74,
5071
    MIPS_INS_BEQC = 75,
5072
    MIPS_INS_BEQL = 76,
5073
    MIPS_INS_BEQZ16 = 77,
5074
    MIPS_INS_BEQZALC = 78,
5075
    MIPS_INS_BEQZC = 79,
5076
    MIPS_INS_BGEC = 80,
5077
    MIPS_INS_BGEUC = 81,
5078
    MIPS_INS_BGEZ = 82,
5079
    MIPS_INS_BGEZAL = 83,
5080
    MIPS_INS_BGEZALC = 84,
5081
    MIPS_INS_BGEZALL = 85,
5082
    MIPS_INS_BGEZALS = 86,
5083
    MIPS_INS_BGEZC = 87,
5084
    MIPS_INS_BGEZL = 88,
5085
    MIPS_INS_BGTZ = 89,
5086
    MIPS_INS_BGTZALC = 90,
5087
    MIPS_INS_BGTZC = 91,
5088
    MIPS_INS_BGTZL = 92,
5089
    MIPS_INS_BINSLI = 93,
5090
    MIPS_INS_BINSL = 94,
5091
    MIPS_INS_BINSRI = 95,
5092
    MIPS_INS_BINSR = 96,
5093
    MIPS_INS_BITREV = 97,
5094
    MIPS_INS_BITSWAP = 98,
5095
    MIPS_INS_BLEZ = 99,
5096
    MIPS_INS_BLEZALC = 100,
5097
    MIPS_INS_BLEZC = 101,
5098
    MIPS_INS_BLEZL = 102,
5099
    MIPS_INS_BLTC = 103,
5100
    MIPS_INS_BLTUC = 104,
5101
    MIPS_INS_BLTZ = 105,
5102
    MIPS_INS_BLTZAL = 106,
5103
    MIPS_INS_BLTZALC = 107,
5104
    MIPS_INS_BLTZALL = 108,
5105
    MIPS_INS_BLTZALS = 109,
5106
    MIPS_INS_BLTZC = 110,
5107
    MIPS_INS_BLTZL = 111,
5108
    MIPS_INS_BMNZI = 112,
5109
    MIPS_INS_BMNZ = 113,
5110
    MIPS_INS_BMZI = 114,
5111
    MIPS_INS_BMZ = 115,
5112
    MIPS_INS_BNE = 116,
5113
    MIPS_INS_BNEC = 117,
5114
    MIPS_INS_BNEGI = 118,
5115
    MIPS_INS_BNEG = 119,
5116
    MIPS_INS_BNEL = 120,
5117
    MIPS_INS_BNEZ16 = 121,
5118
    MIPS_INS_BNEZALC = 122,
5119
    MIPS_INS_BNEZC = 123,
5120
    MIPS_INS_BNVC = 124,
5121
    MIPS_INS_BNZ = 125,
5122
    MIPS_INS_BOVC = 126,
5123
    MIPS_INS_BPOSGE32 = 127,
5124
    MIPS_INS_BREAK = 128,
5125
    MIPS_INS_BREAK16 = 129,
5126
    MIPS_INS_BSELI = 130,
5127
    MIPS_INS_BSEL = 131,
5128
    MIPS_INS_BSETI = 132,
5129
    MIPS_INS_BSET = 133,
5130
    MIPS_INS_BZ = 134,
5131
    MIPS_INS_BEQZ = 135,
5132
    MIPS_INS_B = 136,
5133
    MIPS_INS_BNEZ = 137,
5134
    MIPS_INS_BTEQZ = 138,
5135
    MIPS_INS_BTNEZ = 139,
5136
    MIPS_INS_CACHE = 140,
5137
    MIPS_INS_CEIL = 141,
5138
    MIPS_INS_CEQI = 142,
5139
    MIPS_INS_CEQ = 143,
5140
    MIPS_INS_CFC1 = 144,
5141
    MIPS_INS_CFCMSA = 145,
5142
    MIPS_INS_CINS = 146,
5143
    MIPS_INS_CINS32 = 147,
5144
    MIPS_INS_CLASS = 148,
5145
    MIPS_INS_CLEI_S = 149,
5146
    MIPS_INS_CLEI_U = 150,
5147
    MIPS_INS_CLE_S = 151,
5148
    MIPS_INS_CLE_U = 152,
5149
    MIPS_INS_CLO = 153,
5150
    MIPS_INS_CLTI_S = 154,
5151
    MIPS_INS_CLTI_U = 155,
5152
    MIPS_INS_CLT_S = 156,
5153
    MIPS_INS_CLT_U = 157,
5154
    MIPS_INS_CLZ = 158,
5155
    MIPS_INS_CMPGDU = 159,
5156
    MIPS_INS_CMPGU = 160,
5157
    MIPS_INS_CMPU = 161,
5158
    MIPS_INS_CMP = 162,
5159
    MIPS_INS_COPY_S = 163,
5160
    MIPS_INS_COPY_U = 164,
5161
    MIPS_INS_CTC1 = 165,
5162
    MIPS_INS_CTCMSA = 166,
5163
    MIPS_INS_CVT = 167,
5164
    MIPS_INS_C = 168,
5165
    MIPS_INS_CMPI = 169,
5166
    MIPS_INS_DADD = 170,
5167
    MIPS_INS_DADDI = 171,
5168
    MIPS_INS_DADDIU = 172,
5169
    MIPS_INS_DADDU = 173,
5170
    MIPS_INS_DAHI = 174,
5171
    MIPS_INS_DALIGN = 175,
5172
    MIPS_INS_DATI = 176,
5173
    MIPS_INS_DAUI = 177,
5174
    MIPS_INS_DBITSWAP = 178,
5175
    MIPS_INS_DCLO = 179,
5176
    MIPS_INS_DCLZ = 180,
5177
    MIPS_INS_DDIV = 181,
5178
    MIPS_INS_DDIVU = 182,
5179
    MIPS_INS_DERET = 183,
5180
    MIPS_INS_DEXT = 184,
5181
    MIPS_INS_DEXTM = 185,
5182
    MIPS_INS_DEXTU = 186,
5183
    MIPS_INS_DI = 187,
5184
    MIPS_INS_DINS = 188,
5185
    MIPS_INS_DINSM = 189,
5186
    MIPS_INS_DINSU = 190,
5187
    MIPS_INS_DIV = 191,
5188
    MIPS_INS_DIVU = 192,
5189
    MIPS_INS_DIV_S = 193,
5190
    MIPS_INS_DIV_U = 194,
5191
    MIPS_INS_DLSA = 195,
5192
    MIPS_INS_DMFC0 = 196,
5193
    MIPS_INS_DMFC1 = 197,
5194
    MIPS_INS_DMFC2 = 198,
5195
    MIPS_INS_DMOD = 199,
5196
    MIPS_INS_DMODU = 200,
5197
    MIPS_INS_DMTC0 = 201,
5198
    MIPS_INS_DMTC1 = 202,
5199
    MIPS_INS_DMTC2 = 203,
5200
    MIPS_INS_DMUH = 204,
5201
    MIPS_INS_DMUHU = 205,
5202
    MIPS_INS_DMUL = 206,
5203
    MIPS_INS_DMULT = 207,
5204
    MIPS_INS_DMULTU = 208,
5205
    MIPS_INS_DMULU = 209,
5206
    MIPS_INS_DOTP_S = 210,
5207
    MIPS_INS_DOTP_U = 211,
5208
    MIPS_INS_DPADD_S = 212,
5209
    MIPS_INS_DPADD_U = 213,
5210
    MIPS_INS_DPAQX_SA = 214,
5211
    MIPS_INS_DPAQX_S = 215,
5212
    MIPS_INS_DPAQ_SA = 216,
5213
    MIPS_INS_DPAQ_S = 217,
5214
    MIPS_INS_DPAU = 218,
5215
    MIPS_INS_DPAX = 219,
5216
    MIPS_INS_DPA = 220,
5217
    MIPS_INS_DPOP = 221,
5218
    MIPS_INS_DPSQX_SA = 222,
5219
    MIPS_INS_DPSQX_S = 223,
5220
    MIPS_INS_DPSQ_SA = 224,
5221
    MIPS_INS_DPSQ_S = 225,
5222
    MIPS_INS_DPSUB_S = 226,
5223
    MIPS_INS_DPSUB_U = 227,
5224
    MIPS_INS_DPSU = 228,
5225
    MIPS_INS_DPSX = 229,
5226
    MIPS_INS_DPS = 230,
5227
    MIPS_INS_DROTR = 231,
5228
    MIPS_INS_DROTR32 = 232,
5229
    MIPS_INS_DROTRV = 233,
5230
    MIPS_INS_DSBH = 234,
5231
    MIPS_INS_DSHD = 235,
5232
    MIPS_INS_DSLL = 236,
5233
    MIPS_INS_DSLL32 = 237,
5234
    MIPS_INS_DSLLV = 238,
5235
    MIPS_INS_DSRA = 239,
5236
    MIPS_INS_DSRA32 = 240,
5237
    MIPS_INS_DSRAV = 241,
5238
    MIPS_INS_DSRL = 242,
5239
    MIPS_INS_DSRL32 = 243,
5240
    MIPS_INS_DSRLV = 244,
5241
    MIPS_INS_DSUB = 245,
5242
    MIPS_INS_DSUBU = 246,
5243
    MIPS_INS_EHB = 247,
5244
    MIPS_INS_EI = 248,
5245
    MIPS_INS_ERET = 249,
5246
    MIPS_INS_EXT = 250,
5247
    MIPS_INS_EXTP = 251,
5248
    MIPS_INS_EXTPDP = 252,
5249
    MIPS_INS_EXTPDPV = 253,
5250
    MIPS_INS_EXTPV = 254,
5251
    MIPS_INS_EXTRV_RS = 255,
5252
    MIPS_INS_EXTRV_R = 256,
5253
    MIPS_INS_EXTRV_S = 257,
5254
    MIPS_INS_EXTRV = 258,
5255
    MIPS_INS_EXTR_RS = 259,
5256
    MIPS_INS_EXTR_R = 260,
5257
    MIPS_INS_EXTR_S = 261,
5258
    MIPS_INS_EXTR = 262,
5259
    MIPS_INS_EXTS = 263,
5260
    MIPS_INS_EXTS32 = 264,
5261
    MIPS_INS_ABS = 265,
5262
    MIPS_INS_FADD = 266,
5263
    MIPS_INS_FCAF = 267,
5264
    MIPS_INS_FCEQ = 268,
5265
    MIPS_INS_FCLASS = 269,
5266
    MIPS_INS_FCLE = 270,
5267
    MIPS_INS_FCLT = 271,
5268
    MIPS_INS_FCNE = 272,
5269
    MIPS_INS_FCOR = 273,
5270
    MIPS_INS_FCUEQ = 274,
5271
    MIPS_INS_FCULE = 275,
5272
    MIPS_INS_FCULT = 276,
5273
    MIPS_INS_FCUNE = 277,
5274
    MIPS_INS_FCUN = 278,
5275
    MIPS_INS_FDIV = 279,
5276
    MIPS_INS_FEXDO = 280,
5277
    MIPS_INS_FEXP2 = 281,
5278
    MIPS_INS_FEXUPL = 282,
5279
    MIPS_INS_FEXUPR = 283,
5280
    MIPS_INS_FFINT_S = 284,
5281
    MIPS_INS_FFINT_U = 285,
5282
    MIPS_INS_FFQL = 286,
5283
    MIPS_INS_FFQR = 287,
5284
    MIPS_INS_FILL = 288,
5285
    MIPS_INS_FLOG2 = 289,
5286
    MIPS_INS_FLOOR = 290,
5287
    MIPS_INS_FMADD = 291,
5288
    MIPS_INS_FMAX_A = 292,
5289
    MIPS_INS_FMAX = 293,
5290
    MIPS_INS_FMIN_A = 294,
5291
    MIPS_INS_FMIN = 295,
5292
    MIPS_INS_MOV = 296,
5293
    MIPS_INS_FMSUB = 297,
5294
    MIPS_INS_FMUL = 298,
5295
    MIPS_INS_MUL = 299,
5296
    MIPS_INS_NEG = 300,
5297
    MIPS_INS_FRCP = 301,
5298
    MIPS_INS_FRINT = 302,
5299
    MIPS_INS_FRSQRT = 303,
5300
    MIPS_INS_FSAF = 304,
5301
    MIPS_INS_FSEQ = 305,
5302
    MIPS_INS_FSLE = 306,
5303
    MIPS_INS_FSLT = 307,
5304
    MIPS_INS_FSNE = 308,
5305
    MIPS_INS_FSOR = 309,
5306
    MIPS_INS_FSQRT = 310,
5307
    MIPS_INS_SQRT = 311,
5308
    MIPS_INS_FSUB = 312,
5309
    MIPS_INS_SUB = 313,
5310
    MIPS_INS_FSUEQ = 314,
5311
    MIPS_INS_FSULE = 315,
5312
    MIPS_INS_FSULT = 316,
5313
    MIPS_INS_FSUNE = 317,
5314
    MIPS_INS_FSUN = 318,
5315
    MIPS_INS_FTINT_S = 319,
5316
    MIPS_INS_FTINT_U = 320,
5317
    MIPS_INS_FTQ = 321,
5318
    MIPS_INS_FTRUNC_S = 322,
5319
    MIPS_INS_FTRUNC_U = 323,
5320
    MIPS_INS_HADD_S = 324,
5321
    MIPS_INS_HADD_U = 325,
5322
    MIPS_INS_HSUB_S = 326,
5323
    MIPS_INS_HSUB_U = 327,
5324
    MIPS_INS_ILVEV = 328,
5325
    MIPS_INS_ILVL = 329,
5326
    MIPS_INS_ILVOD = 330,
5327
    MIPS_INS_ILVR = 331,
5328
    MIPS_INS_INS = 332,
5329
    MIPS_INS_INSERT = 333,
5330
    MIPS_INS_INSV = 334,
5331
    MIPS_INS_INSVE = 335,
5332
    MIPS_INS_J = 336,
5333
    MIPS_INS_JAL = 337,
5334
    MIPS_INS_JALR = 338,
5335
    MIPS_INS_JALRS16 = 339,
5336
    MIPS_INS_JALRS = 340,
5337
    MIPS_INS_JALS = 341,
5338
    MIPS_INS_JALX = 342,
5339
    MIPS_INS_JIALC = 343,
5340
    MIPS_INS_JIC = 344,
5341
    MIPS_INS_JR = 345,
5342
    MIPS_INS_JR16 = 346,
5343
    MIPS_INS_JRADDIUSP = 347,
5344
    MIPS_INS_JRC = 348,
5345
    MIPS_INS_JALRC = 349,
5346
    MIPS_INS_LB = 350,
5347
    MIPS_INS_LBU16 = 351,
5348
    MIPS_INS_LBUX = 352,
5349
    MIPS_INS_LBU = 353,
5350
    MIPS_INS_LD = 354,
5351
    MIPS_INS_LDC1 = 355,
5352
    MIPS_INS_LDC2 = 356,
5353
    MIPS_INS_LDC3 = 357,
5354
    MIPS_INS_LDI = 358,
5355
    MIPS_INS_LDL = 359,
5356
    MIPS_INS_LDPC = 360,
5357
    MIPS_INS_LDR = 361,
5358
    MIPS_INS_LDXC1 = 362,
5359
    MIPS_INS_LH = 363,
5360
    MIPS_INS_LHU16 = 364,
5361
    MIPS_INS_LHX = 365,
5362
    MIPS_INS_LHU = 366,
5363
    MIPS_INS_LI16 = 367,
5364
    MIPS_INS_LL = 368,
5365
    MIPS_INS_LLD = 369,
5366
    MIPS_INS_LSA = 370,
5367
    MIPS_INS_LUXC1 = 371,
5368
    MIPS_INS_LUI = 372,
5369
    MIPS_INS_LW = 373,
5370
    MIPS_INS_LW16 = 374,
5371
    MIPS_INS_LWC1 = 375,
5372
    MIPS_INS_LWC2 = 376,
5373
    MIPS_INS_LWC3 = 377,
5374
    MIPS_INS_LWL = 378,
5375
    MIPS_INS_LWM16 = 379,
5376
    MIPS_INS_LWM32 = 380,
5377
    MIPS_INS_LWPC = 381,
5378
    MIPS_INS_LWP = 382,
5379
    MIPS_INS_LWR = 383,
5380
    MIPS_INS_LWUPC = 384,
5381
    MIPS_INS_LWU = 385,
5382
    MIPS_INS_LWX = 386,
5383
    MIPS_INS_LWXC1 = 387,
5384
    MIPS_INS_LWXS = 388,
5385
    MIPS_INS_LI = 389,
5386
    MIPS_INS_MADD = 390,
5387
    MIPS_INS_MADDF = 391,
5388
    MIPS_INS_MADDR_Q = 392,
5389
    MIPS_INS_MADDU = 393,
5390
    MIPS_INS_MADDV = 394,
5391
    MIPS_INS_MADD_Q = 395,
5392
    MIPS_INS_MAQ_SA = 396,
5393
    MIPS_INS_MAQ_S = 397,
5394
    MIPS_INS_MAXA = 398,
5395
    MIPS_INS_MAXI_S = 399,
5396
    MIPS_INS_MAXI_U = 400,
5397
    MIPS_INS_MAX_A = 401,
5398
    MIPS_INS_MAX = 402,
5399
    MIPS_INS_MAX_S = 403,
5400
    MIPS_INS_MAX_U = 404,
5401
    MIPS_INS_MFC0 = 405,
5402
    MIPS_INS_MFC1 = 406,
5403
    MIPS_INS_MFC2 = 407,
5404
    MIPS_INS_MFHC1 = 408,
5405
    MIPS_INS_MFHI = 409,
5406
    MIPS_INS_MFLO = 410,
5407
    MIPS_INS_MINA = 411,
5408
    MIPS_INS_MINI_S = 412,
5409
    MIPS_INS_MINI_U = 413,
5410
    MIPS_INS_MIN_A = 414,
5411
    MIPS_INS_MIN = 415,
5412
    MIPS_INS_MIN_S = 416,
5413
    MIPS_INS_MIN_U = 417,
5414
    MIPS_INS_MOD = 418,
5415
    MIPS_INS_MODSUB = 419,
5416
    MIPS_INS_MODU = 420,
5417
    MIPS_INS_MOD_S = 421,
5418
    MIPS_INS_MOD_U = 422,
5419
    MIPS_INS_MOVE = 423,
5420
    MIPS_INS_MOVEP = 424,
5421
    MIPS_INS_MOVF = 425,
5422
    MIPS_INS_MOVN = 426,
5423
    MIPS_INS_MOVT = 427,
5424
    MIPS_INS_MOVZ = 428,
5425
    MIPS_INS_MSUB = 429,
5426
    MIPS_INS_MSUBF = 430,
5427
    MIPS_INS_MSUBR_Q = 431,
5428
    MIPS_INS_MSUBU = 432,
5429
    MIPS_INS_MSUBV = 433,
5430
    MIPS_INS_MSUB_Q = 434,
5431
    MIPS_INS_MTC0 = 435,
5432
    MIPS_INS_MTC1 = 436,
5433
    MIPS_INS_MTC2 = 437,
5434
    MIPS_INS_MTHC1 = 438,
5435
    MIPS_INS_MTHI = 439,
5436
    MIPS_INS_MTHLIP = 440,
5437
    MIPS_INS_MTLO = 441,
5438
    MIPS_INS_MTM0 = 442,
5439
    MIPS_INS_MTM1 = 443,
5440
    MIPS_INS_MTM2 = 444,
5441
    MIPS_INS_MTP0 = 445,
5442
    MIPS_INS_MTP1 = 446,
5443
    MIPS_INS_MTP2 = 447,
5444
    MIPS_INS_MUH = 448,
5445
    MIPS_INS_MUHU = 449,
5446
    MIPS_INS_MULEQ_S = 450,
5447
    MIPS_INS_MULEU_S = 451,
5448
    MIPS_INS_MULQ_RS = 452,
5449
    MIPS_INS_MULQ_S = 453,
5450
    MIPS_INS_MULR_Q = 454,
5451
    MIPS_INS_MULSAQ_S = 455,
5452
    MIPS_INS_MULSA = 456,
5453
    MIPS_INS_MULT = 457,
5454
    MIPS_INS_MULTU = 458,
5455
    MIPS_INS_MULU = 459,
5456
    MIPS_INS_MULV = 460,
5457
    MIPS_INS_MUL_Q = 461,
5458
    MIPS_INS_MUL_S = 462,
5459
    MIPS_INS_NLOC = 463,
5460
    MIPS_INS_NLZC = 464,
5461
    MIPS_INS_NMADD = 465,
5462
    MIPS_INS_NMSUB = 466,
5463
    MIPS_INS_NOR = 467,
5464
    MIPS_INS_NORI = 468,
5465
    MIPS_INS_NOT16 = 469,
5466
    MIPS_INS_NOT = 470,
5467
    MIPS_INS_OR = 471,
5468
    MIPS_INS_OR16 = 472,
5469
    MIPS_INS_ORI = 473,
5470
    MIPS_INS_PACKRL = 474,
5471
    MIPS_INS_PAUSE = 475,
5472
    MIPS_INS_PCKEV = 476,
5473
    MIPS_INS_PCKOD = 477,
5474
    MIPS_INS_PCNT = 478,
5475
    MIPS_INS_PICK = 479,
5476
    MIPS_INS_POP = 480,
5477
    MIPS_INS_PRECEQU = 481,
5478
    MIPS_INS_PRECEQ = 482,
5479
    MIPS_INS_PRECEU = 483,
5480
    MIPS_INS_PRECRQU_S = 484,
5481
    MIPS_INS_PRECRQ = 485,
5482
    MIPS_INS_PRECRQ_RS = 486,
5483
    MIPS_INS_PRECR = 487,
5484
    MIPS_INS_PRECR_SRA = 488,
5485
    MIPS_INS_PRECR_SRA_R = 489,
5486
    MIPS_INS_PREF = 490,
5487
    MIPS_INS_PREPEND = 491,
5488
    MIPS_INS_RADDU = 492,
5489
    MIPS_INS_RDDSP = 493,
5490
    MIPS_INS_RDHWR = 494,
5491
    MIPS_INS_REPLV = 495,
5492
    MIPS_INS_REPL = 496,
5493
    MIPS_INS_RINT = 497,
5494
    MIPS_INS_ROTR = 498,
5495
    MIPS_INS_ROTRV = 499,
5496
    MIPS_INS_ROUND = 500,
5497
    MIPS_INS_SAT_S = 501,
5498
    MIPS_INS_SAT_U = 502,
5499
    MIPS_INS_SB = 503,
5500
    MIPS_INS_SB16 = 504,
5501
    MIPS_INS_SC = 505,
5502
    MIPS_INS_SCD = 506,
5503
    MIPS_INS_SD = 507,
5504
    MIPS_INS_SDBBP = 508,
5505
    MIPS_INS_SDBBP16 = 509,
5506
    MIPS_INS_SDC1 = 510,
5507
    MIPS_INS_SDC2 = 511,
5508
    MIPS_INS_SDC3 = 512,
5509
    MIPS_INS_SDL = 513,
5510
    MIPS_INS_SDR = 514,
5511
    MIPS_INS_SDXC1 = 515,
5512
    MIPS_INS_SEB = 516,
5513
    MIPS_INS_SEH = 517,
5514
    MIPS_INS_SELEQZ = 518,
5515
    MIPS_INS_SELNEZ = 519,
5516
    MIPS_INS_SEL = 520,
5517
    MIPS_INS_SEQ = 521,
5518
    MIPS_INS_SEQI = 522,
5519
    MIPS_INS_SH = 523,
5520
    MIPS_INS_SH16 = 524,
5521
    MIPS_INS_SHF = 525,
5522
    MIPS_INS_SHILO = 526,
5523
    MIPS_INS_SHILOV = 527,
5524
    MIPS_INS_SHLLV = 528,
5525
    MIPS_INS_SHLLV_S = 529,
5526
    MIPS_INS_SHLL = 530,
5527
    MIPS_INS_SHLL_S = 531,
5528
    MIPS_INS_SHRAV = 532,
5529
    MIPS_INS_SHRAV_R = 533,
5530
    MIPS_INS_SHRA = 534,
5531
    MIPS_INS_SHRA_R = 535,
5532
    MIPS_INS_SHRLV = 536,
5533
    MIPS_INS_SHRL = 537,
5534
    MIPS_INS_SLDI = 538,
5535
    MIPS_INS_SLD = 539,
5536
    MIPS_INS_SLL = 540,
5537
    MIPS_INS_SLL16 = 541,
5538
    MIPS_INS_SLLI = 542,
5539
    MIPS_INS_SLLV = 543,
5540
    MIPS_INS_SLT = 544,
5541
    MIPS_INS_SLTI = 545,
5542
    MIPS_INS_SLTIU = 546,
5543
    MIPS_INS_SLTU = 547,
5544
    MIPS_INS_SNE = 548,
5545
    MIPS_INS_SNEI = 549,
5546
    MIPS_INS_SPLATI = 550,
5547
    MIPS_INS_SPLAT = 551,
5548
    MIPS_INS_SRA = 552,
5549
    MIPS_INS_SRAI = 553,
5550
    MIPS_INS_SRARI = 554,
5551
    MIPS_INS_SRAR = 555,
5552
    MIPS_INS_SRAV = 556,
5553
    MIPS_INS_SRL = 557,
5554
    MIPS_INS_SRL16 = 558,
5555
    MIPS_INS_SRLI = 559,
5556
    MIPS_INS_SRLRI = 560,
5557
    MIPS_INS_SRLR = 561,
5558
    MIPS_INS_SRLV = 562,
5559
    MIPS_INS_SSNOP = 563,
5560
    MIPS_INS_ST = 564,
5561
    MIPS_INS_SUBQH = 565,
5562
    MIPS_INS_SUBQH_R = 566,
5563
    MIPS_INS_SUBQ = 567,
5564
    MIPS_INS_SUBQ_S = 568,
5565
    MIPS_INS_SUBSUS_U = 569,
5566
    MIPS_INS_SUBSUU_S = 570,
5567
    MIPS_INS_SUBS_S = 571,
5568
    MIPS_INS_SUBS_U = 572,
5569
    MIPS_INS_SUBU16 = 573,
5570
    MIPS_INS_SUBUH = 574,
5571
    MIPS_INS_SUBUH_R = 575,
5572
    MIPS_INS_SUBU = 576,
5573
    MIPS_INS_SUBU_S = 577,
5574
    MIPS_INS_SUBVI = 578,
5575
    MIPS_INS_SUBV = 579,
5576
    MIPS_INS_SUXC1 = 580,
5577
    MIPS_INS_SW = 581,
5578
    MIPS_INS_SW16 = 582,
5579
    MIPS_INS_SWC1 = 583,
5580
    MIPS_INS_SWC2 = 584,
5581
    MIPS_INS_SWC3 = 585,
5582
    MIPS_INS_SWL = 586,
5583
    MIPS_INS_SWM16 = 587,
5584
    MIPS_INS_SWM32 = 588,
5585
    MIPS_INS_SWP = 589,
5586
    MIPS_INS_SWR = 590,
5587
    MIPS_INS_SWXC1 = 591,
5588
    MIPS_INS_SYNC = 592,
5589
    MIPS_INS_SYNCI = 593,
5590
    MIPS_INS_SYSCALL = 594,
5591
    MIPS_INS_TEQ = 595,
5592
    MIPS_INS_TEQI = 596,
5593
    MIPS_INS_TGE = 597,
5594
    MIPS_INS_TGEI = 598,
5595
    MIPS_INS_TGEIU = 599,
5596
    MIPS_INS_TGEU = 600,
5597
    MIPS_INS_TLBP = 601,
5598
    MIPS_INS_TLBR = 602,
5599
    MIPS_INS_TLBWI = 603,
5600
    MIPS_INS_TLBWR = 604,
5601
    MIPS_INS_TLT = 605,
5602
    MIPS_INS_TLTI = 606,
5603
    MIPS_INS_TLTIU = 607,
5604
    MIPS_INS_TLTU = 608,
5605
    MIPS_INS_TNE = 609,
5606
    MIPS_INS_TNEI = 610,
5607
    MIPS_INS_TRUNC = 611,
5608
    MIPS_INS_V3MULU = 612,
5609
    MIPS_INS_VMM0 = 613,
5610
    MIPS_INS_VMULU = 614,
5611
    MIPS_INS_VSHF = 615,
5612
    MIPS_INS_WAIT = 616,
5613
    MIPS_INS_WRDSP = 617,
5614
    MIPS_INS_WSBH = 618,
5615
    MIPS_INS_XOR = 619,
5616
    MIPS_INS_XOR16 = 620,
5617
    MIPS_INS_XORI = 621,
5618
    MIPS_INS_NOP = 622,
5619
    MIPS_INS_NEGU = 623,
5620
    MIPS_INS_JALR_HB = 624,
5621
    MIPS_INS_JR_HB = 625,
5622
    MIPS_INS_ENDING = 626,
5623
}
5624
pub mod mips_insn_group {
5625
    #[doc = " Group of MIPS instructions"]
5626
    pub type Type = libc::c_uint;
5627
    #[doc = "< = CS_GRP_INVALID"]
5628
    pub const MIPS_GRP_INVALID: Type = 0;
5629
    #[doc = "< = CS_GRP_JUMP"]
5630
    pub const MIPS_GRP_JUMP: Type = 1;
5631
    #[doc = "< = CS_GRP_CALL"]
5632
    pub const MIPS_GRP_CALL: Type = 2;
5633
    #[doc = "< = CS_GRP_RET"]
5634
    pub const MIPS_GRP_RET: Type = 3;
5635
    #[doc = "< = CS_GRP_INT"]
5636
    pub const MIPS_GRP_INT: Type = 4;
5637
    #[doc = "< = CS_GRP_IRET"]
5638
    pub const MIPS_GRP_IRET: Type = 5;
5639
    #[doc = "< = CS_GRP_PRIVILEGE"]
5640
    pub const MIPS_GRP_PRIVILEGE: Type = 6;
5641
    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
5642
    pub const MIPS_GRP_BRANCH_RELATIVE: Type = 7;
5643
    pub const MIPS_GRP_BITCOUNT: Type = 128;
5644
    pub const MIPS_GRP_DSP: Type = 129;
5645
    pub const MIPS_GRP_DSPR2: Type = 130;
5646
    pub const MIPS_GRP_FPIDX: Type = 131;
5647
    pub const MIPS_GRP_MSA: Type = 132;
5648
    pub const MIPS_GRP_MIPS32R2: Type = 133;
5649
    pub const MIPS_GRP_MIPS64: Type = 134;
5650
    pub const MIPS_GRP_MIPS64R2: Type = 135;
5651
    pub const MIPS_GRP_SEINREG: Type = 136;
5652
    pub const MIPS_GRP_STDENC: Type = 137;
5653
    pub const MIPS_GRP_SWAP: Type = 138;
5654
    pub const MIPS_GRP_MICROMIPS: Type = 139;
5655
    pub const MIPS_GRP_MIPS16MODE: Type = 140;
5656
    pub const MIPS_GRP_FP64BIT: Type = 141;
5657
    pub const MIPS_GRP_NONANSFPMATH: Type = 142;
5658
    pub const MIPS_GRP_NOTFP64BIT: Type = 143;
5659
    pub const MIPS_GRP_NOTINMICROMIPS: Type = 144;
5660
    pub const MIPS_GRP_NOTNACL: Type = 145;
5661
    pub const MIPS_GRP_NOTMIPS32R6: Type = 146;
5662
    pub const MIPS_GRP_NOTMIPS64R6: Type = 147;
5663
    pub const MIPS_GRP_CNMIPS: Type = 148;
5664
    pub const MIPS_GRP_MIPS32: Type = 149;
5665
    pub const MIPS_GRP_MIPS32R6: Type = 150;
5666
    pub const MIPS_GRP_MIPS64R6: Type = 151;
5667
    pub const MIPS_GRP_MIPS2: Type = 152;
5668
    pub const MIPS_GRP_MIPS3: Type = 153;
5669
    pub const MIPS_GRP_MIPS3_32: Type = 154;
5670
    pub const MIPS_GRP_MIPS3_32R2: Type = 155;
5671
    pub const MIPS_GRP_MIPS4_32: Type = 156;
5672
    pub const MIPS_GRP_MIPS4_32R2: Type = 157;
5673
    pub const MIPS_GRP_MIPS5_32R2: Type = 158;
5674
    pub const MIPS_GRP_GP32BIT: Type = 159;
5675
    pub const MIPS_GRP_GP64BIT: Type = 160;
5676
    pub const MIPS_GRP_ENDING: Type = 161;
5677
}
5678
#[repr(u32)]
5679
#[doc = " PPC branch codes for some branch instructions"]
5680
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
5681
pub enum ppc_bc {
5682
    PPC_BC_INVALID = 0,
5683
    PPC_BC_LT = 12,
5684
    PPC_BC_LE = 36,
5685
    PPC_BC_EQ = 76,
5686
    PPC_BC_GE = 4,
5687
    PPC_BC_GT = 44,
5688
    PPC_BC_NE = 68,
5689
    PPC_BC_UN = 108,
5690
    PPC_BC_NU = 100,
5691
    #[doc = "< summary overflow"]
5692
    PPC_BC_SO = 140,
5693
    #[doc = "< not summary overflow"]
5694
    PPC_BC_NS = 132,
5695
}
5696
#[repr(u32)]
5697
#[doc = " PPC branch hint for some branch instructions"]
5698
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
5699
pub enum ppc_bh {
5700
    #[doc = "< no hint"]
5701
    PPC_BH_INVALID = 0,
5702
    #[doc = "< PLUS hint"]
5703
    PPC_BH_PLUS = 1,
5704
    #[doc = "< MINUS hint"]
5705
    PPC_BH_MINUS = 2,
5706
}
5707
#[repr(u32)]
5708
#[doc = " Operand type for instruction's operands"]
5709
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
5710
pub enum ppc_op_type {
5711
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
5712
    PPC_OP_INVALID = 0,
5713
    #[doc = "< = CS_OP_REG (Register operand)."]
5714
    PPC_OP_REG = 1,
5715
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
5716
    PPC_OP_IMM = 2,
5717
    #[doc = "< = CS_OP_MEM (Memory operand)."]
5718
    PPC_OP_MEM = 3,
5719
    #[doc = "< Condition Register field"]
5720
    PPC_OP_CRX = 64,
5721
}
5722
pub mod ppc_reg {
5723
    #[doc = " PPC registers"]
5724
    pub type Type = libc::c_uint;
5725
    pub const PPC_REG_INVALID: Type = 0;
5726
    pub const PPC_REG_CARRY: Type = 2;
5727
    pub const PPC_REG_CTR: Type = 3;
5728
    pub const PPC_REG_LR: Type = 5;
5729
    pub const PPC_REG_RM: Type = 6;
5730
    pub const PPC_REG_VRSAVE: Type = 8;
5731
    pub const PPC_REG_XER: Type = 9;
5732
    pub const PPC_REG_ZERO: Type = 10;
5733
    pub const PPC_REG_CR0: Type = 12;
5734
    pub const PPC_REG_CR1: Type = 13;
5735
    pub const PPC_REG_CR2: Type = 14;
5736
    pub const PPC_REG_CR3: Type = 15;
5737
    pub const PPC_REG_CR4: Type = 16;
5738
    pub const PPC_REG_CR5: Type = 17;
5739
    pub const PPC_REG_CR6: Type = 18;
5740
    pub const PPC_REG_CR7: Type = 19;
5741
    pub const PPC_REG_CTR8: Type = 20;
5742
    pub const PPC_REG_F0: Type = 21;
5743
    pub const PPC_REG_F1: Type = 22;
5744
    pub const PPC_REG_F2: Type = 23;
5745
    pub const PPC_REG_F3: Type = 24;
5746
    pub const PPC_REG_F4: Type = 25;
5747
    pub const PPC_REG_F5: Type = 26;
5748
    pub const PPC_REG_F6: Type = 27;
5749
    pub const PPC_REG_F7: Type = 28;
5750
    pub const PPC_REG_F8: Type = 29;
5751
    pub const PPC_REG_F9: Type = 30;
5752
    pub const PPC_REG_F10: Type = 31;
5753
    pub const PPC_REG_F11: Type = 32;
5754
    pub const PPC_REG_F12: Type = 33;
5755
    pub const PPC_REG_F13: Type = 34;
5756
    pub const PPC_REG_F14: Type = 35;
5757
    pub const PPC_REG_F15: Type = 36;
5758
    pub const PPC_REG_F16: Type = 37;
5759
    pub const PPC_REG_F17: Type = 38;
5760
    pub const PPC_REG_F18: Type = 39;
5761
    pub const PPC_REG_F19: Type = 40;
5762
    pub const PPC_REG_F20: Type = 41;
5763
    pub const PPC_REG_F21: Type = 42;
5764
    pub const PPC_REG_F22: Type = 43;
5765
    pub const PPC_REG_F23: Type = 44;
5766
    pub const PPC_REG_F24: Type = 45;
5767
    pub const PPC_REG_F25: Type = 46;
5768
    pub const PPC_REG_F26: Type = 47;
5769
    pub const PPC_REG_F27: Type = 48;
5770
    pub const PPC_REG_F28: Type = 49;
5771
    pub const PPC_REG_F29: Type = 50;
5772
    pub const PPC_REG_F30: Type = 51;
5773
    pub const PPC_REG_F31: Type = 52;
5774
    pub const PPC_REG_LR8: Type = 54;
5775
    pub const PPC_REG_Q0: Type = 55;
5776
    pub const PPC_REG_Q1: Type = 56;
5777
    pub const PPC_REG_Q2: Type = 57;
5778
    pub const PPC_REG_Q3: Type = 58;
5779
    pub const PPC_REG_Q4: Type = 59;
5780
    pub const PPC_REG_Q5: Type = 60;
5781
    pub const PPC_REG_Q6: Type = 61;
5782
    pub const PPC_REG_Q7: Type = 62;
5783
    pub const PPC_REG_Q8: Type = 63;
5784
    pub const PPC_REG_Q9: Type = 64;
5785
    pub const PPC_REG_Q10: Type = 65;
5786
    pub const PPC_REG_Q11: Type = 66;
5787
    pub const PPC_REG_Q12: Type = 67;
5788
    pub const PPC_REG_Q13: Type = 68;
5789
    pub const PPC_REG_Q14: Type = 69;
5790
    pub const PPC_REG_Q15: Type = 70;
5791
    pub const PPC_REG_Q16: Type = 71;
5792
    pub const PPC_REG_Q17: Type = 72;
5793
    pub const PPC_REG_Q18: Type = 73;
5794
    pub const PPC_REG_Q19: Type = 74;
5795
    pub const PPC_REG_Q20: Type = 75;
5796
    pub const PPC_REG_Q21: Type = 76;
5797
    pub const PPC_REG_Q22: Type = 77;
5798
    pub const PPC_REG_Q23: Type = 78;
5799
    pub const PPC_REG_Q24: Type = 79;
5800
    pub const PPC_REG_Q25: Type = 80;
5801
    pub const PPC_REG_Q26: Type = 81;
5802
    pub const PPC_REG_Q27: Type = 82;
5803
    pub const PPC_REG_Q28: Type = 83;
5804
    pub const PPC_REG_Q29: Type = 84;
5805
    pub const PPC_REG_Q30: Type = 85;
5806
    pub const PPC_REG_Q31: Type = 86;
5807
    pub const PPC_REG_R0: Type = 87;
5808
    pub const PPC_REG_R1: Type = 88;
5809
    pub const PPC_REG_R2: Type = 89;
5810
    pub const PPC_REG_R3: Type = 90;
5811
    pub const PPC_REG_R4: Type = 91;
5812
    pub const PPC_REG_R5: Type = 92;
5813
    pub const PPC_REG_R6: Type = 93;
5814
    pub const PPC_REG_R7: Type = 94;
5815
    pub const PPC_REG_R8: Type = 95;
5816
    pub const PPC_REG_R9: Type = 96;
5817
    pub const PPC_REG_R10: Type = 97;
5818
    pub const PPC_REG_R11: Type = 98;
5819
    pub const PPC_REG_R12: Type = 99;
5820
    pub const PPC_REG_R13: Type = 100;
5821
    pub const PPC_REG_R14: Type = 101;
5822
    pub const PPC_REG_R15: Type = 102;
5823
    pub const PPC_REG_R16: Type = 103;
5824
    pub const PPC_REG_R17: Type = 104;
5825
    pub const PPC_REG_R18: Type = 105;
5826
    pub const PPC_REG_R19: Type = 106;
5827
    pub const PPC_REG_R20: Type = 107;
5828
    pub const PPC_REG_R21: Type = 108;
5829
    pub const PPC_REG_R22: Type = 109;
5830
    pub const PPC_REG_R23: Type = 110;
5831
    pub const PPC_REG_R24: Type = 111;
5832
    pub const PPC_REG_R25: Type = 112;
5833
    pub const PPC_REG_R26: Type = 113;
5834
    pub const PPC_REG_R27: Type = 114;
5835
    pub const PPC_REG_R28: Type = 115;
5836
    pub const PPC_REG_R29: Type = 116;
5837
    pub const PPC_REG_R30: Type = 117;
5838
    pub const PPC_REG_R31: Type = 118;
5839
    pub const PPC_REG_V0: Type = 151;
5840
    pub const PPC_REG_V1: Type = 152;
5841
    pub const PPC_REG_V2: Type = 153;
5842
    pub const PPC_REG_V3: Type = 154;
5843
    pub const PPC_REG_V4: Type = 155;
5844
    pub const PPC_REG_V5: Type = 156;
5845
    pub const PPC_REG_V6: Type = 157;
5846
    pub const PPC_REG_V7: Type = 158;
5847
    pub const PPC_REG_V8: Type = 159;
5848
    pub const PPC_REG_V9: Type = 160;
5849
    pub const PPC_REG_V10: Type = 161;
5850
    pub const PPC_REG_V11: Type = 162;
5851
    pub const PPC_REG_V12: Type = 163;
5852
    pub const PPC_REG_V13: Type = 164;
5853
    pub const PPC_REG_V14: Type = 165;
5854
    pub const PPC_REG_V15: Type = 166;
5855
    pub const PPC_REG_V16: Type = 167;
5856
    pub const PPC_REG_V17: Type = 168;
5857
    pub const PPC_REG_V18: Type = 169;
5858
    pub const PPC_REG_V19: Type = 170;
5859
    pub const PPC_REG_V20: Type = 171;
5860
    pub const PPC_REG_V21: Type = 172;
5861
    pub const PPC_REG_V22: Type = 173;
5862
    pub const PPC_REG_V23: Type = 174;
5863
    pub const PPC_REG_V24: Type = 175;
5864
    pub const PPC_REG_V25: Type = 176;
5865
    pub const PPC_REG_V26: Type = 177;
5866
    pub const PPC_REG_V27: Type = 178;
5867
    pub const PPC_REG_V28: Type = 179;
5868
    pub const PPC_REG_V29: Type = 180;
5869
    pub const PPC_REG_V30: Type = 181;
5870
    pub const PPC_REG_V31: Type = 182;
5871
    pub const PPC_REG_VS0: Type = 215;
5872
    pub const PPC_REG_VS1: Type = 216;
5873
    pub const PPC_REG_VS2: Type = 217;
5874
    pub const PPC_REG_VS3: Type = 218;
5875
    pub const PPC_REG_VS4: Type = 219;
5876
    pub const PPC_REG_VS5: Type = 220;
5877
    pub const PPC_REG_VS6: Type = 221;
5878
    pub const PPC_REG_VS7: Type = 222;
5879
    pub const PPC_REG_VS8: Type = 223;
5880
    pub const PPC_REG_VS9: Type = 224;
5881
    pub const PPC_REG_VS10: Type = 225;
5882
    pub const PPC_REG_VS11: Type = 226;
5883
    pub const PPC_REG_VS12: Type = 227;
5884
    pub const PPC_REG_VS13: Type = 228;
5885
    pub const PPC_REG_VS14: Type = 229;
5886
    pub const PPC_REG_VS15: Type = 230;
5887
    pub const PPC_REG_VS16: Type = 231;
5888
    pub const PPC_REG_VS17: Type = 232;
5889
    pub const PPC_REG_VS18: Type = 233;
5890
    pub const PPC_REG_VS19: Type = 234;
5891
    pub const PPC_REG_VS20: Type = 235;
5892
    pub const PPC_REG_VS21: Type = 236;
5893
    pub const PPC_REG_VS22: Type = 237;
5894
    pub const PPC_REG_VS23: Type = 238;
5895
    pub const PPC_REG_VS24: Type = 239;
5896
    pub const PPC_REG_VS25: Type = 240;
5897
    pub const PPC_REG_VS26: Type = 241;
5898
    pub const PPC_REG_VS27: Type = 242;
5899
    pub const PPC_REG_VS28: Type = 243;
5900
    pub const PPC_REG_VS29: Type = 244;
5901
    pub const PPC_REG_VS30: Type = 245;
5902
    pub const PPC_REG_VS31: Type = 246;
5903
    pub const PPC_REG_VS32: Type = 247;
5904
    pub const PPC_REG_VS33: Type = 248;
5905
    pub const PPC_REG_VS34: Type = 249;
5906
    pub const PPC_REG_VS35: Type = 250;
5907
    pub const PPC_REG_VS36: Type = 251;
5908
    pub const PPC_REG_VS37: Type = 252;
5909
    pub const PPC_REG_VS38: Type = 253;
5910
    pub const PPC_REG_VS39: Type = 254;
5911
    pub const PPC_REG_VS40: Type = 255;
5912
    pub const PPC_REG_VS41: Type = 256;
5913
    pub const PPC_REG_VS42: Type = 257;
5914
    pub const PPC_REG_VS43: Type = 258;
5915
    pub const PPC_REG_VS44: Type = 259;
5916
    pub const PPC_REG_VS45: Type = 260;
5917
    pub const PPC_REG_VS46: Type = 261;
5918
    pub const PPC_REG_VS47: Type = 262;
5919
    pub const PPC_REG_VS48: Type = 263;
5920
    pub const PPC_REG_VS49: Type = 264;
5921
    pub const PPC_REG_VS50: Type = 265;
5922
    pub const PPC_REG_VS51: Type = 266;
5923
    pub const PPC_REG_VS52: Type = 267;
5924
    pub const PPC_REG_VS53: Type = 268;
5925
    pub const PPC_REG_VS54: Type = 269;
5926
    pub const PPC_REG_VS55: Type = 270;
5927
    pub const PPC_REG_VS56: Type = 271;
5928
    pub const PPC_REG_VS57: Type = 272;
5929
    pub const PPC_REG_VS58: Type = 273;
5930
    pub const PPC_REG_VS59: Type = 274;
5931
    pub const PPC_REG_VS60: Type = 275;
5932
    pub const PPC_REG_VS61: Type = 276;
5933
    pub const PPC_REG_VS62: Type = 277;
5934
    pub const PPC_REG_VS63: Type = 278;
5935
    pub const PPC_REG_CR0EQ: Type = 312;
5936
    pub const PPC_REG_CR1EQ: Type = 313;
5937
    pub const PPC_REG_CR2EQ: Type = 314;
5938
    pub const PPC_REG_CR3EQ: Type = 315;
5939
    pub const PPC_REG_CR4EQ: Type = 316;
5940
    pub const PPC_REG_CR5EQ: Type = 317;
5941
    pub const PPC_REG_CR6EQ: Type = 318;
5942
    pub const PPC_REG_CR7EQ: Type = 319;
5943
    pub const PPC_REG_CR0GT: Type = 320;
5944
    pub const PPC_REG_CR1GT: Type = 321;
5945
    pub const PPC_REG_CR2GT: Type = 322;
5946
    pub const PPC_REG_CR3GT: Type = 323;
5947
    pub const PPC_REG_CR4GT: Type = 324;
5948
    pub const PPC_REG_CR5GT: Type = 325;
5949
    pub const PPC_REG_CR6GT: Type = 326;
5950
    pub const PPC_REG_CR7GT: Type = 327;
5951
    pub const PPC_REG_CR0LT: Type = 328;
5952
    pub const PPC_REG_CR1LT: Type = 329;
5953
    pub const PPC_REG_CR2LT: Type = 330;
5954
    pub const PPC_REG_CR3LT: Type = 331;
5955
    pub const PPC_REG_CR4LT: Type = 332;
5956
    pub const PPC_REG_CR5LT: Type = 333;
5957
    pub const PPC_REG_CR6LT: Type = 334;
5958
    pub const PPC_REG_CR7LT: Type = 335;
5959
    pub const PPC_REG_CR0UN: Type = 336;
5960
    pub const PPC_REG_CR1UN: Type = 337;
5961
    pub const PPC_REG_CR2UN: Type = 338;
5962
    pub const PPC_REG_CR3UN: Type = 339;
5963
    pub const PPC_REG_CR4UN: Type = 340;
5964
    pub const PPC_REG_CR5UN: Type = 341;
5965
    pub const PPC_REG_CR6UN: Type = 342;
5966
    pub const PPC_REG_CR7UN: Type = 343;
5967
    pub const PPC_REG_ENDING: Type = 344;
5968
}
5969
#[doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"]
5970
#[repr(C)]
5971
#[derive(Debug, Copy, Clone)]
5972
pub struct ppc_op_mem {
5973
    #[doc = "< base register"]
5974
    pub base: ppc_reg::Type,
5975
    #[doc = "< displacement/offset value"]
5976
    pub disp: i32,
5977
}
5978
#[repr(C)]
5979
#[derive(Debug, Copy, Clone)]
5980
pub struct ppc_op_crx {
5981
    pub scale: libc::c_uint,
5982
    pub reg: ppc_reg::Type,
5983
    pub cond: ppc_bc,
5984
}
5985
#[doc = " Instruction operand"]
5986
#[repr(C)]
5987
#[derive(Copy, Clone)]
5988
pub struct cs_ppc_op {
5989
    #[doc = "< operand type"]
5990
    pub type_: ppc_op_type,
5991
    pub __bindgen_anon_1: cs_ppc_op__bindgen_ty_1,
5992
}
5993
#[repr(C)]
5994
#[derive(Copy, Clone)]
5995
pub union cs_ppc_op__bindgen_ty_1 {
5996
    #[doc = "< register value for REG operand"]
5997
    pub reg: ppc_reg::Type,
5998
    #[doc = "< immediate value for IMM operand"]
5999
    pub imm: i64,
6000
    #[doc = "< base/disp value for MEM operand"]
6001
    pub mem: ppc_op_mem,
6002
    #[doc = "< operand with condition register"]
6003
    pub crx: ppc_op_crx,
6004
}
6005
impl ::core::fmt::Debug for cs_ppc_op__bindgen_ty_1 {
6006
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
6007
0
        write!(f, "cs_ppc_op__bindgen_ty_1 {{ union }}")
6008
0
    }
6009
}
6010
impl ::core::fmt::Debug for cs_ppc_op {
6011
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
6012
0
        write!(
6013
0
            f,
6014
0
            "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
6015
            self.type_, self.__bindgen_anon_1
6016
        )
6017
0
    }
6018
}
6019
#[doc = " Instruction structure"]
6020
#[repr(C)]
6021
#[derive(Copy, Clone)]
6022
pub struct cs_ppc {
6023
    #[doc = " branch code for branch instructions"]
6024
    pub bc: ppc_bc,
6025
    #[doc = " branch hint for branch instructions"]
6026
    pub bh: ppc_bh,
6027
    #[doc = " if update_cr0 = True, then this 'dot' insn updates CR0"]
6028
    pub update_cr0: bool,
6029
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
6030
    pub op_count: u8,
6031
    #[doc = "< operands for this instruction."]
6032
    pub operands: [cs_ppc_op; 8usize],
6033
}
6034
impl ::core::fmt::Debug for cs_ppc {
6035
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
6036
0
        write!(
6037
0
            f,
6038
0
            "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, operands: {:?} }}",
6039
            self.bc, self.bh, self.update_cr0, self.operands
6040
        )
6041
0
    }
6042
}
6043
#[repr(u32)]
6044
#[doc = " PPC instruction"]
6045
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
6046
pub enum ppc_insn {
6047
    PPC_INS_INVALID = 0,
6048
    PPC_INS_ADD = 1,
6049
    PPC_INS_ADDC = 2,
6050
    PPC_INS_ADDE = 3,
6051
    PPC_INS_ADDI = 4,
6052
    PPC_INS_ADDIC = 5,
6053
    PPC_INS_ADDIS = 6,
6054
    PPC_INS_ADDME = 7,
6055
    PPC_INS_ADDPCIS = 8,
6056
    PPC_INS_ADDZE = 9,
6057
    PPC_INS_AND = 10,
6058
    PPC_INS_ANDC = 11,
6059
    PPC_INS_ANDI = 12,
6060
    PPC_INS_ANDIS = 13,
6061
    PPC_INS_ATTN = 14,
6062
    PPC_INS_B = 15,
6063
    PPC_INS_BA = 16,
6064
    PPC_INS_BC = 17,
6065
    PPC_INS_BCA = 18,
6066
    PPC_INS_BCCTR = 19,
6067
    PPC_INS_BCCTRL = 20,
6068
    PPC_INS_BCDCFN = 21,
6069
    PPC_INS_BCDCFSQ = 22,
6070
    PPC_INS_BCDCFZ = 23,
6071
    PPC_INS_BCDCPSGN = 24,
6072
    PPC_INS_BCDCTN = 25,
6073
    PPC_INS_BCDCTSQ = 26,
6074
    PPC_INS_BCDCTZ = 27,
6075
    PPC_INS_BCDS = 28,
6076
    PPC_INS_BCDSETSGN = 29,
6077
    PPC_INS_BCDSR = 30,
6078
    PPC_INS_BCDTRUNC = 31,
6079
    PPC_INS_BCDUS = 32,
6080
    PPC_INS_BCDUTRUNC = 33,
6081
    PPC_INS_BCL = 34,
6082
    PPC_INS_BCLA = 35,
6083
    PPC_INS_BCLR = 36,
6084
    PPC_INS_BCLRL = 37,
6085
    PPC_INS_BCTR = 38,
6086
    PPC_INS_BCTRL = 39,
6087
    PPC_INS_BDNZ = 40,
6088
    PPC_INS_BDNZA = 41,
6089
    PPC_INS_BDNZF = 42,
6090
    PPC_INS_BDNZFA = 43,
6091
    PPC_INS_BDNZFL = 44,
6092
    PPC_INS_BDNZFLA = 45,
6093
    PPC_INS_BDNZFLR = 46,
6094
    PPC_INS_BDNZFLRL = 47,
6095
    PPC_INS_BDNZL = 48,
6096
    PPC_INS_BDNZLA = 49,
6097
    PPC_INS_BDNZLR = 50,
6098
    PPC_INS_BDNZLRL = 51,
6099
    PPC_INS_BDNZT = 52,
6100
    PPC_INS_BDNZTA = 53,
6101
    PPC_INS_BDNZTL = 54,
6102
    PPC_INS_BDNZTLA = 55,
6103
    PPC_INS_BDNZTLR = 56,
6104
    PPC_INS_BDNZTLRL = 57,
6105
    PPC_INS_BDZ = 58,
6106
    PPC_INS_BDZA = 59,
6107
    PPC_INS_BDZF = 60,
6108
    PPC_INS_BDZFA = 61,
6109
    PPC_INS_BDZFL = 62,
6110
    PPC_INS_BDZFLA = 63,
6111
    PPC_INS_BDZFLR = 64,
6112
    PPC_INS_BDZFLRL = 65,
6113
    PPC_INS_BDZL = 66,
6114
    PPC_INS_BDZLA = 67,
6115
    PPC_INS_BDZLR = 68,
6116
    PPC_INS_BDZLRL = 69,
6117
    PPC_INS_BDZT = 70,
6118
    PPC_INS_BDZTA = 71,
6119
    PPC_INS_BDZTL = 72,
6120
    PPC_INS_BDZTLA = 73,
6121
    PPC_INS_BDZTLR = 74,
6122
    PPC_INS_BDZTLRL = 75,
6123
    PPC_INS_BEQ = 76,
6124
    PPC_INS_BEQA = 77,
6125
    PPC_INS_BEQCTR = 78,
6126
    PPC_INS_BEQCTRL = 79,
6127
    PPC_INS_BEQL = 80,
6128
    PPC_INS_BEQLA = 81,
6129
    PPC_INS_BEQLR = 82,
6130
    PPC_INS_BEQLRL = 83,
6131
    PPC_INS_BF = 84,
6132
    PPC_INS_BFA = 85,
6133
    PPC_INS_BFCTR = 86,
6134
    PPC_INS_BFCTRL = 87,
6135
    PPC_INS_BFL = 88,
6136
    PPC_INS_BFLA = 89,
6137
    PPC_INS_BFLR = 90,
6138
    PPC_INS_BFLRL = 91,
6139
    PPC_INS_BGE = 92,
6140
    PPC_INS_BGEA = 93,
6141
    PPC_INS_BGECTR = 94,
6142
    PPC_INS_BGECTRL = 95,
6143
    PPC_INS_BGEL = 96,
6144
    PPC_INS_BGELA = 97,
6145
    PPC_INS_BGELR = 98,
6146
    PPC_INS_BGELRL = 99,
6147
    PPC_INS_BGT = 100,
6148
    PPC_INS_BGTA = 101,
6149
    PPC_INS_BGTCTR = 102,
6150
    PPC_INS_BGTCTRL = 103,
6151
    PPC_INS_BGTL = 104,
6152
    PPC_INS_BGTLA = 105,
6153
    PPC_INS_BGTLR = 106,
6154
    PPC_INS_BGTLRL = 107,
6155
    PPC_INS_BL = 108,
6156
    PPC_INS_BLA = 109,
6157
    PPC_INS_BLE = 110,
6158
    PPC_INS_BLEA = 111,
6159
    PPC_INS_BLECTR = 112,
6160
    PPC_INS_BLECTRL = 113,
6161
    PPC_INS_BLEL = 114,
6162
    PPC_INS_BLELA = 115,
6163
    PPC_INS_BLELR = 116,
6164
    PPC_INS_BLELRL = 117,
6165
    PPC_INS_BLR = 118,
6166
    PPC_INS_BLRL = 119,
6167
    PPC_INS_BLT = 120,
6168
    PPC_INS_BLTA = 121,
6169
    PPC_INS_BLTCTR = 122,
6170
    PPC_INS_BLTCTRL = 123,
6171
    PPC_INS_BLTL = 124,
6172
    PPC_INS_BLTLA = 125,
6173
    PPC_INS_BLTLR = 126,
6174
    PPC_INS_BLTLRL = 127,
6175
    PPC_INS_BNE = 128,
6176
    PPC_INS_BNEA = 129,
6177
    PPC_INS_BNECTR = 130,
6178
    PPC_INS_BNECTRL = 131,
6179
    PPC_INS_BNEL = 132,
6180
    PPC_INS_BNELA = 133,
6181
    PPC_INS_BNELR = 134,
6182
    PPC_INS_BNELRL = 135,
6183
    PPC_INS_BNG = 136,
6184
    PPC_INS_BNGA = 137,
6185
    PPC_INS_BNGCTR = 138,
6186
    PPC_INS_BNGCTRL = 139,
6187
    PPC_INS_BNGL = 140,
6188
    PPC_INS_BNGLA = 141,
6189
    PPC_INS_BNGLR = 142,
6190
    PPC_INS_BNGLRL = 143,
6191
    PPC_INS_BNL = 144,
6192
    PPC_INS_BNLA = 145,
6193
    PPC_INS_BNLCTR = 146,
6194
    PPC_INS_BNLCTRL = 147,
6195
    PPC_INS_BNLL = 148,
6196
    PPC_INS_BNLLA = 149,
6197
    PPC_INS_BNLLR = 150,
6198
    PPC_INS_BNLLRL = 151,
6199
    PPC_INS_BNS = 152,
6200
    PPC_INS_BNSA = 153,
6201
    PPC_INS_BNSCTR = 154,
6202
    PPC_INS_BNSCTRL = 155,
6203
    PPC_INS_BNSL = 156,
6204
    PPC_INS_BNSLA = 157,
6205
    PPC_INS_BNSLR = 158,
6206
    PPC_INS_BNSLRL = 159,
6207
    PPC_INS_BNU = 160,
6208
    PPC_INS_BNUA = 161,
6209
    PPC_INS_BNUCTR = 162,
6210
    PPC_INS_BNUCTRL = 163,
6211
    PPC_INS_BNUL = 164,
6212
    PPC_INS_BNULA = 165,
6213
    PPC_INS_BNULR = 166,
6214
    PPC_INS_BNULRL = 167,
6215
    PPC_INS_BPERMD = 168,
6216
    PPC_INS_BRINC = 169,
6217
    PPC_INS_BSO = 170,
6218
    PPC_INS_BSOA = 171,
6219
    PPC_INS_BSOCTR = 172,
6220
    PPC_INS_BSOCTRL = 173,
6221
    PPC_INS_BSOL = 174,
6222
    PPC_INS_BSOLA = 175,
6223
    PPC_INS_BSOLR = 176,
6224
    PPC_INS_BSOLRL = 177,
6225
    PPC_INS_BT = 178,
6226
    PPC_INS_BTA = 179,
6227
    PPC_INS_BTCTR = 180,
6228
    PPC_INS_BTCTRL = 181,
6229
    PPC_INS_BTL = 182,
6230
    PPC_INS_BTLA = 183,
6231
    PPC_INS_BTLR = 184,
6232
    PPC_INS_BTLRL = 185,
6233
    PPC_INS_BUN = 186,
6234
    PPC_INS_BUNA = 187,
6235
    PPC_INS_BUNCTR = 188,
6236
    PPC_INS_BUNCTRL = 189,
6237
    PPC_INS_BUNL = 190,
6238
    PPC_INS_BUNLA = 191,
6239
    PPC_INS_BUNLR = 192,
6240
    PPC_INS_BUNLRL = 193,
6241
    PPC_INS_CLRBHRB = 194,
6242
    PPC_INS_CLRLDI = 195,
6243
    PPC_INS_CLRLSLDI = 196,
6244
    PPC_INS_CLRLSLWI = 197,
6245
    PPC_INS_CLRLWI = 198,
6246
    PPC_INS_CLRRDI = 199,
6247
    PPC_INS_CLRRWI = 200,
6248
    PPC_INS_CMP = 201,
6249
    PPC_INS_CMPB = 202,
6250
    PPC_INS_CMPD = 203,
6251
    PPC_INS_CMPDI = 204,
6252
    PPC_INS_CMPEQB = 205,
6253
    PPC_INS_CMPI = 206,
6254
    PPC_INS_CMPL = 207,
6255
    PPC_INS_CMPLD = 208,
6256
    PPC_INS_CMPLDI = 209,
6257
    PPC_INS_CMPLI = 210,
6258
    PPC_INS_CMPLW = 211,
6259
    PPC_INS_CMPLWI = 212,
6260
    PPC_INS_CMPRB = 213,
6261
    PPC_INS_CMPW = 214,
6262
    PPC_INS_CMPWI = 215,
6263
    PPC_INS_CNTLZD = 216,
6264
    PPC_INS_CNTLZW = 217,
6265
    PPC_INS_CNTTZD = 218,
6266
    PPC_INS_CNTTZW = 219,
6267
    PPC_INS_COPY = 220,
6268
    PPC_INS_COPY_FIRST = 221,
6269
    PPC_INS_CP_ABORT = 222,
6270
    PPC_INS_CRAND = 223,
6271
    PPC_INS_CRANDC = 224,
6272
    PPC_INS_CRCLR = 225,
6273
    PPC_INS_CREQV = 226,
6274
    PPC_INS_CRMOVE = 227,
6275
    PPC_INS_CRNAND = 228,
6276
    PPC_INS_CRNOR = 229,
6277
    PPC_INS_CRNOT = 230,
6278
    PPC_INS_CROR = 231,
6279
    PPC_INS_CRORC = 232,
6280
    PPC_INS_CRSET = 233,
6281
    PPC_INS_CRXOR = 234,
6282
    PPC_INS_DARN = 235,
6283
    PPC_INS_DCBA = 236,
6284
    PPC_INS_DCBF = 237,
6285
    PPC_INS_DCBFEP = 238,
6286
    PPC_INS_DCBFL = 239,
6287
    PPC_INS_DCBFLP = 240,
6288
    PPC_INS_DCBI = 241,
6289
    PPC_INS_DCBST = 242,
6290
    PPC_INS_DCBSTEP = 243,
6291
    PPC_INS_DCBT = 244,
6292
    PPC_INS_DCBTCT = 245,
6293
    PPC_INS_DCBTDS = 246,
6294
    PPC_INS_DCBTEP = 247,
6295
    PPC_INS_DCBTST = 248,
6296
    PPC_INS_DCBTSTCT = 249,
6297
    PPC_INS_DCBTSTDS = 250,
6298
    PPC_INS_DCBTSTEP = 251,
6299
    PPC_INS_DCBTSTT = 252,
6300
    PPC_INS_DCBTT = 253,
6301
    PPC_INS_DCBZ = 254,
6302
    PPC_INS_DCBZEP = 255,
6303
    PPC_INS_DCBZL = 256,
6304
    PPC_INS_DCBZLEP = 257,
6305
    PPC_INS_DCCCI = 258,
6306
    PPC_INS_DCI = 259,
6307
    PPC_INS_DIVD = 260,
6308
    PPC_INS_DIVDE = 261,
6309
    PPC_INS_DIVDEU = 262,
6310
    PPC_INS_DIVDU = 263,
6311
    PPC_INS_DIVW = 264,
6312
    PPC_INS_DIVWE = 265,
6313
    PPC_INS_DIVWEU = 266,
6314
    PPC_INS_DIVWU = 267,
6315
    PPC_INS_DSS = 268,
6316
    PPC_INS_DSSALL = 269,
6317
    PPC_INS_DST = 270,
6318
    PPC_INS_DSTST = 271,
6319
    PPC_INS_DSTSTT = 272,
6320
    PPC_INS_DSTT = 273,
6321
    PPC_INS_EFDABS = 274,
6322
    PPC_INS_EFDADD = 275,
6323
    PPC_INS_EFDCFS = 276,
6324
    PPC_INS_EFDCFSF = 277,
6325
    PPC_INS_EFDCFSI = 278,
6326
    PPC_INS_EFDCFSID = 279,
6327
    PPC_INS_EFDCFUF = 280,
6328
    PPC_INS_EFDCFUI = 281,
6329
    PPC_INS_EFDCFUID = 282,
6330
    PPC_INS_EFDCMPEQ = 283,
6331
    PPC_INS_EFDCMPGT = 284,
6332
    PPC_INS_EFDCMPLT = 285,
6333
    PPC_INS_EFDCTSF = 286,
6334
    PPC_INS_EFDCTSI = 287,
6335
    PPC_INS_EFDCTSIDZ = 288,
6336
    PPC_INS_EFDCTSIZ = 289,
6337
    PPC_INS_EFDCTUF = 290,
6338
    PPC_INS_EFDCTUI = 291,
6339
    PPC_INS_EFDCTUIDZ = 292,
6340
    PPC_INS_EFDCTUIZ = 293,
6341
    PPC_INS_EFDDIV = 294,
6342
    PPC_INS_EFDMUL = 295,
6343
    PPC_INS_EFDNABS = 296,
6344
    PPC_INS_EFDNEG = 297,
6345
    PPC_INS_EFDSUB = 298,
6346
    PPC_INS_EFDTSTEQ = 299,
6347
    PPC_INS_EFDTSTGT = 300,
6348
    PPC_INS_EFDTSTLT = 301,
6349
    PPC_INS_EFSABS = 302,
6350
    PPC_INS_EFSADD = 303,
6351
    PPC_INS_EFSCFD = 304,
6352
    PPC_INS_EFSCFSF = 305,
6353
    PPC_INS_EFSCFSI = 306,
6354
    PPC_INS_EFSCFUF = 307,
6355
    PPC_INS_EFSCFUI = 308,
6356
    PPC_INS_EFSCMPEQ = 309,
6357
    PPC_INS_EFSCMPGT = 310,
6358
    PPC_INS_EFSCMPLT = 311,
6359
    PPC_INS_EFSCTSF = 312,
6360
    PPC_INS_EFSCTSI = 313,
6361
    PPC_INS_EFSCTSIZ = 314,
6362
    PPC_INS_EFSCTUF = 315,
6363
    PPC_INS_EFSCTUI = 316,
6364
    PPC_INS_EFSCTUIZ = 317,
6365
    PPC_INS_EFSDIV = 318,
6366
    PPC_INS_EFSMUL = 319,
6367
    PPC_INS_EFSNABS = 320,
6368
    PPC_INS_EFSNEG = 321,
6369
    PPC_INS_EFSSUB = 322,
6370
    PPC_INS_EFSTSTEQ = 323,
6371
    PPC_INS_EFSTSTGT = 324,
6372
    PPC_INS_EFSTSTLT = 325,
6373
    PPC_INS_EIEIO = 326,
6374
    PPC_INS_EQV = 327,
6375
    PPC_INS_EVABS = 328,
6376
    PPC_INS_EVADDIW = 329,
6377
    PPC_INS_EVADDSMIAAW = 330,
6378
    PPC_INS_EVADDSSIAAW = 331,
6379
    PPC_INS_EVADDUMIAAW = 332,
6380
    PPC_INS_EVADDUSIAAW = 333,
6381
    PPC_INS_EVADDW = 334,
6382
    PPC_INS_EVAND = 335,
6383
    PPC_INS_EVANDC = 336,
6384
    PPC_INS_EVCMPEQ = 337,
6385
    PPC_INS_EVCMPGTS = 338,
6386
    PPC_INS_EVCMPGTU = 339,
6387
    PPC_INS_EVCMPLTS = 340,
6388
    PPC_INS_EVCMPLTU = 341,
6389
    PPC_INS_EVCNTLSW = 342,
6390
    PPC_INS_EVCNTLZW = 343,
6391
    PPC_INS_EVDIVWS = 344,
6392
    PPC_INS_EVDIVWU = 345,
6393
    PPC_INS_EVEQV = 346,
6394
    PPC_INS_EVEXTSB = 347,
6395
    PPC_INS_EVEXTSH = 348,
6396
    PPC_INS_EVFSABS = 349,
6397
    PPC_INS_EVFSADD = 350,
6398
    PPC_INS_EVFSCFSF = 351,
6399
    PPC_INS_EVFSCFSI = 352,
6400
    PPC_INS_EVFSCFUF = 353,
6401
    PPC_INS_EVFSCFUI = 354,
6402
    PPC_INS_EVFSCMPEQ = 355,
6403
    PPC_INS_EVFSCMPGT = 356,
6404
    PPC_INS_EVFSCMPLT = 357,
6405
    PPC_INS_EVFSCTSF = 358,
6406
    PPC_INS_EVFSCTSI = 359,
6407
    PPC_INS_EVFSCTSIZ = 360,
6408
    PPC_INS_EVFSCTUI = 361,
6409
    PPC_INS_EVFSDIV = 362,
6410
    PPC_INS_EVFSMUL = 363,
6411
    PPC_INS_EVFSNABS = 364,
6412
    PPC_INS_EVFSNEG = 365,
6413
    PPC_INS_EVFSSUB = 366,
6414
    PPC_INS_EVFSTSTEQ = 367,
6415
    PPC_INS_EVFSTSTGT = 368,
6416
    PPC_INS_EVFSTSTLT = 369,
6417
    PPC_INS_EVLDD = 370,
6418
    PPC_INS_EVLDDX = 371,
6419
    PPC_INS_EVLDH = 372,
6420
    PPC_INS_EVLDHX = 373,
6421
    PPC_INS_EVLDW = 374,
6422
    PPC_INS_EVLDWX = 375,
6423
    PPC_INS_EVLHHESPLAT = 376,
6424
    PPC_INS_EVLHHESPLATX = 377,
6425
    PPC_INS_EVLHHOSSPLAT = 378,
6426
    PPC_INS_EVLHHOSSPLATX = 379,
6427
    PPC_INS_EVLHHOUSPLAT = 380,
6428
    PPC_INS_EVLHHOUSPLATX = 381,
6429
    PPC_INS_EVLWHE = 382,
6430
    PPC_INS_EVLWHEX = 383,
6431
    PPC_INS_EVLWHOS = 384,
6432
    PPC_INS_EVLWHOSX = 385,
6433
    PPC_INS_EVLWHOU = 386,
6434
    PPC_INS_EVLWHOUX = 387,
6435
    PPC_INS_EVLWHSPLAT = 388,
6436
    PPC_INS_EVLWHSPLATX = 389,
6437
    PPC_INS_EVLWWSPLAT = 390,
6438
    PPC_INS_EVLWWSPLATX = 391,
6439
    PPC_INS_EVMERGEHI = 392,
6440
    PPC_INS_EVMERGEHILO = 393,
6441
    PPC_INS_EVMERGELO = 394,
6442
    PPC_INS_EVMERGELOHI = 395,
6443
    PPC_INS_EVMHEGSMFAA = 396,
6444
    PPC_INS_EVMHEGSMFAN = 397,
6445
    PPC_INS_EVMHEGSMIAA = 398,
6446
    PPC_INS_EVMHEGSMIAN = 399,
6447
    PPC_INS_EVMHEGUMIAA = 400,
6448
    PPC_INS_EVMHEGUMIAN = 401,
6449
    PPC_INS_EVMHESMF = 402,
6450
    PPC_INS_EVMHESMFA = 403,
6451
    PPC_INS_EVMHESMFAAW = 404,
6452
    PPC_INS_EVMHESMFANW = 405,
6453
    PPC_INS_EVMHESMI = 406,
6454
    PPC_INS_EVMHESMIA = 407,
6455
    PPC_INS_EVMHESMIAAW = 408,
6456
    PPC_INS_EVMHESMIANW = 409,
6457
    PPC_INS_EVMHESSF = 410,
6458
    PPC_INS_EVMHESSFA = 411,
6459
    PPC_INS_EVMHESSFAAW = 412,
6460
    PPC_INS_EVMHESSFANW = 413,
6461
    PPC_INS_EVMHESSIAAW = 414,
6462
    PPC_INS_EVMHESSIANW = 415,
6463
    PPC_INS_EVMHEUMI = 416,
6464
    PPC_INS_EVMHEUMIA = 417,
6465
    PPC_INS_EVMHEUMIAAW = 418,
6466
    PPC_INS_EVMHEUMIANW = 419,
6467
    PPC_INS_EVMHEUSIAAW = 420,
6468
    PPC_INS_EVMHEUSIANW = 421,
6469
    PPC_INS_EVMHOGSMFAA = 422,
6470
    PPC_INS_EVMHOGSMFAN = 423,
6471
    PPC_INS_EVMHOGSMIAA = 424,
6472
    PPC_INS_EVMHOGSMIAN = 425,
6473
    PPC_INS_EVMHOGUMIAA = 426,
6474
    PPC_INS_EVMHOGUMIAN = 427,
6475
    PPC_INS_EVMHOSMF = 428,
6476
    PPC_INS_EVMHOSMFA = 429,
6477
    PPC_INS_EVMHOSMFAAW = 430,
6478
    PPC_INS_EVMHOSMFANW = 431,
6479
    PPC_INS_EVMHOSMI = 432,
6480
    PPC_INS_EVMHOSMIA = 433,
6481
    PPC_INS_EVMHOSMIAAW = 434,
6482
    PPC_INS_EVMHOSMIANW = 435,
6483
    PPC_INS_EVMHOSSF = 436,
6484
    PPC_INS_EVMHOSSFA = 437,
6485
    PPC_INS_EVMHOSSFAAW = 438,
6486
    PPC_INS_EVMHOSSFANW = 439,
6487
    PPC_INS_EVMHOSSIAAW = 440,
6488
    PPC_INS_EVMHOSSIANW = 441,
6489
    PPC_INS_EVMHOUMI = 442,
6490
    PPC_INS_EVMHOUMIA = 443,
6491
    PPC_INS_EVMHOUMIAAW = 444,
6492
    PPC_INS_EVMHOUMIANW = 445,
6493
    PPC_INS_EVMHOUSIAAW = 446,
6494
    PPC_INS_EVMHOUSIANW = 447,
6495
    PPC_INS_EVMRA = 448,
6496
    PPC_INS_EVMWHSMF = 449,
6497
    PPC_INS_EVMWHSMFA = 450,
6498
    PPC_INS_EVMWHSMI = 451,
6499
    PPC_INS_EVMWHSMIA = 452,
6500
    PPC_INS_EVMWHSSF = 453,
6501
    PPC_INS_EVMWHSSFA = 454,
6502
    PPC_INS_EVMWHUMI = 455,
6503
    PPC_INS_EVMWHUMIA = 456,
6504
    PPC_INS_EVMWLSMIAAW = 457,
6505
    PPC_INS_EVMWLSMIANW = 458,
6506
    PPC_INS_EVMWLSSIAAW = 459,
6507
    PPC_INS_EVMWLSSIANW = 460,
6508
    PPC_INS_EVMWLUMI = 461,
6509
    PPC_INS_EVMWLUMIA = 462,
6510
    PPC_INS_EVMWLUMIAAW = 463,
6511
    PPC_INS_EVMWLUMIANW = 464,
6512
    PPC_INS_EVMWLUSIAAW = 465,
6513
    PPC_INS_EVMWLUSIANW = 466,
6514
    PPC_INS_EVMWSMF = 467,
6515
    PPC_INS_EVMWSMFA = 468,
6516
    PPC_INS_EVMWSMFAA = 469,
6517
    PPC_INS_EVMWSMFAN = 470,
6518
    PPC_INS_EVMWSMI = 471,
6519
    PPC_INS_EVMWSMIA = 472,
6520
    PPC_INS_EVMWSMIAA = 473,
6521
    PPC_INS_EVMWSMIAN = 474,
6522
    PPC_INS_EVMWSSF = 475,
6523
    PPC_INS_EVMWSSFA = 476,
6524
    PPC_INS_EVMWSSFAA = 477,
6525
    PPC_INS_EVMWSSFAN = 478,
6526
    PPC_INS_EVMWUMI = 479,
6527
    PPC_INS_EVMWUMIA = 480,
6528
    PPC_INS_EVMWUMIAA = 481,
6529
    PPC_INS_EVMWUMIAN = 482,
6530
    PPC_INS_EVNAND = 483,
6531
    PPC_INS_EVNEG = 484,
6532
    PPC_INS_EVNOR = 485,
6533
    PPC_INS_EVOR = 486,
6534
    PPC_INS_EVORC = 487,
6535
    PPC_INS_EVRLW = 488,
6536
    PPC_INS_EVRLWI = 489,
6537
    PPC_INS_EVRNDW = 490,
6538
    PPC_INS_EVSEL = 491,
6539
    PPC_INS_EVSLW = 492,
6540
    PPC_INS_EVSLWI = 493,
6541
    PPC_INS_EVSPLATFI = 494,
6542
    PPC_INS_EVSPLATI = 495,
6543
    PPC_INS_EVSRWIS = 496,
6544
    PPC_INS_EVSRWIU = 497,
6545
    PPC_INS_EVSRWS = 498,
6546
    PPC_INS_EVSRWU = 499,
6547
    PPC_INS_EVSTDD = 500,
6548
    PPC_INS_EVSTDDX = 501,
6549
    PPC_INS_EVSTDH = 502,
6550
    PPC_INS_EVSTDHX = 503,
6551
    PPC_INS_EVSTDW = 504,
6552
    PPC_INS_EVSTDWX = 505,
6553
    PPC_INS_EVSTWHE = 506,
6554
    PPC_INS_EVSTWHEX = 507,
6555
    PPC_INS_EVSTWHO = 508,
6556
    PPC_INS_EVSTWHOX = 509,
6557
    PPC_INS_EVSTWWE = 510,
6558
    PPC_INS_EVSTWWEX = 511,
6559
    PPC_INS_EVSTWWO = 512,
6560
    PPC_INS_EVSTWWOX = 513,
6561
    PPC_INS_EVSUBFSMIAAW = 514,
6562
    PPC_INS_EVSUBFSSIAAW = 515,
6563
    PPC_INS_EVSUBFUMIAAW = 516,
6564
    PPC_INS_EVSUBFUSIAAW = 517,
6565
    PPC_INS_EVSUBFW = 518,
6566
    PPC_INS_EVSUBIFW = 519,
6567
    PPC_INS_EVXOR = 520,
6568
    PPC_INS_EXTLDI = 521,
6569
    PPC_INS_EXTLWI = 522,
6570
    PPC_INS_EXTRDI = 523,
6571
    PPC_INS_EXTRWI = 524,
6572
    PPC_INS_EXTSB = 525,
6573
    PPC_INS_EXTSH = 526,
6574
    PPC_INS_EXTSW = 527,
6575
    PPC_INS_EXTSWSLI = 528,
6576
    PPC_INS_FABS = 529,
6577
    PPC_INS_FADD = 530,
6578
    PPC_INS_FADDS = 531,
6579
    PPC_INS_FCFID = 532,
6580
    PPC_INS_FCFIDS = 533,
6581
    PPC_INS_FCFIDU = 534,
6582
    PPC_INS_FCFIDUS = 535,
6583
    PPC_INS_FCMPU = 536,
6584
    PPC_INS_FCPSGN = 537,
6585
    PPC_INS_FCTID = 538,
6586
    PPC_INS_FCTIDU = 539,
6587
    PPC_INS_FCTIDUZ = 540,
6588
    PPC_INS_FCTIDZ = 541,
6589
    PPC_INS_FCTIW = 542,
6590
    PPC_INS_FCTIWU = 543,
6591
    PPC_INS_FCTIWUZ = 544,
6592
    PPC_INS_FCTIWZ = 545,
6593
    PPC_INS_FDIV = 546,
6594
    PPC_INS_FDIVS = 547,
6595
    PPC_INS_FMADD = 548,
6596
    PPC_INS_FMADDS = 549,
6597
    PPC_INS_FMR = 550,
6598
    PPC_INS_FMSUB = 551,
6599
    PPC_INS_FMSUBS = 552,
6600
    PPC_INS_FMUL = 553,
6601
    PPC_INS_FMULS = 554,
6602
    PPC_INS_FNABS = 555,
6603
    PPC_INS_FNEG = 556,
6604
    PPC_INS_FNMADD = 557,
6605
    PPC_INS_FNMADDS = 558,
6606
    PPC_INS_FNMSUB = 559,
6607
    PPC_INS_FNMSUBS = 560,
6608
    PPC_INS_FRE = 561,
6609
    PPC_INS_FRES = 562,
6610
    PPC_INS_FRIM = 563,
6611
    PPC_INS_FRIN = 564,
6612
    PPC_INS_FRIP = 565,
6613
    PPC_INS_FRIZ = 566,
6614
    PPC_INS_FRSP = 567,
6615
    PPC_INS_FRSQRTE = 568,
6616
    PPC_INS_FRSQRTES = 569,
6617
    PPC_INS_FSEL = 570,
6618
    PPC_INS_FSQRT = 571,
6619
    PPC_INS_FSQRTS = 572,
6620
    PPC_INS_FSUB = 573,
6621
    PPC_INS_FSUBS = 574,
6622
    PPC_INS_FTDIV = 575,
6623
    PPC_INS_FTSQRT = 576,
6624
    PPC_INS_HRFID = 577,
6625
    PPC_INS_ICBI = 578,
6626
    PPC_INS_ICBIEP = 579,
6627
    PPC_INS_ICBLC = 580,
6628
    PPC_INS_ICBLQ = 581,
6629
    PPC_INS_ICBT = 582,
6630
    PPC_INS_ICBTLS = 583,
6631
    PPC_INS_ICCCI = 584,
6632
    PPC_INS_ICI = 585,
6633
    PPC_INS_INSLWI = 586,
6634
    PPC_INS_INSRDI = 587,
6635
    PPC_INS_INSRWI = 588,
6636
    PPC_INS_ISEL = 589,
6637
    PPC_INS_ISYNC = 590,
6638
    PPC_INS_LA = 591,
6639
    PPC_INS_LBARX = 592,
6640
    PPC_INS_LBEPX = 593,
6641
    PPC_INS_LBZ = 594,
6642
    PPC_INS_LBZCIX = 595,
6643
    PPC_INS_LBZU = 596,
6644
    PPC_INS_LBZUX = 597,
6645
    PPC_INS_LBZX = 598,
6646
    PPC_INS_LD = 599,
6647
    PPC_INS_LDARX = 600,
6648
    PPC_INS_LDAT = 601,
6649
    PPC_INS_LDBRX = 602,
6650
    PPC_INS_LDCIX = 603,
6651
    PPC_INS_LDMX = 604,
6652
    PPC_INS_LDU = 605,
6653
    PPC_INS_LDUX = 606,
6654
    PPC_INS_LDX = 607,
6655
    PPC_INS_LFD = 608,
6656
    PPC_INS_LFDEPX = 609,
6657
    PPC_INS_LFDU = 610,
6658
    PPC_INS_LFDUX = 611,
6659
    PPC_INS_LFDX = 612,
6660
    PPC_INS_LFIWAX = 613,
6661
    PPC_INS_LFIWZX = 614,
6662
    PPC_INS_LFS = 615,
6663
    PPC_INS_LFSU = 616,
6664
    PPC_INS_LFSUX = 617,
6665
    PPC_INS_LFSX = 618,
6666
    PPC_INS_LHA = 619,
6667
    PPC_INS_LHARX = 620,
6668
    PPC_INS_LHAU = 621,
6669
    PPC_INS_LHAUX = 622,
6670
    PPC_INS_LHAX = 623,
6671
    PPC_INS_LHBRX = 624,
6672
    PPC_INS_LHEPX = 625,
6673
    PPC_INS_LHZ = 626,
6674
    PPC_INS_LHZCIX = 627,
6675
    PPC_INS_LHZU = 628,
6676
    PPC_INS_LHZUX = 629,
6677
    PPC_INS_LHZX = 630,
6678
    PPC_INS_LI = 631,
6679
    PPC_INS_LIS = 632,
6680
    PPC_INS_LMW = 633,
6681
    PPC_INS_LNIA = 634,
6682
    PPC_INS_LSWI = 635,
6683
    PPC_INS_LVEBX = 636,
6684
    PPC_INS_LVEHX = 637,
6685
    PPC_INS_LVEWX = 638,
6686
    PPC_INS_LVSL = 639,
6687
    PPC_INS_LVSR = 640,
6688
    PPC_INS_LVX = 641,
6689
    PPC_INS_LVXL = 642,
6690
    PPC_INS_LWA = 643,
6691
    PPC_INS_LWARX = 644,
6692
    PPC_INS_LWAT = 645,
6693
    PPC_INS_LWAUX = 646,
6694
    PPC_INS_LWAX = 647,
6695
    PPC_INS_LWBRX = 648,
6696
    PPC_INS_LWEPX = 649,
6697
    PPC_INS_LWSYNC = 650,
6698
    PPC_INS_LWZ = 651,
6699
    PPC_INS_LWZCIX = 652,
6700
    PPC_INS_LWZU = 653,
6701
    PPC_INS_LWZUX = 654,
6702
    PPC_INS_LWZX = 655,
6703
    PPC_INS_LXSD = 656,
6704
    PPC_INS_LXSDX = 657,
6705
    PPC_INS_LXSIBZX = 658,
6706
    PPC_INS_LXSIHZX = 659,
6707
    PPC_INS_LXSIWAX = 660,
6708
    PPC_INS_LXSIWZX = 661,
6709
    PPC_INS_LXSSP = 662,
6710
    PPC_INS_LXSSPX = 663,
6711
    PPC_INS_LXV = 664,
6712
    PPC_INS_LXVB16X = 665,
6713
    PPC_INS_LXVD2X = 666,
6714
    PPC_INS_LXVDSX = 667,
6715
    PPC_INS_LXVH8X = 668,
6716
    PPC_INS_LXVL = 669,
6717
    PPC_INS_LXVLL = 670,
6718
    PPC_INS_LXVW4X = 671,
6719
    PPC_INS_LXVWSX = 672,
6720
    PPC_INS_LXVX = 673,
6721
    PPC_INS_MADDHD = 674,
6722
    PPC_INS_MADDHDU = 675,
6723
    PPC_INS_MADDLD = 676,
6724
    PPC_INS_MBAR = 677,
6725
    PPC_INS_MCRF = 678,
6726
    PPC_INS_MCRFS = 679,
6727
    PPC_INS_MCRXRX = 680,
6728
    PPC_INS_MFAMR = 681,
6729
    PPC_INS_MFASR = 682,
6730
    PPC_INS_MFBHRBE = 683,
6731
    PPC_INS_MFBR0 = 684,
6732
    PPC_INS_MFBR1 = 685,
6733
    PPC_INS_MFBR2 = 686,
6734
    PPC_INS_MFBR3 = 687,
6735
    PPC_INS_MFBR4 = 688,
6736
    PPC_INS_MFBR5 = 689,
6737
    PPC_INS_MFBR6 = 690,
6738
    PPC_INS_MFBR7 = 691,
6739
    PPC_INS_MFCFAR = 692,
6740
    PPC_INS_MFCR = 693,
6741
    PPC_INS_MFCTR = 694,
6742
    PPC_INS_MFDAR = 695,
6743
    PPC_INS_MFDBATL = 696,
6744
    PPC_INS_MFDBATU = 697,
6745
    PPC_INS_MFDCCR = 698,
6746
    PPC_INS_MFDCR = 699,
6747
    PPC_INS_MFDEAR = 700,
6748
    PPC_INS_MFDEC = 701,
6749
    PPC_INS_MFDSCR = 702,
6750
    PPC_INS_MFDSISR = 703,
6751
    PPC_INS_MFESR = 704,
6752
    PPC_INS_MFFPRD = 705,
6753
    PPC_INS_MFFS = 706,
6754
    PPC_INS_MFFSCDRN = 707,
6755
    PPC_INS_MFFSCDRNI = 708,
6756
    PPC_INS_MFFSCE = 709,
6757
    PPC_INS_MFFSCRN = 710,
6758
    PPC_INS_MFFSCRNI = 711,
6759
    PPC_INS_MFFSL = 712,
6760
    PPC_INS_MFIBATL = 713,
6761
    PPC_INS_MFIBATU = 714,
6762
    PPC_INS_MFICCR = 715,
6763
    PPC_INS_MFLR = 716,
6764
    PPC_INS_MFMSR = 717,
6765
    PPC_INS_MFOCRF = 718,
6766
    PPC_INS_MFPID = 719,
6767
    PPC_INS_MFPMR = 720,
6768
    PPC_INS_MFPVR = 721,
6769
    PPC_INS_MFRTCL = 722,
6770
    PPC_INS_MFRTCU = 723,
6771
    PPC_INS_MFSDR1 = 724,
6772
    PPC_INS_MFSPEFSCR = 725,
6773
    PPC_INS_MFSPR = 726,
6774
    PPC_INS_MFSPRG = 727,
6775
    PPC_INS_MFSPRG0 = 728,
6776
    PPC_INS_MFSPRG1 = 729,
6777
    PPC_INS_MFSPRG2 = 730,
6778
    PPC_INS_MFSPRG3 = 731,
6779
    PPC_INS_MFSPRG4 = 732,
6780
    PPC_INS_MFSPRG5 = 733,
6781
    PPC_INS_MFSPRG6 = 734,
6782
    PPC_INS_MFSPRG7 = 735,
6783
    PPC_INS_MFSR = 736,
6784
    PPC_INS_MFSRIN = 737,
6785
    PPC_INS_MFSRR0 = 738,
6786
    PPC_INS_MFSRR1 = 739,
6787
    PPC_INS_MFSRR2 = 740,
6788
    PPC_INS_MFSRR3 = 741,
6789
    PPC_INS_MFTB = 742,
6790
    PPC_INS_MFTBHI = 743,
6791
    PPC_INS_MFTBL = 744,
6792
    PPC_INS_MFTBLO = 745,
6793
    PPC_INS_MFTBU = 746,
6794
    PPC_INS_MFTCR = 747,
6795
    PPC_INS_MFVRD = 748,
6796
    PPC_INS_MFVRSAVE = 749,
6797
    PPC_INS_MFVSCR = 750,
6798
    PPC_INS_MFVSRD = 751,
6799
    PPC_INS_MFVSRLD = 752,
6800
    PPC_INS_MFVSRWZ = 753,
6801
    PPC_INS_MFXER = 754,
6802
    PPC_INS_MODSD = 755,
6803
    PPC_INS_MODSW = 756,
6804
    PPC_INS_MODUD = 757,
6805
    PPC_INS_MODUW = 758,
6806
    PPC_INS_MR = 759,
6807
    PPC_INS_MSGSYNC = 760,
6808
    PPC_INS_MSYNC = 761,
6809
    PPC_INS_MTAMR = 762,
6810
    PPC_INS_MTASR = 763,
6811
    PPC_INS_MTBR0 = 764,
6812
    PPC_INS_MTBR1 = 765,
6813
    PPC_INS_MTBR2 = 766,
6814
    PPC_INS_MTBR3 = 767,
6815
    PPC_INS_MTBR4 = 768,
6816
    PPC_INS_MTBR5 = 769,
6817
    PPC_INS_MTBR6 = 770,
6818
    PPC_INS_MTBR7 = 771,
6819
    PPC_INS_MTCFAR = 772,
6820
    PPC_INS_MTCR = 773,
6821
    PPC_INS_MTCRF = 774,
6822
    PPC_INS_MTCTR = 775,
6823
    PPC_INS_MTDAR = 776,
6824
    PPC_INS_MTDBATL = 777,
6825
    PPC_INS_MTDBATU = 778,
6826
    PPC_INS_MTDCCR = 779,
6827
    PPC_INS_MTDCR = 780,
6828
    PPC_INS_MTDEAR = 781,
6829
    PPC_INS_MTDEC = 782,
6830
    PPC_INS_MTDSCR = 783,
6831
    PPC_INS_MTDSISR = 784,
6832
    PPC_INS_MTESR = 785,
6833
    PPC_INS_MTFSB0 = 786,
6834
    PPC_INS_MTFSB1 = 787,
6835
    PPC_INS_MTFSF = 788,
6836
    PPC_INS_MTFSFI = 789,
6837
    PPC_INS_MTIBATL = 790,
6838
    PPC_INS_MTIBATU = 791,
6839
    PPC_INS_MTICCR = 792,
6840
    PPC_INS_MTLR = 793,
6841
    PPC_INS_MTMSR = 794,
6842
    PPC_INS_MTMSRD = 795,
6843
    PPC_INS_MTOCRF = 796,
6844
    PPC_INS_MTPID = 797,
6845
    PPC_INS_MTPMR = 798,
6846
    PPC_INS_MTSDR1 = 799,
6847
    PPC_INS_MTSPEFSCR = 800,
6848
    PPC_INS_MTSPR = 801,
6849
    PPC_INS_MTSPRG = 802,
6850
    PPC_INS_MTSPRG0 = 803,
6851
    PPC_INS_MTSPRG1 = 804,
6852
    PPC_INS_MTSPRG2 = 805,
6853
    PPC_INS_MTSPRG3 = 806,
6854
    PPC_INS_MTSPRG4 = 807,
6855
    PPC_INS_MTSPRG5 = 808,
6856
    PPC_INS_MTSPRG6 = 809,
6857
    PPC_INS_MTSPRG7 = 810,
6858
    PPC_INS_MTSR = 811,
6859
    PPC_INS_MTSRIN = 812,
6860
    PPC_INS_MTSRR0 = 813,
6861
    PPC_INS_MTSRR1 = 814,
6862
    PPC_INS_MTSRR2 = 815,
6863
    PPC_INS_MTSRR3 = 816,
6864
    PPC_INS_MTTBHI = 817,
6865
    PPC_INS_MTTBL = 818,
6866
    PPC_INS_MTTBLO = 819,
6867
    PPC_INS_MTTBU = 820,
6868
    PPC_INS_MTTCR = 821,
6869
    PPC_INS_MTVRSAVE = 822,
6870
    PPC_INS_MTVSCR = 823,
6871
    PPC_INS_MTVSRD = 824,
6872
    PPC_INS_MTVSRDD = 825,
6873
    PPC_INS_MTVSRWA = 826,
6874
    PPC_INS_MTVSRWS = 827,
6875
    PPC_INS_MTVSRWZ = 828,
6876
    PPC_INS_MTXER = 829,
6877
    PPC_INS_MULHD = 830,
6878
    PPC_INS_MULHDU = 831,
6879
    PPC_INS_MULHW = 832,
6880
    PPC_INS_MULHWU = 833,
6881
    PPC_INS_MULLD = 834,
6882
    PPC_INS_MULLI = 835,
6883
    PPC_INS_MULLW = 836,
6884
    PPC_INS_NAND = 837,
6885
    PPC_INS_NAP = 838,
6886
    PPC_INS_NEG = 839,
6887
    PPC_INS_NOP = 840,
6888
    PPC_INS_NOR = 841,
6889
    PPC_INS_NOT = 842,
6890
    PPC_INS_OR = 843,
6891
    PPC_INS_ORC = 844,
6892
    PPC_INS_ORI = 845,
6893
    PPC_INS_ORIS = 846,
6894
    PPC_INS_PASTE = 847,
6895
    PPC_INS_PASTE_LAST = 848,
6896
    PPC_INS_POPCNTB = 849,
6897
    PPC_INS_POPCNTD = 850,
6898
    PPC_INS_POPCNTW = 851,
6899
    PPC_INS_PTESYNC = 852,
6900
    PPC_INS_QVALIGNI = 853,
6901
    PPC_INS_QVESPLATI = 854,
6902
    PPC_INS_QVFABS = 855,
6903
    PPC_INS_QVFADD = 856,
6904
    PPC_INS_QVFADDS = 857,
6905
    PPC_INS_QVFAND = 858,
6906
    PPC_INS_QVFANDC = 859,
6907
    PPC_INS_QVFCFID = 860,
6908
    PPC_INS_QVFCFIDS = 861,
6909
    PPC_INS_QVFCFIDU = 862,
6910
    PPC_INS_QVFCFIDUS = 863,
6911
    PPC_INS_QVFCLR = 864,
6912
    PPC_INS_QVFCMPEQ = 865,
6913
    PPC_INS_QVFCMPGT = 866,
6914
    PPC_INS_QVFCMPLT = 867,
6915
    PPC_INS_QVFCPSGN = 868,
6916
    PPC_INS_QVFCTFB = 869,
6917
    PPC_INS_QVFCTID = 870,
6918
    PPC_INS_QVFCTIDU = 871,
6919
    PPC_INS_QVFCTIDUZ = 872,
6920
    PPC_INS_QVFCTIDZ = 873,
6921
    PPC_INS_QVFCTIW = 874,
6922
    PPC_INS_QVFCTIWU = 875,
6923
    PPC_INS_QVFCTIWUZ = 876,
6924
    PPC_INS_QVFCTIWZ = 877,
6925
    PPC_INS_QVFEQU = 878,
6926
    PPC_INS_QVFLOGICAL = 879,
6927
    PPC_INS_QVFMADD = 880,
6928
    PPC_INS_QVFMADDS = 881,
6929
    PPC_INS_QVFMR = 882,
6930
    PPC_INS_QVFMSUB = 883,
6931
    PPC_INS_QVFMSUBS = 884,
6932
    PPC_INS_QVFMUL = 885,
6933
    PPC_INS_QVFMULS = 886,
6934
    PPC_INS_QVFNABS = 887,
6935
    PPC_INS_QVFNAND = 888,
6936
    PPC_INS_QVFNEG = 889,
6937
    PPC_INS_QVFNMADD = 890,
6938
    PPC_INS_QVFNMADDS = 891,
6939
    PPC_INS_QVFNMSUB = 892,
6940
    PPC_INS_QVFNMSUBS = 893,
6941
    PPC_INS_QVFNOR = 894,
6942
    PPC_INS_QVFNOT = 895,
6943
    PPC_INS_QVFOR = 896,
6944
    PPC_INS_QVFORC = 897,
6945
    PPC_INS_QVFPERM = 898,
6946
    PPC_INS_QVFRE = 899,
6947
    PPC_INS_QVFRES = 900,
6948
    PPC_INS_QVFRIM = 901,
6949
    PPC_INS_QVFRIN = 902,
6950
    PPC_INS_QVFRIP = 903,
6951
    PPC_INS_QVFRIZ = 904,
6952
    PPC_INS_QVFRSP = 905,
6953
    PPC_INS_QVFRSQRTE = 906,
6954
    PPC_INS_QVFRSQRTES = 907,
6955
    PPC_INS_QVFSEL = 908,
6956
    PPC_INS_QVFSET = 909,
6957
    PPC_INS_QVFSUB = 910,
6958
    PPC_INS_QVFSUBS = 911,
6959
    PPC_INS_QVFTSTNAN = 912,
6960
    PPC_INS_QVFXMADD = 913,
6961
    PPC_INS_QVFXMADDS = 914,
6962
    PPC_INS_QVFXMUL = 915,
6963
    PPC_INS_QVFXMULS = 916,
6964
    PPC_INS_QVFXOR = 917,
6965
    PPC_INS_QVFXXCPNMADD = 918,
6966
    PPC_INS_QVFXXCPNMADDS = 919,
6967
    PPC_INS_QVFXXMADD = 920,
6968
    PPC_INS_QVFXXMADDS = 921,
6969
    PPC_INS_QVFXXNPMADD = 922,
6970
    PPC_INS_QVFXXNPMADDS = 923,
6971
    PPC_INS_QVGPCI = 924,
6972
    PPC_INS_QVLFCDUX = 925,
6973
    PPC_INS_QVLFCDUXA = 926,
6974
    PPC_INS_QVLFCDX = 927,
6975
    PPC_INS_QVLFCDXA = 928,
6976
    PPC_INS_QVLFCSUX = 929,
6977
    PPC_INS_QVLFCSUXA = 930,
6978
    PPC_INS_QVLFCSX = 931,
6979
    PPC_INS_QVLFCSXA = 932,
6980
    PPC_INS_QVLFDUX = 933,
6981
    PPC_INS_QVLFDUXA = 934,
6982
    PPC_INS_QVLFDX = 935,
6983
    PPC_INS_QVLFDXA = 936,
6984
    PPC_INS_QVLFIWAX = 937,
6985
    PPC_INS_QVLFIWAXA = 938,
6986
    PPC_INS_QVLFIWZX = 939,
6987
    PPC_INS_QVLFIWZXA = 940,
6988
    PPC_INS_QVLFSUX = 941,
6989
    PPC_INS_QVLFSUXA = 942,
6990
    PPC_INS_QVLFSX = 943,
6991
    PPC_INS_QVLFSXA = 944,
6992
    PPC_INS_QVLPCLDX = 945,
6993
    PPC_INS_QVLPCLSX = 946,
6994
    PPC_INS_QVLPCRDX = 947,
6995
    PPC_INS_QVLPCRSX = 948,
6996
    PPC_INS_QVSTFCDUX = 949,
6997
    PPC_INS_QVSTFCDUXA = 950,
6998
    PPC_INS_QVSTFCDUXI = 951,
6999
    PPC_INS_QVSTFCDUXIA = 952,
7000
    PPC_INS_QVSTFCDX = 953,
7001
    PPC_INS_QVSTFCDXA = 954,
7002
    PPC_INS_QVSTFCDXI = 955,
7003
    PPC_INS_QVSTFCDXIA = 956,
7004
    PPC_INS_QVSTFCSUX = 957,
7005
    PPC_INS_QVSTFCSUXA = 958,
7006
    PPC_INS_QVSTFCSUXI = 959,
7007
    PPC_INS_QVSTFCSUXIA = 960,
7008
    PPC_INS_QVSTFCSX = 961,
7009
    PPC_INS_QVSTFCSXA = 962,
7010
    PPC_INS_QVSTFCSXI = 963,
7011
    PPC_INS_QVSTFCSXIA = 964,
7012
    PPC_INS_QVSTFDUX = 965,
7013
    PPC_INS_QVSTFDUXA = 966,
7014
    PPC_INS_QVSTFDUXI = 967,
7015
    PPC_INS_QVSTFDUXIA = 968,
7016
    PPC_INS_QVSTFDX = 969,
7017
    PPC_INS_QVSTFDXA = 970,
7018
    PPC_INS_QVSTFDXI = 971,
7019
    PPC_INS_QVSTFDXIA = 972,
7020
    PPC_INS_QVSTFIWX = 973,
7021
    PPC_INS_QVSTFIWXA = 974,
7022
    PPC_INS_QVSTFSUX = 975,
7023
    PPC_INS_QVSTFSUXA = 976,
7024
    PPC_INS_QVSTFSUXI = 977,
7025
    PPC_INS_QVSTFSUXIA = 978,
7026
    PPC_INS_QVSTFSX = 979,
7027
    PPC_INS_QVSTFSXA = 980,
7028
    PPC_INS_QVSTFSXI = 981,
7029
    PPC_INS_QVSTFSXIA = 982,
7030
    PPC_INS_RFCI = 983,
7031
    PPC_INS_RFDI = 984,
7032
    PPC_INS_RFEBB = 985,
7033
    PPC_INS_RFI = 986,
7034
    PPC_INS_RFID = 987,
7035
    PPC_INS_RFMCI = 988,
7036
    PPC_INS_RLDCL = 989,
7037
    PPC_INS_RLDCR = 990,
7038
    PPC_INS_RLDIC = 991,
7039
    PPC_INS_RLDICL = 992,
7040
    PPC_INS_RLDICR = 993,
7041
    PPC_INS_RLDIMI = 994,
7042
    PPC_INS_RLWIMI = 995,
7043
    PPC_INS_RLWINM = 996,
7044
    PPC_INS_RLWNM = 997,
7045
    PPC_INS_ROTLD = 998,
7046
    PPC_INS_ROTLDI = 999,
7047
    PPC_INS_ROTLW = 1000,
7048
    PPC_INS_ROTLWI = 1001,
7049
    PPC_INS_ROTRDI = 1002,
7050
    PPC_INS_ROTRWI = 1003,
7051
    PPC_INS_SC = 1004,
7052
    PPC_INS_SETB = 1005,
7053
    PPC_INS_SLBIA = 1006,
7054
    PPC_INS_SLBIE = 1007,
7055
    PPC_INS_SLBIEG = 1008,
7056
    PPC_INS_SLBMFEE = 1009,
7057
    PPC_INS_SLBMFEV = 1010,
7058
    PPC_INS_SLBMTE = 1011,
7059
    PPC_INS_SLBSYNC = 1012,
7060
    PPC_INS_SLD = 1013,
7061
    PPC_INS_SLDI = 1014,
7062
    PPC_INS_SLW = 1015,
7063
    PPC_INS_SLWI = 1016,
7064
    PPC_INS_SRAD = 1017,
7065
    PPC_INS_SRADI = 1018,
7066
    PPC_INS_SRAW = 1019,
7067
    PPC_INS_SRAWI = 1020,
7068
    PPC_INS_SRD = 1021,
7069
    PPC_INS_SRDI = 1022,
7070
    PPC_INS_SRW = 1023,
7071
    PPC_INS_SRWI = 1024,
7072
    PPC_INS_STB = 1025,
7073
    PPC_INS_STBCIX = 1026,
7074
    PPC_INS_STBCX = 1027,
7075
    PPC_INS_STBEPX = 1028,
7076
    PPC_INS_STBU = 1029,
7077
    PPC_INS_STBUX = 1030,
7078
    PPC_INS_STBX = 1031,
7079
    PPC_INS_STD = 1032,
7080
    PPC_INS_STDAT = 1033,
7081
    PPC_INS_STDBRX = 1034,
7082
    PPC_INS_STDCIX = 1035,
7083
    PPC_INS_STDCX = 1036,
7084
    PPC_INS_STDU = 1037,
7085
    PPC_INS_STDUX = 1038,
7086
    PPC_INS_STDX = 1039,
7087
    PPC_INS_STFD = 1040,
7088
    PPC_INS_STFDEPX = 1041,
7089
    PPC_INS_STFDU = 1042,
7090
    PPC_INS_STFDUX = 1043,
7091
    PPC_INS_STFDX = 1044,
7092
    PPC_INS_STFIWX = 1045,
7093
    PPC_INS_STFS = 1046,
7094
    PPC_INS_STFSU = 1047,
7095
    PPC_INS_STFSUX = 1048,
7096
    PPC_INS_STFSX = 1049,
7097
    PPC_INS_STH = 1050,
7098
    PPC_INS_STHBRX = 1051,
7099
    PPC_INS_STHCIX = 1052,
7100
    PPC_INS_STHCX = 1053,
7101
    PPC_INS_STHEPX = 1054,
7102
    PPC_INS_STHU = 1055,
7103
    PPC_INS_STHUX = 1056,
7104
    PPC_INS_STHX = 1057,
7105
    PPC_INS_STMW = 1058,
7106
    PPC_INS_STOP = 1059,
7107
    PPC_INS_STSWI = 1060,
7108
    PPC_INS_STVEBX = 1061,
7109
    PPC_INS_STVEHX = 1062,
7110
    PPC_INS_STVEWX = 1063,
7111
    PPC_INS_STVX = 1064,
7112
    PPC_INS_STVXL = 1065,
7113
    PPC_INS_STW = 1066,
7114
    PPC_INS_STWAT = 1067,
7115
    PPC_INS_STWBRX = 1068,
7116
    PPC_INS_STWCIX = 1069,
7117
    PPC_INS_STWCX = 1070,
7118
    PPC_INS_STWEPX = 1071,
7119
    PPC_INS_STWU = 1072,
7120
    PPC_INS_STWUX = 1073,
7121
    PPC_INS_STWX = 1074,
7122
    PPC_INS_STXSD = 1075,
7123
    PPC_INS_STXSDX = 1076,
7124
    PPC_INS_STXSIBX = 1077,
7125
    PPC_INS_STXSIHX = 1078,
7126
    PPC_INS_STXSIWX = 1079,
7127
    PPC_INS_STXSSP = 1080,
7128
    PPC_INS_STXSSPX = 1081,
7129
    PPC_INS_STXV = 1082,
7130
    PPC_INS_STXVB16X = 1083,
7131
    PPC_INS_STXVD2X = 1084,
7132
    PPC_INS_STXVH8X = 1085,
7133
    PPC_INS_STXVL = 1086,
7134
    PPC_INS_STXVLL = 1087,
7135
    PPC_INS_STXVW4X = 1088,
7136
    PPC_INS_STXVX = 1089,
7137
    PPC_INS_SUB = 1090,
7138
    PPC_INS_SUBC = 1091,
7139
    PPC_INS_SUBF = 1092,
7140
    PPC_INS_SUBFC = 1093,
7141
    PPC_INS_SUBFE = 1094,
7142
    PPC_INS_SUBFIC = 1095,
7143
    PPC_INS_SUBFME = 1096,
7144
    PPC_INS_SUBFZE = 1097,
7145
    PPC_INS_SUBI = 1098,
7146
    PPC_INS_SUBIC = 1099,
7147
    PPC_INS_SUBIS = 1100,
7148
    PPC_INS_SUBPCIS = 1101,
7149
    PPC_INS_SYNC = 1102,
7150
    PPC_INS_TABORT = 1103,
7151
    PPC_INS_TABORTDC = 1104,
7152
    PPC_INS_TABORTDCI = 1105,
7153
    PPC_INS_TABORTWC = 1106,
7154
    PPC_INS_TABORTWCI = 1107,
7155
    PPC_INS_TBEGIN = 1108,
7156
    PPC_INS_TCHECK = 1109,
7157
    PPC_INS_TD = 1110,
7158
    PPC_INS_TDEQ = 1111,
7159
    PPC_INS_TDEQI = 1112,
7160
    PPC_INS_TDGE = 1113,
7161
    PPC_INS_TDGEI = 1114,
7162
    PPC_INS_TDGT = 1115,
7163
    PPC_INS_TDGTI = 1116,
7164
    PPC_INS_TDI = 1117,
7165
    PPC_INS_TDLE = 1118,
7166
    PPC_INS_TDLEI = 1119,
7167
    PPC_INS_TDLGE = 1120,
7168
    PPC_INS_TDLGEI = 1121,
7169
    PPC_INS_TDLGT = 1122,
7170
    PPC_INS_TDLGTI = 1123,
7171
    PPC_INS_TDLLE = 1124,
7172
    PPC_INS_TDLLEI = 1125,
7173
    PPC_INS_TDLLT = 1126,
7174
    PPC_INS_TDLLTI = 1127,
7175
    PPC_INS_TDLNG = 1128,
7176
    PPC_INS_TDLNGI = 1129,
7177
    PPC_INS_TDLNL = 1130,
7178
    PPC_INS_TDLNLI = 1131,
7179
    PPC_INS_TDLT = 1132,
7180
    PPC_INS_TDLTI = 1133,
7181
    PPC_INS_TDNE = 1134,
7182
    PPC_INS_TDNEI = 1135,
7183
    PPC_INS_TDNG = 1136,
7184
    PPC_INS_TDNGI = 1137,
7185
    PPC_INS_TDNL = 1138,
7186
    PPC_INS_TDNLI = 1139,
7187
    PPC_INS_TDU = 1140,
7188
    PPC_INS_TDUI = 1141,
7189
    PPC_INS_TEND = 1142,
7190
    PPC_INS_TLBIA = 1143,
7191
    PPC_INS_TLBIE = 1144,
7192
    PPC_INS_TLBIEL = 1145,
7193
    PPC_INS_TLBIVAX = 1146,
7194
    PPC_INS_TLBLD = 1147,
7195
    PPC_INS_TLBLI = 1148,
7196
    PPC_INS_TLBRE = 1149,
7197
    PPC_INS_TLBREHI = 1150,
7198
    PPC_INS_TLBRELO = 1151,
7199
    PPC_INS_TLBSX = 1152,
7200
    PPC_INS_TLBSYNC = 1153,
7201
    PPC_INS_TLBWE = 1154,
7202
    PPC_INS_TLBWEHI = 1155,
7203
    PPC_INS_TLBWELO = 1156,
7204
    PPC_INS_TRAP = 1157,
7205
    PPC_INS_TRECHKPT = 1158,
7206
    PPC_INS_TRECLAIM = 1159,
7207
    PPC_INS_TSR = 1160,
7208
    PPC_INS_TW = 1161,
7209
    PPC_INS_TWEQ = 1162,
7210
    PPC_INS_TWEQI = 1163,
7211
    PPC_INS_TWGE = 1164,
7212
    PPC_INS_TWGEI = 1165,
7213
    PPC_INS_TWGT = 1166,
7214
    PPC_INS_TWGTI = 1167,
7215
    PPC_INS_TWI = 1168,
7216
    PPC_INS_TWLE = 1169,
7217
    PPC_INS_TWLEI = 1170,
7218
    PPC_INS_TWLGE = 1171,
7219
    PPC_INS_TWLGEI = 1172,
7220
    PPC_INS_TWLGT = 1173,
7221
    PPC_INS_TWLGTI = 1174,
7222
    PPC_INS_TWLLE = 1175,
7223
    PPC_INS_TWLLEI = 1176,
7224
    PPC_INS_TWLLT = 1177,
7225
    PPC_INS_TWLLTI = 1178,
7226
    PPC_INS_TWLNG = 1179,
7227
    PPC_INS_TWLNGI = 1180,
7228
    PPC_INS_TWLNL = 1181,
7229
    PPC_INS_TWLNLI = 1182,
7230
    PPC_INS_TWLT = 1183,
7231
    PPC_INS_TWLTI = 1184,
7232
    PPC_INS_TWNE = 1185,
7233
    PPC_INS_TWNEI = 1186,
7234
    PPC_INS_TWNG = 1187,
7235
    PPC_INS_TWNGI = 1188,
7236
    PPC_INS_TWNL = 1189,
7237
    PPC_INS_TWNLI = 1190,
7238
    PPC_INS_TWU = 1191,
7239
    PPC_INS_TWUI = 1192,
7240
    PPC_INS_VABSDUB = 1193,
7241
    PPC_INS_VABSDUH = 1194,
7242
    PPC_INS_VABSDUW = 1195,
7243
    PPC_INS_VADDCUQ = 1196,
7244
    PPC_INS_VADDCUW = 1197,
7245
    PPC_INS_VADDECUQ = 1198,
7246
    PPC_INS_VADDEUQM = 1199,
7247
    PPC_INS_VADDFP = 1200,
7248
    PPC_INS_VADDSBS = 1201,
7249
    PPC_INS_VADDSHS = 1202,
7250
    PPC_INS_VADDSWS = 1203,
7251
    PPC_INS_VADDUBM = 1204,
7252
    PPC_INS_VADDUBS = 1205,
7253
    PPC_INS_VADDUDM = 1206,
7254
    PPC_INS_VADDUHM = 1207,
7255
    PPC_INS_VADDUHS = 1208,
7256
    PPC_INS_VADDUQM = 1209,
7257
    PPC_INS_VADDUWM = 1210,
7258
    PPC_INS_VADDUWS = 1211,
7259
    PPC_INS_VAND = 1212,
7260
    PPC_INS_VANDC = 1213,
7261
    PPC_INS_VAVGSB = 1214,
7262
    PPC_INS_VAVGSH = 1215,
7263
    PPC_INS_VAVGSW = 1216,
7264
    PPC_INS_VAVGUB = 1217,
7265
    PPC_INS_VAVGUH = 1218,
7266
    PPC_INS_VAVGUW = 1219,
7267
    PPC_INS_VBPERMD = 1220,
7268
    PPC_INS_VBPERMQ = 1221,
7269
    PPC_INS_VCFSX = 1222,
7270
    PPC_INS_VCFUX = 1223,
7271
    PPC_INS_VCIPHER = 1224,
7272
    PPC_INS_VCIPHERLAST = 1225,
7273
    PPC_INS_VCLZB = 1226,
7274
    PPC_INS_VCLZD = 1227,
7275
    PPC_INS_VCLZH = 1228,
7276
    PPC_INS_VCLZLSBB = 1229,
7277
    PPC_INS_VCLZW = 1230,
7278
    PPC_INS_VCMPBFP = 1231,
7279
    PPC_INS_VCMPEQFP = 1232,
7280
    PPC_INS_VCMPEQUB = 1233,
7281
    PPC_INS_VCMPEQUD = 1234,
7282
    PPC_INS_VCMPEQUH = 1235,
7283
    PPC_INS_VCMPEQUW = 1236,
7284
    PPC_INS_VCMPGEFP = 1237,
7285
    PPC_INS_VCMPGTFP = 1238,
7286
    PPC_INS_VCMPGTSB = 1239,
7287
    PPC_INS_VCMPGTSD = 1240,
7288
    PPC_INS_VCMPGTSH = 1241,
7289
    PPC_INS_VCMPGTSW = 1242,
7290
    PPC_INS_VCMPGTUB = 1243,
7291
    PPC_INS_VCMPGTUD = 1244,
7292
    PPC_INS_VCMPGTUH = 1245,
7293
    PPC_INS_VCMPGTUW = 1246,
7294
    PPC_INS_VCMPNEB = 1247,
7295
    PPC_INS_VCMPNEH = 1248,
7296
    PPC_INS_VCMPNEW = 1249,
7297
    PPC_INS_VCMPNEZB = 1250,
7298
    PPC_INS_VCMPNEZH = 1251,
7299
    PPC_INS_VCMPNEZW = 1252,
7300
    PPC_INS_VCTSXS = 1253,
7301
    PPC_INS_VCTUXS = 1254,
7302
    PPC_INS_VCTZB = 1255,
7303
    PPC_INS_VCTZD = 1256,
7304
    PPC_INS_VCTZH = 1257,
7305
    PPC_INS_VCTZLSBB = 1258,
7306
    PPC_INS_VCTZW = 1259,
7307
    PPC_INS_VEQV = 1260,
7308
    PPC_INS_VEXPTEFP = 1261,
7309
    PPC_INS_VEXTRACTD = 1262,
7310
    PPC_INS_VEXTRACTUB = 1263,
7311
    PPC_INS_VEXTRACTUH = 1264,
7312
    PPC_INS_VEXTRACTUW = 1265,
7313
    PPC_INS_VEXTSB2D = 1266,
7314
    PPC_INS_VEXTSB2W = 1267,
7315
    PPC_INS_VEXTSH2D = 1268,
7316
    PPC_INS_VEXTSH2W = 1269,
7317
    PPC_INS_VEXTSW2D = 1270,
7318
    PPC_INS_VEXTUBLX = 1271,
7319
    PPC_INS_VEXTUBRX = 1272,
7320
    PPC_INS_VEXTUHLX = 1273,
7321
    PPC_INS_VEXTUHRX = 1274,
7322
    PPC_INS_VEXTUWLX = 1275,
7323
    PPC_INS_VEXTUWRX = 1276,
7324
    PPC_INS_VGBBD = 1277,
7325
    PPC_INS_VINSERTB = 1278,
7326
    PPC_INS_VINSERTD = 1279,
7327
    PPC_INS_VINSERTH = 1280,
7328
    PPC_INS_VINSERTW = 1281,
7329
    PPC_INS_VLOGEFP = 1282,
7330
    PPC_INS_VMADDFP = 1283,
7331
    PPC_INS_VMAXFP = 1284,
7332
    PPC_INS_VMAXSB = 1285,
7333
    PPC_INS_VMAXSD = 1286,
7334
    PPC_INS_VMAXSH = 1287,
7335
    PPC_INS_VMAXSW = 1288,
7336
    PPC_INS_VMAXUB = 1289,
7337
    PPC_INS_VMAXUD = 1290,
7338
    PPC_INS_VMAXUH = 1291,
7339
    PPC_INS_VMAXUW = 1292,
7340
    PPC_INS_VMHADDSHS = 1293,
7341
    PPC_INS_VMHRADDSHS = 1294,
7342
    PPC_INS_VMINFP = 1295,
7343
    PPC_INS_VMINSB = 1296,
7344
    PPC_INS_VMINSD = 1297,
7345
    PPC_INS_VMINSH = 1298,
7346
    PPC_INS_VMINSW = 1299,
7347
    PPC_INS_VMINUB = 1300,
7348
    PPC_INS_VMINUD = 1301,
7349
    PPC_INS_VMINUH = 1302,
7350
    PPC_INS_VMINUW = 1303,
7351
    PPC_INS_VMLADDUHM = 1304,
7352
    PPC_INS_VMR = 1305,
7353
    PPC_INS_VMRGEW = 1306,
7354
    PPC_INS_VMRGHB = 1307,
7355
    PPC_INS_VMRGHH = 1308,
7356
    PPC_INS_VMRGHW = 1309,
7357
    PPC_INS_VMRGLB = 1310,
7358
    PPC_INS_VMRGLH = 1311,
7359
    PPC_INS_VMRGLW = 1312,
7360
    PPC_INS_VMRGOW = 1313,
7361
    PPC_INS_VMSUMMBM = 1314,
7362
    PPC_INS_VMSUMSHM = 1315,
7363
    PPC_INS_VMSUMSHS = 1316,
7364
    PPC_INS_VMSUMUBM = 1317,
7365
    PPC_INS_VMSUMUHM = 1318,
7366
    PPC_INS_VMSUMUHS = 1319,
7367
    PPC_INS_VMUL10CUQ = 1320,
7368
    PPC_INS_VMUL10ECUQ = 1321,
7369
    PPC_INS_VMUL10EUQ = 1322,
7370
    PPC_INS_VMUL10UQ = 1323,
7371
    PPC_INS_VMULESB = 1324,
7372
    PPC_INS_VMULESH = 1325,
7373
    PPC_INS_VMULESW = 1326,
7374
    PPC_INS_VMULEUB = 1327,
7375
    PPC_INS_VMULEUH = 1328,
7376
    PPC_INS_VMULEUW = 1329,
7377
    PPC_INS_VMULOSB = 1330,
7378
    PPC_INS_VMULOSH = 1331,
7379
    PPC_INS_VMULOSW = 1332,
7380
    PPC_INS_VMULOUB = 1333,
7381
    PPC_INS_VMULOUH = 1334,
7382
    PPC_INS_VMULOUW = 1335,
7383
    PPC_INS_VMULUWM = 1336,
7384
    PPC_INS_VNAND = 1337,
7385
    PPC_INS_VNCIPHER = 1338,
7386
    PPC_INS_VNCIPHERLAST = 1339,
7387
    PPC_INS_VNEGD = 1340,
7388
    PPC_INS_VNEGW = 1341,
7389
    PPC_INS_VNMSUBFP = 1342,
7390
    PPC_INS_VNOR = 1343,
7391
    PPC_INS_VNOT = 1344,
7392
    PPC_INS_VOR = 1345,
7393
    PPC_INS_VORC = 1346,
7394
    PPC_INS_VPERM = 1347,
7395
    PPC_INS_VPERMR = 1348,
7396
    PPC_INS_VPERMXOR = 1349,
7397
    PPC_INS_VPKPX = 1350,
7398
    PPC_INS_VPKSDSS = 1351,
7399
    PPC_INS_VPKSDUS = 1352,
7400
    PPC_INS_VPKSHSS = 1353,
7401
    PPC_INS_VPKSHUS = 1354,
7402
    PPC_INS_VPKSWSS = 1355,
7403
    PPC_INS_VPKSWUS = 1356,
7404
    PPC_INS_VPKUDUM = 1357,
7405
    PPC_INS_VPKUDUS = 1358,
7406
    PPC_INS_VPKUHUM = 1359,
7407
    PPC_INS_VPKUHUS = 1360,
7408
    PPC_INS_VPKUWUM = 1361,
7409
    PPC_INS_VPKUWUS = 1362,
7410
    PPC_INS_VPMSUMB = 1363,
7411
    PPC_INS_VPMSUMD = 1364,
7412
    PPC_INS_VPMSUMH = 1365,
7413
    PPC_INS_VPMSUMW = 1366,
7414
    PPC_INS_VPOPCNTB = 1367,
7415
    PPC_INS_VPOPCNTD = 1368,
7416
    PPC_INS_VPOPCNTH = 1369,
7417
    PPC_INS_VPOPCNTW = 1370,
7418
    PPC_INS_VPRTYBD = 1371,
7419
    PPC_INS_VPRTYBQ = 1372,
7420
    PPC_INS_VPRTYBW = 1373,
7421
    PPC_INS_VREFP = 1374,
7422
    PPC_INS_VRFIM = 1375,
7423
    PPC_INS_VRFIN = 1376,
7424
    PPC_INS_VRFIP = 1377,
7425
    PPC_INS_VRFIZ = 1378,
7426
    PPC_INS_VRLB = 1379,
7427
    PPC_INS_VRLD = 1380,
7428
    PPC_INS_VRLDMI = 1381,
7429
    PPC_INS_VRLDNM = 1382,
7430
    PPC_INS_VRLH = 1383,
7431
    PPC_INS_VRLW = 1384,
7432
    PPC_INS_VRLWMI = 1385,
7433
    PPC_INS_VRLWNM = 1386,
7434
    PPC_INS_VRSQRTEFP = 1387,
7435
    PPC_INS_VSBOX = 1388,
7436
    PPC_INS_VSEL = 1389,
7437
    PPC_INS_VSHASIGMAD = 1390,
7438
    PPC_INS_VSHASIGMAW = 1391,
7439
    PPC_INS_VSL = 1392,
7440
    PPC_INS_VSLB = 1393,
7441
    PPC_INS_VSLD = 1394,
7442
    PPC_INS_VSLDOI = 1395,
7443
    PPC_INS_VSLH = 1396,
7444
    PPC_INS_VSLO = 1397,
7445
    PPC_INS_VSLV = 1398,
7446
    PPC_INS_VSLW = 1399,
7447
    PPC_INS_VSPLTB = 1400,
7448
    PPC_INS_VSPLTH = 1401,
7449
    PPC_INS_VSPLTISB = 1402,
7450
    PPC_INS_VSPLTISH = 1403,
7451
    PPC_INS_VSPLTISW = 1404,
7452
    PPC_INS_VSPLTW = 1405,
7453
    PPC_INS_VSR = 1406,
7454
    PPC_INS_VSRAB = 1407,
7455
    PPC_INS_VSRAD = 1408,
7456
    PPC_INS_VSRAH = 1409,
7457
    PPC_INS_VSRAW = 1410,
7458
    PPC_INS_VSRB = 1411,
7459
    PPC_INS_VSRD = 1412,
7460
    PPC_INS_VSRH = 1413,
7461
    PPC_INS_VSRO = 1414,
7462
    PPC_INS_VSRV = 1415,
7463
    PPC_INS_VSRW = 1416,
7464
    PPC_INS_VSUBCUQ = 1417,
7465
    PPC_INS_VSUBCUW = 1418,
7466
    PPC_INS_VSUBECUQ = 1419,
7467
    PPC_INS_VSUBEUQM = 1420,
7468
    PPC_INS_VSUBFP = 1421,
7469
    PPC_INS_VSUBSBS = 1422,
7470
    PPC_INS_VSUBSHS = 1423,
7471
    PPC_INS_VSUBSWS = 1424,
7472
    PPC_INS_VSUBUBM = 1425,
7473
    PPC_INS_VSUBUBS = 1426,
7474
    PPC_INS_VSUBUDM = 1427,
7475
    PPC_INS_VSUBUHM = 1428,
7476
    PPC_INS_VSUBUHS = 1429,
7477
    PPC_INS_VSUBUQM = 1430,
7478
    PPC_INS_VSUBUWM = 1431,
7479
    PPC_INS_VSUBUWS = 1432,
7480
    PPC_INS_VSUM2SWS = 1433,
7481
    PPC_INS_VSUM4SBS = 1434,
7482
    PPC_INS_VSUM4SHS = 1435,
7483
    PPC_INS_VSUM4UBS = 1436,
7484
    PPC_INS_VSUMSWS = 1437,
7485
    PPC_INS_VUPKHPX = 1438,
7486
    PPC_INS_VUPKHSB = 1439,
7487
    PPC_INS_VUPKHSH = 1440,
7488
    PPC_INS_VUPKHSW = 1441,
7489
    PPC_INS_VUPKLPX = 1442,
7490
    PPC_INS_VUPKLSB = 1443,
7491
    PPC_INS_VUPKLSH = 1444,
7492
    PPC_INS_VUPKLSW = 1445,
7493
    PPC_INS_VXOR = 1446,
7494
    PPC_INS_WAIT = 1447,
7495
    PPC_INS_WAITIMPL = 1448,
7496
    PPC_INS_WAITRSV = 1449,
7497
    PPC_INS_WRTEE = 1450,
7498
    PPC_INS_WRTEEI = 1451,
7499
    PPC_INS_XNOP = 1452,
7500
    PPC_INS_XOR = 1453,
7501
    PPC_INS_XORI = 1454,
7502
    PPC_INS_XORIS = 1455,
7503
    PPC_INS_XSABSDP = 1456,
7504
    PPC_INS_XSABSQP = 1457,
7505
    PPC_INS_XSADDDP = 1458,
7506
    PPC_INS_XSADDQP = 1459,
7507
    PPC_INS_XSADDQPO = 1460,
7508
    PPC_INS_XSADDSP = 1461,
7509
    PPC_INS_XSCMPEQDP = 1462,
7510
    PPC_INS_XSCMPEXPDP = 1463,
7511
    PPC_INS_XSCMPEXPQP = 1464,
7512
    PPC_INS_XSCMPGEDP = 1465,
7513
    PPC_INS_XSCMPGTDP = 1466,
7514
    PPC_INS_XSCMPODP = 1467,
7515
    PPC_INS_XSCMPOQP = 1468,
7516
    PPC_INS_XSCMPUDP = 1469,
7517
    PPC_INS_XSCMPUQP = 1470,
7518
    PPC_INS_XSCPSGNDP = 1471,
7519
    PPC_INS_XSCPSGNQP = 1472,
7520
    PPC_INS_XSCVDPHP = 1473,
7521
    PPC_INS_XSCVDPQP = 1474,
7522
    PPC_INS_XSCVDPSP = 1475,
7523
    PPC_INS_XSCVDPSPN = 1476,
7524
    PPC_INS_XSCVDPSXDS = 1477,
7525
    PPC_INS_XSCVDPSXWS = 1478,
7526
    PPC_INS_XSCVDPUXDS = 1479,
7527
    PPC_INS_XSCVDPUXWS = 1480,
7528
    PPC_INS_XSCVHPDP = 1481,
7529
    PPC_INS_XSCVQPDP = 1482,
7530
    PPC_INS_XSCVQPDPO = 1483,
7531
    PPC_INS_XSCVQPSDZ = 1484,
7532
    PPC_INS_XSCVQPSWZ = 1485,
7533
    PPC_INS_XSCVQPUDZ = 1486,
7534
    PPC_INS_XSCVQPUWZ = 1487,
7535
    PPC_INS_XSCVSDQP = 1488,
7536
    PPC_INS_XSCVSPDP = 1489,
7537
    PPC_INS_XSCVSPDPN = 1490,
7538
    PPC_INS_XSCVSXDDP = 1491,
7539
    PPC_INS_XSCVSXDSP = 1492,
7540
    PPC_INS_XSCVUDQP = 1493,
7541
    PPC_INS_XSCVUXDDP = 1494,
7542
    PPC_INS_XSCVUXDSP = 1495,
7543
    PPC_INS_XSDIVDP = 1496,
7544
    PPC_INS_XSDIVQP = 1497,
7545
    PPC_INS_XSDIVQPO = 1498,
7546
    PPC_INS_XSDIVSP = 1499,
7547
    PPC_INS_XSIEXPDP = 1500,
7548
    PPC_INS_XSIEXPQP = 1501,
7549
    PPC_INS_XSMADDADP = 1502,
7550
    PPC_INS_XSMADDASP = 1503,
7551
    PPC_INS_XSMADDMDP = 1504,
7552
    PPC_INS_XSMADDMSP = 1505,
7553
    PPC_INS_XSMADDQP = 1506,
7554
    PPC_INS_XSMADDQPO = 1507,
7555
    PPC_INS_XSMAXCDP = 1508,
7556
    PPC_INS_XSMAXDP = 1509,
7557
    PPC_INS_XSMAXJDP = 1510,
7558
    PPC_INS_XSMINCDP = 1511,
7559
    PPC_INS_XSMINDP = 1512,
7560
    PPC_INS_XSMINJDP = 1513,
7561
    PPC_INS_XSMSUBADP = 1514,
7562
    PPC_INS_XSMSUBASP = 1515,
7563
    PPC_INS_XSMSUBMDP = 1516,
7564
    PPC_INS_XSMSUBMSP = 1517,
7565
    PPC_INS_XSMSUBQP = 1518,
7566
    PPC_INS_XSMSUBQPO = 1519,
7567
    PPC_INS_XSMULDP = 1520,
7568
    PPC_INS_XSMULQP = 1521,
7569
    PPC_INS_XSMULQPO = 1522,
7570
    PPC_INS_XSMULSP = 1523,
7571
    PPC_INS_XSNABSDP = 1524,
7572
    PPC_INS_XSNABSQP = 1525,
7573
    PPC_INS_XSNEGDP = 1526,
7574
    PPC_INS_XSNEGQP = 1527,
7575
    PPC_INS_XSNMADDADP = 1528,
7576
    PPC_INS_XSNMADDASP = 1529,
7577
    PPC_INS_XSNMADDMDP = 1530,
7578
    PPC_INS_XSNMADDMSP = 1531,
7579
    PPC_INS_XSNMADDQP = 1532,
7580
    PPC_INS_XSNMADDQPO = 1533,
7581
    PPC_INS_XSNMSUBADP = 1534,
7582
    PPC_INS_XSNMSUBASP = 1535,
7583
    PPC_INS_XSNMSUBMDP = 1536,
7584
    PPC_INS_XSNMSUBMSP = 1537,
7585
    PPC_INS_XSNMSUBQP = 1538,
7586
    PPC_INS_XSNMSUBQPO = 1539,
7587
    PPC_INS_XSRDPI = 1540,
7588
    PPC_INS_XSRDPIC = 1541,
7589
    PPC_INS_XSRDPIM = 1542,
7590
    PPC_INS_XSRDPIP = 1543,
7591
    PPC_INS_XSRDPIZ = 1544,
7592
    PPC_INS_XSREDP = 1545,
7593
    PPC_INS_XSRESP = 1546,
7594
    PPC_INS_XSRQPI = 1547,
7595
    PPC_INS_XSRQPIX = 1548,
7596
    PPC_INS_XSRQPXP = 1549,
7597
    PPC_INS_XSRSP = 1550,
7598
    PPC_INS_XSRSQRTEDP = 1551,
7599
    PPC_INS_XSRSQRTESP = 1552,
7600
    PPC_INS_XSSQRTDP = 1553,
7601
    PPC_INS_XSSQRTQP = 1554,
7602
    PPC_INS_XSSQRTQPO = 1555,
7603
    PPC_INS_XSSQRTSP = 1556,
7604
    PPC_INS_XSSUBDP = 1557,
7605
    PPC_INS_XSSUBQP = 1558,
7606
    PPC_INS_XSSUBQPO = 1559,
7607
    PPC_INS_XSSUBSP = 1560,
7608
    PPC_INS_XSTDIVDP = 1561,
7609
    PPC_INS_XSTSQRTDP = 1562,
7610
    PPC_INS_XSTSTDCDP = 1563,
7611
    PPC_INS_XSTSTDCQP = 1564,
7612
    PPC_INS_XSTSTDCSP = 1565,
7613
    PPC_INS_XSXEXPDP = 1566,
7614
    PPC_INS_XSXEXPQP = 1567,
7615
    PPC_INS_XSXSIGDP = 1568,
7616
    PPC_INS_XSXSIGQP = 1569,
7617
    PPC_INS_XVABSDP = 1570,
7618
    PPC_INS_XVABSSP = 1571,
7619
    PPC_INS_XVADDDP = 1572,
7620
    PPC_INS_XVADDSP = 1573,
7621
    PPC_INS_XVCMPEQDP = 1574,
7622
    PPC_INS_XVCMPEQSP = 1575,
7623
    PPC_INS_XVCMPGEDP = 1576,
7624
    PPC_INS_XVCMPGESP = 1577,
7625
    PPC_INS_XVCMPGTDP = 1578,
7626
    PPC_INS_XVCMPGTSP = 1579,
7627
    PPC_INS_XVCPSGNDP = 1580,
7628
    PPC_INS_XVCPSGNSP = 1581,
7629
    PPC_INS_XVCVDPSP = 1582,
7630
    PPC_INS_XVCVDPSXDS = 1583,
7631
    PPC_INS_XVCVDPSXWS = 1584,
7632
    PPC_INS_XVCVDPUXDS = 1585,
7633
    PPC_INS_XVCVDPUXWS = 1586,
7634
    PPC_INS_XVCVHPSP = 1587,
7635
    PPC_INS_XVCVSPDP = 1588,
7636
    PPC_INS_XVCVSPHP = 1589,
7637
    PPC_INS_XVCVSPSXDS = 1590,
7638
    PPC_INS_XVCVSPSXWS = 1591,
7639
    PPC_INS_XVCVSPUXDS = 1592,
7640
    PPC_INS_XVCVSPUXWS = 1593,
7641
    PPC_INS_XVCVSXDDP = 1594,
7642
    PPC_INS_XVCVSXDSP = 1595,
7643
    PPC_INS_XVCVSXWDP = 1596,
7644
    PPC_INS_XVCVSXWSP = 1597,
7645
    PPC_INS_XVCVUXDDP = 1598,
7646
    PPC_INS_XVCVUXDSP = 1599,
7647
    PPC_INS_XVCVUXWDP = 1600,
7648
    PPC_INS_XVCVUXWSP = 1601,
7649
    PPC_INS_XVDIVDP = 1602,
7650
    PPC_INS_XVDIVSP = 1603,
7651
    PPC_INS_XVIEXPDP = 1604,
7652
    PPC_INS_XVIEXPSP = 1605,
7653
    PPC_INS_XVMADDADP = 1606,
7654
    PPC_INS_XVMADDASP = 1607,
7655
    PPC_INS_XVMADDMDP = 1608,
7656
    PPC_INS_XVMADDMSP = 1609,
7657
    PPC_INS_XVMAXDP = 1610,
7658
    PPC_INS_XVMAXSP = 1611,
7659
    PPC_INS_XVMINDP = 1612,
7660
    PPC_INS_XVMINSP = 1613,
7661
    PPC_INS_XVMOVDP = 1614,
7662
    PPC_INS_XVMOVSP = 1615,
7663
    PPC_INS_XVMSUBADP = 1616,
7664
    PPC_INS_XVMSUBASP = 1617,
7665
    PPC_INS_XVMSUBMDP = 1618,
7666
    PPC_INS_XVMSUBMSP = 1619,
7667
    PPC_INS_XVMULDP = 1620,
7668
    PPC_INS_XVMULSP = 1621,
7669
    PPC_INS_XVNABSDP = 1622,
7670
    PPC_INS_XVNABSSP = 1623,
7671
    PPC_INS_XVNEGDP = 1624,
7672
    PPC_INS_XVNEGSP = 1625,
7673
    PPC_INS_XVNMADDADP = 1626,
7674
    PPC_INS_XVNMADDASP = 1627,
7675
    PPC_INS_XVNMADDMDP = 1628,
7676
    PPC_INS_XVNMADDMSP = 1629,
7677
    PPC_INS_XVNMSUBADP = 1630,
7678
    PPC_INS_XVNMSUBASP = 1631,
7679
    PPC_INS_XVNMSUBMDP = 1632,
7680
    PPC_INS_XVNMSUBMSP = 1633,
7681
    PPC_INS_XVRDPI = 1634,
7682
    PPC_INS_XVRDPIC = 1635,
7683
    PPC_INS_XVRDPIM = 1636,
7684
    PPC_INS_XVRDPIP = 1637,
7685
    PPC_INS_XVRDPIZ = 1638,
7686
    PPC_INS_XVREDP = 1639,
7687
    PPC_INS_XVRESP = 1640,
7688
    PPC_INS_XVRSPI = 1641,
7689
    PPC_INS_XVRSPIC = 1642,
7690
    PPC_INS_XVRSPIM = 1643,
7691
    PPC_INS_XVRSPIP = 1644,
7692
    PPC_INS_XVRSPIZ = 1645,
7693
    PPC_INS_XVRSQRTEDP = 1646,
7694
    PPC_INS_XVRSQRTESP = 1647,
7695
    PPC_INS_XVSQRTDP = 1648,
7696
    PPC_INS_XVSQRTSP = 1649,
7697
    PPC_INS_XVSUBDP = 1650,
7698
    PPC_INS_XVSUBSP = 1651,
7699
    PPC_INS_XVTDIVDP = 1652,
7700
    PPC_INS_XVTDIVSP = 1653,
7701
    PPC_INS_XVTSQRTDP = 1654,
7702
    PPC_INS_XVTSQRTSP = 1655,
7703
    PPC_INS_XVTSTDCDP = 1656,
7704
    PPC_INS_XVTSTDCSP = 1657,
7705
    PPC_INS_XVXEXPDP = 1658,
7706
    PPC_INS_XVXEXPSP = 1659,
7707
    PPC_INS_XVXSIGDP = 1660,
7708
    PPC_INS_XVXSIGSP = 1661,
7709
    PPC_INS_XXBRD = 1662,
7710
    PPC_INS_XXBRH = 1663,
7711
    PPC_INS_XXBRQ = 1664,
7712
    PPC_INS_XXBRW = 1665,
7713
    PPC_INS_XXEXTRACTUW = 1666,
7714
    PPC_INS_XXINSERTW = 1667,
7715
    PPC_INS_XXLAND = 1668,
7716
    PPC_INS_XXLANDC = 1669,
7717
    PPC_INS_XXLEQV = 1670,
7718
    PPC_INS_XXLNAND = 1671,
7719
    PPC_INS_XXLNOR = 1672,
7720
    PPC_INS_XXLOR = 1673,
7721
    PPC_INS_XXLORC = 1674,
7722
    PPC_INS_XXLXOR = 1675,
7723
    PPC_INS_XXMRGHD = 1676,
7724
    PPC_INS_XXMRGHW = 1677,
7725
    PPC_INS_XXMRGLD = 1678,
7726
    PPC_INS_XXMRGLW = 1679,
7727
    PPC_INS_XXPERM = 1680,
7728
    PPC_INS_XXPERMDI = 1681,
7729
    PPC_INS_XXPERMR = 1682,
7730
    PPC_INS_XXSEL = 1683,
7731
    PPC_INS_XXSLDWI = 1684,
7732
    PPC_INS_XXSPLTD = 1685,
7733
    PPC_INS_XXSPLTIB = 1686,
7734
    PPC_INS_XXSPLTW = 1687,
7735
    PPC_INS_XXSWAPD = 1688,
7736
    PPC_INS_ENDING = 1689,
7737
}
7738
pub mod ppc_insn_group {
7739
    #[doc = " Group of PPC instructions"]
7740
    pub type Type = libc::c_uint;
7741
    #[doc = "< = CS_GRP_INVALID"]
7742
    pub const PPC_GRP_INVALID: Type = 0;
7743
    #[doc = "< = CS_GRP_JUMP"]
7744
    pub const PPC_GRP_JUMP: Type = 1;
7745
    pub const PPC_GRP_ALTIVEC: Type = 128;
7746
    pub const PPC_GRP_MODE32: Type = 129;
7747
    pub const PPC_GRP_MODE64: Type = 130;
7748
    pub const PPC_GRP_BOOKE: Type = 131;
7749
    pub const PPC_GRP_NOTBOOKE: Type = 132;
7750
    pub const PPC_GRP_SPE: Type = 133;
7751
    pub const PPC_GRP_VSX: Type = 134;
7752
    pub const PPC_GRP_E500: Type = 135;
7753
    pub const PPC_GRP_PPC4XX: Type = 136;
7754
    pub const PPC_GRP_PPC6XX: Type = 137;
7755
    pub const PPC_GRP_ICBT: Type = 138;
7756
    pub const PPC_GRP_P8ALTIVEC: Type = 139;
7757
    pub const PPC_GRP_P8VECTOR: Type = 140;
7758
    pub const PPC_GRP_QPX: Type = 141;
7759
    pub const PPC_GRP_ENDING: Type = 142;
7760
}
7761
#[repr(u32)]
7762
#[doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."]
7763
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
7764
pub enum sparc_cc {
7765
    #[doc = "< invalid CC (default)"]
7766
    SPARC_CC_INVALID = 0,
7767
    #[doc = "< Always"]
7768
    SPARC_CC_ICC_A = 264,
7769
    #[doc = "< Never"]
7770
    SPARC_CC_ICC_N = 256,
7771
    #[doc = "< Not Equal"]
7772
    SPARC_CC_ICC_NE = 265,
7773
    #[doc = "< Equal"]
7774
    SPARC_CC_ICC_E = 257,
7775
    #[doc = "< Greater"]
7776
    SPARC_CC_ICC_G = 266,
7777
    #[doc = "< Less or Equal"]
7778
    SPARC_CC_ICC_LE = 258,
7779
    #[doc = "< Greater or Equal"]
7780
    SPARC_CC_ICC_GE = 267,
7781
    #[doc = "< Less"]
7782
    SPARC_CC_ICC_L = 259,
7783
    #[doc = "< Greater Unsigned"]
7784
    SPARC_CC_ICC_GU = 268,
7785
    #[doc = "< Less or Equal Unsigned"]
7786
    SPARC_CC_ICC_LEU = 260,
7787
    #[doc = "< Carry Clear/Great or Equal Unsigned"]
7788
    SPARC_CC_ICC_CC = 269,
7789
    #[doc = "< Carry Set/Less Unsigned"]
7790
    SPARC_CC_ICC_CS = 261,
7791
    #[doc = "< Positive"]
7792
    SPARC_CC_ICC_POS = 270,
7793
    #[doc = "< Negative"]
7794
    SPARC_CC_ICC_NEG = 262,
7795
    #[doc = "< Overflow Clear"]
7796
    SPARC_CC_ICC_VC = 271,
7797
    #[doc = "< Overflow Set"]
7798
    SPARC_CC_ICC_VS = 263,
7799
    #[doc = "< Always"]
7800
    SPARC_CC_FCC_A = 280,
7801
    #[doc = "< Never"]
7802
    SPARC_CC_FCC_N = 272,
7803
    #[doc = "< Unordered"]
7804
    SPARC_CC_FCC_U = 279,
7805
    #[doc = "< Greater"]
7806
    SPARC_CC_FCC_G = 278,
7807
    #[doc = "< Unordered or Greater"]
7808
    SPARC_CC_FCC_UG = 277,
7809
    #[doc = "< Less"]
7810
    SPARC_CC_FCC_L = 276,
7811
    #[doc = "< Unordered or Less"]
7812
    SPARC_CC_FCC_UL = 275,
7813
    #[doc = "< Less or Greater"]
7814
    SPARC_CC_FCC_LG = 274,
7815
    #[doc = "< Not Equal"]
7816
    SPARC_CC_FCC_NE = 273,
7817
    #[doc = "< Equal"]
7818
    SPARC_CC_FCC_E = 281,
7819
    #[doc = "< Unordered or Equal"]
7820
    SPARC_CC_FCC_UE = 282,
7821
    #[doc = "< Greater or Equal"]
7822
    SPARC_CC_FCC_GE = 283,
7823
    #[doc = "< Unordered or Greater or Equal"]
7824
    SPARC_CC_FCC_UGE = 284,
7825
    #[doc = "< Less or Equal"]
7826
    SPARC_CC_FCC_LE = 285,
7827
    #[doc = "< Unordered or Less or Equal"]
7828
    SPARC_CC_FCC_ULE = 286,
7829
    #[doc = "< Ordered"]
7830
    SPARC_CC_FCC_O = 287,
7831
}
7832
#[repr(u32)]
7833
#[doc = " Branch hint"]
7834
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
7835
pub enum sparc_hint {
7836
    #[doc = "< no hint"]
7837
    SPARC_HINT_INVALID = 0,
7838
    #[doc = "< annul delay slot instruction"]
7839
    SPARC_HINT_A = 1,
7840
    #[doc = "< branch taken"]
7841
    SPARC_HINT_PT = 2,
7842
    #[doc = "< branch NOT taken"]
7843
    SPARC_HINT_PN = 4,
7844
}
7845
#[repr(u32)]
7846
#[doc = " Operand type for instruction's operands"]
7847
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
7848
pub enum sparc_op_type {
7849
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
7850
    SPARC_OP_INVALID = 0,
7851
    #[doc = "< = CS_OP_REG (Register operand)."]
7852
    SPARC_OP_REG = 1,
7853
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
7854
    SPARC_OP_IMM = 2,
7855
    #[doc = "< = CS_OP_MEM (Memory operand)."]
7856
    SPARC_OP_MEM = 3,
7857
}
7858
pub mod sparc_reg {
7859
    #[doc = " SPARC registers"]
7860
    pub type Type = libc::c_uint;
7861
    pub const SPARC_REG_INVALID: Type = 0;
7862
    pub const SPARC_REG_F0: Type = 1;
7863
    pub const SPARC_REG_F1: Type = 2;
7864
    pub const SPARC_REG_F2: Type = 3;
7865
    pub const SPARC_REG_F3: Type = 4;
7866
    pub const SPARC_REG_F4: Type = 5;
7867
    pub const SPARC_REG_F5: Type = 6;
7868
    pub const SPARC_REG_F6: Type = 7;
7869
    pub const SPARC_REG_F7: Type = 8;
7870
    pub const SPARC_REG_F8: Type = 9;
7871
    pub const SPARC_REG_F9: Type = 10;
7872
    pub const SPARC_REG_F10: Type = 11;
7873
    pub const SPARC_REG_F11: Type = 12;
7874
    pub const SPARC_REG_F12: Type = 13;
7875
    pub const SPARC_REG_F13: Type = 14;
7876
    pub const SPARC_REG_F14: Type = 15;
7877
    pub const SPARC_REG_F15: Type = 16;
7878
    pub const SPARC_REG_F16: Type = 17;
7879
    pub const SPARC_REG_F17: Type = 18;
7880
    pub const SPARC_REG_F18: Type = 19;
7881
    pub const SPARC_REG_F19: Type = 20;
7882
    pub const SPARC_REG_F20: Type = 21;
7883
    pub const SPARC_REG_F21: Type = 22;
7884
    pub const SPARC_REG_F22: Type = 23;
7885
    pub const SPARC_REG_F23: Type = 24;
7886
    pub const SPARC_REG_F24: Type = 25;
7887
    pub const SPARC_REG_F25: Type = 26;
7888
    pub const SPARC_REG_F26: Type = 27;
7889
    pub const SPARC_REG_F27: Type = 28;
7890
    pub const SPARC_REG_F28: Type = 29;
7891
    pub const SPARC_REG_F29: Type = 30;
7892
    pub const SPARC_REG_F30: Type = 31;
7893
    pub const SPARC_REG_F31: Type = 32;
7894
    pub const SPARC_REG_F32: Type = 33;
7895
    pub const SPARC_REG_F34: Type = 34;
7896
    pub const SPARC_REG_F36: Type = 35;
7897
    pub const SPARC_REG_F38: Type = 36;
7898
    pub const SPARC_REG_F40: Type = 37;
7899
    pub const SPARC_REG_F42: Type = 38;
7900
    pub const SPARC_REG_F44: Type = 39;
7901
    pub const SPARC_REG_F46: Type = 40;
7902
    pub const SPARC_REG_F48: Type = 41;
7903
    pub const SPARC_REG_F50: Type = 42;
7904
    pub const SPARC_REG_F52: Type = 43;
7905
    pub const SPARC_REG_F54: Type = 44;
7906
    pub const SPARC_REG_F56: Type = 45;
7907
    pub const SPARC_REG_F58: Type = 46;
7908
    pub const SPARC_REG_F60: Type = 47;
7909
    pub const SPARC_REG_F62: Type = 48;
7910
    pub const SPARC_REG_FCC0: Type = 49;
7911
    pub const SPARC_REG_FCC1: Type = 50;
7912
    pub const SPARC_REG_FCC2: Type = 51;
7913
    pub const SPARC_REG_FCC3: Type = 52;
7914
    pub const SPARC_REG_FP: Type = 53;
7915
    pub const SPARC_REG_G0: Type = 54;
7916
    pub const SPARC_REG_G1: Type = 55;
7917
    pub const SPARC_REG_G2: Type = 56;
7918
    pub const SPARC_REG_G3: Type = 57;
7919
    pub const SPARC_REG_G4: Type = 58;
7920
    pub const SPARC_REG_G5: Type = 59;
7921
    pub const SPARC_REG_G6: Type = 60;
7922
    pub const SPARC_REG_G7: Type = 61;
7923
    pub const SPARC_REG_I0: Type = 62;
7924
    pub const SPARC_REG_I1: Type = 63;
7925
    pub const SPARC_REG_I2: Type = 64;
7926
    pub const SPARC_REG_I3: Type = 65;
7927
    pub const SPARC_REG_I4: Type = 66;
7928
    pub const SPARC_REG_I5: Type = 67;
7929
    pub const SPARC_REG_I7: Type = 68;
7930
    pub const SPARC_REG_ICC: Type = 69;
7931
    pub const SPARC_REG_L0: Type = 70;
7932
    pub const SPARC_REG_L1: Type = 71;
7933
    pub const SPARC_REG_L2: Type = 72;
7934
    pub const SPARC_REG_L3: Type = 73;
7935
    pub const SPARC_REG_L4: Type = 74;
7936
    pub const SPARC_REG_L5: Type = 75;
7937
    pub const SPARC_REG_L6: Type = 76;
7938
    pub const SPARC_REG_L7: Type = 77;
7939
    pub const SPARC_REG_O0: Type = 78;
7940
    pub const SPARC_REG_O1: Type = 79;
7941
    pub const SPARC_REG_O2: Type = 80;
7942
    pub const SPARC_REG_O3: Type = 81;
7943
    pub const SPARC_REG_O4: Type = 82;
7944
    pub const SPARC_REG_O5: Type = 83;
7945
    pub const SPARC_REG_O7: Type = 84;
7946
    pub const SPARC_REG_SP: Type = 85;
7947
    pub const SPARC_REG_Y: Type = 86;
7948
    pub const SPARC_REG_XCC: Type = 87;
7949
    pub const SPARC_REG_ENDING: Type = 88;
7950
    pub const SPARC_REG_O6: Type = 85;
7951
    pub const SPARC_REG_I6: Type = 53;
7952
}
7953
#[doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"]
7954
#[repr(C)]
7955
#[derive(Debug, Copy, Clone)]
7956
pub struct sparc_op_mem {
7957
    #[doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"]
7958
    pub base: u8,
7959
    #[doc = "< index register, same conditions apply here"]
7960
    pub index: u8,
7961
    #[doc = "< displacement/offset value"]
7962
    pub disp: i32,
7963
}
7964
#[doc = " Instruction operand"]
7965
#[repr(C)]
7966
#[derive(Copy, Clone)]
7967
pub struct cs_sparc_op {
7968
    #[doc = "< operand type"]
7969
    pub type_: sparc_op_type,
7970
    pub __bindgen_anon_1: cs_sparc_op__bindgen_ty_1,
7971
}
7972
#[repr(C)]
7973
#[derive(Copy, Clone)]
7974
pub union cs_sparc_op__bindgen_ty_1 {
7975
    #[doc = "< register value for REG operand"]
7976
    pub reg: sparc_reg::Type,
7977
    #[doc = "< immediate value for IMM operand"]
7978
    pub imm: i64,
7979
    #[doc = "< base/disp value for MEM operand"]
7980
    pub mem: sparc_op_mem,
7981
}
7982
impl ::core::fmt::Debug for cs_sparc_op__bindgen_ty_1 {
7983
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
7984
0
        write!(f, "cs_sparc_op__bindgen_ty_1 {{ union }}")
7985
0
    }
7986
}
7987
impl ::core::fmt::Debug for cs_sparc_op {
7988
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
7989
0
        write!(
7990
0
            f,
7991
0
            "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
7992
            self.type_, self.__bindgen_anon_1
7993
        )
7994
0
    }
7995
}
7996
#[doc = " Instruction structure"]
7997
#[repr(C)]
7998
#[derive(Copy, Clone)]
7999
pub struct cs_sparc {
8000
    #[doc = "< code condition for this insn"]
8001
    pub cc: sparc_cc,
8002
    #[doc = "< branch hint: encoding as bitwise OR of sparc_hint."]
8003
    pub hint: sparc_hint,
8004
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
8005
    pub op_count: u8,
8006
    #[doc = "< operands for this instruction."]
8007
    pub operands: [cs_sparc_op; 4usize],
8008
}
8009
impl ::core::fmt::Debug for cs_sparc {
8010
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
8011
0
        write!(
8012
0
            f,
8013
0
            "cs_sparc {{ cc: {:?}, hint: {:?}, operands: {:?} }}",
8014
            self.cc, self.hint, self.operands
8015
        )
8016
0
    }
8017
}
8018
#[repr(u32)]
8019
#[doc = " SPARC instruction"]
8020
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
8021
pub enum sparc_insn {
8022
    SPARC_INS_INVALID = 0,
8023
    SPARC_INS_ADDCC = 1,
8024
    SPARC_INS_ADDX = 2,
8025
    SPARC_INS_ADDXCC = 3,
8026
    SPARC_INS_ADDXC = 4,
8027
    SPARC_INS_ADDXCCC = 5,
8028
    SPARC_INS_ADD = 6,
8029
    SPARC_INS_ALIGNADDR = 7,
8030
    SPARC_INS_ALIGNADDRL = 8,
8031
    SPARC_INS_ANDCC = 9,
8032
    SPARC_INS_ANDNCC = 10,
8033
    SPARC_INS_ANDN = 11,
8034
    SPARC_INS_AND = 12,
8035
    SPARC_INS_ARRAY16 = 13,
8036
    SPARC_INS_ARRAY32 = 14,
8037
    SPARC_INS_ARRAY8 = 15,
8038
    SPARC_INS_B = 16,
8039
    SPARC_INS_JMP = 17,
8040
    SPARC_INS_BMASK = 18,
8041
    SPARC_INS_FB = 19,
8042
    SPARC_INS_BRGEZ = 20,
8043
    SPARC_INS_BRGZ = 21,
8044
    SPARC_INS_BRLEZ = 22,
8045
    SPARC_INS_BRLZ = 23,
8046
    SPARC_INS_BRNZ = 24,
8047
    SPARC_INS_BRZ = 25,
8048
    SPARC_INS_BSHUFFLE = 26,
8049
    SPARC_INS_CALL = 27,
8050
    SPARC_INS_CASX = 28,
8051
    SPARC_INS_CAS = 29,
8052
    SPARC_INS_CMASK16 = 30,
8053
    SPARC_INS_CMASK32 = 31,
8054
    SPARC_INS_CMASK8 = 32,
8055
    SPARC_INS_CMP = 33,
8056
    SPARC_INS_EDGE16 = 34,
8057
    SPARC_INS_EDGE16L = 35,
8058
    SPARC_INS_EDGE16LN = 36,
8059
    SPARC_INS_EDGE16N = 37,
8060
    SPARC_INS_EDGE32 = 38,
8061
    SPARC_INS_EDGE32L = 39,
8062
    SPARC_INS_EDGE32LN = 40,
8063
    SPARC_INS_EDGE32N = 41,
8064
    SPARC_INS_EDGE8 = 42,
8065
    SPARC_INS_EDGE8L = 43,
8066
    SPARC_INS_EDGE8LN = 44,
8067
    SPARC_INS_EDGE8N = 45,
8068
    SPARC_INS_FABSD = 46,
8069
    SPARC_INS_FABSQ = 47,
8070
    SPARC_INS_FABSS = 48,
8071
    SPARC_INS_FADDD = 49,
8072
    SPARC_INS_FADDQ = 50,
8073
    SPARC_INS_FADDS = 51,
8074
    SPARC_INS_FALIGNDATA = 52,
8075
    SPARC_INS_FAND = 53,
8076
    SPARC_INS_FANDNOT1 = 54,
8077
    SPARC_INS_FANDNOT1S = 55,
8078
    SPARC_INS_FANDNOT2 = 56,
8079
    SPARC_INS_FANDNOT2S = 57,
8080
    SPARC_INS_FANDS = 58,
8081
    SPARC_INS_FCHKSM16 = 59,
8082
    SPARC_INS_FCMPD = 60,
8083
    SPARC_INS_FCMPEQ16 = 61,
8084
    SPARC_INS_FCMPEQ32 = 62,
8085
    SPARC_INS_FCMPGT16 = 63,
8086
    SPARC_INS_FCMPGT32 = 64,
8087
    SPARC_INS_FCMPLE16 = 65,
8088
    SPARC_INS_FCMPLE32 = 66,
8089
    SPARC_INS_FCMPNE16 = 67,
8090
    SPARC_INS_FCMPNE32 = 68,
8091
    SPARC_INS_FCMPQ = 69,
8092
    SPARC_INS_FCMPS = 70,
8093
    SPARC_INS_FDIVD = 71,
8094
    SPARC_INS_FDIVQ = 72,
8095
    SPARC_INS_FDIVS = 73,
8096
    SPARC_INS_FDMULQ = 74,
8097
    SPARC_INS_FDTOI = 75,
8098
    SPARC_INS_FDTOQ = 76,
8099
    SPARC_INS_FDTOS = 77,
8100
    SPARC_INS_FDTOX = 78,
8101
    SPARC_INS_FEXPAND = 79,
8102
    SPARC_INS_FHADDD = 80,
8103
    SPARC_INS_FHADDS = 81,
8104
    SPARC_INS_FHSUBD = 82,
8105
    SPARC_INS_FHSUBS = 83,
8106
    SPARC_INS_FITOD = 84,
8107
    SPARC_INS_FITOQ = 85,
8108
    SPARC_INS_FITOS = 86,
8109
    SPARC_INS_FLCMPD = 87,
8110
    SPARC_INS_FLCMPS = 88,
8111
    SPARC_INS_FLUSHW = 89,
8112
    SPARC_INS_FMEAN16 = 90,
8113
    SPARC_INS_FMOVD = 91,
8114
    SPARC_INS_FMOVQ = 92,
8115
    SPARC_INS_FMOVRDGEZ = 93,
8116
    SPARC_INS_FMOVRQGEZ = 94,
8117
    SPARC_INS_FMOVRSGEZ = 95,
8118
    SPARC_INS_FMOVRDGZ = 96,
8119
    SPARC_INS_FMOVRQGZ = 97,
8120
    SPARC_INS_FMOVRSGZ = 98,
8121
    SPARC_INS_FMOVRDLEZ = 99,
8122
    SPARC_INS_FMOVRQLEZ = 100,
8123
    SPARC_INS_FMOVRSLEZ = 101,
8124
    SPARC_INS_FMOVRDLZ = 102,
8125
    SPARC_INS_FMOVRQLZ = 103,
8126
    SPARC_INS_FMOVRSLZ = 104,
8127
    SPARC_INS_FMOVRDNZ = 105,
8128
    SPARC_INS_FMOVRQNZ = 106,
8129
    SPARC_INS_FMOVRSNZ = 107,
8130
    SPARC_INS_FMOVRDZ = 108,
8131
    SPARC_INS_FMOVRQZ = 109,
8132
    SPARC_INS_FMOVRSZ = 110,
8133
    SPARC_INS_FMOVS = 111,
8134
    SPARC_INS_FMUL8SUX16 = 112,
8135
    SPARC_INS_FMUL8ULX16 = 113,
8136
    SPARC_INS_FMUL8X16 = 114,
8137
    SPARC_INS_FMUL8X16AL = 115,
8138
    SPARC_INS_FMUL8X16AU = 116,
8139
    SPARC_INS_FMULD = 117,
8140
    SPARC_INS_FMULD8SUX16 = 118,
8141
    SPARC_INS_FMULD8ULX16 = 119,
8142
    SPARC_INS_FMULQ = 120,
8143
    SPARC_INS_FMULS = 121,
8144
    SPARC_INS_FNADDD = 122,
8145
    SPARC_INS_FNADDS = 123,
8146
    SPARC_INS_FNAND = 124,
8147
    SPARC_INS_FNANDS = 125,
8148
    SPARC_INS_FNEGD = 126,
8149
    SPARC_INS_FNEGQ = 127,
8150
    SPARC_INS_FNEGS = 128,
8151
    SPARC_INS_FNHADDD = 129,
8152
    SPARC_INS_FNHADDS = 130,
8153
    SPARC_INS_FNOR = 131,
8154
    SPARC_INS_FNORS = 132,
8155
    SPARC_INS_FNOT1 = 133,
8156
    SPARC_INS_FNOT1S = 134,
8157
    SPARC_INS_FNOT2 = 135,
8158
    SPARC_INS_FNOT2S = 136,
8159
    SPARC_INS_FONE = 137,
8160
    SPARC_INS_FONES = 138,
8161
    SPARC_INS_FOR = 139,
8162
    SPARC_INS_FORNOT1 = 140,
8163
    SPARC_INS_FORNOT1S = 141,
8164
    SPARC_INS_FORNOT2 = 142,
8165
    SPARC_INS_FORNOT2S = 143,
8166
    SPARC_INS_FORS = 144,
8167
    SPARC_INS_FPACK16 = 145,
8168
    SPARC_INS_FPACK32 = 146,
8169
    SPARC_INS_FPACKFIX = 147,
8170
    SPARC_INS_FPADD16 = 148,
8171
    SPARC_INS_FPADD16S = 149,
8172
    SPARC_INS_FPADD32 = 150,
8173
    SPARC_INS_FPADD32S = 151,
8174
    SPARC_INS_FPADD64 = 152,
8175
    SPARC_INS_FPMERGE = 153,
8176
    SPARC_INS_FPSUB16 = 154,
8177
    SPARC_INS_FPSUB16S = 155,
8178
    SPARC_INS_FPSUB32 = 156,
8179
    SPARC_INS_FPSUB32S = 157,
8180
    SPARC_INS_FQTOD = 158,
8181
    SPARC_INS_FQTOI = 159,
8182
    SPARC_INS_FQTOS = 160,
8183
    SPARC_INS_FQTOX = 161,
8184
    SPARC_INS_FSLAS16 = 162,
8185
    SPARC_INS_FSLAS32 = 163,
8186
    SPARC_INS_FSLL16 = 164,
8187
    SPARC_INS_FSLL32 = 165,
8188
    SPARC_INS_FSMULD = 166,
8189
    SPARC_INS_FSQRTD = 167,
8190
    SPARC_INS_FSQRTQ = 168,
8191
    SPARC_INS_FSQRTS = 169,
8192
    SPARC_INS_FSRA16 = 170,
8193
    SPARC_INS_FSRA32 = 171,
8194
    SPARC_INS_FSRC1 = 172,
8195
    SPARC_INS_FSRC1S = 173,
8196
    SPARC_INS_FSRC2 = 174,
8197
    SPARC_INS_FSRC2S = 175,
8198
    SPARC_INS_FSRL16 = 176,
8199
    SPARC_INS_FSRL32 = 177,
8200
    SPARC_INS_FSTOD = 178,
8201
    SPARC_INS_FSTOI = 179,
8202
    SPARC_INS_FSTOQ = 180,
8203
    SPARC_INS_FSTOX = 181,
8204
    SPARC_INS_FSUBD = 182,
8205
    SPARC_INS_FSUBQ = 183,
8206
    SPARC_INS_FSUBS = 184,
8207
    SPARC_INS_FXNOR = 185,
8208
    SPARC_INS_FXNORS = 186,
8209
    SPARC_INS_FXOR = 187,
8210
    SPARC_INS_FXORS = 188,
8211
    SPARC_INS_FXTOD = 189,
8212
    SPARC_INS_FXTOQ = 190,
8213
    SPARC_INS_FXTOS = 191,
8214
    SPARC_INS_FZERO = 192,
8215
    SPARC_INS_FZEROS = 193,
8216
    SPARC_INS_JMPL = 194,
8217
    SPARC_INS_LDD = 195,
8218
    SPARC_INS_LD = 196,
8219
    SPARC_INS_LDQ = 197,
8220
    SPARC_INS_LDSB = 198,
8221
    SPARC_INS_LDSH = 199,
8222
    SPARC_INS_LDSW = 200,
8223
    SPARC_INS_LDUB = 201,
8224
    SPARC_INS_LDUH = 202,
8225
    SPARC_INS_LDX = 203,
8226
    SPARC_INS_LZCNT = 204,
8227
    SPARC_INS_MEMBAR = 205,
8228
    SPARC_INS_MOVDTOX = 206,
8229
    SPARC_INS_MOV = 207,
8230
    SPARC_INS_MOVRGEZ = 208,
8231
    SPARC_INS_MOVRGZ = 209,
8232
    SPARC_INS_MOVRLEZ = 210,
8233
    SPARC_INS_MOVRLZ = 211,
8234
    SPARC_INS_MOVRNZ = 212,
8235
    SPARC_INS_MOVRZ = 213,
8236
    SPARC_INS_MOVSTOSW = 214,
8237
    SPARC_INS_MOVSTOUW = 215,
8238
    SPARC_INS_MULX = 216,
8239
    SPARC_INS_NOP = 217,
8240
    SPARC_INS_ORCC = 218,
8241
    SPARC_INS_ORNCC = 219,
8242
    SPARC_INS_ORN = 220,
8243
    SPARC_INS_OR = 221,
8244
    SPARC_INS_PDIST = 222,
8245
    SPARC_INS_PDISTN = 223,
8246
    SPARC_INS_POPC = 224,
8247
    SPARC_INS_RD = 225,
8248
    SPARC_INS_RESTORE = 226,
8249
    SPARC_INS_RETT = 227,
8250
    SPARC_INS_SAVE = 228,
8251
    SPARC_INS_SDIVCC = 229,
8252
    SPARC_INS_SDIVX = 230,
8253
    SPARC_INS_SDIV = 231,
8254
    SPARC_INS_SETHI = 232,
8255
    SPARC_INS_SHUTDOWN = 233,
8256
    SPARC_INS_SIAM = 234,
8257
    SPARC_INS_SLLX = 235,
8258
    SPARC_INS_SLL = 236,
8259
    SPARC_INS_SMULCC = 237,
8260
    SPARC_INS_SMUL = 238,
8261
    SPARC_INS_SRAX = 239,
8262
    SPARC_INS_SRA = 240,
8263
    SPARC_INS_SRLX = 241,
8264
    SPARC_INS_SRL = 242,
8265
    SPARC_INS_STBAR = 243,
8266
    SPARC_INS_STB = 244,
8267
    SPARC_INS_STD = 245,
8268
    SPARC_INS_ST = 246,
8269
    SPARC_INS_STH = 247,
8270
    SPARC_INS_STQ = 248,
8271
    SPARC_INS_STX = 249,
8272
    SPARC_INS_SUBCC = 250,
8273
    SPARC_INS_SUBX = 251,
8274
    SPARC_INS_SUBXCC = 252,
8275
    SPARC_INS_SUB = 253,
8276
    SPARC_INS_SWAP = 254,
8277
    SPARC_INS_TADDCCTV = 255,
8278
    SPARC_INS_TADDCC = 256,
8279
    SPARC_INS_T = 257,
8280
    SPARC_INS_TSUBCCTV = 258,
8281
    SPARC_INS_TSUBCC = 259,
8282
    SPARC_INS_UDIVCC = 260,
8283
    SPARC_INS_UDIVX = 261,
8284
    SPARC_INS_UDIV = 262,
8285
    SPARC_INS_UMULCC = 263,
8286
    SPARC_INS_UMULXHI = 264,
8287
    SPARC_INS_UMUL = 265,
8288
    SPARC_INS_UNIMP = 266,
8289
    SPARC_INS_FCMPED = 267,
8290
    SPARC_INS_FCMPEQ = 268,
8291
    SPARC_INS_FCMPES = 269,
8292
    SPARC_INS_WR = 270,
8293
    SPARC_INS_XMULX = 271,
8294
    SPARC_INS_XMULXHI = 272,
8295
    SPARC_INS_XNORCC = 273,
8296
    SPARC_INS_XNOR = 274,
8297
    SPARC_INS_XORCC = 275,
8298
    SPARC_INS_XOR = 276,
8299
    SPARC_INS_RET = 277,
8300
    SPARC_INS_RETL = 278,
8301
    SPARC_INS_ENDING = 279,
8302
}
8303
pub mod sparc_insn_group {
8304
    #[doc = " Group of SPARC instructions"]
8305
    pub type Type = libc::c_uint;
8306
    #[doc = "< = CS_GRP_INVALID"]
8307
    pub const SPARC_GRP_INVALID: Type = 0;
8308
    #[doc = "< = CS_GRP_JUMP"]
8309
    pub const SPARC_GRP_JUMP: Type = 1;
8310
    pub const SPARC_GRP_HARDQUAD: Type = 128;
8311
    pub const SPARC_GRP_V9: Type = 129;
8312
    pub const SPARC_GRP_VIS: Type = 130;
8313
    pub const SPARC_GRP_VIS2: Type = 131;
8314
    pub const SPARC_GRP_VIS3: Type = 132;
8315
    pub const SPARC_GRP_32BIT: Type = 133;
8316
    pub const SPARC_GRP_64BIT: Type = 134;
8317
    pub const SPARC_GRP_ENDING: Type = 135;
8318
}
8319
#[repr(u32)]
8320
#[doc = " Enums corresponding to SystemZ condition codes"]
8321
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
8322
pub enum sysz_cc {
8323
    #[doc = "< invalid CC (default)"]
8324
    SYSZ_CC_INVALID = 0,
8325
    SYSZ_CC_O = 1,
8326
    SYSZ_CC_H = 2,
8327
    SYSZ_CC_NLE = 3,
8328
    SYSZ_CC_L = 4,
8329
    SYSZ_CC_NHE = 5,
8330
    SYSZ_CC_LH = 6,
8331
    SYSZ_CC_NE = 7,
8332
    SYSZ_CC_E = 8,
8333
    SYSZ_CC_NLH = 9,
8334
    SYSZ_CC_HE = 10,
8335
    SYSZ_CC_NL = 11,
8336
    SYSZ_CC_LE = 12,
8337
    SYSZ_CC_NH = 13,
8338
    SYSZ_CC_NO = 14,
8339
}
8340
#[repr(u32)]
8341
#[doc = " Operand type for instruction's operands"]
8342
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
8343
pub enum sysz_op_type {
8344
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
8345
    SYSZ_OP_INVALID = 0,
8346
    #[doc = "< = CS_OP_REG (Register operand)."]
8347
    SYSZ_OP_REG = 1,
8348
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
8349
    SYSZ_OP_IMM = 2,
8350
    #[doc = "< = CS_OP_MEM (Memory operand)."]
8351
    SYSZ_OP_MEM = 3,
8352
    #[doc = "< Access register operand."]
8353
    SYSZ_OP_ACREG = 64,
8354
}
8355
pub mod sysz_reg {
8356
    #[doc = " SystemZ registers"]
8357
    pub type Type = libc::c_uint;
8358
    pub const SYSZ_REG_INVALID: Type = 0;
8359
    pub const SYSZ_REG_0: Type = 1;
8360
    pub const SYSZ_REG_1: Type = 2;
8361
    pub const SYSZ_REG_2: Type = 3;
8362
    pub const SYSZ_REG_3: Type = 4;
8363
    pub const SYSZ_REG_4: Type = 5;
8364
    pub const SYSZ_REG_5: Type = 6;
8365
    pub const SYSZ_REG_6: Type = 7;
8366
    pub const SYSZ_REG_7: Type = 8;
8367
    pub const SYSZ_REG_8: Type = 9;
8368
    pub const SYSZ_REG_9: Type = 10;
8369
    pub const SYSZ_REG_10: Type = 11;
8370
    pub const SYSZ_REG_11: Type = 12;
8371
    pub const SYSZ_REG_12: Type = 13;
8372
    pub const SYSZ_REG_13: Type = 14;
8373
    pub const SYSZ_REG_14: Type = 15;
8374
    pub const SYSZ_REG_15: Type = 16;
8375
    pub const SYSZ_REG_CC: Type = 17;
8376
    pub const SYSZ_REG_F0: Type = 18;
8377
    pub const SYSZ_REG_F1: Type = 19;
8378
    pub const SYSZ_REG_F2: Type = 20;
8379
    pub const SYSZ_REG_F3: Type = 21;
8380
    pub const SYSZ_REG_F4: Type = 22;
8381
    pub const SYSZ_REG_F5: Type = 23;
8382
    pub const SYSZ_REG_F6: Type = 24;
8383
    pub const SYSZ_REG_F7: Type = 25;
8384
    pub const SYSZ_REG_F8: Type = 26;
8385
    pub const SYSZ_REG_F9: Type = 27;
8386
    pub const SYSZ_REG_F10: Type = 28;
8387
    pub const SYSZ_REG_F11: Type = 29;
8388
    pub const SYSZ_REG_F12: Type = 30;
8389
    pub const SYSZ_REG_F13: Type = 31;
8390
    pub const SYSZ_REG_F14: Type = 32;
8391
    pub const SYSZ_REG_F15: Type = 33;
8392
    pub const SYSZ_REG_R0L: Type = 34;
8393
    pub const SYSZ_REG_A0: Type = 35;
8394
    pub const SYSZ_REG_A1: Type = 36;
8395
    pub const SYSZ_REG_A2: Type = 37;
8396
    pub const SYSZ_REG_A3: Type = 38;
8397
    pub const SYSZ_REG_A4: Type = 39;
8398
    pub const SYSZ_REG_A5: Type = 40;
8399
    pub const SYSZ_REG_A6: Type = 41;
8400
    pub const SYSZ_REG_A7: Type = 42;
8401
    pub const SYSZ_REG_A8: Type = 43;
8402
    pub const SYSZ_REG_A9: Type = 44;
8403
    pub const SYSZ_REG_A10: Type = 45;
8404
    pub const SYSZ_REG_A11: Type = 46;
8405
    pub const SYSZ_REG_A12: Type = 47;
8406
    pub const SYSZ_REG_A13: Type = 48;
8407
    pub const SYSZ_REG_A14: Type = 49;
8408
    pub const SYSZ_REG_A15: Type = 50;
8409
    pub const SYSZ_REG_C0: Type = 51;
8410
    pub const SYSZ_REG_C1: Type = 52;
8411
    pub const SYSZ_REG_C2: Type = 53;
8412
    pub const SYSZ_REG_C3: Type = 54;
8413
    pub const SYSZ_REG_C4: Type = 55;
8414
    pub const SYSZ_REG_C5: Type = 56;
8415
    pub const SYSZ_REG_C6: Type = 57;
8416
    pub const SYSZ_REG_C7: Type = 58;
8417
    pub const SYSZ_REG_C8: Type = 59;
8418
    pub const SYSZ_REG_C9: Type = 60;
8419
    pub const SYSZ_REG_C10: Type = 61;
8420
    pub const SYSZ_REG_C11: Type = 62;
8421
    pub const SYSZ_REG_C12: Type = 63;
8422
    pub const SYSZ_REG_C13: Type = 64;
8423
    pub const SYSZ_REG_C14: Type = 65;
8424
    pub const SYSZ_REG_C15: Type = 66;
8425
    pub const SYSZ_REG_V0: Type = 67;
8426
    pub const SYSZ_REG_V1: Type = 68;
8427
    pub const SYSZ_REG_V2: Type = 69;
8428
    pub const SYSZ_REG_V3: Type = 70;
8429
    pub const SYSZ_REG_V4: Type = 71;
8430
    pub const SYSZ_REG_V5: Type = 72;
8431
    pub const SYSZ_REG_V6: Type = 73;
8432
    pub const SYSZ_REG_V7: Type = 74;
8433
    pub const SYSZ_REG_V8: Type = 75;
8434
    pub const SYSZ_REG_V9: Type = 76;
8435
    pub const SYSZ_REG_V10: Type = 77;
8436
    pub const SYSZ_REG_V11: Type = 78;
8437
    pub const SYSZ_REG_V12: Type = 79;
8438
    pub const SYSZ_REG_V13: Type = 80;
8439
    pub const SYSZ_REG_V14: Type = 81;
8440
    pub const SYSZ_REG_V15: Type = 82;
8441
    pub const SYSZ_REG_V16: Type = 83;
8442
    pub const SYSZ_REG_V17: Type = 84;
8443
    pub const SYSZ_REG_V18: Type = 85;
8444
    pub const SYSZ_REG_V19: Type = 86;
8445
    pub const SYSZ_REG_V20: Type = 87;
8446
    pub const SYSZ_REG_V21: Type = 88;
8447
    pub const SYSZ_REG_V22: Type = 89;
8448
    pub const SYSZ_REG_V23: Type = 90;
8449
    pub const SYSZ_REG_V24: Type = 91;
8450
    pub const SYSZ_REG_V25: Type = 92;
8451
    pub const SYSZ_REG_V26: Type = 93;
8452
    pub const SYSZ_REG_V27: Type = 94;
8453
    pub const SYSZ_REG_V28: Type = 95;
8454
    pub const SYSZ_REG_V29: Type = 96;
8455
    pub const SYSZ_REG_V30: Type = 97;
8456
    pub const SYSZ_REG_V31: Type = 98;
8457
    pub const SYSZ_REG_F16: Type = 99;
8458
    pub const SYSZ_REG_F17: Type = 100;
8459
    pub const SYSZ_REG_F18: Type = 101;
8460
    pub const SYSZ_REG_F19: Type = 102;
8461
    pub const SYSZ_REG_F20: Type = 103;
8462
    pub const SYSZ_REG_F21: Type = 104;
8463
    pub const SYSZ_REG_F22: Type = 105;
8464
    pub const SYSZ_REG_F23: Type = 106;
8465
    pub const SYSZ_REG_F24: Type = 107;
8466
    pub const SYSZ_REG_F25: Type = 108;
8467
    pub const SYSZ_REG_F26: Type = 109;
8468
    pub const SYSZ_REG_F27: Type = 110;
8469
    pub const SYSZ_REG_F28: Type = 111;
8470
    pub const SYSZ_REG_F29: Type = 112;
8471
    pub const SYSZ_REG_F30: Type = 113;
8472
    pub const SYSZ_REG_F31: Type = 114;
8473
    pub const SYSZ_REG_F0Q: Type = 115;
8474
    pub const SYSZ_REG_F4Q: Type = 116;
8475
    pub const SYSZ_REG_ENDING: Type = 117;
8476
}
8477
#[doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"]
8478
#[repr(C)]
8479
#[derive(Debug, Copy, Clone)]
8480
pub struct sysz_op_mem {
8481
    #[doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"]
8482
    pub base: u8,
8483
    #[doc = "< index register, same conditions apply here"]
8484
    pub index: u8,
8485
    #[doc = "< BDLAddr operand"]
8486
    pub length: u64,
8487
    #[doc = "< displacement/offset value"]
8488
    pub disp: i64,
8489
}
8490
#[doc = " Instruction operand"]
8491
#[repr(C)]
8492
#[derive(Copy, Clone)]
8493
pub struct cs_sysz_op {
8494
    #[doc = "< operand type"]
8495
    pub type_: sysz_op_type,
8496
    pub __bindgen_anon_1: cs_sysz_op__bindgen_ty_1,
8497
}
8498
#[repr(C)]
8499
#[derive(Copy, Clone)]
8500
pub union cs_sysz_op__bindgen_ty_1 {
8501
    #[doc = "< register value for REG operand"]
8502
    pub reg: sysz_reg::Type,
8503
    #[doc = "< immediate value for IMM operand"]
8504
    pub imm: i64,
8505
    #[doc = "< base/disp value for MEM operand"]
8506
    pub mem: sysz_op_mem,
8507
}
8508
impl ::core::fmt::Debug for cs_sysz_op__bindgen_ty_1 {
8509
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
8510
0
        write!(f, "cs_sysz_op__bindgen_ty_1 {{ union }}")
8511
0
    }
8512
}
8513
impl ::core::fmt::Debug for cs_sysz_op {
8514
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
8515
0
        write!(
8516
0
            f,
8517
0
            "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
8518
            self.type_, self.__bindgen_anon_1
8519
        )
8520
0
    }
8521
}
8522
#[repr(C)]
8523
#[derive(Copy, Clone)]
8524
pub struct cs_sysz {
8525
    #[doc = "< Code condition"]
8526
    pub cc: sysz_cc,
8527
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
8528
    pub op_count: u8,
8529
    #[doc = "< operands for this instruction."]
8530
    pub operands: [cs_sysz_op; 6usize],
8531
}
8532
impl ::core::fmt::Debug for cs_sysz {
8533
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
8534
0
        write!(
8535
0
            f,
8536
0
            "cs_sysz {{ cc: {:?}, operands: {:?} }}",
8537
            self.cc, self.operands
8538
        )
8539
0
    }
8540
}
8541
#[repr(u32)]
8542
#[doc = " SystemZ instruction"]
8543
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
8544
pub enum sysz_insn {
8545
    SYSZ_INS_INVALID = 0,
8546
    SYSZ_INS_A = 1,
8547
    SYSZ_INS_ADB = 2,
8548
    SYSZ_INS_ADBR = 3,
8549
    SYSZ_INS_AEB = 4,
8550
    SYSZ_INS_AEBR = 5,
8551
    SYSZ_INS_AFI = 6,
8552
    SYSZ_INS_AG = 7,
8553
    SYSZ_INS_AGF = 8,
8554
    SYSZ_INS_AGFI = 9,
8555
    SYSZ_INS_AGFR = 10,
8556
    SYSZ_INS_AGHI = 11,
8557
    SYSZ_INS_AGHIK = 12,
8558
    SYSZ_INS_AGR = 13,
8559
    SYSZ_INS_AGRK = 14,
8560
    SYSZ_INS_AGSI = 15,
8561
    SYSZ_INS_AH = 16,
8562
    SYSZ_INS_AHI = 17,
8563
    SYSZ_INS_AHIK = 18,
8564
    SYSZ_INS_AHY = 19,
8565
    SYSZ_INS_AIH = 20,
8566
    SYSZ_INS_AL = 21,
8567
    SYSZ_INS_ALC = 22,
8568
    SYSZ_INS_ALCG = 23,
8569
    SYSZ_INS_ALCGR = 24,
8570
    SYSZ_INS_ALCR = 25,
8571
    SYSZ_INS_ALFI = 26,
8572
    SYSZ_INS_ALG = 27,
8573
    SYSZ_INS_ALGF = 28,
8574
    SYSZ_INS_ALGFI = 29,
8575
    SYSZ_INS_ALGFR = 30,
8576
    SYSZ_INS_ALGHSIK = 31,
8577
    SYSZ_INS_ALGR = 32,
8578
    SYSZ_INS_ALGRK = 33,
8579
    SYSZ_INS_ALHSIK = 34,
8580
    SYSZ_INS_ALR = 35,
8581
    SYSZ_INS_ALRK = 36,
8582
    SYSZ_INS_ALY = 37,
8583
    SYSZ_INS_AR = 38,
8584
    SYSZ_INS_ARK = 39,
8585
    SYSZ_INS_ASI = 40,
8586
    SYSZ_INS_AXBR = 41,
8587
    SYSZ_INS_AY = 42,
8588
    SYSZ_INS_BCR = 43,
8589
    SYSZ_INS_BRC = 44,
8590
    SYSZ_INS_BRCL = 45,
8591
    SYSZ_INS_CGIJ = 46,
8592
    SYSZ_INS_CGRJ = 47,
8593
    SYSZ_INS_CIJ = 48,
8594
    SYSZ_INS_CLGIJ = 49,
8595
    SYSZ_INS_CLGRJ = 50,
8596
    SYSZ_INS_CLIJ = 51,
8597
    SYSZ_INS_CLRJ = 52,
8598
    SYSZ_INS_CRJ = 53,
8599
    SYSZ_INS_BER = 54,
8600
    SYSZ_INS_JE = 55,
8601
    SYSZ_INS_JGE = 56,
8602
    SYSZ_INS_LOCE = 57,
8603
    SYSZ_INS_LOCGE = 58,
8604
    SYSZ_INS_LOCGRE = 59,
8605
    SYSZ_INS_LOCRE = 60,
8606
    SYSZ_INS_STOCE = 61,
8607
    SYSZ_INS_STOCGE = 62,
8608
    SYSZ_INS_BHR = 63,
8609
    SYSZ_INS_BHER = 64,
8610
    SYSZ_INS_JHE = 65,
8611
    SYSZ_INS_JGHE = 66,
8612
    SYSZ_INS_LOCHE = 67,
8613
    SYSZ_INS_LOCGHE = 68,
8614
    SYSZ_INS_LOCGRHE = 69,
8615
    SYSZ_INS_LOCRHE = 70,
8616
    SYSZ_INS_STOCHE = 71,
8617
    SYSZ_INS_STOCGHE = 72,
8618
    SYSZ_INS_JH = 73,
8619
    SYSZ_INS_JGH = 74,
8620
    SYSZ_INS_LOCH = 75,
8621
    SYSZ_INS_LOCGH = 76,
8622
    SYSZ_INS_LOCGRH = 77,
8623
    SYSZ_INS_LOCRH = 78,
8624
    SYSZ_INS_STOCH = 79,
8625
    SYSZ_INS_STOCGH = 80,
8626
    SYSZ_INS_CGIJNLH = 81,
8627
    SYSZ_INS_CGRJNLH = 82,
8628
    SYSZ_INS_CIJNLH = 83,
8629
    SYSZ_INS_CLGIJNLH = 84,
8630
    SYSZ_INS_CLGRJNLH = 85,
8631
    SYSZ_INS_CLIJNLH = 86,
8632
    SYSZ_INS_CLRJNLH = 87,
8633
    SYSZ_INS_CRJNLH = 88,
8634
    SYSZ_INS_CGIJE = 89,
8635
    SYSZ_INS_CGRJE = 90,
8636
    SYSZ_INS_CIJE = 91,
8637
    SYSZ_INS_CLGIJE = 92,
8638
    SYSZ_INS_CLGRJE = 93,
8639
    SYSZ_INS_CLIJE = 94,
8640
    SYSZ_INS_CLRJE = 95,
8641
    SYSZ_INS_CRJE = 96,
8642
    SYSZ_INS_CGIJNLE = 97,
8643
    SYSZ_INS_CGRJNLE = 98,
8644
    SYSZ_INS_CIJNLE = 99,
8645
    SYSZ_INS_CLGIJNLE = 100,
8646
    SYSZ_INS_CLGRJNLE = 101,
8647
    SYSZ_INS_CLIJNLE = 102,
8648
    SYSZ_INS_CLRJNLE = 103,
8649
    SYSZ_INS_CRJNLE = 104,
8650
    SYSZ_INS_CGIJH = 105,
8651
    SYSZ_INS_CGRJH = 106,
8652
    SYSZ_INS_CIJH = 107,
8653
    SYSZ_INS_CLGIJH = 108,
8654
    SYSZ_INS_CLGRJH = 109,
8655
    SYSZ_INS_CLIJH = 110,
8656
    SYSZ_INS_CLRJH = 111,
8657
    SYSZ_INS_CRJH = 112,
8658
    SYSZ_INS_CGIJNL = 113,
8659
    SYSZ_INS_CGRJNL = 114,
8660
    SYSZ_INS_CIJNL = 115,
8661
    SYSZ_INS_CLGIJNL = 116,
8662
    SYSZ_INS_CLGRJNL = 117,
8663
    SYSZ_INS_CLIJNL = 118,
8664
    SYSZ_INS_CLRJNL = 119,
8665
    SYSZ_INS_CRJNL = 120,
8666
    SYSZ_INS_CGIJHE = 121,
8667
    SYSZ_INS_CGRJHE = 122,
8668
    SYSZ_INS_CIJHE = 123,
8669
    SYSZ_INS_CLGIJHE = 124,
8670
    SYSZ_INS_CLGRJHE = 125,
8671
    SYSZ_INS_CLIJHE = 126,
8672
    SYSZ_INS_CLRJHE = 127,
8673
    SYSZ_INS_CRJHE = 128,
8674
    SYSZ_INS_CGIJNHE = 129,
8675
    SYSZ_INS_CGRJNHE = 130,
8676
    SYSZ_INS_CIJNHE = 131,
8677
    SYSZ_INS_CLGIJNHE = 132,
8678
    SYSZ_INS_CLGRJNHE = 133,
8679
    SYSZ_INS_CLIJNHE = 134,
8680
    SYSZ_INS_CLRJNHE = 135,
8681
    SYSZ_INS_CRJNHE = 136,
8682
    SYSZ_INS_CGIJL = 137,
8683
    SYSZ_INS_CGRJL = 138,
8684
    SYSZ_INS_CIJL = 139,
8685
    SYSZ_INS_CLGIJL = 140,
8686
    SYSZ_INS_CLGRJL = 141,
8687
    SYSZ_INS_CLIJL = 142,
8688
    SYSZ_INS_CLRJL = 143,
8689
    SYSZ_INS_CRJL = 144,
8690
    SYSZ_INS_CGIJNH = 145,
8691
    SYSZ_INS_CGRJNH = 146,
8692
    SYSZ_INS_CIJNH = 147,
8693
    SYSZ_INS_CLGIJNH = 148,
8694
    SYSZ_INS_CLGRJNH = 149,
8695
    SYSZ_INS_CLIJNH = 150,
8696
    SYSZ_INS_CLRJNH = 151,
8697
    SYSZ_INS_CRJNH = 152,
8698
    SYSZ_INS_CGIJLE = 153,
8699
    SYSZ_INS_CGRJLE = 154,
8700
    SYSZ_INS_CIJLE = 155,
8701
    SYSZ_INS_CLGIJLE = 156,
8702
    SYSZ_INS_CLGRJLE = 157,
8703
    SYSZ_INS_CLIJLE = 158,
8704
    SYSZ_INS_CLRJLE = 159,
8705
    SYSZ_INS_CRJLE = 160,
8706
    SYSZ_INS_CGIJNE = 161,
8707
    SYSZ_INS_CGRJNE = 162,
8708
    SYSZ_INS_CIJNE = 163,
8709
    SYSZ_INS_CLGIJNE = 164,
8710
    SYSZ_INS_CLGRJNE = 165,
8711
    SYSZ_INS_CLIJNE = 166,
8712
    SYSZ_INS_CLRJNE = 167,
8713
    SYSZ_INS_CRJNE = 168,
8714
    SYSZ_INS_CGIJLH = 169,
8715
    SYSZ_INS_CGRJLH = 170,
8716
    SYSZ_INS_CIJLH = 171,
8717
    SYSZ_INS_CLGIJLH = 172,
8718
    SYSZ_INS_CLGRJLH = 173,
8719
    SYSZ_INS_CLIJLH = 174,
8720
    SYSZ_INS_CLRJLH = 175,
8721
    SYSZ_INS_CRJLH = 176,
8722
    SYSZ_INS_BLR = 177,
8723
    SYSZ_INS_BLER = 178,
8724
    SYSZ_INS_JLE = 179,
8725
    SYSZ_INS_JGLE = 180,
8726
    SYSZ_INS_LOCLE = 181,
8727
    SYSZ_INS_LOCGLE = 182,
8728
    SYSZ_INS_LOCGRLE = 183,
8729
    SYSZ_INS_LOCRLE = 184,
8730
    SYSZ_INS_STOCLE = 185,
8731
    SYSZ_INS_STOCGLE = 186,
8732
    SYSZ_INS_BLHR = 187,
8733
    SYSZ_INS_JLH = 188,
8734
    SYSZ_INS_JGLH = 189,
8735
    SYSZ_INS_LOCLH = 190,
8736
    SYSZ_INS_LOCGLH = 191,
8737
    SYSZ_INS_LOCGRLH = 192,
8738
    SYSZ_INS_LOCRLH = 193,
8739
    SYSZ_INS_STOCLH = 194,
8740
    SYSZ_INS_STOCGLH = 195,
8741
    SYSZ_INS_JL = 196,
8742
    SYSZ_INS_JGL = 197,
8743
    SYSZ_INS_LOCL = 198,
8744
    SYSZ_INS_LOCGL = 199,
8745
    SYSZ_INS_LOCGRL = 200,
8746
    SYSZ_INS_LOCRL = 201,
8747
    SYSZ_INS_LOC = 202,
8748
    SYSZ_INS_LOCG = 203,
8749
    SYSZ_INS_LOCGR = 204,
8750
    SYSZ_INS_LOCR = 205,
8751
    SYSZ_INS_STOCL = 206,
8752
    SYSZ_INS_STOCGL = 207,
8753
    SYSZ_INS_BNER = 208,
8754
    SYSZ_INS_JNE = 209,
8755
    SYSZ_INS_JGNE = 210,
8756
    SYSZ_INS_LOCNE = 211,
8757
    SYSZ_INS_LOCGNE = 212,
8758
    SYSZ_INS_LOCGRNE = 213,
8759
    SYSZ_INS_LOCRNE = 214,
8760
    SYSZ_INS_STOCNE = 215,
8761
    SYSZ_INS_STOCGNE = 216,
8762
    SYSZ_INS_BNHR = 217,
8763
    SYSZ_INS_BNHER = 218,
8764
    SYSZ_INS_JNHE = 219,
8765
    SYSZ_INS_JGNHE = 220,
8766
    SYSZ_INS_LOCNHE = 221,
8767
    SYSZ_INS_LOCGNHE = 222,
8768
    SYSZ_INS_LOCGRNHE = 223,
8769
    SYSZ_INS_LOCRNHE = 224,
8770
    SYSZ_INS_STOCNHE = 225,
8771
    SYSZ_INS_STOCGNHE = 226,
8772
    SYSZ_INS_JNH = 227,
8773
    SYSZ_INS_JGNH = 228,
8774
    SYSZ_INS_LOCNH = 229,
8775
    SYSZ_INS_LOCGNH = 230,
8776
    SYSZ_INS_LOCGRNH = 231,
8777
    SYSZ_INS_LOCRNH = 232,
8778
    SYSZ_INS_STOCNH = 233,
8779
    SYSZ_INS_STOCGNH = 234,
8780
    SYSZ_INS_BNLR = 235,
8781
    SYSZ_INS_BNLER = 236,
8782
    SYSZ_INS_JNLE = 237,
8783
    SYSZ_INS_JGNLE = 238,
8784
    SYSZ_INS_LOCNLE = 239,
8785
    SYSZ_INS_LOCGNLE = 240,
8786
    SYSZ_INS_LOCGRNLE = 241,
8787
    SYSZ_INS_LOCRNLE = 242,
8788
    SYSZ_INS_STOCNLE = 243,
8789
    SYSZ_INS_STOCGNLE = 244,
8790
    SYSZ_INS_BNLHR = 245,
8791
    SYSZ_INS_JNLH = 246,
8792
    SYSZ_INS_JGNLH = 247,
8793
    SYSZ_INS_LOCNLH = 248,
8794
    SYSZ_INS_LOCGNLH = 249,
8795
    SYSZ_INS_LOCGRNLH = 250,
8796
    SYSZ_INS_LOCRNLH = 251,
8797
    SYSZ_INS_STOCNLH = 252,
8798
    SYSZ_INS_STOCGNLH = 253,
8799
    SYSZ_INS_JNL = 254,
8800
    SYSZ_INS_JGNL = 255,
8801
    SYSZ_INS_LOCNL = 256,
8802
    SYSZ_INS_LOCGNL = 257,
8803
    SYSZ_INS_LOCGRNL = 258,
8804
    SYSZ_INS_LOCRNL = 259,
8805
    SYSZ_INS_STOCNL = 260,
8806
    SYSZ_INS_STOCGNL = 261,
8807
    SYSZ_INS_BNOR = 262,
8808
    SYSZ_INS_JNO = 263,
8809
    SYSZ_INS_JGNO = 264,
8810
    SYSZ_INS_LOCNO = 265,
8811
    SYSZ_INS_LOCGNO = 266,
8812
    SYSZ_INS_LOCGRNO = 267,
8813
    SYSZ_INS_LOCRNO = 268,
8814
    SYSZ_INS_STOCNO = 269,
8815
    SYSZ_INS_STOCGNO = 270,
8816
    SYSZ_INS_BOR = 271,
8817
    SYSZ_INS_JO = 272,
8818
    SYSZ_INS_JGO = 273,
8819
    SYSZ_INS_LOCO = 274,
8820
    SYSZ_INS_LOCGO = 275,
8821
    SYSZ_INS_LOCGRO = 276,
8822
    SYSZ_INS_LOCRO = 277,
8823
    SYSZ_INS_STOCO = 278,
8824
    SYSZ_INS_STOCGO = 279,
8825
    SYSZ_INS_STOC = 280,
8826
    SYSZ_INS_STOCG = 281,
8827
    SYSZ_INS_BASR = 282,
8828
    SYSZ_INS_BR = 283,
8829
    SYSZ_INS_BRAS = 284,
8830
    SYSZ_INS_BRASL = 285,
8831
    SYSZ_INS_J = 286,
8832
    SYSZ_INS_JG = 287,
8833
    SYSZ_INS_BRCT = 288,
8834
    SYSZ_INS_BRCTG = 289,
8835
    SYSZ_INS_C = 290,
8836
    SYSZ_INS_CDB = 291,
8837
    SYSZ_INS_CDBR = 292,
8838
    SYSZ_INS_CDFBR = 293,
8839
    SYSZ_INS_CDGBR = 294,
8840
    SYSZ_INS_CDLFBR = 295,
8841
    SYSZ_INS_CDLGBR = 296,
8842
    SYSZ_INS_CEB = 297,
8843
    SYSZ_INS_CEBR = 298,
8844
    SYSZ_INS_CEFBR = 299,
8845
    SYSZ_INS_CEGBR = 300,
8846
    SYSZ_INS_CELFBR = 301,
8847
    SYSZ_INS_CELGBR = 302,
8848
    SYSZ_INS_CFDBR = 303,
8849
    SYSZ_INS_CFEBR = 304,
8850
    SYSZ_INS_CFI = 305,
8851
    SYSZ_INS_CFXBR = 306,
8852
    SYSZ_INS_CG = 307,
8853
    SYSZ_INS_CGDBR = 308,
8854
    SYSZ_INS_CGEBR = 309,
8855
    SYSZ_INS_CGF = 310,
8856
    SYSZ_INS_CGFI = 311,
8857
    SYSZ_INS_CGFR = 312,
8858
    SYSZ_INS_CGFRL = 313,
8859
    SYSZ_INS_CGH = 314,
8860
    SYSZ_INS_CGHI = 315,
8861
    SYSZ_INS_CGHRL = 316,
8862
    SYSZ_INS_CGHSI = 317,
8863
    SYSZ_INS_CGR = 318,
8864
    SYSZ_INS_CGRL = 319,
8865
    SYSZ_INS_CGXBR = 320,
8866
    SYSZ_INS_CH = 321,
8867
    SYSZ_INS_CHF = 322,
8868
    SYSZ_INS_CHHSI = 323,
8869
    SYSZ_INS_CHI = 324,
8870
    SYSZ_INS_CHRL = 325,
8871
    SYSZ_INS_CHSI = 326,
8872
    SYSZ_INS_CHY = 327,
8873
    SYSZ_INS_CIH = 328,
8874
    SYSZ_INS_CL = 329,
8875
    SYSZ_INS_CLC = 330,
8876
    SYSZ_INS_CLFDBR = 331,
8877
    SYSZ_INS_CLFEBR = 332,
8878
    SYSZ_INS_CLFHSI = 333,
8879
    SYSZ_INS_CLFI = 334,
8880
    SYSZ_INS_CLFXBR = 335,
8881
    SYSZ_INS_CLG = 336,
8882
    SYSZ_INS_CLGDBR = 337,
8883
    SYSZ_INS_CLGEBR = 338,
8884
    SYSZ_INS_CLGF = 339,
8885
    SYSZ_INS_CLGFI = 340,
8886
    SYSZ_INS_CLGFR = 341,
8887
    SYSZ_INS_CLGFRL = 342,
8888
    SYSZ_INS_CLGHRL = 343,
8889
    SYSZ_INS_CLGHSI = 344,
8890
    SYSZ_INS_CLGR = 345,
8891
    SYSZ_INS_CLGRL = 346,
8892
    SYSZ_INS_CLGXBR = 347,
8893
    SYSZ_INS_CLHF = 348,
8894
    SYSZ_INS_CLHHSI = 349,
8895
    SYSZ_INS_CLHRL = 350,
8896
    SYSZ_INS_CLI = 351,
8897
    SYSZ_INS_CLIH = 352,
8898
    SYSZ_INS_CLIY = 353,
8899
    SYSZ_INS_CLR = 354,
8900
    SYSZ_INS_CLRL = 355,
8901
    SYSZ_INS_CLST = 356,
8902
    SYSZ_INS_CLY = 357,
8903
    SYSZ_INS_CPSDR = 358,
8904
    SYSZ_INS_CR = 359,
8905
    SYSZ_INS_CRL = 360,
8906
    SYSZ_INS_CS = 361,
8907
    SYSZ_INS_CSG = 362,
8908
    SYSZ_INS_CSY = 363,
8909
    SYSZ_INS_CXBR = 364,
8910
    SYSZ_INS_CXFBR = 365,
8911
    SYSZ_INS_CXGBR = 366,
8912
    SYSZ_INS_CXLFBR = 367,
8913
    SYSZ_INS_CXLGBR = 368,
8914
    SYSZ_INS_CY = 369,
8915
    SYSZ_INS_DDB = 370,
8916
    SYSZ_INS_DDBR = 371,
8917
    SYSZ_INS_DEB = 372,
8918
    SYSZ_INS_DEBR = 373,
8919
    SYSZ_INS_DL = 374,
8920
    SYSZ_INS_DLG = 375,
8921
    SYSZ_INS_DLGR = 376,
8922
    SYSZ_INS_DLR = 377,
8923
    SYSZ_INS_DSG = 378,
8924
    SYSZ_INS_DSGF = 379,
8925
    SYSZ_INS_DSGFR = 380,
8926
    SYSZ_INS_DSGR = 381,
8927
    SYSZ_INS_DXBR = 382,
8928
    SYSZ_INS_EAR = 383,
8929
    SYSZ_INS_FIDBR = 384,
8930
    SYSZ_INS_FIDBRA = 385,
8931
    SYSZ_INS_FIEBR = 386,
8932
    SYSZ_INS_FIEBRA = 387,
8933
    SYSZ_INS_FIXBR = 388,
8934
    SYSZ_INS_FIXBRA = 389,
8935
    SYSZ_INS_FLOGR = 390,
8936
    SYSZ_INS_IC = 391,
8937
    SYSZ_INS_ICY = 392,
8938
    SYSZ_INS_IIHF = 393,
8939
    SYSZ_INS_IIHH = 394,
8940
    SYSZ_INS_IIHL = 395,
8941
    SYSZ_INS_IILF = 396,
8942
    SYSZ_INS_IILH = 397,
8943
    SYSZ_INS_IILL = 398,
8944
    SYSZ_INS_IPM = 399,
8945
    SYSZ_INS_L = 400,
8946
    SYSZ_INS_LA = 401,
8947
    SYSZ_INS_LAA = 402,
8948
    SYSZ_INS_LAAG = 403,
8949
    SYSZ_INS_LAAL = 404,
8950
    SYSZ_INS_LAALG = 405,
8951
    SYSZ_INS_LAN = 406,
8952
    SYSZ_INS_LANG = 407,
8953
    SYSZ_INS_LAO = 408,
8954
    SYSZ_INS_LAOG = 409,
8955
    SYSZ_INS_LARL = 410,
8956
    SYSZ_INS_LAX = 411,
8957
    SYSZ_INS_LAXG = 412,
8958
    SYSZ_INS_LAY = 413,
8959
    SYSZ_INS_LB = 414,
8960
    SYSZ_INS_LBH = 415,
8961
    SYSZ_INS_LBR = 416,
8962
    SYSZ_INS_LCDBR = 417,
8963
    SYSZ_INS_LCEBR = 418,
8964
    SYSZ_INS_LCGFR = 419,
8965
    SYSZ_INS_LCGR = 420,
8966
    SYSZ_INS_LCR = 421,
8967
    SYSZ_INS_LCXBR = 422,
8968
    SYSZ_INS_LD = 423,
8969
    SYSZ_INS_LDEB = 424,
8970
    SYSZ_INS_LDEBR = 425,
8971
    SYSZ_INS_LDGR = 426,
8972
    SYSZ_INS_LDR = 427,
8973
    SYSZ_INS_LDXBR = 428,
8974
    SYSZ_INS_LDXBRA = 429,
8975
    SYSZ_INS_LDY = 430,
8976
    SYSZ_INS_LE = 431,
8977
    SYSZ_INS_LEDBR = 432,
8978
    SYSZ_INS_LEDBRA = 433,
8979
    SYSZ_INS_LER = 434,
8980
    SYSZ_INS_LEXBR = 435,
8981
    SYSZ_INS_LEXBRA = 436,
8982
    SYSZ_INS_LEY = 437,
8983
    SYSZ_INS_LFH = 438,
8984
    SYSZ_INS_LG = 439,
8985
    SYSZ_INS_LGB = 440,
8986
    SYSZ_INS_LGBR = 441,
8987
    SYSZ_INS_LGDR = 442,
8988
    SYSZ_INS_LGF = 443,
8989
    SYSZ_INS_LGFI = 444,
8990
    SYSZ_INS_LGFR = 445,
8991
    SYSZ_INS_LGFRL = 446,
8992
    SYSZ_INS_LGH = 447,
8993
    SYSZ_INS_LGHI = 448,
8994
    SYSZ_INS_LGHR = 449,
8995
    SYSZ_INS_LGHRL = 450,
8996
    SYSZ_INS_LGR = 451,
8997
    SYSZ_INS_LGRL = 452,
8998
    SYSZ_INS_LH = 453,
8999
    SYSZ_INS_LHH = 454,
9000
    SYSZ_INS_LHI = 455,
9001
    SYSZ_INS_LHR = 456,
9002
    SYSZ_INS_LHRL = 457,
9003
    SYSZ_INS_LHY = 458,
9004
    SYSZ_INS_LLC = 459,
9005
    SYSZ_INS_LLCH = 460,
9006
    SYSZ_INS_LLCR = 461,
9007
    SYSZ_INS_LLGC = 462,
9008
    SYSZ_INS_LLGCR = 463,
9009
    SYSZ_INS_LLGF = 464,
9010
    SYSZ_INS_LLGFR = 465,
9011
    SYSZ_INS_LLGFRL = 466,
9012
    SYSZ_INS_LLGH = 467,
9013
    SYSZ_INS_LLGHR = 468,
9014
    SYSZ_INS_LLGHRL = 469,
9015
    SYSZ_INS_LLH = 470,
9016
    SYSZ_INS_LLHH = 471,
9017
    SYSZ_INS_LLHR = 472,
9018
    SYSZ_INS_LLHRL = 473,
9019
    SYSZ_INS_LLIHF = 474,
9020
    SYSZ_INS_LLIHH = 475,
9021
    SYSZ_INS_LLIHL = 476,
9022
    SYSZ_INS_LLILF = 477,
9023
    SYSZ_INS_LLILH = 478,
9024
    SYSZ_INS_LLILL = 479,
9025
    SYSZ_INS_LMG = 480,
9026
    SYSZ_INS_LNDBR = 481,
9027
    SYSZ_INS_LNEBR = 482,
9028
    SYSZ_INS_LNGFR = 483,
9029
    SYSZ_INS_LNGR = 484,
9030
    SYSZ_INS_LNR = 485,
9031
    SYSZ_INS_LNXBR = 486,
9032
    SYSZ_INS_LPDBR = 487,
9033
    SYSZ_INS_LPEBR = 488,
9034
    SYSZ_INS_LPGFR = 489,
9035
    SYSZ_INS_LPGR = 490,
9036
    SYSZ_INS_LPR = 491,
9037
    SYSZ_INS_LPXBR = 492,
9038
    SYSZ_INS_LR = 493,
9039
    SYSZ_INS_LRL = 494,
9040
    SYSZ_INS_LRV = 495,
9041
    SYSZ_INS_LRVG = 496,
9042
    SYSZ_INS_LRVGR = 497,
9043
    SYSZ_INS_LRVR = 498,
9044
    SYSZ_INS_LT = 499,
9045
    SYSZ_INS_LTDBR = 500,
9046
    SYSZ_INS_LTEBR = 501,
9047
    SYSZ_INS_LTG = 502,
9048
    SYSZ_INS_LTGF = 503,
9049
    SYSZ_INS_LTGFR = 504,
9050
    SYSZ_INS_LTGR = 505,
9051
    SYSZ_INS_LTR = 506,
9052
    SYSZ_INS_LTXBR = 507,
9053
    SYSZ_INS_LXDB = 508,
9054
    SYSZ_INS_LXDBR = 509,
9055
    SYSZ_INS_LXEB = 510,
9056
    SYSZ_INS_LXEBR = 511,
9057
    SYSZ_INS_LXR = 512,
9058
    SYSZ_INS_LY = 513,
9059
    SYSZ_INS_LZDR = 514,
9060
    SYSZ_INS_LZER = 515,
9061
    SYSZ_INS_LZXR = 516,
9062
    SYSZ_INS_MADB = 517,
9063
    SYSZ_INS_MADBR = 518,
9064
    SYSZ_INS_MAEB = 519,
9065
    SYSZ_INS_MAEBR = 520,
9066
    SYSZ_INS_MDB = 521,
9067
    SYSZ_INS_MDBR = 522,
9068
    SYSZ_INS_MDEB = 523,
9069
    SYSZ_INS_MDEBR = 524,
9070
    SYSZ_INS_MEEB = 525,
9071
    SYSZ_INS_MEEBR = 526,
9072
    SYSZ_INS_MGHI = 527,
9073
    SYSZ_INS_MH = 528,
9074
    SYSZ_INS_MHI = 529,
9075
    SYSZ_INS_MHY = 530,
9076
    SYSZ_INS_MLG = 531,
9077
    SYSZ_INS_MLGR = 532,
9078
    SYSZ_INS_MS = 533,
9079
    SYSZ_INS_MSDB = 534,
9080
    SYSZ_INS_MSDBR = 535,
9081
    SYSZ_INS_MSEB = 536,
9082
    SYSZ_INS_MSEBR = 537,
9083
    SYSZ_INS_MSFI = 538,
9084
    SYSZ_INS_MSG = 539,
9085
    SYSZ_INS_MSGF = 540,
9086
    SYSZ_INS_MSGFI = 541,
9087
    SYSZ_INS_MSGFR = 542,
9088
    SYSZ_INS_MSGR = 543,
9089
    SYSZ_INS_MSR = 544,
9090
    SYSZ_INS_MSY = 545,
9091
    SYSZ_INS_MVC = 546,
9092
    SYSZ_INS_MVGHI = 547,
9093
    SYSZ_INS_MVHHI = 548,
9094
    SYSZ_INS_MVHI = 549,
9095
    SYSZ_INS_MVI = 550,
9096
    SYSZ_INS_MVIY = 551,
9097
    SYSZ_INS_MVST = 552,
9098
    SYSZ_INS_MXBR = 553,
9099
    SYSZ_INS_MXDB = 554,
9100
    SYSZ_INS_MXDBR = 555,
9101
    SYSZ_INS_N = 556,
9102
    SYSZ_INS_NC = 557,
9103
    SYSZ_INS_NG = 558,
9104
    SYSZ_INS_NGR = 559,
9105
    SYSZ_INS_NGRK = 560,
9106
    SYSZ_INS_NI = 561,
9107
    SYSZ_INS_NIHF = 562,
9108
    SYSZ_INS_NIHH = 563,
9109
    SYSZ_INS_NIHL = 564,
9110
    SYSZ_INS_NILF = 565,
9111
    SYSZ_INS_NILH = 566,
9112
    SYSZ_INS_NILL = 567,
9113
    SYSZ_INS_NIY = 568,
9114
    SYSZ_INS_NR = 569,
9115
    SYSZ_INS_NRK = 570,
9116
    SYSZ_INS_NY = 571,
9117
    SYSZ_INS_O = 572,
9118
    SYSZ_INS_OC = 573,
9119
    SYSZ_INS_OG = 574,
9120
    SYSZ_INS_OGR = 575,
9121
    SYSZ_INS_OGRK = 576,
9122
    SYSZ_INS_OI = 577,
9123
    SYSZ_INS_OIHF = 578,
9124
    SYSZ_INS_OIHH = 579,
9125
    SYSZ_INS_OIHL = 580,
9126
    SYSZ_INS_OILF = 581,
9127
    SYSZ_INS_OILH = 582,
9128
    SYSZ_INS_OILL = 583,
9129
    SYSZ_INS_OIY = 584,
9130
    SYSZ_INS_OR = 585,
9131
    SYSZ_INS_ORK = 586,
9132
    SYSZ_INS_OY = 587,
9133
    SYSZ_INS_PFD = 588,
9134
    SYSZ_INS_PFDRL = 589,
9135
    SYSZ_INS_RISBG = 590,
9136
    SYSZ_INS_RISBHG = 591,
9137
    SYSZ_INS_RISBLG = 592,
9138
    SYSZ_INS_RLL = 593,
9139
    SYSZ_INS_RLLG = 594,
9140
    SYSZ_INS_RNSBG = 595,
9141
    SYSZ_INS_ROSBG = 596,
9142
    SYSZ_INS_RXSBG = 597,
9143
    SYSZ_INS_S = 598,
9144
    SYSZ_INS_SDB = 599,
9145
    SYSZ_INS_SDBR = 600,
9146
    SYSZ_INS_SEB = 601,
9147
    SYSZ_INS_SEBR = 602,
9148
    SYSZ_INS_SG = 603,
9149
    SYSZ_INS_SGF = 604,
9150
    SYSZ_INS_SGFR = 605,
9151
    SYSZ_INS_SGR = 606,
9152
    SYSZ_INS_SGRK = 607,
9153
    SYSZ_INS_SH = 608,
9154
    SYSZ_INS_SHY = 609,
9155
    SYSZ_INS_SL = 610,
9156
    SYSZ_INS_SLB = 611,
9157
    SYSZ_INS_SLBG = 612,
9158
    SYSZ_INS_SLBR = 613,
9159
    SYSZ_INS_SLFI = 614,
9160
    SYSZ_INS_SLG = 615,
9161
    SYSZ_INS_SLBGR = 616,
9162
    SYSZ_INS_SLGF = 617,
9163
    SYSZ_INS_SLGFI = 618,
9164
    SYSZ_INS_SLGFR = 619,
9165
    SYSZ_INS_SLGR = 620,
9166
    SYSZ_INS_SLGRK = 621,
9167
    SYSZ_INS_SLL = 622,
9168
    SYSZ_INS_SLLG = 623,
9169
    SYSZ_INS_SLLK = 624,
9170
    SYSZ_INS_SLR = 625,
9171
    SYSZ_INS_SLRK = 626,
9172
    SYSZ_INS_SLY = 627,
9173
    SYSZ_INS_SQDB = 628,
9174
    SYSZ_INS_SQDBR = 629,
9175
    SYSZ_INS_SQEB = 630,
9176
    SYSZ_INS_SQEBR = 631,
9177
    SYSZ_INS_SQXBR = 632,
9178
    SYSZ_INS_SR = 633,
9179
    SYSZ_INS_SRA = 634,
9180
    SYSZ_INS_SRAG = 635,
9181
    SYSZ_INS_SRAK = 636,
9182
    SYSZ_INS_SRK = 637,
9183
    SYSZ_INS_SRL = 638,
9184
    SYSZ_INS_SRLG = 639,
9185
    SYSZ_INS_SRLK = 640,
9186
    SYSZ_INS_SRST = 641,
9187
    SYSZ_INS_ST = 642,
9188
    SYSZ_INS_STC = 643,
9189
    SYSZ_INS_STCH = 644,
9190
    SYSZ_INS_STCY = 645,
9191
    SYSZ_INS_STD = 646,
9192
    SYSZ_INS_STDY = 647,
9193
    SYSZ_INS_STE = 648,
9194
    SYSZ_INS_STEY = 649,
9195
    SYSZ_INS_STFH = 650,
9196
    SYSZ_INS_STG = 651,
9197
    SYSZ_INS_STGRL = 652,
9198
    SYSZ_INS_STH = 653,
9199
    SYSZ_INS_STHH = 654,
9200
    SYSZ_INS_STHRL = 655,
9201
    SYSZ_INS_STHY = 656,
9202
    SYSZ_INS_STMG = 657,
9203
    SYSZ_INS_STRL = 658,
9204
    SYSZ_INS_STRV = 659,
9205
    SYSZ_INS_STRVG = 660,
9206
    SYSZ_INS_STY = 661,
9207
    SYSZ_INS_SXBR = 662,
9208
    SYSZ_INS_SY = 663,
9209
    SYSZ_INS_TM = 664,
9210
    SYSZ_INS_TMHH = 665,
9211
    SYSZ_INS_TMHL = 666,
9212
    SYSZ_INS_TMLH = 667,
9213
    SYSZ_INS_TMLL = 668,
9214
    SYSZ_INS_TMY = 669,
9215
    SYSZ_INS_X = 670,
9216
    SYSZ_INS_XC = 671,
9217
    SYSZ_INS_XG = 672,
9218
    SYSZ_INS_XGR = 673,
9219
    SYSZ_INS_XGRK = 674,
9220
    SYSZ_INS_XI = 675,
9221
    SYSZ_INS_XIHF = 676,
9222
    SYSZ_INS_XILF = 677,
9223
    SYSZ_INS_XIY = 678,
9224
    SYSZ_INS_XR = 679,
9225
    SYSZ_INS_XRK = 680,
9226
    SYSZ_INS_XY = 681,
9227
    SYSZ_INS_AD = 682,
9228
    SYSZ_INS_ADR = 683,
9229
    SYSZ_INS_ADTR = 684,
9230
    SYSZ_INS_ADTRA = 685,
9231
    SYSZ_INS_AE = 686,
9232
    SYSZ_INS_AER = 687,
9233
    SYSZ_INS_AGH = 688,
9234
    SYSZ_INS_AHHHR = 689,
9235
    SYSZ_INS_AHHLR = 690,
9236
    SYSZ_INS_ALGSI = 691,
9237
    SYSZ_INS_ALHHHR = 692,
9238
    SYSZ_INS_ALHHLR = 693,
9239
    SYSZ_INS_ALSI = 694,
9240
    SYSZ_INS_ALSIH = 695,
9241
    SYSZ_INS_ALSIHN = 696,
9242
    SYSZ_INS_AP = 697,
9243
    SYSZ_INS_AU = 698,
9244
    SYSZ_INS_AUR = 699,
9245
    SYSZ_INS_AW = 700,
9246
    SYSZ_INS_AWR = 701,
9247
    SYSZ_INS_AXR = 702,
9248
    SYSZ_INS_AXTR = 703,
9249
    SYSZ_INS_AXTRA = 704,
9250
    SYSZ_INS_B = 705,
9251
    SYSZ_INS_BAKR = 706,
9252
    SYSZ_INS_BAL = 707,
9253
    SYSZ_INS_BALR = 708,
9254
    SYSZ_INS_BAS = 709,
9255
    SYSZ_INS_BASSM = 710,
9256
    SYSZ_INS_BC = 711,
9257
    SYSZ_INS_BCT = 712,
9258
    SYSZ_INS_BCTG = 713,
9259
    SYSZ_INS_BCTGR = 714,
9260
    SYSZ_INS_BCTR = 715,
9261
    SYSZ_INS_BE = 716,
9262
    SYSZ_INS_BH = 717,
9263
    SYSZ_INS_BHE = 718,
9264
    SYSZ_INS_BI = 719,
9265
    SYSZ_INS_BIC = 720,
9266
    SYSZ_INS_BIE = 721,
9267
    SYSZ_INS_BIH = 722,
9268
    SYSZ_INS_BIHE = 723,
9269
    SYSZ_INS_BIL = 724,
9270
    SYSZ_INS_BILE = 725,
9271
    SYSZ_INS_BILH = 726,
9272
    SYSZ_INS_BIM = 727,
9273
    SYSZ_INS_BINE = 728,
9274
    SYSZ_INS_BINH = 729,
9275
    SYSZ_INS_BINHE = 730,
9276
    SYSZ_INS_BINL = 731,
9277
    SYSZ_INS_BINLE = 732,
9278
    SYSZ_INS_BINLH = 733,
9279
    SYSZ_INS_BINM = 734,
9280
    SYSZ_INS_BINO = 735,
9281
    SYSZ_INS_BINP = 736,
9282
    SYSZ_INS_BINZ = 737,
9283
    SYSZ_INS_BIO = 738,
9284
    SYSZ_INS_BIP = 739,
9285
    SYSZ_INS_BIZ = 740,
9286
    SYSZ_INS_BL = 741,
9287
    SYSZ_INS_BLE = 742,
9288
    SYSZ_INS_BLH = 743,
9289
    SYSZ_INS_BM = 744,
9290
    SYSZ_INS_BMR = 745,
9291
    SYSZ_INS_BNE = 746,
9292
    SYSZ_INS_BNH = 747,
9293
    SYSZ_INS_BNHE = 748,
9294
    SYSZ_INS_BNL = 749,
9295
    SYSZ_INS_BNLE = 750,
9296
    SYSZ_INS_BNLH = 751,
9297
    SYSZ_INS_BNM = 752,
9298
    SYSZ_INS_BNMR = 753,
9299
    SYSZ_INS_BNO = 754,
9300
    SYSZ_INS_BNP = 755,
9301
    SYSZ_INS_BNPR = 756,
9302
    SYSZ_INS_BNZ = 757,
9303
    SYSZ_INS_BNZR = 758,
9304
    SYSZ_INS_BO = 759,
9305
    SYSZ_INS_BP = 760,
9306
    SYSZ_INS_BPP = 761,
9307
    SYSZ_INS_BPR = 762,
9308
    SYSZ_INS_BPRP = 763,
9309
    SYSZ_INS_BRCTH = 764,
9310
    SYSZ_INS_BRXH = 765,
9311
    SYSZ_INS_BRXHG = 766,
9312
    SYSZ_INS_BRXLE = 767,
9313
    SYSZ_INS_BRXLG = 768,
9314
    SYSZ_INS_BSA = 769,
9315
    SYSZ_INS_BSG = 770,
9316
    SYSZ_INS_BSM = 771,
9317
    SYSZ_INS_BXH = 772,
9318
    SYSZ_INS_BXHG = 773,
9319
    SYSZ_INS_BXLE = 774,
9320
    SYSZ_INS_BXLEG = 775,
9321
    SYSZ_INS_BZ = 776,
9322
    SYSZ_INS_BZR = 777,
9323
    SYSZ_INS_CD = 778,
9324
    SYSZ_INS_CDFBRA = 779,
9325
    SYSZ_INS_CDFR = 780,
9326
    SYSZ_INS_CDFTR = 781,
9327
    SYSZ_INS_CDGBRA = 782,
9328
    SYSZ_INS_CDGR = 783,
9329
    SYSZ_INS_CDGTR = 784,
9330
    SYSZ_INS_CDGTRA = 785,
9331
    SYSZ_INS_CDLFTR = 786,
9332
    SYSZ_INS_CDLGTR = 787,
9333
    SYSZ_INS_CDPT = 788,
9334
    SYSZ_INS_CDR = 789,
9335
    SYSZ_INS_CDS = 790,
9336
    SYSZ_INS_CDSG = 791,
9337
    SYSZ_INS_CDSTR = 792,
9338
    SYSZ_INS_CDSY = 793,
9339
    SYSZ_INS_CDTR = 794,
9340
    SYSZ_INS_CDUTR = 795,
9341
    SYSZ_INS_CDZT = 796,
9342
    SYSZ_INS_CE = 797,
9343
    SYSZ_INS_CEDTR = 798,
9344
    SYSZ_INS_CEFBRA = 799,
9345
    SYSZ_INS_CEFR = 800,
9346
    SYSZ_INS_CEGBRA = 801,
9347
    SYSZ_INS_CEGR = 802,
9348
    SYSZ_INS_CER = 803,
9349
    SYSZ_INS_CEXTR = 804,
9350
    SYSZ_INS_CFC = 805,
9351
    SYSZ_INS_CFDBRA = 806,
9352
    SYSZ_INS_CFDR = 807,
9353
    SYSZ_INS_CFDTR = 808,
9354
    SYSZ_INS_CFEBRA = 809,
9355
    SYSZ_INS_CFER = 810,
9356
    SYSZ_INS_CFXBRA = 811,
9357
    SYSZ_INS_CFXR = 812,
9358
    SYSZ_INS_CFXTR = 813,
9359
    SYSZ_INS_CGDBRA = 814,
9360
    SYSZ_INS_CGDR = 815,
9361
    SYSZ_INS_CGDTR = 816,
9362
    SYSZ_INS_CGDTRA = 817,
9363
    SYSZ_INS_CGEBRA = 818,
9364
    SYSZ_INS_CGER = 819,
9365
    SYSZ_INS_CGIB = 820,
9366
    SYSZ_INS_CGIBE = 821,
9367
    SYSZ_INS_CGIBH = 822,
9368
    SYSZ_INS_CGIBHE = 823,
9369
    SYSZ_INS_CGIBL = 824,
9370
    SYSZ_INS_CGIBLE = 825,
9371
    SYSZ_INS_CGIBLH = 826,
9372
    SYSZ_INS_CGIBNE = 827,
9373
    SYSZ_INS_CGIBNH = 828,
9374
    SYSZ_INS_CGIBNHE = 829,
9375
    SYSZ_INS_CGIBNL = 830,
9376
    SYSZ_INS_CGIBNLE = 831,
9377
    SYSZ_INS_CGIBNLH = 832,
9378
    SYSZ_INS_CGIT = 833,
9379
    SYSZ_INS_CGITE = 834,
9380
    SYSZ_INS_CGITH = 835,
9381
    SYSZ_INS_CGITHE = 836,
9382
    SYSZ_INS_CGITL = 837,
9383
    SYSZ_INS_CGITLE = 838,
9384
    SYSZ_INS_CGITLH = 839,
9385
    SYSZ_INS_CGITNE = 840,
9386
    SYSZ_INS_CGITNH = 841,
9387
    SYSZ_INS_CGITNHE = 842,
9388
    SYSZ_INS_CGITNL = 843,
9389
    SYSZ_INS_CGITNLE = 844,
9390
    SYSZ_INS_CGITNLH = 845,
9391
    SYSZ_INS_CGRB = 846,
9392
    SYSZ_INS_CGRBE = 847,
9393
    SYSZ_INS_CGRBH = 848,
9394
    SYSZ_INS_CGRBHE = 849,
9395
    SYSZ_INS_CGRBL = 850,
9396
    SYSZ_INS_CGRBLE = 851,
9397
    SYSZ_INS_CGRBLH = 852,
9398
    SYSZ_INS_CGRBNE = 853,
9399
    SYSZ_INS_CGRBNH = 854,
9400
    SYSZ_INS_CGRBNHE = 855,
9401
    SYSZ_INS_CGRBNL = 856,
9402
    SYSZ_INS_CGRBNLE = 857,
9403
    SYSZ_INS_CGRBNLH = 858,
9404
    SYSZ_INS_CGRT = 859,
9405
    SYSZ_INS_CGRTE = 860,
9406
    SYSZ_INS_CGRTH = 861,
9407
    SYSZ_INS_CGRTHE = 862,
9408
    SYSZ_INS_CGRTL = 863,
9409
    SYSZ_INS_CGRTLE = 864,
9410
    SYSZ_INS_CGRTLH = 865,
9411
    SYSZ_INS_CGRTNE = 866,
9412
    SYSZ_INS_CGRTNH = 867,
9413
    SYSZ_INS_CGRTNHE = 868,
9414
    SYSZ_INS_CGRTNL = 869,
9415
    SYSZ_INS_CGRTNLE = 870,
9416
    SYSZ_INS_CGRTNLH = 871,
9417
    SYSZ_INS_CGXBRA = 872,
9418
    SYSZ_INS_CGXR = 873,
9419
    SYSZ_INS_CGXTR = 874,
9420
    SYSZ_INS_CGXTRA = 875,
9421
    SYSZ_INS_CHHR = 876,
9422
    SYSZ_INS_CHLR = 877,
9423
    SYSZ_INS_CIB = 878,
9424
    SYSZ_INS_CIBE = 879,
9425
    SYSZ_INS_CIBH = 880,
9426
    SYSZ_INS_CIBHE = 881,
9427
    SYSZ_INS_CIBL = 882,
9428
    SYSZ_INS_CIBLE = 883,
9429
    SYSZ_INS_CIBLH = 884,
9430
    SYSZ_INS_CIBNE = 885,
9431
    SYSZ_INS_CIBNH = 886,
9432
    SYSZ_INS_CIBNHE = 887,
9433
    SYSZ_INS_CIBNL = 888,
9434
    SYSZ_INS_CIBNLE = 889,
9435
    SYSZ_INS_CIBNLH = 890,
9436
    SYSZ_INS_CIT = 891,
9437
    SYSZ_INS_CITE = 892,
9438
    SYSZ_INS_CITH = 893,
9439
    SYSZ_INS_CITHE = 894,
9440
    SYSZ_INS_CITL = 895,
9441
    SYSZ_INS_CITLE = 896,
9442
    SYSZ_INS_CITLH = 897,
9443
    SYSZ_INS_CITNE = 898,
9444
    SYSZ_INS_CITNH = 899,
9445
    SYSZ_INS_CITNHE = 900,
9446
    SYSZ_INS_CITNL = 901,
9447
    SYSZ_INS_CITNLE = 902,
9448
    SYSZ_INS_CITNLH = 903,
9449
    SYSZ_INS_CKSM = 904,
9450
    SYSZ_INS_CLCL = 905,
9451
    SYSZ_INS_CLCLE = 906,
9452
    SYSZ_INS_CLCLU = 907,
9453
    SYSZ_INS_CLFDTR = 908,
9454
    SYSZ_INS_CLFIT = 909,
9455
    SYSZ_INS_CLFITE = 910,
9456
    SYSZ_INS_CLFITH = 911,
9457
    SYSZ_INS_CLFITHE = 912,
9458
    SYSZ_INS_CLFITL = 913,
9459
    SYSZ_INS_CLFITLE = 914,
9460
    SYSZ_INS_CLFITLH = 915,
9461
    SYSZ_INS_CLFITNE = 916,
9462
    SYSZ_INS_CLFITNH = 917,
9463
    SYSZ_INS_CLFITNHE = 918,
9464
    SYSZ_INS_CLFITNL = 919,
9465
    SYSZ_INS_CLFITNLE = 920,
9466
    SYSZ_INS_CLFITNLH = 921,
9467
    SYSZ_INS_CLFXTR = 922,
9468
    SYSZ_INS_CLGDTR = 923,
9469
    SYSZ_INS_CLGIB = 924,
9470
    SYSZ_INS_CLGIBE = 925,
9471
    SYSZ_INS_CLGIBH = 926,
9472
    SYSZ_INS_CLGIBHE = 927,
9473
    SYSZ_INS_CLGIBL = 928,
9474
    SYSZ_INS_CLGIBLE = 929,
9475
    SYSZ_INS_CLGIBLH = 930,
9476
    SYSZ_INS_CLGIBNE = 931,
9477
    SYSZ_INS_CLGIBNH = 932,
9478
    SYSZ_INS_CLGIBNHE = 933,
9479
    SYSZ_INS_CLGIBNL = 934,
9480
    SYSZ_INS_CLGIBNLE = 935,
9481
    SYSZ_INS_CLGIBNLH = 936,
9482
    SYSZ_INS_CLGIT = 937,
9483
    SYSZ_INS_CLGITE = 938,
9484
    SYSZ_INS_CLGITH = 939,
9485
    SYSZ_INS_CLGITHE = 940,
9486
    SYSZ_INS_CLGITL = 941,
9487
    SYSZ_INS_CLGITLE = 942,
9488
    SYSZ_INS_CLGITLH = 943,
9489
    SYSZ_INS_CLGITNE = 944,
9490
    SYSZ_INS_CLGITNH = 945,
9491
    SYSZ_INS_CLGITNHE = 946,
9492
    SYSZ_INS_CLGITNL = 947,
9493
    SYSZ_INS_CLGITNLE = 948,
9494
    SYSZ_INS_CLGITNLH = 949,
9495
    SYSZ_INS_CLGRB = 950,
9496
    SYSZ_INS_CLGRBE = 951,
9497
    SYSZ_INS_CLGRBH = 952,
9498
    SYSZ_INS_CLGRBHE = 953,
9499
    SYSZ_INS_CLGRBL = 954,
9500
    SYSZ_INS_CLGRBLE = 955,
9501
    SYSZ_INS_CLGRBLH = 956,
9502
    SYSZ_INS_CLGRBNE = 957,
9503
    SYSZ_INS_CLGRBNH = 958,
9504
    SYSZ_INS_CLGRBNHE = 959,
9505
    SYSZ_INS_CLGRBNL = 960,
9506
    SYSZ_INS_CLGRBNLE = 961,
9507
    SYSZ_INS_CLGRBNLH = 962,
9508
    SYSZ_INS_CLGRT = 963,
9509
    SYSZ_INS_CLGRTE = 964,
9510
    SYSZ_INS_CLGRTH = 965,
9511
    SYSZ_INS_CLGRTHE = 966,
9512
    SYSZ_INS_CLGRTL = 967,
9513
    SYSZ_INS_CLGRTLE = 968,
9514
    SYSZ_INS_CLGRTLH = 969,
9515
    SYSZ_INS_CLGRTNE = 970,
9516
    SYSZ_INS_CLGRTNH = 971,
9517
    SYSZ_INS_CLGRTNHE = 972,
9518
    SYSZ_INS_CLGRTNL = 973,
9519
    SYSZ_INS_CLGRTNLE = 974,
9520
    SYSZ_INS_CLGRTNLH = 975,
9521
    SYSZ_INS_CLGT = 976,
9522
    SYSZ_INS_CLGTE = 977,
9523
    SYSZ_INS_CLGTH = 978,
9524
    SYSZ_INS_CLGTHE = 979,
9525
    SYSZ_INS_CLGTL = 980,
9526
    SYSZ_INS_CLGTLE = 981,
9527
    SYSZ_INS_CLGTLH = 982,
9528
    SYSZ_INS_CLGTNE = 983,
9529
    SYSZ_INS_CLGTNH = 984,
9530
    SYSZ_INS_CLGTNHE = 985,
9531
    SYSZ_INS_CLGTNL = 986,
9532
    SYSZ_INS_CLGTNLE = 987,
9533
    SYSZ_INS_CLGTNLH = 988,
9534
    SYSZ_INS_CLGXTR = 989,
9535
    SYSZ_INS_CLHHR = 990,
9536
    SYSZ_INS_CLHLR = 991,
9537
    SYSZ_INS_CLIB = 992,
9538
    SYSZ_INS_CLIBE = 993,
9539
    SYSZ_INS_CLIBH = 994,
9540
    SYSZ_INS_CLIBHE = 995,
9541
    SYSZ_INS_CLIBL = 996,
9542
    SYSZ_INS_CLIBLE = 997,
9543
    SYSZ_INS_CLIBLH = 998,
9544
    SYSZ_INS_CLIBNE = 999,
9545
    SYSZ_INS_CLIBNH = 1000,
9546
    SYSZ_INS_CLIBNHE = 1001,
9547
    SYSZ_INS_CLIBNL = 1002,
9548
    SYSZ_INS_CLIBNLE = 1003,
9549
    SYSZ_INS_CLIBNLH = 1004,
9550
    SYSZ_INS_CLM = 1005,
9551
    SYSZ_INS_CLMH = 1006,
9552
    SYSZ_INS_CLMY = 1007,
9553
    SYSZ_INS_CLRB = 1008,
9554
    SYSZ_INS_CLRBE = 1009,
9555
    SYSZ_INS_CLRBH = 1010,
9556
    SYSZ_INS_CLRBHE = 1011,
9557
    SYSZ_INS_CLRBL = 1012,
9558
    SYSZ_INS_CLRBLE = 1013,
9559
    SYSZ_INS_CLRBLH = 1014,
9560
    SYSZ_INS_CLRBNE = 1015,
9561
    SYSZ_INS_CLRBNH = 1016,
9562
    SYSZ_INS_CLRBNHE = 1017,
9563
    SYSZ_INS_CLRBNL = 1018,
9564
    SYSZ_INS_CLRBNLE = 1019,
9565
    SYSZ_INS_CLRBNLH = 1020,
9566
    SYSZ_INS_CLRT = 1021,
9567
    SYSZ_INS_CLRTE = 1022,
9568
    SYSZ_INS_CLRTH = 1023,
9569
    SYSZ_INS_CLRTHE = 1024,
9570
    SYSZ_INS_CLRTL = 1025,
9571
    SYSZ_INS_CLRTLE = 1026,
9572
    SYSZ_INS_CLRTLH = 1027,
9573
    SYSZ_INS_CLRTNE = 1028,
9574
    SYSZ_INS_CLRTNH = 1029,
9575
    SYSZ_INS_CLRTNHE = 1030,
9576
    SYSZ_INS_CLRTNL = 1031,
9577
    SYSZ_INS_CLRTNLE = 1032,
9578
    SYSZ_INS_CLRTNLH = 1033,
9579
    SYSZ_INS_CLT = 1034,
9580
    SYSZ_INS_CLTE = 1035,
9581
    SYSZ_INS_CLTH = 1036,
9582
    SYSZ_INS_CLTHE = 1037,
9583
    SYSZ_INS_CLTL = 1038,
9584
    SYSZ_INS_CLTLE = 1039,
9585
    SYSZ_INS_CLTLH = 1040,
9586
    SYSZ_INS_CLTNE = 1041,
9587
    SYSZ_INS_CLTNH = 1042,
9588
    SYSZ_INS_CLTNHE = 1043,
9589
    SYSZ_INS_CLTNL = 1044,
9590
    SYSZ_INS_CLTNLE = 1045,
9591
    SYSZ_INS_CLTNLH = 1046,
9592
    SYSZ_INS_CMPSC = 1047,
9593
    SYSZ_INS_CP = 1048,
9594
    SYSZ_INS_CPDT = 1049,
9595
    SYSZ_INS_CPXT = 1050,
9596
    SYSZ_INS_CPYA = 1051,
9597
    SYSZ_INS_CRB = 1052,
9598
    SYSZ_INS_CRBE = 1053,
9599
    SYSZ_INS_CRBH = 1054,
9600
    SYSZ_INS_CRBHE = 1055,
9601
    SYSZ_INS_CRBL = 1056,
9602
    SYSZ_INS_CRBLE = 1057,
9603
    SYSZ_INS_CRBLH = 1058,
9604
    SYSZ_INS_CRBNE = 1059,
9605
    SYSZ_INS_CRBNH = 1060,
9606
    SYSZ_INS_CRBNHE = 1061,
9607
    SYSZ_INS_CRBNL = 1062,
9608
    SYSZ_INS_CRBNLE = 1063,
9609
    SYSZ_INS_CRBNLH = 1064,
9610
    SYSZ_INS_CRDTE = 1065,
9611
    SYSZ_INS_CRT = 1066,
9612
    SYSZ_INS_CRTE = 1067,
9613
    SYSZ_INS_CRTH = 1068,
9614
    SYSZ_INS_CRTHE = 1069,
9615
    SYSZ_INS_CRTL = 1070,
9616
    SYSZ_INS_CRTLE = 1071,
9617
    SYSZ_INS_CRTLH = 1072,
9618
    SYSZ_INS_CRTNE = 1073,
9619
    SYSZ_INS_CRTNH = 1074,
9620
    SYSZ_INS_CRTNHE = 1075,
9621
    SYSZ_INS_CRTNL = 1076,
9622
    SYSZ_INS_CRTNLE = 1077,
9623
    SYSZ_INS_CRTNLH = 1078,
9624
    SYSZ_INS_CSCH = 1079,
9625
    SYSZ_INS_CSDTR = 1080,
9626
    SYSZ_INS_CSP = 1081,
9627
    SYSZ_INS_CSPG = 1082,
9628
    SYSZ_INS_CSST = 1083,
9629
    SYSZ_INS_CSXTR = 1084,
9630
    SYSZ_INS_CU12 = 1085,
9631
    SYSZ_INS_CU14 = 1086,
9632
    SYSZ_INS_CU21 = 1087,
9633
    SYSZ_INS_CU24 = 1088,
9634
    SYSZ_INS_CU41 = 1089,
9635
    SYSZ_INS_CU42 = 1090,
9636
    SYSZ_INS_CUDTR = 1091,
9637
    SYSZ_INS_CUSE = 1092,
9638
    SYSZ_INS_CUTFU = 1093,
9639
    SYSZ_INS_CUUTF = 1094,
9640
    SYSZ_INS_CUXTR = 1095,
9641
    SYSZ_INS_CVB = 1096,
9642
    SYSZ_INS_CVBG = 1097,
9643
    SYSZ_INS_CVBY = 1098,
9644
    SYSZ_INS_CVD = 1099,
9645
    SYSZ_INS_CVDG = 1100,
9646
    SYSZ_INS_CVDY = 1101,
9647
    SYSZ_INS_CXFBRA = 1102,
9648
    SYSZ_INS_CXFR = 1103,
9649
    SYSZ_INS_CXFTR = 1104,
9650
    SYSZ_INS_CXGBRA = 1105,
9651
    SYSZ_INS_CXGR = 1106,
9652
    SYSZ_INS_CXGTR = 1107,
9653
    SYSZ_INS_CXGTRA = 1108,
9654
    SYSZ_INS_CXLFTR = 1109,
9655
    SYSZ_INS_CXLGTR = 1110,
9656
    SYSZ_INS_CXPT = 1111,
9657
    SYSZ_INS_CXR = 1112,
9658
    SYSZ_INS_CXSTR = 1113,
9659
    SYSZ_INS_CXTR = 1114,
9660
    SYSZ_INS_CXUTR = 1115,
9661
    SYSZ_INS_CXZT = 1116,
9662
    SYSZ_INS_CZDT = 1117,
9663
    SYSZ_INS_CZXT = 1118,
9664
    SYSZ_INS_D = 1119,
9665
    SYSZ_INS_DD = 1120,
9666
    SYSZ_INS_DDR = 1121,
9667
    SYSZ_INS_DDTR = 1122,
9668
    SYSZ_INS_DDTRA = 1123,
9669
    SYSZ_INS_DE = 1124,
9670
    SYSZ_INS_DER = 1125,
9671
    SYSZ_INS_DIAG = 1126,
9672
    SYSZ_INS_DIDBR = 1127,
9673
    SYSZ_INS_DIEBR = 1128,
9674
    SYSZ_INS_DP = 1129,
9675
    SYSZ_INS_DR = 1130,
9676
    SYSZ_INS_DXR = 1131,
9677
    SYSZ_INS_DXTR = 1132,
9678
    SYSZ_INS_DXTRA = 1133,
9679
    SYSZ_INS_ECAG = 1134,
9680
    SYSZ_INS_ECCTR = 1135,
9681
    SYSZ_INS_ECPGA = 1136,
9682
    SYSZ_INS_ECTG = 1137,
9683
    SYSZ_INS_ED = 1138,
9684
    SYSZ_INS_EDMK = 1139,
9685
    SYSZ_INS_EEDTR = 1140,
9686
    SYSZ_INS_EEXTR = 1141,
9687
    SYSZ_INS_EFPC = 1142,
9688
    SYSZ_INS_EPAIR = 1143,
9689
    SYSZ_INS_EPAR = 1144,
9690
    SYSZ_INS_EPCTR = 1145,
9691
    SYSZ_INS_EPSW = 1146,
9692
    SYSZ_INS_EREG = 1147,
9693
    SYSZ_INS_EREGG = 1148,
9694
    SYSZ_INS_ESAIR = 1149,
9695
    SYSZ_INS_ESAR = 1150,
9696
    SYSZ_INS_ESDTR = 1151,
9697
    SYSZ_INS_ESEA = 1152,
9698
    SYSZ_INS_ESTA = 1153,
9699
    SYSZ_INS_ESXTR = 1154,
9700
    SYSZ_INS_ETND = 1155,
9701
    SYSZ_INS_EX = 1156,
9702
    SYSZ_INS_EXRL = 1157,
9703
    SYSZ_INS_FIDR = 1158,
9704
    SYSZ_INS_FIDTR = 1159,
9705
    SYSZ_INS_FIER = 1160,
9706
    SYSZ_INS_FIXR = 1161,
9707
    SYSZ_INS_FIXTR = 1162,
9708
    SYSZ_INS_HDR = 1163,
9709
    SYSZ_INS_HER = 1164,
9710
    SYSZ_INS_HSCH = 1165,
9711
    SYSZ_INS_IAC = 1166,
9712
    SYSZ_INS_ICM = 1167,
9713
    SYSZ_INS_ICMH = 1168,
9714
    SYSZ_INS_ICMY = 1169,
9715
    SYSZ_INS_IDTE = 1170,
9716
    SYSZ_INS_IEDTR = 1171,
9717
    SYSZ_INS_IEXTR = 1172,
9718
    SYSZ_INS_IPK = 1173,
9719
    SYSZ_INS_IPTE = 1174,
9720
    SYSZ_INS_IRBM = 1175,
9721
    SYSZ_INS_ISKE = 1176,
9722
    SYSZ_INS_IVSK = 1177,
9723
    SYSZ_INS_JGM = 1178,
9724
    SYSZ_INS_JGNM = 1179,
9725
    SYSZ_INS_JGNP = 1180,
9726
    SYSZ_INS_JGNZ = 1181,
9727
    SYSZ_INS_JGP = 1182,
9728
    SYSZ_INS_JGZ = 1183,
9729
    SYSZ_INS_JM = 1184,
9730
    SYSZ_INS_JNM = 1185,
9731
    SYSZ_INS_JNP = 1186,
9732
    SYSZ_INS_JNZ = 1187,
9733
    SYSZ_INS_JP = 1188,
9734
    SYSZ_INS_JZ = 1189,
9735
    SYSZ_INS_KDB = 1190,
9736
    SYSZ_INS_KDBR = 1191,
9737
    SYSZ_INS_KDTR = 1192,
9738
    SYSZ_INS_KEB = 1193,
9739
    SYSZ_INS_KEBR = 1194,
9740
    SYSZ_INS_KIMD = 1195,
9741
    SYSZ_INS_KLMD = 1196,
9742
    SYSZ_INS_KM = 1197,
9743
    SYSZ_INS_KMA = 1198,
9744
    SYSZ_INS_KMAC = 1199,
9745
    SYSZ_INS_KMC = 1200,
9746
    SYSZ_INS_KMCTR = 1201,
9747
    SYSZ_INS_KMF = 1202,
9748
    SYSZ_INS_KMO = 1203,
9749
    SYSZ_INS_KXBR = 1204,
9750
    SYSZ_INS_KXTR = 1205,
9751
    SYSZ_INS_LAE = 1206,
9752
    SYSZ_INS_LAEY = 1207,
9753
    SYSZ_INS_LAM = 1208,
9754
    SYSZ_INS_LAMY = 1209,
9755
    SYSZ_INS_LASP = 1210,
9756
    SYSZ_INS_LAT = 1211,
9757
    SYSZ_INS_LCBB = 1212,
9758
    SYSZ_INS_LCCTL = 1213,
9759
    SYSZ_INS_LCDFR = 1214,
9760
    SYSZ_INS_LCDR = 1215,
9761
    SYSZ_INS_LCER = 1216,
9762
    SYSZ_INS_LCTL = 1217,
9763
    SYSZ_INS_LCTLG = 1218,
9764
    SYSZ_INS_LCXR = 1219,
9765
    SYSZ_INS_LDE = 1220,
9766
    SYSZ_INS_LDER = 1221,
9767
    SYSZ_INS_LDETR = 1222,
9768
    SYSZ_INS_LDXR = 1223,
9769
    SYSZ_INS_LDXTR = 1224,
9770
    SYSZ_INS_LEDR = 1225,
9771
    SYSZ_INS_LEDTR = 1226,
9772
    SYSZ_INS_LEXR = 1227,
9773
    SYSZ_INS_LFAS = 1228,
9774
    SYSZ_INS_LFHAT = 1229,
9775
    SYSZ_INS_LFPC = 1230,
9776
    SYSZ_INS_LGAT = 1231,
9777
    SYSZ_INS_LGG = 1232,
9778
    SYSZ_INS_LGSC = 1233,
9779
    SYSZ_INS_LLGFAT = 1234,
9780
    SYSZ_INS_LLGFSG = 1235,
9781
    SYSZ_INS_LLGT = 1236,
9782
    SYSZ_INS_LLGTAT = 1237,
9783
    SYSZ_INS_LLGTR = 1238,
9784
    SYSZ_INS_LLZRGF = 1239,
9785
    SYSZ_INS_LM = 1240,
9786
    SYSZ_INS_LMD = 1241,
9787
    SYSZ_INS_LMH = 1242,
9788
    SYSZ_INS_LMY = 1243,
9789
    SYSZ_INS_LNDFR = 1244,
9790
    SYSZ_INS_LNDR = 1245,
9791
    SYSZ_INS_LNER = 1246,
9792
    SYSZ_INS_LNXR = 1247,
9793
    SYSZ_INS_LOCFH = 1248,
9794
    SYSZ_INS_LOCFHE = 1249,
9795
    SYSZ_INS_LOCFHH = 1250,
9796
    SYSZ_INS_LOCFHHE = 1251,
9797
    SYSZ_INS_LOCFHL = 1252,
9798
    SYSZ_INS_LOCFHLE = 1253,
9799
    SYSZ_INS_LOCFHLH = 1254,
9800
    SYSZ_INS_LOCFHM = 1255,
9801
    SYSZ_INS_LOCFHNE = 1256,
9802
    SYSZ_INS_LOCFHNH = 1257,
9803
    SYSZ_INS_LOCFHNHE = 1258,
9804
    SYSZ_INS_LOCFHNL = 1259,
9805
    SYSZ_INS_LOCFHNLE = 1260,
9806
    SYSZ_INS_LOCFHNLH = 1261,
9807
    SYSZ_INS_LOCFHNM = 1262,
9808
    SYSZ_INS_LOCFHNO = 1263,
9809
    SYSZ_INS_LOCFHNP = 1264,
9810
    SYSZ_INS_LOCFHNZ = 1265,
9811
    SYSZ_INS_LOCFHO = 1266,
9812
    SYSZ_INS_LOCFHP = 1267,
9813
    SYSZ_INS_LOCFHR = 1268,
9814
    SYSZ_INS_LOCFHRE = 1269,
9815
    SYSZ_INS_LOCFHRH = 1270,
9816
    SYSZ_INS_LOCFHRHE = 1271,
9817
    SYSZ_INS_LOCFHRL = 1272,
9818
    SYSZ_INS_LOCFHRLE = 1273,
9819
    SYSZ_INS_LOCFHRLH = 1274,
9820
    SYSZ_INS_LOCFHRM = 1275,
9821
    SYSZ_INS_LOCFHRNE = 1276,
9822
    SYSZ_INS_LOCFHRNH = 1277,
9823
    SYSZ_INS_LOCFHRNHE = 1278,
9824
    SYSZ_INS_LOCFHRNL = 1279,
9825
    SYSZ_INS_LOCFHRNLE = 1280,
9826
    SYSZ_INS_LOCFHRNLH = 1281,
9827
    SYSZ_INS_LOCFHRNM = 1282,
9828
    SYSZ_INS_LOCFHRNO = 1283,
9829
    SYSZ_INS_LOCFHRNP = 1284,
9830
    SYSZ_INS_LOCFHRNZ = 1285,
9831
    SYSZ_INS_LOCFHRO = 1286,
9832
    SYSZ_INS_LOCFHRP = 1287,
9833
    SYSZ_INS_LOCFHRZ = 1288,
9834
    SYSZ_INS_LOCFHZ = 1289,
9835
    SYSZ_INS_LOCGHI = 1290,
9836
    SYSZ_INS_LOCGHIE = 1291,
9837
    SYSZ_INS_LOCGHIH = 1292,
9838
    SYSZ_INS_LOCGHIHE = 1293,
9839
    SYSZ_INS_LOCGHIL = 1294,
9840
    SYSZ_INS_LOCGHILE = 1295,
9841
    SYSZ_INS_LOCGHILH = 1296,
9842
    SYSZ_INS_LOCGHIM = 1297,
9843
    SYSZ_INS_LOCGHINE = 1298,
9844
    SYSZ_INS_LOCGHINH = 1299,
9845
    SYSZ_INS_LOCGHINHE = 1300,
9846
    SYSZ_INS_LOCGHINL = 1301,
9847
    SYSZ_INS_LOCGHINLE = 1302,
9848
    SYSZ_INS_LOCGHINLH = 1303,
9849
    SYSZ_INS_LOCGHINM = 1304,
9850
    SYSZ_INS_LOCGHINO = 1305,
9851
    SYSZ_INS_LOCGHINP = 1306,
9852
    SYSZ_INS_LOCGHINZ = 1307,
9853
    SYSZ_INS_LOCGHIO = 1308,
9854
    SYSZ_INS_LOCGHIP = 1309,
9855
    SYSZ_INS_LOCGHIZ = 1310,
9856
    SYSZ_INS_LOCGM = 1311,
9857
    SYSZ_INS_LOCGNM = 1312,
9858
    SYSZ_INS_LOCGNP = 1313,
9859
    SYSZ_INS_LOCGNZ = 1314,
9860
    SYSZ_INS_LOCGP = 1315,
9861
    SYSZ_INS_LOCGRM = 1316,
9862
    SYSZ_INS_LOCGRNM = 1317,
9863
    SYSZ_INS_LOCGRNP = 1318,
9864
    SYSZ_INS_LOCGRNZ = 1319,
9865
    SYSZ_INS_LOCGRP = 1320,
9866
    SYSZ_INS_LOCGRZ = 1321,
9867
    SYSZ_INS_LOCGZ = 1322,
9868
    SYSZ_INS_LOCHHI = 1323,
9869
    SYSZ_INS_LOCHHIE = 1324,
9870
    SYSZ_INS_LOCHHIH = 1325,
9871
    SYSZ_INS_LOCHHIHE = 1326,
9872
    SYSZ_INS_LOCHHIL = 1327,
9873
    SYSZ_INS_LOCHHILE = 1328,
9874
    SYSZ_INS_LOCHHILH = 1329,
9875
    SYSZ_INS_LOCHHIM = 1330,
9876
    SYSZ_INS_LOCHHINE = 1331,
9877
    SYSZ_INS_LOCHHINH = 1332,
9878
    SYSZ_INS_LOCHHINHE = 1333,
9879
    SYSZ_INS_LOCHHINL = 1334,
9880
    SYSZ_INS_LOCHHINLE = 1335,
9881
    SYSZ_INS_LOCHHINLH = 1336,
9882
    SYSZ_INS_LOCHHINM = 1337,
9883
    SYSZ_INS_LOCHHINO = 1338,
9884
    SYSZ_INS_LOCHHINP = 1339,
9885
    SYSZ_INS_LOCHHINZ = 1340,
9886
    SYSZ_INS_LOCHHIO = 1341,
9887
    SYSZ_INS_LOCHHIP = 1342,
9888
    SYSZ_INS_LOCHHIZ = 1343,
9889
    SYSZ_INS_LOCHI = 1344,
9890
    SYSZ_INS_LOCHIE = 1345,
9891
    SYSZ_INS_LOCHIH = 1346,
9892
    SYSZ_INS_LOCHIHE = 1347,
9893
    SYSZ_INS_LOCHIL = 1348,
9894
    SYSZ_INS_LOCHILE = 1349,
9895
    SYSZ_INS_LOCHILH = 1350,
9896
    SYSZ_INS_LOCHIM = 1351,
9897
    SYSZ_INS_LOCHINE = 1352,
9898
    SYSZ_INS_LOCHINH = 1353,
9899
    SYSZ_INS_LOCHINHE = 1354,
9900
    SYSZ_INS_LOCHINL = 1355,
9901
    SYSZ_INS_LOCHINLE = 1356,
9902
    SYSZ_INS_LOCHINLH = 1357,
9903
    SYSZ_INS_LOCHINM = 1358,
9904
    SYSZ_INS_LOCHINO = 1359,
9905
    SYSZ_INS_LOCHINP = 1360,
9906
    SYSZ_INS_LOCHINZ = 1361,
9907
    SYSZ_INS_LOCHIO = 1362,
9908
    SYSZ_INS_LOCHIP = 1363,
9909
    SYSZ_INS_LOCHIZ = 1364,
9910
    SYSZ_INS_LOCM = 1365,
9911
    SYSZ_INS_LOCNM = 1366,
9912
    SYSZ_INS_LOCNP = 1367,
9913
    SYSZ_INS_LOCNZ = 1368,
9914
    SYSZ_INS_LOCP = 1369,
9915
    SYSZ_INS_LOCRM = 1370,
9916
    SYSZ_INS_LOCRNM = 1371,
9917
    SYSZ_INS_LOCRNP = 1372,
9918
    SYSZ_INS_LOCRNZ = 1373,
9919
    SYSZ_INS_LOCRP = 1374,
9920
    SYSZ_INS_LOCRZ = 1375,
9921
    SYSZ_INS_LOCZ = 1376,
9922
    SYSZ_INS_LPCTL = 1377,
9923
    SYSZ_INS_LPD = 1378,
9924
    SYSZ_INS_LPDFR = 1379,
9925
    SYSZ_INS_LPDG = 1380,
9926
    SYSZ_INS_LPDR = 1381,
9927
    SYSZ_INS_LPER = 1382,
9928
    SYSZ_INS_LPP = 1383,
9929
    SYSZ_INS_LPQ = 1384,
9930
    SYSZ_INS_LPSW = 1385,
9931
    SYSZ_INS_LPSWE = 1386,
9932
    SYSZ_INS_LPTEA = 1387,
9933
    SYSZ_INS_LPXR = 1388,
9934
    SYSZ_INS_LRA = 1389,
9935
    SYSZ_INS_LRAG = 1390,
9936
    SYSZ_INS_LRAY = 1391,
9937
    SYSZ_INS_LRDR = 1392,
9938
    SYSZ_INS_LRER = 1393,
9939
    SYSZ_INS_LRVH = 1394,
9940
    SYSZ_INS_LSCTL = 1395,
9941
    SYSZ_INS_LTDR = 1396,
9942
    SYSZ_INS_LTDTR = 1397,
9943
    SYSZ_INS_LTER = 1398,
9944
    SYSZ_INS_LTXR = 1399,
9945
    SYSZ_INS_LTXTR = 1400,
9946
    SYSZ_INS_LURA = 1401,
9947
    SYSZ_INS_LURAG = 1402,
9948
    SYSZ_INS_LXD = 1403,
9949
    SYSZ_INS_LXDR = 1404,
9950
    SYSZ_INS_LXDTR = 1405,
9951
    SYSZ_INS_LXE = 1406,
9952
    SYSZ_INS_LXER = 1407,
9953
    SYSZ_INS_LZRF = 1408,
9954
    SYSZ_INS_LZRG = 1409,
9955
    SYSZ_INS_M = 1410,
9956
    SYSZ_INS_MAD = 1411,
9957
    SYSZ_INS_MADR = 1412,
9958
    SYSZ_INS_MAE = 1413,
9959
    SYSZ_INS_MAER = 1414,
9960
    SYSZ_INS_MAY = 1415,
9961
    SYSZ_INS_MAYH = 1416,
9962
    SYSZ_INS_MAYHR = 1417,
9963
    SYSZ_INS_MAYL = 1418,
9964
    SYSZ_INS_MAYLR = 1419,
9965
    SYSZ_INS_MAYR = 1420,
9966
    SYSZ_INS_MC = 1421,
9967
    SYSZ_INS_MD = 1422,
9968
    SYSZ_INS_MDE = 1423,
9969
    SYSZ_INS_MDER = 1424,
9970
    SYSZ_INS_MDR = 1425,
9971
    SYSZ_INS_MDTR = 1426,
9972
    SYSZ_INS_MDTRA = 1427,
9973
    SYSZ_INS_ME = 1428,
9974
    SYSZ_INS_MEE = 1429,
9975
    SYSZ_INS_MEER = 1430,
9976
    SYSZ_INS_MER = 1431,
9977
    SYSZ_INS_MFY = 1432,
9978
    SYSZ_INS_MG = 1433,
9979
    SYSZ_INS_MGH = 1434,
9980
    SYSZ_INS_MGRK = 1435,
9981
    SYSZ_INS_ML = 1436,
9982
    SYSZ_INS_MLR = 1437,
9983
    SYSZ_INS_MP = 1438,
9984
    SYSZ_INS_MR = 1439,
9985
    SYSZ_INS_MSC = 1440,
9986
    SYSZ_INS_MSCH = 1441,
9987
    SYSZ_INS_MSD = 1442,
9988
    SYSZ_INS_MSDR = 1443,
9989
    SYSZ_INS_MSE = 1444,
9990
    SYSZ_INS_MSER = 1445,
9991
    SYSZ_INS_MSGC = 1446,
9992
    SYSZ_INS_MSGRKC = 1447,
9993
    SYSZ_INS_MSRKC = 1448,
9994
    SYSZ_INS_MSTA = 1449,
9995
    SYSZ_INS_MVCDK = 1450,
9996
    SYSZ_INS_MVCIN = 1451,
9997
    SYSZ_INS_MVCK = 1452,
9998
    SYSZ_INS_MVCL = 1453,
9999
    SYSZ_INS_MVCLE = 1454,
10000
    SYSZ_INS_MVCLU = 1455,
10001
    SYSZ_INS_MVCOS = 1456,
10002
    SYSZ_INS_MVCP = 1457,
10003
    SYSZ_INS_MVCS = 1458,
10004
    SYSZ_INS_MVCSK = 1459,
10005
    SYSZ_INS_MVN = 1460,
10006
    SYSZ_INS_MVO = 1461,
10007
    SYSZ_INS_MVPG = 1462,
10008
    SYSZ_INS_MVZ = 1463,
10009
    SYSZ_INS_MXD = 1464,
10010
    SYSZ_INS_MXDR = 1465,
10011
    SYSZ_INS_MXR = 1466,
10012
    SYSZ_INS_MXTR = 1467,
10013
    SYSZ_INS_MXTRA = 1468,
10014
    SYSZ_INS_MY = 1469,
10015
    SYSZ_INS_MYH = 1470,
10016
    SYSZ_INS_MYHR = 1471,
10017
    SYSZ_INS_MYL = 1472,
10018
    SYSZ_INS_MYLR = 1473,
10019
    SYSZ_INS_MYR = 1474,
10020
    SYSZ_INS_NIAI = 1475,
10021
    SYSZ_INS_NTSTG = 1476,
10022
    SYSZ_INS_PACK = 1477,
10023
    SYSZ_INS_PALB = 1478,
10024
    SYSZ_INS_PC = 1479,
10025
    SYSZ_INS_PCC = 1480,
10026
    SYSZ_INS_PCKMO = 1481,
10027
    SYSZ_INS_PFMF = 1482,
10028
    SYSZ_INS_PFPO = 1483,
10029
    SYSZ_INS_PGIN = 1484,
10030
    SYSZ_INS_PGOUT = 1485,
10031
    SYSZ_INS_PKA = 1486,
10032
    SYSZ_INS_PKU = 1487,
10033
    SYSZ_INS_PLO = 1488,
10034
    SYSZ_INS_POPCNT = 1489,
10035
    SYSZ_INS_PPA = 1490,
10036
    SYSZ_INS_PPNO = 1491,
10037
    SYSZ_INS_PR = 1492,
10038
    SYSZ_INS_PRNO = 1493,
10039
    SYSZ_INS_PT = 1494,
10040
    SYSZ_INS_PTF = 1495,
10041
    SYSZ_INS_PTFF = 1496,
10042
    SYSZ_INS_PTI = 1497,
10043
    SYSZ_INS_PTLB = 1498,
10044
    SYSZ_INS_QADTR = 1499,
10045
    SYSZ_INS_QAXTR = 1500,
10046
    SYSZ_INS_QCTRI = 1501,
10047
    SYSZ_INS_QSI = 1502,
10048
    SYSZ_INS_RCHP = 1503,
10049
    SYSZ_INS_RISBGN = 1504,
10050
    SYSZ_INS_RP = 1505,
10051
    SYSZ_INS_RRBE = 1506,
10052
    SYSZ_INS_RRBM = 1507,
10053
    SYSZ_INS_RRDTR = 1508,
10054
    SYSZ_INS_RRXTR = 1509,
10055
    SYSZ_INS_RSCH = 1510,
10056
    SYSZ_INS_SAC = 1511,
10057
    SYSZ_INS_SACF = 1512,
10058
    SYSZ_INS_SAL = 1513,
10059
    SYSZ_INS_SAM24 = 1514,
10060
    SYSZ_INS_SAM31 = 1515,
10061
    SYSZ_INS_SAM64 = 1516,
10062
    SYSZ_INS_SAR = 1517,
10063
    SYSZ_INS_SCCTR = 1518,
10064
    SYSZ_INS_SCHM = 1519,
10065
    SYSZ_INS_SCK = 1520,
10066
    SYSZ_INS_SCKC = 1521,
10067
    SYSZ_INS_SCKPF = 1522,
10068
    SYSZ_INS_SD = 1523,
10069
    SYSZ_INS_SDR = 1524,
10070
    SYSZ_INS_SDTR = 1525,
10071
    SYSZ_INS_SDTRA = 1526,
10072
    SYSZ_INS_SE = 1527,
10073
    SYSZ_INS_SER = 1528,
10074
    SYSZ_INS_SFASR = 1529,
10075
    SYSZ_INS_SFPC = 1530,
10076
    SYSZ_INS_SGH = 1531,
10077
    SYSZ_INS_SHHHR = 1532,
10078
    SYSZ_INS_SHHLR = 1533,
10079
    SYSZ_INS_SIE = 1534,
10080
    SYSZ_INS_SIGA = 1535,
10081
    SYSZ_INS_SIGP = 1536,
10082
    SYSZ_INS_SLA = 1537,
10083
    SYSZ_INS_SLAG = 1538,
10084
    SYSZ_INS_SLAK = 1539,
10085
    SYSZ_INS_SLDA = 1540,
10086
    SYSZ_INS_SLDL = 1541,
10087
    SYSZ_INS_SLDT = 1542,
10088
    SYSZ_INS_SLHHHR = 1543,
10089
    SYSZ_INS_SLHHLR = 1544,
10090
    SYSZ_INS_SLXT = 1545,
10091
    SYSZ_INS_SP = 1546,
10092
    SYSZ_INS_SPCTR = 1547,
10093
    SYSZ_INS_SPKA = 1548,
10094
    SYSZ_INS_SPM = 1549,
10095
    SYSZ_INS_SPT = 1550,
10096
    SYSZ_INS_SPX = 1551,
10097
    SYSZ_INS_SQD = 1552,
10098
    SYSZ_INS_SQDR = 1553,
10099
    SYSZ_INS_SQE = 1554,
10100
    SYSZ_INS_SQER = 1555,
10101
    SYSZ_INS_SQXR = 1556,
10102
    SYSZ_INS_SRDA = 1557,
10103
    SYSZ_INS_SRDL = 1558,
10104
    SYSZ_INS_SRDT = 1559,
10105
    SYSZ_INS_SRNM = 1560,
10106
    SYSZ_INS_SRNMB = 1561,
10107
    SYSZ_INS_SRNMT = 1562,
10108
    SYSZ_INS_SRP = 1563,
10109
    SYSZ_INS_SRSTU = 1564,
10110
    SYSZ_INS_SRXT = 1565,
10111
    SYSZ_INS_SSAIR = 1566,
10112
    SYSZ_INS_SSAR = 1567,
10113
    SYSZ_INS_SSCH = 1568,
10114
    SYSZ_INS_SSKE = 1569,
10115
    SYSZ_INS_SSM = 1570,
10116
    SYSZ_INS_STAM = 1571,
10117
    SYSZ_INS_STAMY = 1572,
10118
    SYSZ_INS_STAP = 1573,
10119
    SYSZ_INS_STCK = 1574,
10120
    SYSZ_INS_STCKC = 1575,
10121
    SYSZ_INS_STCKE = 1576,
10122
    SYSZ_INS_STCKF = 1577,
10123
    SYSZ_INS_STCM = 1578,
10124
    SYSZ_INS_STCMH = 1579,
10125
    SYSZ_INS_STCMY = 1580,
10126
    SYSZ_INS_STCPS = 1581,
10127
    SYSZ_INS_STCRW = 1582,
10128
    SYSZ_INS_STCTG = 1583,
10129
    SYSZ_INS_STCTL = 1584,
10130
    SYSZ_INS_STFL = 1585,
10131
    SYSZ_INS_STFLE = 1586,
10132
    SYSZ_INS_STFPC = 1587,
10133
    SYSZ_INS_STGSC = 1588,
10134
    SYSZ_INS_STIDP = 1589,
10135
    SYSZ_INS_STM = 1590,
10136
    SYSZ_INS_STMH = 1591,
10137
    SYSZ_INS_STMY = 1592,
10138
    SYSZ_INS_STNSM = 1593,
10139
    SYSZ_INS_STOCFH = 1594,
10140
    SYSZ_INS_STOCFHE = 1595,
10141
    SYSZ_INS_STOCFHH = 1596,
10142
    SYSZ_INS_STOCFHHE = 1597,
10143
    SYSZ_INS_STOCFHL = 1598,
10144
    SYSZ_INS_STOCFHLE = 1599,
10145
    SYSZ_INS_STOCFHLH = 1600,
10146
    SYSZ_INS_STOCFHM = 1601,
10147
    SYSZ_INS_STOCFHNE = 1602,
10148
    SYSZ_INS_STOCFHNH = 1603,
10149
    SYSZ_INS_STOCFHNHE = 1604,
10150
    SYSZ_INS_STOCFHNL = 1605,
10151
    SYSZ_INS_STOCFHNLE = 1606,
10152
    SYSZ_INS_STOCFHNLH = 1607,
10153
    SYSZ_INS_STOCFHNM = 1608,
10154
    SYSZ_INS_STOCFHNO = 1609,
10155
    SYSZ_INS_STOCFHNP = 1610,
10156
    SYSZ_INS_STOCFHNZ = 1611,
10157
    SYSZ_INS_STOCFHO = 1612,
10158
    SYSZ_INS_STOCFHP = 1613,
10159
    SYSZ_INS_STOCFHZ = 1614,
10160
    SYSZ_INS_STOCGM = 1615,
10161
    SYSZ_INS_STOCGNM = 1616,
10162
    SYSZ_INS_STOCGNP = 1617,
10163
    SYSZ_INS_STOCGNZ = 1618,
10164
    SYSZ_INS_STOCGP = 1619,
10165
    SYSZ_INS_STOCGZ = 1620,
10166
    SYSZ_INS_STOCM = 1621,
10167
    SYSZ_INS_STOCNM = 1622,
10168
    SYSZ_INS_STOCNP = 1623,
10169
    SYSZ_INS_STOCNZ = 1624,
10170
    SYSZ_INS_STOCP = 1625,
10171
    SYSZ_INS_STOCZ = 1626,
10172
    SYSZ_INS_STOSM = 1627,
10173
    SYSZ_INS_STPQ = 1628,
10174
    SYSZ_INS_STPT = 1629,
10175
    SYSZ_INS_STPX = 1630,
10176
    SYSZ_INS_STRAG = 1631,
10177
    SYSZ_INS_STRVH = 1632,
10178
    SYSZ_INS_STSCH = 1633,
10179
    SYSZ_INS_STSI = 1634,
10180
    SYSZ_INS_STURA = 1635,
10181
    SYSZ_INS_STURG = 1636,
10182
    SYSZ_INS_SU = 1637,
10183
    SYSZ_INS_SUR = 1638,
10184
    SYSZ_INS_SVC = 1639,
10185
    SYSZ_INS_SW = 1640,
10186
    SYSZ_INS_SWR = 1641,
10187
    SYSZ_INS_SXR = 1642,
10188
    SYSZ_INS_SXTR = 1643,
10189
    SYSZ_INS_SXTRA = 1644,
10190
    SYSZ_INS_TABORT = 1645,
10191
    SYSZ_INS_TAM = 1646,
10192
    SYSZ_INS_TAR = 1647,
10193
    SYSZ_INS_TB = 1648,
10194
    SYSZ_INS_TBDR = 1649,
10195
    SYSZ_INS_TBEDR = 1650,
10196
    SYSZ_INS_TBEGIN = 1651,
10197
    SYSZ_INS_TBEGINC = 1652,
10198
    SYSZ_INS_TCDB = 1653,
10199
    SYSZ_INS_TCEB = 1654,
10200
    SYSZ_INS_TCXB = 1655,
10201
    SYSZ_INS_TDCDT = 1656,
10202
    SYSZ_INS_TDCET = 1657,
10203
    SYSZ_INS_TDCXT = 1658,
10204
    SYSZ_INS_TDGDT = 1659,
10205
    SYSZ_INS_TDGET = 1660,
10206
    SYSZ_INS_TDGXT = 1661,
10207
    SYSZ_INS_TEND = 1662,
10208
    SYSZ_INS_THDER = 1663,
10209
    SYSZ_INS_THDR = 1664,
10210
    SYSZ_INS_TP = 1665,
10211
    SYSZ_INS_TPI = 1666,
10212
    SYSZ_INS_TPROT = 1667,
10213
    SYSZ_INS_TR = 1668,
10214
    SYSZ_INS_TRACE = 1669,
10215
    SYSZ_INS_TRACG = 1670,
10216
    SYSZ_INS_TRAP2 = 1671,
10217
    SYSZ_INS_TRAP4 = 1672,
10218
    SYSZ_INS_TRE = 1673,
10219
    SYSZ_INS_TROO = 1674,
10220
    SYSZ_INS_TROT = 1675,
10221
    SYSZ_INS_TRT = 1676,
10222
    SYSZ_INS_TRTE = 1677,
10223
    SYSZ_INS_TRTO = 1678,
10224
    SYSZ_INS_TRTR = 1679,
10225
    SYSZ_INS_TRTRE = 1680,
10226
    SYSZ_INS_TRTT = 1681,
10227
    SYSZ_INS_TS = 1682,
10228
    SYSZ_INS_TSCH = 1683,
10229
    SYSZ_INS_UNPK = 1684,
10230
    SYSZ_INS_UNPKA = 1685,
10231
    SYSZ_INS_UNPKU = 1686,
10232
    SYSZ_INS_UPT = 1687,
10233
    SYSZ_INS_VA = 1688,
10234
    SYSZ_INS_VAB = 1689,
10235
    SYSZ_INS_VAC = 1690,
10236
    SYSZ_INS_VACC = 1691,
10237
    SYSZ_INS_VACCB = 1692,
10238
    SYSZ_INS_VACCC = 1693,
10239
    SYSZ_INS_VACCCQ = 1694,
10240
    SYSZ_INS_VACCF = 1695,
10241
    SYSZ_INS_VACCG = 1696,
10242
    SYSZ_INS_VACCH = 1697,
10243
    SYSZ_INS_VACCQ = 1698,
10244
    SYSZ_INS_VACQ = 1699,
10245
    SYSZ_INS_VAF = 1700,
10246
    SYSZ_INS_VAG = 1701,
10247
    SYSZ_INS_VAH = 1702,
10248
    SYSZ_INS_VAP = 1703,
10249
    SYSZ_INS_VAQ = 1704,
10250
    SYSZ_INS_VAVG = 1705,
10251
    SYSZ_INS_VAVGB = 1706,
10252
    SYSZ_INS_VAVGF = 1707,
10253
    SYSZ_INS_VAVGG = 1708,
10254
    SYSZ_INS_VAVGH = 1709,
10255
    SYSZ_INS_VAVGL = 1710,
10256
    SYSZ_INS_VAVGLB = 1711,
10257
    SYSZ_INS_VAVGLF = 1712,
10258
    SYSZ_INS_VAVGLG = 1713,
10259
    SYSZ_INS_VAVGLH = 1714,
10260
    SYSZ_INS_VBPERM = 1715,
10261
    SYSZ_INS_VCDG = 1716,
10262
    SYSZ_INS_VCDGB = 1717,
10263
    SYSZ_INS_VCDLG = 1718,
10264
    SYSZ_INS_VCDLGB = 1719,
10265
    SYSZ_INS_VCEQ = 1720,
10266
    SYSZ_INS_VCEQB = 1721,
10267
    SYSZ_INS_VCEQBS = 1722,
10268
    SYSZ_INS_VCEQF = 1723,
10269
    SYSZ_INS_VCEQFS = 1724,
10270
    SYSZ_INS_VCEQG = 1725,
10271
    SYSZ_INS_VCEQGS = 1726,
10272
    SYSZ_INS_VCEQH = 1727,
10273
    SYSZ_INS_VCEQHS = 1728,
10274
    SYSZ_INS_VCGD = 1729,
10275
    SYSZ_INS_VCGDB = 1730,
10276
    SYSZ_INS_VCH = 1731,
10277
    SYSZ_INS_VCHB = 1732,
10278
    SYSZ_INS_VCHBS = 1733,
10279
    SYSZ_INS_VCHF = 1734,
10280
    SYSZ_INS_VCHFS = 1735,
10281
    SYSZ_INS_VCHG = 1736,
10282
    SYSZ_INS_VCHGS = 1737,
10283
    SYSZ_INS_VCHH = 1738,
10284
    SYSZ_INS_VCHHS = 1739,
10285
    SYSZ_INS_VCHL = 1740,
10286
    SYSZ_INS_VCHLB = 1741,
10287
    SYSZ_INS_VCHLBS = 1742,
10288
    SYSZ_INS_VCHLF = 1743,
10289
    SYSZ_INS_VCHLFS = 1744,
10290
    SYSZ_INS_VCHLG = 1745,
10291
    SYSZ_INS_VCHLGS = 1746,
10292
    SYSZ_INS_VCHLH = 1747,
10293
    SYSZ_INS_VCHLHS = 1748,
10294
    SYSZ_INS_VCKSM = 1749,
10295
    SYSZ_INS_VCLGD = 1750,
10296
    SYSZ_INS_VCLGDB = 1751,
10297
    SYSZ_INS_VCLZ = 1752,
10298
    SYSZ_INS_VCLZB = 1753,
10299
    SYSZ_INS_VCLZF = 1754,
10300
    SYSZ_INS_VCLZG = 1755,
10301
    SYSZ_INS_VCLZH = 1756,
10302
    SYSZ_INS_VCP = 1757,
10303
    SYSZ_INS_VCTZ = 1758,
10304
    SYSZ_INS_VCTZB = 1759,
10305
    SYSZ_INS_VCTZF = 1760,
10306
    SYSZ_INS_VCTZG = 1761,
10307
    SYSZ_INS_VCTZH = 1762,
10308
    SYSZ_INS_VCVB = 1763,
10309
    SYSZ_INS_VCVBG = 1764,
10310
    SYSZ_INS_VCVD = 1765,
10311
    SYSZ_INS_VCVDG = 1766,
10312
    SYSZ_INS_VDP = 1767,
10313
    SYSZ_INS_VEC = 1768,
10314
    SYSZ_INS_VECB = 1769,
10315
    SYSZ_INS_VECF = 1770,
10316
    SYSZ_INS_VECG = 1771,
10317
    SYSZ_INS_VECH = 1772,
10318
    SYSZ_INS_VECL = 1773,
10319
    SYSZ_INS_VECLB = 1774,
10320
    SYSZ_INS_VECLF = 1775,
10321
    SYSZ_INS_VECLG = 1776,
10322
    SYSZ_INS_VECLH = 1777,
10323
    SYSZ_INS_VERIM = 1778,
10324
    SYSZ_INS_VERIMB = 1779,
10325
    SYSZ_INS_VERIMF = 1780,
10326
    SYSZ_INS_VERIMG = 1781,
10327
    SYSZ_INS_VERIMH = 1782,
10328
    SYSZ_INS_VERLL = 1783,
10329
    SYSZ_INS_VERLLB = 1784,
10330
    SYSZ_INS_VERLLF = 1785,
10331
    SYSZ_INS_VERLLG = 1786,
10332
    SYSZ_INS_VERLLH = 1787,
10333
    SYSZ_INS_VERLLV = 1788,
10334
    SYSZ_INS_VERLLVB = 1789,
10335
    SYSZ_INS_VERLLVF = 1790,
10336
    SYSZ_INS_VERLLVG = 1791,
10337
    SYSZ_INS_VERLLVH = 1792,
10338
    SYSZ_INS_VESL = 1793,
10339
    SYSZ_INS_VESLB = 1794,
10340
    SYSZ_INS_VESLF = 1795,
10341
    SYSZ_INS_VESLG = 1796,
10342
    SYSZ_INS_VESLH = 1797,
10343
    SYSZ_INS_VESLV = 1798,
10344
    SYSZ_INS_VESLVB = 1799,
10345
    SYSZ_INS_VESLVF = 1800,
10346
    SYSZ_INS_VESLVG = 1801,
10347
    SYSZ_INS_VESLVH = 1802,
10348
    SYSZ_INS_VESRA = 1803,
10349
    SYSZ_INS_VESRAB = 1804,
10350
    SYSZ_INS_VESRAF = 1805,
10351
    SYSZ_INS_VESRAG = 1806,
10352
    SYSZ_INS_VESRAH = 1807,
10353
    SYSZ_INS_VESRAV = 1808,
10354
    SYSZ_INS_VESRAVB = 1809,
10355
    SYSZ_INS_VESRAVF = 1810,
10356
    SYSZ_INS_VESRAVG = 1811,
10357
    SYSZ_INS_VESRAVH = 1812,
10358
    SYSZ_INS_VESRL = 1813,
10359
    SYSZ_INS_VESRLB = 1814,
10360
    SYSZ_INS_VESRLF = 1815,
10361
    SYSZ_INS_VESRLG = 1816,
10362
    SYSZ_INS_VESRLH = 1817,
10363
    SYSZ_INS_VESRLV = 1818,
10364
    SYSZ_INS_VESRLVB = 1819,
10365
    SYSZ_INS_VESRLVF = 1820,
10366
    SYSZ_INS_VESRLVG = 1821,
10367
    SYSZ_INS_VESRLVH = 1822,
10368
    SYSZ_INS_VFA = 1823,
10369
    SYSZ_INS_VFADB = 1824,
10370
    SYSZ_INS_VFAE = 1825,
10371
    SYSZ_INS_VFAEB = 1826,
10372
    SYSZ_INS_VFAEBS = 1827,
10373
    SYSZ_INS_VFAEF = 1828,
10374
    SYSZ_INS_VFAEFS = 1829,
10375
    SYSZ_INS_VFAEH = 1830,
10376
    SYSZ_INS_VFAEHS = 1831,
10377
    SYSZ_INS_VFAEZB = 1832,
10378
    SYSZ_INS_VFAEZBS = 1833,
10379
    SYSZ_INS_VFAEZF = 1834,
10380
    SYSZ_INS_VFAEZFS = 1835,
10381
    SYSZ_INS_VFAEZH = 1836,
10382
    SYSZ_INS_VFAEZHS = 1837,
10383
    SYSZ_INS_VFASB = 1838,
10384
    SYSZ_INS_VFCE = 1839,
10385
    SYSZ_INS_VFCEDB = 1840,
10386
    SYSZ_INS_VFCEDBS = 1841,
10387
    SYSZ_INS_VFCESB = 1842,
10388
    SYSZ_INS_VFCESBS = 1843,
10389
    SYSZ_INS_VFCH = 1844,
10390
    SYSZ_INS_VFCHDB = 1845,
10391
    SYSZ_INS_VFCHDBS = 1846,
10392
    SYSZ_INS_VFCHE = 1847,
10393
    SYSZ_INS_VFCHEDB = 1848,
10394
    SYSZ_INS_VFCHEDBS = 1849,
10395
    SYSZ_INS_VFCHESB = 1850,
10396
    SYSZ_INS_VFCHESBS = 1851,
10397
    SYSZ_INS_VFCHSB = 1852,
10398
    SYSZ_INS_VFCHSBS = 1853,
10399
    SYSZ_INS_VFD = 1854,
10400
    SYSZ_INS_VFDDB = 1855,
10401
    SYSZ_INS_VFDSB = 1856,
10402
    SYSZ_INS_VFEE = 1857,
10403
    SYSZ_INS_VFEEB = 1858,
10404
    SYSZ_INS_VFEEBS = 1859,
10405
    SYSZ_INS_VFEEF = 1860,
10406
    SYSZ_INS_VFEEFS = 1861,
10407
    SYSZ_INS_VFEEH = 1862,
10408
    SYSZ_INS_VFEEHS = 1863,
10409
    SYSZ_INS_VFEEZB = 1864,
10410
    SYSZ_INS_VFEEZBS = 1865,
10411
    SYSZ_INS_VFEEZF = 1866,
10412
    SYSZ_INS_VFEEZFS = 1867,
10413
    SYSZ_INS_VFEEZH = 1868,
10414
    SYSZ_INS_VFEEZHS = 1869,
10415
    SYSZ_INS_VFENE = 1870,
10416
    SYSZ_INS_VFENEB = 1871,
10417
    SYSZ_INS_VFENEBS = 1872,
10418
    SYSZ_INS_VFENEF = 1873,
10419
    SYSZ_INS_VFENEFS = 1874,
10420
    SYSZ_INS_VFENEH = 1875,
10421
    SYSZ_INS_VFENEHS = 1876,
10422
    SYSZ_INS_VFENEZB = 1877,
10423
    SYSZ_INS_VFENEZBS = 1878,
10424
    SYSZ_INS_VFENEZF = 1879,
10425
    SYSZ_INS_VFENEZFS = 1880,
10426
    SYSZ_INS_VFENEZH = 1881,
10427
    SYSZ_INS_VFENEZHS = 1882,
10428
    SYSZ_INS_VFI = 1883,
10429
    SYSZ_INS_VFIDB = 1884,
10430
    SYSZ_INS_VFISB = 1885,
10431
    SYSZ_INS_VFKEDB = 1886,
10432
    SYSZ_INS_VFKEDBS = 1887,
10433
    SYSZ_INS_VFKESB = 1888,
10434
    SYSZ_INS_VFKESBS = 1889,
10435
    SYSZ_INS_VFKHDB = 1890,
10436
    SYSZ_INS_VFKHDBS = 1891,
10437
    SYSZ_INS_VFKHEDB = 1892,
10438
    SYSZ_INS_VFKHEDBS = 1893,
10439
    SYSZ_INS_VFKHESB = 1894,
10440
    SYSZ_INS_VFKHESBS = 1895,
10441
    SYSZ_INS_VFKHSB = 1896,
10442
    SYSZ_INS_VFKHSBS = 1897,
10443
    SYSZ_INS_VFLCDB = 1898,
10444
    SYSZ_INS_VFLCSB = 1899,
10445
    SYSZ_INS_VFLL = 1900,
10446
    SYSZ_INS_VFLLS = 1901,
10447
    SYSZ_INS_VFLNDB = 1902,
10448
    SYSZ_INS_VFLNSB = 1903,
10449
    SYSZ_INS_VFLPDB = 1904,
10450
    SYSZ_INS_VFLPSB = 1905,
10451
    SYSZ_INS_VFLR = 1906,
10452
    SYSZ_INS_VFLRD = 1907,
10453
    SYSZ_INS_VFM = 1908,
10454
    SYSZ_INS_VFMA = 1909,
10455
    SYSZ_INS_VFMADB = 1910,
10456
    SYSZ_INS_VFMASB = 1911,
10457
    SYSZ_INS_VFMAX = 1912,
10458
    SYSZ_INS_VFMAXDB = 1913,
10459
    SYSZ_INS_VFMAXSB = 1914,
10460
    SYSZ_INS_VFMDB = 1915,
10461
    SYSZ_INS_VFMIN = 1916,
10462
    SYSZ_INS_VFMINDB = 1917,
10463
    SYSZ_INS_VFMINSB = 1918,
10464
    SYSZ_INS_VFMS = 1919,
10465
    SYSZ_INS_VFMSB = 1920,
10466
    SYSZ_INS_VFMSDB = 1921,
10467
    SYSZ_INS_VFMSSB = 1922,
10468
    SYSZ_INS_VFNMA = 1923,
10469
    SYSZ_INS_VFNMADB = 1924,
10470
    SYSZ_INS_VFNMASB = 1925,
10471
    SYSZ_INS_VFNMS = 1926,
10472
    SYSZ_INS_VFNMSDB = 1927,
10473
    SYSZ_INS_VFNMSSB = 1928,
10474
    SYSZ_INS_VFPSO = 1929,
10475
    SYSZ_INS_VFPSODB = 1930,
10476
    SYSZ_INS_VFPSOSB = 1931,
10477
    SYSZ_INS_VFS = 1932,
10478
    SYSZ_INS_VFSDB = 1933,
10479
    SYSZ_INS_VFSQ = 1934,
10480
    SYSZ_INS_VFSQDB = 1935,
10481
    SYSZ_INS_VFSQSB = 1936,
10482
    SYSZ_INS_VFSSB = 1937,
10483
    SYSZ_INS_VFTCI = 1938,
10484
    SYSZ_INS_VFTCIDB = 1939,
10485
    SYSZ_INS_VFTCISB = 1940,
10486
    SYSZ_INS_VGBM = 1941,
10487
    SYSZ_INS_VGEF = 1942,
10488
    SYSZ_INS_VGEG = 1943,
10489
    SYSZ_INS_VGFM = 1944,
10490
    SYSZ_INS_VGFMA = 1945,
10491
    SYSZ_INS_VGFMAB = 1946,
10492
    SYSZ_INS_VGFMAF = 1947,
10493
    SYSZ_INS_VGFMAG = 1948,
10494
    SYSZ_INS_VGFMAH = 1949,
10495
    SYSZ_INS_VGFMB = 1950,
10496
    SYSZ_INS_VGFMF = 1951,
10497
    SYSZ_INS_VGFMG = 1952,
10498
    SYSZ_INS_VGFMH = 1953,
10499
    SYSZ_INS_VGM = 1954,
10500
    SYSZ_INS_VGMB = 1955,
10501
    SYSZ_INS_VGMF = 1956,
10502
    SYSZ_INS_VGMG = 1957,
10503
    SYSZ_INS_VGMH = 1958,
10504
    SYSZ_INS_VISTR = 1959,
10505
    SYSZ_INS_VISTRB = 1960,
10506
    SYSZ_INS_VISTRBS = 1961,
10507
    SYSZ_INS_VISTRF = 1962,
10508
    SYSZ_INS_VISTRFS = 1963,
10509
    SYSZ_INS_VISTRH = 1964,
10510
    SYSZ_INS_VISTRHS = 1965,
10511
    SYSZ_INS_VL = 1966,
10512
    SYSZ_INS_VLBB = 1967,
10513
    SYSZ_INS_VLC = 1968,
10514
    SYSZ_INS_VLCB = 1969,
10515
    SYSZ_INS_VLCF = 1970,
10516
    SYSZ_INS_VLCG = 1971,
10517
    SYSZ_INS_VLCH = 1972,
10518
    SYSZ_INS_VLDE = 1973,
10519
    SYSZ_INS_VLDEB = 1974,
10520
    SYSZ_INS_VLEB = 1975,
10521
    SYSZ_INS_VLED = 1976,
10522
    SYSZ_INS_VLEDB = 1977,
10523
    SYSZ_INS_VLEF = 1978,
10524
    SYSZ_INS_VLEG = 1979,
10525
    SYSZ_INS_VLEH = 1980,
10526
    SYSZ_INS_VLEIB = 1981,
10527
    SYSZ_INS_VLEIF = 1982,
10528
    SYSZ_INS_VLEIG = 1983,
10529
    SYSZ_INS_VLEIH = 1984,
10530
    SYSZ_INS_VLGV = 1985,
10531
    SYSZ_INS_VLGVB = 1986,
10532
    SYSZ_INS_VLGVF = 1987,
10533
    SYSZ_INS_VLGVG = 1988,
10534
    SYSZ_INS_VLGVH = 1989,
10535
    SYSZ_INS_VLIP = 1990,
10536
    SYSZ_INS_VLL = 1991,
10537
    SYSZ_INS_VLLEZ = 1992,
10538
    SYSZ_INS_VLLEZB = 1993,
10539
    SYSZ_INS_VLLEZF = 1994,
10540
    SYSZ_INS_VLLEZG = 1995,
10541
    SYSZ_INS_VLLEZH = 1996,
10542
    SYSZ_INS_VLLEZLF = 1997,
10543
    SYSZ_INS_VLM = 1998,
10544
    SYSZ_INS_VLP = 1999,
10545
    SYSZ_INS_VLPB = 2000,
10546
    SYSZ_INS_VLPF = 2001,
10547
    SYSZ_INS_VLPG = 2002,
10548
    SYSZ_INS_VLPH = 2003,
10549
    SYSZ_INS_VLR = 2004,
10550
    SYSZ_INS_VLREP = 2005,
10551
    SYSZ_INS_VLREPB = 2006,
10552
    SYSZ_INS_VLREPF = 2007,
10553
    SYSZ_INS_VLREPG = 2008,
10554
    SYSZ_INS_VLREPH = 2009,
10555
    SYSZ_INS_VLRL = 2010,
10556
    SYSZ_INS_VLRLR = 2011,
10557
    SYSZ_INS_VLVG = 2012,
10558
    SYSZ_INS_VLVGB = 2013,
10559
    SYSZ_INS_VLVGF = 2014,
10560
    SYSZ_INS_VLVGG = 2015,
10561
    SYSZ_INS_VLVGH = 2016,
10562
    SYSZ_INS_VLVGP = 2017,
10563
    SYSZ_INS_VMAE = 2018,
10564
    SYSZ_INS_VMAEB = 2019,
10565
    SYSZ_INS_VMAEF = 2020,
10566
    SYSZ_INS_VMAEH = 2021,
10567
    SYSZ_INS_VMAH = 2022,
10568
    SYSZ_INS_VMAHB = 2023,
10569
    SYSZ_INS_VMAHF = 2024,
10570
    SYSZ_INS_VMAHH = 2025,
10571
    SYSZ_INS_VMAL = 2026,
10572
    SYSZ_INS_VMALB = 2027,
10573
    SYSZ_INS_VMALE = 2028,
10574
    SYSZ_INS_VMALEB = 2029,
10575
    SYSZ_INS_VMALEF = 2030,
10576
    SYSZ_INS_VMALEH = 2031,
10577
    SYSZ_INS_VMALF = 2032,
10578
    SYSZ_INS_VMALH = 2033,
10579
    SYSZ_INS_VMALHB = 2034,
10580
    SYSZ_INS_VMALHF = 2035,
10581
    SYSZ_INS_VMALHH = 2036,
10582
    SYSZ_INS_VMALHW = 2037,
10583
    SYSZ_INS_VMALO = 2038,
10584
    SYSZ_INS_VMALOB = 2039,
10585
    SYSZ_INS_VMALOF = 2040,
10586
    SYSZ_INS_VMALOH = 2041,
10587
    SYSZ_INS_VMAO = 2042,
10588
    SYSZ_INS_VMAOB = 2043,
10589
    SYSZ_INS_VMAOF = 2044,
10590
    SYSZ_INS_VMAOH = 2045,
10591
    SYSZ_INS_VME = 2046,
10592
    SYSZ_INS_VMEB = 2047,
10593
    SYSZ_INS_VMEF = 2048,
10594
    SYSZ_INS_VMEH = 2049,
10595
    SYSZ_INS_VMH = 2050,
10596
    SYSZ_INS_VMHB = 2051,
10597
    SYSZ_INS_VMHF = 2052,
10598
    SYSZ_INS_VMHH = 2053,
10599
    SYSZ_INS_VML = 2054,
10600
    SYSZ_INS_VMLB = 2055,
10601
    SYSZ_INS_VMLE = 2056,
10602
    SYSZ_INS_VMLEB = 2057,
10603
    SYSZ_INS_VMLEF = 2058,
10604
    SYSZ_INS_VMLEH = 2059,
10605
    SYSZ_INS_VMLF = 2060,
10606
    SYSZ_INS_VMLH = 2061,
10607
    SYSZ_INS_VMLHB = 2062,
10608
    SYSZ_INS_VMLHF = 2063,
10609
    SYSZ_INS_VMLHH = 2064,
10610
    SYSZ_INS_VMLHW = 2065,
10611
    SYSZ_INS_VMLO = 2066,
10612
    SYSZ_INS_VMLOB = 2067,
10613
    SYSZ_INS_VMLOF = 2068,
10614
    SYSZ_INS_VMLOH = 2069,
10615
    SYSZ_INS_VMN = 2070,
10616
    SYSZ_INS_VMNB = 2071,
10617
    SYSZ_INS_VMNF = 2072,
10618
    SYSZ_INS_VMNG = 2073,
10619
    SYSZ_INS_VMNH = 2074,
10620
    SYSZ_INS_VMNL = 2075,
10621
    SYSZ_INS_VMNLB = 2076,
10622
    SYSZ_INS_VMNLF = 2077,
10623
    SYSZ_INS_VMNLG = 2078,
10624
    SYSZ_INS_VMNLH = 2079,
10625
    SYSZ_INS_VMO = 2080,
10626
    SYSZ_INS_VMOB = 2081,
10627
    SYSZ_INS_VMOF = 2082,
10628
    SYSZ_INS_VMOH = 2083,
10629
    SYSZ_INS_VMP = 2084,
10630
    SYSZ_INS_VMRH = 2085,
10631
    SYSZ_INS_VMRHB = 2086,
10632
    SYSZ_INS_VMRHF = 2087,
10633
    SYSZ_INS_VMRHG = 2088,
10634
    SYSZ_INS_VMRHH = 2089,
10635
    SYSZ_INS_VMRL = 2090,
10636
    SYSZ_INS_VMRLB = 2091,
10637
    SYSZ_INS_VMRLF = 2092,
10638
    SYSZ_INS_VMRLG = 2093,
10639
    SYSZ_INS_VMRLH = 2094,
10640
    SYSZ_INS_VMSL = 2095,
10641
    SYSZ_INS_VMSLG = 2096,
10642
    SYSZ_INS_VMSP = 2097,
10643
    SYSZ_INS_VMX = 2098,
10644
    SYSZ_INS_VMXB = 2099,
10645
    SYSZ_INS_VMXF = 2100,
10646
    SYSZ_INS_VMXG = 2101,
10647
    SYSZ_INS_VMXH = 2102,
10648
    SYSZ_INS_VMXL = 2103,
10649
    SYSZ_INS_VMXLB = 2104,
10650
    SYSZ_INS_VMXLF = 2105,
10651
    SYSZ_INS_VMXLG = 2106,
10652
    SYSZ_INS_VMXLH = 2107,
10653
    SYSZ_INS_VN = 2108,
10654
    SYSZ_INS_VNC = 2109,
10655
    SYSZ_INS_VNN = 2110,
10656
    SYSZ_INS_VNO = 2111,
10657
    SYSZ_INS_VNX = 2112,
10658
    SYSZ_INS_VO = 2113,
10659
    SYSZ_INS_VOC = 2114,
10660
    SYSZ_INS_VONE = 2115,
10661
    SYSZ_INS_VPDI = 2116,
10662
    SYSZ_INS_VPERM = 2117,
10663
    SYSZ_INS_VPK = 2118,
10664
    SYSZ_INS_VPKF = 2119,
10665
    SYSZ_INS_VPKG = 2120,
10666
    SYSZ_INS_VPKH = 2121,
10667
    SYSZ_INS_VPKLS = 2122,
10668
    SYSZ_INS_VPKLSF = 2123,
10669
    SYSZ_INS_VPKLSFS = 2124,
10670
    SYSZ_INS_VPKLSG = 2125,
10671
    SYSZ_INS_VPKLSGS = 2126,
10672
    SYSZ_INS_VPKLSH = 2127,
10673
    SYSZ_INS_VPKLSHS = 2128,
10674
    SYSZ_INS_VPKS = 2129,
10675
    SYSZ_INS_VPKSF = 2130,
10676
    SYSZ_INS_VPKSFS = 2131,
10677
    SYSZ_INS_VPKSG = 2132,
10678
    SYSZ_INS_VPKSGS = 2133,
10679
    SYSZ_INS_VPKSH = 2134,
10680
    SYSZ_INS_VPKSHS = 2135,
10681
    SYSZ_INS_VPKZ = 2136,
10682
    SYSZ_INS_VPOPCT = 2137,
10683
    SYSZ_INS_VPOPCTB = 2138,
10684
    SYSZ_INS_VPOPCTF = 2139,
10685
    SYSZ_INS_VPOPCTG = 2140,
10686
    SYSZ_INS_VPOPCTH = 2141,
10687
    SYSZ_INS_VPSOP = 2142,
10688
    SYSZ_INS_VREP = 2143,
10689
    SYSZ_INS_VREPB = 2144,
10690
    SYSZ_INS_VREPF = 2145,
10691
    SYSZ_INS_VREPG = 2146,
10692
    SYSZ_INS_VREPH = 2147,
10693
    SYSZ_INS_VREPI = 2148,
10694
    SYSZ_INS_VREPIB = 2149,
10695
    SYSZ_INS_VREPIF = 2150,
10696
    SYSZ_INS_VREPIG = 2151,
10697
    SYSZ_INS_VREPIH = 2152,
10698
    SYSZ_INS_VRP = 2153,
10699
    SYSZ_INS_VS = 2154,
10700
    SYSZ_INS_VSB = 2155,
10701
    SYSZ_INS_VSBCBI = 2156,
10702
    SYSZ_INS_VSBCBIQ = 2157,
10703
    SYSZ_INS_VSBI = 2158,
10704
    SYSZ_INS_VSBIQ = 2159,
10705
    SYSZ_INS_VSCBI = 2160,
10706
    SYSZ_INS_VSCBIB = 2161,
10707
    SYSZ_INS_VSCBIF = 2162,
10708
    SYSZ_INS_VSCBIG = 2163,
10709
    SYSZ_INS_VSCBIH = 2164,
10710
    SYSZ_INS_VSCBIQ = 2165,
10711
    SYSZ_INS_VSCEF = 2166,
10712
    SYSZ_INS_VSCEG = 2167,
10713
    SYSZ_INS_VSDP = 2168,
10714
    SYSZ_INS_VSEG = 2169,
10715
    SYSZ_INS_VSEGB = 2170,
10716
    SYSZ_INS_VSEGF = 2171,
10717
    SYSZ_INS_VSEGH = 2172,
10718
    SYSZ_INS_VSEL = 2173,
10719
    SYSZ_INS_VSF = 2174,
10720
    SYSZ_INS_VSG = 2175,
10721
    SYSZ_INS_VSH = 2176,
10722
    SYSZ_INS_VSL = 2177,
10723
    SYSZ_INS_VSLB = 2178,
10724
    SYSZ_INS_VSLDB = 2179,
10725
    SYSZ_INS_VSP = 2180,
10726
    SYSZ_INS_VSQ = 2181,
10727
    SYSZ_INS_VSRA = 2182,
10728
    SYSZ_INS_VSRAB = 2183,
10729
    SYSZ_INS_VSRL = 2184,
10730
    SYSZ_INS_VSRLB = 2185,
10731
    SYSZ_INS_VSRP = 2186,
10732
    SYSZ_INS_VST = 2187,
10733
    SYSZ_INS_VSTEB = 2188,
10734
    SYSZ_INS_VSTEF = 2189,
10735
    SYSZ_INS_VSTEG = 2190,
10736
    SYSZ_INS_VSTEH = 2191,
10737
    SYSZ_INS_VSTL = 2192,
10738
    SYSZ_INS_VSTM = 2193,
10739
    SYSZ_INS_VSTRC = 2194,
10740
    SYSZ_INS_VSTRCB = 2195,
10741
    SYSZ_INS_VSTRCBS = 2196,
10742
    SYSZ_INS_VSTRCF = 2197,
10743
    SYSZ_INS_VSTRCFS = 2198,
10744
    SYSZ_INS_VSTRCH = 2199,
10745
    SYSZ_INS_VSTRCHS = 2200,
10746
    SYSZ_INS_VSTRCZB = 2201,
10747
    SYSZ_INS_VSTRCZBS = 2202,
10748
    SYSZ_INS_VSTRCZF = 2203,
10749
    SYSZ_INS_VSTRCZFS = 2204,
10750
    SYSZ_INS_VSTRCZH = 2205,
10751
    SYSZ_INS_VSTRCZHS = 2206,
10752
    SYSZ_INS_VSTRL = 2207,
10753
    SYSZ_INS_VSTRLR = 2208,
10754
    SYSZ_INS_VSUM = 2209,
10755
    SYSZ_INS_VSUMB = 2210,
10756
    SYSZ_INS_VSUMG = 2211,
10757
    SYSZ_INS_VSUMGF = 2212,
10758
    SYSZ_INS_VSUMGH = 2213,
10759
    SYSZ_INS_VSUMH = 2214,
10760
    SYSZ_INS_VSUMQ = 2215,
10761
    SYSZ_INS_VSUMQF = 2216,
10762
    SYSZ_INS_VSUMQG = 2217,
10763
    SYSZ_INS_VTM = 2218,
10764
    SYSZ_INS_VTP = 2219,
10765
    SYSZ_INS_VUPH = 2220,
10766
    SYSZ_INS_VUPHB = 2221,
10767
    SYSZ_INS_VUPHF = 2222,
10768
    SYSZ_INS_VUPHH = 2223,
10769
    SYSZ_INS_VUPKZ = 2224,
10770
    SYSZ_INS_VUPL = 2225,
10771
    SYSZ_INS_VUPLB = 2226,
10772
    SYSZ_INS_VUPLF = 2227,
10773
    SYSZ_INS_VUPLH = 2228,
10774
    SYSZ_INS_VUPLHB = 2229,
10775
    SYSZ_INS_VUPLHF = 2230,
10776
    SYSZ_INS_VUPLHH = 2231,
10777
    SYSZ_INS_VUPLHW = 2232,
10778
    SYSZ_INS_VUPLL = 2233,
10779
    SYSZ_INS_VUPLLB = 2234,
10780
    SYSZ_INS_VUPLLF = 2235,
10781
    SYSZ_INS_VUPLLH = 2236,
10782
    SYSZ_INS_VX = 2237,
10783
    SYSZ_INS_VZERO = 2238,
10784
    SYSZ_INS_WCDGB = 2239,
10785
    SYSZ_INS_WCDLGB = 2240,
10786
    SYSZ_INS_WCGDB = 2241,
10787
    SYSZ_INS_WCLGDB = 2242,
10788
    SYSZ_INS_WFADB = 2243,
10789
    SYSZ_INS_WFASB = 2244,
10790
    SYSZ_INS_WFAXB = 2245,
10791
    SYSZ_INS_WFC = 2246,
10792
    SYSZ_INS_WFCDB = 2247,
10793
    SYSZ_INS_WFCEDB = 2248,
10794
    SYSZ_INS_WFCEDBS = 2249,
10795
    SYSZ_INS_WFCESB = 2250,
10796
    SYSZ_INS_WFCESBS = 2251,
10797
    SYSZ_INS_WFCEXB = 2252,
10798
    SYSZ_INS_WFCEXBS = 2253,
10799
    SYSZ_INS_WFCHDB = 2254,
10800
    SYSZ_INS_WFCHDBS = 2255,
10801
    SYSZ_INS_WFCHEDB = 2256,
10802
    SYSZ_INS_WFCHEDBS = 2257,
10803
    SYSZ_INS_WFCHESB = 2258,
10804
    SYSZ_INS_WFCHESBS = 2259,
10805
    SYSZ_INS_WFCHEXB = 2260,
10806
    SYSZ_INS_WFCHEXBS = 2261,
10807
    SYSZ_INS_WFCHSB = 2262,
10808
    SYSZ_INS_WFCHSBS = 2263,
10809
    SYSZ_INS_WFCHXB = 2264,
10810
    SYSZ_INS_WFCHXBS = 2265,
10811
    SYSZ_INS_WFCSB = 2266,
10812
    SYSZ_INS_WFCXB = 2267,
10813
    SYSZ_INS_WFDDB = 2268,
10814
    SYSZ_INS_WFDSB = 2269,
10815
    SYSZ_INS_WFDXB = 2270,
10816
    SYSZ_INS_WFIDB = 2271,
10817
    SYSZ_INS_WFISB = 2272,
10818
    SYSZ_INS_WFIXB = 2273,
10819
    SYSZ_INS_WFK = 2274,
10820
    SYSZ_INS_WFKDB = 2275,
10821
    SYSZ_INS_WFKEDB = 2276,
10822
    SYSZ_INS_WFKEDBS = 2277,
10823
    SYSZ_INS_WFKESB = 2278,
10824
    SYSZ_INS_WFKESBS = 2279,
10825
    SYSZ_INS_WFKEXB = 2280,
10826
    SYSZ_INS_WFKEXBS = 2281,
10827
    SYSZ_INS_WFKHDB = 2282,
10828
    SYSZ_INS_WFKHDBS = 2283,
10829
    SYSZ_INS_WFKHEDB = 2284,
10830
    SYSZ_INS_WFKHEDBS = 2285,
10831
    SYSZ_INS_WFKHESB = 2286,
10832
    SYSZ_INS_WFKHESBS = 2287,
10833
    SYSZ_INS_WFKHEXB = 2288,
10834
    SYSZ_INS_WFKHEXBS = 2289,
10835
    SYSZ_INS_WFKHSB = 2290,
10836
    SYSZ_INS_WFKHSBS = 2291,
10837
    SYSZ_INS_WFKHXB = 2292,
10838
    SYSZ_INS_WFKHXBS = 2293,
10839
    SYSZ_INS_WFKSB = 2294,
10840
    SYSZ_INS_WFKXB = 2295,
10841
    SYSZ_INS_WFLCDB = 2296,
10842
    SYSZ_INS_WFLCSB = 2297,
10843
    SYSZ_INS_WFLCXB = 2298,
10844
    SYSZ_INS_WFLLD = 2299,
10845
    SYSZ_INS_WFLLS = 2300,
10846
    SYSZ_INS_WFLNDB = 2301,
10847
    SYSZ_INS_WFLNSB = 2302,
10848
    SYSZ_INS_WFLNXB = 2303,
10849
    SYSZ_INS_WFLPDB = 2304,
10850
    SYSZ_INS_WFLPSB = 2305,
10851
    SYSZ_INS_WFLPXB = 2306,
10852
    SYSZ_INS_WFLRD = 2307,
10853
    SYSZ_INS_WFLRX = 2308,
10854
    SYSZ_INS_WFMADB = 2309,
10855
    SYSZ_INS_WFMASB = 2310,
10856
    SYSZ_INS_WFMAXB = 2311,
10857
    SYSZ_INS_WFMAXDB = 2312,
10858
    SYSZ_INS_WFMAXSB = 2313,
10859
    SYSZ_INS_WFMAXXB = 2314,
10860
    SYSZ_INS_WFMDB = 2315,
10861
    SYSZ_INS_WFMINDB = 2316,
10862
    SYSZ_INS_WFMINSB = 2317,
10863
    SYSZ_INS_WFMINXB = 2318,
10864
    SYSZ_INS_WFMSB = 2319,
10865
    SYSZ_INS_WFMSDB = 2320,
10866
    SYSZ_INS_WFMSSB = 2321,
10867
    SYSZ_INS_WFMSXB = 2322,
10868
    SYSZ_INS_WFMXB = 2323,
10869
    SYSZ_INS_WFNMADB = 2324,
10870
    SYSZ_INS_WFNMASB = 2325,
10871
    SYSZ_INS_WFNMAXB = 2326,
10872
    SYSZ_INS_WFNMSDB = 2327,
10873
    SYSZ_INS_WFNMSSB = 2328,
10874
    SYSZ_INS_WFNMSXB = 2329,
10875
    SYSZ_INS_WFPSODB = 2330,
10876
    SYSZ_INS_WFPSOSB = 2331,
10877
    SYSZ_INS_WFPSOXB = 2332,
10878
    SYSZ_INS_WFSDB = 2333,
10879
    SYSZ_INS_WFSQDB = 2334,
10880
    SYSZ_INS_WFSQSB = 2335,
10881
    SYSZ_INS_WFSQXB = 2336,
10882
    SYSZ_INS_WFSSB = 2337,
10883
    SYSZ_INS_WFSXB = 2338,
10884
    SYSZ_INS_WFTCIDB = 2339,
10885
    SYSZ_INS_WFTCISB = 2340,
10886
    SYSZ_INS_WFTCIXB = 2341,
10887
    SYSZ_INS_WLDEB = 2342,
10888
    SYSZ_INS_WLEDB = 2343,
10889
    SYSZ_INS_XSCH = 2344,
10890
    SYSZ_INS_ZAP = 2345,
10891
    SYSZ_INS_ENDING = 2346,
10892
}
10893
pub mod sysz_insn_group {
10894
    #[doc = " Group of SystemZ instructions"]
10895
    pub type Type = libc::c_uint;
10896
    #[doc = "< = CS_GRP_INVALID"]
10897
    pub const SYSZ_GRP_INVALID: Type = 0;
10898
    #[doc = "< = CS_GRP_JUMP"]
10899
    pub const SYSZ_GRP_JUMP: Type = 1;
10900
    pub const SYSZ_GRP_DISTINCTOPS: Type = 128;
10901
    pub const SYSZ_GRP_FPEXTENSION: Type = 129;
10902
    pub const SYSZ_GRP_HIGHWORD: Type = 130;
10903
    pub const SYSZ_GRP_INTERLOCKEDACCESS1: Type = 131;
10904
    pub const SYSZ_GRP_LOADSTOREONCOND: Type = 132;
10905
    pub const SYSZ_GRP_DFPPACKEDCONVERSION: Type = 133;
10906
    pub const SYSZ_GRP_DFPZONEDCONVERSION: Type = 134;
10907
    pub const SYSZ_GRP_ENHANCEDDAT2: Type = 135;
10908
    pub const SYSZ_GRP_EXECUTIONHINT: Type = 136;
10909
    pub const SYSZ_GRP_GUARDEDSTORAGE: Type = 137;
10910
    pub const SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE: Type = 138;
10911
    pub const SYSZ_GRP_LOADANDTRAP: Type = 139;
10912
    pub const SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE: Type = 140;
10913
    pub const SYSZ_GRP_LOADSTOREONCOND2: Type = 141;
10914
    pub const SYSZ_GRP_MESSAGESECURITYASSIST3: Type = 142;
10915
    pub const SYSZ_GRP_MESSAGESECURITYASSIST4: Type = 143;
10916
    pub const SYSZ_GRP_MESSAGESECURITYASSIST5: Type = 144;
10917
    pub const SYSZ_GRP_MESSAGESECURITYASSIST7: Type = 145;
10918
    pub const SYSZ_GRP_MESSAGESECURITYASSIST8: Type = 146;
10919
    pub const SYSZ_GRP_MISCELLANEOUSEXTENSIONS: Type = 147;
10920
    pub const SYSZ_GRP_MISCELLANEOUSEXTENSIONS2: Type = 148;
10921
    pub const SYSZ_GRP_NOVECTOR: Type = 149;
10922
    pub const SYSZ_GRP_POPULATIONCOUNT: Type = 150;
10923
    pub const SYSZ_GRP_PROCESSORASSIST: Type = 151;
10924
    pub const SYSZ_GRP_RESETREFERENCEBITSMULTIPLE: Type = 152;
10925
    pub const SYSZ_GRP_TRANSACTIONALEXECUTION: Type = 153;
10926
    pub const SYSZ_GRP_VECTOR: Type = 154;
10927
    pub const SYSZ_GRP_VECTORENHANCEMENTS1: Type = 155;
10928
    pub const SYSZ_GRP_VECTORPACKEDDECIMAL: Type = 156;
10929
    pub const SYSZ_GRP_ENDING: Type = 157;
10930
}
10931
pub mod x86_reg {
10932
    #[doc = " X86 registers"]
10933
    pub type Type = libc::c_uint;
10934
    pub const X86_REG_INVALID: Type = 0;
10935
    pub const X86_REG_AH: Type = 1;
10936
    pub const X86_REG_AL: Type = 2;
10937
    pub const X86_REG_AX: Type = 3;
10938
    pub const X86_REG_BH: Type = 4;
10939
    pub const X86_REG_BL: Type = 5;
10940
    pub const X86_REG_BP: Type = 6;
10941
    pub const X86_REG_BPL: Type = 7;
10942
    pub const X86_REG_BX: Type = 8;
10943
    pub const X86_REG_CH: Type = 9;
10944
    pub const X86_REG_CL: Type = 10;
10945
    pub const X86_REG_CS: Type = 11;
10946
    pub const X86_REG_CX: Type = 12;
10947
    pub const X86_REG_DH: Type = 13;
10948
    pub const X86_REG_DI: Type = 14;
10949
    pub const X86_REG_DIL: Type = 15;
10950
    pub const X86_REG_DL: Type = 16;
10951
    pub const X86_REG_DS: Type = 17;
10952
    pub const X86_REG_DX: Type = 18;
10953
    pub const X86_REG_EAX: Type = 19;
10954
    pub const X86_REG_EBP: Type = 20;
10955
    pub const X86_REG_EBX: Type = 21;
10956
    pub const X86_REG_ECX: Type = 22;
10957
    pub const X86_REG_EDI: Type = 23;
10958
    pub const X86_REG_EDX: Type = 24;
10959
    pub const X86_REG_EFLAGS: Type = 25;
10960
    pub const X86_REG_EIP: Type = 26;
10961
    pub const X86_REG_EIZ: Type = 27;
10962
    pub const X86_REG_ES: Type = 28;
10963
    pub const X86_REG_ESI: Type = 29;
10964
    pub const X86_REG_ESP: Type = 30;
10965
    pub const X86_REG_FPSW: Type = 31;
10966
    pub const X86_REG_FS: Type = 32;
10967
    pub const X86_REG_GS: Type = 33;
10968
    pub const X86_REG_IP: Type = 34;
10969
    pub const X86_REG_RAX: Type = 35;
10970
    pub const X86_REG_RBP: Type = 36;
10971
    pub const X86_REG_RBX: Type = 37;
10972
    pub const X86_REG_RCX: Type = 38;
10973
    pub const X86_REG_RDI: Type = 39;
10974
    pub const X86_REG_RDX: Type = 40;
10975
    pub const X86_REG_RIP: Type = 41;
10976
    pub const X86_REG_RIZ: Type = 42;
10977
    pub const X86_REG_RSI: Type = 43;
10978
    pub const X86_REG_RSP: Type = 44;
10979
    pub const X86_REG_SI: Type = 45;
10980
    pub const X86_REG_SIL: Type = 46;
10981
    pub const X86_REG_SP: Type = 47;
10982
    pub const X86_REG_SPL: Type = 48;
10983
    pub const X86_REG_SS: Type = 49;
10984
    pub const X86_REG_CR0: Type = 50;
10985
    pub const X86_REG_CR1: Type = 51;
10986
    pub const X86_REG_CR2: Type = 52;
10987
    pub const X86_REG_CR3: Type = 53;
10988
    pub const X86_REG_CR4: Type = 54;
10989
    pub const X86_REG_CR5: Type = 55;
10990
    pub const X86_REG_CR6: Type = 56;
10991
    pub const X86_REG_CR7: Type = 57;
10992
    pub const X86_REG_CR8: Type = 58;
10993
    pub const X86_REG_CR9: Type = 59;
10994
    pub const X86_REG_CR10: Type = 60;
10995
    pub const X86_REG_CR11: Type = 61;
10996
    pub const X86_REG_CR12: Type = 62;
10997
    pub const X86_REG_CR13: Type = 63;
10998
    pub const X86_REG_CR14: Type = 64;
10999
    pub const X86_REG_CR15: Type = 65;
11000
    pub const X86_REG_DR0: Type = 66;
11001
    pub const X86_REG_DR1: Type = 67;
11002
    pub const X86_REG_DR2: Type = 68;
11003
    pub const X86_REG_DR3: Type = 69;
11004
    pub const X86_REG_DR4: Type = 70;
11005
    pub const X86_REG_DR5: Type = 71;
11006
    pub const X86_REG_DR6: Type = 72;
11007
    pub const X86_REG_DR7: Type = 73;
11008
    pub const X86_REG_DR8: Type = 74;
11009
    pub const X86_REG_DR9: Type = 75;
11010
    pub const X86_REG_DR10: Type = 76;
11011
    pub const X86_REG_DR11: Type = 77;
11012
    pub const X86_REG_DR12: Type = 78;
11013
    pub const X86_REG_DR13: Type = 79;
11014
    pub const X86_REG_DR14: Type = 80;
11015
    pub const X86_REG_DR15: Type = 81;
11016
    pub const X86_REG_FP0: Type = 82;
11017
    pub const X86_REG_FP1: Type = 83;
11018
    pub const X86_REG_FP2: Type = 84;
11019
    pub const X86_REG_FP3: Type = 85;
11020
    pub const X86_REG_FP4: Type = 86;
11021
    pub const X86_REG_FP5: Type = 87;
11022
    pub const X86_REG_FP6: Type = 88;
11023
    pub const X86_REG_FP7: Type = 89;
11024
    pub const X86_REG_K0: Type = 90;
11025
    pub const X86_REG_K1: Type = 91;
11026
    pub const X86_REG_K2: Type = 92;
11027
    pub const X86_REG_K3: Type = 93;
11028
    pub const X86_REG_K4: Type = 94;
11029
    pub const X86_REG_K5: Type = 95;
11030
    pub const X86_REG_K6: Type = 96;
11031
    pub const X86_REG_K7: Type = 97;
11032
    pub const X86_REG_MM0: Type = 98;
11033
    pub const X86_REG_MM1: Type = 99;
11034
    pub const X86_REG_MM2: Type = 100;
11035
    pub const X86_REG_MM3: Type = 101;
11036
    pub const X86_REG_MM4: Type = 102;
11037
    pub const X86_REG_MM5: Type = 103;
11038
    pub const X86_REG_MM6: Type = 104;
11039
    pub const X86_REG_MM7: Type = 105;
11040
    pub const X86_REG_R8: Type = 106;
11041
    pub const X86_REG_R9: Type = 107;
11042
    pub const X86_REG_R10: Type = 108;
11043
    pub const X86_REG_R11: Type = 109;
11044
    pub const X86_REG_R12: Type = 110;
11045
    pub const X86_REG_R13: Type = 111;
11046
    pub const X86_REG_R14: Type = 112;
11047
    pub const X86_REG_R15: Type = 113;
11048
    pub const X86_REG_ST0: Type = 114;
11049
    pub const X86_REG_ST1: Type = 115;
11050
    pub const X86_REG_ST2: Type = 116;
11051
    pub const X86_REG_ST3: Type = 117;
11052
    pub const X86_REG_ST4: Type = 118;
11053
    pub const X86_REG_ST5: Type = 119;
11054
    pub const X86_REG_ST6: Type = 120;
11055
    pub const X86_REG_ST7: Type = 121;
11056
    pub const X86_REG_XMM0: Type = 122;
11057
    pub const X86_REG_XMM1: Type = 123;
11058
    pub const X86_REG_XMM2: Type = 124;
11059
    pub const X86_REG_XMM3: Type = 125;
11060
    pub const X86_REG_XMM4: Type = 126;
11061
    pub const X86_REG_XMM5: Type = 127;
11062
    pub const X86_REG_XMM6: Type = 128;
11063
    pub const X86_REG_XMM7: Type = 129;
11064
    pub const X86_REG_XMM8: Type = 130;
11065
    pub const X86_REG_XMM9: Type = 131;
11066
    pub const X86_REG_XMM10: Type = 132;
11067
    pub const X86_REG_XMM11: Type = 133;
11068
    pub const X86_REG_XMM12: Type = 134;
11069
    pub const X86_REG_XMM13: Type = 135;
11070
    pub const X86_REG_XMM14: Type = 136;
11071
    pub const X86_REG_XMM15: Type = 137;
11072
    pub const X86_REG_XMM16: Type = 138;
11073
    pub const X86_REG_XMM17: Type = 139;
11074
    pub const X86_REG_XMM18: Type = 140;
11075
    pub const X86_REG_XMM19: Type = 141;
11076
    pub const X86_REG_XMM20: Type = 142;
11077
    pub const X86_REG_XMM21: Type = 143;
11078
    pub const X86_REG_XMM22: Type = 144;
11079
    pub const X86_REG_XMM23: Type = 145;
11080
    pub const X86_REG_XMM24: Type = 146;
11081
    pub const X86_REG_XMM25: Type = 147;
11082
    pub const X86_REG_XMM26: Type = 148;
11083
    pub const X86_REG_XMM27: Type = 149;
11084
    pub const X86_REG_XMM28: Type = 150;
11085
    pub const X86_REG_XMM29: Type = 151;
11086
    pub const X86_REG_XMM30: Type = 152;
11087
    pub const X86_REG_XMM31: Type = 153;
11088
    pub const X86_REG_YMM0: Type = 154;
11089
    pub const X86_REG_YMM1: Type = 155;
11090
    pub const X86_REG_YMM2: Type = 156;
11091
    pub const X86_REG_YMM3: Type = 157;
11092
    pub const X86_REG_YMM4: Type = 158;
11093
    pub const X86_REG_YMM5: Type = 159;
11094
    pub const X86_REG_YMM6: Type = 160;
11095
    pub const X86_REG_YMM7: Type = 161;
11096
    pub const X86_REG_YMM8: Type = 162;
11097
    pub const X86_REG_YMM9: Type = 163;
11098
    pub const X86_REG_YMM10: Type = 164;
11099
    pub const X86_REG_YMM11: Type = 165;
11100
    pub const X86_REG_YMM12: Type = 166;
11101
    pub const X86_REG_YMM13: Type = 167;
11102
    pub const X86_REG_YMM14: Type = 168;
11103
    pub const X86_REG_YMM15: Type = 169;
11104
    pub const X86_REG_YMM16: Type = 170;
11105
    pub const X86_REG_YMM17: Type = 171;
11106
    pub const X86_REG_YMM18: Type = 172;
11107
    pub const X86_REG_YMM19: Type = 173;
11108
    pub const X86_REG_YMM20: Type = 174;
11109
    pub const X86_REG_YMM21: Type = 175;
11110
    pub const X86_REG_YMM22: Type = 176;
11111
    pub const X86_REG_YMM23: Type = 177;
11112
    pub const X86_REG_YMM24: Type = 178;
11113
    pub const X86_REG_YMM25: Type = 179;
11114
    pub const X86_REG_YMM26: Type = 180;
11115
    pub const X86_REG_YMM27: Type = 181;
11116
    pub const X86_REG_YMM28: Type = 182;
11117
    pub const X86_REG_YMM29: Type = 183;
11118
    pub const X86_REG_YMM30: Type = 184;
11119
    pub const X86_REG_YMM31: Type = 185;
11120
    pub const X86_REG_ZMM0: Type = 186;
11121
    pub const X86_REG_ZMM1: Type = 187;
11122
    pub const X86_REG_ZMM2: Type = 188;
11123
    pub const X86_REG_ZMM3: Type = 189;
11124
    pub const X86_REG_ZMM4: Type = 190;
11125
    pub const X86_REG_ZMM5: Type = 191;
11126
    pub const X86_REG_ZMM6: Type = 192;
11127
    pub const X86_REG_ZMM7: Type = 193;
11128
    pub const X86_REG_ZMM8: Type = 194;
11129
    pub const X86_REG_ZMM9: Type = 195;
11130
    pub const X86_REG_ZMM10: Type = 196;
11131
    pub const X86_REG_ZMM11: Type = 197;
11132
    pub const X86_REG_ZMM12: Type = 198;
11133
    pub const X86_REG_ZMM13: Type = 199;
11134
    pub const X86_REG_ZMM14: Type = 200;
11135
    pub const X86_REG_ZMM15: Type = 201;
11136
    pub const X86_REG_ZMM16: Type = 202;
11137
    pub const X86_REG_ZMM17: Type = 203;
11138
    pub const X86_REG_ZMM18: Type = 204;
11139
    pub const X86_REG_ZMM19: Type = 205;
11140
    pub const X86_REG_ZMM20: Type = 206;
11141
    pub const X86_REG_ZMM21: Type = 207;
11142
    pub const X86_REG_ZMM22: Type = 208;
11143
    pub const X86_REG_ZMM23: Type = 209;
11144
    pub const X86_REG_ZMM24: Type = 210;
11145
    pub const X86_REG_ZMM25: Type = 211;
11146
    pub const X86_REG_ZMM26: Type = 212;
11147
    pub const X86_REG_ZMM27: Type = 213;
11148
    pub const X86_REG_ZMM28: Type = 214;
11149
    pub const X86_REG_ZMM29: Type = 215;
11150
    pub const X86_REG_ZMM30: Type = 216;
11151
    pub const X86_REG_ZMM31: Type = 217;
11152
    pub const X86_REG_R8B: Type = 218;
11153
    pub const X86_REG_R9B: Type = 219;
11154
    pub const X86_REG_R10B: Type = 220;
11155
    pub const X86_REG_R11B: Type = 221;
11156
    pub const X86_REG_R12B: Type = 222;
11157
    pub const X86_REG_R13B: Type = 223;
11158
    pub const X86_REG_R14B: Type = 224;
11159
    pub const X86_REG_R15B: Type = 225;
11160
    pub const X86_REG_R8D: Type = 226;
11161
    pub const X86_REG_R9D: Type = 227;
11162
    pub const X86_REG_R10D: Type = 228;
11163
    pub const X86_REG_R11D: Type = 229;
11164
    pub const X86_REG_R12D: Type = 230;
11165
    pub const X86_REG_R13D: Type = 231;
11166
    pub const X86_REG_R14D: Type = 232;
11167
    pub const X86_REG_R15D: Type = 233;
11168
    pub const X86_REG_R8W: Type = 234;
11169
    pub const X86_REG_R9W: Type = 235;
11170
    pub const X86_REG_R10W: Type = 236;
11171
    pub const X86_REG_R11W: Type = 237;
11172
    pub const X86_REG_R12W: Type = 238;
11173
    pub const X86_REG_R13W: Type = 239;
11174
    pub const X86_REG_R14W: Type = 240;
11175
    pub const X86_REG_R15W: Type = 241;
11176
    pub const X86_REG_BND0: Type = 242;
11177
    pub const X86_REG_BND1: Type = 243;
11178
    pub const X86_REG_BND2: Type = 244;
11179
    pub const X86_REG_BND3: Type = 245;
11180
    pub const X86_REG_ENDING: Type = 246;
11181
}
11182
#[repr(u32)]
11183
#[doc = " Operand type for instruction's operands"]
11184
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
11185
pub enum x86_op_type {
11186
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
11187
    X86_OP_INVALID = 0,
11188
    #[doc = "< = CS_OP_REG (Register operand)."]
11189
    X86_OP_REG = 1,
11190
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
11191
    X86_OP_IMM = 2,
11192
    #[doc = "< = CS_OP_MEM (Memory operand)."]
11193
    X86_OP_MEM = 3,
11194
}
11195
#[repr(u32)]
11196
#[doc = " XOP Code Condition type"]
11197
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
11198
pub enum x86_xop_cc {
11199
    #[doc = "< Uninitialized."]
11200
    X86_XOP_CC_INVALID = 0,
11201
    X86_XOP_CC_LT = 1,
11202
    X86_XOP_CC_LE = 2,
11203
    X86_XOP_CC_GT = 3,
11204
    X86_XOP_CC_GE = 4,
11205
    X86_XOP_CC_EQ = 5,
11206
    X86_XOP_CC_NEQ = 6,
11207
    X86_XOP_CC_FALSE = 7,
11208
    X86_XOP_CC_TRUE = 8,
11209
}
11210
#[repr(u32)]
11211
#[doc = " AVX broadcast type"]
11212
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
11213
pub enum x86_avx_bcast {
11214
    #[doc = "< Uninitialized."]
11215
    X86_AVX_BCAST_INVALID = 0,
11216
    #[doc = "< AVX512 broadcast type {1to2}"]
11217
    X86_AVX_BCAST_2 = 1,
11218
    #[doc = "< AVX512 broadcast type {1to4}"]
11219
    X86_AVX_BCAST_4 = 2,
11220
    #[doc = "< AVX512 broadcast type {1to8}"]
11221
    X86_AVX_BCAST_8 = 3,
11222
    #[doc = "< AVX512 broadcast type {1to16}"]
11223
    X86_AVX_BCAST_16 = 4,
11224
}
11225
#[repr(u32)]
11226
#[doc = " SSE Code Condition type"]
11227
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
11228
pub enum x86_sse_cc {
11229
    #[doc = "< Uninitialized."]
11230
    X86_SSE_CC_INVALID = 0,
11231
    X86_SSE_CC_EQ = 1,
11232
    X86_SSE_CC_LT = 2,
11233
    X86_SSE_CC_LE = 3,
11234
    X86_SSE_CC_UNORD = 4,
11235
    X86_SSE_CC_NEQ = 5,
11236
    X86_SSE_CC_NLT = 6,
11237
    X86_SSE_CC_NLE = 7,
11238
    X86_SSE_CC_ORD = 8,
11239
}
11240
#[repr(u32)]
11241
#[doc = " AVX Code Condition type"]
11242
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
11243
pub enum x86_avx_cc {
11244
    #[doc = "< Uninitialized."]
11245
    X86_AVX_CC_INVALID = 0,
11246
    X86_AVX_CC_EQ = 1,
11247
    X86_AVX_CC_LT = 2,
11248
    X86_AVX_CC_LE = 3,
11249
    X86_AVX_CC_UNORD = 4,
11250
    X86_AVX_CC_NEQ = 5,
11251
    X86_AVX_CC_NLT = 6,
11252
    X86_AVX_CC_NLE = 7,
11253
    X86_AVX_CC_ORD = 8,
11254
    X86_AVX_CC_EQ_UQ = 9,
11255
    X86_AVX_CC_NGE = 10,
11256
    X86_AVX_CC_NGT = 11,
11257
    X86_AVX_CC_FALSE = 12,
11258
    X86_AVX_CC_NEQ_OQ = 13,
11259
    X86_AVX_CC_GE = 14,
11260
    X86_AVX_CC_GT = 15,
11261
    X86_AVX_CC_TRUE = 16,
11262
    X86_AVX_CC_EQ_OS = 17,
11263
    X86_AVX_CC_LT_OQ = 18,
11264
    X86_AVX_CC_LE_OQ = 19,
11265
    X86_AVX_CC_UNORD_S = 20,
11266
    X86_AVX_CC_NEQ_US = 21,
11267
    X86_AVX_CC_NLT_UQ = 22,
11268
    X86_AVX_CC_NLE_UQ = 23,
11269
    X86_AVX_CC_ORD_S = 24,
11270
    X86_AVX_CC_EQ_US = 25,
11271
    X86_AVX_CC_NGE_UQ = 26,
11272
    X86_AVX_CC_NGT_UQ = 27,
11273
    X86_AVX_CC_FALSE_OS = 28,
11274
    X86_AVX_CC_NEQ_OS = 29,
11275
    X86_AVX_CC_GE_OQ = 30,
11276
    X86_AVX_CC_GT_OQ = 31,
11277
    X86_AVX_CC_TRUE_US = 32,
11278
}
11279
#[repr(u32)]
11280
#[doc = " AVX static rounding mode type"]
11281
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
11282
pub enum x86_avx_rm {
11283
    #[doc = "< Uninitialized."]
11284
    X86_AVX_RM_INVALID = 0,
11285
    #[doc = "< Round to nearest"]
11286
    X86_AVX_RM_RN = 1,
11287
    #[doc = "< Round down"]
11288
    X86_AVX_RM_RD = 2,
11289
    #[doc = "< Round up"]
11290
    X86_AVX_RM_RU = 3,
11291
    #[doc = "< Round toward zero"]
11292
    X86_AVX_RM_RZ = 4,
11293
}
11294
impl x86_prefix {
11295
    pub const X86_PREFIX_REPE: x86_prefix = x86_prefix::X86_PREFIX_REP;
11296
}
11297
#[repr(u32)]
11298
#[doc = " Instruction prefixes - to be used in cs_x86.prefix[]"]
11299
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
11300
pub enum x86_prefix {
11301
    #[doc = "< lock (cs_x86.prefix[0]"]
11302
    X86_PREFIX_LOCK = 240,
11303
    #[doc = "< rep (cs_x86.prefix[0]"]
11304
    X86_PREFIX_REP = 243,
11305
    #[doc = "< repne/repnz (cs_x86.prefix[0]"]
11306
    X86_PREFIX_REPNE = 242,
11307
    #[doc = "< segment override CS (cs_x86.prefix[1]"]
11308
    X86_PREFIX_CS = 46,
11309
    #[doc = "< segment override SS (cs_x86.prefix[1]"]
11310
    X86_PREFIX_SS = 54,
11311
    #[doc = "< segment override DS (cs_x86.prefix[1]"]
11312
    X86_PREFIX_DS = 62,
11313
    #[doc = "< segment override ES (cs_x86.prefix[1]"]
11314
    X86_PREFIX_ES = 38,
11315
    #[doc = "< segment override FS (cs_x86.prefix[1]"]
11316
    X86_PREFIX_FS = 100,
11317
    #[doc = "< segment override GS (cs_x86.prefix[1]"]
11318
    X86_PREFIX_GS = 101,
11319
    #[doc = "< operand-size override (cs_x86.prefix[2]"]
11320
    X86_PREFIX_OPSIZE = 102,
11321
    #[doc = "< address-size override (cs_x86.prefix[3]"]
11322
    X86_PREFIX_ADDRSIZE = 103,
11323
}
11324
#[doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"]
11325
#[repr(C)]
11326
#[derive(Debug, Copy, Clone)]
11327
pub struct x86_op_mem {
11328
    #[doc = "< segment register (or X86_REG_INVALID if irrelevant)"]
11329
    pub segment: x86_reg::Type,
11330
    #[doc = "< base register (or X86_REG_INVALID if irrelevant)"]
11331
    pub base: x86_reg::Type,
11332
    #[doc = "< index register (or X86_REG_INVALID if irrelevant)"]
11333
    pub index: x86_reg::Type,
11334
    #[doc = "< scale for index register"]
11335
    pub scale: libc::c_int,
11336
    #[doc = "< displacement value"]
11337
    pub disp: i64,
11338
}
11339
#[doc = " Instruction operand"]
11340
#[repr(C)]
11341
#[derive(Copy, Clone)]
11342
pub struct cs_x86_op {
11343
    #[doc = "< operand type"]
11344
    pub type_: x86_op_type,
11345
    pub __bindgen_anon_1: cs_x86_op__bindgen_ty_1,
11346
    #[doc = " size of this operand (in bytes)."]
11347
    pub size: u8,
11348
    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."]
11349
    pub access: u8,
11350
    #[doc = " AVX broadcast type, or 0 if irrelevant"]
11351
    pub avx_bcast: x86_avx_bcast,
11352
    #[doc = " AVX zero opmask {z}"]
11353
    pub avx_zero_opmask: bool,
11354
}
11355
#[repr(C)]
11356
#[derive(Copy, Clone)]
11357
pub union cs_x86_op__bindgen_ty_1 {
11358
    #[doc = "< register value for REG operand"]
11359
    pub reg: x86_reg::Type,
11360
    #[doc = "< immediate value for IMM operand"]
11361
    pub imm: i64,
11362
    #[doc = "< base/index/scale/disp value for MEM operand"]
11363
    pub mem: x86_op_mem,
11364
}
11365
impl ::core::fmt::Debug for cs_x86_op__bindgen_ty_1 {
11366
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
11367
0
        write!(f, "cs_x86_op__bindgen_ty_1 {{ union }}")
11368
0
    }
11369
}
11370
impl ::core::fmt::Debug for cs_x86_op {
11371
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
11372
0
        write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . avx_bcast , self . avx_zero_opmask)
11373
0
    }
11374
}
11375
#[repr(C)]
11376
#[derive(Debug, Copy, Clone)]
11377
pub struct cs_x86_encoding {
11378
    #[doc = " ModR/M offset, or 0 when irrelevant"]
11379
    pub modrm_offset: u8,
11380
    #[doc = " Displacement offset, or 0 when irrelevant."]
11381
    pub disp_offset: u8,
11382
    pub disp_size: u8,
11383
    #[doc = " Immediate offset, or 0 when irrelevant."]
11384
    pub imm_offset: u8,
11385
    pub imm_size: u8,
11386
}
11387
#[doc = " Instruction structure"]
11388
#[repr(C)]
11389
#[derive(Copy, Clone)]
11390
pub struct cs_x86 {
11391
    #[doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"]
11392
    pub prefix: [u8; 4usize],
11393
    #[doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."]
11394
    pub opcode: [u8; 4usize],
11395
    #[doc = " REX prefix: only a non-zero value is relevant for x86_64"]
11396
    pub rex: u8,
11397
    #[doc = " Address size, which can be overridden with above prefix[5]."]
11398
    pub addr_size: u8,
11399
    #[doc = " ModR/M byte"]
11400
    pub modrm: u8,
11401
    #[doc = " SIB value, or 0 when irrelevant."]
11402
    pub sib: u8,
11403
    #[doc = " Displacement value, valid if encoding.disp_offset != 0"]
11404
    pub disp: i64,
11405
    #[doc = " SIB index register, or X86_REG_INVALID when irrelevant."]
11406
    pub sib_index: x86_reg::Type,
11407
    #[doc = " SIB scale, only applicable if sib_index is valid."]
11408
    pub sib_scale: i8,
11409
    #[doc = " SIB base register, or X86_REG_INVALID when irrelevant."]
11410
    pub sib_base: x86_reg::Type,
11411
    #[doc = " XOP Code Condition"]
11412
    pub xop_cc: x86_xop_cc,
11413
    #[doc = " SSE Code Condition"]
11414
    pub sse_cc: x86_sse_cc,
11415
    #[doc = " AVX Code Condition"]
11416
    pub avx_cc: x86_avx_cc,
11417
    #[doc = " AVX Suppress all Exception"]
11418
    pub avx_sae: bool,
11419
    #[doc = " AVX static rounding mode"]
11420
    pub avx_rm: x86_avx_rm,
11421
    pub __bindgen_anon_1: cs_x86__bindgen_ty_1,
11422
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
11423
    pub op_count: u8,
11424
    #[doc = "< operands for this instruction."]
11425
    pub operands: [cs_x86_op; 8usize],
11426
    #[doc = "< encoding information"]
11427
    pub encoding: cs_x86_encoding,
11428
}
11429
#[repr(C)]
11430
#[derive(Copy, Clone)]
11431
pub union cs_x86__bindgen_ty_1 {
11432
    #[doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"]
11433
    pub eflags: u64,
11434
    #[doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"]
11435
    pub fpu_flags: u64,
11436
}
11437
impl ::core::fmt::Debug for cs_x86__bindgen_ty_1 {
11438
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
11439
0
        write!(f, "cs_x86__bindgen_ty_1 {{ union }}")
11440
0
    }
11441
}
11442
impl ::core::fmt::Debug for cs_x86 {
11443
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
11444
0
        write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, sib_index: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . sib_index , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . operands , self . encoding)
11445
0
    }
11446
}
11447
#[repr(u32)]
11448
#[doc = " X86 instructions"]
11449
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
11450
pub enum x86_insn {
11451
    X86_INS_INVALID = 0,
11452
    X86_INS_AAA = 1,
11453
    X86_INS_AAD = 2,
11454
    X86_INS_AAM = 3,
11455
    X86_INS_AAS = 4,
11456
    X86_INS_FABS = 5,
11457
    X86_INS_ADC = 6,
11458
    X86_INS_ADCX = 7,
11459
    X86_INS_ADD = 8,
11460
    X86_INS_ADDPD = 9,
11461
    X86_INS_ADDPS = 10,
11462
    X86_INS_ADDSD = 11,
11463
    X86_INS_ADDSS = 12,
11464
    X86_INS_ADDSUBPD = 13,
11465
    X86_INS_ADDSUBPS = 14,
11466
    X86_INS_FADD = 15,
11467
    X86_INS_FIADD = 16,
11468
    X86_INS_ADOX = 17,
11469
    X86_INS_AESDECLAST = 18,
11470
    X86_INS_AESDEC = 19,
11471
    X86_INS_AESENCLAST = 20,
11472
    X86_INS_AESENC = 21,
11473
    X86_INS_AESIMC = 22,
11474
    X86_INS_AESKEYGENASSIST = 23,
11475
    X86_INS_AND = 24,
11476
    X86_INS_ANDN = 25,
11477
    X86_INS_ANDNPD = 26,
11478
    X86_INS_ANDNPS = 27,
11479
    X86_INS_ANDPD = 28,
11480
    X86_INS_ANDPS = 29,
11481
    X86_INS_ARPL = 30,
11482
    X86_INS_BEXTR = 31,
11483
    X86_INS_BLCFILL = 32,
11484
    X86_INS_BLCI = 33,
11485
    X86_INS_BLCIC = 34,
11486
    X86_INS_BLCMSK = 35,
11487
    X86_INS_BLCS = 36,
11488
    X86_INS_BLENDPD = 37,
11489
    X86_INS_BLENDPS = 38,
11490
    X86_INS_BLENDVPD = 39,
11491
    X86_INS_BLENDVPS = 40,
11492
    X86_INS_BLSFILL = 41,
11493
    X86_INS_BLSI = 42,
11494
    X86_INS_BLSIC = 43,
11495
    X86_INS_BLSMSK = 44,
11496
    X86_INS_BLSR = 45,
11497
    X86_INS_BNDCL = 46,
11498
    X86_INS_BNDCN = 47,
11499
    X86_INS_BNDCU = 48,
11500
    X86_INS_BNDLDX = 49,
11501
    X86_INS_BNDMK = 50,
11502
    X86_INS_BNDMOV = 51,
11503
    X86_INS_BNDSTX = 52,
11504
    X86_INS_BOUND = 53,
11505
    X86_INS_BSF = 54,
11506
    X86_INS_BSR = 55,
11507
    X86_INS_BSWAP = 56,
11508
    X86_INS_BT = 57,
11509
    X86_INS_BTC = 58,
11510
    X86_INS_BTR = 59,
11511
    X86_INS_BTS = 60,
11512
    X86_INS_BZHI = 61,
11513
    X86_INS_CALL = 62,
11514
    X86_INS_CBW = 63,
11515
    X86_INS_CDQ = 64,
11516
    X86_INS_CDQE = 65,
11517
    X86_INS_FCHS = 66,
11518
    X86_INS_CLAC = 67,
11519
    X86_INS_CLC = 68,
11520
    X86_INS_CLD = 69,
11521
    X86_INS_CLDEMOTE = 70,
11522
    X86_INS_CLFLUSH = 71,
11523
    X86_INS_CLFLUSHOPT = 72,
11524
    X86_INS_CLGI = 73,
11525
    X86_INS_CLI = 74,
11526
    X86_INS_CLRSSBSY = 75,
11527
    X86_INS_CLTS = 76,
11528
    X86_INS_CLWB = 77,
11529
    X86_INS_CLZERO = 78,
11530
    X86_INS_CMC = 79,
11531
    X86_INS_CMOVA = 80,
11532
    X86_INS_CMOVAE = 81,
11533
    X86_INS_CMOVB = 82,
11534
    X86_INS_CMOVBE = 83,
11535
    X86_INS_FCMOVBE = 84,
11536
    X86_INS_FCMOVB = 85,
11537
    X86_INS_CMOVE = 86,
11538
    X86_INS_FCMOVE = 87,
11539
    X86_INS_CMOVG = 88,
11540
    X86_INS_CMOVGE = 89,
11541
    X86_INS_CMOVL = 90,
11542
    X86_INS_CMOVLE = 91,
11543
    X86_INS_FCMOVNBE = 92,
11544
    X86_INS_FCMOVNB = 93,
11545
    X86_INS_CMOVNE = 94,
11546
    X86_INS_FCMOVNE = 95,
11547
    X86_INS_CMOVNO = 96,
11548
    X86_INS_CMOVNP = 97,
11549
    X86_INS_FCMOVNU = 98,
11550
    X86_INS_FCMOVNP = 99,
11551
    X86_INS_CMOVNS = 100,
11552
    X86_INS_CMOVO = 101,
11553
    X86_INS_CMOVP = 102,
11554
    X86_INS_FCMOVU = 103,
11555
    X86_INS_CMOVS = 104,
11556
    X86_INS_CMP = 105,
11557
    X86_INS_CMPPD = 106,
11558
    X86_INS_CMPPS = 107,
11559
    X86_INS_CMPSB = 108,
11560
    X86_INS_CMPSD = 109,
11561
    X86_INS_CMPSQ = 110,
11562
    X86_INS_CMPSS = 111,
11563
    X86_INS_CMPSW = 112,
11564
    X86_INS_CMPXCHG16B = 113,
11565
    X86_INS_CMPXCHG = 114,
11566
    X86_INS_CMPXCHG8B = 115,
11567
    X86_INS_COMISD = 116,
11568
    X86_INS_COMISS = 117,
11569
    X86_INS_FCOMP = 118,
11570
    X86_INS_FCOMPI = 119,
11571
    X86_INS_FCOMI = 120,
11572
    X86_INS_FCOM = 121,
11573
    X86_INS_FCOS = 122,
11574
    X86_INS_CPUID = 123,
11575
    X86_INS_CQO = 124,
11576
    X86_INS_CRC32 = 125,
11577
    X86_INS_CVTDQ2PD = 126,
11578
    X86_INS_CVTDQ2PS = 127,
11579
    X86_INS_CVTPD2DQ = 128,
11580
    X86_INS_CVTPD2PS = 129,
11581
    X86_INS_CVTPS2DQ = 130,
11582
    X86_INS_CVTPS2PD = 131,
11583
    X86_INS_CVTSD2SI = 132,
11584
    X86_INS_CVTSD2SS = 133,
11585
    X86_INS_CVTSI2SD = 134,
11586
    X86_INS_CVTSI2SS = 135,
11587
    X86_INS_CVTSS2SD = 136,
11588
    X86_INS_CVTSS2SI = 137,
11589
    X86_INS_CVTTPD2DQ = 138,
11590
    X86_INS_CVTTPS2DQ = 139,
11591
    X86_INS_CVTTSD2SI = 140,
11592
    X86_INS_CVTTSS2SI = 141,
11593
    X86_INS_CWD = 142,
11594
    X86_INS_CWDE = 143,
11595
    X86_INS_DAA = 144,
11596
    X86_INS_DAS = 145,
11597
    X86_INS_DATA16 = 146,
11598
    X86_INS_DEC = 147,
11599
    X86_INS_DIV = 148,
11600
    X86_INS_DIVPD = 149,
11601
    X86_INS_DIVPS = 150,
11602
    X86_INS_FDIVR = 151,
11603
    X86_INS_FIDIVR = 152,
11604
    X86_INS_FDIVRP = 153,
11605
    X86_INS_DIVSD = 154,
11606
    X86_INS_DIVSS = 155,
11607
    X86_INS_FDIV = 156,
11608
    X86_INS_FIDIV = 157,
11609
    X86_INS_FDIVP = 158,
11610
    X86_INS_DPPD = 159,
11611
    X86_INS_DPPS = 160,
11612
    X86_INS_ENCLS = 161,
11613
    X86_INS_ENCLU = 162,
11614
    X86_INS_ENCLV = 163,
11615
    X86_INS_ENDBR32 = 164,
11616
    X86_INS_ENDBR64 = 165,
11617
    X86_INS_ENTER = 166,
11618
    X86_INS_EXTRACTPS = 167,
11619
    X86_INS_EXTRQ = 168,
11620
    X86_INS_F2XM1 = 169,
11621
    X86_INS_LCALL = 170,
11622
    X86_INS_LJMP = 171,
11623
    X86_INS_JMP = 172,
11624
    X86_INS_FBLD = 173,
11625
    X86_INS_FBSTP = 174,
11626
    X86_INS_FCOMPP = 175,
11627
    X86_INS_FDECSTP = 176,
11628
    X86_INS_FDISI8087_NOP = 177,
11629
    X86_INS_FEMMS = 178,
11630
    X86_INS_FENI8087_NOP = 179,
11631
    X86_INS_FFREE = 180,
11632
    X86_INS_FFREEP = 181,
11633
    X86_INS_FICOM = 182,
11634
    X86_INS_FICOMP = 183,
11635
    X86_INS_FINCSTP = 184,
11636
    X86_INS_FLDCW = 185,
11637
    X86_INS_FLDENV = 186,
11638
    X86_INS_FLDL2E = 187,
11639
    X86_INS_FLDL2T = 188,
11640
    X86_INS_FLDLG2 = 189,
11641
    X86_INS_FLDLN2 = 190,
11642
    X86_INS_FLDPI = 191,
11643
    X86_INS_FNCLEX = 192,
11644
    X86_INS_FNINIT = 193,
11645
    X86_INS_FNOP = 194,
11646
    X86_INS_FNSTCW = 195,
11647
    X86_INS_FNSTSW = 196,
11648
    X86_INS_FPATAN = 197,
11649
    X86_INS_FSTPNCE = 198,
11650
    X86_INS_FPREM = 199,
11651
    X86_INS_FPREM1 = 200,
11652
    X86_INS_FPTAN = 201,
11653
    X86_INS_FRNDINT = 202,
11654
    X86_INS_FRSTOR = 203,
11655
    X86_INS_FNSAVE = 204,
11656
    X86_INS_FSCALE = 205,
11657
    X86_INS_FSETPM = 206,
11658
    X86_INS_FSINCOS = 207,
11659
    X86_INS_FNSTENV = 208,
11660
    X86_INS_FXAM = 209,
11661
    X86_INS_FXRSTOR = 210,
11662
    X86_INS_FXRSTOR64 = 211,
11663
    X86_INS_FXSAVE = 212,
11664
    X86_INS_FXSAVE64 = 213,
11665
    X86_INS_FXTRACT = 214,
11666
    X86_INS_FYL2X = 215,
11667
    X86_INS_FYL2XP1 = 216,
11668
    X86_INS_GETSEC = 217,
11669
    X86_INS_GF2P8AFFINEINVQB = 218,
11670
    X86_INS_GF2P8AFFINEQB = 219,
11671
    X86_INS_GF2P8MULB = 220,
11672
    X86_INS_HADDPD = 221,
11673
    X86_INS_HADDPS = 222,
11674
    X86_INS_HLT = 223,
11675
    X86_INS_HSUBPD = 224,
11676
    X86_INS_HSUBPS = 225,
11677
    X86_INS_IDIV = 226,
11678
    X86_INS_FILD = 227,
11679
    X86_INS_IMUL = 228,
11680
    X86_INS_IN = 229,
11681
    X86_INS_INC = 230,
11682
    X86_INS_INCSSPD = 231,
11683
    X86_INS_INCSSPQ = 232,
11684
    X86_INS_INSB = 233,
11685
    X86_INS_INSERTPS = 234,
11686
    X86_INS_INSERTQ = 235,
11687
    X86_INS_INSD = 236,
11688
    X86_INS_INSW = 237,
11689
    X86_INS_INT = 238,
11690
    X86_INS_INT1 = 239,
11691
    X86_INS_INT3 = 240,
11692
    X86_INS_INTO = 241,
11693
    X86_INS_INVD = 242,
11694
    X86_INS_INVEPT = 243,
11695
    X86_INS_INVLPG = 244,
11696
    X86_INS_INVLPGA = 245,
11697
    X86_INS_INVPCID = 246,
11698
    X86_INS_INVVPID = 247,
11699
    X86_INS_IRET = 248,
11700
    X86_INS_IRETD = 249,
11701
    X86_INS_IRETQ = 250,
11702
    X86_INS_FISTTP = 251,
11703
    X86_INS_FIST = 252,
11704
    X86_INS_FISTP = 253,
11705
    X86_INS_JAE = 254,
11706
    X86_INS_JA = 255,
11707
    X86_INS_JBE = 256,
11708
    X86_INS_JB = 257,
11709
    X86_INS_JCXZ = 258,
11710
    X86_INS_JECXZ = 259,
11711
    X86_INS_JE = 260,
11712
    X86_INS_JGE = 261,
11713
    X86_INS_JG = 262,
11714
    X86_INS_JLE = 263,
11715
    X86_INS_JL = 264,
11716
    X86_INS_JNE = 265,
11717
    X86_INS_JNO = 266,
11718
    X86_INS_JNP = 267,
11719
    X86_INS_JNS = 268,
11720
    X86_INS_JO = 269,
11721
    X86_INS_JP = 270,
11722
    X86_INS_JRCXZ = 271,
11723
    X86_INS_JS = 272,
11724
    X86_INS_KADDB = 273,
11725
    X86_INS_KADDD = 274,
11726
    X86_INS_KADDQ = 275,
11727
    X86_INS_KADDW = 276,
11728
    X86_INS_KANDB = 277,
11729
    X86_INS_KANDD = 278,
11730
    X86_INS_KANDNB = 279,
11731
    X86_INS_KANDND = 280,
11732
    X86_INS_KANDNQ = 281,
11733
    X86_INS_KANDNW = 282,
11734
    X86_INS_KANDQ = 283,
11735
    X86_INS_KANDW = 284,
11736
    X86_INS_KMOVB = 285,
11737
    X86_INS_KMOVD = 286,
11738
    X86_INS_KMOVQ = 287,
11739
    X86_INS_KMOVW = 288,
11740
    X86_INS_KNOTB = 289,
11741
    X86_INS_KNOTD = 290,
11742
    X86_INS_KNOTQ = 291,
11743
    X86_INS_KNOTW = 292,
11744
    X86_INS_KORB = 293,
11745
    X86_INS_KORD = 294,
11746
    X86_INS_KORQ = 295,
11747
    X86_INS_KORTESTB = 296,
11748
    X86_INS_KORTESTD = 297,
11749
    X86_INS_KORTESTQ = 298,
11750
    X86_INS_KORTESTW = 299,
11751
    X86_INS_KORW = 300,
11752
    X86_INS_KSHIFTLB = 301,
11753
    X86_INS_KSHIFTLD = 302,
11754
    X86_INS_KSHIFTLQ = 303,
11755
    X86_INS_KSHIFTLW = 304,
11756
    X86_INS_KSHIFTRB = 305,
11757
    X86_INS_KSHIFTRD = 306,
11758
    X86_INS_KSHIFTRQ = 307,
11759
    X86_INS_KSHIFTRW = 308,
11760
    X86_INS_KTESTB = 309,
11761
    X86_INS_KTESTD = 310,
11762
    X86_INS_KTESTQ = 311,
11763
    X86_INS_KTESTW = 312,
11764
    X86_INS_KUNPCKBW = 313,
11765
    X86_INS_KUNPCKDQ = 314,
11766
    X86_INS_KUNPCKWD = 315,
11767
    X86_INS_KXNORB = 316,
11768
    X86_INS_KXNORD = 317,
11769
    X86_INS_KXNORQ = 318,
11770
    X86_INS_KXNORW = 319,
11771
    X86_INS_KXORB = 320,
11772
    X86_INS_KXORD = 321,
11773
    X86_INS_KXORQ = 322,
11774
    X86_INS_KXORW = 323,
11775
    X86_INS_LAHF = 324,
11776
    X86_INS_LAR = 325,
11777
    X86_INS_LDDQU = 326,
11778
    X86_INS_LDMXCSR = 327,
11779
    X86_INS_LDS = 328,
11780
    X86_INS_FLDZ = 329,
11781
    X86_INS_FLD1 = 330,
11782
    X86_INS_FLD = 331,
11783
    X86_INS_LEA = 332,
11784
    X86_INS_LEAVE = 333,
11785
    X86_INS_LES = 334,
11786
    X86_INS_LFENCE = 335,
11787
    X86_INS_LFS = 336,
11788
    X86_INS_LGDT = 337,
11789
    X86_INS_LGS = 338,
11790
    X86_INS_LIDT = 339,
11791
    X86_INS_LLDT = 340,
11792
    X86_INS_LLWPCB = 341,
11793
    X86_INS_LMSW = 342,
11794
    X86_INS_LOCK = 343,
11795
    X86_INS_LODSB = 344,
11796
    X86_INS_LODSD = 345,
11797
    X86_INS_LODSQ = 346,
11798
    X86_INS_LODSW = 347,
11799
    X86_INS_LOOP = 348,
11800
    X86_INS_LOOPE = 349,
11801
    X86_INS_LOOPNE = 350,
11802
    X86_INS_RETF = 351,
11803
    X86_INS_RETFQ = 352,
11804
    X86_INS_LSL = 353,
11805
    X86_INS_LSS = 354,
11806
    X86_INS_LTR = 355,
11807
    X86_INS_LWPINS = 356,
11808
    X86_INS_LWPVAL = 357,
11809
    X86_INS_LZCNT = 358,
11810
    X86_INS_MASKMOVDQU = 359,
11811
    X86_INS_MAXPD = 360,
11812
    X86_INS_MAXPS = 361,
11813
    X86_INS_MAXSD = 362,
11814
    X86_INS_MAXSS = 363,
11815
    X86_INS_MFENCE = 364,
11816
    X86_INS_MINPD = 365,
11817
    X86_INS_MINPS = 366,
11818
    X86_INS_MINSD = 367,
11819
    X86_INS_MINSS = 368,
11820
    X86_INS_CVTPD2PI = 369,
11821
    X86_INS_CVTPI2PD = 370,
11822
    X86_INS_CVTPI2PS = 371,
11823
    X86_INS_CVTPS2PI = 372,
11824
    X86_INS_CVTTPD2PI = 373,
11825
    X86_INS_CVTTPS2PI = 374,
11826
    X86_INS_EMMS = 375,
11827
    X86_INS_MASKMOVQ = 376,
11828
    X86_INS_MOVD = 377,
11829
    X86_INS_MOVQ = 378,
11830
    X86_INS_MOVDQ2Q = 379,
11831
    X86_INS_MOVNTQ = 380,
11832
    X86_INS_MOVQ2DQ = 381,
11833
    X86_INS_PABSB = 382,
11834
    X86_INS_PABSD = 383,
11835
    X86_INS_PABSW = 384,
11836
    X86_INS_PACKSSDW = 385,
11837
    X86_INS_PACKSSWB = 386,
11838
    X86_INS_PACKUSWB = 387,
11839
    X86_INS_PADDB = 388,
11840
    X86_INS_PADDD = 389,
11841
    X86_INS_PADDQ = 390,
11842
    X86_INS_PADDSB = 391,
11843
    X86_INS_PADDSW = 392,
11844
    X86_INS_PADDUSB = 393,
11845
    X86_INS_PADDUSW = 394,
11846
    X86_INS_PADDW = 395,
11847
    X86_INS_PALIGNR = 396,
11848
    X86_INS_PANDN = 397,
11849
    X86_INS_PAND = 398,
11850
    X86_INS_PAVGB = 399,
11851
    X86_INS_PAVGW = 400,
11852
    X86_INS_PCMPEQB = 401,
11853
    X86_INS_PCMPEQD = 402,
11854
    X86_INS_PCMPEQW = 403,
11855
    X86_INS_PCMPGTB = 404,
11856
    X86_INS_PCMPGTD = 405,
11857
    X86_INS_PCMPGTW = 406,
11858
    X86_INS_PEXTRW = 407,
11859
    X86_INS_PHADDD = 408,
11860
    X86_INS_PHADDSW = 409,
11861
    X86_INS_PHADDW = 410,
11862
    X86_INS_PHSUBD = 411,
11863
    X86_INS_PHSUBSW = 412,
11864
    X86_INS_PHSUBW = 413,
11865
    X86_INS_PINSRW = 414,
11866
    X86_INS_PMADDUBSW = 415,
11867
    X86_INS_PMADDWD = 416,
11868
    X86_INS_PMAXSW = 417,
11869
    X86_INS_PMAXUB = 418,
11870
    X86_INS_PMINSW = 419,
11871
    X86_INS_PMINUB = 420,
11872
    X86_INS_PMOVMSKB = 421,
11873
    X86_INS_PMULHRSW = 422,
11874
    X86_INS_PMULHUW = 423,
11875
    X86_INS_PMULHW = 424,
11876
    X86_INS_PMULLW = 425,
11877
    X86_INS_PMULUDQ = 426,
11878
    X86_INS_POR = 427,
11879
    X86_INS_PSADBW = 428,
11880
    X86_INS_PSHUFB = 429,
11881
    X86_INS_PSHUFW = 430,
11882
    X86_INS_PSIGNB = 431,
11883
    X86_INS_PSIGND = 432,
11884
    X86_INS_PSIGNW = 433,
11885
    X86_INS_PSLLD = 434,
11886
    X86_INS_PSLLQ = 435,
11887
    X86_INS_PSLLW = 436,
11888
    X86_INS_PSRAD = 437,
11889
    X86_INS_PSRAW = 438,
11890
    X86_INS_PSRLD = 439,
11891
    X86_INS_PSRLQ = 440,
11892
    X86_INS_PSRLW = 441,
11893
    X86_INS_PSUBB = 442,
11894
    X86_INS_PSUBD = 443,
11895
    X86_INS_PSUBQ = 444,
11896
    X86_INS_PSUBSB = 445,
11897
    X86_INS_PSUBSW = 446,
11898
    X86_INS_PSUBUSB = 447,
11899
    X86_INS_PSUBUSW = 448,
11900
    X86_INS_PSUBW = 449,
11901
    X86_INS_PUNPCKHBW = 450,
11902
    X86_INS_PUNPCKHDQ = 451,
11903
    X86_INS_PUNPCKHWD = 452,
11904
    X86_INS_PUNPCKLBW = 453,
11905
    X86_INS_PUNPCKLDQ = 454,
11906
    X86_INS_PUNPCKLWD = 455,
11907
    X86_INS_PXOR = 456,
11908
    X86_INS_MONITORX = 457,
11909
    X86_INS_MONITOR = 458,
11910
    X86_INS_MONTMUL = 459,
11911
    X86_INS_MOV = 460,
11912
    X86_INS_MOVABS = 461,
11913
    X86_INS_MOVAPD = 462,
11914
    X86_INS_MOVAPS = 463,
11915
    X86_INS_MOVBE = 464,
11916
    X86_INS_MOVDDUP = 465,
11917
    X86_INS_MOVDIR64B = 466,
11918
    X86_INS_MOVDIRI = 467,
11919
    X86_INS_MOVDQA = 468,
11920
    X86_INS_MOVDQU = 469,
11921
    X86_INS_MOVHLPS = 470,
11922
    X86_INS_MOVHPD = 471,
11923
    X86_INS_MOVHPS = 472,
11924
    X86_INS_MOVLHPS = 473,
11925
    X86_INS_MOVLPD = 474,
11926
    X86_INS_MOVLPS = 475,
11927
    X86_INS_MOVMSKPD = 476,
11928
    X86_INS_MOVMSKPS = 477,
11929
    X86_INS_MOVNTDQA = 478,
11930
    X86_INS_MOVNTDQ = 479,
11931
    X86_INS_MOVNTI = 480,
11932
    X86_INS_MOVNTPD = 481,
11933
    X86_INS_MOVNTPS = 482,
11934
    X86_INS_MOVNTSD = 483,
11935
    X86_INS_MOVNTSS = 484,
11936
    X86_INS_MOVSB = 485,
11937
    X86_INS_MOVSD = 486,
11938
    X86_INS_MOVSHDUP = 487,
11939
    X86_INS_MOVSLDUP = 488,
11940
    X86_INS_MOVSQ = 489,
11941
    X86_INS_MOVSS = 490,
11942
    X86_INS_MOVSW = 491,
11943
    X86_INS_MOVSX = 492,
11944
    X86_INS_MOVSXD = 493,
11945
    X86_INS_MOVUPD = 494,
11946
    X86_INS_MOVUPS = 495,
11947
    X86_INS_MOVZX = 496,
11948
    X86_INS_MPSADBW = 497,
11949
    X86_INS_MUL = 498,
11950
    X86_INS_MULPD = 499,
11951
    X86_INS_MULPS = 500,
11952
    X86_INS_MULSD = 501,
11953
    X86_INS_MULSS = 502,
11954
    X86_INS_MULX = 503,
11955
    X86_INS_FMUL = 504,
11956
    X86_INS_FIMUL = 505,
11957
    X86_INS_FMULP = 506,
11958
    X86_INS_MWAITX = 507,
11959
    X86_INS_MWAIT = 508,
11960
    X86_INS_NEG = 509,
11961
    X86_INS_NOP = 510,
11962
    X86_INS_NOT = 511,
11963
    X86_INS_OR = 512,
11964
    X86_INS_ORPD = 513,
11965
    X86_INS_ORPS = 514,
11966
    X86_INS_OUT = 515,
11967
    X86_INS_OUTSB = 516,
11968
    X86_INS_OUTSD = 517,
11969
    X86_INS_OUTSW = 518,
11970
    X86_INS_PACKUSDW = 519,
11971
    X86_INS_PAUSE = 520,
11972
    X86_INS_PAVGUSB = 521,
11973
    X86_INS_PBLENDVB = 522,
11974
    X86_INS_PBLENDW = 523,
11975
    X86_INS_PCLMULQDQ = 524,
11976
    X86_INS_PCMPEQQ = 525,
11977
    X86_INS_PCMPESTRI = 526,
11978
    X86_INS_PCMPESTRM = 527,
11979
    X86_INS_PCMPGTQ = 528,
11980
    X86_INS_PCMPISTRI = 529,
11981
    X86_INS_PCMPISTRM = 530,
11982
    X86_INS_PCONFIG = 531,
11983
    X86_INS_PDEP = 532,
11984
    X86_INS_PEXT = 533,
11985
    X86_INS_PEXTRB = 534,
11986
    X86_INS_PEXTRD = 535,
11987
    X86_INS_PEXTRQ = 536,
11988
    X86_INS_PF2ID = 537,
11989
    X86_INS_PF2IW = 538,
11990
    X86_INS_PFACC = 539,
11991
    X86_INS_PFADD = 540,
11992
    X86_INS_PFCMPEQ = 541,
11993
    X86_INS_PFCMPGE = 542,
11994
    X86_INS_PFCMPGT = 543,
11995
    X86_INS_PFMAX = 544,
11996
    X86_INS_PFMIN = 545,
11997
    X86_INS_PFMUL = 546,
11998
    X86_INS_PFNACC = 547,
11999
    X86_INS_PFPNACC = 548,
12000
    X86_INS_PFRCPIT1 = 549,
12001
    X86_INS_PFRCPIT2 = 550,
12002
    X86_INS_PFRCP = 551,
12003
    X86_INS_PFRSQIT1 = 552,
12004
    X86_INS_PFRSQRT = 553,
12005
    X86_INS_PFSUBR = 554,
12006
    X86_INS_PFSUB = 555,
12007
    X86_INS_PHMINPOSUW = 556,
12008
    X86_INS_PI2FD = 557,
12009
    X86_INS_PI2FW = 558,
12010
    X86_INS_PINSRB = 559,
12011
    X86_INS_PINSRD = 560,
12012
    X86_INS_PINSRQ = 561,
12013
    X86_INS_PMAXSB = 562,
12014
    X86_INS_PMAXSD = 563,
12015
    X86_INS_PMAXUD = 564,
12016
    X86_INS_PMAXUW = 565,
12017
    X86_INS_PMINSB = 566,
12018
    X86_INS_PMINSD = 567,
12019
    X86_INS_PMINUD = 568,
12020
    X86_INS_PMINUW = 569,
12021
    X86_INS_PMOVSXBD = 570,
12022
    X86_INS_PMOVSXBQ = 571,
12023
    X86_INS_PMOVSXBW = 572,
12024
    X86_INS_PMOVSXDQ = 573,
12025
    X86_INS_PMOVSXWD = 574,
12026
    X86_INS_PMOVSXWQ = 575,
12027
    X86_INS_PMOVZXBD = 576,
12028
    X86_INS_PMOVZXBQ = 577,
12029
    X86_INS_PMOVZXBW = 578,
12030
    X86_INS_PMOVZXDQ = 579,
12031
    X86_INS_PMOVZXWD = 580,
12032
    X86_INS_PMOVZXWQ = 581,
12033
    X86_INS_PMULDQ = 582,
12034
    X86_INS_PMULHRW = 583,
12035
    X86_INS_PMULLD = 584,
12036
    X86_INS_POP = 585,
12037
    X86_INS_POPAW = 586,
12038
    X86_INS_POPAL = 587,
12039
    X86_INS_POPCNT = 588,
12040
    X86_INS_POPF = 589,
12041
    X86_INS_POPFD = 590,
12042
    X86_INS_POPFQ = 591,
12043
    X86_INS_PREFETCH = 592,
12044
    X86_INS_PREFETCHNTA = 593,
12045
    X86_INS_PREFETCHT0 = 594,
12046
    X86_INS_PREFETCHT1 = 595,
12047
    X86_INS_PREFETCHT2 = 596,
12048
    X86_INS_PREFETCHW = 597,
12049
    X86_INS_PREFETCHWT1 = 598,
12050
    X86_INS_PSHUFD = 599,
12051
    X86_INS_PSHUFHW = 600,
12052
    X86_INS_PSHUFLW = 601,
12053
    X86_INS_PSLLDQ = 602,
12054
    X86_INS_PSRLDQ = 603,
12055
    X86_INS_PSWAPD = 604,
12056
    X86_INS_PTEST = 605,
12057
    X86_INS_PTWRITE = 606,
12058
    X86_INS_PUNPCKHQDQ = 607,
12059
    X86_INS_PUNPCKLQDQ = 608,
12060
    X86_INS_PUSH = 609,
12061
    X86_INS_PUSHAW = 610,
12062
    X86_INS_PUSHAL = 611,
12063
    X86_INS_PUSHF = 612,
12064
    X86_INS_PUSHFD = 613,
12065
    X86_INS_PUSHFQ = 614,
12066
    X86_INS_RCL = 615,
12067
    X86_INS_RCPPS = 616,
12068
    X86_INS_RCPSS = 617,
12069
    X86_INS_RCR = 618,
12070
    X86_INS_RDFSBASE = 619,
12071
    X86_INS_RDGSBASE = 620,
12072
    X86_INS_RDMSR = 621,
12073
    X86_INS_RDPID = 622,
12074
    X86_INS_RDPKRU = 623,
12075
    X86_INS_RDPMC = 624,
12076
    X86_INS_RDRAND = 625,
12077
    X86_INS_RDSEED = 626,
12078
    X86_INS_RDSSPD = 627,
12079
    X86_INS_RDSSPQ = 628,
12080
    X86_INS_RDTSC = 629,
12081
    X86_INS_RDTSCP = 630,
12082
    X86_INS_REPNE = 631,
12083
    X86_INS_REP = 632,
12084
    X86_INS_RET = 633,
12085
    X86_INS_REX64 = 634,
12086
    X86_INS_ROL = 635,
12087
    X86_INS_ROR = 636,
12088
    X86_INS_RORX = 637,
12089
    X86_INS_ROUNDPD = 638,
12090
    X86_INS_ROUNDPS = 639,
12091
    X86_INS_ROUNDSD = 640,
12092
    X86_INS_ROUNDSS = 641,
12093
    X86_INS_RSM = 642,
12094
    X86_INS_RSQRTPS = 643,
12095
    X86_INS_RSQRTSS = 644,
12096
    X86_INS_RSTORSSP = 645,
12097
    X86_INS_SAHF = 646,
12098
    X86_INS_SAL = 647,
12099
    X86_INS_SALC = 648,
12100
    X86_INS_SAR = 649,
12101
    X86_INS_SARX = 650,
12102
    X86_INS_SAVEPREVSSP = 651,
12103
    X86_INS_SBB = 652,
12104
    X86_INS_SCASB = 653,
12105
    X86_INS_SCASD = 654,
12106
    X86_INS_SCASQ = 655,
12107
    X86_INS_SCASW = 656,
12108
    X86_INS_SETAE = 657,
12109
    X86_INS_SETA = 658,
12110
    X86_INS_SETBE = 659,
12111
    X86_INS_SETB = 660,
12112
    X86_INS_SETE = 661,
12113
    X86_INS_SETGE = 662,
12114
    X86_INS_SETG = 663,
12115
    X86_INS_SETLE = 664,
12116
    X86_INS_SETL = 665,
12117
    X86_INS_SETNE = 666,
12118
    X86_INS_SETNO = 667,
12119
    X86_INS_SETNP = 668,
12120
    X86_INS_SETNS = 669,
12121
    X86_INS_SETO = 670,
12122
    X86_INS_SETP = 671,
12123
    X86_INS_SETSSBSY = 672,
12124
    X86_INS_SETS = 673,
12125
    X86_INS_SFENCE = 674,
12126
    X86_INS_SGDT = 675,
12127
    X86_INS_SHA1MSG1 = 676,
12128
    X86_INS_SHA1MSG2 = 677,
12129
    X86_INS_SHA1NEXTE = 678,
12130
    X86_INS_SHA1RNDS4 = 679,
12131
    X86_INS_SHA256MSG1 = 680,
12132
    X86_INS_SHA256MSG2 = 681,
12133
    X86_INS_SHA256RNDS2 = 682,
12134
    X86_INS_SHL = 683,
12135
    X86_INS_SHLD = 684,
12136
    X86_INS_SHLX = 685,
12137
    X86_INS_SHR = 686,
12138
    X86_INS_SHRD = 687,
12139
    X86_INS_SHRX = 688,
12140
    X86_INS_SHUFPD = 689,
12141
    X86_INS_SHUFPS = 690,
12142
    X86_INS_SIDT = 691,
12143
    X86_INS_FSIN = 692,
12144
    X86_INS_SKINIT = 693,
12145
    X86_INS_SLDT = 694,
12146
    X86_INS_SLWPCB = 695,
12147
    X86_INS_SMSW = 696,
12148
    X86_INS_SQRTPD = 697,
12149
    X86_INS_SQRTPS = 698,
12150
    X86_INS_SQRTSD = 699,
12151
    X86_INS_SQRTSS = 700,
12152
    X86_INS_FSQRT = 701,
12153
    X86_INS_STAC = 702,
12154
    X86_INS_STC = 703,
12155
    X86_INS_STD = 704,
12156
    X86_INS_STGI = 705,
12157
    X86_INS_STI = 706,
12158
    X86_INS_STMXCSR = 707,
12159
    X86_INS_STOSB = 708,
12160
    X86_INS_STOSD = 709,
12161
    X86_INS_STOSQ = 710,
12162
    X86_INS_STOSW = 711,
12163
    X86_INS_STR = 712,
12164
    X86_INS_FST = 713,
12165
    X86_INS_FSTP = 714,
12166
    X86_INS_SUB = 715,
12167
    X86_INS_SUBPD = 716,
12168
    X86_INS_SUBPS = 717,
12169
    X86_INS_FSUBR = 718,
12170
    X86_INS_FISUBR = 719,
12171
    X86_INS_FSUBRP = 720,
12172
    X86_INS_SUBSD = 721,
12173
    X86_INS_SUBSS = 722,
12174
    X86_INS_FSUB = 723,
12175
    X86_INS_FISUB = 724,
12176
    X86_INS_FSUBP = 725,
12177
    X86_INS_SWAPGS = 726,
12178
    X86_INS_SYSCALL = 727,
12179
    X86_INS_SYSENTER = 728,
12180
    X86_INS_SYSEXIT = 729,
12181
    X86_INS_SYSEXITQ = 730,
12182
    X86_INS_SYSRET = 731,
12183
    X86_INS_SYSRETQ = 732,
12184
    X86_INS_T1MSKC = 733,
12185
    X86_INS_TEST = 734,
12186
    X86_INS_TPAUSE = 735,
12187
    X86_INS_FTST = 736,
12188
    X86_INS_TZCNT = 737,
12189
    X86_INS_TZMSK = 738,
12190
    X86_INS_UCOMISD = 739,
12191
    X86_INS_UCOMISS = 740,
12192
    X86_INS_FUCOMPI = 741,
12193
    X86_INS_FUCOMI = 742,
12194
    X86_INS_FUCOMPP = 743,
12195
    X86_INS_FUCOMP = 744,
12196
    X86_INS_FUCOM = 745,
12197
    X86_INS_UD0 = 746,
12198
    X86_INS_UD1 = 747,
12199
    X86_INS_UD2 = 748,
12200
    X86_INS_UMONITOR = 749,
12201
    X86_INS_UMWAIT = 750,
12202
    X86_INS_UNPCKHPD = 751,
12203
    X86_INS_UNPCKHPS = 752,
12204
    X86_INS_UNPCKLPD = 753,
12205
    X86_INS_UNPCKLPS = 754,
12206
    X86_INS_V4FMADDPS = 755,
12207
    X86_INS_V4FMADDSS = 756,
12208
    X86_INS_V4FNMADDPS = 757,
12209
    X86_INS_V4FNMADDSS = 758,
12210
    X86_INS_VADDPD = 759,
12211
    X86_INS_VADDPS = 760,
12212
    X86_INS_VADDSD = 761,
12213
    X86_INS_VADDSS = 762,
12214
    X86_INS_VADDSUBPD = 763,
12215
    X86_INS_VADDSUBPS = 764,
12216
    X86_INS_VAESDECLAST = 765,
12217
    X86_INS_VAESDEC = 766,
12218
    X86_INS_VAESENCLAST = 767,
12219
    X86_INS_VAESENC = 768,
12220
    X86_INS_VAESIMC = 769,
12221
    X86_INS_VAESKEYGENASSIST = 770,
12222
    X86_INS_VALIGND = 771,
12223
    X86_INS_VALIGNQ = 772,
12224
    X86_INS_VANDNPD = 773,
12225
    X86_INS_VANDNPS = 774,
12226
    X86_INS_VANDPD = 775,
12227
    X86_INS_VANDPS = 776,
12228
    X86_INS_VBLENDMPD = 777,
12229
    X86_INS_VBLENDMPS = 778,
12230
    X86_INS_VBLENDPD = 779,
12231
    X86_INS_VBLENDPS = 780,
12232
    X86_INS_VBLENDVPD = 781,
12233
    X86_INS_VBLENDVPS = 782,
12234
    X86_INS_VBROADCASTF128 = 783,
12235
    X86_INS_VBROADCASTF32X2 = 784,
12236
    X86_INS_VBROADCASTF32X4 = 785,
12237
    X86_INS_VBROADCASTF32X8 = 786,
12238
    X86_INS_VBROADCASTF64X2 = 787,
12239
    X86_INS_VBROADCASTF64X4 = 788,
12240
    X86_INS_VBROADCASTI128 = 789,
12241
    X86_INS_VBROADCASTI32X2 = 790,
12242
    X86_INS_VBROADCASTI32X4 = 791,
12243
    X86_INS_VBROADCASTI32X8 = 792,
12244
    X86_INS_VBROADCASTI64X2 = 793,
12245
    X86_INS_VBROADCASTI64X4 = 794,
12246
    X86_INS_VBROADCASTSD = 795,
12247
    X86_INS_VBROADCASTSS = 796,
12248
    X86_INS_VCMP = 797,
12249
    X86_INS_VCMPPD = 798,
12250
    X86_INS_VCMPPS = 799,
12251
    X86_INS_VCMPSD = 800,
12252
    X86_INS_VCMPSS = 801,
12253
    X86_INS_VCOMISD = 802,
12254
    X86_INS_VCOMISS = 803,
12255
    X86_INS_VCOMPRESSPD = 804,
12256
    X86_INS_VCOMPRESSPS = 805,
12257
    X86_INS_VCVTDQ2PD = 806,
12258
    X86_INS_VCVTDQ2PS = 807,
12259
    X86_INS_VCVTPD2DQ = 808,
12260
    X86_INS_VCVTPD2PS = 809,
12261
    X86_INS_VCVTPD2QQ = 810,
12262
    X86_INS_VCVTPD2UDQ = 811,
12263
    X86_INS_VCVTPD2UQQ = 812,
12264
    X86_INS_VCVTPH2PS = 813,
12265
    X86_INS_VCVTPS2DQ = 814,
12266
    X86_INS_VCVTPS2PD = 815,
12267
    X86_INS_VCVTPS2PH = 816,
12268
    X86_INS_VCVTPS2QQ = 817,
12269
    X86_INS_VCVTPS2UDQ = 818,
12270
    X86_INS_VCVTPS2UQQ = 819,
12271
    X86_INS_VCVTQQ2PD = 820,
12272
    X86_INS_VCVTQQ2PS = 821,
12273
    X86_INS_VCVTSD2SI = 822,
12274
    X86_INS_VCVTSD2SS = 823,
12275
    X86_INS_VCVTSD2USI = 824,
12276
    X86_INS_VCVTSI2SD = 825,
12277
    X86_INS_VCVTSI2SS = 826,
12278
    X86_INS_VCVTSS2SD = 827,
12279
    X86_INS_VCVTSS2SI = 828,
12280
    X86_INS_VCVTSS2USI = 829,
12281
    X86_INS_VCVTTPD2DQ = 830,
12282
    X86_INS_VCVTTPD2QQ = 831,
12283
    X86_INS_VCVTTPD2UDQ = 832,
12284
    X86_INS_VCVTTPD2UQQ = 833,
12285
    X86_INS_VCVTTPS2DQ = 834,
12286
    X86_INS_VCVTTPS2QQ = 835,
12287
    X86_INS_VCVTTPS2UDQ = 836,
12288
    X86_INS_VCVTTPS2UQQ = 837,
12289
    X86_INS_VCVTTSD2SI = 838,
12290
    X86_INS_VCVTTSD2USI = 839,
12291
    X86_INS_VCVTTSS2SI = 840,
12292
    X86_INS_VCVTTSS2USI = 841,
12293
    X86_INS_VCVTUDQ2PD = 842,
12294
    X86_INS_VCVTUDQ2PS = 843,
12295
    X86_INS_VCVTUQQ2PD = 844,
12296
    X86_INS_VCVTUQQ2PS = 845,
12297
    X86_INS_VCVTUSI2SD = 846,
12298
    X86_INS_VCVTUSI2SS = 847,
12299
    X86_INS_VDBPSADBW = 848,
12300
    X86_INS_VDIVPD = 849,
12301
    X86_INS_VDIVPS = 850,
12302
    X86_INS_VDIVSD = 851,
12303
    X86_INS_VDIVSS = 852,
12304
    X86_INS_VDPPD = 853,
12305
    X86_INS_VDPPS = 854,
12306
    X86_INS_VERR = 855,
12307
    X86_INS_VERW = 856,
12308
    X86_INS_VEXP2PD = 857,
12309
    X86_INS_VEXP2PS = 858,
12310
    X86_INS_VEXPANDPD = 859,
12311
    X86_INS_VEXPANDPS = 860,
12312
    X86_INS_VEXTRACTF128 = 861,
12313
    X86_INS_VEXTRACTF32X4 = 862,
12314
    X86_INS_VEXTRACTF32X8 = 863,
12315
    X86_INS_VEXTRACTF64X2 = 864,
12316
    X86_INS_VEXTRACTF64X4 = 865,
12317
    X86_INS_VEXTRACTI128 = 866,
12318
    X86_INS_VEXTRACTI32X4 = 867,
12319
    X86_INS_VEXTRACTI32X8 = 868,
12320
    X86_INS_VEXTRACTI64X2 = 869,
12321
    X86_INS_VEXTRACTI64X4 = 870,
12322
    X86_INS_VEXTRACTPS = 871,
12323
    X86_INS_VFIXUPIMMPD = 872,
12324
    X86_INS_VFIXUPIMMPS = 873,
12325
    X86_INS_VFIXUPIMMSD = 874,
12326
    X86_INS_VFIXUPIMMSS = 875,
12327
    X86_INS_VFMADD132PD = 876,
12328
    X86_INS_VFMADD132PS = 877,
12329
    X86_INS_VFMADD132SD = 878,
12330
    X86_INS_VFMADD132SS = 879,
12331
    X86_INS_VFMADD213PD = 880,
12332
    X86_INS_VFMADD213PS = 881,
12333
    X86_INS_VFMADD213SD = 882,
12334
    X86_INS_VFMADD213SS = 883,
12335
    X86_INS_VFMADD231PD = 884,
12336
    X86_INS_VFMADD231PS = 885,
12337
    X86_INS_VFMADD231SD = 886,
12338
    X86_INS_VFMADD231SS = 887,
12339
    X86_INS_VFMADDPD = 888,
12340
    X86_INS_VFMADDPS = 889,
12341
    X86_INS_VFMADDSD = 890,
12342
    X86_INS_VFMADDSS = 891,
12343
    X86_INS_VFMADDSUB132PD = 892,
12344
    X86_INS_VFMADDSUB132PS = 893,
12345
    X86_INS_VFMADDSUB213PD = 894,
12346
    X86_INS_VFMADDSUB213PS = 895,
12347
    X86_INS_VFMADDSUB231PD = 896,
12348
    X86_INS_VFMADDSUB231PS = 897,
12349
    X86_INS_VFMADDSUBPD = 898,
12350
    X86_INS_VFMADDSUBPS = 899,
12351
    X86_INS_VFMSUB132PD = 900,
12352
    X86_INS_VFMSUB132PS = 901,
12353
    X86_INS_VFMSUB132SD = 902,
12354
    X86_INS_VFMSUB132SS = 903,
12355
    X86_INS_VFMSUB213PD = 904,
12356
    X86_INS_VFMSUB213PS = 905,
12357
    X86_INS_VFMSUB213SD = 906,
12358
    X86_INS_VFMSUB213SS = 907,
12359
    X86_INS_VFMSUB231PD = 908,
12360
    X86_INS_VFMSUB231PS = 909,
12361
    X86_INS_VFMSUB231SD = 910,
12362
    X86_INS_VFMSUB231SS = 911,
12363
    X86_INS_VFMSUBADD132PD = 912,
12364
    X86_INS_VFMSUBADD132PS = 913,
12365
    X86_INS_VFMSUBADD213PD = 914,
12366
    X86_INS_VFMSUBADD213PS = 915,
12367
    X86_INS_VFMSUBADD231PD = 916,
12368
    X86_INS_VFMSUBADD231PS = 917,
12369
    X86_INS_VFMSUBADDPD = 918,
12370
    X86_INS_VFMSUBADDPS = 919,
12371
    X86_INS_VFMSUBPD = 920,
12372
    X86_INS_VFMSUBPS = 921,
12373
    X86_INS_VFMSUBSD = 922,
12374
    X86_INS_VFMSUBSS = 923,
12375
    X86_INS_VFNMADD132PD = 924,
12376
    X86_INS_VFNMADD132PS = 925,
12377
    X86_INS_VFNMADD132SD = 926,
12378
    X86_INS_VFNMADD132SS = 927,
12379
    X86_INS_VFNMADD213PD = 928,
12380
    X86_INS_VFNMADD213PS = 929,
12381
    X86_INS_VFNMADD213SD = 930,
12382
    X86_INS_VFNMADD213SS = 931,
12383
    X86_INS_VFNMADD231PD = 932,
12384
    X86_INS_VFNMADD231PS = 933,
12385
    X86_INS_VFNMADD231SD = 934,
12386
    X86_INS_VFNMADD231SS = 935,
12387
    X86_INS_VFNMADDPD = 936,
12388
    X86_INS_VFNMADDPS = 937,
12389
    X86_INS_VFNMADDSD = 938,
12390
    X86_INS_VFNMADDSS = 939,
12391
    X86_INS_VFNMSUB132PD = 940,
12392
    X86_INS_VFNMSUB132PS = 941,
12393
    X86_INS_VFNMSUB132SD = 942,
12394
    X86_INS_VFNMSUB132SS = 943,
12395
    X86_INS_VFNMSUB213PD = 944,
12396
    X86_INS_VFNMSUB213PS = 945,
12397
    X86_INS_VFNMSUB213SD = 946,
12398
    X86_INS_VFNMSUB213SS = 947,
12399
    X86_INS_VFNMSUB231PD = 948,
12400
    X86_INS_VFNMSUB231PS = 949,
12401
    X86_INS_VFNMSUB231SD = 950,
12402
    X86_INS_VFNMSUB231SS = 951,
12403
    X86_INS_VFNMSUBPD = 952,
12404
    X86_INS_VFNMSUBPS = 953,
12405
    X86_INS_VFNMSUBSD = 954,
12406
    X86_INS_VFNMSUBSS = 955,
12407
    X86_INS_VFPCLASSPD = 956,
12408
    X86_INS_VFPCLASSPS = 957,
12409
    X86_INS_VFPCLASSSD = 958,
12410
    X86_INS_VFPCLASSSS = 959,
12411
    X86_INS_VFRCZPD = 960,
12412
    X86_INS_VFRCZPS = 961,
12413
    X86_INS_VFRCZSD = 962,
12414
    X86_INS_VFRCZSS = 963,
12415
    X86_INS_VGATHERDPD = 964,
12416
    X86_INS_VGATHERDPS = 965,
12417
    X86_INS_VGATHERPF0DPD = 966,
12418
    X86_INS_VGATHERPF0DPS = 967,
12419
    X86_INS_VGATHERPF0QPD = 968,
12420
    X86_INS_VGATHERPF0QPS = 969,
12421
    X86_INS_VGATHERPF1DPD = 970,
12422
    X86_INS_VGATHERPF1DPS = 971,
12423
    X86_INS_VGATHERPF1QPD = 972,
12424
    X86_INS_VGATHERPF1QPS = 973,
12425
    X86_INS_VGATHERQPD = 974,
12426
    X86_INS_VGATHERQPS = 975,
12427
    X86_INS_VGETEXPPD = 976,
12428
    X86_INS_VGETEXPPS = 977,
12429
    X86_INS_VGETEXPSD = 978,
12430
    X86_INS_VGETEXPSS = 979,
12431
    X86_INS_VGETMANTPD = 980,
12432
    X86_INS_VGETMANTPS = 981,
12433
    X86_INS_VGETMANTSD = 982,
12434
    X86_INS_VGETMANTSS = 983,
12435
    X86_INS_VGF2P8AFFINEINVQB = 984,
12436
    X86_INS_VGF2P8AFFINEQB = 985,
12437
    X86_INS_VGF2P8MULB = 986,
12438
    X86_INS_VHADDPD = 987,
12439
    X86_INS_VHADDPS = 988,
12440
    X86_INS_VHSUBPD = 989,
12441
    X86_INS_VHSUBPS = 990,
12442
    X86_INS_VINSERTF128 = 991,
12443
    X86_INS_VINSERTF32X4 = 992,
12444
    X86_INS_VINSERTF32X8 = 993,
12445
    X86_INS_VINSERTF64X2 = 994,
12446
    X86_INS_VINSERTF64X4 = 995,
12447
    X86_INS_VINSERTI128 = 996,
12448
    X86_INS_VINSERTI32X4 = 997,
12449
    X86_INS_VINSERTI32X8 = 998,
12450
    X86_INS_VINSERTI64X2 = 999,
12451
    X86_INS_VINSERTI64X4 = 1000,
12452
    X86_INS_VINSERTPS = 1001,
12453
    X86_INS_VLDDQU = 1002,
12454
    X86_INS_VLDMXCSR = 1003,
12455
    X86_INS_VMASKMOVDQU = 1004,
12456
    X86_INS_VMASKMOVPD = 1005,
12457
    X86_INS_VMASKMOVPS = 1006,
12458
    X86_INS_VMAXPD = 1007,
12459
    X86_INS_VMAXPS = 1008,
12460
    X86_INS_VMAXSD = 1009,
12461
    X86_INS_VMAXSS = 1010,
12462
    X86_INS_VMCALL = 1011,
12463
    X86_INS_VMCLEAR = 1012,
12464
    X86_INS_VMFUNC = 1013,
12465
    X86_INS_VMINPD = 1014,
12466
    X86_INS_VMINPS = 1015,
12467
    X86_INS_VMINSD = 1016,
12468
    X86_INS_VMINSS = 1017,
12469
    X86_INS_VMLAUNCH = 1018,
12470
    X86_INS_VMLOAD = 1019,
12471
    X86_INS_VMMCALL = 1020,
12472
    X86_INS_VMOVQ = 1021,
12473
    X86_INS_VMOVAPD = 1022,
12474
    X86_INS_VMOVAPS = 1023,
12475
    X86_INS_VMOVDDUP = 1024,
12476
    X86_INS_VMOVD = 1025,
12477
    X86_INS_VMOVDQA32 = 1026,
12478
    X86_INS_VMOVDQA64 = 1027,
12479
    X86_INS_VMOVDQA = 1028,
12480
    X86_INS_VMOVDQU16 = 1029,
12481
    X86_INS_VMOVDQU32 = 1030,
12482
    X86_INS_VMOVDQU64 = 1031,
12483
    X86_INS_VMOVDQU8 = 1032,
12484
    X86_INS_VMOVDQU = 1033,
12485
    X86_INS_VMOVHLPS = 1034,
12486
    X86_INS_VMOVHPD = 1035,
12487
    X86_INS_VMOVHPS = 1036,
12488
    X86_INS_VMOVLHPS = 1037,
12489
    X86_INS_VMOVLPD = 1038,
12490
    X86_INS_VMOVLPS = 1039,
12491
    X86_INS_VMOVMSKPD = 1040,
12492
    X86_INS_VMOVMSKPS = 1041,
12493
    X86_INS_VMOVNTDQA = 1042,
12494
    X86_INS_VMOVNTDQ = 1043,
12495
    X86_INS_VMOVNTPD = 1044,
12496
    X86_INS_VMOVNTPS = 1045,
12497
    X86_INS_VMOVSD = 1046,
12498
    X86_INS_VMOVSHDUP = 1047,
12499
    X86_INS_VMOVSLDUP = 1048,
12500
    X86_INS_VMOVSS = 1049,
12501
    X86_INS_VMOVUPD = 1050,
12502
    X86_INS_VMOVUPS = 1051,
12503
    X86_INS_VMPSADBW = 1052,
12504
    X86_INS_VMPTRLD = 1053,
12505
    X86_INS_VMPTRST = 1054,
12506
    X86_INS_VMREAD = 1055,
12507
    X86_INS_VMRESUME = 1056,
12508
    X86_INS_VMRUN = 1057,
12509
    X86_INS_VMSAVE = 1058,
12510
    X86_INS_VMULPD = 1059,
12511
    X86_INS_VMULPS = 1060,
12512
    X86_INS_VMULSD = 1061,
12513
    X86_INS_VMULSS = 1062,
12514
    X86_INS_VMWRITE = 1063,
12515
    X86_INS_VMXOFF = 1064,
12516
    X86_INS_VMXON = 1065,
12517
    X86_INS_VORPD = 1066,
12518
    X86_INS_VORPS = 1067,
12519
    X86_INS_VP4DPWSSDS = 1068,
12520
    X86_INS_VP4DPWSSD = 1069,
12521
    X86_INS_VPABSB = 1070,
12522
    X86_INS_VPABSD = 1071,
12523
    X86_INS_VPABSQ = 1072,
12524
    X86_INS_VPABSW = 1073,
12525
    X86_INS_VPACKSSDW = 1074,
12526
    X86_INS_VPACKSSWB = 1075,
12527
    X86_INS_VPACKUSDW = 1076,
12528
    X86_INS_VPACKUSWB = 1077,
12529
    X86_INS_VPADDB = 1078,
12530
    X86_INS_VPADDD = 1079,
12531
    X86_INS_VPADDQ = 1080,
12532
    X86_INS_VPADDSB = 1081,
12533
    X86_INS_VPADDSW = 1082,
12534
    X86_INS_VPADDUSB = 1083,
12535
    X86_INS_VPADDUSW = 1084,
12536
    X86_INS_VPADDW = 1085,
12537
    X86_INS_VPALIGNR = 1086,
12538
    X86_INS_VPANDD = 1087,
12539
    X86_INS_VPANDND = 1088,
12540
    X86_INS_VPANDNQ = 1089,
12541
    X86_INS_VPANDN = 1090,
12542
    X86_INS_VPANDQ = 1091,
12543
    X86_INS_VPAND = 1092,
12544
    X86_INS_VPAVGB = 1093,
12545
    X86_INS_VPAVGW = 1094,
12546
    X86_INS_VPBLENDD = 1095,
12547
    X86_INS_VPBLENDMB = 1096,
12548
    X86_INS_VPBLENDMD = 1097,
12549
    X86_INS_VPBLENDMQ = 1098,
12550
    X86_INS_VPBLENDMW = 1099,
12551
    X86_INS_VPBLENDVB = 1100,
12552
    X86_INS_VPBLENDW = 1101,
12553
    X86_INS_VPBROADCASTB = 1102,
12554
    X86_INS_VPBROADCASTD = 1103,
12555
    X86_INS_VPBROADCASTMB2Q = 1104,
12556
    X86_INS_VPBROADCASTMW2D = 1105,
12557
    X86_INS_VPBROADCASTQ = 1106,
12558
    X86_INS_VPBROADCASTW = 1107,
12559
    X86_INS_VPCLMULQDQ = 1108,
12560
    X86_INS_VPCMOV = 1109,
12561
    X86_INS_VPCMP = 1110,
12562
    X86_INS_VPCMPB = 1111,
12563
    X86_INS_VPCMPD = 1112,
12564
    X86_INS_VPCMPEQB = 1113,
12565
    X86_INS_VPCMPEQD = 1114,
12566
    X86_INS_VPCMPEQQ = 1115,
12567
    X86_INS_VPCMPEQW = 1116,
12568
    X86_INS_VPCMPESTRI = 1117,
12569
    X86_INS_VPCMPESTRM = 1118,
12570
    X86_INS_VPCMPGTB = 1119,
12571
    X86_INS_VPCMPGTD = 1120,
12572
    X86_INS_VPCMPGTQ = 1121,
12573
    X86_INS_VPCMPGTW = 1122,
12574
    X86_INS_VPCMPISTRI = 1123,
12575
    X86_INS_VPCMPISTRM = 1124,
12576
    X86_INS_VPCMPQ = 1125,
12577
    X86_INS_VPCMPUB = 1126,
12578
    X86_INS_VPCMPUD = 1127,
12579
    X86_INS_VPCMPUQ = 1128,
12580
    X86_INS_VPCMPUW = 1129,
12581
    X86_INS_VPCMPW = 1130,
12582
    X86_INS_VPCOM = 1131,
12583
    X86_INS_VPCOMB = 1132,
12584
    X86_INS_VPCOMD = 1133,
12585
    X86_INS_VPCOMPRESSB = 1134,
12586
    X86_INS_VPCOMPRESSD = 1135,
12587
    X86_INS_VPCOMPRESSQ = 1136,
12588
    X86_INS_VPCOMPRESSW = 1137,
12589
    X86_INS_VPCOMQ = 1138,
12590
    X86_INS_VPCOMUB = 1139,
12591
    X86_INS_VPCOMUD = 1140,
12592
    X86_INS_VPCOMUQ = 1141,
12593
    X86_INS_VPCOMUW = 1142,
12594
    X86_INS_VPCOMW = 1143,
12595
    X86_INS_VPCONFLICTD = 1144,
12596
    X86_INS_VPCONFLICTQ = 1145,
12597
    X86_INS_VPDPBUSDS = 1146,
12598
    X86_INS_VPDPBUSD = 1147,
12599
    X86_INS_VPDPWSSDS = 1148,
12600
    X86_INS_VPDPWSSD = 1149,
12601
    X86_INS_VPERM2F128 = 1150,
12602
    X86_INS_VPERM2I128 = 1151,
12603
    X86_INS_VPERMB = 1152,
12604
    X86_INS_VPERMD = 1153,
12605
    X86_INS_VPERMI2B = 1154,
12606
    X86_INS_VPERMI2D = 1155,
12607
    X86_INS_VPERMI2PD = 1156,
12608
    X86_INS_VPERMI2PS = 1157,
12609
    X86_INS_VPERMI2Q = 1158,
12610
    X86_INS_VPERMI2W = 1159,
12611
    X86_INS_VPERMIL2PD = 1160,
12612
    X86_INS_VPERMILPD = 1161,
12613
    X86_INS_VPERMIL2PS = 1162,
12614
    X86_INS_VPERMILPS = 1163,
12615
    X86_INS_VPERMPD = 1164,
12616
    X86_INS_VPERMPS = 1165,
12617
    X86_INS_VPERMQ = 1166,
12618
    X86_INS_VPERMT2B = 1167,
12619
    X86_INS_VPERMT2D = 1168,
12620
    X86_INS_VPERMT2PD = 1169,
12621
    X86_INS_VPERMT2PS = 1170,
12622
    X86_INS_VPERMT2Q = 1171,
12623
    X86_INS_VPERMT2W = 1172,
12624
    X86_INS_VPERMW = 1173,
12625
    X86_INS_VPEXPANDB = 1174,
12626
    X86_INS_VPEXPANDD = 1175,
12627
    X86_INS_VPEXPANDQ = 1176,
12628
    X86_INS_VPEXPANDW = 1177,
12629
    X86_INS_VPEXTRB = 1178,
12630
    X86_INS_VPEXTRD = 1179,
12631
    X86_INS_VPEXTRQ = 1180,
12632
    X86_INS_VPEXTRW = 1181,
12633
    X86_INS_VPGATHERDD = 1182,
12634
    X86_INS_VPGATHERDQ = 1183,
12635
    X86_INS_VPGATHERQD = 1184,
12636
    X86_INS_VPGATHERQQ = 1185,
12637
    X86_INS_VPHADDBD = 1186,
12638
    X86_INS_VPHADDBQ = 1187,
12639
    X86_INS_VPHADDBW = 1188,
12640
    X86_INS_VPHADDDQ = 1189,
12641
    X86_INS_VPHADDD = 1190,
12642
    X86_INS_VPHADDSW = 1191,
12643
    X86_INS_VPHADDUBD = 1192,
12644
    X86_INS_VPHADDUBQ = 1193,
12645
    X86_INS_VPHADDUBW = 1194,
12646
    X86_INS_VPHADDUDQ = 1195,
12647
    X86_INS_VPHADDUWD = 1196,
12648
    X86_INS_VPHADDUWQ = 1197,
12649
    X86_INS_VPHADDWD = 1198,
12650
    X86_INS_VPHADDWQ = 1199,
12651
    X86_INS_VPHADDW = 1200,
12652
    X86_INS_VPHMINPOSUW = 1201,
12653
    X86_INS_VPHSUBBW = 1202,
12654
    X86_INS_VPHSUBDQ = 1203,
12655
    X86_INS_VPHSUBD = 1204,
12656
    X86_INS_VPHSUBSW = 1205,
12657
    X86_INS_VPHSUBWD = 1206,
12658
    X86_INS_VPHSUBW = 1207,
12659
    X86_INS_VPINSRB = 1208,
12660
    X86_INS_VPINSRD = 1209,
12661
    X86_INS_VPINSRQ = 1210,
12662
    X86_INS_VPINSRW = 1211,
12663
    X86_INS_VPLZCNTD = 1212,
12664
    X86_INS_VPLZCNTQ = 1213,
12665
    X86_INS_VPMACSDD = 1214,
12666
    X86_INS_VPMACSDQH = 1215,
12667
    X86_INS_VPMACSDQL = 1216,
12668
    X86_INS_VPMACSSDD = 1217,
12669
    X86_INS_VPMACSSDQH = 1218,
12670
    X86_INS_VPMACSSDQL = 1219,
12671
    X86_INS_VPMACSSWD = 1220,
12672
    X86_INS_VPMACSSWW = 1221,
12673
    X86_INS_VPMACSWD = 1222,
12674
    X86_INS_VPMACSWW = 1223,
12675
    X86_INS_VPMADCSSWD = 1224,
12676
    X86_INS_VPMADCSWD = 1225,
12677
    X86_INS_VPMADD52HUQ = 1226,
12678
    X86_INS_VPMADD52LUQ = 1227,
12679
    X86_INS_VPMADDUBSW = 1228,
12680
    X86_INS_VPMADDWD = 1229,
12681
    X86_INS_VPMASKMOVD = 1230,
12682
    X86_INS_VPMASKMOVQ = 1231,
12683
    X86_INS_VPMAXSB = 1232,
12684
    X86_INS_VPMAXSD = 1233,
12685
    X86_INS_VPMAXSQ = 1234,
12686
    X86_INS_VPMAXSW = 1235,
12687
    X86_INS_VPMAXUB = 1236,
12688
    X86_INS_VPMAXUD = 1237,
12689
    X86_INS_VPMAXUQ = 1238,
12690
    X86_INS_VPMAXUW = 1239,
12691
    X86_INS_VPMINSB = 1240,
12692
    X86_INS_VPMINSD = 1241,
12693
    X86_INS_VPMINSQ = 1242,
12694
    X86_INS_VPMINSW = 1243,
12695
    X86_INS_VPMINUB = 1244,
12696
    X86_INS_VPMINUD = 1245,
12697
    X86_INS_VPMINUQ = 1246,
12698
    X86_INS_VPMINUW = 1247,
12699
    X86_INS_VPMOVB2M = 1248,
12700
    X86_INS_VPMOVD2M = 1249,
12701
    X86_INS_VPMOVDB = 1250,
12702
    X86_INS_VPMOVDW = 1251,
12703
    X86_INS_VPMOVM2B = 1252,
12704
    X86_INS_VPMOVM2D = 1253,
12705
    X86_INS_VPMOVM2Q = 1254,
12706
    X86_INS_VPMOVM2W = 1255,
12707
    X86_INS_VPMOVMSKB = 1256,
12708
    X86_INS_VPMOVQ2M = 1257,
12709
    X86_INS_VPMOVQB = 1258,
12710
    X86_INS_VPMOVQD = 1259,
12711
    X86_INS_VPMOVQW = 1260,
12712
    X86_INS_VPMOVSDB = 1261,
12713
    X86_INS_VPMOVSDW = 1262,
12714
    X86_INS_VPMOVSQB = 1263,
12715
    X86_INS_VPMOVSQD = 1264,
12716
    X86_INS_VPMOVSQW = 1265,
12717
    X86_INS_VPMOVSWB = 1266,
12718
    X86_INS_VPMOVSXBD = 1267,
12719
    X86_INS_VPMOVSXBQ = 1268,
12720
    X86_INS_VPMOVSXBW = 1269,
12721
    X86_INS_VPMOVSXDQ = 1270,
12722
    X86_INS_VPMOVSXWD = 1271,
12723
    X86_INS_VPMOVSXWQ = 1272,
12724
    X86_INS_VPMOVUSDB = 1273,
12725
    X86_INS_VPMOVUSDW = 1274,
12726
    X86_INS_VPMOVUSQB = 1275,
12727
    X86_INS_VPMOVUSQD = 1276,
12728
    X86_INS_VPMOVUSQW = 1277,
12729
    X86_INS_VPMOVUSWB = 1278,
12730
    X86_INS_VPMOVW2M = 1279,
12731
    X86_INS_VPMOVWB = 1280,
12732
    X86_INS_VPMOVZXBD = 1281,
12733
    X86_INS_VPMOVZXBQ = 1282,
12734
    X86_INS_VPMOVZXBW = 1283,
12735
    X86_INS_VPMOVZXDQ = 1284,
12736
    X86_INS_VPMOVZXWD = 1285,
12737
    X86_INS_VPMOVZXWQ = 1286,
12738
    X86_INS_VPMULDQ = 1287,
12739
    X86_INS_VPMULHRSW = 1288,
12740
    X86_INS_VPMULHUW = 1289,
12741
    X86_INS_VPMULHW = 1290,
12742
    X86_INS_VPMULLD = 1291,
12743
    X86_INS_VPMULLQ = 1292,
12744
    X86_INS_VPMULLW = 1293,
12745
    X86_INS_VPMULTISHIFTQB = 1294,
12746
    X86_INS_VPMULUDQ = 1295,
12747
    X86_INS_VPOPCNTB = 1296,
12748
    X86_INS_VPOPCNTD = 1297,
12749
    X86_INS_VPOPCNTQ = 1298,
12750
    X86_INS_VPOPCNTW = 1299,
12751
    X86_INS_VPORD = 1300,
12752
    X86_INS_VPORQ = 1301,
12753
    X86_INS_VPOR = 1302,
12754
    X86_INS_VPPERM = 1303,
12755
    X86_INS_VPROLD = 1304,
12756
    X86_INS_VPROLQ = 1305,
12757
    X86_INS_VPROLVD = 1306,
12758
    X86_INS_VPROLVQ = 1307,
12759
    X86_INS_VPRORD = 1308,
12760
    X86_INS_VPRORQ = 1309,
12761
    X86_INS_VPRORVD = 1310,
12762
    X86_INS_VPRORVQ = 1311,
12763
    X86_INS_VPROTB = 1312,
12764
    X86_INS_VPROTD = 1313,
12765
    X86_INS_VPROTQ = 1314,
12766
    X86_INS_VPROTW = 1315,
12767
    X86_INS_VPSADBW = 1316,
12768
    X86_INS_VPSCATTERDD = 1317,
12769
    X86_INS_VPSCATTERDQ = 1318,
12770
    X86_INS_VPSCATTERQD = 1319,
12771
    X86_INS_VPSCATTERQQ = 1320,
12772
    X86_INS_VPSHAB = 1321,
12773
    X86_INS_VPSHAD = 1322,
12774
    X86_INS_VPSHAQ = 1323,
12775
    X86_INS_VPSHAW = 1324,
12776
    X86_INS_VPSHLB = 1325,
12777
    X86_INS_VPSHLDD = 1326,
12778
    X86_INS_VPSHLDQ = 1327,
12779
    X86_INS_VPSHLDVD = 1328,
12780
    X86_INS_VPSHLDVQ = 1329,
12781
    X86_INS_VPSHLDVW = 1330,
12782
    X86_INS_VPSHLDW = 1331,
12783
    X86_INS_VPSHLD = 1332,
12784
    X86_INS_VPSHLQ = 1333,
12785
    X86_INS_VPSHLW = 1334,
12786
    X86_INS_VPSHRDD = 1335,
12787
    X86_INS_VPSHRDQ = 1336,
12788
    X86_INS_VPSHRDVD = 1337,
12789
    X86_INS_VPSHRDVQ = 1338,
12790
    X86_INS_VPSHRDVW = 1339,
12791
    X86_INS_VPSHRDW = 1340,
12792
    X86_INS_VPSHUFBITQMB = 1341,
12793
    X86_INS_VPSHUFB = 1342,
12794
    X86_INS_VPSHUFD = 1343,
12795
    X86_INS_VPSHUFHW = 1344,
12796
    X86_INS_VPSHUFLW = 1345,
12797
    X86_INS_VPSIGNB = 1346,
12798
    X86_INS_VPSIGND = 1347,
12799
    X86_INS_VPSIGNW = 1348,
12800
    X86_INS_VPSLLDQ = 1349,
12801
    X86_INS_VPSLLD = 1350,
12802
    X86_INS_VPSLLQ = 1351,
12803
    X86_INS_VPSLLVD = 1352,
12804
    X86_INS_VPSLLVQ = 1353,
12805
    X86_INS_VPSLLVW = 1354,
12806
    X86_INS_VPSLLW = 1355,
12807
    X86_INS_VPSRAD = 1356,
12808
    X86_INS_VPSRAQ = 1357,
12809
    X86_INS_VPSRAVD = 1358,
12810
    X86_INS_VPSRAVQ = 1359,
12811
    X86_INS_VPSRAVW = 1360,
12812
    X86_INS_VPSRAW = 1361,
12813
    X86_INS_VPSRLDQ = 1362,
12814
    X86_INS_VPSRLD = 1363,
12815
    X86_INS_VPSRLQ = 1364,
12816
    X86_INS_VPSRLVD = 1365,
12817
    X86_INS_VPSRLVQ = 1366,
12818
    X86_INS_VPSRLVW = 1367,
12819
    X86_INS_VPSRLW = 1368,
12820
    X86_INS_VPSUBB = 1369,
12821
    X86_INS_VPSUBD = 1370,
12822
    X86_INS_VPSUBQ = 1371,
12823
    X86_INS_VPSUBSB = 1372,
12824
    X86_INS_VPSUBSW = 1373,
12825
    X86_INS_VPSUBUSB = 1374,
12826
    X86_INS_VPSUBUSW = 1375,
12827
    X86_INS_VPSUBW = 1376,
12828
    X86_INS_VPTERNLOGD = 1377,
12829
    X86_INS_VPTERNLOGQ = 1378,
12830
    X86_INS_VPTESTMB = 1379,
12831
    X86_INS_VPTESTMD = 1380,
12832
    X86_INS_VPTESTMQ = 1381,
12833
    X86_INS_VPTESTMW = 1382,
12834
    X86_INS_VPTESTNMB = 1383,
12835
    X86_INS_VPTESTNMD = 1384,
12836
    X86_INS_VPTESTNMQ = 1385,
12837
    X86_INS_VPTESTNMW = 1386,
12838
    X86_INS_VPTEST = 1387,
12839
    X86_INS_VPUNPCKHBW = 1388,
12840
    X86_INS_VPUNPCKHDQ = 1389,
12841
    X86_INS_VPUNPCKHQDQ = 1390,
12842
    X86_INS_VPUNPCKHWD = 1391,
12843
    X86_INS_VPUNPCKLBW = 1392,
12844
    X86_INS_VPUNPCKLDQ = 1393,
12845
    X86_INS_VPUNPCKLQDQ = 1394,
12846
    X86_INS_VPUNPCKLWD = 1395,
12847
    X86_INS_VPXORD = 1396,
12848
    X86_INS_VPXORQ = 1397,
12849
    X86_INS_VPXOR = 1398,
12850
    X86_INS_VRANGEPD = 1399,
12851
    X86_INS_VRANGEPS = 1400,
12852
    X86_INS_VRANGESD = 1401,
12853
    X86_INS_VRANGESS = 1402,
12854
    X86_INS_VRCP14PD = 1403,
12855
    X86_INS_VRCP14PS = 1404,
12856
    X86_INS_VRCP14SD = 1405,
12857
    X86_INS_VRCP14SS = 1406,
12858
    X86_INS_VRCP28PD = 1407,
12859
    X86_INS_VRCP28PS = 1408,
12860
    X86_INS_VRCP28SD = 1409,
12861
    X86_INS_VRCP28SS = 1410,
12862
    X86_INS_VRCPPS = 1411,
12863
    X86_INS_VRCPSS = 1412,
12864
    X86_INS_VREDUCEPD = 1413,
12865
    X86_INS_VREDUCEPS = 1414,
12866
    X86_INS_VREDUCESD = 1415,
12867
    X86_INS_VREDUCESS = 1416,
12868
    X86_INS_VRNDSCALEPD = 1417,
12869
    X86_INS_VRNDSCALEPS = 1418,
12870
    X86_INS_VRNDSCALESD = 1419,
12871
    X86_INS_VRNDSCALESS = 1420,
12872
    X86_INS_VROUNDPD = 1421,
12873
    X86_INS_VROUNDPS = 1422,
12874
    X86_INS_VROUNDSD = 1423,
12875
    X86_INS_VROUNDSS = 1424,
12876
    X86_INS_VRSQRT14PD = 1425,
12877
    X86_INS_VRSQRT14PS = 1426,
12878
    X86_INS_VRSQRT14SD = 1427,
12879
    X86_INS_VRSQRT14SS = 1428,
12880
    X86_INS_VRSQRT28PD = 1429,
12881
    X86_INS_VRSQRT28PS = 1430,
12882
    X86_INS_VRSQRT28SD = 1431,
12883
    X86_INS_VRSQRT28SS = 1432,
12884
    X86_INS_VRSQRTPS = 1433,
12885
    X86_INS_VRSQRTSS = 1434,
12886
    X86_INS_VSCALEFPD = 1435,
12887
    X86_INS_VSCALEFPS = 1436,
12888
    X86_INS_VSCALEFSD = 1437,
12889
    X86_INS_VSCALEFSS = 1438,
12890
    X86_INS_VSCATTERDPD = 1439,
12891
    X86_INS_VSCATTERDPS = 1440,
12892
    X86_INS_VSCATTERPF0DPD = 1441,
12893
    X86_INS_VSCATTERPF0DPS = 1442,
12894
    X86_INS_VSCATTERPF0QPD = 1443,
12895
    X86_INS_VSCATTERPF0QPS = 1444,
12896
    X86_INS_VSCATTERPF1DPD = 1445,
12897
    X86_INS_VSCATTERPF1DPS = 1446,
12898
    X86_INS_VSCATTERPF1QPD = 1447,
12899
    X86_INS_VSCATTERPF1QPS = 1448,
12900
    X86_INS_VSCATTERQPD = 1449,
12901
    X86_INS_VSCATTERQPS = 1450,
12902
    X86_INS_VSHUFF32X4 = 1451,
12903
    X86_INS_VSHUFF64X2 = 1452,
12904
    X86_INS_VSHUFI32X4 = 1453,
12905
    X86_INS_VSHUFI64X2 = 1454,
12906
    X86_INS_VSHUFPD = 1455,
12907
    X86_INS_VSHUFPS = 1456,
12908
    X86_INS_VSQRTPD = 1457,
12909
    X86_INS_VSQRTPS = 1458,
12910
    X86_INS_VSQRTSD = 1459,
12911
    X86_INS_VSQRTSS = 1460,
12912
    X86_INS_VSTMXCSR = 1461,
12913
    X86_INS_VSUBPD = 1462,
12914
    X86_INS_VSUBPS = 1463,
12915
    X86_INS_VSUBSD = 1464,
12916
    X86_INS_VSUBSS = 1465,
12917
    X86_INS_VTESTPD = 1466,
12918
    X86_INS_VTESTPS = 1467,
12919
    X86_INS_VUCOMISD = 1468,
12920
    X86_INS_VUCOMISS = 1469,
12921
    X86_INS_VUNPCKHPD = 1470,
12922
    X86_INS_VUNPCKHPS = 1471,
12923
    X86_INS_VUNPCKLPD = 1472,
12924
    X86_INS_VUNPCKLPS = 1473,
12925
    X86_INS_VXORPD = 1474,
12926
    X86_INS_VXORPS = 1475,
12927
    X86_INS_VZEROALL = 1476,
12928
    X86_INS_VZEROUPPER = 1477,
12929
    X86_INS_WAIT = 1478,
12930
    X86_INS_WBINVD = 1479,
12931
    X86_INS_WBNOINVD = 1480,
12932
    X86_INS_WRFSBASE = 1481,
12933
    X86_INS_WRGSBASE = 1482,
12934
    X86_INS_WRMSR = 1483,
12935
    X86_INS_WRPKRU = 1484,
12936
    X86_INS_WRSSD = 1485,
12937
    X86_INS_WRSSQ = 1486,
12938
    X86_INS_WRUSSD = 1487,
12939
    X86_INS_WRUSSQ = 1488,
12940
    X86_INS_XABORT = 1489,
12941
    X86_INS_XACQUIRE = 1490,
12942
    X86_INS_XADD = 1491,
12943
    X86_INS_XBEGIN = 1492,
12944
    X86_INS_XCHG = 1493,
12945
    X86_INS_FXCH = 1494,
12946
    X86_INS_XCRYPTCBC = 1495,
12947
    X86_INS_XCRYPTCFB = 1496,
12948
    X86_INS_XCRYPTCTR = 1497,
12949
    X86_INS_XCRYPTECB = 1498,
12950
    X86_INS_XCRYPTOFB = 1499,
12951
    X86_INS_XEND = 1500,
12952
    X86_INS_XGETBV = 1501,
12953
    X86_INS_XLATB = 1502,
12954
    X86_INS_XOR = 1503,
12955
    X86_INS_XORPD = 1504,
12956
    X86_INS_XORPS = 1505,
12957
    X86_INS_XRELEASE = 1506,
12958
    X86_INS_XRSTOR = 1507,
12959
    X86_INS_XRSTOR64 = 1508,
12960
    X86_INS_XRSTORS = 1509,
12961
    X86_INS_XRSTORS64 = 1510,
12962
    X86_INS_XSAVE = 1511,
12963
    X86_INS_XSAVE64 = 1512,
12964
    X86_INS_XSAVEC = 1513,
12965
    X86_INS_XSAVEC64 = 1514,
12966
    X86_INS_XSAVEOPT = 1515,
12967
    X86_INS_XSAVEOPT64 = 1516,
12968
    X86_INS_XSAVES = 1517,
12969
    X86_INS_XSAVES64 = 1518,
12970
    X86_INS_XSETBV = 1519,
12971
    X86_INS_XSHA1 = 1520,
12972
    X86_INS_XSHA256 = 1521,
12973
    X86_INS_XSTORE = 1522,
12974
    X86_INS_XTEST = 1523,
12975
    X86_INS_ENDING = 1524,
12976
}
12977
pub mod x86_insn_group {
12978
    #[doc = " Group of X86 instructions"]
12979
    pub type Type = libc::c_uint;
12980
    #[doc = "< = CS_GRP_INVALID"]
12981
    pub const X86_GRP_INVALID: Type = 0;
12982
    #[doc = "< = CS_GRP_JUMP"]
12983
    pub const X86_GRP_JUMP: Type = 1;
12984
    #[doc = "< = CS_GRP_CALL"]
12985
    pub const X86_GRP_CALL: Type = 2;
12986
    #[doc = "< = CS_GRP_RET"]
12987
    pub const X86_GRP_RET: Type = 3;
12988
    #[doc = "< = CS_GRP_INT"]
12989
    pub const X86_GRP_INT: Type = 4;
12990
    #[doc = "< = CS_GRP_IRET"]
12991
    pub const X86_GRP_IRET: Type = 5;
12992
    #[doc = "< = CS_GRP_PRIVILEGE"]
12993
    pub const X86_GRP_PRIVILEGE: Type = 6;
12994
    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
12995
    pub const X86_GRP_BRANCH_RELATIVE: Type = 7;
12996
    #[doc = "< all virtualization instructions (VT-x + AMD-V)"]
12997
    pub const X86_GRP_VM: Type = 128;
12998
    pub const X86_GRP_3DNOW: Type = 129;
12999
    pub const X86_GRP_AES: Type = 130;
13000
    pub const X86_GRP_ADX: Type = 131;
13001
    pub const X86_GRP_AVX: Type = 132;
13002
    pub const X86_GRP_AVX2: Type = 133;
13003
    pub const X86_GRP_AVX512: Type = 134;
13004
    pub const X86_GRP_BMI: Type = 135;
13005
    pub const X86_GRP_BMI2: Type = 136;
13006
    pub const X86_GRP_CMOV: Type = 137;
13007
    pub const X86_GRP_F16C: Type = 138;
13008
    pub const X86_GRP_FMA: Type = 139;
13009
    pub const X86_GRP_FMA4: Type = 140;
13010
    pub const X86_GRP_FSGSBASE: Type = 141;
13011
    pub const X86_GRP_HLE: Type = 142;
13012
    pub const X86_GRP_MMX: Type = 143;
13013
    pub const X86_GRP_MODE32: Type = 144;
13014
    pub const X86_GRP_MODE64: Type = 145;
13015
    pub const X86_GRP_RTM: Type = 146;
13016
    pub const X86_GRP_SHA: Type = 147;
13017
    pub const X86_GRP_SSE1: Type = 148;
13018
    pub const X86_GRP_SSE2: Type = 149;
13019
    pub const X86_GRP_SSE3: Type = 150;
13020
    pub const X86_GRP_SSE41: Type = 151;
13021
    pub const X86_GRP_SSE42: Type = 152;
13022
    pub const X86_GRP_SSE4A: Type = 153;
13023
    pub const X86_GRP_SSSE3: Type = 154;
13024
    pub const X86_GRP_PCLMUL: Type = 155;
13025
    pub const X86_GRP_XOP: Type = 156;
13026
    pub const X86_GRP_CDI: Type = 157;
13027
    pub const X86_GRP_ERI: Type = 158;
13028
    pub const X86_GRP_TBM: Type = 159;
13029
    pub const X86_GRP_16BITMODE: Type = 160;
13030
    pub const X86_GRP_NOT64BITMODE: Type = 161;
13031
    pub const X86_GRP_SGX: Type = 162;
13032
    pub const X86_GRP_DQI: Type = 163;
13033
    pub const X86_GRP_BWI: Type = 164;
13034
    pub const X86_GRP_PFI: Type = 165;
13035
    pub const X86_GRP_VLX: Type = 166;
13036
    pub const X86_GRP_SMAP: Type = 167;
13037
    pub const X86_GRP_NOVLX: Type = 168;
13038
    pub const X86_GRP_FPU: Type = 169;
13039
    pub const X86_GRP_ENDING: Type = 170;
13040
}
13041
#[repr(u32)]
13042
#[doc = " Operand type for instruction's operands"]
13043
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13044
pub enum xcore_op_type {
13045
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
13046
    XCORE_OP_INVALID = 0,
13047
    #[doc = "< = CS_OP_REG (Register operand)."]
13048
    XCORE_OP_REG = 1,
13049
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
13050
    XCORE_OP_IMM = 2,
13051
    #[doc = "< = CS_OP_MEM (Memory operand)."]
13052
    XCORE_OP_MEM = 3,
13053
}
13054
pub mod xcore_reg {
13055
    #[doc = " XCore registers"]
13056
    pub type Type = libc::c_uint;
13057
    pub const XCORE_REG_INVALID: Type = 0;
13058
    pub const XCORE_REG_CP: Type = 1;
13059
    pub const XCORE_REG_DP: Type = 2;
13060
    pub const XCORE_REG_LR: Type = 3;
13061
    pub const XCORE_REG_SP: Type = 4;
13062
    pub const XCORE_REG_R0: Type = 5;
13063
    pub const XCORE_REG_R1: Type = 6;
13064
    pub const XCORE_REG_R2: Type = 7;
13065
    pub const XCORE_REG_R3: Type = 8;
13066
    pub const XCORE_REG_R4: Type = 9;
13067
    pub const XCORE_REG_R5: Type = 10;
13068
    pub const XCORE_REG_R6: Type = 11;
13069
    pub const XCORE_REG_R7: Type = 12;
13070
    pub const XCORE_REG_R8: Type = 13;
13071
    pub const XCORE_REG_R9: Type = 14;
13072
    pub const XCORE_REG_R10: Type = 15;
13073
    pub const XCORE_REG_R11: Type = 16;
13074
    #[doc = "< pc"]
13075
    pub const XCORE_REG_PC: Type = 17;
13076
    #[doc = "< save pc"]
13077
    pub const XCORE_REG_SCP: Type = 18;
13078
    pub const XCORE_REG_SSR: Type = 19;
13079
    pub const XCORE_REG_ET: Type = 20;
13080
    pub const XCORE_REG_ED: Type = 21;
13081
    pub const XCORE_REG_SED: Type = 22;
13082
    pub const XCORE_REG_KEP: Type = 23;
13083
    pub const XCORE_REG_KSP: Type = 24;
13084
    pub const XCORE_REG_ID: Type = 25;
13085
    pub const XCORE_REG_ENDING: Type = 26;
13086
}
13087
#[doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"]
13088
#[repr(C)]
13089
#[derive(Debug, Copy, Clone)]
13090
pub struct xcore_op_mem {
13091
    #[doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"]
13092
    pub base: u8,
13093
    #[doc = "< index register, same conditions apply here"]
13094
    pub index: u8,
13095
    #[doc = "< displacement/offset value"]
13096
    pub disp: i32,
13097
    #[doc = "< +1: forward, -1: backward"]
13098
    pub direct: libc::c_int,
13099
}
13100
#[doc = " Instruction operand"]
13101
#[repr(C)]
13102
#[derive(Copy, Clone)]
13103
pub struct cs_xcore_op {
13104
    #[doc = "< operand type"]
13105
    pub type_: xcore_op_type,
13106
    pub __bindgen_anon_1: cs_xcore_op__bindgen_ty_1,
13107
}
13108
#[repr(C)]
13109
#[derive(Copy, Clone)]
13110
pub union cs_xcore_op__bindgen_ty_1 {
13111
    #[doc = "< register value for REG operand"]
13112
    pub reg: xcore_reg::Type,
13113
    #[doc = "< immediate value for IMM operand"]
13114
    pub imm: i32,
13115
    #[doc = "< base/disp value for MEM operand"]
13116
    pub mem: xcore_op_mem,
13117
}
13118
impl ::core::fmt::Debug for cs_xcore_op__bindgen_ty_1 {
13119
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13120
0
        write!(f, "cs_xcore_op__bindgen_ty_1 {{ union }}")
13121
0
    }
13122
}
13123
impl ::core::fmt::Debug for cs_xcore_op {
13124
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13125
0
        write!(
13126
0
            f,
13127
0
            "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
13128
            self.type_, self.__bindgen_anon_1
13129
        )
13130
0
    }
13131
}
13132
#[doc = " Instruction structure"]
13133
#[repr(C)]
13134
#[derive(Copy, Clone)]
13135
pub struct cs_xcore {
13136
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
13137
    pub op_count: u8,
13138
    #[doc = "< operands for this instruction."]
13139
    pub operands: [cs_xcore_op; 8usize],
13140
}
13141
impl ::core::fmt::Debug for cs_xcore {
13142
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13143
0
        write!(f, "cs_xcore {{ operands: {:?} }}", self.operands)
13144
0
    }
13145
}
13146
#[repr(u32)]
13147
#[doc = " XCore instruction"]
13148
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13149
pub enum xcore_insn {
13150
    XCORE_INS_INVALID = 0,
13151
    XCORE_INS_ADD = 1,
13152
    XCORE_INS_ANDNOT = 2,
13153
    XCORE_INS_AND = 3,
13154
    XCORE_INS_ASHR = 4,
13155
    XCORE_INS_BAU = 5,
13156
    XCORE_INS_BITREV = 6,
13157
    XCORE_INS_BLA = 7,
13158
    XCORE_INS_BLAT = 8,
13159
    XCORE_INS_BL = 9,
13160
    XCORE_INS_BF = 10,
13161
    XCORE_INS_BT = 11,
13162
    XCORE_INS_BU = 12,
13163
    XCORE_INS_BRU = 13,
13164
    XCORE_INS_BYTEREV = 14,
13165
    XCORE_INS_CHKCT = 15,
13166
    XCORE_INS_CLRE = 16,
13167
    XCORE_INS_CLRPT = 17,
13168
    XCORE_INS_CLRSR = 18,
13169
    XCORE_INS_CLZ = 19,
13170
    XCORE_INS_CRC8 = 20,
13171
    XCORE_INS_CRC32 = 21,
13172
    XCORE_INS_DCALL = 22,
13173
    XCORE_INS_DENTSP = 23,
13174
    XCORE_INS_DGETREG = 24,
13175
    XCORE_INS_DIVS = 25,
13176
    XCORE_INS_DIVU = 26,
13177
    XCORE_INS_DRESTSP = 27,
13178
    XCORE_INS_DRET = 28,
13179
    XCORE_INS_ECALLF = 29,
13180
    XCORE_INS_ECALLT = 30,
13181
    XCORE_INS_EDU = 31,
13182
    XCORE_INS_EEF = 32,
13183
    XCORE_INS_EET = 33,
13184
    XCORE_INS_EEU = 34,
13185
    XCORE_INS_ENDIN = 35,
13186
    XCORE_INS_ENTSP = 36,
13187
    XCORE_INS_EQ = 37,
13188
    XCORE_INS_EXTDP = 38,
13189
    XCORE_INS_EXTSP = 39,
13190
    XCORE_INS_FREER = 40,
13191
    XCORE_INS_FREET = 41,
13192
    XCORE_INS_GETD = 42,
13193
    XCORE_INS_GET = 43,
13194
    XCORE_INS_GETN = 44,
13195
    XCORE_INS_GETR = 45,
13196
    XCORE_INS_GETSR = 46,
13197
    XCORE_INS_GETST = 47,
13198
    XCORE_INS_GETTS = 48,
13199
    XCORE_INS_INCT = 49,
13200
    XCORE_INS_INIT = 50,
13201
    XCORE_INS_INPW = 51,
13202
    XCORE_INS_INSHR = 52,
13203
    XCORE_INS_INT = 53,
13204
    XCORE_INS_IN = 54,
13205
    XCORE_INS_KCALL = 55,
13206
    XCORE_INS_KENTSP = 56,
13207
    XCORE_INS_KRESTSP = 57,
13208
    XCORE_INS_KRET = 58,
13209
    XCORE_INS_LADD = 59,
13210
    XCORE_INS_LD16S = 60,
13211
    XCORE_INS_LD8U = 61,
13212
    XCORE_INS_LDA16 = 62,
13213
    XCORE_INS_LDAP = 63,
13214
    XCORE_INS_LDAW = 64,
13215
    XCORE_INS_LDC = 65,
13216
    XCORE_INS_LDW = 66,
13217
    XCORE_INS_LDIVU = 67,
13218
    XCORE_INS_LMUL = 68,
13219
    XCORE_INS_LSS = 69,
13220
    XCORE_INS_LSUB = 70,
13221
    XCORE_INS_LSU = 71,
13222
    XCORE_INS_MACCS = 72,
13223
    XCORE_INS_MACCU = 73,
13224
    XCORE_INS_MJOIN = 74,
13225
    XCORE_INS_MKMSK = 75,
13226
    XCORE_INS_MSYNC = 76,
13227
    XCORE_INS_MUL = 77,
13228
    XCORE_INS_NEG = 78,
13229
    XCORE_INS_NOT = 79,
13230
    XCORE_INS_OR = 80,
13231
    XCORE_INS_OUTCT = 81,
13232
    XCORE_INS_OUTPW = 82,
13233
    XCORE_INS_OUTSHR = 83,
13234
    XCORE_INS_OUTT = 84,
13235
    XCORE_INS_OUT = 85,
13236
    XCORE_INS_PEEK = 86,
13237
    XCORE_INS_REMS = 87,
13238
    XCORE_INS_REMU = 88,
13239
    XCORE_INS_RETSP = 89,
13240
    XCORE_INS_SETCLK = 90,
13241
    XCORE_INS_SET = 91,
13242
    XCORE_INS_SETC = 92,
13243
    XCORE_INS_SETD = 93,
13244
    XCORE_INS_SETEV = 94,
13245
    XCORE_INS_SETN = 95,
13246
    XCORE_INS_SETPSC = 96,
13247
    XCORE_INS_SETPT = 97,
13248
    XCORE_INS_SETRDY = 98,
13249
    XCORE_INS_SETSR = 99,
13250
    XCORE_INS_SETTW = 100,
13251
    XCORE_INS_SETV = 101,
13252
    XCORE_INS_SEXT = 102,
13253
    XCORE_INS_SHL = 103,
13254
    XCORE_INS_SHR = 104,
13255
    XCORE_INS_SSYNC = 105,
13256
    XCORE_INS_ST16 = 106,
13257
    XCORE_INS_ST8 = 107,
13258
    XCORE_INS_STW = 108,
13259
    XCORE_INS_SUB = 109,
13260
    XCORE_INS_SYNCR = 110,
13261
    XCORE_INS_TESTCT = 111,
13262
    XCORE_INS_TESTLCL = 112,
13263
    XCORE_INS_TESTWCT = 113,
13264
    XCORE_INS_TSETMR = 114,
13265
    XCORE_INS_START = 115,
13266
    XCORE_INS_WAITEF = 116,
13267
    XCORE_INS_WAITET = 117,
13268
    XCORE_INS_WAITEU = 118,
13269
    XCORE_INS_XOR = 119,
13270
    XCORE_INS_ZEXT = 120,
13271
    XCORE_INS_ENDING = 121,
13272
}
13273
pub mod xcore_insn_group {
13274
    #[doc = " Group of XCore instructions"]
13275
    pub type Type = libc::c_uint;
13276
    #[doc = "< = CS_GRP_INVALID"]
13277
    pub const XCORE_GRP_INVALID: Type = 0;
13278
    #[doc = "< = CS_GRP_JUMP"]
13279
    pub const XCORE_GRP_JUMP: Type = 1;
13280
    pub const XCORE_GRP_ENDING: Type = 2;
13281
}
13282
#[repr(u32)]
13283
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13284
pub enum tms320c64x_op_type {
13285
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
13286
    TMS320C64X_OP_INVALID = 0,
13287
    #[doc = "< = CS_OP_REG (Register operand)."]
13288
    TMS320C64X_OP_REG = 1,
13289
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
13290
    TMS320C64X_OP_IMM = 2,
13291
    #[doc = "< = CS_OP_MEM (Memory operand)."]
13292
    TMS320C64X_OP_MEM = 3,
13293
    #[doc = "< Register pair for double word ops"]
13294
    TMS320C64X_OP_REGPAIR = 64,
13295
}
13296
#[repr(u32)]
13297
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13298
pub enum tms320c64x_mem_disp {
13299
    TMS320C64X_MEM_DISP_INVALID = 0,
13300
    TMS320C64X_MEM_DISP_CONSTANT = 1,
13301
    TMS320C64X_MEM_DISP_REGISTER = 2,
13302
}
13303
#[repr(u32)]
13304
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13305
pub enum tms320c64x_mem_dir {
13306
    TMS320C64X_MEM_DIR_INVALID = 0,
13307
    TMS320C64X_MEM_DIR_FW = 1,
13308
    TMS320C64X_MEM_DIR_BW = 2,
13309
}
13310
#[repr(u32)]
13311
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13312
pub enum tms320c64x_mem_mod {
13313
    TMS320C64X_MEM_MOD_INVALID = 0,
13314
    TMS320C64X_MEM_MOD_NO = 1,
13315
    TMS320C64X_MEM_MOD_PRE = 2,
13316
    TMS320C64X_MEM_MOD_POST = 3,
13317
}
13318
#[repr(C)]
13319
#[derive(Debug, Copy, Clone)]
13320
pub struct tms320c64x_op_mem {
13321
    #[doc = "< base register"]
13322
    pub base: libc::c_uint,
13323
    #[doc = "< displacement/offset value"]
13324
    pub disp: libc::c_uint,
13325
    #[doc = "< unit of base and offset register"]
13326
    pub unit: libc::c_uint,
13327
    #[doc = "< offset scaled"]
13328
    pub scaled: libc::c_uint,
13329
    #[doc = "< displacement type"]
13330
    pub disptype: libc::c_uint,
13331
    #[doc = "< direction"]
13332
    pub direction: libc::c_uint,
13333
    #[doc = "< modification"]
13334
    pub modify: libc::c_uint,
13335
}
13336
#[repr(C)]
13337
#[derive(Copy, Clone)]
13338
pub struct cs_tms320c64x_op {
13339
    #[doc = "< operand type"]
13340
    pub type_: tms320c64x_op_type,
13341
    pub __bindgen_anon_1: cs_tms320c64x_op__bindgen_ty_1,
13342
}
13343
#[repr(C)]
13344
#[derive(Copy, Clone)]
13345
pub union cs_tms320c64x_op__bindgen_ty_1 {
13346
    #[doc = "< register value for REG operand or first register for REGPAIR operand"]
13347
    pub reg: libc::c_uint,
13348
    #[doc = "< immediate value for IMM operand"]
13349
    pub imm: i32,
13350
    #[doc = "< base/disp value for MEM operand"]
13351
    pub mem: tms320c64x_op_mem,
13352
}
13353
impl ::core::fmt::Debug for cs_tms320c64x_op__bindgen_ty_1 {
13354
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13355
0
        write!(f, "cs_tms320c64x_op__bindgen_ty_1 {{ union }}")
13356
0
    }
13357
}
13358
impl ::core::fmt::Debug for cs_tms320c64x_op {
13359
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13360
0
        write!(
13361
0
            f,
13362
0
            "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
13363
            self.type_, self.__bindgen_anon_1
13364
        )
13365
0
    }
13366
}
13367
#[repr(C)]
13368
#[derive(Copy, Clone)]
13369
pub struct cs_tms320c64x {
13370
    pub op_count: u8,
13371
    #[doc = "< operands for this instruction."]
13372
    pub operands: [cs_tms320c64x_op; 8usize],
13373
    pub condition: cs_tms320c64x__bindgen_ty_1,
13374
    pub funit: cs_tms320c64x__bindgen_ty_2,
13375
    pub parallel: libc::c_uint,
13376
}
13377
#[repr(C)]
13378
#[derive(Debug, Copy, Clone)]
13379
pub struct cs_tms320c64x__bindgen_ty_1 {
13380
    pub reg: libc::c_uint,
13381
    pub zero: libc::c_uint,
13382
}
13383
#[repr(C)]
13384
#[derive(Debug, Copy, Clone)]
13385
pub struct cs_tms320c64x__bindgen_ty_2 {
13386
    pub unit: libc::c_uint,
13387
    pub side: libc::c_uint,
13388
    pub crosspath: libc::c_uint,
13389
}
13390
impl ::core::fmt::Debug for cs_tms320c64x {
13391
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13392
0
        write!(
13393
0
            f,
13394
0
            "cs_tms320c64x {{ operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}",
13395
            self.operands, self.condition, self.funit, self.parallel
13396
        )
13397
0
    }
13398
}
13399
pub mod tms320c64x_reg {
13400
    pub type Type = libc::c_uint;
13401
    pub const TMS320C64X_REG_INVALID: Type = 0;
13402
    pub const TMS320C64X_REG_AMR: Type = 1;
13403
    pub const TMS320C64X_REG_CSR: Type = 2;
13404
    pub const TMS320C64X_REG_DIER: Type = 3;
13405
    pub const TMS320C64X_REG_DNUM: Type = 4;
13406
    pub const TMS320C64X_REG_ECR: Type = 5;
13407
    pub const TMS320C64X_REG_GFPGFR: Type = 6;
13408
    pub const TMS320C64X_REG_GPLYA: Type = 7;
13409
    pub const TMS320C64X_REG_GPLYB: Type = 8;
13410
    pub const TMS320C64X_REG_ICR: Type = 9;
13411
    pub const TMS320C64X_REG_IER: Type = 10;
13412
    pub const TMS320C64X_REG_IERR: Type = 11;
13413
    pub const TMS320C64X_REG_ILC: Type = 12;
13414
    pub const TMS320C64X_REG_IRP: Type = 13;
13415
    pub const TMS320C64X_REG_ISR: Type = 14;
13416
    pub const TMS320C64X_REG_ISTP: Type = 15;
13417
    pub const TMS320C64X_REG_ITSR: Type = 16;
13418
    pub const TMS320C64X_REG_NRP: Type = 17;
13419
    pub const TMS320C64X_REG_NTSR: Type = 18;
13420
    pub const TMS320C64X_REG_REP: Type = 19;
13421
    pub const TMS320C64X_REG_RILC: Type = 20;
13422
    pub const TMS320C64X_REG_SSR: Type = 21;
13423
    pub const TMS320C64X_REG_TSCH: Type = 22;
13424
    pub const TMS320C64X_REG_TSCL: Type = 23;
13425
    pub const TMS320C64X_REG_TSR: Type = 24;
13426
    pub const TMS320C64X_REG_A0: Type = 25;
13427
    pub const TMS320C64X_REG_A1: Type = 26;
13428
    pub const TMS320C64X_REG_A2: Type = 27;
13429
    pub const TMS320C64X_REG_A3: Type = 28;
13430
    pub const TMS320C64X_REG_A4: Type = 29;
13431
    pub const TMS320C64X_REG_A5: Type = 30;
13432
    pub const TMS320C64X_REG_A6: Type = 31;
13433
    pub const TMS320C64X_REG_A7: Type = 32;
13434
    pub const TMS320C64X_REG_A8: Type = 33;
13435
    pub const TMS320C64X_REG_A9: Type = 34;
13436
    pub const TMS320C64X_REG_A10: Type = 35;
13437
    pub const TMS320C64X_REG_A11: Type = 36;
13438
    pub const TMS320C64X_REG_A12: Type = 37;
13439
    pub const TMS320C64X_REG_A13: Type = 38;
13440
    pub const TMS320C64X_REG_A14: Type = 39;
13441
    pub const TMS320C64X_REG_A15: Type = 40;
13442
    pub const TMS320C64X_REG_A16: Type = 41;
13443
    pub const TMS320C64X_REG_A17: Type = 42;
13444
    pub const TMS320C64X_REG_A18: Type = 43;
13445
    pub const TMS320C64X_REG_A19: Type = 44;
13446
    pub const TMS320C64X_REG_A20: Type = 45;
13447
    pub const TMS320C64X_REG_A21: Type = 46;
13448
    pub const TMS320C64X_REG_A22: Type = 47;
13449
    pub const TMS320C64X_REG_A23: Type = 48;
13450
    pub const TMS320C64X_REG_A24: Type = 49;
13451
    pub const TMS320C64X_REG_A25: Type = 50;
13452
    pub const TMS320C64X_REG_A26: Type = 51;
13453
    pub const TMS320C64X_REG_A27: Type = 52;
13454
    pub const TMS320C64X_REG_A28: Type = 53;
13455
    pub const TMS320C64X_REG_A29: Type = 54;
13456
    pub const TMS320C64X_REG_A30: Type = 55;
13457
    pub const TMS320C64X_REG_A31: Type = 56;
13458
    pub const TMS320C64X_REG_B0: Type = 57;
13459
    pub const TMS320C64X_REG_B1: Type = 58;
13460
    pub const TMS320C64X_REG_B2: Type = 59;
13461
    pub const TMS320C64X_REG_B3: Type = 60;
13462
    pub const TMS320C64X_REG_B4: Type = 61;
13463
    pub const TMS320C64X_REG_B5: Type = 62;
13464
    pub const TMS320C64X_REG_B6: Type = 63;
13465
    pub const TMS320C64X_REG_B7: Type = 64;
13466
    pub const TMS320C64X_REG_B8: Type = 65;
13467
    pub const TMS320C64X_REG_B9: Type = 66;
13468
    pub const TMS320C64X_REG_B10: Type = 67;
13469
    pub const TMS320C64X_REG_B11: Type = 68;
13470
    pub const TMS320C64X_REG_B12: Type = 69;
13471
    pub const TMS320C64X_REG_B13: Type = 70;
13472
    pub const TMS320C64X_REG_B14: Type = 71;
13473
    pub const TMS320C64X_REG_B15: Type = 72;
13474
    pub const TMS320C64X_REG_B16: Type = 73;
13475
    pub const TMS320C64X_REG_B17: Type = 74;
13476
    pub const TMS320C64X_REG_B18: Type = 75;
13477
    pub const TMS320C64X_REG_B19: Type = 76;
13478
    pub const TMS320C64X_REG_B20: Type = 77;
13479
    pub const TMS320C64X_REG_B21: Type = 78;
13480
    pub const TMS320C64X_REG_B22: Type = 79;
13481
    pub const TMS320C64X_REG_B23: Type = 80;
13482
    pub const TMS320C64X_REG_B24: Type = 81;
13483
    pub const TMS320C64X_REG_B25: Type = 82;
13484
    pub const TMS320C64X_REG_B26: Type = 83;
13485
    pub const TMS320C64X_REG_B27: Type = 84;
13486
    pub const TMS320C64X_REG_B28: Type = 85;
13487
    pub const TMS320C64X_REG_B29: Type = 86;
13488
    pub const TMS320C64X_REG_B30: Type = 87;
13489
    pub const TMS320C64X_REG_B31: Type = 88;
13490
    pub const TMS320C64X_REG_PCE1: Type = 89;
13491
    pub const TMS320C64X_REG_ENDING: Type = 90;
13492
    pub const TMS320C64X_REG_EFR: Type = 5;
13493
    pub const TMS320C64X_REG_IFR: Type = 14;
13494
}
13495
#[repr(u32)]
13496
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13497
pub enum tms320c64x_insn {
13498
    TMS320C64X_INS_INVALID = 0,
13499
    TMS320C64X_INS_ABS = 1,
13500
    TMS320C64X_INS_ABS2 = 2,
13501
    TMS320C64X_INS_ADD = 3,
13502
    TMS320C64X_INS_ADD2 = 4,
13503
    TMS320C64X_INS_ADD4 = 5,
13504
    TMS320C64X_INS_ADDAB = 6,
13505
    TMS320C64X_INS_ADDAD = 7,
13506
    TMS320C64X_INS_ADDAH = 8,
13507
    TMS320C64X_INS_ADDAW = 9,
13508
    TMS320C64X_INS_ADDK = 10,
13509
    TMS320C64X_INS_ADDKPC = 11,
13510
    TMS320C64X_INS_ADDU = 12,
13511
    TMS320C64X_INS_AND = 13,
13512
    TMS320C64X_INS_ANDN = 14,
13513
    TMS320C64X_INS_AVG2 = 15,
13514
    TMS320C64X_INS_AVGU4 = 16,
13515
    TMS320C64X_INS_B = 17,
13516
    TMS320C64X_INS_BDEC = 18,
13517
    TMS320C64X_INS_BITC4 = 19,
13518
    TMS320C64X_INS_BNOP = 20,
13519
    TMS320C64X_INS_BPOS = 21,
13520
    TMS320C64X_INS_CLR = 22,
13521
    TMS320C64X_INS_CMPEQ = 23,
13522
    TMS320C64X_INS_CMPEQ2 = 24,
13523
    TMS320C64X_INS_CMPEQ4 = 25,
13524
    TMS320C64X_INS_CMPGT = 26,
13525
    TMS320C64X_INS_CMPGT2 = 27,
13526
    TMS320C64X_INS_CMPGTU4 = 28,
13527
    TMS320C64X_INS_CMPLT = 29,
13528
    TMS320C64X_INS_CMPLTU = 30,
13529
    TMS320C64X_INS_DEAL = 31,
13530
    TMS320C64X_INS_DOTP2 = 32,
13531
    TMS320C64X_INS_DOTPN2 = 33,
13532
    TMS320C64X_INS_DOTPNRSU2 = 34,
13533
    TMS320C64X_INS_DOTPRSU2 = 35,
13534
    TMS320C64X_INS_DOTPSU4 = 36,
13535
    TMS320C64X_INS_DOTPU4 = 37,
13536
    TMS320C64X_INS_EXT = 38,
13537
    TMS320C64X_INS_EXTU = 39,
13538
    TMS320C64X_INS_GMPGTU = 40,
13539
    TMS320C64X_INS_GMPY4 = 41,
13540
    TMS320C64X_INS_LDB = 42,
13541
    TMS320C64X_INS_LDBU = 43,
13542
    TMS320C64X_INS_LDDW = 44,
13543
    TMS320C64X_INS_LDH = 45,
13544
    TMS320C64X_INS_LDHU = 46,
13545
    TMS320C64X_INS_LDNDW = 47,
13546
    TMS320C64X_INS_LDNW = 48,
13547
    TMS320C64X_INS_LDW = 49,
13548
    TMS320C64X_INS_LMBD = 50,
13549
    TMS320C64X_INS_MAX2 = 51,
13550
    TMS320C64X_INS_MAXU4 = 52,
13551
    TMS320C64X_INS_MIN2 = 53,
13552
    TMS320C64X_INS_MINU4 = 54,
13553
    TMS320C64X_INS_MPY = 55,
13554
    TMS320C64X_INS_MPY2 = 56,
13555
    TMS320C64X_INS_MPYH = 57,
13556
    TMS320C64X_INS_MPYHI = 58,
13557
    TMS320C64X_INS_MPYHIR = 59,
13558
    TMS320C64X_INS_MPYHL = 60,
13559
    TMS320C64X_INS_MPYHLU = 61,
13560
    TMS320C64X_INS_MPYHSLU = 62,
13561
    TMS320C64X_INS_MPYHSU = 63,
13562
    TMS320C64X_INS_MPYHU = 64,
13563
    TMS320C64X_INS_MPYHULS = 65,
13564
    TMS320C64X_INS_MPYHUS = 66,
13565
    TMS320C64X_INS_MPYLH = 67,
13566
    TMS320C64X_INS_MPYLHU = 68,
13567
    TMS320C64X_INS_MPYLI = 69,
13568
    TMS320C64X_INS_MPYLIR = 70,
13569
    TMS320C64X_INS_MPYLSHU = 71,
13570
    TMS320C64X_INS_MPYLUHS = 72,
13571
    TMS320C64X_INS_MPYSU = 73,
13572
    TMS320C64X_INS_MPYSU4 = 74,
13573
    TMS320C64X_INS_MPYU = 75,
13574
    TMS320C64X_INS_MPYU4 = 76,
13575
    TMS320C64X_INS_MPYUS = 77,
13576
    TMS320C64X_INS_MVC = 78,
13577
    TMS320C64X_INS_MVD = 79,
13578
    TMS320C64X_INS_MVK = 80,
13579
    TMS320C64X_INS_MVKL = 81,
13580
    TMS320C64X_INS_MVKLH = 82,
13581
    TMS320C64X_INS_NOP = 83,
13582
    TMS320C64X_INS_NORM = 84,
13583
    TMS320C64X_INS_OR = 85,
13584
    TMS320C64X_INS_PACK2 = 86,
13585
    TMS320C64X_INS_PACKH2 = 87,
13586
    TMS320C64X_INS_PACKH4 = 88,
13587
    TMS320C64X_INS_PACKHL2 = 89,
13588
    TMS320C64X_INS_PACKL4 = 90,
13589
    TMS320C64X_INS_PACKLH2 = 91,
13590
    TMS320C64X_INS_ROTL = 92,
13591
    TMS320C64X_INS_SADD = 93,
13592
    TMS320C64X_INS_SADD2 = 94,
13593
    TMS320C64X_INS_SADDU4 = 95,
13594
    TMS320C64X_INS_SADDUS2 = 96,
13595
    TMS320C64X_INS_SAT = 97,
13596
    TMS320C64X_INS_SET = 98,
13597
    TMS320C64X_INS_SHFL = 99,
13598
    TMS320C64X_INS_SHL = 100,
13599
    TMS320C64X_INS_SHLMB = 101,
13600
    TMS320C64X_INS_SHR = 102,
13601
    TMS320C64X_INS_SHR2 = 103,
13602
    TMS320C64X_INS_SHRMB = 104,
13603
    TMS320C64X_INS_SHRU = 105,
13604
    TMS320C64X_INS_SHRU2 = 106,
13605
    TMS320C64X_INS_SMPY = 107,
13606
    TMS320C64X_INS_SMPY2 = 108,
13607
    TMS320C64X_INS_SMPYH = 109,
13608
    TMS320C64X_INS_SMPYHL = 110,
13609
    TMS320C64X_INS_SMPYLH = 111,
13610
    TMS320C64X_INS_SPACK2 = 112,
13611
    TMS320C64X_INS_SPACKU4 = 113,
13612
    TMS320C64X_INS_SSHL = 114,
13613
    TMS320C64X_INS_SSHVL = 115,
13614
    TMS320C64X_INS_SSHVR = 116,
13615
    TMS320C64X_INS_SSUB = 117,
13616
    TMS320C64X_INS_STB = 118,
13617
    TMS320C64X_INS_STDW = 119,
13618
    TMS320C64X_INS_STH = 120,
13619
    TMS320C64X_INS_STNDW = 121,
13620
    TMS320C64X_INS_STNW = 122,
13621
    TMS320C64X_INS_STW = 123,
13622
    TMS320C64X_INS_SUB = 124,
13623
    TMS320C64X_INS_SUB2 = 125,
13624
    TMS320C64X_INS_SUB4 = 126,
13625
    TMS320C64X_INS_SUBAB = 127,
13626
    TMS320C64X_INS_SUBABS4 = 128,
13627
    TMS320C64X_INS_SUBAH = 129,
13628
    TMS320C64X_INS_SUBAW = 130,
13629
    TMS320C64X_INS_SUBC = 131,
13630
    TMS320C64X_INS_SUBU = 132,
13631
    TMS320C64X_INS_SWAP4 = 133,
13632
    TMS320C64X_INS_UNPKHU4 = 134,
13633
    TMS320C64X_INS_UNPKLU4 = 135,
13634
    TMS320C64X_INS_XOR = 136,
13635
    TMS320C64X_INS_XPND2 = 137,
13636
    TMS320C64X_INS_XPND4 = 138,
13637
    TMS320C64X_INS_IDLE = 139,
13638
    TMS320C64X_INS_MV = 140,
13639
    TMS320C64X_INS_NEG = 141,
13640
    TMS320C64X_INS_NOT = 142,
13641
    TMS320C64X_INS_SWAP2 = 143,
13642
    TMS320C64X_INS_ZERO = 144,
13643
    TMS320C64X_INS_ENDING = 145,
13644
}
13645
pub mod tms320c64x_insn_group {
13646
    pub type Type = libc::c_uint;
13647
    #[doc = "< = CS_GRP_INVALID"]
13648
    pub const TMS320C64X_GRP_INVALID: Type = 0;
13649
    #[doc = "< = CS_GRP_JUMP"]
13650
    pub const TMS320C64X_GRP_JUMP: Type = 1;
13651
    pub const TMS320C64X_GRP_FUNIT_D: Type = 128;
13652
    pub const TMS320C64X_GRP_FUNIT_L: Type = 129;
13653
    pub const TMS320C64X_GRP_FUNIT_M: Type = 130;
13654
    pub const TMS320C64X_GRP_FUNIT_S: Type = 131;
13655
    pub const TMS320C64X_GRP_FUNIT_NO: Type = 132;
13656
    pub const TMS320C64X_GRP_ENDING: Type = 133;
13657
}
13658
#[repr(u32)]
13659
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13660
pub enum tms320c64x_funit {
13661
    TMS320C64X_FUNIT_INVALID = 0,
13662
    TMS320C64X_FUNIT_D = 1,
13663
    TMS320C64X_FUNIT_L = 2,
13664
    TMS320C64X_FUNIT_M = 3,
13665
    TMS320C64X_FUNIT_S = 4,
13666
    TMS320C64X_FUNIT_NO = 5,
13667
}
13668
pub mod m680x_reg {
13669
    #[doc = " M680X registers and special registers"]
13670
    pub type Type = libc::c_uint;
13671
    pub const M680X_REG_INVALID: Type = 0;
13672
    #[doc = "< M6800/1/2/3/9, HD6301/9"]
13673
    pub const M680X_REG_A: Type = 1;
13674
    #[doc = "< M6800/1/2/3/9, HD6301/9"]
13675
    pub const M680X_REG_B: Type = 2;
13676
    #[doc = "< HD6309"]
13677
    pub const M680X_REG_E: Type = 3;
13678
    #[doc = "< HD6309"]
13679
    pub const M680X_REG_F: Type = 4;
13680
    #[doc = "< HD6309"]
13681
    pub const M680X_REG_0: Type = 5;
13682
    #[doc = "< M6801/3/9, HD6301/9"]
13683
    pub const M680X_REG_D: Type = 6;
13684
    #[doc = "< HD6309"]
13685
    pub const M680X_REG_W: Type = 7;
13686
    #[doc = "< M6800/1/2/3/9, M6301/9"]
13687
    pub const M680X_REG_CC: Type = 8;
13688
    #[doc = "< M6809/M6309"]
13689
    pub const M680X_REG_DP: Type = 9;
13690
    #[doc = "< M6309"]
13691
    pub const M680X_REG_MD: Type = 10;
13692
    #[doc = "< M6808"]
13693
    pub const M680X_REG_HX: Type = 11;
13694
    #[doc = "< M6808"]
13695
    pub const M680X_REG_H: Type = 12;
13696
    #[doc = "< M6800/1/2/3/9, M6301/9"]
13697
    pub const M680X_REG_X: Type = 13;
13698
    #[doc = "< M6809/M6309"]
13699
    pub const M680X_REG_Y: Type = 14;
13700
    #[doc = "< M6809/M6309"]
13701
    pub const M680X_REG_S: Type = 15;
13702
    #[doc = "< M6809/M6309"]
13703
    pub const M680X_REG_U: Type = 16;
13704
    #[doc = "< M6309"]
13705
    pub const M680X_REG_V: Type = 17;
13706
    #[doc = "< M6309"]
13707
    pub const M680X_REG_Q: Type = 18;
13708
    #[doc = "< M6800/1/2/3/9, M6301/9"]
13709
    pub const M680X_REG_PC: Type = 19;
13710
    #[doc = "< CPU12"]
13711
    pub const M680X_REG_TMP2: Type = 20;
13712
    #[doc = "< CPU12"]
13713
    pub const M680X_REG_TMP3: Type = 21;
13714
    #[doc = "< <-- mark the end of the list of registers"]
13715
    pub const M680X_REG_ENDING: Type = 22;
13716
}
13717
#[repr(u32)]
13718
#[doc = " Operand type for instruction's operands"]
13719
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13720
pub enum m680x_op_type {
13721
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
13722
    M680X_OP_INVALID = 0,
13723
    #[doc = "< = Register operand."]
13724
    M680X_OP_REGISTER = 1,
13725
    #[doc = "< = Immediate operand."]
13726
    M680X_OP_IMMEDIATE = 2,
13727
    #[doc = "< = Indexed addressing operand."]
13728
    M680X_OP_INDEXED = 3,
13729
    #[doc = "< = Extended addressing operand."]
13730
    M680X_OP_EXTENDED = 4,
13731
    #[doc = "< = Direct addressing operand."]
13732
    M680X_OP_DIRECT = 5,
13733
    #[doc = "< = Relative addressing operand."]
13734
    M680X_OP_RELATIVE = 6,
13735
    #[doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."]
13736
    M680X_OP_CONSTANT = 7,
13737
}
13738
#[doc = " Instruction's operand referring to indexed addressing"]
13739
#[repr(C)]
13740
#[derive(Debug, Copy, Clone)]
13741
pub struct m680x_op_idx {
13742
    #[doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"]
13743
    pub base_reg: m680x_reg::Type,
13744
    #[doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"]
13745
    pub offset_reg: m680x_reg::Type,
13746
    #[doc = "< 5-,8- or 16-bit offset. See also offset_bits."]
13747
    pub offset: i16,
13748
    #[doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"]
13749
    pub offset_addr: u16,
13750
    #[doc = "< offset width in bits for indexed addressing"]
13751
    pub offset_bits: u8,
13752
    #[doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"]
13753
    pub inc_dec: i8,
13754
    #[doc = "< 8-bit flags (see above)"]
13755
    pub flags: u8,
13756
}
13757
#[doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"]
13758
#[repr(C)]
13759
#[derive(Debug, Copy, Clone)]
13760
pub struct m680x_op_rel {
13761
    #[doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."]
13762
    pub address: u16,
13763
    #[doc = "< the offset/displacement value"]
13764
    pub offset: i16,
13765
}
13766
#[doc = " Instruction's operand referring to extended addressing"]
13767
#[repr(C)]
13768
#[derive(Debug, Copy, Clone)]
13769
pub struct m680x_op_ext {
13770
    #[doc = "< The absolute address"]
13771
    pub address: u16,
13772
    #[doc = "< true if extended indirect addressing"]
13773
    pub indirect: bool,
13774
}
13775
#[doc = " Instruction operand"]
13776
#[repr(C)]
13777
#[derive(Copy, Clone)]
13778
pub struct cs_m680x_op {
13779
    pub type_: m680x_op_type,
13780
    pub __bindgen_anon_1: cs_m680x_op__bindgen_ty_1,
13781
    #[doc = "< size of this operand (in bytes)"]
13782
    pub size: u8,
13783
    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"]
13784
    pub access: u8,
13785
}
13786
#[repr(C)]
13787
#[derive(Copy, Clone)]
13788
pub union cs_m680x_op__bindgen_ty_1 {
13789
    #[doc = "< immediate value for IMM operand"]
13790
    pub imm: i32,
13791
    #[doc = "< register value for REG operand"]
13792
    pub reg: m680x_reg::Type,
13793
    #[doc = "< Indexed addressing operand"]
13794
    pub idx: m680x_op_idx,
13795
    #[doc = "< Relative address. operand (Bcc/LBcc)"]
13796
    pub rel: m680x_op_rel,
13797
    #[doc = "< Extended address"]
13798
    pub ext: m680x_op_ext,
13799
    #[doc = "<</ Direct address (lower 8-bit)"]
13800
    pub direct_addr: u8,
13801
    #[doc = "< constant value (bit index, page nr.)"]
13802
    pub const_val: u8,
13803
}
13804
impl ::core::fmt::Debug for cs_m680x_op__bindgen_ty_1 {
13805
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13806
0
        write!(f, "cs_m680x_op__bindgen_ty_1 {{ union }}")
13807
0
    }
13808
}
13809
impl ::core::fmt::Debug for cs_m680x_op {
13810
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13811
0
        write!(
13812
0
            f,
13813
0
            "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
13814
            self.type_, self.__bindgen_anon_1
13815
        )
13816
0
    }
13817
}
13818
#[repr(u32)]
13819
#[doc = " Group of M680X instructions"]
13820
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13821
pub enum m680x_group_type {
13822
    M680X_GRP_INVALID = 0,
13823
    #[doc = "< = CS_GRP_JUMP"]
13824
    M680X_GRP_JUMP = 1,
13825
    #[doc = "< = CS_GRP_CALL"]
13826
    M680X_GRP_CALL = 2,
13827
    #[doc = "< = CS_GRP_RET"]
13828
    M680X_GRP_RET = 3,
13829
    #[doc = "< = CS_GRP_INT"]
13830
    M680X_GRP_INT = 4,
13831
    #[doc = "< = CS_GRP_IRET"]
13832
    M680X_GRP_IRET = 5,
13833
    #[doc = "< = CS_GRP_PRIVILEDGE; not used"]
13834
    M680X_GRP_PRIV = 6,
13835
    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
13836
    M680X_GRP_BRAREL = 7,
13837
    M680X_GRP_ENDING = 8,
13838
}
13839
#[doc = " The M680X instruction and it's operands"]
13840
#[repr(C)]
13841
#[derive(Copy, Clone)]
13842
pub struct cs_m680x {
13843
    #[doc = "< See: M680X instruction flags"]
13844
    pub flags: u8,
13845
    #[doc = "< number of operands for the instruction or 0"]
13846
    pub op_count: u8,
13847
    #[doc = "< operands for this insn."]
13848
    pub operands: [cs_m680x_op; 9usize],
13849
}
13850
impl ::core::fmt::Debug for cs_m680x {
13851
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
13852
0
        write!(f, "cs_m680x {{ operands: {:?} }}", self.operands)
13853
0
    }
13854
}
13855
#[repr(u32)]
13856
#[doc = " M680X instruction IDs"]
13857
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13858
pub enum m680x_insn {
13859
    M680X_INS_INVLD = 0,
13860
    #[doc = "< M6800/1/2/3"]
13861
    M680X_INS_ABA = 1,
13862
    M680X_INS_ABX = 2,
13863
    M680X_INS_ABY = 3,
13864
    M680X_INS_ADC = 4,
13865
    M680X_INS_ADCA = 5,
13866
    M680X_INS_ADCB = 6,
13867
    M680X_INS_ADCD = 7,
13868
    M680X_INS_ADCR = 8,
13869
    M680X_INS_ADD = 9,
13870
    M680X_INS_ADDA = 10,
13871
    M680X_INS_ADDB = 11,
13872
    M680X_INS_ADDD = 12,
13873
    M680X_INS_ADDE = 13,
13874
    M680X_INS_ADDF = 14,
13875
    M680X_INS_ADDR = 15,
13876
    M680X_INS_ADDW = 16,
13877
    M680X_INS_AIM = 17,
13878
    M680X_INS_AIS = 18,
13879
    M680X_INS_AIX = 19,
13880
    M680X_INS_AND = 20,
13881
    M680X_INS_ANDA = 21,
13882
    M680X_INS_ANDB = 22,
13883
    M680X_INS_ANDCC = 23,
13884
    M680X_INS_ANDD = 24,
13885
    M680X_INS_ANDR = 25,
13886
    M680X_INS_ASL = 26,
13887
    M680X_INS_ASLA = 27,
13888
    M680X_INS_ASLB = 28,
13889
    #[doc = "< or LSLD"]
13890
    M680X_INS_ASLD = 29,
13891
    M680X_INS_ASR = 30,
13892
    M680X_INS_ASRA = 31,
13893
    M680X_INS_ASRB = 32,
13894
    M680X_INS_ASRD = 33,
13895
    M680X_INS_ASRX = 34,
13896
    M680X_INS_BAND = 35,
13897
    #[doc = "< or BHS"]
13898
    M680X_INS_BCC = 36,
13899
    M680X_INS_BCLR = 37,
13900
    #[doc = "< or BLO"]
13901
    M680X_INS_BCS = 38,
13902
    M680X_INS_BEOR = 39,
13903
    M680X_INS_BEQ = 40,
13904
    M680X_INS_BGE = 41,
13905
    M680X_INS_BGND = 42,
13906
    M680X_INS_BGT = 43,
13907
    M680X_INS_BHCC = 44,
13908
    M680X_INS_BHCS = 45,
13909
    M680X_INS_BHI = 46,
13910
    M680X_INS_BIAND = 47,
13911
    M680X_INS_BIEOR = 48,
13912
    M680X_INS_BIH = 49,
13913
    M680X_INS_BIL = 50,
13914
    M680X_INS_BIOR = 51,
13915
    M680X_INS_BIT = 52,
13916
    M680X_INS_BITA = 53,
13917
    M680X_INS_BITB = 54,
13918
    M680X_INS_BITD = 55,
13919
    M680X_INS_BITMD = 56,
13920
    M680X_INS_BLE = 57,
13921
    M680X_INS_BLS = 58,
13922
    M680X_INS_BLT = 59,
13923
    M680X_INS_BMC = 60,
13924
    M680X_INS_BMI = 61,
13925
    M680X_INS_BMS = 62,
13926
    M680X_INS_BNE = 63,
13927
    M680X_INS_BOR = 64,
13928
    M680X_INS_BPL = 65,
13929
    M680X_INS_BRCLR = 66,
13930
    M680X_INS_BRSET = 67,
13931
    M680X_INS_BRA = 68,
13932
    M680X_INS_BRN = 69,
13933
    M680X_INS_BSET = 70,
13934
    M680X_INS_BSR = 71,
13935
    M680X_INS_BVC = 72,
13936
    M680X_INS_BVS = 73,
13937
    M680X_INS_CALL = 74,
13938
    #[doc = "< M6800/1/2/3"]
13939
    M680X_INS_CBA = 75,
13940
    M680X_INS_CBEQ = 76,
13941
    M680X_INS_CBEQA = 77,
13942
    M680X_INS_CBEQX = 78,
13943
    #[doc = "< M6800/1/2/3"]
13944
    M680X_INS_CLC = 79,
13945
    #[doc = "< M6800/1/2/3"]
13946
    M680X_INS_CLI = 80,
13947
    M680X_INS_CLR = 81,
13948
    M680X_INS_CLRA = 82,
13949
    M680X_INS_CLRB = 83,
13950
    M680X_INS_CLRD = 84,
13951
    M680X_INS_CLRE = 85,
13952
    M680X_INS_CLRF = 86,
13953
    M680X_INS_CLRH = 87,
13954
    M680X_INS_CLRW = 88,
13955
    M680X_INS_CLRX = 89,
13956
    #[doc = "< M6800/1/2/3"]
13957
    M680X_INS_CLV = 90,
13958
    M680X_INS_CMP = 91,
13959
    M680X_INS_CMPA = 92,
13960
    M680X_INS_CMPB = 93,
13961
    M680X_INS_CMPD = 94,
13962
    M680X_INS_CMPE = 95,
13963
    M680X_INS_CMPF = 96,
13964
    M680X_INS_CMPR = 97,
13965
    M680X_INS_CMPS = 98,
13966
    M680X_INS_CMPU = 99,
13967
    M680X_INS_CMPW = 100,
13968
    M680X_INS_CMPX = 101,
13969
    M680X_INS_CMPY = 102,
13970
    M680X_INS_COM = 103,
13971
    M680X_INS_COMA = 104,
13972
    M680X_INS_COMB = 105,
13973
    M680X_INS_COMD = 106,
13974
    M680X_INS_COME = 107,
13975
    M680X_INS_COMF = 108,
13976
    M680X_INS_COMW = 109,
13977
    M680X_INS_COMX = 110,
13978
    M680X_INS_CPD = 111,
13979
    M680X_INS_CPHX = 112,
13980
    M680X_INS_CPS = 113,
13981
    #[doc = "< M6800/1/2/3"]
13982
    M680X_INS_CPX = 114,
13983
    M680X_INS_CPY = 115,
13984
    M680X_INS_CWAI = 116,
13985
    M680X_INS_DAA = 117,
13986
    M680X_INS_DBEQ = 118,
13987
    M680X_INS_DBNE = 119,
13988
    M680X_INS_DBNZ = 120,
13989
    M680X_INS_DBNZA = 121,
13990
    M680X_INS_DBNZX = 122,
13991
    M680X_INS_DEC = 123,
13992
    M680X_INS_DECA = 124,
13993
    M680X_INS_DECB = 125,
13994
    M680X_INS_DECD = 126,
13995
    M680X_INS_DECE = 127,
13996
    M680X_INS_DECF = 128,
13997
    M680X_INS_DECW = 129,
13998
    M680X_INS_DECX = 130,
13999
    #[doc = "< M6800/1/2/3"]
14000
    M680X_INS_DES = 131,
14001
    #[doc = "< M6800/1/2/3"]
14002
    M680X_INS_DEX = 132,
14003
    M680X_INS_DEY = 133,
14004
    M680X_INS_DIV = 134,
14005
    M680X_INS_DIVD = 135,
14006
    M680X_INS_DIVQ = 136,
14007
    M680X_INS_EDIV = 137,
14008
    M680X_INS_EDIVS = 138,
14009
    M680X_INS_EIM = 139,
14010
    M680X_INS_EMACS = 140,
14011
    M680X_INS_EMAXD = 141,
14012
    M680X_INS_EMAXM = 142,
14013
    M680X_INS_EMIND = 143,
14014
    M680X_INS_EMINM = 144,
14015
    M680X_INS_EMUL = 145,
14016
    M680X_INS_EMULS = 146,
14017
    M680X_INS_EOR = 147,
14018
    M680X_INS_EORA = 148,
14019
    M680X_INS_EORB = 149,
14020
    M680X_INS_EORD = 150,
14021
    M680X_INS_EORR = 151,
14022
    M680X_INS_ETBL = 152,
14023
    M680X_INS_EXG = 153,
14024
    M680X_INS_FDIV = 154,
14025
    M680X_INS_IBEQ = 155,
14026
    M680X_INS_IBNE = 156,
14027
    M680X_INS_IDIV = 157,
14028
    M680X_INS_IDIVS = 158,
14029
    M680X_INS_ILLGL = 159,
14030
    M680X_INS_INC = 160,
14031
    M680X_INS_INCA = 161,
14032
    M680X_INS_INCB = 162,
14033
    M680X_INS_INCD = 163,
14034
    M680X_INS_INCE = 164,
14035
    M680X_INS_INCF = 165,
14036
    M680X_INS_INCW = 166,
14037
    M680X_INS_INCX = 167,
14038
    #[doc = "< M6800/1/2/3"]
14039
    M680X_INS_INS = 168,
14040
    #[doc = "< M6800/1/2/3"]
14041
    M680X_INS_INX = 169,
14042
    M680X_INS_INY = 170,
14043
    M680X_INS_JMP = 171,
14044
    M680X_INS_JSR = 172,
14045
    #[doc = "< or LBHS"]
14046
    M680X_INS_LBCC = 173,
14047
    #[doc = "< or LBLO"]
14048
    M680X_INS_LBCS = 174,
14049
    M680X_INS_LBEQ = 175,
14050
    M680X_INS_LBGE = 176,
14051
    M680X_INS_LBGT = 177,
14052
    M680X_INS_LBHI = 178,
14053
    M680X_INS_LBLE = 179,
14054
    M680X_INS_LBLS = 180,
14055
    M680X_INS_LBLT = 181,
14056
    M680X_INS_LBMI = 182,
14057
    M680X_INS_LBNE = 183,
14058
    M680X_INS_LBPL = 184,
14059
    M680X_INS_LBRA = 185,
14060
    M680X_INS_LBRN = 186,
14061
    M680X_INS_LBSR = 187,
14062
    M680X_INS_LBVC = 188,
14063
    M680X_INS_LBVS = 189,
14064
    M680X_INS_LDA = 190,
14065
    #[doc = "< M6800/1/2/3"]
14066
    M680X_INS_LDAA = 191,
14067
    #[doc = "< M6800/1/2/3"]
14068
    M680X_INS_LDAB = 192,
14069
    M680X_INS_LDB = 193,
14070
    M680X_INS_LDBT = 194,
14071
    M680X_INS_LDD = 195,
14072
    M680X_INS_LDE = 196,
14073
    M680X_INS_LDF = 197,
14074
    M680X_INS_LDHX = 198,
14075
    M680X_INS_LDMD = 199,
14076
    M680X_INS_LDQ = 200,
14077
    M680X_INS_LDS = 201,
14078
    M680X_INS_LDU = 202,
14079
    M680X_INS_LDW = 203,
14080
    M680X_INS_LDX = 204,
14081
    M680X_INS_LDY = 205,
14082
    M680X_INS_LEAS = 206,
14083
    M680X_INS_LEAU = 207,
14084
    M680X_INS_LEAX = 208,
14085
    M680X_INS_LEAY = 209,
14086
    M680X_INS_LSL = 210,
14087
    M680X_INS_LSLA = 211,
14088
    M680X_INS_LSLB = 212,
14089
    M680X_INS_LSLD = 213,
14090
    M680X_INS_LSLX = 214,
14091
    M680X_INS_LSR = 215,
14092
    M680X_INS_LSRA = 216,
14093
    M680X_INS_LSRB = 217,
14094
    #[doc = "< or ASRD"]
14095
    M680X_INS_LSRD = 218,
14096
    M680X_INS_LSRW = 219,
14097
    M680X_INS_LSRX = 220,
14098
    M680X_INS_MAXA = 221,
14099
    M680X_INS_MAXM = 222,
14100
    M680X_INS_MEM = 223,
14101
    M680X_INS_MINA = 224,
14102
    M680X_INS_MINM = 225,
14103
    M680X_INS_MOV = 226,
14104
    M680X_INS_MOVB = 227,
14105
    M680X_INS_MOVW = 228,
14106
    M680X_INS_MUL = 229,
14107
    M680X_INS_MULD = 230,
14108
    M680X_INS_NEG = 231,
14109
    M680X_INS_NEGA = 232,
14110
    M680X_INS_NEGB = 233,
14111
    M680X_INS_NEGD = 234,
14112
    M680X_INS_NEGX = 235,
14113
    M680X_INS_NOP = 236,
14114
    M680X_INS_NSA = 237,
14115
    M680X_INS_OIM = 238,
14116
    M680X_INS_ORA = 239,
14117
    #[doc = "< M6800/1/2/3"]
14118
    M680X_INS_ORAA = 240,
14119
    #[doc = "< M6800/1/2/3"]
14120
    M680X_INS_ORAB = 241,
14121
    M680X_INS_ORB = 242,
14122
    M680X_INS_ORCC = 243,
14123
    M680X_INS_ORD = 244,
14124
    M680X_INS_ORR = 245,
14125
    #[doc = "< M6800/1/2/3"]
14126
    M680X_INS_PSHA = 246,
14127
    #[doc = "< M6800/1/2/3"]
14128
    M680X_INS_PSHB = 247,
14129
    M680X_INS_PSHC = 248,
14130
    M680X_INS_PSHD = 249,
14131
    M680X_INS_PSHH = 250,
14132
    M680X_INS_PSHS = 251,
14133
    M680X_INS_PSHSW = 252,
14134
    M680X_INS_PSHU = 253,
14135
    M680X_INS_PSHUW = 254,
14136
    #[doc = "< M6800/1/2/3"]
14137
    M680X_INS_PSHX = 255,
14138
    M680X_INS_PSHY = 256,
14139
    #[doc = "< M6800/1/2/3"]
14140
    M680X_INS_PULA = 257,
14141
    #[doc = "< M6800/1/2/3"]
14142
    M680X_INS_PULB = 258,
14143
    M680X_INS_PULC = 259,
14144
    M680X_INS_PULD = 260,
14145
    M680X_INS_PULH = 261,
14146
    M680X_INS_PULS = 262,
14147
    M680X_INS_PULSW = 263,
14148
    M680X_INS_PULU = 264,
14149
    M680X_INS_PULUW = 265,
14150
    #[doc = "< M6800/1/2/3"]
14151
    M680X_INS_PULX = 266,
14152
    M680X_INS_PULY = 267,
14153
    M680X_INS_REV = 268,
14154
    M680X_INS_REVW = 269,
14155
    M680X_INS_ROL = 270,
14156
    M680X_INS_ROLA = 271,
14157
    M680X_INS_ROLB = 272,
14158
    M680X_INS_ROLD = 273,
14159
    M680X_INS_ROLW = 274,
14160
    M680X_INS_ROLX = 275,
14161
    M680X_INS_ROR = 276,
14162
    M680X_INS_RORA = 277,
14163
    M680X_INS_RORB = 278,
14164
    M680X_INS_RORD = 279,
14165
    M680X_INS_RORW = 280,
14166
    M680X_INS_RORX = 281,
14167
    M680X_INS_RSP = 282,
14168
    M680X_INS_RTC = 283,
14169
    M680X_INS_RTI = 284,
14170
    M680X_INS_RTS = 285,
14171
    #[doc = "< M6800/1/2/3"]
14172
    M680X_INS_SBA = 286,
14173
    M680X_INS_SBC = 287,
14174
    M680X_INS_SBCA = 288,
14175
    M680X_INS_SBCB = 289,
14176
    M680X_INS_SBCD = 290,
14177
    M680X_INS_SBCR = 291,
14178
    M680X_INS_SEC = 292,
14179
    M680X_INS_SEI = 293,
14180
    M680X_INS_SEV = 294,
14181
    M680X_INS_SEX = 295,
14182
    M680X_INS_SEXW = 296,
14183
    M680X_INS_SLP = 297,
14184
    M680X_INS_STA = 298,
14185
    #[doc = "< M6800/1/2/3"]
14186
    M680X_INS_STAA = 299,
14187
    #[doc = "< M6800/1/2/3"]
14188
    M680X_INS_STAB = 300,
14189
    M680X_INS_STB = 301,
14190
    M680X_INS_STBT = 302,
14191
    M680X_INS_STD = 303,
14192
    M680X_INS_STE = 304,
14193
    M680X_INS_STF = 305,
14194
    M680X_INS_STOP = 306,
14195
    M680X_INS_STHX = 307,
14196
    M680X_INS_STQ = 308,
14197
    M680X_INS_STS = 309,
14198
    M680X_INS_STU = 310,
14199
    M680X_INS_STW = 311,
14200
    M680X_INS_STX = 312,
14201
    M680X_INS_STY = 313,
14202
    M680X_INS_SUB = 314,
14203
    M680X_INS_SUBA = 315,
14204
    M680X_INS_SUBB = 316,
14205
    M680X_INS_SUBD = 317,
14206
    M680X_INS_SUBE = 318,
14207
    M680X_INS_SUBF = 319,
14208
    M680X_INS_SUBR = 320,
14209
    M680X_INS_SUBW = 321,
14210
    M680X_INS_SWI = 322,
14211
    M680X_INS_SWI2 = 323,
14212
    M680X_INS_SWI3 = 324,
14213
    M680X_INS_SYNC = 325,
14214
    #[doc = "< M6800/1/2/3"]
14215
    M680X_INS_TAB = 326,
14216
    #[doc = "< M6800/1/2/3"]
14217
    M680X_INS_TAP = 327,
14218
    M680X_INS_TAX = 328,
14219
    #[doc = "< M6800/1/2/3"]
14220
    M680X_INS_TBA = 329,
14221
    M680X_INS_TBEQ = 330,
14222
    M680X_INS_TBL = 331,
14223
    M680X_INS_TBNE = 332,
14224
    M680X_INS_TEST = 333,
14225
    M680X_INS_TFM = 334,
14226
    M680X_INS_TFR = 335,
14227
    M680X_INS_TIM = 336,
14228
    #[doc = "< M6800/1/2/3"]
14229
    M680X_INS_TPA = 337,
14230
    M680X_INS_TST = 338,
14231
    M680X_INS_TSTA = 339,
14232
    M680X_INS_TSTB = 340,
14233
    M680X_INS_TSTD = 341,
14234
    M680X_INS_TSTE = 342,
14235
    M680X_INS_TSTF = 343,
14236
    M680X_INS_TSTW = 344,
14237
    M680X_INS_TSTX = 345,
14238
    #[doc = "< M6800/1/2/3"]
14239
    M680X_INS_TSX = 346,
14240
    M680X_INS_TSY = 347,
14241
    M680X_INS_TXA = 348,
14242
    #[doc = "< M6800/1/2/3"]
14243
    M680X_INS_TXS = 349,
14244
    M680X_INS_TYS = 350,
14245
    #[doc = "< M6800/1/2/3"]
14246
    M680X_INS_WAI = 351,
14247
    M680X_INS_WAIT = 352,
14248
    M680X_INS_WAV = 353,
14249
    M680X_INS_WAVR = 354,
14250
    #[doc = "< HD6301"]
14251
    M680X_INS_XGDX = 355,
14252
    M680X_INS_XGDY = 356,
14253
    M680X_INS_ENDING = 357,
14254
}
14255
#[doc = " Instruction structure"]
14256
#[repr(C)]
14257
#[derive(Debug, Copy, Clone)]
14258
pub struct cs_evm {
14259
    #[doc = "< number of items popped from the stack"]
14260
    pub pop: libc::c_uchar,
14261
    #[doc = "< number of items pushed into the stack"]
14262
    pub push: libc::c_uchar,
14263
    #[doc = "< gas fee for the instruction"]
14264
    pub fee: libc::c_uint,
14265
}
14266
#[repr(u32)]
14267
#[doc = " EVM instruction"]
14268
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
14269
pub enum evm_insn {
14270
    EVM_INS_STOP = 0,
14271
    EVM_INS_ADD = 1,
14272
    EVM_INS_MUL = 2,
14273
    EVM_INS_SUB = 3,
14274
    EVM_INS_DIV = 4,
14275
    EVM_INS_SDIV = 5,
14276
    EVM_INS_MOD = 6,
14277
    EVM_INS_SMOD = 7,
14278
    EVM_INS_ADDMOD = 8,
14279
    EVM_INS_MULMOD = 9,
14280
    EVM_INS_EXP = 10,
14281
    EVM_INS_SIGNEXTEND = 11,
14282
    EVM_INS_LT = 16,
14283
    EVM_INS_GT = 17,
14284
    EVM_INS_SLT = 18,
14285
    EVM_INS_SGT = 19,
14286
    EVM_INS_EQ = 20,
14287
    EVM_INS_ISZERO = 21,
14288
    EVM_INS_AND = 22,
14289
    EVM_INS_OR = 23,
14290
    EVM_INS_XOR = 24,
14291
    EVM_INS_NOT = 25,
14292
    EVM_INS_BYTE = 26,
14293
    EVM_INS_SHA3 = 32,
14294
    EVM_INS_ADDRESS = 48,
14295
    EVM_INS_BALANCE = 49,
14296
    EVM_INS_ORIGIN = 50,
14297
    EVM_INS_CALLER = 51,
14298
    EVM_INS_CALLVALUE = 52,
14299
    EVM_INS_CALLDATALOAD = 53,
14300
    EVM_INS_CALLDATASIZE = 54,
14301
    EVM_INS_CALLDATACOPY = 55,
14302
    EVM_INS_CODESIZE = 56,
14303
    EVM_INS_CODECOPY = 57,
14304
    EVM_INS_GASPRICE = 58,
14305
    EVM_INS_EXTCODESIZE = 59,
14306
    EVM_INS_EXTCODECOPY = 60,
14307
    EVM_INS_RETURNDATASIZE = 61,
14308
    EVM_INS_RETURNDATACOPY = 62,
14309
    EVM_INS_BLOCKHASH = 64,
14310
    EVM_INS_COINBASE = 65,
14311
    EVM_INS_TIMESTAMP = 66,
14312
    EVM_INS_NUMBER = 67,
14313
    EVM_INS_DIFFICULTY = 68,
14314
    EVM_INS_GASLIMIT = 69,
14315
    EVM_INS_POP = 80,
14316
    EVM_INS_MLOAD = 81,
14317
    EVM_INS_MSTORE = 82,
14318
    EVM_INS_MSTORE8 = 83,
14319
    EVM_INS_SLOAD = 84,
14320
    EVM_INS_SSTORE = 85,
14321
    EVM_INS_JUMP = 86,
14322
    EVM_INS_JUMPI = 87,
14323
    EVM_INS_PC = 88,
14324
    EVM_INS_MSIZE = 89,
14325
    EVM_INS_GAS = 90,
14326
    EVM_INS_JUMPDEST = 91,
14327
    EVM_INS_PUSH1 = 96,
14328
    EVM_INS_PUSH2 = 97,
14329
    EVM_INS_PUSH3 = 98,
14330
    EVM_INS_PUSH4 = 99,
14331
    EVM_INS_PUSH5 = 100,
14332
    EVM_INS_PUSH6 = 101,
14333
    EVM_INS_PUSH7 = 102,
14334
    EVM_INS_PUSH8 = 103,
14335
    EVM_INS_PUSH9 = 104,
14336
    EVM_INS_PUSH10 = 105,
14337
    EVM_INS_PUSH11 = 106,
14338
    EVM_INS_PUSH12 = 107,
14339
    EVM_INS_PUSH13 = 108,
14340
    EVM_INS_PUSH14 = 109,
14341
    EVM_INS_PUSH15 = 110,
14342
    EVM_INS_PUSH16 = 111,
14343
    EVM_INS_PUSH17 = 112,
14344
    EVM_INS_PUSH18 = 113,
14345
    EVM_INS_PUSH19 = 114,
14346
    EVM_INS_PUSH20 = 115,
14347
    EVM_INS_PUSH21 = 116,
14348
    EVM_INS_PUSH22 = 117,
14349
    EVM_INS_PUSH23 = 118,
14350
    EVM_INS_PUSH24 = 119,
14351
    EVM_INS_PUSH25 = 120,
14352
    EVM_INS_PUSH26 = 121,
14353
    EVM_INS_PUSH27 = 122,
14354
    EVM_INS_PUSH28 = 123,
14355
    EVM_INS_PUSH29 = 124,
14356
    EVM_INS_PUSH30 = 125,
14357
    EVM_INS_PUSH31 = 126,
14358
    EVM_INS_PUSH32 = 127,
14359
    EVM_INS_DUP1 = 128,
14360
    EVM_INS_DUP2 = 129,
14361
    EVM_INS_DUP3 = 130,
14362
    EVM_INS_DUP4 = 131,
14363
    EVM_INS_DUP5 = 132,
14364
    EVM_INS_DUP6 = 133,
14365
    EVM_INS_DUP7 = 134,
14366
    EVM_INS_DUP8 = 135,
14367
    EVM_INS_DUP9 = 136,
14368
    EVM_INS_DUP10 = 137,
14369
    EVM_INS_DUP11 = 138,
14370
    EVM_INS_DUP12 = 139,
14371
    EVM_INS_DUP13 = 140,
14372
    EVM_INS_DUP14 = 141,
14373
    EVM_INS_DUP15 = 142,
14374
    EVM_INS_DUP16 = 143,
14375
    EVM_INS_SWAP1 = 144,
14376
    EVM_INS_SWAP2 = 145,
14377
    EVM_INS_SWAP3 = 146,
14378
    EVM_INS_SWAP4 = 147,
14379
    EVM_INS_SWAP5 = 148,
14380
    EVM_INS_SWAP6 = 149,
14381
    EVM_INS_SWAP7 = 150,
14382
    EVM_INS_SWAP8 = 151,
14383
    EVM_INS_SWAP9 = 152,
14384
    EVM_INS_SWAP10 = 153,
14385
    EVM_INS_SWAP11 = 154,
14386
    EVM_INS_SWAP12 = 155,
14387
    EVM_INS_SWAP13 = 156,
14388
    EVM_INS_SWAP14 = 157,
14389
    EVM_INS_SWAP15 = 158,
14390
    EVM_INS_SWAP16 = 159,
14391
    EVM_INS_LOG0 = 160,
14392
    EVM_INS_LOG1 = 161,
14393
    EVM_INS_LOG2 = 162,
14394
    EVM_INS_LOG3 = 163,
14395
    EVM_INS_LOG4 = 164,
14396
    EVM_INS_CREATE = 240,
14397
    EVM_INS_CALL = 241,
14398
    EVM_INS_CALLCODE = 242,
14399
    EVM_INS_RETURN = 243,
14400
    EVM_INS_DELEGATECALL = 244,
14401
    EVM_INS_CALLBLACKBOX = 245,
14402
    EVM_INS_STATICCALL = 250,
14403
    EVM_INS_REVERT = 253,
14404
    EVM_INS_SUICIDE = 255,
14405
    EVM_INS_INVALID = 512,
14406
    EVM_INS_ENDING = 513,
14407
}
14408
pub mod evm_insn_group {
14409
    #[doc = " Group of EVM instructions"]
14410
    pub type Type = libc::c_uint;
14411
    #[doc = "< = CS_GRP_INVALID"]
14412
    pub const EVM_GRP_INVALID: Type = 0;
14413
    #[doc = "< all jump instructions"]
14414
    pub const EVM_GRP_JUMP: Type = 1;
14415
    #[doc = "< math instructions"]
14416
    pub const EVM_GRP_MATH: Type = 8;
14417
    #[doc = "< instructions write to stack"]
14418
    pub const EVM_GRP_STACK_WRITE: Type = 9;
14419
    #[doc = "< instructions read from stack"]
14420
    pub const EVM_GRP_STACK_READ: Type = 10;
14421
    #[doc = "< instructions write to memory"]
14422
    pub const EVM_GRP_MEM_WRITE: Type = 11;
14423
    #[doc = "< instructions read from memory"]
14424
    pub const EVM_GRP_MEM_READ: Type = 12;
14425
    #[doc = "< instructions write to storage"]
14426
    pub const EVM_GRP_STORE_WRITE: Type = 13;
14427
    #[doc = "< instructions read from storage"]
14428
    pub const EVM_GRP_STORE_READ: Type = 14;
14429
    #[doc = "< instructions halt execution"]
14430
    pub const EVM_GRP_HALT: Type = 15;
14431
    #[doc = "< <-- mark the end of the list of groups"]
14432
    pub const EVM_GRP_ENDING: Type = 16;
14433
}
14434
#[repr(u32)]
14435
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
14436
pub enum riscv_op_type {
14437
    RISCV_OP_INVALID = 0,
14438
    RISCV_OP_REG = 1,
14439
    RISCV_OP_IMM = 2,
14440
    RISCV_OP_MEM = 3,
14441
}
14442
#[repr(C)]
14443
#[derive(Debug, Copy, Clone)]
14444
pub struct riscv_op_mem {
14445
    pub base: libc::c_uint,
14446
    pub disp: i64,
14447
}
14448
#[repr(C)]
14449
#[derive(Copy, Clone)]
14450
pub struct cs_riscv_op {
14451
    pub type_: riscv_op_type,
14452
    pub __bindgen_anon_1: cs_riscv_op__bindgen_ty_1,
14453
}
14454
#[repr(C)]
14455
#[derive(Copy, Clone)]
14456
pub union cs_riscv_op__bindgen_ty_1 {
14457
    pub reg: libc::c_uint,
14458
    pub imm: i64,
14459
    pub mem: riscv_op_mem,
14460
}
14461
impl ::core::fmt::Debug for cs_riscv_op__bindgen_ty_1 {
14462
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
14463
0
        write!(f, "cs_riscv_op__bindgen_ty_1 {{ union }}")
14464
0
    }
14465
}
14466
impl ::core::fmt::Debug for cs_riscv_op {
14467
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
14468
0
        write!(
14469
0
            f,
14470
0
            "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
14471
            self.type_, self.__bindgen_anon_1
14472
        )
14473
0
    }
14474
}
14475
#[repr(C)]
14476
#[derive(Copy, Clone)]
14477
pub struct cs_riscv {
14478
    pub need_effective_addr: bool,
14479
    pub op_count: u8,
14480
    pub operands: [cs_riscv_op; 8usize],
14481
}
14482
impl ::core::fmt::Debug for cs_riscv {
14483
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
14484
0
        write!(
14485
0
            f,
14486
0
            "cs_riscv {{ need_effective_addr: {:?}, operands: {:?} }}",
14487
            self.need_effective_addr, self.operands
14488
        )
14489
0
    }
14490
}
14491
pub mod riscv_reg {
14492
    pub type Type = libc::c_uint;
14493
    pub const RISCV_REG_INVALID: Type = 0;
14494
    pub const RISCV_REG_X0: Type = 1;
14495
    pub const RISCV_REG_ZERO: Type = 1;
14496
    pub const RISCV_REG_X1: Type = 2;
14497
    pub const RISCV_REG_RA: Type = 2;
14498
    pub const RISCV_REG_X2: Type = 3;
14499
    pub const RISCV_REG_SP: Type = 3;
14500
    pub const RISCV_REG_X3: Type = 4;
14501
    pub const RISCV_REG_GP: Type = 4;
14502
    pub const RISCV_REG_X4: Type = 5;
14503
    pub const RISCV_REG_TP: Type = 5;
14504
    pub const RISCV_REG_X5: Type = 6;
14505
    pub const RISCV_REG_T0: Type = 6;
14506
    pub const RISCV_REG_X6: Type = 7;
14507
    pub const RISCV_REG_T1: Type = 7;
14508
    pub const RISCV_REG_X7: Type = 8;
14509
    pub const RISCV_REG_T2: Type = 8;
14510
    pub const RISCV_REG_X8: Type = 9;
14511
    pub const RISCV_REG_S0: Type = 9;
14512
    pub const RISCV_REG_FP: Type = 9;
14513
    pub const RISCV_REG_X9: Type = 10;
14514
    pub const RISCV_REG_S1: Type = 10;
14515
    pub const RISCV_REG_X10: Type = 11;
14516
    pub const RISCV_REG_A0: Type = 11;
14517
    pub const RISCV_REG_X11: Type = 12;
14518
    pub const RISCV_REG_A1: Type = 12;
14519
    pub const RISCV_REG_X12: Type = 13;
14520
    pub const RISCV_REG_A2: Type = 13;
14521
    pub const RISCV_REG_X13: Type = 14;
14522
    pub const RISCV_REG_A3: Type = 14;
14523
    pub const RISCV_REG_X14: Type = 15;
14524
    pub const RISCV_REG_A4: Type = 15;
14525
    pub const RISCV_REG_X15: Type = 16;
14526
    pub const RISCV_REG_A5: Type = 16;
14527
    pub const RISCV_REG_X16: Type = 17;
14528
    pub const RISCV_REG_A6: Type = 17;
14529
    pub const RISCV_REG_X17: Type = 18;
14530
    pub const RISCV_REG_A7: Type = 18;
14531
    pub const RISCV_REG_X18: Type = 19;
14532
    pub const RISCV_REG_S2: Type = 19;
14533
    pub const RISCV_REG_X19: Type = 20;
14534
    pub const RISCV_REG_S3: Type = 20;
14535
    pub const RISCV_REG_X20: Type = 21;
14536
    pub const RISCV_REG_S4: Type = 21;
14537
    pub const RISCV_REG_X21: Type = 22;
14538
    pub const RISCV_REG_S5: Type = 22;
14539
    pub const RISCV_REG_X22: Type = 23;
14540
    pub const RISCV_REG_S6: Type = 23;
14541
    pub const RISCV_REG_X23: Type = 24;
14542
    pub const RISCV_REG_S7: Type = 24;
14543
    pub const RISCV_REG_X24: Type = 25;
14544
    pub const RISCV_REG_S8: Type = 25;
14545
    pub const RISCV_REG_X25: Type = 26;
14546
    pub const RISCV_REG_S9: Type = 26;
14547
    pub const RISCV_REG_X26: Type = 27;
14548
    pub const RISCV_REG_S10: Type = 27;
14549
    pub const RISCV_REG_X27: Type = 28;
14550
    pub const RISCV_REG_S11: Type = 28;
14551
    pub const RISCV_REG_X28: Type = 29;
14552
    pub const RISCV_REG_T3: Type = 29;
14553
    pub const RISCV_REG_X29: Type = 30;
14554
    pub const RISCV_REG_T4: Type = 30;
14555
    pub const RISCV_REG_X30: Type = 31;
14556
    pub const RISCV_REG_T5: Type = 31;
14557
    pub const RISCV_REG_X31: Type = 32;
14558
    pub const RISCV_REG_T6: Type = 32;
14559
    pub const RISCV_REG_F0_32: Type = 33;
14560
    pub const RISCV_REG_F0_64: Type = 34;
14561
    pub const RISCV_REG_F1_32: Type = 35;
14562
    pub const RISCV_REG_F1_64: Type = 36;
14563
    pub const RISCV_REG_F2_32: Type = 37;
14564
    pub const RISCV_REG_F2_64: Type = 38;
14565
    pub const RISCV_REG_F3_32: Type = 39;
14566
    pub const RISCV_REG_F3_64: Type = 40;
14567
    pub const RISCV_REG_F4_32: Type = 41;
14568
    pub const RISCV_REG_F4_64: Type = 42;
14569
    pub const RISCV_REG_F5_32: Type = 43;
14570
    pub const RISCV_REG_F5_64: Type = 44;
14571
    pub const RISCV_REG_F6_32: Type = 45;
14572
    pub const RISCV_REG_F6_64: Type = 46;
14573
    pub const RISCV_REG_F7_32: Type = 47;
14574
    pub const RISCV_REG_F7_64: Type = 48;
14575
    pub const RISCV_REG_F8_32: Type = 49;
14576
    pub const RISCV_REG_F8_64: Type = 50;
14577
    pub const RISCV_REG_F9_32: Type = 51;
14578
    pub const RISCV_REG_F9_64: Type = 52;
14579
    pub const RISCV_REG_F10_32: Type = 53;
14580
    pub const RISCV_REG_F10_64: Type = 54;
14581
    pub const RISCV_REG_F11_32: Type = 55;
14582
    pub const RISCV_REG_F11_64: Type = 56;
14583
    pub const RISCV_REG_F12_32: Type = 57;
14584
    pub const RISCV_REG_F12_64: Type = 58;
14585
    pub const RISCV_REG_F13_32: Type = 59;
14586
    pub const RISCV_REG_F13_64: Type = 60;
14587
    pub const RISCV_REG_F14_32: Type = 61;
14588
    pub const RISCV_REG_F14_64: Type = 62;
14589
    pub const RISCV_REG_F15_32: Type = 63;
14590
    pub const RISCV_REG_F15_64: Type = 64;
14591
    pub const RISCV_REG_F16_32: Type = 65;
14592
    pub const RISCV_REG_F16_64: Type = 66;
14593
    pub const RISCV_REG_F17_32: Type = 67;
14594
    pub const RISCV_REG_F17_64: Type = 68;
14595
    pub const RISCV_REG_F18_32: Type = 69;
14596
    pub const RISCV_REG_F18_64: Type = 70;
14597
    pub const RISCV_REG_F19_32: Type = 71;
14598
    pub const RISCV_REG_F19_64: Type = 72;
14599
    pub const RISCV_REG_F20_32: Type = 73;
14600
    pub const RISCV_REG_F20_64: Type = 74;
14601
    pub const RISCV_REG_F21_32: Type = 75;
14602
    pub const RISCV_REG_F21_64: Type = 76;
14603
    pub const RISCV_REG_F22_32: Type = 77;
14604
    pub const RISCV_REG_F22_64: Type = 78;
14605
    pub const RISCV_REG_F23_32: Type = 79;
14606
    pub const RISCV_REG_F23_64: Type = 80;
14607
    pub const RISCV_REG_F24_32: Type = 81;
14608
    pub const RISCV_REG_F24_64: Type = 82;
14609
    pub const RISCV_REG_F25_32: Type = 83;
14610
    pub const RISCV_REG_F25_64: Type = 84;
14611
    pub const RISCV_REG_F26_32: Type = 85;
14612
    pub const RISCV_REG_F26_64: Type = 86;
14613
    pub const RISCV_REG_F27_32: Type = 87;
14614
    pub const RISCV_REG_F27_64: Type = 88;
14615
    pub const RISCV_REG_F28_32: Type = 89;
14616
    pub const RISCV_REG_F28_64: Type = 90;
14617
    pub const RISCV_REG_F29_32: Type = 91;
14618
    pub const RISCV_REG_F29_64: Type = 92;
14619
    pub const RISCV_REG_F30_32: Type = 93;
14620
    pub const RISCV_REG_F30_64: Type = 94;
14621
    pub const RISCV_REG_F31_32: Type = 95;
14622
    pub const RISCV_REG_F31_64: Type = 96;
14623
    pub const RISCV_REG_ENDING: Type = 97;
14624
}
14625
#[repr(u32)]
14626
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
14627
pub enum riscv_insn {
14628
    RISCV_INS_INVALID = 0,
14629
    RISCV_INS_ADD = 1,
14630
    RISCV_INS_ADDI = 2,
14631
    RISCV_INS_ADDIW = 3,
14632
    RISCV_INS_ADDW = 4,
14633
    RISCV_INS_AMOADD_D = 5,
14634
    RISCV_INS_AMOADD_D_AQ = 6,
14635
    RISCV_INS_AMOADD_D_AQ_RL = 7,
14636
    RISCV_INS_AMOADD_D_RL = 8,
14637
    RISCV_INS_AMOADD_W = 9,
14638
    RISCV_INS_AMOADD_W_AQ = 10,
14639
    RISCV_INS_AMOADD_W_AQ_RL = 11,
14640
    RISCV_INS_AMOADD_W_RL = 12,
14641
    RISCV_INS_AMOAND_D = 13,
14642
    RISCV_INS_AMOAND_D_AQ = 14,
14643
    RISCV_INS_AMOAND_D_AQ_RL = 15,
14644
    RISCV_INS_AMOAND_D_RL = 16,
14645
    RISCV_INS_AMOAND_W = 17,
14646
    RISCV_INS_AMOAND_W_AQ = 18,
14647
    RISCV_INS_AMOAND_W_AQ_RL = 19,
14648
    RISCV_INS_AMOAND_W_RL = 20,
14649
    RISCV_INS_AMOMAXU_D = 21,
14650
    RISCV_INS_AMOMAXU_D_AQ = 22,
14651
    RISCV_INS_AMOMAXU_D_AQ_RL = 23,
14652
    RISCV_INS_AMOMAXU_D_RL = 24,
14653
    RISCV_INS_AMOMAXU_W = 25,
14654
    RISCV_INS_AMOMAXU_W_AQ = 26,
14655
    RISCV_INS_AMOMAXU_W_AQ_RL = 27,
14656
    RISCV_INS_AMOMAXU_W_RL = 28,
14657
    RISCV_INS_AMOMAX_D = 29,
14658
    RISCV_INS_AMOMAX_D_AQ = 30,
14659
    RISCV_INS_AMOMAX_D_AQ_RL = 31,
14660
    RISCV_INS_AMOMAX_D_RL = 32,
14661
    RISCV_INS_AMOMAX_W = 33,
14662
    RISCV_INS_AMOMAX_W_AQ = 34,
14663
    RISCV_INS_AMOMAX_W_AQ_RL = 35,
14664
    RISCV_INS_AMOMAX_W_RL = 36,
14665
    RISCV_INS_AMOMINU_D = 37,
14666
    RISCV_INS_AMOMINU_D_AQ = 38,
14667
    RISCV_INS_AMOMINU_D_AQ_RL = 39,
14668
    RISCV_INS_AMOMINU_D_RL = 40,
14669
    RISCV_INS_AMOMINU_W = 41,
14670
    RISCV_INS_AMOMINU_W_AQ = 42,
14671
    RISCV_INS_AMOMINU_W_AQ_RL = 43,
14672
    RISCV_INS_AMOMINU_W_RL = 44,
14673
    RISCV_INS_AMOMIN_D = 45,
14674
    RISCV_INS_AMOMIN_D_AQ = 46,
14675
    RISCV_INS_AMOMIN_D_AQ_RL = 47,
14676
    RISCV_INS_AMOMIN_D_RL = 48,
14677
    RISCV_INS_AMOMIN_W = 49,
14678
    RISCV_INS_AMOMIN_W_AQ = 50,
14679
    RISCV_INS_AMOMIN_W_AQ_RL = 51,
14680
    RISCV_INS_AMOMIN_W_RL = 52,
14681
    RISCV_INS_AMOOR_D = 53,
14682
    RISCV_INS_AMOOR_D_AQ = 54,
14683
    RISCV_INS_AMOOR_D_AQ_RL = 55,
14684
    RISCV_INS_AMOOR_D_RL = 56,
14685
    RISCV_INS_AMOOR_W = 57,
14686
    RISCV_INS_AMOOR_W_AQ = 58,
14687
    RISCV_INS_AMOOR_W_AQ_RL = 59,
14688
    RISCV_INS_AMOOR_W_RL = 60,
14689
    RISCV_INS_AMOSWAP_D = 61,
14690
    RISCV_INS_AMOSWAP_D_AQ = 62,
14691
    RISCV_INS_AMOSWAP_D_AQ_RL = 63,
14692
    RISCV_INS_AMOSWAP_D_RL = 64,
14693
    RISCV_INS_AMOSWAP_W = 65,
14694
    RISCV_INS_AMOSWAP_W_AQ = 66,
14695
    RISCV_INS_AMOSWAP_W_AQ_RL = 67,
14696
    RISCV_INS_AMOSWAP_W_RL = 68,
14697
    RISCV_INS_AMOXOR_D = 69,
14698
    RISCV_INS_AMOXOR_D_AQ = 70,
14699
    RISCV_INS_AMOXOR_D_AQ_RL = 71,
14700
    RISCV_INS_AMOXOR_D_RL = 72,
14701
    RISCV_INS_AMOXOR_W = 73,
14702
    RISCV_INS_AMOXOR_W_AQ = 74,
14703
    RISCV_INS_AMOXOR_W_AQ_RL = 75,
14704
    RISCV_INS_AMOXOR_W_RL = 76,
14705
    RISCV_INS_AND = 77,
14706
    RISCV_INS_ANDI = 78,
14707
    RISCV_INS_AUIPC = 79,
14708
    RISCV_INS_BEQ = 80,
14709
    RISCV_INS_BGE = 81,
14710
    RISCV_INS_BGEU = 82,
14711
    RISCV_INS_BLT = 83,
14712
    RISCV_INS_BLTU = 84,
14713
    RISCV_INS_BNE = 85,
14714
    RISCV_INS_CSRRC = 86,
14715
    RISCV_INS_CSRRCI = 87,
14716
    RISCV_INS_CSRRS = 88,
14717
    RISCV_INS_CSRRSI = 89,
14718
    RISCV_INS_CSRRW = 90,
14719
    RISCV_INS_CSRRWI = 91,
14720
    RISCV_INS_C_ADD = 92,
14721
    RISCV_INS_C_ADDI = 93,
14722
    RISCV_INS_C_ADDI16SP = 94,
14723
    RISCV_INS_C_ADDI4SPN = 95,
14724
    RISCV_INS_C_ADDIW = 96,
14725
    RISCV_INS_C_ADDW = 97,
14726
    RISCV_INS_C_AND = 98,
14727
    RISCV_INS_C_ANDI = 99,
14728
    RISCV_INS_C_BEQZ = 100,
14729
    RISCV_INS_C_BNEZ = 101,
14730
    RISCV_INS_C_EBREAK = 102,
14731
    RISCV_INS_C_FLD = 103,
14732
    RISCV_INS_C_FLDSP = 104,
14733
    RISCV_INS_C_FLW = 105,
14734
    RISCV_INS_C_FLWSP = 106,
14735
    RISCV_INS_C_FSD = 107,
14736
    RISCV_INS_C_FSDSP = 108,
14737
    RISCV_INS_C_FSW = 109,
14738
    RISCV_INS_C_FSWSP = 110,
14739
    RISCV_INS_C_J = 111,
14740
    RISCV_INS_C_JAL = 112,
14741
    RISCV_INS_C_JALR = 113,
14742
    RISCV_INS_C_JR = 114,
14743
    RISCV_INS_C_LD = 115,
14744
    RISCV_INS_C_LDSP = 116,
14745
    RISCV_INS_C_LI = 117,
14746
    RISCV_INS_C_LUI = 118,
14747
    RISCV_INS_C_LW = 119,
14748
    RISCV_INS_C_LWSP = 120,
14749
    RISCV_INS_C_MV = 121,
14750
    RISCV_INS_C_NOP = 122,
14751
    RISCV_INS_C_OR = 123,
14752
    RISCV_INS_C_SD = 124,
14753
    RISCV_INS_C_SDSP = 125,
14754
    RISCV_INS_C_SLLI = 126,
14755
    RISCV_INS_C_SRAI = 127,
14756
    RISCV_INS_C_SRLI = 128,
14757
    RISCV_INS_C_SUB = 129,
14758
    RISCV_INS_C_SUBW = 130,
14759
    RISCV_INS_C_SW = 131,
14760
    RISCV_INS_C_SWSP = 132,
14761
    RISCV_INS_C_UNIMP = 133,
14762
    RISCV_INS_C_XOR = 134,
14763
    RISCV_INS_DIV = 135,
14764
    RISCV_INS_DIVU = 136,
14765
    RISCV_INS_DIVUW = 137,
14766
    RISCV_INS_DIVW = 138,
14767
    RISCV_INS_EBREAK = 139,
14768
    RISCV_INS_ECALL = 140,
14769
    RISCV_INS_FADD_D = 141,
14770
    RISCV_INS_FADD_S = 142,
14771
    RISCV_INS_FCLASS_D = 143,
14772
    RISCV_INS_FCLASS_S = 144,
14773
    RISCV_INS_FCVT_D_L = 145,
14774
    RISCV_INS_FCVT_D_LU = 146,
14775
    RISCV_INS_FCVT_D_S = 147,
14776
    RISCV_INS_FCVT_D_W = 148,
14777
    RISCV_INS_FCVT_D_WU = 149,
14778
    RISCV_INS_FCVT_LU_D = 150,
14779
    RISCV_INS_FCVT_LU_S = 151,
14780
    RISCV_INS_FCVT_L_D = 152,
14781
    RISCV_INS_FCVT_L_S = 153,
14782
    RISCV_INS_FCVT_S_D = 154,
14783
    RISCV_INS_FCVT_S_L = 155,
14784
    RISCV_INS_FCVT_S_LU = 156,
14785
    RISCV_INS_FCVT_S_W = 157,
14786
    RISCV_INS_FCVT_S_WU = 158,
14787
    RISCV_INS_FCVT_WU_D = 159,
14788
    RISCV_INS_FCVT_WU_S = 160,
14789
    RISCV_INS_FCVT_W_D = 161,
14790
    RISCV_INS_FCVT_W_S = 162,
14791
    RISCV_INS_FDIV_D = 163,
14792
    RISCV_INS_FDIV_S = 164,
14793
    RISCV_INS_FENCE = 165,
14794
    RISCV_INS_FENCE_I = 166,
14795
    RISCV_INS_FENCE_TSO = 167,
14796
    RISCV_INS_FEQ_D = 168,
14797
    RISCV_INS_FEQ_S = 169,
14798
    RISCV_INS_FLD = 170,
14799
    RISCV_INS_FLE_D = 171,
14800
    RISCV_INS_FLE_S = 172,
14801
    RISCV_INS_FLT_D = 173,
14802
    RISCV_INS_FLT_S = 174,
14803
    RISCV_INS_FLW = 175,
14804
    RISCV_INS_FMADD_D = 176,
14805
    RISCV_INS_FMADD_S = 177,
14806
    RISCV_INS_FMAX_D = 178,
14807
    RISCV_INS_FMAX_S = 179,
14808
    RISCV_INS_FMIN_D = 180,
14809
    RISCV_INS_FMIN_S = 181,
14810
    RISCV_INS_FMSUB_D = 182,
14811
    RISCV_INS_FMSUB_S = 183,
14812
    RISCV_INS_FMUL_D = 184,
14813
    RISCV_INS_FMUL_S = 185,
14814
    RISCV_INS_FMV_D_X = 186,
14815
    RISCV_INS_FMV_W_X = 187,
14816
    RISCV_INS_FMV_X_D = 188,
14817
    RISCV_INS_FMV_X_W = 189,
14818
    RISCV_INS_FNMADD_D = 190,
14819
    RISCV_INS_FNMADD_S = 191,
14820
    RISCV_INS_FNMSUB_D = 192,
14821
    RISCV_INS_FNMSUB_S = 193,
14822
    RISCV_INS_FSD = 194,
14823
    RISCV_INS_FSGNJN_D = 195,
14824
    RISCV_INS_FSGNJN_S = 196,
14825
    RISCV_INS_FSGNJX_D = 197,
14826
    RISCV_INS_FSGNJX_S = 198,
14827
    RISCV_INS_FSGNJ_D = 199,
14828
    RISCV_INS_FSGNJ_S = 200,
14829
    RISCV_INS_FSQRT_D = 201,
14830
    RISCV_INS_FSQRT_S = 202,
14831
    RISCV_INS_FSUB_D = 203,
14832
    RISCV_INS_FSUB_S = 204,
14833
    RISCV_INS_FSW = 205,
14834
    RISCV_INS_JAL = 206,
14835
    RISCV_INS_JALR = 207,
14836
    RISCV_INS_LB = 208,
14837
    RISCV_INS_LBU = 209,
14838
    RISCV_INS_LD = 210,
14839
    RISCV_INS_LH = 211,
14840
    RISCV_INS_LHU = 212,
14841
    RISCV_INS_LR_D = 213,
14842
    RISCV_INS_LR_D_AQ = 214,
14843
    RISCV_INS_LR_D_AQ_RL = 215,
14844
    RISCV_INS_LR_D_RL = 216,
14845
    RISCV_INS_LR_W = 217,
14846
    RISCV_INS_LR_W_AQ = 218,
14847
    RISCV_INS_LR_W_AQ_RL = 219,
14848
    RISCV_INS_LR_W_RL = 220,
14849
    RISCV_INS_LUI = 221,
14850
    RISCV_INS_LW = 222,
14851
    RISCV_INS_LWU = 223,
14852
    RISCV_INS_MRET = 224,
14853
    RISCV_INS_MUL = 225,
14854
    RISCV_INS_MULH = 226,
14855
    RISCV_INS_MULHSU = 227,
14856
    RISCV_INS_MULHU = 228,
14857
    RISCV_INS_MULW = 229,
14858
    RISCV_INS_OR = 230,
14859
    RISCV_INS_ORI = 231,
14860
    RISCV_INS_REM = 232,
14861
    RISCV_INS_REMU = 233,
14862
    RISCV_INS_REMUW = 234,
14863
    RISCV_INS_REMW = 235,
14864
    RISCV_INS_SB = 236,
14865
    RISCV_INS_SC_D = 237,
14866
    RISCV_INS_SC_D_AQ = 238,
14867
    RISCV_INS_SC_D_AQ_RL = 239,
14868
    RISCV_INS_SC_D_RL = 240,
14869
    RISCV_INS_SC_W = 241,
14870
    RISCV_INS_SC_W_AQ = 242,
14871
    RISCV_INS_SC_W_AQ_RL = 243,
14872
    RISCV_INS_SC_W_RL = 244,
14873
    RISCV_INS_SD = 245,
14874
    RISCV_INS_SFENCE_VMA = 246,
14875
    RISCV_INS_SH = 247,
14876
    RISCV_INS_SLL = 248,
14877
    RISCV_INS_SLLI = 249,
14878
    RISCV_INS_SLLIW = 250,
14879
    RISCV_INS_SLLW = 251,
14880
    RISCV_INS_SLT = 252,
14881
    RISCV_INS_SLTI = 253,
14882
    RISCV_INS_SLTIU = 254,
14883
    RISCV_INS_SLTU = 255,
14884
    RISCV_INS_SRA = 256,
14885
    RISCV_INS_SRAI = 257,
14886
    RISCV_INS_SRAIW = 258,
14887
    RISCV_INS_SRAW = 259,
14888
    RISCV_INS_SRET = 260,
14889
    RISCV_INS_SRL = 261,
14890
    RISCV_INS_SRLI = 262,
14891
    RISCV_INS_SRLIW = 263,
14892
    RISCV_INS_SRLW = 264,
14893
    RISCV_INS_SUB = 265,
14894
    RISCV_INS_SUBW = 266,
14895
    RISCV_INS_SW = 267,
14896
    RISCV_INS_UNIMP = 268,
14897
    RISCV_INS_URET = 269,
14898
    RISCV_INS_WFI = 270,
14899
    RISCV_INS_XOR = 271,
14900
    RISCV_INS_XORI = 272,
14901
    RISCV_INS_ENDING = 273,
14902
}
14903
pub mod riscv_insn_group {
14904
    pub type Type = libc::c_uint;
14905
    pub const RISCV_GRP_INVALID: Type = 0;
14906
    pub const RISCV_GRP_JUMP: Type = 1;
14907
    pub const RISCV_GRP_ISRV32: Type = 128;
14908
    pub const RISCV_GRP_ISRV64: Type = 129;
14909
    pub const RISCV_GRP_HASSTDEXTA: Type = 130;
14910
    pub const RISCV_GRP_HASSTDEXTC: Type = 131;
14911
    pub const RISCV_GRP_HASSTDEXTD: Type = 132;
14912
    pub const RISCV_GRP_HASSTDEXTF: Type = 133;
14913
    pub const RISCV_GRP_HASSTDEXTM: Type = 134;
14914
    pub const RISCV_GRP_ENDING: Type = 135;
14915
}
14916
#[repr(u32)]
14917
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
14918
pub enum wasm_op_type {
14919
    WASM_OP_INVALID = 0,
14920
    WASM_OP_NONE = 1,
14921
    WASM_OP_INT7 = 2,
14922
    WASM_OP_VARUINT32 = 3,
14923
    WASM_OP_VARUINT64 = 4,
14924
    WASM_OP_UINT32 = 5,
14925
    WASM_OP_UINT64 = 6,
14926
    WASM_OP_IMM = 7,
14927
    WASM_OP_BRTABLE = 8,
14928
}
14929
#[repr(C)]
14930
#[derive(Debug, Copy, Clone)]
14931
pub struct cs_wasm_brtable {
14932
    pub length: u32,
14933
    pub address: u64,
14934
    pub default_target: u32,
14935
}
14936
#[repr(C)]
14937
#[derive(Copy, Clone)]
14938
pub struct cs_wasm_op {
14939
    pub type_: wasm_op_type,
14940
    pub size: u32,
14941
    pub __bindgen_anon_1: cs_wasm_op__bindgen_ty_1,
14942
}
14943
#[repr(C)]
14944
#[derive(Copy, Clone)]
14945
pub union cs_wasm_op__bindgen_ty_1 {
14946
    pub int7: i8,
14947
    pub varuint32: u32,
14948
    pub varuint64: u64,
14949
    pub uint32: u32,
14950
    pub uint64: u64,
14951
    pub immediate: [u32; 2usize],
14952
    pub brtable: cs_wasm_brtable,
14953
}
14954
impl ::core::fmt::Debug for cs_wasm_op__bindgen_ty_1 {
14955
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
14956
0
        write!(f, "cs_wasm_op__bindgen_ty_1 {{ union }}")
14957
0
    }
14958
}
14959
impl ::core::fmt::Debug for cs_wasm_op {
14960
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
14961
0
        write!(
14962
0
            f,
14963
0
            "cs_wasm_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
14964
            self.type_, self.__bindgen_anon_1
14965
        )
14966
0
    }
14967
}
14968
#[doc = " Instruction structure"]
14969
#[repr(C)]
14970
#[derive(Copy, Clone)]
14971
pub struct cs_wasm {
14972
    pub op_count: u8,
14973
    pub operands: [cs_wasm_op; 2usize],
14974
}
14975
impl ::core::fmt::Debug for cs_wasm {
14976
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
14977
0
        write!(f, "cs_wasm {{ operands: {:?} }}", self.operands)
14978
0
    }
14979
}
14980
#[repr(u32)]
14981
#[doc = " MOS65XX registers and special registers"]
14982
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
14983
pub enum mos65xx_reg {
14984
    MOS65XX_REG_INVALID = 0,
14985
    #[doc = "< accumulator"]
14986
    MOS65XX_REG_ACC = 1,
14987
    #[doc = "< X index register"]
14988
    MOS65XX_REG_X = 2,
14989
    #[doc = "< Y index register"]
14990
    MOS65XX_REG_Y = 3,
14991
    #[doc = "< status register"]
14992
    MOS65XX_REG_P = 4,
14993
    #[doc = "< stack pointer register"]
14994
    MOS65XX_REG_SP = 5,
14995
    #[doc = "< direct page register"]
14996
    MOS65XX_REG_DP = 6,
14997
    #[doc = "< data bank register"]
14998
    MOS65XX_REG_B = 7,
14999
    #[doc = "< program bank register"]
15000
    MOS65XX_REG_K = 8,
15001
    MOS65XX_REG_ENDING = 9,
15002
}
15003
#[repr(u32)]
15004
#[doc = " MOS65XX Addressing Modes"]
15005
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
15006
pub enum mos65xx_address_mode {
15007
    #[doc = "< No address mode."]
15008
    MOS65XX_AM_NONE = 0,
15009
    #[doc = "< implied addressing (no addressing mode)"]
15010
    MOS65XX_AM_IMP = 1,
15011
    #[doc = "< accumulator addressing"]
15012
    MOS65XX_AM_ACC = 2,
15013
    #[doc = "< 8/16 Bit immediate value"]
15014
    MOS65XX_AM_IMM = 3,
15015
    #[doc = "< relative addressing used by branches"]
15016
    MOS65XX_AM_REL = 4,
15017
    #[doc = "< interrupt addressing"]
15018
    MOS65XX_AM_INT = 5,
15019
    #[doc = "< memory block addressing"]
15020
    MOS65XX_AM_BLOCK = 6,
15021
    #[doc = "< zeropage addressing"]
15022
    MOS65XX_AM_ZP = 7,
15023
    #[doc = "< indexed zeropage addressing by the X index register"]
15024
    MOS65XX_AM_ZP_X = 8,
15025
    #[doc = "< indexed zeropage addressing by the Y index register"]
15026
    MOS65XX_AM_ZP_Y = 9,
15027
    #[doc = "< zero page address, branch relative address"]
15028
    MOS65XX_AM_ZP_REL = 10,
15029
    #[doc = "< indirect zeropage addressing"]
15030
    MOS65XX_AM_ZP_IND = 11,
15031
    #[doc = "< indexed zeropage indirect addressing by the X index register"]
15032
    MOS65XX_AM_ZP_X_IND = 12,
15033
    #[doc = "< indirect zeropage indexed addressing by the Y index register"]
15034
    MOS65XX_AM_ZP_IND_Y = 13,
15035
    #[doc = "< zeropage indirect long addressing"]
15036
    MOS65XX_AM_ZP_IND_LONG = 14,
15037
    #[doc = "< zeropage indirect long addressing indexed by Y register"]
15038
    MOS65XX_AM_ZP_IND_LONG_Y = 15,
15039
    #[doc = "< absolute addressing"]
15040
    MOS65XX_AM_ABS = 16,
15041
    #[doc = "< indexed absolute addressing by the X index register"]
15042
    MOS65XX_AM_ABS_X = 17,
15043
    #[doc = "< indexed absolute addressing by the Y index register"]
15044
    MOS65XX_AM_ABS_Y = 18,
15045
    #[doc = "< absolute indirect addressing"]
15046
    MOS65XX_AM_ABS_IND = 19,
15047
    #[doc = "< indexed absolute indirect addressing by the X index register"]
15048
    MOS65XX_AM_ABS_X_IND = 20,
15049
    #[doc = "< absolute indirect long addressing"]
15050
    MOS65XX_AM_ABS_IND_LONG = 21,
15051
    #[doc = "< absolute long address mode"]
15052
    MOS65XX_AM_ABS_LONG = 22,
15053
    #[doc = "< absolute long address mode, indexed by X register"]
15054
    MOS65XX_AM_ABS_LONG_X = 23,
15055
    #[doc = "< stack relative addressing"]
15056
    MOS65XX_AM_SR = 24,
15057
    #[doc = "< indirect stack relative addressing indexed by the Y index register"]
15058
    MOS65XX_AM_SR_IND_Y = 25,
15059
}
15060
#[repr(u32)]
15061
#[doc = " Operand type for instruction's operands"]
15062
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
15063
pub enum mos65xx_op_type {
15064
    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
15065
    MOS65XX_OP_INVALID = 0,
15066
    #[doc = "< = CS_OP_REG (Register operand)."]
15067
    MOS65XX_OP_REG = 1,
15068
    #[doc = "< = CS_OP_IMM (Immediate operand)."]
15069
    MOS65XX_OP_IMM = 2,
15070
    #[doc = "< = CS_OP_MEM (Memory operand)."]
15071
    MOS65XX_OP_MEM = 3,
15072
}
15073
#[doc = " Instruction operand"]
15074
#[repr(C)]
15075
#[derive(Copy, Clone)]
15076
pub struct cs_mos65xx_op {
15077
    #[doc = "< operand type"]
15078
    pub type_: mos65xx_op_type,
15079
    pub __bindgen_anon_1: cs_mos65xx_op__bindgen_ty_1,
15080
}
15081
#[repr(C)]
15082
#[derive(Copy, Clone)]
15083
pub union cs_mos65xx_op__bindgen_ty_1 {
15084
    #[doc = "< register value for REG operand"]
15085
    pub reg: mos65xx_reg,
15086
    #[doc = "< immediate value for IMM operand"]
15087
    pub imm: u16,
15088
    #[doc = "< address for MEM operand"]
15089
    pub mem: u32,
15090
}
15091
impl ::core::fmt::Debug for cs_mos65xx_op__bindgen_ty_1 {
15092
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15093
0
        write!(f, "cs_mos65xx_op__bindgen_ty_1 {{ union }}")
15094
0
    }
15095
}
15096
impl ::core::fmt::Debug for cs_mos65xx_op {
15097
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15098
0
        write!(
15099
0
            f,
15100
0
            "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
15101
            self.type_, self.__bindgen_anon_1
15102
        )
15103
0
    }
15104
}
15105
#[doc = " The MOS65XX address mode and it's operands"]
15106
#[repr(C)]
15107
#[derive(Copy, Clone)]
15108
pub struct cs_mos65xx {
15109
    pub am: mos65xx_address_mode,
15110
    pub modifies_flags: bool,
15111
    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
15112
    pub op_count: u8,
15113
    #[doc = "< operands for this instruction."]
15114
    pub operands: [cs_mos65xx_op; 3usize],
15115
}
15116
impl ::core::fmt::Debug for cs_mos65xx {
15117
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15118
0
        write!(
15119
0
            f,
15120
0
            "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, operands: {:?} }}",
15121
            self.am, self.modifies_flags, self.operands
15122
        )
15123
0
    }
15124
}
15125
#[repr(u32)]
15126
#[doc = " Operand type for instruction's operands"]
15127
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
15128
pub enum bpf_op_type {
15129
    BPF_OP_INVALID = 0,
15130
    BPF_OP_REG = 1,
15131
    BPF_OP_IMM = 2,
15132
    BPF_OP_OFF = 3,
15133
    BPF_OP_MEM = 4,
15134
    #[doc = "< M[k] in cBPF"]
15135
    BPF_OP_MMEM = 5,
15136
    #[doc = "< corresponds to cBPF's BPF_MSH mode"]
15137
    BPF_OP_MSH = 6,
15138
    #[doc = "< cBPF's extension (not eBPF)"]
15139
    BPF_OP_EXT = 7,
15140
}
15141
pub mod bpf_reg {
15142
    #[doc = " BPF registers"]
15143
    pub type Type = libc::c_uint;
15144
    pub const BPF_REG_INVALID: Type = 0;
15145
    pub const BPF_REG_A: Type = 1;
15146
    pub const BPF_REG_X: Type = 2;
15147
    pub const BPF_REG_R0: Type = 3;
15148
    pub const BPF_REG_R1: Type = 4;
15149
    pub const BPF_REG_R2: Type = 5;
15150
    pub const BPF_REG_R3: Type = 6;
15151
    pub const BPF_REG_R4: Type = 7;
15152
    pub const BPF_REG_R5: Type = 8;
15153
    pub const BPF_REG_R6: Type = 9;
15154
    pub const BPF_REG_R7: Type = 10;
15155
    pub const BPF_REG_R8: Type = 11;
15156
    pub const BPF_REG_R9: Type = 12;
15157
    pub const BPF_REG_R10: Type = 13;
15158
    pub const BPF_REG_ENDING: Type = 14;
15159
}
15160
#[doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"]
15161
#[repr(C)]
15162
#[derive(Debug, Copy, Clone)]
15163
pub struct bpf_op_mem {
15164
    #[doc = "< base register"]
15165
    pub base: bpf_reg::Type,
15166
    #[doc = "< offset value"]
15167
    pub disp: u32,
15168
}
15169
#[repr(u32)]
15170
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
15171
pub enum bpf_ext_type {
15172
    BPF_EXT_INVALID = 0,
15173
    BPF_EXT_LEN = 1,
15174
}
15175
#[doc = " Instruction operand"]
15176
#[repr(C)]
15177
#[derive(Copy, Clone)]
15178
pub struct cs_bpf_op {
15179
    pub type_: bpf_op_type,
15180
    pub __bindgen_anon_1: cs_bpf_op__bindgen_ty_1,
15181
    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."]
15182
    pub access: u8,
15183
}
15184
#[repr(C)]
15185
#[derive(Copy, Clone)]
15186
pub union cs_bpf_op__bindgen_ty_1 {
15187
    #[doc = "< register value for REG operand"]
15188
    pub reg: u8,
15189
    #[doc = "< immediate value IMM operand"]
15190
    pub imm: u64,
15191
    #[doc = "< offset value, used in jump & call"]
15192
    pub off: u32,
15193
    #[doc = "< base/disp value for MEM operand"]
15194
    pub mem: bpf_op_mem,
15195
    #[doc = "< M[k] in cBPF"]
15196
    pub mmem: u32,
15197
    #[doc = "< corresponds to cBPF's BPF_MSH mode"]
15198
    pub msh: u32,
15199
    #[doc = "< cBPF's extension (not eBPF)"]
15200
    pub ext: u32,
15201
}
15202
impl ::core::fmt::Debug for cs_bpf_op__bindgen_ty_1 {
15203
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15204
0
        write!(f, "cs_bpf_op__bindgen_ty_1 {{ union }}")
15205
0
    }
15206
}
15207
impl ::core::fmt::Debug for cs_bpf_op {
15208
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15209
0
        write!(
15210
0
            f,
15211
0
            "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
15212
            self.type_, self.__bindgen_anon_1
15213
        )
15214
0
    }
15215
}
15216
#[doc = " Instruction structure"]
15217
#[repr(C)]
15218
#[derive(Copy, Clone)]
15219
pub struct cs_bpf {
15220
    pub op_count: u8,
15221
    pub operands: [cs_bpf_op; 4usize],
15222
}
15223
impl ::core::fmt::Debug for cs_bpf {
15224
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15225
0
        write!(f, "cs_bpf {{ operands: {:?} }}", self.operands)
15226
0
    }
15227
}
15228
impl bpf_insn {
15229
    pub const BPF_INS_LD: bpf_insn = bpf_insn::BPF_INS_LDW;
15230
}
15231
impl bpf_insn {
15232
    pub const BPF_INS_LDX: bpf_insn = bpf_insn::BPF_INS_LDXW;
15233
}
15234
impl bpf_insn {
15235
    pub const BPF_INS_ST: bpf_insn = bpf_insn::BPF_INS_STW;
15236
}
15237
impl bpf_insn {
15238
    pub const BPF_INS_STX: bpf_insn = bpf_insn::BPF_INS_STXW;
15239
}
15240
#[repr(u32)]
15241
#[doc = " BPF instruction"]
15242
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
15243
pub enum bpf_insn {
15244
    BPF_INS_INVALID = 0,
15245
    BPF_INS_ADD = 1,
15246
    BPF_INS_SUB = 2,
15247
    BPF_INS_MUL = 3,
15248
    BPF_INS_DIV = 4,
15249
    BPF_INS_OR = 5,
15250
    BPF_INS_AND = 6,
15251
    BPF_INS_LSH = 7,
15252
    BPF_INS_RSH = 8,
15253
    BPF_INS_NEG = 9,
15254
    BPF_INS_MOD = 10,
15255
    BPF_INS_XOR = 11,
15256
    #[doc = "< eBPF only"]
15257
    BPF_INS_MOV = 12,
15258
    #[doc = "< eBPF only"]
15259
    BPF_INS_ARSH = 13,
15260
    BPF_INS_ADD64 = 14,
15261
    BPF_INS_SUB64 = 15,
15262
    BPF_INS_MUL64 = 16,
15263
    BPF_INS_DIV64 = 17,
15264
    BPF_INS_OR64 = 18,
15265
    BPF_INS_AND64 = 19,
15266
    BPF_INS_LSH64 = 20,
15267
    BPF_INS_RSH64 = 21,
15268
    BPF_INS_NEG64 = 22,
15269
    BPF_INS_MOD64 = 23,
15270
    BPF_INS_XOR64 = 24,
15271
    BPF_INS_MOV64 = 25,
15272
    BPF_INS_ARSH64 = 26,
15273
    BPF_INS_LE16 = 27,
15274
    BPF_INS_LE32 = 28,
15275
    BPF_INS_LE64 = 29,
15276
    BPF_INS_BE16 = 30,
15277
    BPF_INS_BE32 = 31,
15278
    BPF_INS_BE64 = 32,
15279
    #[doc = "< eBPF only"]
15280
    BPF_INS_LDW = 33,
15281
    BPF_INS_LDH = 34,
15282
    BPF_INS_LDB = 35,
15283
    #[doc = "< eBPF only: load 64-bit imm"]
15284
    BPF_INS_LDDW = 36,
15285
    #[doc = "< eBPF only"]
15286
    BPF_INS_LDXW = 37,
15287
    #[doc = "< eBPF only"]
15288
    BPF_INS_LDXH = 38,
15289
    #[doc = "< eBPF only"]
15290
    BPF_INS_LDXB = 39,
15291
    #[doc = "< eBPF only"]
15292
    BPF_INS_LDXDW = 40,
15293
    #[doc = "< eBPF only"]
15294
    BPF_INS_STW = 41,
15295
    #[doc = "< eBPF only"]
15296
    BPF_INS_STH = 42,
15297
    #[doc = "< eBPF only"]
15298
    BPF_INS_STB = 43,
15299
    #[doc = "< eBPF only"]
15300
    BPF_INS_STDW = 44,
15301
    #[doc = "< eBPF only"]
15302
    BPF_INS_STXW = 45,
15303
    #[doc = "< eBPF only"]
15304
    BPF_INS_STXH = 46,
15305
    #[doc = "< eBPF only"]
15306
    BPF_INS_STXB = 47,
15307
    #[doc = "< eBPF only"]
15308
    BPF_INS_STXDW = 48,
15309
    #[doc = "< eBPF only"]
15310
    BPF_INS_XADDW = 49,
15311
    #[doc = "< eBPF only"]
15312
    BPF_INS_XADDDW = 50,
15313
    BPF_INS_JMP = 51,
15314
    BPF_INS_JEQ = 52,
15315
    BPF_INS_JGT = 53,
15316
    BPF_INS_JGE = 54,
15317
    BPF_INS_JSET = 55,
15318
    #[doc = "< eBPF only"]
15319
    BPF_INS_JNE = 56,
15320
    #[doc = "< eBPF only"]
15321
    BPF_INS_JSGT = 57,
15322
    #[doc = "< eBPF only"]
15323
    BPF_INS_JSGE = 58,
15324
    #[doc = "< eBPF only"]
15325
    BPF_INS_CALL = 59,
15326
    #[doc = "< eBPF only"]
15327
    BPF_INS_EXIT = 60,
15328
    #[doc = "< eBPF only"]
15329
    BPF_INS_JLT = 61,
15330
    #[doc = "< eBPF only"]
15331
    BPF_INS_JLE = 62,
15332
    #[doc = "< eBPF only"]
15333
    BPF_INS_JSLT = 63,
15334
    #[doc = "< eBPF only"]
15335
    BPF_INS_JSLE = 64,
15336
    BPF_INS_RET = 65,
15337
    BPF_INS_TAX = 66,
15338
    BPF_INS_TXA = 67,
15339
    BPF_INS_ENDING = 68,
15340
}
15341
pub mod bpf_insn_group {
15342
    #[doc = " Group of BPF instructions"]
15343
    pub type Type = libc::c_uint;
15344
    #[doc = "< = CS_GRP_INVALID"]
15345
    pub const BPF_GRP_INVALID: Type = 0;
15346
    pub const BPF_GRP_LOAD: Type = 1;
15347
    pub const BPF_GRP_STORE: Type = 2;
15348
    pub const BPF_GRP_ALU: Type = 3;
15349
    pub const BPF_GRP_JUMP: Type = 4;
15350
    #[doc = "< eBPF only"]
15351
    pub const BPF_GRP_CALL: Type = 5;
15352
    pub const BPF_GRP_RETURN: Type = 6;
15353
    #[doc = "< cBPF only"]
15354
    pub const BPF_GRP_MISC: Type = 7;
15355
    pub const BPF_GRP_ENDING: Type = 8;
15356
}
15357
#[doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"]
15358
#[repr(C)]
15359
#[derive(Copy, Clone)]
15360
pub struct cs_detail {
15361
    #[doc = "< list of implicit registers read by this insn"]
15362
    pub regs_read: [u16; 16usize],
15363
    #[doc = "< number of implicit registers read by this insn"]
15364
    pub regs_read_count: u8,
15365
    #[doc = "< list of implicit registers modified by this insn"]
15366
    pub regs_write: [u16; 20usize],
15367
    #[doc = "< number of implicit registers modified by this insn"]
15368
    pub regs_write_count: u8,
15369
    #[doc = "< list of group this instruction belong to"]
15370
    pub groups: [u8; 8usize],
15371
    #[doc = "< number of groups this insn belongs to"]
15372
    pub groups_count: u8,
15373
    pub __bindgen_anon_1: cs_detail__bindgen_ty_1,
15374
}
15375
#[doc = " Architecture-specific instruction info"]
15376
#[repr(C)]
15377
#[derive(Copy, Clone)]
15378
pub union cs_detail__bindgen_ty_1 {
15379
    #[doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"]
15380
    pub x86: cs_x86,
15381
    #[doc = "< ARM64 architecture (aka AArch64)"]
15382
    pub arm64: cs_arm64,
15383
    #[doc = "< ARM architecture (including Thumb/Thumb2)"]
15384
    pub arm: cs_arm,
15385
    #[doc = "< M68K architecture"]
15386
    pub m68k: cs_m68k,
15387
    #[doc = "< MIPS architecture"]
15388
    pub mips: cs_mips,
15389
    #[doc = "< PowerPC architecture"]
15390
    pub ppc: cs_ppc,
15391
    #[doc = "< Sparc architecture"]
15392
    pub sparc: cs_sparc,
15393
    #[doc = "< SystemZ architecture"]
15394
    pub sysz: cs_sysz,
15395
    #[doc = "< XCore architecture"]
15396
    pub xcore: cs_xcore,
15397
    #[doc = "< TMS320C64x architecture"]
15398
    pub tms320c64x: cs_tms320c64x,
15399
    #[doc = "< M680X architecture"]
15400
    pub m680x: cs_m680x,
15401
    #[doc = "< Ethereum architecture"]
15402
    pub evm: cs_evm,
15403
    #[doc = "< MOS65XX architecture (including MOS6502)"]
15404
    pub mos65xx: cs_mos65xx,
15405
    #[doc = "< Web Assembly architecture"]
15406
    pub wasm: cs_wasm,
15407
    #[doc = "< Berkeley Packet Filter architecture (including eBPF)"]
15408
    pub bpf: cs_bpf,
15409
    #[doc = "< RISCV architecture"]
15410
    pub riscv: cs_riscv,
15411
}
15412
impl ::core::fmt::Debug for cs_detail__bindgen_ty_1 {
15413
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15414
0
        write!(f, "cs_detail__bindgen_ty_1 {{ union }}")
15415
0
    }
15416
}
15417
impl ::core::fmt::Debug for cs_detail {
15418
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15419
0
        write ! (f , "cs_detail {{ regs_read: {:?}, regs_write: {:?}, groups: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_write , self . groups , self . __bindgen_anon_1)
15420
0
    }
15421
}
15422
#[doc = " Detail information of disassembled instruction"]
15423
#[repr(C)]
15424
pub struct cs_insn {
15425
    #[doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."]
15426
    pub id: libc::c_uint,
15427
    #[doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
15428
    pub address: u64,
15429
    #[doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
15430
    pub size: u16,
15431
    #[doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
15432
    pub bytes: [u8; 24usize],
15433
    #[doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
15434
    pub mnemonic: [libc::c_char; 32usize],
15435
    #[doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
15436
    pub op_str: [libc::c_char; 160usize],
15437
    #[doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."]
15438
    pub detail: *mut cs_detail,
15439
}
15440
impl ::core::fmt::Debug for cs_insn {
15441
0
    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
15442
0
        write!(
15443
0
            f,
15444
0
            "cs_insn {{ id: {:?}, bytes: {:?}, mnemonic: [...], op_str: [...], detail: {:?} }}",
15445
            self.id, self.bytes, self.detail
15446
        )
15447
0
    }
15448
}
15449
pub mod cs_err {
15450
    #[doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"]
15451
    pub type Type = libc::c_uint;
15452
    #[doc = "< No error: everything was fine"]
15453
    pub const CS_ERR_OK: Type = 0;
15454
    #[doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"]
15455
    pub const CS_ERR_MEM: Type = 1;
15456
    #[doc = "< Unsupported architecture: cs_open()"]
15457
    pub const CS_ERR_ARCH: Type = 2;
15458
    #[doc = "< Invalid handle: cs_op_count(), cs_op_index()"]
15459
    pub const CS_ERR_HANDLE: Type = 3;
15460
    #[doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"]
15461
    pub const CS_ERR_CSH: Type = 4;
15462
    #[doc = "< Invalid/unsupported mode: cs_open()"]
15463
    pub const CS_ERR_MODE: Type = 5;
15464
    #[doc = "< Invalid/unsupported option: cs_option()"]
15465
    pub const CS_ERR_OPTION: Type = 6;
15466
    #[doc = "< Information is unavailable because detail option is OFF"]
15467
    pub const CS_ERR_DETAIL: Type = 7;
15468
    #[doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"]
15469
    pub const CS_ERR_MEMSETUP: Type = 8;
15470
    #[doc = "< Unsupported version (bindings)"]
15471
    pub const CS_ERR_VERSION: Type = 9;
15472
    #[doc = "< Access irrelevant data in \"diet\" engine"]
15473
    pub const CS_ERR_DIET: Type = 10;
15474
    #[doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"]
15475
    pub const CS_ERR_SKIPDATA: Type = 11;
15476
    #[doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"]
15477
    pub const CS_ERR_X86_ATT: Type = 12;
15478
    #[doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"]
15479
    pub const CS_ERR_X86_INTEL: Type = 13;
15480
    #[doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"]
15481
    pub const CS_ERR_X86_MASM: Type = 14;
15482
}
15483
extern "C" {
15484
    #[doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."]
15485
    pub fn cs_version(major: *mut libc::c_int, minor: *mut libc::c_int) -> libc::c_uint;
15486
}
15487
extern "C" {
15488
    #[doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."]
15489
    pub fn cs_support(query: libc::c_int) -> bool;
15490
}
15491
extern "C" {
15492
    #[doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."]
15493
    pub fn cs_open(arch: cs_arch, mode: cs_mode, handle: *mut csh) -> cs_err::Type;
15494
}
15495
extern "C" {
15496
    #[doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."]
15497
    pub fn cs_close(handle: *mut csh) -> cs_err::Type;
15498
}
15499
extern "C" {
15500
    #[doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"]
15501
    pub fn cs_option(handle: csh, type_: cs_opt_type, value: usize) -> cs_err::Type;
15502
}
15503
extern "C" {
15504
    #[doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"]
15505
    pub fn cs_errno(handle: csh) -> cs_err::Type;
15506
}
15507
extern "C" {
15508
    #[doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"]
15509
    pub fn cs_strerror(code: cs_err::Type) -> *const libc::c_char;
15510
}
15511
extern "C" {
15512
    #[doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."]
15513
    pub fn cs_disasm(
15514
        handle: csh,
15515
        code: *const u8,
15516
        code_size: usize,
15517
        address: u64,
15518
        count: usize,
15519
        insn: *mut *mut cs_insn,
15520
    ) -> usize;
15521
}
15522
extern "C" {
15523
    #[doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."]
15524
    pub fn cs_free(insn: *mut cs_insn, count: usize);
15525
}
15526
extern "C" {
15527
    #[doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"]
15528
    pub fn cs_malloc(handle: csh) -> *mut cs_insn;
15529
}
15530
extern "C" {
15531
    #[doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."]
15532
    pub fn cs_disasm_iter(
15533
        handle: csh,
15534
        code: *mut *const u8,
15535
        size: *mut usize,
15536
        address: *mut u64,
15537
        insn: *mut cs_insn,
15538
    ) -> bool;
15539
}
15540
extern "C" {
15541
    #[doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."]
15542
    pub fn cs_reg_name(handle: csh, reg_id: libc::c_uint) -> *const libc::c_char;
15543
}
15544
extern "C" {
15545
    #[doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."]
15546
    pub fn cs_insn_name(handle: csh, insn_id: libc::c_uint) -> *const libc::c_char;
15547
}
15548
extern "C" {
15549
    #[doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."]
15550
    pub fn cs_group_name(handle: csh, group_id: libc::c_uint) -> *const libc::c_char;
15551
}
15552
extern "C" {
15553
    #[doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."]
15554
    pub fn cs_insn_group(handle: csh, insn: *const cs_insn, group_id: libc::c_uint) -> bool;
15555
}
15556
extern "C" {
15557
    #[doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."]
15558
    pub fn cs_reg_read(handle: csh, insn: *const cs_insn, reg_id: libc::c_uint) -> bool;
15559
}
15560
extern "C" {
15561
    #[doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."]
15562
    pub fn cs_reg_write(handle: csh, insn: *const cs_insn, reg_id: libc::c_uint) -> bool;
15563
}
15564
extern "C" {
15565
    #[doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."]
15566
    pub fn cs_op_count(handle: csh, insn: *const cs_insn, op_type: libc::c_uint) -> libc::c_int;
15567
}
15568
extern "C" {
15569
    #[doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."]
15570
    pub fn cs_op_index(
15571
        handle: csh,
15572
        insn: *const cs_insn,
15573
        op_type: libc::c_uint,
15574
        position: libc::c_uint,
15575
    ) -> libc::c_int;
15576
}
15577
#[doc = " Type of array to keep the list of registers"]
15578
pub type cs_regs = [u16; 64usize];
15579
extern "C" {
15580
    #[doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."]
15581
    pub fn cs_regs_access(
15582
        handle: csh,
15583
        insn: *const cs_insn,
15584
        regs_read: *mut u16,
15585
        regs_read_count: *mut u8,
15586
        regs_write: *mut u16,
15587
        regs_write_count: *mut u8,
15588
    ) -> cs_err::Type;
15589
}
15590
pub type __builtin_va_list = [__va_list_tag; 1usize];
15591
#[repr(C)]
15592
#[derive(Debug, Copy, Clone)]
15593
pub struct __va_list_tag {
15594
    pub gp_offset: libc::c_uint,
15595
    pub fp_offset: libc::c_uint,
15596
    pub overflow_arg_area: *mut libc::c_void,
15597
    pub reg_save_area: *mut libc::c_void,
15598
}