Coverage Report

Created: 2026-01-02 06:13

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/wireshark/epan/dissectors/packet-rfid-pn532.c
Line
Count
Source
1
/* packet-rfid-pn532.c
2
 * Dissector for the NXP PN532 Protocol
3
 *
4
 * References:
5
 * http://www.nxp.com/documents/user_manual/141520.pdf
6
 *
7
 * Copyright 2012, Tyson Key <tyson.key@gmail.com>
8
 * Copyright 2013, Michal Labedzki for Tieto Corporation
9
 *
10
 * Wireshark - Network traffic analyzer
11
 * By Gerald Combs <gerald@wireshark.org>
12
 * Copyright 1998 Gerald Combs
13
 *
14
 * SPDX-License-Identifier: GPL-2.0-or-later
15
 *
16
 */
17
18
#include "config.h"
19
20
#include <epan/packet.h>
21
#include <epan/prefs.h>
22
#include <epan/expert.h>
23
#include "packet-usb.h"
24
25
static int proto_pn532;
26
27
static int hf_pn532_command;
28
static int hf_pn532_direction;
29
static int hf_pn532_MaxTg;
30
static int hf_pn532_Tg;
31
static int hf_pn532_NbTg;
32
static int hf_pn532_BrTy;
33
static int hf_pn532_error;
34
static int hf_pn532_status_nad_present;
35
static int hf_pn532_status_mi;
36
static int hf_pn532_status_error_code;
37
static int hf_pn532_payload_length;
38
static int hf_pn532_ic_version;
39
static int hf_pn532_fw_version;
40
static int hf_pn532_fw_revision;
41
static int hf_pn532_fw_support;
42
static int hf_pn532_fw_support_rfu;
43
static int hf_pn532_fw_support_iso_018092;
44
static int hf_pn532_fw_support_iso_iec_14443_type_b;
45
static int hf_pn532_fw_support_iso_iec_14443_type_a;
46
static int hf_pn532_14443a_uid;
47
static int hf_pn532_sam_mode;
48
static int hf_pn532_sam_timeout;
49
static int hf_pn532_sam_irq;
50
static int hf_pn532_config;
51
static int hf_pn532_config_not_used;
52
static int hf_pn532_config_auto_rfca;
53
static int hf_pn532_config_rf;
54
static int hf_pn532_config_rfu;
55
static int hf_pn532_config_atr_res_timeout;
56
static int hf_pn532_config_timeout_non_dep;
57
static int hf_pn532_config_max_rty_com;
58
static int hf_pn532_config_max_rty_atr;
59
static int hf_pn532_config_max_rty_psl;
60
static int hf_pn532_config_max_rty_passive_activation;
61
static int hf_pn532_afi;
62
static int hf_pn532_polling_method;
63
static int hf_pn532_config_ciu_rf_cfg;
64
static int hf_pn532_config_ciu_cw_gs_p;
65
static int hf_pn532_config_ciu_mod_gs_p;
66
static int hf_pn532_config_ciu_rx_threshold;
67
static int hf_pn532_config_ciu_demon_rf_on;
68
static int hf_pn532_config_ciu_demon_rf_off;
69
static int hf_pn532_config_ciu_gs_n_on;
70
static int hf_pn532_config_ciu_gs_n_off;
71
static int hf_pn532_config_ciu_mod_width;
72
static int hf_pn532_config_ciu_mif_nfc;
73
static int hf_pn532_config_ciu_tx_bit_phase;
74
static int hf_pn532_config_212_kbps;
75
static int hf_pn532_config_424_kbps;
76
static int hf_pn532_config_848_kbps;
77
static int hf_pn532_state;
78
static int hf_pn532_brit_nu_7;
79
static int hf_pn532_brit_speed_target;
80
static int hf_pn532_brit_nu_3;
81
static int hf_pn532_brit_speed_initiator;
82
static int hf_pn532_tg_response;
83
static int hf_pn532_initiator_command;
84
static int hf_pn532_data_in;
85
static int hf_pn532_data_out;
86
static int hf_pn532_gt;
87
static int hf_pn532_mode_nu_7;
88
static int hf_pn532_mode_nu_3_7;
89
static int hf_pn532_mode_picc_only;
90
static int hf_pn532_mode_dep_only;
91
static int hf_pn532_mode_passive_only;
92
static int hf_pn532_mode_mifare_parameters;
93
static int hf_pn532_mode_mifare_parameters_sens_res;
94
static int hf_pn532_mode_mifare_parameters_nfc_id_1t;
95
static int hf_pn532_mode_mifare_parameters_sel_res;
96
static int hf_pn532_mode_felica_parameters;
97
static int hf_pn532_mode_felica_parameters_nfc_id_2t;
98
static int hf_pn532_mode_felica_parameters_pad;
99
static int hf_pn532_mode_felica_parameters_system_code;
100
static int hf_pn532_mode_nfc_id_3t;
101
static int hf_pn532_mode_gt_length;
102
static int hf_pn532_mode_gt;
103
static int hf_pn532_mode_tk_length;
104
static int hf_pn532_mode_tk;
105
static int hf_pn532_mode_baudrate;
106
static int hf_pn532_mode_iso_iec_14443_4_picc;
107
static int hf_pn532_mode_dep;
108
static int hf_pn532_mode_framing_type;
109
static int hf_pn532_brit;
110
static int hf_pn532_brti;
111
static int hf_pn532_txmode_nu_7;
112
static int hf_pn532_txmode_tx_speed;
113
static int hf_pn532_txmode_nu_2_3;
114
static int hf_pn532_txmode_tx_framing;
115
static int hf_pn532_baudrate;
116
static int hf_pn532_flags;
117
static int hf_pn532_flags_rfu_7;
118
static int hf_pn532_flags_remove_preamble_and_postamble;
119
static int hf_pn532_flags_iso_14443_4_picc_emulation;
120
static int hf_pn532_flags_automatic_rats;
121
static int hf_pn532_flags_rfu_3;
122
static int hf_pn532_flags_automatic_atr_res;
123
static int hf_pn532_flags_did_used;
124
static int hf_pn532_flags_nad_used;
125
static int hf_pn532_target;
126
static int hf_pn532_wakeup_enable;
127
static int hf_pn532_generate_irq;
128
static int hf_pn532_register_address;
129
static int hf_pn532_register_value;
130
static int hf_pn532_field;
131
static int hf_pn532_brrx;
132
static int hf_pn532_brtx;
133
static int hf_pn532_type;
134
static int hf_pn532_sam_status;
135
static int hf_pn532_wakeup_enable_i2c;
136
static int hf_pn532_wakeup_enable_gpio;
137
static int hf_pn532_wakeup_enable_spi;
138
static int hf_pn532_wakeup_enable_hsu;
139
static int hf_pn532_wakeup_enable_rf_level_detector;
140
static int hf_pn532_wakeup_enable_rfu_2;
141
static int hf_pn532_wakeup_enable_int_1;
142
static int hf_pn532_wakeup_enable_int_0;
143
static int hf_pn532_gpio_ioi1;
144
static int hf_pn532_gpio_p3;
145
static int hf_pn532_gpio_p7;
146
static int hf_pn532_poll_number;
147
static int hf_pn532_period;
148
static int hf_pn532_autopoll_type;
149
static int hf_pn532_autopoll_type_act;
150
static int hf_pn532_autopoll_type_dep;
151
static int hf_pn532_autopoll_type_tcl;
152
static int hf_pn532_autopoll_type_mf_fe;
153
static int hf_pn532_autopoll_type_not_used;
154
static int hf_pn532_autopoll_type_baudrate_and_modulation;
155
static int hf_pn532_target_data;
156
static int hf_pn532_target_data_length;
157
static int hf_pn532_nfc_id_3i;
158
static int hf_pn532_gi;
159
static int hf_pn532_next_not_used_2_7;
160
static int hf_pn532_next_gi;
161
static int hf_pn532_next_nfc_id_3i;
162
static int hf_pn532_nfc_id_3t;
163
static int hf_pn532_activation_baudrate;
164
static int hf_pn532_communication_mode;
165
static int hf_pn532_jump_next_not_used_3_7;
166
static int hf_pn532_jump_next_passive_initiator_data;
167
static int hf_pn532_jump_next_gi;
168
static int hf_pn532_jump_next_nfc_id_3i;
169
static int hf_pn532_passive_initiator_data;
170
static int hf_pn532_did_target;
171
static int hf_pn532_send_bit_rate_target;
172
static int hf_pn532_receive_bit_rate_target;
173
static int hf_pn532_timeout;
174
static int hf_pn532_optional_parameters;
175
static int hf_pn532_test_number;
176
static int hf_pn532_parameters;
177
static int hf_pn532_parameters_length;
178
static int hf_pn532_sens_res;
179
static int hf_pn532_sel_res;
180
static int hf_pn532_nfc_id_length;
181
static int hf_pn532_nfc_id_1;
182
static int hf_pn532_ats_length;
183
static int hf_pn532_ats;
184
static int hf_pn532_pol_res_length;
185
static int hf_pn532_response_code;
186
static int hf_pn532_nfc_id_2t;
187
static int hf_pn532_pad;
188
static int hf_pn532_syst_code;
189
static int hf_pn532_atqb_response;
190
static int hf_pn532_attrib_res_length;
191
static int hf_pn532_attrib_res;
192
static int hf_pn532_jewel_id;
193
static int hf_pn532_response_for;
194
static int hf_pn532_diagnose_baudrate;
195
static int hf_pn532_reply_delay;
196
static int hf_pn532_ciu_tx_mode;
197
static int hf_pn532_ciu_rx_mode;
198
static int hf_pn532_diagnose_result;
199
static int hf_pn532_diagnose_number_of_fails;
200
static int hf_pn532_andet_bot;
201
static int hf_pn532_andet_up;
202
static int hf_pn532_andet_ith;
203
static int hf_pn532_andet_en;
204
205
static expert_field ei_unknown_data;
206
static expert_field ei_unexpected_data;
207
208
static wmem_tree_t *command_info;
209
210
static dissector_handle_t pn532_handle;
211
212
void proto_register_pn532(void);
213
void proto_reg_handoff_pn532(void);
214
215
0
#define DIAGNOSE_REQ               0x00
216
0
#define DIAGNOSE_RSP               0x01
217
0
#define GET_FIRMWARE_VERSION_REQ   0x02
218
0
#define GET_FIRMWARE_VERSION_RSP   0x03
219
0
#define GET_GENERAL_STATUS_REQ     0x04
220
0
#define GET_GENERAL_STATUS_RSP     0x05
221
0
#define READ_REGISTER_REQ          0x06
222
0
#define READ_REGISTER_RSP          0x07
223
0
#define WRITE_REGISTER_REQ         0x08
224
0
#define WRITE_REGISTER_RSP         0x09
225
0
#define READ_GPIO_REQ              0x0C
226
0
#define READ_GPIO_RSP              0x0D
227
0
#define WRITE_GPIO_REQ             0x0E
228
0
#define WRITE_GPIO_RSP             0x0F
229
0
#define SET_SERIAL_BAUD_RATE_REQ   0x10
230
0
#define SET_SERIAL_BAUD_RATE_RSP   0x11
231
0
#define SET_PARAMETERS_REQ         0x12
232
0
#define SET_PARAMETERS_RSP         0x13
233
0
#define SAM_CONFIGURATION_REQ      0x14
234
0
#define SAM_CONFIGURATION_RSP      0x15
235
0
#define POWER_DOWN_REQ             0x16
236
0
#define POWER_DOWN_RSP             0x17
237
0
#define RF_CONFIGURATION_REQ       0x32
238
0
#define RF_CONFIGURATION_RSP       0x33
239
0
#define IN_DATA_EXCHANGE_REQ       0x40
240
0
#define IN_DATA_EXCHANGE_RSP       0x41
241
0
#define IN_COMMUNICATE_THRU_REQ    0x42
242
0
#define IN_COMMUNICATE_THRU_RSP    0x43
243
0
#define IN_DESELECT_REQ            0x44
244
0
#define IN_DESELECT_RSP            0x45
245
0
#define IN_JUMP_FOR_PSL_REQ        0x46
246
0
#define IN_JUMP_FOR_PSL_RSP        0x47
247
0
#define IN_LIST_PASSIVE_TARGET_REQ 0x4A
248
0
#define IN_LIST_PASSIVE_TARGET_RSP 0x4B
249
0
#define IN_PSL_REQ                 0x4E
250
0
#define IN_PSL_RSP                 0x4F
251
0
#define IN_ATR_REQ                 0x50
252
0
#define IN_ATR_RSP                 0x51
253
0
#define IN_RELEASE_REQ             0x52
254
0
#define IN_RELEASE_RSP             0x53
255
0
#define IN_SELECT_REQ              0x54
256
0
#define IN_SELECT_RSP              0x55
257
0
#define IN_JUMP_FOR_DEP_REQ        0x56
258
0
#define IN_JUMP_FOR_DEP_RSP        0x57
259
0
#define RF_REGULATION_TEST_REQ     0x58
260
0
#define RF_REGULATION_TEST_RSP     0x59
261
0
#define IN_AUTO_POLL_REQ           0x60
262
0
#define IN_AUTO_POLL_RSP           0x61
263
0
#define TG_GET_DATA_REQ            0x86
264
0
#define TG_GET_DATA_RSP            0x87
265
0
#define TG_GET_INITIATOR_CMD_REQ   0x88
266
0
#define TG_GET_INITIATOR_CMD_RSP   0x89
267
0
#define TG_GET_TARGET_STATUS_REQ   0x8A
268
0
#define TG_GET_TARGET_STATUS_RSP   0x8B
269
0
#define TG_INIT_AS_TARGET_REQ      0x8C
270
0
#define TG_INIT_AS_TARGET_RSP      0x8D
271
0
#define TG_SET_DATA_REQ            0x8E
272
0
#define TG_SET_DATA_RSP            0x8F
273
0
#define TG_RESP_TO_INITIATOR_REQ   0x90
274
0
#define TG_RESP_TO_INITIATOR_RSP   0x91
275
0
#define TG_SET_GENERAL_BYTES_REQ   0x92
276
0
#define TG_SET_GENERAL_BYTES_RSP   0x93
277
0
#define TG_SET_METADATA_REQ        0x94
278
0
#define TG_SET_METADATA_RSP        0x95
279
280
/* Baud rate and modulation types */
281
0
#define ISO_IEC_14443A_106         0x00
282
0
#define FELICA_212                 0x01
283
0
#define FELICA_424                 0x02
284
0
#define ISO_IEC_14443B_106         0x03
285
0
#define JEWEL_14443A_106           0x04
286
287
288
/* Table of payload types - adapted from the I2C dissector */
289
enum {
290
    SUB_DATA = 0,
291
    SUB_FELICA,
292
    SUB_MIFARE,
293
    SUB_ISO7816,
294
    SUB_MAX
295
};
296
297
typedef struct command_data_t {
298
    uint32_t bus_id;
299
    uint32_t device_address;
300
    uint32_t endpoint;
301
302
    uint8_t  command;
303
    uint32_t command_frame_number;
304
    uint32_t response_frame_number;
305
    union {
306
        int16_t test_number;
307
        int16_t baudrate;
308
    } data;
309
} command_data_t;
310
311
static dissector_handle_t sub_handles[SUB_MAX];
312
static int sub_selected = SUB_DATA;
313
314
/* Subtree handles: set by register_subtree_array */
315
static int ett_pn532;
316
static int ett_pn532_flags;
317
static int ett_pn532_target;
318
static int ett_pn532_fw_support;
319
static int ett_pn532_config_212_kbps;
320
static int ett_pn532_config_424_kbps;
321
static int ett_pn532_config_848_kbps;
322
static int ett_pn532_mifare_parameters;
323
static int ett_pn532_felica_parameters;
324
static int ett_pn532_wakeup_enable;
325
static int ett_pn532_autopoll_type;
326
327
/* Re-arranged from defs above to be in ascending order by value */
328
static const value_string pn532_commands[] = {
329
    {DIAGNOSE_REQ,               "Diagnose"},
330
    {DIAGNOSE_RSP,               "Diagnose (Response)"},
331
    {GET_FIRMWARE_VERSION_REQ,   "GetFirmwareVersion"},
332
    {GET_FIRMWARE_VERSION_RSP,   "GetFirmwareVersion (Response)"},
333
    {GET_GENERAL_STATUS_REQ,     "GetGeneralStatus"},
334
    {GET_GENERAL_STATUS_RSP,     "GetGeneralStatus (Response)"},
335
    {READ_REGISTER_REQ,          "ReadRegister"},
336
    {READ_REGISTER_RSP,          "ReadRegister (Response)"},
337
    {WRITE_REGISTER_REQ,         "WriteRegister"},
338
    {WRITE_REGISTER_RSP,         "WriteRegister (Response)"},
339
    {READ_GPIO_REQ,              "ReadGPIO"},
340
    {READ_GPIO_RSP,              "ReadGPIO (Response)"},
341
    {WRITE_GPIO_REQ,             "WriteGPIO"},
342
    {WRITE_GPIO_RSP,             "WriteGPIO (Response)"},
343
    {SET_SERIAL_BAUD_RATE_REQ,   "SetSerialBaudRate"},
344
    {SET_SERIAL_BAUD_RATE_RSP,   "SetSerialBaudRate (Response)"},
345
    {SET_PARAMETERS_REQ,         "SetParameters"},
346
    {SET_PARAMETERS_RSP,         "SetParameters (Response)"},
347
    {SAM_CONFIGURATION_REQ,      "SAMConfiguration"},
348
    {SAM_CONFIGURATION_RSP,      "SAMConfiguration (Response)"},
349
    {POWER_DOWN_REQ,             "PowerDown"},
350
    {POWER_DOWN_RSP,             "PowerDown (Response)"},
351
    {RF_CONFIGURATION_REQ,       "RFConfiguration"},
352
    {RF_CONFIGURATION_RSP,       "RFConfiguration (Response)"},
353
    {IN_DATA_EXCHANGE_REQ,       "InDataExchange"},
354
    {IN_DATA_EXCHANGE_RSP,       "InDataExchange (Response)"},
355
    {IN_COMMUNICATE_THRU_REQ,    "InCommunicateThru"},
356
    {IN_COMMUNICATE_THRU_RSP,    "InCommunicateThru (Response)"},
357
    {IN_DESELECT_REQ,            "InDeselect"},
358
    {IN_DESELECT_RSP,            "InDeselect (Response)"},
359
    {IN_JUMP_FOR_PSL_REQ,        "InJumpForPSL"},
360
    {IN_JUMP_FOR_PSL_RSP,        "InJumpForPSL (Response)"},
361
    {IN_LIST_PASSIVE_TARGET_REQ, "InListPassiveTarget"},
362
    {IN_LIST_PASSIVE_TARGET_RSP, "InListPassiveTarget (Response)"},
363
    {IN_PSL_REQ,                 "InPSL"},
364
    {IN_PSL_RSP,                 "InPSL (Response)"},
365
    {IN_ATR_REQ,                 "InATR"},
366
    {IN_ATR_RSP,                 "InATR (Response)"},
367
    {IN_RELEASE_REQ,             "InRelease"},
368
    {IN_RELEASE_RSP,             "InRelease (Response)"},
369
    {IN_SELECT_REQ,              "InSelect"},
370
    {IN_SELECT_RSP,              "InSelect (Response)"},
371
    {IN_JUMP_FOR_DEP_REQ,        "InJumpForDEP"},
372
    {IN_JUMP_FOR_DEP_RSP,        "InJumpForDEP (Response)"},
373
    {RF_REGULATION_TEST_REQ,     "RFRegulationTest"},
374
    {RF_REGULATION_TEST_RSP,     "RFRegulationTest (Response)"},
375
    {IN_AUTO_POLL_REQ,           "InAutoPoll"},
376
    {IN_AUTO_POLL_RSP,           "InAutoPoll (Response)"},
377
    {TG_GET_DATA_REQ,            "TgGetData"},
378
    {TG_GET_DATA_RSP,            "TgGetData (Response)"},
379
    {TG_GET_INITIATOR_CMD_REQ,   "TgGetInitiatorCommand"},
380
    {TG_GET_INITIATOR_CMD_RSP,   "TgGetInitiatorCommand (Response)"},
381
    {TG_GET_TARGET_STATUS_REQ,   "TgGetTargetStatus"},
382
    {TG_GET_TARGET_STATUS_RSP,   "TgGetTargetStatus (Response)"},
383
    {TG_INIT_AS_TARGET_REQ,      "TgInitAsTarget"},
384
    {TG_INIT_AS_TARGET_RSP,      "TgInitAsTarget (Response)"},
385
    {TG_SET_DATA_REQ,            "TgSetData"},
386
    {TG_SET_DATA_RSP,            "TgSetData (Response)"},
387
    {TG_RESP_TO_INITIATOR_REQ,   "TgResponseToInitiator"},
388
    {TG_RESP_TO_INITIATOR_RSP,   "TgResponseToInitiator (Response)"},
389
    {TG_SET_GENERAL_BYTES_REQ,   "TgSetGeneralBytes"},
390
    {TG_SET_GENERAL_BYTES_RSP,   "TgSetGeneralBytes (Response)"},
391
    {TG_SET_METADATA_REQ,        "TgSetMetaData"},
392
    {TG_SET_METADATA_RSP,        "TgSetMetaData (Response)"},
393
    {0x00, NULL}
394
};
395
static value_string_ext pn532_commands_ext = VALUE_STRING_EXT_INIT(pn532_commands);
396
397
/* TFI - 1 byte frame identifier; specifying direction of communication */
398
static const value_string pn532_directions[] = {
399
    {0xD4,  "Host to PN532"},
400
    {0xD5,  "PN532 to Host"},
401
    {0x00, NULL}
402
};
403
404
static const value_string pn532_errors[] = {
405
    {0x00,  "No Error"},
406
    {0x01,  "Time Out"},
407
    {0x02,  "CRC Error detected by the CIU"},
408
    {0x03,  "Parity Error detected by the CIU"},
409
    {0x04,  "Erroneous Bit Count has been detected"},
410
    {0x05,  "Framing error during Mifare operation"},
411
    {0x06,  "Abnormal Bit-Collision"},
412
    {0x07,  "Communication Buffer Size Insufficient"},
413
    {0x09,  "RF Buffer overflow has been detected by the CIU"},
414
    {0x0A,  "In active communication mode, the RF field has not been switched on in time by the counterpart"},
415
    {0x0B,  "RF Protocol Error"},
416
    {0x0D,  "Temperature Error"},
417
    {0x0E,  "Internal Buffer Overflow"},
418
    {0x10,  "Invalid Parameter"},
419
    {0x12,  "The PN532 configured in target mode does not support the command received from the initiator"},
420
    {0x13,  "Invalid Data Format"},
421
    {0x14,  "Authentication Error"},
422
    {0x23,  "UID Check Byte is Wrong"},
423
    {0x25,  "Invalid Device State"},
424
    {0x26,  "Operation not allowed in this configuration"},
425
    {0x27,  "Unacceptable Command"},
426
    {0x29,  "The PN532 configured as target has been released by its initiator"},
427
    {0x2A,  "ID of the card does not match"},
428
    {0x2B,  "Card previously activated has disappeared"},
429
    {0x2C,  "Mismatch between the NFCID3 initiator and the NFCID3 target in DEP 212/424 kbps passive"},
430
    {0x2D,  "Over-current event has been detected"},
431
    {0x2E,  "NAD missing in DEP frame"},
432
    {0x00, NULL}
433
};
434
435
static const value_string pn532_config_vals[] = {
436
    {0x01,  "RF Field"},
437
    {0x02,  "Various Timings"},
438
    {0x04,  "Max Rty COM"},
439
    {0x05,  "Max Retries"},
440
    {0x0A,  "Analog settings for the baudrate 106 kbps type A"},
441
    {0x0B,  "Analog settings for the baudrate 212/424 kbps"},
442
    {0x0C,  "Analog settings for the type B"},
443
    {0x0D,  "Analog settings for baudrates 212/424 and 848 kbps with ISO/IEC14443-4 protocol"},
444
    {0x00, NULL}
445
};
446
447
static const value_string pn532_config_timeout_vals[] = {
448
    {0x00,  "No Timeout"},
449
    {0x01,  "100 us"},
450
    {0x02,  "200 us"},
451
    {0x03,  "400 us"},
452
    {0x04,  "800 us"},
453
    {0x05,  "1.6 ms"},
454
    {0x06,  "3.2 ms"},
455
    {0x07,  "6.4 ms"},
456
    {0x08,  "12.8 ms"},
457
    {0x09,  "25.6 ms"},
458
    {0x0A,  "51.2 ms"},
459
    {0x0B,  "102.4 ms"},
460
    {0x0C,  "204.8 ms"},
461
    {0x0D,  "409.6 ms"},
462
    {0x0E,  "819.2 ms"},
463
    {0x0F,  "1.64 sec"},
464
    {0x10,  "3.28 sec"},
465
    {0x00, NULL}
466
};
467
468
static const value_string pn532_polling_method_vals[] = {
469
    {0x00,  "Timeslot Approach"},
470
    {0x01,  "Probabilistic Approach"},
471
    {0x00, NULL}
472
};
473
474
/* Baud rates and modulation types */
475
static const value_string pn532_brtypes[] = {
476
    {ISO_IEC_14443A_106,        "ISO/IEC 14443-A at 106 kbps"},
477
    {FELICA_212,                "FeliCa at 212 kbps"},
478
    {FELICA_424,                "FeliCa at 424 kbps"},
479
    {ISO_IEC_14443B_106,        "ISO/IEC 14443-B at 106 kbps"},
480
    {JEWEL_14443A_106,          "InnoVision Jewel/Topaz at 106 kbps"},
481
    {0x00, NULL}
482
};
483
484
/* SAM Modes */
485
static const value_string pn532_sam_modes[] = {
486
    {0x01,  "Normal Mode"},
487
    {0x02,  "Virtual Card Mode"},
488
    {0x03,  "Wired Card Mode"},
489
    {0x04,  "Dual Card Mode"},
490
    {0x00, NULL}
491
};
492
493
static const value_string pn532_state_vals[] = {
494
    {0x00,  "TG Idle / TG Released"},
495
    {0x01,  "TG Activated"},
496
    {0x02,  "TG Deselected"},
497
    {0x80,  "PICC Released"},
498
    {0x81,  "PICC Activated"},
499
    {0x82,  "PICC Deselected"},
500
    {0x00, NULL}
501
};
502
503
static const value_string pn532_speed_vals[] = {
504
    {0x00,  "106 kbps"},
505
    {0x01,  "212 kbps"},
506
    {0x02,  "424 kbps"},
507
    {0x00, NULL}
508
};
509
510
static const value_string pn532_framing_type_vals[] = {
511
    {0x00,  "Mifare"},
512
    {0x01,  "Active Mode"},
513
    {0x02,  "FeliCa"},
514
    {0x00, NULL}
515
};
516
517
static const value_string pn532_txspeed_vals[] = {
518
    {0x00,  "106 kbps"},
519
    {0x01,  "212 kbps"},
520
    {0x02,  "424 kbps"},
521
    {0x03,  "848 kbps"},
522
    {0x00, NULL}
523
};
524
525
static const value_string pn532_txframing_vals[] = {
526
    {0x00,  "Mifare"},
527
    {0x02,  "FeliCa"},
528
    {0x00, NULL}
529
};
530
531
static const value_string pn532_baudrate_vals[] = {
532
    {0x00,  "9.6 kbaud"},
533
    {0x01,  "19.2 kbaud"},
534
    {0x02,  "38.4 kbaud"},
535
    {0x03,  "57.6 kbaud"},
536
    {0x04,  "115.2 kbaud"},
537
    {0x05,  "230.4 kbaud"},
538
    {0x06,  "460.8 kbaud"},
539
    {0x07,  "921.6 kbaud"},
540
    {0x08,  "1.288 Mbaud"},
541
    {0x00, NULL}
542
};
543
544
static const value_string pn532_type_vals[] = {
545
    {0x00,  "Mifare, ISO/IEC14443-3 Type A, ISO/IEC14443-3 Type B, ISO/IEC18092 passive 106 kbps"},
546
    {0x01,  "ISO/IEC18092 Active Mode"},
547
    {0x02,  "Innovision Jewel Tag"},
548
    {0x10,  "FeliCa, ISO/IEC18092 passive 212/424 kbps"},
549
    {0x00, NULL}
550
};
551
552
static const value_string pn532_communication_mode_vals[] = {
553
    {0x00,  "Passive Mode"},
554
    {0x01,  "Active Mode"},
555
    {0x00, NULL}
556
};
557
558
static const value_string pn532_test_number_vals[] = {
559
    {0x00,  "Communication Line Test"},
560
    {0x01,  "ROM Test"},
561
    {0x02,  "RAM Test"},
562
    {0x04,  "Polling Test to Target"},
563
    {0x05,  "Echo Back Test"},
564
    {0x06,  "Attention Request Test or ISO/IEC14443-4 card presence detection"},
565
    {0x07,  "Self Antenna Test"},
566
    {0x00, NULL}
567
};
568
569
static const value_string pn532_diagnose_baudrate_vals[] = {
570
    {0x01,  "212 kbps"},
571
    {0x02,  "424 kbps"},
572
    {0x00, NULL}
573
};
574
575
0
static void sam_timeout_base(char* buf, uint32_t value) {
576
0
    if (value == 0x00) {
577
0
        snprintf(buf, ITEM_LABEL_LENGTH, "No timeout control");
578
0
    } else if (0x01 <= value && value <= 0x13) {
579
0
        snprintf(buf, ITEM_LABEL_LENGTH, "%u ms", value * 50);
580
0
    } else {
581
0
        snprintf(buf, ITEM_LABEL_LENGTH, "%u.%03u s", value * 50 / 1000, value * 50 % 1000);
582
0
    }
583
0
}
584
585
0
static void replay_delay_base(char* buf, uint32_t value) {
586
0
        snprintf(buf, ITEM_LABEL_LENGTH, "%u.%03u s", value * 500 / 1000, value * 500 % 1000);
587
0
}
588
589
static int
590
dissect_status(proto_tree *tree, tvbuff_t *tvb, int offset)
591
0
{
592
0
    proto_tree_add_item(tree, hf_pn532_status_nad_present, tvb, offset, 1, ENC_BIG_ENDIAN);
593
0
    proto_tree_add_item(tree, hf_pn532_status_mi, tvb, offset, 1, ENC_BIG_ENDIAN);
594
0
    proto_tree_add_item(tree, hf_pn532_status_error_code, tvb, offset, 1, ENC_BIG_ENDIAN);
595
596
0
    return offset + 1;
597
0
}
598
599
static int
600
dissect_pn532(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree, void *data)
601
0
{
602
0
    proto_item *item;
603
0
    proto_tree *pn532_tree;
604
0
    proto_item *sub_item;
605
0
    proto_tree *sub_tree;
606
0
    proto_item *next_item;
607
0
    proto_tree *next_tree;
608
0
    uint8_t     cmd;
609
0
    uint8_t     config;
610
0
    int16_t     baudrate;
611
0
    int16_t     test_number;
612
0
    uint8_t     length;
613
0
    uint8_t     value;
614
0
    uint8_t     type;
615
0
    uint8_t     item_value;
616
0
    tvbuff_t   *next_tvb;
617
0
    int         offset = 0;
618
0
    command_data_t  *command_data = NULL;
619
0
    urb_info_t      *urb;
620
0
    wmem_tree_key_t  key[5];
621
0
    uint32_t         bus_id;
622
0
    uint32_t         device_address;
623
0
    uint32_t         endpoint;
624
0
    uint32_t         k_bus_id;
625
0
    uint32_t         k_device_address;
626
0
    uint32_t         k_endpoint;
627
0
    uint32_t         k_frame_number;
628
629
    /* Reject the packet if data is NULL */
630
0
    if (data == NULL)
631
0
        return 0;
632
0
    urb = (urb_info_t *)data;
633
634
0
    col_set_str(pinfo->cinfo, COL_PROTOCOL, "PN532");
635
636
0
    item = proto_tree_add_item(tree, proto_pn532, tvb, 0, -1, ENC_NA);
637
0
    pn532_tree = proto_item_add_subtree(item, ett_pn532);
638
639
0
    proto_tree_add_item(pn532_tree, hf_pn532_direction, tvb, offset, 1, ENC_NA);
640
0
    offset += 1;
641
642
0
    proto_tree_add_item(pn532_tree, hf_pn532_command, tvb, offset, 1, ENC_NA);
643
0
    cmd = tvb_get_uint8(tvb, offset);
644
0
    offset += 1;
645
646
0
    col_set_str(pinfo->cinfo, COL_INFO, val_to_str_ext_const(cmd, &pn532_commands_ext, "Unknown command"));
647
648
0
    bus_id = urb->bus_id;
649
0
    device_address = urb->device_address;
650
0
    endpoint = urb->endpoint;
651
652
0
    k_bus_id          = bus_id;
653
0
    k_device_address  = device_address;
654
0
    k_endpoint        = endpoint;
655
0
    k_frame_number    = pinfo->num;
656
657
0
    key[0].length = 1;
658
0
    key[0].key = &k_bus_id;
659
0
    key[1].length = 1;
660
0
    key[1].key = &k_device_address;
661
0
    key[2].length = 1;
662
0
    key[2].key = &k_endpoint;
663
0
    key[3].length = 1;
664
0
    key[3].key = &k_frame_number;
665
0
    key[4].length = 0;
666
0
    key[4].key = NULL;
667
668
0
    if (!pinfo->fd->visited && !(cmd & 0x01)) {
669
0
        command_data = wmem_new(wmem_file_scope(), command_data_t);
670
0
        command_data->bus_id = bus_id;
671
0
        command_data->device_address = device_address;
672
0
        command_data->endpoint = endpoint;
673
674
0
        command_data->command = cmd;
675
0
        command_data->command_frame_number = pinfo->num;
676
0
        command_data->response_frame_number = 0;
677
678
0
        wmem_tree_insert32_array(command_info, key, command_data);
679
680
0
        k_bus_id          = bus_id;
681
0
        k_device_address  = device_address;
682
0
        k_endpoint        = endpoint;
683
0
        k_frame_number    = pinfo->num;
684
685
0
        key[0].length = 1;
686
0
        key[0].key = &k_bus_id;
687
0
        key[1].length = 1;
688
0
        key[1].key = &k_device_address;
689
0
        key[2].length = 1;
690
0
        key[2].key = &k_endpoint;
691
0
        key[3].length = 1;
692
0
        key[3].key = &k_frame_number;
693
0
        key[4].length = 0;
694
0
        key[4].key = NULL;
695
0
    }
696
697
0
    if (cmd & 0x01) {
698
0
        wmem_tree_t  *wmem_tree;
699
700
0
        key[3].length = 0;
701
0
        key[3].key = NULL;
702
703
0
        wmem_tree = (wmem_tree_t *) wmem_tree_lookup32_array(command_info, key);
704
0
        if (wmem_tree) {
705
0
            command_data = (command_data_t *) wmem_tree_lookup32_le(wmem_tree, pinfo->num);
706
707
0
            if (command_data && (command_data->response_frame_number == 0 ||
708
0
                    command_data->response_frame_number == pinfo->num)) {
709
710
0
                if (!pinfo->fd->visited && command_data->response_frame_number == 0) {
711
0
                    command_data->response_frame_number = pinfo->num;
712
0
                }
713
714
0
            }
715
0
        }
716
717
0
        if (command_data) {
718
0
            sub_item = proto_tree_add_uint(pn532_tree, hf_pn532_response_for, tvb, offset, tvb_captured_length_remaining(tvb, offset), command_data->command_frame_number);
719
0
            proto_item_set_generated(sub_item);
720
0
        }
721
0
    }
722
723
0
    switch (cmd) {
724
725
0
    case DIAGNOSE_REQ:
726
0
        proto_tree_add_item(pn532_tree, hf_pn532_test_number, tvb, offset, 1, ENC_NA);
727
0
        test_number = tvb_get_uint8(tvb, offset);
728
0
        offset += 1;
729
730
0
        if (command_data)
731
0
            command_data->data.test_number = test_number;
732
733
0
        proto_tree_add_item(pn532_tree, hf_pn532_parameters_length, tvb, offset, 1, ENC_NA);
734
0
        length = tvb_get_uint8(tvb, offset);
735
0
        offset += 1;
736
737
0
        switch (test_number) {
738
0
        case 0x00:
739
0
            proto_tree_add_item(pn532_tree, hf_pn532_data_in, tvb, offset, length, ENC_NA);
740
0
            offset += length;
741
0
            break;
742
0
        case 0x04:
743
0
            proto_tree_add_item(pn532_tree, hf_pn532_diagnose_baudrate, tvb, offset, 1, ENC_NA);
744
0
            offset += 1;
745
0
            break;
746
0
        case 0x05:
747
0
            proto_tree_add_item(pn532_tree, hf_pn532_reply_delay, tvb, offset, 1, ENC_NA);
748
0
            offset += 1;
749
750
0
            proto_tree_add_item(pn532_tree, hf_pn532_ciu_tx_mode, tvb, offset, 1, ENC_NA);
751
0
            offset += 1;
752
753
0
            proto_tree_add_item(pn532_tree, hf_pn532_ciu_rx_mode, tvb, offset, 1, ENC_NA);
754
0
            offset += 1;
755
0
            break;
756
0
        case 0x07:
757
0
            proto_tree_add_item(pn532_tree, hf_pn532_andet_bot, tvb, offset, 1, ENC_NA);
758
0
            proto_tree_add_item(pn532_tree, hf_pn532_andet_up,  tvb, offset, 1, ENC_NA);
759
0
            proto_tree_add_item(pn532_tree, hf_pn532_andet_ith, tvb, offset, 1, ENC_NA);
760
0
            proto_tree_add_item(pn532_tree, hf_pn532_andet_en,  tvb, offset, 1, ENC_NA);
761
0
            offset += 1;
762
0
            break;
763
0
        case 0x01:
764
0
        case 0x02:
765
0
        case 0x06:
766
            /* No parameters */
767
0
            break;
768
769
0
        default:
770
0
            proto_tree_add_item(pn532_tree, hf_pn532_parameters, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
771
0
            offset += tvb_captured_length_remaining(tvb, offset);
772
0
        }
773
0
        break;
774
775
0
    case DIAGNOSE_RSP:
776
0
        if (command_data && command_data->command == DIAGNOSE_REQ)
777
0
            test_number = command_data->data.test_number;
778
0
        else
779
0
            test_number = -1; /* Force unknown test_number */
780
781
0
        if (tvb_reported_length_remaining(tvb, offset) >= 1) {
782
0
            proto_tree_add_item(pn532_tree, hf_pn532_parameters_length, tvb, offset, 1, ENC_NA);
783
0
            offset += 1;
784
785
0
            switch (test_number) {
786
0
            case 0x00:
787
0
                proto_tree_add_item(pn532_tree, hf_pn532_test_number, tvb, offset, 1, ENC_NA);
788
0
                offset += 1;
789
790
0
                proto_tree_add_item(pn532_tree, hf_pn532_parameters_length, tvb, offset, 1, ENC_NA);
791
0
                length = tvb_captured_length_remaining(tvb, offset);
792
0
                offset += 1;
793
794
0
                proto_tree_add_item(pn532_tree, hf_pn532_data_out, tvb, offset, length, ENC_NA);
795
0
                offset += length;
796
0
                break;
797
0
            case 0x01:
798
0
            case 0x02:
799
0
            case 0x06:
800
0
            case 0x07:
801
0
                proto_tree_add_item(pn532_tree, hf_pn532_diagnose_result, tvb, offset, 1, ENC_NA);
802
0
                offset += 1;
803
0
                break;
804
0
            case 0x04:
805
0
                proto_tree_add_item(pn532_tree, hf_pn532_diagnose_number_of_fails, tvb, offset, 1, ENC_NA);
806
0
                offset += 1;
807
0
                break;
808
0
            case 0x05:
809
                /* Not possible; test 0x05 runs infinitely */
810
0
                break;
811
0
            default:
812
0
                proto_tree_add_item(pn532_tree, hf_pn532_parameters, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
813
0
                offset += tvb_captured_length_remaining(tvb, offset);
814
0
            }
815
0
        }
816
0
        break;
817
818
0
    case GET_FIRMWARE_VERSION_REQ:
819
        /* No parameters */
820
0
        break;
821
822
0
    case GET_FIRMWARE_VERSION_RSP:
823
0
        proto_tree_add_item(pn532_tree, hf_pn532_ic_version, tvb, offset, 1, ENC_NA);
824
0
        offset += 1;
825
826
0
        proto_tree_add_item(pn532_tree, hf_pn532_fw_version, tvb, offset, 1, ENC_NA);
827
0
        offset += 1;
828
829
0
        proto_tree_add_item(pn532_tree, hf_pn532_fw_revision, tvb, offset, 1, ENC_NA);
830
0
        offset += 1;
831
832
0
        sub_item = proto_tree_add_item(pn532_tree, hf_pn532_fw_support, tvb, offset, 1, ENC_NA);
833
0
        sub_tree = proto_item_add_subtree(sub_item, ett_pn532_fw_support);
834
0
        proto_tree_add_item(sub_tree, hf_pn532_fw_support_rfu, tvb, offset, 1, ENC_NA);
835
0
        proto_tree_add_item(sub_tree, hf_pn532_fw_support_iso_018092, tvb, offset, 1, ENC_NA);
836
0
        proto_tree_add_item(sub_tree, hf_pn532_fw_support_iso_iec_14443_type_b, tvb, offset, 1, ENC_NA);
837
0
        proto_tree_add_item(sub_tree, hf_pn532_fw_support_iso_iec_14443_type_a, tvb, offset, 1, ENC_NA);
838
0
        offset += 1;
839
0
        break;
840
841
0
    case GET_GENERAL_STATUS_REQ:
842
        /* No parameters */
843
0
        break;
844
845
0
    case GET_GENERAL_STATUS_RSP:
846
0
        proto_tree_add_item(pn532_tree, hf_pn532_error, tvb, offset, 1, ENC_BIG_ENDIAN);
847
0
        offset += 1;
848
849
0
        proto_tree_add_item(pn532_tree, hf_pn532_field, tvb, offset, 1, ENC_BIG_ENDIAN);
850
0
        offset += 1;
851
852
0
        proto_tree_add_item(pn532_tree, hf_pn532_NbTg, tvb, offset, 1, ENC_BIG_ENDIAN);
853
0
        value = tvb_get_uint8(tvb, offset);
854
0
        offset += 1;
855
856
0
        for (item_value = 1; item_value <= value; item_value += 1) {
857
0
            sub_item = proto_tree_add_item(pn532_tree, hf_pn532_target, tvb, offset, 4, ENC_NA);
858
0
            sub_tree = proto_item_add_subtree(sub_item, ett_pn532_target);
859
0
            proto_item_append_text(sub_item, " %u/%u", item_value, value);
860
861
0
            proto_tree_add_item(sub_tree, hf_pn532_Tg, tvb, offset, 1, ENC_BIG_ENDIAN);
862
0
            offset += 1;
863
864
0
            proto_tree_add_item(sub_tree, hf_pn532_brrx, tvb, offset, 1, ENC_BIG_ENDIAN);
865
0
            offset += 1;
866
867
0
            proto_tree_add_item(sub_tree, hf_pn532_brtx, tvb, offset, 1, ENC_BIG_ENDIAN);
868
0
            offset += 1;
869
870
0
            proto_tree_add_item(sub_tree, hf_pn532_type, tvb, offset, 1, ENC_BIG_ENDIAN);
871
0
            offset += 1;
872
0
        }
873
874
0
        proto_tree_add_item(pn532_tree, hf_pn532_sam_status, tvb, offset, 1, ENC_BIG_ENDIAN);
875
0
        offset += 1;
876
877
0
        break;
878
879
0
    case READ_REGISTER_REQ:
880
0
        while (tvb_reported_length_remaining(tvb, offset) >= 2) {
881
0
            proto_tree_add_item(pn532_tree, hf_pn532_register_address, tvb, offset, 2, ENC_BIG_ENDIAN);
882
0
            offset += 2;
883
0
        }
884
0
        break;
885
886
0
    case READ_REGISTER_RSP:
887
0
        while (tvb_reported_length_remaining(tvb, offset) >= 1) {
888
0
            proto_tree_add_item(pn532_tree, hf_pn532_register_value, tvb, offset, 1, ENC_BIG_ENDIAN);
889
0
            offset += 1;
890
0
        }
891
0
        break;
892
893
0
    case WRITE_REGISTER_REQ:
894
0
        while (tvb_reported_length_remaining(tvb, offset) >= 3) {
895
0
            proto_tree_add_item(pn532_tree, hf_pn532_register_address, tvb, offset, 2, ENC_BIG_ENDIAN);
896
0
            offset += 2;
897
898
0
            proto_tree_add_item(pn532_tree, hf_pn532_register_value, tvb, offset, 1, ENC_BIG_ENDIAN);
899
0
            offset += 1;
900
0
        }
901
0
        break;
902
903
0
    case WRITE_REGISTER_RSP:
904
        /* No parameters */
905
0
        break;
906
907
0
    case READ_GPIO_REQ:
908
        /* No parameters */
909
0
        break;
910
911
0
    case READ_GPIO_RSP:
912
0
        proto_tree_add_item(pn532_tree, hf_pn532_gpio_p3, tvb, offset, 1, ENC_BIG_ENDIAN);
913
0
        offset += 1;
914
915
0
        proto_tree_add_item(pn532_tree, hf_pn532_gpio_p7, tvb, offset, 1, ENC_BIG_ENDIAN);
916
0
        offset += 1;
917
918
0
        proto_tree_add_item(pn532_tree, hf_pn532_gpio_ioi1, tvb, offset, 1, ENC_BIG_ENDIAN);
919
0
        offset += 1;
920
0
        break;
921
922
0
    case WRITE_GPIO_REQ:
923
0
        proto_tree_add_item(pn532_tree, hf_pn532_gpio_p3, tvb, offset, 1, ENC_BIG_ENDIAN);
924
0
        offset += 1;
925
926
0
        proto_tree_add_item(pn532_tree, hf_pn532_gpio_p7, tvb, offset, 1, ENC_BIG_ENDIAN);
927
0
        offset += 1;
928
0
        break;
929
930
0
    case WRITE_GPIO_RSP:
931
        /* No parameters */
932
0
        break;
933
934
0
    case SET_SERIAL_BAUD_RATE_REQ:
935
0
        proto_tree_add_item(pn532_tree, hf_pn532_baudrate, tvb, offset, 1, ENC_BIG_ENDIAN);
936
0
        offset += 1;
937
0
        break;
938
939
0
    case SET_SERIAL_BAUD_RATE_RSP:
940
        /* No parameters */
941
0
        break;
942
943
0
    case SET_PARAMETERS_REQ:
944
0
        sub_item = proto_tree_add_item(pn532_tree, hf_pn532_flags, tvb, offset, 1, ENC_NA);
945
0
        sub_tree = proto_item_add_subtree(sub_item, ett_pn532_flags);
946
947
0
        proto_tree_add_item(sub_tree, hf_pn532_flags_rfu_7, tvb, offset, 1, ENC_BIG_ENDIAN);
948
0
        proto_tree_add_item(sub_tree, hf_pn532_flags_remove_preamble_and_postamble, tvb, offset, 1, ENC_BIG_ENDIAN);
949
0
        proto_tree_add_item(sub_tree, hf_pn532_flags_iso_14443_4_picc_emulation, tvb, offset, 1, ENC_BIG_ENDIAN);
950
0
        proto_tree_add_item(sub_tree, hf_pn532_flags_automatic_rats, tvb, offset, 1, ENC_BIG_ENDIAN);
951
0
        proto_tree_add_item(sub_tree, hf_pn532_flags_rfu_3, tvb, offset, 1, ENC_BIG_ENDIAN);
952
0
        proto_tree_add_item(sub_tree, hf_pn532_flags_automatic_atr_res, tvb, offset, 1, ENC_BIG_ENDIAN);
953
0
        proto_tree_add_item(sub_tree, hf_pn532_flags_did_used, tvb, offset, 1, ENC_BIG_ENDIAN);
954
0
        proto_tree_add_item(sub_tree, hf_pn532_flags_nad_used, tvb, offset, 1, ENC_BIG_ENDIAN);
955
0
        offset += 1;
956
0
        break;
957
958
0
    case SET_PARAMETERS_RSP:
959
        /* No parameters */
960
0
        break;
961
962
0
    case SAM_CONFIGURATION_REQ: /* Secure Application/Security Access Module Configuration Request */
963
0
        proto_tree_add_item(pn532_tree, hf_pn532_sam_mode, tvb, offset, 1, ENC_BIG_ENDIAN);
964
0
        offset += 1;
965
966
0
        proto_tree_add_item(pn532_tree, hf_pn532_sam_timeout, tvb, offset, 1, ENC_BIG_ENDIAN);
967
0
        offset += 1;
968
969
0
        if (tvb_reported_length_remaining(tvb, offset) >= 1) {
970
0
            proto_tree_add_item(pn532_tree, hf_pn532_sam_irq, tvb, offset, 1, ENC_BIG_ENDIAN);
971
0
            offset += 1;
972
0
        }
973
0
        break;
974
975
0
    case SAM_CONFIGURATION_RSP:
976
        /* No parameters */
977
0
        break;
978
979
0
    case POWER_DOWN_REQ:
980
0
        sub_item = proto_tree_add_item(pn532_tree, hf_pn532_wakeup_enable, tvb, offset, 1, ENC_NA);
981
0
        sub_tree = proto_item_add_subtree(sub_item, ett_pn532_wakeup_enable);
982
983
0
        proto_tree_add_item(sub_tree, hf_pn532_wakeup_enable_i2c, tvb, offset, 1, ENC_BIG_ENDIAN);
984
0
        proto_tree_add_item(sub_tree, hf_pn532_wakeup_enable_gpio, tvb, offset, 1, ENC_BIG_ENDIAN);
985
0
        proto_tree_add_item(sub_tree, hf_pn532_wakeup_enable_spi, tvb, offset, 1, ENC_BIG_ENDIAN);
986
0
        proto_tree_add_item(sub_tree, hf_pn532_wakeup_enable_hsu, tvb, offset, 1, ENC_BIG_ENDIAN);
987
0
        proto_tree_add_item(sub_tree, hf_pn532_wakeup_enable_rf_level_detector, tvb, offset, 1, ENC_BIG_ENDIAN);
988
0
        proto_tree_add_item(sub_tree, hf_pn532_wakeup_enable_rfu_2, tvb, offset, 1, ENC_BIG_ENDIAN);
989
0
        proto_tree_add_item(sub_tree, hf_pn532_wakeup_enable_int_1, tvb, offset, 1, ENC_BIG_ENDIAN);
990
0
        proto_tree_add_item(sub_tree, hf_pn532_wakeup_enable_int_0, tvb, offset, 1, ENC_BIG_ENDIAN);
991
0
        offset += 1;
992
993
0
        if (tvb_reported_length_remaining(tvb, offset) >= 1) {
994
0
            proto_tree_add_item(pn532_tree, hf_pn532_generate_irq, tvb, offset, 1, ENC_BIG_ENDIAN);
995
0
            offset += 1;
996
0
        }
997
0
        break;
998
999
0
    case POWER_DOWN_RSP:
1000
0
        offset = dissect_status(pn532_tree, tvb, offset);
1001
0
        break;
1002
1003
0
    case RF_CONFIGURATION_REQ:
1004
0
        proto_tree_add_item(pn532_tree, hf_pn532_config, tvb, offset, 1, ENC_BIG_ENDIAN);
1005
0
        config = tvb_get_uint8(tvb, offset);
1006
0
        offset += 1;
1007
1008
0
        switch(config) {
1009
0
        case 0x01:
1010
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_not_used, tvb, offset, 1, ENC_BIG_ENDIAN);
1011
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_auto_rfca, tvb, offset, 1, ENC_BIG_ENDIAN);
1012
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_rf, tvb, offset, 1, ENC_BIG_ENDIAN);
1013
0
            offset += 1;
1014
0
            break;
1015
0
        case 0x02:
1016
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_rfu, tvb, offset, 1, ENC_BIG_ENDIAN);
1017
0
            offset += 1;
1018
1019
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_atr_res_timeout, tvb, offset, 1, ENC_BIG_ENDIAN);
1020
0
            offset += 1;
1021
1022
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_timeout_non_dep, tvb, offset, 1, ENC_BIG_ENDIAN);
1023
0
            offset += 1;
1024
0
            break;
1025
0
        case 0x04:
1026
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_max_rty_com, tvb, offset, 1, ENC_BIG_ENDIAN);
1027
0
            offset += 1;
1028
0
            break;
1029
0
        case 0x05:
1030
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_max_rty_atr, tvb, offset, 1, ENC_BIG_ENDIAN);
1031
0
            offset += 1;
1032
1033
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_max_rty_psl, tvb, offset, 1, ENC_BIG_ENDIAN);
1034
0
            offset += 1;
1035
1036
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_max_rty_passive_activation, tvb, offset, 1, ENC_BIG_ENDIAN);
1037
0
            offset += 1;
1038
0
            break;
1039
0
        case 0x0A:
1040
0
        case 0x0B:
1041
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_rf_cfg, tvb, offset, 1, ENC_BIG_ENDIAN);
1042
0
            offset += 1;
1043
1044
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_gs_n_on, tvb, offset, 1, ENC_BIG_ENDIAN);
1045
0
            offset += 1;
1046
1047
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_cw_gs_p, tvb, offset, 1, ENC_BIG_ENDIAN);
1048
0
            offset += 1;
1049
1050
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_mod_gs_p, tvb, offset, 1, ENC_BIG_ENDIAN);
1051
0
            offset += 1;
1052
1053
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_demon_rf_on, tvb, offset, 1, ENC_BIG_ENDIAN);
1054
0
            offset += 1;
1055
1056
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_rx_threshold, tvb, offset, 1, ENC_BIG_ENDIAN);
1057
0
            offset += 1;
1058
1059
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_demon_rf_off, tvb, offset, 1, ENC_BIG_ENDIAN);
1060
0
            offset += 1;
1061
1062
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_gs_n_off, tvb, offset, 1, ENC_BIG_ENDIAN);
1063
0
            offset += 1;
1064
1065
0
            if (config == 0x0A) {
1066
0
                proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_mod_width, tvb, offset, 1, ENC_BIG_ENDIAN);
1067
0
                offset += 1;
1068
1069
0
                proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_mif_nfc, tvb, offset, 1, ENC_BIG_ENDIAN);
1070
0
                offset += 1;
1071
1072
0
                proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_tx_bit_phase, tvb, offset, 1, ENC_BIG_ENDIAN);
1073
0
                offset += 1;
1074
0
            }
1075
0
            break;
1076
0
        case 0x0C:
1077
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_gs_n_on, tvb, offset, 1, ENC_BIG_ENDIAN);
1078
0
            offset += 1;
1079
1080
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_mod_gs_p, tvb, offset, 1, ENC_BIG_ENDIAN);
1081
0
            offset += 1;
1082
1083
0
            proto_tree_add_item(pn532_tree, hf_pn532_config_ciu_rx_threshold, tvb, offset, 1, ENC_BIG_ENDIAN);
1084
0
            offset += 1;
1085
0
            break;
1086
0
        case 0x0D:
1087
0
            sub_item = proto_tree_add_item(pn532_tree, hf_pn532_config_212_kbps, tvb, offset, 3, ENC_BIG_ENDIAN);
1088
0
            sub_tree = proto_item_add_subtree(sub_item, ett_pn532_config_212_kbps);
1089
1090
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_rx_threshold, tvb, offset, 1, ENC_BIG_ENDIAN);
1091
0
            offset += 1;
1092
1093
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_mod_width, tvb, offset, 1, ENC_BIG_ENDIAN);
1094
0
            offset += 1;
1095
1096
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_mif_nfc, tvb, offset, 1, ENC_BIG_ENDIAN);
1097
0
            offset += 1;
1098
1099
0
            sub_item = proto_tree_add_item(pn532_tree, hf_pn532_config_424_kbps, tvb, offset, 3, ENC_BIG_ENDIAN);
1100
0
            sub_tree = proto_item_add_subtree(sub_item, ett_pn532_config_424_kbps);
1101
1102
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_rx_threshold, tvb, offset, 1, ENC_BIG_ENDIAN);
1103
0
            offset += 1;
1104
1105
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_mod_width, tvb, offset, 1, ENC_BIG_ENDIAN);
1106
0
            offset += 1;
1107
1108
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_mif_nfc, tvb, offset, 1, ENC_BIG_ENDIAN);
1109
0
            offset += 1;
1110
1111
0
            sub_item = proto_tree_add_item(pn532_tree, hf_pn532_config_848_kbps, tvb, offset, 3, ENC_BIG_ENDIAN);
1112
0
            sub_tree = proto_item_add_subtree(sub_item, ett_pn532_config_848_kbps);
1113
1114
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_rx_threshold, tvb, offset, 1, ENC_BIG_ENDIAN);
1115
0
            offset += 1;
1116
1117
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_mod_width, tvb, offset, 1, ENC_BIG_ENDIAN);
1118
0
            offset += 1;
1119
1120
0
            proto_tree_add_item(sub_tree, hf_pn532_config_ciu_mif_nfc, tvb, offset, 1, ENC_BIG_ENDIAN);
1121
0
            offset += 1;
1122
0
            break;
1123
0
        default:
1124
0
            proto_tree_add_expert(pn532_tree, pinfo, &ei_unknown_data, tvb, offset, tvb_captured_length_remaining(tvb, offset));
1125
0
            offset += tvb_captured_length_remaining(tvb, offset);
1126
0
        }
1127
0
        break;
1128
1129
0
    case RF_CONFIGURATION_RSP:
1130
        /* No parameters */
1131
0
        break;
1132
1133
0
    case RF_REGULATION_TEST_REQ:
1134
0
        proto_tree_add_item(pn532_tree, hf_pn532_txmode_nu_7, tvb, offset, 1, ENC_BIG_ENDIAN);
1135
0
        proto_tree_add_item(pn532_tree, hf_pn532_txmode_tx_speed, tvb, offset, 1, ENC_BIG_ENDIAN);
1136
0
        proto_tree_add_item(pn532_tree, hf_pn532_txmode_nu_2_3, tvb, offset, 1, ENC_BIG_ENDIAN);
1137
0
        proto_tree_add_item(pn532_tree, hf_pn532_txmode_tx_framing, tvb, offset, 1, ENC_BIG_ENDIAN);
1138
0
        offset += 1;
1139
0
        break;
1140
1141
0
    case RF_REGULATION_TEST_RSP:
1142
        /* This should never happened */
1143
0
        break;
1144
1145
0
    case IN_JUMP_FOR_DEP_REQ:
1146
0
    case IN_JUMP_FOR_PSL_REQ:
1147
0
        proto_tree_add_item(pn532_tree, hf_pn532_communication_mode, tvb, offset, 1, ENC_BIG_ENDIAN);
1148
0
        offset += 1;
1149
1150
0
        proto_tree_add_item(pn532_tree, hf_pn532_activation_baudrate, tvb, offset, 1, ENC_BIG_ENDIAN);
1151
0
        baudrate = tvb_get_uint8(tvb, offset);
1152
0
        offset += 1;
1153
1154
0
        proto_tree_add_item(pn532_tree, hf_pn532_jump_next_not_used_3_7, tvb, offset, 1, ENC_BIG_ENDIAN);
1155
0
        proto_tree_add_item(pn532_tree, hf_pn532_jump_next_passive_initiator_data, tvb, offset, 1, ENC_BIG_ENDIAN);
1156
0
        proto_tree_add_item(pn532_tree, hf_pn532_jump_next_gi, tvb, offset, 1, ENC_BIG_ENDIAN);
1157
0
        proto_tree_add_item(pn532_tree, hf_pn532_jump_next_nfc_id_3i, tvb, offset, 1, ENC_BIG_ENDIAN);
1158
0
        value = tvb_get_uint8(tvb, offset);
1159
0
        offset += 1;
1160
1161
0
        if (value & 0x01) {
1162
0
            if (baudrate == 0x00) {
1163
0
                proto_tree_add_item(pn532_tree, hf_pn532_passive_initiator_data, tvb, offset, 4, ENC_NA);
1164
0
                offset += 4;
1165
0
            } else {
1166
0
                proto_tree_add_item(pn532_tree, hf_pn532_passive_initiator_data, tvb, offset, 5, ENC_NA);
1167
0
                offset += 5;
1168
0
            }
1169
0
        }
1170
1171
0
        if (value & 0x02) {
1172
0
            proto_tree_add_item(pn532_tree, hf_pn532_nfc_id_3i, tvb, offset, 10, ENC_NA);
1173
0
            offset += 10;
1174
0
        }
1175
1176
0
        if (value & 0x04) {
1177
0
            proto_tree_add_item(pn532_tree, hf_pn532_gi, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1178
0
            offset += tvb_captured_length_remaining(tvb, offset);
1179
0
        }
1180
0
        break;
1181
1182
0
    case IN_JUMP_FOR_DEP_RSP:
1183
0
    case IN_JUMP_FOR_PSL_RSP:
1184
0
        offset = dissect_status(pn532_tree, tvb, offset);
1185
1186
0
        proto_tree_add_item(pn532_tree, hf_pn532_Tg, tvb, offset, 1, ENC_BIG_ENDIAN);
1187
0
        offset += 1;
1188
1189
0
        proto_tree_add_item(pn532_tree, hf_pn532_nfc_id_3t, tvb, offset, 10, ENC_NA);
1190
0
        offset += 10;
1191
1192
0
        proto_tree_add_item(pn532_tree, hf_pn532_did_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1193
0
        offset += 1;
1194
1195
0
        proto_tree_add_item(pn532_tree, hf_pn532_send_bit_rate_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1196
0
        offset += 1;
1197
1198
0
        proto_tree_add_item(pn532_tree, hf_pn532_receive_bit_rate_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1199
0
        offset += 1;
1200
1201
0
        proto_tree_add_item(pn532_tree, hf_pn532_timeout, tvb, offset, 1, ENC_BIG_ENDIAN);
1202
0
        offset += 1;
1203
1204
0
        proto_tree_add_item(pn532_tree, hf_pn532_optional_parameters, tvb, offset, 1, ENC_BIG_ENDIAN);
1205
0
        offset += 1;
1206
1207
0
        proto_tree_add_item(pn532_tree, hf_pn532_gt, tvb, offset, 10, ENC_NA);
1208
0
        offset += 10;
1209
0
        break;
1210
1211
0
    case IN_LIST_PASSIVE_TARGET_REQ:
1212
1213
0
        proto_tree_add_item(pn532_tree, hf_pn532_MaxTg, tvb, offset, 1, ENC_BIG_ENDIAN);
1214
0
        offset += 1;
1215
1216
0
        proto_tree_add_item(pn532_tree, hf_pn532_BrTy, tvb, offset, 1, ENC_BIG_ENDIAN);
1217
0
        baudrate = tvb_get_uint8(tvb, offset);
1218
0
        offset += 1;
1219
1220
0
        if (command_data)
1221
0
            command_data->data.baudrate = baudrate;
1222
1223
0
        switch(baudrate) {
1224
0
        case ISO_IEC_14443A_106:
1225
0
            while (tvb_reported_length_remaining(tvb, offset) >= 4) {
1226
0
                proto_tree_add_item(pn532_tree, hf_pn532_14443a_uid, tvb, 6, 4, ENC_BIG_ENDIAN);
1227
0
                offset += 4;
1228
0
            }
1229
0
            break;
1230
0
        case FELICA_212:
1231
0
        case FELICA_424:
1232
0
            next_tvb = tvb_new_subset_length(tvb, offset, 5);
1233
0
            call_dissector(sub_handles[SUB_FELICA], next_tvb, pinfo, tree);
1234
0
            offset += 5;
1235
0
            break;
1236
1237
0
        case ISO_IEC_14443B_106:
1238
0
            proto_tree_add_item(pn532_tree, hf_pn532_afi, tvb, offset, 1, ENC_BIG_ENDIAN);
1239
0
            offset += 1;
1240
1241
0
            if (tvb_reported_length_remaining(tvb, offset) >= 1) {
1242
0
                proto_tree_add_item(pn532_tree, hf_pn532_polling_method, tvb, offset, 1, ENC_BIG_ENDIAN);
1243
0
                offset += 1;
1244
0
            }
1245
0
            break;
1246
0
        case JEWEL_14443A_106:
1247
            /* No parameter */
1248
0
            break;
1249
0
        }
1250
0
        break;
1251
1252
0
    case IN_LIST_PASSIVE_TARGET_RSP:
1253
0
        proto_tree_add_item(pn532_tree, hf_pn532_NbTg, tvb, offset, 1, ENC_BIG_ENDIAN);
1254
0
        value = tvb_get_uint8(tvb, offset);
1255
0
        offset += 1;
1256
1257
0
        if (command_data  && command_data->command == IN_LIST_PASSIVE_TARGET_REQ)
1258
0
            baudrate = command_data->data.baudrate;
1259
0
        else
1260
0
            baudrate = -1; /* Force unknown baudrate... */
1261
1262
0
        sub_item = proto_tree_add_uint(pn532_tree, hf_pn532_BrTy, tvb, offset, tvb_captured_length_remaining(tvb, offset), baudrate);
1263
0
        proto_item_set_generated(sub_item);
1264
1265
0
        for (item_value = 1; item_value <= value; item_value += 1) {
1266
0
            sub_item = proto_tree_add_item(pn532_tree, hf_pn532_target, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1267
0
            sub_tree = proto_item_add_subtree(sub_item, ett_pn532_target);
1268
0
            proto_item_append_text(sub_item, " %u/%u", item_value, value);
1269
1270
0
            proto_tree_add_item(sub_tree, hf_pn532_Tg, tvb, offset, 1, ENC_BIG_ENDIAN);
1271
0
            offset += 1;
1272
1273
0
            switch (baudrate) {
1274
0
            case ISO_IEC_14443A_106:
1275
0
                proto_tree_add_item(sub_tree, hf_pn532_sens_res, tvb, offset, 2, ENC_BIG_ENDIAN);
1276
0
                offset += 2;
1277
1278
0
                proto_tree_add_item(sub_tree, hf_pn532_sel_res, tvb, offset, 1, ENC_BIG_ENDIAN);
1279
0
                offset += 1;
1280
1281
0
                proto_tree_add_item(sub_tree, hf_pn532_nfc_id_length, tvb, offset, 1, ENC_BIG_ENDIAN);
1282
0
                length = tvb_get_uint8(tvb, offset);
1283
0
                offset += 1;
1284
1285
0
                proto_tree_add_item(sub_tree, hf_pn532_nfc_id_1, tvb, offset, length, ENC_NA);
1286
0
                offset += length;
1287
1288
0
                if (tvb_reported_length_remaining(tvb, offset)) {
1289
0
                    proto_tree_add_item(sub_tree, hf_pn532_ats_length, tvb, offset, 1, ENC_BIG_ENDIAN);
1290
0
                    length = tvb_get_uint8(tvb, offset);
1291
0
                    offset += 1;
1292
1293
0
                    proto_tree_add_item(sub_tree, hf_pn532_ats, tvb, offset, length - 1, ENC_NA);
1294
0
                    offset += length - 1;
1295
0
                }
1296
0
                break;
1297
0
            case FELICA_212:
1298
0
            case FELICA_424:
1299
0
                proto_tree_add_item(sub_tree, hf_pn532_pol_res_length, tvb, offset, 1, ENC_BIG_ENDIAN);
1300
0
                offset += 1;
1301
1302
0
                proto_tree_add_item(sub_tree, hf_pn532_response_code, tvb, offset, 1, ENC_BIG_ENDIAN);
1303
0
                offset += 1;
1304
1305
0
                proto_tree_add_item(sub_tree, hf_pn532_nfc_id_2t, tvb, offset, 8, ENC_NA);
1306
0
                offset += 8;
1307
1308
0
                proto_tree_add_item(sub_tree, hf_pn532_pad, tvb, offset, 8, ENC_NA);
1309
0
                offset += 8;
1310
1311
0
                if (tvb_reported_length_remaining(tvb, offset) >= 2) {
1312
0
                    proto_tree_add_item(sub_tree, hf_pn532_syst_code, tvb, offset, 2, ENC_BIG_ENDIAN);
1313
0
                    offset += 2;
1314
0
                } else if (tvb_reported_length_remaining(tvb, offset) == 1) {
1315
0
                    proto_tree_add_expert(pn532_tree, pinfo, &ei_unexpected_data, tvb, offset, 1);
1316
0
                    offset += 1;
1317
0
                }
1318
0
                break;
1319
0
            case ISO_IEC_14443B_106:
1320
0
                proto_tree_add_item(sub_tree, hf_pn532_atqb_response, tvb, offset, 12, ENC_NA);
1321
0
                offset += 12;
1322
1323
0
                proto_tree_add_item(sub_tree, hf_pn532_attrib_res_length, tvb, offset, 1, ENC_BIG_ENDIAN);
1324
0
                length = tvb_get_uint8(tvb, offset);
1325
0
                offset += 1;
1326
1327
0
                proto_tree_add_item(sub_tree, hf_pn532_attrib_res, tvb, offset, length, ENC_NA);
1328
0
                offset += length;
1329
0
                break;
1330
0
            case JEWEL_14443A_106:
1331
0
                proto_tree_add_item(sub_tree, hf_pn532_sens_res, tvb, offset, 2, ENC_BIG_ENDIAN);
1332
0
                offset += 2;
1333
1334
0
                proto_tree_add_item(sub_tree, hf_pn532_jewel_id, tvb, offset, 4, ENC_NA);
1335
0
                offset += 4;
1336
0
                break;
1337
0
            default:
1338
0
                proto_tree_add_expert(pn532_tree, pinfo, &ei_unknown_data, tvb, offset, tvb_captured_length_remaining(tvb, offset));
1339
0
                offset += tvb_captured_length_remaining(tvb, offset);
1340
0
            }
1341
1342
0
        }
1343
0
        break;
1344
1345
0
    case IN_ATR_REQ:
1346
0
        proto_tree_add_item(pn532_tree, hf_pn532_Tg, tvb, offset, 1, ENC_BIG_ENDIAN);
1347
0
        offset += 1;
1348
1349
0
        proto_tree_add_item(pn532_tree, hf_pn532_next_not_used_2_7, tvb, offset, 1, ENC_BIG_ENDIAN);
1350
0
        proto_tree_add_item(pn532_tree, hf_pn532_next_gi, tvb, offset, 1, ENC_BIG_ENDIAN);
1351
0
        proto_tree_add_item(pn532_tree, hf_pn532_next_nfc_id_3i, tvb, offset, 1, ENC_BIG_ENDIAN);
1352
0
        value = tvb_get_uint8(tvb, offset);
1353
0
        offset += 1;
1354
1355
0
        if (value & 0x01) {
1356
0
            proto_tree_add_item(pn532_tree, hf_pn532_nfc_id_3i, tvb, offset, 10, ENC_NA);
1357
0
            offset += 10;
1358
0
        }
1359
1360
0
        if (value & 0x02) {
1361
0
            proto_tree_add_item(pn532_tree, hf_pn532_gi, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1362
0
            offset += tvb_captured_length_remaining(tvb, offset);
1363
0
        }
1364
0
        break;
1365
1366
0
    case IN_ATR_RSP:
1367
0
        offset = dissect_status(pn532_tree, tvb, offset);
1368
1369
0
        proto_tree_add_item(pn532_tree, hf_pn532_nfc_id_3t, tvb, offset, 10, ENC_NA);
1370
0
        offset += 10;
1371
1372
0
        proto_tree_add_item(pn532_tree, hf_pn532_did_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1373
0
        offset += 1;
1374
1375
0
        proto_tree_add_item(pn532_tree, hf_pn532_send_bit_rate_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1376
0
        offset += 1;
1377
1378
0
        proto_tree_add_item(pn532_tree, hf_pn532_receive_bit_rate_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1379
0
        offset += 1;
1380
1381
0
        proto_tree_add_item(pn532_tree, hf_pn532_timeout, tvb, offset, 1, ENC_BIG_ENDIAN);
1382
0
        offset += 1;
1383
1384
0
        proto_tree_add_item(pn532_tree, hf_pn532_optional_parameters, tvb, offset, 1, ENC_BIG_ENDIAN);
1385
0
        offset += 1;
1386
1387
0
        proto_tree_add_item(pn532_tree, hf_pn532_gt, tvb, offset, 10, ENC_NA);
1388
0
        offset += 10;
1389
0
        break;
1390
1391
0
    case IN_PSL_REQ:
1392
0
        proto_tree_add_item(pn532_tree, hf_pn532_Tg, tvb, offset, 1, ENC_BIG_ENDIAN);
1393
0
        offset += 1;
1394
1395
0
        proto_tree_add_item(pn532_tree, hf_pn532_brit, tvb, offset, 1, ENC_BIG_ENDIAN);
1396
0
        offset += 1;
1397
1398
0
        proto_tree_add_item(pn532_tree, hf_pn532_brti, tvb, offset, 1, ENC_BIG_ENDIAN);
1399
0
        offset += 1;
1400
0
        break;
1401
1402
0
    case IN_PSL_RSP:
1403
0
        offset = dissect_status(pn532_tree, tvb, offset);
1404
0
        break;
1405
1406
0
    case IN_DATA_EXCHANGE_REQ:
1407
0
        proto_tree_add_item(pn532_tree, hf_pn532_Tg, tvb, offset, 1, ENC_BIG_ENDIAN);
1408
0
        offset += 1;
1409
1410
0
        if (sub_selected == SUB_MIFARE) {
1411
            /* Seems to work for payloads from LibNFC's "nfc-mfultralight" command */
1412
0
            next_tvb = tvb_new_subset_remaining(tvb, offset);
1413
0
            call_dissector(sub_handles[SUB_MIFARE], next_tvb, pinfo, tree);
1414
0
            offset += tvb_captured_length_remaining(tvb, offset);
1415
0
        } else if (sub_selected == SUB_ISO7816) {
1416
            /* Seems to work for EMV payloads sent using TAMA shell scripts */
1417
0
            next_tvb = tvb_new_subset_remaining(tvb, offset);
1418
1419
            /* Need to do this, for the ISO7816 dissector to work, it seems */
1420
0
            pinfo->p2p_dir = P2P_DIR_SENT;
1421
0
            call_dissector(sub_handles[SUB_ISO7816], next_tvb, pinfo, tree);
1422
0
            offset += tvb_captured_length_remaining(tvb, offset);
1423
0
        } else {
1424
0
            proto_tree_add_item(pn532_tree, hf_pn532_data_out, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1425
0
            offset += tvb_captured_length_remaining(tvb, offset);
1426
0
        }
1427
1428
0
        break;
1429
1430
0
    case IN_DATA_EXCHANGE_RSP:
1431
0
        offset = dissect_status(pn532_tree, tvb, offset);
1432
1433
0
        if (sub_selected == SUB_ISO7816) {
1434
1435
            /* Seems to work for identifying responses to Select File requests...
1436
               Might need to investigate "Status Words", later */
1437
1438
0
            next_tvb = tvb_new_subset_remaining(tvb, offset);
1439
1440
            /* Need to do this, for the ISO7816 dissector to work, it seems */
1441
0
            pinfo->p2p_dir = P2P_DIR_RECV;
1442
0
            call_dissector(sub_handles[SUB_ISO7816], next_tvb, pinfo, tree);
1443
0
            offset += tvb_captured_length_remaining(tvb, offset);
1444
0
        } else {
1445
0
            proto_tree_add_item(pn532_tree, hf_pn532_data_in, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1446
0
            offset += tvb_captured_length_remaining(tvb, offset);
1447
0
        }
1448
1449
0
        break;
1450
1451
0
    case IN_COMMUNICATE_THRU_REQ:
1452
0
        if (sub_selected == SUB_FELICA) {
1453
1454
            /* Alleged payload length for FeliCa */
1455
0
            proto_tree_add_item(pn532_tree, hf_pn532_payload_length, tvb, 2, 1, ENC_BIG_ENDIAN);
1456
1457
            /* Attempt to dissect FeliCa payloads */
1458
0
            next_tvb = tvb_new_subset_remaining(tvb, 3);
1459
0
            call_dissector(sub_handles[SUB_FELICA], next_tvb, pinfo, tree);
1460
0
        } else {
1461
            /* NOTE: MiFare transmissions may identify as spurious FeliCa packets, in some cases */
1462
1463
0
            proto_tree_add_item(pn532_tree, hf_pn532_data_out, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1464
0
            offset += tvb_captured_length_remaining(tvb, offset);
1465
0
        }
1466
0
        break;
1467
1468
0
    case IN_COMMUNICATE_THRU_RSP:
1469
0
        offset = dissect_status(pn532_tree, tvb, offset);
1470
1471
0
        if (sub_selected == SUB_FELICA) {
1472
1473
            /* Alleged payload length for FeliCa */
1474
0
            proto_tree_add_item(pn532_tree, hf_pn532_payload_length, tvb, 3, 1, ENC_BIG_ENDIAN);
1475
1476
            /* Attempt to dissect FeliCa payloads */
1477
0
            next_tvb = tvb_new_subset_remaining(tvb, 4);
1478
0
            call_dissector(sub_handles[SUB_FELICA], next_tvb, pinfo, tree);
1479
0
        } else {
1480
            /* NOTE: MiFare transmissions may identify as spurious FeliCa packets, in some cases */
1481
1482
0
            proto_tree_add_item(pn532_tree, hf_pn532_data_in, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1483
0
            offset += tvb_captured_length_remaining(tvb, offset);
1484
0
        }
1485
0
        break;
1486
1487
0
    case IN_DESELECT_REQ:
1488
0
    case IN_RELEASE_REQ:
1489
0
    case IN_SELECT_REQ:
1490
0
        proto_tree_add_item(pn532_tree, hf_pn532_Tg, tvb, offset, 1, ENC_BIG_ENDIAN);
1491
0
        offset += 1;
1492
0
        break;
1493
1494
0
    case IN_DESELECT_RSP:
1495
0
    case IN_RELEASE_RSP:
1496
0
    case IN_SELECT_RSP:
1497
0
        offset = dissect_status(pn532_tree, tvb, offset);
1498
0
        break;
1499
1500
0
    case IN_AUTO_POLL_REQ:
1501
0
        proto_tree_add_item(pn532_tree, hf_pn532_poll_number, tvb, offset, 1, ENC_BIG_ENDIAN);
1502
0
        offset += 1;
1503
1504
0
        proto_tree_add_item(pn532_tree, hf_pn532_period, tvb, offset, 1, ENC_BIG_ENDIAN);
1505
0
        offset += 1;
1506
1507
        /* This one is mandatory */
1508
0
        sub_item = proto_tree_add_item(pn532_tree, hf_pn532_autopoll_type, tvb, offset, 1, ENC_BIG_ENDIAN);
1509
0
        sub_tree = proto_item_add_subtree(sub_item, ett_pn532_autopoll_type);
1510
0
        proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_act, tvb, offset, 1, ENC_BIG_ENDIAN);
1511
0
        proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_dep, tvb, offset, 1, ENC_BIG_ENDIAN);
1512
0
        proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_tcl, tvb, offset, 1, ENC_BIG_ENDIAN);
1513
0
        proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_mf_fe, tvb, offset, 1, ENC_BIG_ENDIAN);
1514
0
        proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_not_used, tvb, offset, 1, ENC_BIG_ENDIAN);
1515
0
        proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_baudrate_and_modulation, tvb, offset, 1, ENC_BIG_ENDIAN);
1516
0
        offset += 1;
1517
1518
0
        while (tvb_reported_length_remaining(tvb, offset) >= 1) {
1519
0
            sub_item = proto_tree_add_item(pn532_tree, hf_pn532_autopoll_type, tvb, offset, 1, ENC_BIG_ENDIAN);
1520
0
            sub_tree = proto_item_add_subtree(sub_item, ett_pn532_autopoll_type);
1521
0
            proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_act, tvb, offset, 1, ENC_BIG_ENDIAN);
1522
0
            proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_dep, tvb, offset, 1, ENC_BIG_ENDIAN);
1523
0
            proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_tcl, tvb, offset, 1, ENC_BIG_ENDIAN);
1524
0
            proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_mf_fe, tvb, offset, 1, ENC_BIG_ENDIAN);
1525
0
            proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_not_used, tvb, offset, 1, ENC_BIG_ENDIAN);
1526
0
            proto_tree_add_item(sub_tree, hf_pn532_autopoll_type_baudrate_and_modulation, tvb, offset, 1, ENC_BIG_ENDIAN);
1527
0
            offset += 1;
1528
0
        }
1529
1530
0
        break;
1531
1532
0
    case IN_AUTO_POLL_RSP:
1533
0
        proto_tree_add_item(pn532_tree, hf_pn532_NbTg, tvb, offset, 1, ENC_BIG_ENDIAN);
1534
0
        value = tvb_get_uint8(tvb, offset);
1535
0
        offset += 1;
1536
1537
0
        for (item_value = 1; item_value <= value; item_value += 1) {
1538
0
            sub_item = proto_tree_add_item(pn532_tree, hf_pn532_target, tvb, offset, 4, ENC_NA);
1539
0
            sub_tree = proto_item_add_subtree(sub_item, ett_pn532_target);
1540
0
            proto_item_append_text(sub_item, " %u/%u", item_value, value);
1541
1542
0
            next_item = proto_tree_add_item(sub_tree, hf_pn532_autopoll_type, tvb, offset, 1, ENC_BIG_ENDIAN);
1543
0
            next_tree = proto_item_add_subtree(next_item, ett_pn532_autopoll_type);
1544
0
            proto_tree_add_item(next_tree, hf_pn532_autopoll_type_act, tvb, offset, 1, ENC_BIG_ENDIAN);
1545
0
            proto_tree_add_item(next_tree, hf_pn532_autopoll_type_dep, tvb, offset, 1, ENC_BIG_ENDIAN);
1546
0
            proto_tree_add_item(next_tree, hf_pn532_autopoll_type_tcl, tvb, offset, 1, ENC_BIG_ENDIAN);
1547
0
            proto_tree_add_item(next_tree, hf_pn532_autopoll_type_mf_fe, tvb, offset, 1, ENC_BIG_ENDIAN);
1548
0
            proto_tree_add_item(next_tree, hf_pn532_autopoll_type_not_used, tvb, offset, 1, ENC_BIG_ENDIAN);
1549
0
            proto_tree_add_item(next_tree, hf_pn532_autopoll_type_baudrate_and_modulation, tvb, offset, 1, ENC_BIG_ENDIAN);
1550
0
            type = tvb_get_uint8(tvb, offset);
1551
0
            offset += 1;
1552
1553
0
            proto_tree_add_item(sub_tree, hf_pn532_target_data_length, tvb, offset, 1, ENC_BIG_ENDIAN);
1554
0
            length = tvb_get_uint8(tvb, offset);
1555
0
            proto_item_set_len(sub_item, length + 4);
1556
0
            offset += 1;
1557
1558
0
            if (type & 0x40) { /* DEP */
1559
0
                if (type & 0x80) { /* Passive mode */
1560
0
                    proto_tree_add_item(pn532_tree, hf_pn532_target_data, tvb, offset, length, ENC_NA);
1561
0
                    offset += length;
1562
0
                }
1563
1564
0
                proto_tree_add_item(pn532_tree, hf_pn532_nfc_id_3t, tvb, offset, 10, ENC_NA);
1565
0
                offset += 10;
1566
1567
0
                proto_tree_add_item(pn532_tree, hf_pn532_did_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1568
0
                offset += 1;
1569
1570
0
                proto_tree_add_item(pn532_tree, hf_pn532_send_bit_rate_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1571
0
                offset += 1;
1572
1573
0
                proto_tree_add_item(pn532_tree, hf_pn532_receive_bit_rate_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1574
0
                offset += 1;
1575
1576
0
                proto_tree_add_item(pn532_tree, hf_pn532_timeout, tvb, offset, 1, ENC_BIG_ENDIAN);
1577
0
                offset += 1;
1578
1579
0
                proto_tree_add_item(pn532_tree, hf_pn532_optional_parameters, tvb, offset, 1, ENC_BIG_ENDIAN);
1580
0
                offset += 1;
1581
1582
0
                proto_tree_add_item(pn532_tree, hf_pn532_gt, tvb, offset, 10, ENC_NA);
1583
0
                offset += 10;
1584
0
            } else { /* non-DEP */
1585
0
                proto_tree_add_item(pn532_tree, hf_pn532_target_data, tvb, offset, length, ENC_NA);
1586
0
                offset += length;
1587
0
            }
1588
0
        }
1589
1590
0
        break;
1591
1592
0
    case TG_INIT_AS_TARGET_REQ:
1593
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_nu_3_7, tvb, offset, 1, ENC_BIG_ENDIAN);
1594
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_picc_only, tvb, offset, 1, ENC_BIG_ENDIAN);
1595
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_dep_only, tvb, offset, 1, ENC_BIG_ENDIAN);
1596
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_passive_only, tvb, offset, 1, ENC_BIG_ENDIAN);
1597
0
        offset += 1;
1598
1599
0
        sub_item = proto_tree_add_item(pn532_tree, hf_pn532_mode_mifare_parameters, tvb, offset, 6, ENC_NA);
1600
0
        sub_tree = proto_item_add_subtree(sub_item, ett_pn532_mifare_parameters);
1601
1602
0
        proto_tree_add_item(sub_tree, hf_pn532_mode_mifare_parameters_sens_res, tvb, offset, 2, ENC_BIG_ENDIAN);
1603
0
        offset += 2;
1604
1605
0
        proto_tree_add_item(sub_tree, hf_pn532_mode_mifare_parameters_nfc_id_1t, tvb, offset, 3, ENC_NA);
1606
0
        offset += 3;
1607
1608
0
        proto_tree_add_item(sub_tree, hf_pn532_mode_mifare_parameters_sel_res, tvb, offset, 1, ENC_BIG_ENDIAN);
1609
0
        offset += 1;
1610
1611
0
        sub_item = proto_tree_add_item(pn532_tree, hf_pn532_mode_felica_parameters, tvb, offset, 18, ENC_NA);
1612
0
        sub_tree = proto_item_add_subtree(sub_item, ett_pn532_felica_parameters);
1613
1614
0
        proto_tree_add_item(sub_tree, hf_pn532_mode_felica_parameters_nfc_id_2t, tvb, offset, 8, ENC_NA);
1615
0
        offset += 8;
1616
1617
0
        proto_tree_add_item(sub_tree, hf_pn532_mode_felica_parameters_pad, tvb, offset, 8, ENC_NA);
1618
0
        offset += 8;
1619
1620
0
        proto_tree_add_item(sub_tree, hf_pn532_mode_felica_parameters_system_code, tvb, offset, 2, ENC_BIG_ENDIAN);
1621
0
        offset += 2;
1622
1623
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_nfc_id_3t, tvb, offset, 10, ENC_NA);
1624
0
        offset += 10;
1625
1626
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_gt_length, tvb, offset, 1, ENC_BIG_ENDIAN);
1627
0
        length = tvb_get_uint8(tvb, offset);
1628
0
        offset += 1;
1629
1630
0
        if (length > 0) {
1631
0
            proto_tree_add_item(pn532_tree, hf_pn532_mode_gt, tvb, offset, length, ENC_NA);
1632
0
            offset += length;
1633
0
        }
1634
1635
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_tk_length, tvb, offset, 1, ENC_BIG_ENDIAN);
1636
0
        length = tvb_get_uint8(tvb, offset);
1637
0
        offset += 1;
1638
1639
0
        if (length > 0) {
1640
0
            proto_tree_add_item(pn532_tree, hf_pn532_mode_tk, tvb, offset, length, ENC_NA);
1641
0
            offset += length;
1642
0
        }
1643
0
        break;
1644
1645
0
    case TG_INIT_AS_TARGET_RSP:
1646
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_nu_7, tvb, offset, 1, ENC_BIG_ENDIAN);
1647
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_baudrate, tvb, offset, 1, ENC_BIG_ENDIAN);
1648
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_iso_iec_14443_4_picc, tvb, offset, 1, ENC_BIG_ENDIAN);
1649
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_dep, tvb, offset, 1, ENC_BIG_ENDIAN);
1650
0
        proto_tree_add_item(pn532_tree, hf_pn532_mode_framing_type, tvb, offset, 1, ENC_BIG_ENDIAN);
1651
0
        offset += 1;
1652
1653
0
        proto_tree_add_item(pn532_tree, hf_pn532_initiator_command, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1654
0
        offset += tvb_captured_length_remaining(tvb, offset);
1655
0
        break;
1656
1657
0
    case TG_SET_GENERAL_BYTES_REQ:
1658
0
        proto_tree_add_item(pn532_tree, hf_pn532_gt, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1659
0
        offset += tvb_captured_length_remaining(tvb, offset);
1660
0
        break;
1661
1662
0
    case TG_SET_GENERAL_BYTES_RSP:
1663
0
        offset = dissect_status(pn532_tree, tvb, offset);
1664
0
        break;
1665
1666
0
    case TG_GET_DATA_REQ:
1667
        /* No parameters */
1668
0
        break;
1669
1670
0
    case TG_GET_DATA_RSP:
1671
0
        offset = dissect_status(pn532_tree, tvb, offset);
1672
1673
0
        proto_tree_add_item(pn532_tree, hf_pn532_data_in, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1674
0
        offset += tvb_captured_length_remaining(tvb, offset);
1675
0
        break;
1676
1677
0
    case TG_SET_DATA_REQ:
1678
0
    case TG_SET_METADATA_REQ:
1679
0
        proto_tree_add_item(pn532_tree, hf_pn532_data_out, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1680
0
        offset += tvb_captured_length_remaining(tvb, offset);
1681
0
        break;
1682
1683
0
    case TG_SET_DATA_RSP:
1684
0
    case TG_SET_METADATA_RSP:
1685
0
        offset = dissect_status(pn532_tree, tvb, offset);
1686
0
        break;
1687
1688
0
    case TG_GET_INITIATOR_CMD_REQ:
1689
        /* No parameters */
1690
0
        break;
1691
1692
0
    case TG_GET_INITIATOR_CMD_RSP:
1693
0
        offset = dissect_status(pn532_tree, tvb, offset);
1694
1695
0
        proto_tree_add_item(pn532_tree, hf_pn532_initiator_command, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1696
0
        offset += tvb_captured_length_remaining(tvb, offset);
1697
0
        break;
1698
1699
0
    case TG_RESP_TO_INITIATOR_REQ:
1700
0
        proto_tree_add_item(pn532_tree, hf_pn532_tg_response, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1701
0
        offset += tvb_captured_length_remaining(tvb, offset);
1702
0
        break;
1703
1704
0
    case TG_RESP_TO_INITIATOR_RSP:
1705
0
        offset = dissect_status(pn532_tree, tvb, offset);
1706
0
        break;
1707
1708
0
    case TG_GET_TARGET_STATUS_REQ:
1709
        /* No parameters */
1710
0
        break;
1711
1712
0
    case TG_GET_TARGET_STATUS_RSP:
1713
0
        proto_tree_add_item(pn532_tree, hf_pn532_state, tvb, offset, 1, ENC_BIG_ENDIAN);
1714
0
        offset += 1;
1715
1716
0
        proto_tree_add_item(pn532_tree, hf_pn532_brit_nu_7, tvb, offset, 1, ENC_BIG_ENDIAN);
1717
0
        proto_tree_add_item(pn532_tree, hf_pn532_brit_speed_initiator, tvb, offset, 1, ENC_BIG_ENDIAN);
1718
0
        proto_tree_add_item(pn532_tree, hf_pn532_brit_nu_3, tvb, offset, 1, ENC_BIG_ENDIAN);
1719
0
        proto_tree_add_item(pn532_tree, hf_pn532_brit_speed_target, tvb, offset, 1, ENC_BIG_ENDIAN);
1720
0
        offset += 1;
1721
0
        break;
1722
1723
0
    default:
1724
0
        proto_tree_add_expert(pn532_tree, pinfo, &ei_unknown_data, tvb, offset, tvb_captured_length_remaining(tvb, offset));
1725
0
        offset += tvb_captured_length_remaining(tvb, offset);
1726
0
        break;
1727
0
    }
1728
1729
0
    if (tvb_reported_length_remaining(tvb, offset) > 0) {
1730
0
        proto_tree_add_expert(pn532_tree, pinfo, &ei_unexpected_data, tvb, offset, tvb_captured_length_remaining(tvb, offset));
1731
0
        offset += tvb_captured_length_remaining(tvb, offset);
1732
0
    }
1733
1734
0
    return offset;
1735
0
}
1736
1737
void proto_register_pn532(void)
1738
14
{
1739
14
    module_t *pref_mod;
1740
14
    expert_module_t *expert_pn532;
1741
1742
14
    static hf_register_info hf[] = {
1743
1744
14
        {&hf_pn532_command,
1745
14
         {"Command", "pn532.cmd", FT_UINT8, BASE_HEX | BASE_EXT_STRING,
1746
14
          &pn532_commands_ext, 0x0, NULL, HFILL}},
1747
14
        {&hf_pn532_direction,
1748
14
         {"Direction", "pn532.tfi", FT_UINT8, BASE_HEX,
1749
14
          VALS(pn532_directions), 0x0, NULL, HFILL}},
1750
14
        {&hf_pn532_status_nad_present,
1751
14
         {"NAD Present", "pn532.status.nad_present", FT_UINT8, BASE_HEX,
1752
14
          NULL, 0x80, NULL, HFILL}},
1753
14
        {&hf_pn532_status_mi,
1754
14
         {"MI", "pn532.status.mi", FT_UINT8, BASE_HEX,
1755
14
          NULL, 0x40, NULL, HFILL}},
1756
14
        {&hf_pn532_status_error_code,
1757
14
         {"Error Code", "pn532.status.error_code", FT_UINT8, BASE_HEX,
1758
14
          VALS(pn532_errors), 0x3F, NULL, HFILL}},
1759
14
        {&hf_pn532_error,
1760
14
         {"Last Error", "pn532.last_error", FT_UINT8, BASE_HEX,
1761
14
          VALS(pn532_errors), 0x00, NULL, HFILL}},
1762
14
        {&hf_pn532_BrTy,
1763
14
         {"Baud Rate and Modulation", "pn532.BrTy", FT_UINT8, BASE_HEX,
1764
14
          VALS(pn532_brtypes), 0x0, NULL, HFILL}},
1765
14
        {&hf_pn532_MaxTg,
1766
14
         {"Maximum Number of Targets", "pn532.MaxTg", FT_UINT8, BASE_DEC,
1767
14
          NULL, 0x0, NULL, HFILL}},
1768
14
        {&hf_pn532_Tg,
1769
14
         {"Logical Target Number", "pn532.Tg", FT_INT8, BASE_DEC,
1770
14
          NULL, 0x0, NULL, HFILL}},
1771
14
        {&hf_pn532_NbTg,
1772
14
         {"Number of Targets", "pn532.NbTg", FT_UINT8, BASE_DEC,
1773
14
          NULL, 0x0, NULL, HFILL}},
1774
14
        {&hf_pn532_payload_length,
1775
14
         {"Payload Length", "pn532.payload.length", FT_INT8, BASE_DEC,
1776
14
          NULL, 0x0, NULL, HFILL}},
1777
14
        {&hf_pn532_ic_version,
1778
14
         {"Integrated Circuit Version", "pn532.ic.version", FT_UINT8, BASE_HEX,
1779
14
          NULL, 0x0, "Version of the IC. For PN532, the contain of this byte is 0x32", HFILL}},
1780
14
        {&hf_pn532_fw_version,
1781
14
         {"Firmware Version", "pn532.fw.version", FT_UINT8, BASE_DEC,
1782
14
          NULL, 0x0, NULL, HFILL}},
1783
14
        {&hf_pn532_fw_revision,
1784
14
         {"Firmware Revision", "pn532.fw.revision", FT_UINT8, BASE_DEC,
1785
14
          NULL, 0x0, NULL, HFILL}},
1786
14
        {&hf_pn532_fw_support,
1787
14
         {"Firmware Support", "pn532.fw.support", FT_UINT8, BASE_DEC,
1788
14
          NULL, 0x0, NULL, HFILL}},
1789
14
        {&hf_pn532_fw_support_rfu,
1790
14
         {"RFU", "pn532.fw.support.rfu", FT_UINT8, BASE_HEX,
1791
14
          NULL, 0xF8, NULL, HFILL}},
1792
14
        {&hf_pn532_fw_support_iso_018092,
1793
14
         {"ISO 018092", "pn532.fw.support.iso_018092", FT_BOOLEAN, 8,
1794
14
          NULL, 0x04, NULL, HFILL}},
1795
14
        {&hf_pn532_fw_support_iso_iec_14443_type_b,
1796
14
         {"ISO/IEC 14443 Type B", "pn532.fw.support.iso_iec_14443_type_b", FT_BOOLEAN, 8,
1797
14
          NULL, 0x02, NULL, HFILL}},
1798
14
        {&hf_pn532_fw_support_iso_iec_14443_type_a,
1799
14
         {"ISO/IEC 14443 Type A", "pn532.fw.support.iso_iec_14443_type_a", FT_BOOLEAN, 8,
1800
14
          NULL, 0x01, NULL, HFILL}},
1801
14
        {&hf_pn532_14443a_uid,
1802
14
         {"ISO/IEC 14443-A UID", "pn532.iso.14443a.uid", FT_UINT64, BASE_HEX,
1803
14
          NULL, 0x0, NULL, HFILL}},
1804
14
        {&hf_pn532_sam_mode,
1805
14
         {"SAM Mode", "pn532.sam.mode", FT_UINT8, BASE_HEX,
1806
14
          VALS(pn532_sam_modes), 0x0, NULL, HFILL}},
1807
14
        {&hf_pn532_sam_timeout,
1808
14
         {"SAM Timeout", "pn532.sam.timeout", FT_UINT8, BASE_CUSTOM,
1809
14
          CF_FUNC(sam_timeout_base), 0x0, NULL, HFILL}},
1810
14
        {&hf_pn532_sam_irq,
1811
14
         {"SAM IRQ", "pn532.sam.irq", FT_UINT8, BASE_HEX,
1812
14
          NULL, 0x0, NULL, HFILL}},
1813
14
        {&hf_pn532_config,
1814
14
         {"Config Item", "pn532.config", FT_UINT8, BASE_HEX,
1815
14
          VALS(pn532_config_vals), 0x0, NULL, HFILL}},
1816
14
        {&hf_pn532_config_not_used,
1817
14
         {"Not used", "pn532.config.not_used", FT_UINT8, BASE_HEX,
1818
14
          NULL, 0xFC, NULL, HFILL}},
1819
14
        {&hf_pn532_config_auto_rfca,
1820
14
         {"Auto RFCA", "pn532.config.auto_rfca", FT_BOOLEAN, 8,
1821
14
          NULL, 0x02, NULL, HFILL}},
1822
14
        {&hf_pn532_config_rf,
1823
14
         {"RF", "pn532.config.rf", FT_BOOLEAN, 8,
1824
14
          NULL, 0x01, NULL, HFILL}},
1825
14
        {&hf_pn532_config_rfu,
1826
14
         {"RFU", "pn532.config.rfu", FT_UINT8, BASE_HEX,
1827
14
          NULL, 0x00, NULL, HFILL}},
1828
14
        {&hf_pn532_config_atr_res_timeout,
1829
14
         {"ATR Res Timeout", "pn532.config.atr_res_timeout", FT_UINT8, BASE_HEX,
1830
14
          VALS(pn532_config_timeout_vals), 0x00, NULL, HFILL}},
1831
14
        {&hf_pn532_config_timeout_non_dep,
1832
14
         {"TimeOut during non-DEP communications", "pn532.config.timeout_non_dep", FT_UINT8, BASE_HEX,
1833
14
          VALS(pn532_config_timeout_vals), 0x00, NULL, HFILL}},
1834
14
        {&hf_pn532_config_max_rty_com,
1835
14
         {"Max Retry COM", "pn532.config.max_rty_com", FT_UINT8, BASE_HEX,
1836
14
          NULL, 0x00, NULL, HFILL}},
1837
14
        {&hf_pn532_config_max_rty_atr,
1838
14
         {"Max Retry ATR", "pn532.config.max_rty_atr", FT_UINT8, BASE_DEC,
1839
14
          NULL, 0x00, NULL, HFILL}},
1840
14
        {&hf_pn532_config_max_rty_psl,
1841
14
         {"Max Retry PSL", "pn532.config.max_rty_psl", FT_UINT8, BASE_DEC,
1842
14
          NULL, 0x00, NULL, HFILL}},
1843
14
        {&hf_pn532_config_max_rty_passive_activation,
1844
14
         {"Max Retry Passive Activation", "pn532.config.max_rty_passive_activation", FT_UINT8, BASE_DEC,
1845
14
          NULL, 0x00, NULL, HFILL}},
1846
14
        {&hf_pn532_afi,
1847
14
         {"AFI", "pn532.afi", FT_UINT8, BASE_DEC,
1848
14
          NULL, 0x00, NULL, HFILL}},
1849
14
        {&hf_pn532_polling_method,
1850
14
         {"Polling Method", "pn532.polling_method", FT_UINT8, BASE_DEC,
1851
14
          VALS(pn532_polling_method_vals), 0x00, NULL, HFILL}},
1852
14
        {&hf_pn532_config_ciu_rf_cfg,
1853
14
         {"CIU RF Cfg", "pn532.ciu_rf_cfg", FT_UINT8, BASE_HEX,
1854
14
          NULL, 0x00, NULL, HFILL}},
1855
14
        {&hf_pn532_config_ciu_gs_n_on,
1856
14
         {"CIU GsN On", "pn532.ciu_gs_n_on", FT_UINT8, BASE_HEX,
1857
14
          NULL, 0x00, NULL, HFILL}},
1858
14
        {&hf_pn532_config_ciu_gs_n_off,
1859
14
         {"CIU GsN Off", "pn532.ciu_gs_n_off", FT_UINT8, BASE_HEX,
1860
14
          NULL, 0x00, NULL, HFILL}},
1861
14
        {&hf_pn532_config_ciu_cw_gs_p,
1862
14
         {"CIU CW GsP", "pn532.ciu_cw_gs_p", FT_UINT8, BASE_HEX,
1863
14
          NULL, 0x00, NULL, HFILL}},
1864
14
        {&hf_pn532_config_ciu_demon_rf_on,
1865
14
         {"CIU Demon when RF is On", "pn532.ciu_demon_rf_on", FT_UINT8, BASE_HEX,
1866
14
          NULL, 0x00, NULL, HFILL}},
1867
14
        {&hf_pn532_config_ciu_demon_rf_off,
1868
14
         {"CIU Demon when RF is Off", "pn532.ciu_demon_rf_off", FT_UINT8, BASE_HEX,
1869
14
          NULL, 0x00, NULL, HFILL}},
1870
14
        {&hf_pn532_config_ciu_rx_threshold,
1871
14
         {"CIU RX Threshold", "pn532.ciu_rx_threshold", FT_UINT8, BASE_HEX,
1872
14
          NULL, 0x00, NULL, HFILL}},
1873
14
        {&hf_pn532_config_ciu_mod_width,
1874
14
         {"CIU Mod Width", "pn532.ciu_mod_width", FT_UINT8, BASE_HEX,
1875
14
          NULL, 0x00, NULL, HFILL}},
1876
14
        {&hf_pn532_config_ciu_mod_gs_p,
1877
14
         {"CIU Mod GsP", "pn532.ciu_mod_gs_p", FT_UINT8, BASE_HEX,
1878
14
          NULL, 0x00, NULL, HFILL}},
1879
14
        {&hf_pn532_config_ciu_mif_nfc,
1880
14
         {"CIU Mif NFC", "pn532.ciu_mif_nfc", FT_UINT8, BASE_HEX,
1881
14
          NULL, 0x00, NULL, HFILL}},
1882
14
        {&hf_pn532_config_ciu_tx_bit_phase,
1883
14
         {"CIU TX Bit Phase", "pn532.ciu_tx_bit_phase", FT_UINT8, BASE_HEX,
1884
14
          NULL, 0x00, NULL, HFILL}},
1885
14
        {&hf_pn532_config_212_kbps,
1886
14
         {"212 kbps settings", "pn532.212_kbps", FT_UINT24, BASE_HEX,
1887
14
          NULL, 0x00, NULL, HFILL}},
1888
14
        {&hf_pn532_config_424_kbps,
1889
14
         {"424 kbps settings", "pn532.424_kbps", FT_UINT24, BASE_HEX,
1890
14
          NULL, 0x00, NULL, HFILL}},
1891
14
        {&hf_pn532_config_848_kbps,
1892
14
         {"848 kbps settings", "pn532.848_kbps", FT_UINT24, BASE_HEX,
1893
14
          NULL, 0x00, NULL, HFILL}},
1894
14
        {&hf_pn532_state,
1895
14
         {"State", "pn532.state", FT_UINT8, BASE_HEX,
1896
14
          VALS(pn532_state_vals), 0x00, NULL, HFILL}},
1897
14
        {&hf_pn532_brit_nu_7,
1898
14
         {"Not Used", "pn532.brit.not_used.7", FT_UINT8, BASE_HEX,
1899
14
          NULL, 0x80, NULL, HFILL}},
1900
14
        {&hf_pn532_brit_speed_initiator,
1901
14
         {"Speed Initiator", "pn532.brit.speed_initiator", FT_UINT8, BASE_HEX,
1902
14
          VALS(pn532_speed_vals), 0x70, NULL, HFILL}},
1903
14
        {&hf_pn532_brit_nu_3,
1904
14
         {"Not Used", "pn532.brit.not_used.3", FT_UINT8, BASE_HEX,
1905
14
          NULL, 0x08, NULL, HFILL}},
1906
14
        {&hf_pn532_brit_speed_target,
1907
14
         {"Speed Target", "pn532.brit.speed_target", FT_UINT8, BASE_HEX,
1908
14
          VALS(pn532_speed_vals), 0x07, NULL, HFILL}},
1909
14
        {&hf_pn532_tg_response,
1910
14
         {"TG Response", "pn532.tg_response", FT_BYTES, BASE_NONE,
1911
14
          NULL, 0x00, NULL, HFILL}},
1912
14
        {&hf_pn532_initiator_command,
1913
14
         {"Initiator Command", "pn532.initiator_command", FT_BYTES, BASE_NONE,
1914
14
          NULL, 0x00, NULL, HFILL}},
1915
14
        {&hf_pn532_data_out,
1916
14
         {"Data Out", "pn532.data_out", FT_BYTES, BASE_NONE,
1917
14
          NULL, 0x00, NULL, HFILL}},
1918
14
        {&hf_pn532_data_in,
1919
14
         {"Data In", "pn532.data_in", FT_BYTES, BASE_NONE,
1920
14
          NULL, 0x00, NULL, HFILL}},
1921
14
        {&hf_pn532_gt,
1922
14
         {"Gt", "pn532.gt", FT_BYTES, BASE_NONE,
1923
14
          NULL, 0x00, NULL, HFILL}},
1924
14
        {&hf_pn532_gi,
1925
14
         {"Gi", "pn532.gi", FT_BYTES, BASE_NONE,
1926
14
          NULL, 0x00, NULL, HFILL}},
1927
14
        {&hf_pn532_mode_nu_3_7,
1928
14
         {"Not Used", "pn532.mode.not_used.3_7", FT_UINT8, BASE_HEX,
1929
14
          NULL, 0xF8, NULL, HFILL}},
1930
14
        {&hf_pn532_mode_picc_only,
1931
14
         {"PICC Only", "pn532.mode.picc_only", FT_BOOLEAN, 8,
1932
14
          NULL, 0x04, NULL, HFILL}},
1933
14
        {&hf_pn532_mode_dep_only,
1934
14
         {"DEP Only", "pn532.mode.dep_only", FT_BOOLEAN, 8,
1935
14
          NULL, 0x02, NULL, HFILL}},
1936
14
        {&hf_pn532_mode_passive_only,
1937
14
         {"Passive Only", "pn532.mode.passive_only", FT_BOOLEAN, 8,
1938
14
          NULL, 0x01, NULL, HFILL}},
1939
14
        {&hf_pn532_mode_mifare_parameters,
1940
14
         {"Mifare Parameters", "pn532.mode.mifare_parameters", FT_NONE, BASE_NONE,
1941
14
          NULL, 0x00, NULL, HFILL}},
1942
14
        {&hf_pn532_mode_mifare_parameters_sens_res,
1943
14
         {"SENS RES", "pn532.mode.mifare_parameters.sens_res", FT_UINT16, BASE_HEX,
1944
14
          NULL, 0x00, NULL, HFILL}},
1945
14
        {&hf_pn532_mode_mifare_parameters_nfc_id_1t,
1946
14
         {"NFC ID 1t", "pn532.mode.mifare_parameters.nfc_id_1t", FT_BYTES, BASE_NONE,
1947
14
          NULL, 0x00, NULL, HFILL}},
1948
14
        {&hf_pn532_mode_mifare_parameters_sel_res,
1949
14
         {"SEL RES", "pn532.mode.mifare_parameters.sel_res", FT_UINT8, BASE_HEX,
1950
14
          NULL, 0x00, NULL, HFILL}},
1951
14
        {&hf_pn532_mode_felica_parameters,
1952
14
         {"FeliCA Parameters", "pn532.mode.felica_parameters", FT_NONE, BASE_NONE,
1953
14
          NULL, 0x00, NULL, HFILL}},
1954
14
        {&hf_pn532_mode_felica_parameters_nfc_id_2t,
1955
14
         {"NFC ID 2t", "pn532.mode.felica_parameters.nfc_id_2t", FT_BYTES, BASE_NONE,
1956
14
          NULL, 0x00, NULL, HFILL}},
1957
14
        {&hf_pn532_mode_felica_parameters_pad,
1958
14
         {"Pad", "pn532.mode.felica_parameters.pad", FT_BYTES, BASE_NONE,
1959
14
          NULL, 0x00, NULL, HFILL}},
1960
14
        {&hf_pn532_mode_felica_parameters_system_code,
1961
14
         {"System Code", "pn532.mode.felica_parameters.system_code", FT_UINT16, BASE_HEX,
1962
14
          NULL, 0x00, NULL, HFILL}},
1963
14
        {&hf_pn532_mode_nfc_id_3t,
1964
14
         {"NFC ID 3t", "pn532.mode.nfc_id_3t", FT_BYTES, BASE_NONE,
1965
14
          NULL, 0x00, NULL, HFILL}},
1966
14
        {&hf_pn532_mode_gt,
1967
14
         {"Gt", "pn532.mode.gt", FT_BYTES, BASE_NONE,
1968
14
          NULL, 0x00, NULL, HFILL}},
1969
14
        {&hf_pn532_mode_gt_length,
1970
14
         {"Gt Length", "pn532.mode.gt.length", FT_UINT8, BASE_DEC,
1971
14
          NULL, 0x00, NULL, HFILL}},
1972
14
        {&hf_pn532_mode_tk,
1973
14
         {"Tk", "pn532.mode.tk", FT_BYTES, BASE_NONE,
1974
14
          NULL, 0x00, NULL, HFILL}},
1975
14
        {&hf_pn532_mode_tk_length,
1976
14
         {"Tk Length", "pn532.mode.tk.length", FT_UINT8, BASE_DEC,
1977
14
          NULL, 0x00, NULL, HFILL}},
1978
14
        {&hf_pn532_mode_nu_7,
1979
14
         {"Not Used", "pn532.mode.not_used.7", FT_BOOLEAN, 8,
1980
14
          NULL, 0x80, NULL, HFILL}},
1981
14
        {&hf_pn532_mode_baudrate,
1982
14
         {"Baudrate", "pn532.mode.baudrate", FT_UINT8, BASE_HEX,
1983
14
          VALS(pn532_speed_vals), 0x70, NULL, HFILL}},
1984
14
        {&hf_pn532_mode_iso_iec_14443_4_picc,
1985
14
         {"ISO/IEC 14443-4 PICC", "pn532.mode.iso_iec_14443_4_picc", FT_BOOLEAN, 8,
1986
14
          NULL, 0x08, NULL, HFILL}},
1987
14
        {&hf_pn532_mode_dep,
1988
14
         {"DEP", "pn532.mode.dep", FT_BOOLEAN, 8,
1989
14
          NULL, 0x04, NULL, HFILL}},
1990
14
        {&hf_pn532_mode_framing_type,
1991
14
         {"Framing Type", "pn532.mode.framing_type", FT_UINT8, BASE_HEX,
1992
14
          VALS(pn532_framing_type_vals), 0x03, NULL, HFILL}},
1993
14
        {&hf_pn532_brit,
1994
14
         {"BRit", "pn532.brit", FT_UINT8, BASE_HEX,
1995
14
          VALS(pn532_speed_vals), 0x00, NULL, HFILL}},
1996
14
        {&hf_pn532_brti,
1997
14
         {"BRti", "pn532.brti", FT_UINT8, BASE_HEX,
1998
14
          VALS(pn532_speed_vals), 0x00, NULL, HFILL}},
1999
14
        {&hf_pn532_txmode_nu_7,
2000
14
         {"Not Used", "pn532.txmode.not_used.7", FT_BOOLEAN, 8,
2001
14
          NULL, 0x80, NULL, HFILL}},
2002
14
        {&hf_pn532_txmode_tx_speed,
2003
14
         {"Tx Speed", "pn532.txmode.txspeed", FT_UINT8, BASE_HEX,
2004
14
          VALS(pn532_txspeed_vals), 0x70, NULL, HFILL}},
2005
14
        {&hf_pn532_txmode_nu_2_3,
2006
14
         {"Not Used", "pn532.txmode.not_used.2_3", FT_UINT8, BASE_HEX,
2007
14
          NULL, 0xC0, NULL, HFILL}},
2008
14
        {&hf_pn532_txmode_tx_framing,
2009
14
         {"Tx Framing", "pn532.txmode.tx_framing", FT_UINT8, BASE_HEX,
2010
14
          VALS(pn532_txframing_vals), 0x03, NULL, HFILL}},
2011
14
        {&hf_pn532_baudrate,
2012
14
         {"Baudrate", "pn532.baudrate", FT_UINT8, BASE_HEX,
2013
14
          VALS(pn532_baudrate_vals), 0x00, NULL, HFILL}},
2014
14
        {&hf_pn532_flags,
2015
14
         {"Flags", "pn532.flags", FT_UINT8, BASE_HEX,
2016
14
          NULL, 0x00, NULL, HFILL}},
2017
14
        {&hf_pn532_flags_rfu_7,
2018
14
         {"RFU", "pn532.flags.rfu.7", FT_BOOLEAN, 8,
2019
14
          NULL, 0x80, NULL, HFILL}},
2020
14
        {&hf_pn532_flags_remove_preamble_and_postamble,
2021
14
         {"Remove Preamble and Postamble", "pn532.flags.remove_preamble_and_postamble", FT_BOOLEAN, 8,
2022
14
          NULL, 0x40, NULL, HFILL}},
2023
14
        {&hf_pn532_flags_iso_14443_4_picc_emulation,
2024
14
         {"ISO 14443-4 PICC Emulation", "pn532.flags.iso_14443_4_picc_emulation", FT_BOOLEAN, 8,
2025
14
          NULL, 0x20, NULL, HFILL}},
2026
14
        {&hf_pn532_flags_automatic_rats,
2027
14
         {"Automatic RATS", "pn532.flags.automatic_rats", FT_BOOLEAN, 8,
2028
14
          NULL, 0x10, NULL, HFILL}},
2029
14
        {&hf_pn532_flags_rfu_3,
2030
14
         {"RFU", "pn532.flags.rfu.3", FT_BOOLEAN, 8,
2031
14
          NULL, 0x08, NULL, HFILL}},
2032
14
        {&hf_pn532_flags_automatic_atr_res,
2033
14
         {"Automatic ATR RES", "pn532.flags.automatic_atr_res", FT_BOOLEAN, 8,
2034
14
          NULL, 0x04, NULL, HFILL}},
2035
14
        {&hf_pn532_flags_did_used,
2036
14
         {"DID Used", "pn532.flags.did_used", FT_BOOLEAN, 8,
2037
14
          NULL, 0x02, NULL, HFILL}},
2038
14
        {&hf_pn532_flags_nad_used,
2039
14
         {"NAD Used", "pn532.flags.nad_used", FT_BOOLEAN, 8,
2040
14
          NULL, 0x01, NULL, HFILL}},
2041
14
        {&hf_pn532_wakeup_enable,
2042
14
         {"Wakeup Enable", "pn532.wakeup_enable", FT_UINT8, BASE_HEX,
2043
14
          NULL, 0x00, NULL, HFILL}},
2044
14
        {&hf_pn532_target,
2045
14
         {"Target", "pn532.target", FT_NONE, BASE_NONE,
2046
14
          NULL, 0x00, NULL, HFILL}},
2047
14
        {&hf_pn532_generate_irq,
2048
14
         {"Generate IRQ", "pn532.generate_irq", FT_UINT8, BASE_HEX,
2049
14
          NULL, 0x00, NULL, HFILL}},
2050
14
        {&hf_pn532_register_address,
2051
14
         {"Register Address", "pn532.register.address", FT_UINT16, BASE_HEX,
2052
14
          NULL, 0x00, NULL, HFILL}},
2053
14
        {&hf_pn532_register_value,
2054
14
         {"Register Value", "pn532.register.value", FT_UINT8, BASE_HEX,
2055
14
          NULL, 0x00, NULL, HFILL}},
2056
14
        {&hf_pn532_field,
2057
14
         {"Field", "pn532.field", FT_BOOLEAN, BASE_NONE,
2058
14
          TFS(&tfs_present_not_present), 0x00, "Field indicates if an external RF field is present and detected by the PN532", HFILL}},
2059
14
        {&hf_pn532_brrx,
2060
14
         {"Baudrate Rx", "pn532.brrx", FT_UINT8, BASE_HEX,
2061
14
          VALS(pn532_speed_vals), 0x00, NULL, HFILL}},
2062
14
        {&hf_pn532_brtx,
2063
14
         {"Baudrate Tx", "pn532.brtx", FT_UINT8, BASE_HEX,
2064
14
          VALS(pn532_speed_vals), 0x00, NULL, HFILL}},
2065
14
        {&hf_pn532_type,
2066
14
         {"Type", "pn532.type", FT_UINT8, BASE_HEX,
2067
14
          VALS(pn532_type_vals), 0x00, NULL, HFILL}},
2068
14
        {&hf_pn532_sam_status,
2069
14
         {"SAM Status", "pn532.sam.status", FT_UINT8, BASE_HEX,
2070
14
          NULL, 0x00, NULL, HFILL}},
2071
14
        {&hf_pn532_wakeup_enable_i2c,
2072
14
         {"I2C", "pn532.wakeup_enable.i2c", FT_BOOLEAN, 8,
2073
14
          NULL, 0x80, NULL, HFILL}},
2074
14
        {&hf_pn532_wakeup_enable_gpio,
2075
14
         {"GPIO", "pn532.wakeup_enable.gpio", FT_BOOLEAN, 8,
2076
14
          NULL, 0x40, NULL, HFILL}},
2077
14
        {&hf_pn532_wakeup_enable_spi,
2078
14
         {"SPI", "pn532.wakeup_enable.spi", FT_BOOLEAN, 8,
2079
14
          NULL, 0x20, NULL, HFILL}},
2080
14
        {&hf_pn532_wakeup_enable_hsu,
2081
14
         {"HSU", "pn532.wakeup_enable.hsu", FT_BOOLEAN, 8,
2082
14
          NULL, 0x10, NULL, HFILL}},
2083
14
        {&hf_pn532_wakeup_enable_rf_level_detector,
2084
14
         {"RF Level Detector", "pn532.wakeup_enable.rf_level_detector", FT_BOOLEAN, 8,
2085
14
          NULL, 0x08, NULL, HFILL}},
2086
14
        {&hf_pn532_wakeup_enable_rfu_2,
2087
14
         {"RFU", "pn532.wakeup_enable.rfu_2", FT_BOOLEAN, 8,
2088
14
          NULL, 0x04, NULL, HFILL}},
2089
14
        {&hf_pn532_wakeup_enable_int_1,
2090
14
         {"I2C", "pn532.wakeup_enable.int.1", FT_BOOLEAN, 8,
2091
14
          NULL, 0x02, NULL, HFILL}},
2092
14
        {&hf_pn532_wakeup_enable_int_0,
2093
14
         {"I2C", "pn532.wakeup_enable.int.0", FT_BOOLEAN, 8,
2094
14
          NULL, 0x01, NULL, HFILL}},
2095
14
        {&hf_pn532_gpio_ioi1,
2096
14
         {"GPIO IOI1", "pn532.gpio.ioi1", FT_UINT8, BASE_HEX,
2097
14
          NULL, 0xFF, NULL, HFILL}},
2098
14
        {&hf_pn532_gpio_p3,
2099
14
         {"GPIO P3", "pn532.gpio.p3", FT_UINT8, BASE_HEX,
2100
14
          NULL, 0xFF, NULL, HFILL}},
2101
14
        {&hf_pn532_gpio_p7,
2102
14
         {"GPIO P7", "pn532.gpio.p7", FT_UINT8, BASE_HEX,
2103
14
          NULL, 0xFF, NULL, HFILL}},
2104
14
        {&hf_pn532_poll_number,
2105
14
         {"Poll Number", "pn532.poll_number", FT_UINT8, BASE_DEC,
2106
14
          NULL, 0x00, NULL, HFILL}},
2107
14
        {&hf_pn532_period,
2108
14
         {"Period", "pn532.period", FT_UINT8, BASE_DEC,
2109
14
          NULL, 0x00, NULL, HFILL}},
2110
14
        {&hf_pn532_autopoll_type,
2111
14
         {"Type", "pn532.autopoll_type", FT_UINT8, BASE_HEX,
2112
14
          NULL, 0x00, NULL, HFILL}},
2113
14
        {&hf_pn532_target_data,
2114
14
         {"Target Data", "pn532.target_data", FT_BYTES, BASE_NONE,
2115
14
          NULL, 0x00, NULL, HFILL}},
2116
14
        {&hf_pn532_target_data_length,
2117
14
         {"Target Data Length", "pn532.target_data.length", FT_UINT8, BASE_DEC,
2118
14
          NULL, 0x00, NULL, HFILL}},
2119
14
        {&hf_pn532_autopoll_type_act,
2120
14
         {"Active Mode", "pn532.autopoll_type.active", FT_BOOLEAN, 8,
2121
14
          NULL, 0x80, NULL, HFILL}},
2122
14
        {&hf_pn532_autopoll_type_dep,
2123
14
         {"DEP", "pn532.autopoll_type.dep", FT_BOOLEAN, 8,
2124
14
          NULL, 0x40, NULL, HFILL}},
2125
14
        {&hf_pn532_autopoll_type_tcl,
2126
14
         {"TCL", "pn532.autopoll_type.tcl", FT_BOOLEAN, 8,
2127
14
          NULL, 0x20, NULL, HFILL}},
2128
14
        {&hf_pn532_autopoll_type_mf_fe,
2129
14
         {"Mf_Fe", "pn532.autopoll_type.mf_fe", FT_BOOLEAN, 8,
2130
14
          NULL, 0x10, NULL, HFILL}},
2131
14
        {&hf_pn532_autopoll_type_not_used,
2132
14
         {"Not used", "pn532.autopoll_type.not_used", FT_BOOLEAN, 8,
2133
14
          NULL, 0x08, NULL, HFILL}},
2134
14
        {&hf_pn532_autopoll_type_baudrate_and_modulation,
2135
14
         {"Baudrate and Modulation", "pn532.autopoll_type.baudrate_and_modulation", FT_UINT8, BASE_HEX,
2136
14
          VALS(pn532_brtypes), 0x07, NULL, HFILL}},
2137
14
        {&hf_pn532_nfc_id_3i,
2138
14
         {"NFC ID 3i", "pn532.nfc_id_3i", FT_BYTES, BASE_NONE,
2139
14
          NULL, 0x00, NULL, HFILL}},
2140
14
        {&hf_pn532_next_not_used_2_7,
2141
14
         {"Not Used", "pn532.next.not_used.2_7", FT_BOOLEAN, 8,
2142
14
          NULL, 0xFC, NULL, HFILL}},
2143
14
        {&hf_pn532_next_gi,
2144
14
         {"Gi", "pn532.next.gi", FT_BOOLEAN, 8,
2145
14
          TFS(&tfs_present_not_present), 0x02, NULL, HFILL}},
2146
14
        {&hf_pn532_next_nfc_id_3i,
2147
14
         {"NFC ID 3i", "pn532.next.nfc_id_3i", FT_BOOLEAN, 8,
2148
14
          TFS(&tfs_present_not_present), 0x01, NULL, HFILL}},
2149
14
        {&hf_pn532_nfc_id_3t,
2150
14
         {"NFC ID 3t", "pn532.nfc_id_3t", FT_BYTES, BASE_NONE,
2151
14
          NULL, 0x00, NULL, HFILL}},
2152
14
        {&hf_pn532_communication_mode,
2153
14
         {"Communication Mode", "pn532.communication_mode", FT_UINT8, BASE_HEX,
2154
14
          VALS(pn532_communication_mode_vals), 0x00, NULL, HFILL}},
2155
14
        {&hf_pn532_activation_baudrate,
2156
14
         {"Baudrate", "pn532.activation_baudrate", FT_UINT8, BASE_HEX,
2157
14
          VALS(pn532_speed_vals), 0x70, NULL, HFILL}},
2158
14
        {&hf_pn532_jump_next_not_used_3_7,
2159
14
         {"Not Used", "pn532.jump_next.not_used.3_7", FT_BOOLEAN, 8,
2160
14
          NULL, 0xF8, NULL, HFILL}},
2161
14
        {&hf_pn532_jump_next_gi,
2162
14
         {"Gi", "pn532.jump_next.gi", FT_BOOLEAN, 8,
2163
14
          TFS(&tfs_present_not_present), 0x04, NULL, HFILL}},
2164
14
        {&hf_pn532_jump_next_nfc_id_3i,
2165
14
         {"NFC ID 3i", "pn532.jump_next.nfc_id_3i", FT_BOOLEAN, 8,
2166
14
          TFS(&tfs_present_not_present), 0x02, NULL, HFILL}},
2167
14
        {&hf_pn532_jump_next_passive_initiator_data,
2168
14
         {"Passive Initiator Data", "pn532.jump_next.passive_initiator_data", FT_BOOLEAN, 8,
2169
14
          TFS(&tfs_present_not_present), 0x01, NULL, HFILL}},
2170
14
        {&hf_pn532_passive_initiator_data,
2171
14
         {"Passive Initiator Data", "pn532.passive_initiator_data", FT_BYTES, BASE_NONE,
2172
14
          NULL, 0x00, NULL, HFILL}},
2173
14
        {&hf_pn532_did_target,
2174
14
         {"DID Target", "pn532.did_target", FT_UINT8, BASE_HEX_DEC,
2175
14
          NULL, 0x00, NULL, HFILL}},
2176
14
        {&hf_pn532_send_bit_rate_target,
2177
14
         {"Send Bit Rate Target", "pn532.send_bit_rate_target", FT_UINT8, BASE_DEC_HEX,
2178
14
          NULL, 0x00, NULL, HFILL}},
2179
14
        {&hf_pn532_receive_bit_rate_target,
2180
14
         {"Receive Bit Rate Target", "pn532.receive_bit_rate_target", FT_UINT8, BASE_DEC_HEX,
2181
14
          NULL, 0x00, NULL, HFILL}},
2182
14
        {&hf_pn532_timeout,
2183
14
         {"Timeout", "pn532.timeout", FT_UINT8, BASE_DEC_HEX,
2184
14
          NULL, 0x00, NULL, HFILL}},
2185
14
        {&hf_pn532_optional_parameters,
2186
14
         {"Optional Parameters", "pn532.optional_parameters", FT_UINT8, BASE_HEX,
2187
14
          NULL, 0x00, NULL, HFILL}},
2188
14
        {&hf_pn532_test_number,
2189
14
         {"Test Number", "pn532.test_number", FT_UINT8, BASE_HEX,
2190
14
          VALS(pn532_test_number_vals), 0x00, NULL, HFILL}},
2191
14
        {&hf_pn532_parameters,
2192
14
         {"Parameters", "pn532.diagnose_parameters", FT_BYTES, BASE_NONE,
2193
14
          NULL, 0x00, NULL, HFILL}},
2194
14
        {&hf_pn532_parameters_length,
2195
14
         {"Parameters Length", "pn532.diagnose_parameters.length", FT_UINT8, BASE_DEC,
2196
14
          NULL, 0x00, NULL, HFILL}},
2197
14
        {&hf_pn532_sens_res,
2198
14
         {"SENS RES", "pn532.sens_res", FT_UINT16, BASE_HEX,
2199
14
          NULL, 0x00, NULL, HFILL}},
2200
14
        {&hf_pn532_sel_res,
2201
14
         {"SEL RES", "pn532.sel_res", FT_UINT8, BASE_HEX,
2202
14
          NULL, 0x00, NULL, HFILL}},
2203
14
        {&hf_pn532_nfc_id_length,
2204
14
         {"NFC ID Length", "pn532.nfc_id_length", FT_UINT8, BASE_DEC,
2205
14
          NULL, 0x00, NULL, HFILL}},
2206
14
        {&hf_pn532_nfc_id_1,
2207
14
         {"NFC ID 1", "pn532.nfc_id_1", FT_BYTES, BASE_NONE,
2208
14
          NULL, 0x00, NULL, HFILL}},
2209
14
        {&hf_pn532_ats_length,
2210
14
         {"ATS Length", "pn532.ats_length", FT_UINT8, BASE_DEC,
2211
14
          NULL, 0x00, NULL, HFILL}},
2212
14
        {&hf_pn532_ats,
2213
14
         {"ATS", "pn532.ats", FT_BYTES, BASE_NONE,
2214
14
          NULL, 0x00, NULL, HFILL}},
2215
14
        {&hf_pn532_pol_res_length,
2216
14
         {"POL RES Length", "pn532.pol_res_length", FT_UINT8, BASE_DEC,
2217
14
          NULL, 0x00, NULL, HFILL}},
2218
14
        {&hf_pn532_response_code,
2219
14
         {"Response Code", "pn532.response_code", FT_UINT8, BASE_HEX,
2220
14
          NULL, 0x00, NULL, HFILL}},
2221
14
        {&hf_pn532_nfc_id_2t,
2222
14
         {"NFC ID 2t", "pn532.nfc_id_2t", FT_BYTES, BASE_NONE,
2223
14
          NULL, 0x00, NULL, HFILL}},
2224
14
        {&hf_pn532_pad,
2225
14
         {"Pad", "pn532.pad", FT_BYTES, BASE_NONE,
2226
14
          NULL, 0x00, NULL, HFILL}},
2227
14
        {&hf_pn532_syst_code,
2228
14
         {"Syst Code", "pn532.syst_code", FT_UINT16, BASE_HEX,
2229
14
          NULL, 0x00, NULL, HFILL}},
2230
14
        {&hf_pn532_atqb_response,
2231
14
         {"ATQB Response", "pn532.atqb_response", FT_BYTES, BASE_NONE,
2232
14
          NULL, 0x00, NULL, HFILL}},
2233
14
        {&hf_pn532_attrib_res_length,
2234
14
         {"Attrib RES Length", "pn532.attrib_res_length", FT_UINT8, BASE_DEC,
2235
14
          NULL, 0x00, NULL, HFILL}},
2236
14
        {&hf_pn532_attrib_res,
2237
14
         {"Attrib RES", "pn532.attrib_res", FT_BYTES, BASE_NONE,
2238
14
          NULL, 0x00, NULL, HFILL}},
2239
14
        {&hf_pn532_jewel_id,
2240
14
         {"Jewel ID", "pn532.jewel_id", FT_BYTES, BASE_NONE,
2241
14
          NULL, 0x00, NULL, HFILL}},
2242
14
        {&hf_pn532_response_for,
2243
14
         { "Response for", "pn532.response_for", FT_FRAMENUM, BASE_NONE,
2244
14
          NULL, 0x00, NULL, HFILL}},
2245
14
        {&hf_pn532_diagnose_baudrate,
2246
14
         {"Diagnose Baudrate", "pn532.diagnose_baudrate", FT_UINT8, BASE_HEX,
2247
14
          VALS(pn532_diagnose_baudrate_vals), 0x00, NULL, HFILL}},
2248
14
        {&hf_pn532_reply_delay,
2249
14
         {"Reply Delay", "pn532.sam.reply_delay", FT_UINT8, BASE_CUSTOM,
2250
14
          CF_FUNC(replay_delay_base), 0x0, NULL, HFILL}},
2251
14
        {&hf_pn532_ciu_tx_mode,
2252
14
         {"CIU Tx Mode", "pn532.ciu_tx_mode", FT_UINT8, BASE_HEX,
2253
14
          NULL, 0x00, NULL, HFILL}},
2254
14
        {&hf_pn532_ciu_rx_mode,
2255
14
         {"CIU Rx Mode", "pn532.ciu_rx_mode", FT_UINT8, BASE_HEX,
2256
14
          NULL, 0x00, NULL, HFILL}},
2257
14
        {&hf_pn532_diagnose_number_of_fails,
2258
14
         {"Number of Fails", "pn532.number_of_fails", FT_UINT8, BASE_DEC,
2259
14
          NULL, 0x00, NULL, HFILL}},
2260
14
        {&hf_pn532_diagnose_result,
2261
14
         {"Result", "pn532.result", FT_BOOLEAN, BASE_NONE,
2262
14
          TFS(&tfs_ok_error), 0x00, NULL, HFILL}},
2263
14
        {&hf_pn532_andet_bot,
2264
14
         {"Andet Bot", "pn532.andet.bot", FT_BOOLEAN, 8,
2265
14
          NULL, 0x80, NULL, HFILL}},
2266
14
        {&hf_pn532_andet_up,
2267
14
         {"Andet Up", "pn532.andet.up", FT_BOOLEAN, 8,
2268
14
          NULL, 0x40, NULL, HFILL}},
2269
14
        {&hf_pn532_andet_ith,
2270
14
         {"Andet Ith", "pn532.andet.ith", FT_BOOLEAN, 8,
2271
14
          NULL, 0x3E, NULL, HFILL}},
2272
14
        {&hf_pn532_andet_en,
2273
14
         {"Andet En", "pn532.andet.en", FT_BOOLEAN, 8,
2274
14
          NULL, 0x01, NULL, HFILL}}
2275
14
    };
2276
2277
14
    static ei_register_info ei[] = {
2278
14
        { &ei_unknown_data,    { "pn532.expert.unknown_data",    PI_PROTOCOL, PI_NOTE, "Unknown data", EXPFILL }},
2279
14
        { &ei_unexpected_data, { "pn532.expert.unexpected_data", PI_PROTOCOL, PI_WARN, "Unexpected data", EXPFILL }},
2280
14
    };
2281
2282
14
    static int *ett[] = {
2283
14
        &ett_pn532,
2284
14
        &ett_pn532_flags,
2285
14
        &ett_pn532_target,
2286
14
        &ett_pn532_fw_support,
2287
14
        &ett_pn532_config_212_kbps,
2288
14
        &ett_pn532_config_424_kbps,
2289
14
        &ett_pn532_config_848_kbps,
2290
14
        &ett_pn532_mifare_parameters,
2291
14
        &ett_pn532_felica_parameters,
2292
14
        &ett_pn532_wakeup_enable,
2293
14
        &ett_pn532_autopoll_type
2294
14
    };
2295
2296
14
    static const enum_val_t sub_enum_vals[] = {
2297
14
        { "data",    "Data",        SUB_DATA    },
2298
14
        { "felica",  "Sony FeliCa", SUB_FELICA  },
2299
14
        { "mifare",  "NXP MiFare",  SUB_MIFARE  },
2300
14
        { "iso7816", "ISO 7816",    SUB_ISO7816 },
2301
14
        { NULL, NULL, 0 }
2302
14
    };
2303
2304
14
    command_info = wmem_tree_new_autoreset(wmem_epan_scope(), wmem_file_scope());
2305
2306
14
    proto_pn532 = proto_register_protocol("NXP PN532", "PN532", "pn532");
2307
14
    proto_register_field_array(proto_pn532, hf, array_length(hf));
2308
14
    proto_register_subtree_array(ett, array_length(ett));
2309
2310
14
    expert_pn532 = expert_register_protocol(proto_pn532);
2311
14
    expert_register_field_array(expert_pn532, ei, array_length(ei));
2312
2313
14
    pref_mod = prefs_register_protocol(proto_pn532, NULL);
2314
14
    prefs_register_static_text_preference(pref_mod, "version",
2315
14
            "PN532 protocol version is based on: \"UM0701-02; PN532 User Manual\"",
2316
14
            "Version of protocol supported by this dissector.");
2317
14
    prefs_register_enum_preference(pref_mod, "prtype532", "Payload Type", "Protocol payload type",
2318
14
        &sub_selected, sub_enum_vals, false);
2319
2320
14
    pn532_handle = register_dissector("pn532", dissect_pn532, proto_pn532);
2321
14
}
2322
2323
/* Handler registration */
2324
void proto_reg_handoff_pn532(void)
2325
14
{
2326
14
    dissector_add_for_decode_as("usbccid.subdissector", pn532_handle);
2327
2328
14
    sub_handles[SUB_DATA] = find_dissector("data");
2329
14
    sub_handles[SUB_FELICA] = find_dissector_add_dependency("felica", proto_pn532);
2330
14
    sub_handles[SUB_MIFARE] = find_dissector_add_dependency("mifare", proto_pn532);
2331
14
    sub_handles[SUB_ISO7816] = find_dissector_add_dependency("iso7816", proto_pn532);
2332
14
}
2333
2334
/*
2335
 * Editor modelines - https://www.wireshark.org/tools/modelines.html
2336
 *
2337
 * Local variables:
2338
 * c-basic-offset: 4
2339
 * tab-width: 8
2340
 * indent-tabs-mode: nil
2341
 * End:
2342
 *
2343
 * ex: set shiftwidth=4 tabstop=8 expandtab:
2344
 * :indentSize=4:tabSize=8:noTabs=true:
2345
 */