/* packet-nvme-mi-mi.c

 * NVMe-MI MI Command dissector (NMIMT=1, NVMe-MI 2.1 §5)

 * Copyright 2026, Brandon Chiu

 *

 * Wireshark - Network traffic analyzer

 * By Gerald Combs <gerald@wireshark.org>

 * Copyright 1998 Gerald Combs

 *

 * SPDX-License-Identifier: GPL-2.0-or-later

 */

/* Reference: NVM Express Management Interface specification

 * https://nvmexpress.org/specification/nvme-mi-specification/

 *

 * Decodes the Management Interface Command Set request dwords (NMD0/NMD1),

 * the command-specific NVMe Management Response field, and the Response Data

 * structures for opcodes 00h-04h.  Opcodes 05h-0Ch are named but their

 * bodies are rendered as raw dwords/data until fixtures exist for them.

 */

#include <config.h>

#include <epan/expert.h>

#include <epan/packet.h>

#include <epan/tfs.h>

#include <wsutil/array.h>

#include <wsutil/utf8_entities.h>

#include "packet-nvme.h"

#include "packet-nvme-mi.h"

void proto_register_nvme_mi_mi(void);

void proto_reg_handoff_nvme_mi_mi(void);

static int proto_nvme_mi_mi;

static dissector_handle_t nvme_mi_mi_handle;

static int hf_nvme_mi_mi_opcode;

static int hf_nvme_mi_mi_cdw0;

static int hf_nvme_mi_mi_cdw1;

static int hf_nvme_mi_mi_status;

static int hf_nvme_mi_mi_nmresp;

static int hf_nvme_mi_mi_data;

/* Read NVMe-MI Data Structure (00h) */

static int hf_nvme_mi_mi_rds_dtyp;

static int hf_nvme_mi_mi_rds_portid;

static int hf_nvme_mi_mi_rds_ctrlid;

static int hf_nvme_mi_mi_rds_iocsi;

static int hf_nvme_mi_mi_rds_rdl;

/* NVM Subsystem Health Status Poll (01h) */

static int hf_nvme_mi_mi_nshsp_cs;

/* Controller Health Status Poll (02h) */

static int hf_nvme_mi_mi_chsp_all;

static int hf_nvme_mi_mi_chsp_incvf;

static int hf_nvme_mi_mi_chsp_incpf;

static int hf_nvme_mi_mi_chsp_incf;

static int hf_nvme_mi_mi_chsp_maxrent;

static int hf_nvme_mi_mi_chsp_sctlid;

static int hf_nvme_mi_mi_chsp_ccf;

static int hf_nvme_mi_mi_chsp_cwarn;

static int hf_nvme_mi_mi_chsp_spare;

static int hf_nvme_mi_mi_chsp_pdlu;

static int hf_nvme_mi_mi_chsp_ctemp;

static int hf_nvme_mi_mi_chsp_csts;

static int hf_nvme_mi_mi_chsp_rent;

/* Configuration Set (03h) / Configuration Get (04h) */

static int hf_nvme_mi_mi_cfg_cid;

static int hf_nvme_mi_mi_cfg_portid;

static int hf_nvme_mi_mi_cfg_sfreq;

static int hf_nvme_mi_mi_cfg_mtus;

static int hf_nvme_mi_mi_cfg_sfreq_cur;

static int hf_nvme_mi_mi_cfg_mtus_cur;

static int hf_nvme_mi_mi_cfg_aeelver;

/* Health Status Change clear-selection bits (Configuration Set, NMD1) */

static int hf_nvme_mi_mi_cfg_hsc_tcida;

static int hf_nvme_mi_mi_cfg_hsc_cwarn;

static int hf_nvme_mi_mi_cfg_hsc_spare;

static int hf_nvme_mi_mi_cfg_hsc_pdlu;

static int hf_nvme_mi_mi_cfg_hsc_ctemp;

static int hf_nvme_mi_mi_cfg_hsc_cschng;

static int hf_nvme_mi_mi_cfg_hsc_fa;

static int hf_nvme_mi_mi_cfg_hsc_nac;

static int hf_nvme_mi_mi_cfg_hsc_ceco;

static int hf_nvme_mi_mi_cfg_hsc_nssro;

static int hf_nvme_mi_mi_cfg_hsc_shst;

static int hf_nvme_mi_mi_cfg_hsc_cfs;

static int hf_nvme_mi_mi_cfg_hsc_rdy;

/* VPD Read (05h) / VPD Write (06h) — shared layout */

static int hf_nvme_mi_mi_vpd_dofst;

static int hf_nvme_mi_mi_vpd_dlen;

static int hf_nvme_mi_mi_vpd_data;

/* Configuration Set (03h) Asynchronous Event — request dword 0

 * and the AE Enable List request data */

static int hf_nvme_mi_mi_cfg_ae_envfa;

static int hf_nvme_mi_mi_cfg_ae_enpfa;

static int hf_nvme_mi_mi_cfg_ae_encfa;

static int hf_nvme_mi_mi_cfg_ae_aemd;

static int hf_nvme_mi_mi_cfg_ae_aerd;

static int hf_nvme_mi_mi_ae;

static int hf_nvme_mi_mi_ae_numaee;

static int hf_nvme_mi_mi_ae_aeelver;

static int hf_nvme_mi_mi_ae_aeetl;

static int hf_nvme_mi_mi_ae_aeelhl;

static int hf_nvme_mi_mi_ae_entry;

static int hf_nvme_mi_mi_ae_aeel;

static int hf_nvme_mi_mi_ae_aee;

static int hf_nvme_mi_mi_ae_id;

/* Configuration Get (04h) Asynchronous Event — AE Supported List response

 * data; same shape as the AE Enable List, different names. */

static int hf_nvme_mi_mi_aes;

static int hf_nvme_mi_mi_aes_numaes;

static int hf_nvme_mi_mi_aes_aeslver;

static int hf_nvme_mi_mi_aes_aestl;

static int hf_nvme_mi_mi_aes_aeslhl;

static int hf_nvme_mi_mi_aes_entry;

static int hf_nvme_mi_mi_aes_aesl;

static int hf_nvme_mi_mi_aes_aese;

static int hf_nvme_mi_mi_aes_id;

/* Reset (07h) */

static int hf_nvme_mi_mi_reset_rsttyp;

/* Shutdown (0Ch) */

static int hf_nvme_mi_mi_shutdown_shdntyp;

/* NVM Subsystem Information data structure (DTYP 00h) */

static int hf_nvme_mi_mi_subsys_nump;

static int hf_nvme_mi_mi_subsys_mjr;

static int hf_nvme_mi_mi_subsys_mnr;

static int hf_nvme_mi_mi_subsys_nnsc;

static int hf_nvme_mi_mi_subsys_sre;

/* Port Information data structure (DTYP 01h) */

static int hf_nvme_mi_mi_port_prttyp;

static int hf_nvme_mi_mi_port_prtcap;

static int hf_nvme_mi_mi_port_aems;

static int hf_nvme_mi_mi_port_ciaps;

static int hf_nvme_mi_mi_port_mmtus;

static int hf_nvme_mi_mi_port_mebs;

static int hf_nvme_mi_mi_port_pcie_mps;

static int hf_nvme_mi_mi_port_pcie_slsv;

static int hf_nvme_mi_mi_port_pcie_cls;

static int hf_nvme_mi_mi_port_pcie_mlw;

static int hf_nvme_mi_mi_port_pcie_nlw;

static int hf_nvme_mi_mi_port_pcie_pn;

static int hf_nvme_mi_mi_port_twire_cvpdaddr;

static int hf_nvme_mi_mi_port_twire_mvpdfreq;

static int hf_nvme_mi_mi_port_twire_cmeaddr;

static int hf_nvme_mi_mi_port_twire_twprt;

static int hf_nvme_mi_mi_port_twire_i3csprt;

static int hf_nvme_mi_mi_port_twire_msmbfreq;

static int hf_nvme_mi_mi_port_twire_nvmebm;

static int hf_nvme_mi_mi_port_twire_nvmebms;

/* Controller List data structure (DTYP 02h, NVMe Base) */

static int hf_nvme_mi_mi_ctrllist_numids;

static int hf_nvme_mi_mi_ctrllist_ctrlid;

/* Controller Information data structure (DTYP 03h) */

static int hf_nvme_mi_mi_ctrlinfo_portid;

static int hf_nvme_mi_mi_ctrlinfo_prii;

static int hf_nvme_mi_mi_ctrlinfo_riv;

static int hf_nvme_mi_mi_ctrlinfo_pri;

static int hf_nvme_mi_mi_ctrlinfo_pri_bus;

static int hf_nvme_mi_mi_ctrlinfo_pri_dev;

static int hf_nvme_mi_mi_ctrlinfo_pri_fn;

static int hf_nvme_mi_mi_ctrlinfo_pcivid;

static int hf_nvme_mi_mi_ctrlinfo_pcidid;

static int hf_nvme_mi_mi_ctrlinfo_pcisvid;

static int hf_nvme_mi_mi_ctrlinfo_pcisdid;

static int hf_nvme_mi_mi_ctrlinfo_pciesn;

/* Optionally Supported / MEB Supported Command List (DTYP 04h/05h) */

static int hf_nvme_mi_mi_cmdlist_numcmd;

static int hf_nvme_mi_mi_cmdlist_ctyp;

static int hf_nvme_mi_mi_cmdlist_nmimt;

static int hf_nvme_mi_mi_cmdlist_opc;

/* NVM Subsystem Health Data Structure (NSHDS) */

static int hf_nvme_mi_mi_nshds_nss;

static int hf_nvme_mi_mi_nshds_nss_atf;

static int hf_nvme_mi_mi_nshds_nss_sfm;

static int hf_nvme_mi_mi_nshds_nss_df;

static int hf_nvme_mi_mi_nshds_nss_rnr;

static int hf_nvme_mi_mi_nshds_nss_p0la;

static int hf_nvme_mi_mi_nshds_nss_p1la;

static int hf_nvme_mi_mi_nshds_nss_snfm;

static int hf_nvme_mi_mi_nshds_sw;

static int hf_nvme_mi_mi_nshds_sw_ips;

static int hf_nvme_mi_mi_nshds_sw_pmre;

static int hf_nvme_mi_mi_nshds_sw_vmbf;

static int hf_nvme_mi_mi_nshds_sw_ro;

static int hf_nvme_mi_mi_nshds_sw_rd;

static int hf_nvme_mi_mi_nshds_sw_taut;

static int hf_nvme_mi_mi_nshds_sw_st;

static int hf_nvme_mi_mi_nshds_ctemp;

static int hf_nvme_mi_mi_nshds_pdlu;

static int hf_nvme_mi_mi_nshds_ccs;

/* Shared health-status flag bits — same bit layout in the NVMe-MI 2.1

 * "Composite Controller Status Data Structure (CCSDS)" and "Controller

 * Health Status Changed Flags (CHSCF)" figures. */

static int hf_nvme_mi_mi_hsf_tcida;

static int hf_nvme_mi_mi_hsf_cwarn;

static int hf_nvme_mi_mi_hsf_spare;

static int hf_nvme_mi_mi_hsf_pdlu;

static int hf_nvme_mi_mi_hsf_ctemp;

static int hf_nvme_mi_mi_hsf_csts;

static int hf_nvme_mi_mi_hsf_fa;

static int hf_nvme_mi_mi_hsf_nac;

static int hf_nvme_mi_mi_hsf_ceco;

static int hf_nvme_mi_mi_hsf_nssro;

static int hf_nvme_mi_mi_hsf_shst;

static int hf_nvme_mi_mi_hsf_cfs;

static int hf_nvme_mi_mi_hsf_rdy;

/* Controller Health Data Structure (CHDS) */

static int hf_nvme_mi_mi_chds_ctlid;

static int hf_nvme_mi_mi_chds_csts;

static int hf_nvme_mi_mi_chds_csts_tcida;

static int hf_nvme_mi_mi_chds_csts_fa;

static int hf_nvme_mi_mi_chds_csts_nac;

static int hf_nvme_mi_mi_chds_csts_ceco;

static int hf_nvme_mi_mi_chds_csts_nssro;

static int hf_nvme_mi_mi_chds_csts_shst;

static int hf_nvme_mi_mi_chds_csts_cfs;

static int hf_nvme_mi_mi_chds_csts_rdy;

static int hf_nvme_mi_mi_chds_ctemp;

static int hf_nvme_mi_mi_chds_pdlu;

static int hf_nvme_mi_mi_chds_spare;

static int hf_nvme_mi_mi_chds_cwarn;

static int hf_nvme_mi_mi_chds_cwarn_ips;

static int hf_nvme_mi_mi_chds_cwarn_pmre;

static int hf_nvme_mi_mi_chds_cwarn_vmbf;

static int hf_nvme_mi_mi_chds_cwarn_ro;

static int hf_nvme_mi_mi_chds_cwarn_rd;

static int hf_nvme_mi_mi_chds_cwarn_taut;

static int hf_nvme_mi_mi_chds_cwarn_st;

static int hf_nvme_mi_mi_chds_chsc;

static int ett_nvme_mi_mi;

static int ett_nvme_mi_mi_field;

static int ett_nvme_mi_mi_entry;

static expert_field ei_nvme_mi_mi_truncated;

static expert_field ei_nvme_mi_mi_orphan_response;

static expert_field ei_nvme_mi_mi_reserved_dtyp;

static expert_field ei_nvme_mi_mi_reserved_configid;

static expert_field ei_nvme_mi_mi_reserved_value;

/* MI command opcodes (NVMe-MI 2.1 "Opcodes for Management Interface Command

 * Set").  Only 00h-07h, 0Ch get field-level

 * decode; 08h-0Bh are named for display and fall through to the raw dword

 * rendering. */

enum nvme_mi_mi_opc {

    NVME_MI_MI_OPC_READ_DS    = 0x00,

    NVME_MI_MI_OPC_SUBSYS_HSP = 0x01,

    NVME_MI_MI_OPC_CTRL_HSP   = 0x02,

    NVME_MI_MI_OPC_CONFIG_SET = 0x03,

    NVME_MI_MI_OPC_CONFIG_GET = 0x04,

    NVME_MI_MI_OPC_VPD_READ   = 0x05,

    NVME_MI_MI_OPC_VPD_WRITE  = 0x06,

    NVME_MI_MI_OPC_RESET      = 0x07,

    NVME_MI_MI_OPC_SES_RECV   = 0x08,

    NVME_MI_MI_OPC_SES_SEND   = 0x09,

    NVME_MI_MI_OPC_MEB_READ   = 0x0A,

    NVME_MI_MI_OPC_MEB_WRITE  = 0x0B,

    NVME_MI_MI_OPC_SHUTDOWN   = 0x0C,

};

static const range_string mi_opcode_vals[] = {

    { NVME_MI_MI_OPC_READ_DS,    NVME_MI_MI_OPC_READ_DS,    "Read NVMe-MI Data Structure" },

    { NVME_MI_MI_OPC_SUBSYS_HSP, NVME_MI_MI_OPC_SUBSYS_HSP, "NVM Subsystem Health Status Poll" },

    { NVME_MI_MI_OPC_CTRL_HSP,   NVME_MI_MI_OPC_CTRL_HSP,   "Controller Health Status Poll" },

    { NVME_MI_MI_OPC_CONFIG_SET, NVME_MI_MI_OPC_CONFIG_SET, "Configuration Set" },

    { NVME_MI_MI_OPC_CONFIG_GET, NVME_MI_MI_OPC_CONFIG_GET, "Configuration Get" },

    { NVME_MI_MI_OPC_VPD_READ,   NVME_MI_MI_OPC_VPD_READ,   "VPD Read" },

    { NVME_MI_MI_OPC_VPD_WRITE,  NVME_MI_MI_OPC_VPD_WRITE,  "VPD Write" },

    { NVME_MI_MI_OPC_RESET,      NVME_MI_MI_OPC_RESET,      "Reset" },

    { NVME_MI_MI_OPC_SES_RECV,   NVME_MI_MI_OPC_SES_RECV,   "SES Receive" },

    { NVME_MI_MI_OPC_SES_SEND,   NVME_MI_MI_OPC_SES_SEND,   "SES Send" },

    { NVME_MI_MI_OPC_MEB_READ,   NVME_MI_MI_OPC_MEB_READ,   "Management Endpoint Buffer Read" },

    { NVME_MI_MI_OPC_MEB_WRITE,  NVME_MI_MI_OPC_MEB_WRITE,  "Management Endpoint Buffer Write" },

    { NVME_MI_MI_OPC_SHUTDOWN,   NVME_MI_MI_OPC_SHUTDOWN,   "Shutdown" },

    { 0xC0, 0xFF,                                           "Vendor Specific" },

    { 0, 0, NULL },

};

/* Data Structure Types (Read NVMe-MI Data Structure NVMe Management

 * Dword 0); 06h-FFh are reserved. */

enum nvme_mi_dtyp {

    NVME_MI_DTYP_SUBSYS_INFO = 0x00,

    NVME_MI_DTYP_PORT_INFO   = 0x01,

    NVME_MI_DTYP_CTRL_LIST   = 0x02,

    NVME_MI_DTYP_CTRL_INFO   = 0x03,

    NVME_MI_DTYP_OSC_LIST    = 0x04,

    NVME_MI_DTYP_MEB_LIST    = 0x05,

    NVME_MI_DTYP_MAX         = NVME_MI_DTYP_MEB_LIST,

};

static const value_string mi_dtyp_vals[] = {

    { NVME_MI_DTYP_SUBSYS_INFO, "NVM Subsystem Information" },

    { NVME_MI_DTYP_PORT_INFO,   "Port Information" },

    { NVME_MI_DTYP_CTRL_LIST,   "Controller List" },

    { NVME_MI_DTYP_CTRL_INFO,   "Controller Information" },

    { NVME_MI_DTYP_OSC_LIST,    "Optionally Supported Command List" },

    { NVME_MI_DTYP_MEB_LIST,    "Management Endpoint Buffer Command Support List" },

    { 0, NULL },

};

/* Configuration Identifiers; 00h and 05h-BFh are reserved,

 * C0h-FFh vendor specific. */

enum nvme_mi_cfgid {

    NVME_MI_CFGID_SMBUS_FREQ = 0x01,

    NVME_MI_CFGID_HSC        = 0x02,

    NVME_MI_CFGID_MTUS       = 0x03,

    NVME_MI_CFGID_AE         = 0x04,

    NVME_MI_CFGID_RESERVED_FIRST = 0x05,

    NVME_MI_CFGID_RESERVED_LAST  = 0xBF,

};

static const range_string mi_configid_vals[] = {

    { 0x00, 0x00,                                                 "Reserved" },

    { NVME_MI_CFGID_SMBUS_FREQ, NVME_MI_CFGID_SMBUS_FREQ,         "SMBus/I2C Frequency" },

    { NVME_MI_CFGID_HSC,        NVME_MI_CFGID_HSC,                "Health Status Change" },

    { NVME_MI_CFGID_MTUS,       NVME_MI_CFGID_MTUS,               "MCTP Transmission Unit Size" },

    { NVME_MI_CFGID_AE,         NVME_MI_CFGID_AE,                 "Asynchronous Event" },

    { NVME_MI_CFGID_RESERVED_FIRST, NVME_MI_CFGID_RESERVED_LAST,  "Reserved" },

    { 0xC0, 0xFF,                                                 "Vendor Specific" },

    { 0, 0, NULL },

};

/* AE Enable ID — Asynchronous Events */

static const range_string mi_ae_id_vals[] = {

    { 0x00, 0x00, "Controller Ready" },

    { 0x01, 0x01, "Controller Fatal Status" },

    { 0x02, 0x02, "Shutdown Status" },

    { 0x03, 0x03, "Controller Enable" },

    { 0x04, 0x04, "Namespace Attribute Changed" },

    { 0x05, 0x05, "Firmware Activated" },

    { 0x06, 0x06, "Composite Temperature" },

    { 0x07, 0x07, "Percentage Drive Life Used" },

    { 0x08, 0x08, "Available Spare" },

    { 0x09, 0x09, "SMART Warnings" },

    { 0x0a, 0x0a, "Telemetry Controller-Initiated Data Available" },

    { 0x0b, 0x0b, "PCIe Link Active" },

    { 0x0c, 0x0c, "Sanitize Failure Mode" },

    { 0x0d, 0x0d, "Sanitize Namespace Failure Mode" },

    { 0x0e, 0x0e, "Power Threshold Exceeded" },

    { 0xC0, 0xFF, "Vendor Specific" },

    { 0, 0, NULL },

};

/* SMBus/I2C frequency encoding */

static const value_string mi_sfreq_vals[] = {

    { 0x0, "Obsolete/Reserved" },

    { 0x1, "100 kHz" },

    { 0x2, "400 kHz" },

    { 0x3, "1 MHz" },

    { 0, NULL },

};

/* Maximum VPD access / maximum SMBus frequency (2-Wire Port Specific

 * Data) */

static const value_string mi_vpdfreq_vals[] = {

    { 0x0, "Not supported" },

    { 0x1, "100 kHz" },

    { 0x2, "400 kHz" },

    { 0x3, "1 MHz" },

    { 0, NULL },

};

static const value_string mi_prttyp_vals[] = {

    { 0x0, "Inactive" },

    { 0x1, "PCIe" },

    { 0x2, "2-Wire" },

    { 0, NULL },

};

static const value_string mi_pciemps_vals[] = {

    { 0x0, "128 bytes" },

    { 0x1, "256 bytes" },

    { 0x2, "512 bytes" },

    { 0x3, "1 KiB" },

    { 0x4, "2 KiB" },

    { 0x5, "4 KiB" },

    { 0, NULL },

};

static const value_string mi_pciecls_vals[] = {

    { 0x0, "Link not active" },

    { 0x1, "2.5 GT/s" },

    { 0x2, "5.0 GT/s" },

    { 0x3, "8.0 GT/s" },

    { 0x4, "16.0 GT/s" },

    { 0x5, "32.0 GT/s" },

    { 0x6, "64.0 GT/s" },

    { 0, NULL },

};

/* Reset Type; 01h-FFh reserved */

#define NVME_MI_RSTTYP_MAX 0x00     /* highest valid Reset Type */

static const value_string mi_rsttyp_vals[] = {

    { 0x00, "Reset NVM Subsystem" },

    { 0, NULL },

};

/* Shutdown Type; 02h-FFh reserved */

#define NVME_MI_SHDNTYP_MAX 0x01    /* highest valid Shutdown Type */

static const value_string mi_shdntyp_vals[] = {

    { 0x00, "Normal NVM Subsystem Shutdown" },

    { 0x01, "Abrupt NVM Subsystem Shutdown" },

    { 0, NULL },

};

/*

 * CSTS.SHST shutdown status: reuse packet-nvme.c's shst_table (shared via

 * packet-nvme.h) so the MI CHDS decode and the NVMe Base decode never drift.

 *

 * NMIMT in command-list entries (the Optionally/MEB Supported Command Data

 * Structure entries) uses the same encoding as the

 * message header, so the entry decode reuses mi_type_vals (packet-nvme-mi.h).

 */

/*

 * Per-transaction request context hung off nvme_mi_transaction.body_ctx

 * (wmem_file_scope).  Records the request parameter that selects the

 * response layout; only the member matching the transaction's opcode is

 * meaningful.

 */

struct nvme_mi_mi_req_ctx {

    uint8_t dtyp;       /* Read NVMe-MI Data Structure (00h) */

    uint8_t configid;   /* Configuration Set/Get (03h/04h) */

};

static int * const rds_cdw0_fields[] = {

    &hf_nvme_mi_mi_rds_dtyp,

    &hf_nvme_mi_mi_rds_portid,

    &hf_nvme_mi_mi_rds_ctrlid,

    NULL,

};

static int * const rds_cdw1_fields[] = {

    &hf_nvme_mi_mi_rds_iocsi,

    NULL,

};

static int * const nshsp_cdw1_fields[] = {

    &hf_nvme_mi_mi_nshsp_cs,

    NULL,

};

static int * const chsp_cdw0_fields[] = {

    &hf_nvme_mi_mi_chsp_all,

    &hf_nvme_mi_mi_chsp_incvf,

    &hf_nvme_mi_mi_chsp_incpf,

    &hf_nvme_mi_mi_chsp_incf,

    &hf_nvme_mi_mi_chsp_maxrent,

    &hf_nvme_mi_mi_chsp_sctlid,

    NULL,

};

static int * const chsp_cdw1_fields[] = {

    &hf_nvme_mi_mi_chsp_ccf,

    &hf_nvme_mi_mi_chsp_cwarn,

    &hf_nvme_mi_mi_chsp_spare,

    &hf_nvme_mi_mi_chsp_pdlu,

    &hf_nvme_mi_mi_chsp_ctemp,

    &hf_nvme_mi_mi_chsp_csts,

    NULL,

};

static int * const cfg_cdw0_fields_cid[] = {

    &hf_nvme_mi_mi_cfg_cid,

    NULL,

};

static int * const cfg_cdw0_fields_port[] = {

    &hf_nvme_mi_mi_cfg_portid,

    &hf_nvme_mi_mi_cfg_cid,

    NULL,

};

static int * const cfg_cdw0_fields_sfreq[] = {

    &hf_nvme_mi_mi_cfg_portid,

    &hf_nvme_mi_mi_cfg_sfreq,

    &hf_nvme_mi_mi_cfg_cid,

    NULL,

};

static int * const cfg_cdw1_fields_hsc[] = {

    &hf_nvme_mi_mi_cfg_hsc_tcida,

    &hf_nvme_mi_mi_cfg_hsc_cwarn,

    &hf_nvme_mi_mi_cfg_hsc_spare,

    &hf_nvme_mi_mi_cfg_hsc_pdlu,

    &hf_nvme_mi_mi_cfg_hsc_ctemp,

    &hf_nvme_mi_mi_cfg_hsc_cschng,

    &hf_nvme_mi_mi_cfg_hsc_fa,

    &hf_nvme_mi_mi_cfg_hsc_nac,

    &hf_nvme_mi_mi_cfg_hsc_ceco,

    &hf_nvme_mi_mi_cfg_hsc_nssro,

    &hf_nvme_mi_mi_cfg_hsc_shst,

    &hf_nvme_mi_mi_cfg_hsc_cfs,

    &hf_nvme_mi_mi_cfg_hsc_rdy,

    NULL,

};

static int * const cfg_cdw1_fields_mtus[] = {

    &hf_nvme_mi_mi_cfg_mtus,

    NULL,

};

/* Configuration Set of the Asynchronous Event configuration; the

 * Configuration Get form has these bits reserved. */

static int * const cfg_cdw0_fields_ae_set[] = {

    &hf_nvme_mi_mi_cfg_ae_envfa,

    &hf_nvme_mi_mi_cfg_ae_enpfa,

    &hf_nvme_mi_mi_cfg_ae_encfa,

    &hf_nvme_mi_mi_cfg_ae_aemd,

    &hf_nvme_mi_mi_cfg_ae_aerd,

    &hf_nvme_mi_mi_cfg_cid,

    NULL,

};

static int * const vpd_cdw0_fields[] = {

    &hf_nvme_mi_mi_vpd_dofst,

    NULL,

};

static int * const vpd_cdw1_fields[] = {

    &hf_nvme_mi_mi_vpd_dlen,

    NULL,

};

static int * const reset_cdw0_fields[] = {

    &hf_nvme_mi_mi_reset_rsttyp,

    NULL,

};

static int * const shutdown_cdw0_fields[] = {

    &hf_nvme_mi_mi_shutdown_shdntyp,

    NULL,

};

static int * const subsys_nnsc_fields[] = {

    &hf_nvme_mi_mi_subsys_sre,

    NULL,

};

static int * const port_prtcap_fields[] = {

    &hf_nvme_mi_mi_port_aems,

    &hf_nvme_mi_mi_port_ciaps,

    NULL,

};

static int * const port_twprt_fields[] = {

    &hf_nvme_mi_mi_port_twire_i3csprt,

    &hf_nvme_mi_mi_port_twire_msmbfreq,

    NULL,

};

static int * const port_nvmebm_fields[] = {

    &hf_nvme_mi_mi_port_twire_nvmebms,

    NULL,

};

static int * const ctrlinfo_prii_fields[] = {

    &hf_nvme_mi_mi_ctrlinfo_riv,

    NULL,

};

static int * const ctrlinfo_pri_fields[] = {

    &hf_nvme_mi_mi_ctrlinfo_pri_bus,

    &hf_nvme_mi_mi_ctrlinfo_pri_dev,

    &hf_nvme_mi_mi_ctrlinfo_pri_fn,

    NULL,

};

static int * const cmdlist_ctyp_fields[] = {

    &hf_nvme_mi_mi_cmdlist_nmimt,

    NULL,

};

static int * const nshds_nss_fields[] = {

    &hf_nvme_mi_mi_nshds_nss_atf,

    &hf_nvme_mi_mi_nshds_nss_sfm,

    &hf_nvme_mi_mi_nshds_nss_df,

    &hf_nvme_mi_mi_nshds_nss_rnr,

    &hf_nvme_mi_mi_nshds_nss_p0la,

    &hf_nvme_mi_mi_nshds_nss_p1la,

    &hf_nvme_mi_mi_nshds_nss_snfm,

    NULL,

};

/*

 * NSHDS SMART Warnings is the bitwise *inverse* of the SMART / Health

 * Information Critical Warning field: a bit is set to '1' when the condition

 * is clear on every Controller in the NVM Subsystem, and cleared to '0' when

 * any Controller asserts it.  The bit positions match CHDS CWARN, but the

 * sense is opposite, so these must not use tfs_set_notset.

 */

static const true_false_string tfs_nshds_sw = { "Normal", "Warning" };

static int * const nshds_sw_fields[] = {

    &hf_nvme_mi_mi_nshds_sw_ips,

    &hf_nvme_mi_mi_nshds_sw_pmre,

    &hf_nvme_mi_mi_nshds_sw_vmbf,

    &hf_nvme_mi_mi_nshds_sw_ro,

    &hf_nvme_mi_mi_nshds_sw_rd,

    &hf_nvme_mi_mi_nshds_sw_taut,

    &hf_nvme_mi_mi_nshds_sw_st,

    NULL,

};

static int * const hsf_fields[] = {

    &hf_nvme_mi_mi_hsf_tcida,

    &hf_nvme_mi_mi_hsf_cwarn,

    &hf_nvme_mi_mi_hsf_spare,

    &hf_nvme_mi_mi_hsf_pdlu,

    &hf_nvme_mi_mi_hsf_ctemp,

    &hf_nvme_mi_mi_hsf_csts,

    &hf_nvme_mi_mi_hsf_fa,

    &hf_nvme_mi_mi_hsf_nac,

    &hf_nvme_mi_mi_hsf_ceco,

    &hf_nvme_mi_mi_hsf_nssro,

    &hf_nvme_mi_mi_hsf_shst,

    &hf_nvme_mi_mi_hsf_cfs,

    &hf_nvme_mi_mi_hsf_rdy,

    NULL,

};

static int * const chds_csts_fields[] = {

    &hf_nvme_mi_mi_chds_csts_tcida,

    &hf_nvme_mi_mi_chds_csts_fa,

    &hf_nvme_mi_mi_chds_csts_nac,

    &hf_nvme_mi_mi_chds_csts_ceco,

    &hf_nvme_mi_mi_chds_csts_nssro,

    &hf_nvme_mi_mi_chds_csts_shst,

    &hf_nvme_mi_mi_chds_csts_cfs,

    &hf_nvme_mi_mi_chds_csts_rdy,

    NULL,

};

static int * const chds_cwarn_fields[] = {

    &hf_nvme_mi_mi_chds_cwarn_ips,

    &hf_nvme_mi_mi_chds_cwarn_pmre,

    &hf_nvme_mi_mi_chds_cwarn_vmbf,

    &hf_nvme_mi_mi_chds_cwarn_ro,

    &hf_nvme_mi_mi_chds_cwarn_rd,

    &hf_nvme_mi_mi_chds_cwarn_taut,

    &hf_nvme_mi_mi_chds_cwarn_st,

    NULL,

};

/*

 * NSHDS CTEMP encoding: 00h-7Eh = 0-126 °C, 7Fh = 127 °C or

 * higher, 80h/81h = sentinel codes, C4h = -60 °C or lower, C5h-FFh =

 * -59 to -1 °C in two's complement, the rest reserved.

 */

static void

nvme_mi_mi_fmt_nshds_ctemp(char *buf, uint32_t value)

{

    if (value <= 0x7e)

        snprintf(buf, ITEM_LABEL_LENGTH, "%u " UTF8_DEGREE_SIGN "C", value);

    else if (value == 0x7f)

        snprintf(buf, ITEM_LABEL_LENGTH, "127 " UTF8_DEGREE_SIGN "C or higher");

    else if (value == 0x80)

        snprintf(buf, ITEM_LABEL_LENGTH, "No temperature data or data is stale");

    else if (value == 0x81)

        snprintf(buf, ITEM_LABEL_LENGTH, "Temperature sensor failure");

    else if (value <= 0xc3)

        snprintf(buf, ITEM_LABEL_LENGTH, "Reserved (0x%02x)", value);

    else if (value == 0xc4)

        snprintf(buf, ITEM_LABEL_LENGTH, "-60 " UTF8_DEGREE_SIGN "C or lower");

    else

        snprintf(buf, ITEM_LABEL_LENGTH, "%d " UTF8_DEGREE_SIGN "C",

                 (int)value - 256);

}

/* Flag truncated response data and render the leftover bytes raw. */

static void

nvme_mi_mi_data_truncated(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree,

                          proto_item *it, int off)

{

    nvme_mi_dissect_truncated(tvb, pinfo, tree, it, &ei_nvme_mi_mi_truncated,

                              hf_nvme_mi_mi_data, off);

}

/* DTYP 00h — NVM Subsystem Information Data Structure */

static void

nvme_mi_mi_data_subsys_info(tvbuff_t *tvb, packet_info *pinfo,

                            proto_tree *tree, proto_item *it, int off, int len)

{

    if (len < 4) {

        nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, off);

        return;

    }

    proto_tree_add_item(tree, hf_nvme_mi_mi_subsys_nump, tvb, off, 1, ENC_NA);

    proto_tree_add_item(tree, hf_nvme_mi_mi_subsys_mjr, tvb, off + 1, 1, ENC_NA);

    proto_tree_add_item(tree, hf_nvme_mi_mi_subsys_mnr, tvb, off + 2, 1, ENC_NA);

    proto_tree_add_bitmask(tree, tvb, off + 3, hf_nvme_mi_mi_subsys_nnsc,

                           ett_nvme_mi_mi_field, subsys_nnsc_fields, ENC_NA);

    /* bytes 31:04 reserved */

}

/* DTYP 01h — Port Information Data Structure */

static void

nvme_mi_mi_data_port_info(tvbuff_t *tvb, packet_info *pinfo,

                          proto_tree *tree, proto_item *it, int off, int len)

{

    uint32_t prttyp;

    if (len < 8) {

        nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, off);

        return;

    }

    proto_tree_add_item_ret_uint(tree, hf_nvme_mi_mi_port_prttyp,

                                 tvb, off, 1, ENC_NA, &prttyp);

    proto_tree_add_bitmask(tree, tvb, off + 1, hf_nvme_mi_mi_port_prtcap,

                           ett_nvme_mi_mi_field, port_prtcap_fields, ENC_NA);

    proto_tree_add_item(tree, hf_nvme_mi_mi_port_mmtus,

                        tvb, off + 2, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(tree, hf_nvme_mi_mi_port_mebs,

                        tvb, off + 4, 4, ENC_LITTLE_ENDIAN);

    switch (prttyp) {

    case 0x1:   /* PCIe Port Specific Data */

        if (len < 14) {

            nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, off + 8);

            return;

        }

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_pcie_mps,

                            tvb, off + 8, 1, ENC_NA);

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_pcie_slsv,

                            tvb, off + 9, 1, ENC_NA);

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_pcie_cls,

                            tvb, off + 10, 1, ENC_NA);

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_pcie_mlw,

                            tvb, off + 11, 1, ENC_NA);

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_pcie_nlw,

                            tvb, off + 12, 1, ENC_NA);

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_pcie_pn,

                            tvb, off + 13, 1, ENC_NA);

        break;

    case 0x2:   /* 2-Wire Port Specific Data */

        if (len < 13) {

            nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, off + 8);

            return;

        }

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_twire_cvpdaddr,

                            tvb, off + 8, 1, ENC_NA);

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_twire_mvpdfreq,

                            tvb, off + 9, 1, ENC_NA);

        proto_tree_add_item(tree, hf_nvme_mi_mi_port_twire_cmeaddr,

                            tvb, off + 10, 1, ENC_NA);

        proto_tree_add_bitmask(tree, tvb, off + 11,

                               hf_nvme_mi_mi_port_twire_twprt,

                               ett_nvme_mi_mi_field, port_twprt_fields, ENC_NA);

        proto_tree_add_bitmask(tree, tvb, off + 12,

                               hf_nvme_mi_mi_port_twire_nvmebm,

                               ett_nvme_mi_mi_field, port_nvmebm_fields, ENC_NA);

        break;

    default:

        /* Inactive or reserved port type: PTSP bytes rendered raw */

        if (len > 8)

            proto_tree_add_item(tree, hf_nvme_mi_mi_data, tvb, off + 8, -1,

                                ENC_NA);

        break;

    }

}

/* DTYP 02h — Controller List (NVMe Base format: count + uint16le IDs) */

static void

nvme_mi_mi_data_ctrl_list(tvbuff_t *tvb, packet_info *pinfo,

                          proto_tree *tree, proto_item *it, int off, int len)

{

    uint32_t numids;

    int pos = off + 2;

    if (len < 2) {

        nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, off);

        return;

    }

    proto_tree_add_item_ret_uint(tree, hf_nvme_mi_mi_ctrllist_numids,

                                 tvb, off, 2, ENC_LITTLE_ENDIAN, &numids);

    for (uint32_t i = 0; i < numids; i++) {

        if (pos + 2 > off + len) {

            nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, pos);

            return;

        }

        proto_tree_add_item(tree, hf_nvme_mi_mi_ctrllist_ctrlid,

                            tvb, pos, 2, ENC_LITTLE_ENDIAN);

        pos += 2;

    }

}

/* DTYP 03h — Controller Information Data Structure */

static void

nvme_mi_mi_data_ctrl_info(tvbuff_t *tvb, packet_info *pinfo,

                          proto_tree *tree, proto_item *it, int off, int len)

{

    if (len < 17) {

        nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, off);

        return;

    }

    proto_tree_add_item(tree, hf_nvme_mi_mi_ctrlinfo_portid,

                        tvb, off, 1, ENC_NA);

    /* bytes 04:01 reserved */

    proto_tree_add_bitmask(tree, tvb, off + 5, hf_nvme_mi_mi_ctrlinfo_prii,

                           ett_nvme_mi_mi_field, ctrlinfo_prii_fields, ENC_NA);

    proto_tree_add_bitmask(tree, tvb, off + 6, hf_nvme_mi_mi_ctrlinfo_pri,

                           ett_nvme_mi_mi_field, ctrlinfo_pri_fields,

                           ENC_LITTLE_ENDIAN);

    proto_tree_add_item(tree, hf_nvme_mi_mi_ctrlinfo_pcivid,

                        tvb, off + 8, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(tree, hf_nvme_mi_mi_ctrlinfo_pcidid,

                        tvb, off + 10, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(tree, hf_nvme_mi_mi_ctrlinfo_pcisvid,

                        tvb, off + 12, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(tree, hf_nvme_mi_mi_ctrlinfo_pcisdid,

                        tvb, off + 14, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(tree, hf_nvme_mi_mi_ctrlinfo_pciesn,

                        tvb, off + 16, 1, ENC_NA);

    /* bytes 31:17 reserved */

}

/* DTYP 04h/05h — Optionally Supported / MEB Supported Command List

 * (both share the count + (CTYP, OPC) entry format) */

static void

nvme_mi_mi_data_cmd_list(tvbuff_t *tvb, packet_info *pinfo,

                         proto_tree *tree, proto_item *it, int off, int len)

{

    uint32_t numcmd;

    int pos = off + 2;

    if (len < 2) {

        nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, off);

        return;

    }

    proto_tree_add_item_ret_uint(tree, hf_nvme_mi_mi_cmdlist_numcmd,

                                 tvb, off, 2, ENC_LITTLE_ENDIAN, &numcmd);

    for (uint32_t i = 0; i < numcmd; i++) {

        uint64_t ctyp;

        uint8_t opc;

        proto_item *opc_it;

        const char *opc_name = NULL;

        if (pos + 2 > off + len) {

            nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, pos);

            return;

        }

        proto_tree_add_bitmask_ret_uint64(tree, tvb, pos, hf_nvme_mi_mi_cmdlist_ctyp,

                                          ett_nvme_mi_mi_field, cmdlist_ctyp_fields,

                                          ENC_NA, &ctyp);

        opc_it = proto_tree_add_item_ret_uint8(tree, hf_nvme_mi_mi_cmdlist_opc,

                                               tvb, pos + 1, 1, ENC_NA, &opc);

        /* NMIMT (CTYP bits 6:3) selects which opcode namespace OPC belongs to

         * -- both tables already exist in-tree, so name the entry from

         * whichever one the command actually lives in instead of leaving it

         * a bare byte. */

        switch ((ctyp & 0x78) >> 3) {

        case NVME_MI_TYPE_MI:

            opc_name = rval_to_str_const(opc, mi_opcode_vals, "Unknown");

            break;

        case NVME_MI_TYPE_ADMIN:

            opc_name = nvme_get_opcode_string(opc, 0);

            break;

        default:

            break;

        }

        if (opc_name)

            proto_item_append_text(opc_it, " (%s)", opc_name);

        pos += 2;

    }

}

/* NVM Subsystem Health Data Structure (NSHDS; 8 bytes) */

static void

nvme_mi_mi_data_nshds(tvbuff_t *tvb, packet_info *pinfo,

                      proto_tree *tree, proto_item *it, int off, int len)

{

    if (len < 8) {

        nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, off);

        return;

    }

    proto_tree_add_bitmask(tree, tvb, off, hf_nvme_mi_mi_nshds_nss,

                           ett_nvme_mi_mi_field, nshds_nss_fields, ENC_NA);

    proto_tree_add_bitmask(tree, tvb, off + 1, hf_nvme_mi_mi_nshds_sw,

                           ett_nvme_mi_mi_field, nshds_sw_fields, ENC_NA);

    proto_tree_add_item(tree, hf_nvme_mi_mi_nshds_ctemp,

                        tvb, off + 2, 1, ENC_NA);

    proto_tree_add_item(tree, hf_nvme_mi_mi_nshds_pdlu,

                        tvb, off + 3, 1, ENC_NA);

    proto_tree_add_bitmask(tree, tvb, off + 4, hf_nvme_mi_mi_nshds_ccs,

                           ett_nvme_mi_mi_field, hsf_fields,

                           ENC_LITTLE_ENDIAN);

    /* bytes 7:6 reserved */

}

/* Array of 16-byte Controller Health Data Structures (CHDS) */

static void

nvme_mi_mi_data_chds_list(tvbuff_t *tvb, packet_info *pinfo,

                          proto_tree *tree, proto_item *it, int off, int len)

{

    unsigned idx = 0;

    int pos = off;

    while (off + len - pos >= 16) {

        proto_tree *etree = proto_tree_add_subtree_format(tree, tvb, pos, 16,

                ett_nvme_mi_mi_entry, NULL,

                "Controller Health Data Structure %u", idx);

        proto_tree_add_item(etree, hf_nvme_mi_mi_chds_ctlid,

                            tvb, pos, 2, ENC_LITTLE_ENDIAN);

        proto_tree_add_bitmask(etree, tvb, pos + 2, hf_nvme_mi_mi_chds_csts,

                               ett_nvme_mi_mi_field, chds_csts_fields,

                               ENC_LITTLE_ENDIAN);

        proto_tree_add_item(etree, hf_nvme_mi_mi_chds_ctemp,

                            tvb, pos + 4, 2, ENC_LITTLE_ENDIAN);

        proto_tree_add_item(etree, hf_nvme_mi_mi_chds_pdlu,

                            tvb, pos + 6, 1, ENC_NA);

        proto_tree_add_item(etree, hf_nvme_mi_mi_chds_spare,

                            tvb, pos + 7, 1, ENC_NA);

        proto_tree_add_bitmask(etree, tvb, pos + 8, hf_nvme_mi_mi_chds_cwarn,

                               ett_nvme_mi_mi_field, chds_cwarn_fields,

                               ENC_NA);

        proto_tree_add_bitmask(etree, tvb, pos + 9, hf_nvme_mi_mi_chds_chsc,

                               ett_nvme_mi_mi_field, hsf_fields,

                               ENC_LITTLE_ENDIAN);

        /* bytes 15:11 reserved */

        pos += 16;

        idx++;

    }

    if (pos < off + len)

        nvme_mi_mi_data_truncated(tvb, pinfo, tree, it, pos);

}

/* Append " (<opcode>[: <detail>])" to COL_INFO. */

static void

nvme_mi_mi_col_append(packet_info *pinfo, unsigned opcode, const char *detail)

{

    const char *name = rval_to_str_const(opcode, mi_opcode_vals, "Unknown");

    if (detail)

        col_append_fstr(pinfo->cinfo, COL_INFO, " (%s: %s)", name, detail);

    else

        col_append_fstr(pinfo->cinfo, COL_INFO, " (%s)", name);

}

static const char *

nvme_mi_mi_configid_name(uint8_t cid)

{

    return rval_to_str_const(cid, mi_configid_vals, "Reserved");

}

/*

 * Decode a request whose only parameter is a type byte in NMD0 bits 31:24

 * with NMD1 reserved (Reset RSTTYP; Shutdown SHDNTYP).  Values above

 * max_valid are in the Reserved range.  Returns

 * the type's display name for COL_INFO.

 */

static const char *

nvme_mi_mi_dissect_typebyte_req(tvbuff_t *tvb, packet_info *pinfo,

                                proto_tree *mi_tree, int * const *cdw0_fields,

                                uint8_t max_valid, const value_string *vals)

{

    proto_item *cdw_it;

    uint64_t cdw0;

    uint8_t typ;

    cdw_it = proto_tree_add_bitmask_ret_uint64(mi_tree, tvb, 4,

            hf_nvme_mi_mi_cdw0, ett_nvme_mi_mi_field,

            cdw0_fields, ENC_LITTLE_ENDIAN, &cdw0);

    typ = (uint8_t)(cdw0 >> 24);

    if (typ > max_valid)

        expert_add_info(pinfo, cdw_it, &ei_nvme_mi_mi_reserved_value);

    proto_tree_add_item(mi_tree, hf_nvme_mi_mi_cdw1,

                        tvb, 8, 4, ENC_LITTLE_ENDIAN);

    return val_to_str_const(typ, vals, "Reserved");

}

/*

 * The AE Enable List sent as Configuration Set (03h) request data and the

 * AE Supported List returned as Configuration Get (04h) response data share

 * one layout: a header (count, version,

 * total length, header length) followed by <count> entries, each a 1-byte

 * length plus a 2-byte info word (flag bit 15, AE ID bits 7:0).  Only the

 * field names differ, so the walk below is driven by this descriptor.

 */

struct nvme_mi_mi_ae_list_hf {

    int         list;

    int         num;

    int         ver;

    int         total_len;

    int         hdr_len;

    int         entry;

    int         entry_len;

    int         flag;

    int         id;

    const char *entry_name;

};

static void

dissect_nvme_mi_mi_ae_list(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree,

                           proto_item *it, unsigned off, unsigned len,

                           const struct nvme_mi_mi_ae_list_hf *hf)

{

    proto_tree *ae_tree;

    proto_item *ti;

    uint32_t num, hdr_len, i;

    unsigned pos;

    ti = proto_tree_add_item(tree, hf->list, tvb, off, len, ENC_NA);

    ae_tree = proto_item_add_subtree(ti, ett_nvme_mi_mi);

    /* The list header is 5 bytes; anything shorter is truncated. */

    if (len < 5) {

        nvme_mi_mi_data_truncated(tvb, pinfo, ae_tree, it, off);

        return;

    }

    proto_tree_add_item_ret_uint(ae_tree, hf->num,

                                 tvb, off, 1, ENC_LITTLE_ENDIAN, &num);

    proto_tree_add_item(ae_tree, hf->ver,

                        tvb, off + 1, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(ae_tree, hf->total_len,

                        tvb, off + 2, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item_ret_uint(ae_tree, hf->hdr_len,

                                 tvb, off + 4, 1, ENC_LITTLE_ENDIAN, &hdr_len);

    /* The list body starts at the offset the header declares, not at a fixed

     * 5; a value below the 5 defined header bytes is bogus, so clamp forward

     * to keep the entry walk inside the body. */

    if (hdr_len < 5)

        hdr_len = 5;

    pos = off + hdr_len;

    for (i = 0; i < num; i++) {

        proto_tree *e_tree;

        proto_item *e_ti;

        unsigned elen, entry_len;

        /* Each entry is at least 3 bytes (length + info word).  Stop if the

         * next entry would run past the list data. */

        if (pos + 3 > off + len)

            break;

        elen = tvb_get_uint8(tvb, pos);