/src/wireshark/epan/dissectors/packet-nvme.c

Source
/* packet-nvme.c
 * Routines for NVM Express dissection
 * Copyright 2016
 * Code by Parav Pandit
 *
 * Wireshark - Network traffic analyzer
 * By Gerald Combs <gerald@wireshark.org>
 * Copyright 1998 Gerald Combs
 *
 * SPDX-License-Identifier: GPL-2.0-or-later
 */

/* This file dissects NVMe packets received from the underlying
 * fabric such as RDMA, FC.
 * This is fabric agnostic dissector and depends on cmd_ctx and q_ctx
 * It currently aligns to below specification.
 * http://www.nvmexpress.org/wp-content/uploads/NVM-Express-1_2a.pdf
 */

#include "config.h"

#include <epan/packet.h>
#include <epan/expert.h>
#include <epan/tfs.h>
#include <epan/unit_strings.h>

#include <wsutil/array.h>
#include "packet-nvme.h"

void proto_register_nvme(void);

static int proto_nvme;

/* Dissector table for Security Send/Receive payloads, keyed on the Security
 * Protocol (SECP); see struct nvme_security_info in packet-nvme.h. */
static dissector_table_t nvme_security_secp_table;


/* NVMeOF fields */
/* NVMe Fabric Cmd */
static int hf_nvmeof_cmd;
static int hf_nvmeof_cmd_opc;
static int hf_nvmeof_cmd_rsvd;
static int hf_nvmeof_cmd_cid;
static int hf_nvmeof_cmd_fctype;
static int hf_nvmeof_cmd_connect_rsvd1;
static int hf_nvmeof_cmd_connect_sgl1;
static int hf_nvmeof_cmd_connect_recfmt;
static int hf_nvmeof_cmd_connect_qid;
static int hf_nvmeof_cmd_connect_sqsize;
static int hf_nvmeof_cmd_connect_cattr[5];
static int hf_nvmeof_cmd_connect_rsvd2;
static int hf_nvmeof_cmd_connect_kato;
static int hf_nvmeof_cmd_connect_rsvd3;
static int hf_nvmeof_cmd_connect_data_hostid;
static int hf_nvmeof_cmd_connect_data_cntlid;
static int hf_nvmeof_cmd_connect_data_rsvd0;
static int hf_nvmeof_cmd_connect_data_subnqn;
static int hf_nvmeof_cmd_connect_data_hostnqn;
static int hf_nvmeof_cmd_connect_data_rsvd1;

static int hf_nvmeof_cmd_auth_rsdv1;
static int hf_nvmeof_cmd_auth_sgl1;
static int hf_nvmeof_cmd_auth_rsdv2;
static int hf_nvmeof_cmd_auth_spsp0;
static int hf_nvmeof_cmd_auth_spsp1;
static int hf_nvmeof_cmd_auth_secp;
static int hf_nvmeof_cmd_auth_al;
static int hf_nvmeof_cmd_auth_rsdv3;

static int hf_nvmeof_cmd_disconnect_rsvd0;
static int hf_nvmeof_cmd_disconnect_recfmt;
static int hf_nvmeof_cmd_disconnect_rsvd1;

static int hf_nvmeof_cmd_prop_get_set_rsvd0;
static int hf_nvmeof_cmd_prop_get_set_attrib[3];
static int hf_nvmeof_cmd_prop_get_set_rsvd1;
static int hf_nvmeof_cmd_prop_get_set_offset;
static int hf_nvmeof_cmd_prop_get_rsvd2;

static int hf_nvmeof_cmd_prop_set_rsvd;

static int hf_nvmeof_cmd_generic_rsvd1;
static int hf_nvmeof_cmd_generic_field;

static int hf_nvmeof_prop_get_set_data;
static int hf_nvmeof_prop_get_set_data_4B;
static int hf_nvmeof_prop_get_set_data_4B_rsvd;
static int hf_nvmeof_prop_get_set_data_8B;
static int hf_nvmeof_prop_get_set_cc[10];
static int hf_nvmeof_prop_get_set_csts[7];
static int hf_nvmeof_prop_get_set_nssr[2];
static int hf_nvmeof_prop_get_vs[4];
static int hf_nvmeof_prop_get_ccap[17];


/* NVMe Fabric CQE */
static int hf_nvmeof_cqe;
static int hf_nvmeof_cqe_sts;

static int hf_nvmeof_cqe_connect_cntlid;
static int hf_nvmeof_cqe_connect_authreq;
static int hf_nvmeof_cqe_connect_rsvd;
static int hf_nvmeof_cqe_prop_set_rsvd;

/* tracking Cmd and its respective CQE */
int hf_nvmeof_cmd_pkt;
int hf_nvmeof_data_req;
static int hf_nvmeof_data_tr[NVME_CMD_MAX_TRS];
static int hf_nvmeof_cqe_pkt;
static int hf_nvmeof_cmd_latency;

static const range_string fctype_tbl[] = {
    { NVME_FCTYPE_PROP_SET,      NVME_FCTYPE_PROP_SET,      "Property Set" },
    { NVME_FCTYPE_CONNECT,       NVME_FCTYPE_CONNECT,       "Connect" },
    { NVME_FCTYPE_PROP_GET,      NVME_FCTYPE_PROP_GET,      "Property Get" },
    { NVME_FCTYPE_AUTH_SEND,     NVME_FCTYPE_AUTH_SEND,     "Authentication Send" },
    { NVME_FCTYPE_AUTH_RECV,     NVME_FCTYPE_AUTH_RECV,     "Authentication Recv" },
    { NVME_FCTYPE_DISCONNECT,    NVME_FCTYPE_DISCONNECT,    "Disconnect" },
    { 0xC0, 0xFF,                                           "Vendor Specific" },
    { 0, 0, NULL}
};

static const value_string pclass_tbl[] = {
    { 0x0, "Urgent" },
    { 0x1, "High" },
    { 0x2, "Medium" },
    { 0x3, "Low", },
    { 0, NULL}
};

static const value_string prop_offset_tbl[] = {
    { 0x0,      "Controller Capabilities"},
    { 0x8,      "Version"},
    { 0xc,      "Reserved"},
    { 0x10,     "Reserved"},
    { 0x14,     "Controller Configuration"},
    { 0x18,     "Reserved"},
    { 0x1c,     "Controller Status"},
    { 0x20,     "NVM Subsystem Reset"},
    { 0x24,     "Reserved"},
    { 0x28,     "Reserved"},
    { 0x30,     "Reserved"},
    { 0x38,     "Reserved"},
    { 0x3c,     "Reserved"},
    { 0x40,     "Reserved"},
    { 0x64,     "NVM Subsystem Shutdown"},
    { 0x68,     "Controller Ready Timeouts"},
    { 0, NULL}
};

static const value_string attr_size_tbl[] = {
    { 0,       "4 bytes"},
    { 1,       "8 bytes"},
    { 0, NULL}
};

static const value_string css_table[] = {
     { 0x0, "NVM Command Set"},
     { 0x6, "All Supported I/O Command Sets"},
     { 0x7, "Admin Command Set Only"},
     { 0x0, NULL}
};
static const value_string sn_table[] = {
    { 0x0, "No Shutdown"},
    { 0x1, "Normal Shutdown"},
    { 0x2, "Abrupt Shutdown"},
    { 0x3, "Reserved"},
    { 0x0, NULL}
};
static const value_string ams_table[] = {
    { 0x0, "Round Robin"},
    { 0x1, "Weighted Round Robin with Urgent Priority Class"},
    { 0x2, "Reserved"},
    { 0x3, "Reserved"},
    { 0x4, "Reserved"},
    { 0x5, "Reserved"},
    { 0x6, "Reserved"},
    { 0x7, "Vendor Specific"},
    { 0x0, NULL}
};

/* Shared with the NVMe-MI Controller Health Data Structure CSTS.SHST decode. */
const value_string shst_table[] = {
    { 0x0, "No Shutdown"},
    { 0x1, "Shutdown in Process"},
    { 0x2, "Shutdown Complete"},
    { 0x3, "Reserved"},
    { 0x0, NULL}
};

/* NVMe Cmd fields */
static int hf_nvme_cmd_opc;
static int hf_nvme_cmd_rsvd;
static int hf_nvme_cmd_cid;
static int hf_nvme_cmd_fuse_op;
static int hf_nvme_cmd_psdt;
static int hf_nvme_cmd_nsid;
static int hf_nvme_cmd_rsvd1;
static int hf_nvme_cmd_mptr;
static int hf_nvme_cmd_sgl;
static int hf_nvme_cmd_sgl_desc_type;
static int hf_nvme_cmd_sgl_desc_sub_type;
static int hf_nvme_cmd_sgl_desc_addr;
static int hf_nvme_cmd_sgl_desc_addr_rsvd;
static int hf_nvme_cmd_sgl_desc_len;
static int hf_nvme_cmd_sgl_desc_rsvd;
static int hf_nvme_cmd_sgl_desc_key;
static int hf_nvme_cmd_dword10;
static int hf_nvme_cmd_dword11;
static int hf_nvme_cmd_dword12;
static int hf_nvme_cmd_dword13;
static int hf_nvme_cmd_dword14;
static int hf_nvme_cmd_dword15;
static int hf_nvme_cmd_slba;
static int hf_nvme_cmd_nlb;
static int hf_nvme_cmd_rsvd2;
static int hf_nvme_cmd_prinfo;
static int hf_nvme_cmd_prinfo_prchk_lbrtag;
static int hf_nvme_cmd_prinfo_prchk_apptag;
static int hf_nvme_cmd_prinfo_prchk_guard;
static int hf_nvme_cmd_prinfo_pract;
static int hf_nvme_cmd_fua;
static int hf_nvme_cmd_lr;
static int hf_nvme_cmd_eilbrt;
static int hf_nvme_cmd_elbat;
static int hf_nvme_cmd_elbatm;
static int hf_nvme_cmd_dsm;
static int hf_nvme_cmd_dsm_access_freq;
static int hf_nvme_cmd_dsm_access_lat;
static int hf_nvme_cmd_dsm_seq_req;
static int hf_nvme_cmd_dsm_incompressible;
static int hf_nvme_cmd_rsvd3;
static int hf_nvme_identify_dword10[4];
static int hf_nvme_identify_dword11[4];
static int hf_nvme_identify_dword14[3];

static int hf_nvme_get_logpage_dword10[5];
static int hf_nvme_get_logpage_numd;
static int hf_nvme_get_logpage_dword11[3];
static int hf_nvme_get_logpage_lpo;
static int hf_nvme_get_logpage_dword14[5];
static int hf_nvme_set_features_dword10[4];
static int hf_nvme_set_features_dword14[3];

/* Admin opcodes whose CDW10-15 decode is shared with the NVMe-MI Admin
 * dissector (the request layout is a standard SQE from offset 40 onward). */
static int hf_nvme_format_nvm_dword10[8];
static int hf_nvme_fw_commit_dword10[5];
static int hf_nvme_fw_download_numd;
static int hf_nvme_fw_download_ofst;
static int hf_nvme_self_test_dword10[3];
static int hf_nvme_lockdown_dword10[7];
static int hf_nvme_lockdown_dword14[3];
static int hf_nvme_sanitize_dword10[8];
static int hf_nvme_sanitize_ovrpat;
static int hf_nvme_security_dword10[5];
static int hf_nvme_security_send_dword11_tl;
static int hf_nvme_security_recv_dword11_al;
static int hf_nvme_security_data;
static int hf_nvme_security_info;
static int hf_nvme_security_info_rsvd;
static int hf_nvme_security_info_list_len;
static int hf_nvme_security_info_protocol;
static int hf_nvme_security_info_cert_len;
static int hf_nvme_security_info_cert_data;
static int hf_nvme_cmd_set_features_dword11_arb[6];
static int hf_nvme_cmd_set_features_dword11_pm[4];
static int hf_nvme_cmd_set_features_dword11_lbart[3];
static int hf_nvme_cmd_set_features_dword11_tt[6];
static int hf_nvme_cmd_set_features_dword11_erec[4];
static int hf_nvme_cmd_set_features_dword11_vwce[3];
static int hf_nvme_cmd_set_features_dword11_nq[3];
static int hf_nvme_cmd_set_features_dword11_irqc[3];
static int hf_nvme_cmd_set_features_dword11_irqv[4];
static int hf_nvme_cmd_set_features_dword11_wan[3];
static int hf_nvme_cmd_set_features_dword11_aec[11];
static int hf_nvme_cmd_set_features_dword11_apst[3];
static int hf_nvme_cmd_set_features_dword11_kat[2];
static int hf_nvme_cmd_set_features_dword11_hctm[3];
static int hf_nvme_cmd_set_features_dword11_nops[3];
static int hf_nvme_cmd_set_features_dword11_rrl[3];
static int hf_nvme_cmd_set_features_dword12_rrl[3];
static int hf_nvme_cmd_set_features_dword11_plmc[3];
static int hf_nvme_cmd_set_features_dword12_plmc[3];
static int hf_nvme_cmd_set_features_dword11_plmw[3];
static int hf_nvme_cmd_set_features_dword12_plmw[3];
static int hf_nvme_cmd_set_features_dword11_lbasi[3];
static int hf_nvme_cmd_set_features_dword11_san[3];
static int hf_nvme_cmd_set_features_dword11_eg[4];
static int hf_nvme_cmd_set_features_dword11_swp[3];
static int hf_nvme_cmd_set_features_dword11_hid[3];
static int hf_nvme_cmd_set_features_dword11_rsrvn[6];
static int hf_nvme_cmd_set_features_dword11_rsrvp[3];
static int hf_nvme_cmd_set_features_dword11_nswp[3];
static int hf_nvme_cmd_set_features_dword11_hmd[3];
static int hf_nvme_cmd_set_features_dword11_hmb[6];
static int hf_nvme_cmd_set_features_dword11_iocsp[3];
static int hf_nvme_cmd_set_features_dword11_spinup[3];
static int hf_nvme_cmd_set_features_dword11_plsc[3];
static int hf_nvme_cmd_set_features_dword11_fdp[3];
static int hf_nvme_cmd_set_features_dword11_fdpe[4];
static int hf_nvme_cmd_set_features_dword11_bpwpc[4];
static int hf_nvme_set_features_tr_lbart;
static int hf_nvme_set_features_tr_lbart_type;
static int hf_nvme_set_features_tr_lbart_attr[4];
static int hf_nvme_set_features_tr_lbart_rsvd0;
static int hf_nvme_set_features_tr_lbart_slba;
static int hf_nvme_set_features_tr_lbart_nlb;
static int hf_nvme_set_features_tr_lbart_guid;
static int hf_nvme_set_features_tr_lbart_rsvd1;
static int hf_nvme_set_features_tr_apst[5];
static int hf_nvme_set_features_tr_tst[3];
static int hf_nvme_set_features_tr_plmc;
static int hf_nvme_set_features_tr_plmc_ee[7];
static int hf_nvme_set_features_tr_plmc_rsvd0;
static int hf_nvme_set_features_tr_plmc_dtwinrt;
static int hf_nvme_set_features_tr_plmc_dtwinwt;
static int hf_nvme_set_features_tr_plmc_dtwintt;
static int hf_nvme_set_features_tr_plmc_rsvd1;
static int hf_nvme_set_features_tr_hbs;
static int hf_nvme_set_features_tr_hbs_acre;
static int hf_nvme_set_features_tr_hbs_etdas;
static int hf_nvme_set_features_tr_hbs_lbafee;
static int hf_nvme_set_features_tr_hbs_hdisns;
static int hf_nvme_set_features_tr_hbs_cdfe[6];
static int hf_nvme_set_features_tr_hbs_rsvd;
static int hf_nvme_set_features_tr_hmd;
static int hf_nvme_set_features_tr_hmd_nmed;
static int hf_nvme_set_features_tr_hmd_rsvd;
static int hf_nvme_set_features_tr_hmd_med;
static int hf_nvme_set_features_tr_hmd_med_et;
static int hf_nvme_set_features_tr_hmd_med_er;
static int hf_nvme_set_features_tr_hmd_med_elen;
static int hf_nvme_set_features_tr_hmd_med_eval;
static int hf_nvme_get_features_dword10[4];
static int hf_nvme_get_features_dword14[3];
static int hf_nvme_cmd_get_features_dword11_rrl[3];
static int hf_nvme_cmd_get_features_dword11_plmc[3];
static int hf_nvme_cmd_get_features_dword11_plmw[3];
static int hf_nvme_identify_ns_nsze;
static int hf_nvme_identify_ns_ncap;
static int hf_nvme_identify_ns_nuse;
static int hf_nvme_identify_ns_nsfeat;
static int hf_nvme_identify_ns_nlbaf;
static int hf_nvme_identify_ns_flbas;
static int hf_nvme_identify_ns_mc;
static int hf_nvme_identify_ns_dpc;
static int hf_nvme_identify_ns_dps;
static int hf_nvme_identify_ns_nmic;
static int hf_nvme_identify_ns_rescap;
static int hf_nvme_identify_ns_fpi;
static int hf_nvme_identify_ns_dlfeat[5];
static int hf_nvme_identify_ns_nawun;
static int hf_nvme_identify_ns_nawupf;
static int hf_nvme_identify_ns_nacwu;
static int hf_nvme_identify_ns_nabsn;
static int hf_nvme_identify_ns_nabo;
static int hf_nvme_identify_ns_nabspf;
static int hf_nvme_identify_ns_noiob;
static int hf_nvme_identify_ns_nvmcap;
static int hf_nvme_identify_ns_npwg;
static int hf_nvme_identify_ns_npwa;
static int hf_nvme_identify_ns_npdg;
static int hf_nvme_identify_ns_npda;
static int hf_nvme_identify_ns_nows;
static int hf_nvme_identify_ns_mssrl;
static int hf_nvme_identify_ns_mcl;
static int hf_nvme_identify_ns_msrc;
static int hf_nvme_identify_ns_kpios[4];
static int hf_nvme_identify_ns_nulbaf;
static int hf_nvme_identify_ns_rsvd0;
static int hf_nvme_identify_ns_kpiodaag;
static int hf_nvme_identify_ns_rsvd1;
static int hf_nvme_identify_ns_anagrpid;
static int hf_nvme_identify_ns_rsvd2;
static int hf_nvme_identify_ns_nsattr;
static int hf_nvme_identify_ns_nvmsetid;
static int hf_nvme_identify_ns_endgid;
static int hf_nvme_identify_ns_nguid;
static int hf_nvme_identify_ns_eui64;
static int hf_nvme_identify_ns_lbafs;
static int hf_nvme_identify_ns_lbaf;
static int hf_nvme_identify_ns_vs;
/* CNS 08h: I/O Command Set Independent Identify Namespace (Base 2.3 Fig 335) */
static int hf_nvme_identify_cs_ind_ns_nsfeat[6];
static int hf_nvme_identify_cs_ind_ns_nmic[4];
static int hf_nvme_identify_cs_ind_ns_rescap[9];
static int hf_nvme_identify_cs_ind_ns_fpi[3];
static int hf_nvme_identify_cs_ind_ns_anagrpid;
static int hf_nvme_identify_cs_ind_ns_nsattr[3];
static int hf_nvme_identify_cs_ind_ns_rsvd0;
static int hf_nvme_identify_cs_ind_ns_nvmsetid;
static int hf_nvme_identify_cs_ind_ns_endgid;
static int hf_nvme_identify_cs_ind_ns_nstat[4];
static int hf_nvme_identify_cs_ind_ns_kpios[4];
static int hf_nvme_identify_cs_ind_ns_maxkt;
static int hf_nvme_identify_cs_ind_ns_rsvd1;
static int hf_nvme_identify_cs_ind_ns_rgrpid;
static int hf_nvme_identify_ctrl_vid;
static int hf_nvme_identify_ctrl_ssvid;
static int hf_nvme_identify_ctrl_sn;
static int hf_nvme_identify_ctrl_mn;
static int hf_nvme_identify_ctrl_fr;
static int hf_nvme_identify_ctrl_rab;
static int hf_nvme_identify_ctrl_ieee;
static int hf_nvme_identify_ctrl_cmic[6];
static int hf_nvme_identify_ctrl_mdts;
static int hf_nvme_identify_ctrl_cntlid;
static int hf_nvme_identify_ctrl_ver;
static int hf_nvme_identify_ctrl_ver_min;
static int hf_nvme_identify_ctrl_ver_mjr;
static int hf_nvme_identify_ctrl_ver_ter;
static int hf_nvme_identify_ctrl_rtd3r;
static int hf_nvme_identify_ctrl_rtd3e;
static int hf_nvme_identify_ctrl_oaes[10];
static int hf_nvme_identify_ctrl_ctratt[12];
static int hf_nvme_identify_ctrl_rrls[17];
static int hf_nvme_identify_ctrl_bpcap[4];
static int hf_nvme_identify_ctrl_rsvd0; /* byte 103 */
static int hf_nvme_identify_ctrl_nssl;
static int hf_nvme_identify_ctrl_rsvd6; /* bytes 109:108 */
static int hf_nvme_identify_ctrl_plsi[4];
static int hf_nvme_identify_ctrl_cntrltype;
static int hf_nvme_identify_ctrl_fguid;
static int hf_nvme_identify_ctrl_fguid_vse;
static int hf_nvme_identify_ctrl_fguid_oui;
static int hf_nvme_identify_ctrl_fguid_ei;
static int hf_nvme_identify_ctrl_crdt1;
static int hf_nvme_identify_ctrl_crdt2;
static int hf_nvme_identify_ctrl_crdt3;
static int hf_nvme_identify_ctrl_crcap[4];
static int hf_nvme_identify_ctrl_ciu;
static int hf_nvme_identify_ctrl_cirn;
static int hf_nvme_identify_ctrl_rsvd1; /* bytes 239:144 */
static int hf_nvme_identify_ctrl_mi;
static int hf_nvme_identify_ctrl_mi_rsvd;
static int hf_nvme_identify_ctrl_mi_nvmsr[4];
static int hf_nvme_identify_ctrl_mi_vwci[3];
static int hf_nvme_identify_ctrl_mi_mec[4];
static int hf_nvme_identify_ctrl_oacs[12];
static int hf_nvme_identify_ctrl_acl;
static int hf_nvme_identify_ctrl_aerl;
static int hf_nvme_identify_ctrl_frmw[5];
static int hf_nvme_identify_ctrl_lpa[7];
static int hf_nvme_identify_ctrl_elpe;
static int hf_nvme_identify_ctrl_npss;
static int hf_nvme_identify_ctrl_avscc[3];
static int hf_nvme_identify_ctrl_apsta[3];
static int hf_nvme_identify_ctrl_wctemp;
static int hf_nvme_identify_ctrl_cctemp;
static int hf_nvme_identify_ctrl_mtfa;
static int hf_nvme_identify_ctrl_hmpre;
static int hf_nvme_identify_ctrl_hmmin;
static int hf_nvme_identify_ctrl_tnvmcap;
static int  hf_nvme_identify_ctrl_unvmcap;
static int hf_nvme_identify_ctrl_rpmbs[6];
static int hf_nvme_identify_ctrl_edstt;
static int hf_nvme_identify_ctrl_dsto[3];
static int hf_nvme_identify_ctrl_fwug;
static int hf_nvme_identify_ctrl_kas;
static int hf_nvme_identify_ctrl_hctma[3];
static int hf_nvme_identify_ctrl_mntmt;
static int hf_nvme_identify_ctrl_mxtmt;
static int hf_nvme_identify_ctrl_sanicap[7];
static int hf_nvme_identify_ctrl_hmmminds;
static int hf_nvme_identify_ctrl_hmmaxd;
static int hf_nvme_identify_ctrl_nsetidmax;
static int hf_nvme_identify_ctrl_endgidmax;
static int hf_nvme_identify_ctrl_anatt;
static int hf_nvme_identify_ctrl_anacap[9];
static int hf_nvme_identify_ctrl_anagrpmax;
static int hf_nvme_identify_ctrl_nanagrpid;
static int hf_nvme_identify_ctrl_pels;
static int hf_nvme_identify_ctrl_did;
static int hf_nvme_identify_ctrl_kpioc[4];
static int hf_nvme_identify_ctrl_rsvd2; /* byte 359 */
static int hf_nvme_identify_ctrl_mptfawr;
static int hf_nvme_identify_ctrl_rsvd7; /* bytes 367:362 */
static int hf_nvme_identify_ctrl_megcap;
static int hf_nvme_identify_ctrl_tmpthha[3];
static int hf_nvme_identify_ctrl_mupa[3];
static int hf_nvme_identify_ctrl_cqt;
static int hf_nvme_identify_ctrl_cdpa[3];
static int hf_nvme_identify_ctrl_mup;
static int hf_nvme_identify_ctrl_ipmsr[3];
static int hf_nvme_identify_ctrl_msmt;
static int hf_nvme_identify_ctrl_rsvd8; /* bytes 511:396 */
static int hf_nvme_identify_ctrl_sqes[3];
static int hf_nvme_identify_ctrl_cqes[3];
static int hf_nvme_identify_ctrl_maxcmd;
static int hf_nvme_identify_ctrl_nn;
static int hf_nvme_identify_ctrl_oncs[10];
static int hf_nvme_identify_ctrl_fuses[3];
static int hf_nvme_identify_ctrl_fna[5];
static int hf_nvme_identify_ctrl_vwc[4];
static int hf_nvme_identify_ctrl_awun;
static int hf_nvme_identify_ctrl_awupf;
static int hf_nvme_identify_ctrl_nvscc[3];
static int hf_nvme_identify_ctrl_nwpc[5];
static int hf_nvme_identify_ctrl_acwu;
static int hf_nvme_identify_ctrl_rsvd3;
static int hf_nvme_identify_ctrl_sgls[11];
static int hf_nvme_identify_ctrl_mnan;
static int hf_nvme_identify_ctrl_maxdna;
static int hf_nvme_identify_ctrl_maxcna;
static int hf_nvme_identify_ctrl_oaqd;
static int hf_nvme_identify_ctrl_rhiri;
static int hf_nvme_identify_ctrl_hirt;
static int hf_nvme_identify_ctrl_cmmrtd;
static int hf_nvme_identify_ctrl_nmmrtd;
static int hf_nvme_identify_ctrl_minmrtg;
static int hf_nvme_identify_ctrl_maxmrtg;
static int hf_nvme_identify_ctrl_trattr[5];
static int hf_nvme_identify_ctrl_rsvd4; /* byte 577 */
static int hf_nvme_identify_ctrl_mcudmq;
static int hf_nvme_identify_ctrl_mnsudmq;
static int hf_nvme_identify_ctrl_mcmr;
static int hf_nvme_identify_ctrl_nmcmr;
static int hf_nvme_identify_ctrl_mcdqpc;
static int hf_nvme_identify_ctrl_rsvd9; /* bytes 767:588 */
static int hf_nvme_identify_ctrl_subnqn;
static int hf_nvme_identify_ctrl_rsvd5;
static int hf_nvme_identify_ctrl_nvmeof;
static int hf_nvme_identify_ctrl_nvmeof_ioccsz;
static int hf_nvme_identify_ctrl_nvmeof_iorcsz;
static int hf_nvme_identify_ctrl_nvmeof_icdoff;
static int hf_nvme_identify_ctrl_nvmeof_fcatt[3];
static int hf_nvme_identify_ctrl_nvmeof_msdbd;
static int hf_nvme_identify_ctrl_nvmeof_ofcs[3];
static int hf_nvme_identify_ctrl_nvmeof_dctype;
static int hf_nvme_identify_ctrl_nvmeof_ccrl;
static int hf_nvme_identify_ctrl_nvmeof_rsvd; /* bytes 2047:1808 */
static int hf_nvme_identify_ctrl_psds;
static int hf_nvme_identify_ctrl_psd;
static int hf_nvme_identify_ctrl_psd_mp;
static int hf_nvme_identify_ctrl_psd_rsvd0;
static int hf_nvme_identify_ctrl_psd_mxps;
static int hf_nvme_identify_ctrl_psd_nops;
static int hf_nvme_identify_ctrl_psd_rsvd1;
static int hf_nvme_identify_ctrl_psd_enlat;
static int hf_nvme_identify_ctrl_psd_exlat;
static int hf_nvme_identify_ctrl_psd_rrt;
static int hf_nvme_identify_ctrl_psd_rsvd2;
static int hf_nvme_identify_ctrl_psd_rrl;
static int hf_nvme_identify_ctrl_psd_rsvd3;
static int hf_nvme_identify_ctrl_psd_rwt;
static int hf_nvme_identify_ctrl_psd_rsvd4;
static int hf_nvme_identify_ctrl_psd_rwl;
static int hf_nvme_identify_ctrl_psd_rsvd5;
static int hf_nvme_identify_ctrl_psd_idlp;
static int hf_nvme_identify_ctrl_psd_rsvd6;
static int hf_nvme_identify_ctrl_psd_ips;
static int hf_nvme_identify_ctrl_psd_rsvd7;
static int hf_nvme_identify_ctrl_psd_actp;
static int hf_nvme_identify_ctrl_psd_apw;
static int hf_nvme_identify_ctrl_psd_rsvd8;
static int hf_nvme_identify_ctrl_psd_aps;
static int hf_nvme_identify_ctrl_psd_epfrt;
static int hf_nvme_identify_ctrl_psd_fqvt;
static int hf_nvme_identify_ctrl_psd_epfvt;
static int hf_nvme_identify_ctrl_psd_epfrts;
static int hf_nvme_identify_ctrl_psd_fqvts;
static int hf_nvme_identify_ctrl_psd_epfvts;
static int hf_nvme_identify_ctrl_psd_rsvd9;
static int hf_nvme_identify_ctrl_psd_mbw;
static int hf_nvme_identify_ctrl_psd_mbws;
static int hf_nvme_identify_ctrl_psd_rsvd10;
static int hf_nvme_identify_ctrl_psd_rsvd11;
static int hf_nvme_identify_ctrl_vs;

static int hf_nvme_identify_nslist_nsid;

/* Identify Namespace Identification Descriptor list (CNS 03h) response */
static int hf_nvme_identify_nsdesc_nidt;
static int hf_nvme_identify_nsdesc_nidl;
static int hf_nvme_identify_nsdesc_nid;

/* Identify Controller List (CNS 12h/13h) response */
static int hf_nvme_identify_ctrl_list_num;
static int hf_nvme_identify_ctrl_list_id;

/* Identify NVM Set List (CNS 04h) response */
static int hf_nvme_identify_nvmset_num;
static int hf_nvme_identify_nvmset_id;
static int hf_nvme_identify_nvmset_endgid;
static int hf_nvme_identify_nvmset_r4krt;
static int hf_nvme_identify_nvmset_ows;
static int hf_nvme_identify_nvmset_tnvmsc;
static int hf_nvme_identify_nvmset_unvmsc;

/* Identify Primary Controller Capabilities (CNS 14h) response */
static int hf_nvme_identify_pcc_cntlid;
static int hf_nvme_identify_pcc_portid;
static int hf_nvme_identify_pcc_crt[4];
static int hf_nvme_identify_pcc_vqfrt;
static int hf_nvme_identify_pcc_vqrfa;
static int hf_nvme_identify_pcc_vqrfap;
static int hf_nvme_identify_pcc_vqprt;
static int hf_nvme_identify_pcc_vqfrsm;
static int hf_nvme_identify_pcc_vqgran;
static int hf_nvme_identify_pcc_vifrt;
static int hf_nvme_identify_pcc_virfa;
static int hf_nvme_identify_pcc_virfap;
static int hf_nvme_identify_pcc_viprt;
static int hf_nvme_identify_pcc_vifrsm;
static int hf_nvme_identify_pcc_vigran;

/* Identify Secondary Controller List (CNS 15h) response */
static int hf_nvme_identify_scl_num;
static int hf_nvme_identify_scl_scid;
static int hf_nvme_identify_scl_pcid;
static int hf_nvme_identify_scl_scs[3];
static int hf_nvme_identify_scl_vfn;
static int hf_nvme_identify_scl_nvq;
static int hf_nvme_identify_scl_nvi;

/* Identify Namespace Granularity List (CNS 16h) response */
static int hf_nvme_identify_ngl_nga[3];
static int hf_nvme_identify_ngl_nd;
static int hf_nvme_identify_ngl_nsg;
static int hf_nvme_identify_ngl_ncg;

/* Identify UUID List (CNS 17h) response */
static int hf_nvme_identify_uuid_idassoc;
static int hf_nvme_identify_uuid_uuid;

/* get logpage response */
static int hf_nvme_get_logpage_ify_genctr;
static int hf_nvme_get_logpage_ify_numrec;
static int hf_nvme_get_logpage_ify_recfmt;
static int hf_nvme_get_logpage_ify_rsvd;
static int hf_nvme_get_logpage_ify_rcrd;
static int hf_nvme_get_logpage_ify_rcrd_trtype;
static int hf_nvme_get_logpage_ify_rcrd_adrfam;
static int hf_nvme_get_logpage_ify_rcrd_subtype;
static int hf_nvme_get_logpage_ify_rcrd_treq[6];
static int hf_nvme_get_logpage_ify_rcrd_portid;
static int hf_nvme_get_logpage_ify_rcrd_cntlid;
static int hf_nvme_get_logpage_ify_rcrd_asqsz;
static int hf_nvme_get_logpage_ify_rcrd_rsvd0;
static int hf_nvme_get_logpage_ify_rcrd_trsvcid;
static int hf_nvme_get_logpage_ify_rcrd_rsvd1;
static int hf_nvme_get_logpage_ify_rcrd_subnqn;
static int hf_nvme_get_logpage_ify_rcrd_traddr;
static int hf_nvme_get_logpage_ify_rcrd_tsas;
static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_qptype;
static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_prtype;
static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_cms;
static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd0;
static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_pkey;
static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd1;
static int hf_nvme_get_logpage_ify_rcrd_tsas_tcp_sectype;
static int hf_nvme_get_logpage_ify_rcrd_tsas_tcp_rsvd;
static int hf_nvme_get_logpage_errinf_errcnt;
static int hf_nvme_get_logpage_errinf_sqid;
static int hf_nvme_get_logpage_errinf_cid;
static int hf_nvme_get_logpage_errinf_sf[3];
static int hf_nvme_get_logpage_errinf_pel[4];
static int hf_nvme_get_logpage_errinf_lba;
static int hf_nvme_get_logpage_errinf_ns;
static int hf_nvme_get_logpage_errinf_vsi;
static int hf_nvme_get_logpage_errinf_trtype;
static int hf_nvme_get_logpage_errinf_cmdset;
static int hf_nvme_get_logpage_errinf_opc;
static int hf_nvme_get_logpage_errinf_csi;
static int hf_nvme_get_logpage_errinf_tsi;
static int hf_nvme_get_logpage_errinf_rsvd1;
static int hf_nvme_get_logpage_errinf_lpver;
static int hf_nvme_get_logpage_smart_cw[9];
static int hf_nvme_get_logpage_smart_ct;
static int hf_nvme_get_logpage_smart_asc;
static int hf_nvme_get_logpage_smart_ast;
static int hf_nvme_get_logpage_smart_lpu;
static int hf_nvme_get_logpage_smart_egcws[6];
static int hf_nvme_get_logpage_smart_rsvd0;
static int hf_nvme_get_logpage_smart_dur;
static int hf_nvme_get_logpage_smart_duw;
static int hf_nvme_get_logpage_smart_hrc;
static int hf_nvme_get_logpage_smart_hwc;
static int hf_nvme_get_logpage_smart_cbt;
static int hf_nvme_get_logpage_smart_pc;
static int hf_nvme_get_logpage_smart_poh;
static int hf_nvme_get_logpage_smart_us;
static int hf_nvme_get_logpage_smart_mie;
static int hf_nvme_get_logpage_smart_ele;
static int hf_nvme_get_logpage_smart_wctt;
static int hf_nvme_get_logpage_smart_cctt;
static int hf_nvme_get_logpage_smart_ts[9];
static int hf_nvme_get_logpage_smart_tmt1c;
static int hf_nvme_get_logpage_smart_tmt2c;
static int hf_nvme_get_logpage_smart_tmt1t;
static int hf_nvme_get_logpage_smart_tmt2t;
static int hf_nvme_get_logpage_smart_rsvd1;
static int hf_nvme_get_logpage_fw_slot_afi[5];
static int hf_nvme_get_logpage_fw_slot_rsvd0;
static int hf_nvme_get_logpage_fw_slot_frs;
static int hf_nvme_get_logpage_fw_slot_frs_ascii[7];
static int hf_nvme_get_logpage_fw_slot_rsvd1;
static int hf_nvme_get_logpage_changed_nslist;
static int hf_nvme_get_logpage_cmd_and_eff_cs;
static int hf_nvme_get_logpage_cmd_and_eff_cseds[10];
static int hf_nvme_get_logpage_supported_lids;
static int hf_nvme_get_logpage_supported_lidseds[5];
static int hf_nvme_get_logpage_selftest_csto[3];
static int hf_nvme_get_logpage_selftest_cstc[3];
static int hf_nvme_get_logpage_selftest_rsvd;
static int hf_nvme_get_logpage_selftest_res;
static int hf_nvme_get_logpage_selftest_res_status[3];
static int hf_nvme_get_logpage_selftest_res_sn;
static int hf_nvme_get_logpage_selftest_res_vdi[6];
static int hf_nvme_get_logpage_selftest_res_rsvd;
static int hf_nvme_get_logpage_selftest_res_poh;
static int hf_nvme_get_logpage_selftest_res_nsid;
static int hf_nvme_get_logpage_selftest_res_flba;
static int hf_nvme_get_logpage_selftest_res_sct[3];
static int hf_nvme_get_logpage_selftest_res_sc;
static int hf_nvme_get_logpage_selftest_res_vs;
static int hf_nvme_get_logpage_telemetry_li;
static int hf_nvme_get_logpage_telemetry_rsvd0;
static int hf_nvme_get_logpage_telemetry_ieee;
static int hf_nvme_get_logpage_telemetry_da1lb;
static int hf_nvme_get_logpage_telemetry_da2lb;
static int hf_nvme_get_logpage_telemetry_da3lb;
static int hf_nvme_get_logpage_telemetry_rsvd1;
static int hf_nvme_get_logpage_telemetry_da4lb;
static int hf_nvme_get_logpage_telemetry_rsvd2;
static int hf_nvme_get_logpage_telemetry_scope;
static int hf_nvme_get_logpage_telemetry_hdgn;
static int hf_nvme_get_logpage_telemetry_da;
static int hf_nvme_get_logpage_telemetry_dgn;
static int hf_nvme_get_logpage_telemetry_ri;
static int hf_nvme_get_logpage_telemetry_db;
static int hf_nvme_get_logpage_egroup_cw[6];
static int hf_nvme_get_logpage_egroup_egfeat[3];
static int hf_nvme_get_logpage_egroup_rsvd0;
static int hf_nvme_get_logpage_egroup_as;
static int hf_nvme_get_logpage_egroup_ast;
static int hf_nvme_get_logpage_egroup_pu;
static int hf_nvme_get_logpage_egroup_did;
static int hf_nvme_get_logpage_egroup_rsvd1;
static int hf_nvme_get_logpage_egroup_ee;
static int hf_nvme_get_logpage_egroup_dur;
static int hf_nvme_get_logpage_egroup_duw;
static int hf_nvme_get_logpage_egroup_muw;
static int hf_nvme_get_logpage_egroup_hrc;
static int hf_nvme_get_logpage_egroup_hwc;
static int hf_nvme_get_logpage_egroup_mdie;
static int hf_nvme_get_logpage_egroup_ele;
static int hf_nvme_get_logpage_egroup_tegcap;
static int hf_nvme_get_logpage_egroup_uegcap;
static int hf_nvme_get_logpage_egroup_rsvd2;
static int hf_nvme_get_logpage_pred_lat_status[3];
static int hf_nvme_get_logpage_pred_lat_rsvd0;
static int hf_nvme_get_logpage_pred_lat_etype[7];
static int hf_nvme_get_logpage_pred_lat_rsvd1;
static int hf_nvme_get_logpage_pred_lat_dtwin_rt;
static int hf_nvme_get_logpage_pred_lat_dtwin_wt;
static int hf_nvme_get_logpage_pred_lat_dtwin_tm;
static int hf_nvme_get_logpage_pred_lat_ndwin_tmh;
static int hf_nvme_get_logpage_pred_lat_ndwin_tml;
static int hf_nvme_get_logpage_pred_lat_rsvd2;
static int hf_nvme_get_logpage_pred_lat_dtwin_re;
static int hf_nvme_get_logpage_pred_lat_dtwin_we;
static int hf_nvme_get_logpage_pred_lat_dtwin_te;
static int hf_nvme_get_logpage_pred_lat_rsvd3;
static int hf_nvme_get_logpage_pred_lat_aggreg_ne;
static int hf_nvme_get_logpage_pred_lat_aggreg_nset;
static int hf_nvme_get_logpage_ana_chcnt;
static int hf_nvme_get_logpage_ana_ngd;
static int hf_nvme_get_logpage_ana_rsvd;
static int hf_nvme_get_logpage_ana_grp;
static int hf_nvme_get_logpage_ana_grp_id;
static int hf_nvme_get_logpage_ana_grp_nns;
static int hf_nvme_get_logpage_ana_grp_chcnt;
static int hf_nvme_get_logpage_ana_grp_anas[3];
static int hf_nvme_get_logpage_ana_grp_rsvd;
static int hf_nvme_get_logpage_ana_grp_nsid;
static int hf_nvme_get_logpage_lba_status_lslplen;
static int hf_nvme_get_logpage_lba_status_nlslne;
static int hf_nvme_get_logpage_lba_status_estulb;
static int hf_nvme_get_logpage_lba_status_rsvd;
static int hf_nvme_get_logpage_lba_status_lsgc;
static int hf_nvme_get_logpage_lba_status_nel;
static int hf_nvme_get_logpage_lba_status_nel_ne;
static int hf_nvme_get_logpage_lba_status_nel_ne_neid;
static int hf_nvme_get_logpage_lba_status_nel_ne_nlrd;
static int hf_nvme_get_logpage_lba_status_nel_ne_ratype;
static int hf_nvme_get_logpage_lba_status_nel_ne_rsvd;
static int hf_nvme_get_logpage_lba_status_nel_ne_rd;
static int hf_nvme_get_logpage_lba_status_nel_ne_rd_rslba;
static int hf_nvme_get_logpage_lba_status_nel_ne_rd_rnlb;
static int hf_nvme_get_logpage_lba_status_nel_ne_rd_rsvd;
static int hf_nvme_get_logpage_egroup_aggreg_ne;
static int hf_nvme_get_logpage_egroup_aggreg_eg;
static int hf_nvme_get_logpage_reserv_notif_lpc;
static int hf_nvme_get_logpage_reserv_notif_lpt;
static int hf_nvme_get_logpage_reserv_notif_nalp;
static int hf_nvme_get_logpage_reserv_notif_rsvd0;
static int hf_nvme_get_logpage_reserv_notif_nsid;
static int hf_nvme_get_logpage_reserv_notif_rsvd1;
static int hf_nvme_get_logpage_sanitize_sprog;
static int hf_nvme_get_logpage_sanitize_sstat[7];
static int hf_nvme_get_logpage_sanitize_scdw10;
static int hf_nvme_get_logpage_sanitize_eto;
static int hf_nvme_get_logpage_sanitize_etbe;
static int hf_nvme_get_logpage_sanitize_etce;
static int hf_nvme_get_logpage_sanitize_etond;
static int hf_nvme_get_logpage_sanitize_etbend;
static int hf_nvme_get_logpage_sanitize_etcend;
static int hf_nvme_get_logpage_sanitize_etpvds;
static int hf_nvme_get_logpage_sanitize_ssi[3];
static int hf_nvme_get_logpage_sanitize_rsvd0;
static int hf_nvme_get_logpage_sanitize_mnsoip;
static int hf_nvme_get_logpage_sanitize_stnsid;
static int hf_nvme_get_logpage_sanitize_rsvd;
static int hf_nvme_get_logpage_disc_rcrd_eflags[5];
/* Feature Identifiers Supported and Effects Response */
static int hf_nvme_get_logpage_feat_sup_and_eff_fidx;
static int hf_nvme_get_logpage_feat_sup_and_eff_fids[9];
/* NVMe-MI Commands Supported and Effects Response */
static int hf_nvme_get_logpage_mi_cmd_sup_and_eff_cs;
static int hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[8];
/* Command and Feature Lockdown Response */
static int hf_nvme_get_logpage_cmd_feat_lockdown_cfila[4];
static int hf_nvme_get_logpage_cmd_feat_lockdown_rsvd;
static int hf_nvme_get_logpage_cmd_feat_lockdown_lngth;
static int hf_nvme_get_logpage_cmd_feat_lockdown_cfil;
static int hf_nvme_get_logpage_cmd_feat_lockdown_rsvd1;
/* Physical Interface Receiver Eye Opening Measurement Response (LID 19h) */
static int hf_nvme_get_logpage_eom_lid;
static int hf_nvme_get_logpage_eom_eomip;
static int hf_nvme_get_logpage_eom_hsize;
static int hf_nvme_get_logpage_eom_rsz;
static int hf_nvme_get_logpage_eom_edgn;
static int hf_nvme_get_logpage_eom_lrev;
static int hf_nvme_get_logpage_eom_odp[4];
static int hf_nvme_get_logpage_eom_lns;
static int hf_nvme_get_logpage_eom_epl;
static int hf_nvme_get_logpage_eom_lspfc[3];
static int hf_nvme_get_logpage_eom_linfo[3];
static int hf_nvme_get_logpage_eom_rsvd0;
static int hf_nvme_get_logpage_eom_lsic;
static int hf_nvme_get_logpage_eom_ds;
static int hf_nvme_get_logpage_eom_nd;
static int hf_nvme_get_logpage_eom_maxtb;
static int hf_nvme_get_logpage_eom_maxlr;
static int hf_nvme_get_logpage_eom_etgood;
static int hf_nvme_get_logpage_eom_etbetter;
static int hf_nvme_get_logpage_eom_etbest;
static int hf_nvme_get_logpage_eom_rsvd1;
static int hf_nvme_get_logpage_eom_desc;
static int hf_nvme_get_logpage_eom_desc_rsvd0;
static int hf_nvme_get_logpage_eom_desc_mstat[3];
static int hf_nvme_get_logpage_eom_desc_ln;
static int hf_nvme_get_logpage_eom_desc_eye;
static int hf_nvme_get_logpage_eom_desc_top;
static int hf_nvme_get_logpage_eom_desc_btm;
static int hf_nvme_get_logpage_eom_desc_lft;
static int hf_nvme_get_logpage_eom_desc_rgt;
static int hf_nvme_get_logpage_eom_desc_nrows;
static int hf_nvme_get_logpage_eom_desc_ncols;
static int hf_nvme_get_logpage_eom_desc_edlen;
static int hf_nvme_get_logpage_eom_desc_rsvd1;
static int hf_nvme_get_logpage_eom_desc_pe;
static int hf_nvme_get_logpage_eom_desc_ed;

/* NVMe CQE fields */
static int hf_nvme_cqe_dword0;
static int hf_nvme_cqe_aev_dword0[6];
static int hf_nvme_cqe_dword0_sf_nq[3];
static int hf_nvme_cqe_dword0_sf_err;

static int hf_nvme_cqe_get_features_dword0_arb[6];
static int hf_nvme_cqe_get_features_dword0_pm[4];
static int hf_nvme_cqe_get_features_dword0_lbart[3];
static int hf_nvme_cqe_get_features_dword0_tt[6];
static int hf_nvme_cqe_get_features_dword0_erec[4];
static int hf_nvme_cqe_get_features_dword0_vwce[3];
static int hf_nvme_cqe_get_features_dword0_nq[3];
static int hf_nvme_cqe_get_features_dword0_irqc[3];
static int hf_nvme_cqe_get_features_dword0_irqv[4];
static int hf_nvme_cqe_get_features_dword0_wan[3];
static int hf_nvme_cqe_get_features_dword0_aec[11];
static int hf_nvme_cqe_get_features_dword0_apst[3];
static int hf_nvme_cqe_get_features_dword0_kat[2];
static int hf_nvme_cqe_get_features_dword0_hctm[3];
static int hf_nvme_cqe_get_features_dword0_nops[3];
static int hf_nvme_cqe_get_features_dword0_rrl[3];
static int hf_nvme_cqe_get_features_dword0_plmc[3];
static int hf_nvme_cqe_get_features_dword0_plmw[3];
static int hf_nvme_cqe_get_features_dword0_lbasi[3];
static int hf_nvme_cqe_get_features_dword0_san[3];
static int hf_nvme_cqe_get_features_dword0_eg[4];
static int hf_nvme_cqe_get_features_dword0_swp[3];
static int hf_nvme_cqe_get_features_dword0_hid[3];
static int hf_nvme_cqe_get_features_dword0_rsrvn[6];
static int hf_nvme_cqe_get_features_dword0_rsrvp[3];
static int hf_nvme_cqe_get_features_dword0_nswp[3];

static int hf_nvme_cqe_dword1;
static int hf_nvme_cqe_sqhd;
static int hf_nvme_cqe_sqid;
static int hf_nvme_cqe_cid;
static int hf_nvme_cqe_status[7];
static int hf_nvme_cqe_status_rsvd;

/* tracking Cmd and its respective CQE */
static int hf_nvme_cmd_pkt;
static int hf_nvme_data_req;
static int hf_nvme_data_tr[NVME_CMD_MAX_TRS];
static int hf_nvme_cqe_pkt;
static int hf_nvme_cmd_latency;

/* Data response fields */
static int hf_nvme_gen_data;
/* Initialize the subtree pointers */
static int ett_data;

static expert_field ei_nvme_cqe_status_error;
static expert_field ei_nvme_lbaf_count_invalid;
static expert_field ei_nvme_data_len_exceeds_frame;
static expert_field ei_nvme_logpage_window_misaligned;
static expert_field ei_nvme_eom_desc_truncated;

/* NVME_AQ_OPC_* admin opcodes are defined in packet-nvme.h (shared with the
 * NVMe-MI Admin dissector). */

#define NVME_IOQ_OPC_FLUSH                  0x0
#define NVME_IOQ_OPC_WRITE                  0x1
#define NVME_IOQ_OPC_READ                   0x2
#define NVME_IOQ_OPC_WRITE_UNCORRECTABLE    0x4
#define NVME_IOQ_OPC_COMPARE                0x5
#define NVME_IOQ_OPC_WRITE_ZEROS            0x8
#define NVME_IOQ_OPC_DATASET_MGMT           0x9
#define NVME_IOQ_OPC_VERIFY                 0xc
#define NVME_IOQ_OPC_RESV_REG               0xd
#define NVME_IOQ_OPC_RESV_REPORT            0xe
#define NVME_IOQ_OPC_RESV_ACQUIRE           0x11
#define NVME_IOQ_OPC_IO_MGMT_RECV           0x12
#define NVME_IOQ_OPC_RESV_RELEASE           0x15
#define NVME_IOQ_OPC_CANCEL                 0x18
#define NVME_IOQ_OPC_COPY                   0x19
#define NVME_IOQ_OPC_IO_MGMT_SEND           0x1d

/* NVME_IDENTIFY_CNS_* values are defined in packet-nvme.h. */

typedef enum {
    NVME_CQE_SCT_GENERIC = 0x0,
    NVME_CQE_SCT_COMMAND = 0x1,
    NVME_CQE_SCT_MEDIA = 0x2,
    NVME_CQE_SCT_PATH = 0x3,
    NVME_CQE_SCT_VENDOR = 0x7,
} nvme_cqe_sct_t;

typedef enum {
    NVME_CQE_SC_GEN_CMD_OK = 0x00,
    NVME_CQE_SC_CMD_INVALID_OPCODE = 0x01,
    NVME_CQE_SC_GEN_CMD_INVALID_FIELD = 0x02,
    NVME_CQE_SC_GEN_CMD_CID_CONFLICT = 0x03,
    NVME_CQE_SC_GEN_DATA_TRANSFER_ERR = 0x04,
    NVME_CQE_SC_GEN_ABORT_DUE_TO_POWER_LOSS = 0x05,
    NVME_CQE_SC_GEN_INTERNAL_ERROR = 0x06,
    NVME_CQE_SC_GEN_ABORT_REQUESTED = 0x07,
    NVME_CQE_SC_GEN_ABORT_DUE_TO_SQ_DELETE = 0x08,
    NVME_CQE_SC_GEN_ABORT_DUE_TO_FAILED_FUSE = 0x09,
    NVME_CQE_SC_GEN_ABORT_DUE_TO_MISSED_FUSE = 0x0A,
    NVME_CQE_SC_GEN_INVALID_NAMESPACE_OR_FMT = 0x0B,
    NVME_CQE_SC_GEN_COMMAND_SEQUENCE_ERR = 0x0C,
    NVME_CQE_SC_GEN_INVALID_SGL_SD = 0x0D,
    NVME_CQE_SC_GEN_INVALID_SGL_SD_NUM = 0x0E,
    NVME_CQE_SC_GEN_INVALID_SGL_LEN = 0x0F,
    NVME_CQE_SC_GEN_INVALID_MDATA_SGL_LEN = 0x10,
    NVME_CQE_SC_GEN_INVALID_SGL_SD_TYPE = 0x11,
    NVME_CQE_SC_GEN_INVALID_USE_OF_MC_BUF = 0x12,
    NVME_CQE_SC_GEN_INVALID_PRP_OFFSET = 0x13,
    NVME_CQE_SC_GEN_ATOMIC_WRITE_UNIT_EXCEED = 0x14,
    NVME_CQE_SC_GEN_OPERATION_DENIED = 0x15,
    NVME_CQE_SC_GEN_INVALID_SGL_OFFSET = 0x16,
    NVME_CQE_SC_GEN_RESERVED_17H = 0x17,
    NVME_CQE_SC_GEN_HOST_ID_INVALID_FMT = 0x18,
    NVME_CQE_SC_GEN_KEEP_ALLIVE_EXPIRED = 0x19,
    NVME_CQE_SC_GEN_KEEP_ALIVE_INVALID = 0x1A,
    NVME_CQE_SC_GEN_ABORT_DUE_TO_PREEMPT_ABRT = 0x1B,
    NVME_CQE_SC_GEN_SANITIZE_FAILED = 0x1C,
    NVME_CQE_SC_GEN_SANITZE_IN_PROGRESS = 0x1D,
    NVME_CQE_SC_GEN_SGL_BLOCK_GRAN_INVALID = 0x1E,
    NVME_CQE_SC_GEN_CMD_NOT_SUPP_IN_CMB = 0x1F,
    NVME_CQE_SC_GEN_NAMESPACE_IS_WP = 0x20,
    NVME_CQE_SC_GEN_COMMAND_INTERRUPTED = 0x21,
    NVME_CQE_SC_GEN_TRANSIENT_TRASPORT_ERROR = 0x22,
    NVME_CQE_SC_GEN_CMD_PROHIBITED_LOCKDOWN = 0x23,
    NVME_CQE_SC_GEN_ADMIN_CMD_MEDIA_NOT_READY = 0x24,
    NVME_CQE_SC_GEN_INVALID_KEY_TAG = 0x25,
    NVME_CQE_SC_GEN_HOST_DISP_NS_SUPP_NOT_ENABLED = 0x26,
    NVME_CQE_SC_GEN_HOST_ID_NOT_INITIALIZED = 0x27,
    NVME_CQE_SC_GEN_INCORRECT_KEY = 0x28,
    NVME_CQE_SC_GEN_FDP_DISABLED = 0x29,
    NVME_CQE_SC_GEN_INVALID_PLACEMENT_HANDLE_LIST = 0x2A,
    NVME_CQE_SC_GEN_SANITIZE_NAMESPACE_FAILED = 0x2B,
    NVME_CQE_SC_GEN_SANITIZE_NAMESPACE_IN_PROGRESS = 0x2C,
    NVME_CQE_SC_GEN_LBA_OUT_OF_RANGE = 0x80,
    NVME_CQE_SC_GEN_CAPACITY_EXCEED = 0x81,
    NVME_CQE_SC_GEN_NAMESPACE_NOT_ERADY = 0x82,
    NVME_CQE_SC_GEN_RESERVATION_CONFLICT = 0x83,
    NVME_CQE_SC_GEN_FMT_IN_PROGRESS = 0x84,
    NVME_CQE_SC_GEN_INVALID_VALUE_SIZE = 0x85,
    NVME_CQE_SC_GEN_INVALID_KEY_SIZE = 0x86,
    NVME_CQE_SC_GEN_KV_KEY_DOES_NOT_EXIST = 0x87,
    NVME_CQE_SC_GEN_UNRECOVERED_ERROR = 0x88,
    NVME_CQE_SC_GEN_KEY_EXISTS = 0x89,
} nvme_cqe_sc_gen_t;

typedef enum {
    NVME_CQE_SC_CMD_INVALID_CQ = 0x00,
    NVME_CQE_SC_CMD_INVALID_QID = 0x01,
    NVME_CQE_SC_CMD_INVALID_QUEUE_SIZE = 0x02,
    NVME_CQE_SC_CMD_ABORT_LIMIT_EXCEED = 0x03,
    NVME_CQE_SC_CMD_RESERVED_4H = 0x04,
    NVME_CQE_SC_CMD_ASYNC_REQ_LIMIT_EXCEED = 0x05,
    NVME_CQE_SC_CMD_INVALID_FW_SLOT = 0x06,
    NVME_CQE_SC_CMD_INVALID_FW_IMAGE = 0x07,
    NVME_CQE_SC_CMD_INVALID_IRQ_VECTOR = 0x08,
    NVME_CQE_SC_CMD_INVALID_LOG_PAGE = 0x09,
    NVME_CQE_SC_CMD_INVALID_FMT = 0x0A,
    NVME_CQE_SC_CMD_FW_ACTIVATION_NEEDS_RESET = 0x0B,
    NVME_CQE_SC_CMD_INVALID_QUEUE_DELETE = 0x0C,
    NVME_CQE_SC_CMD_FEATURE_ID_NOT_SAVEABLE = 0x0D,
    NVME_CQE_SC_CMD_FEATURE_NOT_CHANGEABLE = 0x0E,
    NVME_CQE_SC_CMD_FEATURE_NOT_NAMESPACE = 0x0F,
    NVME_CQE_SC_CMD_FEATURE_ACTIVATION_NEEDS_NVM_RESET = 0x10,
    NVME_CQE_SC_CMD_FEATURE_ACTIVATION_NEEDS_CNTRL_RESET = 0x11,
    NVME_CQE_SC_CMD_FW_ACTIVATION_NEED_MAX_TIME = 0x12,
    NVME_CQE_SC_CMD_FW_ACTIVATION_PROHIBITED = 0x13,
    NVME_CQE_SC_CMD_OVERLAPPING_RANGE = 0x14,
    NVME_CQE_SC_CMD_NAMESPACE_INSUF_CAPACITY = 0x15,
    NVME_CQE_SC_CMD_NAMESPACE_ID_NOT_AVAILABLE = 0x16,
    NVME_CQE_SC_CMD_RESERVED_17H = 0x17,
    NVME_CQE_SC_CMD_NAMESPACE_ALREADY_ATATCHED = 0x18,
    NVME_CQE_SC_CMD_NAMESPACE_IS_PRIVATE = 0x19,
    NVME_CQE_SC_CMD_NAMESPACE_NOT_ATTACHED = 0x1A,
    NVME_CQE_SC_CMD_THIN_PROVISION_NOT_SUPP = 0x1B,
    NVME_CQE_SC_CMD_INVALID_CNTRL_LIST = 0x1C,
    NVME_CQE_SC_CMD_SELF_TEST_IN_PROGRESS = 0x1D,
    NVME_CQE_SC_CMD_BOOT_PART_WRITE_PROHIBIT = 0x1E,
    NVME_CQE_SC_CMD_INVALID_CNTRL_ID = 0x1F,
    NVME_CQE_SC_CMD_INVALID_SECOND_CNTRL_STATE = 0x20,
    NVME_CQE_SC_CMD_IBVALID_CNRL_RES_NUM = 0x21,
    NVME_CQE_SC_CMD_INVALID_RESOURSE_ID = 0x22,
    NVME_CQE_SC_CMD_SANITIZE_PROHIBIT_WITH_PMR = 0x23,
    NVME_CQE_SC_CMD_INVALID_ANA_GROUP_ID = 0x24,
    NVME_CQE_SC_CMD_ANA_ATTACH_FAILED = 0x25,
    NVME_CQE_SC_CMD_INSUFFICIENT_CAPACITY = 0x26,
    NVME_CQE_SC_CMD_NS_ATTACHMENT_LIMIT_EXCEEDED = 0x27,
    NVME_CQE_SC_CMD_PROHIBITION_NOT_SUPPORTED = 0x28,
    NVME_CQE_SC_CMD_IO_CMD_SET_NOT_SUPPORTED = 0x29,
    NVME_CQE_SC_CMD_IO_CMD_SET_NOT_ENABLED = 0x2A,
    NVME_CQE_SC_CMD_IO_CMD_SET_COMBINATION_REJECTED = 0x2B,
    NVME_CQE_SC_CMD_INVALID_IO_CMD_SET = 0x2C,
    NVME_CQE_SC_CMD_IDENTIFIER_UNAVAILABLE = 0x2D,
    NVME_CQE_SC_CMD_NAMESPACE_IS_DISPERSED = 0x2E,
    NVME_CQE_SC_CMD_INVALID_DISCOVERY_INFO = 0x2F,
    NVME_CQE_SC_CMD_ZONING_DS_LOCKED = 0x30,
    NVME_CQE_SC_CMD_ZONING_DS_NOT_FOUND = 0x31,
    NVME_CQE_SC_CMD_INSUFFICIENT_DISCOVERY_RES = 0x32,
    NVME_CQE_SC_CMD_REQUESTED_FUNCTION_DISABLED = 0x33,
    NVME_CQE_SC_CMD_ZONEGROUP_ORIGINATOR_INVALID = 0x34,
    NVME_CQE_SC_CMD_INVALID_HOST = 0x35,
    NVME_CQE_SC_CMD_INVALID_NVM_SUBSYSTEM = 0x36,
    NVME_CQE_SC_CMD_INVALID_CTRL_DATA_QUEUE = 0x37,
    NVME_CQE_SC_CMD_NOT_ENOUGH_RESOURCES = 0x38,
    NVME_CQE_SC_CMD_CONTROLLER_SUSPENDED = 0x39,
    NVME_CQE_SC_CMD_CONTROLLER_NOT_SUSPENDED = 0x3A,
    NVME_CQE_SC_CMD_CTRL_DATA_QUEUE_FULL = 0x3B,
    NVME_CQE_SC_CMD_EXCEEDS_MAX_NS_SANITIZE_OPS = 0x3C,
    NVME_CQE_SC_CMD_MFG_DEFAULT_PERSONALITY_REQUIRED = 0x3D,
    NVME_CQE_SC_CMD_INVALID_POWER_LIMIT = 0x3E,
    NVME_CQE_SC_CMD_CROSS_CTRL_RESET_IN_PROGRESS = 0x3F,
    NVME_CQE_SC_CMD_CROSS_CTRL_RESET_LOG_PAGE_FULL = 0x40,
    NVME_CQE_SC_CMD_CROSS_CTRL_RESET_LIMIT_EXCEEDED = 0x41,
    NVME_CQE_SC_CMD_CONFLICTING_ATTRS = 0x80,
    NVME_CQE_SC_CMD_INVALID_PROTECTION_INF = 0x81,
    NVME_CQE_SC_CMD_WRITE_TO_RO_REGION = 0x82,
    NVME_CQE_SC_CMD_SIZE_LIMIT_EXCEEDED = 0x83,
    NVME_CQE_SC_CMD_INVALID_COMMAND_ID = 0x84,
    NVME_CQE_SC_CMD_INCOMPAT_NAMESPACE_OR_FMT = 0x85,
    NVME_CQE_SC_CMD_FAST_COPY_NOT_POSSIBLE = 0x86,
    NVME_CQE_SC_CMD_OVERLAPPING_IO_RANGE = 0x87,
    NVME_CQE_SC_CMD_NAMESPACE_NOT_REACHABLE = 0x88,
    NVME_CQE_SC_CMD_INSUFFICIENT_RESOURCES = 0x89,
    NVME_CQE_SC_CMD_INSUFFICIENT_PROGRAM_RESOURCES = 0x8A,
    NVME_CQE_SC_CMD_INVALID_MEMORY_NAMESPACE = 0x8B,
    NVME_CQE_SC_CMD_INVALID_MEMORY_RANGE_SET = 0x8C,
    NVME_CQE_SC_CMD_INVALID_MEMORY_RANGE_SET_ID = 0x8D,
    NVME_CQE_SC_CMD_INVALID_PROGRAM_DATA = 0x8E,
    NVME_CQE_SC_CMD_INVALID_PROGRAM_INDEX = 0x8F,
    NVME_CQE_SC_CMD_INVALID_PROGRAM_TYPE = 0x90,
    NVME_CQE_SC_CMD_MAX_MEMORY_RANGES_EXCEEDED = 0x91,
    NVME_CQE_SC_CMD_MAX_MEMORY_RANGE_SETS_EXCEEDED = 0x92,
    NVME_CQE_SC_CMD_MAX_PROGRAMS_ACTIVATED = 0x93,
    NVME_CQE_SC_CMD_MAX_PROGRAM_BYTES_EXCEEDED = 0x94,
    NVME_CQE_SC_CMD_MEMORY_RANGE_SET_IN_USE = 0x95,
    NVME_CQE_SC_CMD_NO_PROGRAM = 0x96,
    NVME_CQE_SC_CMD_OVERLAPPING_MEMORY_RANGES = 0x97,
    NVME_CQE_SC_CMD_PROGRAM_NOT_ACTIVATED = 0x98,
    NVME_CQE_SC_CMD_PROGRAM_IN_USE = 0x99,
    NVME_CQE_SC_CMD_PROGRAM_INDEX_NOT_DOWNLOADABLE = 0x9A,
    NVME_CQE_SC_CMD_PROGRAM_TOO_BIG = 0x9B,
    NVME_CQE_SC_CMD_SUCCESSFUL_MEDIA_VERIFICATION_READ = 0x9C,
    NVME_CQE_SC_CMD_ZONE_BOUNDARY_ERROR = 0xB8,
    NVME_CQE_SC_CMD_ZONE_IS_FULL = 0xB9,
    NVME_CQE_SC_CMD_ZONE_IS_READ_ONLY = 0xBA,
    NVME_CQE_SC_CMD_ZONE_IS_OFFLINE = 0xBB,
    NVME_CQE_SC_CMD_ZONE_INVALID_WRITE = 0xBC,
    NVME_CQE_SC_CMD_TOO_MANY_ACTIVE_ZONES = 0xBD,
    NVME_CQE_SC_CMD_TOO_MANY_OPEN_ZONES = 0xBE,
    NVME_CQE_SC_CMD_INVALID_ZONE_STATE_TRANSITION = 0xBF,
} nvme_cqe_sc_cmd_t;

typedef enum {
    NVMEOF_CQE_SC_CMD_INCOMPAT_FORMAT = 0x80,
    NVMEOF_CQE_SC_CMD_CONT_BUSY = 0x81,
    NVMEOF_CQE_SC_CMD_CNCT_INV_PARAMS = 0x82,
    NVMEOF_CQE_SC_CMD_CNCT_RESTART_DISC = 0x83,
    NVMEOF_CQE_SC_CMD_CNCT_INV_HOST = 0x84,
    NVMEOF_CQE_SC_CMD_INV_QUEUE_TYPE = 0x85,
    NVMEOF_CQE_SC_CMD_DISC_RESTART = 0x90,
    NVMEOF_CQE_SC_CMD_AUTH_REQ = 0x91,
} nvmeof_cqe_sc_cmd_t;

typedef enum {
    NVME_CQE_SC_MEDIA_WRITE_FAULT = 0x80,
    NVME_CQE_SC_MEDIA_READ_FAULT = 0x81,
    NVME_CQE_SC_MEDIA_ETE_GUARD_CHECK_ERR = 0x82,
    NVME_CQE_SC_MEDIA_ETE_APPTAG_CHECK_ERR = 0x83,
    NVME_CQE_SC_MEDIA_ETE_REFTAG_CHECK_ERR = 0x84,
    NVME_CQE_SC_MEDIA_COMPARE_FAILURE = 0x85,
    NVME_CQE_SC_MEDIA_ACCESS_DENIED = 0x86,
    NVME_CQE_SC_MEDIA_DEALLOCATED_LBA = 0x87,
    NVME_CQE_SC_MEDIA_ETE_STORAGE_TAG_CHECK_ERR = 0x88,
} nvme_cqe_sc_media_t;

typedef enum {
    NVME_CQE_SC_PATH_INTERNAL_PATH_ERROR = 0x00,
    NVME_CQE_SC_PATH_ANA_PERSISTENT_LOSS = 0x01,
    NVME_CQE_SC_PATH_ANA_INACCESSIBLE = 0x02,
    NVME_CQE_SC_PATH_ANA_TRANSIENT = 0x03,
    NVME_CQE_SC_PATH_CNTRL_PATH_ERROR = 0x60,
    NVME_CQE_SC_PATH_HOST_PATH_ERROR = 0x70,
    NVME_CQE_SC_PATH_CMD_ABORT = 0x71,
} nvme_cqe_sc_path_t;

static const value_string nvme_cqe_sct_tbl[] = {
    { NVME_CQE_SCT_GENERIC, "Generic Command Status" },
    { NVME_CQE_SCT_COMMAND, "Command Specific Status" },
    { NVME_CQE_SCT_MEDIA, "Media and Data Integrity Errors" },
    { NVME_CQE_SCT_PATH, "Path Related Status" },
    { NVME_CQE_SCT_VENDOR, "Vendor Specific" },
    { 0, NULL },
};

static const value_string nvme_cqe_sc_gen_tbl[] = {
    { NVME_CQE_SC_GEN_CMD_OK, "Successful Completion" },
    { NVME_CQE_SC_CMD_INVALID_OPCODE, "Invalid opcode field" },
    { NVME_CQE_SC_GEN_CMD_INVALID_FIELD, "Invalid Field in Command" },
    { NVME_CQE_SC_GEN_CMD_CID_CONFLICT, "Command ID Conflict" },
    { NVME_CQE_SC_GEN_DATA_TRANSFER_ERR, "Data Transfer Error" },
    { NVME_CQE_SC_GEN_ABORT_DUE_TO_POWER_LOSS, "Commands Aborted due to Power Loss Notification" },
    { NVME_CQE_SC_GEN_INTERNAL_ERROR, "Internal Error" },
    { NVME_CQE_SC_GEN_ABORT_REQUESTED, "Command Abort Requested" },
    { NVME_CQE_SC_GEN_ABORT_DUE_TO_SQ_DELETE, "Command Aborted due to SQ Deletion" },
    { NVME_CQE_SC_GEN_ABORT_DUE_TO_FAILED_FUSE, "Command Aborted due to Failed Fused Command" },
    { NVME_CQE_SC_GEN_ABORT_DUE_TO_MISSED_FUSE, "Command Aborted due to Missing Fused Command" },
    { NVME_CQE_SC_GEN_INVALID_NAMESPACE_OR_FMT, "Invalid Namespace or Format" },
    { NVME_CQE_SC_GEN_COMMAND_SEQUENCE_ERR, "Command Sequence Error" },
    { NVME_CQE_SC_GEN_INVALID_SGL_SD, "Invalid SGL Segment Descriptor" },
    { NVME_CQE_SC_GEN_INVALID_SGL_SD_NUM, "Invalid Number of SGL Descriptors" },
    { NVME_CQE_SC_GEN_INVALID_SGL_LEN, "Data SGL Length Invalid" },
    { NVME_CQE_SC_GEN_INVALID_MDATA_SGL_LEN, "Metadata SGL Length Invalid" },
    { NVME_CQE_SC_GEN_INVALID_SGL_SD_TYPE, "SGL Descriptor Type Invalid" },
    { NVME_CQE_SC_GEN_INVALID_USE_OF_MC_BUF, "Invalid Use of Controller Memory Buffer" },
    { NVME_CQE_SC_GEN_INVALID_PRP_OFFSET, "PRP Offset Invalid" },
    { NVME_CQE_SC_GEN_ATOMIC_WRITE_UNIT_EXCEED, "Atomic Write Unit Exceeded" },
    { NVME_CQE_SC_GEN_OPERATION_DENIED, "Operation Denied" },
    { NVME_CQE_SC_GEN_INVALID_SGL_OFFSET, "SGL Offset Invalid" },
    { NVME_CQE_SC_GEN_RESERVED_17H, "Reserved" },
    { NVME_CQE_SC_GEN_HOST_ID_INVALID_FMT, "Host Identifier Inconsistent Format" },
    { NVME_CQE_SC_GEN_KEEP_ALLIVE_EXPIRED, "Keep Alive Timer Expired" },
    { NVME_CQE_SC_GEN_KEEP_ALIVE_INVALID, "Keep Alive Timeout Invalid" },
    { NVME_CQE_SC_GEN_ABORT_DUE_TO_PREEMPT_ABRT, "Command Aborted due to Preempt and Abort" },
    { NVME_CQE_SC_GEN_SANITIZE_FAILED, "Sanitize Failed" },
    { NVME_CQE_SC_GEN_SANITZE_IN_PROGRESS,"Sanitize In Progress"  },
    { NVME_CQE_SC_GEN_SGL_BLOCK_GRAN_INVALID, "SGL Data Block Granularity Invalid" },
    { NVME_CQE_SC_GEN_CMD_NOT_SUPP_IN_CMB, "Command Not Supported for Queue in CMB" },
    { NVME_CQE_SC_GEN_NAMESPACE_IS_WP, "Namespace is Write Protected" },
    { NVME_CQE_SC_GEN_COMMAND_INTERRUPTED,"Command Interrupted" },
    { NVME_CQE_SC_GEN_TRANSIENT_TRASPORT_ERROR, "Transient Transport Error"},
    { NVME_CQE_SC_GEN_CMD_PROHIBITED_LOCKDOWN, "Command Prohibited by Command and Feature Lockdown" },
    { NVME_CQE_SC_GEN_ADMIN_CMD_MEDIA_NOT_READY, "Admin Command Media Not Ready" },
    { NVME_CQE_SC_GEN_INVALID_KEY_TAG, "Invalid Key Tag" },
    { NVME_CQE_SC_GEN_HOST_DISP_NS_SUPP_NOT_ENABLED, "Host Dispersed Namespace Support Not Enabled" },
    { NVME_CQE_SC_GEN_HOST_ID_NOT_INITIALIZED, "Host Identifier Not Initialized" },
    { NVME_CQE_SC_GEN_INCORRECT_KEY, "Incorrect Key" },
    { NVME_CQE_SC_GEN_FDP_DISABLED, "FDP Disabled" },
    { NVME_CQE_SC_GEN_INVALID_PLACEMENT_HANDLE_LIST, "Invalid Placement Handle List" },
    { NVME_CQE_SC_GEN_SANITIZE_NAMESPACE_FAILED, "Sanitize Namespace Failed" },
    { NVME_CQE_SC_GEN_SANITIZE_NAMESPACE_IN_PROGRESS, "Sanitize Namespace In Progress" },
    { NVME_CQE_SC_GEN_LBA_OUT_OF_RANGE, "LBA Out of Range" },
    { NVME_CQE_SC_GEN_CAPACITY_EXCEED, "Capacity Exceeded" },
    { NVME_CQE_SC_GEN_NAMESPACE_NOT_ERADY, "Namespace Not Ready" },
    { NVME_CQE_SC_GEN_RESERVATION_CONFLICT, "Reservation Conflict" },
    { NVME_CQE_SC_GEN_FMT_IN_PROGRESS, "Format In Progress"},
    { NVME_CQE_SC_GEN_INVALID_VALUE_SIZE, "Invalid Value Size" },
    { NVME_CQE_SC_GEN_INVALID_KEY_SIZE, "Invalid Key Size" },
    { NVME_CQE_SC_GEN_KV_KEY_DOES_NOT_EXIST, "KV Key Does Not Exist" },
    { NVME_CQE_SC_GEN_UNRECOVERED_ERROR, "Unrecovered Error" },
    { NVME_CQE_SC_GEN_KEY_EXISTS, "Key Exists" },
    { 0, NULL },
};

static const value_string nvme_cqe_sc_cmd_tbl[] = {
    { NVME_CQE_SC_CMD_INVALID_CQ, "Completion Queue Invalid" },
    { NVME_CQE_SC_CMD_INVALID_QID, "Invalid Queue Identifier" },
    { NVME_CQE_SC_CMD_INVALID_QUEUE_SIZE, "Invalid Queue Size" },
    { NVME_CQE_SC_CMD_ABORT_LIMIT_EXCEED, "Abort Command Limit Exceeded" },
    { NVME_CQE_SC_CMD_RESERVED_4H, "Reserved" },
    { NVME_CQE_SC_CMD_ASYNC_REQ_LIMIT_EXCEED, "Asynchronous Event Request Limit Exceeded" },
    { NVME_CQE_SC_CMD_INVALID_FW_SLOT, "Invalid Firmware Slot" },
    { NVME_CQE_SC_CMD_INVALID_FW_IMAGE, "Invalid Firmware Image" },
    { NVME_CQE_SC_CMD_INVALID_IRQ_VECTOR, "Invalid Interrupt Vector" },
    { NVME_CQE_SC_CMD_INVALID_LOG_PAGE, "Invalid Log Page" },
    { NVME_CQE_SC_CMD_INVALID_FMT, "Invalid Format" },
    { NVME_CQE_SC_CMD_FW_ACTIVATION_NEEDS_RESET, "Firmware Activation Requires Conventional Reset" },
    { NVME_CQE_SC_CMD_INVALID_QUEUE_DELETE, "Invalid Queue Deletion" },
    { NVME_CQE_SC_CMD_FEATURE_ID_NOT_SAVEABLE, "Feature Identifier Not Saveable" },
    { NVME_CQE_SC_CMD_FEATURE_NOT_CHANGEABLE, "Feature Not Changeable" },
    { NVME_CQE_SC_CMD_FEATURE_NOT_NAMESPACE, "Feature Not Namespace Specific" },
    { NVME_CQE_SC_CMD_FEATURE_ACTIVATION_NEEDS_NVM_RESET, "Firmware Activation Requires NVM Subsystem Reset" },
    { NVME_CQE_SC_CMD_FEATURE_ACTIVATION_NEEDS_CNTRL_RESET, "Firmware Activation Requires Controller Level Reset" },
    { NVME_CQE_SC_CMD_FW_ACTIVATION_NEED_MAX_TIME, "Firmware Activation Requires Maximum Time Violation" },
    { NVME_CQE_SC_CMD_FW_ACTIVATION_PROHIBITED, "Firmware Activation Prohibited" },
    { NVME_CQE_SC_CMD_OVERLAPPING_RANGE, "Overlapping Range" },
    { NVME_CQE_SC_CMD_NAMESPACE_INSUF_CAPACITY, "Namespace Insufficient Capacity" },
    { NVME_CQE_SC_CMD_NAMESPACE_ID_NOT_AVAILABLE, "Namespace Identifier Unavailable" },
    { NVME_CQE_SC_CMD_RESERVED_17H, "Reserved" },
    { NVME_CQE_SC_CMD_NAMESPACE_ALREADY_ATATCHED, "Namespace Already Attached" },
    { NVME_CQE_SC_CMD_NAMESPACE_IS_PRIVATE, "Namespace Is Private" },
    { NVME_CQE_SC_CMD_NAMESPACE_NOT_ATTACHED, "Namespace Not Attached" },
    { NVME_CQE_SC_CMD_THIN_PROVISION_NOT_SUPP, "Thin Provisioning Not Supported" },
    { NVME_CQE_SC_CMD_INVALID_CNTRL_LIST, "Controller List Invalid" },
    { NVME_CQE_SC_CMD_SELF_TEST_IN_PROGRESS, "Device Self-test In Progress" },
    { NVME_CQE_SC_CMD_BOOT_PART_WRITE_PROHIBIT, "Boot Partition Write Prohibited" },
    { NVME_CQE_SC_CMD_INVALID_CNTRL_ID, "Invalid Controller Identifier" },
    { NVME_CQE_SC_CMD_INVALID_SECOND_CNTRL_STATE, "Invalid Secondary Controller State" },
    { NVME_CQE_SC_CMD_IBVALID_CNRL_RES_NUM, "Invalid Number of Controller Resources" },
    { NVME_CQE_SC_CMD_INVALID_RESOURSE_ID, "Invalid Resource Identifier" },
    { NVME_CQE_SC_CMD_SANITIZE_PROHIBIT_WITH_PMR, "Sanitize Prohibited While Persistent Memory Region  is Enabled" },
    { NVME_CQE_SC_CMD_INVALID_ANA_GROUP_ID, "ANA Group Identifier Invalid" },
    { NVME_CQE_SC_CMD_ANA_ATTACH_FAILED, "ANA Attach Failed" },
    { NVME_CQE_SC_CMD_INSUFFICIENT_CAPACITY, "Insufficient Capacity" },
    { NVME_CQE_SC_CMD_NS_ATTACHMENT_LIMIT_EXCEEDED, "Namespace Attachment Limit Exceeded" },
    { NVME_CQE_SC_CMD_PROHIBITION_NOT_SUPPORTED, "Prohibition of Command Execution Not Supported" },
    { NVME_CQE_SC_CMD_IO_CMD_SET_NOT_SUPPORTED, "I/O Command Set Not Supported" },
    { NVME_CQE_SC_CMD_IO_CMD_SET_NOT_ENABLED, "I/O Command Set Not Enabled" },
    { NVME_CQE_SC_CMD_IO_CMD_SET_COMBINATION_REJECTED, "I/O Command Set Combination Rejected" },
    { NVME_CQE_SC_CMD_INVALID_IO_CMD_SET, "Invalid I/O Command Set" },
    { NVME_CQE_SC_CMD_IDENTIFIER_UNAVAILABLE, "Identifier Unavailable" },
    { NVME_CQE_SC_CMD_NAMESPACE_IS_DISPERSED, "Namespace Is Dispersed" },
    { NVME_CQE_SC_CMD_INVALID_DISCOVERY_INFO, "Invalid Discovery Information" },
    { NVME_CQE_SC_CMD_ZONING_DS_LOCKED, "Zoning Data Structure Locked" },
    { NVME_CQE_SC_CMD_ZONING_DS_NOT_FOUND, "Zoning Data Structure Not Found" },
    { NVME_CQE_SC_CMD_INSUFFICIENT_DISCOVERY_RES, "Insufficient Discovery Resources" },
    { NVME_CQE_SC_CMD_REQUESTED_FUNCTION_DISABLED, "Requested Function Disabled" },
    { NVME_CQE_SC_CMD_ZONEGROUP_ORIGINATOR_INVALID, "ZoneGroup Originator Invalid" },
    { NVME_CQE_SC_CMD_INVALID_HOST, "Invalid Host" },
    { NVME_CQE_SC_CMD_INVALID_NVM_SUBSYSTEM, "Invalid NVM Subsystem" },
    { NVME_CQE_SC_CMD_INVALID_CTRL_DATA_QUEUE, "Invalid Controller Data Queue" },
    { NVME_CQE_SC_CMD_NOT_ENOUGH_RESOURCES, "Not Enough Resources" },
    { NVME_CQE_SC_CMD_CONTROLLER_SUSPENDED, "Controller Suspended" },
    { NVME_CQE_SC_CMD_CONTROLLER_NOT_SUSPENDED, "Controller Not Suspended" },
    { NVME_CQE_SC_CMD_CTRL_DATA_QUEUE_FULL, "Controller Data Queue Full" },
    { NVME_CQE_SC_CMD_EXCEEDS_MAX_NS_SANITIZE_OPS, "Request Exceeds Maximum Namespace Sanitize Operations In Progress" },
    { NVME_CQE_SC_CMD_MFG_DEFAULT_PERSONALITY_REQUIRED, "Manufacturing Default Personality Required" },
    { NVME_CQE_SC_CMD_INVALID_POWER_LIMIT, "Invalid Power Limit" },
    { NVME_CQE_SC_CMD_CROSS_CTRL_RESET_IN_PROGRESS, "Cross-Controller Reset in Progress" },
    { NVME_CQE_SC_CMD_CROSS_CTRL_RESET_LOG_PAGE_FULL, "Cross-Controller Reset Log Page Full" },
    { NVME_CQE_SC_CMD_CROSS_CTRL_RESET_LIMIT_EXCEEDED, "Cross-Controller Reset Limit Exceeded" },
    { NVME_CQE_SC_CMD_CONFLICTING_ATTRS, "Conflicting Attributes" },
    { NVME_CQE_SC_CMD_INVALID_PROTECTION_INF, "Invalid Protection Information" },
    { NVME_CQE_SC_CMD_WRITE_TO_RO_REGION, "Attempted Write to Read Only Range" },
    { NVME_CQE_SC_CMD_SIZE_LIMIT_EXCEEDED, "Command Size Limit Exceeded" },
    { NVME_CQE_SC_CMD_INVALID_COMMAND_ID, "Invalid Command ID" },
    { NVME_CQE_SC_CMD_INCOMPAT_NAMESPACE_OR_FMT, "Incompatible Namespace or Format" },
    { NVME_CQE_SC_CMD_FAST_COPY_NOT_POSSIBLE, "Fast Copy Not Possible" },
    { NVME_CQE_SC_CMD_OVERLAPPING_IO_RANGE, "Overlapping I/O Range" },
    { NVME_CQE_SC_CMD_NAMESPACE_NOT_REACHABLE, "Namespace Not Reachable" },
    { NVME_CQE_SC_CMD_INSUFFICIENT_RESOURCES, "Insufficient Resources" },
    { NVME_CQE_SC_CMD_INSUFFICIENT_PROGRAM_RESOURCES, "Insufficient Program Resources" },
    { NVME_CQE_SC_CMD_INVALID_MEMORY_NAMESPACE, "Invalid Memory Namespace" },
    { NVME_CQE_SC_CMD_INVALID_MEMORY_RANGE_SET, "Invalid Memory Range Set" },
    { NVME_CQE_SC_CMD_INVALID_MEMORY_RANGE_SET_ID, "Invalid Memory Range Set Identifier" },
    { NVME_CQE_SC_CMD_INVALID_PROGRAM_DATA, "Invalid Program Data" },
    { NVME_CQE_SC_CMD_INVALID_PROGRAM_INDEX, "Invalid Program Index" },
    { NVME_CQE_SC_CMD_INVALID_PROGRAM_TYPE, "Invalid Program Type" },
    { NVME_CQE_SC_CMD_MAX_MEMORY_RANGES_EXCEEDED, "Maximum Memory Ranges Exceeded" },
    { NVME_CQE_SC_CMD_MAX_MEMORY_RANGE_SETS_EXCEEDED, "Maximum Memory Range Sets Exceeded" },
    { NVME_CQE_SC_CMD_MAX_PROGRAMS_ACTIVATED, "Maximum Programs Activated" },
    { NVME_CQE_SC_CMD_MAX_PROGRAM_BYTES_EXCEEDED, "Maximum Program Bytes Exceeded" },
    { NVME_CQE_SC_CMD_MEMORY_RANGE_SET_IN_USE, "Memory Range Set In Use" },
    { NVME_CQE_SC_CMD_NO_PROGRAM, "No Program" },
    { NVME_CQE_SC_CMD_OVERLAPPING_MEMORY_RANGES, "Overlapping Memory Ranges" },
    { NVME_CQE_SC_CMD_PROGRAM_NOT_ACTIVATED, "Program Not Activated" },
    { NVME_CQE_SC_CMD_PROGRAM_IN_USE, "Program In Use" },
    { NVME_CQE_SC_CMD_PROGRAM_INDEX_NOT_DOWNLOADABLE, "Program Index Not Downloadable" },
    { NVME_CQE_SC_CMD_PROGRAM_TOO_BIG, "Program Too Big" },
    { NVME_CQE_SC_CMD_SUCCESSFUL_MEDIA_VERIFICATION_READ, "Successful Media Verification Read" },
    { NVME_CQE_SC_CMD_ZONE_BOUNDARY_ERROR, "Zoned Boundary Error" },
    { NVME_CQE_SC_CMD_ZONE_IS_FULL, "Zone Is Full" },
    { NVME_CQE_SC_CMD_ZONE_IS_READ_ONLY, "Zone Is Read Only" },
    { NVME_CQE_SC_CMD_ZONE_IS_OFFLINE, "Zone Is Offline" },
    { NVME_CQE_SC_CMD_ZONE_INVALID_WRITE, "Zone Invalid Write" },
    { NVME_CQE_SC_CMD_TOO_MANY_ACTIVE_ZONES, "Too Many Active Zones" },
    { NVME_CQE_SC_CMD_TOO_MANY_OPEN_ZONES, "Too Many Open Zones" },
    { NVME_CQE_SC_CMD_INVALID_ZONE_STATE_TRANSITION, "Invalid Zone State Transition" },
    { 0, NULL },
};

static const value_string nvmeof_cqe_sc_cmd_tbl[] = {
    { NVMEOF_CQE_SC_CMD_INCOMPAT_FORMAT, "Incompatible Format" },
    { NVMEOF_CQE_SC_CMD_CONT_BUSY, "Controller Busy" },
    { NVMEOF_CQE_SC_CMD_CNCT_INV_PARAMS, "Connect Invalid Parameters" },
    { NVMEOF_CQE_SC_CMD_CNCT_RESTART_DISC, "Connect Restart Discovery" },
    { NVMEOF_CQE_SC_CMD_CNCT_INV_HOST, "Connect Invalid Host" },
    { NVMEOF_CQE_SC_CMD_INV_QUEUE_TYPE, "Invalid Queue Type" },
    { NVMEOF_CQE_SC_CMD_DISC_RESTART, "Discover Restart" },
    { NVMEOF_CQE_SC_CMD_AUTH_REQ, "Authentication Required" },
    { 0, NULL },
};

static const value_string nvme_cqe_sc_media_tbl[] = {
    { NVME_CQE_SC_MEDIA_WRITE_FAULT, "Write Fault" },
    { NVME_CQE_SC_MEDIA_READ_FAULT, "Unrecovered Read Error" },
    { NVME_CQE_SC_MEDIA_ETE_GUARD_CHECK_ERR, "End-to-end Guard Check Error" },
    { NVME_CQE_SC_MEDIA_ETE_APPTAG_CHECK_ERR, "End-to-end Application Tag Check Error" },
    { NVME_CQE_SC_MEDIA_ETE_REFTAG_CHECK_ERR, "End-to-end Reference Tag Check Error" },
    { NVME_CQE_SC_MEDIA_COMPARE_FAILURE, "Compare Failure" },
    { NVME_CQE_SC_MEDIA_ACCESS_DENIED, "Access Denied" },
    { NVME_CQE_SC_MEDIA_DEALLOCATED_LBA, "Deallocated or Unwritten Logical Block" },
    { NVME_CQE_SC_MEDIA_ETE_STORAGE_TAG_CHECK_ERR, "End-to-End Storage Tag Check Error" },
    { 0, NULL },
};

static const value_string nvme_cqe_sc_path_tbl[] = {
    { NVME_CQE_SC_PATH_INTERNAL_PATH_ERROR, "Internal Path Error" },
    { NVME_CQE_SC_PATH_ANA_PERSISTENT_LOSS, "Asymmetric Access Persistent Loss" },
    { NVME_CQE_SC_PATH_ANA_INACCESSIBLE, "Asymmetric Access Inaccessible" },
    { NVME_CQE_SC_PATH_ANA_TRANSIENT, "Asymmetric Access Transition" },
    { NVME_CQE_SC_PATH_CNTRL_PATH_ERROR, "Controller Pathing Error" },
    { NVME_CQE_SC_PATH_HOST_PATH_ERROR, "Host Pathing Error" },
    { NVME_CQE_SC_PATH_CMD_ABORT, "Command Aborted By Host" },
    { 0, NULL },
};

static const value_string aq_opc_tbl[] = {
    { NVME_AQ_OPC_DELETE_SQ,     "Delete SQ"},
    { NVME_AQ_OPC_CREATE_SQ,     "Create SQ"},
    { NVME_AQ_OPC_GET_LOG_PAGE,  "Get Log Page"},
    { NVME_AQ_OPC_DELETE_CQ,     "Delete CQ"},
    { NVME_AQ_OPC_CREATE_CQ,     "Create CQ"},
    { NVME_AQ_OPC_IDENTIFY,      "Identify"},
    { NVME_AQ_OPC_ABORT,         "Abort"},
    { NVME_AQ_OPC_SET_FEATURES,  "Set Features"},
    { NVME_AQ_OPC_GET_FEATURES,  "Get Features"},
    { NVME_AQ_OPC_ASYNC_EVE_REQ, "Async Event Request"},
    { NVME_AQ_OPC_NS_MGMT,       "Namespace Management"},
    { NVME_AQ_OPC_FW_COMMIT,     "Firmware Commit"},
    { NVME_AQ_OPC_FW_IMG_DOWNLOAD, "Firmware Image Download"},
    { NVME_AQ_OPC_SELF_TEST,     "Device Self-test"},
    { NVME_AQ_OPC_NS_ATTACH,     "Namespace attach"},
    { NVME_AQ_OPC_KEEP_ALIVE,    "Keep Alive"},
    { NVME_AQ_OPC_DIRECTIVE_SEND, "Directive Send"},
    { NVME_AQ_OPC_DIRECTIVE_RECV, "Directive Receive"},
    { NVME_AQ_OPC_VIRT_MGMT,     "Virtualization Management"},
    { NVME_AQ_OPC_MI_SEND,       "NVMe-MI Send"},
    { NVME_AQ_OPC_MI_RECV,       "NVMe-MI Receive"},
    { NVME_AQ_OPC_CAP_MGMT,      "Capacity Management"},
    { NVME_AQ_OPC_DISC_INFO_MGMT, "Discovery Information Management"},
    { NVME_AQ_OPC_FABRIC_ZONING_RECV, "Fabric Zoning Receive"},
    { NVME_AQ_OPC_LOCKDOWN,      "Lockdown"},
    { NVME_AQ_OPC_FABRIC_ZONING_LOOKUP, "Fabric Zoning Lookup"},
    { NVME_AQ_OPC_CLEAR_EXP_NVM_CFG, "Clear Exported NVM Resource Configuration"},
    { NVME_AQ_OPC_FABRIC_ZONING_SEND, "Fabric Zoning Send"},
    { NVME_AQ_OPC_CREATE_EXP_NVM_SUBSYS, "Create Exported NVM Subsystem"},
    { NVME_AQ_OPC_MANAGE_EXP_NVM_SUBSYS, "Manage Exported NVM Subsystem"},
    { NVME_AQ_OPC_MANAGE_EXP_NS, "Manage Exported Namespace"},
    { NVME_AQ_OPC_MANAGE_EXP_PORT, "Manage Exported Port"},
    { NVME_AQ_OPC_CROSS_CTRL_RESET, "Cross-Controller Reset"},
    { NVME_AQ_OPC_SEND_DISC_LOG_PAGE, "Send Discovery Log Page"},
    { NVME_AQ_OPC_TRACK_SEND,    "Track Send"},
    { NVME_AQ_OPC_TRACK_RECV,    "Track Receive"},
    { NVME_AQ_OPC_MIGRATION_SEND, "Migration Send"},
    { NVME_AQ_OPC_MIGRATION_RECV, "Migration Receive"},
    { NVME_AQ_OPC_CTRL_DATA_QUEUE, "Controller Data Queue"},
    { NVME_AQ_OPC_DBBUF_CONFIG,  "Doorbell Buffer Config"},
    { NVME_AQ_OPC_FORMAT_NVM,    "Format NVM"},
    { NVME_AQ_OPC_SECURITY_SEND, "Security Send"},
    { NVME_AQ_OPC_SECURITY_RECV, "Security Receive"},
    { NVME_AQ_OPC_SANITIZE,      "Sanitize"},
    { NVME_AQ_OPC_LOAD_PROGRAM,  "Load Program"},
    { NVME_AQ_OPC_GET_LBA_STATUS, "Get LBA Status"},
    { NVME_AQ_OPC_PROG_ACTIVATION_MGMT, "Program Activation Management"},
    { NVME_AQ_OPC_MEM_RANGE_SET_MGMT, "Memory Range Set Management"},
    { NVME_AQ_OPC_SANITIZE_NS,   "Sanitize Namespace"},
    { NVME_FABRIC_OPC,           "Fabrics Commands"},
    { 0, NULL}
};

static const value_string ioq_opc_tbl[] = {
    { NVME_IOQ_OPC_FLUSH,         "Flush"},
    { NVME_IOQ_OPC_WRITE,         "Write"},
    { NVME_IOQ_OPC_READ,          "Read"},
    { NVME_IOQ_OPC_WRITE_UNCORRECTABLE, "Write Uncorrectable"},
    { NVME_IOQ_OPC_COMPARE,       "Compare"},
    { NVME_IOQ_OPC_WRITE_ZEROS,   "Write Zeroes"},
    { NVME_IOQ_OPC_DATASET_MGMT,  "Dataset Management"},
    { NVME_IOQ_OPC_VERIFY,        "Verify"},
    { NVME_IOQ_OPC_RESV_REG,      "Reservation Register"},
    { NVME_IOQ_OPC_RESV_REPORT,   "Reservation Report"},
    { NVME_IOQ_OPC_RESV_ACQUIRE,  "Reservation Acquire"},
    { NVME_IOQ_OPC_IO_MGMT_RECV,  "I/O Management Receive"},
    { NVME_IOQ_OPC_RESV_RELEASE,  "Reservation Release"},
    { NVME_IOQ_OPC_CANCEL,        "Cancel"},
    { NVME_IOQ_OPC_COPY,          "Copy"},
    { NVME_IOQ_OPC_IO_MGMT_SEND,  "I/O Management Send"},
    { 0, NULL}
};

/* aq_opc_tbl/ioq_opc_tbl only cover the assigned opcode space; C0h-FFh
 * (Admin, NVM CS 1.2 Fig 21) and 80h-FFh (I/O, NVM CS 1.2 Fig 21) are
 * Vendor Specific, not Reserved -- special-case them the same way
 * get_logpage_name() does for the logpage table. */
static const char *get_aq_opcode_name(uint8_t opcode)
{
    if (opcode >= 0xC0)
        return "Vendor Specific";
    return val_to_str_const(opcode, aq_opc_tbl, "Reserved");
}

static const char *get_ioq_opcode_name(uint8_t opcode)
{
    if (opcode >= 0x80)
        return "Vendor Specific";
    return val_to_str_const(opcode, ioq_opc_tbl, "Reserved");
}

#define NVME_CMD_SGL_DATA_DESC          0x0
#define NVME_CMD_SGL_BIT_BUCKET_DESC    0x1
#define NVME_CMD_SGL_SEGMENT_DESC       0x2
#define NVME_CMD_SGL_LAST_SEGMENT_DESC  0x3
#define NVME_CMD_SGL_KEYED_DATA_DESC    0x4
#define NVME_CMD_SGL_TRANSPORT_DESC     0x5
#define NVME_CMD_SGL_VENDOR_DESC        0xf

static const value_string sgl_type_tbl[] = {
    { NVME_CMD_SGL_DATA_DESC,         "Data Block"},
    { NVME_CMD_SGL_BIT_BUCKET_DESC,   "Bit Bucket"},
    { NVME_CMD_SGL_SEGMENT_DESC,      "Segment"},
    { NVME_CMD_SGL_LAST_SEGMENT_DESC, "Last Segment"},
    { NVME_CMD_SGL_KEYED_DATA_DESC,   "Keyed Data Block"},
    { NVME_CMD_SGL_TRANSPORT_DESC,    "Transport SGL Data Block descriptor"},
    { NVME_CMD_SGL_VENDOR_DESC,       "Vendor Specific"},
    { 0, NULL}
};

#define NVME_CMD_SGL_SUB_DESC_ADDR      0x0
#define NVME_CMD_SGL_SUB_DESC_OFFSET    0x1
#define NVME_CMD_SGL_SUB_DESC_TRANSPORT 0xf

static const value_string sgl_sub_type_tbl[] = {
    { NVME_CMD_SGL_SUB_DESC_ADDR,      "Address"},
    { NVME_CMD_SGL_SUB_DESC_OFFSET,    "Offset"},
    { 0xa,                             "NVMe Transport Specific"},
    { 0xb,                             "NVMe Transport Specific"},
    { 0xc,                             "NVMe Transport Specific"},
    { 0xd,                             "NVMe Transport Specific"},
    { 0xe,                             "NVMe Transport Specific"},
    { NVME_CMD_SGL_SUB_DESC_TRANSPORT, "Transport specific"},
    { 0, NULL}
};


static const value_string cns_table[] = {
    { 0, "Namespace"},
    { 1, "Controller"},
    { 2, "Active Namespace List"},
    { 3, "Namespace Identification Descriptor"},
    {4, "NVM Set List"},
    {0x5, "I/O Command Set Specific Namespace"},
    {0x6, "I/O Command Set Specific Controller"},
    {0x7, "I/O Command Set Specific Active Namespace List"},
    {0x8, "I/O Command Set Independent Namespace"},
    {0x9, "NVM Command Set Namespace (Format Index)"},
    {0xa, "I/O Command Set Specific Namespace (Format Index)"},
    {0x10, "Allocated Namespace ID List"},
    {0x11, "Namespace Data Structure"},
    {0x12, "Controller List Attached to NSID"},
    {0x13, "Existing Controllers List"},
    {0x14, "Primary Controller Capabilities"},
    {0x15, "Secondary Controller List"},
    {0x16, "Namespace Granularity List"},
    {0x17, "UUID List"},
    {0x18, "Domain List"},
    {0x19, "Endurance Group List"},
    {0x1a, "I/O Command Set Specific Allocated Namespace ID List"},
    {0x1b, "I/O Command Set Specific Namespace (Allocated NSID)"},
    {0x1c, "I/O Command Set Data Structure"},
    {0x1d, "Get Underlying Namespace List"},
    {0x1e, "Get Ports List"},
    {0x1f, "I/O Command Set Independent Namespace (Allocated NSID)"},
    {0x20, "Supported Controller State Formats"},
    {0, NULL}
};

/* Namespace Identifier Type (NIDT), NVMe Base 2.3 "Identify – Namespace
 * Identification Descriptor". */
static const value_string nidt_tbl[] = {
    { 0x1, "IEEE Extended Unique Identifier (EUI64)" },
    { 0x2, "Namespace Globally Unique Identifier (NGUID)" },
    { 0x3, "Namespace UUID" },
    { 0x4, "Command Set Identifier (CSI)" },
    { 0, NULL }
};

/* UUID List Entry Identifier Association (IDASSOC), NVMe Base 2.3 "UUID
 * List Entry". */
static const value_string uuid_idassoc_tbl[] = {
    { 0x0, "No association reported" },
    { 0x1, "Associated with PCI Vendor ID" },
    { 0x2, "Associated with PCI Subsystem Vendor ID" },
    { 0x3, "Reserved" },
    { 0, NULL }
};

static const value_string dsm_acc_freq_tbl[] = {
    { 0, "No frequency"},
    { 1, "Typical"},
    { 2, "Infrequent Read/Write"},
    { 3, "Infrequent Writes, Frequent Reads"},
    { 4, "Frequent Writes, Infrequent Reads"},
    { 5, "Frequent Read/Write"},
    { 6, "One time read"},
    { 7, "Speculative read"},
    { 8, "Likely tobe overwritten"},
    { 0, NULL}
};

static const value_string dsm_acc_lat_tbl[] = {
    { 0, "None"},
    { 1, "Idle (Longer)"},
    { 2, "Normal (Typical)"},
    { 3, "Low (Smallest)"},
    { 0, NULL}
};


void
nvme_publish_qid(proto_tree *tree, int field_index, uint16_t qid)
{
    proto_item *cmd_ref_item;

    cmd_ref_item = proto_tree_add_uint_format_value(tree, field_index, NULL,
                       0, 0, qid,
                     qid ? "%d (IOQ)" : "%d (AQ)",
                                     qid);

    proto_item_set_generated(cmd_ref_item);
}

static void nvme_build_pending_cmd_key(wmem_tree_key_t *cmd_key, uint32_t *key)
{
    cmd_key[0].length = 1;
    cmd_key[0].key = key;
    cmd_key[1].length = 0;
    cmd_key[1].key = NULL;
}

static void
nvme_build_done_frame_key(wmem_tree_key_t *cmd_key, uint32_t *key, uint32_t *frame)
{
    unsigned idx = 0;
    if (key) {
        cmd_key[0].length = 1;
        cmd_key[0].key = key;
        idx = 1;
    }
    cmd_key[idx].length = 1;
    cmd_key[idx].key = frame;
    idx++;

    cmd_key[idx].length = 0;
    cmd_key[idx].key = NULL;
}

void
nvme_add_cmd_to_pending_list(packet_info *pinfo, struct nvme_q_ctx *q_ctx,
                             struct nvme_cmd_ctx *cmd_ctx,
                             void *ctx, uint16_t cmd_id)
{
    wmem_tree_key_t cmd_key[3];
    uint32_t key = cmd_id;

    cmd_ctx->cmd_pkt_num = pinfo->num;
    cmd_ctx->cqe_pkt_num = 0;
    cmd_ctx->cmd_start_time = pinfo->abs_ts;
    nstime_set_zero(&cmd_ctx->cmd_end_time);

    /* this is a new cmd, create a new command context and map it to the
       unmatched table
     */
    nvme_build_pending_cmd_key(cmd_key, &key);
    wmem_tree_insert32_array(q_ctx->pending_cmds, cmd_key, (void *)ctx);
}

void* nvme_lookup_cmd_in_pending_list(struct nvme_q_ctx *q_ctx, uint16_t cmd_id)
{
    wmem_tree_key_t cmd_key[3];
    uint32_t key = cmd_id;

    nvme_build_pending_cmd_key(cmd_key, &key);
    return wmem_tree_lookup32_array(q_ctx->pending_cmds, cmd_key);
}


static void nvme_build_pending_transfer_key(wmem_tree_key_t *key, struct keyed_data_req *req)
{
    key[0].length = 2;
    key[0].key = (uint32_t *)&req->addr;
    key[1].length = 1;
    key[1].key = &req->key;
    key[2].length = 1;
    key[2].key = &req->size;
    key[3].length = 0;
    key[3].key = NULL;
}

void nvme_add_data_request(struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx,
                                        struct keyed_data_req *req)
{
    wmem_tree_key_t tr_key[4];

    memset(cmd_ctx->data_tr_pkt_num, 0, sizeof(cmd_ctx->data_tr_pkt_num));
    nvme_build_pending_transfer_key(tr_key, req);
    wmem_tree_insert32_array(q_ctx->data_requests, tr_key, (void *)cmd_ctx);
}

struct nvme_cmd_ctx* nvme_lookup_data_request(struct nvme_q_ctx *q_ctx,
                                        struct keyed_data_req *req)
{
    wmem_tree_key_t tr_key[4];

    nvme_build_pending_transfer_key(tr_key, req);
    return (struct nvme_cmd_ctx*)wmem_tree_lookup32_array(q_ctx->data_requests, tr_key);
}

void
nvme_add_data_tr_pkt(struct nvme_q_ctx *q_ctx,
                       struct nvme_cmd_ctx *cmd_ctx, uint32_t rkey, uint32_t frame_num)
{
    wmem_tree_key_t cmd_key[3];

    nvme_build_done_frame_key(cmd_key, &rkey, &frame_num);
    wmem_tree_insert32_array(q_ctx->data_responses, cmd_key, (void*)cmd_ctx);
}

struct nvme_cmd_ctx*
nvme_lookup_data_tr_pkt(struct nvme_q_ctx *q_ctx,
                          uint32_t rkey, uint32_t frame_num)
{
    wmem_tree_key_t cmd_key[3];

    nvme_build_done_frame_key(cmd_key, &rkey, &frame_num);
    return (struct nvme_cmd_ctx*)wmem_tree_lookup32_array(q_ctx->data_responses, cmd_key);
}

void
nvme_add_data_tr_off(struct nvme_q_ctx *q_ctx, uint32_t off, uint32_t frame_num)
{
    wmem_tree_key_t cmd_key[2];

    nvme_build_done_frame_key(cmd_key, NULL, &frame_num);
    wmem_tree_insert32_array(q_ctx->data_offsets, cmd_key, GUINT_TO_POINTER(off));
}

uint32_t
nvme_lookup_data_tr_off(struct nvme_q_ctx *q_ctx, uint32_t frame_num)
{
    wmem_tree_key_t cmd_key[2];

    nvme_build_done_frame_key(cmd_key, NULL, &frame_num);
    return GPOINTER_TO_UINT(wmem_tree_lookup32_array(q_ctx->data_offsets, cmd_key));
}

void
nvme_add_cmd_cqe_to_done_list(struct nvme_q_ctx *q_ctx,
                              struct nvme_cmd_ctx *cmd_ctx, uint16_t cmd_id)
{
    wmem_tree_key_t cmd_key[3];
    uint32_t key = cmd_id;
    uint32_t frame_num;

    nvme_build_done_frame_key(cmd_key, &key, &frame_num);

    /* found matching entry. Add entries to the matched table for both cmd and cqe.
     */
    frame_num = cmd_ctx->cqe_pkt_num;
    wmem_tree_insert32_array(q_ctx->done_cmds, cmd_key, (void*)cmd_ctx);

    frame_num = cmd_ctx->cmd_pkt_num;
    wmem_tree_insert32_array(q_ctx->done_cmds, cmd_key, (void*)cmd_ctx);
}

void*
nvme_lookup_cmd_in_done_list(packet_info *pinfo, struct nvme_q_ctx *q_ctx,
                             uint16_t cmd_id)
{
    wmem_tree_key_t cmd_key[3];
    uint32_t key = cmd_id;
    uint32_t frame_num = pinfo->num;

    nvme_build_done_frame_key(cmd_key, &key, &frame_num);

    return wmem_tree_lookup32_array(q_ctx->done_cmds, cmd_key);
}

void
nvme_publish_cmd_latency(proto_tree *tree, struct nvme_cmd_ctx *cmd_ctx,
                         int field_index)
{
    proto_item *cmd_ref_item;
    nstime_t ns;
    double cmd_latency;

    nstime_delta(&ns, &cmd_ctx->cmd_end_time, &cmd_ctx->cmd_start_time);
    cmd_latency = nstime_to_msec(&ns);
    cmd_ref_item = proto_tree_add_double_format_value(tree, field_index,
                            NULL, 0, 0, cmd_latency,
                            "%.3f ms", cmd_latency);
    proto_item_set_generated(cmd_ref_item);
}

void nvme_update_cmd_end_info(packet_info *pinfo, struct nvme_cmd_ctx *cmd_ctx)
{
    cmd_ctx->cmd_end_time = pinfo->abs_ts;
    cmd_ctx->cqe_pkt_num = pinfo->num;
}

void
nvme_publish_link(proto_tree *tree, tvbuff_t *tvb, int hf_index,
                                       uint32_t pkt_no, bool zero_ok)
{
    proto_item *ref_item;

    if (pkt_no || zero_ok) {
        ref_item = proto_tree_add_uint(tree, hf_index,
                                 tvb, 0, 0, pkt_no);
        proto_item_set_generated(ref_item);
    }
}

void
nvme_publish_to_cmd_link(proto_tree *tree, tvbuff_t *tvb,
                          int hf_index, struct nvme_cmd_ctx *cmd_ctx)
{
    nvme_publish_link(tree, tvb, hf_index, cmd_ctx->cmd_pkt_num, true);
}

void
nvme_publish_to_cqe_link(proto_tree *tree, tvbuff_t *tvb,
                             int hf_index, struct nvme_cmd_ctx *cmd_ctx)
{
    nvme_publish_link(tree, tvb, hf_index, cmd_ctx->cqe_pkt_num, false);
}

void
nvme_publish_to_data_req_link(proto_tree *tree, tvbuff_t *tvb,
                             int hf_index, struct nvme_cmd_ctx *cmd_ctx)
{
    nvme_publish_link(tree, tvb, hf_index, cmd_ctx->data_req_pkt_num, false);
}

static void
nvme_publish_to_data_tr_links(proto_tree *tree, tvbuff_t *tvb,
                             int *index_arr, struct nvme_cmd_ctx *cmd_ctx)
{
    unsigned i;
    for (i = 0; i < NVME_CMD_MAX_TRS; i++)
        nvme_publish_link(tree, tvb, index_arr[i], cmd_ctx->data_tr_pkt_num[i], false);
}

void nvme_publish_to_data_resp_link(proto_tree *tree, tvbuff_t *tvb,
                             int hf_index, struct nvme_cmd_ctx *cmd_ctx)
{
    nvme_publish_link(tree, tvb, hf_index, cmd_ctx->data_tr_pkt_num[0], false);
}

void dissect_nvme_cmd_sgl(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
                          int field_index, struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx, unsigned cmd_off, bool visited)
{
    proto_item *ti, *sgl_tree, *type_item, *sub_type_item;
    uint8_t sgl_identifier, desc_type, desc_sub_type;
    int offset = 24 + cmd_off;

    ti = proto_tree_add_item(cmd_tree, field_index, cmd_tvb, offset,
                             16, ENC_NA);
    sgl_tree = proto_item_add_subtree(ti, ett_data);

    sgl_identifier = tvb_get_uint8(cmd_tvb, offset + 15);
    desc_type = (sgl_identifier & 0xff) >> 4;
    desc_sub_type = sgl_identifier & 0x0f;

    type_item = proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_type,
                                    cmd_tvb, offset + 15, 1, ENC_LITTLE_ENDIAN);
    proto_item_append_text(type_item, " %s",
                           val_to_str_const(desc_type, sgl_type_tbl, "Reserved"));

    sub_type_item = proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_sub_type,
                                        cmd_tvb,
                                        offset + 15, 1, ENC_LITTLE_ENDIAN);
    proto_item_append_text(sub_type_item, " %s",
                           val_to_str_const(desc_sub_type, sgl_sub_type_tbl, "Reserved"));

    switch (desc_type) {
    case NVME_CMD_SGL_DATA_DESC:
    case NVME_CMD_SGL_LAST_SEGMENT_DESC:
    case NVME_CMD_SGL_SEGMENT_DESC:
        proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_addr, cmd_tvb,
                            offset, 8, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_len, cmd_tvb,
                            offset + 8, 4, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_rsvd, cmd_tvb,
                            offset + 12, 3, ENC_NA);
        break;
    case NVME_CMD_SGL_BIT_BUCKET_DESC:
        proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_addr_rsvd, cmd_tvb,
                            offset, 8, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_len, cmd_tvb,
                            offset + 8, 4, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_rsvd, cmd_tvb,
                            offset + 12, 3, ENC_NA);
        break;
    case NVME_CMD_SGL_KEYED_DATA_DESC:
    {
        struct keyed_data_req req;
        proto_tree_add_item_ret_uint64(sgl_tree, hf_nvme_cmd_sgl_desc_addr, cmd_tvb,
                            offset, 8, ENC_LITTLE_ENDIAN, &req.addr);
        proto_tree_add_item_ret_uint(sgl_tree, hf_nvme_cmd_sgl_desc_len, cmd_tvb,
                            offset + 8, 3, ENC_LITTLE_ENDIAN, &req.size);
        proto_tree_add_item_ret_uint(sgl_tree, hf_nvme_cmd_sgl_desc_key, cmd_tvb,
                            offset + 11, 4, ENC_LITTLE_ENDIAN, &req.key);
        if (!visited && cmd_ctx && q_ctx && q_ctx->data_requests)
            nvme_add_data_request(q_ctx, cmd_ctx, &req);
        break;
    }
    case NVME_CMD_SGL_VENDOR_DESC:
    default:
        break;
    }
}

static void
dissect_nvme_rwc_common_word_10_11_12_14_15(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    proto_item *ti, *prinfo_tree;
    uint16_t num_lba;

    /* word 10, 11 */
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_slba, cmd_tvb,
                        40, 8, ENC_LITTLE_ENDIAN);
    /* add 1 for readability, as its zero based value */
    num_lba = tvb_get_uint16(cmd_tvb, 48, ENC_LITTLE_ENDIAN) + 1;

    /* word 12 */
    proto_tree_add_uint(cmd_tree, hf_nvme_cmd_nlb,
                        cmd_tvb, 48, 2, num_lba);

    proto_tree_add_item(cmd_tree, hf_nvme_cmd_rsvd2, cmd_tvb,
                        50, 2, ENC_LITTLE_ENDIAN);

    ti = proto_tree_add_item(cmd_tree, hf_nvme_cmd_prinfo, cmd_tvb, 50,
                             2, ENC_LITTLE_ENDIAN);
    prinfo_tree = proto_item_add_subtree(ti, ett_data);

    proto_tree_add_item(prinfo_tree, hf_nvme_cmd_prinfo_prchk_lbrtag, cmd_tvb,
                        50, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(prinfo_tree, hf_nvme_cmd_prinfo_prchk_apptag, cmd_tvb,
                        50, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(prinfo_tree, hf_nvme_cmd_prinfo_prchk_guard, cmd_tvb,
                        50, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(prinfo_tree, hf_nvme_cmd_prinfo_pract, cmd_tvb,
                        50, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(cmd_tree, hf_nvme_cmd_fua, cmd_tvb,
                        50, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_lr, cmd_tvb,
                        50, 2, ENC_LITTLE_ENDIAN);

    /* word 14, 15 */
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_eilbrt, cmd_tvb,
                        56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_elbat, cmd_tvb,
                        60, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_elbatm, cmd_tvb,
                        62, 2, ENC_LITTLE_ENDIAN);
}

/* Stop dissecting an offset-windowed response structure once the field at
 * __field_off__ (length __field_len__) no longer fits in the transfer: the
 * caller's 'off' is the structure offset the data begins at and 'len' the
 * bytes available, so a chunked or NVMe-MI DLEN-truncated response stops
 * cleanly rather than overrunning the payload. */
#define CHECK_STOP_PARSE(__field_off__, __field_len__) \
do { \
    if ((__field_off__ - off + __field_len__) > len) \
        return; \
} while(0)

static void dissect_nvme_identify_ns_lbafs(tvbuff_t *cmd_tvb, packet_info *pinfo, proto_tree *cmd_tree)
{
    proto_item *ti, *lbafs_tree, *item;
    int lbaf_off, i, nlbaf;
    uint8_t lbads;
    uint16_t ms;
    uint32_t lbaf_raw;
    bool over_declared;

    /* Supported formats are the NLBAF (byte 25, 0's based) shared-attribute
     * ones followed directly by the NULBAF (byte 82) unique-attribute ones;
     * a Format Index at or above their sum is invalid and not supported
     * (NVM Command Set 1.2 section 5.5).  Section 5.5 also caps the total at
     * 64, the number of entries the 383:128 region holds, so clamp there too
     * and a bogus NLBAF/NULBAF cannot drive reads past the region. */
    nlbaf = tvb_get_uint8(cmd_tvb, 25) + 1 + tvb_get_uint8(cmd_tvb, 82);
    over_declared = (nlbaf > 64);
    if (over_declared)
        nlbaf = 64;

    ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_lbafs, cmd_tvb,
                             128, 256, ENC_NA);
    /* The count is intrinsically impossible rather than merely unseen: the
     * 383:128 region holds exactly 64 entries, so no transfer window can make
     * NLBAF+1+NULBAF > 64 legitimate. */
    if (over_declared)
        expert_add_info(pinfo, ti, &ei_nvme_lbaf_count_invalid);
    lbafs_tree = proto_item_add_subtree(ti, ett_data);

    for (i = 0; i < nlbaf; i++) {
        lbaf_off = 128 + i * 4;

        lbaf_raw = tvb_get_uint32(cmd_tvb, lbaf_off, ENC_LITTLE_ENDIAN);
        ms = lbaf_raw & 0xFF;
        lbads = (lbaf_raw >> 16) & 0xF;
        item = proto_tree_add_item(lbafs_tree, hf_nvme_identify_ns_lbaf,
                                   cmd_tvb, lbaf_off, 4, ENC_LITTLE_ENDIAN);
        proto_item_set_text(item, "LBAF%d: lbads %d ms %d", i, lbads, ms);
    }
}

/* Deallocation Read Behavior (DRB), the low 3 bits of DLFEAT. */
static const value_string ns_dlfeat_drb_tbl[] = {
    { 0, "read behavior is not reported" },
    { 1, "deallocated logical block returns all bytes cleared to 0h" },
    { 2, "deallocated logical block returns all bytes set to FFh" },
    { 0, NULL}
};

#define ASPEC(_x_) _x_, array_length(_x_)

/* Both defined further down; used here for the bit-defined bytes (DLFEAT,
 * KPIOS) and the 16-byte NVM Capacity of the Identify Namespace structure. */
static void add_group_mask_entry(tvbuff_t *tvb, proto_tree *tree, unsigned offset, unsigned bytes, int *array, unsigned array_len);
static void post_add_bytes_from_16bytes(proto_item *ti, tvbuff_t *tvb, unsigned off, uint8_t shiftl);

static void dissect_nvme_identify_ns_resp(tvbuff_t *cmd_tvb, packet_info *pinfo,
                                            proto_tree *cmd_tree, unsigned off, unsigned len)
{
    proto_item *ti;
    unsigned start;
    if (!off) {
        /* Fixed-layout fields at the start of the structure.  Each read is
         * length-guarded (off is 0 here) so a response truncated by a small
         * DLEN -- e.g. a chunked Identify over a low-MTU transport -- stops
         * cleanly instead of overrunning the payload. */
        CHECK_STOP_PARSE(0, 8);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nsze, cmd_tvb,
                        0, 8, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(8, 8);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_ncap, cmd_tvb,
                        8, 8, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(16, 8);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nuse, cmd_tvb,
                        16, 8, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(24, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nsfeat, cmd_tvb,
                        24, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(25, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nlbaf, cmd_tvb,
                        25, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(26, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_flbas, cmd_tvb,
                        26, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(27, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_mc, cmd_tvb,
                        27, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(28, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_dpc, cmd_tvb,
                        28, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(29, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_dps, cmd_tvb,
                        29, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(30, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nmic, cmd_tvb,
                        30, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(31, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_rescap, cmd_tvb,
                        31, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(32, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_fpi, cmd_tvb,
                        32, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(33, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 33, 1, ASPEC(hf_nvme_identify_ns_dlfeat));
        CHECK_STOP_PARSE(34, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nawun, cmd_tvb,
                        34, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(36, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nawupf, cmd_tvb,
                        36, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(38, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nacwu, cmd_tvb,
                        38, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(40, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nabsn, cmd_tvb,
                        40, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(42, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nabo, cmd_tvb,
                        42, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(44, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nabspf, cmd_tvb,
                        44, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(46, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_noiob, cmd_tvb,
                        46, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(48, 16);
        ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nvmcap, cmd_tvb,
                        48, 16, ENC_NA);
        post_add_bytes_from_16bytes(ti, cmd_tvb, 48, 0);
        CHECK_STOP_PARSE(64, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_npwg, cmd_tvb,
                        64, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(66, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_npwa, cmd_tvb,
                        66, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(68, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_npdg, cmd_tvb,
                        68, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(70, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_npda, cmd_tvb,
                        70, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(72, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nows, cmd_tvb,
                        72, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(74, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_mssrl, cmd_tvb,
                        74, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(76, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_mcl, cmd_tvb,
                        76, 4, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(80, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_msrc, cmd_tvb,
                        80, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(81, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 81, 1, ASPEC(hf_nvme_identify_ns_kpios));
        CHECK_STOP_PARSE(82, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nulbaf, cmd_tvb,
                        82, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(83, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_rsvd0, cmd_tvb,
                        83, 1, ENC_NA);
        CHECK_STOP_PARSE(84, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_kpiodaag, cmd_tvb,
                        84, 4, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(88, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_rsvd1, cmd_tvb,
                        88, 4, ENC_NA);
        CHECK_STOP_PARSE(92, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_anagrpid, cmd_tvb,
                        92, 4, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(96, 3);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_rsvd2, cmd_tvb,
                        96, 3, ENC_NA);
        CHECK_STOP_PARSE(99, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nsattr, cmd_tvb,
                        99, 1, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(100, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nvmsetid, cmd_tvb,
                        100, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(102, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_endgid, cmd_tvb,
                        102, 2, ENC_LITTLE_ENDIAN);
        CHECK_STOP_PARSE(104, 16);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nguid, cmd_tvb,
                        104, 16, ENC_NA);
        CHECK_STOP_PARSE(120, 8);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_eui64, cmd_tvb,
                        120, 8, ENC_NA);

        /* LBA Formats occupy 383:128 (LBAF0..LBAF63) and Vendor Specific
         * starts immediately at 384 -- nothing in 4095:0 is Reserved. */
        CHECK_STOP_PARSE(128, 256);
        dissect_nvme_identify_ns_lbafs(cmd_tvb, pinfo, cmd_tree);
    }
    if (off >= 384)
        start = 0;
    else
        start = 384 - off;
    /* Vendor-specific area (structure offset 384+).  Only render it once the
     * transfer window actually reaches it; a shorter chunk carries no VS bytes
     * (and 'len - start' would otherwise underflow). */
    if (start < len) {
        ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_vs, cmd_tvb,
                            start, len - start, ENC_NA);
        proto_item_append_text(ti, " (offset %u)", (off <= 384) ? 0 : off-384);
    }
}

/* NSTAT.IOI (I/O Impacted) sub-field, NVMe Base 2.3 Figure 335. */
static const value_string cs_ind_ns_ioi_tbl[] = {
    { 0, "I/O performance degradation is not reported" },
    { 1, "Reserved" },
    { 2, "I/O performance is not currently degraded" },
    { 3, "I/O performance is currently degraded" },
    { 0, NULL }
};

/* Identify - I/O Command Set Independent Identify Namespace (CNS 08h), NVMe
 * Base 2.3 Figure 335.  The defined fields occupy bytes 23:00; 4095:24 is
 * reserved.  Windowed the same way as the sibling Identify decoders: each
 * field renders only when the transfer window starts at or before it, and
 * CHECK_STOP_PARSE stops cleanly on a DLEN-truncated chunk. */
static void dissect_nvme_identify_cs_ind_ns_resp(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, unsigned off, unsigned len)
{
    if (!off) {
        CHECK_STOP_PARSE(0, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 0, 1, ASPEC(hf_nvme_identify_cs_ind_ns_nsfeat));
    }
    if (off <= 1) {
        CHECK_STOP_PARSE(1, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 1-off, 1, ASPEC(hf_nvme_identify_cs_ind_ns_nmic));
    }
    if (off <= 2) {
        CHECK_STOP_PARSE(2, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 2-off, 1, ASPEC(hf_nvme_identify_cs_ind_ns_rescap));
    }
    if (off <= 3) {
        CHECK_STOP_PARSE(3, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 3-off, 1, ASPEC(hf_nvme_identify_cs_ind_ns_fpi));
    }
    if (off <= 4) {
        CHECK_STOP_PARSE(4, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_cs_ind_ns_anagrpid, cmd_tvb, 4-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 8) {
        CHECK_STOP_PARSE(8, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 8-off, 1, ASPEC(hf_nvme_identify_cs_ind_ns_nsattr));
    }
    if (off <= 9) {
        CHECK_STOP_PARSE(9, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_cs_ind_ns_rsvd0, cmd_tvb, 9-off, 1, ENC_NA);
    }
    if (off <= 10) {
        CHECK_STOP_PARSE(10, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_cs_ind_ns_nvmsetid, cmd_tvb, 10-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 12) {
        CHECK_STOP_PARSE(12, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_cs_ind_ns_endgid, cmd_tvb, 12-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 14) {
        CHECK_STOP_PARSE(14, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 14-off, 1, ASPEC(hf_nvme_identify_cs_ind_ns_nstat));
    }
    if (off <= 15) {
        CHECK_STOP_PARSE(15, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 15-off, 1, ASPEC(hf_nvme_identify_cs_ind_ns_kpios));
    }
    if (off <= 16) {
        CHECK_STOP_PARSE(16, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_cs_ind_ns_maxkt, cmd_tvb, 16-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 18) {
        CHECK_STOP_PARSE(18, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_cs_ind_ns_rsvd1, cmd_tvb, 18-off, 2, ENC_NA);
    }
    if (off <= 20) {
        CHECK_STOP_PARSE(20, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_cs_ind_ns_rgrpid, cmd_tvb, 20-off, 4, ENC_LITTLE_ENDIAN);
    }
}

static void dissect_nvme_identify_nslist_resp(tvbuff_t *cmd_tvb,
                                              proto_tree *cmd_tree, unsigned off, unsigned len)
{
    uint32_t nsid;
    proto_item *item;
    unsigned done = 0;

    for (; off < 4096 && (done + 4) <= len; off += 4) {
        nsid = tvb_get_uint32(cmd_tvb, done, ENC_LITTLE_ENDIAN);
        if (nsid == 0)
            break;

        item = proto_tree_add_item(cmd_tree, hf_nvme_identify_nslist_nsid,
                                   cmd_tvb, done, 4, ENC_LITTLE_ENDIAN);
        proto_item_set_text(item, "nsid[%u]: %u", off / 4, nsid);
        done += 4;
    }
}

/* Namespace Identification Descriptor list (CNS 03h), NVMe Base 2.3 Figure
 * 331: a packed list of variable-length descriptors, each NIDT(1)+NIDL(1)+
 * reserved(2)+NID(NIDL), terminated by a descriptor with NIDL == 0.  The list
 * is self-delimiting and cannot be resynchronised from a mid-structure window,
 * so only a transfer starting at structure offset 0 is decoded. */
static void dissect_nvme_identify_nsid_desc_list_resp(tvbuff_t *cmd_tvb,
                                              proto_tree *cmd_tree, unsigned off, unsigned len)
{
    unsigned done = 0;
    unsigned idx = 0;

    if (off)
        return;

    while (done + 4 <= len) {
        uint8_t nidl = tvb_get_uint8(cmd_tvb, done + 1);
        unsigned dlen;
        proto_tree *grp;

        if (nidl == 0)
            break;          /* NIDL 0h marks the end of the list */
        dlen = 4u + nidl;
        if (done + dlen > len)
            break;          /* descriptor would overrun the payload */

        grp = proto_tree_add_subtree_format(cmd_tree, cmd_tvb, done, dlen,
                                            ett_data, NULL,
                                            "Namespace Identification Descriptor %u", idx);
        proto_tree_add_item(grp, hf_nvme_identify_nsdesc_nidt, cmd_tvb, done, 1, ENC_NA);
        proto_tree_add_item(grp, hf_nvme_identify_nsdesc_nidl, cmd_tvb, done + 1, 1, ENC_NA);
        proto_tree_add_item(grp, hf_nvme_identify_nsdesc_nid, cmd_tvb, done + 4, nidl, ENC_NA);

        done += dlen;
        idx++;
    }
}

/* Controller List (CNS 12h attached-to-NSID / CNS 13h NVM-subsystem), NVMe
 * Base 2.3 "Controller List Format": a 2-byte NUMCIDS count followed by that
 * many 2-byte controller identifiers (up to 2,047).  Only decoded from
 * structure offset 0 since NUMCIDS sits in the header. */
static void dissect_nvme_identify_ctrl_list_resp(tvbuff_t *cmd_tvb,
                                              proto_tree *cmd_tree, unsigned off, unsigned len)
{
    uint32_t numcids;
    unsigned i, done;

    if (off || len < 2)
        return;

    proto_tree_add_item_ret_uint(cmd_tree, hf_nvme_identify_ctrl_list_num,
                                 cmd_tvb, 0, 2, ENC_LITTLE_ENDIAN, &numcids);

    done = 2;
    for (i = 0; i < numcids && i < 2047 && done + 2 <= len; i++) {
        uint32_t cid;
        proto_item *item = proto_tree_add_item_ret_uint(cmd_tree,
                                hf_nvme_identify_ctrl_list_id, cmd_tvb, done, 2,
                                ENC_LITTLE_ENDIAN, &cid);
        proto_item_set_text(item, "Controller Identifier[%u]: 0x%04x", i, cid);
        done += 2;
    }
}

static void add_group_mask_entry(tvbuff_t *tvb, proto_tree *tree, unsigned offset, unsigned bytes, int *array, unsigned array_len)
{
    proto_item *ti;
    proto_tree *grp;
    unsigned i;

    ti = proto_tree_add_item(tree, array[0], tvb, offset, bytes, ENC_LITTLE_ENDIAN);
    grp =  proto_item_add_subtree(ti, ett_data);

    for (i = 1; i < array_len; i++)
        proto_tree_add_item(grp, array[i], tvb, offset, bytes, ENC_LITTLE_ENDIAN);
}

/* NVM Set List (CNS 04h): a 1-byte NUMENT header (up to 31 entries) with the
 * entry list starting at structure offset 128, each entry 128 bytes.  Only
 * decoded from structure offset 0 since NUMENT sits in the header. */
static void dissect_nvme_identify_nvmset_resp(tvbuff_t *cmd_tvb,
                                              proto_tree *cmd_tree, unsigned off, unsigned len)
{
    uint32_t nument;
    unsigned i;

    if (off || len < 1)
        return;

    proto_tree_add_item_ret_uint(cmd_tree, hf_nvme_identify_nvmset_num,
                                 cmd_tvb, 0, 1, ENC_LITTLE_ENDIAN, &nument);

    for (i = 0; i < nument && i < 31; i++) {
        unsigned entry = 128 + i * 128;
        proto_tree *grp;

        if (entry + 48 > len)
            break;          /* entry (through UNVMSC) would overrun the payload */

        grp = proto_tree_add_subtree_format(cmd_tree, cmd_tvb, entry, 128,
                                            ett_data, NULL,
                                            "NVM Set Attributes Entry %u", i);
        proto_tree_add_item(grp, hf_nvme_identify_nvmset_id, cmd_tvb, entry, 2, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_nvmset_endgid, cmd_tvb, entry + 2, 2, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_nvmset_r4krt, cmd_tvb, entry + 8, 4, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_nvmset_ows, cmd_tvb, entry + 12, 4, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_nvmset_tnvmsc, cmd_tvb, entry + 16, 16, ENC_NA);
        proto_tree_add_item(grp, hf_nvme_identify_nvmset_unvmsc, cmd_tvb, entry + 32, 16, ENC_NA);
    }
}

/* Primary Controller Capabilities (CNS 14h): fixed 80-byte layout at the
 * start of the 4 KiB structure; only decoded from structure offset 0. */
static void dissect_nvme_identify_pri_ctrl_cap_resp(tvbuff_t *cmd_tvb,
                                              proto_tree *cmd_tree, unsigned off, unsigned len)
{
    if (off || len < 80)
        return;

    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_cntlid, cmd_tvb, 0, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_portid, cmd_tvb, 2, 2, ENC_LITTLE_ENDIAN);
    add_group_mask_entry(cmd_tvb, cmd_tree, 4, 4, ASPEC(hf_nvme_identify_pcc_crt));
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vqfrt, cmd_tvb, 32, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vqrfa, cmd_tvb, 36, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vqrfap, cmd_tvb, 40, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vqprt, cmd_tvb, 42, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vqfrsm, cmd_tvb, 44, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vqgran, cmd_tvb, 46, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vifrt, cmd_tvb, 64, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_virfa, cmd_tvb, 68, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_virfap, cmd_tvb, 72, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_viprt, cmd_tvb, 74, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vifrsm, cmd_tvb, 76, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_identify_pcc_vigran, cmd_tvb, 78, 2, ENC_LITTLE_ENDIAN);
}

/* Secondary Controller List (CNS 15h): a 1-byte NUMENT header (up to 127
 * entries) with the entry list starting at structure offset 32, each entry
 * 32 bytes.  Only decoded from structure offset 0. */
static void dissect_nvme_identify_sec_ctrl_list_resp(tvbuff_t *cmd_tvb,
                                              proto_tree *cmd_tree, unsigned off, unsigned len)
{
    uint32_t nument;
    unsigned i;

    if (off || len < 1)
        return;

    proto_tree_add_item_ret_uint(cmd_tree, hf_nvme_identify_scl_num,
                                 cmd_tvb, 0, 1, ENC_LITTLE_ENDIAN, &nument);

    for (i = 0; i < nument && i < 127; i++) {
        unsigned entry = 32 + i * 32;
        proto_tree *grp;

        if (entry + 14 > len)
            break;          /* entry (through NVI) would overrun the payload */

        grp = proto_tree_add_subtree_format(cmd_tree, cmd_tvb, entry, 32,
                                            ett_data, NULL,
                                            "Secondary Controller Entry %u", i);
        proto_tree_add_item(grp, hf_nvme_identify_scl_scid, cmd_tvb, entry, 2, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_scl_pcid, cmd_tvb, entry + 2, 2, ENC_LITTLE_ENDIAN);
        add_group_mask_entry(cmd_tvb, grp, entry + 4, 1, ASPEC(hf_nvme_identify_scl_scs));
        proto_tree_add_item(grp, hf_nvme_identify_scl_vfn, cmd_tvb, entry + 8, 2, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_scl_nvq, cmd_tvb, entry + 10, 2, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_scl_nvi, cmd_tvb, entry + 12, 2, ENC_LITTLE_ENDIAN);
    }
}

/* Namespace Granularity List (CNS 16h): a 4-byte NGA header, a 1-byte ND
 * count (0's based, up to 64 descriptors), with the descriptor list starting
 * at structure offset 32, each descriptor 16 bytes (NSG + NCG).  Only
 * decoded from structure offset 0. */
static void dissect_nvme_identify_ns_gran_list_resp(tvbuff_t *cmd_tvb,
                                              proto_tree *cmd_tree, unsigned off, unsigned len)
{
    uint32_t nd;
    unsigned i;

    if (off || len < 5)
        return;

    add_group_mask_entry(cmd_tvb, cmd_tree, 0, 4, ASPEC(hf_nvme_identify_ngl_nga));
    proto_tree_add_item_ret_uint(cmd_tree, hf_nvme_identify_ngl_nd,
                                 cmd_tvb, 4, 1, ENC_LITTLE_ENDIAN, &nd);

    /* ND is a 0's based count of valid descriptors. */
    for (i = 0; i <= nd && i < 64; i++) {
        unsigned entry = 32 + i * 16;
        proto_tree *grp;

        if (entry + 16 > len)
            break;          /* descriptor would overrun the payload */

        grp = proto_tree_add_subtree_format(cmd_tree, cmd_tvb, entry, 16,
                                            ett_data, NULL,
                                            "Namespace Granularity Descriptor %u", i);
        proto_tree_add_item(grp, hf_nvme_identify_ngl_nsg, cmd_tvb, entry, 8, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_ngl_ncg, cmd_tvb, entry + 8, 8, ENC_LITTLE_ENDIAN);
    }
}

/* UUID List (CNS 17h): a 32-byte reserved header followed by up to 127 UUID
 * List Entries, each 32 bytes (a 1-byte header carrying the Identifier
 * Association, then a 128-bit UUID at byte 16).  A UUID cleared to 0h marks
 * the end of the list.  Only decoded from structure offset 0 since entries
 * are indexed from the fixed header. */
static void dissect_nvme_identify_uuid_list_resp(tvbuff_t *cmd_tvb,
                                              proto_tree *cmd_tree, unsigned off, unsigned len)
{
    unsigned i;

    if (off)
        return;

    for (i = 1; i < 128; i++) {
        unsigned entry = i * 32;
        proto_tree *grp;

        if (entry + 32 > len)
            break;          /* entry would overrun the payload */
        if (tvb_get_uint64(cmd_tvb, entry + 16, ENC_LITTLE_ENDIAN) == 0 &&
            tvb_get_uint64(cmd_tvb, entry + 24, ENC_LITTLE_ENDIAN) == 0)
            break;          /* a UUID cleared to 0h ends the list */

        grp = proto_tree_add_subtree_format(cmd_tree, cmd_tvb, entry, 32,
                                            ett_data, NULL,
                                            "UUID List Entry %u", i);
        proto_tree_add_item(grp, hf_nvme_identify_uuid_idassoc, cmd_tvb, entry, 1, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_identify_uuid_uuid, cmd_tvb, entry + 16, 16, ENC_NA);
    }
}

static void add_ctrl_x16_bytes( char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "%x (%u bytes)", val, val * 16);
}

static void dissect_nvme_identify_ctrl_resp_nvmeof(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
{
    proto_item *ti;
    proto_tree *grp;

    ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nvmeof, cmd_tvb, 1792-off, 256, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_ioccsz, cmd_tvb, 1792-off, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_iorcsz, cmd_tvb, 1796-off, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_icdoff, cmd_tvb, 1800-off, 2, ENC_LITTLE_ENDIAN);

    add_group_mask_entry(cmd_tvb, grp, 1802-off, 1, ASPEC(hf_nvme_identify_ctrl_nvmeof_fcatt));
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_msdbd, cmd_tvb, 1803-off, 1, ENC_LITTLE_ENDIAN);
    add_group_mask_entry(cmd_tvb, grp, 1804-off, 2, ASPEC(hf_nvme_identify_ctrl_nvmeof_ofcs));
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_dctype, cmd_tvb, 1806-off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_ccrl, cmd_tvb, 1807-off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_rsvd, cmd_tvb, 1808-off, 240, ENC_NA);
}


static const true_false_string units_watts = {
    "1 (0.0001 Watt units)",
    "0 (0.01 Watt units)"
};


static const value_string power_scale_tbl[] = {
    { 0, "not reported for this power state" },
    { 1, "0.0001 Watt units" },
    { 2, "0.01 Watt units" },
    { 3,  "reserved value" },
    { 0, NULL}
};

/* Time Scale Values, NVMe Base 2.3 Figure 330 (EPFRTS / FQVTS / EPFVTS) */
static const value_string time_scale_tbl[] = {
    { 0x0, "1 microsecond" },
    { 0x1, "10 microseconds" },
    { 0x2, "100 microseconds" },
    { 0x3, "1 millisecond" },
    { 0x4, "10 milliseconds" },
    { 0x5, "100 milliseconds" },
    { 0x6, "1 second" },
    { 0x7, "10 seconds" },
    { 0x8, "100 seconds" },
    { 0x9, "1,000 seconds" },
    { 0xA, "10,000 seconds" },
    { 0xB, "100,000 seconds" },
    { 0xC, "1,000,000 seconds" },
    { 0xD, "reserved value" },
    { 0xE, "reserved value" },
    { 0xF, "reserved value" },
    { 0, NULL}
};

/* Max Bandwidth Scale, NVMe Base 2.3 Figure 329 (bits 234:232) */
static const value_string max_bw_scale_tbl[] = {
    { 0, "1 MiB/second" },
    { 1, "10 MiB/second" },
    { 2, "100 MiB/second" },
    { 3, "1 GiB/second" },
    { 4, "10 GiB/second" },
    { 5, "100 GiB/second" },
    { 6, "reserved value" },
    { 7, "reserved value" },
    { 0, NULL}
};

static void dissect_nvme_identify_ctrl_resp_power_state_descriptor(tvbuff_t *cmd_tvb, proto_tree *tree, uint8_t idx, uint32_t off)
{
    proto_item *ti;
    proto_tree *grp;

    off = 2048 - off + idx *32;
    ti = proto_tree_add_bytes_format(tree, hf_nvme_identify_ctrl_psd, cmd_tvb, off, 32, NULL,
                                           "Power State %u Descriptor (PSD%u)", idx, idx);
    grp =  proto_item_add_subtree(ti, ett_data);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_mp, cmd_tvb, off, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd0, cmd_tvb, off+2, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_mxps, cmd_tvb, off+3, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_nops, cmd_tvb, off+3, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd1, cmd_tvb, off+3, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_enlat, cmd_tvb, off+4, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_exlat, cmd_tvb, off+8, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rrt, cmd_tvb, off+12, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd2, cmd_tvb, off+12, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rrl, cmd_tvb, off+13, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd3, cmd_tvb, off+13, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rwt, cmd_tvb, off+14, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd4, cmd_tvb, off+14, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rwl, cmd_tvb, off+15, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd5, cmd_tvb, off+15, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_idlp, cmd_tvb, off+16, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd6, cmd_tvb, off+18, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_ips, cmd_tvb, off+18, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd7, cmd_tvb, off+19, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_actp, cmd_tvb, off+20, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_apw, cmd_tvb, off+22, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd8, cmd_tvb, off+22, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_aps, cmd_tvb, off+22, 1, ENC_LITTLE_ENDIAN);
    /* Bytes 31:23, NVMe Base 2.3 Figure 329: only 31:30 and the two odd
     * nibbles are actually Reserved. */
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_epfrt, cmd_tvb, off+23, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_fqvt, cmd_tvb, off+24, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_epfvt, cmd_tvb, off+25, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_epfrts, cmd_tvb, off+26, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_fqvts, cmd_tvb, off+26, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_epfvts, cmd_tvb, off+27, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd9, cmd_tvb, off+27, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_mbw, cmd_tvb, off+28, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_mbws, cmd_tvb, off+29, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd10, cmd_tvb, off+29, 1, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd11, cmd_tvb, off+30, 2, ENC_NA);
}

static void dissect_nvme_identify_ctrl_resp_power_state_descriptors(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
{
    proto_item *ti;
    proto_tree *grp;
    unsigned i;

    ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_psds, cmd_tvb, 2048-off, 1024, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);
    for (i = 0; i < 32; i++)
        dissect_nvme_identify_ctrl_resp_power_state_descriptor(cmd_tvb, grp, i, off);
}


static void add_ctrl_rab(char *result, uint32_t val)
{
    if (val >= 64)
        snprintf(result, ITEM_LABEL_LENGTH, "0x%x (overflow)", val);
    else
        snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%"PRIu64" command%s)", val, ((uint64_t)1) << val, val ? "s" : "");
}

static void add_ctrl_mdts(char *result, uint32_t val)
{
    if (val >= 64)
        snprintf(result, ITEM_LABEL_LENGTH, "0x%x (overflow)", val);
    else if (val)
        snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%"PRIu64" pages)", val, ((uint64_t)1) << val);
    else
        snprintf(result, ITEM_LABEL_LENGTH, "0x%x (unlimited)", val);
}

static void add_ctrl_rtd3(char *result, uint32_t val)
{
    if (!val)
        snprintf(result, ITEM_LABEL_LENGTH, "0 (not reported)");
    else
        snprintf(result, ITEM_LABEL_LENGTH, "%u (%u microsecond%s)", val, val, (val > 1) ? "s" : "");
}

static const value_string ctrl_type_tbl[] = {
    { 0,  "Reserved (not reported)" },
    { 1,  "I/O Controller" },
    { 2,  "Discovery Controller" },
    { 3,  "Administrative Controller" },
    { 0, NULL}
};

static const value_string ctrl_rpmbbpwps_tbl[] = {
    { 0,  "Not specified" },
    { 1,  "Not supported" },
    { 2,  "Supported" },
    { 3,  "Reserved" },
    { 0, NULL}
};

static const value_string ctrl_mups_tbl[] = {
    { 0,  "Reserved" },
    { 1,  "0.0001 W" },
    { 2,  "0.01 W" },
    { 3,  "Reserved" },
    { 0, NULL}
};

static const value_string ctrl_srs_tbl[] = {
    { 0,  "Not reported" },
    { 1,  "1 microsecond" },
    { 2,  "10 microseconds" },
    { 3,  "100 microseconds" },
    { 4,  "1 millisecond" },
    { 5,  "10 milliseconds" },
    { 0, NULL}
};

static const value_string ctrl_dctype_tbl[] = {
    { 0,  "Not reported" },
    { 1,  "Direct Discovery Controller (DDC)" },
    { 2,  "Centralized Discovery Controller (CDC)" },
    { 0, NULL}
};

static void add_ctrl_ms(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "%u (%u ms)", val, val * 100);
}

static void dissect_nvme_identify_ctrl_resp_ver(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
{
    proto_item *ti;
    proto_tree *grp;

    ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_ver, cmd_tvb,  80-off, 4, ENC_LITTLE_ENDIAN);
    grp =  proto_item_add_subtree(ti, ett_data);

    proto_tree_add_item(grp, hf_nvme_identify_ctrl_ver_mjr, cmd_tvb, 82-off, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_ver_min, cmd_tvb, 81-off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_ver_ter, cmd_tvb, 80-off, 1, ENC_LITTLE_ENDIAN);
}

static void dissect_nvme_identify_ctrl_resp_fguid(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
{
    proto_item *ti;
    proto_tree *grp;

    /* FGUID uses the EUI-64 based 16-byte designator format and, per the
     * NVMe Base spec, "This field is big endian" -- unlike virtually all
     * other multi-byte NVMe fields, which default to little endian. */
    ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_fguid, cmd_tvb, 112-off, 16, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_fguid_vse, cmd_tvb, 112-off, 8, ENC_BIG_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_fguid_oui, cmd_tvb, 120-off, 3, ENC_BIG_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_fguid_ei, cmd_tvb, 123-off, 5, ENC_BIG_ENDIAN);
}

static void dissect_nvme_identify_ctrl_resp_mi(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
{
    proto_item *ti;
    proto_tree *grp;

    ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mi, cmd_tvb, 240-off, 16, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);
    proto_tree_add_item(grp, hf_nvme_identify_ctrl_mi_rsvd, cmd_tvb, 240-off, 13, ENC_NA);
    add_group_mask_entry(cmd_tvb, grp, 253-off, 1, ASPEC(hf_nvme_identify_ctrl_mi_nvmsr));
    add_group_mask_entry(cmd_tvb, grp, 254-off, 1, ASPEC(hf_nvme_identify_ctrl_mi_vwci));
    add_group_mask_entry(cmd_tvb, grp, 255-off, 1, ASPEC(hf_nvme_identify_ctrl_mi_mec));
}

static void add_ctrl_commands(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "0x%x: (%u command%s)", val, val+1, val ? "s" : "");
}

static void add_ctrl_events(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "0x%x: (%u event%s)", val, val+1, val ? "s" : "");
}

static void add_ctrl_entries(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "0x%x: (%u entr%s)", val, val+1, val ? "ies" : "y");
}

static void add_ctrl_states(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "0x%x: (%u state%s)", val, val+1, val ? "s" : "");
}

static void add_ctrl_hmpre(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%"PRIu64" bytes)", val, ((uint64_t)(val)) * 4096);
}

static void post_add_bytes_from_16bytes(proto_item *ti, tvbuff_t *tvb, unsigned off, uint8_t shiftl)
{
    /* The 128-bit value is little-endian on the wire: byte `off` holds the
     * low-order 64 bits and byte `off+8` holds the high-order 64 bits. */
    uint64_t lo = tvb_get_uint64(tvb, off, ENC_LITTLE_ENDIAN);
    uint64_t hi = tvb_get_uint64(tvb, off+8, ENC_LITTLE_ENDIAN);

    if (shiftl) {
        hi = hi << shiftl;
        hi |= (lo >> (64-shiftl));
        lo = lo << shiftl;
    }
    if (hi) {
        if (!(hi >> 10))
            proto_item_append_text(ti, " (%" PRIu64 " KiB)", (hi << 54) | (lo >> 10));
        else if (!(hi >> 20))
            proto_item_append_text(ti, " (%" PRIu64 " MiB)", (hi << 44) | (lo >> 20));
        else if (!(hi >> 30))
            proto_item_append_text(ti, " (%" PRIu64 " GiB)", (hi << 34) | (lo >> 30));
        else if (!(hi >> 40))
            proto_item_append_text(ti, " (%" PRIu64 " TiB)", (hi << 24) | (lo >> 40));
        else if (!(hi >> 50))
            proto_item_append_text(ti, " (%" PRIu64 " PiB)", (hi << 14) | (lo >> 50));
        else if (!(hi >> 60))
            proto_item_append_text(ti, " (%" PRIu64 " EiB)", (hi << 4) | (lo >> 60));
        else
            proto_item_append_text(ti, " (%" PRIu64 " ZiB)", hi >> 6);
    } else {
        proto_item_append_text(ti, " (%" PRIu64 " bytes)", lo);
    }
}

static void add_ctrl_tmt(char *result, uint32_t val)
{
    if (!val)
        snprintf(result, ITEM_LABEL_LENGTH, "0 (not supported)");
    else
        snprintf(result, ITEM_LABEL_LENGTH, "%u degrees K", val);
}

static const value_string mmas_type_tbl[] = {
    { 0,  "modification not defined" },
    { 1,  "no modification after sanitize completion" },
    { 2,  "additional modification after sanitize completion" },
    { 0, NULL}
};

static void add_ctrl_pow2_bytes(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%" PRIu64" bytes)", val, ((uint64_t)1) << val);
}

static void add_ctrl_pow2_page_size(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%" PRIu64" bytes)", val, ((uint64_t)1) << (12+val));
}

static void add_ctrl_pow2_dstrd_size(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%" PRIu64" bytes)", val, ((uint64_t)1) << (2+val));
}


static const value_string fcb_type_tbl[] = {
    { 0, "support for the NSID field set to FFFFFFFFh is not indicated" },
    { 1, "reserved value" },
    { 2, "Flush command does not support the NSID field set to FFFFFFFFh" },
    { 3, "Flush command supports the NSID field set to FFFFFFFFh" },
    { 0, NULL}
};


static void add_ctrl_lblocks(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "%u logical block%s", val + 1, val ? "s" : "");
}

static const value_string sgls_ify_type_tbl[] = {
    { 0,  "SGLs are not supported." },
    { 1, "SGLs are supported without alignment or granularity limitations" },
    { 2, "SGLs are supported with DWORD alignment and granularity limitation" },
    { 3,  "reserved value" },
    { 0, NULL}
};

/* Defined further down with the Get Log Page helpers; used here for the two
 * 16-byte count fields (MAXDNA) in the Identify Controller structure. */
static void post_add_intval_from_16bytes(proto_item *ti, tvbuff_t *tvb, unsigned off);

static void dissect_nvme_identify_ctrl_resp(tvbuff_t *cmd_tvb,
                                            proto_tree *cmd_tree, unsigned off, unsigned len)
{
    proto_item *ti;

    if (!off) {
        CHECK_STOP_PARSE(0, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_vid, cmd_tvb, 0, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 2) {
        CHECK_STOP_PARSE(2, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_ssvid, cmd_tvb, 2-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 4) {
        CHECK_STOP_PARSE(4, 20);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_sn, cmd_tvb, 4-off, 20, ENC_ASCII);
    }
    if (off <= 24) {
        CHECK_STOP_PARSE(24, 40);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mn, cmd_tvb, 24-off, 40, ENC_ASCII);
    }
    if (off <= 64) {
        CHECK_STOP_PARSE(64, 8);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_fr, cmd_tvb, 64-off, 8, ENC_ASCII);
    }
    if (off <= 72) {
        CHECK_STOP_PARSE(72, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rab, cmd_tvb, 72-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 73) {
        CHECK_STOP_PARSE(73, 3);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_ieee, cmd_tvb, 73-off, 3, ENC_LITTLE_ENDIAN);
    }
    if (off <= 76) {
        CHECK_STOP_PARSE(76, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 76-off, 1, ASPEC(hf_nvme_identify_ctrl_cmic));
    }
    if (off <= 77) {
        CHECK_STOP_PARSE(77, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mdts, cmd_tvb, 77-off, 1, ENC_LITTLE_ENDIAN);
    }

    if (off <= 78) {
        CHECK_STOP_PARSE(78, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cntlid, cmd_tvb, 78-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 80) {
        CHECK_STOP_PARSE(80, 4);
        dissect_nvme_identify_ctrl_resp_ver(cmd_tvb, cmd_tree, off);
    }
    if (off <= 84) {
        CHECK_STOP_PARSE(84, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rtd3r, cmd_tvb, 84-off, 4, ENC_LITTLE_ENDIAN);
    }

    if (off <= 88) {
        CHECK_STOP_PARSE(88, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rtd3e, cmd_tvb, 88-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 92) {
        CHECK_STOP_PARSE(92, 4);
        add_group_mask_entry(cmd_tvb, cmd_tree, 92-off, 4, ASPEC(hf_nvme_identify_ctrl_oaes));
    }
    if (off <= 96) {
        CHECK_STOP_PARSE(96, 4);
        add_group_mask_entry(cmd_tvb, cmd_tree, 96-off, 4, ASPEC(hf_nvme_identify_ctrl_ctratt));
    }

    if (off <= 100) {
        CHECK_STOP_PARSE(100, 2);
        add_group_mask_entry(cmd_tvb, cmd_tree, 100-off, 2, ASPEC(hf_nvme_identify_ctrl_rrls));
    }
    if (off <= 102) {
        CHECK_STOP_PARSE(102, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 102-off, 1, ASPEC(hf_nvme_identify_ctrl_bpcap));
    }
    if (off <= 103) {
        CHECK_STOP_PARSE(103, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd0, cmd_tvb, 103-off, 1, ENC_NA);
    }
    if (off <= 104) {
        CHECK_STOP_PARSE(104, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nssl, cmd_tvb, 104-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 108) {
        CHECK_STOP_PARSE(108, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd6, cmd_tvb, 108-off, 2, ENC_NA);
    }
    if (off <= 110) {
        CHECK_STOP_PARSE(110, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 110-off, 1, ASPEC(hf_nvme_identify_ctrl_plsi));
    }
    if (off <= 111) {
        CHECK_STOP_PARSE(111, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cntrltype, cmd_tvb, 111-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 112) {
        CHECK_STOP_PARSE(112, 16);
        dissect_nvme_identify_ctrl_resp_fguid(cmd_tvb, cmd_tree, off);
    }

    if (off <= 128) {
        CHECK_STOP_PARSE(128, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_crdt1, cmd_tvb, 128-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 130) {
        CHECK_STOP_PARSE(130, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_crdt2, cmd_tvb, 130-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 132)  {
        CHECK_STOP_PARSE(132, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_crdt3, cmd_tvb, 132-off, 2, ENC_LITTLE_ENDIAN);
    }

    if (off <= 134)  {
        CHECK_STOP_PARSE(134, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 134-off, 1, ASPEC(hf_nvme_identify_ctrl_crcap));
    }
    if (off <= 135)  {
        CHECK_STOP_PARSE(135, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_ciu, cmd_tvb, 135-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 136)  {
        CHECK_STOP_PARSE(136, 8);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cirn, cmd_tvb, 136-off, 8, ENC_LITTLE_ENDIAN);
    }
    if (off <= 144)  {
        CHECK_STOP_PARSE(144, 96);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd1, cmd_tvb, 144-off, 96, ENC_NA);
    }
    if (off <= 240)  {
        CHECK_STOP_PARSE(240, 16);
        dissect_nvme_identify_ctrl_resp_mi(cmd_tvb, cmd_tree, off);
    }
    if (off <= 256)  {
        CHECK_STOP_PARSE(256, 2);
        add_group_mask_entry(cmd_tvb, cmd_tree, 256-off, 2, ASPEC(hf_nvme_identify_ctrl_oacs));
    }

    if (off <= 258)  {
        CHECK_STOP_PARSE(258, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_acl, cmd_tvb,  258-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 259)  {
        CHECK_STOP_PARSE(259, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_aerl, cmd_tvb, 259-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 260)  {
        CHECK_STOP_PARSE(260, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 260-off, 1, ASPEC(hf_nvme_identify_ctrl_frmw));
    }

    if (off <= 261)  {
        CHECK_STOP_PARSE(261, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 261-off, 1, ASPEC(hf_nvme_identify_ctrl_lpa));
    }
    if (off <= 262)  {
        CHECK_STOP_PARSE(262, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_elpe, cmd_tvb, 262-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 263)  {
        CHECK_STOP_PARSE(263, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_npss, cmd_tvb, 263-off, 1, ENC_LITTLE_ENDIAN);
    }

    if (off <= 264)  {
        CHECK_STOP_PARSE(264, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 264-off, 1, ASPEC(hf_nvme_identify_ctrl_avscc));
    }
    if (off <= 265)  {
        CHECK_STOP_PARSE(265, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 265-off, 1, ASPEC(hf_nvme_identify_ctrl_apsta));
    }
    if (off <= 266)  {
        CHECK_STOP_PARSE(266, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_wctemp, cmd_tvb, 266-off, 2, ENC_LITTLE_ENDIAN);

    }
    if (off <= 268)  {
        CHECK_STOP_PARSE(268, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cctemp, cmd_tvb, 268-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 270)  {
        CHECK_STOP_PARSE(270, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mtfa, cmd_tvb, 270-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 272)  {
        CHECK_STOP_PARSE(272, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hmpre, cmd_tvb, 272-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 276)  {
        CHECK_STOP_PARSE(276, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hmmin, cmd_tvb, 276-off, 4, ENC_LITTLE_ENDIAN);
    }

    if (off <= 280)  {
        CHECK_STOP_PARSE(280, 16);
        ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_tnvmcap, cmd_tvb, 280-off, 16, ENC_NA);
        post_add_bytes_from_16bytes(ti, cmd_tvb, 280-off, 0);
    }
    if (off <= 296)  {
        CHECK_STOP_PARSE(296, 16);
        ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_unvmcap, cmd_tvb, 296-off, 16, ENC_NA);
        post_add_bytes_from_16bytes(ti, cmd_tvb, 296-off, 0);
    }

    if (off <= 312)  {
        CHECK_STOP_PARSE(312, 4);
        add_group_mask_entry(cmd_tvb, cmd_tree, 312-off, 4, ASPEC(hf_nvme_identify_ctrl_rpmbs));
    }
    if (off <= 316)  {
        CHECK_STOP_PARSE(316, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_edstt, cmd_tvb, 316-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 318)  {
        CHECK_STOP_PARSE(318, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 318-off, 1, ASPEC(hf_nvme_identify_ctrl_dsto));
    }

    if (off <= 319)  {
        CHECK_STOP_PARSE(319, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_fwug, cmd_tvb, 319-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 320)  {
        CHECK_STOP_PARSE(320, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_kas, cmd_tvb, 320-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 322)  {
        CHECK_STOP_PARSE(322, 2);
        add_group_mask_entry(cmd_tvb, cmd_tree, 322-off, 2, ASPEC(hf_nvme_identify_ctrl_hctma));
    }

    if (off <= 324)  {
        CHECK_STOP_PARSE(324, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mntmt, cmd_tvb, 324-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 326)  {
        CHECK_STOP_PARSE(326, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mxtmt, cmd_tvb, 326-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 328)  {
        CHECK_STOP_PARSE(328, 4);
        add_group_mask_entry(cmd_tvb, cmd_tree, 328-off, 4, ASPEC(hf_nvme_identify_ctrl_sanicap));
    }

    if (off <= 332)  {
        CHECK_STOP_PARSE(332, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hmmminds, cmd_tvb, 332-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 336)  {
        CHECK_STOP_PARSE(336, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hmmaxd, cmd_tvb, 336-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 338)  {
        CHECK_STOP_PARSE(338, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nsetidmax, cmd_tvb, 338-off, 2, ENC_LITTLE_ENDIAN);
    }

    if (off <= 340)  {
        CHECK_STOP_PARSE(340, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_endgidmax, cmd_tvb, 340-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 342)  {
        CHECK_STOP_PARSE(342, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_anatt, cmd_tvb, 342-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 343)  {
        CHECK_STOP_PARSE(343, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 343-off, 1, ASPEC(hf_nvme_identify_ctrl_anacap));
    }

    if (off <= 344)  {
        CHECK_STOP_PARSE(344, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_anagrpmax, cmd_tvb, 344-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 348)  {
        CHECK_STOP_PARSE(348, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nanagrpid, cmd_tvb, 348-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 352)  {
        CHECK_STOP_PARSE(352, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_pels, cmd_tvb, 352-off, 4, ENC_LITTLE_ENDIAN);
    }

    if (off <= 356)  {
        CHECK_STOP_PARSE(356, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_did, cmd_tvb, 356-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 358)  {
        CHECK_STOP_PARSE(358, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 358-off, 1, ASPEC(hf_nvme_identify_ctrl_kpioc));
    }
    if (off <= 359)  {
        CHECK_STOP_PARSE(359, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd2, cmd_tvb, 359-off, 1, ENC_NA);
    }
    if (off <= 360)  {
        CHECK_STOP_PARSE(360, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mptfawr, cmd_tvb, 360-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 362)  {
        CHECK_STOP_PARSE(362, 6);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd7, cmd_tvb, 362-off, 6, ENC_NA);
    }
    if (off <= 368)  {
        CHECK_STOP_PARSE(368, 16);
        ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_megcap, cmd_tvb, 368-off, 16, ENC_NA);
        post_add_bytes_from_16bytes(ti, cmd_tvb, 368-off, 0);
    }
    if (off <= 384)  {
        CHECK_STOP_PARSE(384, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 384-off, 1, ASPEC(hf_nvme_identify_ctrl_tmpthha));
    }
    if (off <= 385)  {
        CHECK_STOP_PARSE(385, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 385-off, 1, ASPEC(hf_nvme_identify_ctrl_mupa));
    }
    if (off <= 386)  {
        CHECK_STOP_PARSE(386, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cqt, cmd_tvb, 386-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 388)  {
        CHECK_STOP_PARSE(388, 2);
        add_group_mask_entry(cmd_tvb, cmd_tree, 388-off, 2, ASPEC(hf_nvme_identify_ctrl_cdpa));
    }
    if (off <= 390)  {
        CHECK_STOP_PARSE(390, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mup, cmd_tvb, 390-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 392)  {
        CHECK_STOP_PARSE(392, 2);
        add_group_mask_entry(cmd_tvb, cmd_tree, 392-off, 2, ASPEC(hf_nvme_identify_ctrl_ipmsr));
    }
    if (off <= 394)  {
        CHECK_STOP_PARSE(394, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_msmt, cmd_tvb, 394-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 396)  {
        CHECK_STOP_PARSE(396, 116);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd8, cmd_tvb, 396-off, 116, ENC_NA);
    }
    if (off <= 512)  {
        CHECK_STOP_PARSE(512, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 512-off, 1, ASPEC(hf_nvme_identify_ctrl_sqes));
    }
    if (off <= 513)  {
        CHECK_STOP_PARSE(513, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 513-off, 1, ASPEC(hf_nvme_identify_ctrl_cqes));
    }

    if (off <= 514)  {
        CHECK_STOP_PARSE(514, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_maxcmd, cmd_tvb, 514-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 516)  {
        CHECK_STOP_PARSE(516, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nn, cmd_tvb, 516-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 520)  {
        CHECK_STOP_PARSE(520, 2);
        add_group_mask_entry(cmd_tvb, cmd_tree, 520-off, 2, ASPEC(hf_nvme_identify_ctrl_oncs));
    }

    if (off <= 522)  {
        CHECK_STOP_PARSE(522, 2);
        add_group_mask_entry(cmd_tvb, cmd_tree, 522-off, 2, ASPEC(hf_nvme_identify_ctrl_fuses));
    }
    if (off <= 524)  {
        CHECK_STOP_PARSE(524, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 524-off, 1, ASPEC(hf_nvme_identify_ctrl_fna));
    }
    if (off <= 525)  {
        CHECK_STOP_PARSE(525, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 525-off, 1, ASPEC(hf_nvme_identify_ctrl_vwc));
    }

    if (off <= 526)  {
        CHECK_STOP_PARSE(526, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_awun, cmd_tvb, 526-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 528)  {
        CHECK_STOP_PARSE(528, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_awupf, cmd_tvb, 528-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 530)  {
        CHECK_STOP_PARSE(530, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 530-off, 1, ASPEC(hf_nvme_identify_ctrl_nvscc));
    }

    if (off <= 531)  {
        CHECK_STOP_PARSE(531, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 531-off, 1, ASPEC(hf_nvme_identify_ctrl_nwpc));
    }
    if (off <= 532)  {
        CHECK_STOP_PARSE(532, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_acwu, cmd_tvb, 532-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 534)  {
        CHECK_STOP_PARSE(534, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd3, cmd_tvb, 534-off, 2, ENC_NA);
    }

    if (off <= 536)  {
        CHECK_STOP_PARSE(536, 4);
        add_group_mask_entry(cmd_tvb, cmd_tree, 536-off, 4, ASPEC(hf_nvme_identify_ctrl_sgls));
    }
    if (off <= 540)  {
        CHECK_STOP_PARSE(540, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mnan, cmd_tvb, 540-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 544)  {
        CHECK_STOP_PARSE(544, 16);
        ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_maxdna, cmd_tvb, 544-off, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, 544-off);
    }
    if (off <= 560)  {
        CHECK_STOP_PARSE(560, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_maxcna, cmd_tvb, 560-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 564)  {
        CHECK_STOP_PARSE(564, 4);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_oaqd, cmd_tvb, 564-off, 4, ENC_LITTLE_ENDIAN);
    }
    if (off <= 568)  {
        CHECK_STOP_PARSE(568, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rhiri, cmd_tvb, 568-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 569)  {
        CHECK_STOP_PARSE(569, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hirt, cmd_tvb, 569-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 570)  {
        CHECK_STOP_PARSE(570, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cmmrtd, cmd_tvb, 570-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 572)  {
        CHECK_STOP_PARSE(572, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nmmrtd, cmd_tvb, 572-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 574)  {
        CHECK_STOP_PARSE(574, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_minmrtg, cmd_tvb, 574-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 575)  {
        CHECK_STOP_PARSE(575, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_maxmrtg, cmd_tvb, 575-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 576)  {
        CHECK_STOP_PARSE(576, 1);
        add_group_mask_entry(cmd_tvb, cmd_tree, 576-off, 1, ASPEC(hf_nvme_identify_ctrl_trattr));
    }
    if (off <= 577)  {
        CHECK_STOP_PARSE(577, 1);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd4, cmd_tvb, 577-off, 1, ENC_NA);
    }
    if (off <= 578)  {
        CHECK_STOP_PARSE(578, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mcudmq, cmd_tvb, 578-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 580)  {
        CHECK_STOP_PARSE(580, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mnsudmq, cmd_tvb, 580-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 582)  {
        CHECK_STOP_PARSE(582, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mcmr, cmd_tvb, 582-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 584)  {
        CHECK_STOP_PARSE(584, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nmcmr, cmd_tvb, 584-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 586)  {
        CHECK_STOP_PARSE(586, 2);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mcdqpc, cmd_tvb, 586-off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 588)  {
        CHECK_STOP_PARSE(588, 180);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd9, cmd_tvb, 588-off, 180, ENC_NA);
    }

    if (off <= 768)  {
        CHECK_STOP_PARSE(768, 256);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_subnqn, cmd_tvb, 768-off, 256, ENC_ASCII);
    }
    if (off <= 1024)  {
        CHECK_STOP_PARSE(1024, 768);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd5, cmd_tvb, 1024-off, 768, ENC_NA);
    }
    if (off <= 1792)  {
        CHECK_STOP_PARSE(1792, 256);
        dissect_nvme_identify_ctrl_resp_nvmeof(cmd_tvb, cmd_tree, off);
    }

    if (off <= 2048)  {
        CHECK_STOP_PARSE(2048, 1024);
        dissect_nvme_identify_ctrl_resp_power_state_descriptors(cmd_tvb, cmd_tree, off);
    }

    if (off <= 3072)  {
        CHECK_STOP_PARSE(3072, 1024);
        proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_vs, cmd_tvb, 3072-off, 1024, ENC_NA);
    }
}

static void dissect_nvme_identify_resp(tvbuff_t *cmd_tvb, packet_info *pinfo, proto_tree *cmd_tree,
                                       struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
{
    switch(cmd_ctx->cmd_ctx.cmd_identify.cns) {
    case NVME_IDENTIFY_CNS_IDENTIFY_NS:
    case NVME_IDENTIFY_CNS_NS_ALLOC:        /* same Identify Namespace structure */
        dissect_nvme_identify_ns_resp(cmd_tvb, pinfo, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_IDENTIFY_CTRL:
        dissect_nvme_identify_ctrl_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_IDENTIFY_NSLIST:
    case NVME_IDENTIFY_CNS_NS_ALLOC_LIST:   /* same Namespace ID list structure */
        dissect_nvme_identify_nslist_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_NSID_DESC_LIST:
        dissect_nvme_identify_nsid_desc_list_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_NVM_SET_LIST:
        dissect_nvme_identify_nvmset_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_CS_IND_NS:
        dissect_nvme_identify_cs_ind_ns_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_CTRL_LIST_NS:
    case NVME_IDENTIFY_CNS_CTRL_LIST:       /* same Controller List structure */
        dissect_nvme_identify_ctrl_list_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_PRI_CTRL_CAP:
        dissect_nvme_identify_pri_ctrl_cap_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_SEC_CTRL_LIST:
        dissect_nvme_identify_sec_ctrl_list_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_NS_GRAN_LIST:
        dissect_nvme_identify_ns_gran_list_resp(cmd_tvb, cmd_tree, off, len);
        break;
    case NVME_IDENTIFY_CNS_UUID_LIST:
        dissect_nvme_identify_uuid_list_resp(cmd_tvb, cmd_tree, off, len);
        break;
    default:
        break;
    }
}

static void dissect_nvme_identify_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_identify_dword10));
    add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_identify_dword11));

    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);

    add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_identify_dword14));

    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

/* Log Page Identifiers (NVMe Base 2.3 "Get Log Page – Log Page
 * Identifiers").  LID 0Eh is defined by the
 * NVM Command Set Specification (LBA Status Information). */
typedef enum {
    NVME_LID_SUPPORTED_LOG_PAGES        = 0x00,
    NVME_LID_ERROR_INFO                 = 0x01,
    NVME_LID_SMART                      = 0x02,
    NVME_LID_FW_SLOT                    = 0x03,
    NVME_LID_CHANGED_NSLIST             = 0x04,
    NVME_LID_CMD_SUP_AND_EFF            = 0x05,
    NVME_LID_DEVICE_SELF_TEST           = 0x06,
    NVME_LID_TELEMETRY_HOST             = 0x07,
    NVME_LID_TELEMETRY_CTRL             = 0x08,
    NVME_LID_ENDURANCE_GROUP            = 0x09,
    NVME_LID_PRED_LAT_NVM_SET           = 0x0A,
    NVME_LID_PRED_LAT_EVENT_AGG         = 0x0B,
    NVME_LID_ANA                        = 0x0C,
    NVME_LID_PERSISTENT_EVENT           = 0x0D,
    NVME_LID_LBA_STATUS                 = 0x0E,
    NVME_LID_ENDURANCE_GROUP_EVENT_AGG  = 0x0F,
    NVME_LID_MEDIA_UNIT_STATUS          = 0x10,
    NVME_LID_SUP_CAP_CONFIG_LIST        = 0x11,
    NVME_LID_FEATURE_ID_SUP_AND_EFF     = 0x12,
    NVME_LID_NVME_MI_CMD_SUP_AND_EFF    = 0x13,
    NVME_LID_CMD_FEAT_LOCKDOWN          = 0x14,
    NVME_LID_BOOT_PARTITION             = 0x15,
    NVME_LID_ROTATIONAL_MEDIA           = 0x16,
    NVME_LID_DISPERSED_NS               = 0x17,
    NVME_LID_MGMT_ADDR_LIST             = 0x18,
    NVME_LID_PHY_RX_EOM                 = 0x19,
    NVME_LID_REACHABILITY_GROUPS        = 0x1A,
    NVME_LID_REACHABILITY_ASSOC         = 0x1B,
    NVME_LID_CHANGED_ALLOC_NSLIST       = 0x1C,
    NVME_LID_DEVICE_PERSONALITIES       = 0x1D,
    NVME_LID_CROSS_CTRL_RESET           = 0x1E,
    NVME_LID_LOST_HOST_COMM             = 0x1F,
    NVME_LID_FDP_CONFIGS                = 0x20,
    NVME_LID_RECLAIM_UNIT_HANDLE_USAGE  = 0x21,
    NVME_LID_FDP_STATS                  = 0x22,
    NVME_LID_FDP_EVENTS                 = 0x23,
    NVME_LID_POWER_MEASUREMENT          = 0x25,
    NVME_LID_DISCOVERY                  = 0x70,
    NVME_LID_HOST_DISCOVERY             = 0x71,
    NVME_LID_AVE_DISCOVERY              = 0x72,
    NVME_LID_PULL_MODEL_DDC_REQ         = 0x73,
    NVME_LID_SANITIZE_NS_STATUS_LIST    = 0x7F,
    NVME_LID_RESERVATION_NOTIFICATION   = 0x80,
    NVME_LID_SANITIZE_STATUS            = 0x81,
} nvme_logpage_lid_t;

static const value_string logpage_tbl[] = {
    { NVME_LID_SUPPORTED_LOG_PAGES, "Supported Log Pages" },
    { NVME_LID_ERROR_INFO, "Error Information" },
    { NVME_LID_SMART, "SMART/Health Information" },
    { NVME_LID_FW_SLOT, "Firmware Slot Information" },
    { NVME_LID_CHANGED_NSLIST, "Changed Attached Namespace List" },
    { NVME_LID_CMD_SUP_AND_EFF, "Commands Supported and Effects" },
    { NVME_LID_DEVICE_SELF_TEST, "Device Self-test" },
    { NVME_LID_TELEMETRY_HOST, "Telemetry Host-Initiated" },
    { NVME_LID_TELEMETRY_CTRL, "Telemetry Controller-Initiated" },
    { NVME_LID_ENDURANCE_GROUP, "Endurance Group Information" },
    { NVME_LID_PRED_LAT_NVM_SET, "Predictable Latency Per NVM Set" },
    { NVME_LID_PRED_LAT_EVENT_AGG, "Predictable Latency Event Aggregate" },
    { NVME_LID_ANA, "Asymmetric Namespace Access" },
    { NVME_LID_PERSISTENT_EVENT, "Persistent Event Log" },
    { NVME_LID_LBA_STATUS, "LBA Status Information" },
    { NVME_LID_ENDURANCE_GROUP_EVENT_AGG, "Endurance Group Event Aggregate" },
    { NVME_LID_MEDIA_UNIT_STATUS, "Media Unit Status" },
    { NVME_LID_SUP_CAP_CONFIG_LIST, "Supported Capacity Configuration List" },
    { NVME_LID_FEATURE_ID_SUP_AND_EFF, "Feature Identifiers Supported and Effects" },
    { NVME_LID_NVME_MI_CMD_SUP_AND_EFF, "NVMe-MI Commands Supported and Effects" },
    { NVME_LID_CMD_FEAT_LOCKDOWN, "Command and Feature Lockdown" },
    { NVME_LID_BOOT_PARTITION, "Boot Partition" },
    { NVME_LID_ROTATIONAL_MEDIA, "Rotational Media Information" },
    { NVME_LID_DISPERSED_NS, "Dispersed Namespace Participating NVM Subsystems" },
    { NVME_LID_MGMT_ADDR_LIST, "Management Address List" },
    { NVME_LID_PHY_RX_EOM, "Physical Interface Receiver Eye Opening Measurement" },
    { NVME_LID_REACHABILITY_GROUPS, "Reachability Groups" },
    { NVME_LID_REACHABILITY_ASSOC, "Reachability Associations" },
    { NVME_LID_CHANGED_ALLOC_NSLIST, "Changed Allocated Namespace List" },
    { NVME_LID_DEVICE_PERSONALITIES, "Device Personalities" },
    { NVME_LID_CROSS_CTRL_RESET, "Cross-Controller Reset" },
    { NVME_LID_LOST_HOST_COMM, "Lost Host Communication" },
    { NVME_LID_FDP_CONFIGS, "FDP Configurations" },
    { NVME_LID_RECLAIM_UNIT_HANDLE_USAGE, "Reclaim Unit Handle Usage" },
    { NVME_LID_FDP_STATS, "FDP Statistics" },
    { NVME_LID_FDP_EVENTS, "FDP Events" },
    { NVME_LID_POWER_MEASUREMENT, "Power Measurement" },
    { NVME_LID_DISCOVERY, "Discovery" },
    { NVME_LID_HOST_DISCOVERY, "Host Discovery" },
    { NVME_LID_AVE_DISCOVERY, "AVE Discovery" },
    { NVME_LID_PULL_MODEL_DDC_REQ, "Pull Model DDC Request" },
    { NVME_LID_SANITIZE_NS_STATUS_LIST, "Sanitize Namespace Status List" },
    { NVME_LID_RESERVATION_NOTIFICATION, "Reservation Notification" },
    { NVME_LID_SANITIZE_STATUS, "Sanitize Status" },
    { 0, NULL }
};

static const char *get_logpage_name(unsigned lid)
{
    if (lid >= 0x82 && lid <= 0xBE)
        return "I/O Command Set Specific";
    else if (lid == 0xBF)
        return "Zoned Namespace Command Set";
    else if (lid >= 0xC0)
        return "Vendor Specific";
    else
        return val_to_str_const(lid, logpage_tbl, "Reserved");
}

static void add_logpage_lid(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "%s (0x%x)", get_logpage_name(val), val);
}

static const value_string sec_type_tbl[] = {
    { 0, "No security" },
    { 1, "Transport Layer Security (TLS) version >= 1.2" },
    { 0, NULL }
};

static void dissect_nvme_get_logpage_ify_rcrd_tsas_tcp(tvbuff_t *cmd_tvb, proto_item *ti, unsigned off)
{
    proto_tree *grp =  proto_item_add_subtree(ti, ett_data);
    proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_tcp_sectype, cmd_tvb, off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_tcp_rsvd, cmd_tvb, off+1, 255, ENC_NA);
}

static const value_string qp_type_tbl[] = {
    { 1, "Reliable Connected" },
    { 2, "Reliable Datagram" },
    { 0, NULL }
};

static const value_string pr_type_tbl[] = {
    { 1, "No provider specified" },
    { 2, "InfiniBand" },
    { 3, "RoCE (v1)" },
    { 4, "RoCE (v2)" },
    { 5, "iWARP" },
    { 0, NULL }
};

static const value_string cms_type_tbl[] = {
    { 1, "RDMA_IP_CM" },
    { 0, NULL }
};

static void dissect_nvme_get_logpage_ify_rcrd_tsas_rdma(tvbuff_t *cmd_tvb, proto_item *ti, unsigned off)
{
    proto_tree *grp;

    grp =  proto_item_add_subtree(ti, ett_data);
    proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_qptype, cmd_tvb, off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_prtype, cmd_tvb, off+1, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_cms, cmd_tvb, off+2, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd0, cmd_tvb, off+3, 5, ENC_NA);
    proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_pkey, cmd_tvb, off+8, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd1, cmd_tvb, off+10, 246, ENC_NA);
}

static const value_string trt_type_tbl[] = {
    { 0, "Reserved" },
    { 1, "RDMA Transport" },
    { 2, "Fibre Channel Transport" },
    { 3, "TCP Transport" },
    { 254, "Intra-host Transport" },
    { 0, NULL }
};

static const value_string adrfam_type_tbl[] = {
    { 0, "Reserved" },
    { 1, "AF_INET" },
    { 2, "AF_INET6" },
    { 3, "AF_IB" },
    { 4, "Fibre Channel" },
    { 254, "Intra-Host" },
    { 0, NULL }
};

/* Command Set Identifiers, NVMe Base 2.3 Figure 327 */
static const value_string csi_tbl[] = {
    { 0x00, "NVM Command Set" },
    { 0x01, "Key Value Command Set" },
    { 0x02, "Zoned Namespace Command Set" },
    { 0x03, "Subsystem Local Memory Command Set" },
    { 0x04, "Computational Programs Command Set" },
    { 0, NULL }
};

static const value_string sub_type_tbl[] = {
    { 0, "Reserved" },
    { 1, "Referral to another Discovery Subsystem" },
    { 2, "NVM subsystem with IO controllers" },
    { 3, "Current Discovery Subsystem" },
    { 0, NULL }
};

/* TREQ bits 1:0, NVMe Base 2.3 Figure 310 */
static const value_string treq_tsc_tbl[] = {
    { 0, "Not specified" },
    { 1, "Required" },
    { 2, "Not required" },
    { 3, "Reserved" },
    { 0, NULL }
};

/* TREQ bits 5:4, NVMe Base 2.3 Figure 310 */
static const value_string treq_tasc_tbl[] = {
    { 0, "Not specified" },
    { 1, "Authentication required" },
    { 2, "Authentication concatenated to secure channel establishment required" },
    { 3, "Reserved" },
    { 0, NULL }
};

static void dissect_nvme_get_logpage_ify_rcrd_resp(tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, proto_tree *tree, uint64_t rcrd, unsigned roff, int off, unsigned len)
{
    proto_item *ti;
    proto_tree *grp;
    unsigned tr_type;

    ti = proto_tree_add_bytes_format(tree, hf_nvme_get_logpage_ify_rcrd, cmd_tvb, off,
        (len < 1024) ? len : 1024, NULL, "Discovery Log Entry %"PRIu64" (DLE%"PRIu64")", rcrd, rcrd);
    grp =  proto_item_add_subtree(ti, ett_data);

    if (!roff) {
        proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_ify_rcrd_trtype, cmd_tvb, off, 1, ENC_LITTLE_ENDIAN, &tr_type);
        cmd_ctx->cmd_ctx.get_logpage.tr_type = tr_type;
    } else {
        tr_type = cmd_ctx->cmd_ctx.get_logpage.tr_type;
    }

    if (roff <= 1 && (2-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_adrfam, cmd_tvb, off-roff+1, 1, ENC_LITTLE_ENDIAN);

    if (roff <= 2 && (3-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_subtype, cmd_tvb, off-roff+2, 1, ENC_LITTLE_ENDIAN);

    if (roff <= 3 && (4-roff) <= len)
        add_group_mask_entry(cmd_tvb, grp, off-roff+3, 1, ASPEC(hf_nvme_get_logpage_ify_rcrd_treq));

    if (roff <= 4 && (6-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_portid, cmd_tvb, off-roff+4, 2, ENC_LITTLE_ENDIAN);

    if (roff <= 6 && (8-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_cntlid, cmd_tvb, off-roff+6, 2, ENC_LITTLE_ENDIAN);

    if (roff <= 8 && (10-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_asqsz, cmd_tvb, off-roff+8, 2, ENC_LITTLE_ENDIAN);

    if (roff <= 10 && (12-roff) <= len)
        add_group_mask_entry(cmd_tvb, grp, off-roff+10, 2, ASPEC(hf_nvme_get_logpage_disc_rcrd_eflags));

    if (roff <= 12 && (32-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_rsvd0, cmd_tvb, off-roff+12, 20, ENC_NA);

    if (roff <= 32 && (64-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_trsvcid, cmd_tvb, off-roff+32, 32, ENC_ASCII);

    if (roff <= 64 && (256-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_rsvd1, cmd_tvb, off-roff+64, 192, ENC_NA);

    if (roff <= 256 && (512-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_subnqn, cmd_tvb, off-roff+256, 256, ENC_ASCII);

    if (roff <= 512 && (768-roff) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_traddr, cmd_tvb, off-roff+512, 256, ENC_ASCII);

    if (roff <= 768 && (1024-roff) <= len) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas, cmd_tvb, off-roff+768, 256, ENC_NA);
        if (tr_type == 1)
            dissect_nvme_get_logpage_ify_rcrd_tsas_rdma(cmd_tvb, ti, off-roff+768);
        else if (tr_type == 3)
            dissect_nvme_get_logpage_ify_rcrd_tsas_tcp(cmd_tvb, ti, off-roff+768);
    }
}

static void dissect_nvme_get_logpage_ify_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
{
    uint64_t off = cmd_ctx->cmd_ctx.get_logpage.off + tr_off;
    proto_tree *grp;
    unsigned poff;
    unsigned roff;
    unsigned max_bytes;
    uint64_t rcrd, rcrd_ctr = 0;
    uint64_t recnum = 0;

    grp =  proto_item_add_subtree(ti, ett_data);

    if (!off && len >= 8)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_genctr, cmd_tvb, 0, 8, ENC_LITTLE_ENDIAN);

    /* unsigned casts are to silence clang-11 compile errors */
    if (off <= 8 && (16 - (unsigned)off) <= len)
        proto_tree_add_item_ret_uint64(grp, hf_nvme_get_logpage_ify_numrec, cmd_tvb, (unsigned)(8-off), 8, ENC_LITTLE_ENDIAN, &recnum);

    if (off <= 16 && (18 - (unsigned)off) <= len) {
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_recfmt, cmd_tvb, (unsigned)(16-off), 2, ENC_LITTLE_ENDIAN);
        cmd_ctx->cmd_ctx.get_logpage.records = (recnum & 0xffffffff);
    } else if (tr_off) {
        recnum = cmd_ctx->cmd_ctx.get_logpage.records;
    }

    if (off <= 18 && (1024 - (unsigned)off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rsvd, cmd_tvb, (unsigned)(18-off), 1006, ENC_NA);

    if (off <= 1024) {
        poff = (1024 - (unsigned)off); /* clang-11 is so strange, hence the cast */
        if (poff >= len)
            return;
        max_bytes = 1024;
        rcrd = 0;
        roff = 0;
        len -= poff;
    } else {
        poff = 0;
        roff = (off & 1023);
        max_bytes = 1024 - (roff);
        rcrd = (off - roff) / 1024 - 1;
    }

    max_bytes = (max_bytes <= len) ? max_bytes : len;
    dissect_nvme_get_logpage_ify_rcrd_resp(cmd_tvb, cmd_ctx, grp, rcrd, roff, poff, len);
    poff += max_bytes;
    len -= max_bytes;
    rcrd++;
    rcrd_ctr++;

    /* `recnum` is the total number of Discovery Log Entries, and one has just
     * been rendered unconditionally above, so `rcrd_ctr` is already 1 here.
     * When NUMREC (NVMe Base 2.3 Figure 312, bytes 15:08) was not visible in
     * this window, fall back to "one entry per remaining 1024-byte record",
     * plus the one already rendered, so the counter keeps the same meaning on
     * both paths and `len` stays the real terminator. */
    if (!recnum)
        recnum = 1 + (len  + 1023) / 1024;

    while (len && rcrd_ctr < recnum) {
        max_bytes = (len >= 1024) ? 1024 : len;
        dissect_nvme_get_logpage_ify_rcrd_resp(cmd_tvb, cmd_ctx, grp, rcrd, 0, poff, len);
        poff += max_bytes;
        len -= max_bytes;
        rcrd++;
        rcrd_ctr++;
    }
}

/* True if the field at absolute structure offset `struct_off` (width
 * `field_len`) is present in the currently-visible window [off, off+len)
 * handed to a windowed Get Log Page / Set Features decoder, and sets
 * *rel_off to its position relative to cmd_tvb (whose byte 0 is `off` into
 * the logical structure).  Centralizes the "off <= struct_off &&
 * (struct_off + field_len - off) <= len" bounds check that was previously
 * hand-duplicated across every decoder in this file -- and, for the
 * trailing/variable-length field in several of them, was computed via an
 * unguarded "len -= poff" that underflows (wrapping to a huge unsigned
 * value) whenever the window is shorter than `struct_off` implies. */
static bool
nvme_field_in_window(unsigned off, unsigned len, unsigned struct_off, unsigned field_len,
                     unsigned *rel_off)
{
    if (off > struct_off || (struct_off + field_len - off) > len)
        return false;
    *rel_off = struct_off - off;
    return true;
}

/* True if `off` (the combined LPO+transport window offset) is a multiple of
 * `rec_len`, the fixed record size of a repeating Log Page array (e.g. the
 * 4-byte-per-entry Supported Log Pages / *-Supported-and-Effects tables).
 * A compliant target should never split such a transfer mid-record, but
 * this dissector has no way to enforce that on the wire -- a non-compliant
 * device or a crafted/fuzzed capture can still hand a decoder a window that
 * starts mid-record, which would otherwise be silently spliced into a
 * bogus entry instead of being rejected. */
static bool
nvme_offset_record_aligned(unsigned off, unsigned rec_len)
{
    return (off % rec_len) == 0;
}

static void dissect_nvme_get_logpage_err_inf_resp(proto_item *ti, tvbuff_t *cmd_tvb, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned rel;

    grp =  proto_item_add_subtree(ti, ett_data);

    if (off > 63)
        return; /* max allowed offset is 63 */

    if (nvme_field_in_window(off, len, 0, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_errcnt, cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 8, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_sqid, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 10, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_cid, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 12, 2, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 2, ASPEC(hf_nvme_get_logpage_errinf_sf));
    if (nvme_field_in_window(off, len, 14, 2, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 2, ASPEC(hf_nvme_get_logpage_errinf_pel));
    if (nvme_field_in_window(off, len, 16, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_lba, cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 24, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_ns, cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 28, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_vsi, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 29, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_trtype, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    /* The spec's "CSI" here is Command Set Indicator (byte 30), but the
     * ".csi" filter name was already taken upstream in 2021 by Command
     * Specific Information (byte 32, below) and has shipped since 3.6.0, so
     * this field uses ".cmdset" rather than silently repurposing it. */
    if (nvme_field_in_window(off, len, 30, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_cmdset, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 31, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_opc, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 32, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_csi, cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 40, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_tsi, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 42, 21, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_rsvd1, cmd_tvb, rel, 21, ENC_NA);
    if (nvme_field_in_window(off, len, 63, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_lpver, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
}

static void post_add_intval_from_16bytes(proto_item *ti, tvbuff_t *tvb, unsigned off)
{
    /* The 128-bit value is little-endian on the wire: byte `off` holds the
     * low-order 64 bits and byte `off+8` holds the high-order 64 bits. */
    uint64_t lo = tvb_get_uint64(tvb, off, ENC_LITTLE_ENDIAN);
    uint64_t hi = tvb_get_uint64(tvb, off+8, ENC_LITTLE_ENDIAN);
    double res;

    res = (double)hi;
    res *= (((uint64_t)1) << 63);
    res *= 2;
    res += lo;
    if (res > 99999999)
        proto_item_append_text(ti, " (%.8le)", res);
    else
        proto_item_append_text(ti, " (%.0lf)", res);
}

static void decode_smart_resp_temps(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned off, unsigned len)
{
    proto_item *ti;
    unsigned bytes;
    unsigned poff;
    unsigned max_bytes;
    unsigned i;


    poff = (off < 200) ? 200-off : 0;

    if (off > 214 || (poff + 2) > len)
        return;

    bytes = len - poff;
    max_bytes = (off <= 200) ? 16 : (216 - off);

    if (bytes > max_bytes)
        bytes = max_bytes;

    ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ts[0],  cmd_tvb, poff, bytes, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);
    for (i = 0; i < 8; i++) {
        unsigned pos = 200 + i * 2;
        unsigned rel;
        if (nvme_field_in_window(off, len, pos, 2, &rel))
            proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ts[i+1],  cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    }
}

static void dissect_nvme_get_logpage_smart_resp(proto_item *ti, tvbuff_t *cmd_tvb, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned rel;

    if (off >= 512)
        return; /* max allowed offset is < 512 */

    grp =  proto_item_add_subtree(ti, ett_data);
    if (nvme_field_in_window(off, len, 0, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_smart_cw));
    if (nvme_field_in_window(off, len, 1, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ct,  cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 3, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_asc,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 4, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ast,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 5, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_lpu,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 6, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_smart_egcws));
    if (nvme_field_in_window(off, len, 7, 25, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_rsvd0,  cmd_tvb, rel, 25, ENC_NA);
    if (nvme_field_in_window(off, len, 32, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_dur,  cmd_tvb, rel, 16, ENC_NA);
        post_add_bytes_from_16bytes(ti, cmd_tvb, rel, 16);
    }
    if (nvme_field_in_window(off, len, 48, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_duw,  cmd_tvb, rel, 16, ENC_NA);
        post_add_bytes_from_16bytes(ti, cmd_tvb, rel, 16);
    }
    if (nvme_field_in_window(off, len, 64, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_hrc,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 80, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_hwc,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 96, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_cbt,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 112, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_pc,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 128, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_poh,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 144, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_us,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 160, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_mie,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 176, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ele,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 192, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_wctt,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 196, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_cctt,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);

    decode_smart_resp_temps(grp, cmd_tvb, off, len);

    if (off <= 216 && (220 -off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_tmt1c,  cmd_tvb, 216-off, 4, ENC_LITTLE_ENDIAN);
    if (off <= 220 && (224 -off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_tmt2c,  cmd_tvb, 220-off, 4, ENC_LITTLE_ENDIAN);
    if (off <= 224 && (228 -off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_tmt1t,  cmd_tvb, 224-off, 4, ENC_LITTLE_ENDIAN);
    if (off <= 228 && (232 -off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_smart_tmt2t,  cmd_tvb, 228-off, 4, ENC_LITTLE_ENDIAN);
    if (off < 512) {
        unsigned poff = (off < 232) ? (232 - off) : 0;
        unsigned max_len = (off <= 232) ? 280 : 512 - off;
        if (len > poff) {
            len -= poff;
            if (len > max_len)
                len = max_len;
            proto_tree_add_item(grp, hf_nvme_get_logpage_smart_rsvd1,  cmd_tvb, poff, len, ENC_NA);
        }
    }
}

static void decode_fw_slot_frs(proto_tree *grp, tvbuff_t *cmd_tvb, uint32_t off, unsigned len)
{
    proto_item *ti;
    unsigned bytes;
    unsigned poff;
    unsigned max_bytes;
    unsigned i;


    /* poff is cmd_tvb-relative (cmd_tvb byte 0 == struct byte `off`): for
     * off < 8, struct offset 8 (where the frs array starts) is still ahead
     * of the window, at tvb position (8-off); for off >= 8, the window
     * already begins inside-or-past the frs array, so the array's group
     * item starts at tvb position 0.  This previously read ": off" instead
     * of ": 0" -- dimensionally wrong (mixing a struct-absolute offset into
     * a tvb-relative position) and never reachable/tested before the
     * DOFST/LPO windowing fix, since off was always 0 here beforehand. */
    poff = (off < 8) ? 8-off : 0;

    if (off > 56 || (poff + 8) > len)
        return;

    bytes = len - poff;
    max_bytes = (off <= 8) ? 56 : (64 - off);

    if (bytes > max_bytes)
        bytes = max_bytes;

    ti = proto_tree_add_item(grp, hf_nvme_get_logpage_fw_slot_frs,  cmd_tvb, poff, bytes, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);
    for (i = 0; i < 7; i++) {
        unsigned pos = 8 + i * 8;
        unsigned rel;
        if (nvme_field_in_window(off, len, pos, 8, &rel))
            /* Base 2.3 Fig 212: "The firmware revision is indicated as an
             * ASCII string." The raw bytes remain visible in the hex dump
             * of the reassembled message if needed. */
            proto_tree_add_item(grp, hf_nvme_get_logpage_fw_slot_frs_ascii[i],  cmd_tvb, rel, 8, ENC_ASCII);
    }
}

static void dissect_nvme_get_logpage_fw_slot_resp(proto_item *ti, tvbuff_t *cmd_tvb, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned rel;

    if (off >= 512)
        return;  /* max allowed offset is < 512 */

    grp =  proto_item_add_subtree(ti, ett_data);

    if (!off && len >= 1)
        add_group_mask_entry(cmd_tvb, grp, 0, 1, ASPEC(hf_nvme_get_logpage_fw_slot_afi));
    if (nvme_field_in_window(off, len, 1, 7, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_fw_slot_rsvd0,  cmd_tvb, rel, 7, ENC_LITTLE_ENDIAN);

    decode_fw_slot_frs(grp, cmd_tvb, off, len);

    if (off < 512) {
        unsigned poff = (off < 64) ? (64 - off) : 0;
        unsigned max_len = (off <= 64) ? 448 : 512 - off;
        /* Guard before subtracting: len < poff would otherwise underflow
         * `len` (unsigned) to a huge value on a short/truncated transfer. */
        if (len > poff) {
            len -= poff;
            if (len > max_len)
                len = max_len;
            proto_tree_add_item(grp, hf_nvme_get_logpage_fw_slot_rsvd1,  cmd_tvb, poff, len, ENC_NA);
        }
    }
}

static void dissect_nvme_get_logpage_changed_nslist_resp(proto_item *ti, tvbuff_t *cmd_tvb, packet_info *pinfo, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned poff = 0;
    /* Page is 1024 four-byte entries = 4096 bytes; a nonzero window offset
     * moves where the spec-mandated 4096-byte ceiling falls relative to
     * this window, and (if 4-byte aligned) where cmd_tvb position 0 lands
     * relative to an entry boundary -- see the alignment guard below. */
    unsigned max_len = (off < 4096) ? (4096 - off) : 0;

    if (len > max_len)
        len = max_len;

    if (!nvme_offset_record_aligned(off, 4)) {
        expert_add_info(pinfo, ti, &ei_nvme_logpage_window_misaligned);
        return;
    }

    grp =  proto_item_add_subtree(ti, ett_data);
    while (len >= 4) {
        proto_tree_add_item(grp, hf_nvme_get_logpage_changed_nslist,  cmd_tvb, poff, 4, ENC_LITTLE_ENDIAN);
        len -= 4;
        poff += 4;
    }
}

static const value_string lockdown_scope_tbl[] = {
    { 0, "Admin Command Set opcodes" },
    { 2, "Feature Identifiers" },
    { 3, "Management Interface Command Set opcodes" },
    { 4, "PCIe Command Set opcodes" },
    { 0, NULL }
};

static const value_string lockdown_contents_tbl[] = {
    { 0, "Can-be-prohibited list" },
    { 1, "Currently prohibited (Admin Submission Queue)" },
    { 2, "Currently prohibited (out-of-band Management Endpoint)" },
    { 0, NULL }
};

static const value_string cmd_eff_cse_tbl[] = {
    { 0, "No command submission or execution restriction" },
    { 1, "One concurrent command per namespace" },
    { 2, "One concurrent command per system" },
    { 0, NULL}
};

static void dissect_nvme_get_logpage_cmd_sup_and_eff_grp(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned poff, unsigned nrec, unsigned fidx, bool acs)
{
    unsigned i;
    proto_item *ti;
    proto_tree *ent;
    for (i = 0; i < nrec; i++) {
        if (acs)
            ti = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_cmd_and_eff_cs, cmd_tvb, poff, 4, NULL, "Admin Command Supported %u (ACS%u)", fidx+i, fidx+i);
        else
            ti = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_cmd_and_eff_cs, cmd_tvb, poff, 4, NULL, "I/O Command Supported %u (IOCS%u)", fidx+i, fidx+i);
        ent =  proto_item_add_subtree(ti, ett_data);
        add_group_mask_entry(cmd_tvb, ent, poff, 4, ASPEC(hf_nvme_get_logpage_cmd_and_eff_cseds));
        poff += 4;
    }
}


static void dissect_nvme_get_logpage_cmd_sup_and_eff_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
{
    uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
    proto_tree *grp;
    unsigned nrec = 0;
    unsigned fidx;

    off += tr_off;
    if (cmd_ctx->cmd_ctx.get_logpage.off >= 4096)
        return; /* max allowed offset is < 4096, so we do not loose bits by casting to unsigned type */

    grp =  proto_item_add_subtree(ti, ett_data);
    if (off <= 1024 && len >= 4) {
        fidx = off / 4;
        nrec = (1024-off) / 4;
        if (nrec > (len / 4))
            nrec = len / 4;
        dissect_nvme_get_logpage_cmd_sup_and_eff_grp(grp, cmd_tvb, 0, nrec, fidx, true);
    }

    nrec = len / 4 - nrec;
    if (!nrec)
        return;
    if (nrec > 256)
        nrec = 256;

    fidx = (off > 1024) ? (off - 1024) / 4 : 0;
    off = (off < 1024) ? (1024 - off) : 0;

    dissect_nvme_get_logpage_cmd_sup_and_eff_grp(grp, cmd_tvb, off, nrec, fidx, false);
}

static const value_string stest_type_active_tbl[] = {
    { 0,  "No device self-test operation in progress" },
    { 1,  "Short device self-test operation in progress" },
    { 2,  "Extended device self-test operation in progress" },
    { 3,  "Host-Initiated Refresh operation" },
    { 0xE,  "Vendor Specific" },
    { 0, NULL}
};

static const value_string stest_result_tbl[] = {
    { 0, "Operation completed without error" },
    { 1, "Operation was aborted by a Device Self-test command" },
    { 2, "Operation was aborted by a Controller Level Reset" },
    { 3, "Operation was aborted due to a removal of a namespace from the namespace inventory" },
    { 4, "Operation was aborted due to the processing of a Format NVM command" },
    { 5, "A fatal error or unknown test error occurred while the controller was executing the device self-test operation and the operation did not complete" },
    { 6, "Operation completed with a segment that failed and the segment that failed is not known" },
    { 7, "Operation completed with one or more failed segments and the first segment that failed is indicated in the Segment Number field" },
    { 8, "Operation was aborted for unknown reason" },
    { 9, "Operation was aborted due to a sanitize operation" },
    { 0xF, "Entry not used (does not contain a test result)" },
    {  0, NULL}
};

/* DSTC of a *completed* result (Base 2.3 Figure 216), not the in-progress
 * operation status of Figure 215 that stest_type_active_tbl names. */
static const value_string stest_type_done_tbl[] = {
    { 0,  "Entry is empty" },
    { 1,  "Short device self-test operation" },
    { 2,  "Extended device self-test operation" },
    { 3,  "Host-Initiated Refresh operation" },
    { 0xE,  "Vendor Specific" },
    { 0, NULL}
};

static void dissect_nvme_get_logpage_selftest_result(proto_tree *grp, tvbuff_t *cmd_tvb, uint32_t off, unsigned tst_idx)
{
    proto_item *ti;

    /* Base 2.3 Figure 216: the Self-test Result data structure is 28 bytes
     * (23:00 plus STCT/STC/VS at 27:24), which is also the stride the caller
     * walks. */
    ti = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_selftest_res, cmd_tvb, off, 28, NULL,
                                "Latest Self-test Result Data Structure (latest %u)", tst_idx);
    grp =  proto_item_add_subtree(ti, ett_data);
    add_group_mask_entry(cmd_tvb, grp, off, 1, ASPEC(hf_nvme_get_logpage_selftest_res_status));
    proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_sn, cmd_tvb, off+1, 1, ENC_LITTLE_ENDIAN);
    add_group_mask_entry(cmd_tvb, grp, off+2, 1, ASPEC(hf_nvme_get_logpage_selftest_res_vdi));
    proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_rsvd, cmd_tvb, off+3, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_poh, cmd_tvb, off+4, 8, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_nsid, cmd_tvb, off+12, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_flba, cmd_tvb, off+16, 8, ENC_LITTLE_ENDIAN);
    add_group_mask_entry(cmd_tvb, grp, off+24, 1, ASPEC(hf_nvme_get_logpage_selftest_res_sct));
    proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_sc, cmd_tvb, off+25, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_vs, cmd_tvb, off+26, 2, ENC_LITTLE_ENDIAN);
}

static void dissect_nvme_get_logpage_selftest_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
{
    uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
    proto_tree *grp;
    unsigned tst_idx;

    off += tr_off;
    if (cmd_ctx->cmd_ctx.get_logpage.off > 536)
        return; /* max offset is <= 536, so we do not loose bits by casting to unsigned type */

    grp =  proto_item_add_subtree(ti, ett_data);

    if (!off && len >= 1)
        add_group_mask_entry(cmd_tvb, grp, 0, 1, ASPEC(hf_nvme_get_logpage_selftest_csto));
    if (off <= 1 && (2 - off) <= len)
        add_group_mask_entry(cmd_tvb, grp, 1-off, 1, ASPEC(hf_nvme_get_logpage_selftest_cstc));
    if (off <= 2 && (4 - off) <= len)
         proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_rsvd, cmd_tvb, 2-off, 2, ENC_LITTLE_ENDIAN);

    if (off <= 4) {
        unsigned skip = 4 - off;                 /* cmd_tvb pos of result 0 */
        if (len < skip)
            return;
        len -= skip;
        tst_idx = 0;
        off = skip;
    } else {
        unsigned skip;
        tst_idx = (off - 4 + 27) / 28;            /* first fully-contained result */
        skip = tst_idx * 28 - (off - 4);          /* cmd_tvb pos of result[tst_idx] */
        if (len < skip)
            return;
        len -= skip;
        off = skip;
    }
    while (len >= 28) {
        dissect_nvme_get_logpage_selftest_result(grp, cmd_tvb, off, tst_idx);
        off += 28;
        len -= 28;
        tst_idx++;
    }
}

/* NVMe Base 2.3 "Telemetry Host-Initiated Log Page" / "Telemetry
 * Controller-Initiated Log Page" (Telemetry Scope) */
static const value_string telemetry_scope_tbl[] = {
    { 0, "Not reported" },
    { 1, "Controller" },
    { 2, "NVM subsystem" },
    { 0, NULL },
};

static void dissect_nvme_get_logpage_telemetry_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
{
    uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off  & 0xffffffff; /* need unsigned type to silence clang-11 errors */
    proto_tree *grp;
    uint64_t next_block;
    uint32_t poff;
    bool host_init = (cmd_ctx->cmd_ctx.get_logpage.lid == 0x7);
    const char *pfx = host_init ? "Host-Initiated" : "Controller-Initiated";

    off += tr_off;
    /* off==0 means the window starts at the very beginning of the log page
     * (the 512-byte header), so poff must skip past it to reach data block 1.
     * Any other exact multiple of 512 means the window already starts at a
     * data block boundary, so poff must be 0, not another full 512 skip. */
    poff = (off == 0) ? 512 : (512 - (off & 0x1ff)) % 512;
    next_block = (off + poff) / 512;

    grp =  proto_item_add_subtree(ti, ett_data);


    if (poff >= len && cmd_ctx->cmd_ctx.get_logpage.off >= 384)
        return;

    if (!off && len >= 1)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_li, cmd_tvb, 0, 1, ENC_LITTLE_ENDIAN);
    if (off <= 1 && (5 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_rsvd0, cmd_tvb, 1-off, 4, ENC_LITTLE_ENDIAN);
    if (off <= 5 && (8 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_ieee, cmd_tvb, 5-off, 3, ENC_LITTLE_ENDIAN);
    if (off <= 8 && (10 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da1lb, cmd_tvb, 8-off, 2, ENC_LITTLE_ENDIAN);
    if (off <= 10 && (12 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da2lb, cmd_tvb, 10-off, 2, ENC_LITTLE_ENDIAN);
    if (off <= 12 && (14 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da3lb, cmd_tvb, 12-off, 2, ENC_LITTLE_ENDIAN);
    if (off <= 14 && (16 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_rsvd1, cmd_tvb, 14-off, 2, ENC_NA);
    if (off <= 16 && (20 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da4lb, cmd_tvb, 16-off, 4, ENC_LITTLE_ENDIAN);
    if (host_init) {
        /* Telemetry Host-Initiated Log Page: bytes 379:20 reserved, 380 THS,
         * 381 THDGN */
        if (off <= 20 && (380 - off) <= len)
            proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_rsvd2, cmd_tvb, 20-off, 360, ENC_NA);
        if (off <= 380 && (381 - off) <= len)
            proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_scope, cmd_tvb, 380-off, 1, ENC_LITTLE_ENDIAN);
        if (off <= 381 && (382 - off) <= len)
            proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_hdgn, cmd_tvb, 381-off, 1, ENC_LITTLE_ENDIAN);
    } else {
        /* Telemetry Controller-Initiated Log Page: bytes 380:20 reserved,
         * 381 TCS */
        if (off <= 20 && (381 - off) <= len)
            proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_rsvd2, cmd_tvb, 20-off, 361, ENC_NA);
        if (off <= 381 && (382 - off) <= len)
            proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_scope, cmd_tvb, 381-off, 1, ENC_LITTLE_ENDIAN);
    }
    if (off <= 382 && (383 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da, cmd_tvb, 382-off, 1, ENC_LITTLE_ENDIAN);
    if (off <= 383 && (384 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_dgn, cmd_tvb, 383-off, 1, ENC_LITTLE_ENDIAN);
    if (off <= 384 && (512 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_ri, cmd_tvb, 384-off, 128, ENC_NA);

    if (len < poff)
        return;
    len -= poff;
    while (len >= 512) {
         proto_tree_add_bytes_format_value(grp, hf_nvme_get_logpage_telemetry_db, cmd_tvb, poff, 512, NULL,
                                           "Telemetry %s data block %"PRIu64, pfx, next_block);
        len -= 512;
        next_block++;
        poff += 512;
    }
}

static void dissect_nvme_get_logpage_egroup_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned rel;

    /* Figure 222 carries no Endurance Group Identifier: the subject of the log
     * page is named only by the Log Specific Identifier of the request
     * (NVMe Base 2.3 section 5.2.12.1.9 and Figure 221), so without this the
     * responses for two Endurance Groups are indistinguishable in the tree.
     * No "was the request seen" guard is needed: the caller selects this
     * decoder on the stored LID, which is 0h when the request was not seen,
     * so reaching here means the request supplied both LID and LSI. */
    proto_item_append_text(ti, ", Endurance Group %u", cmd_ctx->cmd_ctx.get_logpage.lsi);

    if (off >= 512)
        return; /* max allowed offset is < 512 */

    grp =  proto_item_add_subtree(ti, ett_data);
    if (nvme_field_in_window(off, len, 0, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_egroup_cw));
    if (nvme_field_in_window(off, len, 1, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_egroup_egfeat));
    if (nvme_field_in_window(off, len, 2, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_rsvd0,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 3, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_as,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 4, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_ast,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 5, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_pu,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 6, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_did,  cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 8, 24, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_rsvd1,  cmd_tvb, rel, 24, ENC_NA);
    if (nvme_field_in_window(off, len, 32, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_ee,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 48, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_dur,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 64, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_duw,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 80, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_muw,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 96, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_hrc,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 112, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_hwc,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 128, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_mdie,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 144, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_ele,  cmd_tvb, rel, 16, ENC_NA);
        post_add_intval_from_16bytes(ti, cmd_tvb, rel);
    }
    if (nvme_field_in_window(off, len, 160, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_tegcap,  cmd_tvb, rel, 16, ENC_NA);
        post_add_bytes_from_16bytes(ti, cmd_tvb, rel, 0);
    }
    if (nvme_field_in_window(off, len, 176, 16, &rel)) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_uegcap,  cmd_tvb, rel, 16, ENC_NA);
        post_add_bytes_from_16bytes(ti, cmd_tvb, rel, 0);
    }
    if (off <= 508 && (512 - off) <= len) {
        unsigned poff = (off <= 192) ? (192 - off) : 0;
        /* poff isn't derived from (512-off), so the guard above doesn't by
         * itself guarantee poff <= len -- check explicitly before subtracting. */
        if (poff <= len) {
            /* Remaining room at tvb position poff is (512-off)-poff, not the
             * raw len -- an oversized/malformed len must not render bytes
             * past the structure's real 512-byte end as "Reserved2". */
            unsigned max_len = (512 - off) - poff;
            unsigned rlen = len - poff;
            if (rlen > max_len)
                rlen = max_len;
            proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_rsvd2,  cmd_tvb, poff, rlen, ENC_NA);
        }
    }
}
static const value_string plat_status_tbl[] = {
    { 0,  "Predictable Latency Mode not Enabled" },
    { 1,  "Deterministic Window (DTWIN)" },
    { 2,  "Non-Deterministic Window (NDWIN)" },
    { 0, NULL}
};

static void dissect_nvme_get_logpage_pred_lat_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned poff;
    unsigned rel;

    /* As for the Endurance Group log page above: Figure 224 does not echo the
     * NVM Set Identifier, which is carried only in the Log Specific Identifier
     * of the request (NVMe Base 2.3 section 5.2.12.1.11 and Figure 223).
     * There is one such log page per NVM Set, so the label is what tells them
     * apart. */
    proto_item_append_text(ti, ", NVM Set %u", cmd_ctx->cmd_ctx.get_logpage.lsi);

    if (off > 508)
        return; /* max allowed offset is < 508 */

    grp =  proto_item_add_subtree(ti, ett_data);
    if (nvme_field_in_window(off, len, 0, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_pred_lat_status));
    if (nvme_field_in_window(off, len, 1, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_rsvd0,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 2, 2, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 2, ASPEC(hf_nvme_get_logpage_pred_lat_etype));
    if (nvme_field_in_window(off, len, 4, 28, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_rsvd1,  cmd_tvb, rel, 28, ENC_NA);
    if (nvme_field_in_window(off, len, 32, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_rt,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 40, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_wt,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 48, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_tm,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 56, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_ndwin_tmh,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 64, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_ndwin_tml,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 72, 56, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_rsvd2,  cmd_tvb, rel, 56, ENC_NA);
    if (nvme_field_in_window(off, len, 128, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_re,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 136, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_we,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 144, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_te,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    poff = (off <= 152) ? (152 - off) : 0;
    if (poff > len)
        return;
    {
        /* Remaining room at tvb position poff is (512-off)-poff, not the
         * raw len -- an oversized/malformed len must not render bytes past
         * the structure's real 512-byte end as "Reserved3". */
        unsigned max_len = (512 - off) - poff;
        unsigned rlen = len - poff;
        if (rlen > max_len)
            rlen = max_len;
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_rsvd3,  cmd_tvb, poff, rlen, ENC_NA);
    }
}

static void dissect_nvme_get_logpage_pred_lat_aggreg_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
{
    uint64_t off = cmd_ctx->cmd_ctx.get_logpage.off;
    proto_tree *grp;
    unsigned poff;

    off += tr_off;
    if (off < 8) {
        poff = (unsigned)(off & 0x7);
        poff = 8 - poff;
    } else {
        poff = 0;
    }
    if (len < (poff + 2) && off)
        return; /* nothing to display */

    grp =  proto_item_add_subtree(ti, ett_data);
    if (!off && len >= 8)
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_aggreg_ne,  cmd_tvb, 0, 8, ENC_LITTLE_ENDIAN);
    if (len < poff)
        return;
    len -= poff;
    while (len >= 2) {
        proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_aggreg_nset,  cmd_tvb, poff, 2, ENC_LITTLE_ENDIAN);
        poff += 2;
        len -= 2;
    }
}

static const value_string ana_state_tbl[] = {
    { 0x1,  "ANA Optimized State" },
    { 0x2,  "ANA Non-Optimized State" },
    { 0x3,  "ANA Inaccessible State" },
    { 0x4,  "ANA Persistent Loss State" },
    { 0xF,  "ANA Change State" },
    { 0, NULL}
};

static unsigned dissect_nvme_get_logpage_ana_resp_grp(proto_tree *grp, tvbuff_t *cmd_tvb,  struct nvme_cmd_ctx *cmd_ctx, unsigned len, uint32_t poff)
{
    unsigned done = 0;
    unsigned bytes;
    proto_item *ti;
    unsigned group_id;
    unsigned nns;
    unsigned prev_off = cmd_ctx->cmd_ctx.get_logpage.tr_off;

    if (len < 4) {
        if (prev_off)
            cmd_ctx->cmd_ctx.get_logpage.tr_off += len;
        return 0;
    }

    if (prev_off <= 4) {
        if ((len + prev_off) < 8) {
            /* The entry guard above only proves the 4-byte ANA Group ID is
             * present.  Number of NSID Values (NVMe Base 2.3 Figure 228,
             * bytes 07:04) needs 4 more, so a window holding 4..7 bytes of a
             * fresh descriptor cannot be read for it -- reading anyway threw
             * a bounds exception and rendered the whole frame malformed
             * instead of decoding the Group ID that did arrive. */
            nns = 0;
            bytes = len;
        } else {
            nns = tvb_get_uint32(cmd_tvb, poff+4-prev_off, ENC_LITTLE_ENDIAN);
            bytes = 32 + 4 * nns;
            cmd_ctx->cmd_ctx.get_logpage.tr_sub_entries = nns;
        }
    } else if (prev_off ) {
        nns = cmd_ctx->cmd_ctx.get_logpage.tr_sub_entries;
        bytes = (prev_off > 32) ? 4 * nns : ((32-prev_off) + 4 * nns);
    } else {
        bytes = len;
    }

    if (bytes > len)
            bytes = len;

    ti = proto_tree_add_bytes_format_value(grp, hf_nvme_get_logpage_ana_grp, cmd_tvb, poff, bytes, NULL,
            "ANA Group Descriptor");
    grp =  proto_item_add_subtree(ti, ett_data);

    if (prev_off) {
        group_id = cmd_ctx->cmd_ctx.get_logpage.tr_rcrd_id;
        proto_item_append_text(ti, " %u (continued)", group_id);
    } else {
        proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_ana_grp_id,  cmd_tvb, poff, 4, ENC_LITTLE_ENDIAN, &group_id);
        done += 4;
        proto_item_append_text(ti, " %u", group_id);
        cmd_ctx->cmd_ctx.get_logpage.tr_rcrd_id = group_id;
    }

    if (prev_off <= 4) {
        if ((len - done) < 4) {
            cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
            return done;
        }
        proto_tree_add_item(grp, hf_nvme_get_logpage_ana_grp_nns,  cmd_tvb, poff+4-prev_off, 4, ENC_LITTLE_ENDIAN);
        done += 4;
    }
    if (prev_off <= 8) {
        if ((len - done) < 8) {
            cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
            return done;
        }
        proto_tree_add_item(grp, hf_nvme_get_logpage_ana_grp_chcnt,  cmd_tvb, poff+8-prev_off, 8, ENC_LITTLE_ENDIAN);
        done += 8;
    }

    if (prev_off <= 16) {
        if ((len - done) < 1) {
            cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
            return done;
        }
        add_group_mask_entry(cmd_tvb, grp, poff+16-prev_off, 1, ASPEC(hf_nvme_get_logpage_ana_grp_anas));
        done += 1;
    }

    if (prev_off <= 17) {
        if ((len - done) < 15) {
            cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
            return done;
        }
        proto_tree_add_item(grp, hf_nvme_get_logpage_ana_grp_rsvd,  cmd_tvb, poff+17-prev_off, 15, ENC_NA);
        done += 15;
    }

    poff += done;
    while ((len - done) >= 4 && nns) {
        proto_tree_add_item(grp, hf_nvme_get_logpage_ana_grp_nsid,  cmd_tvb, poff, 4, ENC_LITTLE_ENDIAN);
        poff += 4;
        done += 4;
        nns--;
    }
    if (nns) {
        cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
        cmd_ctx->cmd_ctx.get_logpage.tr_sub_entries = nns;
    } else {
        cmd_ctx->cmd_ctx.get_logpage.tr_off = 0;
        cmd_ctx->cmd_ctx.get_logpage.tr_sub_entries = 0;
        cmd_ctx->cmd_ctx.get_logpage.tr_rcrd_id = 0;
        cmd_ctx->cmd_ctx.get_logpage.records--;
    }
    return done;
}

static unsigned dissect_nvme_get_logpage_ana_resp_header(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned len, uint32_t off)
{
    unsigned groups=1;
    if (!off && len >= 8)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ana_chcnt,  cmd_tvb, off, 8, ENC_LITTLE_ENDIAN);
    if (off <= 8 && (10 - off) <= len)
        proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_ana_ngd,  cmd_tvb, 8-off, 2, ENC_LITTLE_ENDIAN, &groups);
    if (off <= 10 && (16 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_ana_rsvd,  cmd_tvb, 10-off, 6, ENC_LITTLE_ENDIAN);
    return groups;
}

static void dissect_nvme_get_logpage_ana_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
{
    uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
    proto_tree *grp;
    unsigned poff = 0;
    unsigned groups = 1;

    grp =  proto_item_add_subtree(ti, ett_data);
    if (cmd_ctx->cmd_ctx.get_logpage.off < 16 && !tr_off) {
        groups = dissect_nvme_get_logpage_ana_resp_header(grp, cmd_tvb, len, off);
        cmd_ctx->cmd_ctx.get_logpage.records = groups;
        poff = 16 - off;
    } else if (tr_off) {
        uint32_t combined = off + tr_off;
        groups = cmd_ctx->cmd_ctx.get_logpage.records;
        /* A continuation chunk can still start inside the 16-byte header
         * (e.g. off < 16 too, just split across more than one message) --
         * skip only the remaining header bytes, not the whole thing. */
        poff = (combined < 16) ? (16 - combined) : 0;
        /* NAGD (NVMe Base 2.3 Figure 227, bytes 09:08) lives in the 16-byte
         * header, so a window that starts past it never supplies `records`.
         * Over NVMe-MI that is every window, including the first: each
         * transaction gets a freshly wmem_alloc0'd cmd_ctx, so `records` is 0
         * and the walk below never ran at all.  NVMe-MI 2.1 Figure 136 caps
         * DLEN at 4,096, so any ANA log page larger than that must be fetched
         * with successive nonzero DOFST -- the normal path, not an edge case.
         * Fall back to walking until the window is exhausted, the way
         * dissect_nvme_get_logpage_ify_resp() does for NUMREC.  An ANA Group
         * Descriptor is at least 32 bytes (Figure 228: 31:00 header, then the
         * NSID list), so (len + 31) / 32 can never stop the walk early. */
        if (!groups)
            groups = (len + 31) / 32;
    } else {
        /* off >= 16 with tr_off == 0: the Get Log Page command's own Log Page
         * Offset already starts this window past the 16-byte header, so NAGD
         * is not in this message either and neither branch above ran --
         * `groups` kept its initializer of 1 and exactly one descriptor
         * rendered no matter how many the window held.  Same bound and same
         * justification as the tr_off path. */
        groups = cmd_ctx->cmd_ctx.get_logpage.records;
        if (!groups)
            groups = (len + 31) / 32;
    }
    if (len < poff)
        return;
    len -= poff;
    while (len >= 4 && groups) {
        unsigned done = dissect_nvme_get_logpage_ana_resp_grp(grp, cmd_tvb, cmd_ctx, len, poff);
        /* A descriptor continuation that cannot make progress (the window
         * holds fewer bytes than its next field needs) returns 0.  Without
         * this the loop would keep re-rendering empty descriptor items until
         * `groups` ran out -- harmless while `groups` was always the wire's
         * NAGD, but not with the bound above. */
        if (!done)
            break;
        poff += done;
        len -= done;
        groups--;
    }
}

static void dissect_nvme_get_logpage_lba_status_resp_header(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned len, uint32_t off)
{
    if (!off && len >= 4)
        proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_lslplen,  cmd_tvb, off, 4, ENC_LITTLE_ENDIAN);
    if (off <= 4 && (8 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nlslne,  cmd_tvb, 4-off, 4, ENC_LITTLE_ENDIAN);
    if (off <= 8 && (12 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_estulb,  cmd_tvb, 8-off, 4, ENC_LITTLE_ENDIAN);
    if (off <= 12 && (14 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_rsvd,  cmd_tvb, 12-off, 2, ENC_LITTLE_ENDIAN);
    if (off <= 14 && (16 - off) <= len)
        proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_lsgc,  cmd_tvb, 14-off, 2, ENC_LITTLE_ENDIAN);
    /* The Namespace Element List item is added by the caller, over the same
     * byte range; adding it here as well made the field match twice per
     * frame. */
}

static unsigned dissect_nvme_get_logpage_lba_status_lba_range(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned len, uint32_t poff)
{
    uint32_t nlrd = 0;
    uint64_t slen64;
    unsigned slen, rem;
    proto_item *ti;
    proto_tree *rd;

    ti = proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne,  cmd_tvb, poff, (len < 16) ? len : 16, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);

    if (len >= 4)
        proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_neid,  cmd_tvb, poff, 4, ENC_LITTLE_ENDIAN);
    if (len >= 8)
        proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_lba_status_nel_ne_nlrd,  cmd_tvb, poff+4, 4, ENC_LITTLE_ENDIAN, &nlrd);
    if (len >= 9)
        proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_ratype,  cmd_tvb, poff+8, 1, ENC_LITTLE_ENDIAN);
    if (len >= 16)
        proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_rsvd,  cmd_tvb, poff+9, 7, ENC_NA);

    if (len < 16)
        return len;

    /* NVM CS 1.2 Figure 110: a Namespace Element is a 16-byte header followed
     * by NLRD 16-byte LBA Range Descriptors (Figure 111), so the element is
     * 16 * (NLRD + 1) bytes.  NLRD is a 32-bit field at 07:04 of *this*
     * element, and FFFFFFFFh means no descriptor list is present.  Computed in
     * 64-bit: NLRD is a raw wire value and 16 * (NLRD + 1) overflows 32 bits.
     * The element length is what bounds the descriptor walk -- bounding it on
     * the bytes remaining in the whole list instead swallowed every following
     * Namespace Element into the first one. */
    if (!nlrd || nlrd == 0xffffffff)
        slen64 = 16;
    else
        slen64 = 16ULL * ((uint64_t)nlrd + 1);
    slen = (slen64 > len) ? len : (unsigned)slen64;
    proto_item_set_len(ti, slen);

    rem = slen - 16;
    poff += 16;
    while (rem >= 8) {
        ti = proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_rd,  cmd_tvb, poff, rem >= 16 ? 16 : rem, ENC_NA);
        rd =  proto_item_add_subtree(ti, ett_data);
        proto_tree_add_item(rd, hf_nvme_get_logpage_lba_status_nel_ne_rd_rslba, cmd_tvb, poff, 8, ENC_LITTLE_ENDIAN);
        if (rem >= 12)
            proto_tree_add_item(rd, hf_nvme_get_logpage_lba_status_nel_ne_rd_rnlb, cmd_tvb, poff+8, 4, ENC_LITTLE_ENDIAN);
        if (rem >= 16) {
            proto_tree_add_item(rd, hf_nvme_get_logpage_lba_status_nel_ne_rd_rsvd, cmd_tvb, poff+12, 4, ENC_LITTLE_ENDIAN);
            poff += 16;
            rem -= 16;
        } else {
            rem = 0;
        }
    }
    return slen;
}

static void dissect_nvme_get_logpage_lba_status_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
{
    uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
    proto_tree *grp = NULL;
    unsigned poff = 0;

    off += tr_off;
    if (off < 16) {
        grp =  proto_item_add_subtree(ti, ett_data);
        dissect_nvme_get_logpage_lba_status_resp_header(grp, cmd_tvb, len, off);
        poff = 16 - off;
    } else if (off & 15) {
        poff = 16 - (off & 15);
    }

    if (len < (poff + 8))
        return;

    if (off >= 16)
        grp =  proto_item_add_subtree(ti, ett_data);

    len -= poff;
    ti = proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel,  cmd_tvb, poff, len, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);

    while (len >= 8) {
        unsigned done = dissect_nvme_get_logpage_lba_status_lba_range(grp, cmd_tvb, len, poff);
        poff += done;
        len -= done;
    }
}

static void dissect_nvme_get_logpage_egroup_aggreg_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
{
    proto_tree *grp;
    unsigned poff = 0;

    if (!tr_off) {
        if (cmd_ctx->cmd_ctx.get_logpage.off < 8) {
            poff = 8 - (unsigned)cmd_ctx->cmd_ctx.get_logpage.off;
            if (poff > len || (cmd_ctx->cmd_ctx.get_logpage.off && poff == len))
                return;
        } else if (len < 2) {
            return;
        }
    }

    len -= poff;
    grp =  proto_item_add_subtree(ti, ett_data);
    if (!(cmd_ctx->cmd_ctx.get_logpage.off + tr_off))
        proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_aggreg_ne, cmd_tvb, 0, 8, ENC_LITTLE_ENDIAN);
    while (len >= 2) {
        proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_aggreg_eg, cmd_tvb, poff, 2, ENC_LITTLE_ENDIAN);
        len -= 2;
        poff += 2;
    }
}

static const value_string rnlpt_tbl[] = {
    { 0,  "Empty Log Page" },
    { 1,  "Registration Preempted" },
    { 2,  "Reservation Released" },
    { 3,  "Reservation Preempted" },
    { 0, NULL}
};

static void dissect_nvme_get_logpage_reserv_notif_resp(proto_item *ti, tvbuff_t *cmd_tvb, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned poff = 0;
    unsigned rel;

    if (off > 60)
        return; /* max allowed offset is < 60 */

    grp =  proto_item_add_subtree(ti, ett_data);
    if (nvme_field_in_window(off, len, 0, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_lpc,  cmd_tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 8, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_lpt,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 9, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_nalp,  cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 10, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_rsvd0,  cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 12, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_nsid,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (off < 16) {
        poff = 16 - off;
        if (len <= poff)
            return;
        len -= poff;
        if (len > 48)
            len = 48; /* max padding size is 48 */
    } else {
        if (len > (64 - off))
            len = 64 - off; /* max padding size is 48 */
    }
    proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_rsvd1, cmd_tvb, poff, len, ENC_NA);
}


/* Sanitize State (SANS) in the Sanitize State Information field; the Failure
 * State (FAILS) field takes its values from the same set (NVMe Base 2.3
 * "Sanitize Status Log Page"). */
static const value_string san_sans_tbl[] = {
    { 0, "Idle" },
    { 1, "Restricted Processing" },
    { 2, "Restricted Failure" },
    { 3, "Unrestricted Processing" },
    { 4, "Unrestricted Failure" },
    { 5, "Media Verification" },
    { 6, "Post-Verification Deallocation" },
    { 0, NULL}
};

static const value_string san_mrst_tbl[] = {
    { 0, "The NVM subsystem has never been sanitized" },
    { 1, "The most recent sanitize operation completed successfully" },
    { 2, "A sanitize operation is currently in progress" },
    { 3, "The most recent sanitize operation failed" },
    { 4, "The most recent sanitize operation with No-Deallocate has completed successfully with deallocation of all logical blocks"},
    { 0, NULL}
};

static void dissect_nvme_get_logpage_sanitize_resp(proto_item *ti, tvbuff_t *cmd_tvb, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned poff = 0;
    unsigned rel;

    if (off > 508)
        return; /* max allowed offset is < 508 */

    grp =  proto_item_add_subtree(ti, ett_data);
    if (nvme_field_in_window(off, len, 0, 2, &rel))
         proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_sprog,  cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 2, 2, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 2, ASPEC(hf_nvme_get_logpage_sanitize_sstat));
    if (nvme_field_in_window(off, len, 4, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_scdw10,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 8, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_eto,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 12, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etbe,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 16, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etce,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 20, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etond,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 24, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etbend,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 28, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etcend,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 32, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etpvds,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 36, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_sanitize_ssi));
    if (nvme_field_in_window(off, len, 37, 3, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_rsvd0,  cmd_tvb, rel, 3, ENC_NA);
    if (nvme_field_in_window(off, len, 40, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_mnsoip,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 44, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_stnsid,  cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (off < 48) {
        poff = 48 - off;
        /* Inverted before this fix: bailed out exactly when there WAS
         * enough data (poff <= len) and fell through to an underflowing
         * "len -= poff" exactly when there wasn't -- corrected to match the
         * safe pattern used elsewhere in this file (bail when unsafe). */
        if (len <= poff)
            return;
        len -= poff;
        /* Remaining room at tvb position poff (struct offset 48) is (512 -
         * off) - poff, not 512 - poff: poff is tvb-relative (48-off), so
         * "512 - poff" silently adds back `off` bytes past the structure's
         * real 512-byte end. */
        if (len > (512 - off - poff))
            len = 512 - off - poff;
    } else {
        if (len > (512 - off))
            len = 512 - off;
    }
    proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_rsvd,  cmd_tvb, poff, len, ENC_NA);
}

static void dissect_nvme_get_logpage_feat_sup_and_eff_resp(proto_item *ti, tvbuff_t *cmd_tvb, packet_info *pinfo, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned nrec, fidx, i;

    /* off >= 1024 is a window past the end of the page -- normal.  A window
     * that starts mid-record is not, so the two halves are reported apart. */
    if (off >= 1024)
        return;
    if (!nvme_offset_record_aligned(off, 4)) {
        expert_add_info(pinfo, ti, &ei_nvme_logpage_window_misaligned);
        return;
    }

    grp = proto_item_add_subtree(ti, ett_data);
    fidx = off / 4;
    nrec = (1024 - off) / 4;
    if (nrec > (len / 4))
        nrec = len / 4;

    for (i = 0; i < nrec; i++) {
        proto_item *entry;
        proto_tree *egrp;
        unsigned fid = fidx + i;
        entry = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_feat_sup_and_eff_fidx,
            cmd_tvb, i * 4, 4, NULL, "FID %02Xh Supported and Effects", fid);
        egrp = proto_item_add_subtree(entry, ett_data);
        add_group_mask_entry(cmd_tvb, egrp, i * 4, 4, ASPEC(hf_nvme_get_logpage_feat_sup_and_eff_fids));
    }
}

static void dissect_nvme_get_logpage_mi_cmd_sup_and_eff_resp(proto_item *ti, tvbuff_t *cmd_tvb, packet_info *pinfo, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned nrec, fidx, i;

    if (off >= 1024)
        return;
    if (!nvme_offset_record_aligned(off, 4)) {
        expert_add_info(pinfo, ti, &ei_nvme_logpage_window_misaligned);
        return;
    }

    grp = proto_item_add_subtree(ti, ett_data);
    fidx = off / 4;
    nrec = (1024 - off) / 4;
    if (nrec > (len / 4))
        nrec = len / 4;

    for (i = 0; i < nrec; i++) {
        proto_item *entry;
        proto_tree *egrp;
        entry = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_mi_cmd_sup_and_eff_cs,
            cmd_tvb, i * 4, 4, NULL, "MI Command Opcode %02Xh Supported and Effects", fidx + i);
        egrp = proto_item_add_subtree(entry, ett_data);
        add_group_mask_entry(cmd_tvb, egrp, i * 4, 4, ASPEC(hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds));
    }
}

/* Defined further down, next to the fid_table it wraps. */
static const char *get_feature_id_name(uint8_t fid);

static void dissect_nvme_get_logpage_cmd_feat_lockdown_resp(proto_item *ti, tvbuff_t *cmd_tvb, unsigned off, unsigned len)
{
    proto_tree *grp;
    proto_item *cfil_ti;
    uint8_t lngth, ss, code;
    unsigned i, list_end;

    if (off)
        return; /* variable-length CFIL list can only be decoded starting at offset 0 */
    if (len < 4)
        return;

    grp = proto_item_add_subtree(ti, ett_data);
    add_group_mask_entry(cmd_tvb, grp, 0, 1, ASPEC(hf_nvme_get_logpage_cmd_feat_lockdown_cfila));
    proto_tree_add_item(grp, hf_nvme_get_logpage_cmd_feat_lockdown_rsvd, cmd_tvb, 1, 2, ENC_NA);
    proto_tree_add_item_ret_uint8(grp, hf_nvme_get_logpage_cmd_feat_lockdown_lngth, cmd_tvb, 3, 1, ENC_LITTLE_ENDIAN, &lngth);

    /* NVMe Base 2.3 Figure 271: the Command and Feature Identifier List holds
     * "a list of coded values identified by the Scope Selected field and the
     * Content Selected field", so the same byte names an Admin opcode under
     * Scope 0h and a Set Features Feature Identifier under Scope 2h -- 02h is
     * Get Log Page in the first and Power Management in the second.  Scope is
     * echoed back in CFILA (byte 0, bits 3:0), so the response names its own
     * list and nothing has to be carried over from the request.
     *
     * Scopes 3h and 4h are Management Interface and PCIe Command Set opcodes;
     * neither table lives in this dissector, so those bytes stay raw rather
     * than being labelled from the wrong one. */
    ss = tvb_get_uint8(cmd_tvb, 0) & 0x0f;
    for (i = 0; i < lngth && (4 + i) < len; i++) {
        cfil_ti = proto_tree_add_item_ret_uint8(grp, hf_nvme_get_logpage_cmd_feat_lockdown_cfil,
                                                cmd_tvb, 4 + i, 1, ENC_LITTLE_ENDIAN, &code);
        if (ss == 0)
            proto_item_append_text(cfil_ti, " (%s)", get_aq_opcode_name(code));
        else if (ss == 2)
            proto_item_append_text(cfil_ti, " (%s)", get_feature_id_name(code));
    }
    list_end = 4 + lngth;
    if (len > list_end)
        proto_tree_add_item(grp, hf_nvme_get_logpage_cmd_feat_lockdown_rsvd1, cmd_tvb, list_end, len - list_end, ENC_NA);
}

/* Supported Log Pages (LID 00h): an array of 256 four-byte LID Supported and
 * Effects data structures, one per Log Page
 * Identifier 00h..FFh.  cmd_tvb begins at the returned data window; entry 0
 * here is the LID at logical offset `off` (LPO + the MI transfer/DOFF), so the
 * first decoded entry describes LID (off / 4). */
static void dissect_nvme_get_logpage_supported_grp(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned nrec, unsigned lid0)
{
    unsigned i;
    proto_item *ti;
    proto_tree *sub;

    for (i = 0; i < nrec; i++) {
        ti = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_supported_lids, cmd_tvb, i * 4, 4, NULL,
                                         "Log Page Identifier 0x%02x Supported (LIDS%u)", lid0 + i, lid0 + i);
        sub =  proto_item_add_subtree(ti, ett_data);
        add_group_mask_entry(cmd_tvb, sub, i * 4, 4, ASPEC(hf_nvme_get_logpage_supported_lidseds));
    }
}

static void dissect_nvme_get_logpage_supported_resp(proto_item *ti, tvbuff_t *cmd_tvb, packet_info *pinfo, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned nrec;

    if (off >= 1024)
        return; /* page is 256 four-byte entries = 1024 bytes */
    if (!nvme_offset_record_aligned(off, 4)) {
        expert_add_info(pinfo, ti, &ei_nvme_logpage_window_misaligned);
        return;
    }

    grp =  proto_item_add_subtree(ti, ett_data);

    nrec = (1024 - off) / 4;
    if (nrec > (len / 4))
        nrec = len / 4;
    dissect_nvme_get_logpage_supported_grp(grp, cmd_tvb, nrec, off / 4);
}

static const value_string eom_eomip_tbl[] = {
    { 0, "No Measurement Started" },
    { 1, "Measurement In Progress" },
    { 2, "Measurement Completed" },
    { 0, NULL },
};

/* One EOM Lane Descriptor (NVMe over PCIe Transport 1.3 Figure 73): a fixed
 * 32-byte header (Reserved, MSTAT, LN, EYE, TOP, BTM, LFT, RGT, NROWS, NCOLS,
 * EDLEN, Reserved) followed by an optional Printable Eye field (NROWS*NCOLS
 * bytes) and an optional Eye Data field (EDLEN bytes); both are wire-controlled
 * so their end offsets are computed in 64-bit and checked against both the
 * descriptor's own size (ds) and the available response length (len) before
 * being handed to proto_tree_add_item(), whose length parameter is a signed
 * int. */
static void dissect_nvme_get_logpage_eom_desc(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned desc_off, unsigned ds, unsigned len, unsigned idx)
{
    proto_item *desc_ti;
    proto_tree *desc_tree;
    uint32_t nrows = 0, ncols = 0, edlen = 0;
    uint64_t eye_off, eye_end;
    bool pe_ok = true;

    desc_ti = proto_tree_add_bytes_format_value(grp, hf_nvme_get_logpage_eom_desc, cmd_tvb,
                    desc_off, ds, NULL, "EOM Lane Descriptor %u", idx);
    desc_tree = proto_item_add_subtree(desc_ti, ett_data);

    proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_rsvd0, cmd_tvb, desc_off, 1, ENC_NA);
    add_group_mask_entry(cmd_tvb, desc_tree, desc_off + 1, 1, ASPEC(hf_nvme_get_logpage_eom_desc_mstat));
    proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_ln, cmd_tvb, desc_off + 2, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_eye, cmd_tvb, desc_off + 3, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_top, cmd_tvb, desc_off + 4, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_btm, cmd_tvb, desc_off + 6, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_lft, cmd_tvb, desc_off + 8, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_rgt, cmd_tvb, desc_off + 10, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item_ret_uint(desc_tree, hf_nvme_get_logpage_eom_desc_nrows, cmd_tvb, desc_off + 12, 2, ENC_LITTLE_ENDIAN, &nrows);
    proto_tree_add_item_ret_uint(desc_tree, hf_nvme_get_logpage_eom_desc_ncols, cmd_tvb, desc_off + 14, 2, ENC_LITTLE_ENDIAN, &ncols);
    proto_tree_add_item_ret_uint(desc_tree, hf_nvme_get_logpage_eom_desc_edlen, cmd_tvb, desc_off + 16, 4, ENC_LITTLE_ENDIAN, &edlen);
    proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_rsvd1, cmd_tvb, desc_off + 20, 12, ENC_NA);

    /* Figure 73 places Eye Data at (NROWS*NCOLS+32), i.e. directly after the
     * Printable Eye.  So if PE is declared but does not fit in the descriptor,
     * ED's own start offset is past the end of the descriptor too and the
     * descriptor is internally inconsistent -- rendering ED at the PE offset
     * instead would present eye-diagram bytes under the Eye Data label. */
    eye_off = (uint64_t)desc_off + 32;
    if (nrows && ncols) {
        eye_end = eye_off + (uint64_t)nrows * ncols;
        pe_ok = (eye_end <= (uint64_t)desc_off + ds && eye_end <= len);
        if (pe_ok) {
            proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_pe, cmd_tvb,
                        (unsigned)eye_off, (int)(nrows * ncols), ENC_ASCII);
            eye_off = eye_end;
        }
    }
    if (edlen && pe_ok) {
        eye_end = eye_off + edlen;
        if (eye_end <= (uint64_t)desc_off + ds && eye_end <= len)
            proto_tree_add_item(desc_tree, hf_nvme_get_logpage_eom_desc_ed, cmd_tvb,
                        (unsigned)eye_off, (int)edlen, ENC_NA);
    }
}

/* Physical Interface Receiver Eye Opening Measurement (LID 19h): defined by
 * the NVMe over PCIe Transport Specification, not NVMe Base -- Base's Get Log
 * Page LID table just says "refer to the applicable NVM Express Transport
 * specification" for 19h (get_logpage_name() already renders it as "Transport
 * Specific" for that reason). Layout is a fixed 64-byte EOM Header (Figure 72)
 * followed by ND EOM Lane Descriptors (Figure 73) of DS bytes each; ND and DS
 * both live in the header, so -- like the CFIL list in
 * dissect_nvme_get_logpage_cmd_feat_lockdown_resp() -- the descriptor list can
 * only be walked when this call's window starts at offset 0 and covers the
 * whole header. */
static void dissect_nvme_get_logpage_eom_resp(proto_item *ti, tvbuff_t *cmd_tvb, packet_info *pinfo, struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
{
    proto_tree *grp;
    unsigned rel, i;
    uint32_t ds = 0, nd = 0;

    grp = proto_item_add_subtree(ti, ett_data);

    if (nvme_field_in_window(off, len, 0, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_lid, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 1, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_eomip, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 2, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_hsize, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 4, 4, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_rsz, cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 8, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_edgn, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 9, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_lrev, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 10, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_eom_odp));
    if (nvme_field_in_window(off, len, 11, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_lns, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 12, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_epl, cmd_tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 13, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_eom_lspfc));
    if (nvme_field_in_window(off, len, 14, 1, &rel))
        add_group_mask_entry(cmd_tvb, grp, rel, 1, ASPEC(hf_nvme_get_logpage_eom_linfo));
    if (nvme_field_in_window(off, len, 15, 3, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_rsvd0, cmd_tvb, rel, 3, ENC_NA);
    if (nvme_field_in_window(off, len, 18, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_lsic, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 20, 4, &rel))
        proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_eom_ds, cmd_tvb, rel, 4, ENC_LITTLE_ENDIAN, &ds);
    if (nvme_field_in_window(off, len, 24, 2, &rel))
        proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_eom_nd, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN, &nd);
    if (nvme_field_in_window(off, len, 26, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_maxtb, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 28, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_maxlr, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 30, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_etgood, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 32, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_etbetter, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 34, 2, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_etbest, cmd_tvb, rel, 2, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 36, 28, &rel))
        proto_tree_add_item(grp, hf_nvme_get_logpage_eom_rsvd1, cmd_tvb, rel, 28, ENC_NA);

    if (off != 0 || len < 64 || ds < 32 || nd == 0)
        return; /* need DS/ND from the header to walk the descriptor list */

    for (i = 0; i < nd; i++) {
        uint64_t desc_off64 = 64ULL + (uint64_t)i * ds;

        /* ND and DS are both wire-declared and unvalidated, so a header can
         * claim more descriptors than the response holds.  `len` is already
         * bounded by the buffer by the callers (see
         * dissect_nvme_get_logpage_resp()), so this is the structural bound:
         * stop at the last descriptor that fits in the declared response. */
        if (desc_off64 + ds > len) {
            /* Running out of descriptors is only a contradiction when this
             * window already holds everything the host asked for; over
             * NVMe-MI the remainder is normally just in a later window.  NUMD
             * is 0's based and counts dwords (NVMe Base 2.3 Figure 202/203).
             * The request must have been seen to reach this decoder at all --
             * the caller selects it on the stored LID, which is 0h otherwise
             * -- so NUMD is valid here. */
            uint64_t declared = ((uint64_t)cmd_ctx->cmd_ctx.get_logpage.numd + 1) * 4;

            if (len >= declared)
                expert_add_info(pinfo, ti, &ei_nvme_eom_desc_truncated);
            break;
        }
        dissect_nvme_get_logpage_eom_desc(grp, cmd_tvb, (unsigned)desc_off64, ds, len, i);
    }
}

static void dissect_nvme_get_logpage_resp(tvbuff_t *cmd_tvb, packet_info *pinfo, proto_tree *cmd_tree, struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
{
    /* `len` is already bounded by the buffer: every caller reaches this either
     * through dissect_nvme_data_response(), which clamps a lying transport
     * length to tvb_reported_length(), or from packet-nvme-mi-admin.c, which
     * sizes it from tvb_reported_length() itself.  So this container item does
     * not clamp again -- on a snaplen-sliced capture it is meant to throw, the
     * same as every decoder below it. */
    proto_item *ti = proto_tree_add_bytes_format_value(cmd_tree, hf_nvme_gen_data, cmd_tvb, 0,
                            len, NULL,
                            "NVMe Get Log Page (%s)", get_logpage_name(cmd_ctx->cmd_ctx.get_logpage.lid));
    /* Per NVMe-MI 2.1 SS "Request and Response Data" (the "NVMe Admin
     * Command Response Data Example" / "NVMe Get Log Page Command Response
     * Data Example" figures): the
     * Log Page Offset (LPO, captured from the request's CDW12/13 into
     * cmd_ctx->cmd_ctx.get_logpage.off by dissect_nvme_get_logpage_cmd())
     * is applied first to select the logical response data, then the
     * transport-level window (`off` here -- NVMe-MI DOFST, or the
     * TCP/RDMA transfer offset) is applied on top of that.  Several
     * decoders below take a single combined offset directly; others
     * (unchanged here) already do this same LPO+transport combination
     * internally using their own `tr_off`-named parameter.
     *
     * LPO is a wire-controlled uint64_t with no upper-bound validation at
     * parse time, so the sum is computed in 64-bit and saturated (not
     * truncated) to unsigned: every decoder below rejects an out-of-range
     * offset via an "off > <max>" style guard, so clamping an overflowing
     * sum to UINT32_MAX guarantees those guards reject it, instead of a
     * huge LPO silently wrapping into a small, in-range-looking offset. */
    uint64_t lpo = cmd_ctx->cmd_ctx.get_logpage.off;
    uint64_t combined_off64 = (lpo > UINT64_MAX - off) ? UINT64_MAX : lpo + off;
    unsigned combined_off = (combined_off64 > UINT32_MAX) ? UINT32_MAX : (unsigned)combined_off64;

    switch(cmd_ctx->cmd_ctx.get_logpage.lid) {
        case NVME_LID_SUPPORTED_LOG_PAGES:
            dissect_nvme_get_logpage_supported_resp(ti, cmd_tvb, pinfo, combined_off, len); break;
        case NVME_LID_DISCOVERY:
            dissect_nvme_get_logpage_ify_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
        case NVME_LID_ERROR_INFO:
            dissect_nvme_get_logpage_err_inf_resp(ti, cmd_tvb, combined_off, len); break;
        case NVME_LID_SMART:
            dissect_nvme_get_logpage_smart_resp(ti, cmd_tvb, combined_off, len); break;
        case NVME_LID_FW_SLOT:
            dissect_nvme_get_logpage_fw_slot_resp(ti, cmd_tvb, combined_off, len); break;
        case NVME_LID_CHANGED_NSLIST:
        case NVME_LID_CHANGED_ALLOC_NSLIST:
            dissect_nvme_get_logpage_changed_nslist_resp(ti, cmd_tvb, pinfo, combined_off, len); break;
        case NVME_LID_CMD_SUP_AND_EFF:
            dissect_nvme_get_logpage_cmd_sup_and_eff_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
        case NVME_LID_DEVICE_SELF_TEST:
            dissect_nvme_get_logpage_selftest_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
        case NVME_LID_TELEMETRY_HOST:
        case NVME_LID_TELEMETRY_CTRL:
            dissect_nvme_get_logpage_telemetry_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
        case NVME_LID_ENDURANCE_GROUP:
            dissect_nvme_get_logpage_egroup_resp(ti, cmd_tvb, cmd_ctx, combined_off, len); break;
        case NVME_LID_PRED_LAT_NVM_SET:
            dissect_nvme_get_logpage_pred_lat_resp(ti, cmd_tvb, cmd_ctx, combined_off, len); break;
        case NVME_LID_PRED_LAT_EVENT_AGG:
            dissect_nvme_get_logpage_pred_lat_aggreg_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
        case NVME_LID_ANA:
            dissect_nvme_get_logpage_ana_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
        case NVME_LID_LBA_STATUS:
            dissect_nvme_get_logpage_lba_status_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
        case NVME_LID_ENDURANCE_GROUP_EVENT_AGG:
            dissect_nvme_get_logpage_egroup_aggreg_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
        case NVME_LID_RESERVATION_NOTIFICATION:
            dissect_nvme_get_logpage_reserv_notif_resp(ti, cmd_tvb, combined_off, len); break;
        case NVME_LID_SANITIZE_STATUS:
            dissect_nvme_get_logpage_sanitize_resp(ti, cmd_tvb, combined_off, len); break;
        case NVME_LID_FEATURE_ID_SUP_AND_EFF:
            dissect_nvme_get_logpage_feat_sup_and_eff_resp(ti, cmd_tvb, pinfo, combined_off, len); break;
        case NVME_LID_NVME_MI_CMD_SUP_AND_EFF:
            dissect_nvme_get_logpage_mi_cmd_sup_and_eff_resp(ti, cmd_tvb, pinfo, combined_off, len); break;
        case NVME_LID_CMD_FEAT_LOCKDOWN:
            dissect_nvme_get_logpage_cmd_feat_lockdown_resp(ti, cmd_tvb, combined_off, len); break;
        case NVME_LID_PHY_RX_EOM:
            dissect_nvme_get_logpage_eom_resp(ti, cmd_tvb, pinfo, cmd_ctx, combined_off, len); break;
        default:
            return;
    }
}

static void dissect_nvme_get_logpage_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
                                      struct nvme_cmd_ctx *cmd_ctx)
{
    proto_item *ti;
    unsigned val;

    cmd_ctx->cmd_ctx.get_logpage.lid = tvb_get_uint8(cmd_tvb, 40);
    cmd_ctx->cmd_ctx.get_logpage.lsi = tvb_get_uint16(cmd_tvb, 46, ENC_LITTLE_ENDIAN);

    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_get_logpage_dword10));
    ti = proto_tree_add_item_ret_uint(cmd_tree, hf_nvme_get_logpage_numd, cmd_tvb, 42, 4, ENC_LITTLE_ENDIAN, &val);
    proto_item_append_text(ti, " (%"PRIu64" bytes)", ((uint64_t)val + 1) * 4);
    cmd_ctx->cmd_ctx.get_logpage.numd = val;

    add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_get_logpage_dword11));

    proto_tree_add_item_ret_uint64(cmd_tree, hf_nvme_get_logpage_lpo, cmd_tvb, 48, 8, ENC_LITTLE_ENDIAN, &cmd_ctx->cmd_ctx.get_logpage.off);
    cmd_ctx->cmd_ctx.get_logpage.off &= (~((uint64_t)3)); /* clear two low bits, the target shall either deny the command or clear the bits */

    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);

    add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_get_logpage_dword14));

    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

typedef enum {
    F_ARBITRATION = 0x01,
    F_POWER_MGMT = 0x02,
    F_LBA_RANGE_TYPE = 0x03,
    F_TEMP_THRESHOLD = 0x04,
    F_ERROR_RECOVERY = 0x05,
    F_VOLATILE_WC = 0x06,
    F_NUM_OF_QUEUES = 0x07,
    F_IRQ_COALESCING = 0x08,
    F_IRQ_VECTOR_CONF = 0x09,
    F_WRITE_ATOM_NORM = 0x0A,
    F_ASYNC_EVENT_CONF = 0x0B,
    F_AUTO_PS_TRANSITION = 0x0C,
    F_HOST_MEM_BUF = 0x0D,
    F_TIMESTAMP = 0x0E,
    F_KA_TIMER = 0x0F,
    F_HOST_CNTL_THERM_MGMT = 0x10,
    F_NO_POWER_STATE_CONF = 0x11,
    F_READ_REC_LEVEL_CONF = 0x12,
    F_PRED_LAT_MODE_CONF = 0x13,
    F_PRED_LAT_MODE_WIND = 0x14,
    F_LBA_ST_INF_REP_INT = 0x15,
    F_HOST_BEHV_SUPPORT = 0x16,
    F_SANITIZE_CON = 0x17,
    F_END_GROUP_EV_CONF = 0x18,
    F_IO_CMD_SET_PROFILE = 0x19,
    F_SPINUP_CONTROL = 0x1A,
    F_POWER_LOSS_SIG_CONF = 0x1B,
    F_PERF_CHARACTERISTICS = 0x1C,
    F_FDP = 0x1D,
    F_FDP_EVENTS = 0x1E,
    F_NS_ADMIN_LABEL = 0x1F,
    F_KV_CONFIG = 0x20,
    F_CTRL_DATA_QUEUE = 0x21,
    F_CONF_DEV_PERSONALITY = 0x22,
    F_POWER_LIMIT = 0x23,
    F_POWER_THRESHOLD = 0x24,
    F_POWER_MEASUREMENT = 0x25,
    F_EMB_MGMT_CTRL_ADDR = 0x78,
    F_HOST_MGMT_AGENT_ADDR = 0x79,
    F_ENH_CTRL_METADATA = 0x7D,
    F_CTRL_METADATA = 0x7E,
    F_NS_METADATA = 0x7F,
    F_SW_PR_MARKER = 0x80,
    F_HOST_ID = 0x81,
    F_RSRV_NOT_MASK = 0x82,
    F_RSRV_PRST = 0x83,
    F_NS_WRITE_CONF = 0x84,
    F_BP_WRITE_PROT_CONF = 0x85,
} nvme_setf_t;


static const range_string fid_table[] = {
    { F_ARBITRATION, F_ARBITRATION, "Arbitration" },
    { F_POWER_MGMT, F_POWER_MGMT, "Power Management" },
    { F_LBA_RANGE_TYPE, F_LBA_RANGE_TYPE, "LBA Range Type" },
    { F_TEMP_THRESHOLD, F_TEMP_THRESHOLD, "Temperature Threshold" },
    { F_ERROR_RECOVERY, F_ERROR_RECOVERY, "Error Recovery" },
    { F_VOLATILE_WC, F_VOLATILE_WC, "Volatile Write Cache" },
    { F_NUM_OF_QUEUES, F_NUM_OF_QUEUES, "Number of Queues" },
    { F_IRQ_COALESCING, F_IRQ_COALESCING, "Interrupt Coalescing" },
    { F_IRQ_VECTOR_CONF, F_IRQ_VECTOR_CONF, "Interrupt Vector Configuration" },
    { F_WRITE_ATOM_NORM, F_WRITE_ATOM_NORM, "Write Atomicity Normal" },
    { F_ASYNC_EVENT_CONF, F_ASYNC_EVENT_CONF, "Asynchronous Event Configuration" },
    { F_AUTO_PS_TRANSITION, F_AUTO_PS_TRANSITION, "Autonomous Power State Transition" },
    { F_HOST_MEM_BUF, F_HOST_MEM_BUF, "Host Memory Buffer" },
    { F_TIMESTAMP, F_TIMESTAMP, "Timestamp" },
    { F_KA_TIMER, F_KA_TIMER, "Keep Alive Timer" },
    { F_HOST_CNTL_THERM_MGMT, F_HOST_CNTL_THERM_MGMT, "Host Controlled Thermal Management" },
    { F_NO_POWER_STATE_CONF, F_NO_POWER_STATE_CONF, "Non-Operational Power State Config" },
    { F_READ_REC_LEVEL_CONF, F_READ_REC_LEVEL_CONF, "Read Recovery Level Config" },
    { F_PRED_LAT_MODE_CONF, F_PRED_LAT_MODE_CONF, "Predictable Latency Mode Config" },
    { F_PRED_LAT_MODE_WIND, F_PRED_LAT_MODE_WIND, "Predictable Latency Mode Window" },
    { F_LBA_ST_INF_REP_INT, F_LBA_ST_INF_REP_INT, "LBA Status Information Report Interval" },
    { F_HOST_BEHV_SUPPORT, F_HOST_BEHV_SUPPORT, "Host Behavior Support" },
    { F_SANITIZE_CON, F_SANITIZE_CON, "Sanitize Config" },
    { F_END_GROUP_EV_CONF, F_END_GROUP_EV_CONF, "Endurance Group Event Configuration" },
    { F_IO_CMD_SET_PROFILE, F_IO_CMD_SET_PROFILE, "I/O Command Set Profile" },
    { F_SPINUP_CONTROL, F_SPINUP_CONTROL, "Spinup Control" },
    { F_POWER_LOSS_SIG_CONF, F_POWER_LOSS_SIG_CONF, "Power Loss Signaling Config" },
    { F_PERF_CHARACTERISTICS, F_PERF_CHARACTERISTICS, "Performance Characteristics" },
    { F_FDP, F_FDP, "Flexible Data Placement" },
    { F_FDP_EVENTS, F_FDP_EVENTS, "Flexible Data Placement Events" },
    { F_NS_ADMIN_LABEL, F_NS_ADMIN_LABEL, "Namespace Admin Label" },
    { F_KV_CONFIG, F_KV_CONFIG, "Key Value Configuration" },
    { F_CTRL_DATA_QUEUE, F_CTRL_DATA_QUEUE, "Controller Data Queue" },
    { F_CONF_DEV_PERSONALITY, F_CONF_DEV_PERSONALITY, "Configurable Device Personality" },
    { F_POWER_LIMIT, F_POWER_LIMIT, "Power Limit" },
    { F_POWER_THRESHOLD, F_POWER_THRESHOLD, "Power Threshold" },
    { F_POWER_MEASUREMENT, F_POWER_MEASUREMENT, "Power Measurement" },
    { F_EMB_MGMT_CTRL_ADDR, F_EMB_MGMT_CTRL_ADDR, "Embedded Management Controller Address" },
    { F_HOST_MGMT_AGENT_ADDR, F_HOST_MGMT_AGENT_ADDR, "Host Management Agent Address" },
    { F_ENH_CTRL_METADATA, F_ENH_CTRL_METADATA, "Enhanced Controller Metadata" },
    { F_CTRL_METADATA, F_CTRL_METADATA, "Controller Metadata" },
    { F_NS_METADATA, F_NS_METADATA, "Namespace Metadata" },
    { F_SW_PR_MARKER, F_SW_PR_MARKER, "Software Progress Marker" },
    { F_HOST_ID, F_HOST_ID, "Host Identifier" },
    { F_RSRV_NOT_MASK, F_RSRV_NOT_MASK, "Reservation Notification Mask" },
    { F_RSRV_PRST, F_RSRV_PRST, "Reservation Persistence" },
    { F_NS_WRITE_CONF, F_NS_WRITE_CONF, "Namespace Write Protection Config" },
    { F_BP_WRITE_PROT_CONF, F_BP_WRITE_PROT_CONF, "Boot Partition Write Protection Config" },
    { 0xC0, 0xFF, "Vendor Specific" },
    { 0, 0, NULL },
};

/* Forward-declared above for dissect_nvme_get_logpage_cmd_feat_lockdown_resp(),
 * which names Command and Feature Identifier List entries when the log page's
 * Scope Selected field says they are Feature Identifiers. */
static const char *get_feature_id_name(uint8_t fid)
{
    return rval_to_str_const(fid, fid_table, "Reserved");
}

static const value_string sel_table[] = {
    { 0, "Current" },
    { 1, "Default" },
    { 2, "Saved" },
    { 3, "Supported Capabilities" },
    { 0, NULL },
};

static const value_string sf_tmpsel_table[] = {
    { 0x0, "Composite Temperature" },
    { 0x1, "Temperature Sensor 1" },
    { 0x2, "Temperature Sensor 2" },
    { 0x3, "Temperature Sensor 3" },
    { 0x4, "Temperature Sensor 4" },
    { 0x5, "Temperature Sensor 5" },
    { 0x6, "Temperature Sensor 6" },
    { 0x7, "Temperature Sensor 7" },
    { 0x8, "Temperature Sensor 8" },
    { 0xF, "All Temperature Sensors" },
    { 0, NULL },
};

static const value_string sf_thpsel_table[] = {
    { 0x0, "Over Temperature Threshold" },
    { 0x1, "Under Temperature Threshold" },
    { 0x2, "Reserved" },
    { 0x3, "Reserved" },
    { 0, NULL },
};

static const value_string sf_ws_table[] = {
    { 0x0, "Reserved" },
    { 0x1, "Deterministic Window" },
    { 0x2, "Non-Deterministic Window" },
    { 0x3, "Reserved" },
    { 0x4, "Reserved" },
    { 0x5, "Reserved" },
    { 0x6, "Reserved" },
    { 0x7, "Reserved" },
    { 0, NULL },
};

static const value_string sf_wps[] = {
    { 0x0, "No Write Protect" },
    { 0x1, "Write Protect" },
    { 0x2, "Write Protect Until Power Cycle" },
    { 0x3, "Permanent Write Protect" },
    { 0x4, "Reserved" },
    { 0x5, "Reserved" },
    { 0x6, "Reserved" },
    { 0x7, "Reserved" },
    { 0, NULL },
};

/* Power Loss Signaling Mode (PLSM), Power Loss Signaling Config Set Features
 * Command Dword 11 bits 1:0. */
static const value_string sf_plsm[] = {
    { 0x0, "Power Loss Signaling not enabled" },
    { 0x1, "Power Loss Signaling with Emergency Power Fail enabled" },
    { 0x2, "Power Loss Signaling with Forced Quiescence enabled" },
    { 0x3, "Reserved" },
    { 0, NULL },
};

/* Boot Partition Write Protection State (BP0WPS/BP1WPS), Boot Partition Write
 * Protection Config Set Features Command Dword 11. */
static const value_string sf_bpwps[] = {
    { 0x0, "Change in state not requested" },
    { 0x1, "Write Unlocked" },
    { 0x2, "Write Locked" },
    { 0x3, "Write Locked Until Power Cycle" },
    { 0x4, "Write Protection controlled by RPMB" },
    { 0x5, "Reserved" },
    { 0x6, "Reserved" },
    { 0x7, "Reserved" },
    { 0, NULL },
};

static void add_nvme_queues(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "%x (%u)", val, val+1);
}

/* Host Metadata features (FID 7Dh/7Eh/7Fh) Element Action, Set Features
 * Command Dword 11 bits 14:13. */
static const value_string sf_host_metadata_ea[] = {
    { 0x0, "Add or Replace Entry" },
    { 0x1, "Delete Entry Multiple" },
    { 0x2, "Add Entry Multiple" },
    { 0x3, "Reserved" },
    { 0, NULL },
};

/* Metadata Element Descriptor Element Type for the (Enhanced) Controller
 * Metadata features 7Dh/7Eh (NVMe Base 2.3 "Controller Metadata Element
 * Types"). */
static const range_string host_metadata_ctrl_et[] = {
    { 0x00, 0x00, "Reserved" },
    { 0x01, 0x01, "Operating System Controller Name" },
    { 0x02, 0x02, "Operating System Driver Name" },
    { 0x03, 0x03, "Operating System Driver Version" },
    { 0x04, 0x04, "Pre-boot Controller Name" },
    { 0x05, 0x05, "Pre-boot Driver Name" },
    { 0x06, 0x06, "Pre-boot Driver Version" },
    { 0x07, 0x07, "System Processor Model" },
    { 0x08, 0x08, "Chipset Driver Name" },
    { 0x09, 0x09, "Chipset Driver Version" },
    { 0x0A, 0x0A, "Operating System Name and Build" },
    { 0x0B, 0x0B, "System Product Name" },
    { 0x0C, 0x0C, "Firmware Version" },
    { 0x0D, 0x0D, "Operating System Driver Filename" },
    { 0x0E, 0x0E, "Display Driver Name" },
    { 0x0F, 0x0F, "Display Driver Version" },
    { 0x10, 0x10, "Host-Determined Failure Record" },
    { 0x11, 0x17, "Reserved" },
    { 0x18, 0x1F, "Vendor Specific" },
    { 0, 0, NULL },
};

/* Metadata Element Descriptor Element Type for the Namespace Metadata feature
 * 7Fh (NVMe Base 2.3 "Namespace Metadata Element Types"). */
static const range_string host_metadata_ns_et[] = {
    { 0x00, 0x00, "Reserved" },
    { 0x01, 0x01, "Operating System Namespace Name" },
    { 0x02, 0x02, "Pre-boot Namespace Name" },
    { 0x03, 0x03, "Operating System Namespace Name Qualifier 1" },
    { 0x04, 0x04, "Operating System Namespace Name Qualifier 2" },
    { 0x05, 0x17, "Reserved" },
    { 0x18, 0x1F, "Vendor Specific" },
    { 0, 0, NULL },
};

static void dissect_nvme_set_features_dword11(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, unsigned fid)
{
    switch (fid) {
        case F_ARBITRATION: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_arb)); break;
        case F_POWER_MGMT: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_pm)); break;
        case F_LBA_RANGE_TYPE: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_lbart)); break;
        case F_TEMP_THRESHOLD: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_tt)); break;
        case F_ERROR_RECOVERY: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_erec)); break;
        case F_VOLATILE_WC: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_vwce)); break;
        case F_NUM_OF_QUEUES: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_nq)); break;
        case F_IRQ_COALESCING: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_irqc)); break;
        case F_IRQ_VECTOR_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_irqv)); break;
        case F_WRITE_ATOM_NORM: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_wan)); break;
        case F_ASYNC_EVENT_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_aec)); break;
        case F_AUTO_PS_TRANSITION: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_apst)); break;
        case F_KA_TIMER: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_kat)); break;
        case F_HOST_CNTL_THERM_MGMT: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_hctm)); break;
        case F_NO_POWER_STATE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_nops)); break;
        case F_READ_REC_LEVEL_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_rrl)); break;
        case F_PRED_LAT_MODE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_plmc)); break;
        case F_PRED_LAT_MODE_WIND: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_plmw)); break;
        case F_LBA_ST_INF_REP_INT: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_lbasi)); break;
        case F_SANITIZE_CON: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_san)); break;
        case F_END_GROUP_EV_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_eg)); break;
        case F_SW_PR_MARKER: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_swp)); break;
        case F_HOST_ID: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_hid)); break;
        case F_RSRV_NOT_MASK: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_rsrvn)); break;
        case F_RSRV_PRST: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_rsrvp)); break;
        case F_NS_WRITE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_nswp)); break;
        case F_ENH_CTRL_METADATA:
        case F_CTRL_METADATA:
        case F_NS_METADATA: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_hmd)); break;
        case F_HOST_MEM_BUF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_hmb)); break;
        case F_IO_CMD_SET_PROFILE: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_iocsp)); break;
        case F_SPINUP_CONTROL: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_spinup)); break;
        case F_POWER_LOSS_SIG_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_plsc)); break;
        case F_FDP: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_fdp)); break;
        case F_FDP_EVENTS: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_fdpe)); break;
        case F_BP_WRITE_PROT_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_bpwpc)); break;
        default: proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN);
    }
}

static void dissect_nvme_set_features_dword12(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, unsigned fid)
{
    switch (fid) {
        case F_READ_REC_LEVEL_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 48, 4, ASPEC(hf_nvme_cmd_set_features_dword12_rrl)); break;
        case F_PRED_LAT_MODE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 48, 4, ASPEC(hf_nvme_cmd_set_features_dword12_plmc)); break;
        case F_PRED_LAT_MODE_WIND: add_group_mask_entry(cmd_tvb, cmd_tree, 48, 4, ASPEC(hf_nvme_cmd_set_features_dword12_plmw)); break;
        default: proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    }
}

static void dissect_nvme_set_features_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
                                      struct nvme_cmd_ctx *cmd_ctx)
{
    cmd_ctx->cmd_ctx.set_features.fid = tvb_get_uint8(cmd_tvb, 40);
    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_set_features_dword10));
    dissect_nvme_set_features_dword11(cmd_tvb, cmd_tree, cmd_ctx->cmd_ctx.set_features.fid);
    dissect_nvme_set_features_dword12(cmd_tvb, cmd_tree, cmd_ctx->cmd_ctx.set_features.fid);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_set_features_dword14));
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

static void dissect_nvme_get_features_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
                                      struct nvme_cmd_ctx *cmd_ctx)
{
    cmd_ctx->cmd_ctx.set_features.fid = tvb_get_uint8(cmd_tvb, 40);
    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_get_features_dword10));
    switch(cmd_ctx->cmd_ctx.set_features.fid) {
        case F_READ_REC_LEVEL_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_get_features_dword11_rrl)); break;
        case F_PRED_LAT_MODE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_get_features_dword11_plmc)); break;
        case F_PRED_LAT_MODE_WIND: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_get_features_dword11_plmw)); break;
        default: proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN); break;
    }
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_get_features_dword14));
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

static void dissect_nvme_rw_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    proto_item *ti, *dsm_tree, *item;
    uint8_t val;

    dissect_nvme_rwc_common_word_10_11_12_14_15(cmd_tvb, cmd_tree);

    ti = proto_tree_add_item(cmd_tree, hf_nvme_cmd_dsm, cmd_tvb, 52,
                             1, ENC_NA);
    dsm_tree = proto_item_add_subtree(ti, ett_data);

    val = tvb_get_uint8(cmd_tvb, 52) & 0x0f;
    item = proto_tree_add_item(dsm_tree, hf_nvme_cmd_dsm_access_freq, cmd_tvb,
                               52, 1, ENC_LITTLE_ENDIAN);
    proto_item_append_text(item, " %s",
                           val_to_str_const(val, dsm_acc_freq_tbl, "Reserved"));

    val = (tvb_get_uint8(cmd_tvb, 52) & 0x30) >> 4;
    item = proto_tree_add_item(dsm_tree, hf_nvme_cmd_dsm_access_lat, cmd_tvb,
                               52, 1, ENC_LITTLE_ENDIAN);
    proto_item_append_text(item, " %s",
                           val_to_str_const(val, dsm_acc_lat_tbl, "Reserved"));

    proto_tree_add_item(dsm_tree, hf_nvme_cmd_dsm_seq_req, cmd_tvb,
                        52, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(dsm_tree, hf_nvme_cmd_dsm_incompressible, cmd_tvb,
                        52, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_rsvd3, cmd_tvb,
                        53, 3, ENC_NA);
}

static const range_string sf_lbart_type_table[] = {
    { 0x0, 0x0, "General Purpose" },
    { 0x1, 0x1, "Filesystem" },
    { 0x2, 0x2, "RAID" },
    { 0x3, 0x3, "Cache" },
    { 0x4, 0x4, "Swap" },
    { 0x80, 0xFF, "Vendor Specific" },
    { 0, 0, NULL },
};

static void dissect_nvme_set_features_transfer_lbart(tvbuff_t *tvb, proto_tree *tree, unsigned off, unsigned len)
{
    proto_tree *grp;
    proto_item *ti;
    unsigned done = 0;
    while (len >= 64) {
        ti =  proto_tree_add_bytes_format_value(tree, hf_nvme_set_features_tr_lbart, tvb, done, 64, NULL, "LBA Range Structure %u", (done + off) / 64);
        grp =  proto_item_add_subtree(ti, ett_data);
        proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_type, tvb, done, 1, ENC_LITTLE_ENDIAN);
        add_group_mask_entry(tvb, grp, done+1, 1, ASPEC(hf_nvme_set_features_tr_lbart_attr));
        proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_rsvd0, tvb, done+2, 14, ENC_NA);
        proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_slba, tvb, done+16, 8, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_nlb, tvb, done+24, 8, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_guid, tvb, done+32, 16, ENC_NA);
        proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_rsvd1, tvb, done+48, 16, ENC_NA);
        len -= 64;
        done += 64;
    }
}

static void dissect_nvme_set_features_transfer_apst(tvbuff_t *tvb, proto_tree *tree, unsigned off, unsigned len)
{
    unsigned poff = 0;
    /* Non-Operational Power State Transition table: 32 entries * 8 bytes =
     * 256 bytes max.  Each entry's value is self-contained, but a nonzero
     * window offset moves where that 256-byte ceiling falls. */
    unsigned max_len = (off < 256) ? (256 - off) : 0;

    if (len > max_len)
        len = max_len;
    while (len >= 8) {
        add_group_mask_entry(tvb, tree, poff, 8, ASPEC(hf_nvme_set_features_tr_apst));
        len -= 8;
        poff += 8;
    }
}

static void dissect_nvme_set_features_transfer_tst(tvbuff_t *tvb, proto_tree *tree, unsigned off, unsigned len)
{
    unsigned rel;

    if (nvme_field_in_window(off, len, 0, 8, &rel))
        add_group_mask_entry(tvb, tree, rel, 8, ASPEC(hf_nvme_set_features_tr_tst));
}


static void dissect_nvme_set_features_transfer_plmc(tvbuff_t *tvb, proto_tree *tree, unsigned off, unsigned len)
{
    proto_tree *grp;
    proto_item *ti;
    unsigned rel;

    ti = proto_tree_add_item(tree, hf_nvme_set_features_tr_plmc, tvb, 0, len, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);
    if (nvme_field_in_window(off, len, 0, 2, &rel))
        add_group_mask_entry(tvb, grp, rel, 2, ASPEC(hf_nvme_set_features_tr_plmc_ee));
    if (nvme_field_in_window(off, len, 2, 30, &rel))
        proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_rsvd0, tvb, rel, 30, ENC_NA);
    if (nvme_field_in_window(off, len, 32, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_dtwinrt, tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 40, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_dtwinwt, tvb, rel, 8, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 48, 8, &rel))
        proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_dtwintt, tvb, rel, 8, ENC_LITTLE_ENDIAN);
    /* Trailing/remaining-length field: guard before subtracting so a short
     * or windowed transfer can't underflow `len` (this is exactly the
     * unsigned-subtraction bug the DOFST-windowing audit found here).
     * off > 56 means the whole window already lies inside this trailing
     * field, so it renders entirely from tvb position 0 (poff=0) rather
     * than being silently dropped. */
    {
        unsigned poff = (off <= 56) ? (56 - off) : 0;
        if (poff <= len && off <= 512) {
            /* Remaining room at tvb position poff is (512-off)-poff, not the
             * raw len -- an oversized/malformed len must not render bytes
             * past the structure's real 512-byte end (NVMe Base 2.3 Figure
             * 423) as "Reserved1". */
            unsigned max_len = (512 - off) - poff;
            unsigned rlen = len - poff;
            if (rlen > max_len)
                rlen = max_len;
            proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_rsvd1, tvb, poff, rlen, ENC_NA);
        }
    }
}

static void dissect_nvme_set_features_transfer_hbs(tvbuff_t *tvb, proto_tree *tree, unsigned off, unsigned len)
{
    proto_tree *grp;
    proto_item *ti;
    unsigned rel;

    ti = proto_tree_add_item(tree, hf_nvme_set_features_tr_hbs, tvb, 0, len, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);
    if (nvme_field_in_window(off, len, 0, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_set_features_tr_hbs_acre, tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 1, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_set_features_tr_hbs_etdas, tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 2, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_set_features_tr_hbs_lbafee, tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 3, 1, &rel))
        proto_tree_add_item(grp, hf_nvme_set_features_tr_hbs_hdisns, tvb, rel, 1, ENC_LITTLE_ENDIAN);
    if (nvme_field_in_window(off, len, 4, 2, &rel))
        add_group_mask_entry(tvb, grp, rel, 2, ASPEC(hf_nvme_set_features_tr_hbs_cdfe));
    /* off > 6 means the whole window already lies inside this trailing
     * field, so it renders entirely from tvb position 0 (poff=0) rather
     * than being silently dropped. */
    {
        unsigned poff = (off <= 6) ? (6 - off) : 0;
        if (poff <= len && off <= 512) {
            /* Remaining room at tvb position poff is (512-off)-poff, not the
             * raw len -- an oversized/malformed len must not render bytes
             * past the structure's real 512-byte end (NVMe Base 2.3 Figure
             * 426) as "Reserved". */
            unsigned max_len = (512 - off) - poff;
            unsigned rlen = len - poff;
            if (rlen > max_len)
                rlen = max_len;
            proto_tree_add_item(grp, hf_nvme_set_features_tr_hbs_rsvd, tvb, poff, rlen, ENC_NA);
        }
    }
}

/* Host Metadata data structure, shared by the (Enhanced) Controller Metadata
 * and Namespace Metadata features (7Dh/7Eh/7Fh).
 * A 4 KiB structure: a 1-byte NMED count, a reserved byte, then a list of
 * variable-length Metadata Element Descriptors (a 4-byte header carrying
 * ET/ER/ELEN, followed by ELEN bytes of UTF-8 Element Value). */
static void dissect_nvme_host_metadata(tvbuff_t *tvb, proto_tree *tree, struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
{
    const range_string *et_rs = (cmd_ctx->cmd_ctx.set_features.fid == F_NS_METADATA)
        ? host_metadata_ns_et : host_metadata_ctrl_et;
    proto_tree *grp;
    proto_item *ti;
    unsigned pos;
    uint32_t nmed, i;

    ti = proto_tree_add_item(tree, hf_nvme_set_features_tr_hmd, tvb, 0, len, ENC_NA);
    grp = proto_item_add_subtree(ti, ett_data);

    /* The NMED header is only present at the start of the structure.  Over a
     * windowed transfer (off > 0) the chunk begins mid-list and cannot be
     * realigned, so show it raw rather than misparse. */
    if (off != 0 || len < 2) {
        proto_tree_add_item(grp, hf_nvme_gen_data, tvb, 0, len, ENC_NA);
        return;
    }

    proto_tree_add_item_ret_uint(grp, hf_nvme_set_features_tr_hmd_nmed, tvb, 0, 1, ENC_LITTLE_ENDIAN, &nmed);
    proto_tree_add_item(grp, hf_nvme_set_features_tr_hmd_rsvd, tvb, 1, 1, ENC_NA);
    pos = 2;

    for (i = 0; i < nmed; i++) {
        proto_tree *med;
        proto_item *med_ti, *et_ti;
        uint32_t et, elen;

        /* Stop cleanly if the descriptor header or value runs past the
         * available data (a DLEN-truncated or windowed chunk). */
        if (pos + 4 > len)
            break;
        elen = tvb_get_uint16(tvb, pos + 2, ENC_LITTLE_ENDIAN);
        if (pos + 4 + elen > len)
            break;

        med_ti = proto_tree_add_item(grp, hf_nvme_set_features_tr_hmd_med, tvb, pos, 4 + elen, ENC_NA);
        proto_item_set_text(med_ti, "Metadata Element Descriptor %u", i);
        med = proto_item_add_subtree(med_ti, ett_data);

        et_ti = proto_tree_add_item_ret_uint(med, hf_nvme_set_features_tr_hmd_med_et, tvb, pos, 4, ENC_LITTLE_ENDIAN, &et);
        proto_item_append_text(et_ti, " (%s)", rval_to_str_const(et, et_rs, "Unknown"));
        proto_tree_add_item(med, hf_nvme_set_features_tr_hmd_med_er, tvb, pos, 4, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(med, hf_nvme_set_features_tr_hmd_med_elen, tvb, pos, 4, ENC_LITTLE_ENDIAN);
        if (elen)
            proto_tree_add_item(med, hf_nvme_set_features_tr_hmd_med_eval, tvb, pos + 4, elen, ENC_UTF_8);
        pos += 4 + elen;
    }
}

static void dissect_nvme_set_features_transfer(tvbuff_t *tvb, proto_tree *tree, struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
{
    switch(cmd_ctx->cmd_ctx.set_features.fid) {
        case F_LBA_RANGE_TYPE:
            dissect_nvme_set_features_transfer_lbart(tvb, tree, off, len);
            break;
        case F_AUTO_PS_TRANSITION:
            dissect_nvme_set_features_transfer_apst(tvb, tree, off, len);
            break;
        case F_TIMESTAMP:
            dissect_nvme_set_features_transfer_tst(tvb, tree, off, len);
            break;
        case F_PRED_LAT_MODE_CONF:
            dissect_nvme_set_features_transfer_plmc(tvb, tree, off, len);
            break;
        case F_HOST_BEHV_SUPPORT:
            dissect_nvme_set_features_transfer_hbs(tvb, tree, off, len);
            break;
        case F_ENH_CTRL_METADATA:
        case F_CTRL_METADATA:
        case F_NS_METADATA:
            dissect_nvme_host_metadata(tvb, tree, cmd_ctx, off, len);
            break;
        default:
            proto_tree_add_bytes_format_value(tree, hf_nvme_gen_data, tvb, 0, len, NULL,
                (cmd_ctx->opcode == NVME_AQ_OPC_SET_FEATURES) ? "Unhandled Set Features Transfer" : "Unhandled Get Features Transfer");
            break;
    }
}


void nvme_update_transfer_request(packet_info *pinfo, struct nvme_cmd_ctx *cmd, struct nvme_q_ctx *q_ctx)
{
    if (cmd->fabric) {
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF Data Request for %s",
            rval_to_str_const(cmd->cmd_ctx.fabric_cmd.fctype, fctype_tbl, "Unknown Command"));
        return;
    }
    if (!q_ctx->qid) {
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF Data Request for %s", get_aq_opcode_name(cmd->opcode));
        if (cmd->opcode == NVME_AQ_OPC_IDENTIFY)
            col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(cmd->cmd_ctx.cmd_identify.cns, cns_table, "Unknown"));
        else if (cmd->opcode == NVME_AQ_OPC_GET_LOG_PAGE)
            col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", get_logpage_name(cmd->cmd_ctx.get_logpage.lid));
    } else {
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF Data Request for %s", get_ioq_opcode_name(cmd->opcode));
    }
}

static void dissect_nvme_security_data(tvbuff_t *tvb, packet_info *pinfo,
                                       proto_tree *tree,
                                       struct nvme_cmd_ctx *cmd_ctx,
                                       unsigned off, unsigned len);

bool
nvme_dissect_admin_data_resp(tvbuff_t *nvme_tvb, packet_info *pinfo,
                             proto_tree *cmd_tree, struct nvme_cmd_ctx *cmd_ctx,
                             unsigned off, unsigned len)
{
    switch (cmd_ctx->opcode) {
    case NVME_AQ_OPC_IDENTIFY:
        dissect_nvme_identify_resp(nvme_tvb, pinfo, cmd_tree, cmd_ctx, off, len);
        return true;
    case NVME_AQ_OPC_GET_LOG_PAGE:
        dissect_nvme_get_logpage_resp(nvme_tvb, pinfo, cmd_tree, cmd_ctx, off, len);
        return true;
    case NVME_AQ_OPC_SET_FEATURES:
    case NVME_AQ_OPC_GET_FEATURES:
        dissect_nvme_set_features_transfer(nvme_tvb, cmd_tree, cmd_ctx, off, len);
        return true;
    case NVME_AQ_OPC_SECURITY_SEND:
    case NVME_AQ_OPC_SECURITY_RECV:
        dissect_nvme_security_data(nvme_tvb, pinfo, cmd_tree, cmd_ctx, off, len);
        return true;
    default:
        return false;
    }
}

void
dissect_nvme_data_response(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *root_tree,
                 struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx, unsigned len, bool is_inline)
{
    proto_tree *cmd_tree;
    proto_item *ti;
    const char *str_opcode;
    uint32_t off;
    unsigned avail;
    bool over_declared;

    /* `len` is the transport's wire-declared response length: over NVMe/TCP it
     * is the C2HData PDU's DATAL field, taken straight off the wire by
     * dissect_nvme_tcp_data_pdu() (packet-nvme-tcp.c) with no check against the
     * bytes the PDU actually carries, while nvme_tvb is only a
     * tvb_new_subset_remaining().  Every decoder below bounds its fields on
     * `len`, so a DATAL larger than the PDU walks off the end of the tvb and
     * the resulting exception replaces the whole frame's dissection with
     * [Malformed Packet].  Clamp once, here, rather than in each per-structure
     * decoder.
     *
     * The clamp is to the *reported* length, not the captured length, so the
     * two cases stay distinguishable:
     *
     *   - a DATAL larger than the PDU is a lie about data that was never sent;
     *     clamping to the reported length keeps every decoder in bounds and no
     *     exception is raised.
     *   - a snaplen-sliced capture still has an honest DATAL, so `len` stays
     *     larger than what was captured, the decoders read into the missing
     *     bytes and throw BoundsError, and Wireshark reports
     *     [Packet size limited during capture] as it does for every other
     *     protocol.  Clamping to tvb_captured_length() would silently hide
     *     that.
     *
     * NVMe-MI is unaffected either way (packet-nvme-mi-admin.c calls
     * nvme_dissect_admin_data_resp() directly, sized from
     * tvb_reported_length()) and NVMe/RDMA already passes
     * tvb_reported_length(). */
    avail = tvb_reported_length(nvme_tvb);
    over_declared = (len > avail);
    if (over_declared)
        len = avail;

    off = (PINFO_FD_VISITED(pinfo)) ? nvme_lookup_data_tr_off(q_ctx, pinfo->num) : cmd_ctx->tr_bytes;

    col_set_str(pinfo->cinfo, COL_PROTOCOL, "NVMe");
    ti = proto_tree_add_item(root_tree, proto_nvme, nvme_tvb, 0,
                             len, ENC_NA);
    cmd_tree = proto_item_add_subtree(ti, ett_data);
    /* The transport asked for more bytes than the frame reports.  This is not
     * capture truncation -- tvb_reported_length() is the on-the-wire length,
     * unaffected by the snaplen -- so the transport header and the frame
     * genuinely disagree. */
    if (over_declared)
        expert_add_info(pinfo, ti, &ei_nvme_data_len_exceeds_frame);
    if (q_ctx->qid) { //IOQ
        str_opcode = get_ioq_opcode_name(cmd_ctx->opcode);
      } else { //AQ
        str_opcode = get_aq_opcode_name(cmd_ctx->opcode);
        if (!nvme_dissect_admin_data_resp(nvme_tvb, pinfo, cmd_tree, cmd_ctx, off, len)) {
            proto_tree_add_bytes_format_value(cmd_tree, hf_nvme_gen_data,
                                              nvme_tvb, 0, len, NULL,
                                              "%s, offset %u", str_opcode, off);
        }
    }
    if (is_inline)
        return;
    col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF Data for %s", str_opcode);
    if (!q_ctx->qid) {
        if (cmd_ctx->opcode == NVME_AQ_OPC_IDENTIFY)
            col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s, offset %u", val_to_str_const(cmd_ctx->cmd_ctx.cmd_identify.cns, cns_table, "Unknown"), off);
        else if (cmd_ctx->opcode == NVME_AQ_OPC_GET_LOG_PAGE)
            col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s, offset %u", get_logpage_name(cmd_ctx->cmd_ctx.get_logpage.lid), off);
    } else {
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, ", ", "offset %u", off);
    }
}

static void add_nvme_qid(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "%x (%s)", val, val ? "IOQ" : "AQ");
}

static void add_zero_base(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "%u", val+1);
}

static
void dissect_nvmeof_fabric_connect_cmd(proto_tree *cmd_tree, packet_info *pinfo, tvbuff_t *cmd_tvb,
        struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd, unsigned off)
{
    uint32_t qid;

    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_rsvd1, cmd_tvb,
                        5+off, 19, ENC_NA);
    dissect_nvme_cmd_sgl(cmd_tvb, cmd_tree, hf_nvmeof_cmd_connect_sgl1,
        q_ctx, cmd, off, PINFO_FD_VISITED(pinfo));
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_recfmt, cmd_tvb,
                        40+off, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item_ret_uint(cmd_tree, hf_nvmeof_cmd_connect_qid, cmd_tvb,
                        42+off, 2, ENC_LITTLE_ENDIAN, &qid);
    cmd->cmd_ctx.fabric_cmd.cnct.qid = qid;
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_sqsize, cmd_tvb,
                        44+off, 2, ENC_LITTLE_ENDIAN);

    add_group_mask_entry(cmd_tvb, cmd_tree, 46+off, 1, ASPEC(hf_nvmeof_cmd_connect_cattr));
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_rsvd2, cmd_tvb,
                        47+off, 1, ENC_NA);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_kato, cmd_tvb,
                        48+off, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_rsvd3, cmd_tvb,
                        52+off, 12, ENC_NA);
}

static
void dissect_nvmeof_fabric_auth_cmd(proto_tree *cmd_tree, packet_info *pinfo, tvbuff_t *cmd_tvb,
        struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd, unsigned off)
{
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_rsdv1, cmd_tvb,
                        5+off, 19, ENC_NA);
    dissect_nvme_cmd_sgl(cmd_tvb, cmd_tree, hf_nvmeof_cmd_auth_sgl1,
        q_ctx, cmd, off, PINFO_FD_VISITED(pinfo));
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_rsdv2, cmd_tvb,
                        40+off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_spsp0, cmd_tvb,
                        41+off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_spsp1, cmd_tvb,
                        42+off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_secp, cmd_tvb,
                        43+off, 1, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_al, cmd_tvb,
                        44+off, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_rsdv3, cmd_tvb,
                        48+off, 16, ENC_NA);
}

static void dissect_nvme_fabric_disconnect_cmd(proto_tree *cmd_tree, tvbuff_t *cmd_tvb,  unsigned off)
{
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_disconnect_rsvd0, cmd_tvb,
                        5+off, 35, ENC_NA);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_disconnect_recfmt, cmd_tvb,
                        40+off, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_disconnect_rsvd1, cmd_tvb,
                        42+off, 22, ENC_NA);
}

static void dissect_nvme_fabric_prop_cmd_common(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, unsigned off)
{
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_get_set_rsvd0, cmd_tvb,
                        5+off, 35, ENC_NA);

    add_group_mask_entry(cmd_tvb, cmd_tree, 40+off, 1, ASPEC(hf_nvmeof_cmd_prop_get_set_attrib));

    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_get_set_rsvd1, cmd_tvb,
                        41+off, 3, ENC_NA);

    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_get_set_offset, cmd_tvb,
                        44+off, 4, ENC_LITTLE_ENDIAN);
}

static void dissect_nvmeof_fabric_prop_get_cmd(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd, unsigned off)
{
    cmd->cmd_ctx.fabric_cmd.prop_get.offset = tvb_get_uint8(cmd_tvb, 44+off);
    dissect_nvme_fabric_prop_cmd_common(cmd_tree, cmd_tvb, off);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_get_rsvd2, cmd_tvb,
                        48+off, 16, ENC_NA);
}

static void add_500ms_units(char *result, uint32_t val)
{
    snprintf(result, ITEM_LABEL_LENGTH, "%x (%u ms)", val, val * 500);
}

static void add_ccap_css(char *result, uint32_t val)
{
    /* Base 2.3 Figure 36, CAP.CSS (bits 44:37) is a bitmask, not an enum:
     * bit 7 NOIOCSS, bit 6 IOCSS, bits 5:1 Reserved, bit 0 NCSS. */
    char buf[64] = "";
    bool have_bit = false;

    if (val & 0x80) {
        (void)g_strlcat(buf, "NOIOCSS", sizeof(buf));
        have_bit = true;
    }
    if (val & 0x40) {
        if (have_bit)
            (void)g_strlcat(buf, ", ", sizeof(buf));
        (void)g_strlcat(buf, "IOCSS", sizeof(buf));
        have_bit = true;
    }
    if (val & 0x1) {
        if (have_bit)
            (void)g_strlcat(buf, ", ", sizeof(buf));
        (void)g_strlcat(buf, "NCSS", sizeof(buf));
        have_bit = true;
    }
    if (!have_bit)
        (void)g_strlcat(buf, "None", sizeof(buf));

    snprintf(result, ITEM_LABEL_LENGTH, "%x (%s)", val, buf);
}

static void dissect_nvmeof_fabric_prop_data(proto_tree *tree, tvbuff_t *tvb, unsigned off, unsigned prop_off, uint8_t attr)
{
    proto_item *ti, *grp;
    ti = proto_tree_add_item(tree, hf_nvmeof_prop_get_set_data, tvb, off, 8, ENC_NA);
    grp =  proto_item_add_subtree(ti, ett_data);
    switch(prop_off) {
        case 0x0:  add_group_mask_entry(tvb, grp, off, 8, ASPEC(hf_nvmeof_prop_get_ccap)); attr=1; break;
        case 0x8:  add_group_mask_entry(tvb, grp, off, 4, ASPEC(hf_nvmeof_prop_get_vs)); attr=0; break;
        case 0x14: add_group_mask_entry(tvb, grp, off, 4, ASPEC(hf_nvmeof_prop_get_set_cc)); attr=0; break;
        case 0x1c: add_group_mask_entry(tvb, grp, off, 4, ASPEC(hf_nvmeof_prop_get_set_csts)); attr=0; break;
        case 0x20: add_group_mask_entry(tvb, grp, off, 4, ASPEC(hf_nvmeof_prop_get_set_nssr)); attr=0; break;
        default:
        {
            if (attr == 0)
            proto_tree_add_item(grp, hf_nvmeof_prop_get_set_data_4B, tvb,
                            off, 4, ENC_LITTLE_ENDIAN);
            else
                proto_tree_add_item(grp, hf_nvmeof_prop_get_set_data_8B, tvb,
                            off, 8, ENC_LITTLE_ENDIAN);
            break;
        }
    }
    if (attr == 0)
        proto_tree_add_item(grp, hf_nvmeof_prop_get_set_data_4B_rsvd, tvb,
                        off+4, 4, ENC_LITTLE_ENDIAN);
}
static void dissect_nvmeof_fabric_prop_set_cmd(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd, unsigned off)
{
    uint8_t attr;
    uint32_t prop_off;

    dissect_nvme_fabric_prop_cmd_common(cmd_tree, cmd_tvb, off);
    attr = tvb_get_uint8(cmd_tvb, 40+off) & 0x7;
    prop_off = tvb_get_uint32(cmd_tvb, 44+off, ENC_LITTLE_ENDIAN);
    cmd->cmd_ctx.fabric_cmd.prop_get.offset = prop_off;
    dissect_nvmeof_fabric_prop_data(cmd_tree, cmd_tvb, 48+off, prop_off, attr);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_set_rsvd, cmd_tvb,
                        56+off, 8, ENC_NA);
}

static void dissect_nvmeof_fabric_generic_cmd(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, unsigned off)
{
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_generic_rsvd1, cmd_tvb,
                        5+off, 35, ENC_NA);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_generic_field, cmd_tvb,
                        40+off, 24, ENC_NA);
}

void dissect_nvmeof_fabric_cmd(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *nvme_tree,
        struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd, unsigned off, bool link_data_req)
{
    proto_tree *cmd_tree;
    proto_item *ti;
    uint8_t fctype;
    uint32_t prop_off;

    fctype = tvb_get_uint8(nvme_tvb, 4+off);
    cmd->cmd_ctx.fabric_cmd.fctype = fctype;

    ti = proto_tree_add_item(nvme_tree, hf_nvmeof_cmd, nvme_tvb, off,
                             NVME_CMD_SIZE, ENC_NA);
    cmd_tree = proto_item_add_subtree(ti, ett_data);

    proto_tree_add_bytes_format(cmd_tree, hf_nvmeof_cmd_opc, nvme_tvb, off, 1, NULL, "Opcode: 0x%x (Fabric Command)",
                                NVME_FABRIC_OPC);
    col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF %s", rval_to_str_const(fctype, fctype_tbl, "Unknown Command"));
    prop_off = tvb_get_uint32(nvme_tvb, 44+off, ENC_LITTLE_ENDIAN);

    cmd->opcode = NVME_FABRIC_OPC;
    if (link_data_req)
        nvme_publish_to_data_req_link(cmd_tree, nvme_tvb, hf_nvmeof_data_req, cmd);
    nvme_publish_to_data_tr_links(cmd_tree, nvme_tvb, hf_nvmeof_data_tr, cmd);
    nvme_publish_to_cqe_link(cmd_tree, nvme_tvb, hf_nvmeof_cqe_pkt, cmd);

    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_rsvd, nvme_tvb,
                        1+off, 1, ENC_NA);
    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_cid, nvme_tvb,
                        2+off, 2, ENC_LITTLE_ENDIAN);

    proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_fctype, nvme_tvb,
                        4+off, 1, ENC_LITTLE_ENDIAN);
    switch(fctype) {
    case NVME_FCTYPE_CONNECT:
        dissect_nvmeof_fabric_connect_cmd(cmd_tree, pinfo, nvme_tvb, q_ctx, cmd, off);
        break;
    case NVME_FCTYPE_PROP_GET:
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(prop_off, prop_offset_tbl, "Unknown Property"));
        dissect_nvmeof_fabric_prop_get_cmd(cmd_tree, nvme_tvb, cmd, off);
        break;
    case NVME_FCTYPE_PROP_SET:
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(prop_off, prop_offset_tbl, "Unknown Property"));
        dissect_nvmeof_fabric_prop_set_cmd(cmd_tree, nvme_tvb, cmd, off);
        break;
    case NVME_FCTYPE_DISCONNECT:
        dissect_nvme_fabric_disconnect_cmd(cmd_tree, nvme_tvb, off);
        break;
    case NVME_FCTYPE_AUTH_RECV:
    case NVME_FCTYPE_AUTH_SEND:
        dissect_nvmeof_fabric_auth_cmd(cmd_tree, pinfo, nvme_tvb, q_ctx, cmd, off);
        break;
    default:
        dissect_nvmeof_fabric_generic_cmd(cmd_tree, nvme_tvb, off);
        break;
    }
}

static void
dissect_nvmeof_fabric_connect_cmd_data(tvbuff_t *data_tvb, proto_tree *data_tree,
                                     unsigned pkt_off, unsigned off, unsigned len)
{
    if (!off) {
        CHECK_STOP_PARSE(0, 16);
        proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_hostid, data_tvb,
                            pkt_off, 16, ENC_NA);
    }
    if (off <= 16) {
        CHECK_STOP_PARSE(16, 2);
        proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_cntlid, data_tvb,
                            pkt_off + 16 - off, 2, ENC_LITTLE_ENDIAN);
    }
    if (off <= 18) {
        CHECK_STOP_PARSE(18, 238);
        proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_rsvd0, data_tvb,
                            pkt_off + 18 - off, 238, ENC_NA);
    }
    if (off <= 256) {
        CHECK_STOP_PARSE(256, 256);
        proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_subnqn, data_tvb,
                            pkt_off + 256 - off, 256, ENC_ASCII);
    }
    if (off <= 512) {
        CHECK_STOP_PARSE(512, 256);
        proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_hostnqn, data_tvb,
                            pkt_off + 512 - off, 256, ENC_ASCII);
    }
    if (off <= 768) {
        CHECK_STOP_PARSE(768, 256);
        proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_rsvd1, data_tvb,
                            pkt_off + 768 - off, 256, ENC_NA);
    }
}

void
dissect_nvmeof_cmd_data(tvbuff_t *data_tvb, packet_info *pinfo, proto_tree *data_tree,
                                 unsigned pkt_off, struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd, unsigned len)
{
    uint32_t tr_off = (PINFO_FD_VISITED(pinfo)) ? nvme_lookup_data_tr_off(q_ctx, pinfo->num) : cmd->tr_bytes;

    if (!pkt_off) {
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeoF Data for %s, offset %u",
            rval_to_str_const(cmd->cmd_ctx.fabric_cmd.fctype, fctype_tbl, "Unknown Command"), tr_off);
    }
    if (cmd->cmd_ctx.fabric_cmd.fctype == NVME_FCTYPE_CONNECT && len >= 768)
        dissect_nvmeof_fabric_connect_cmd_data(data_tvb, data_tree, pkt_off, tr_off, len);
}

static void
dissect_nvmeof_status_prop_get(proto_tree *cqe_tree, tvbuff_t *cqe_tvb, struct nvme_cmd_ctx *cmd, unsigned off)
{
    dissect_nvmeof_fabric_prop_data(cqe_tree, cqe_tvb, off, cmd->cmd_ctx.fabric_cmd.prop_get.offset, 1);
}

static void
dissect_nvmeof_cqe_status_8B(proto_tree *cqe_tree, tvbuff_t *cqe_tvb,
                                  struct nvme_cmd_ctx *cmd, unsigned off)
{
    switch (cmd->cmd_ctx.fabric_cmd.fctype) {
    case NVME_FCTYPE_CONNECT:
        proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_connect_cntlid, cqe_tvb,
                            0+off, 2, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_connect_authreq, cqe_tvb,
                            2+off, 2, ENC_LITTLE_ENDIAN);
        proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_connect_rsvd, cqe_tvb,
                            4+off, 4, ENC_NA);
        break;
    case NVME_FCTYPE_PROP_GET:
        dissect_nvmeof_status_prop_get(cqe_tree, cqe_tvb, cmd, off);
        break;
    case NVME_FCTYPE_PROP_SET:
        proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_prop_set_rsvd, cqe_tvb,
                            0+off, 8, ENC_NA);
        break;
    default:
        proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_sts, cqe_tvb,
                            0+off, 8, ENC_LITTLE_ENDIAN);
        break;
    };
}


const char *get_nvmeof_cmd_string(uint8_t fctype)
{
    return rval_to_str_const(fctype, fctype_tbl, "Unknown Fabric Command");
}

static void dissect_nvme_cqe_common(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *cqe_tree, unsigned off, bool nvmeof);

void
dissect_nvmeof_fabric_cqe(tvbuff_t *nvme_tvb, packet_info *pinfo,
                        proto_tree *nvme_tree,
                        struct nvme_cmd_ctx *cmd, unsigned off)
{
    proto_tree *cqe_tree;
    proto_item *ti;
    uint8_t fctype = cmd->cmd_ctx.fabric_cmd.fctype;

    ti = proto_tree_add_item(nvme_tree, hf_nvmeof_cqe, nvme_tvb,
                             0+off, NVME_CQE_SIZE, ENC_NA);

    if (fctype != NVME_FCTYPE_PROP_GET && fctype != NVME_FCTYPE_PROP_SET)
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF CQE for %s", rval_to_str_const(fctype, fctype_tbl, "Unknown Command"));
    else
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF CQE for Property %s %s",
                            (fctype == NVME_FCTYPE_PROP_GET) ? "Get" : "Set",
                            val_to_str_const(cmd->cmd_ctx.fabric_cmd.prop_get.offset, prop_offset_tbl, "Unknown Property"));

    proto_item_append_text(ti, " (For Cmd: %s)", rval_to_str_const(fctype, fctype_tbl, "Unknown Cmd"));

    cqe_tree = proto_item_add_subtree(ti, ett_data);

    nvme_publish_to_cmd_link(cqe_tree, nvme_tvb, hf_nvmeof_cmd_pkt,
                                 cmd);
    nvme_publish_cmd_latency(cqe_tree, cmd, hf_nvmeof_cmd_latency);

    dissect_nvmeof_cqe_status_8B(cqe_tree, nvme_tvb, cmd, off);

    dissect_nvme_cqe_common(nvme_tvb, pinfo, cqe_tree, off, true);
}

static void dissect_nvme_unhandled_cmd(tvbuff_t *nvme_tvb, proto_tree *cmd_tree)
{
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword10, nvme_tvb, 40, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, nvme_tvb, 44, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, nvme_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, nvme_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, nvme_tvb, 56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, nvme_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

/* Format NVM – Secure Erase Settings (SES). */
static const value_string fmt_nvm_ses_tbl[] = {
    { 0x0, "No secure erase operation requested" },
    { 0x1, "User Data Erase" },
    { 0x2, "Cryptographic Erase" },
    { 0, NULL }
};

static void dissect_nvme_format_nvm_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_format_nvm_dword10));
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, cmd_tvb, 56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

/* Firmware Commit – Commit Action (CA). */
static const value_string fw_commit_ca_tbl[] = {
    { 0x0, "Replace image in slot, do not activate" },
    { 0x1, "Replace image in slot, activate at next reset" },
    { 0x2, "Activate existing image in slot at next reset" },
    { 0x3, "Replace image in slot and activate immediately" },
    { 0x6, "Replace Boot Partition specified by BPID" },
    { 0x7, "Mark Boot Partition in BPID active, update BPINFO.ABPID" },
    { 0, NULL }
};

static void dissect_nvme_fw_commit_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_fw_commit_dword10));
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, cmd_tvb, 56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

static void dissect_nvme_fw_download_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    proto_tree_add_item(cmd_tree, hf_nvme_fw_download_numd, cmd_tvb, 40, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_fw_download_ofst, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, cmd_tvb, 56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

/* Device Self-test – Self-test Code (STC). */
static const value_string self_test_stc_tbl[] = {
    { 0x1, "Short device self-test" },
    { 0x2, "Extended device self-test" },
    { 0x3, "Host-Initiated Refresh" },
    { 0xe, "Vendor specific" },
    { 0xf, "Abort device self-test" },
    { 0, NULL }
};

static void dissect_nvme_self_test_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_self_test_dword10));
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, cmd_tvb, 56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

/* Lockdown – Scope (SCP) / Interface (IFC). */
static const value_string lockdown_scp_tbl[] = {
    { 0x0, "Admin command opcode" },
    { 0x2, "Set Features Feature Identifier" },
    { 0x3, "Management Interface Command Set opcode" },
    { 0x4, "PCIe Command Set opcode" },
    { 0, NULL }
};

static const value_string lockdown_ifc_tbl[] = {
    { 0x0, "Admin Submission Queue" },
    { 0x1, "Admin Submission Queue and out-of-band Management Endpoint" },
    { 0x2, "Out-of-band Management Endpoint" },
    { 0, NULL }
};

static void dissect_nvme_lockdown_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_lockdown_dword10));
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_lockdown_dword14));
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

/* Sanitize – Sanitize Action (SANACT). */
static const value_string sanitize_act_tbl[] = {
    { 0x1, "Exit Failure Mode" },
    { 0x2, "Block Erase" },
    { 0x3, "Overwrite" },
    { 0x4, "Crypto Erase" },
    { 0x5, "Exit Media Verification State" },
    { 0, NULL }
};

static void dissect_nvme_sanitize_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
{
    add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_sanitize_dword10));
    proto_tree_add_item(cmd_tree, hf_nvme_sanitize_ovrpat, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, cmd_tvb, 56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

/* Security Protocol (SECP), Security Send/Receive Command Dword 10.  Values
 * are assigned by SPC-5; the commonly used identifiers are named here. */
static const range_string security_secp_tbl[] = {
    { 0x00, 0x00, "Security Protocol Information" },
    { 0x01, 0x01, "TCG Storage - SP 1" },
    { 0x02, 0x02, "TCG Storage - SP 2" },
    { 0x03, 0x03, "TCG Storage - SP 3" },
    { 0x04, 0x04, "TCG Storage - SP 4" },
    { 0x05, 0x05, "TCG Storage - SP 5" },
    { 0x06, 0x06, "TCG Storage - SP 6" },
    { 0xE9, 0xE9, "NVMe over Fabrics Authentication" },
    { 0xEA, 0xEA, "NVMe (RPMB / CDP Authentication)" },
    { 0xEE, 0xEE, "IEEE 1667" },
    { 0xF0, 0xFF, "Vendor Specific" },
    { 0, 0, NULL }
};

/* Security Send Command Dword 10 and Security Receive Command Dword 10
 * share an identical layout: SECP/SPSP1/SPSP0/NSSF.
 * The SECP and SPSP selectors are saved in cmd_ctx so the data payload
 * (request data for Send, response data for Receive) can be dispatched to
 * the matching security-protocol dissector. */
static void dissect_nvme_security_dword10(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
                                          struct nvme_cmd_ctx *cmd_ctx)
{
    const unsigned dw10_off = 40;
    uint32_t dw10 = tvb_get_uint32(cmd_tvb, dw10_off, ENC_LITTLE_ENDIAN);

    add_group_mask_entry(cmd_tvb, cmd_tree, dw10_off, 4, ASPEC(hf_nvme_security_dword10));
    cmd_ctx->cmd_ctx.security.secp = (uint8_t)(dw10 >> 24);
    /* SPSP1 (bits 23:16) is the high byte of the SP Specific value, SPSP0
     * (bits 15:08) the low byte, so bits 23:8 read as one field. */
    cmd_ctx->cmd_ctx.security.spsp = (uint16_t)((dw10 >> 8) & 0xffff);
}

static void dissect_nvme_security_send_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
                                           struct nvme_cmd_ctx *cmd_ctx)
{
    dissect_nvme_security_dword10(cmd_tvb, cmd_tree, cmd_ctx);
    proto_tree_add_item_ret_uint(cmd_tree, hf_nvme_security_send_dword11_tl, cmd_tvb, 44, 4,
                                 ENC_LITTLE_ENDIAN, &cmd_ctx->cmd_ctx.security.xfer_len);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, cmd_tvb, 56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

static void dissect_nvme_security_recv_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
                                           struct nvme_cmd_ctx *cmd_ctx)
{
    dissect_nvme_security_dword10(cmd_tvb, cmd_tree, cmd_ctx);
    proto_tree_add_item_ret_uint(cmd_tree, hf_nvme_security_recv_dword11_al, cmd_tvb, 44, 4,
                                 ENC_LITTLE_ENDIAN, &cmd_ctx->cmd_ctx.security.xfer_len);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, cmd_tvb, 56, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
}

/* Security Protocol Information (SECP 00h), SPC-5 7.7.1: discovery data
 * returned by Security Receive only, all fields big-endian.  SPSP 0000h
 * returns the Supported Security Protocols List (6 reserved bytes, a 2-byte
 * list length, then 1-byte protocol identifiers); SPSP 0001h returns
 * Certificate Data (2 reserved bytes, a 2-byte length, then the certificate
 * bytes, not parsed further).  Lengths are clamped to the payload.  Returns
 * false for other SPSP values or truncated headers so the caller can fall
 * back to the raw blob. */
static bool dissect_nvme_security_info_resp(tvbuff_t *tvb, proto_tree *tree,
                                            uint16_t spsp, unsigned len)
{
    proto_item *ti;
    proto_tree *grp;
    uint32_t plen;
    unsigned i;

    if (spsp == 0x0000) {
        if (len < 8)
            return false;
        ti = proto_tree_add_item(tree, hf_nvme_security_info, tvb, 0, len, ENC_NA);
        grp = proto_item_add_subtree(ti, ett_data);
        proto_tree_add_item(grp, hf_nvme_security_info_rsvd, tvb, 0, 6, ENC_NA);
        proto_tree_add_item_ret_uint(grp, hf_nvme_security_info_list_len,
                                     tvb, 6, 2, ENC_BIG_ENDIAN, &plen);
        if (plen > len - 8)
            plen = len - 8;
        for (i = 0; i < plen; i++)
            proto_tree_add_item(grp, hf_nvme_security_info_protocol, tvb, 8 + i, 1, ENC_BIG_ENDIAN);
        return true;
    }
    if (spsp == 0x0001) {
        if (len < 4)
            return false;
        ti = proto_tree_add_item(tree, hf_nvme_security_info, tvb, 0, len, ENC_NA);
        grp = proto_item_add_subtree(ti, ett_data);
        proto_tree_add_item(grp, hf_nvme_security_info_rsvd, tvb, 0, 2, ENC_NA);
        proto_tree_add_item_ret_uint(grp, hf_nvme_security_info_cert_len,
                                     tvb, 2, 2, ENC_BIG_ENDIAN, &plen);
        if (plen > len - 4)
            plen = len - 4;
        if (plen)
            proto_tree_add_item(grp, hf_nvme_security_info_cert_data, tvb, 4, plen, ENC_NA);
        return true;
    }
    return false;
}

/* The Security Send request data and Security Receive response data are
 * Security Protocol specific (SPC-5), opaque at the NVMe layer.  SECP 00h
 * (Security Protocol Information) response data is decoded here; other
 * protocols dispatch to a registered security-protocol dissector (e.g. TCG
 * Storage for SECP 01h/02h) via the "nvme.security.secp" table.  Payloads
 * for protocols without a registered dissector, empty payloads, and windows
 * that do not hold the complete protocol structure fall back to a labeled
 * byte blob.  A window is only handed on when it starts at offset 0 (a later
 * window cannot be re-aligned to the start of the structure) and is not known
 * to be short: Security Send Dword 11 (Transfer Length) is the exact payload
 * size, so a first window smaller than it is a partial transfer and would
 * make the protocol dissector flag the frame as malformed.  Security Receive
 * Dword 11 (Allocation Length) is only an upper bound - the controller may
 * return less - so a short window there is indistinguishable from a complete
 * short response and is still dispatched, as is any payload whose request
 * (and hence Dword 11) was not captured. */
static void dissect_nvme_security_data(tvbuff_t *tvb, packet_info *pinfo,
                                       proto_tree *tree,
                                       struct nvme_cmd_ctx *cmd_ctx,
                                       unsigned off, unsigned len)
{
    bool is_send = (cmd_ctx->opcode == NVME_AQ_OPC_SECURITY_SEND);
    uint32_t xfer_len = cmd_ctx->cmd_ctx.security.xfer_len;
    bool partial = is_send && xfer_len != 0 && len < xfer_len;

    if (off == 0 && len > 0 && !partial) {
        struct nvme_security_info sec = {
            .send = is_send,
            .secp = cmd_ctx->cmd_ctx.security.secp,
            .spsp = cmd_ctx->cmd_ctx.security.spsp,
        };
        tvbuff_t *sec_tvb = tvb_new_subset_length(tvb, 0, len);

        if (sec.secp == 0x00 && !sec.send &&
            dissect_nvme_security_info_resp(sec_tvb, tree, sec.spsp, len))
            return;

        if (dissector_try_uint_with_data(nvme_security_secp_table, sec.secp,
                                         sec_tvb, pinfo, tree, false, &sec))
            return;
    }
    proto_tree_add_bytes_format_value(tree, hf_nvme_security_data, tvb, 0, len, NULL,
                                      "NVMe Security Protocol Data (offset %u, %u bytes)", off, len);
}

void
nvme_dissect_admin_sqe_cdws(tvbuff_t *sqe_tvb, packet_info *pinfo,
                            proto_tree *tree, struct nvme_cmd_ctx *cmd_ctx)
{
    switch (cmd_ctx->opcode) {
    case NVME_AQ_OPC_IDENTIFY:
        /* CNS is one byte (CDW10 07:00); byte 41 is reserved */
        cmd_ctx->cmd_ctx.cmd_identify.cns = tvb_get_uint8(sqe_tvb, 40);
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(cmd_ctx->cmd_ctx.cmd_identify.cns, cns_table, "Unknown"));
        dissect_nvme_identify_cmd(sqe_tvb, tree);
        break;
    case NVME_AQ_OPC_GET_LOG_PAGE:
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", get_logpage_name(tvb_get_uint8(sqe_tvb, 40)));
        dissect_nvme_get_logpage_cmd(sqe_tvb, tree, cmd_ctx);
        break;
    case NVME_AQ_OPC_SET_FEATURES:
        dissect_nvme_set_features_cmd(sqe_tvb, tree, cmd_ctx);
        break;
    case NVME_AQ_OPC_GET_FEATURES:
        dissect_nvme_get_features_cmd(sqe_tvb, tree, cmd_ctx);
        break;
    case NVME_AQ_OPC_FW_COMMIT:
        dissect_nvme_fw_commit_cmd(sqe_tvb, tree);
        break;
    case NVME_AQ_OPC_FW_IMG_DOWNLOAD:
        dissect_nvme_fw_download_cmd(sqe_tvb, tree);
        break;
    case NVME_AQ_OPC_SELF_TEST:
        dissect_nvme_self_test_cmd(sqe_tvb, tree);
        break;
    case NVME_AQ_OPC_LOCKDOWN:
        dissect_nvme_lockdown_cmd(sqe_tvb, tree);
        break;
    case NVME_AQ_OPC_FORMAT_NVM:
        dissect_nvme_format_nvm_cmd(sqe_tvb, tree);
        break;
    case NVME_AQ_OPC_SANITIZE:
        dissect_nvme_sanitize_cmd(sqe_tvb, tree);
        break;
    case NVME_AQ_OPC_SECURITY_SEND:
        dissect_nvme_security_send_cmd(sqe_tvb, tree, cmd_ctx);
        break;
    case NVME_AQ_OPC_SECURITY_RECV:
        dissect_nvme_security_recv_cmd(sqe_tvb, tree, cmd_ctx);
        break;
    default:
        dissect_nvme_unhandled_cmd(sqe_tvb, tree);
        break;
    }
}

void
dissect_nvme_cmd(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *root_tree,
                 struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx)
{
    proto_tree *cmd_tree;
    proto_item *ti, *opc_item;

    col_set_str(pinfo->cinfo, COL_PROTOCOL, "NVMe");
    ti = proto_tree_add_item(root_tree, proto_nvme, nvme_tvb, 0,
                             NVME_CMD_SIZE, ENC_NA);
    proto_item_append_text(ti, " (Cmd)");
    cmd_tree = proto_item_add_subtree(ti, ett_data);

    cmd_ctx->opcode = tvb_get_uint8(nvme_tvb, 0);
    opc_item = proto_tree_add_item(cmd_tree, hf_nvme_cmd_opc, nvme_tvb,
                        0, 1, ENC_LITTLE_ENDIAN);
    if (q_ctx->qid) {
        proto_item_append_text(opc_item, " %s", get_ioq_opcode_name(cmd_ctx->opcode));
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMe %s", get_ioq_opcode_name(cmd_ctx->opcode));
    } else {
        proto_item_append_text(opc_item, " %s", get_aq_opcode_name(cmd_ctx->opcode));
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMe %s", get_aq_opcode_name(cmd_ctx->opcode));
    }

    nvme_publish_to_data_req_link(cmd_tree, nvme_tvb, hf_nvme_data_req, cmd_ctx);
    nvme_publish_to_data_tr_links(cmd_tree, nvme_tvb, hf_nvme_data_tr, cmd_ctx);
    nvme_publish_to_cqe_link(cmd_tree, nvme_tvb, hf_nvme_cqe_pkt, cmd_ctx);

    proto_tree_add_item(cmd_tree, hf_nvme_cmd_fuse_op, nvme_tvb,
                        1, 1, ENC_NA);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_rsvd, nvme_tvb,
                        1, 1, ENC_NA);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_psdt, nvme_tvb,
                        1, 1, ENC_NA);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_cid, nvme_tvb,
                        2, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_nsid, nvme_tvb,
                        4, 4, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_rsvd1, nvme_tvb,
                        8, 8, ENC_NA);
    proto_tree_add_item(cmd_tree, hf_nvme_cmd_mptr, nvme_tvb,
                        16, 8, ENC_LITTLE_ENDIAN);

    dissect_nvme_cmd_sgl(nvme_tvb, cmd_tree, hf_nvme_cmd_sgl, q_ctx, cmd_ctx, 0, PINFO_FD_VISITED(pinfo));

    if (q_ctx->qid) { //IOQ
        switch (cmd_ctx->opcode) {
        case NVME_IOQ_OPC_READ:
        case NVME_IOQ_OPC_WRITE:
            dissect_nvme_rw_cmd(nvme_tvb, cmd_tree);
            break;
        default:
            dissect_nvme_unhandled_cmd(nvme_tvb, cmd_tree);
            break;
        }
    } else { //AQ
        nvme_dissect_admin_sqe_cdws(nvme_tvb, pinfo, cmd_tree, cmd_ctx);
    }
}

const char *nvme_get_opcode_string(uint8_t opcode, uint16_t qid)
{
    if (qid)
        return get_ioq_opcode_name(opcode);
    else
        return get_aq_opcode_name(opcode);
}

int
nvme_is_io_queue_opcode(uint8_t opcode)
{
    return ((opcode == NVME_IOQ_OPC_FLUSH) ||
            (opcode == NVME_IOQ_OPC_WRITE) ||
            (opcode == NVME_IOQ_OPC_READ) ||
            (opcode == NVME_IOQ_OPC_WRITE_UNCORRECTABLE) ||
            (opcode == NVME_IOQ_OPC_COMPARE) ||
            (opcode == NVME_IOQ_OPC_WRITE_ZEROS) ||
            (opcode == NVME_IOQ_OPC_DATASET_MGMT) ||
            (opcode == NVME_IOQ_OPC_RESV_REG) ||
            (opcode == NVME_IOQ_OPC_RESV_REPORT) ||
            (opcode == NVME_IOQ_OPC_RESV_ACQUIRE) ||
            (opcode == NVME_IOQ_OPC_RESV_RELEASE));
}

static const char *get_cqe_sc_string(unsigned sct, unsigned sc, bool nvmeof)
{
    switch (sct) {
        case NVME_CQE_SCT_GENERIC: return val_to_str_const(sc, nvme_cqe_sc_gen_tbl, "Unknown Status Code");
        case NVME_CQE_SCT_COMMAND: return (nvmeof) ? val_to_str_const(sc, nvmeof_cqe_sc_cmd_tbl, "Unknown Fabrics Status Code") :
            val_to_str_const(sc, nvme_cqe_sc_cmd_tbl, "Unknown Status Code");
        case NVME_CQE_SCT_MEDIA: return val_to_str_const(sc, nvme_cqe_sc_media_tbl, "Unknown Status Code");
        case NVME_CQE_SCT_PATH: return val_to_str_const(sc, nvme_cqe_sc_path_tbl, "Unknown Status Code");
        case NVME_CQE_SCT_VENDOR: return "Vendor Error";
        default: return "Unknown Status Code";
    }
}

static const value_string nvme_cqe_sc_sf_err_dword0_tbl[] = {
    { 0xD, "Feature Identifier Not Saveable" },
    { 0xE, "Feature Not Changeable" },
    { 0xF, "Feature Not Namespace Specific" },
    { 0x14, "Overlapping Range" },
    { 0x15, "I/O Command Set Combination Rejected" },
    { 0x37, "Invalid Controller Data Queue" },
    { 0x3E, "Invalid Power Limit" },
    { 0, NULL },
};

static const value_string nvme_cqe_aev_aet_dword0_tbl[] = {
    { 0x0, "Error status" },
    { 0x1, "SMART / Health status" },
    { 0x2, "Notice" },
    { 0x3, "Immediate" },
    { 0x4, "One-Shot" },
    { 0x6, "IO Command Set specific status" },
    { 0x7, "Vendor specific" },
    { 0, NULL },
};

static const value_string nvme_cqe_aev_status_error_tbl[] = {
    { 0x0, "Write to Invalid Doorbell Register" },
    { 0x1, "Invalid Doorbell Write Value" },
    { 0x2, "Diagnostic Failure" },
    { 0x3, "Persistent Internal Error"},
    { 0x4, "Transient Internal Error"},
    { 0x5, "Firmware Image Load Error"},
    { 0, NULL },
};

static const value_string nvme_cqe_aev_status_smart_tbl[] = {
    { 0x0, "NVM subsystem Reliability" },
    { 0x1, "Temperature Threshold" },
    { 0x2, "Spare Below Threshold" },
    { 0, NULL },
};

static const value_string nvme_cqe_aev_status_notice_tbl[] = {
    { 0x0, "Attached Namespace Attribute Changed" },
    { 0x1, "Firmware Activation Starting" },
    { 0x2, "Telemetry Log Changed" },
    { 0x3, "Asymmetric Namespace Access Change" },
    { 0x4, "Predictable Latency Event Aggregate Log Change" },
    { 0x5, "LBA Status Information Alert" },
    { 0x6, "Endurance Group Event Aggregate Log Page Change" },
    { 0x7, "Reachability Group Change" },
    { 0x8, "Reachability Association Change" },
    { 0x9, "Allocated Namespace Attribute Changed" },
    { 0xEF, "Zone Descriptor Changed" },
    { 0xF0, "Discovery Log Page Change" },
    { 0xF1, "Host Discovery Log Page Change" },
    { 0xF2, "AVE Discovery Log Page Change" },
    { 0xF3, "Pull Model DDC Request" },
    { 0xF4, "Cross-Controller Reset Completed" },
    { 0xF5, "Lost Host Communication" },
    { 0, NULL },
};

static const value_string nvme_cqe_aev_status_nvm_tbl[] = {
    { 0x0, "Reservation Log Page Available" },
    { 0x1, "Sanitize Operation Completed" },
    { 0x2, "Sanitize Operation Completed With Unexpected Deallocation" },
    { 0x3, "Sanitize Operation Entered Media Verification State" },
    { 0, NULL },
};

void nvme_dissect_admin_cqe_dw0(tvbuff_t *nvme_tvb, int dw0_off, proto_tree *cqe_tree,
                                uint16_t status, struct nvme_cmd_ctx *cmd_ctx)
{
    switch (cmd_ctx->opcode) {
        case NVME_AQ_OPC_SET_FEATURES:
        {
            uint16_t sc = ((status & 0x1fe) >> 1);
            if (sc) {
                proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword0_sf_err, nvme_tvb, dw0_off, 4, ENC_LITTLE_ENDIAN);
            } else {
                if (cmd_ctx->cmd_ctx.set_features.fid == F_NUM_OF_QUEUES)
                    add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_dword0_sf_nq));
                else
                    proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword0, nvme_tvb, dw0_off, 4, ENC_LITTLE_ENDIAN);
            }
            break;
        }
        case NVME_AQ_OPC_GET_FEATURES:
            switch (cmd_ctx->cmd_ctx.set_features.fid) {
                case F_ARBITRATION: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_arb)); break;
                case F_POWER_MGMT: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_pm)); break;
                case F_LBA_RANGE_TYPE: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_lbart)); break;
                case F_TEMP_THRESHOLD: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_tt)); break;
                case F_ERROR_RECOVERY: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_erec)); break;
                case F_VOLATILE_WC: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_vwce)); break;
                case F_NUM_OF_QUEUES: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_nq)); break;
                case F_IRQ_COALESCING: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_irqc)); break;
                case F_IRQ_VECTOR_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_irqv)); break;
                case F_WRITE_ATOM_NORM: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_wan)); break;
                case F_ASYNC_EVENT_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_aec)); break;
                case F_AUTO_PS_TRANSITION: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_apst)); break;
                case F_KA_TIMER: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_kat)); break;
                case F_HOST_CNTL_THERM_MGMT: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_hctm)); break;
                case F_NO_POWER_STATE_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_nops)); break;
                case F_READ_REC_LEVEL_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_rrl)); break;
                case F_PRED_LAT_MODE_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_plmc)); break;
                case F_PRED_LAT_MODE_WIND: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_plmw)); break;
                case F_LBA_ST_INF_REP_INT: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_lbasi)); break;
                case F_SANITIZE_CON: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_san)); break;
                case F_END_GROUP_EV_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_eg)); break;
                case F_SW_PR_MARKER: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_swp)); break;
                case F_HOST_ID: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_hid)); break;
                case F_RSRV_NOT_MASK: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_rsrvn)); break;
                case F_RSRV_PRST: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_rsrvp)); break;
                case F_NS_WRITE_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, dw0_off, 4, ASPEC(hf_nvme_cqe_get_features_dword0_nswp)); break;
                default: proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword0, nvme_tvb, dw0_off, 4, ENC_LITTLE_ENDIAN); break;
            }
            break;
        case NVME_AQ_OPC_ASYNC_EVE_REQ:
        {
            proto_item *ti;
            proto_tree *grp;
            unsigned i;
            uint8_t aet;
            uint8_t aei;
            ti = proto_tree_add_item(cqe_tree, hf_nvme_cqe_aev_dword0[0], nvme_tvb, dw0_off, 4, ENC_LITTLE_ENDIAN);
            grp =  proto_item_add_subtree(ti, ett_data);
            for (i = 1; i < 4; i++)
                ti = proto_tree_add_item(grp, hf_nvme_cqe_aev_dword0[i], nvme_tvb, dw0_off, 4, ENC_LITTLE_ENDIAN);
            /* Asynchronous Event Information is CQE DW0 bits 15:08 (byte 1);
             * byte 2 is the Log Page Identifier. */
            aet = tvb_get_uint8(nvme_tvb, dw0_off) & 0x7;
            aei = tvb_get_uint8(nvme_tvb, dw0_off + 1);
            switch (aet) {
                case 0: proto_item_append_text(ti, " (%s)", val_to_str_const(aei, nvme_cqe_aev_status_error_tbl, "Unknown")); break;
                case 1: proto_item_append_text(ti, " (%s)", val_to_str_const(aei, nvme_cqe_aev_status_smart_tbl, "Unknown")); break;
                case 2: proto_item_append_text(ti, " (%s)", val_to_str_const(aei, nvme_cqe_aev_status_notice_tbl, "Unknown")); break;
                case 6: proto_item_append_text(ti, " (%s)", val_to_str_const(aei, nvme_cqe_aev_status_nvm_tbl, "Unknown")); break;
            }
            proto_tree_add_item(grp, hf_nvme_cqe_aev_dword0[4], nvme_tvb, dw0_off, 4, ENC_LITTLE_ENDIAN);
            proto_tree_add_item(grp, hf_nvme_cqe_aev_dword0[5], nvme_tvb, dw0_off, 4, ENC_LITTLE_ENDIAN);
            break;
        }
        default:
            proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword0, nvme_tvb, dw0_off, 4, ENC_LITTLE_ENDIAN);
            break;
    }
}

/* Status Field word (Phase/SCT/SC/CRD/M/DNR) at status_off.  Factored out of
 * dissect_nvme_cqe_common() so transports that carry the NVMe status word
 * without the surrounding CQE layout (NVMe-MI omits SQHD/SQID/CID) can decode
 * it at an explicit offset.  nvmeof selects the Reserved vs Phase Tag rendering
 * of bit 0 and the fabrics status-code string table. */
static void nvme_cqe_status_word(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *cqe_tree, unsigned status_off, bool nvmeof)
{
    proto_item *ti;
    proto_tree *grp;
    uint16_t val;
    unsigned i;

    val = tvb_get_uint16(nvme_tvb, status_off, ENC_LITTLE_ENDIAN);
    ti = proto_tree_add_item(cqe_tree, hf_nvme_cqe_status[0], nvme_tvb, status_off, 2, ENC_LITTLE_ENDIAN);
    /* SC (08:01) or SCT (11:09) nonzero means the command did not complete
     * successfully.  Phase Tag, CRD, M and DNR are deliberately excluded --
     * none of them indicates failure. */
    if (val & 0xFFE)
        expert_add_info(pinfo, ti, &ei_nvme_cqe_status_error);
    grp =  proto_item_add_subtree(ti, ett_data);
    if (nvmeof)
        proto_tree_add_item(grp, hf_nvme_cqe_status_rsvd, nvme_tvb, status_off, 2, ENC_LITTLE_ENDIAN);
    else
        proto_tree_add_item(grp, hf_nvme_cqe_status[1], nvme_tvb, status_off, 2, ENC_LITTLE_ENDIAN);

    ti = proto_tree_add_item(grp, hf_nvme_cqe_status[2], nvme_tvb, status_off, 2, ENC_LITTLE_ENDIAN);
    proto_item_append_text(ti, " (%s)", get_cqe_sc_string((val & 0xE00) >> 9, (val & 0x1FE) >> 1, nvmeof));

    for (i = 3; i < array_length(hf_nvme_cqe_status); i++)
        proto_tree_add_item(grp, hf_nvme_cqe_status[i], nvme_tvb, status_off, 2, ENC_LITTLE_ENDIAN);
}

void nvme_dissect_cqe_status(tvbuff_t *nvme_tvb, packet_info *pinfo, int status_off, proto_tree *cqe_tree)
{
    nvme_cqe_status_word(nvme_tvb, pinfo, cqe_tree, (unsigned)status_off, false);
}

static void dissect_nvme_cqe_common(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *cqe_tree, unsigned off, bool nvmeof)
{
    proto_tree_add_item(cqe_tree, hf_nvme_cqe_sqhd, nvme_tvb, off+8, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cqe_tree, hf_nvme_cqe_sqid, nvme_tvb, off+10, 2, ENC_LITTLE_ENDIAN);
    proto_tree_add_item(cqe_tree, hf_nvme_cqe_cid, nvme_tvb, off+12, 2, ENC_LITTLE_ENDIAN);
    nvme_cqe_status_word(nvme_tvb, pinfo, cqe_tree, off+14, nvmeof);
}

void dissect_nvme_cqe(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *root_tree, struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx)
{
    proto_tree *cqe_tree;
    proto_item *ti;

    if (q_ctx->qid)
            col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMe CQE for %s", get_ioq_opcode_name(cmd_ctx->opcode));
    else
        col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMe CQE for %s", get_aq_opcode_name(cmd_ctx->opcode));

    if (!q_ctx->qid) {
        if (cmd_ctx->opcode == NVME_AQ_OPC_IDENTIFY)
            col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(cmd_ctx->cmd_ctx.cmd_identify.cns, cns_table, "Unknown"));
        else if (cmd_ctx->opcode == NVME_AQ_OPC_GET_LOG_PAGE)
            col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", get_logpage_name(cmd_ctx->cmd_ctx.get_logpage.lid));
    }
    col_set_str(pinfo->cinfo, COL_PROTOCOL, "NVMe");
    ti = proto_tree_add_item(root_tree, proto_nvme, nvme_tvb, 0,
                             NVME_CQE_SIZE, ENC_NA);
    proto_item_append_text(ti, " (Cqe)");
    cqe_tree = proto_item_add_subtree(ti, ett_data);

    nvme_publish_to_cmd_link(cqe_tree, nvme_tvb, hf_nvme_cmd_pkt, cmd_ctx);
    nvme_publish_cmd_latency(cqe_tree, cmd_ctx, hf_nvme_cmd_latency);

    nvme_dissect_admin_cqe_dw0(nvme_tvb, 0, cqe_tree,
                               tvb_get_uint16(nvme_tvb, 14, ENC_LITTLE_ENDIAN), cmd_ctx);
    proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword1, nvme_tvb, 4, 4, ENC_LITTLE_ENDIAN);
    dissect_nvme_cqe_common(nvme_tvb, pinfo, cqe_tree, 0, false);
}

void
proto_register_nvme(void)
{
    static hf_register_info hf[] = {
        /* NVMeOF Fabric Command Fields */
        { &hf_nvmeof_cmd,
            { "Cmd", "nvme.fabrics.cmd",
               FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_opc,
            { "Opcode", "nvme.fabrics.cmd.opc",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_rsvd,
            { "Reserved", "nvme.fabrics.cmd.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_cid,
            { "Command Identifier", "nvme.fabrics.cmd.cid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_fctype,
            { "Fabric Command Type", "nvme.fabrics.cmd.fctype",
               FT_UINT8, BASE_HEX | BASE_RANGE_STRING, RVALS(fctype_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_rsvd1,
            { "Reserved", "nvme.fabrics.cmd.connect.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_sgl1,
            { "SGL1", "nvme.fabrics.cmd.connect.sgl1",
               FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_recfmt,
            { "Record Format", "nvme.fabrics.cmd.connect.recfmt",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_qid,
            { "Queue ID", "nvme.fabrics.cmd.connect.qid",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_nvme_qid), 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_sqsize,
            { "Submission Queue Size", "nvme.fabrics.cmd.connect.sqsize",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_zero_base), 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_cattr[0],
            { "Connect Attributes", "nvme.fabrics.cmd.connect.cattr",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_cattr[1],
            { "Priority Class", "nvme.fabrics.cmd.connect.cattr.pc",
               FT_UINT8, BASE_HEX, VALS(pclass_tbl), 0x3, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_cattr[2],
            { "Disable SQ Flow Control", "nvme.fabrics.cmd.connect.cattr.dfc",
               FT_UINT8, BASE_HEX, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_cattr[3],
            { "Support Deletion of IO Queues", "nvme.fabrics.cmd.connect.cattr.dioq",
               FT_UINT8, BASE_HEX, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_cattr[4],
            { "Reserved", "nvme.fabrics.cmd.connect.cattr.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_rsvd2,
            { "Reserved", "nvme.fabrics.cmd.connect.rsvd2",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_kato,
            { "Keep Alive Timeout", "nvme.fabrics.cmd.connect.kato",
               FT_UINT32, BASE_DEC|BASE_UNIT_STRING, UNS(&units_milliseconds), 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_rsvd3,
            { "Reserved", "nvme.fabrics.cmd.connect.rsvd3",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_data_hostid,
            { "Host Identifier", "nvme.fabrics.cmd.connect.data.hostid",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_data_cntlid,
            { "Controller ID", "nvme.fabrics.cmd.connect.data.cntrlid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_data_rsvd0,
            { "Reserved", "nvme.fabrics.cmd.connect.data.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_data_subnqn,
            { "Subsystem NQN", "nvme.fabrics.cmd.connect.data.subnqn",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_data_hostnqn,
            { "Host NQN", "nvme.fabrics.cmd.connect.data.hostnqn",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_connect_data_rsvd1,
            { "Reserved", "nvme.fabrics.cmd.connect.data.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_auth_rsdv1,
            { "Reserved", "nvme.fabrics.cmd.auth.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_auth_sgl1,
            { "SGL1", "nvme.fabrics.cmd.auth.sgl1",
               FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_auth_rsdv2,
            { "Reserved", "nvme.fabrics.cmd.auth.rsvd2",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_auth_spsp0,
            { "SP Specific 0", "nvme.fabrics.cmd.auth.spsp0",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_auth_spsp1,
            { "SP Specific 1", "nvme.fabrics.cmd.auth.spsp1",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_auth_secp,
            { "Security Protocol", "nvme.fabrics.cmd.auth.secp",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_auth_al,
            { "Allocation Length", "nvme.fabrics.cmd.auth.al",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_auth_rsdv3,
            { "Reserved", "nvme.fabrics.cmd.auth.rsvd3",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_disconnect_rsvd0,
            { "Reserved", "nvme.fabrics.cmd.disconnect.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_disconnect_recfmt,
            { "Record Format", "nvme.fabrics.cmd.disconnect.recfmt",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_disconnect_rsvd1,
            { "Reserved", "nvme.fabrics.cmd.disconnect.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_prop_get_set_rsvd0,
            { "Reserved", "nvme.fabrics.cmd.prop_get_set.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_prop_get_set_attrib[0],
            { "Attributes", "nvme.fabrics.cmd.prop_get_set.attrib",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_prop_get_set_attrib[1],
            { "Property Size", "nvme.fabrics.cmd.prop_get_set.attrib.size",
               FT_UINT8, BASE_HEX, VALS(attr_size_tbl), 0x7, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_prop_get_set_attrib[2],
            { "Reserved", "nvme.fabrics.cmd.prop_get_set.attrib.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_prop_get_set_rsvd1,
            { "Reserved", "nvme.fabrics.cmd.prop_get_set.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_prop_get_set_offset,
            { "Offset", "nvme.fabrics.cmd.prop_get_set.offset",
               FT_UINT32, BASE_HEX, VALS(prop_offset_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_prop_get_rsvd2,
            { "Reserved", "nvme.fabrics.cmd.prop_get.rsvd2",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_data,
            { "Property Data", "nvme.fabrics.prop_get_set.data",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_data_4B,
            { "Value", "nvme.fabrics.prop_get_set.data.4B",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_data_4B_rsvd,
            { "Reserved", "nvme.fabrics.prop_get_set.data.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_data_8B,
            { "Value", "nvme.fabrics.prop_get_set.data.8B",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[0],
            { "Controller Configuration", "nvme.fabrics.prop_get_set.cc",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[1],
            { "Enable", "nvme.fabrics.prop_get_set.cc.en",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[2],
            { "Reserved", "nvme.fabrics.prop_get_set.cc.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0xE, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[3],
            { "IO Command Set Selected", "nvme.fabrics.prop_get_set.cc.css",
               FT_UINT32, BASE_HEX, VALS(css_table), 0x70, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[4],
            { "Memory Page Size", "nvme.fabrics.prop_get_set.cc.mps",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_page_size), 0x780, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[5],
            { "Arbitration Mechanism Selected", "nvme.fabrics.prop_get_set.cc.ams",
               FT_UINT32, BASE_HEX, VALS(ams_table), 0x3800, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[6],
            { "Shutdown Notification", "nvme.fabrics.prop_get_set.cc.shn",
               FT_UINT32, BASE_HEX, VALS(sn_table), 0xc000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[7],
            { "IO Submission Queue Entry Size", "nvme.fabrics.prop_get_set.cc.iosqes",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xF0000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[8],
            { "IO Completion Queue Entry Size", "nvme.fabrics.prop_get_set.cc.iocqes",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xF00000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_cc[9],
            { "Reserved", "nvme.fabrics.prop_get_set.cc.rsvd1",
               FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_csts[0],
            { "Controller Status", "nvme.fabrics.prop_get_set.csts",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_csts[1],
            { "Ready", "nvme.fabrics.prop_get_set.csts.rdy",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_csts[2],
            { "Controller Fatal Status", "nvme.fabrics.prop_get_set.csts.cfs",
               FT_UINT32, BASE_HEX, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_csts[3],
            { "Shutdown Status", "nvme.fabrics.prop_get_set.csts.shst",
               FT_UINT32, BASE_HEX, VALS(shst_table), 0xC, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_csts[4],
            { "NVM Subsystem Reset Occurred", "nvme.fabrics.prop_get_set.csts.nssro",
               FT_UINT32, BASE_HEX, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_csts[5],
            { "Processing Paused", "nvme.fabrics.prop_get_set.csts.pp",
               FT_UINT32, BASE_HEX, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_csts[6],
            { "Reserved", "nvme.fabrics.prop_get_set.csts.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffffC0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_nssr[0],
            { "NVM Subsystem Reset", "nvme.fabrics.cmd.prop_attr.set.nssr",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_set_nssr[1],
            { "NVM Subsystem Reset Control", "nvme.fabrics.cmd.prop_attr.set.nssr.nssrc",
               FT_UINT32, BASE_HEX, NULL, 0xffffffff, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_prop_set_rsvd,
            { "Reserved", "nvme.fabrics.cmd.prop_set.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_generic_rsvd1,
            { "Reserved", "nvme.fabrics.cmd.generic.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cmd_generic_field,
            { "Fabric Cmd specific field", "nvme.fabrics.cmd.generic.field",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* NVMeOF Fabric Commands CQE fields */
        { &hf_nvmeof_cqe,
            { "Cqe", "nvme.fabrics.cqe",
               FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cqe_sts,
            { "Cmd specific Status", "nvme.fabrics.cqe.sts",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[0],
            { "Controller Capabilities", "nvme.fabrics.prop_get.ccap",
               FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[1],
            { "Maximum Queue Entries Supported", "nvme.fabrics.prop_get.ccap.mqes",
               FT_UINT64, BASE_CUSTOM, CF_FUNC(add_zero_base), 0xffff, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[2],
            { "Contiguous Queues Required", "nvme.fabrics.prop_get.ccap.cqr",
               FT_BOOLEAN, 64, NULL, 0x10000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[3],
            { "Supports Arbitration Mechanism with Weighted Round Robin and Urgent Priority Class", "nvme.fabrics.prop_get.ccap.ams.wrr",
               FT_BOOLEAN, 64, NULL, 0x20000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[4],
            { "Supports Arbitration Mechanism Vendor Specific", "nvme.fabrics.prop_get.ccap.ams.vs",
               FT_BOOLEAN, 64, NULL, 0x40000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[5],
            { "Reserved", "nvme.fabrics.prop_get.ccap.rsvd0",
               FT_UINT64, BASE_HEX, NULL, 0xF80000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[6],
            { "Timeout (to ready status)", "nvme.fabrics.prop_get.ccap.to",
               FT_UINT64, BASE_CUSTOM, CF_FUNC(add_500ms_units), 0xFF000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[7],
            { "Doorbell Stride", "nvme.fabrics.prop_get.ccap.dstrd",
               FT_UINT64, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_dstrd_size), 0xF00000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[8],
            { "NVM Subsystem Reset Supported", "nvme.fabrics.prop_get.ccap.nssrs",
               FT_BOOLEAN, 64, NULL, 0x1000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[9],
            { "Command Sets Supported", "nvme.fabrics.prop_get.ccap.css",
               FT_UINT64, BASE_CUSTOM, CF_FUNC(add_ccap_css), 0x1FE000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[10],
            { "Boot Partition Support", "nvme.fabrics.prop_get.ccap.bps",
               FT_BOOLEAN, 64, NULL, 0x200000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[11],
            { "Reserved", "nvme.fabrics.prop_get.ccap.rsdv1",
               FT_UINT64, BASE_HEX, NULL, 0xC00000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[12],
            { "Memory Page Size Minimum", "nvme.fabrics.prop_get.ccap.mpsmin",
               FT_UINT64, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_page_size), 0xF000000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[13],
            { "Memory Page Size Maximum", "nvme.fabrics.prop_get.ccap.mpsmax",
               FT_UINT64, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_page_size), 0xF0000000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[14],
            { "Persistent Memory Region Supported", "nvme.fabrics.prop_get.ccap.pmrs",
               FT_BOOLEAN, 64, NULL, 0x100000000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[15],
            { "Controller Memory Buffer Supported", "nvme.fabrics.prop_get.ccap.cmbs",
               FT_BOOLEAN, 64, NULL, 0x200000000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_ccap[16],
            { "Reserved", "nvme.fabrics.prop_get.ccap.rsvd2",
               FT_UINT64, BASE_HEX, NULL, 0xFC00000000000000, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_vs[0],
            { "Version", "nvme.fabrics.prop_get.vs",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_vs[1],
            { "Tertiary Version", "nvme.fabrics.prop_get.vs.ter",
               FT_UINT32, BASE_DEC, NULL, 0xff, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_vs[2],
            { "Minor Version", "nvme.fabrics.prop_get.vs.mnr",
               FT_UINT32, BASE_DEC, NULL, 0xff00, NULL, HFILL}
        },
        { &hf_nvmeof_prop_get_vs[3],
            { "Major Version", "nvme.fabrics.prop_get.vs.mjr",
               FT_UINT32, BASE_DEC, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvmeof_cqe_connect_cntlid,
            { "Controller ID", "nvme.fabrics.cqe.connect.cntrlid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cqe_connect_authreq,
            { "Authentication Required", "nvme.fabrics.cqe.connect.authreq",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cqe_connect_rsvd,
            { "Reserved", "nvme.fabrics.cqe.connect.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvmeof_cqe_prop_set_rsvd,
            { "Reserved", "nvme.fabrics.cqe.prop_set.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Tracking commands, completions and transfers */
                { &hf_nvmeof_cmd_pkt,
            { "Fabric Cmd in", "nvme.fabrics.cmd_pkt",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "The Cmd for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_cqe_pkt,
            { "Fabric Cqe in", "nvme.fabrics.cqe_pkt",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "The Cqe for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_req,
            { "DATA Transfer Request", "nvme.fabrics.data_req",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer request for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[0],
            { "DATA Transfer 0", "nvme.fabrics.data.tr0",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 0 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[1],
            { "DATA Transfer 1", "nvme.fabrics.data_tr1",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 1 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[2],
            { "DATA Transfer 2", "nvme.fabrics.data_tr2",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 2 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[3],
            { "DATA Transfer 3", "nvme.fabrics.data_tr3",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 3 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[4],
            { "DATA Transfer 4", "nvme.fabrics.data_tr4",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 4 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[5],
            { "DATA Transfer 5", "nvme.fabrics.data_tr5",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 5 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[6],
            { "DATA Transfer 6", "nvme.fabrics.data_tr6",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 6 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[7],
            { "DATA Transfer 7", "nvme.fabrics.data_tr7",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 7 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[8],
            { "DATA Transfer 8", "nvme.fabrics.data_tr8",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 8 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[9],
            { "DATA Transfer 9", "nvme.fabrics.data_tr9",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 9 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[10],
            { "DATA Transfer 10", "nvme.fabrics.data_tr10",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 10 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[11],
            { "DATA Transfer 11", "nvme.fabrics.data_tr11",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 11 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[12],
            { "DATA Transfer 12", "nvme.fabrics.data_tr12",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 12 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[13],
            { "DATA Transfer 13", "nvme.fabrics.data_tr13",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 13 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[14],
            { "DATA Transfer 14", "nvme.fabrics.data_tr14",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 14 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_data_tr[15],
            { "DATA Transfer 15", "nvme.fabrics.data_tr15",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 15 for this transaction is in this frame", HFILL }
        },
        { &hf_nvmeof_cmd_latency,
            { "Cmd Latency", "nvme.fabrics.cmd_latency",
              FT_DOUBLE, BASE_NONE, NULL, 0x0,
              "The time between the command and completion, in usec", HFILL }
        },
        /* NVMe Command fields */
        { &hf_nvme_cmd_opc,
            { "Opcode", "nvme.cmd.opc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cmd_fuse_op,
            { "Fuse Operation", "nvme.cmd.fuse_op",
               FT_UINT8, BASE_HEX, NULL, 0x3, NULL, HFILL}
        },
        { &hf_nvme_cmd_rsvd,
            { "Reserved", "nvme.cmd.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0x3c, NULL, HFILL}
        },
        { &hf_nvme_cmd_psdt,
            { "PRP Or SGL", "nvme.cmd.psdt",
               FT_UINT8, BASE_HEX, NULL, 0xc0, NULL, HFILL}
        },
        { &hf_nvme_cmd_cid,
            { "Command ID", "nvme.cmd.cid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cmd_nsid,
            { "Namespace Id", "nvme.cmd.nsid",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_rsvd1,
            { "Reserved", "nvme.cmd.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_mptr,
            { "Metadata Pointer", "nvme.cmd.mptr",
               FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_sgl,
            { "SGL1", "nvme.cmd.sgl1",
               FT_NONE, BASE_NONE, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_sgl_desc_sub_type,
            { "Descriptor Sub Type", "nvme.cmd.sgl.subtype",
               FT_UINT8, BASE_HEX, NULL, 0x0f, NULL, HFILL}
        },
        { &hf_nvme_cmd_sgl_desc_type,
            { "Descriptor Type", "nvme.cmd.sgl.type",
               FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_cmd_sgl_desc_addr,
            { "Address", "nvme.cmd.sgl1.addr",
               FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_sgl_desc_addr_rsvd,
            { "Reserved", "nvme.cmd.sgl1.addr_rsvd",
               FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_sgl_desc_len,
            { "Length", "nvme.cmd.sgl1.len",
               FT_UINT32, BASE_DEC, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_sgl_desc_key,
            { "Key", "nvme.cmd.sgl1.key",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_sgl_desc_rsvd,
            { "Reserved", "nvme.cmd.sgl1.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cmd_dword10,
            { "DWORD10", "nvme.cmd.dword10",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_dword11,
            { "DWORD11", "nvme.cmd.dword11",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_dword12,
            { "DWORD12", "nvme.cmd.dword12",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_dword13,
            { "DWORD13", "nvme.cmd.dword13",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_dword14,
            { "DWORD14", "nvme.cmd.dword14",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_dword15,
            { "DWORD15", "nvme.cmd.dword15",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_slba,
            { "Start LBA", "nvme.cmd.slba",
               FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_nlb,
            { "Absolute Number of Logical Blocks", "nvme.cmd.nlb",
               FT_UINT16, BASE_DEC_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_rsvd2,
            { "Reserved", "nvme.cmd.rsvd2",
               FT_UINT16, BASE_HEX, NULL, 0x03ff, NULL, HFILL}
        },
        { &hf_nvme_cmd_prinfo,
            { "Protection info fields",
              "nvme.cmd.prinfo",
               FT_UINT16, BASE_HEX, NULL, 0x3c00, NULL, HFILL}
        },
        { &hf_nvme_cmd_prinfo_prchk_lbrtag,
            { "check Logical block reference tag",
              "nvme.cmd.prinfo.lbrtag",
               FT_UINT16, BASE_HEX, NULL, 0x0400, NULL, HFILL}
        },
        { &hf_nvme_cmd_prinfo_prchk_apptag,
            { "check application tag field",
              "nvme.cmd.prinfo.apptag",
               FT_UINT16, BASE_HEX, NULL, 0x0800, NULL, HFILL}
        },
        { &hf_nvme_cmd_prinfo_prchk_guard,
            { "check guard field",
              "nvme.cmd.prinfo.guard",
               FT_UINT16, BASE_HEX, NULL, 0x1000, NULL, HFILL}
        },
        { &hf_nvme_cmd_prinfo_pract,
            { "action",
              "nvme.cmd.prinfo.action",
               FT_UINT16, BASE_HEX, NULL, 0x2000, NULL, HFILL}
        },
        { &hf_nvme_cmd_fua,
            { "Force Unit Access", "nvme.cmd.fua",
               FT_UINT16, BASE_HEX, NULL, 0x4000, NULL, HFILL}
        },
        { &hf_nvme_cmd_lr,
            { "Limited Retry", "nvme.cmd.lr",
               FT_UINT16, BASE_HEX, NULL, 0x8000, NULL, HFILL}
        },
        { &hf_nvme_cmd_eilbrt,
            { "Expected Initial Logical Block Reference Tag", "nvme.cmd.eilbrt",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cmd_elbat,
            { "Expected Logical Block Application Tag Mask", "nvme.cmd.elbat",
               FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_elbatm,
            { "Expected Logical Block Application Tag", "nvme.cmd.elbatm",
               FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_dsm,
            { "DSM Flags", "nvme.cmd.dsm",
               FT_NONE, BASE_NONE, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_dsm_access_freq,
            { "Access frequency", "nvme.cmd.dsm.access_freq",
               FT_UINT8, BASE_HEX, NULL, 0x0f, NULL, HFILL}
        },
        { &hf_nvme_cmd_dsm_access_lat,
            { "Access latency", "nvme.cmd.dsm.access_lat",
               FT_UINT8, BASE_HEX, NULL, 0x30, NULL, HFILL}
        },
        { &hf_nvme_cmd_dsm_seq_req,
            { "Sequential Request", "nvme.cmd.dsm.seq_req",
               FT_UINT8, BASE_HEX, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_cmd_dsm_incompressible,
            { "Incompressible", "nvme.cmd.dsm.incompressible",
               FT_UINT8, BASE_HEX, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_cmd_rsvd3 ,
            { "Reserved", "nvme.cmd.rsvd3",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_dword10[0],
            { "DWORD10", "nvme.cmd.identify.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_dword10[1],
            { "Controller or Namespace Structure (CNS)", "nvme.cmd.identify.dword10.cns",
               FT_UINT32, BASE_HEX, VALS(cns_table), 0xff, NULL, HFILL}
        },
        { &hf_nvme_identify_dword10[2],
            { "Reserved", "nvme.cmd.identify.dword10.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xff00, NULL, HFILL}
        },
        { &hf_nvme_identify_dword10[3],
            { "Controller Identifier (CNTID)", "nvme.cmd.identify.dword10.cntid",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_identify_dword11[0],
            { "DWORD11", "nvme.cmd.identify.dword11",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_dword11[1],
            { "NVM Set Identifier (NVMSETID)", "nvme.cmd.identify.dwrod11.nvmesetid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        /* NVMe Base 2.3 Figure 324: Reserved is 23:16, CSI is 31:24. */
        { &hf_nvme_identify_dword11[2],
            { "Reserved", "nvme.cmd.identify.dword11.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x00ff0000, NULL, HFILL}
        },
        { &hf_nvme_identify_dword11[3],
            { "Command Set Identifier (CSI)", "nvme.cmd.identify.dword11.csi",
               FT_UINT32, BASE_HEX, VALS(csi_tbl), 0xff000000, NULL, HFILL}
        },
        { &hf_nvme_identify_dword14[0],
            { "DWORD14", "nvme.cmd.identify.dword14",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_dword14[1],
            { "UUID Index", "nvme.cmd.identify.dword14.uuid_index",
               FT_UINT32, BASE_HEX, NULL, 0x7f, NULL, HFILL}
        },
        { &hf_nvme_identify_dword14[2],
            { "Reserved", "nvme.cmd.identify.dword14.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffff80, NULL, HFILL}
        },
        /* get log page */
        { &hf_nvme_get_logpage_dword10[0],
            { "DWORD 10", "nvme.cmd.get_logpage.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword10[1],
            { "Log Page Identifier (LID)", "nvme.cmd.get_logpage.dword10.id",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_logpage_lid), 0xff, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword10[2],
            { "Log Specific Field (LSP)", "nvme.cmd.get_logpage.dword10.lsp",
               FT_UINT32, BASE_HEX, NULL, 0x7f00, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword10[3],
            { "Retain Asynchronous Event (RAE)", "nvme.cmd.get_logpage.dword10.rae",
               FT_BOOLEAN, 32, NULL, 0x8000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword10[4],
            { "Number of Dwords Lower (NUMDL)", "nvme.cmd.get_logpage.dword10.numdl",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_numd,
            { "Number of Dwords", "nvme.cmd.get_logpage.numd",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword11[0],
            { "DWORD 11", "nvme.cmd.get_logpage.dword11",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword11[1],
            { "Number of Dwords Upper (NUMDU)", "nvme.cmd.get_logpage.dword11.numdu",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword11[2],
            { "Log Specific Identifier", "nvme.cmd.get_logpage.dword11.lsi",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lpo,
            { "Log Page Offset (DWORD 12 and DWORD 13)", "nvme.cmd.get_logpage.lpo",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword14[0],
            { "DWORD 14", "nvme.cmd.get_logpage.dword14",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* NVMe Base 2.3 Figure 205: UIDX is 06:00, Reserved 22:07, Offset Type
         * bit 23, CSI 31:24. */
        { &hf_nvme_get_logpage_dword14[1],
            { "UUID Index", "nvme.cmd.identify.get_logpage.dword14.uuid_index",
               FT_UINT32, BASE_HEX, NULL, 0x7f, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword14[2],
            { "Reserved", "nvme.cmd.identify.get_logpage.dword14.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x007fff80, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword14[3],
            { "Offset Type (OT)", "nvme.cmd.get_logpage.dword14.ot",
               FT_BOOLEAN, 32, NULL, 0x00800000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_dword14[4],
            { "Command Set Identifier (CSI)", "nvme.cmd.get_logpage.dword14.csi",
               FT_UINT32, BASE_HEX, VALS(csi_tbl), 0xff000000, NULL, HFILL}
        },
        /* Set Features */
        { &hf_nvme_set_features_dword10[0],
            { "DWORD 10", "nvme.cmd.set_features.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_dword10[1],
            { "Feature Identifier", "nvme.cmd.set_features.dword10.fid",
               FT_UINT32, BASE_HEX | BASE_RANGE_STRING, RVALS(fid_table), 0xff, NULL, HFILL}
        },
        { &hf_nvme_set_features_dword10[2],
            { "Reserved", "nvme.cmd.set_features.dword10.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x7fffff00, NULL, HFILL}
        },
        { &hf_nvme_set_features_dword10[3],
            { "Save", "nvme.cmd.set_features.dword10.sv",
               FT_UINT32, BASE_HEX, NULL, 0x80000000, NULL, HFILL}
        },
        { &hf_nvme_set_features_dword14[0],
            { "DWORD 14", "nvme.cmd.set_features.dword14",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_dword14[1],
            { "UUID Index", "nvme.cmd.set_features.dword14.uuid",
               FT_UINT32, BASE_HEX, NULL, 0x7f, NULL, HFILL}
        },
        { &hf_nvme_set_features_dword14[2],
            { "Reserved", "nvme.cmd.set_features.dword14.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffff80, NULL, HFILL}
        },
        /* Format NVM – Command Dword 10 */
        { &hf_nvme_format_nvm_dword10[0],
            { "DWORD10", "nvme.cmd.format_nvm.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_format_nvm_dword10[1],
            { "LBA Format Lower (LBAFL)", "nvme.cmd.format_nvm.dword10.lbafl",
               FT_UINT32, BASE_HEX, NULL, 0x0000000f, NULL, HFILL}
        },
        { &hf_nvme_format_nvm_dword10[2],
            { "Metadata Settings (MSET)", "nvme.cmd.format_nvm.dword10.mset",
               FT_UINT32, BASE_HEX, NULL, 0x00000010, NULL, HFILL}
        },
        { &hf_nvme_format_nvm_dword10[3],
            { "Protection Information (PI)", "nvme.cmd.format_nvm.dword10.pi",
               FT_UINT32, BASE_HEX, NULL, 0x000000e0, NULL, HFILL}
        },
        { &hf_nvme_format_nvm_dword10[4],
            { "Protection Information Location (PIL)", "nvme.cmd.format_nvm.dword10.pil",
               FT_UINT32, BASE_HEX, NULL, 0x00000100, NULL, HFILL}
        },
        { &hf_nvme_format_nvm_dword10[5],
            { "Secure Erase Settings (SES)", "nvme.cmd.format_nvm.dword10.ses",
               FT_UINT32, BASE_HEX, VALS(fmt_nvm_ses_tbl), 0x00000e00, NULL, HFILL}
        },
        { &hf_nvme_format_nvm_dword10[6],
            { "LBA Format Upper (LBAFU)", "nvme.cmd.format_nvm.dword10.lbafu",
               FT_UINT32, BASE_HEX, NULL, 0x00003000, NULL, HFILL}
        },
        { &hf_nvme_format_nvm_dword10[7],
            { "Reserved", "nvme.cmd.format_nvm.dword10.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffc000, NULL, HFILL}
        },
        /* Firmware Commit – Command Dword 10 */
        { &hf_nvme_fw_commit_dword10[0],
            { "DWORD10", "nvme.cmd.fw_commit.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_fw_commit_dword10[1],
            { "Firmware Slot (FS)", "nvme.cmd.fw_commit.dword10.fs",
               FT_UINT32, BASE_HEX, NULL, 0x00000007, NULL, HFILL}
        },
        { &hf_nvme_fw_commit_dword10[2],
            { "Commit Action (CA)", "nvme.cmd.fw_commit.dword10.ca",
               FT_UINT32, BASE_HEX, VALS(fw_commit_ca_tbl), 0x00000038, NULL, HFILL}
        },
        { &hf_nvme_fw_commit_dword10[3],
            { "Reserved", "nvme.cmd.fw_commit.dword10.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x7fffffc0, NULL, HFILL}
        },
        { &hf_nvme_fw_commit_dword10[4],
            { "Boot Partition ID (BPID)", "nvme.cmd.fw_commit.dword10.bpid",
               FT_UINT32, BASE_HEX, NULL, 0x80000000, NULL, HFILL}
        },
        /* Firmware Image Download – Command Dwords 10/11 */
        { &hf_nvme_fw_download_numd,
            { "Number of Dwords (NUMD)", "nvme.cmd.fw_download.numd",
               FT_UINT32, BASE_HEX, NULL, 0x0,
               "Number of dwords to transfer, a 0's based value", HFILL}
        },
        { &hf_nvme_fw_download_ofst,
            { "Offset (OFST)", "nvme.cmd.fw_download.ofst",
               FT_UINT32, BASE_HEX, NULL, 0x0,
               "Dword offset from the start of the firmware image", HFILL}
        },
        /* Device Self-test – Command Dword 10 */
        { &hf_nvme_self_test_dword10[0],
            { "DWORD10", "nvme.cmd.self_test.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_self_test_dword10[1],
            { "Self-test Code (STC)", "nvme.cmd.self_test.dword10.stc",
               FT_UINT32, BASE_HEX, VALS(self_test_stc_tbl), 0x0000000f, NULL, HFILL}
        },
        { &hf_nvme_self_test_dword10[2],
            { "Reserved", "nvme.cmd.self_test.dword10.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffff0, NULL, HFILL}
        },
        /* Lockdown – Command Dword 10 */
        { &hf_nvme_lockdown_dword10[0],
            { "DWORD10", "nvme.cmd.lockdown.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_lockdown_dword10[1],
            { "Scope (SCP)", "nvme.cmd.lockdown.dword10.scp",
               FT_UINT32, BASE_HEX, VALS(lockdown_scp_tbl), 0x0000000f, NULL, HFILL}
        },
        { &hf_nvme_lockdown_dword10[2],
            { "Prohibit (PRHBT)", "nvme.cmd.lockdown.dword10.prhbt",
               FT_UINT32, BASE_HEX, NULL, 0x00000010, NULL, HFILL}
        },
        { &hf_nvme_lockdown_dword10[3],
            { "Interface (IFC)", "nvme.cmd.lockdown.dword10.ifc",
               FT_UINT32, BASE_HEX, VALS(lockdown_ifc_tbl), 0x00000060, NULL, HFILL}
        },
        { &hf_nvme_lockdown_dword10[4],
            { "Reserved", "nvme.cmd.lockdown.dword10.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0x00000080, NULL, HFILL}
        },
        { &hf_nvme_lockdown_dword10[5],
            { "Opcode or Feature Identifier (OFI)", "nvme.cmd.lockdown.dword10.ofi",
               FT_UINT32, BASE_HEX, NULL, 0x0000ff00, NULL, HFILL}
        },
        { &hf_nvme_lockdown_dword10[6],
            { "Reserved", "nvme.cmd.lockdown.dword10.rsvd1",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        /* Lockdown – Command Dword 14 */
        { &hf_nvme_lockdown_dword14[0],
            { "DWORD14", "nvme.cmd.lockdown.dword14",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_lockdown_dword14[1],
            { "UUID Index (UIDX)", "nvme.cmd.lockdown.dword14.uidx",
               FT_UINT32, BASE_HEX, NULL, 0x0000007f, NULL, HFILL}
        },
        { &hf_nvme_lockdown_dword14[2],
            { "Reserved", "nvme.cmd.lockdown.dword14.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffff80, NULL, HFILL}
        },
        /* Sanitize – Command Dwords 10/11 */
        { &hf_nvme_sanitize_dword10[0],
            { "DWORD10", "nvme.cmd.sanitize.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_sanitize_dword10[1],
            { "Sanitize Action (SANACT)", "nvme.cmd.sanitize.dword10.sanact",
               FT_UINT32, BASE_HEX, VALS(sanitize_act_tbl), 0x00000007, NULL, HFILL}
        },
        { &hf_nvme_sanitize_dword10[2],
            { "Allow Unrestricted Sanitize Exit (AUSE)", "nvme.cmd.sanitize.dword10.ause",
               FT_UINT32, BASE_HEX, NULL, 0x00000008, NULL, HFILL}
        },
        { &hf_nvme_sanitize_dword10[3],
            { "Overwrite Pass Count (OWPASS)", "nvme.cmd.sanitize.dword10.owpass",
               FT_UINT32, BASE_HEX, NULL, 0x000000f0, NULL, HFILL}
        },
        { &hf_nvme_sanitize_dword10[4],
            { "Overwrite Invert Pattern Between Passes (OIPBP)", "nvme.cmd.sanitize.dword10.oipbp",
               FT_UINT32, BASE_HEX, NULL, 0x00000100, NULL, HFILL}
        },
        { &hf_nvme_sanitize_dword10[5],
            { "No-Deallocate After Sanitize (NDAS)", "nvme.cmd.sanitize.dword10.ndas",
               FT_UINT32, BASE_HEX, NULL, 0x00000200, NULL, HFILL}
        },
        { &hf_nvme_sanitize_dword10[6],
            { "Enter Media Verification State (EMVS)", "nvme.cmd.sanitize.dword10.emvs",
               FT_UINT32, BASE_HEX, NULL, 0x00000400, NULL, HFILL}
        },
        { &hf_nvme_sanitize_dword10[7],
            { "Reserved", "nvme.cmd.sanitize.dword10.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffff800, NULL, HFILL}
        },
        { &hf_nvme_sanitize_ovrpat,
            { "Overwrite Pattern (OVRPAT)", "nvme.cmd.sanitize.ovrpat",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Security Send (81h) / Security Receive (82h) */
        { &hf_nvme_security_dword10[0],
            { "DWORD10", "nvme.cmd.security.dword10",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_security_dword10[1],
            { "Security Protocol (SECP)", "nvme.cmd.security.dword10.secp",
               FT_UINT32, BASE_HEX | BASE_RANGE_STRING, RVALS(security_secp_tbl), 0xff000000, NULL, HFILL}
        },
        { &hf_nvme_security_dword10[2],
            { "SP Specific 1 (SPSP1)", "nvme.cmd.security.dword10.spsp1",
               FT_UINT32, BASE_HEX, NULL, 0x00ff0000, NULL, HFILL}
        },
        { &hf_nvme_security_dword10[3],
            { "SP Specific 0 (SPSP0)", "nvme.cmd.security.dword10.spsp0",
               FT_UINT32, BASE_HEX, NULL, 0x0000ff00, NULL, HFILL}
        },
        { &hf_nvme_security_dword10[4],
            { "NVMe Security Specific Field (NSSF)", "nvme.cmd.security.dword10.nssf",
               FT_UINT32, BASE_HEX, NULL, 0x000000ff, NULL, HFILL}
        },
        { &hf_nvme_security_send_dword11_tl,
            { "Transfer Length (TL)", "nvme.cmd.security_send.dword11.tl",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_security_recv_dword11_al,
            { "Allocation Length (AL)", "nvme.cmd.security_recv.dword11.al",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_security_data,
            { "Security Protocol Data", "nvme.cmd.security.data",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_security_info,
            { "Security Protocol Information", "nvme.security.info",
               FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_security_info_rsvd,
            { "Reserved", "nvme.security.info.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_security_info_list_len,
            { "Supported Security Protocol List Length", "nvme.security.info.list_len",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_security_info_protocol,
            { "Supported Security Protocol", "nvme.security.info.protocol",
               FT_UINT8, BASE_HEX | BASE_RANGE_STRING, RVALS(security_secp_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_security_info_cert_len,
            { "Certificate Data Length", "nvme.security.info.cert_len",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_security_info_cert_data,
            { "Certificate Data", "nvme.security.info.cert_data",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_arb[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.arb",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_arb[1],
            { "Arbitration Burst", "nvme.cmd.set_features.dword11.arb.ab",
               FT_UINT32, BASE_HEX, NULL, 0x7, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_arb[2],
            { "Reserved", "nvme.cmd.set_features.dword11.arb.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_arb[3],
            { "Low Priority Weight", "nvme.cmd.set_features.dword11.arb.lpw",
               FT_UINT32, BASE_HEX, NULL, 0xff00, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_arb[4],
            { "Medium Priority Weight", "nvme.cmd.set_features.dword11.arb.mpw",
               FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_arb[5],
            { "High Priority Weight", "nvme.cmd.set_features.dword11.arb.hpw",
               FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_pm[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.pm",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_pm[1],
            { "Power State", "nvme.cmd.set_features.dword11.pm.ps",
               FT_UINT32, BASE_HEX, NULL, 0x1f, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_pm[2],
            { "Work Hint", "nvme.cmd.set_features.dword11.pm.wh",
               FT_UINT32, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_pm[3],
            { "Reserved", "nvme.cmd.set_features.dword11.pm.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffff00, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_lbart[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.lbart",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_lbart[1],
            { "Number of LBA Ranges (NUM)", "nvme.cmd.set_features.dword11.lbart.lbarn",
               FT_UINT32, BASE_HEX, NULL, 0x3f, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_lbart[2],
            { "Reserved", "nvme.cmd.set_features.dword11.lbart.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffffc0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_tt[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.tt",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_tt[1],
            { "Temperature Threshold", "nvme.cmd.set_features.dword11.tt.tmpth",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_tt[2],
            { "Threshold Temperature Select", "nvme.cmd.set_features.dword11.tt.tmpsel",
               FT_UINT32, BASE_HEX, VALS(sf_tmpsel_table), 0xf0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_tt[3],
            { "Threshold Type Select", "nvme.cmd.set_features.dword11.tt.thpsel",
               FT_UINT32, BASE_HEX, VALS(sf_thpsel_table), 0x300000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_tt[4],
            { "Temperature Threshold Hysteresis", "nvme.cmd.set_features.dword11.tt.tmpthh",
               FT_UINT32, BASE_HEX, NULL, 0x1c00000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_tt[5],
            { "Reserved", "nvme.cmd.set_features.dword11.tt.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfe000000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_erec[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.erec",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_erec[1],
            { "Time Limited Error Recovery (100 ms units)", "nvme.cmd.set_features.dword11.erec.tler",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_erec[2],
            { "Deallocated or Unwritten Logical Block Error Enable", "nvme.cmd.set_features.dword11.erec.dulbe",
               FT_BOOLEAN, 32, NULL, 0x10000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_erec[3],
            { "Reserved", "nvme.cmd.set_features.dword11.erec.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfe0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_vwce[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.vwce",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_vwce[1],
            { "Volatile Write Cache Enable", "nvme.cmd.set_features.dword11.vwce.wce",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_vwce[2],
            { "Reserved", "nvme.cmd.set_features.dword11.vwce.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nq[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.nq",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nq[1],
            { "Number of IO Submission Queues Requested", "nvme.cmd.set_features.dword11.nq.nsqr",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nq[2],
            { "Number of IO Completion Queues Requested", "nvme.cmd.set_features.dword11.nq.ncqr",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_irqc[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.irqc",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_irqc[1],
            { "Aggregation Threshold", "nvme.cmd.set_features.dword11.irqc.thr",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_irqc[2],
            { "Aggregation Time (100 us units)", "nvme.cmd.set_features.dword11.irqc.time",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_irqv[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.irqv",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_irqv[1],
            { "IRQ Vector", "nvme.cmd.set_features.dword11.irqv.iv",
               FT_UINT32, BASE_HEX, NULL, 0x0000ffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_irqv[2],
            { "Coalescing Disable", "nvme.cmd.set_features.dword11.irqv.cd",
               FT_BOOLEAN, 32, NULL, 0x00010000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_irqv[3],
            { "Reserved", "nvme.cmd.set_features.dword11.irqv.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffe0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_wan[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.wan",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_wan[1],
            { "Disable Normal", "nvme.cmd.set_features.dword11.wan.dn",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_wan[2],
            { "Reserved", "nvme.cmd.set_features.dword11.wan.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.aec",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[1],
            { "SMART and Health Critical Warnings Bitmask", "nvme.cmd.set_features.dword11.aec.smart",
               FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[2],
            { "Namespace Attribute Notices", "nvme.cmd.set_features.dword11.aec.ns",
               FT_BOOLEAN, 32, NULL, 0x100, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[3],
            { "Firmware Activation Notices", "nvme.cmd.set_features.dword11.aec.fwa",
               FT_BOOLEAN, 32, NULL, 0x200, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[4],
            { "Telemetry Log Notices", "nvme.cmd.set_features.dword11.aec.tel",
               FT_BOOLEAN, 32, NULL, 0x400, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[5],
            { "ANA Change Notices", "nvme.cmd.set_features.dword11.aec.ana",
               FT_BOOLEAN, 32, NULL, 0x800, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[6],
            { "Predictable Latency Event Aggregate Log Change Notices", "nvme.cmd.set_features.dword11.aec.plat",
               FT_BOOLEAN, 32, NULL, 0x1000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[7],
            { "LBA Status Information Notices", "nvme.cmd.set_features.dword11.aec.lba",
               FT_BOOLEAN, 32, NULL, 0x2000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[8],
            { "Endurance Group Event Aggregate Log Change Notices", "nvme.cmd.set_features.dword11.aec.eg",
               FT_BOOLEAN, 32, NULL, 0x4000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[9],
            { "Reserved", "nvme.cmd.set_features.dword11.aec.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x7fff8000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_aec[10],
            { "Discovery Log Page Change Notification", "nvme.cmd.set_features.dword11.aec.disc",
               FT_BOOLEAN, 32, NULL, 0x80000000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_apst[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.apst",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_apst[1],
            { "Autonomous Power State Transition Enable", "nvme.cmd.set_features.dword11.apst.apste",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_apst[2],
            { "Reserved", "nvme.cmd.set_features.dword11.apst.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_kat[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.kat",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_kat[1],
            { "Keep Alive Timeout", "nvme.cmd.set_features.dword11.kat.kato",
               FT_UINT32, BASE_DEC|BASE_UNIT_STRING, UNS(&units_milliseconds), 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hctm[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.hctm",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hctm[1],
            { "Thermal Management Temperature 2 (K)", "nvme.cmd.set_features.dword11.hctm.tmt2",
               FT_UINT32, BASE_HEX, NULL, 0x0000ffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hctm[2],
            { "Thermal Management Temperature 1 (K)", "nvme.cmd.set_features.dword11.hctm.tmt1",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nops[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.nops",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nops[1],
            { "Non-Operational Power State Permissive Mode Enable", "nvme.cmd.set_features.dword11.nops.noppme",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nops[2],
            { "Reserved", "nvme.cmd.set_features.dword11.nops.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rrl[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.rrl",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rrl[1],
            { "NVM Set Identifier", "nvme.cmd.set_features.dword11.rrl.nvmsetid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rrl[2],
            { "Reserved", "nvme.cmd.set_features.dword11.rrl.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_rrl[0],
            { "DWORD12", "nvme.cmd.set_features.dword12.rrl",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_rrl[1],
            { "Read Recovery Level", "nvme.cmd.set_features.dword12.rrl.rrl",
               FT_UINT32, BASE_HEX, NULL, 0xf, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_rrl[2],
            { "Reserved", "nvme.cmd.set_features.dword12.rrl.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffff0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plmc[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.plmc",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plmc[1],
            { "NVM Set Identifier", "nvme.cmd.set_features.dword11.plmc.nvmsetid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plmc[2],
            { "Reserved", "nvme.cmd.set_features.dword11.plmc.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_plmc[0],
            { "DWORD12", "nvme.cmd.set_features.dword12.plmc",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_plmc[1],
            { "Predictable Latency Enable", "nvme.cmd.set_features.dword12.plmc.ple",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_plmc[2],
            { "Reserved", "nvme.cmd.set_features.dword12.plmc.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plmw[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.plmw",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plmw[1],
            { "NVM Set Identifier", "nvme.cmd.set_features.dword11.plmw.nvmsetid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plmw[2],
            { "Reserved", "nvme.cmd.set_features.dword11.plmw.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_plmw[0],
            { "DWORD12", "nvme.cmd.set_features.dword12.plmw",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_plmw[1],
            { "Window Select (WSEL)", "nvme.cmd.set_features.dword12.plmw.ws",
               FT_UINT32, BASE_HEX, VALS(sf_ws_table), 0x7, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword12_plmw[2],
            { "Reserved", "nvme.cmd.set_features.dword12.plmw.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffff8, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_lbasi[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.lbasi",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_lbasi[1],
            { "LBA Status Information Report Interval (100 ms)", "nvme.cmd.set_features.dword11.lbasi.lsiri",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_lbasi[2],
            { "LBA Status Information Poll Interval (100 ms)", "nvme.cmd.set_features.dword11.lbasi.lsipi",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_san[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.san",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_san[1],
            { "No-Deallocate Response Mode", "nvme.cmd.set_features.dword11.san.nodrm",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_san[2],
            { "Reserved", "nvme.cmd.set_features.dword11.san.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_eg[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.eg",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_eg[1],
            { "Endurance Group Identifier", "nvme.cmd.set_features.dword11.eg.endgid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_eg[2],
            { "Endurance Group Critical Warnings Bitmask", "nvme.cmd.set_features.dword11.eg.egcw",
               FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_eg[3],
            { "Reserved", "nvme.cmd.set_features.dword11.eg.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_swp[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.swp",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_swp[1],
            { "Pre-boot Software Load Count", "nvme.cmd.set_features.dword11.swp.pbslc",
               FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_swp[2],
            { "Reserved", "nvme.cmd.set_features.dword11.swp.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffff00, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hid[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.hid",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hid[1],
            { "Enable Extended Host Identifier", "nvme.cmd.set_features.dword11.hid.exhid",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hid[2],
            { "Reserved", "nvme.cmd.set_features.dword11.hid.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvn[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.rsrvn",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvn[1],
            { "Reserved", "nvme.cmd.set_features.dword11.rsrvn.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvn[2],
            { "Mask Registration Preempted Notification" , "nvme.cmd.set_features.dword11.rsrvn.regpre",
               FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvn[3],
            { "Mask Reservation Released Notification", "nvme.cmd.set_features.dword11.rsrvn.resrel",
               FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvn[4],
            { "Mask Reservation Preempted Notification", "nvme.cmd.set_features.dword11.rsrvn.resrpe",
               FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvn[5],
            { "Reserved", "nvme.cmd.set_features.dword11.rsrvn.rsvd1",
               FT_UINT32, BASE_HEX, NULL, 0xfffff0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvp[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.rsrvp",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvp[1],
            { "Persist Through Power Loss", "nvme.cmd.set_features.dword11.rsrvp.ptpl",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_rsrvp[2],
            { "Reserved", "nvme.cmd.set_features.dword11.rsrvp.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nswp[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.nswp",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nswp[1],
            { "Write Protection State (WPS)", "nvme.cmd.set_features.dword11.nswp.wps",
               FT_UINT32, BASE_HEX, VALS(sf_wps), 0x7, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_nswp[2],
            { "Reserved", "nvme.cmd.set_features.dword11.nswp.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffff8, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmd[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.hmd",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmd[1],
            { "Element Action", "nvme.cmd.set_features.dword11.hmd.ea",
               FT_UINT32, BASE_HEX, VALS(sf_host_metadata_ea), 0x6000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmd[2],
            { "Reserved", "nvme.cmd.set_features.dword11.hmd.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff9fff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmb[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.hmb",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmb[1],
            { "Enable Host Memory (EHM)", "nvme.cmd.set_features.dword11.hmb.ehm",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmb[2],
            { "Memory Return (MR)", "nvme.cmd.set_features.dword11.hmb.mr",
               FT_UINT32, BASE_HEX, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmb[3],
            { "Host Memory Non-operational Access Restriction Enable (HMNARE)", "nvme.cmd.set_features.dword11.hmb.hmnare",
               FT_UINT32, BASE_HEX, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmb[4],
            { "Cleared to Zero (CTZ)", "nvme.cmd.set_features.dword11.hmb.ctz",
               FT_UINT32, BASE_HEX, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_hmb[5],
            { "Reserved", "nvme.cmd.set_features.dword11.hmb.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffff0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_iocsp[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.iocsp",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_iocsp[1],
            { "I/O Command Set Combination Index (IOCSCI)", "nvme.cmd.set_features.dword11.iocsp.iocsci",
               FT_UINT32, BASE_HEX, NULL, 0x1ff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_iocsp[2],
            { "Reserved", "nvme.cmd.set_features.dword11.iocsp.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffe00, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_spinup[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.spinup",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_spinup[1],
            { "Spinup Control Enable (SCE)", "nvme.cmd.set_features.dword11.spinup.sce",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_spinup[2],
            { "Reserved", "nvme.cmd.set_features.dword11.spinup.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plsc[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.plsc",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plsc[1],
            { "Power Loss Signaling Mode (PLSM)", "nvme.cmd.set_features.dword11.plsc.plsm",
               FT_UINT32, BASE_HEX, VALS(sf_plsm), 0x3, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_plsc[2],
            { "Reserved", "nvme.cmd.set_features.dword11.plsc.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffc, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_fdp[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.fdp",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_fdp[1],
            { "Endurance Group Identifier (ENDGID)", "nvme.cmd.set_features.dword11.fdp.endgid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_fdp[2],
            { "Reserved", "nvme.cmd.set_features.dword11.fdp.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_fdpe[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.fdpe",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_fdpe[1],
            { "Placement Handle (PHNDL)", "nvme.cmd.set_features.dword11.fdpe.phndl",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_fdpe[2],
            { "Number of FDP Event Types (NOET)", "nvme.cmd.set_features.dword11.fdpe.noet",
               FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_fdpe[3],
            { "Reserved", "nvme.cmd.set_features.dword11.fdpe.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_bpwpc[0],
            { "DWORD11", "nvme.cmd.set_features.dword11.bpwpc",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_bpwpc[1],
            { "Boot Partition 0 Write Protection State (BP0WPS)", "nvme.cmd.set_features.dword11.bpwpc.bp0wps",
               FT_UINT32, BASE_HEX, VALS(sf_bpwps), 0x7, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_bpwpc[2],
            { "Boot Partition 1 Write Protection State (BP1WPS)", "nvme.cmd.set_features.dword11.bpwpc.bp1wps",
               FT_UINT32, BASE_HEX, VALS(sf_bpwps), 0x38, NULL, HFILL}
        },
        { &hf_nvme_cmd_set_features_dword11_bpwpc[3],
            { "Reserved", "nvme.cmd.set_features.dword11.bpwpc.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffffc0, NULL, HFILL}
        },
        /* Set Features Transfers */
        { &hf_nvme_set_features_tr_lbart,
            { "LBA Range Structure", "nvme.set_features.lbart",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_type,
            { "Type", "nvme.set_features.lbart.type",
               FT_UINT8, BASE_HEX | BASE_RANGE_STRING, RVALS(sf_lbart_type_table), 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_attr[0],
            { "Attributes", "nvme.set_features.lbart.attr",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_attr[1],
            { "LBA Range may be overwritten", "nvme.set_features.lbart.attr.ovw",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_attr[2],
            { "LBA Range shall be hidden from OS/EFI/BIOS", "nvme.set_features.lbart.attr.hid",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_attr[3],
            { "Reserved", "nvme.set_features.lbart.attr.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_rsvd0,
            { "Reserved", "nvme.set_features.lbart.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_slba,
            { "Starting LBA", "nvme.set_features.lbart.slba",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_nlb,
            { "Number of Logical Blocks", "nvme.set_features.lbart.nlb",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_guid,
            { "Unique Identifier", "nvme.set_features.lbart.guid",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_lbart_rsvd1,
            { "Reserved", "nvme.set_features.lbart.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_apst[0],
            { "Autonomous Power State Transition Structure", "nvme.set_features.lbart.apst",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_apst[1],
            { "Reserved", "nvme.set_features.lbart.apst.rsvd0",
               FT_UINT64, BASE_HEX, NULL, 0x7, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_apst[2],
            { "Idle Transition Power State", "nvme.set_features.lbart.apst.itps",
               FT_UINT64, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_apst[3],
            { "Idle Time Prior to Transition (ms)", "nvme.set_features.lbart.apst.itpt",
               FT_UINT64, BASE_HEX, NULL, 0xffffff00, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_apst[4],
            { "Reserved", "nvme.set_features.lbart.apst.rsvd1",
               FT_UINT64, BASE_HEX, NULL, 0xffffffff00000000, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_tst[0],
            { "Timestamp Structure", "nvme.set_features.tst",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_tst[1],
            { "Timestamp (milliseconds since 01-Jan-1970)", "nvme.set_features.tst.ms",
               FT_UINT64, BASE_HEX, NULL, 0xffffffffffff, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_tst[2],
            { "Reserved", "nvme.set_features.tst.rsvd",
               FT_UINT64, BASE_HEX, NULL, 0xffff000000000000, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc,
            { "Deterministic Threshold Configuration Structure", "nvme.set_features.plmc",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_ee[0],
            { "Enable Event", "nvme.set_features.plmc.ee",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_ee[1],
            { "DTWIN Reads Warning", "nvme.set_features.plmc.ee.dtwinr",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_ee[2],
            { "DTWIN Writes Warning", "nvme.set_features.plmc.ee.dtwinw",
               FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_ee[3],
            { "DTWIN Time Warning", "nvme.set_features.plmc.ee.dtwint",
               FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_ee[4],
            { "Reserved", "nvme.set_features.plmc.ee.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0x3ff8, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_ee[5],
            { "DTWIN to NDWIN transition due to typical or maximum value exceeded", "nvme.set_features.plmc.ee.ndtwindv",
               FT_BOOLEAN, 16, NULL, 0x4000, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_ee[6],
            { "DTWIN to NDWIN transition due to Deterministic Excursion", "nvme.set_features.plmc.ee.ndtwindde",
               FT_BOOLEAN, 16, NULL, 0x8000, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_rsvd0,
            { "Reserved", "nvme.set_features.plmc.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_dtwinrt,
            { "DTWIN Reads Threshold", "nvme.set_features.plmc.dtwinrt",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_dtwinwt,
            { "DTWIN Writes Threshold", "nvme.set_features.plmc.dtwinwt",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_dtwintt,
            { "DTWIN Time Threshold", "nvme.set_features.plmc.dtwintt",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_plmc_rsvd1,
            { "Reserved", "nvme.set_features.plmc.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs,
            { "Host Behavior Support Structure", "nvme.set_features.hbs",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_acre,
            { "Advanced Command Retry Enable", "nvme.set_features.hbs.acre",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_etdas,
            { "Extended Telemetry Data Area 4 Supported", "nvme.set_features.hbs.etdas",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_lbafee,
            { "LBA Format Extension Enable", "nvme.set_features.hbs.lbafee",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_hdisns,
            { "Host Dispersed Namespace Support", "nvme.set_features.hbs.hdisns",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_cdfe[0],
            { "Copy Descriptor Formats Enable (CDFE)", "nvme.set_features.hbs.cdfe",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_cdfe[1],
            { "Not Used (NUSED)", "nvme.set_features.hbs.cdfe.nused",
               FT_UINT16, BASE_HEX, NULL, 0x0003, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_cdfe[2],
            { "Copy Descriptor Format 2h Enable", "nvme.set_features.hbs.cdfe.cdf2e",
               FT_BOOLEAN, 16, NULL, 0x0004, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_cdfe[3],
            { "Copy Descriptor Format 3h Enable", "nvme.set_features.hbs.cdfe.cdf3e",
               FT_BOOLEAN, 16, NULL, 0x0008, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_cdfe[4],
            { "Copy Descriptor Format 4h Enable", "nvme.set_features.hbs.cdfe.cdf4e",
               FT_BOOLEAN, 16, NULL, 0x0010, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_cdfe[5],
            { "Reserved", "nvme.set_features.hbs.cdfe.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0xffe0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hbs_rsvd,
            { "Reserved", "nvme.set_features.hbs.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hmd,
            { "Host Metadata Data Structure", "nvme.set_features.hmd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hmd_nmed,
            { "Number of Metadata Element Descriptors", "nvme.set_features.hmd.nmed",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hmd_rsvd,
            { "Reserved", "nvme.set_features.hmd.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hmd_med,
            { "Metadata Element Descriptor", "nvme.set_features.hmd.med",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hmd_med_et,
            { "Element Type", "nvme.set_features.hmd.med.et",
               FT_UINT32, BASE_HEX, NULL, 0x0000001f, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hmd_med_er,
            { "Element Revision", "nvme.set_features.hmd.med.er",
               FT_UINT32, BASE_HEX, NULL, 0x00000f00, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hmd_med_elen,
            { "Element Length", "nvme.set_features.hmd.med.elen",
               FT_UINT32, BASE_DEC, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_set_features_tr_hmd_med_eval,
            { "Element Value", "nvme.set_features.hmd.med.eval",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Get Features */
        { &hf_nvme_get_features_dword10[0],
            { "DWORD 10", "nvme.cmd.get_features.dword10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_features_dword10[1],
            { "Feature Identifier", "nvme.cmd.get_features.dword10.fid",
               FT_UINT32, BASE_HEX | BASE_RANGE_STRING, RVALS(fid_table), 0xff, NULL, HFILL}
        },
        { &hf_nvme_get_features_dword10[2],
            { "Select", "nvme.cmd.set_features.dword10.sel",
               FT_UINT32, BASE_HEX, VALS(sel_table), 0x700, NULL, HFILL}
        },
        { &hf_nvme_get_features_dword10[3],
            { "Reserved", "nvme.cmd.get_features.dword10.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffff800, NULL, HFILL}
        },
        { &hf_nvme_get_features_dword14[0],
            { "DWORD 14", "nvme.cmd.get_features.dword14",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_features_dword14[1],
            { "UUID Index", "nvme.cmd.get_features.dword14.uuid",
               FT_UINT32, BASE_HEX, NULL, 0x7f, NULL, HFILL}
        },
        { &hf_nvme_get_features_dword14[2],
            { "Reserved", "nvme.cmd.get_features.dword14.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffff80, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_rrl[0],
            { "DWORD11", "nvme.cmd.get_features.dword11.rrl",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_rrl[1],
            { "NVM Set Identifier", "nvme.cmd_get_features.dword11.rrl.nvmsetid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_rrl[2],
            { "Reserved", "nvme.cmd.get_features.dword11.rrl.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_plmc[0],
            { "DWORD11", "nvme.cmd.get_features.dword11.plmc",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_plmc[1],
            { "NVM Set Identifier", "nvme.cmd.get_features.dword11.plmc.nvmsetid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_plmc[2],
            { "Reserved", "nvme.cmd.get_features.dword11.plmc.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_plmw[0],
            { "DWORD11", "nvme.cmd.get_features.dword11.plmw",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_plmw[1],
            { "NVM Set Identifier", "nvme.cmd.get_features.dword11.plmw.nvmsetid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cmd_get_features_dword11_plmw[2],
            { "Reserved", "nvme.cmd.get_features.dword11.plmw.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        /* Identify NS response */
        { &hf_nvme_identify_ns_nsze,
            { "Namespace Size (NSZE)", "nvme.cmd.identify.ns.nsze",
               FT_UINT64, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_ncap,
            { "Namespace Capacity (NCAP)", "nvme.cmd.identify.ns.ncap",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nuse,
            { "Namespace Utilization (NUSE)", "nvme.cmd.identify.ns.nuse",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nsfeat,
            { "Namespace Features (NSFEAT)", "nvme.cmd.identify.ns.nsfeat",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nlbaf,
            { "Number of LBA Formats (NLBAF)", "nvme.cmd.identify.ns.nlbaf",
               FT_UINT8, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_flbas,
            { "Formatted LBA Size (FLBAS)", "nvme.cmd.identify.ns.flbas",
               FT_UINT8, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_mc,
            { "Metadata Capabilities (MC)", "nvme.cmd.identify.ns.mc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_dpc,
            { "End-to-end Data Protection Capabilities (DPC)", "nvme.cmd.identify.ns.dpc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_dps,
            { "End-to-end Data Protection Type Settings (DPS)", "nvme.cmd.identify.ns.dps",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nmic,
            { "Namespace Multi-path I/O and Namespace Sharing Capabilities (NMIC)",
              "nvme.cmd.identify.ns.nmic", FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_rescap,
            { "Reservation Capabilities (RESCAP)", "nvme.cmd.identify.ns.rescap",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_fpi,
            { "Format Progress Indicator (FPI)", "nvme.cmd.identify.ns.fpi",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_dlfeat[0],
            { "Deallocate Logical Block Features (DLFEAT)", "nvme.cmd.identify.ns.dlfeat",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_dlfeat[1],
            { "Deallocation Read Behavior (DRB)", "nvme.cmd.identify.ns.dlfeat.drb",
               FT_UINT8, BASE_HEX, VALS(ns_dlfeat_drb_tbl), 0x7, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_dlfeat[2],
            { "Write Zeroes Deallocation Support (WZDS)", "nvme.cmd.identify.ns.dlfeat.wzds",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_dlfeat[3],
            { "Guard Deallocation Status (GDS)", "nvme.cmd.identify.ns.dlfeat.gds",
               FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_dlfeat[4],
            { "Reserved", "nvme.cmd.identify.ns.dlfeat.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nawun,
            { "Namespace Atomic Write Unit Normal (NAWUN)", "nvme.cmd.identify.ns.nawun",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nawupf,
            { "Namespace Atomic Write Unit Power Fail (NAWUPF)", "nvme.cmd.identify.ns.nawupf",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nacwu,
            { "Namespace Atomic Compare & Write Unit (NACWU)", "nvme.cmd.identify.ns.nacwu",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nabsn,
            { "Namespace Atomic Boundary Size Normal (NABSN)", "nvme.cmd.identify.ns.nabsn",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nabo,
            { "Namespace Atomic Boundary Offset (NABO)", "nvme.cmd.identify.ns.nabo",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nabspf,
            { "Namespace Atomic Boundary Size Power Fail (NABSPF)", "nvme.cmd.identify.ns.nabspf",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_noiob,
            { "Namespace Optimal I/O Boundary (NOIOB)", "nvme.cmd.identify.ns.noiob",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nvmcap,
            { "NVM Capacity (NVMCAP)", "nvme.cmd.identify.ns.nvmcap",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_npwg,
            { "Namespace Preferred Write Granularity (NPWG)", "nvme.cmd.identify.ns.npwg",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_npwa,
            { "Namespace Preferred Write Alignment (NPWA)", "nvme.cmd.identify.ns.npwa",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_npdg,
            { "Namespace Preferred Deallocate Granularity (NPDG)", "nvme.cmd.identify.ns.npdg",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_npda,
            { "Namespace Preferred Deallocate Alignment (NPDA)", "nvme.cmd.identify.ns.npda",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nows,
            { "Namespace Optimal Write Size (NOWS)", "nvme.cmd.identify.ns.nows",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_mssrl,
            { "Maximum Single Source Range Length (MSSRL)", "nvme.cmd.identify.ns.mssrl",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_mcl,
            { "Maximum Copy Length (MCL)", "nvme.cmd.identify.ns.mcl",
               FT_UINT32, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_msrc,
            { "Maximum Source Range Count (MSRC)", "nvme.cmd.identify.ns.msrc",
               FT_UINT8, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_kpios[0],
            { "Key Per I/O Status (KPIOS)", "nvme.cmd.identify.ns.kpios",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_kpios[1],
            { "Key Per I/O Enabled in Namespace (KPIOENS)", "nvme.cmd.identify.ns.kpios.kpioens",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_kpios[2],
            { "Key Per I/O Supported in Namespace (KPIOSNS)", "nvme.cmd.identify.ns.kpios.kpiosns",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_kpios[3],
            { "Reserved", "nvme.cmd.identify.ns.kpios.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nulbaf,
            { "Number of Unique Attribute LBA Formats (NULBAF)", "nvme.cmd.identify.ns.nulbaf",
               FT_UINT8, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_rsvd0,
            { "Reserved", "nvme.cmd.identify.ns.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_kpiodaag,
            { "Key Per I/O Data Access Alignment and Granularity (KPIODAAG)",
              "nvme.cmd.identify.ns.kpiodaag",
               FT_UINT32, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_rsvd1,
            { "Reserved", "nvme.cmd.identify.ns.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_anagrpid,
            { "ANA Group Identifier (ANAGRPID)", "nvme.cmd.identify.ns.anagrpid",
               FT_UINT32, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_rsvd2,
            { "Reserved", "nvme.cmd.identify.ns.rsvd2",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nsattr,
            { "Namespace Attributes (NSATTR)", "nvme.cmd.identify.ns.nsattr",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nvmsetid,
            { "NVM Set Identifier (NVMSETID)", "nvme.cmd.identify.ns.nvmsetid",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_endgid,
            { "Endurance Group Identifier (ENDGID)", "nvme.cmd.identify.ns.endgid",
               FT_UINT16, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_nguid,
            { "Namespace Globally Unique Identifier (NGUID)", "nvme.cmd.identify.ns.nguid",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_eui64,
            { "IEEE Extended Unique Identifier (EUI64)", "nvme.cmd.identify.ns.eui64",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_lbafs,
            { "LBA Formats", "nvme.cmd.identify.ns.lbafs",
               FT_NONE, BASE_NONE, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_lbaf,
            { "LBA Format", "nvme.cmd.identify.ns.lbaf",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ns_vs,
            { "Vendor Specific", "nvme.cmd.identify.ns.vs",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Identify - I/O Command Set Independent Namespace (CNS 08h), Fig 335 */
        { &hf_nvme_identify_cs_ind_ns_nsfeat[0],
            { "Common Namespace Features (NSFEAT)", "nvme.cmd.identify.cs_ind_ns.nsfeat",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nsfeat[1],
            { "Volatile Write Cache Not Present (VWCNP)", "nvme.cmd.identify.cs_ind_ns.nsfeat.vwcnp",
               FT_BOOLEAN, 8, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nsfeat[2],
            { "Rotational Media (RMEDIA)", "nvme.cmd.identify.cs_ind_ns.nsfeat.rmedia",
               FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nsfeat[3],
            { "UID Reuse (UIDREUSE)", "nvme.cmd.identify.cs_ind_ns.nsfeat.uidreuse",
               FT_BOOLEAN, 8, NULL, 0x08, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nsfeat[4],
            { "Reserved", "nvme.cmd.identify.cs_ind_ns.nsfeat.rsvd0",
               FT_UINT8, BASE_HEX, NULL, 0xc0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nsfeat[5],
            { "Reserved", "nvme.cmd.identify.cs_ind_ns.nsfeat.rsvd1",
               FT_UINT8, BASE_HEX, NULL, 0x07, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nmic[0],
            { "Namespace Multi-path I/O and Namespace Sharing Capabilities (NMIC)", "nvme.cmd.identify.cs_ind_ns.nmic",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nmic[1],
            { "Dispersed Namespace (DISNS)", "nvme.cmd.identify.cs_ind_ns.nmic.disns",
               FT_BOOLEAN, 8, NULL, 0x02, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nmic[2],
            { "Shared Namespace (SHRNS)", "nvme.cmd.identify.cs_ind_ns.nmic.shrns",
               FT_BOOLEAN, 8, NULL, 0x01, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nmic[3],
            { "Reserved", "nvme.cmd.identify.cs_ind_ns.nmic.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[0],
            { "Reservation Capabilities (RESCAP)", "nvme.cmd.identify.cs_ind_ns.rescap",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[1],
            { "Ignore Existing Key Support (IEKS)", "nvme.cmd.identify.cs_ind_ns.rescap.ieks",
               FT_BOOLEAN, 8, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[2],
            { "Exclusive Access - All Registrants Support (EAARS)", "nvme.cmd.identify.cs_ind_ns.rescap.eaars",
               FT_BOOLEAN, 8, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[3],
            { "Write Exclusive - All Registrants Support (WEARS)", "nvme.cmd.identify.cs_ind_ns.rescap.wears",
               FT_BOOLEAN, 8, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[4],
            { "Exclusive Access - Registrants Only Support (EAROS)", "nvme.cmd.identify.cs_ind_ns.rescap.earos",
               FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[5],
            { "Write Exclusive - Registrants Only Support (WEROS)", "nvme.cmd.identify.cs_ind_ns.rescap.weros",
               FT_BOOLEAN, 8, NULL, 0x08, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[6],
            { "Exclusive Access Support (EAS)", "nvme.cmd.identify.cs_ind_ns.rescap.eas",
               FT_BOOLEAN, 8, NULL, 0x04, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[7],
            { "Write Exclusive Support (WES)", "nvme.cmd.identify.cs_ind_ns.rescap.wes",
               FT_BOOLEAN, 8, NULL, 0x02, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rescap[8],
            { "Persist Through Power Loss Support (PTPLS)", "nvme.cmd.identify.cs_ind_ns.rescap.ptpls",
               FT_BOOLEAN, 8, NULL, 0x01, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_fpi[0],
            { "Format Progress Indicator (FPI)", "nvme.cmd.identify.cs_ind_ns.fpi",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_fpi[1],
            { "Format Progress Indicator Support (FPIS)", "nvme.cmd.identify.cs_ind_ns.fpi.fpis",
               FT_BOOLEAN, 8, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_fpi[2],
            { "Remaining Format NVM (RFNVM)", "nvme.cmd.identify.cs_ind_ns.fpi.rfnvm",
               FT_UINT8, BASE_DEC, NULL, 0x7f, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_anagrpid,
            { "ANA Group Identifier (ANAGRPID)", "nvme.cmd.identify.cs_ind_ns.anagrpid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nsattr[0],
            { "Namespace Attributes (NSATTR)", "nvme.cmd.identify.cs_ind_ns.nsattr",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nsattr[1],
            { "Currently Write Protected (CWP)", "nvme.cmd.identify.cs_ind_ns.nsattr.cwp",
               FT_BOOLEAN, 8, NULL, 0x01, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nsattr[2],
            { "Reserved", "nvme.cmd.identify.cs_ind_ns.nsattr.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rsvd0,
            { "Reserved", "nvme.cmd.identify.cs_ind_ns.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nvmsetid,
            { "NVM Set Identifier (NVMSETID)", "nvme.cmd.identify.cs_ind_ns.nvmsetid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_endgid,
            { "Endurance Group Identifier (ENDGID)", "nvme.cmd.identify.cs_ind_ns.endgid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nstat[0],
            { "Namespace Status (NSTAT)", "nvme.cmd.identify.cs_ind_ns.nstat",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nstat[1],
            { "I/O Impacted (IOI)", "nvme.cmd.identify.cs_ind_ns.nstat.ioi",
               FT_UINT8, BASE_HEX, VALS(cs_ind_ns_ioi_tbl), 0x06, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nstat[2],
            { "Namespace Ready (NRDY)", "nvme.cmd.identify.cs_ind_ns.nstat.nrdy",
               FT_BOOLEAN, 8, NULL, 0x01, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_nstat[3],
            { "Reserved", "nvme.cmd.identify.cs_ind_ns.nstat.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_kpios[0],
            { "Key Per I/O Status (KPIOS)", "nvme.cmd.identify.cs_ind_ns.kpios",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_kpios[1],
            { "Key Per I/O Supported in Namespace (KPIOSNS)", "nvme.cmd.identify.cs_ind_ns.kpios.kpiosns",
               FT_BOOLEAN, 8, NULL, 0x02, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_kpios[2],
            { "Key Per I/O Enabled in Namespace (KPIOENS)", "nvme.cmd.identify.cs_ind_ns.kpios.kpioens",
               FT_BOOLEAN, 8, NULL, 0x01, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_kpios[3],
            { "Reserved", "nvme.cmd.identify.cs_ind_ns.kpios.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_maxkt,
            { "Maximum Key Tag (MAXKT)", "nvme.cmd.identify.cs_ind_ns.maxkt",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rsvd1,
            { "Reserved", "nvme.cmd.identify.cs_ind_ns.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_cs_ind_ns_rgrpid,
            { "Reachability Group Identifier (RGRPID)", "nvme.cmd.identify.cs_ind_ns.rgrpid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Identify Ctrl response */
        { &hf_nvme_identify_ctrl_vid,
            { "PCI Vendor ID (VID)", "nvme.cmd.identify.ctrl.vid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ssvid,
            { "PCI Subsystem Vendor ID (SSVID)", "nvme.cmd.identify.ctrl.ssvid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sn,
            { "Serial Number (SN)", "nvme.cmd.identify.ctrl.sn",
               FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mn,
            { "Model Number (MN)", "nvme.cmd.identify.ctrl.mn",
               FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fr,
            { "Firmware Revision (FR)", "nvme.cmd.identify.ctrl.fr",
               FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rab,
            { "Recommended Arbitration Burst (RAB)", "nvme.cmd.identify.ctrl.rab",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_rab), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ieee,
            { "IEEE OUI Identifier (IEEE)", "nvme.cmd.identify.ctrl.ieee",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cmic[0],
            { "Controller Multi-Path I/O and Namespace Sharing Capabilities (CMIC)", "nvme.cmd.identify.ctrl.cmic",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cmic[1],
            { "Multiple Ports Support", "nvme.cmd.identify.ctrl.cmic.mp",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cmic[2],
            { "Multiple Controllers Support", "nvme.cmd.identify.ctrl.cmic.mc",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cmic[3],
            { "SRIOV Association", "nvme.cmd.identify.ctrl.cmic.sriov",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cmic[4],
            { "ANA Reporting Support", "nvme.cmd.identify.ctrl.cmic.ana",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cmic[5],
            { "Reserved", "nvme.cmd.identify.ctrl.cmic.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mdts,
            { "Maximum Data Transfer Size (MDTS)", "nvme.cmd.identify.ctrl.mdts",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_mdts), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cntlid,
            { "Controller ID (CNTLID)", "nvme.cmd.identify.ctrl.cntlid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ver,
            { "Version (VER)", "nvme.cmd.identify.ctrl.ver",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ver_ter,
            { "Tertiary Version Number (TER)", "nvme.cmd.identify.ctrl.ver.ter",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ver_min,
            { "Minor Version Number (MNR)", "nvme.cmd.identify.ctrl.ver.min",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ver_mjr,
            { "Major Version Number (MJR)", "nvme.cmd.identify.ctrl.ver.mjr",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rtd3r,
            { "RTD3 Resume Latency (RTD3R)", "nvme.cmd.identify.ctrl.rtd3r",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_rtd3), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rtd3e,
            { "RTD3 Entry Latency (RTD3E)", "nvme.cmd.identify.ctrl.rtd3e",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_rtd3), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[0],
            { "Optional Asynchronous Events Supported (OAES)", "nvme.cmd.identify.ctrl.oaes",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[1],
            { "Reserved", "nvme.cmd.identify.ctrl.oaes.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[2],
            { "Namespace Attribute Notices Supported", "nvme.cmd.identify.ctrl.oaes.nan",
               FT_BOOLEAN, 32, NULL, 0x100, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[3],
            { "Firmware Activation Supported", "nvme.cmd.identify.ctrl.oaes.fan",
               FT_BOOLEAN, 32, NULL, 0x200, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[4],
            { "Reserved", "nvme.cmd.identify.ctrl.oaes.rsvd1",
               FT_UINT32, BASE_HEX, NULL, 0x400, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[5],
            { "Asymmetric Namespace Access Change Notices Supported", "nvme.cmd.identify.ctrl.oaes.ana",
               FT_BOOLEAN, 32, NULL, 0x800, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[6],
            { "Predictable Latency Event Aggregate Log Change Notices Supported", "nvme.cmd.identify.ctrl.oaes.ple",
               FT_BOOLEAN, 32, NULL, 0x1000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[7],
            { "LBA Status Information Notices Supported", "nvme.cmd.identify.ctrl.oaes.lba",
               FT_BOOLEAN, 32, NULL, 0x2000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[8],
            { "Endurance Group Event Aggregate Log Page Change Notices Supported", "nvme.cmd.identify.ctrl.oaes.ege",
               FT_BOOLEAN, 32, NULL, 0x4000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaes[9],
            { "Reserved", "nvme.cmd.identify.ctrl.oaes.rsvd2",
               FT_UINT32, BASE_HEX, NULL, 0xffff8000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[0],
            { "Controller Attributes (CTRATT)", "nvme.cmd.identify.ctrl.ctratt",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[1],
            { "128-bit Host Identifier Support", "nvme.cmd.identify.ctrl.ctratt.hi_128",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[2],
            { "Non-Operational Power State Permissive Mode Supported", "nvme.cmd.identify.ctrl.ctratt.nopspm",
               FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[3],
            { "NVM Sets Supported", "nvme.cmd.identify.ctrl.ctratt.nvmset",
               FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[4],
            { "Read Recovery Levels Supported", "nvme.cmd.identify.ctrl.ctratt.rrl",
               FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[5],
            { "Endurance Groups Supported", "nvme.cmd.identify.ctrl.ctratt.eg",
               FT_BOOLEAN, 32, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[6],
            { "Predictable Latency Mode Supported", "nvme.cmd.identify.ctrl.ctratt.plm",
               FT_BOOLEAN, 32, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[7],
            { "Traffic Based Keep Alive Support (TBKAS)", "nvme.cmd.identify.ctrl.ctratt.tbkas",
               FT_BOOLEAN, 32, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[8],
            { "Namespace Granularity", "nvme.cmd.identify.ctrl.ctratt.ng",
               FT_BOOLEAN, 32, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[9],
            { "SQ Associations Support", "nvme.cmd.identify.ctrl.ctratt.sqa",
               FT_BOOLEAN, 32, NULL, 0x100, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[10],
            { "UUID List Support", "nvme.cmd.identify.ctrl.ctratt.uuidl",
               FT_BOOLEAN, 32, NULL, 0x200, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ctratt[11],
            { "Reserved", "nvme.cmd.identify.ctrl.ctratt.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffc00, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[0],
            { "Read Recovery Levels Support (RRLS)", "nvme.cmd.identify.ctrl.rrls",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[1],
            { "Read Recovery Level 0 Support", "nvme.cmd.identify.ctrl.rrls.rrls0",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[2],
            { "Read Recovery Level 1 Support", "nvme.cmd.identify.ctrl.rrls.rrls1",
               FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[3],
            { "Read Recovery Level 2 Support", "nvme.cmd.identify.ctrl.rrls.rrls2",
               FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[4],
            { "Read Recovery Level 3 Support", "nvme.cmd.identify.ctrl.rrls.rrls3",
               FT_BOOLEAN, 16, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[5],
            { "Read Recovery Level 4 (Default) Support", "nvme.cmd.identify.ctrl.rrls.rrls4",
               FT_BOOLEAN, 16, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[6],
            { "Read Recovery Level 5 Support", "nvme.cmd.identify.ctrl.rrls.rrls5",
               FT_BOOLEAN, 16, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[7],
            { "Read Recovery Level 6 Support", "nvme.cmd.identify.ctrl.rrls.rrls6",
               FT_BOOLEAN, 16, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[8],
            { "Read Recovery Level 7 Support", "nvme.cmd.identify.ctrl.rrls.rrls7",
               FT_BOOLEAN, 16, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[9],
            { "Read Recovery Level 8 Support", "nvme.cmd.identify.ctrl.rrls.rrls8",
               FT_BOOLEAN, 16, NULL, 0x100, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[10],
            { "Read Recovery Level 9 Support", "nvme.cmd.identify.ctrl.rrls.rrls9",
               FT_BOOLEAN, 16, NULL, 0x200, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[11],
            { "Read Recovery Level 10 Support", "nvme.cmd.identify.ctrl.rrls.rrls10",
               FT_BOOLEAN, 16, NULL, 0x400, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[12],
            { "Read Recovery Level 11 Support", "nvme.cmd.identify.ctrl.rrls.rrls11",
               FT_BOOLEAN, 16, NULL, 0x800, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[13],
            { "Read Recovery Level 12 Support", "nvme.cmd.identify.ctrl.rrls.rrls12",
               FT_BOOLEAN, 16, NULL, 0x1000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[14],
            { "Read Recovery Level 13 Support", "nvme.cmd.identify.ctrl.rrls.rrls13",
               FT_BOOLEAN, 16, NULL, 0x2000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[15],
            { "Read Recovery Level 14 Support", "nvme.cmd.identify.ctrl.rrls.rrls14",
               FT_BOOLEAN, 16, NULL, 0x4000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rrls[16],
            { "Read Recovery Level 15 (Fast Fail) Support", "nvme.cmd.identify.ctrl.rrls.rrls15",
               FT_BOOLEAN, 16, NULL, 0x8000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_bpcap[0],
            { "Boot Partition Capabilities (BPCAP)", "nvme.cmd.identify.ctrl.bpcap",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_bpcap[1],
            { "RPMB Boot Partition Write Protection Support (RPMBBPWPS)", "nvme.cmd.identify.ctrl.bpcap.rpmbbpwps",
               FT_UINT8, BASE_HEX, VALS(ctrl_rpmbbpwps_tbl), 0x3, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_bpcap[2],
            { "Set Features Boot Partition Write Protection Support (SFBPWPS)", "nvme.cmd.identify.ctrl.bpcap.sfbpwps",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_bpcap[3],
            { "Reserved", "nvme.cmd.identify.ctrl.bpcap.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd0,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nssl,
            { "NVM Subsystem Shutdown Latency (NSSL)", "nvme.cmd.identify.ctrl.nssl",
               FT_UINT32, BASE_DEC|BASE_UNIT_STRING, UNS(&units_microseconds), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd6,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd6",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_plsi[0],
            { "Power Loss Signaling Information (PLSI)", "nvme.cmd.identify.ctrl.plsi",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_plsi[1],
            { "PLS Emergency Power Fail (PLSEPF)", "nvme.cmd.identify.ctrl.plsi.plsepf",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_plsi[2],
            { "PLS Forced Quiescence (PLSFQ)", "nvme.cmd.identify.ctrl.plsi.plsfq",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_plsi[3],
            { "Reserved", "nvme.cmd.identify.ctrl.plsi.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cntrltype,
            { "Controller Type (CNTRLTYPE)", "nvme.cmd.identify.ctrl.cntrltype",
               FT_UINT8, BASE_HEX, VALS(ctrl_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fguid,
            { "FRU Globally Unique Identifier (FGUID)", "nvme.cmd.identify.ctrl.fguid",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fguid_vse,
            { "Vendor Specific Extension Identifier", "nvme.cmd.identify.ctrl.fguid.vse",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fguid_oui,
            { "Organizationally Unique Identifier", "nvme.cmd.identify.ctrl.fguid.oui",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fguid_ei,
            { "Extension Identifier", "nvme.cmd.identify.ctrl.fguid.ei",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_crdt1,
            { "Command Retry Delay Time 1", "nvme.cmd.identify.ctrl.crdt1",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_crdt2,
            { "Command Retry Delay Time 2", "nvme.cmd.identify.ctrl.crdt2",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_crdt3,
            { "Command Retry Delay Time 3", "nvme.cmd.identify.ctrl.crdt3",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_crcap[0],
            { "Controller Reachability Capabilities (CRCAP)", "nvme.cmd.identify.ctrl.crcap",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_crcap[1],
            { "Reachability Reporting Supported (RRSUP)", "nvme.cmd.identify.ctrl.crcap.rrsup",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_crcap[2],
            { "Reachability Group ID Changeable (RGIDC)", "nvme.cmd.identify.ctrl.crcap.rgidc",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_crcap[3],
            { "Reserved", "nvme.cmd.identify.ctrl.crcap.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ciu,
            { "Controller Instance Uniquifier (CIU)", "nvme.cmd.identify.ctrl.ciu",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cirn,
            { "Controller Instance Random Number (CIRN)", "nvme.cmd.identify.ctrl.cirn",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd1,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi,
            { "NVMe Management Interface", "nvme.cmd.identify.ctrl.mi",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_rsvd,
            { "Reserved", "nvme.cmd.identify.ctrl.mi.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_nvmsr[0],
            { "NVM Subsystem Report (NVMSR)", "nvme.cmd.identify.ctrl.mi.nvmsr",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_nvmsr[1],
            { "NVMe Storage Device (NVMESD)", "nvme.cmd.identify.ctrl.mi.nvmsr.nvmesd",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_nvmsr[2],
            { "NVMe Enclosure (NVMEE)", "nvme.cmd.identify.ctrl.mi.nvmsr.nvmee",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_nvmsr[3],
            { "Reserved", "nvme.cmd.identify.ctrl.mi.nvmsr.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_vwci[0],
            { "VPD Write Cycle Information (VWCI)", "nvme.cmd.identify.ctrl.mi.vwci",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_vwci[1],
            { "VPD Write Cycles Remaining (VWCR)", "nvme.cmd.identify.ctrl.mi.vwci.vwcr",
               FT_UINT8, BASE_HEX, NULL, 0x7f, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_vwci[2],
            { "VPD Write Cycle Remaining Valid (VWCRV)", "nvme.cmd.identify.ctrl.mi.vwci.vwcrv",
               FT_BOOLEAN, 8, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_mec[0],
            { "Management Endpoint Capabilities (MEC)", "nvme.cmd.identify.ctrl.mi.mec",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_mec[1],
            { "SMBus/I2C Port Management Endpoint (SMBUSME)", "nvme.cmd.identify.ctrl.mi.mec.smbusme",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_mec[2],
            { "PCIe Port Management Endpoint (PCIEME)", "nvme.cmd.identify.ctrl.mi.mec.pcieme",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mi_mec[3],
            { "Reserved", "nvme.cmd.identify.ctrl.mi.mec.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[0],
            { "Optional Admin Command Support (OACS)", "nvme.cmd.identify.ctrl.oacs",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[1],
            { "Security Send and Security Receive Support", "nvme.cmd.identify.ctrl.oacs.sec",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[2],
            { "Format NVM Support", "nvme.cmd.identify.ctrl.oacs.fmt",
               FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[3],
            { "Firmware Download and Commit Support", "nvme.cmd.identify.ctrl.oacs.fw",
               FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[4],
            { "Namespace Management Support", "nvme.cmd.identify.ctrl.oacs.nsmgmt",
               FT_BOOLEAN, 16, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[5],
            { "Device Self-Test Support", "nvme.cmd.identify.ctrl.oacs.stst",
               FT_BOOLEAN, 16, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[6],
            { "Directive Send and Directive Receive Support", "nvme.cmd.identify.ctrl.oacs.dtv",
               FT_BOOLEAN, 16, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[7],
            { "NVMe-MI Send and NVMe-MI Receive Support", "nvme.cmd.identify.ctrl.oacs.mi",
               FT_BOOLEAN, 16, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[8],
            { "Virtualization Management Support", "nvme.cmd.identify.ctrl.oacs.vm",
               FT_BOOLEAN, 16, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[9],
            { "Doorbell Buffer Config Support", "nvme.cmd.identify.ctrl.oacs.db",
               FT_BOOLEAN, 16, NULL, 0x100, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[10],
            { "Get LBA Status Support", "nvme.cmd.identify.ctrl.oacs.sec.lba",
               FT_BOOLEAN, 16, NULL, 0x200, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oacs[11],
            { "Reserved", "nvme.cmd.identify.ctrl.oacs.sec.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0xfc00, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_acl,
            { "Abort Command Limit (ACL)", "nvme.cmd.identify.ctrl.acl",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_commands), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_aerl,
            { "Asynchronous Event Request Limit (AERL)", "nvme.cmd.identify.ctrl.aerl",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_events), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_frmw[0],
            { "Firmware Updates (FRMW)", "nvme.cmd.identify.ctrl.frmw",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_frmw[1],
            { "First Firmware Slot Read-Only", "nvme.cmd.identify.ctrl.frmw.fro",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_frmw[2],
            { "Number of Firmware Slots", "nvme.cmd.identify.ctrl.frmw.fsn",
               FT_UINT8, BASE_HEX, NULL, 0xe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_frmw[3],
            { "Supports Activation Without Reset", "nvme.cmd.identify.ctrl.frmw.anr",
               FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_frmw[4],
            { "Reserved", "nvme.cmd.identify.ctrl.frmw.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_lpa[0],
            { "Log Page Attributes (LPA)", "nvme.cmd.identify.ctrl.lpa",
               FT_BOOLEAN, 8, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_lpa[1],
            { "Smart Log Page per Namespace Support", "nvme.cmd.identify.ctrl.lpa.smrt",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_lpa[2],
            { "Commands Supported and Effects Log Page Support", "nvme.cmd.identify.ctrl.lpa.cmds",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_lpa[3],
            { "Extended Data Get Log Page Support", "nvme.cmd.identify.ctrl.lpa.elp",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_lpa[4],
            { "Telemetry Log Page and Notices Support", "nvme.cmd.identify.ctrl.lpa.tel",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_lpa[5],
            { "Persistent Event Log Support", "nvme.cmd.identify.ctrl.lpa.ple",
               FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_lpa[6],
            { "Reserved", "nvme.cmd.identify.ctrl.lpa.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_elpe,
            { "Error Log Page Entries (ELPE)", "nvme.cmd.identify.ctrl.elpe",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_entries), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_npss,
            { "Number of Power States Supported (NPSS)", "nvme.cmd.identify.ctrl.npss",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_states), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_avscc[0],
            { "Admin Vendor Specific Command Configuration (AVSCC)", "nvme.cmd.identify.ctrl.avscc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_avscc[1],
            { "Standard Command Format", "nvme.cmd.identify.ctrl.avscc.std",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_avscc[2],
            { "Reserved", "nvme.cmd.identify.ctrl.avscc.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_apsta[0],
            { "Autonomous Power State Transition Attributes (APSTA)", "nvme.cmd.identify.ctrl.apsta",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_apsta[1],
            { "Autonomous Power State Transitions Supported", "nvme.cmd.identify.ctrl.apsta.aut",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_apsta[2],
            { "Reserved", "nvme.cmd.identify.ctrl.apsta.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_wctemp,
            { "Warning Composite Temperature Threshold (WCTEMP)", "nvme.cmd.identify.ctrl.wctemp",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cctemp,
            { "Critical Composite Temperature Threshold (CCTEMP)", "nvme.cmd.identify.ctrl.cctemp",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mtfa,
            { "Maximum Time for Firmware Activation (MTFA)", "nvme.cmd.identify.ctrl.mtfa",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_hmpre,
            { "Host Memory Buffer Preferred Size (HMPRE)", "nvme.cmd.identify.ctrl.hmpre",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_hmpre), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_hmmin,
            { "Host Memory Buffer Minimum Size (HMMIN)", "nvme.cmd.identify.ctrl.hmmin",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_hmpre), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_tnvmcap,
            { "Total NVM Capacity (TNVMCAP)", "nvme.cmd.identify.ctrl.tnvmcap",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_unvmcap,
            { "Unallocated NVM Capacity (UNVMCAP)", "nvme.cmd.identify.ctrl.unvmcap",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rpmbs[0],
            { "Replay Protected Memory Block Support (RPMBS)", "nvme.cmd.identify.ctrl.rpmbs",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rpmbs[1],
            { "Number of RPMB Units", "nvme.cmd.identify.ctrl.rpmbs.nu",
               FT_UINT32, BASE_HEX, NULL, 0x7, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rpmbs[2],
            { "Authentication Method", "nvme.cmd.identify.ctrl.rpmbs.au",
               FT_UINT32, BASE_HEX, NULL, 0x38, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rpmbs[3],
            { "Reserved", "nvme.cmd.identify.ctrl.rpmbs.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffc0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rpmbs[4],
            { "Total RPMB Unit Size (128 KiB blocks, zero based)", "nvme.cmd.identify.ctrl.rpmbs.ts",
               FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rpmbs[5],
            { "Access Size (512-byte blocks, zero based)", "nvme.cmd.identify.ctrl.rpmbs.as",
               FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
        },
            { &hf_nvme_identify_ctrl_edstt,
            { "Extended Device Self-test Time (EDSTT) (in minutes)", "nvme.cmd.identify.ctrl.edstt",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_dsto[0],
            { "Device Self-test Options (DSTO)", "nvme.cmd.identify.ctrl.dsto",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_dsto[1],
            { "Single Device Self-test Operation (SDSO)", "nvme.cmd.identify.ctrl.dsto.mds",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_dsto[2],
            { "Reserved", "nvme.cmd.identify.ctrl.dsto.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fwug,
            { "Firmware Update Granularity in 4 KiB Units (FWUG)", "nvme.cmd.identify.ctrl.fwug",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_kas,
            { "Keep Alive Support - Timer Value (KAS)", "nvme.cmd.identify.ctrl.kas",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_hctma[0],
            { "Host Controlled Thermal Management Attributes (HCTMA)", "nvme.cmd.identify.ctrl.hctma",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_hctma[1],
            { "Controller Supports Thermal Management", "nvme.cmd.identify.ctrl.hctma.sup",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_hctma[2],
            { "Reserved", "nvme.cmd.identify.ctrl.hctma.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0xfffe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mntmt,
            { "Minimum Thermal Management Temperature (MNTMT)", "nvme.cmd.identify.ctrl.mntmt",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_tmt), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mxtmt,
            { "Maximum Thermal Management Temperature (MXTMT)", "nvme.cmd.identify.ctrl.mxtmt",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_tmt), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sanicap[0],
            { "Sanitize Capabilities (SANICAP)", "nvme.cmd.identify.ctrl.sanicap",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sanicap[1],
            { "Crypto Erase Support (CES)", "nvme.cmd.identify.ctrl.sanicap.ces",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sanicap[2],
            { "Block Erase Support (BES)", "nvme.cmd.identify.ctrl.sanicap.bes",
               FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sanicap[3],
            { "Overwrite Support (OWS)", "nvme.cmd.identify.ctrl.sanicap.ows",
               FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sanicap[4],
            { "Reserved", "nvme.cmd.identify.ctrl.sanicap.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x1ffffff8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sanicap[5],
            { "No-Deallocate Inhibited (NDI)", "nvme.cmd.identify.ctrl.sanicap.ndi",
               FT_BOOLEAN, 32, NULL, 0x20000000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sanicap[6],
            { "No-Deallocate Modifies Media After Sanitize (NODMMAS)", "nvme.cmd.identify.ctrl.sanicap.nodmmas",
               FT_UINT32, BASE_HEX, VALS(mmas_type_tbl), 0xc0000000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_hmmminds,
            { "Host Memory Buffer Minimum Descriptor Entry Size in 4 KiB Units (HMMINDS)", "nvme.cmd.identify.ctrl.hmmminds",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_hmmaxd,
            { "Host Memory Maximum Descriptors Entries (HMMAXD)", "nvme.cmd.identify.ctrl.hmmaxd",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nsetidmax,
            { "NVM Set Identifier Maximum (NSETIDMAX)", "nvme.cmd.identify.ctrl.nsetidmax",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_endgidmax,
            { "Endurance Group Identifier Maximum (ENDGIDMAX)", "nvme.cmd.identify.ctrl.endgidmax",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anatt,
            { "ANA Transition Time in Seconds (ANATT)", "nvme.cmd.identify.ctrl.anatt",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[0],
            { "Asymmetric Namespace Access Capabilities (ANACAP)", "nvme.cmd.identify.ctrl.anacap",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[1],
            { "Reports ANA Optimized State", "nvme.cmd.identify.ctrl.anacap.osr",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[2],
            { "Reports ANA Non-Optimized State", "nvme.cmd.identify.ctrl.anacap.nosr",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[3],
            { "Reports Inaccessible State", "nvme.cmd.identify.ctrl.anacap.isr",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[4],
            { "Reports ANA Persistent Loss State", "nvme.cmd.identify.ctrl.anacap.plsr",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[5],
            { "Reports ANA Change State", "nvme.cmd.identify.ctrl.anacap.csr",
               FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[6],
            { "Reserved", "nvme.cmd.identify.ctrl.anacap.rsvd",
               FT_BOOLEAN, 8, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[7],
            { "ANAGRPID field in the Identify Namespace does not change", "nvme.cmd.identify.ctrl.anacap.panagrpid",
               FT_BOOLEAN, 8, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anacap[8],
            { "Supports non-zero value in the ANAGRPID field", "nvme.cmd.identify.ctrl.anacap.nzpanagrpid",
               FT_BOOLEAN, 8, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_anagrpmax,
            { "ANA Group Identifier Maximum (ANAGRPMAX)", "nvme.cmd.identify.ctrl.anagrpmax",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nanagrpid,
            { "Number of ANA Group Identifiers (NANAGRPID)", "nvme.cmd.identify.ctrl.nanagrpid",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_pels,
            { "Persistent Event Log Size in 64 KiB Units (PELS)", "nvme.cmd.identify.ctrl.pels",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_did,
            { "Domain Identifier (DID)", "nvme.cmd.identify.ctrl.did",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_kpioc[0],
            { "Key Per I/O Capabilities (KPIOC)", "nvme.cmd.identify.ctrl.kpioc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_kpioc[1],
            { "Key Per I/O Supported (KPIOS)", "nvme.cmd.identify.ctrl.kpioc.kpios",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_kpioc[2],
            { "Key Per I/O Scope (KPIOSC)", "nvme.cmd.identify.ctrl.kpioc.kpiosc",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_kpioc[3],
            { "Reserved", "nvme.cmd.identify.ctrl.kpioc.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd2,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd2",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mptfawr,
            { "Maximum Processing Time for Firmware Activation Without Reset (MPTFAWR)", "nvme.cmd.identify.ctrl.mptfawr",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd7,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd7",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_megcap,
            { "Max Endurance Group Capacity (MEGCAP)", "nvme.cmd.identify.ctrl.megcap",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_tmpthha[0],
            { "Temperature Threshold Hysteresis Attributes (TMPTHHA)", "nvme.cmd.identify.ctrl.tmpthha",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_tmpthha[1],
            { "Temperature Threshold Maximum Hysteresis (TMPTHMH)", "nvme.cmd.identify.ctrl.tmpthha.tmpthmh",
               FT_UINT8, BASE_DEC, NULL, 0x7, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_tmpthha[2],
            { "Reserved", "nvme.cmd.identify.ctrl.tmpthha.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mupa[0],
            { "Maximum Unlimited Power Attributes (MUPA)", "nvme.cmd.identify.ctrl.mupa",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mupa[1],
            { "Maximum Unlimited Power Scale (MUPS)", "nvme.cmd.identify.ctrl.mupa.mups",
               FT_UINT8, BASE_HEX, VALS(ctrl_mups_tbl), 0x3, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mupa[2],
            { "Reserved", "nvme.cmd.identify.ctrl.mupa.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cqt,
            { "Command Quiesce Time (CQT)", "nvme.cmd.identify.ctrl.cqt",
               FT_UINT16, BASE_DEC|BASE_UNIT_STRING, UNS(&units_milliseconds), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cdpa[0],
            { "Configurable Device Personality Attributes (CDPA)", "nvme.cmd.identify.ctrl.cdpa",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cdpa[1],
            { "HMAC-SHA-384 (HS3)", "nvme.cmd.identify.ctrl.cdpa.hs3",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cdpa[2],
            { "Reserved", "nvme.cmd.identify.ctrl.cdpa.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0xfffe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mup,
            { "Maximum Unlimited Power (MUP)", "nvme.cmd.identify.ctrl.mup",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ipmsr[0],
            { "Interval Power Measurement Sample Rate (IPMSR)", "nvme.cmd.identify.ctrl.ipmsr",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ipmsr[1],
            { "Sample Rate Value (SRV)", "nvme.cmd.identify.ctrl.ipmsr.srv",
               FT_UINT16, BASE_DEC, NULL, 0x00ff, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_ipmsr[2],
            { "Sample Rate Scale (SRS)", "nvme.cmd.identify.ctrl.ipmsr.srs",
               FT_UINT16, BASE_HEX, VALS(ctrl_srs_tbl), 0xff00, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_msmt,
            { "Maximum Stop Measurement Time (MSMT)", "nvme.cmd.identify.ctrl.msmt",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd8,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd8",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sqes[0],
            { "Submission Queue Entry Size (SQES)", "nvme.cmd.identify.ctrl.sqes",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sqes[1],
            { "Minimum (required) Size", "nvme.cmd.identify.ctrl.sqes.mins",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xf, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sqes[2],
            { "Maximum (allowed) Size", "nvme.cmd.identify.ctrl.sqes.maxs",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xf0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cqes[0],
            { "Completion Queue Entry Size (CQES)", "nvme.cmd.identify.ctrl.cqes",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cqes[1],
            { "Minimum (required) Size", "nvme.cmd.identify.ctrl.cqes.mins",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xf, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cqes[2],
            { "Maximum (allowed) Size", "nvme.cmd.identify.ctrl.cqes.maxs",
               FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xf0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_maxcmd,
            { "Maximum Outstanding Commands (MAXCMD)", "nvme.cmd.identify.ctrl.maxcmd",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nn,
            { "Number of Namespaces (NN)", "nvme.cmd.identify.ctrl.nn",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[0],
            { "Optional NVM Command Support (ONCS)", "nvme.cmd.identify.ctrl.oncs",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[1],
            { "Supports Compare Command", "nvme.cmd.identify.ctrl.oncs.ccs",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[2],
            { "Supports Write Uncorrectable Command", "nvme.cmd.identify.ctrl.oncs.wus",
               FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[3],
            { "Supports Dataset Management Command", "nvme.cmd.identify.ctrl.oncs.dsms",
               FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[4],
            { "Support Write Zeroes Command", "nvme.cmd.identify.ctrl.oncs.wzs",
               FT_BOOLEAN, 16, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[5],
            { "Supports non-zero Save Field in Set/Get Features", "nvme.cmd.identify.ctrl.oncs.nzfs",
               FT_BOOLEAN, 16, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[6],
            { "Supports Reservations", "nvme.cmd.identify.ctrl.oncs.ress",
               FT_BOOLEAN, 16, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[7],
            { "Supports Timestamps", "nvme.cmd.identify.ctrl.oncs.tstmps",
               FT_BOOLEAN, 16, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[8],
            { "Supports Verify Command", "nvme.cmd.identify.ctrl.oncs.vers",
               FT_BOOLEAN, 16, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oncs[9],
            { "Reserved", "nvme.cmd.identify.ctrl.oncs.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0xff00, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fuses[0],
            { "Fused Operation Support (FUSES)", "nvme.cmd.identify.ctrl.fuses",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fuses[1],
            { "Compare and Write Fused Operation Support", "nvme.cmd.identify.ctrl.fuses.cws",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fuses[2],
            { "Reserved", "nvme.cmd.identify.ctrl.fuses.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0xfffe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fna[0],
            { "Format NVM Attributes (FNA)", "nvme.cmd.identify.ctrl.fna",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fna[1],
            { "Format Operation Applies to all Namespaces", "nvme.cmd.identify.ctrl.fna.fall",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fna[2],
            { "Secure Erase Operation Applies to all Namespaces", "nvme.cmd.identify.ctrl.fna.seall",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fna[3],
            { "Cryptographic Erase Supported", "nvme.cmd.identify.ctrl.fna.ces",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_fna[4],
            { "Reserved", "nvme.cmd.identify.ctrl.fna.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_vwc[0],
            { "Volatile Write Cache (VWC)", "nvme.cmd.identify.ctrl.vwc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_vwc[1],
            { "Volatile Write Cache Present", "nvme.cmd.identify.ctrl.vwc.cp",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_vwc[2],
            { "Flush Command Behavior", "nvme.cmd.identify.ctrl.vwc.cfb",
               FT_UINT8, BASE_HEX, VALS(fcb_type_tbl), 0x6, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_vwc[3],
            { "Reserved", "nvme.cmd.identify.ctrl.vwc.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_awun,
            { "Atomic Write Unit Normal (AWUN)", "nvme.cmd.identify.ctrl.awun",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_lblocks), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_awupf,
            { "Atomic Write Unit Power Fail (AWUPF)", "nvme.cmd.identify.ctrl.awupf",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_lblocks), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvscc[0],
            { "NVM Vendor Specific Command Configuration (NVSCC)", "nvme.cmd.identify.ctrl.nvscc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvscc[1],
            { "Standard Format Used for Vendor Specific Commands", "nvme.cmd.identify.ctrl.nvscc.std",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvscc[2],
            { "Reserved", "nvme.cmd.identify.ctrl.nvscc.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nwpc[0],
            { "Namespace Write Protection Capabilities (NWPC)", "nvme.cmd.identify.ctrl.nwpc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nwpc[1],
            { "No Write Protect and Write Protect namespace write protection states Support", "nvme.cmd.identify.ctrl.nwpc.wpss",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nwpc[2],
            { "Write Protect Until Power Cycle state Support", "nvme.cmd.identify.ctrl.nwpc.wppcs",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nwpc[3],
            { "Permanent Write Protect state Support", "nvme.cmd.identify.ctrl.nwpc.pwpss",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nwpc[4],
            { "Reserved", "nvme.cmd.identify.ctrl.nwpc.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_acwu,
            { "Atomic Compare & Write Unit (ACWU)", "nvme.cmd.identify.ctrl.acwu",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_hmpre), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd3,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd3",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[0],
            { "SGL Support (SGLS)", "nvme.cmd.identify.ctrl.sgls",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[1],
            { "SGL Supported", "nvme.cmd.identify.ctrl.sgls.sgls",
               FT_UINT32, BASE_HEX, VALS(sgls_ify_type_tbl), 0x3, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[2],
            { "Supports Keyed SGL Data Block Descriptor", "nvme.cmd.identify.ctrl.sgls.kdbs",
               FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[3],
            { "Reserved", "nvme.cmd.identify.ctrl.sgls.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0xfff8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[4],
            { "Supports SGL Bit Bucket Descriptor", "nvme.cmd.identify.ctrl.sgls.bbd",
               FT_BOOLEAN, 32, NULL, 0x10000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[5],
            { "Supports byte aligned contiguous buffer in MPTR Field", "nvme.cmd.identify.ctrl.sgls.bufmptr",
               FT_BOOLEAN, 32, NULL, 0x20000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[6],
            { "Supports Larger SGL List than Command Requires", "nvme.cmd.identify.ctrl.sgls.lsgl",
               FT_BOOLEAN, 32, NULL, 0x40000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[7],
            { "Supports SGL Segment in MPTR Field", "nvme.cmd.identify.ctrl.sgls.kmptr",
               FT_BOOLEAN, 32, NULL, 0x80000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[8],
            { "Supports Address Field as offset in Data Block, Segment and Last Segment SGLs", "nvme.cmd.identify.ctrl.sgls.offs",
               FT_BOOLEAN, 32, NULL, 0x100000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[9],
            { "Supports Transport SGL Data Block Descriptor", "nvme.cmd.identify.ctrl.sgls.tdbd",
               FT_BOOLEAN, 32, NULL, 0x200000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_sgls[10],
            { "Reserved", "nvme.cmd.identify.ctrl.sgls.rsvd1",
               FT_UINT32, BASE_HEX, NULL, 0xffc00000, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mnan,
            { "Maximum Number of Allowed Namespaces (MNAN)", "nvme.cmd.identify.ctrl.mnan",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_maxdna,
            { "Maximum Domain Namespace Attachments (MAXDNA)", "nvme.cmd.identify.ctrl.maxdna",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_maxcna,
            { "Maximum I/O Controller Namespace Attachments (MAXCNA)", "nvme.cmd.identify.ctrl.maxcna",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_oaqd,
            { "Optimal Aggregated Queue Depth (OAQD)", "nvme.cmd.identify.ctrl.oaqd",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rhiri,
            { "Recommended Host-Initiated Refresh Interval (RHIRI)", "nvme.cmd.identify.ctrl.rhiri",
               FT_UINT8, BASE_DEC|BASE_UNIT_STRING, UNS(&units_day_days), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_hirt,
            { "Host-Initiated Refresh Time (HIRT)", "nvme.cmd.identify.ctrl.hirt",
               FT_UINT8, BASE_DEC|BASE_UNIT_STRING, UNS(&units_minutes), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_cmmrtd,
            { "Controller Maximum Memory Range Tracking Descriptors (CMMRTD)", "nvme.cmd.identify.ctrl.cmmrtd",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nmmrtd,
            { "NVM Subsystem Maximum Memory Range Tracking Descriptors (NMMRTD)", "nvme.cmd.identify.ctrl.nmmrtd",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_minmrtg,
            { "Minimum Memory Range Tracking Granularity (MINMRTG)", "nvme.cmd.identify.ctrl.minmrtg",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_maxmrtg,
            { "Maximum Memory Range Tracking Granularity (MAXMRTG)", "nvme.cmd.identify.ctrl.maxmrtg",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_trattr[0],
            { "Tracking Attributes (TRATTR)", "nvme.cmd.identify.ctrl.trattr",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_trattr[1],
            { "Track Host Memory Changes Support (THMCS)", "nvme.cmd.identify.ctrl.trattr.thmcs",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_trattr[2],
            { "Track User Data Changes Support (TUDCS)", "nvme.cmd.identify.ctrl.trattr.tudcs",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_trattr[3],
            { "Memory Range Tracking Length Limit (MRTLL)", "nvme.cmd.identify.ctrl.trattr.mrtll",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_trattr[4],
            { "Reserved", "nvme.cmd.identify.ctrl.trattr.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd4,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd4",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mcudmq,
            { "Maximum Controller User Data Migration Queues (MCUDMQ)", "nvme.cmd.identify.ctrl.mcudmq",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mnsudmq,
            { "Maximum NVM Subsystem User Data Migration Queues (MNSUDMQ)", "nvme.cmd.identify.ctrl.mnsudmq",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mcmr,
            { "Maximum CDQ Memory Ranges (MCMR)", "nvme.cmd.identify.ctrl.mcmr",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nmcmr,
            { "NVM Subsystem Maximum CDQ Memory Ranges (NMCMR)", "nvme.cmd.identify.ctrl.nmcmr",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_mcdqpc,
            { "Maximum Controller Data Queue PRP Count (MCDQPC)", "nvme.cmd.identify.ctrl.mcdqpc",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd9,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd9",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_subnqn,
            { "NVM Subsystem NVMe Qualified Name (SUBNQN)", "nvme.cmd.identify.ctrl.subnqn",
               FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_rsvd5,
            { "Reserved", "nvme.cmd.identify.ctrl.rsvd5",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof,
            { "NVMeOF Attributes", "nvme.cmd.identify.ctrl.nvmeof",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_ioccsz,
            { "I/O Queue Command Capsule Supported Size (IOCCSZ)", "nvme.cmd.identify.ctrl.nvmeof.ioccsz",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_x16_bytes), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_iorcsz,
            { "I/O Queue Response Capsule Supported Size (IORCSZ)", "nvme.cmd.identify.ctrl.nvmeof.iorcsz",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_x16_bytes), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_icdoff,
            { "In Capsule Data Offset (ICDOFF)", "nvme.cmd.identify.ctrl.nvmeof.icdoff",
               FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_x16_bytes), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_fcatt[0],
            { "Fabrics Controller Attributes (FCATT)", "nvme.cmd.identify.ctrl.nvmeof.fcatt",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_fcatt[1],
            { "Dynamic Controller Model", "nvme.cmd.identify.ctrl.nvmeof.fcatt.dcm",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_fcatt[2],
            { "Reserved", "nvme.cmd.identify.ctrl.nvmeof.fcatt.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_msdbd,
            { "Maximum SGL Data Block Descriptors (MSDBD)", "nvme.cmd.identify.ctrl.nvmeof.msdbd",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_ofcs[0],
            { "Optional Fabric Commands Support (OFCS)", "nvme.cmd.identify.ctrl.nvmeof.ofcs",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_ofcs[1],
            { "Supports Disconnect Command", "nvme.cmd.identify.ctrl.nvmeof.ofcs.dcs",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_ofcs[2],
            { "Reserved", "nvme.cmd.identify.ctrl.nvmeof.ofcs.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0xfffe, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_dctype,
            { "Discovery Controller Type (DCTYPE)", "nvme.cmd.identify.ctrl.nvmeof.dctype",
               FT_UINT8, BASE_HEX, VALS(ctrl_dctype_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_ccrl,
            { "Cross-Controller Reset Limit (CCRL)", "nvme.cmd.identify.ctrl.nvmeof.ccrl",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_nvmeof_rsvd,
            { "Reserved", "nvme.cmd.identify.ctrl.nvmeof.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psds,
            { "Power State Attributes", "nvme.cmd.identify.ctrl.psds",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd,
            { "Power State 0 Descriptor (PSD0)", "nvme.cmd.identify.ctrl.psds.psd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_mp,
            { "Maximum Power (MP)", "nvme.cmd.identify.ctrl.psds.psd.mp",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd0,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd0",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_mxps,
            { "Max Power Scale (MXPS)", "nvme.cmd.identify.ctrl.psds.psd.mxps",
               FT_BOOLEAN, 8, TFS(&units_watts), 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_nops,
            { "Non-Operational State (NOPS)", "nvme.cmd.identify.ctrl.psds.psd.nops",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd1,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd1",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_enlat,
            { "Entry Latency (ENLAT)", "nvme.cmd.identify.ctrl.psds.psd.enlat",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_exlat,
            { "Exit Latency (EXLAT)", "nvme.cmd.identify.ctrl.psds.psd.exlat",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rrt,
            { "Relative Read Throughput (RRT)", "nvme.cmd.identify.ctrl.psds.psd.rrt",
               FT_UINT8, BASE_DEC, NULL, 0x1f, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd2,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd2",
               FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rrl,
            { "Relative Read Latency (RRL)", "nvme.cmd.identify.ctrl.psds.psd.rrl",
               FT_UINT8, BASE_DEC, NULL, 0x1f, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd3,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd3",
               FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rwt,
            { "Relative Write Throughput (RWT)", "nvme.cmd.identify.ctrl.psds.psd.rwt",
               FT_UINT8, BASE_DEC, NULL, 0x1f, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd4,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd4",
               FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rwl,
            { "Relative Write Latency (RWL)", "nvme.cmd.identify.ctrl.psds.psd.rwl",
               FT_UINT8, BASE_DEC, NULL, 0x1f, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd5,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd5",
               FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_idlp,
            { "Idle Power (IDLP)", "nvme.cmd.identify.ctrl.psds.psd.idlp",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd6,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd6",
               FT_UINT8, BASE_HEX, NULL, 0x3f, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_ips,
            { "Idle Power Scale (IPS)", "nvme.cmd.identify.ctrl.psds.psd.ips",
               FT_UINT8, BASE_HEX, VALS(power_scale_tbl), 0xc0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd7,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd7",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_actp,
            { "Active Power (ACTP)", "nvme.cmd.identify.ctrl.psds.psd.actp",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_apw,
            { "Active Power Workload (APW)", "nvme.cmd.identify.ctrl.psds.psd.apw",
               FT_UINT8, BASE_HEX, NULL, 0x7, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd8,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd8",
               FT_UINT8, BASE_HEX, NULL, 0x38, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_aps,
            { "Active Power Scale (APS)", "nvme.cmd.identify.ctrl.psds.psd.aps",
               FT_UINT8, BASE_HEX, VALS(power_scale_tbl), 0xc0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_epfrt,
            { "Emergency Power Fail Recovery Time (EPFRT)", "nvme.cmd.identify.ctrl.psds.psd.epfrt",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_fqvt,
            { "Forced Quiescence Vault Time (FQVT)", "nvme.cmd.identify.ctrl.psds.psd.fqvt",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_epfvt,
            { "Emergency Power Fail Vault Time (EPFVT)", "nvme.cmd.identify.ctrl.psds.psd.epfvt",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_epfrts,
            { "Emergency Power Fail Recovery Time Scale (EPFRTS)", "nvme.cmd.identify.ctrl.psds.psd.epfrts",
               FT_UINT8, BASE_HEX, VALS(time_scale_tbl), 0x0f, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_fqvts,
            { "Forced Quiescence Vault Time Scale (FQVTS)", "nvme.cmd.identify.ctrl.psds.psd.fqvts",
               FT_UINT8, BASE_HEX, VALS(time_scale_tbl), 0xf0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_epfvts,
            { "Emergency Power Fail Vault Time Scale (EPFVTS)", "nvme.cmd.identify.ctrl.psds.psd.epfvts",
               FT_UINT8, BASE_HEX, VALS(time_scale_tbl), 0x0f, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd9,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd9",
               FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_mbw,
            { "Max Bandwidth (MBW)", "nvme.cmd.identify.ctrl.psds.psd.mbw",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_mbws,
            { "Max Bandwidth Scale (MBWS)", "nvme.cmd.identify.ctrl.psds.psd.mbws",
               FT_UINT8, BASE_HEX, VALS(max_bw_scale_tbl), 0x07, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd10,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd10",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_psd_rsvd11,
            { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd11",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_vs,
            { "Vendor Specific", "nvme.cmd.identify.ctrl.vs",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },

        /* Identify nslist response */
        { &hf_nvme_identify_nslist_nsid,
            { "Namespace list element", "nvme.cmd.identify.nslist.nsid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Identify Namespace Identification Descriptor list (CNS 03h) response */
        { &hf_nvme_identify_nsdesc_nidt,
            { "Namespace Identifier Type (NIDT)", "nvme.cmd.identify.nsdesc.nidt",
               FT_UINT8, BASE_HEX, VALS(nidt_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_nsdesc_nidl,
            { "Namespace Identifier Length (NIDL)", "nvme.cmd.identify.nsdesc.nidl",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_nsdesc_nid,
            { "Namespace Identifier (NID)", "nvme.cmd.identify.nsdesc.nid",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Identify Controller List (CNS 12h/13h) response */
        { &hf_nvme_identify_ctrl_list_num,
            { "Number of Controller Identifiers (NUMCIDS)", "nvme.cmd.identify.ctrl_list.num",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ctrl_list_id,
            { "Controller Identifier", "nvme.cmd.identify.ctrl_list.id",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Identify NVM Set List (CNS 04h) response */
        { &hf_nvme_identify_nvmset_num,
            { "Number of Entries (NUMENT)", "nvme.cmd.identify.nvmset.num",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_nvmset_id,
            { "NVM Set Identifier (NSETID)", "nvme.cmd.identify.nvmset.id",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_nvmset_endgid,
            { "Endurance Group Identifier (ENDGID)", "nvme.cmd.identify.nvmset.endgid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_nvmset_r4krt,
            { "Random 4 KiB Read Typical (R4KRT)", "nvme.cmd.identify.nvmset.r4krt",
               FT_UINT32, BASE_DEC, NULL, 0x0, "In 100 ns units", HFILL}
        },
        { &hf_nvme_identify_nvmset_ows,
            { "Optimal Write Size (OWS)", "nvme.cmd.identify.nvmset.ows",
               FT_UINT32, BASE_DEC, NULL, 0x0, "In bytes", HFILL}
        },
        { &hf_nvme_identify_nvmset_tnvmsc,
            { "Total NVM Set Capacity (TNVMSC)", "nvme.cmd.identify.nvmset.tnvmsc",
               FT_BYTES, BASE_NONE, NULL, 0x0, "In bytes (128-bit)", HFILL}
        },
        { &hf_nvme_identify_nvmset_unvmsc,
            { "Unallocated NVM Set Capacity (UNVMSC)", "nvme.cmd.identify.nvmset.unvmsc",
               FT_BYTES, BASE_NONE, NULL, 0x0, "In bytes (128-bit)", HFILL}
        },
        /* Identify Primary Controller Capabilities (CNS 14h) response */
        { &hf_nvme_identify_pcc_cntlid,
            { "Controller Identifier (CNTLID)", "nvme.cmd.identify.pcc.cntlid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_portid,
            { "Port Identifier (PORTID)", "nvme.cmd.identify.pcc.portid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_crt[0],
            { "Controller Resource Types (CRT)", "nvme.cmd.identify.pcc.crt",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_crt[1],
            { "VQ Resources Support (VQRS)", "nvme.cmd.identify.pcc.crt.vqrs",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_crt[2],
            { "VI Resources Support (VIRS)", "nvme.cmd.identify.pcc.crt.virs",
               FT_UINT32, BASE_HEX, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_crt[3],
            { "Reserved", "nvme.cmd.identify.pcc.crt.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffc, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vqfrt,
            { "VQ Resources Flexible Total (VQFRT)", "nvme.cmd.identify.pcc.vqfrt",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vqrfa,
            { "VQ Resources Flexible Assigned (VQRFA)", "nvme.cmd.identify.pcc.vqrfa",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vqrfap,
            { "VQ Resources Flexible Allocated to Primary (VQRFAP)", "nvme.cmd.identify.pcc.vqrfap",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vqprt,
            { "VQ Resources Private Total (VQPRT)", "nvme.cmd.identify.pcc.vqprt",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vqfrsm,
            { "VQ Resources Flexible Secondary Maximum (VQFRSM)", "nvme.cmd.identify.pcc.vqfrsm",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vqgran,
            { "VQ Flexible Resource Preferred Granularity (VQGRAN)", "nvme.cmd.identify.pcc.vqgran",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vifrt,
            { "VI Resources Flexible Total (VIFRT)", "nvme.cmd.identify.pcc.vifrt",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_virfa,
            { "VI Resources Flexible Assigned (VIRFA)", "nvme.cmd.identify.pcc.virfa",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_virfap,
            { "VI Resources Flexible Allocated to Primary (VIRFAP)", "nvme.cmd.identify.pcc.virfap",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_viprt,
            { "VI Resources Private Total (VIPRT)", "nvme.cmd.identify.pcc.viprt",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vifrsm,
            { "VI Resources Flexible Secondary Maximum (VIFRSM)", "nvme.cmd.identify.pcc.vifrsm",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_pcc_vigran,
            { "VI Flexible Resource Preferred Granularity (VIGRAN)", "nvme.cmd.identify.pcc.vigran",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        /* Identify Secondary Controller List (CNS 15h) response */
        { &hf_nvme_identify_scl_num,
            { "Number of Entries (NUMENT)", "nvme.cmd.identify.scl.num",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_scl_scid,
            { "Secondary Controller Identifier (SCID)", "nvme.cmd.identify.scl.scid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_scl_pcid,
            { "Primary Controller Identifier (PCID)", "nvme.cmd.identify.scl.pcid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_scl_scs[0],
            { "Secondary Controller State (SCS)", "nvme.cmd.identify.scl.scs",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_scl_scs[1],
            { "Online State (OLS)", "nvme.cmd.identify.scl.scs.ols",
               FT_UINT8, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_scl_scs[2],
            { "Reserved", "nvme.cmd.identify.scl.scs.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_identify_scl_vfn,
            { "Virtual Function Number (VFN)", "nvme.cmd.identify.scl.vfn",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_scl_nvq,
            { "Number of VQ Flexible Resources Assigned (NVQ)", "nvme.cmd.identify.scl.nvq",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_scl_nvi,
            { "Number of VI Flexible Resources Assigned (NVI)", "nvme.cmd.identify.scl.nvi",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        /* Identify Namespace Granularity List (CNS 16h) response */
        { &hf_nvme_identify_ngl_nga[0],
            { "Namespace Granularity Attributes (NGA)", "nvme.cmd.identify.ngl.nga",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_identify_ngl_nga[1],
            { "Granularity Descriptor Mapping (GDM)", "nvme.cmd.identify.ngl.nga.gdm",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_identify_ngl_nga[2],
            { "Reserved", "nvme.cmd.identify.ngl.nga.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_identify_ngl_nd,
            { "Number of Descriptors (ND)", "nvme.cmd.identify.ngl.nd",
               FT_UINT8, BASE_DEC, NULL, 0x0, "0's based count", HFILL}
        },
        { &hf_nvme_identify_ngl_nsg,
            { "Namespace Size Granularity (NSG)", "nvme.cmd.identify.ngl.nsg",
               FT_UINT64, BASE_DEC, NULL, 0x0, "In bytes", HFILL}
        },
        { &hf_nvme_identify_ngl_ncg,
            { "Namespace Capacity Granularity (NCG)", "nvme.cmd.identify.ngl.ncg",
               FT_UINT64, BASE_DEC, NULL, 0x0, "In bytes", HFILL}
        },
        /* Identify UUID List (CNS 17h) response */
        { &hf_nvme_identify_uuid_idassoc,
            { "Identifier Association (IDASSOC)", "nvme.cmd.identify.uuid.idassoc",
               FT_UINT8, BASE_HEX, VALS(uuid_idassoc_tbl), 0x3, NULL, HFILL}
        },
        { &hf_nvme_identify_uuid_uuid,
            { "UUID", "nvme.cmd.identify.uuid.uuid",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* get logpage response */
        /* Identify Response */
        { &hf_nvme_get_logpage_ify_genctr,
            { "Generation Counter (GENCTR)", "nvme.cmd.get_logpage.identify.genctr",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_numrec,
            { "Number of Records (NUMREC)", "nvme.cmd.get_logpage.identify.numrec",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_recfmt,
            { "Record Format (RECFMT)", "nvme.cmd.get_logpage.identify.recfmt",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.identify.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd,
            { "Discovery Log Entry", "nvme.cmd.get_logpage.identify.rcrd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_trtype,
            { "Transport Type (TRTYPE)", "nvme.cmd.get_logpage.identify.rcrd.trtype",
               FT_UINT8, BASE_HEX, VALS(trt_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_adrfam,
            { "Address Family (ADRFAM)", "nvme.cmd.get_logpage.identify.rcrd.adrfam",
               FT_UINT8, BASE_HEX, VALS(adrfam_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_subtype,
            { "Subsystem Type (SUBTYPE)", "nvme.cmd.get_logpage.identify.rcrd.subtype",
               FT_UINT8, BASE_HEX, VALS(sub_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_treq[0],
            { "Transport Requirements (TREQ)", "nvme.cmd.get_logpage.identify.rcrd.treq",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* NVMe Base 2.3 Figure 310, byte 03: TSC 1:0, SQFCD 2, ZHIDS 3,
         * TASC 5:4, Reserved 7:6.  The pre-2.0 layout this was written against
         * had a 1-bit secure-channel flag and SQ flow control on bit 1. */
        { &hf_nvme_get_logpage_ify_rcrd_treq[1],
            { "Transport Secure Channel (TSC)", "nvme.cmd.get_logpage.identify.rcrd.treq.secch",
               FT_UINT8, BASE_HEX, VALS(treq_tsc_tbl), 0x3, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_treq[2],
            { "SQ Flow Control Disable (SQFCD)", "nvme.cmd.get_logpage.identify.rcrd.treq.sqfc",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_treq[3],
            { "Zero Host ID Support (ZHIDS)", "nvme.cmd.get_logpage.identify.rcrd.treq.zhids",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_treq[4],
            { "Transport Authentication and Secure Channel (TASC)",
               "nvme.cmd.get_logpage.identify.rcrd.treq.tasc",
               FT_UINT8, BASE_HEX, VALS(treq_tasc_tbl), 0x30, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_treq[5],
            { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.treq.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xc0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_portid,
            { "Port ID (PORTID)", "nvme.cmd.get_logpage.identify.rcrd.portid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_cntlid,
            { "Controller ID (CNTLID)", "nvme.cmd.get_logpage.identify.rcrd.cntlid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_asqsz,
            { "Admin Max SQ Size (ASQSZ)", "nvme.cmd.get_logpage.identify.rcrd.asqsz",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_disc_rcrd_eflags[0],
            { "Entry flags (EFLAGS)", "nvme.cmd.get_logpage.discovery.rcrd.eflags",
                FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_disc_rcrd_eflags[1],
            { "Duplicate Returned Information (DUPRETINFO)", "nvme.cmd.get_logpage.discovery.rcrd.eflags.dupretinfo",
                FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_disc_rcrd_eflags[2],
            { "Explicit Persistent Connection Support for Discovery (EPCSD)",
                "nvme.cmd.get_logpage.discovery.rcrd.eflags.epcsd",
                FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
        },
        /* NVMe Base 2.3 Figure 310, bytes 11:10: NCC is bit 2. */
        { &hf_nvme_get_logpage_disc_rcrd_eflags[3],
            { "No CDC Connectivity (NCC)", "nvme.cmd.get_logpage.discovery.rcrd.eflags.ncc",
                FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_disc_rcrd_eflags[4],
            { "Reserved", "nvme.cmd.get_logpage.discovery.rcrd.eflags.rsvd0",
                FT_UINT16, BASE_HEX, NULL, 0xfff8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_trsvcid,
            { "Transport Service Identifier (TRSVCID)", "nvme.cmd.get_logpage.identify.rcrd.trsvcid",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_subnqn,
            { "NVM Subsystem Qualified Name (SUBNQN)", "nvme.cmd.get_logpage.identify.rcrd.subnqn",
               FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_traddr,
            { "Transport Address (TRADDR)", "nvme.cmd.get_logpage.identify.rcrd.traddr",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas,
            { "Transport Specific Address Subtype (TSAS)", "nvme.cmd.get_logpage.identify.rcrd.tsas",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_qptype,
            { "RDMA QP Service Type (RDMA_QPTYPE)", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_qptype",
               FT_UINT8, BASE_HEX, VALS(qp_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_prtype,
            { "RDMA Provider Type (RDMA_PRTYPE)", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_prtype",
               FT_UINT8, BASE_HEX, VALS(pr_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_cms,
            { "RDMA Connection Management Service (RDMA_CMS)", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_cms",
               FT_UINT8, BASE_HEX, VALS(cms_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_pkey,
            { "RDMA Partition Key (RDMA_PKEY)", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_pkey",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas_tcp_sectype,
            { "Security Type (SECTYPE)", "nvme.cmd.get_logpage.identify.rcrd.tsas.tcp_sectype",
               FT_UINT8, BASE_HEX, VALS(sec_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ify_rcrd_tsas_tcp_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.tsas.tcp_rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Error Information Response */
        { &hf_nvme_get_logpage_errinf_errcnt,
            { "Error Count", "nvme.cmd.get_logpage.errinf.errcnt",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_sqid,
            { "Submission Queue ID", "nvme.cmd.get_logpage.errinf.sqid",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_cid,
            { "Command ID", "nvme.cmd.get_logpage.errinf.cid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_sf[0],
            { "Status Field", "nvme.cmd.get_logpage.errinf.sf",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_sf[1],
            { "Status Field Value", "nvme.cmd.get_logpage.errinf.sf.val",
               FT_UINT16, BASE_HEX, NULL, 0x7fff, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_sf[2],
            { "Status Field Phase Tag", "nvme.cmd.get_logpage.errinf.sf.ptag",
               FT_UINT16, BASE_HEX, NULL, 0x8000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_pel[0],
            { "Parameter Error Location", "nvme.cmd.get_logpage.errinf.pel",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_pel[1],
            { "Byte in command that contained the error", "nvme.cmd.get_logpage.errinf.pel.bytee",
               FT_UINT16, BASE_DEC, NULL, 0xff, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_pel[2],
            { "Bit in command that contained the error", "nvme.cmd.get_logpage.errinf.pel.bite",
               FT_UINT16, BASE_DEC, NULL, 0x0700, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_pel[3],
            { "Reserved", "nvme.cmd.get_logpage.errinf.pel.rsvd",
               FT_UINT16, BASE_DEC, NULL, 0xf800, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_lba,
            { "LBA", "nvme.cmd.get_logpage.errinf.lba",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_ns,
            { "Namespace ID", "nvme.cmd.get_logpage.errinf.nsid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_vsi,
            { "Vendor Specific Information Available", "nvme.cmd.get_logpage.errinf.vsi",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_trtype,
            { "Transport Type", "nvme.cmd.get_logpage.errinf.trype",
               FT_UINT8, BASE_HEX, VALS(trt_type_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_cmdset,
            { "Command Set Indicator (CSI)", "nvme.cmd.get_logpage.errinf.cmdset",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_opc,
            { "Opcode", "nvme.cmd.get_logpage.errinf.opc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_csi,
            { "Command Specific Information", "nvme.cmd.get_logpage.errinf.csi",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_tsi,
            { "Transport Type Specific Information", "nvme.cmd.get_logpage.errinf.tsi",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.errinf.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_errinf_lpver,
            { "Log Page Version", "nvme.cmd.get_logpage.errinf.lpver",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Get LogPage SMART response */
        { &hf_nvme_get_logpage_smart_cw[0],
            { "Critical Warning", "nvme.cmd.get_logpage.smart.cw",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cw[1],
            { "Spare Capacity Below Threshold", "nvme.cmd.get_logpage.smart.cw.sc",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cw[2],
            { "Temperature Crossed Threshold", "nvme.cmd.get_logpage.smart.cw.temp",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cw[3],
            { "Reliability Degraded due to Significant Media Errors", "nvme.cmd.get_logpage.smart.cw.sme",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cw[4],
            { "Media Placed in RO State", "nvme.cmd.get_logpage.smart.cw.ro",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cw[5],
            { "Volatile Memory Backup Device Has Failed", "nvme.cmd.get_logpage.smart.cw.bdf",
               FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cw[6],
            { "Persistent Memory Region Placed in RO State", "nvme.cmd.get_logpage.smart.cw.mrro",
               FT_BOOLEAN, 8, NULL, 0x20, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cw[7],
            { "Indeterminate Personality State", "nvme.cmd.get_logpage.smart.cw.ips",
               FT_BOOLEAN, 8, NULL, 0x40, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cw[8],
            { "Reserved", "nvme.cmd.get_logpage.smart.cw.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ct,
            { "Composite Temperature (degrees K)", "nvme.cmd.get_logpage.smart.ct",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_asc,
            { "Available Spare Capacity (%)", "nvme.cmd.get_logpage.smart.asc",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ast,
            { "Available Spare Capacity Threshold (%)", "nvme.cmd.get_logpage.smart.ast",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_lpu,
            { "Life Age Estimate (%)", "nvme.cmd.get_logpage.smart.lae",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_egcws[0],
            { "Endurance Group Critical Warning Summary", "nvme.cmd.get_logpage.smart.egcws",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_egcws[1],
            { "Spare Capacity of Endurance Group Below Threshold", "nvme.cmd.get_logpage.smart.egcws.sc",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_egcws[2],
            { "Reserved", "nvme.cmd.get_logpage.smart.egcws.rsvd0",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_egcws[3],
            { "Reliability of Endurance Group Degraded due to Media Errors", "nvme.cmd.get_logpage.smart.egcws.me",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_egcws[4],
            { "A Namespace in Endurance Group Placed in RO State", "nvme.cmd.get_logpage.smart.egcws.ro",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_egcws[5],
            { "Reserved", "nvme.cmd.get_logpage.smart.egcws.rsvd1",
               FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.smart.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_dur,
            { "Data Units Read", "nvme.cmd.get_logpage.smart.dur",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_duw,
            { "Data Units Written", "nvme.cmd.get_logpage.smart.duw",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_hrc,
            { "Host Read Commands", "nvme.cmd.get_logpage.smart.hrc",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_hwc,
            { "Host Write Commands", "nvme.cmd.get_logpage.smart.hwc",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cbt,
            { "Controller Busy Time (minutes)", "nvme.cmd.get_logpage.smart.cbt",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_pc,
            { "Power Cycles", "nvme.cmd.get_logpage.smart.pc",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_poh,
            { "Power On Hours", "nvme.cmd.get_logpage.smart.poh",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_mie,
            { "Media Integrity Errors", "nvme.cmd.get_logpage.smart.mie",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_us,
            { "Unsafe Shutdowns", "nvme.cmd.get_logpage.smart.us",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ele,
            { "Number of Error Information Log Entries", "nvme.cmd.get_logpage.smart.ele",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_wctt,
            { "Warning Composite Temperature Time (minutes)", "nvme.cmd.get_logpage.smart.wctt",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_cctt,
            { "Critical Composite Temperature Time (minutes)", "nvme.cmd.get_logpage.smart.cctt",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[0],
            { "Temperature Sensors", "nvme.cmd.get_logpage.smart.ts",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[1],
            { "Temperature Sensor 1 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s1",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[2],
            { "Temperature Sensor 2 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s2",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[3],
            { "Temperature Sensor 3 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s3",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[4],
            { "Temperature Sensor 4 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s4",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[5],
            { "Temperature Sensor 5 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s5",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[6],
            { "Temperature Sensor 6 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s6",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[7],
            { "Temperature Sensor 7 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s7",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_ts[8],
            { "Temperature Sensor 8 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s8",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_tmt1c,
            { "Thermal Management Temperature 1 Transition Count", "nvme.cmd.get_logpage.smart.tmt1c",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_tmt2c,
            { "Thermal Management Temperature 2 Transition Count", "nvme.cmd.get_logpage.smart.tmt2c",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_tmt1t,
            { "Total Time For Thermal Management Temperature 1 (seconds)", "nvme.cmd.get_logpage.smart.tmt1t",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_tmt2t,
            { "Total Time For Thermal Management Temperature 2 (seconds)", "nvme.cmd.get_logpage.smart.tmt2t",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_smart_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.smart.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* FW Slot Information Response */
        { &hf_nvme_get_logpage_fw_slot_afi[0],
            { "Active Firmware Info (AFI)", "nvme.cmd.get_logpage.fw_slot.afi",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_afi[1],
            { "Active Firmware Slot", "nvme.cmd.get_logpage.fw_slot.afi.afs",
               FT_UINT8, BASE_HEX, NULL, 0x7, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_afi[2],
            { "Reserved", "nvme.cmd.get_logpage.fw_slot.afi.rsvd0",
               FT_UINT8, BASE_HEX, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_afi[3],
            { "Next Reset Firmware Slot", "nvme.cmd.get_logpage.fw_slot.afi.nfs",
               FT_UINT8, BASE_HEX, NULL, 0x70, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_afi[4],
            { "Reserved", "nvme.cmd.get_logpage.fw_slot.afi.rsvd1",
               FT_UINT8, BASE_HEX, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.fw_slot.rsvd0",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_frs,
            { "Firmware Slot Revisions", "nvme.cmd.get_logpage.fw_slot.frs",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_frs_ascii[0],
            { "Firmware Revision for Slot 1 (ASCII)", "nvme.cmd.get_logpage.fw_slot.frs.s1.ascii",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_frs_ascii[1],
            { "Firmware Revision for Slot 2 (ASCII)", "nvme.cmd.get_logpage.fw_slot.frs.s2.ascii",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_frs_ascii[2],
            { "Firmware Revision for Slot 3 (ASCII)", "nvme.cmd.get_logpage.fw_slot.frs.s3.ascii",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_frs_ascii[3],
            { "Firmware Revision for Slot 4 (ASCII)", "nvme.cmd.get_logpage.fw_slot.frs.s4.ascii",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_frs_ascii[4],
            { "Firmware Revision for Slot 5 (ASCII)", "nvme.cmd.get_logpage.fw_slot.frs.s5.ascii",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_frs_ascii[5],
            { "Firmware Revision for Slot 6 (ASCII)", "nvme.cmd.get_logpage.fw_slot.frs.s6.ascii",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_frs_ascii[6],
            { "Firmware Revision for Slot 7 (ASCII)", "nvme.cmd.get_logpage.fw_slot.frs.s7.ascii",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_fw_slot_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.fw_slot.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Changed NameSpace List Response */
        { &hf_nvme_get_logpage_changed_nslist,
            { "Changed Namespace", "nvme.cmd.get_logpage.changed_nslist",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Commands Supported and Effects Response */
        { &hf_nvme_get_logpage_cmd_and_eff_cs,
            { "Command Supported Entry", "nvme.cmd.get_logpage.cmd_and_eff.cs",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[0],
            { "Commands Supported and Effects Data Structure", "nvme.cmd.get_logpage.cmd_and_eff.cseds",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[1],
            { "Command Supported (CSUPP)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.csupp",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[2],
            { "Logical Block Content Change (LBCC)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.lbcc",
               FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[3],
            { "Namespace Capability Change (NCC)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.ncc",
               FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[4],
            { "Namespace Inventory Change (NIC)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.nic",
               FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[5],
            { "Controller Capability Change (CCC)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.ccc",
               FT_BOOLEAN, 32, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[6],
            { "Reserved", "nvme.cmd.get_logpage.cmd_and_eff.cseds.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0xffe0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[7],
            { "Command Submission and Execution (CSE)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.cse",
               FT_UINT32, BASE_HEX, VALS(cmd_eff_cse_tbl), 0x70000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[8],
            { "UUID Selection Supported", "nvme.cmd.get_logpage.cmd_and_eff.cseds.uss",
               FT_BOOLEAN, 32, NULL, 0x80000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_and_eff_cseds[9],
            { "Reserved", "nvme.cmd.get_logpage.cmd_and_eff.cseds.rsvd1",
               FT_UINT32, BASE_HEX, NULL, 0xfff00000, NULL, HFILL}
        },
        /* Supported Log Pages Response (LID 00h) */
        { &hf_nvme_get_logpage_supported_lids,
            { "Log Page Identifier Supported", "nvme.cmd.get_logpage.supported.lids",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_supported_lidseds[0],
            { "LID Supported and Effects Data Structure", "nvme.cmd.get_logpage.supported.lidseds",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_supported_lidseds[1],
            { "LID Supported (LSUPP)", "nvme.cmd.get_logpage.supported.lidseds.lsupp",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_supported_lidseds[2],
            { "Index Offset Supported (IOS)", "nvme.cmd.get_logpage.supported.lidseds.ios",
               FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_supported_lidseds[3],
            { "Reserved", "nvme.cmd.get_logpage.supported.lidseds.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffc, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_supported_lidseds[4],
            { "LID Specific Parameter (LIDSP)", "nvme.cmd.get_logpage.supported.lidseds.lidsp",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        /* Device Self-Test Response */
                { &hf_nvme_get_logpage_selftest_csto[0],
            { "Current Device Self-Test Operation", "nvme.cmd.get_logpage.selftest.csto",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_csto[1],
            { "Current Self-Test Operation Status", "nvme.cmd.get_logpage.selftest.csto.st",
               FT_UINT8, BASE_HEX, VALS(stest_type_active_tbl), 0xf, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_csto[2],
            { "Reserved", "nvme.cmd.get_logpage.selftest.csto.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_cstc[0],
            { "Current Device Self-Test Completion", "nvme.cmd.get_logpage.selftest.cstc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_cstc[1],
            { "Self-Test Completion Percent", "nvme.cmd.get_logpage.selftest.cstc.pcnt",
               FT_UINT8, BASE_DEC, NULL, 0x7f, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_cstc[2],
            { "Reserved", "nvme.cmd.get_logpage.selftest.cstc.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.selftest.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res,
            { "Latest Self-test Result Data Structure", "nvme.cmd.get_logpage.selftest.res",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_status[0],
            { "Device Self-test Status", "nvme.cmd.get_logpage.selftest.res.status",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_status[1],
            { "Device Self-test Result", "nvme.cmd.get_logpage.selftest.res.status.result",
               FT_UINT8, BASE_HEX, VALS(stest_result_tbl), 0xf, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_status[2],
            { "Device Self-test Type", "nvme.cmd.get_logpage.selftest.res.status.type",
               FT_UINT8, BASE_HEX, VALS(stest_type_done_tbl), 0xf0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_sn,
            { "Segment Number", "nvme.cmd.get_logpage.selftest.res.sn",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_vdi[0],
            { "Valid Diagnostic Information", "nvme.cmd.get_logpage.selftest.res.vdi",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_vdi[1],
            { "Namespace Identifier (NSID) Field Valid", "nvme.cmd.get_logpage.selftest.res.vdi.nsid",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_vdi[2],
            { "Failing LBA (FLBA) Field Valid", "nvme.cmd.get_logpage.selftest.res.vdi.flba",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_vdi[3],
            { "Status Code Type (SCT) Field Valid", "nvme.cmd.get_logpage.selftest.res.vdi.sct",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_vdi[4],
            { "Status Code (SC) Field Valid", "nvme.cmd.get_logpage.selftest.res.vdi.sc",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_vdi[5],
            { "Reserved", "nvme.cmd.get_logpage.selftest.res.vdi.rsvd",
               FT_BOOLEAN, 8, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.selftest.res.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_poh,
            { "Power On Hours (POH)", "nvme.cmd.get_logpage.selftest.res.poh",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_nsid,
            { "Namespace Identifier (NSID)", "nvme.cmd.get_logpage.selftest.res.nsid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_flba,
            { "Failing LBA", "nvme.cmd.get_logpage.selftest.res.flba",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_sct[0],
            { "Status Code Type", "nvme.cmd.get_logpage.selftest.res.sct",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_sct[1],
            { "Additional Information", "nvme.cmd.get_logpage.selftest.res.sct.ai",
               FT_UINT8, BASE_HEX, NULL, 0x7, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_sct[2],
            { "Reserved", "nvme.cmd.get_logpage.selftest.res.sct.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_sc,
            { "Status Code", "nvme.cmd.get_logpage.selftest.res.sc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_selftest_res_vs,
            { "Vendor Specific", "nvme.cmd.get_logpage.selftest.res.vs",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Telemetry Log Response */
        { &hf_nvme_get_logpage_telemetry_li,
            { "Log Identifier", "nvme.cmd.get_logpage.telemetry.li",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.telemetry.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_ieee,
            { "IEEE OUI Identifier (IEEE)", "nvme.cmd.get_logpage.telemetry.ieee",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_da1lb,
            { "Telemetry Data Area 1 Last Block", "nvme.cmd.get_logpage.telemetry.da1b",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_da2lb,
            { "Telemetry Data Area 2 Last Block", "nvme.cmd.get_logpage.telemetry.da2b",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_da3lb,
            { "Telemetry Data Area 3 Last Block", "nvme.cmd.get_logpage.telemetry.da3b",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.telemetry.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_da4lb,
            { "Telemetry Data Area 4 Last Block", "nvme.cmd.get_logpage.telemetry.da4b",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_rsvd2,
            { "Reserved", "nvme.cmd.get_logpage.telemetry.rsvd2",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_scope,
            { "Telemetry Scope", "nvme.cmd.get_logpage.telemetry.scope",
               FT_UINT8, BASE_HEX, VALS(telemetry_scope_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_hdgn,
            { "Telemetry Host-Initiated Data Generation Number", "nvme.cmd.get_logpage.telemetry.hdgn",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_da,
            { "Telemetry Controller-Initiated Data Available", "nvme.cmd.get_logpage.telemetry.da",
               FT_BOOLEAN, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_dgn,
            { "Telemetry Controller-Initiated Data Generation Number", "nvme.cmd.get_logpage.telemetry.dgn",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_ri,
            { "Reason Identifier", "nvme.cmd.get_logpage.telemetry.ri",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_telemetry_db,
            { "Telemetry Data Block", "nvme.cmd.get_logpage.telemetry.db",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Endurance Group Response */
        { &hf_nvme_get_logpage_egroup_cw[0],
            { "Critical Warning", "nvme.cmd.get_logpage.egroup.cw",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_cw[1],
            { "Available Spare Capacity Below Threshold", "nvme.cmd.get_logpage.egroup.cw.asc",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_cw[2],
            { "Reserved", "nvme.cmd.get_logpage.egroup.cw.rsvd0",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_cw[3],
            { "Reliability of Endurance Group Degraded due to Media Errors", "nvme.cmd.get_logpage.egroup.cw.rd",
               FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_cw[4],
            { "All Namespaces in Endurance Group Placed in RO State", "nvme.cmd.get_logpage.egroup.cw.ro",
               FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_cw[5],
            { "Reserved", "nvme.cmd.get_logpage.egroup.cw.rsvd1",
               FT_BOOLEAN, 8, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_egfeat[0],
            { "Endurance Group Features", "nvme.cmd.get_logpage.egroup.egfeat",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_egfeat[1],
            { "Endurance Group Media (Rotational)", "nvme.cmd.get_logpage.egroup.egfeat.egrmedia",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_egfeat[2],
            { "Reserved", "nvme.cmd.get_logpage.egroup.egfeat.rsvd0",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.egroup.rsvd0",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_as,
            { "Available Spare Capacity %", "nvme.cmd.get_logpage.egroup.as",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_ast,
            { "Available Spare Threshold %", "nvme.cmd.get_logpage.egroup.ast",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_pu,
            { "Life Age (Percentage Used) %", "nvme.cmd.get_logpage.egroup.pu",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_did,
            { "Domain Identifier", "nvme.cmd.get_logpage.egroup.did",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.egroup.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_ee,
            { "Endurance Estimate (GB that may be written)", "nvme.cmd.get_logpage.egroup.ee",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_dur,
            { "Data Units Read (GB)", "nvme.cmd.get_logpage.egroup.dur",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_duw,
            { "Data Units Written (GB)", "nvme.cmd.get_logpage.egroup.duw",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_muw,
            { "Media Units Written (GB)", "nvme.cmd.get_logpage.egroup.muw",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_hrc,
            { "Host Read Commands", "nvme.cmd.get_logpage.egroup.hrc",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_hwc,
            { "Host Write Commands", "nvme.cmd.get_logpage.egroup.hwc",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_mdie,
            { "Media and Data Integrity Errors", "nvme.cmd.get_logpage.egroup.mdie",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_ele,
            { "Number of Error Information Log Entries", "nvme.cmd.get_logpage.egroup.ele",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_tegcap,
            { "Total Endurance Group Capacity (TEGCAP)", "nvme.cmd.get_logpage.egroup.tegcap",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_uegcap,
            { "Unallocated Endurance Group Capacity (UEGCAP)", "nvme.cmd.get_logpage.egroup.uegcap",
               FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_rsvd2,
            { "Reserved", "nvme.cmd.get_logpage.egroup.rsvd2",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Predictable Latency NVMSet Response */
        { &hf_nvme_get_logpage_pred_lat_status[0],
            { "Predictable Latency NVM Set Status", "nvme.cmd.get_logpage.pred_lat.status",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_status[1],
            { "Enabled Window Setting", "nvme.cmd.get_logpage.pred_lat.status.ws",
               FT_UINT8, BASE_HEX, VALS(plat_status_tbl), 0x7, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_status[2],
            { "Reserved", "nvme.cmd.get_logpage.pred_lat.status.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.pred_lat.rsvd0",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_etype[0],
            { "Event Type", "nvme.cmd.get_logpage.pred_lat.etype",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_etype[1],
            { "DTWIN Reads Warning", "nvme.cmd.get_logpage.pred_lat.etype.rw",
               FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_etype[2],
            { "DTWIN Writes Warning", "nvme.cmd.get_logpage.pred_lat.etype.ww",
               FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_etype[3],
            { "DTWIN Time Warning", "nvme.cmd.get_logpage.pred_lat.etype.tw",
               FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_etype[4],
            { "Reserved", "nvme.cmd.get_logpage.pred_lat.etype.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0x3ff8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_etype[5],
            { "Autonomous transition from DTWIN to NDWIN due to typical or maximum value exceeded", "nvme.cmd.get_logpage.pred_lat.etype.atve",
               FT_BOOLEAN, 16, NULL, 0x4000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_etype[6],
            { "Autonomous transition from DTWIN to NDWIN due to Deterministic Excursion", "nvme.cmd.get_logpage.pred_lat.etype.atde",
               FT_BOOLEAN, 16, NULL, 0x8000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.pred_lat.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_dtwin_rt,
            { "DTWIN Reads Typical (4 KiB blocks)", "nvme.cmd.get_logpage.pred_lat.dtwin_rt",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_dtwin_wt,
            { "DTWIN Writes Typical (optimal block size)", "nvme.cmd.get_logpage.pred_lat.dtwin_wt",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_dtwin_tm,
            { "DTWIN Time Maximum (ms)", "nvme.cmd.get_logpage.pred_lat.dtwin_tm",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_ndwin_tmh,
            { "NDWIN Time Minimum High (ms)", "nvme.cmd.get_logpage.pred_lat.ndwin_tmh",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_ndwin_tml,
            { "NDWIN Time Minimum Low (ms)", "nvme.cmd.get_logpage.pred_lat.ndwin_tml",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_rsvd2,
            { "Reserved", "nvme.cmd.get_logpage.pred_lat.rsvd2",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_dtwin_re,
            { "DTWIN Reads Estimate (4 KiB blocks)", "nvme.cmd.get_logpage.pred_lat.dtwin_re",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_dtwin_we,
            { "DTWIN Writes Estimate (optimal block size)", "nvme.cmd.get_logpage.pred_lat.dtwin_we",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_dtwin_te,
            { "DTWIN Time Estimate (ms)", "nvme.cmd.get_logpage.pred_lat.dtwin_te",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_rsvd3,
            { "Reserved", "nvme.cmd.get_logpage.pred_lat.rsvd3",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Predictable Latency NVMSet Aggregate Response */
        { &hf_nvme_get_logpage_pred_lat_aggreg_ne,
            { "Number of Entries", "nvme.cmd.get_logpage.pred_lat_aggreg.ne",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_pred_lat_aggreg_nset,
            { "NVM Set with Pending Predictable Latency Event", "nvme.cmd.get_logpage.pred_lat_aggreg.nset",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* ANA Response */
        { &hf_nvme_get_logpage_ana_chcnt,
            { "Change Count", "nvme.cmd.get_logpage.ana.chcnt",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_ngd,
            { "Number of ANA Group Descriptors", "nvme.cmd.get_logpage.ana.ngd",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.ana.rsvd",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp,
            { "ANA Group Descriptor", "nvme.cmd.get_logpage.ana.grp",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp_id,
            { "ANA Group ID", "nvme.cmd.get_logpage.ana.grp.id",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp_nns,
            { "Number of NSID Values", "nvme.cmd.get_logpage.ana.grp.nns",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp_chcnt,
            { "Change Count", "nvme.cmd.get_logpage.ana.grp.chcnt",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp_anas[0],
            { "ANA State", "nvme.cmd.get_logpage.ana.grp.anas",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp_anas[1],
            { "Asymmetric Namespace Access State", "nvme.cmd.get_logpage.ana.grp.anas.state",
               FT_UINT8, BASE_HEX, VALS(ana_state_tbl), 0xf, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp_anas[2],
            { "Reserved", "nvme.cmd.get_logpage.ana.grp.anas.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.ana.grp.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_ana_grp_nsid,
            { "Namespace Identifier", "nvme.cmd.get_logpage.ana.grp.nsid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* LBA Status Information Response */
        { &hf_nvme_get_logpage_lba_status_lslplen,
            { "LBA Status Log Page Length (LSLPLEN)", "nvme.cmd.get_logpage.lba_status.lslplen",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nlslne,
            { "Number of LBA Status Log Namespace Elements (NLSLNE)", "nvme.cmd.get_logpage.lba_status.nlslne",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_estulb,
            { "Estimate of Unrecoverable Logical Blocks (ESTULB)", "nvme.cmd.get_logpage.lba_status.estulb",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.lba_status.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_lsgc,
            { "LBA Status Generation Counter (LSGC)", "nvme.cmd.get_logpage.lba_status.lsgc",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel,
            { "LBA Status Log Namespace Element List", "nvme.cmd.get_logpage.lba_status.nel",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne,
            { "LBA Status Log Namespace Element", "nvme.cmd.get_logpage.lba_status.nel.ne",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne_neid,
            { "Namespace Element Identifier (NEID)", "nvme.cmd.get_logpage.lba_status.nel.ne.neid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne_nlrd,
            { "Number of LBA Range Descriptors (NLRD)", "nvme.cmd.get_logpage.lba_status.nel.ne.nlrd",
               FT_UINT32, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne_ratype,
            { "Recommended Action Type (RATYPE)", "nvme.cmd.get_logpage.lba_status.nel.ne.ratype",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.lba_status.nel.ne.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne_rd,
            { "LBA Range Descriptor", "nvme.cmd.get_logpage.lba_status.nel.ne.rd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne_rd_rslba,
            { "Range Starting LBA (RSLBA)", "nvme.cmd.get_logpage.lba_status.nel.ne.rd.rslba",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne_rd_rnlb,
            { "Range Number of Logical Blocks (RNLB)", "nvme.cmd.get_logpage.lba_status.nel.ne.rd.rnlb",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_lba_status_nel_ne_rd_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.lba_status.nel.ne.rd.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Get LogPage Endurance Group Aggregate Response */
        { &hf_nvme_get_logpage_egroup_aggreg_ne,
            { "Number of Entries", "nvme.cmd.get_logpage.egroup_agreg.ne",
               FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_egroup_aggreg_eg,
            { "Endurance Group", "nvme.cmd.get_logpage.egroup_agreg.eg",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        /* Get LogPage Reservation Notification Response */
        { &hf_nvme_get_logpage_reserv_notif_lpc,
            { "Log Page Count", "nvme.cmd.get_logpage.reserv_notif.lpc",
               FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_reserv_notif_lpt,
            { "Reservation Notification Log Page Type", "nvme.cmd.get_logpage.reserv_notif.lpt",
               FT_UINT8, BASE_HEX, VALS(rnlpt_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_reserv_notif_nalp,
            { "Number of Available Log Pages", "nvme.cmd.get_logpage.reserv_notif.nalp",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_reserv_notif_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.reserv_notif.rsvd0",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_reserv_notif_nsid,
            { "Namespace ID", "nvme.cmd.get_logpage.reserv_notif.nsid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_reserv_notif_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.reserv_notif.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Get LogPage Sanitize Response */
        { &hf_nvme_get_logpage_sanitize_sprog,
            { "Sanitize Progress (SPROG)", "nvme.cmd.get_logpage.sanitize.sprog",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_sstat[0],
            { "Sanitize Status (SSTAT)", "nvme.cmd.get_logpage.sanitize.sstat",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_sstat[1],
            { "Status of the most recent Sanitize Operation", "nvme.cmd.get_logpage.sanitize.sstat.mrst",
               FT_UINT16, BASE_HEX, VALS(san_mrst_tbl), 0x7, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_sstat[2],
            { "Number of Completed Overwrite Passes", "nvme.cmd.get_logpage.sanitize.sstat.cop",
               FT_UINT16, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_sstat[3],
            { "Global Data Erased", "nvme.cmd.get_logpage.sanitize.sstat.gde",
               FT_BOOLEAN, 16, NULL, 0x100, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_sstat[4],
            { "Media Verification Canceled", "nvme.cmd.get_logpage.sanitize.sstat.mvcncld",
               FT_BOOLEAN, 16, NULL, 0x200, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_sstat[5],
            { "Namespace Data Erased", "nvme.cmd.get_logpage.sanitize.sstat.nde",
               FT_BOOLEAN, 16, NULL, 0x400, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_sstat[6],
            { "Reserved", "nvme.cmd.get_logpage.sanitize.sstat.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0xf800, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_scdw10,
            { "Sanitize Command Dword 10 Information (SCDW10)", "nvme.cmd.get_logpage.sanitize.scdw10",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_eto,
            { "Estimated Time For Overwrite (seconds)", "nvme.cmd.get_logpage.sanitize.eto",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_etbe,
            { "Estimated Time For Block Erase (seconds)", "nvme.cmd.get_logpage.sanitize.etbe",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_etce,
            { "Estimated Time For Crypto Erase (seconds)", "nvme.cmd.get_logpage.sanitize.etce",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_etond,
            { "Estimated Time For Overwrite (seconds) with No-Deallocate", "nvme.cmd.get_logpage.sanitize.etond",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_etbend,
            { "Estimated Time For Block Erase (seconds) with No-Deallocate", "nvme.cmd.get_logpage.sanitize.etbend",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_etcend,
            { "Estimated Time For Crypto Erase (seconds) with No-Deallocate", "nvme.cmd.get_logpage.sanitize.etcend",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_etpvds,
            { "Estimated Time For Post-Verification Deallocation State (seconds)", "nvme.cmd.get_logpage.sanitize.etpvds",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_ssi[0],
            { "Sanitize State Information (SSI)", "nvme.cmd.get_logpage.sanitize.ssi",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_ssi[1],
            { "Sanitize State (SANS)", "nvme.cmd.get_logpage.sanitize.ssi.sans",
               FT_UINT8, BASE_HEX, VALS(san_sans_tbl), 0x0f, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_ssi[2],
            { "Failure State (FAILS)", "nvme.cmd.get_logpage.sanitize.ssi.fails",
               FT_UINT8, BASE_HEX, VALS(san_sans_tbl), 0xf0,
               "Sanitize state in which the failure occurred", HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.sanitize.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_mnsoip,
            { "Maximum Namespace Sanitize Operations In Progress (MNSOIP)", "nvme.cmd.get_logpage.sanitize.mnsoip",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_stnsid,
            { "Sanitization Target NSID (STNSID)", "nvme.cmd.get_logpage.sanitize.stnsid",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_sanitize_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.sanitize.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Feature Identifiers Supported and Effects Response */
        { &hf_nvme_get_logpage_feat_sup_and_eff_fidx,
            { "FID Supported Entry", "nvme.cmd.get_logpage.feat_sup_and_eff.fidx",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[0],
            { "FID Supported and Effects Data Structure", "nvme.cmd.get_logpage.feat_sup_and_eff.fids",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[1],
            { "FID Supported (FSUPP)", "nvme.cmd.get_logpage.feat_sup_and_eff.fids.fsupp",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[2],
            { "User Data Content Change (UDCC)", "nvme.cmd.get_logpage.feat_sup_and_eff.fids.udcc",
               FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[3],
            { "Namespace Capability Change (NCC)", "nvme.cmd.get_logpage.feat_sup_and_eff.fids.ncc",
               FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[4],
            { "Namespace Inventory Change (NIC)", "nvme.cmd.get_logpage.feat_sup_and_eff.fids.nic",
               FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[5],
            { "Controller Capability Change (CCC)", "nvme.cmd.get_logpage.feat_sup_and_eff.fids.ccc",
               FT_BOOLEAN, 32, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[6],
            { "Reserved", "nvme.cmd.get_logpage.feat_sup_and_eff.fids.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0x7ffe0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[7],
            { "UUID Selection Supported (USS)", "nvme.cmd.get_logpage.feat_sup_and_eff.fids.uss",
               FT_BOOLEAN, 32, NULL, 0x80000, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_feat_sup_and_eff_fids[8],
            { "FID Scope (FSP)", "nvme.cmd.get_logpage.feat_sup_and_eff.fids.fsp",
               FT_UINT32, BASE_HEX, NULL, 0xfff00000, NULL, HFILL}
        },
        /* NVMe-MI Commands Supported and Effects Response */
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cs,
            { "MI Command Supported Entry", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cs",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[0],
            { "NVMe-MI Commands Supported and Effects Data Structure", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cseds",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[1],
            { "Command Supported (CSUPP)", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cseds.csupp",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[2],
            { "User Data Content Change (UDCC)", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cseds.udcc",
               FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[3],
            { "Namespace Capability Change (NCC)", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cseds.ncc",
               FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[4],
            { "Namespace Inventory Change (NIC)", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cseds.nic",
               FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[5],
            { "Controller Capability Change (CCC)", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cseds.ccc",
               FT_BOOLEAN, 32, NULL, 0x10, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[6],
            { "Reserved", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cseds.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffe0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_mi_cmd_sup_and_eff_cseds[7],
            { "Command Scope (CSP)", "nvme.cmd.get_logpage.mi_cmd_sup_and_eff.cseds.csp",
               FT_UINT32, BASE_HEX, NULL, 0xfff00000, NULL, HFILL}
        },
        /* Command and Feature Lockdown Response */
        { &hf_nvme_get_logpage_cmd_feat_lockdown_cfila[0],
            { "Command and Feature Identifier List Attributes (CFILA)", "nvme.cmd.get_logpage.cmd_feat_lockdown.cfila",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_feat_lockdown_cfila[1],
            { "Scope Selected (SS)", "nvme.cmd.get_logpage.cmd_feat_lockdown.cfila.ss",
               FT_UINT8, BASE_HEX, VALS(lockdown_scope_tbl), 0x0f, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_feat_lockdown_cfila[2],
            { "Contents Selected (CS)", "nvme.cmd.get_logpage.cmd_feat_lockdown.cfila.cs",
               FT_UINT8, BASE_HEX, VALS(lockdown_contents_tbl), 0x30, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_feat_lockdown_cfila[3],
            { "Reserved", "nvme.cmd.get_logpage.cmd_feat_lockdown.cfila.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xc0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_feat_lockdown_rsvd,
            { "Reserved", "nvme.cmd.get_logpage.cmd_feat_lockdown.rsvd",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_feat_lockdown_lngth,
            { "Length (LNGTH)", "nvme.cmd.get_logpage.cmd_feat_lockdown.lngth",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_feat_lockdown_cfil,
            { "Command/Feature Identifier", "nvme.cmd.get_logpage.cmd_feat_lockdown.cfil",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_cmd_feat_lockdown_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.cmd_feat_lockdown.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* Get LogPage Physical Interface Receiver Eye Opening Measurement (LID 19h) response */
        { &hf_nvme_get_logpage_eom_lid,
            { "Log Identifier", "nvme.cmd.get_logpage.eom.lid",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_eomip,
            { "EOM In Progress", "nvme.cmd.get_logpage.eom.eomip",
               FT_UINT8, BASE_HEX, VALS(eom_eomip_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_hsize,
            { "Header Size (bytes)", "nvme.cmd.get_logpage.eom.hsize",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_rsz,
            { "Result Size (bytes)", "nvme.cmd.get_logpage.eom.rsz",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_edgn,
            { "EOM Data Generation Number", "nvme.cmd.get_logpage.eom.edgn",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_lrev,
            { "Log Revision", "nvme.cmd.get_logpage.eom.lrev",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_odp[0],
            { "Optional Data Present", "nvme.cmd.get_logpage.eom.odp",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_odp[1],
            { "Printable Eye Field Present", "nvme.cmd.get_logpage.eom.odp.pefp",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_odp[2],
            { "Eye Data Field Present", "nvme.cmd.get_logpage.eom.odp.edfp",
               FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_odp[3],
            { "Reserved", "nvme.cmd.get_logpage.eom.odp.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_lns,
            { "Lanes Configured", "nvme.cmd.get_logpage.eom.lns",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_epl,
            { "Eyes Per Lane", "nvme.cmd.get_logpage.eom.epl",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_lspfc[0],
            { "Log Specific Parameter Field Copy", "nvme.cmd.get_logpage.eom.lspfc",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_lspfc[1],
            { "Log Specific Parameter Field Value", "nvme.cmd.get_logpage.eom.lspfc.lspfv",
               FT_UINT8, BASE_HEX, NULL, 0x7f, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_lspfc[2],
            { "Reserved", "nvme.cmd.get_logpage.eom.lspfc.rsvd",
               FT_BOOLEAN, 8, NULL, 0x80, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_linfo[0],
            { "Link Information", "nvme.cmd.get_logpage.eom.linfo",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_linfo[1],
            { "Measurement Link Speed", "nvme.cmd.get_logpage.eom.linfo.mls",
               FT_UINT8, BASE_HEX, NULL, 0x0f, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_linfo[2],
            { "Reserved", "nvme.cmd.get_logpage.eom.linfo.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.eom.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_lsic,
            { "Log Specific Identifier Copy", "nvme.cmd.get_logpage.eom.lsic",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_ds,
            { "Descriptor Size (bytes)", "nvme.cmd.get_logpage.eom.ds",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_nd,
            { "Number of Descriptors", "nvme.cmd.get_logpage.eom.nd",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_maxtb,
            { "Maximum Top Bottom", "nvme.cmd.get_logpage.eom.maxtb",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_maxlr,
            { "Maximum Left Right", "nvme.cmd.get_logpage.eom.maxlr",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_etgood,
            { "Estimated Time for Good Quality (seconds)", "nvme.cmd.get_logpage.eom.etgood",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_etbetter,
            { "Estimated Time for Better Quality (seconds)", "nvme.cmd.get_logpage.eom.etbetter",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_etbest,
            { "Estimated Time for Best Quality (seconds)", "nvme.cmd.get_logpage.eom.etbest",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.eom.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc,
            { "EOM Lane Descriptor", "nvme.cmd.get_logpage.eom.desc",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_rsvd0,
            { "Reserved", "nvme.cmd.get_logpage.eom.desc.rsvd0",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_mstat[0],
            { "Measurement Status", "nvme.cmd.get_logpage.eom.desc.mstat",
               FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_mstat[1],
            { "Measurement Successful", "nvme.cmd.get_logpage.eom.desc.mstat.mscs",
               FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_mstat[2],
            { "Reserved", "nvme.cmd.get_logpage.eom.desc.mstat.rsvd",
               FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_ln,
            { "Lane", "nvme.cmd.get_logpage.eom.desc.ln",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_eye,
            { "Eye", "nvme.cmd.get_logpage.eom.desc.eye",
               FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_top,
            { "Top", "nvme.cmd.get_logpage.eom.desc.top",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_btm,
            { "Bottom", "nvme.cmd.get_logpage.eom.desc.btm",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_lft,
            { "Left", "nvme.cmd.get_logpage.eom.desc.lft",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_rgt,
            { "Right", "nvme.cmd.get_logpage.eom.desc.rgt",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_nrows,
            { "Number of Rows", "nvme.cmd.get_logpage.eom.desc.nrows",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_ncols,
            { "Number of Columns", "nvme.cmd.get_logpage.eom.desc.ncols",
               FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_edlen,
            { "Eye Data Length (bytes)", "nvme.cmd.get_logpage.eom.desc.edlen",
               FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_rsvd1,
            { "Reserved", "nvme.cmd.get_logpage.eom.desc.rsvd1",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_pe,
            { "Printable Eye", "nvme.cmd.get_logpage.eom.desc.pe",
               FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_get_logpage_eom_desc_ed,
            { "Eye Data", "nvme.cmd.get_logpage.eom.desc.ed",
               FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
        },
        /* NVMe Response fields */
        { &hf_nvme_cqe_dword0,
            { "DWORD0", "nvme.cqe.dword0",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_dword0_sf_err,
            { "Set Features Error Specific Code", "nvme.cqe.dword0.set_features.err",
               FT_UINT32, BASE_HEX, VALS(nvme_cqe_sc_sf_err_dword0_tbl), 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_aev_dword0[0],
            { "DWORD0", "nvme.cqe.dword0.aev",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_aev_dword0[1],
            { "Asynchronous Event Type", "nvme.cqe.dword0.aev.aet",
               FT_UINT32, BASE_HEX, VALS(nvme_cqe_aev_aet_dword0_tbl), 0x7, NULL, HFILL}
        },
        { &hf_nvme_cqe_aev_dword0[2],
            { "Reserved", "nvme.cqe.dword0.aev.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0xf8, NULL, HFILL}
        },
        { &hf_nvme_cqe_aev_dword0[3],
            { "Asynchronous Event Information", "nvme.cqe.dword0.aev.aei",
               FT_UINT32, BASE_HEX, NULL, 0xff00, NULL, HFILL}
        },
        { &hf_nvme_cqe_aev_dword0[4],
            { "Log Page Identifier", "nvme.cqe.dword0.aev.lpi",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_logpage_lid), 0xff0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_aev_dword0[5],
            { "Reserved", "nvme.cqe.dword0.aev.rsvd1",
               FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
        },
        /* Set Feature Responses */
        { &hf_nvme_cqe_dword0_sf_nq[0],
            { "DWORD0: Set Feature Number of Queues Result", "nvme.cqe.dword0.set_features.nq",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_dword0_sf_nq[1],
            { "Number of IO Submission Queues Allocated", "nvme.cqe.dword0.set_features.nq.nsqa",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_dword0_sf_nq[2],
            { "Number of IO Completion Queues Allocated", "nvme.cqe.dword0.set_features.ncqa",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff0000, NULL, HFILL}
        },
        /* Get Feature Responses */
        { &hf_nvme_cqe_get_features_dword0_arb[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.arb",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_arb[1],
            { "Arbitration Burst", "nvme.cqe.dword0.get_features.arb.ab",
               FT_UINT32, BASE_HEX, NULL, 0x7, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_arb[2],
            { "Reserved", "nvme.cqe.dword0.get_features.arb.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x000000f8, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_arb[3],
            { "Low Priority Weight", "nvme.cqe.dword0.get_features.arb.lpw",
               FT_UINT32, BASE_HEX, NULL, 0xff00, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_arb[4],
            { "Medium Priority Weight", "nvme.cqe.dword0.get_features.arb.mpw",
               FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_arb[5],
            { "High Priority Weight", "nvme.cqe.dword0.get_features.arb.hpw",
               FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_pm[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.pm",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_pm[1],
            { "Power State", "nvme.cqe.dword0.get_features.pm.ps",
               FT_UINT32, BASE_HEX, NULL, 0x1f, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_pm[2],
            { "Work Hint", "nvme.cqe.dword0.get_features.pm.wh",
               FT_UINT32, BASE_HEX, NULL, 0xe0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_pm[3],
            { "Reserved", "nvme.cqe.dword0.get_features.pm.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffff00, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_lbart[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.lbart",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_lbart[1],
            { "Number of LBA Ranges (NUM)", "nvme.cqe.dword0.get_features.lbart.lbarn",
               FT_UINT32, BASE_HEX, NULL, 0x3f, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_lbart[2],
            { "Reserved", "nvme.cqe.dword0.get_features.lbart.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffffc0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_tt[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.tt",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_tt[1],
            { "Temperature Threshold", "nvme.cqe.dword0.get_features.tt.tmpth",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_tt[2],
            { "Threshold Temperature Select", "nvme.cqe.dword0.get_features.tt.tmpsel",
               FT_UINT32, BASE_HEX, VALS(sf_tmpsel_table), 0xf0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_tt[3],
            { "Threshold Type Select", "nvme.cqe.dword0.get_features.tt.thpsel",
               FT_UINT32, BASE_HEX, VALS(sf_thpsel_table), 0x300000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_tt[4],
            { "Temperature Threshold Hysteresis", "nvme.cqe.dword0.get_features.tt.tmpthh",
               FT_UINT32, BASE_HEX, NULL, 0x1c00000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_tt[5],
            { "Reserved", "nvme.cqe.dword0.get_features.tt.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfe000000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_erec[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.erec",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_erec[1],
            { "Time Limited Error Recovery (100 ms units)", "nvme.cqe.dword0.get_features.erec.tler",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_erec[2],
            { "Deallocated or Unwritten Logical Block Error Enable", "nvme.cqe.dword0.get_features.erec.dulbe",
               FT_BOOLEAN, 32, NULL, 0x10000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_erec[3],
            { "Reserved", "nvme.cqe.dword0.get_features.erec.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfe0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_vwce[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.vwce",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_vwce[1],
            { "Volatile Write Cache Enable", "nvme.cqe.dword0.get_features.vwce.wce",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_vwce[2],
            { "Reserved", "nvme.cqe.dword0.get_features.vwce.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nq[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.nq",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nq[1],
            { "Number of IO Submission Queues Allocated", "nvme.cqe.dword0.get_features.nq.nsqa",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nq[2],
            { "Number of IO Completion Queues Allocated", "nvme.cqe.dword0.get_features.nq.ncqa",
               FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_irqc[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.irqc",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_irqc[1],
            { "Aggregation Threshold", "nvme.cqe.dword0.get_features.irqc.thr",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_irqc[2],
            { "Aggregation Time (100 us units)", "nvme.cqe.dword0.get_features.irqc.time",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_irqv[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.irqv",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_irqv[1],
            { "IRQ Vector", "nvme.cqe.dword0.get_features.irqv.iv",
               FT_UINT32, BASE_HEX, NULL, 0x0000ffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_irqv[2],
            { "Coalescing Disable", "nvme.cqe.dword0.get_features.irqv.cd",
               FT_BOOLEAN, 32, NULL, 0x00010000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_irqv[3],
            { "Reserved", "nvme.cqe.dword0.get_features.irqv.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffe0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_wan[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.wan",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_wan[1],
            { "Disable Normal", "nvme.cqe.dword0.get_features.wan.dn",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_wan[2],
            { "Reserved", "nvme.cqe.dword0.get_features.wan.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.aec",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[1],
            { "SMART and Health Critical Warnings Bitmask", "nvme.cqe.dword0.get_features.aec.smart",
               FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[2],
            { "Namespace Attribute Notices", "nvme.cqe.dword0.get_features.aec.ns",
               FT_BOOLEAN, 32, NULL, 0x100, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[3],
            { "Firmware Activation Notices", "nvme.cqe.dword0.get_features.aec.fwa",
               FT_BOOLEAN, 32, NULL, 0x200, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[4],
            { "Telemetry Log Notices", "nvme.cqe.dword0.get_features.aec.tel",
               FT_BOOLEAN, 32, NULL, 0x400, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[5],
            { "ANA Change Notices", "nvme.cqe.dword0.get_features.aec.ana",
               FT_BOOLEAN, 32, NULL, 0x800, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[6],
            { "Predictable Latency Event Aggregate Log Change Notices", "nvme.cqe.dword0.get_features.aec.plat",
               FT_BOOLEAN, 32, NULL, 0x1000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[7],
            { "LBA Status Information Notices", "nvme.cqe.dword0.get_features.aec.lba",
               FT_BOOLEAN, 32, NULL, 0x2000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[8],
            { "Endurance Group Event Aggregate Log Change Notices", "nvme.cqe.dword0.get_features.aec.eg",
               FT_BOOLEAN, 32, NULL, 0x4000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[9],
            { "Reserved", "nvme.cqe.dword0.get_features.aec.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0x7fff8000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_aec[10],
            { "Discovery Log Page Change Notification", "nvme.cqe.dword0.get_features.aec.disc",
               FT_BOOLEAN, 32, NULL, 0x80000000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_apst[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.apst",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_apst[1],
            { "Autonomous Power State Transition Enable", "nvme.cqe.dword0.get_features.apst.apste",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_apst[2],
            { "Reserved", "nvme.cqe.dword0.get_features.apst.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_kat[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.kat",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_kat[1],
            { "Keep Alive Timeout", "nvme.cqe.dword0.get_features.kat.kato",
               FT_UINT32, BASE_DEC|BASE_UNIT_STRING, UNS(&units_milliseconds), 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_hctm[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.hctm",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_hctm[1],
            { "Thermal Management Temperature 2 (K)", "nvme.cqe.dword0.get_features.hctm.tmt2",
               FT_UINT32, BASE_HEX, NULL, 0x0000ffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_hctm[2],
            { "Thermal Management Temperature 1 (K)", "nvme.cqe.dword0.get_features.hctm.tmt1",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nops[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.nops",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nops[1],
            { "Non-Operational Power State Permissive Mode Enable", "nvme.cqe.dword0.get_features.nops.noppme",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nops[2],
            { "Reserved", "nvme.cqe.dword0.get_features.nops.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rrl[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.rrl",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rrl[1],
            { "Read Recovery Level", "nvme.cqe.dword0.get_features.rrl.rrl",
               FT_UINT32, BASE_HEX, NULL, 0xf, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rrl[2],
            { "Reserved", "nvme.cqe.dword0.get_features.rrl.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffff0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_plmc[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.plmc",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_plmc[1],
            { "Predictable Latency Enable", "nvme.cqe.dword0.get_features.plmc.ple",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_plmc[2],
            { "Reserved", "nvme.cqe.dword0.get_features.plmc.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_plmw[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.plmw",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_plmw[1],
            { "NVM Set Identifier", "nvme.cqe.dword0.get_features.plmw.nvmsetid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_plmw[2],
            { "Reserved", "nvme.cqe.dword0.get_features.plmw.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_lbasi[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.lbasi",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_lbasi[1],
            { "LBA Status Information Report Interval (100 ms)", "nvme.cqe.dword0.get_features.lbasi.lsiri",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_lbasi[2],
            { "LBA Status Information Poll Interval (100 ms)", "nvme.cqe.dword0.get_features.lbasi.lsipi",
               FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_san[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.san",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_san[1],
            { "No-Deallocate Response Mode", "nvme.cqe.dword0.get_features.san.nodrm",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_san[2],
            { "Reserved", "nvme.cqe.dword0.get_features.san.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_eg[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.eg",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_eg[1],
            { "Endurance Group Identifier", "nvme.cqe.dword0.get_features.eg.endgid",
               FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_eg[2],
            { "Endurance Group Critical Warnings Bitmask", "nvme.cqe.dword0.get_features.eg.egcw",
               FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_eg[3],
            { "Reserved", "nvme.cqe.dword0.get_features.eg.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_swp[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.swp",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_swp[1],
            { "Pre-boot Software Load Count", "nvme.cqe.dword0.get_features.swp.pbslc",
               FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_swp[2],
            { "Reserved", "nvme.cqe.dword0.get_features.swp.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xffffff00, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_hid[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.hid",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_hid[1],
            { "Enable Extended Host Identifier", "nvme.cqe.dword0.get_features.hid.exhid",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_hid[2],
            { "Reserved", "nvme.cqe.dword0.get_features.hid.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvn[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.rsrvn",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvn[1],
            { "Reserved", "nvme.cqe.dword0.get_features.rsrvn.rsvd0",
               FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvn[2],
            { "Mask Registration Preempted Notification" , "nvme.cqe.dword0.get_features.rsrvn.regpre",
               FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvn[3],
            { "Mask Reservation Released Notification", "nvme.cqe.dword0.get_features.rsrvn.resrel",
               FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvn[4],
            { "Mask Reservation Preempted Notification", "nvme.cqe.dword0.get_features.rsrvn.resrpe",
               FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvn[5],
            { "Reserved", "nvme.cqe.dword0.get_features.rsrvn.rsvd1",
               FT_UINT32, BASE_HEX, NULL, 0xfffff0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvp[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.rsrvp",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvp[1],
            { "Persist Through Power Loss", "nvme.cqe.dword0.get_features.rsrvp.ptpl",
               FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_rsrvp[2],
            { "Reserved", "nvme.cqe.dword0.get_features.rsrvp.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nswp[0],
            { "DWORD0", "nvme.cqe.dword0.get_features.nswp",
               FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nswp[1],
            { "Write Protection State (WPS)", "nvme.cqe.dword0.get_features.nswp.wps",
               FT_UINT32, BASE_HEX, VALS(sf_wps), 0x7, NULL, HFILL}
        },
        { &hf_nvme_cqe_get_features_dword0_nswp[2],
            { "Reserved", "nvme.cqe.dword0.get_features.nswp.rsvd",
               FT_UINT32, BASE_HEX, NULL, 0xfffffff8, NULL, HFILL}
        },
        /* Generic Response Fields */
        { &hf_nvme_cqe_dword1,
            { "DWORD1", "nvme.cqe.dword1",
               FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_sqhd,
            { "SQ Head Pointer", "nvme.cqe.sqhd",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_sqid,
            { "SQ Identifier", "nvme.cqe.sqid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_cid,
            { "Command Identifier", "nvme.cqe.cid",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_status[0],
            { "Status Field", "nvme.cqe.status",
               FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
        },
        { &hf_nvme_cqe_status[1],
            { "Phase Tag", "nvme.cqe.status.p",
               FT_UINT16, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_status_rsvd,
            { "Reserved", "nvme.cqe.status.rsvd",
               FT_UINT16, BASE_HEX, NULL, 0x1, NULL, HFILL}
        },
        { &hf_nvme_cqe_status[2],
            { "Status Code", "nvme.cqe.status.sc",
               FT_UINT16, BASE_HEX, NULL, 0x1fe, NULL, HFILL}
        },
        { &hf_nvme_cqe_status[3],
            { "Status Code Type", "nvme.cqe.status.sct",
               FT_UINT16, BASE_HEX, VALS(nvme_cqe_sct_tbl), 0xE00, NULL, HFILL}
        },
        { &hf_nvme_cqe_status[4],
            { "Command Retry Delay", "nvme.cqe.status.crd",
               FT_UINT16, BASE_HEX, NULL, 0x3000, NULL, HFILL}
        },
        { &hf_nvme_cqe_status[5],
            { "More Information in Log Page", "nvme.cqe.status.m",
               FT_BOOLEAN, 16, NULL, 0x4000, NULL, HFILL}
        },
        { &hf_nvme_cqe_status[6],
            { "Do not Retry", "nvme.cqe.status.dnr",
               FT_BOOLEAN, 16, NULL, 0x8000, NULL, HFILL}
        },
        { &hf_nvme_cmd_pkt,
            { "Cmd in", "nvme.cmd_pkt",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "The Cmd for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_req,
            { "DATA Transfer Request", "nvme.data_req",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer request for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[0],
            { "DATA Transfer 0", "nvme.data.tr0",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 0 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[1],
            { "DATA Transfer 1", "nvme.data_tr1",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 1 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[2],
            { "DATA Transfer 2", "nvme.data_tr2",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 2 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[3],
            { "DATA Transfer 3", "nvme.data_tr3",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 3 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[4],
            { "DATA Transfer 4", "nvme.data_tr4",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 4 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[5],
            { "DATA Transfer 5", "nvme.data_tr5",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 5 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[6],
            { "DATA Transfer 6", "nvme.data_tr6",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 6 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[7],
            { "DATA Transfer 7", "nvme.data_tr7",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 7 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[8],
            { "DATA Transfer 8", "nvme.data_tr8",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 8 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[9],
            { "DATA Transfer 9", "nvme.data_tr9",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 9 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[10],
            { "DATA Transfer 10", "nvme.data_tr10",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 10 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[11],
            { "DATA Transfer 11", "nvme.data_tr11",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 11 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[12],
            { "DATA Transfer 12", "nvme.data_tr12",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 12 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[13],
            { "DATA Transfer 13", "nvme.data_tr13",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 13 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[14],
            { "DATA Transfer 14", "nvme.data_tr14",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 14 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_data_tr[15],
            { "DATA Transfer 15", "nvme.data_tr15",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "DATA transfer 15 for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_cqe_pkt,
            { "Cqe in", "nvme.cqe_pkt",
              FT_FRAMENUM, BASE_NONE, NULL, 0,
              "The Cqe for this transaction is in this frame", HFILL }
        },
        { &hf_nvme_cmd_latency,
            { "Cmd Latency", "nvme.cmd_latency",
              FT_DOUBLE, BASE_NONE, NULL, 0x0,
              "The time between the command and completion, in usec", HFILL }
        },
        { &hf_nvme_gen_data,
            { "Nvme Data", "nvme.data",
              FT_BYTES, BASE_NONE, NULL, 0, NULL, HFILL}
        },
    };
    static int *ett[] = {
        &ett_data,
    };

    static ei_register_info ei[] = {
        { &ei_nvme_cqe_status_error,
            { "nvme.cqe.status.error", PI_RESPONSE_CODE, PI_NOTE,
              "Command completed with an error status", EXPFILL }
        },
        { &ei_nvme_lbaf_count_invalid,
            { "nvme.identify.ns.lbaf.count_invalid", PI_MALFORMED, PI_WARN,
              "NLBAF and NULBAF describe more LBA Formats than the LBA Format list holds", EXPFILL }
        },
        { &ei_nvme_data_len_exceeds_frame,
            { "nvme.data.len_exceeds_frame", PI_MALFORMED, PI_WARN,
              "Transport declared more data than the frame carries", EXPFILL }
        },
        { &ei_nvme_logpage_window_misaligned,
            { "nvme.cmd.get_logpage.window_misaligned", PI_MALFORMED, PI_WARN,
              "Log page window does not start on a record boundary", EXPFILL }
        },
        { &ei_nvme_eom_desc_truncated,
            { "nvme.cmd.get_logpage.eom.desc_truncated", PI_MALFORMED, PI_WARN,
              "Number of Descriptors exceeds the descriptors the response holds", EXPFILL }
        },
    };

    expert_module_t *expert_nvme;

    proto_nvme = proto_register_protocol("NVM Express", "nvme", "nvme");

    proto_register_field_array(proto_nvme, hf, array_length(hf));
    proto_register_subtree_array(ett, array_length(ett));

    expert_nvme = expert_register_protocol(proto_nvme);
    expert_register_field_array(expert_nvme, ei, array_length(ei));

    /* Security Send/Receive payload dissectors register here, keyed on the
     * Security Protocol (SECP) value; struct nvme_security_info is passed
     * as the data pointer. */
    nvme_security_secp_table = register_dissector_table("nvme.security.secp",
            "NVMe Security Protocol (SECP)", proto_nvme, FT_UINT8, BASE_HEX);
}

/*
 * Editor modelines  -  https://www.wireshark.org/tools/modelines.html
 *
 * Local variables:
 * c-basic-offset: 4
 * tab-width: 8
 * indent-tabs-mode: nil
 * End:
 *
 * vi: set shiftwidth=4 tabstop=8 expandtab:
 * :indentSize=4:tabSize=8:noTabs=true:
 */

Coverage Report

Created: 2026-11-12 07:01