_ZN7llvm_ks7APFloat6getInfERKNS_12fltSemanticsEb: 225| 678| static APFloat getInf(const fltSemantics &Sem, bool Negative = false) { 226| 678| APFloat Val(Sem, uninitialized); 227| 678| Val.makeInf(Negative); 228| 678| return Val; 229| 678| } _ZN7llvm_ks7APFloat6getNaNERKNS_12fltSemanticsEbj: 237| 240| unsigned type = 0) { 238| 240| if (type) { ------------------ | Branch (238:9): [True: 240, False: 0] ------------------ 239| 240| APInt fill(64, type); 240| 240| return getQNaN(Sem, Negative, &fill); 241| 240| } else { 242| 0| return getQNaN(Sem, Negative, nullptr); 243| 0| } 244| 240| } _ZN7llvm_ks7APFloat7getQNaNERKNS_12fltSemanticsEbPKNS_5APIntE: 248| 240| const APInt *payload = nullptr) { 249| 240| return makeNaN(Sem, false, Negative, payload); 250| 240| } _ZNK7llvm_ks7APFloat12needsCleanupEv: 208| 10.9k| bool needsCleanup() const { return partCount() > 1; } _ZN7llvm_ks7APFloat7getZeroERKNS_12fltSemanticsEb: 216| 2.29k| static APFloat getZero(const fltSemantics &Sem, bool Negative = false) { 217| 2.29k| APFloat Val(Sem, uninitialized); 218| 2.29k| Val.makeZero(Negative); 219| 2.29k| return Val; 220| 2.29k| } _ZNK7llvm_ks7APFloat8isFiniteEv: 414| 13.6k| bool isFinite() const { return !isNaN() && !isInfinity(); } ------------------ | Branch (414:34): [True: 13.1k, False: 539] | Branch (414:46): [True: 12.1k, False: 960] ------------------ _ZNK7llvm_ks7APFloat6isZeroEv: 417| 12.1k| bool isZero() const { return category == fcZero; } _ZNK7llvm_ks7APFloat10isInfinityEv: 424| 13.1k| bool isInfinity() const { return category == fcInfinity; } _ZNK7llvm_ks7APFloat5isNaNEv: 427| 13.6k| bool isNaN() const { return category == fcNaN; } _ZNK7llvm_ks7APFloat15isFiniteNonZeroEv: 440| 13.6k| bool isFiniteNonZero() const { return isFinite() && !isZero(); } ------------------ | Branch (440:41): [True: 12.1k, False: 1.49k] | Branch (440:55): [True: 11.7k, False: 374] ------------------ _ZN7llvm_ks5APIntC2EPmj: 98| 65.0k| APInt(uint64_t *val, unsigned bits) : BitWidth(bits), pVal(val) {} _ZNK7llvm_ks5APInt12isSingleWordEv: 103| 1.34M| bool isSingleWord() const { return BitWidth <= APINT_BITS_PER_WORD; } _ZN7llvm_ks5APInt15clearUnusedBitsEv: 136| 338k| APInt &clearUnusedBits() { 137| | // Compute how many bits are used in the final word 138| 338k| unsigned wordBits = BitWidth % APINT_BITS_PER_WORD; 139| 338k| if (wordBits == 0) ------------------ | Branch (139:9): [True: 306k, False: 32.1k] ------------------ 140| | // If all bits are used, we want to leave the value alone. This also 141| | // avoids the undefined behavior of >> when the shift is the same size as 142| | // the word size (64). 143| 306k| return *this; 144| | 145| | // Mask out the high bits. 146| 32.1k| uint64_t mask = ~uint64_t(0ULL) >> (APINT_BITS_PER_WORD - wordBits); 147| 32.1k| if (isSingleWord()) ------------------ | Branch (147:9): [True: 2.21k, False: 29.9k] ------------------ 148| 2.21k| VAL &= mask; 149| 29.9k| else 150| 29.9k| pVal[getNumWords() - 1] &= mask; 151| 32.1k| return *this; 152| 338k| } _ZN7llvm_ks5APIntC2Ejmb: 237| 261k| : BitWidth(numBits), VAL(0) { 238| 261k| assert(BitWidth && "bitwidth too small"); ------------------ | Branch (238:5): [True: 261k, False: 0] | Branch (238:5): [True: 261k, Folded] | Branch (238:5): [True: 261k, False: 0] ------------------ 239| 261k| if (isSingleWord()) ------------------ | Branch (239:9): [True: 249k, False: 12.0k] ------------------ 240| 249k| VAL = val; 241| 12.0k| else 242| 12.0k| initSlowCase(numBits, val, isSigned); 243| 261k| clearUnusedBits(); 244| 261k| } _ZN7llvm_ks5APIntC2ERKS0_: 279| 100k| APInt(const APInt &that) : BitWidth(that.BitWidth), VAL(0) { 280| 100k| if (isSingleWord()) ------------------ | Branch (280:9): [True: 78.6k, False: 22.1k] ------------------ 281| 78.6k| VAL = that.VAL; 282| 22.1k| else 283| 22.1k| initSlowCase(that); 284| 100k| } _ZN7llvm_ks5APIntC2EOS0_: 287| 254k| APInt(APInt &&that) : BitWidth(that.BitWidth), VAL(that.VAL) { 288| 254k| that.BitWidth = 0; 289| 254k| } _ZN7llvm_ks5APIntD2Ev: 292| 702k| ~APInt() { 293| 702k| if (needsCleanup()) ------------------ | Branch (293:9): [True: 32.6k, False: 669k] ------------------ 294| 32.6k| delete[] pVal; 295| 702k| } _ZN7llvm_ks5APIntC2Ev: 302| 21.5k| explicit APInt() : BitWidth(1), VAL(0) {} _ZNK7llvm_ks5APInt12needsCleanupEv: 305| 702k| bool needsCleanup() const { return !isSingleWord(); } _ZNK7llvm_ks5APInt6isIntNEj: 373| 12.4k| bool isIntN(unsigned N) const { 374| 12.4k| assert(N && "N == 0 ???"); ------------------ | Branch (374:5): [True: 12.4k, False: 0] | Branch (374:5): [True: 12.4k, Folded] | Branch (374:5): [True: 12.4k, False: 0] ------------------ 375| 12.4k| return getActiveBits() <= N; 376| 12.4k| } _ZNK7llvm_ks5APInt15getLimitedValueEm: 405| 2.21k| uint64_t getLimitedValue(uint64_t Limit = ~0ULL) const { 406| 2.21k| return (getActiveBits() > 64 || getZExtValue() > Limit) ? Limit ------------------ | Branch (406:13): [True: 0, False: 2.21k] | Branch (406:37): [True: 0, False: 2.21k] ------------------ 407| 2.21k| : getZExtValue(); 408| 2.21k| } _ZNK7llvm_ks5APInt10getRawDataEv: 574| 324| const uint64_t *getRawData() const { 575| 324| if (isSingleWord()) ------------------ | Branch (575:9): [True: 240, False: 84] ------------------ 576| 240| return &VAL; 577| 84| return &pVal[0]; 578| 324| } _ZN7llvm_ks5APIntaSERKS0_: 652| 2.33k| APInt &operator=(const APInt &RHS) { 653| | // If the bitwidths are the same, we can avoid mucking with memory 654| 2.33k| if (isSingleWord() && RHS.isSingleWord()) { ------------------ | Branch (654:9): [True: 2.16k, False: 170] | Branch (654:27): [True: 2.05k, False: 109] ------------------ 655| 2.05k| VAL = RHS.VAL; 656| 2.05k| BitWidth = RHS.BitWidth; 657| 2.05k| return clearUnusedBits(); 658| 2.05k| } 659| | 660| 279| return AssignSlowCase(RHS); 661| 2.33k| } _ZN7llvm_ks5APIntaSEOS0_: 664| 66.5k| APInt &operator=(APInt &&that) { 665| 66.5k| if (!isSingleWord()) { ------------------ | Branch (665:9): [True: 66.5k, False: 0] ------------------ 666| | // The MSVC STL shipped in 2013 requires that self move assignment be a 667| | // no-op. Otherwise algorithms like stable_sort will produce answers 668| | // where half of the output is left in a moved-from state. 669| 66.5k| if (this == &that) ------------------ | Branch (669:11): [True: 0, False: 66.5k] ------------------ 670| 0| return *this; 671| 66.5k| delete[] pVal; 672| 66.5k| } 673| | 674| | // Use memcpy so that type based alias analysis sees both VAL and pVal 675| | // as modified. 676| 66.5k| memcpy(&VAL, &that.VAL, sizeof(uint64_t)); 677| | 678| | // If 'this == &that', avoid zeroing our own bitwidth by storing to 'that' 679| | // first. 680| 66.5k| unsigned ThatBitWidth = that.BitWidth; 681| 66.5k| that.BitWidth = 0; 682| 66.5k| BitWidth = ThatBitWidth; 683| | 684| 66.5k| return *this; 685| 66.5k| } _ZN7llvm_ks5APIntoREm: 717| 64.5k| APInt &operator|=(uint64_t RHS) { 718| 64.5k| if (isSingleWord()) { ------------------ | Branch (718:9): [True: 0, False: 64.5k] ------------------ 719| 0| VAL |= RHS; 720| 0| clearUnusedBits(); 721| 64.5k| } else { 722| 64.5k| pVal[0] |= RHS; 723| 64.5k| } 724| 64.5k| return *this; 725| 64.5k| } _ZN7llvm_ks5APIntlSEj: 761| 64.5k| APInt &operator<<=(unsigned shiftAmt) { 762| 64.5k| *this = shl(shiftAmt); 763| 64.5k| return *this; 764| 64.5k| } _ZNK7llvm_ks5APInt3shlEj: 869| 64.6k| APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(unsigned shiftAmt) const { 870| 64.6k| assert(shiftAmt <= BitWidth && "Invalid shift amount"); ------------------ | Branch (870:5): [True: 64.6k, False: 0] | Branch (870:5): [True: 64.6k, Folded] | Branch (870:5): [True: 64.6k, False: 0] ------------------ 871| 64.6k| if (isSingleWord()) { ------------------ | Branch (871:9): [True: 0, False: 64.6k] ------------------ 872| 0| if (shiftAmt >= BitWidth) ------------------ | Branch (872:11): [True: 0, False: 0] ------------------ 873| 0| return APInt(BitWidth, 0); // avoid undefined shift results 874| 0| return APInt(BitWidth, VAL << shiftAmt); 875| 0| } 876| 64.6k| return shlSlowCase(shiftAmt); 877| 64.6k| } _ZNK7llvm_ks5APInt11getBitWidthEv: 1274| 22.7k| unsigned getBitWidth() const { return BitWidth; } _ZNK7llvm_ks5APInt11getNumWordsEv: 1281| 5.75M| unsigned getNumWords() const { return getNumWords(BitWidth); } _ZN7llvm_ks5APInt11getNumWordsEj: 1289| 5.75M| static unsigned getNumWords(unsigned BitWidth) { 1290| 5.75M| return ((uint64_t)BitWidth + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD; 1291| 5.75M| } _ZNK7llvm_ks5APInt13getActiveBitsEv: 1298| 21.2k| unsigned getActiveBits() const { return BitWidth - countLeadingZeros(); } _ZNK7llvm_ks5APInt12getZExtValueEv: 1328| 14.3k| uint64_t getZExtValue() const { 1329| 14.3k| if (isSingleWord()) ------------------ | Branch (1329:9): [True: 7.80k, False: 6.51k] ------------------ 1330| 7.80k| return VAL; 1331| 14.3k| assert(getActiveBits() <= 64 && "Too many bits for uint64_t"); ------------------ | Branch (1331:5): [True: 6.51k, False: 0] | Branch (1331:5): [True: 6.51k, Folded] | Branch (1331:5): [True: 6.51k, False: 0] ------------------ 1332| 6.51k| return pVal[0]; 1333| 6.51k| } _ZNK7llvm_ks5APInt17countLeadingZerosEv: 1362| 21.2k| unsigned countLeadingZeros() const { 1363| 21.2k| if (isSingleWord()) { ------------------ | Branch (1363:9): [True: 4.24k, False: 16.9k] ------------------ 1364| 4.24k| unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth; 1365| 4.24k| return llvm_ks::countLeadingZeros(VAL) - unusedBits; 1366| 4.24k| } 1367| 16.9k| return countLeadingZerosSlowCase(); 1368| 21.2k| } _ZN7llvm_ks8APIntOps4lshrERKNS_5APIntEj: 1841| 296|inline APInt lshr(const APInt &LHS, unsigned shiftAmt) { 1842| 296| return LHS.lshr(shiftAmt); 1843| 296|} _ZN7llvm_ks8APIntOps3shlERKNS_5APIntEj: 1848| 148|inline APInt shl(const APInt &LHS, unsigned shiftAmt) { 1849| 148| return LHS.shl(shiftAmt); 1850| 148|} _ZNK7llvm_ks8ArrayRefINS_18SubtargetFeatureKVEE5beginEv: 123| 61.1k| iterator begin() const { return Data; } _ZNK7llvm_ks8ArrayRefINS_18SubtargetFeatureKVEE3endEv: 124| 65.8k| iterator end() const { return Data + Length; } _ZN7llvm_ks8ArrayRefINS_7SMRangeEEC2ENS_8NoneTypeE: 54| 2.17k| /*implicit*/ ArrayRef(NoneType) : Data(nullptr), Length(0) {} _ZN7llvm_ks8ArrayRefINS_7SMFixItEEC2ENS_8NoneTypeE: 54| 2.47k| /*implicit*/ ArrayRef(NoneType) : Data(nullptr), Length(0) {} _ZN7llvm_ks8ArrayRefINSt3__14pairIjjEEEC2INS1_9allocatorIS3_EEEERKNS1_6vectorIS3_T_EE: 79| 304| : Data(Vec.data()), Length(Vec.size()) {} _ZN7llvm_ks15MutableArrayRefINS_8AsmTokenEEC2ERS1_: 233| 321| /*implicit*/ MutableArrayRef(T &OneElt) : ArrayRef(OneElt) {} _ZN7llvm_ks8ArrayRefINS_8AsmTokenEEC2ERKS1_: 58| 321| : Data(&OneElt), Length(1) {} AsmParser.cpp:_ZNK7llvm_ks8ArrayRefIN12_GLOBAL__N_119MCAsmMacroParameterEE4sizeEv: 135| 441| size_t size() const { return Length; } AsmParser.cpp:_ZNK7llvm_ks8ArrayRefIN12_GLOBAL__N_119MCAsmMacroParameterEE4backEv: 144| 36| const T &back() const { 145| 36| assert(!empty()); ------------------ | Branch (145:7): [True: 36, False: 0] ------------------ 146| 36| return Data[Length-1]; 147| 36| } AsmParser.cpp:_ZNK7llvm_ks8ArrayRefIN12_GLOBAL__N_119MCAsmMacroParameterEE5emptyEv: 130| 36| bool empty() const { return Length == 0; } _ZNK7llvm_ks8ArrayRefINSt3__16vectorINS_8AsmTokenENS1_9allocatorIS3_EEEEE4sizeEv: 135| 36| size_t size() const { return Length; } AsmParser.cpp:_ZNK7llvm_ks8ArrayRefIN12_GLOBAL__N_119MCAsmMacroParameterEEixEm: 185| 3.87k| const T &operator[](size_t Index) const { 186| 3.87k| assert(Index < Length && "Invalid index!"); ------------------ | Branch (186:7): [True: 3.87k, False: 0] | Branch (186:7): [True: 3.87k, Folded] | Branch (186:7): [True: 3.87k, False: 0] ------------------ 187| 3.87k| return Data[Index]; 188| 3.87k| } AsmParser.cpp:_ZN7llvm_ks8ArrayRefIN12_GLOBAL__N_119MCAsmMacroParameterEEC2INSt3__19allocatorIS2_EEEERKNS5_6vectorIS2_T_EE: 79| 35| : Data(Vec.data()), Length(Vec.size()) {} _ZN7llvm_ks8ArrayRefINSt3__16vectorINS_8AsmTokenENS1_9allocatorIS3_EEEEEC2INS4_IS6_EEEERKNS2_IS6_T_EE: 79| 20| : Data(Vec.data()), Length(Vec.size()) {} AsmParser.cpp:_ZN7llvm_ks8ArrayRefIN12_GLOBAL__N_119MCAsmMacroParameterEEC2ENS_8NoneTypeE: 54| 390| /*implicit*/ ArrayRef(NoneType) : Data(nullptr), Length(0) {} _ZN7llvm_ks8ArrayRefINSt3__16vectorINS_8AsmTokenENS1_9allocatorIS3_EEEEEC2ENS_8NoneTypeE: 54| 390| /*implicit*/ ArrayRef(NoneType) : Data(nullptr), Length(0) {} AsmParser.cpp:_ZN7llvm_ks8ArrayRefIN12_GLOBAL__N_119MCAsmMacroParameterEEC2ERKS2_: 58| 16| : Data(&OneElt), Length(1) {} _ZN7llvm_ks8ArrayRefINSt3__16vectorINS_8AsmTokenENS1_9allocatorIS3_EEEEEC2ERKS6_: 58| 16| : Data(&OneElt), Length(1) {} _ZNK7llvm_ks8ArrayRefINS_7SMFixItEE5emptyEv: 130| 1.50k| bool empty() const { return Length == 0; } _ZN7llvm_ks8ArrayRefINS_7SMFixItEEC2IvEERKNS_25SmallVectorTemplateCommonIS1_T_EE: 73| 1.50k| : Data(Vec.data()), Length(Vec.size()) { 74| 1.50k| } _ZNK7llvm_ks8ArrayRefINS_7SMRangeEE4sizeEv: 135| 2.17k| size_t size() const { return Length; } _ZN7llvm_ks8ArrayRefINSt3__14pairIjjEEEC2IvEERKNS_25SmallVectorTemplateCommonIS3_T_EE: 73| 2.17k| : Data(Vec.data()), Length(Vec.size()) { 74| 2.17k| } _ZNK7llvm_ks8ArrayRefINSt3__14pairIjjEEE3vecEv: 193| 2.47k| std::vector vec() const { 194| 2.47k| return std::vector(Data, Data+Length); 195| 2.47k| } _ZNK7llvm_ks8ArrayRefINS_7SMFixItEE5beginEv: 123| 2.47k| iterator begin() const { return Data; } _ZNK7llvm_ks8ArrayRefINS_7SMFixItEE3endEv: 124| 2.47k| iterator end() const { return Data + Length; } _ZN7llvm_ks12makeArrayRefIcEENS_8ArrayRefIT_EEPKS2_m: 313| 1.50k| ArrayRef makeArrayRef(const T *data, size_t length) { 314| 1.50k| return ArrayRef(data, length); 315| 1.50k| } _ZN7llvm_ks8ArrayRefIcEC2EPKcm: 62| 1.50k| : Data(data), Length(length) {} _ZNK7llvm_ks8ArrayRefIcE4sizeEv: 135| 704| size_t size() const { return Length; } _ZN7llvm_ks8ArrayRefINS_18SubtargetFeatureKVEEC2ILm104EEERAT__KS1_: 84| 860| : Data(Arr), Length(N) {} _ZN7llvm_ks8ArrayRefINS_18SubtargetFeatureKVEEC2ILm65EEERAT__KS1_: 84| 860| : Data(Arr), Length(N) {} _ZN7llvm_ks8ArrayRefINS_7MCFixupEEC2Ev: 51| 1.02k| /*implicit*/ ArrayRef() : Data(nullptr), Length(0) {} _ZN7llvm_ks15MutableArrayRefIcEC2Ev: 227| 1.02k| /*implicit*/ MutableArrayRef() : ArrayRef() {} _ZN7llvm_ks8ArrayRefIcEC2Ev: 51| 1.02k| /*implicit*/ ArrayRef() : Data(nullptr), Length(0) {} _ZN7llvm_ks8ArrayRefINS_7MCFixupEEC2IvEERKNS_25SmallVectorTemplateCommonIS1_T_EE: 73| 1.02k| : Data(Vec.data()), Length(Vec.size()) { 74| 1.02k| } _ZN7llvm_ks15MutableArrayRefIcEC2ERNS_15SmallVectorImplIcEE: 244| 1.02k| : ArrayRef(Vec) {} _ZN7llvm_ks8ArrayRefIcEC2IvEERKNS_25SmallVectorTemplateCommonIcT_EE: 73| 1.02k| : Data(Vec.data()), Length(Vec.size()) { 74| 1.02k| } _ZNK7llvm_ks8ArrayRefINS_7MCFixupEE5beginEv: 123| 1.02k| iterator begin() const { return Data; } _ZNK7llvm_ks8ArrayRefINS_7MCFixupEE3endEv: 124| 1.02k| iterator end() const { return Data + Length; } _ZNK7llvm_ks15MutableArrayRefIcE4dataEv: 255| 704| T *data() const { return const_cast(ArrayRef::data()); } _ZNK7llvm_ks8ArrayRefIcE4dataEv: 132| 704| const T *data() const { return Data; } _ZNK7llvm_ks8ArrayRefINS_8AsmTokenEE4sizeEv: 135| 963| size_t size() const { return Length; } _ZNK7llvm_ks15MutableArrayRefINS_8AsmTokenEEixEm: 296| 321| T &operator[](size_t Index) const { 297| 321| assert(Index < this->size() && "Invalid index!"); ------------------ | Branch (297:7): [True: 321, False: 0] | Branch (297:7): [True: 321, Folded] | Branch (297:7): [True: 321, False: 0] ------------------ 298| 321| return data()[Index]; 299| 321| } _ZNK7llvm_ks15MutableArrayRefINS_8AsmTokenEE4dataEv: 255| 321| T *data() const { return const_cast(ArrayRef::data()); } _ZNK7llvm_ks8ArrayRefINS_8AsmTokenEE4dataEv: 132| 321| const T *data() const { return Data; } _ZNK7llvm_ks8ArrayRefINS_18SubtargetFeatureKVEE5emptyEv: 130| 6.38k| bool empty() const { return Length == 0; } _ZN7llvm_ks8DenseMapIjiNS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjiEEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIjiNS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjiEEEEjiS3_S6_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 430, False: 0] ------------------ 266| 430| return; 267| | 268| 0| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 0| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 0, False: 0] ------------------ 270| 0| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 0, False: 0] ------------------ 271| 0| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 0, False: 0] ------------------ 272| 0| P->getSecond().~ValueT(); 273| 0| P->getFirst().~KeyT(); 274| 0| } 275| 0| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIjiNS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjiEEEEjiS3_S6_E13getNumBucketsEv: 381| 430| unsigned getNumBuckets() const { 382| 430| return static_cast(this)->getNumBuckets(); 383| 430| } _ZNK7llvm_ks8DenseMapIjiNS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjiEEE13getNumBucketsEv: 674| 430| unsigned getNumBuckets() const { 675| 430| return NumBuckets; 676| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E6insertERKNSt3__14pairIS3_jEE: 169| 516| std::pair insert(const std::pair &KV) { 170| 516| BucketT *TheBucket; 171| 516| if (LookupBucketFor(KV.first, TheBucket)) ------------------ | Branch (171:9): [True: 510, False: 6] ------------------ 172| 510| return std::make_pair(iterator(TheBucket, getBucketsEnd(), *this, true), 173| 510| false); // Already in map. 174| | 175| | // Otherwise, insert the new element. 176| 6| TheBucket = InsertIntoBucket(KV.first, KV.second, TheBucket); 177| 6| return std::make_pair(iterator(TheBucket, getBucketsEnd(), *this, true), 178| 6| true); 179| 516| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E15LookupBucketForIS3_EEbRKT_RPS8_: 519| 522| bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) { 520| 522| const BucketT *ConstFoundBucket; 521| 522| bool Result = const_cast(this) 522| 522| ->LookupBucketFor(Val, ConstFoundBucket); 523| 522| FoundBucket = const_cast(ConstFoundBucket); 524| 522| return Result; 525| 522| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E15LookupBucketForIS3_EEbRKT_RPKS8_: 469| 522| const BucketT *&FoundBucket) const { 470| 522| const BucketT *BucketsPtr = getBuckets(); 471| 522| const unsigned NumBuckets = getNumBuckets(); 472| | 473| 522| if (NumBuckets == 0) { ------------------ | Branch (473:9): [True: 6, False: 516] ------------------ 474| 6| FoundBucket = nullptr; 475| 6| return false; 476| 6| } 477| | 478| | // FoundTombstone - Keep track of whether we find a tombstone while probing. 479| 516| const BucketT *FoundTombstone = nullptr; 480| 516| const KeyT EmptyKey = getEmptyKey(); 481| 516| const KeyT TombstoneKey = getTombstoneKey(); 482| 516| assert(!KeyInfoT::isEqual(Val, EmptyKey) && ------------------ | Branch (482:5): [True: 516, False: 0] | Branch (482:5): [True: 516, False: 0] | Branch (482:5): [True: 516, Folded] | Branch (482:5): [True: 516, False: 0] ------------------ 483| 516| !KeyInfoT::isEqual(Val, TombstoneKey) && 484| 516| "Empty/Tombstone value shouldn't be inserted into map!"); 485| | 486| 516| unsigned BucketNo = getHashValue(Val) & (NumBuckets-1); 487| 516| unsigned ProbeAmt = 1; 488| 516| while (1) { ------------------ | Branch (488:12): [True: 516, Folded] ------------------ 489| 516| const BucketT *ThisBucket = BucketsPtr + BucketNo; 490| | // Found Val's bucket? If so, return it. 491| 516| if (LLVM_LIKELY(KeyInfoT::isEqual(Val, ThisBucket->getFirst()))) { ------------------ | | 171| 516|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 510, False: 6] | | ------------------ ------------------ 492| 510| FoundBucket = ThisBucket; 493| 510| return true; 494| 510| } 495| | 496| | // If we found an empty bucket, the key doesn't exist in the set. 497| | // Insert it and return the default value. 498| 6| if (LLVM_LIKELY(KeyInfoT::isEqual(ThisBucket->getFirst(), EmptyKey))) { ------------------ | | 171| 6|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 6, False: 0] | | ------------------ ------------------ 499| | // If we've already seen a tombstone while probing, fill it in instead 500| | // of the empty bucket we eventually probed to. 501| 6| FoundBucket = FoundTombstone ? FoundTombstone : ThisBucket; ------------------ | Branch (501:23): [True: 0, False: 6] ------------------ 502| 6| return false; 503| 6| } 504| | 505| | // If this is a tombstone, remember it. If Val ends up not in the map, we 506| | // prefer to return it than something that would require more probing. 507| 0| if (KeyInfoT::isEqual(ThisBucket->getFirst(), TombstoneKey) && ------------------ | Branch (507:11): [True: 0, False: 0] ------------------ 508| 0| !FoundTombstone) ------------------ | Branch (508:11): [True: 0, False: 0] ------------------ 509| 0| FoundTombstone = ThisBucket; // Remember the first tombstone found. 510| | 511| | // Otherwise, it's a hash collision or a tombstone, continue quadratic 512| | // probing. 513| 0| BucketNo += ProbeAmt++; 514| 0| BucketNo &= (NumBuckets-1); 515| 0| } 516| 516| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E10getBucketsEv: 375| 522| const BucketT *getBuckets() const { 376| 522| return static_cast(this)->getBuckets(); 377| 522| } _ZNK7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEE10getBucketsEv: 670| 1.06k| BucketT *getBuckets() const { 671| 1.06k| return Buckets; 672| 1.06k| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E13getNumBucketsEv: 381| 1.50k| unsigned getNumBuckets() const { 382| 1.50k| return static_cast(this)->getNumBuckets(); 383| 1.50k| } _ZNK7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEE13getNumBucketsEv: 674| 1.50k| unsigned getNumBuckets() const { 675| 1.50k| return NumBuckets; 676| 1.50k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E11getEmptyKeyEv: 343| 534| static const KeyT getEmptyKey() { 344| 534| return KeyInfoT::getEmptyKey(); 345| 534| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E15getTombstoneKeyEv: 346| 522| static const KeyT getTombstoneKey() { 347| 522| return KeyInfoT::getTombstoneKey(); 348| 522| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E12getHashValueERKS3_: 336| 516| static unsigned getHashValue(const KeyT &Val) { 337| 516| return KeyInfoT::getHashValue(Val); 338| 516| } _ZNK7llvm_ks6detail12DenseMapPairIPNS_9MCSectionEjE8getFirstEv: 41| 522| const KeyT &getFirst() const { return std::pair::first; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E13getBucketsEndEv: 384| 528| BucketT *getBucketsEnd() { 385| 528| return getBuckets() + getNumBuckets(); 386| 528| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E10getBucketsEv: 378| 540| BucketT *getBuckets() { 379| 540| return static_cast(this)->getBuckets(); 380| 540| } _ZN7llvm_ks6detail12DenseMapPairIPNS_9MCSectionEjE8getFirstEv: 40| 1.17k| KeyT &getFirst() { return std::pair::first; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E16InsertIntoBucketERKS3_RKjPS8_: 401| 6| BucketT *TheBucket) { 402| 6| TheBucket = InsertIntoBucketImpl(Key, TheBucket); 403| | 404| 6| TheBucket->getFirst() = Key; 405| 6| ::new (&TheBucket->getSecond()) ValueT(Value); 406| 6| return TheBucket; 407| 6| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E20InsertIntoBucketImplERKS3_PS8_: 426| 6| BucketT *InsertIntoBucketImpl(const KeyT &Key, BucketT *TheBucket) { 427| 6| incrementEpoch(); 428| | 429| | // If the load of the hash table is more than 3/4, or if fewer than 1/8 of 430| | // the buckets are empty (meaning that many are filled with tombstones), 431| | // grow the table. 432| | // 433| | // The later case is tricky. For example, if we had one empty bucket with 434| | // tons of tombstones, failing lookups (e.g. for insertion) would have to 435| | // probe almost the entire table until it found the empty bucket. If the 436| | // table completely filled with tombstones, no lookup would ever succeed, 437| | // causing infinite loops in lookup. 438| 6| unsigned NewNumEntries = getNumEntries() + 1; 439| 6| unsigned NumBuckets = getNumBuckets(); 440| 6| if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) { ------------------ | | 172| 6|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 6, False: 0] | | ------------------ ------------------ 441| 6| this->grow(NumBuckets * 2); 442| 6| LookupBucketFor(Key, TheBucket); 443| 6| NumBuckets = getNumBuckets(); 444| 6| } else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <= ------------------ | | 172| 0|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 0] | | ------------------ ------------------ 445| 0| NumBuckets/8)) { 446| 0| this->grow(NumBuckets); 447| 0| LookupBucketFor(Key, TheBucket); 448| 0| } 449| 6| assert(TheBucket); ------------------ | Branch (449:5): [True: 6, False: 0] ------------------ 450| | 451| | // Only update the state after we've grown our bucket space appropriately 452| | // so that when growing buckets we have self-consistent entry count. 453| 6| incrementNumEntries(); 454| | 455| | // If we are writing over a tombstone, remember this. 456| 6| const KeyT EmptyKey = getEmptyKey(); 457| 6| if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey)) ------------------ | Branch (457:9): [True: 0, False: 6] ------------------ 458| 0| decrementNumTombstones(); 459| | 460| 6| return TheBucket; 461| 6| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E13getNumEntriesEv: 351| 12| unsigned getNumEntries() const { 352| 12| return static_cast(this)->getNumEntries(); 353| 12| } _ZNK7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEE13getNumEntriesEv: 656| 12| unsigned getNumEntries() const { 657| 12| return NumEntries; 658| 12| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E4growEj: 391| 6| void grow(unsigned AtLeast) { 392| 6| static_cast(this)->grow(AtLeast); 393| 6| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEE4growEj: 621| 6| void grow(unsigned AtLeast) { 622| 6| unsigned OldNumBuckets = NumBuckets; 623| 6| BucketT *OldBuckets = Buckets; 624| | 625| 6| allocateBuckets(std::max(64, static_cast(NextPowerOf2(AtLeast-1)))); 626| 6| assert(Buckets); ------------------ | Branch (626:5): [True: 6, False: 0] ------------------ 627| 6| if (!OldBuckets) { ------------------ | Branch (627:9): [True: 6, False: 0] ------------------ 628| 6| this->BaseT::initEmpty(); 629| 6| return; 630| 6| } 631| | 632| 0| this->moveFromOldBuckets(OldBuckets, OldBuckets+OldNumBuckets); 633| | 634| | // Free the old table. 635| 0| operator delete(OldBuckets); 636| 0| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEE15allocateBucketsEj: 678| 436| bool allocateBuckets(unsigned Num) { 679| 436| NumBuckets = Num; 680| 436| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 6] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 6| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 6| return true; 687| 436| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E9initEmptyEv: 277| 6| void initEmpty() { 278| 6| setNumEntries(0); 279| 6| setNumTombstones(0); 280| | 281| 6| assert((getNumBuckets() & (getNumBuckets()-1)) == 0 && ------------------ | Branch (281:5): [True: 6, False: 0] | Branch (281:5): [True: 6, Folded] | Branch (281:5): [True: 6, False: 0] ------------------ 282| 6| "# initial buckets must be a power of two!"); 283| 6| const KeyT EmptyKey = getEmptyKey(); 284| 390| for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B) ------------------ | Branch (284:59): [True: 384, False: 6] ------------------ 285| 384| ::new (&B->getFirst()) KeyT(EmptyKey); 286| 6| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E13setNumEntriesEj: 354| 12| void setNumEntries(unsigned Num) { 355| 12| static_cast(this)->setNumEntries(Num); 356| 12| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEE13setNumEntriesEj: 659| 12| void setNumEntries(unsigned Num) { 660| 12| NumEntries = Num; 661| 12| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E16setNumTombstonesEj: 366| 6| void setNumTombstones(unsigned Num) { 367| 6| static_cast(this)->setNumTombstones(Num); 368| 6| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEE16setNumTombstonesEj: 666| 6| void setNumTombstones(unsigned Num) { 667| 6| NumTombstones = Num; 668| 6| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E19incrementNumEntriesEv: 357| 6| void incrementNumEntries() { 358| 6| setNumEntries(getNumEntries() + 1); 359| 6| } _ZN7llvm_ks6detail12DenseMapPairIPNS_9MCSectionEjE9getSecondEv: 42| 12| ValueT &getSecond() { return std::pair::second; } _ZNK7llvm_ks16DenseMapIteratorIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEELb0EEptEv: 1024| 516| pointer operator->() const { 1025| 516| assert(isHandleInSync() && "invalid iterator access!"); ------------------ | Branch (1025:5): [True: 516, False: 0] | Branch (1025:5): [True: 516, Folded] | Branch (1025:5): [True: 516, False: 0] ------------------ 1026| 516| return Ptr; 1027| 516| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_8MCSymbolEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E13getNumBucketsEv: 381| 606| unsigned getNumBuckets() const { 382| 606| return static_cast(this)->getNumBuckets(); 383| 606| } _ZNK7llvm_ks8DenseMapIPKNS_8MCSymbolEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE13getNumBucketsEv: 674| 606| unsigned getNumBuckets() const { 675| 606| return NumBuckets; 676| 606| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 424, False: 6] ------------------ 266| 424| return; 267| | 268| 6| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 390| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 384, False: 6] ------------------ 270| 384| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 6, False: 378] ------------------ 271| 6| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 6, False: 0] ------------------ 272| 6| P->getSecond().~ValueT(); 273| 384| P->getFirst().~KeyT(); 274| 384| } 275| 6| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS3_EENS4_12DenseSetPairIS3_EEEES3_S5_S7_S9_E13getNumBucketsEv: 381| 430| unsigned getNumBuckets() const { 382| 430| return static_cast(this)->getNumBuckets(); 383| 430| } _ZNK7llvm_ks8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS2_EENS3_12DenseSetPairIS2_EEE13getNumBucketsEv: 674| 430| unsigned getNumBuckets() const { 675| 430| return NumBuckets; 676| 430| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS3_EENS4_12DenseSetPairIS3_EEEES3_S5_S7_S9_E13getNumEntriesEv: 351| 430| unsigned getNumEntries() const { 352| 430| return static_cast(this)->getNumEntries(); 353| 430| } _ZNK7llvm_ks8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS2_EENS3_12DenseSetPairIS2_EEE13getNumEntriesEv: 656| 430| unsigned getNumEntries() const { 657| 430| return NumEntries; 658| 430| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS2_EENS3_12DenseSetPairIS2_EEE15allocateBucketsEj: 678| 430| bool allocateBuckets(unsigned Num) { 679| 430| NumBuckets = Num; 680| 430| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 0] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 0| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 0| return true; 687| 430| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS3_EENS4_12DenseSetPairIS3_EEEES3_S5_S7_S9_E16getNumTombstonesEv: 363| 430| unsigned getNumTombstones() const { 364| 430| return static_cast(this)->getNumTombstones(); 365| 430| } _ZNK7llvm_ks8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS2_EENS3_12DenseSetPairIS2_EEE16getNumTombstonesEv: 663| 430| unsigned getNumTombstones() const { 664| 430| return NumTombstones; 665| 430| } _ZN7llvm_ks8DenseMapIjiNS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjiEEE15allocateBucketsEj: 678| 430| bool allocateBuckets(unsigned Num) { 679| 430| NumBuckets = Num; 680| 430| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 0] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 0| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 0| return true; 687| 430| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS2_EENS3_12DenseSetPairIS2_EEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS3_EENS4_12DenseSetPairIS3_EEEES3_S5_S7_S9_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 430, False: 0] ------------------ 266| 430| return; 267| | 268| 0| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 0| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 0, False: 0] ------------------ 270| 0| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 0, False: 0] ------------------ 271| 0| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 0, False: 0] ------------------ 272| 0| P->getSecond().~ValueT(); 273| 0| P->getFirst().~KeyT(); 274| 0| } 275| 0| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEES3_jS5_S8_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE15allocateBucketsEj: 678| 860| bool allocateBuckets(unsigned Num) { 679| 860| NumBuckets = Num; 680| 860| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 430] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 430| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 430| return true; 687| 860| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E9initEmptyEv: 277| 430| void initEmpty() { 278| 430| setNumEntries(0); 279| 430| setNumTombstones(0); 280| | 281| 430| assert((getNumBuckets() & (getNumBuckets()-1)) == 0 && ------------------ | Branch (281:5): [True: 430, False: 0] | Branch (281:5): [True: 430, Folded] | Branch (281:5): [True: 430, False: 0] ------------------ 282| 430| "# initial buckets must be a power of two!"); 283| 430| const KeyT EmptyKey = getEmptyKey(); 284| 27.9k| for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B) ------------------ | Branch (284:59): [True: 27.5k, False: 430] ------------------ 285| 27.5k| ::new (&B->getFirst()) KeyT(EmptyKey); 286| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13setNumEntriesEj: 354| 1.29k| void setNumEntries(unsigned Num) { 355| 1.29k| static_cast(this)->setNumEntries(Num); 356| 1.29k| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE13setNumEntriesEj: 659| 1.29k| void setNumEntries(unsigned Num) { 660| 1.29k| NumEntries = Num; 661| 1.29k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16setNumTombstonesEj: 366| 860| void setNumTombstones(unsigned Num) { 367| 860| static_cast(this)->setNumTombstones(Num); 368| 860| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE16setNumTombstonesEj: 666| 860| void setNumTombstones(unsigned Num) { 667| 860| NumTombstones = Num; 668| 860| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13getNumBucketsEv: 381| 5.16k| unsigned getNumBuckets() const { 382| 5.16k| return static_cast(this)->getNumBuckets(); 383| 5.16k| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE13getNumBucketsEv: 674| 5.16k| unsigned getNumBuckets() const { 675| 5.16k| return NumBuckets; 676| 5.16k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E11getEmptyKeyEv: 343| 2.15k| static const KeyT getEmptyKey() { 344| 2.15k| return KeyInfoT::getEmptyKey(); 345| 2.15k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E10getBucketsEv: 378| 2.58k| BucketT *getBuckets() { 379| 2.58k| return static_cast(this)->getBuckets(); 380| 2.58k| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE10getBucketsEv: 670| 3.44k| BucketT *getBuckets() const { 671| 3.44k| return Buckets; 672| 3.44k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13getBucketsEndEv: 384| 1.29k| BucketT *getBucketsEnd() { 385| 1.29k| return getBuckets() + getNumBuckets(); 386| 1.29k| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFEPNS_11MCSymbolELFEE8getFirstEv: 40| 111k| KeyT &getFirst() { return std::pair::first; } _ZN7llvm_ks8DenseMapINSt3__14pairIjjEEPNS_8MCSymbolENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINSt3__14pairIjjEEPNS_8MCSymbolENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapINSt3__14pairIjjEEPNS_8MCSymbolENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks8DenseMapINSt3__14pairIjjEEPNS_8MCSymbolENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE15allocateBucketsEj: 678| 430| bool allocateBuckets(unsigned Num) { 679| 430| NumBuckets = Num; 680| 430| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 0] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 0| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 0| return true; 687| 430| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapINSt3__14pairIjjEEPNS_8MCSymbolENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13getNumBucketsEv: 381| 430| unsigned getNumBuckets() const { 382| 430| return static_cast(this)->getNumBuckets(); 383| 430| } _ZNK7llvm_ks8DenseMapINSt3__14pairIjjEEPNS_8MCSymbolENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE13getNumBucketsEv: 674| 430| unsigned getNumBuckets() const { 675| 430| return NumBuckets; 676| 430| } _ZN7llvm_ks8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS2_EEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS3_EEEEjS3_S5_S8_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS2_EEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS2_EEE15allocateBucketsEj: 678| 430| bool allocateBuckets(unsigned Num) { 679| 430| NumBuckets = Num; 680| 430| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 0] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 0| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 0| return true; 687| 430| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS3_EEEEjS3_S5_S8_E13getNumBucketsEv: 381| 430| unsigned getNumBuckets() const { 382| 430| return static_cast(this)->getNumBuckets(); 383| 430| } _ZNK7llvm_ks8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS2_EEE13getNumBucketsEv: 674| 430| unsigned getNumBuckets() const { 675| 430| return NumBuckets; 676| 430| } _ZN7llvm_ks8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS2_EENS3_12DenseSetPairIS2_EEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS3_EENS4_12DenseSetPairIS3_EEEES3_S5_S7_S9_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS2_EENS3_12DenseSetPairIS2_EEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 0, False: 430] ------------------ 266| 0| return; 267| | 268| 430| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 27.9k| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 27.5k, False: 430] ------------------ 270| 27.5k| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 0, False: 27.5k] ------------------ 271| 0| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 0, False: 0] ------------------ 272| 0| P->getSecond().~ValueT(); 273| 27.5k| P->getFirst().~KeyT(); 274| 27.5k| } 275| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E15getTombstoneKeyEv: 346| 1.29k| static const KeyT getTombstoneKey() { 347| 1.29k| return KeyInfoT::getTombstoneKey(); 348| 1.29k| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFEPNS_11MCSymbolELFEE9getSecondEv: 42| 868| ValueT &getSecond() { return std::pair::second; } _ZN7llvm_ks8DenseMapINSt3__14pairIjjEEPNS_8MCSymbolENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINSt3__14pairIjjEEPNS_8MCSymbolENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 430, False: 0] ------------------ 266| 430| return; 267| | 268| 0| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 0| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 0, False: 0] ------------------ 270| 0| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 0, False: 0] ------------------ 271| 0| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 0, False: 0] ------------------ 272| 0| P->getSecond().~ValueT(); 273| 0| P->getFirst().~KeyT(); 274| 0| } 275| 0| } _ZN7llvm_ks8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS2_EEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS3_EEEEjS3_S5_S8_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 430, False: 0] ------------------ 266| 430| return; 267| | 268| 0| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 0| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 0, False: 0] ------------------ 270| 0| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 0, False: 0] ------------------ 271| 0| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 0, False: 0] ------------------ 272| 0| P->getSecond().~ValueT(); 273| 0| P->getFirst().~KeyT(); 274| 0| } 275| 0| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E5clearEv: 91| 430| void clear() { 92| 430| incrementEpoch(); 93| 430| if (getNumEntries() == 0 && getNumTombstones() == 0) return; ------------------ | Branch (93:9): [True: 0, False: 430] | Branch (93:33): [True: 0, False: 0] ------------------ 94| | 95| | // If the capacity of the array is huge, and the # elements used is small, 96| | // shrink the array. 97| 430| if (getNumEntries() * 4 < getNumBuckets() && getNumBuckets() > 64) { ------------------ | Branch (97:9): [True: 430, False: 0] | Branch (97:50): [True: 0, False: 430] ------------------ 98| 0| shrink_and_clear(); 99| 0| return; 100| 0| } 101| | 102| 430| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 103| 430| unsigned NumEntries = getNumEntries(); 104| 27.9k| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (104:59): [True: 27.5k, False: 430] ------------------ 105| 27.5k| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey)) { ------------------ | Branch (105:11): [True: 434, False: 27.0k] ------------------ 106| 434| if (!KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) { ------------------ | Branch (106:13): [True: 434, False: 0] ------------------ 107| 434| P->getSecond().~ValueT(); 108| 434| --NumEntries; 109| 434| } 110| 434| P->getFirst() = EmptyKey; 111| 434| } 112| 27.5k| } 113| 430| assert(NumEntries == 0 && "Node count imbalance!"); ------------------ | Branch (113:5): [True: 430, False: 0] | Branch (113:5): [True: 430, Folded] | Branch (113:5): [True: 430, False: 0] ------------------ 114| 430| setNumEntries(0); 115| 430| setNumTombstones(0); 116| 430| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13getNumEntriesEv: 351| 2.15k| unsigned getNumEntries() const { 352| 2.15k| return static_cast(this)->getNumEntries(); 353| 2.15k| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE13getNumEntriesEv: 656| 2.15k| unsigned getNumEntries() const { 657| 2.15k| return NumEntries; 658| 2.15k| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16getNumTombstonesEv: 363| 4| unsigned getNumTombstones() const { 364| 4| return static_cast(this)->getNumTombstones(); 365| 4| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE16getNumTombstonesEv: 663| 4| unsigned getNumTombstones() const { 664| 4| return NumTombstones; 665| 4| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS3_EEEEjS3_S5_S8_E5clearEv: 91| 430| void clear() { 92| 430| incrementEpoch(); 93| 430| if (getNumEntries() == 0 && getNumTombstones() == 0) return; ------------------ | Branch (93:9): [True: 430, False: 0] | Branch (93:33): [True: 430, False: 0] ------------------ 94| | 95| | // If the capacity of the array is huge, and the # elements used is small, 96| | // shrink the array. 97| 0| if (getNumEntries() * 4 < getNumBuckets() && getNumBuckets() > 64) { ------------------ | Branch (97:9): [True: 0, False: 0] | Branch (97:50): [True: 0, False: 0] ------------------ 98| 0| shrink_and_clear(); 99| 0| return; 100| 0| } 101| | 102| 0| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 103| 0| unsigned NumEntries = getNumEntries(); 104| 0| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (104:59): [True: 0, False: 0] ------------------ 105| 0| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey)) { ------------------ | Branch (105:11): [True: 0, False: 0] ------------------ 106| 0| if (!KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) { ------------------ | Branch (106:13): [True: 0, False: 0] ------------------ 107| 0| P->getSecond().~ValueT(); 108| 0| --NumEntries; 109| 0| } 110| 0| P->getFirst() = EmptyKey; 111| 0| } 112| 0| } 113| 0| assert(NumEntries == 0 && "Node count imbalance!"); ------------------ | Branch (113:5): [True: 0, False: 0] | Branch (113:5): [True: 0, Folded] | Branch (113:5): [True: 0, False: 0] ------------------ 114| 0| setNumEntries(0); 115| 0| setNumTombstones(0); 116| 0| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS3_EEEEjS3_S5_S8_E13getNumEntriesEv: 351| 432| unsigned getNumEntries() const { 352| 432| return static_cast(this)->getNumEntries(); 353| 432| } _ZNK7llvm_ks8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS2_EEE13getNumEntriesEv: 656| 432| unsigned getNumEntries() const { 657| 432| return NumEntries; 658| 432| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS3_EEEEjS3_S5_S8_E16getNumTombstonesEv: 363| 430| unsigned getNumTombstones() const { 364| 430| return static_cast(this)->getNumTombstones(); 365| 430| } _ZNK7llvm_ks8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS2_EEE16getNumTombstonesEv: 663| 430| unsigned getNumTombstones() const { 664| 430| return NumTombstones; 665| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPNS_9MCSectionENS_6detail13DenseSetEmptyENS_12DenseMapInfoIS3_EENS4_12DenseSetPairIS3_EEEES3_S5_S7_S9_E5clearEv: 91| 430| void clear() { 92| 430| incrementEpoch(); 93| 430| if (getNumEntries() == 0 && getNumTombstones() == 0) return; ------------------ | Branch (93:9): [True: 430, False: 0] | Branch (93:33): [True: 430, False: 0] ------------------ 94| | 95| | // If the capacity of the array is huge, and the # elements used is small, 96| | // shrink the array. 97| 0| if (getNumEntries() * 4 < getNumBuckets() && getNumBuckets() > 64) { ------------------ | Branch (97:9): [True: 0, False: 0] | Branch (97:50): [True: 0, False: 0] ------------------ 98| 0| shrink_and_clear(); 99| 0| return; 100| 0| } 101| | 102| 0| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 103| 0| unsigned NumEntries = getNumEntries(); 104| 0| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (104:59): [True: 0, False: 0] ------------------ 105| 0| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey)) { ------------------ | Branch (105:11): [True: 0, False: 0] ------------------ 106| 0| if (!KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) { ------------------ | Branch (106:13): [True: 0, False: 0] ------------------ 107| 0| P->getSecond().~ValueT(); 108| 0| --NumEntries; 109| 0| } 110| 0| P->getFirst() = EmptyKey; 111| 0| } 112| 0| } 113| 0| assert(NumEntries == 0 && "Node count imbalance!"); ------------------ | Branch (113:5): [True: 0, False: 0] | Branch (113:5): [True: 0, Folded] | Branch (113:5): [True: 0, False: 0] ------------------ 114| 0| setNumEntries(0); 115| 0| setNumTombstones(0); 116| 0| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_EixEOS4_: 245| 434| ValueT &operator[](KeyT &&Key) { 246| 434| return FindAndConstruct(std::move(Key)).second; 247| 434| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16FindAndConstructEOS4_: 237| 434| value_type& FindAndConstruct(KeyT &&Key) { 238| 434| BucketT *TheBucket; 239| 434| if (LookupBucketFor(Key, TheBucket)) ------------------ | Branch (239:9): [True: 0, False: 434] ------------------ 240| 0| return *TheBucket; 241| | 242| 434| return *InsertIntoBucket(std::move(Key), ValueT(), TheBucket); 243| 434| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E15LookupBucketForIS4_EEbRKT_RPSB_: 519| 864| bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) { 520| 864| const BucketT *ConstFoundBucket; 521| 864| bool Result = const_cast(this) 522| 864| ->LookupBucketFor(Val, ConstFoundBucket); 523| 864| FoundBucket = const_cast(ConstFoundBucket); 524| 864| return Result; 525| 864| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E15LookupBucketForIS4_EEbRKT_RPKSB_: 469| 864| const BucketT *&FoundBucket) const { 470| 864| const BucketT *BucketsPtr = getBuckets(); 471| 864| const unsigned NumBuckets = getNumBuckets(); 472| | 473| 864| if (NumBuckets == 0) { ------------------ | Branch (473:9): [True: 430, False: 434] ------------------ 474| 430| FoundBucket = nullptr; 475| 430| return false; 476| 430| } 477| | 478| | // FoundTombstone - Keep track of whether we find a tombstone while probing. 479| 434| const BucketT *FoundTombstone = nullptr; 480| 434| const KeyT EmptyKey = getEmptyKey(); 481| 434| const KeyT TombstoneKey = getTombstoneKey(); 482| 434| assert(!KeyInfoT::isEqual(Val, EmptyKey) && ------------------ | Branch (482:5): [True: 434, False: 0] | Branch (482:5): [True: 434, False: 0] | Branch (482:5): [True: 434, Folded] | Branch (482:5): [True: 434, False: 0] ------------------ 483| 434| !KeyInfoT::isEqual(Val, TombstoneKey) && 484| 434| "Empty/Tombstone value shouldn't be inserted into map!"); 485| | 486| 434| unsigned BucketNo = getHashValue(Val) & (NumBuckets-1); 487| 434| unsigned ProbeAmt = 1; 488| 434| while (1) { ------------------ | Branch (488:12): [True: 434, Folded] ------------------ 489| 434| const BucketT *ThisBucket = BucketsPtr + BucketNo; 490| | // Found Val's bucket? If so, return it. 491| 434| if (LLVM_LIKELY(KeyInfoT::isEqual(Val, ThisBucket->getFirst()))) { ------------------ | | 171| 434|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 0, False: 434] | | ------------------ ------------------ 492| 0| FoundBucket = ThisBucket; 493| 0| return true; 494| 0| } 495| | 496| | // If we found an empty bucket, the key doesn't exist in the set. 497| | // Insert it and return the default value. 498| 434| if (LLVM_LIKELY(KeyInfoT::isEqual(ThisBucket->getFirst(), EmptyKey))) { ------------------ | | 171| 434|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 434, False: 0] | | ------------------ ------------------ 499| | // If we've already seen a tombstone while probing, fill it in instead 500| | // of the empty bucket we eventually probed to. 501| 434| FoundBucket = FoundTombstone ? FoundTombstone : ThisBucket; ------------------ | Branch (501:23): [True: 0, False: 434] ------------------ 502| 434| return false; 503| 434| } 504| | 505| | // If this is a tombstone, remember it. If Val ends up not in the map, we 506| | // prefer to return it than something that would require more probing. 507| 0| if (KeyInfoT::isEqual(ThisBucket->getFirst(), TombstoneKey) && ------------------ | Branch (507:11): [True: 0, False: 0] ------------------ 508| 0| !FoundTombstone) ------------------ | Branch (508:11): [True: 0, False: 0] ------------------ 509| 0| FoundTombstone = ThisBucket; // Remember the first tombstone found. 510| | 511| | // Otherwise, it's a hash collision or a tombstone, continue quadratic 512| | // probing. 513| 0| BucketNo += ProbeAmt++; 514| 0| BucketNo &= (NumBuckets-1); 515| 0| } 516| 434| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E10getBucketsEv: 375| 864| const BucketT *getBuckets() const { 376| 864| return static_cast(this)->getBuckets(); 377| 864| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E12getHashValueERKS4_: 336| 434| static unsigned getHashValue(const KeyT &Val) { 337| 434| return KeyInfoT::getHashValue(Val); 338| 434| } _ZNK7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFEPNS_11MCSymbolELFEE8getFirstEv: 41| 868| const KeyT &getFirst() const { return std::pair::first; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16InsertIntoBucketEOS4_OS6_PSB_: 418| 434| BucketT *InsertIntoBucket(KeyT &&Key, ValueT &&Value, BucketT *TheBucket) { 419| 434| TheBucket = InsertIntoBucketImpl(Key, TheBucket); 420| | 421| 434| TheBucket->getFirst() = std::move(Key); 422| 434| ::new (&TheBucket->getSecond()) ValueT(std::move(Value)); 423| 434| return TheBucket; 424| 434| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E20InsertIntoBucketImplERKS4_PSB_: 426| 434| BucketT *InsertIntoBucketImpl(const KeyT &Key, BucketT *TheBucket) { 427| 434| incrementEpoch(); 428| | 429| | // If the load of the hash table is more than 3/4, or if fewer than 1/8 of 430| | // the buckets are empty (meaning that many are filled with tombstones), 431| | // grow the table. 432| | // 433| | // The later case is tricky. For example, if we had one empty bucket with 434| | // tons of tombstones, failing lookups (e.g. for insertion) would have to 435| | // probe almost the entire table until it found the empty bucket. If the 436| | // table completely filled with tombstones, no lookup would ever succeed, 437| | // causing infinite loops in lookup. 438| 434| unsigned NewNumEntries = getNumEntries() + 1; 439| 434| unsigned NumBuckets = getNumBuckets(); 440| 434| if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) { ------------------ | | 172| 434|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 430, False: 4] | | ------------------ ------------------ 441| 430| this->grow(NumBuckets * 2); 442| 430| LookupBucketFor(Key, TheBucket); 443| 430| NumBuckets = getNumBuckets(); 444| 430| } else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <= ------------------ | | 172| 4|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 4] | | ------------------ ------------------ 445| 4| NumBuckets/8)) { 446| 0| this->grow(NumBuckets); 447| 0| LookupBucketFor(Key, TheBucket); 448| 0| } 449| 434| assert(TheBucket); ------------------ | Branch (449:5): [True: 434, False: 0] ------------------ 450| | 451| | // Only update the state after we've grown our bucket space appropriately 452| | // so that when growing buckets we have self-consistent entry count. 453| 434| incrementNumEntries(); 454| | 455| | // If we are writing over a tombstone, remember this. 456| 434| const KeyT EmptyKey = getEmptyKey(); 457| 434| if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey)) ------------------ | Branch (457:9): [True: 0, False: 434] ------------------ 458| 0| decrementNumTombstones(); 459| | 460| 434| return TheBucket; 461| 434| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E4growEj: 391| 430| void grow(unsigned AtLeast) { 392| 430| static_cast(this)->grow(AtLeast); 393| 430| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE4growEj: 621| 430| void grow(unsigned AtLeast) { 622| 430| unsigned OldNumBuckets = NumBuckets; 623| 430| BucketT *OldBuckets = Buckets; 624| | 625| 430| allocateBuckets(std::max(64, static_cast(NextPowerOf2(AtLeast-1)))); 626| 430| assert(Buckets); ------------------ | Branch (626:5): [True: 430, False: 0] ------------------ 627| 430| if (!OldBuckets) { ------------------ | Branch (627:9): [True: 430, False: 0] ------------------ 628| 430| this->BaseT::initEmpty(); 629| 430| return; 630| 430| } 631| | 632| 0| this->moveFromOldBuckets(OldBuckets, OldBuckets+OldNumBuckets); 633| | 634| | // Free the old table. 635| 0| operator delete(OldBuckets); 636| 0| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEPNS_11MCSymbolELFENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E19incrementNumEntriesEv: 357| 434| void incrementNumEntries() { 358| 434| setNumEntries(getNumEntries() + 1); 359| 434| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIjPNS_7MCLabelENS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjS3_EEEEjS3_S5_S8_E4sizeEv: 82| 2| unsigned size() const { return getNumEntries(); } _ZN7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEEC2Ej: 553| 185| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 185| init(NumInitBuckets); 555| 185| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_EC2Ev: 262| 185| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE4initEj: 612| 185| void init(unsigned InitBuckets) { 613| 185| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 185] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 185| } else { 616| 185| NumEntries = 0; 617| 185| NumTombstones = 0; 618| 185| } 619| 185| } _ZN7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE15allocateBucketsEj: 678| 370| bool allocateBuckets(unsigned Num) { 679| 370| NumBuckets = Num; 680| 370| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 185, False: 185] ------------------ 681| 185| Buckets = nullptr; 682| 185| return false; 683| 185| } 684| | 685| 185| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 185| return true; 687| 370| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E9initEmptyEv: 277| 185| void initEmpty() { 278| 185| setNumEntries(0); 279| 185| setNumTombstones(0); 280| | 281| 185| assert((getNumBuckets() & (getNumBuckets()-1)) == 0 && ------------------ | Branch (281:5): [True: 185, False: 0] | Branch (281:5): [True: 185, Folded] | Branch (281:5): [True: 185, False: 0] ------------------ 282| 185| "# initial buckets must be a power of two!"); 283| 185| const KeyT EmptyKey = getEmptyKey(); 284| 12.0k| for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B) ------------------ | Branch (284:59): [True: 11.8k, False: 185] ------------------ 285| 11.8k| ::new (&B->getFirst()) KeyT(EmptyKey); 286| 185| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13setNumEntriesEj: 354| 372| void setNumEntries(unsigned Num) { 355| 372| static_cast(this)->setNumEntries(Num); 356| 372| } _ZN7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE13setNumEntriesEj: 659| 372| void setNumEntries(unsigned Num) { 660| 372| NumEntries = Num; 661| 372| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16setNumTombstonesEj: 366| 185| void setNumTombstones(unsigned Num) { 367| 185| static_cast(this)->setNumTombstones(Num); 368| 185| } _ZN7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE16setNumTombstonesEj: 666| 185| void setNumTombstones(unsigned Num) { 667| 185| NumTombstones = Num; 668| 185| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13getNumBucketsEv: 381| 20.1k| unsigned getNumBuckets() const { 382| 20.1k| return static_cast(this)->getNumBuckets(); 383| 20.1k| } _ZNK7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE13getNumBucketsEv: 674| 20.1k| unsigned getNumBuckets() const { 675| 20.1k| return NumBuckets; 676| 20.1k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E11getEmptyKeyEv: 343| 19.1k| static const KeyT getEmptyKey() { 344| 19.1k| return KeyInfoT::getEmptyKey(); 345| 19.1k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E10getBucketsEv: 378| 740| BucketT *getBuckets() { 379| 740| return static_cast(this)->getBuckets(); 380| 740| } _ZNK7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE10getBucketsEv: 670| 19.5k| BucketT *getBuckets() const { 671| 19.5k| return Buckets; 672| 19.5k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13getBucketsEndEv: 384| 370| BucketT *getBucketsEnd() { 385| 370| return getBuckets() + getNumBuckets(); 386| 370| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_9MCSectionEPNS_10MCFragmentEE8getFirstEv: 40| 36.0k| KeyT &getFirst() { return std::pair::first; } _ZN7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEED2Ev: 573| 185| ~DenseMap() { 574| 185| this->destroyAll(); 575| 185| operator delete(Buckets); 576| 185| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E10destroyAllEv: 264| 185| void destroyAll() { 265| 185| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 0, False: 185] ------------------ 266| 0| return; 267| | 268| 185| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 12.0k| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 11.8k, False: 185] ------------------ 270| 11.8k| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 187, False: 11.6k] ------------------ 271| 187| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 187, False: 0] ------------------ 272| 187| P->getSecond().~ValueT(); 273| 11.8k| P->getFirst().~KeyT(); 274| 11.8k| } 275| 185| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E15getTombstoneKeyEv: 346| 18.8k| static const KeyT getTombstoneKey() { 347| 18.8k| return KeyInfoT::getTombstoneKey(); 348| 18.8k| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_9MCSectionEPNS_10MCFragmentEE9getSecondEv: 42| 374| ValueT &getSecond() { return std::pair::second; } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E6lookupERKS4_: 159| 11.7k| ValueT lookup(const KeyT &Val) const { 160| 11.7k| const BucketT *TheBucket; 161| 11.7k| if (LookupBucketFor(Val, TheBucket)) ------------------ | Branch (161:9): [True: 11.7k, False: 0] ------------------ 162| 11.7k| return TheBucket->getSecond(); 163| 0| return ValueT(); 164| 11.7k| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E15LookupBucketForIS4_EEbRKT_RPKSB_: 469| 18.8k| const BucketT *&FoundBucket) const { 470| 18.8k| const BucketT *BucketsPtr = getBuckets(); 471| 18.8k| const unsigned NumBuckets = getNumBuckets(); 472| | 473| 18.8k| if (NumBuckets == 0) { ------------------ | Branch (473:9): [True: 185, False: 18.6k] ------------------ 474| 185| FoundBucket = nullptr; 475| 185| return false; 476| 185| } 477| | 478| | // FoundTombstone - Keep track of whether we find a tombstone while probing. 479| 18.6k| const BucketT *FoundTombstone = nullptr; 480| 18.6k| const KeyT EmptyKey = getEmptyKey(); 481| 18.6k| const KeyT TombstoneKey = getTombstoneKey(); 482| 18.6k| assert(!KeyInfoT::isEqual(Val, EmptyKey) && ------------------ | Branch (482:5): [True: 18.6k, False: 0] | Branch (482:5): [True: 18.6k, False: 0] | Branch (482:5): [True: 18.6k, Folded] | Branch (482:5): [True: 18.6k, False: 0] ------------------ 483| 18.6k| !KeyInfoT::isEqual(Val, TombstoneKey) && 484| 18.6k| "Empty/Tombstone value shouldn't be inserted into map!"); 485| | 486| 18.6k| unsigned BucketNo = getHashValue(Val) & (NumBuckets-1); 487| 18.6k| unsigned ProbeAmt = 1; 488| 18.6k| while (1) { ------------------ | Branch (488:12): [True: 18.6k, Folded] ------------------ 489| 18.6k| const BucketT *ThisBucket = BucketsPtr + BucketNo; 490| | // Found Val's bucket? If so, return it. 491| 18.6k| if (LLVM_LIKELY(KeyInfoT::isEqual(Val, ThisBucket->getFirst()))) { ------------------ | | 171| 18.6k|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 18.4k, False: 187] | | ------------------ ------------------ 492| 18.4k| FoundBucket = ThisBucket; 493| 18.4k| return true; 494| 18.4k| } 495| | 496| | // If we found an empty bucket, the key doesn't exist in the set. 497| | // Insert it and return the default value. 498| 187| if (LLVM_LIKELY(KeyInfoT::isEqual(ThisBucket->getFirst(), EmptyKey))) { ------------------ | | 171| 187|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 187, False: 0] | | ------------------ ------------------ 499| | // If we've already seen a tombstone while probing, fill it in instead 500| | // of the empty bucket we eventually probed to. 501| 187| FoundBucket = FoundTombstone ? FoundTombstone : ThisBucket; ------------------ | Branch (501:23): [True: 0, False: 187] ------------------ 502| 187| return false; 503| 187| } 504| | 505| | // If this is a tombstone, remember it. If Val ends up not in the map, we 506| | // prefer to return it than something that would require more probing. 507| 0| if (KeyInfoT::isEqual(ThisBucket->getFirst(), TombstoneKey) && ------------------ | Branch (507:11): [True: 0, False: 0] ------------------ 508| 0| !FoundTombstone) ------------------ | Branch (508:11): [True: 0, False: 0] ------------------ 509| 0| FoundTombstone = ThisBucket; // Remember the first tombstone found. 510| | 511| | // Otherwise, it's a hash collision or a tombstone, continue quadratic 512| | // probing. 513| 0| BucketNo += ProbeAmt++; 514| 0| BucketNo &= (NumBuckets-1); 515| 0| } 516| 18.6k| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E10getBucketsEv: 375| 18.8k| const BucketT *getBuckets() const { 376| 18.8k| return static_cast(this)->getBuckets(); 377| 18.8k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E12getHashValueERKS4_: 336| 18.6k| static unsigned getHashValue(const KeyT &Val) { 337| 18.6k| return KeyInfoT::getHashValue(Val); 338| 18.6k| } _ZNK7llvm_ks6detail12DenseMapPairIPKNS_9MCSectionEPNS_10MCFragmentEE8getFirstEv: 41| 18.8k| const KeyT &getFirst() const { return std::pair::first; } _ZNK7llvm_ks6detail12DenseMapPairIPKNS_9MCSectionEPNS_10MCFragmentEE9getSecondEv: 43| 11.7k| const ValueT &getSecond() const { return std::pair::second; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_EixEOS4_: 245| 2.50k| ValueT &operator[](KeyT &&Key) { 246| 2.50k| return FindAndConstruct(std::move(Key)).second; 247| 2.50k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16FindAndConstructEOS4_: 237| 2.50k| value_type& FindAndConstruct(KeyT &&Key) { 238| 2.50k| BucketT *TheBucket; 239| 2.50k| if (LookupBucketFor(Key, TheBucket)) ------------------ | Branch (239:9): [True: 2.50k, False: 0] ------------------ 240| 2.50k| return *TheBucket; 241| | 242| 0| return *InsertIntoBucket(std::move(Key), ValueT(), TheBucket); 243| 2.50k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E15LookupBucketForIS4_EEbRKT_RPSB_: 519| 7.08k| bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) { 520| 7.08k| const BucketT *ConstFoundBucket; 521| 7.08k| bool Result = const_cast(this) 522| 7.08k| ->LookupBucketFor(Val, ConstFoundBucket); 523| 7.08k| FoundBucket = const_cast(ConstFoundBucket); 524| 7.08k| return Result; 525| 7.08k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E20InsertIntoBucketImplERKS4_PSB_: 426| 187| BucketT *InsertIntoBucketImpl(const KeyT &Key, BucketT *TheBucket) { 427| 187| incrementEpoch(); 428| | 429| | // If the load of the hash table is more than 3/4, or if fewer than 1/8 of 430| | // the buckets are empty (meaning that many are filled with tombstones), 431| | // grow the table. 432| | // 433| | // The later case is tricky. For example, if we had one empty bucket with 434| | // tons of tombstones, failing lookups (e.g. for insertion) would have to 435| | // probe almost the entire table until it found the empty bucket. If the 436| | // table completely filled with tombstones, no lookup would ever succeed, 437| | // causing infinite loops in lookup. 438| 187| unsigned NewNumEntries = getNumEntries() + 1; 439| 187| unsigned NumBuckets = getNumBuckets(); 440| 187| if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) { ------------------ | | 172| 187|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 185, False: 2] | | ------------------ ------------------ 441| 185| this->grow(NumBuckets * 2); 442| 185| LookupBucketFor(Key, TheBucket); 443| 185| NumBuckets = getNumBuckets(); 444| 185| } else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <= ------------------ | | 172| 2|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 2] | | ------------------ ------------------ 445| 2| NumBuckets/8)) { 446| 0| this->grow(NumBuckets); 447| 0| LookupBucketFor(Key, TheBucket); 448| 0| } 449| 187| assert(TheBucket); ------------------ | Branch (449:5): [True: 187, False: 0] ------------------ 450| | 451| | // Only update the state after we've grown our bucket space appropriately 452| | // so that when growing buckets we have self-consistent entry count. 453| 187| incrementNumEntries(); 454| | 455| | // If we are writing over a tombstone, remember this. 456| 187| const KeyT EmptyKey = getEmptyKey(); 457| 187| if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey)) ------------------ | Branch (457:9): [True: 0, False: 187] ------------------ 458| 0| decrementNumTombstones(); 459| | 460| 187| return TheBucket; 461| 187| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E13getNumEntriesEv: 351| 374| unsigned getNumEntries() const { 352| 374| return static_cast(this)->getNumEntries(); 353| 374| } _ZNK7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE13getNumEntriesEv: 656| 374| unsigned getNumEntries() const { 657| 374| return NumEntries; 658| 374| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E4growEj: 391| 185| void grow(unsigned AtLeast) { 392| 185| static_cast(this)->grow(AtLeast); 393| 185| } _ZN7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE4growEj: 621| 185| void grow(unsigned AtLeast) { 622| 185| unsigned OldNumBuckets = NumBuckets; 623| 185| BucketT *OldBuckets = Buckets; 624| | 625| 185| allocateBuckets(std::max(64, static_cast(NextPowerOf2(AtLeast-1)))); 626| 185| assert(Buckets); ------------------ | Branch (626:5): [True: 185, False: 0] ------------------ 627| 185| if (!OldBuckets) { ------------------ | Branch (627:9): [True: 185, False: 0] ------------------ 628| 185| this->BaseT::initEmpty(); 629| 185| return; 630| 185| } 631| | 632| 0| this->moveFromOldBuckets(OldBuckets, OldBuckets+OldNumBuckets); 633| | 634| | // Free the old table. 635| 0| operator delete(OldBuckets); 636| 0| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16getNumTombstonesEv: 363| 2| unsigned getNumTombstones() const { 364| 2| return static_cast(this)->getNumTombstones(); 365| 2| } _ZNK7llvm_ks8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S5_EEE16getNumTombstonesEv: 663| 2| unsigned getNumTombstones() const { 664| 2| return NumTombstones; 665| 2| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E19incrementNumEntriesEv: 357| 187| void incrementNumEntries() { 358| 187| setNumEntries(getNumEntries() + 1); 359| 187| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_EixERKS4_: 233| 4.39k| ValueT &operator[](const KeyT &Key) { 234| 4.39k| return FindAndConstruct(Key).second; 235| 4.39k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16FindAndConstructERKS4_: 225| 4.39k| value_type& FindAndConstruct(const KeyT &Key) { 226| 4.39k| BucketT *TheBucket; 227| 4.39k| if (LookupBucketFor(Key, TheBucket)) ------------------ | Branch (227:9): [True: 4.20k, False: 187] ------------------ 228| 4.20k| return *TheBucket; 229| | 230| 187| return *InsertIntoBucket(Key, ValueT(), TheBucket); 231| 4.39k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_9MCSectionEPNS_10MCFragmentENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S6_EEEES4_S6_S8_SB_E16InsertIntoBucketERKS4_OS6_PSB_: 410| 187| BucketT *TheBucket) { 411| 187| TheBucket = InsertIntoBucketImpl(Key, TheBucket); 412| | 413| 187| TheBucket->getFirst() = Key; 414| 187| ::new (&TheBucket->getSecond()) ValueT(std::move(Value)); 415| 187| return TheBucket; 416| 187| } _ZN7llvm_ks8DenseMapIPKNS_8MCSymbolEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEC2Ej: 553| 606| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 606| init(NumInitBuckets); 555| 606| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_8MCSymbolEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_EC2Ev: 262| 606| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIPKNS_8MCSymbolEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE4initEj: 612| 606| void init(unsigned InitBuckets) { 613| 606| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 606] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 606| } else { 616| 606| NumEntries = 0; 617| 606| NumTombstones = 0; 618| 606| } 619| 606| } _ZN7llvm_ks8DenseMapIPKNS_8MCSymbolEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE15allocateBucketsEj: 678| 606| bool allocateBuckets(unsigned Num) { 679| 606| NumBuckets = Num; 680| 606| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 606, False: 0] ------------------ 681| 606| Buckets = nullptr; 682| 606| return false; 683| 606| } 684| | 685| 0| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 0| return true; 687| 606| } _ZN7llvm_ks8DenseMapIPKNS_8MCSymbolEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEED2Ev: 573| 606| ~DenseMap() { 574| 606| this->destroyAll(); 575| 606| operator delete(Buckets); 576| 606| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_8MCSymbolEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E10destroyAllEv: 264| 606| void destroyAll() { 265| 606| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 606, False: 0] ------------------ 266| 606| return; 267| | 268| 0| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 0| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 0, False: 0] ------------------ 270| 0| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 0, False: 0] ------------------ 271| 0| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 0, False: 0] ------------------ 272| 0| P->getSecond().~ValueT(); 273| 0| P->getFirst().~KeyT(); 274| 0| } 275| 0| } _ZN7llvm_ks8DenseMapIjiNS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjiEEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIjiNS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjiEEEEjiS3_S6_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIjiNS_12DenseMapInfoIjEENS_6detail12DenseMapPairIjiEEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks16DenseMapIteratorIPNS_9MCSectionEjNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEELb0EEC2EPS7_S9_RKNS_14DebugEpochBaseEb: 1006| 516| : DebugEpochBase::HandleBase(&Epoch), Ptr(Pos), End(E) { 1007| 516| assert(isHandleInSync() && "invalid construction!"); ------------------ | Branch (1007:5): [True: 516, False: 0] | Branch (1007:5): [True: 516, Folded] | Branch (1007:5): [True: 516, False: 0] ------------------ 1008| 516| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (1008:9): [True: 0, False: 516] ------------------ 1009| 516| } _ZN7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE15allocateBucketsEj: 678| 436| bool allocateBuckets(unsigned Num) { 679| 436| NumBuckets = Num; 680| 436| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 6] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 6| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 6| return true; 687| 436| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E9initEmptyEv: 277| 6| void initEmpty() { 278| 6| setNumEntries(0); 279| 6| setNumTombstones(0); 280| | 281| 6| assert((getNumBuckets() & (getNumBuckets()-1)) == 0 && ------------------ | Branch (281:5): [True: 6, False: 0] | Branch (281:5): [True: 6, Folded] | Branch (281:5): [True: 6, False: 0] ------------------ 282| 6| "# initial buckets must be a power of two!"); 283| 6| const KeyT EmptyKey = getEmptyKey(); 284| 390| for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B) ------------------ | Branch (284:59): [True: 384, False: 6] ------------------ 285| 384| ::new (&B->getFirst()) KeyT(EmptyKey); 286| 6| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E13setNumEntriesEj: 354| 34| void setNumEntries(unsigned Num) { 355| 34| static_cast(this)->setNumEntries(Num); 356| 34| } _ZN7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE13setNumEntriesEj: 659| 34| void setNumEntries(unsigned Num) { 660| 34| NumEntries = Num; 661| 34| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E16setNumTombstonesEj: 366| 6| void setNumTombstones(unsigned Num) { 367| 6| static_cast(this)->setNumTombstones(Num); 368| 6| } _ZN7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE16setNumTombstonesEj: 666| 6| void setNumTombstones(unsigned Num) { 667| 6| NumTombstones = Num; 668| 6| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E13getNumBucketsEv: 381| 760| unsigned getNumBuckets() const { 382| 760| return static_cast(this)->getNumBuckets(); 383| 760| } _ZNK7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE13getNumBucketsEv: 674| 760| unsigned getNumBuckets() const { 675| 760| return NumBuckets; 676| 760| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E11getEmptyKeyEv: 343| 162| static const KeyT getEmptyKey() { 344| 162| return KeyInfoT::getEmptyKey(); 345| 162| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E10getBucketsEv: 378| 146| BucketT *getBuckets() { 379| 146| return static_cast(this)->getBuckets(); 380| 146| } _ZNK7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE10getBucketsEv: 670| 296| BucketT *getBuckets() const { 671| 296| return Buckets; 672| 296| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E13getBucketsEndEv: 384| 134| BucketT *getBucketsEnd() { 385| 134| return getBuckets() + getNumBuckets(); 386| 134| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_11MCSymbolELFES4_E8getFirstEv: 40| 1.23k| KeyT &getFirst() { return std::pair::first; } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE15allocateBucketsEj: 678| 605| bool allocateBuckets(unsigned Num) { 679| 605| NumBuckets = Num; 680| 605| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 175] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 175| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 175| return true; 687| 605| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E9initEmptyEv: 277| 175| void initEmpty() { 278| 175| setNumEntries(0); 279| 175| setNumTombstones(0); 280| | 281| 175| assert((getNumBuckets() & (getNumBuckets()-1)) == 0 && ------------------ | Branch (281:5): [True: 175, False: 0] | Branch (281:5): [True: 175, Folded] | Branch (281:5): [True: 175, False: 0] ------------------ 282| 175| "# initial buckets must be a power of two!"); 283| 175| const KeyT EmptyKey = getEmptyKey(); 284| 11.3k| for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B) ------------------ | Branch (284:59): [True: 11.2k, False: 175] ------------------ 285| 11.2k| ::new (&B->getFirst()) KeyT(EmptyKey); 286| 175| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E13setNumEntriesEj: 354| 352| void setNumEntries(unsigned Num) { 355| 352| static_cast(this)->setNumEntries(Num); 356| 352| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE13setNumEntriesEj: 659| 352| void setNumEntries(unsigned Num) { 660| 352| NumEntries = Num; 661| 352| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E16setNumTombstonesEj: 366| 175| void setNumTombstones(unsigned Num) { 367| 175| static_cast(this)->setNumTombstones(Num); 368| 175| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE16setNumTombstonesEj: 666| 175| void setNumTombstones(unsigned Num) { 667| 175| NumTombstones = Num; 668| 175| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E13getNumBucketsEv: 381| 1.86k| unsigned getNumBuckets() const { 382| 1.86k| return static_cast(this)->getNumBuckets(); 383| 1.86k| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE13getNumBucketsEv: 674| 1.86k| unsigned getNumBuckets() const { 675| 1.86k| return NumBuckets; 676| 1.86k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E11getEmptyKeyEv: 343| 734| static const KeyT getEmptyKey() { 344| 734| return KeyInfoT::getEmptyKey(); 345| 734| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E10getBucketsEv: 378| 700| BucketT *getBuckets() { 379| 700| return static_cast(this)->getBuckets(); 380| 700| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE10getBucketsEv: 670| 1.08k| BucketT *getBuckets() const { 671| 1.08k| return Buckets; 672| 1.08k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E13getBucketsEndEv: 384| 350| BucketT *getBucketsEnd() { 385| 350| return getBuckets() + getNumBuckets(); 386| 350| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEEE8getFirstEv: 40| 34.1k| KeyT &getFirst() { return std::pair::first; } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 255, False: 175] ------------------ 266| 255| return; 267| | 268| 175| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 11.3k| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 11.2k, False: 175] ------------------ 270| 11.2k| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 177, False: 11.0k] ------------------ 271| 177| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 177, False: 0] ------------------ 272| 177| P->getSecond().~ValueT(); 273| 11.2k| P->getFirst().~KeyT(); 274| 11.2k| } 275| 175| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E15getTombstoneKeyEv: 346| 382| static const KeyT getTombstoneKey() { 347| 382| return KeyInfoT::getTombstoneKey(); 348| 382| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEEE9getSecondEv: 42| 354| ValueT &getSecond() { return std::pair::second; } _ZN7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 424, False: 6] ------------------ 266| 424| return; 267| | 268| 6| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 390| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 384, False: 6] ------------------ 270| 384| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 28, False: 356] ------------------ 271| 28| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 28, False: 0] ------------------ 272| 28| P->getSecond().~ValueT(); 273| 384| P->getFirst().~KeyT(); 274| 384| } 275| 6| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E15getTombstoneKeyEv: 346| 128| static const KeyT getTombstoneKey() { 347| 128| return KeyInfoT::getTombstoneKey(); 348| 128| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_11MCSymbolELFES4_E9getSecondEv: 42| 56| ValueT &getSecond() { return std::pair::second; } _ZN7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEED2Ev: 573| 430| ~DenseMap() { 574| 430| this->destroyAll(); 575| 430| operator delete(Buckets); 576| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E10destroyAllEv: 264| 430| void destroyAll() { 265| 430| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 254, False: 176] ------------------ 266| 254| return; 267| | 268| 176| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 11.4k| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 11.2k, False: 176] ------------------ 270| 11.2k| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 377, False: 10.8k] ------------------ 271| 377| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 377, False: 0] ------------------ 272| 377| P->getSecond().~ValueT(); 273| 11.2k| P->getFirst().~KeyT(); 274| 11.2k| } 275| 176| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E13getNumBucketsEv: 381| 2.61k| unsigned getNumBuckets() const { 382| 2.61k| return static_cast(this)->getNumBuckets(); 383| 2.61k| } _ZNK7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE13getNumBucketsEv: 674| 2.61k| unsigned getNumBuckets() const { 675| 2.61k| return NumBuckets; 676| 2.61k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E11getEmptyKeyEv: 343| 1.10k| static const KeyT getEmptyKey() { 344| 1.10k| return KeyInfoT::getEmptyKey(); 345| 1.10k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E15getTombstoneKeyEv: 346| 554| static const KeyT getTombstoneKey() { 347| 554| return KeyInfoT::getTombstoneKey(); 348| 554| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E10getBucketsEv: 378| 1.08k| BucketT *getBuckets() { 379| 1.08k| return static_cast(this)->getBuckets(); 380| 1.08k| } _ZNK7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE10getBucketsEv: 670| 1.63k| BucketT *getBuckets() const { 671| 1.63k| return Buckets; 672| 1.63k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E13getBucketsEndEv: 384| 730| BucketT *getBucketsEnd() { 385| 730| return getBuckets() + getNumBuckets(); 386| 730| } _ZN7llvm_ks6detail12DenseMapPairINS_9StringRefEmE8getFirstEv: 40| 34.9k| KeyT &getFirst() { return std::pair::first; } _ZN7llvm_ks6detail12DenseMapPairINS_9StringRefEmE9getSecondEv: 42| 754| ValueT &getSecond() { return std::pair::second; } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E13getNumEntriesEv: 351| 56| unsigned getNumEntries() const { 352| 56| return static_cast(this)->getNumEntries(); 353| 56| } _ZNK7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE13getNumEntriesEv: 656| 56| unsigned getNumEntries() const { 657| 56| return NumEntries; 658| 56| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E16getNumTombstonesEv: 363| 22| unsigned getNumTombstones() const { 364| 22| return static_cast(this)->getNumTombstones(); 365| 22| } _ZNK7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE16getNumTombstonesEv: 663| 22| unsigned getNumTombstones() const { 664| 22| return NumTombstones; 665| 22| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E13getNumEntriesEv: 351| 354| unsigned getNumEntries() const { 352| 354| return static_cast(this)->getNumEntries(); 353| 354| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE13getNumEntriesEv: 656| 354| unsigned getNumEntries() const { 657| 354| return NumEntries; 658| 354| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E16getNumTombstonesEv: 363| 2| unsigned getNumTombstones() const { 364| 2| return static_cast(this)->getNumTombstones(); 365| 2| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE16getNumTombstonesEv: 663| 2| unsigned getNumTombstones() const { 664| 2| return NumTombstones; 665| 2| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E6insertEONSt3__14pairIS4_S4_EE: 184| 122| std::pair insert(std::pair &&KV) { 185| 122| BucketT *TheBucket; 186| 122| if (LookupBucketFor(KV.first, TheBucket)) ------------------ | Branch (186:9): [True: 94, False: 28] ------------------ 187| 94| return std::make_pair(iterator(TheBucket, getBucketsEnd(), *this, true), 188| 94| false); // Already in map. 189| | 190| | // Otherwise, insert the new element. 191| 28| TheBucket = InsertIntoBucket(std::move(KV.first), 192| 28| std::move(KV.second), 193| 28| TheBucket); 194| 28| return std::make_pair(iterator(TheBucket, getBucketsEnd(), *this, true), 195| 28| true); 196| 122| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E15LookupBucketForIS4_EEbRKT_RPS9_: 519| 128| bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) { 520| 128| const BucketT *ConstFoundBucket; 521| 128| bool Result = const_cast(this) 522| 128| ->LookupBucketFor(Val, ConstFoundBucket); 523| 128| FoundBucket = const_cast(ConstFoundBucket); 524| 128| return Result; 525| 128| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E15LookupBucketForIS4_EEbRKT_RPKS9_: 469| 150| const BucketT *&FoundBucket) const { 470| 150| const BucketT *BucketsPtr = getBuckets(); 471| 150| const unsigned NumBuckets = getNumBuckets(); 472| | 473| 150| if (NumBuckets == 0) { ------------------ | Branch (473:9): [True: 28, False: 122] ------------------ 474| 28| FoundBucket = nullptr; 475| 28| return false; 476| 28| } 477| | 478| | // FoundTombstone - Keep track of whether we find a tombstone while probing. 479| 122| const BucketT *FoundTombstone = nullptr; 480| 122| const KeyT EmptyKey = getEmptyKey(); 481| 122| const KeyT TombstoneKey = getTombstoneKey(); 482| 122| assert(!KeyInfoT::isEqual(Val, EmptyKey) && ------------------ | Branch (482:5): [True: 122, False: 0] | Branch (482:5): [True: 122, False: 0] | Branch (482:5): [True: 122, Folded] | Branch (482:5): [True: 122, False: 0] ------------------ 483| 122| !KeyInfoT::isEqual(Val, TombstoneKey) && 484| 122| "Empty/Tombstone value shouldn't be inserted into map!"); 485| | 486| 122| unsigned BucketNo = getHashValue(Val) & (NumBuckets-1); 487| 122| unsigned ProbeAmt = 1; 488| 123| while (1) { ------------------ | Branch (488:12): [True: 123, Folded] ------------------ 489| 123| const BucketT *ThisBucket = BucketsPtr + BucketNo; 490| | // Found Val's bucket? If so, return it. 491| 123| if (LLVM_LIKELY(KeyInfoT::isEqual(Val, ThisBucket->getFirst()))) { ------------------ | | 171| 123|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 94, False: 29] | | ------------------ ------------------ 492| 94| FoundBucket = ThisBucket; 493| 94| return true; 494| 94| } 495| | 496| | // If we found an empty bucket, the key doesn't exist in the set. 497| | // Insert it and return the default value. 498| 29| if (LLVM_LIKELY(KeyInfoT::isEqual(ThisBucket->getFirst(), EmptyKey))) { ------------------ | | 171| 29|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 28, False: 1] | | ------------------ ------------------ 499| | // If we've already seen a tombstone while probing, fill it in instead 500| | // of the empty bucket we eventually probed to. 501| 28| FoundBucket = FoundTombstone ? FoundTombstone : ThisBucket; ------------------ | Branch (501:23): [True: 0, False: 28] ------------------ 502| 28| return false; 503| 28| } 504| | 505| | // If this is a tombstone, remember it. If Val ends up not in the map, we 506| | // prefer to return it than something that would require more probing. 507| 1| if (KeyInfoT::isEqual(ThisBucket->getFirst(), TombstoneKey) && ------------------ | Branch (507:11): [True: 0, False: 1] ------------------ 508| 0| !FoundTombstone) ------------------ | Branch (508:11): [True: 0, False: 0] ------------------ 509| 0| FoundTombstone = ThisBucket; // Remember the first tombstone found. 510| | 511| | // Otherwise, it's a hash collision or a tombstone, continue quadratic 512| | // probing. 513| 1| BucketNo += ProbeAmt++; 514| 1| BucketNo &= (NumBuckets-1); 515| 1| } 516| 122| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E10getBucketsEv: 375| 150| const BucketT *getBuckets() const { 376| 150| return static_cast(this)->getBuckets(); 377| 150| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E12getHashValueERKS4_: 336| 122| static unsigned getHashValue(const KeyT &Val) { 337| 122| return KeyInfoT::getHashValue(Val); 338| 122| } _ZNK7llvm_ks6detail12DenseMapPairIPKNS_11MCSymbolELFES4_E8getFirstEv: 41| 153| const KeyT &getFirst() const { return std::pair::first; } _ZN7llvm_ks16DenseMapIteratorIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EELb0EEC2EPS8_SA_RKNS_14DebugEpochBaseEb: 1006| 122| : DebugEpochBase::HandleBase(&Epoch), Ptr(Pos), End(E) { 1007| 122| assert(isHandleInSync() && "invalid construction!"); ------------------ | Branch (1007:5): [True: 122, False: 0] | Branch (1007:5): [True: 122, Folded] | Branch (1007:5): [True: 122, False: 0] ------------------ 1008| 122| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (1008:9): [True: 0, False: 122] ------------------ 1009| 122| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E16InsertIntoBucketEOS4_SC_PS9_: 418| 28| BucketT *InsertIntoBucket(KeyT &&Key, ValueT &&Value, BucketT *TheBucket) { 419| 28| TheBucket = InsertIntoBucketImpl(Key, TheBucket); 420| | 421| 28| TheBucket->getFirst() = std::move(Key); 422| 28| ::new (&TheBucket->getSecond()) ValueT(std::move(Value)); 423| 28| return TheBucket; 424| 28| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E20InsertIntoBucketImplERKS4_PS9_: 426| 28| BucketT *InsertIntoBucketImpl(const KeyT &Key, BucketT *TheBucket) { 427| 28| incrementEpoch(); 428| | 429| | // If the load of the hash table is more than 3/4, or if fewer than 1/8 of 430| | // the buckets are empty (meaning that many are filled with tombstones), 431| | // grow the table. 432| | // 433| | // The later case is tricky. For example, if we had one empty bucket with 434| | // tons of tombstones, failing lookups (e.g. for insertion) would have to 435| | // probe almost the entire table until it found the empty bucket. If the 436| | // table completely filled with tombstones, no lookup would ever succeed, 437| | // causing infinite loops in lookup. 438| 28| unsigned NewNumEntries = getNumEntries() + 1; 439| 28| unsigned NumBuckets = getNumBuckets(); 440| 28| if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) { ------------------ | | 172| 28|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 6, False: 22] | | ------------------ ------------------ 441| 6| this->grow(NumBuckets * 2); 442| 6| LookupBucketFor(Key, TheBucket); 443| 6| NumBuckets = getNumBuckets(); 444| 22| } else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <= ------------------ | | 172| 22|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 22] | | ------------------ ------------------ 445| 22| NumBuckets/8)) { 446| 0| this->grow(NumBuckets); 447| 0| LookupBucketFor(Key, TheBucket); 448| 0| } 449| 28| assert(TheBucket); ------------------ | Branch (449:5): [True: 28, False: 0] ------------------ 450| | 451| | // Only update the state after we've grown our bucket space appropriately 452| | // so that when growing buckets we have self-consistent entry count. 453| 28| incrementNumEntries(); 454| | 455| | // If we are writing over a tombstone, remember this. 456| 28| const KeyT EmptyKey = getEmptyKey(); 457| 28| if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey)) ------------------ | Branch (457:9): [True: 0, False: 28] ------------------ 458| 0| decrementNumTombstones(); 459| | 460| 28| return TheBucket; 461| 28| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E4growEj: 391| 6| void grow(unsigned AtLeast) { 392| 6| static_cast(this)->grow(AtLeast); 393| 6| } _ZN7llvm_ks8DenseMapIPKNS_11MCSymbolELFES3_NS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S3_EEE4growEj: 621| 6| void grow(unsigned AtLeast) { 622| 6| unsigned OldNumBuckets = NumBuckets; 623| 6| BucketT *OldBuckets = Buckets; 624| | 625| 6| allocateBuckets(std::max(64, static_cast(NextPowerOf2(AtLeast-1)))); 626| 6| assert(Buckets); ------------------ | Branch (626:5): [True: 6, False: 0] ------------------ 627| 6| if (!OldBuckets) { ------------------ | Branch (627:9): [True: 6, False: 0] ------------------ 628| 6| this->BaseT::initEmpty(); 629| 6| return; 630| 6| } 631| | 632| 0| this->moveFromOldBuckets(OldBuckets, OldBuckets+OldNumBuckets); 633| | 634| | // Free the old table. 635| 0| operator delete(OldBuckets); 636| 0| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E19incrementNumEntriesEv: 357| 28| void incrementNumEntries() { 358| 28| setNumEntries(getNumEntries() + 1); 359| 28| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_EixEOS4_: 245| 207| ValueT &operator[](KeyT &&Key) { 246| 207| return FindAndConstruct(std::move(Key)).second; 247| 207| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E16FindAndConstructEOS4_: 237| 207| value_type& FindAndConstruct(KeyT &&Key) { 238| 207| BucketT *TheBucket; 239| 207| if (LookupBucketFor(Key, TheBucket)) ------------------ | Branch (239:9): [True: 30, False: 177] ------------------ 240| 30| return *TheBucket; 241| | 242| 177| return *InsertIntoBucket(std::move(Key), ValueT(), TheBucket); 243| 207| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E15LookupBucketForIS4_EEbRKT_RPSF_: 519| 382| bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) { 520| 382| const BucketT *ConstFoundBucket; 521| 382| bool Result = const_cast(this) 522| 382| ->LookupBucketFor(Val, ConstFoundBucket); 523| 382| FoundBucket = const_cast(ConstFoundBucket); 524| 382| return Result; 525| 382| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E15LookupBucketForIS4_EEbRKT_RPKSF_: 469| 382| const BucketT *&FoundBucket) const { 470| 382| const BucketT *BucketsPtr = getBuckets(); 471| 382| const unsigned NumBuckets = getNumBuckets(); 472| | 473| 382| if (NumBuckets == 0) { ------------------ | Branch (473:9): [True: 175, False: 207] ------------------ 474| 175| FoundBucket = nullptr; 475| 175| return false; 476| 175| } 477| | 478| | // FoundTombstone - Keep track of whether we find a tombstone while probing. 479| 207| const BucketT *FoundTombstone = nullptr; 480| 207| const KeyT EmptyKey = getEmptyKey(); 481| 207| const KeyT TombstoneKey = getTombstoneKey(); 482| 207| assert(!KeyInfoT::isEqual(Val, EmptyKey) && ------------------ | Branch (482:5): [True: 207, False: 0] | Branch (482:5): [True: 207, False: 0] | Branch (482:5): [True: 207, Folded] | Branch (482:5): [True: 207, False: 0] ------------------ 483| 207| !KeyInfoT::isEqual(Val, TombstoneKey) && 484| 207| "Empty/Tombstone value shouldn't be inserted into map!"); 485| | 486| 207| unsigned BucketNo = getHashValue(Val) & (NumBuckets-1); 487| 207| unsigned ProbeAmt = 1; 488| 207| while (1) { ------------------ | Branch (488:12): [True: 207, Folded] ------------------ 489| 207| const BucketT *ThisBucket = BucketsPtr + BucketNo; 490| | // Found Val's bucket? If so, return it. 491| 207| if (LLVM_LIKELY(KeyInfoT::isEqual(Val, ThisBucket->getFirst()))) { ------------------ | | 171| 207|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 30, False: 177] | | ------------------ ------------------ 492| 30| FoundBucket = ThisBucket; 493| 30| return true; 494| 30| } 495| | 496| | // If we found an empty bucket, the key doesn't exist in the set. 497| | // Insert it and return the default value. 498| 177| if (LLVM_LIKELY(KeyInfoT::isEqual(ThisBucket->getFirst(), EmptyKey))) { ------------------ | | 171| 177|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 177, False: 0] | | ------------------ ------------------ 499| | // If we've already seen a tombstone while probing, fill it in instead 500| | // of the empty bucket we eventually probed to. 501| 177| FoundBucket = FoundTombstone ? FoundTombstone : ThisBucket; ------------------ | Branch (501:23): [True: 0, False: 177] ------------------ 502| 177| return false; 503| 177| } 504| | 505| | // If this is a tombstone, remember it. If Val ends up not in the map, we 506| | // prefer to return it than something that would require more probing. 507| 0| if (KeyInfoT::isEqual(ThisBucket->getFirst(), TombstoneKey) && ------------------ | Branch (507:11): [True: 0, False: 0] ------------------ 508| 0| !FoundTombstone) ------------------ | Branch (508:11): [True: 0, False: 0] ------------------ 509| 0| FoundTombstone = ThisBucket; // Remember the first tombstone found. 510| | 511| | // Otherwise, it's a hash collision or a tombstone, continue quadratic 512| | // probing. 513| 0| BucketNo += ProbeAmt++; 514| 0| BucketNo &= (NumBuckets-1); 515| 0| } 516| 207| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E10getBucketsEv: 375| 382| const BucketT *getBuckets() const { 376| 382| return static_cast(this)->getBuckets(); 377| 382| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E12getHashValueERKS4_: 336| 207| static unsigned getHashValue(const KeyT &Val) { 337| 207| return KeyInfoT::getHashValue(Val); 338| 207| } _ZNK7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEEE8getFirstEv: 41| 384| const KeyT &getFirst() const { return std::pair::first; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E16InsertIntoBucketEOS4_OSA_PSF_: 418| 177| BucketT *InsertIntoBucket(KeyT &&Key, ValueT &&Value, BucketT *TheBucket) { 419| 177| TheBucket = InsertIntoBucketImpl(Key, TheBucket); 420| | 421| 177| TheBucket->getFirst() = std::move(Key); 422| 177| ::new (&TheBucket->getSecond()) ValueT(std::move(Value)); 423| 177| return TheBucket; 424| 177| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E20InsertIntoBucketImplERKS4_PSF_: 426| 177| BucketT *InsertIntoBucketImpl(const KeyT &Key, BucketT *TheBucket) { 427| 177| incrementEpoch(); 428| | 429| | // If the load of the hash table is more than 3/4, or if fewer than 1/8 of 430| | // the buckets are empty (meaning that many are filled with tombstones), 431| | // grow the table. 432| | // 433| | // The later case is tricky. For example, if we had one empty bucket with 434| | // tons of tombstones, failing lookups (e.g. for insertion) would have to 435| | // probe almost the entire table until it found the empty bucket. If the 436| | // table completely filled with tombstones, no lookup would ever succeed, 437| | // causing infinite loops in lookup. 438| 177| unsigned NewNumEntries = getNumEntries() + 1; 439| 177| unsigned NumBuckets = getNumBuckets(); 440| 177| if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) { ------------------ | | 172| 177|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 175, False: 2] | | ------------------ ------------------ 441| 175| this->grow(NumBuckets * 2); 442| 175| LookupBucketFor(Key, TheBucket); 443| 175| NumBuckets = getNumBuckets(); 444| 175| } else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <= ------------------ | | 172| 2|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 2] | | ------------------ ------------------ 445| 2| NumBuckets/8)) { 446| 0| this->grow(NumBuckets); 447| 0| LookupBucketFor(Key, TheBucket); 448| 0| } 449| 177| assert(TheBucket); ------------------ | Branch (449:5): [True: 177, False: 0] ------------------ 450| | 451| | // Only update the state after we've grown our bucket space appropriately 452| | // so that when growing buckets we have self-consistent entry count. 453| 177| incrementNumEntries(); 454| | 455| | // If we are writing over a tombstone, remember this. 456| 177| const KeyT EmptyKey = getEmptyKey(); 457| 177| if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey)) ------------------ | Branch (457:9): [True: 0, False: 177] ------------------ 458| 0| decrementNumTombstones(); 459| | 460| 177| return TheBucket; 461| 177| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E4growEj: 391| 175| void grow(unsigned AtLeast) { 392| 175| static_cast(this)->grow(AtLeast); 393| 175| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS4_9allocatorIS6_EEEENS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_S9_EEE4growEj: 621| 175| void grow(unsigned AtLeast) { 622| 175| unsigned OldNumBuckets = NumBuckets; 623| 175| BucketT *OldBuckets = Buckets; 624| | 625| 175| allocateBuckets(std::max(64, static_cast(NextPowerOf2(AtLeast-1)))); 626| 175| assert(Buckets); ------------------ | Branch (626:5): [True: 175, False: 0] ------------------ 627| 175| if (!OldBuckets) { ------------------ | Branch (627:9): [True: 175, False: 0] ------------------ 628| 175| this->BaseT::initEmpty(); 629| 175| return; 630| 175| } 631| | 632| 0| this->moveFromOldBuckets(OldBuckets, OldBuckets+OldNumBuckets); 633| | 634| | // Free the old table. 635| 0| operator delete(OldBuckets); 636| 0| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFENSt3__16vectorINS_18ELFRelocationEntryENS5_9allocatorIS7_EEEENS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_SA_EEEES4_SA_SC_SF_E19incrementNumEntriesEv: 357| 177| void incrementNumEntries() { 358| 177| setNumEntries(getNumEntries() + 1); 359| 177| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_11MCSymbolELFES4_NS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_S4_EEEES4_S4_S6_S9_E6lookupERKS4_: 159| 22| ValueT lookup(const KeyT &Val) const { 160| 22| const BucketT *TheBucket; 161| 22| if (LookupBucketFor(Val, TheBucket)) ------------------ | Branch (161:9): [True: 0, False: 22] ------------------ 162| 0| return TheBucket->getSecond(); 163| 22| return ValueT(); 164| 22| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEEC2Ej: 553| 176| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 176| init(NumInitBuckets); 555| 176| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_EC2Ev: 262| 176| DenseMapBase() = default; _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE4initEj: 612| 176| void init(unsigned InitBuckets) { 613| 176| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 176] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 176| } else { 616| 176| NumEntries = 0; 617| 176| NumTombstones = 0; 618| 176| } 619| 176| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE15allocateBucketsEj: 678| 351| bool allocateBuckets(unsigned Num) { 679| 351| NumBuckets = Num; 680| 351| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 176, False: 175] ------------------ 681| 176| Buckets = nullptr; 682| 176| return false; 683| 176| } 684| | 685| 175| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 175| return true; 687| 351| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E9initEmptyEv: 277| 175| void initEmpty() { 278| 175| setNumEntries(0); 279| 175| setNumTombstones(0); 280| | 281| 175| assert((getNumBuckets() & (getNumBuckets()-1)) == 0 && ------------------ | Branch (281:5): [True: 175, False: 0] | Branch (281:5): [True: 175, Folded] | Branch (281:5): [True: 175, False: 0] ------------------ 282| 175| "# initial buckets must be a power of two!"); 283| 175| const KeyT EmptyKey = getEmptyKey(); 284| 11.3k| for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B) ------------------ | Branch (284:59): [True: 11.2k, False: 175] ------------------ 285| 11.2k| ::new (&B->getFirst()) KeyT(EmptyKey); 286| 175| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E13setNumEntriesEj: 354| 377| void setNumEntries(unsigned Num) { 355| 377| static_cast(this)->setNumEntries(Num); 356| 377| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE13setNumEntriesEj: 659| 377| void setNumEntries(unsigned Num) { 660| 377| NumEntries = Num; 661| 377| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E16setNumTombstonesEj: 366| 175| void setNumTombstones(unsigned Num) { 367| 175| static_cast(this)->setNumTombstones(Num); 368| 175| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE16setNumTombstonesEj: 666| 175| void setNumTombstones(unsigned Num) { 667| 175| NumTombstones = Num; 668| 175| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E13getNumBucketsEv: 381| 1.63k| unsigned getNumBuckets() const { 382| 1.63k| return static_cast(this)->getNumBuckets(); 383| 1.63k| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE13getNumBucketsEv: 674| 1.63k| unsigned getNumBuckets() const { 675| 1.63k| return NumBuckets; 676| 1.63k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E11getEmptyKeyEv: 343| 754| static const KeyT getEmptyKey() { 344| 754| return KeyInfoT::getEmptyKey(); 345| 754| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E10getBucketsEv: 378| 700| BucketT *getBuckets() { 379| 700| return static_cast(this)->getBuckets(); 380| 700| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE10getBucketsEv: 670| 1.07k| BucketT *getBuckets() const { 671| 1.07k| return Buckets; 672| 1.07k| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E13getBucketsEndEv: 384| 350| BucketT *getBucketsEnd() { 385| 350| return getBuckets() + getNumBuckets(); 386| 350| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFEjE8getFirstEv: 40| 34.2k| KeyT &getFirst() { return std::pair::first; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_EixEOS4_: 245| 177| ValueT &operator[](KeyT &&Key) { 246| 177| return FindAndConstruct(std::move(Key)).second; 247| 177| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E16FindAndConstructEOS4_: 237| 177| value_type& FindAndConstruct(KeyT &&Key) { 238| 177| BucketT *TheBucket; 239| 177| if (LookupBucketFor(Key, TheBucket)) ------------------ | Branch (239:9): [True: 0, False: 177] ------------------ 240| 0| return *TheBucket; 241| | 242| 177| return *InsertIntoBucket(std::move(Key), ValueT(), TheBucket); 243| 177| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E15LookupBucketForIS4_EEbRKT_RPS9_: 519| 377| bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) { 520| 377| const BucketT *ConstFoundBucket; 521| 377| bool Result = const_cast(this) 522| 377| ->LookupBucketFor(Val, ConstFoundBucket); 523| 377| FoundBucket = const_cast(ConstFoundBucket); 524| 377| return Result; 525| 377| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E15LookupBucketForIS4_EEbRKT_RPKS9_: 469| 377| const BucketT *&FoundBucket) const { 470| 377| const BucketT *BucketsPtr = getBuckets(); 471| 377| const unsigned NumBuckets = getNumBuckets(); 472| | 473| 377| if (NumBuckets == 0) { ------------------ | Branch (473:9): [True: 175, False: 202] ------------------ 474| 175| FoundBucket = nullptr; 475| 175| return false; 476| 175| } 477| | 478| | // FoundTombstone - Keep track of whether we find a tombstone while probing. 479| 202| const BucketT *FoundTombstone = nullptr; 480| 202| const KeyT EmptyKey = getEmptyKey(); 481| 202| const KeyT TombstoneKey = getTombstoneKey(); 482| 202| assert(!KeyInfoT::isEqual(Val, EmptyKey) && ------------------ | Branch (482:5): [True: 202, False: 0] | Branch (482:5): [True: 202, False: 0] | Branch (482:5): [True: 202, Folded] | Branch (482:5): [True: 202, False: 0] ------------------ 483| 202| !KeyInfoT::isEqual(Val, TombstoneKey) && 484| 202| "Empty/Tombstone value shouldn't be inserted into map!"); 485| | 486| 202| unsigned BucketNo = getHashValue(Val) & (NumBuckets-1); 487| 202| unsigned ProbeAmt = 1; 488| 202| while (1) { ------------------ | Branch (488:12): [True: 202, Folded] ------------------ 489| 202| const BucketT *ThisBucket = BucketsPtr + BucketNo; 490| | // Found Val's bucket? If so, return it. 491| 202| if (LLVM_LIKELY(KeyInfoT::isEqual(Val, ThisBucket->getFirst()))) { ------------------ | | 171| 202|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 0, False: 202] | | ------------------ ------------------ 492| 0| FoundBucket = ThisBucket; 493| 0| return true; 494| 0| } 495| | 496| | // If we found an empty bucket, the key doesn't exist in the set. 497| | // Insert it and return the default value. 498| 202| if (LLVM_LIKELY(KeyInfoT::isEqual(ThisBucket->getFirst(), EmptyKey))) { ------------------ | | 171| 202|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 202, False: 0] | | ------------------ ------------------ 499| | // If we've already seen a tombstone while probing, fill it in instead 500| | // of the empty bucket we eventually probed to. 501| 202| FoundBucket = FoundTombstone ? FoundTombstone : ThisBucket; ------------------ | Branch (501:23): [True: 0, False: 202] ------------------ 502| 202| return false; 503| 202| } 504| | 505| | // If this is a tombstone, remember it. If Val ends up not in the map, we 506| | // prefer to return it than something that would require more probing. 507| 0| if (KeyInfoT::isEqual(ThisBucket->getFirst(), TombstoneKey) && ------------------ | Branch (507:11): [True: 0, False: 0] ------------------ 508| 0| !FoundTombstone) ------------------ | Branch (508:11): [True: 0, False: 0] ------------------ 509| 0| FoundTombstone = ThisBucket; // Remember the first tombstone found. 510| | 511| | // Otherwise, it's a hash collision or a tombstone, continue quadratic 512| | // probing. 513| 0| BucketNo += ProbeAmt++; 514| 0| BucketNo &= (NumBuckets-1); 515| 0| } 516| 202| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E10getBucketsEv: 375| 377| const BucketT *getBuckets() const { 376| 377| return static_cast(this)->getBuckets(); 377| 377| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E15getTombstoneKeyEv: 346| 377| static const KeyT getTombstoneKey() { 347| 377| return KeyInfoT::getTombstoneKey(); 348| 377| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E12getHashValueERKS4_: 336| 202| static unsigned getHashValue(const KeyT &Val) { 337| 202| return KeyInfoT::getHashValue(Val); 338| 202| } _ZNK7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFEjE8getFirstEv: 41| 404| const KeyT &getFirst() const { return std::pair::first; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E16InsertIntoBucketEOS4_OjPS9_: 418| 177| BucketT *InsertIntoBucket(KeyT &&Key, ValueT &&Value, BucketT *TheBucket) { 419| 177| TheBucket = InsertIntoBucketImpl(Key, TheBucket); 420| | 421| 177| TheBucket->getFirst() = std::move(Key); 422| 177| ::new (&TheBucket->getSecond()) ValueT(std::move(Value)); 423| 177| return TheBucket; 424| 177| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E20InsertIntoBucketImplERKS4_PS9_: 426| 202| BucketT *InsertIntoBucketImpl(const KeyT &Key, BucketT *TheBucket) { 427| 202| incrementEpoch(); 428| | 429| | // If the load of the hash table is more than 3/4, or if fewer than 1/8 of 430| | // the buckets are empty (meaning that many are filled with tombstones), 431| | // grow the table. 432| | // 433| | // The later case is tricky. For example, if we had one empty bucket with 434| | // tons of tombstones, failing lookups (e.g. for insertion) would have to 435| | // probe almost the entire table until it found the empty bucket. If the 436| | // table completely filled with tombstones, no lookup would ever succeed, 437| | // causing infinite loops in lookup. 438| 202| unsigned NewNumEntries = getNumEntries() + 1; 439| 202| unsigned NumBuckets = getNumBuckets(); 440| 202| if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) { ------------------ | | 172| 202|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 175, False: 27] | | ------------------ ------------------ 441| 175| this->grow(NumBuckets * 2); 442| 175| LookupBucketFor(Key, TheBucket); 443| 175| NumBuckets = getNumBuckets(); 444| 175| } else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <= ------------------ | | 172| 27|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 27] | | ------------------ ------------------ 445| 27| NumBuckets/8)) { 446| 0| this->grow(NumBuckets); 447| 0| LookupBucketFor(Key, TheBucket); 448| 0| } 449| 202| assert(TheBucket); ------------------ | Branch (449:5): [True: 202, False: 0] ------------------ 450| | 451| | // Only update the state after we've grown our bucket space appropriately 452| | // so that when growing buckets we have self-consistent entry count. 453| 202| incrementNumEntries(); 454| | 455| | // If we are writing over a tombstone, remember this. 456| 202| const KeyT EmptyKey = getEmptyKey(); 457| 202| if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey)) ------------------ | Branch (457:9): [True: 0, False: 202] ------------------ 458| 0| decrementNumTombstones(); 459| | 460| 202| return TheBucket; 461| 202| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E13getNumEntriesEv: 351| 404| unsigned getNumEntries() const { 352| 404| return static_cast(this)->getNumEntries(); 353| 404| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE13getNumEntriesEv: 656| 404| unsigned getNumEntries() const { 657| 404| return NumEntries; 658| 404| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E4growEj: 391| 175| void grow(unsigned AtLeast) { 392| 175| static_cast(this)->grow(AtLeast); 393| 175| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE4growEj: 621| 175| void grow(unsigned AtLeast) { 622| 175| unsigned OldNumBuckets = NumBuckets; 623| 175| BucketT *OldBuckets = Buckets; 624| | 625| 175| allocateBuckets(std::max(64, static_cast(NextPowerOf2(AtLeast-1)))); 626| 175| assert(Buckets); ------------------ | Branch (626:5): [True: 175, False: 0] ------------------ 627| 175| if (!OldBuckets) { ------------------ | Branch (627:9): [True: 175, False: 0] ------------------ 628| 175| this->BaseT::initEmpty(); 629| 175| return; 630| 175| } 631| | 632| 0| this->moveFromOldBuckets(OldBuckets, OldBuckets+OldNumBuckets); 633| | 634| | // Free the old table. 635| 0| operator delete(OldBuckets); 636| 0| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E16getNumTombstonesEv: 363| 27| unsigned getNumTombstones() const { 364| 27| return static_cast(this)->getNumTombstones(); 365| 27| } _ZNK7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEE16getNumTombstonesEv: 663| 27| unsigned getNumTombstones() const { 664| 27| return NumTombstones; 665| 27| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E19incrementNumEntriesEv: 357| 202| void incrementNumEntries() { 358| 202| setNumEntries(getNumEntries() + 1); 359| 202| } _ZN7llvm_ks6detail12DenseMapPairIPKNS_12MCSectionELFEjE9getSecondEv: 42| 404| ValueT &getSecond() { return std::pair::second; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_EixERKS4_: 233| 25| ValueT &operator[](const KeyT &Key) { 234| 25| return FindAndConstruct(Key).second; 235| 25| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E16FindAndConstructERKS4_: 225| 25| value_type& FindAndConstruct(const KeyT &Key) { 226| 25| BucketT *TheBucket; 227| 25| if (LookupBucketFor(Key, TheBucket)) ------------------ | Branch (227:9): [True: 0, False: 25] ------------------ 228| 0| return *TheBucket; 229| | 230| 25| return *InsertIntoBucket(Key, ValueT(), TheBucket); 231| 25| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E16InsertIntoBucketERKS4_OjPS9_: 410| 25| BucketT *TheBucket) { 411| 25| TheBucket = InsertIntoBucketImpl(Key, TheBucket); 412| | 413| 25| TheBucket->getFirst() = Key; 414| 25| ::new (&TheBucket->getSecond()) ValueT(std::move(Value)); 415| 25| return TheBucket; 416| 25| } _ZN7llvm_ks8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS3_EENS_6detail12DenseMapPairIS3_jEEED2Ev: 573| 176| ~DenseMap() { 574| 176| this->destroyAll(); 575| 176| operator delete(Buckets); 576| 176| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapIPKNS_12MCSectionELFEjNS_12DenseMapInfoIS4_EENS_6detail12DenseMapPairIS4_jEEEES4_jS6_S9_E10destroyAllEv: 264| 176| void destroyAll() { 265| 176| if (getNumBuckets() == 0) // Nothing to do. ------------------ | Branch (265:9): [True: 1, False: 175] ------------------ 266| 1| return; 267| | 268| 175| const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); 269| 11.3k| for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) { ------------------ | Branch (269:59): [True: 11.2k, False: 175] ------------------ 270| 11.2k| if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) && ------------------ | Branch (270:11): [True: 202, False: 10.9k] ------------------ 271| 202| !KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) ------------------ | Branch (271:11): [True: 202, False: 0] ------------------ 272| 202| P->getSecond().~ValueT(); 273| 11.2k| P->getFirst().~KeyT(); 274| 11.2k| } 275| 175| } _ZN7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEEC2Ej: 553| 430| explicit DenseMap(unsigned NumInitBuckets = 0) { 554| 430| init(NumInitBuckets); 555| 430| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_EC2Ev: 262| 430| DenseMapBase() = default; _ZN7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE4initEj: 612| 430| void init(unsigned InitBuckets) { 613| 430| if (allocateBuckets(InitBuckets)) { ------------------ | Branch (613:9): [True: 0, False: 430] ------------------ 614| 0| this->BaseT::initEmpty(); 615| 430| } else { 616| 430| NumEntries = 0; 617| 430| NumTombstones = 0; 618| 430| } 619| 430| } _ZN7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE15allocateBucketsEj: 678| 606| bool allocateBuckets(unsigned Num) { 679| 606| NumBuckets = Num; 680| 606| if (NumBuckets == 0) { ------------------ | Branch (680:9): [True: 430, False: 176] ------------------ 681| 430| Buckets = nullptr; 682| 430| return false; 683| 430| } 684| | 685| 176| Buckets = static_cast(operator new(sizeof(BucketT) * NumBuckets)); 686| 176| return true; 687| 606| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E9initEmptyEv: 277| 176| void initEmpty() { 278| 176| setNumEntries(0); 279| 176| setNumTombstones(0); 280| | 281| 176| assert((getNumBuckets() & (getNumBuckets()-1)) == 0 && ------------------ | Branch (281:5): [True: 176, False: 0] | Branch (281:5): [True: 176, Folded] | Branch (281:5): [True: 176, False: 0] ------------------ 282| 176| "# initial buckets must be a power of two!"); 283| 176| const KeyT EmptyKey = getEmptyKey(); 284| 11.4k| for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B) ------------------ | Branch (284:59): [True: 11.2k, False: 176] ------------------ 285| 11.2k| ::new (&B->getFirst()) KeyT(EmptyKey); 286| 176| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E13setNumEntriesEj: 354| 553| void setNumEntries(unsigned Num) { 355| 553| static_cast(this)->setNumEntries(Num); 356| 553| } _ZN7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE13setNumEntriesEj: 659| 553| void setNumEntries(unsigned Num) { 660| 553| NumEntries = Num; 661| 553| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E16setNumTombstonesEj: 366| 176| void setNumTombstones(unsigned Num) { 367| 176| static_cast(this)->setNumTombstones(Num); 368| 176| } _ZN7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE16setNumTombstonesEj: 666| 176| void setNumTombstones(unsigned Num) { 667| 176| NumTombstones = Num; 668| 176| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E13getNumEntriesEv: 351| 754| unsigned getNumEntries() const { 352| 754| return static_cast(this)->getNumEntries(); 353| 754| } _ZNK7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE13getNumEntriesEv: 656| 754| unsigned getNumEntries() const { 657| 754| return NumEntries; 658| 754| } _ZN7llvm_ks16DenseMapIteratorINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEELb0EEC2EPS6_S8_RKNS_14DebugEpochBaseEb: 1006| 378| : DebugEpochBase::HandleBase(&Epoch), Ptr(Pos), End(E) { 1007| 378| assert(isHandleInSync() && "invalid construction!"); ------------------ | Branch (1007:5): [True: 378, False: 0] | Branch (1007:5): [True: 378, Folded] | Branch (1007:5): [True: 378, False: 0] ------------------ 1008| 378| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (1008:9): [True: 0, False: 378] ------------------ 1009| 378| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E16getNumTombstonesEv: 363| 201| unsigned getNumTombstones() const { 364| 201| return static_cast(this)->getNumTombstones(); 365| 201| } _ZNK7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE16getNumTombstonesEv: 663| 201| unsigned getNumTombstones() const { 664| 201| return NumTombstones; 665| 201| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E15LookupBucketForIS2_EEbRKT_RPKS7_: 469| 554| const BucketT *&FoundBucket) const { 470| 554| const BucketT *BucketsPtr = getBuckets(); 471| 554| const unsigned NumBuckets = getNumBuckets(); 472| | 473| 554| if (NumBuckets == 0) { ------------------ | Branch (473:9): [True: 176, False: 378] ------------------ 474| 176| FoundBucket = nullptr; 475| 176| return false; 476| 176| } 477| | 478| | // FoundTombstone - Keep track of whether we find a tombstone while probing. 479| 378| const BucketT *FoundTombstone = nullptr; 480| 378| const KeyT EmptyKey = getEmptyKey(); 481| 378| const KeyT TombstoneKey = getTombstoneKey(); 482| 378| assert(!KeyInfoT::isEqual(Val, EmptyKey) && ------------------ | Branch (482:5): [True: 378, False: 0] | Branch (482:5): [True: 378, False: 0] | Branch (482:5): [True: 378, Folded] | Branch (482:5): [True: 378, False: 0] ------------------ 483| 378| !KeyInfoT::isEqual(Val, TombstoneKey) && 484| 378| "Empty/Tombstone value shouldn't be inserted into map!"); 485| | 486| 378| unsigned BucketNo = getHashValue(Val) & (NumBuckets-1); 487| 378| unsigned ProbeAmt = 1; 488| 403| while (1) { ------------------ | Branch (488:12): [True: 403, Folded] ------------------ 489| 403| const BucketT *ThisBucket = BucketsPtr + BucketNo; 490| | // Found Val's bucket? If so, return it. 491| 403| if (LLVM_LIKELY(KeyInfoT::isEqual(Val, ThisBucket->getFirst()))) { ------------------ | | 171| 403|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 1, False: 402] | | ------------------ ------------------ 492| 1| FoundBucket = ThisBucket; 493| 1| return true; 494| 1| } 495| | 496| | // If we found an empty bucket, the key doesn't exist in the set. 497| | // Insert it and return the default value. 498| 402| if (LLVM_LIKELY(KeyInfoT::isEqual(ThisBucket->getFirst(), EmptyKey))) { ------------------ | | 171| 402|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 377, False: 25] | | ------------------ ------------------ 499| | // If we've already seen a tombstone while probing, fill it in instead 500| | // of the empty bucket we eventually probed to. 501| 377| FoundBucket = FoundTombstone ? FoundTombstone : ThisBucket; ------------------ | Branch (501:23): [True: 0, False: 377] ------------------ 502| 377| return false; 503| 377| } 504| | 505| | // If this is a tombstone, remember it. If Val ends up not in the map, we 506| | // prefer to return it than something that would require more probing. 507| 25| if (KeyInfoT::isEqual(ThisBucket->getFirst(), TombstoneKey) && ------------------ | Branch (507:11): [True: 0, False: 25] ------------------ 508| 0| !FoundTombstone) ------------------ | Branch (508:11): [True: 0, False: 0] ------------------ 509| 0| FoundTombstone = ThisBucket; // Remember the first tombstone found. 510| | 511| | // Otherwise, it's a hash collision or a tombstone, continue quadratic 512| | // probing. 513| 25| BucketNo += ProbeAmt++; 514| 25| BucketNo &= (NumBuckets-1); 515| 25| } 516| 378| } _ZNK7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E10getBucketsEv: 375| 554| const BucketT *getBuckets() const { 376| 554| return static_cast(this)->getBuckets(); 377| 554| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E12getHashValueERKS2_: 336| 378| static unsigned getHashValue(const KeyT &Val) { 337| 378| return KeyInfoT::getHashValue(Val); 338| 378| } _ZNK7llvm_ks6detail12DenseMapPairINS_9StringRefEmE8getFirstEv: 41| 830| const KeyT &getFirst() const { return std::pair::first; } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E6insertEONSt3__14pairIS2_mEE: 184| 378| std::pair insert(std::pair &&KV) { 185| 378| BucketT *TheBucket; 186| 378| if (LookupBucketFor(KV.first, TheBucket)) ------------------ | Branch (186:9): [True: 1, False: 377] ------------------ 187| 1| return std::make_pair(iterator(TheBucket, getBucketsEnd(), *this, true), 188| 1| false); // Already in map. 189| | 190| | // Otherwise, insert the new element. 191| 377| TheBucket = InsertIntoBucket(std::move(KV.first), 192| 377| std::move(KV.second), 193| 377| TheBucket); 194| 377| return std::make_pair(iterator(TheBucket, getBucketsEnd(), *this, true), 195| 377| true); 196| 378| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E15LookupBucketForIS2_EEbRKT_RPS7_: 519| 554| bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) { 520| 554| const BucketT *ConstFoundBucket; 521| 554| bool Result = const_cast(this) 522| 554| ->LookupBucketFor(Val, ConstFoundBucket); 523| 554| FoundBucket = const_cast(ConstFoundBucket); 524| 554| return Result; 525| 554| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E16InsertIntoBucketEOS2_OmPS7_: 418| 377| BucketT *InsertIntoBucket(KeyT &&Key, ValueT &&Value, BucketT *TheBucket) { 419| 377| TheBucket = InsertIntoBucketImpl(Key, TheBucket); 420| | 421| 377| TheBucket->getFirst() = std::move(Key); 422| 377| ::new (&TheBucket->getSecond()) ValueT(std::move(Value)); 423| 377| return TheBucket; 424| 377| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E20InsertIntoBucketImplERKS2_PS7_: 426| 377| BucketT *InsertIntoBucketImpl(const KeyT &Key, BucketT *TheBucket) { 427| 377| incrementEpoch(); 428| | 429| | // If the load of the hash table is more than 3/4, or if fewer than 1/8 of 430| | // the buckets are empty (meaning that many are filled with tombstones), 431| | // grow the table. 432| | // 433| | // The later case is tricky. For example, if we had one empty bucket with 434| | // tons of tombstones, failing lookups (e.g. for insertion) would have to 435| | // probe almost the entire table until it found the empty bucket. If the 436| | // table completely filled with tombstones, no lookup would ever succeed, 437| | // causing infinite loops in lookup. 438| 377| unsigned NewNumEntries = getNumEntries() + 1; 439| 377| unsigned NumBuckets = getNumBuckets(); 440| 377| if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) { ------------------ | | 172| 377|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 176, False: 201] | | ------------------ ------------------ 441| 176| this->grow(NumBuckets * 2); 442| 176| LookupBucketFor(Key, TheBucket); 443| 176| NumBuckets = getNumBuckets(); 444| 201| } else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <= ------------------ | | 172| 201|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 201] | | ------------------ ------------------ 445| 201| NumBuckets/8)) { 446| 0| this->grow(NumBuckets); 447| 0| LookupBucketFor(Key, TheBucket); 448| 0| } 449| 377| assert(TheBucket); ------------------ | Branch (449:5): [True: 377, False: 0] ------------------ 450| | 451| | // Only update the state after we've grown our bucket space appropriately 452| | // so that when growing buckets we have self-consistent entry count. 453| 377| incrementNumEntries(); 454| | 455| | // If we are writing over a tombstone, remember this. 456| 377| const KeyT EmptyKey = getEmptyKey(); 457| 377| if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey)) ------------------ | Branch (457:9): [True: 0, False: 377] ------------------ 458| 0| decrementNumTombstones(); 459| | 460| 377| return TheBucket; 461| 377| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E4growEj: 391| 176| void grow(unsigned AtLeast) { 392| 176| static_cast(this)->grow(AtLeast); 393| 176| } _ZN7llvm_ks8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEEE4growEj: 621| 176| void grow(unsigned AtLeast) { 622| 176| unsigned OldNumBuckets = NumBuckets; 623| 176| BucketT *OldBuckets = Buckets; 624| | 625| 176| allocateBuckets(std::max(64, static_cast(NextPowerOf2(AtLeast-1)))); 626| 176| assert(Buckets); ------------------ | Branch (626:5): [True: 176, False: 0] ------------------ 627| 176| if (!OldBuckets) { ------------------ | Branch (627:9): [True: 176, False: 0] ------------------ 628| 176| this->BaseT::initEmpty(); 629| 176| return; 630| 176| } 631| | 632| 0| this->moveFromOldBuckets(OldBuckets, OldBuckets+OldNumBuckets); 633| | 634| | // Free the old table. 635| 0| operator delete(OldBuckets); 636| 0| } _ZN7llvm_ks12DenseMapBaseINS_8DenseMapINS_9StringRefEmNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_mEEEES2_mS4_S7_E19incrementNumEntriesEv: 357| 377| void incrementNumEntries() { 358| 377| setNumEntries(getNumEntries() + 1); 359| 377| } _ZNK7llvm_ks16DenseMapIteratorINS_9StringRefEmNS_12DenseMapInfoIS1_EENS_6detail12DenseMapPairIS1_mEELb0EEptEv: 1024| 378| pointer operator->() const { 1025| 378| assert(isHandleInSync() && "invalid iterator access!"); ------------------ | Branch (1025:5): [True: 378, False: 0] | Branch (1025:5): [True: 378, Folded] | Branch (1025:5): [True: 378, False: 0] ------------------ 1026| 378| return Ptr; 1027| 378| } _ZN7llvm_ks12DenseMapInfoINS_9StringRefEE11getEmptyKeyEv: 171| 27.8k| static inline StringRef getEmptyKey() { 172| 27.8k| return StringRef(reinterpret_cast(~static_cast(0)), 173| 27.8k| 0); 174| 27.8k| } _ZN7llvm_ks12DenseMapInfoINS_9StringRefEE15getTombstoneKeyEv: 175| 2.51k| static inline StringRef getTombstoneKey() { 176| 2.51k| return StringRef(reinterpret_cast(~static_cast(1)), 177| 2.51k| 0); 178| 2.51k| } _ZN7llvm_ks12DenseMapInfoINS_9StringRefEE12getHashValueES1_: 179| 378| static unsigned getHashValue(StringRef Val) { 180| 378| assert(Val.data() != getEmptyKey().data() && "Cannot hash the empty key!"); ------------------ | Branch (180:5): [True: 378, False: 0] | Branch (180:5): [True: 378, Folded] | Branch (180:5): [True: 378, False: 0] ------------------ 181| 378| assert(Val.data() != getTombstoneKey().data() && ------------------ | Branch (181:5): [True: 378, False: 0] | Branch (181:5): [True: 378, Folded] | Branch (181:5): [True: 378, False: 0] ------------------ 182| 378| "Cannot hash the tombstone key!"); 183| 378| return (unsigned)(hash_value(Val)); 184| 378| } _ZN7llvm_ks12DenseMapInfoINS_9StringRefEE7isEqualES1_S1_: 185| 13.6k| static bool isEqual(StringRef LHS, StringRef RHS) { 186| 13.6k| if (RHS.data() == getEmptyKey().data()) ------------------ | Branch (186:9): [True: 12.7k, False: 806] ------------------ 187| 12.7k| return LHS.data() == getEmptyKey().data(); 188| 806| if (RHS.data() == getTombstoneKey().data()) ------------------ | Branch (188:9): [True: 780, False: 26] ------------------ 189| 780| return LHS.data() == getTombstoneKey().data(); 190| 26| return LHS == RHS; 191| 806| } _ZN7llvm_ks12DenseMapInfoIPNS_9MCSectionEE11getEmptyKeyEv: 36| 534| static inline T* getEmptyKey() { 37| 534| uintptr_t Val = static_cast(-1); 38| 534| Val <<= PointerLikeTypeTraits::NumLowBitsAvailable; 39| 534| return reinterpret_cast(Val); 40| 534| } _ZN7llvm_ks12DenseMapInfoIPNS_9MCSectionEE15getTombstoneKeyEv: 41| 522| static inline T* getTombstoneKey() { 42| 522| uintptr_t Val = static_cast(-2); 43| 522| Val <<= PointerLikeTypeTraits::NumLowBitsAvailable; 44| 522| return reinterpret_cast(Val); 45| 522| } _ZN7llvm_ks12DenseMapInfoIPNS_9MCSectionEE7isEqualEPKS1_S5_: 50| 1.95k| static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; } _ZN7llvm_ks12DenseMapInfoIPNS_9MCSectionEE12getHashValueEPKS1_: 46| 516| static unsigned getHashValue(const T *PtrVal) { 47| 516| return (unsigned((uintptr_t)PtrVal) >> 4) ^ 48| 516| (unsigned((uintptr_t)PtrVal) >> 9); 49| 516| } _ZN7llvm_ks12DenseMapInfoIPKNS_12MCSectionELFEE11getEmptyKeyEv: 36| 3.64k| static inline T* getEmptyKey() { 37| 3.64k| uintptr_t Val = static_cast(-1); 38| 3.64k| Val <<= PointerLikeTypeTraits::NumLowBitsAvailable; 39| 3.64k| return reinterpret_cast(Val); 40| 3.64k| } _ZN7llvm_ks12DenseMapInfoIPKNS_12MCSectionELFEE15getTombstoneKeyEv: 41| 2.05k| static inline T* getTombstoneKey() { 42| 2.05k| uintptr_t Val = static_cast(-2); 43| 2.05k| Val <<= PointerLikeTypeTraits::NumLowBitsAvailable; 44| 2.05k| return reinterpret_cast(Val); 45| 2.05k| } _ZN7llvm_ks12DenseMapInfoIPKNS_12MCSectionELFEE7isEqualES3_S3_: 50| 82.4k| static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; } _ZN7llvm_ks12DenseMapInfoIPKNS_12MCSectionELFEE12getHashValueES3_: 46| 843| static unsigned getHashValue(const T *PtrVal) { 47| 843| return (unsigned((uintptr_t)PtrVal) >> 4) ^ 48| 843| (unsigned((uintptr_t)PtrVal) >> 9); 49| 843| } _ZN7llvm_ks12DenseMapInfoIPKNS_9MCSectionEE11getEmptyKeyEv: 36| 19.1k| static inline T* getEmptyKey() { 37| 19.1k| uintptr_t Val = static_cast(-1); 38| 19.1k| Val <<= PointerLikeTypeTraits::NumLowBitsAvailable; 39| 19.1k| return reinterpret_cast(Val); 40| 19.1k| } _ZN7llvm_ks12DenseMapInfoIPKNS_9MCSectionEE15getTombstoneKeyEv: 41| 18.8k| static inline T* getTombstoneKey() { 42| 18.8k| uintptr_t Val = static_cast(-2); 43| 18.8k| Val <<= PointerLikeTypeTraits::NumLowBitsAvailable; 44| 18.8k| return reinterpret_cast(Val); 45| 18.8k| } _ZN7llvm_ks12DenseMapInfoIPKNS_9MCSectionEE7isEqualES3_S3_: 50| 68.2k| static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; } _ZN7llvm_ks12DenseMapInfoIPKNS_9MCSectionEE12getHashValueES3_: 46| 18.6k| static unsigned getHashValue(const T *PtrVal) { 47| 18.6k| return (unsigned((uintptr_t)PtrVal) >> 4) ^ 48| 18.6k| (unsigned((uintptr_t)PtrVal) >> 9); 49| 18.6k| } _ZN7llvm_ks12DenseMapInfoIPKNS_11MCSymbolELFEE11getEmptyKeyEv: 36| 162| static inline T* getEmptyKey() { 37| 162| uintptr_t Val = static_cast(-1); 38| 162| Val <<= PointerLikeTypeTraits::NumLowBitsAvailable; 39| 162| return reinterpret_cast(Val); 40| 162| } _ZN7llvm_ks12DenseMapInfoIPKNS_11MCSymbolELFEE15getTombstoneKeyEv: 41| 128| static inline T* getTombstoneKey() { 42| 128| uintptr_t Val = static_cast(-2); 43| 128| Val <<= PointerLikeTypeTraits::NumLowBitsAvailable; 44| 128| return reinterpret_cast(Val); 45| 128| } _ZN7llvm_ks12DenseMapInfoIPKNS_11MCSymbolELFEE7isEqualES3_S3_: 50| 837| static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; } _ZN7llvm_ks12DenseMapInfoIPKNS_11MCSymbolELFEE12getHashValueES3_: 46| 122| static unsigned getHashValue(const T *PtrVal) { 47| 122| return (unsigned((uintptr_t)PtrVal) >> 4) ^ 48| 122| (unsigned((uintptr_t)PtrVal) >> 9); 49| 122| } _ZN7llvm_ks8DenseSetIPNS_9MCSectionENS_12DenseMapInfoIS2_EEEC2Ej: 51| 430| explicit DenseSet(unsigned NumInitBuckets = 0) : TheMap(NumInitBuckets) {} _ZN7llvm_ks8DenseSetIPNS_9MCSectionENS_12DenseMapInfoIS2_EEE5clearEv: 61| 430| void clear() { 62| 430| TheMap.clear(); 63| 430| } _ZN7llvm_ks14DebugEpochBaseD2Ev: 63| 4.83k| ~DebugEpochBase() { incrementEpoch(); } _ZN7llvm_ks14DebugEpochBase14incrementEpochEv: 59| 7.53k| void incrementEpoch() { ++Epoch; } _ZN7llvm_ks14DebugEpochBaseC2Ev: 55| 4.83k| DebugEpochBase() : Epoch(0) {} _ZN7llvm_ks14DebugEpochBase10HandleBaseC2EPKS0_: 81| 1.01k| : EpochAddress(&Parent->Epoch), EpochAtCreation(Parent->Epoch) {} _ZNK7llvm_ks14DebugEpochBase10HandleBase14isHandleInSyncEv: 86| 1.91k| bool isHandleInSync() const { return *EpochAddress == EpochAtCreation; } _ZN7llvm_ks9hash_codeC2Em: 82| 378| hash_code(size_t value) : value(value) {} _ZNK7llvm_ks9hash_codecvmEv: 85| 378| /*explicit*/ operator size_t() const { return value; } _ZN7llvm_ks7hashing6detail7fetch64EPKc: 146| 50|inline uint64_t fetch64(const char *p) { 147| 50| uint64_t result; 148| 50| memcpy(&result, p, sizeof(result)); 149| 50| if (sys::IsBigEndianHost) ------------------ | Branch (149:7): [Folded, False: 50] ------------------ 150| 0| sys::swapByteOrder(result); 151| 50| return result; 152| 50|} _ZN7llvm_ks7hashing6detail7fetch32EPKc: 154| 702|inline uint32_t fetch32(const char *p) { 155| 702| uint32_t result; 156| 702| memcpy(&result, p, sizeof(result)); 157| 702| if (sys::IsBigEndianHost) ------------------ | Branch (157:7): [Folded, False: 702] ------------------ 158| 0| sys::swapByteOrder(result); 159| 702| return result; 160| 702|} _ZN7llvm_ks7hashing6detail6rotateEmm: 171| 25|inline uint64_t rotate(uint64_t val, size_t shift) { 172| | // Avoid shifting by 64: doing so yields an undefined result. 173| 25| return shift == 0 ? val : ((val >> shift) | (val << (64 - shift))); ------------------ | Branch (173:10): [True: 0, False: 25] ------------------ 174| 25|} _ZN7llvm_ks7hashing6detail13hash_16_bytesEmm: 180| 376|inline uint64_t hash_16_bytes(uint64_t low, uint64_t high) { 181| | // Murmur-inspired hashing. 182| 376| const uint64_t kMul = 0x9ddfea08eb382d69ULL; 183| 376| uint64_t a = (low ^ high) * kMul; 184| 376| a ^= (a >> 47); 185| 376| uint64_t b = (high ^ a) * kMul; 186| 376| b ^= (b >> 47); 187| 376| b *= kMul; 188| 376| return b; 189| 376|} _ZN7llvm_ks7hashing6detail15hash_4to8_bytesEPKcmm: 200| 351|inline uint64_t hash_4to8_bytes(const char *s, size_t len, uint64_t seed) { 201| 351| uint64_t a = fetch32(s); 202| 351| return hash_16_bytes(len + (a << 3), seed ^ fetch32(s + len - 4)); 203| 351|} _ZN7llvm_ks7hashing6detail16hash_9to16_bytesEPKcmm: 205| 25|inline uint64_t hash_9to16_bytes(const char *s, size_t len, uint64_t seed) { 206| 25| uint64_t a = fetch64(s); 207| 25| uint64_t b = fetch64(s + len - 8); 208| 25| return hash_16_bytes(seed ^ a, rotate(b + len, len)) ^ b; 209| 25|} _ZN7llvm_ks7hashing6detail10hash_shortEPKcmm: 243| 378|inline uint64_t hash_short(const char *s, size_t length, uint64_t seed) { 244| 378| if (length >= 4 && length <= 8) ------------------ | Branch (244:7): [True: 376, False: 2] | Branch (244:22): [True: 351, False: 25] ------------------ 245| 351| return hash_4to8_bytes(s, length, seed); 246| 27| if (length > 8 && length <= 16) ------------------ | Branch (246:7): [True: 25, False: 2] | Branch (246:21): [True: 25, False: 0] ------------------ 247| 25| return hash_9to16_bytes(s, length, seed); 248| 2| if (length > 16 && length <= 32) ------------------ | Branch (248:7): [True: 0, False: 2] | Branch (248:22): [True: 0, False: 0] ------------------ 249| 0| return hash_17to32_bytes(s, length, seed); 250| 2| if (length > 32) ------------------ | Branch (250:7): [True: 0, False: 2] ------------------ 251| 0| return hash_33to64_bytes(s, length, seed); 252| 2| if (length != 0) ------------------ | Branch (252:7): [True: 0, False: 2] ------------------ 253| 0| return hash_1to3_bytes(s, length, seed); 254| | 255| 2| return k2 ^ seed; 256| 2|} _ZN7llvm_ks7hashing6detail18get_execution_seedEv: 322| 378|inline size_t get_execution_seed() { 323| | // FIXME: This needs to be a per-execution seed. This is just a placeholder 324| | // implementation. Switching to a per-execution seed is likely to flush out 325| | // instability bugs and so will happen as its own commit. 326| | // 327| | // However, if there is a fixed seed override set the first time this is 328| | // called, return that instead of the per-execution seed. 329| 378| const uint64_t seed_prime = 0xff51afd7ed558ccdULL; 330| 378| static size_t seed = fixed_seed_override ? fixed_seed_override ------------------ | Branch (330:24): [True: 0, False: 378] ------------------ 331| 378| : (size_t)seed_prime; 332| 378| return seed; 333| 378|} _ZN7llvm_ks18hash_combine_rangeIPKcEENS_9hash_codeET_S4_: 481| 378|hash_code hash_combine_range(InputIteratorT first, InputIteratorT last) { 482| 378| return ::llvm_ks::hashing::detail::hash_combine_range_impl(first, last); 483| 378|} _ZN7llvm_ks7hashing6detail23hash_combine_range_implIKcEENSt3__19enable_ifIXsr16is_hashable_dataIT_EE5valueENS_9hash_codeEE4typeEPS6_SA_: 449| 378|hash_combine_range_impl(ValueT *first, ValueT *last) { 450| 378| const size_t seed = get_execution_seed(); 451| 378| const char *s_begin = reinterpret_cast(first); 452| 378| const char *s_end = reinterpret_cast(last); 453| 378| const size_t length = std::distance(s_begin, s_end); 454| 378| if (length <= 64) ------------------ | Branch (454:7): [True: 378, False: 0] ------------------ 455| 378| return hash_short(s_begin, length, seed); 456| | 457| 0| const char *s_aligned_end = s_begin + (length & ~63); 458| 0| hash_state state = state.create(s_begin, seed); 459| 0| s_begin += 64; 460| 0| while (s_begin != s_aligned_end) { ------------------ | Branch (460:10): [True: 0, False: 0] ------------------ 461| 0| state.mix(s_begin); 462| 0| s_begin += 64; 463| 0| } 464| 0| if (length & 63) ------------------ | Branch (464:7): [True: 0, False: 0] ------------------ 465| 0| state.mix(s_end - 64); 466| | 467| 0| return state.finalize(length); 468| 378|} _ZN7llvm_ks9MapVectorIPNS_9MCSectionENS_12ConstantPoolENS_8DenseMapIS2_jNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEEENSt3__16vectorINSB_4pairIS2_S3_EENSB_9allocatorISE_EEEEE3endEv: 48| 185| iterator end() { return Vector.end(); } _ZN7llvm_ks9MapVectorIPNS_9MCSectionENS_12ConstantPoolENS_8DenseMapIS2_jNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEEENSt3__16vectorINSB_4pairIS2_S3_EENSB_9allocatorISE_EEEEEixERKS2_: 75| 516| ValueT &operator[](const KeyT &Key) { 76| 516| std::pair Pair = std::make_pair(Key, 0); 77| 516| std::pair Result = Map.insert(Pair); 78| 516| unsigned &I = Result.first->second; 79| 516| if (Result.second) { ------------------ | Branch (79:9): [True: 6, False: 510] ------------------ 80| 6| Vector.push_back(std::make_pair(Key, ValueT())); 81| 6| I = Vector.size() - 1; 82| 6| } 83| 516| return Vector[I].second; 84| 516| } _ZN7llvm_ks9MapVectorIPNS_9MCSectionENS_12ConstantPoolENS_8DenseMapIS2_jNS_12DenseMapInfoIS2_EENS_6detail12DenseMapPairIS2_jEEEENSt3__16vectorINSB_4pairIS2_S3_EENSB_9allocatorISE_EEEEE5beginEv: 46| 185| iterator begin() { return Vector.begin(); } _ZN7llvm_ks14PointerIntPairIPNS_10MCFragmentELj1EjNS_21PointerLikeTypeTraitsIS2_EENS_18PointerIntPairInfoIS2_Lj1ES4_EEE6setIntEj: 66| 11.7k| void setInt(IntType IntVal) { 67| 11.7k| Value = Info::updateInt(Value, static_cast(IntVal)); 68| 11.7k| } _ZN7llvm_ks18PointerIntPairInfoIPNS_10MCFragmentELj1ENS_21PointerLikeTypeTraitsIS2_EEE9updateIntEll: 165| 11.7k| static intptr_t updateInt(intptr_t OrigValue, intptr_t Int) { 166| 11.7k| intptr_t IntWord = static_cast(Int); 167| 11.7k| assert((IntWord & ~IntMask) == 0 && "Integer too large for field"); ------------------ | Branch (167:5): [True: 11.7k, False: 0] | Branch (167:5): [True: 11.7k, Folded] | Branch (167:5): [True: 11.7k, False: 0] ------------------ 168| | 169| | // Preserve all bits other than the ones we are updating. 170| 11.7k| return (OrigValue & ~ShiftedIntMask) | IntWord << IntShift; 171| 11.7k| } _ZNK7llvm_ks14PointerIntPairIPNS_10MCFragmentELj1EjNS_21PointerLikeTypeTraitsIS2_EENS_18PointerIntPairInfoIS2_Lj1ES4_EEE6getIntEv: 58| 11.9k| IntType getInt() const { 59| 11.9k| return (IntType)Info::getInt(Value); 60| 11.9k| } _ZN7llvm_ks18PointerIntPairInfoIPNS_10MCFragmentELj1ENS_21PointerLikeTypeTraitsIS2_EEE6getIntEl: 152| 11.9k| static intptr_t getInt(intptr_t Value) { 153| 11.9k| return (Value >> IntShift) & IntMask; 154| 11.9k| } _ZN7llvm_ks14PointerIntPairIPNS_10MCFragmentELj1EjNS_21PointerLikeTypeTraitsIS2_EENS_18PointerIntPairInfoIS2_Lj1ES4_EEE10setPointerES2_: 62| 7.09k| void setPointer(PointerTy PtrVal) { 63| 7.09k| Value = Info::updatePointer(Value, PtrVal); 64| 7.09k| } _ZN7llvm_ks18PointerIntPairInfoIPNS_10MCFragmentELj1ENS_21PointerLikeTypeTraitsIS2_EEE13updatePointerElS2_: 156| 7.09k| static intptr_t updatePointer(intptr_t OrigValue, PointerT Ptr) { 157| 7.09k| intptr_t PtrWord = 158| 7.09k| reinterpret_cast(PtrTraits::getAsVoidPointer(Ptr)); 159| 7.09k| assert((PtrWord & ~PointerBitMask) == 0 && ------------------ | Branch (159:5): [True: 7.09k, False: 0] | Branch (159:5): [True: 7.09k, Folded] | Branch (159:5): [True: 7.09k, False: 0] ------------------ 160| 7.09k| "Pointer is not sufficiently aligned"); 161| | // Preserve all low bits, just update the pointer. 162| 7.09k| return PtrWord | (OrigValue & ~PointerBitMask); 163| 7.09k| } _ZNK7llvm_ks14PointerIntPairIPNS_10MCFragmentELj1EjNS_21PointerLikeTypeTraitsIS2_EENS_18PointerIntPairInfoIS2_Lj1ES4_EEE10getPointerEv: 56| 24.8k| PointerTy getPointer() const { return Info::getPointer(Value); } _ZN7llvm_ks18PointerIntPairInfoIPNS_10MCFragmentELj1ENS_21PointerLikeTypeTraitsIS2_EEE10getPointerEl: 147| 24.8k| static PointerT getPointer(intptr_t Value) { 148| 24.8k| return PtrTraits::getFromVoidPointer( 149| 24.8k| reinterpret_cast(Value & PointerBitMask)); 150| 24.8k| } _ZN7llvm_ks14PointerIntPairIPNS_10MCFragmentELj1EjNS_21PointerLikeTypeTraitsIS2_EENS_18PointerIntPairInfoIS2_Lj1ES4_EEEC2Ev: 50| 11.7k| PointerIntPair() : Value(0) {} _ZN7llvm_ks14array_lengthofIbLm4EEEmRAT0__T_: 283| 3.44k|LLVM_CONSTEXPR inline size_t array_lengthof(T (&)[N]) { 284| 3.44k| return N; 285| 3.44k|} ARMAsmParser.cpp:_ZN7llvm_ks11make_uniqueIN12_GLOBAL__N_110ARMOperandEJNS2_6KindTyEEEENSt3__19enable_ifIXntsr3std8is_arrayIT_EE5valueENS4_10unique_ptrIS6_NS4_14default_deleteIS6_EEEEE4typeEDpOT0_: 405| 33.6k|make_unique(Args &&... args) { 406| 33.6k| return std::unique_ptr(new T(std::forward(args)...)); 407| 33.6k|} _ZN7llvm_ks14array_lengthofIKNS_15MCFixupKindInfoELm16EEEmRAT0__T_: 283| 20|LLVM_CONSTEXPR inline size_t array_lengthof(T (&)[N]) { 284| 20| return N; 285| 20|} _ZN7llvm_ks9SetVectorIPNS_9MCSectionENSt3__16vectorIS2_NS3_9allocatorIS2_EEEENS_8DenseSetIS2_NS_12DenseMapInfoIS2_EEEEEC2Ev: 53| 430| SetVector() {} _ZN7llvm_ks9SetVectorIPNS_9MCSectionENSt3__16vectorIS2_NS3_9allocatorIS2_EEEENS_8DenseSetIS2_NS_12DenseMapInfoIS2_EEEEE5clearEv: 185| 430| void clear() { 186| 430| set_.clear(); 187| 430| vector_.clear(); 188| 430| } _ZN7llvm_ks19SmallPtrSetImplBaseC2EPPKvj: 72| 430| SmallArray(SmallStorage), CurArray(SmallStorage), CurArraySize(SmallSize) { 73| 430| assert(SmallSize && (SmallSize & (SmallSize-1)) == 0 && ------------------ | Branch (73:5): [True: 430, False: 0] | Branch (73:5): [True: 430, False: 0] | Branch (73:5): [True: 430, Folded] | Branch (73:5): [True: 430, False: 0] ------------------ 74| 430| "Initial size must be a power of two!"); 75| 430| clear(); 76| 430| } _ZN7llvm_ks19SmallPtrSetImplBaseD2Ev: 77| 430| ~SmallPtrSetImplBase() { 78| 430| if (!isSmall()) ------------------ | Branch (78:9): [True: 0, False: 430] ------------------ 79| 0| free(CurArray); 80| 430| } _ZN7llvm_ks19SmallPtrSetImplBase5clearEv: 87| 430| void clear() { 88| | // If the capacity of the array is huge, and the # elements used is small, 89| | // shrink the array. 90| 430| if (!isSmall() && NumElements*4 < CurArraySize && CurArraySize > 32) ------------------ | Branch (90:9): [True: 0, False: 430] | Branch (90:23): [True: 0, False: 0] | Branch (90:55): [True: 0, False: 0] ------------------ 91| 0| return shrink_and_clear(); 92| | 93| | // Fill the array with empty markers. 94| 430| memset(CurArray, -1, CurArraySize*sizeof(void*)); 95| 430| NumElements = 0; 96| 430| NumTombstones = 0; 97| 430| } _ZNK7llvm_ks19SmallPtrSetImplBase9count_impEPKv: 134| 319| bool count_imp(const void * Ptr) const { 135| 319| if (isSmall()) { ------------------ | Branch (135:9): [True: 319, False: 0] ------------------ 136| | // Linear search for the item. 137| 319| for (const void *const *APtr = SmallArray, 138| 319| *const *E = SmallArray+NumElements; APtr != E; ++APtr) ------------------ | Branch (138:59): [True: 0, False: 319] ------------------ 139| 0| if (*APtr == Ptr) ------------------ | Branch (139:13): [True: 0, False: 0] ------------------ 140| 0| return true; 141| 319| return false; 142| 319| } 143| | 144| | // Big set case. 145| 0| return *FindBucketFor(Ptr) == Ptr; 146| 319| } _ZNK7llvm_ks19SmallPtrSetImplBase7isSmallEv: 149| 1.17k| bool isSmall() const { return CurArray == SmallArray; } _ZN7llvm_ks11SmallPtrSetIPKNS_8MCSymbolELj32EEC2Ev: 345| 430| SmallPtrSet() : BaseT(SmallStorage, SmallSizePowTwo) {} _ZN7llvm_ks15SmallPtrSetImplIPKNS_8MCSymbolEEC2EPPKvj: 286| 430| : SmallPtrSetImplBase(SmallStorage, SmallSize) {} _ZNK7llvm_ks15SmallPtrSetImplIPKNS_8MCSymbolEE5countES3_: 308| 319| size_type count(PtrType Ptr) const { 309| 319| return count_imp(PtrTraits::getAsVoidPointer(Ptr)) ? 1 : 0; ------------------ | Branch (309:12): [True: 0, False: 319] ------------------ 310| 319| } _ZN7llvm_ks11SmallStringILj1024EEC2Ev: 28| 430| SmallString() {} _ZNK7llvm_ks11SmallStringILj128EEcvNS_9StringRefEEv: 277| 21.0k| operator StringRef() const { return str(); } _ZNK7llvm_ks11SmallStringILj128EE3strEv: 267| 21.0k| StringRef str() const { return StringRef(this->begin(), this->size()); } _ZN7llvm_ks11SmallStringILj128EEC2Ev: 28| 27.5k| SmallString() {} _ZN7llvm_ks11SmallStringILj128EEC2ENS_9StringRefE: 31| 11.2k| SmallString(StringRef S) : SmallVector(S.begin(), S.end()) {} _ZN7llvm_ks11SmallStringILj64EEC2Ev: 28| 143| SmallString() {} _ZN7llvm_ks11SmallStringILj64EEpLENS_9StringRefE: 285| 286| SmallString &operator+=(StringRef RHS) { 286| 286| this->append(RHS.begin(), RHS.end()); 287| 286| return *this; 288| 286| } _ZN7llvm_ks11SmallStringILj64EE6appendIPKcEEvT_S5_: 74| 286| void append(in_iter S, in_iter E) { 75| 286| SmallVectorImpl::append(S, E); 76| 286| } _ZNK7llvm_ks11SmallStringILj64EEcvNS_9StringRefEEv: 277| 143| operator StringRef() const { return str(); } _ZNK7llvm_ks11SmallStringILj64EE3strEv: 267| 143| StringRef str() const { return StringRef(this->begin(), this->size()); } _ZN7llvm_ks11SmallStringILj256EEC2Ev: 28| 11.1k| SmallString() {} _ZN7llvm_ks15SmallVectorImplIcED2Ev: 368| 63.4k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 63.4k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 63.4k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 152, False: 63.2k] ------------------ 374| 152| free(this->begin()); 375| 63.4k| } _ZN7llvm_ks23SmallVectorTemplateBaseIcLb1EE13destroy_rangeEPcS2_: 284| 64.3k| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonIcvE5beginEv: 113| 94.0k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonIcvE3endEv: 117| 283k| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIcvE7isSmallEv: 86| 63.4k| bool isSmall() const { 87| 63.4k| return BeginX == static_cast(&FirstEl); 88| 63.4k| } _ZNK7llvm_ks25SmallVectorTemplateCommonIcvE4sizeEv: 132| 74.6k| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonIcvE3endEv: 119| 85.9k| const_iterator end() const { return (const_iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIcvE5beginEv: 115| 120k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonIcvE4dataEv: 139| 4.24k| pointer data() { return pointer(begin()); } _ZN7llvm_ks11SmallVectorIcLj1024EEC2Ev: 872| 430| SmallVector() : SmallVectorImpl(N) { 873| 430| } _ZN7llvm_ks15SmallVectorImplIcEC2Ej: 364| 63.4k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 63.4k| } _ZN7llvm_ks23SmallVectorTemplateBaseIcLb1EEC2Em: 281| 63.4k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonIcvEC2Em: 78| 63.4k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks15SmallVectorBaseC2EPvm: 40| 193k| : BeginX(FirstEl), EndX(FirstEl), CapacityX((char*)FirstEl+Size) {} _ZNK7llvm_ks15SmallVectorBase13size_in_bytesEv: 48| 608| size_t size_in_bytes() const { 49| 608| return size_t((char*)EndX - (char*)BeginX); 50| 608| } _ZNK7llvm_ks15SmallVectorBase17capacity_in_bytesEv: 53| 608| size_t capacity_in_bytes() const { 54| 608| return size_t((char*)CapacityX - (char*)BeginX); 55| 608| } _ZNK7llvm_ks15SmallVectorBase5emptyEv: 57| 983k| bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const { return BeginX == EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIcvE4dataEv: 141| 1.76k| const_pointer data() const { return const_pointer(begin()); } _ZN7llvm_ks23SmallVectorTemplateBaseINS_9MCOperandELb1EE13destroy_rangeEPS1_S3_: 284| 6.12k| static void destroy_range(T *, T *) {} _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE7isSmallEv: 86| 3.37k| bool isSmall() const { 87| 3.37k| return BeginX == static_cast(&FirstEl); 88| 3.37k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvEixEm: 149| 6.36k| const_reference operator[](size_type idx) const { 150| 6.36k| assert(idx < size()); ------------------ | Branch (150:5): [True: 6.36k, False: 0] ------------------ 151| 6.36k| return begin()[idx]; 152| 6.36k| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvEixEm: 144| 15.4k| reference operator[](size_type idx) { 145| 15.4k| assert(idx < size()); ------------------ | Branch (145:5): [True: 15.4k, False: 0] ------------------ 146| 15.4k| return begin()[idx]; 147| 15.4k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE4sizeEv: 132| 26.5k| size_type size() const { return end()-begin(); } _ZN7llvm_ks23SmallVectorTemplateBaseINS_9MCOperandELb1EE9push_backERKS1_: 337| 11.2k| void push_back(const T &Elt) { 338| 11.2k| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 11.2k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 11.2k] | | ------------------ ------------------ 339| 0| this->grow(); 340| 11.2k| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 11.2k| this->setEnd(this->end()+1); 342| 11.2k| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE6setEndEPS1_: 95| 12.2k| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks15SmallVectorImplINS_9MCOperandEE5clearEv: 378| 2.57k| void clear() { 379| 2.57k| this->destroy_range(this->begin(), this->end()); 380| 2.57k| this->EndX = this->BeginX; 381| 2.57k| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE5beginEv: 113| 23.3k| iterator begin() { return (iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE5beginEv: 115| 35.0k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE3endEv: 117| 28.5k| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE3endEv: 119| 27.4k| const_iterator end() const { return (const_iterator)this->EndX; } _ZN7llvm_ks23SmallVectorTemplateBaseINS_7MCFixupELb1EE13destroy_rangeEPS1_S3_: 284| 3.06k| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE5beginEv: 113| 4.77k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE3endEv: 117| 5.92k| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE7isSmallEv: 86| 3.01k| bool isSmall() const { 87| 3.01k| return BeginX == static_cast(&FirstEl); 88| 3.01k| } _ZN7llvm_ks15SmallVectorImplINS_9MCOperandEEaSERKS2_: 739| 1.07k| operator=(const SmallVectorImpl &RHS) { 740| | // Avoid self-assignment. 741| 1.07k| if (this == &RHS) return *this; ------------------ | Branch (741:7): [True: 0, False: 1.07k] ------------------ 742| | 743| | // If we already have sufficient space, assign the common elements, then 744| | // destroy any excess. 745| 1.07k| size_t RHSSize = RHS.size(); 746| 1.07k| size_t CurSize = this->size(); 747| 1.07k| if (CurSize >= RHSSize) { ------------------ | Branch (747:7): [True: 177, False: 896] ------------------ 748| | // Assign common elements. 749| 177| iterator NewEnd; 750| 177| if (RHSSize) ------------------ | Branch (750:9): [True: 177, False: 0] ------------------ 751| 177| NewEnd = std::copy(RHS.begin(), RHS.begin()+RHSSize, this->begin()); 752| 0| else 753| 0| NewEnd = this->begin(); 754| | 755| | // Destroy excess elements. 756| 177| this->destroy_range(NewEnd, this->end()); 757| | 758| | // Trim. 759| 177| this->setEnd(NewEnd); 760| 177| return *this; 761| 177| } 762| | 763| | // If we have to grow to have enough elements, destroy the current elements. 764| | // This allows us to avoid copying them during the grow. 765| | // FIXME: don't do this if they're efficiently moveable. 766| 896| if (this->capacity() < RHSSize) { ------------------ | Branch (766:7): [True: 0, False: 896] ------------------ 767| | // Destroy current elements. 768| 0| this->destroy_range(this->begin(), this->end()); 769| 0| this->setEnd(this->begin()); 770| 0| CurSize = 0; 771| 0| this->grow(RHSSize); 772| 896| } else if (CurSize) { ------------------ | Branch (772:14): [True: 0, False: 896] ------------------ 773| | // Otherwise, use assignment for the already-constructed elements. 774| 0| std::copy(RHS.begin(), RHS.begin()+CurSize, this->begin()); 775| 0| } 776| | 777| | // Copy construct the new elements in place. 778| 896| this->uninitialized_copy(RHS.begin()+CurSize, RHS.end(), 779| 896| this->begin()+CurSize); 780| | 781| | // Set end. 782| 896| this->setEnd(this->begin()+RHSSize); 783| 896| return *this; 784| 1.07k|} _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE8capacityEv: 136| 896| size_t capacity() const { return capacity_ptr() - begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvE12capacity_ptrEv: 122| 896| const_iterator capacity_ptr() const { return (const_iterator)this->CapacityX;} _ZN7llvm_ks23SmallVectorTemplateBaseINS_9MCOperandELb1EE18uninitialized_copyIKS1_S1_EEvPT_S6_PT0_PNSt3__19enable_ifIXsr3std7is_sameINS9_12remove_constIS5_E4typeES7_EE5valueEvE4typeE: 322| 896| T2>::value>::type * = nullptr) { 323| | // Use memcpy for PODs iterated by pointers (which includes SmallVector 324| | // iterators): std::uninitialized_copy optimizes to memmove, but we can 325| | // use memcpy here. Note that I and E are iterators and thus might be 326| | // invalid for memcpy if they are equal. 327| 896| if (I != E) ------------------ | Branch (327:9): [True: 896, False: 0] ------------------ 328| 896| memcpy(Dest, I, (E - I) * sizeof(T)); 329| 896| } _ZN7llvm_ks11SmallVectorINS_9MCOperandELj8EEaSERKS2_: 900| 223| const SmallVector &operator=(const SmallVector &RHS) { 901| 223| SmallVectorImpl::operator=(RHS); 902| 223| return *this; 903| 223| } _ZN7llvm_ks23SmallVectorTemplateBaseIcLb1EE9push_backERKc: 337| 143| void push_back(const T &Elt) { 338| 143| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 143|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 143] | | ------------------ ------------------ 339| 0| this->grow(); 340| 143| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 143| this->setEnd(this->end()+1); 342| 143| } _ZN7llvm_ks23SmallVectorTemplateBaseIcLb1EE4growEm: 333| 260| void grow(size_t MinSize = 0) { 334| 260| this->grow_pod(MinSize*sizeof(T), sizeof(T)); 335| 260| } _ZN7llvm_ks25SmallVectorTemplateCommonIcvE8grow_podEmm: 80| 260| void grow_pod(size_t MinSizeInBytes, size_t TSize) { 81| 260| SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize); 82| 260| } _ZN7llvm_ks25SmallVectorTemplateCommonIcvE6setEndEPc: 95| 83.8k| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_8MCSymbolEvE3endEv: 117| 13.8k| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_8MCSymbolELb1EE4growEm: 333| 130| void grow(size_t MinSize = 0) { 334| 130| this->grow_pod(MinSize*sizeof(T), sizeof(T)); 335| 130| } _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_8MCSymbolEvE8grow_podEmm: 80| 130| void grow_pod(size_t MinSizeInBytes, size_t TSize) { 81| 130| SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize); 82| 130| } _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_8MCSymbolEvE6setEndEPS2_: 95| 5.83k| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_8MCSymbolELb1EE13destroy_rangeEPS2_S4_: 284| 1.28k| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_8MCSymbolEvE5beginEv: 113| 2.16k| iterator begin() { return (iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIPNS_8MCSymbolEvE7isSmallEv: 86| 430| bool isSmall() const { 87| 430| return BeginX == static_cast(&FirstEl); 88| 430| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_14MCLOHDirectiveELb0EE13destroy_rangeEPS1_S3_: 180| 430| static void destroy_range(T *S, T *E) { 181| 430| while (S != E) { ------------------ | Branch (181:12): [True: 0, False: 430] ------------------ 182| 0| --E; 183| 0| E->~T(); 184| 0| } 185| 430| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_14MCLOHDirectiveEvE5beginEv: 113| 430| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_14MCLOHDirectiveEvE3endEv: 117| 430| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_14MCLOHDirectiveEvE7isSmallEv: 86| 430| bool isSmall() const { 87| 430| return BeginX == static_cast(&FirstEl); 88| 430| } _ZN7llvm_ks15SmallVectorImplIPNS_8MCSymbolEE5clearEv: 378| 852| void clear() { 379| 852| this->destroy_range(this->begin(), this->end()); 380| 852| this->EndX = this->BeginX; 381| 852| } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEvE4backEv: 167| 95.1k| const_reference back() const { 168| 95.1k| assert(!empty()); ------------------ | Branch (168:5): [True: 95.1k, False: 0] ------------------ 169| 95.1k| return end()[-1]; 170| 95.1k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEvE3endEv: 119| 95.1k| const_iterator end() const { return (const_iterator)this->EndX; } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EELb1EE9push_backERKS9_: 337| 430| void push_back(const T &Elt) { 338| 430| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 430|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 430] | | ------------------ ------------------ 339| 0| this->grow(); 340| 430| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 430| this->setEnd(this->end()+1); 342| 430| } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEvE6setEndEPS9_: 95| 430| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEvE3endEv: 117| 2.88k| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEvE4backEv: 163| 1.59k| reference back() { 164| 1.59k| assert(!empty()); ------------------ | Branch (164:5): [True: 1.59k, False: 0] ------------------ 165| 1.59k| return end()[-1]; 166| 1.59k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvE5beginEv: 115| 21.6k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvE4sizeEv: 132| 21.6k| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvE3endEv: 119| 21.6k| const_iterator end() const { return (const_iterator)this->EndX; } _ZN7llvm_ks15SmallVectorImplIcE5clearEv: 378| 860| void clear() { 379| 860| this->destroy_range(this->begin(), this->end()); 380| 860| this->EndX = this->BeginX; 381| 860| } _ZN7llvm_ks15SmallVectorImplIcE6appendIPKcEEvT_S5_: 423| 69.9k| void append(in_iter in_start, in_iter in_end) { 424| 69.9k| size_type NumInputs = std::distance(in_start, in_end); 425| | // Grow allocated space if needed. 426| 69.9k| if (NumInputs > size_type(this->capacity_ptr()-this->end())) ------------------ | Branch (426:9): [True: 155, False: 69.7k] ------------------ 427| 155| this->grow(this->size()+NumInputs); 428| | 429| | // Copy the new elements over. 430| 69.9k| this->uninitialized_copy(in_start, in_end, this->end()); 431| 69.9k| this->setEnd(this->end() + NumInputs); 432| 69.9k| } _ZN7llvm_ks25SmallVectorTemplateCommonIcvE12capacity_ptrEv: 121| 72.1k| iterator capacity_ptr() { return (iterator)this->CapacityX; } _ZN7llvm_ks23SmallVectorTemplateBaseIcLb1EE18uninitialized_copyIKccEEvPT_S5_PT0_PNSt3__19enable_ifIXsr3std7is_sameINS8_12remove_constIS4_E4typeES6_EE5valueEvE4typeE: 322| 81.2k| T2>::value>::type * = nullptr) { 323| | // Use memcpy for PODs iterated by pointers (which includes SmallVector 324| | // iterators): std::uninitialized_copy optimizes to memmove, but we can 325| | // use memcpy here. Note that I and E are iterators and thus might be 326| | // invalid for memcpy if they are equal. 327| 81.2k| if (I != E) ------------------ | Branch (327:9): [True: 81.1k, False: 65] ------------------ 328| 81.1k| memcpy(Dest, I, (E - I) * sizeof(T)); 329| 81.2k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairIPvmEELb1EE9push_backERKS4_: 337| 10| void push_back(const T &Elt) { 338| 10| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 10|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 10, False: 0] | | ------------------ ------------------ 339| 10| this->grow(); 340| 10| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 10| this->setEnd(this->end()+1); 342| 10| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairIPvmEELb1EE4growEm: 333| 10| void grow(size_t MinSize = 0) { 334| 10| this->grow_pod(MinSize*sizeof(T), sizeof(T)); 335| 10| } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIPvmEEvE8grow_podEmm: 80| 10| void grow_pod(size_t MinSizeInBytes, size_t TSize) { 81| 10| SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize); 82| 10| } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIPvmEEvE3endEv: 117| 16.3k| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIPvmEEvE6setEndEPS4_: 95| 10| void setEnd(T *P) { this->EndX = P; } _ZNK7llvm_ks25SmallVectorTemplateCommonIPvvE4sizeEv: 132| 2.11k| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonIPvvE3endEv: 119| 2.11k| const_iterator end() const { return (const_iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIPvvE5beginEv: 115| 2.11k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZN7llvm_ks23SmallVectorTemplateBaseIPvLb1EE9push_backERKS1_: 337| 2.11k| void push_back(const T &Elt) { 338| 2.11k| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 2.11k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 31, False: 2.08k] | | ------------------ ------------------ 339| 31| this->grow(); 340| 2.11k| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 2.11k| this->setEnd(this->end()+1); 342| 2.11k| } _ZN7llvm_ks23SmallVectorTemplateBaseIPvLb1EE4growEm: 333| 31| void grow(size_t MinSize = 0) { 334| 31| this->grow_pod(MinSize*sizeof(T), sizeof(T)); 335| 31| } _ZN7llvm_ks25SmallVectorTemplateCommonIPvvE8grow_podEmm: 80| 31| void grow_pod(size_t MinSizeInBytes, size_t TSize) { 81| 31| SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize); 82| 31| } _ZN7llvm_ks25SmallVectorTemplateCommonIPvvE3endEv: 117| 21.5k| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks25SmallVectorTemplateCommonIPvvE6setEndEPS1_: 95| 3.48k| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvE5beginEv: 113| 761k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks15SmallVectorImplINS_8AsmTokenEE5eraseEPS1_: 462| 253k| iterator erase(iterator I) { 463| 253k| assert(I >= this->begin() && "Iterator to erase is out of bounds."); ------------------ | Branch (463:5): [True: 253k, False: 0] | Branch (463:5): [True: 253k, Folded] | Branch (463:5): [True: 253k, False: 0] ------------------ 464| 253k| assert(I < this->end() && "Erasing at past-the-end iterator."); ------------------ | Branch (464:5): [True: 253k, False: 0] | Branch (464:5): [True: 253k, Folded] | Branch (464:5): [True: 253k, False: 0] ------------------ 465| | 466| 253k| iterator N = I; 467| | // Shift all elts down one. 468| 253k| this->move(I+1, this->end(), I); 469| | // Drop the last elt. 470| 253k| this->pop_back(); 471| 253k| return(N); 472| 253k| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvE3endEv: 117| 1.52M| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks23SmallVectorTemplateBaseINS_8AsmTokenELb0EE4moveIPS1_S4_EET0_T_S6_S5_: 191| 253k| static It2 move(It1 I, It1 E, It2 Dest) { 192| 253k| for (; I != E; ++I, ++Dest) ------------------ | Branch (192:12): [True: 0, False: 253k] ------------------ 193| 0| *Dest = ::std::move(*I); 194| 253k| return Dest; 195| 253k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_8AsmTokenELb0EE8pop_backEv: 243| 253k| void pop_back() { 244| 253k| this->setEnd(this->end()-1); 245| 253k| this->end()->~T(); 246| 253k| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvE6setEndEPS1_: 95| 508k| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks15SmallVectorImplINS_8AsmTokenEE12emplace_backIJS1_EEEvDpOT_: 659| 253k| template void emplace_back(ArgTypes &&... Args) { 660| 253k| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 253k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 253k] | | ------------------ ------------------ 661| 0| this->grow(); 662| 253k| ::new ((void *)this->end()) T(std::forward(Args)...); 663| 253k| this->setEnd(this->end() + 1); 664| 253k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvE5beginEv: 115| 2.24M| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvE4sizeEv: 132| 1.12M| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvE3endEv: 119| 1.12M| const_iterator end() const { return (const_iterator)this->EndX; } _ZN7llvm_ks23SmallVectorTemplateBaseINS_8AsmTokenELb0EE13destroy_rangeEPS1_S3_: 180| 430| static void destroy_range(T *S, T *E) { 181| 860| while (S != E) { ------------------ | Branch (181:12): [True: 430, False: 430] ------------------ 182| 430| --E; 183| 430| E->~T(); 184| 430| } 185| 430| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvE7isSmallEv: 86| 430| bool isSmall() const { 87| 430| return BeginX == static_cast(&FirstEl); 88| 430| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvE5frontEv: 154| 253k| reference front() { 155| 253k| assert(!empty()); ------------------ | Branch (155:5): [True: 253k, False: 0] ------------------ 156| 253k| return begin()[0]; 157| 253k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvEixEm: 149| 1.12M| const_reference operator[](size_type idx) const { 150| 1.12M| assert(idx < size()); ------------------ | Branch (150:5): [True: 1.12M, False: 0] ------------------ 151| 1.12M| return begin()[idx]; 152| 1.12M| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_7SMFixItELb0EE13destroy_rangeEPS1_S3_: 180| 2.47k| static void destroy_range(T *S, T *E) { 181| 2.47k| while (S != E) { ------------------ | Branch (181:12): [True: 0, False: 2.47k] ------------------ 182| 0| --E; 183| 0| E->~T(); 184| 0| } 185| 2.47k| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE5beginEv: 113| 4.95k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE3endEv: 117| 12.3k| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE7isSmallEv: 86| 2.47k| bool isSmall() const { 87| 2.47k| return BeginX == static_cast(&FirstEl); 88| 2.47k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE5beginEv: 115| 3.01k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE4sizeEv: 132| 1.50k| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE3endEv: 119| 1.50k| const_iterator end() const { return (const_iterator)this->EndX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE6setEndEPS1_: 95| 2.47k| void setEnd(T *P) { this->EndX = P; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE4dataEv: 141| 1.50k| const_pointer data() const { return const_pointer(begin()); } _ZN7llvm_ks11SmallVectorIcLj128EEC2Ev: 872| 27.5k| SmallVector() : SmallVectorImpl(N) { 873| 27.5k| } _ZN7llvm_ks11SmallVectorIPvLj4EEC2Ev: 872| 2.58k| SmallVector() : SmallVectorImpl(N) { 873| 2.58k| } _ZN7llvm_ks15SmallVectorImplIPvEC2Ej: 364| 2.58k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 2.58k| } _ZN7llvm_ks23SmallVectorTemplateBaseIPvLb1EEC2Em: 281| 2.58k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonIPvvEC2Em: 78| 2.58k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks11SmallVectorINSt3__14pairIPvmEELj0EEC2Ev: 872| 2.58k| SmallVector() : SmallVectorImpl(N) { 873| 2.58k| } _ZN7llvm_ks15SmallVectorImplINSt3__14pairIPvmEEEC2Ej: 364| 2.58k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 2.58k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairIPvmEELb1EEC2Em: 281| 2.58k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIPvmEEvEC2Em: 78| 2.58k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks15SmallVectorImplIPvED2Ev: 368| 2.58k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 2.58k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 2.58k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 25, False: 2.55k] ------------------ 374| 25| free(this->begin()); 375| 2.58k| } _ZN7llvm_ks23SmallVectorTemplateBaseIPvLb1EE13destroy_rangeEPS1_S3_: 284| 3.95k| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonIPvvE5beginEv: 113| 18.1k| iterator begin() { return (iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIPvvE7isSmallEv: 86| 2.58k| bool isSmall() const { 87| 2.58k| return BeginX == static_cast(&FirstEl); 88| 2.58k| } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIPvmEEvE5beginEv: 113| 16.3k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks15SmallVectorImplINSt3__14pairIPvmEEED2Ev: 368| 2.58k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 2.58k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 2.58k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 6, False: 2.57k] ------------------ 374| 6| free(this->begin()); 375| 2.58k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairIPvmEELb1EE13destroy_rangeEPS4_S6_: 284| 6.45k| static void destroy_range(T *, T *) {} _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIPvmEEvE7isSmallEv: 86| 2.58k| bool isSmall() const { 87| 2.58k| return BeginX == static_cast(&FirstEl); 88| 2.58k| } _ZN7llvm_ks25SmallVectorTemplateCommonIPvvE4backEv: 163| 1.88k| reference back() { 164| 1.88k| assert(!empty()); ------------------ | Branch (164:5): [True: 1.88k, False: 0] ------------------ 165| 1.88k| return end()[-1]; 166| 1.88k| } _ZN7llvm_ks15SmallVectorImplINSt3__14pairIPvmEEE5clearEv: 378| 3.87k| void clear() { 379| 3.87k| this->destroy_range(this->begin(), this->end()); 380| 3.87k| this->EndX = this->BeginX; 381| 3.87k| } _ZN7llvm_ks25SmallVectorTemplateCommonIPvvE5frontEv: 154| 1.37k| reference front() { 155| 1.37k| assert(!empty()); ------------------ | Branch (155:5): [True: 1.37k, False: 0] ------------------ 156| 1.37k| return begin()[0]; 157| 1.37k| } _ZN7llvm_ks15SmallVectorImplIPvE5eraseEPS1_S3_: 474| 1.37k| iterator erase(iterator S, iterator E) { 475| 1.37k| assert(S >= this->begin() && "Range to erase is out of bounds."); ------------------ | Branch (475:5): [True: 1.37k, False: 0] | Branch (475:5): [True: 1.37k, Folded] | Branch (475:5): [True: 1.37k, False: 0] ------------------ 476| 1.37k| assert(S <= E && "Trying to erase invalid range."); ------------------ | Branch (476:5): [True: 1.37k, False: 0] | Branch (476:5): [True: 1.37k, Folded] | Branch (476:5): [True: 1.37k, False: 0] ------------------ 477| 1.37k| assert(E <= this->end() && "Trying to erase past the end."); ------------------ | Branch (477:5): [True: 1.37k, False: 0] | Branch (477:5): [True: 1.37k, Folded] | Branch (477:5): [True: 1.37k, False: 0] ------------------ 478| | 479| 1.37k| iterator N = S; 480| | // Shift all elts down. 481| 1.37k| iterator I = this->move(E, this->end(), S); 482| | // Drop the last elts. 483| 1.37k| this->destroy_range(I, this->end()); 484| 1.37k| this->setEnd(I); 485| 1.37k| return(N); 486| 1.37k| } _ZN7llvm_ks23SmallVectorTemplateBaseIPvLb1EE4moveIPS1_S4_EET0_T_S6_S5_: 289| 1.37k| static It2 move(It1 I, It1 E, It2 Dest) { 290| 1.37k| return ::std::copy(I, E, Dest); 291| 1.37k| } _ZN7llvm_ks11SmallVectorIcLj128EEC2IPKcEET_S5_: 881| 11.2k| SmallVector(ItTy S, ItTy E) : SmallVectorImpl(N) { 882| 11.2k| this->append(S, E); 883| 11.2k| } _ZN7llvm_ks15SmallVectorImplIcE6resizeEm: 383| 5.46k| void resize(size_type N) { 384| 5.46k| if (N < this->size()) { ------------------ | Branch (384:9): [True: 0, False: 5.46k] ------------------ 385| 0| this->destroy_range(this->begin()+N, this->end()); 386| 0| this->setEnd(this->begin()+N); 387| 5.46k| } else if (N > this->size()) { ------------------ | Branch (387:16): [True: 0, False: 5.46k] ------------------ 388| 0| if (this->capacity() < N) ------------------ | Branch (388:11): [True: 0, False: 0] ------------------ 389| 0| this->grow(N); 390| 0| for (auto I = this->end(), E = this->begin() + N; I != E; ++I) ------------------ | Branch (390:57): [True: 0, False: 0] ------------------ 391| 0| new (&*I) T(); 392| 0| this->setEnd(this->begin()+N); 393| 0| } 394| 5.46k| } _ZNK7llvm_ks25SmallVectorTemplateCommonIcvE8capacityEv: 136| 11.4k| size_t capacity() const { return capacity_ptr() - begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonIcvE12capacity_ptrEv: 122| 11.4k| const_iterator capacity_ptr() const { return (const_iterator)this->CapacityX;} _ZN7llvm_ks11SmallVectorIcLj128EEC2ERKS1_: 895| 11.2k| SmallVector(const SmallVector &RHS) : SmallVectorImpl(N) { 896| 11.2k| if (!RHS.empty()) ------------------ | Branch (896:9): [True: 11.2k, False: 0] ------------------ 897| 11.2k| SmallVectorImpl::operator=(RHS); 898| 11.2k| } _ZN7llvm_ks15SmallVectorImplIcEaSERKS1_: 739| 11.3k| operator=(const SmallVectorImpl &RHS) { 740| | // Avoid self-assignment. 741| 11.3k| if (this == &RHS) return *this; ------------------ | Branch (741:7): [True: 0, False: 11.3k] ------------------ 742| | 743| | // If we already have sufficient space, assign the common elements, then 744| | // destroy any excess. 745| 11.3k| size_t RHSSize = RHS.size(); 746| 11.3k| size_t CurSize = this->size(); 747| 11.3k| if (CurSize >= RHSSize) { ------------------ | Branch (747:7): [True: 0, False: 11.3k] ------------------ 748| | // Assign common elements. 749| 0| iterator NewEnd; 750| 0| if (RHSSize) ------------------ | Branch (750:9): [True: 0, False: 0] ------------------ 751| 0| NewEnd = std::copy(RHS.begin(), RHS.begin()+RHSSize, this->begin()); 752| 0| else 753| 0| NewEnd = this->begin(); 754| | 755| | // Destroy excess elements. 756| 0| this->destroy_range(NewEnd, this->end()); 757| | 758| | // Trim. 759| 0| this->setEnd(NewEnd); 760| 0| return *this; 761| 0| } 762| | 763| | // If we have to grow to have enough elements, destroy the current elements. 764| | // This allows us to avoid copying them during the grow. 765| | // FIXME: don't do this if they're efficiently moveable. 766| 11.3k| if (this->capacity() < RHSSize) { ------------------ | Branch (766:7): [True: 57, False: 11.2k] ------------------ 767| | // Destroy current elements. 768| 57| this->destroy_range(this->begin(), this->end()); 769| 57| this->setEnd(this->begin()); 770| 57| CurSize = 0; 771| 57| this->grow(RHSSize); 772| 11.2k| } else if (CurSize) { ------------------ | Branch (772:14): [True: 46, False: 11.2k] ------------------ 773| | // Otherwise, use assignment for the already-constructed elements. 774| 46| std::copy(RHS.begin(), RHS.begin()+CurSize, this->begin()); 775| 46| } 776| | 777| | // Copy construct the new elements in place. 778| 11.3k| this->uninitialized_copy(RHS.begin()+CurSize, RHS.end(), 779| 11.3k| this->begin()+CurSize); 780| | 781| | // Set end. 782| 11.3k| this->setEnd(this->begin()+RHSSize); 783| 11.3k| return *this; 784| 11.3k|} _ZN7llvm_ks11SmallVectorIcLj64EEC2Ev: 872| 143| SmallVector() : SmallVectorImpl(N) { 873| 143| } _ZN7llvm_ks23SmallVectorTemplateBaseIcLb1EE18uninitialized_copyIccEEvPT_S4_PT0_PNSt3__19enable_ifIXsr3std7is_sameINS7_12remove_constIS3_E4typeES5_EE5valueEvE4typeE: 322| 2.19k| T2>::value>::type * = nullptr) { 323| | // Use memcpy for PODs iterated by pointers (which includes SmallVector 324| | // iterators): std::uninitialized_copy optimizes to memmove, but we can 325| | // use memcpy here. Note that I and E are iterators and thus might be 326| | // invalid for memcpy if they are equal. 327| 2.19k| if (I != E) ------------------ | Branch (327:9): [True: 2.19k, False: 0] ------------------ 328| 2.19k| memcpy(Dest, I, (E - I) * sizeof(T)); 329| 2.19k| } _ZN7llvm_ks15SmallVectorImplIPNS_14MCDataFragmentEED2Ev: 368| 430| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 430| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 430| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 430] ------------------ 374| 0| free(this->begin()); 375| 430| } _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_14MCDataFragmentELb1EE13destroy_rangeEPS2_S4_: 284| 430| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_14MCDataFragmentEvE5beginEv: 113| 430| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_14MCDataFragmentEvE3endEv: 117| 430| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIPNS_14MCDataFragmentEvE7isSmallEv: 86| 430| bool isSmall() const { 87| 430| return BeginX == static_cast(&FirstEl); 88| 430| } _ZN7llvm_ks11SmallVectorIcLj32EEC2Ev: 872| 779| SmallVector() : SmallVectorImpl(N) { 873| 779| } _ZN7llvm_ks15SmallVectorImplINS_7MCFixupEED2Ev: 368| 3.01k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 3.01k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 3.01k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 5, False: 3.01k] ------------------ 374| 5| free(this->begin()); 375| 3.01k| } _ZN7llvm_ks11SmallVectorIPNS_14MCDataFragmentELj4EEC2Ev: 872| 430| SmallVector() : SmallVectorImpl(N) { 873| 430| } _ZN7llvm_ks15SmallVectorImplIPNS_14MCDataFragmentEEC2Ej: 364| 430| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 430| } _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_14MCDataFragmentELb1EEC2Em: 281| 430| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_14MCDataFragmentEvEC2Em: 78| 430| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks11SmallVectorIcLj256EEC2Ev: 872| 11.1k| SmallVector() : SmallVectorImpl(N) { 873| 11.1k| } _ZN7llvm_ks15SmallVectorImplIcE6appendIPcEEvT_S4_: 423| 2.19k| void append(in_iter in_start, in_iter in_end) { 424| 2.19k| size_type NumInputs = std::distance(in_start, in_end); 425| | // Grow allocated space if needed. 426| 2.19k| if (NumInputs > size_type(this->capacity_ptr()-this->end())) ------------------ | Branch (426:9): [True: 46, False: 2.14k] ------------------ 427| 46| this->grow(this->size()+NumInputs); 428| | 429| | // Copy the new elements over. 430| 2.19k| this->uninitialized_copy(in_start, in_end, this->end()); 431| 2.19k| this->setEnd(this->end() + NumInputs); 432| 2.19k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE4sizeEv: 132| 6.36k| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE3endEv: 119| 7.02k| const_iterator end() const { return (const_iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE5beginEv: 115| 8.14k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvEixEm: 144| 1.70k| reference operator[](size_type idx) { 145| 1.70k| assert(idx < size()); ------------------ | Branch (145:5): [True: 1.70k, False: 0] ------------------ 146| 1.70k| return begin()[idx]; 147| 1.70k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_7MCFixupELb1EE9push_backERKS1_: 337| 1.43k| void push_back(const T &Elt) { 338| 1.43k| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 1.43k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 18, False: 1.41k] | | ------------------ ------------------ 339| 18| this->grow(); 340| 1.43k| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 1.43k| this->setEnd(this->end()+1); 342| 1.43k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_7MCFixupELb1EE4growEm: 333| 18| void grow(size_t MinSize = 0) { 334| 18| this->grow_pod(MinSize*sizeof(T), sizeof(T)); 335| 18| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE8grow_podEmm: 80| 18| void grow_pod(size_t MinSizeInBytes, size_t TSize) { 81| 18| SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize); 82| 18| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE6setEndEPS1_: 95| 1.47k| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks11SmallVectorINS_7MCFixupELj4EEC2Ev: 872| 2.16k| SmallVector() : SmallVectorImpl(N) { 873| 2.16k| } _ZN7llvm_ks15SmallVectorImplINS_7MCFixupEEC2Ej: 364| 3.01k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 3.01k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_7MCFixupELb1EEC2Em: 281| 3.01k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvEC2Em: 78| 3.01k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks15SmallVectorImplIPNS_9MCSectionEED2Ev: 368| 185| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 185| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 185| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 185] ------------------ 374| 0| free(this->begin()); 375| 185| } _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_9MCSectionELb1EE13destroy_rangeEPS2_S4_: 284| 185| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvE5beginEv: 113| 559| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvE3endEv: 117| 559| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvE7isSmallEv: 86| 185| bool isSmall() const { 87| 185| return BeginX == static_cast(&FirstEl); 88| 185| } _ZN7llvm_ks15SmallVectorImplINS_9MCOperandEED2Ev: 368| 3.37k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 3.37k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 3.37k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 3.37k] ------------------ 374| 0| free(this->begin()); 375| 3.37k| } _ZN7llvm_ks11SmallVectorIPNS_9MCSectionELj16EEC2Ev: 872| 185| SmallVector() : SmallVectorImpl(N) { 873| 185| } _ZN7llvm_ks15SmallVectorImplIPNS_9MCSectionEEC2Ej: 364| 185| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 185| } _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_9MCSectionELb1EEC2Em: 281| 185| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvEC2Em: 78| 185| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_9MCSectionELb1EE9push_backERKS2_: 337| 187| void push_back(const T &Elt) { 338| 187| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 187|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 187] | | ------------------ ------------------ 339| 0| this->grow(); 340| 187| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 187| this->setEnd(this->end()+1); 342| 187| } _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvE6setEndEPS2_: 95| 187| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks15SmallVectorImplIPNS_8MCSymbolEED2Ev: 368| 430| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 430| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 430| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 27, False: 403] ------------------ 374| 27| free(this->begin()); 375| 430| } _ZN7llvm_ks11SmallVectorIcLj8EEC2Ev: 872| 850| SmallVector() : SmallVectorImpl(N) { 873| 850| } _ZN7llvm_ks11SmallVectorINS_9MCOperandELj8EEC2Ev: 872| 2.52k| SmallVector() : SmallVectorImpl(N) { 873| 2.52k| } _ZN7llvm_ks15SmallVectorImplINS_9MCOperandEEC2Ej: 364| 3.37k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 3.37k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_9MCOperandELb1EEC2Em: 281| 3.37k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_9MCOperandEvEC2Em: 78| 3.37k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks11SmallVectorINS_7MCFixupELj1EEC2Ev: 872| 850| SmallVector() : SmallVectorImpl(N) { 873| 850| } _ZN7llvm_ks11SmallVectorINS_9MCOperandELj8EEC2ERKS2_: 895| 850| SmallVector(const SmallVector &RHS) : SmallVectorImpl(N) { 896| 850| if (!RHS.empty()) ------------------ | Branch (896:9): [True: 850, False: 0] ------------------ 897| 850| SmallVectorImpl::operator=(RHS); 898| 850| } _ZN7llvm_ks11SmallVectorIPNS_8MCSymbolELj2EEC2Ev: 872| 430| SmallVector() : SmallVectorImpl(N) { 873| 430| } _ZN7llvm_ks15SmallVectorImplIPNS_8MCSymbolEEC2Ej: 364| 430| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 430| } _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_8MCSymbolELb1EEC2Em: 281| 430| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_8MCSymbolEvEC2Em: 78| 430| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks15SmallVectorImplIcE6resizeEmRKc: 396| 180| void resize(size_type N, const T &NV) { 397| 180| if (N < this->size()) { ------------------ | Branch (397:9): [True: 0, False: 180] ------------------ 398| 0| this->destroy_range(this->begin()+N, this->end()); 399| 0| this->setEnd(this->begin()+N); 400| 180| } else if (N > this->size()) { ------------------ | Branch (400:16): [True: 180, False: 0] ------------------ 401| 180| if (this->capacity() < N) ------------------ | Branch (401:11): [True: 2, False: 178] ------------------ 402| 2| this->grow(N); 403| 180| std::uninitialized_fill(this->end(), this->begin()+N, NV); 404| 180| this->setEnd(this->begin()+N); 405| 180| } 406| 180| } _ZN7llvm_ks23SmallVectorTemplateBaseIPNS_8MCSymbolELb1EE9push_backERKS2_: 337| 5.83k| void push_back(const T &Elt) { 338| 5.83k| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 5.83k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 130, False: 5.70k] | | ------------------ ------------------ 339| 130| this->grow(); 340| 5.83k| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 5.83k| this->setEnd(this->end()+1); 342| 5.83k| } _ZN7llvm_ks15SmallVectorImplINS_7SMFixItEED2Ev: 368| 2.47k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 2.47k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 2.47k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 2.47k] ------------------ 374| 0| free(this->begin()); 375| 2.47k| } _ZN7llvm_ks11SmallVectorINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEELj8EEC2Ev: 872| 43.0k| SmallVector() : SmallVectorImpl(N) { 873| 43.0k| } _ZN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEEC2Ej: 364| 43.0k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 43.0k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEELb0EEC2Em: 178| 43.0k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvEC2Em: 78| 43.0k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks11SmallVectorINS_5SMLocELj4EEC2Ev: 872| 8.24k| SmallVector() : SmallVectorImpl(N) { 873| 8.24k| } _ZN7llvm_ks15SmallVectorImplINS_5SMLocEEC2Ej: 364| 8.24k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 8.24k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_5SMLocELb1EEC2Em: 281| 8.24k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvEC2Em: 78| 8.24k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks15SmallVectorImplINS_5SMLocEE6resizeEm: 383| 814| void resize(size_type N) { 384| 814| if (N < this->size()) { ------------------ | Branch (384:9): [True: 0, False: 814] ------------------ 385| 0| this->destroy_range(this->begin()+N, this->end()); 386| 0| this->setEnd(this->begin()+N); 387| 814| } else if (N > this->size()) { ------------------ | Branch (387:16): [True: 251, False: 563] ------------------ 388| 251| if (this->capacity() < N) ------------------ | Branch (388:11): [True: 82, False: 169] ------------------ 389| 82| this->grow(N); 390| 19.5k| for (auto I = this->end(), E = this->begin() + N; I != E; ++I) ------------------ | Branch (390:57): [True: 19.3k, False: 251] ------------------ 391| 19.3k| new (&*I) T(); 392| 251| this->setEnd(this->begin()+N); 393| 251| } 394| 814| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_5SMLocELb1EE13destroy_rangeEPS1_S3_: 284| 19.2k| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE5beginEv: 113| 20.2k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE3endEv: 117| 20.8k| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE6setEndEPS1_: 95| 6.45k| void setEnd(T *P) { this->EndX = P; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE8capacityEv: 136| 251| size_t capacity() const { return capacity_ptr() - begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE12capacity_ptrEv: 122| 251| const_iterator capacity_ptr() const { return (const_iterator)this->CapacityX;} _ZNK7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE5beginEv: 115| 13.9k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZN7llvm_ks23SmallVectorTemplateBaseINS_5SMLocELb1EE4growEm: 333| 95| void grow(size_t MinSize = 0) { 334| 95| this->grow_pod(MinSize*sizeof(T), sizeof(T)); 335| 95| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE8grow_podEmm: 80| 95| void grow_pod(size_t MinSizeInBytes, size_t TSize) { 81| 95| SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize); 82| 95| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE4sizeEv: 132| 13.5k| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE3endEv: 119| 13.7k| const_iterator end() const { return (const_iterator)this->EndX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvEixEm: 144| 441| reference operator[](size_type idx) { 145| 441| assert(idx < size()); ------------------ | Branch (145:5): [True: 441, False: 0] ------------------ 146| 441| return begin()[idx]; 147| 441| } _ZN7llvm_ks15SmallVectorImplINS_5SMLocEED2Ev: 368| 8.24k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 8.24k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 8.24k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 42, False: 8.20k] ------------------ 374| 42| free(this->begin()); 375| 8.24k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_5SMLocEvE7isSmallEv: 86| 13.7k| bool isSmall() const { 87| 13.7k| return BeginX == static_cast(&FirstEl); 88| 13.7k| } _ZN7llvm_ks11SmallVectorIjLj8EEC2Ev: 872| 33.6k| SmallVector() : SmallVectorImpl(N) { 873| 33.6k| } _ZN7llvm_ks15SmallVectorImplIjEC2Ej: 364| 33.6k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 33.6k| } _ZN7llvm_ks23SmallVectorTemplateBaseIjLb1EEC2Em: 281| 33.6k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonIjvEC2Em: 78| 33.6k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonIjvE3endEv: 117| 33.6k| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks15SmallVectorImplIjED2Ev: 368| 33.6k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 33.6k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 33.6k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 33.6k] ------------------ 374| 0| free(this->begin()); 375| 33.6k| } _ZN7llvm_ks23SmallVectorTemplateBaseIjLb1EE13destroy_rangeEPjS2_: 284| 33.6k| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonIjvE5beginEv: 113| 33.6k| iterator begin() { return (iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIjvE7isSmallEv: 86| 33.6k| bool isSmall() const { 87| 33.6k| return BeginX == static_cast(&FirstEl); 88| 33.6k| } _ZN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEED2Ev: 368| 43.0k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 43.0k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 43.0k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 78, False: 42.9k] ------------------ 374| 78| free(this->begin()); 375| 43.0k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEELb0EE13destroy_rangeEPS6_S8_: 180| 43.3k| static void destroy_range(T *S, T *E) { 181| 106k| while (S != E) { ------------------ | Branch (181:12): [True: 62.8k, False: 43.3k] ------------------ 182| 62.8k| --E; 183| 62.8k| E->~T(); 184| 62.8k| } 185| 43.3k| } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE5beginEv: 113| 47.6k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE3endEv: 117| 112k| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE7isSmallEv: 86| 43.3k| bool isSmall() const { 87| 43.3k| return BeginX == static_cast(&FirstEl); 88| 43.3k| } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE4sizeEv: 132| 113k| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE3endEv: 119| 113k| const_iterator end() const { return (const_iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE5beginEv: 115| 159k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvEixEm: 144| 2.67k| reference operator[](size_type idx) { 145| 2.67k| assert(idx < size()); ------------------ | Branch (145:5): [True: 2.67k, False: 0] ------------------ 146| 2.67k| return begin()[idx]; 147| 2.67k| } _ZN7llvm_ks15SmallVectorImplINS_8AsmTokenEED2Ev: 368| 430| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 430| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 430| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 430] ------------------ 374| 0| free(this->begin()); 375| 430| } _ZN7llvm_ks11SmallVectorINS_8AsmTokenELj1EEC2Ev: 872| 430| SmallVector() : SmallVectorImpl(N) { 873| 430| } _ZN7llvm_ks15SmallVectorImplINS_8AsmTokenEEC2Ej: 364| 430| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 430| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_8AsmTokenELb0EEC2Em: 178| 430| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_8AsmTokenEvEC2Em: 78| 430| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks15SmallVectorImplINS_8AsmTokenEE12emplace_backIJNS1_9TokenKindENS_9StringRefEEEEvDpOT_: 659| 430| template void emplace_back(ArgTypes &&... Args) { 660| 430| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 430|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 430] | | ------------------ ------------------ 661| 0| this->grow(); 662| 430| ::new ((void *)this->end()) T(std::forward(Args)...); 663| 430| this->setEnd(this->end() + 1); 664| 430| } _ZN7llvm_ks15SmallVectorImplINSt3__14pairIjPNS_10MCFragmentEEEED2Ev: 368| 18.6k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 18.6k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 18.6k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 18.6k] ------------------ 374| 0| free(this->begin()); 375| 18.6k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairIjPNS_10MCFragmentEEELb1EE13destroy_rangeEPS5_S7_: 284| 18.6k| static void destroy_range(T *, T *) {} _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjPNS_10MCFragmentEEEvE7isSmallEv: 86| 18.6k| bool isSmall() const { 87| 18.6k| return BeginX == static_cast(&FirstEl); 88| 18.6k| } _ZN7llvm_ks11SmallVectorINSt3__14pairIjPNS_10MCFragmentEEELj1EEC2Ev: 872| 18.6k| SmallVector() : SmallVectorImpl(N) { 873| 18.6k| } _ZN7llvm_ks15SmallVectorImplINSt3__14pairIjPNS_10MCFragmentEEEEC2Ej: 364| 18.6k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 18.6k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairIjPNS_10MCFragmentEEELb1EEC2Em: 281| 18.6k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjPNS_10MCFragmentEEEvEC2Em: 78| 18.6k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjPNS_10MCFragmentEEEvE5beginEv: 113| 18.6k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjPNS_10MCFragmentEEEvE3endEv: 117| 18.6k| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvEixEm: 144| 8.67k| reference operator[](size_type idx) { 145| 8.67k| assert(idx < size()); ------------------ | Branch (145:5): [True: 8.67k, False: 0] ------------------ 146| 8.67k| return begin()[idx]; 147| 8.67k| } _ZN7llvm_ks15SmallVectorImplINS_9StringRefEED2Ev: 368| 7.50k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 7.50k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 7.50k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 14, False: 7.49k] ------------------ 374| 14| free(this->begin()); 375| 7.50k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_9StringRefELb1EE13destroy_rangeEPS1_S3_: 284| 7.50k| static void destroy_range(T *, T *) {} _ZNK7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvE7isSmallEv: 86| 7.50k| bool isSmall() const { 87| 7.50k| return BeginX == static_cast(&FirstEl); 88| 7.50k| } _ZN7llvm_ks11SmallVectorINS_9StringRefELj5EEC2Ev: 872| 16| SmallVector() : SmallVectorImpl(N) { 873| 16| } _ZN7llvm_ks15SmallVectorImplINS_9StringRefEEC2Ej: 364| 7.50k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 7.50k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_9StringRefELb1EEC2Em: 281| 7.50k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvEC2Em: 78| 7.50k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvE5beginEv: 113| 19.3k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvE3endEv: 117| 28.4k| iterator end() { return (iterator)this->EndX; } _ZN7llvm_ks15SmallVectorImplINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEED2Ev: 368| 430| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 430| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 430| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 430] ------------------ 374| 0| free(this->begin()); 375| 430| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EELb1EE13destroy_rangeEPS9_SB_: 284| 430| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEvE5beginEv: 113| 430| iterator begin() { return (iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEvE7isSmallEv: 86| 430| bool isSmall() const { 87| 430| return BeginX == static_cast(&FirstEl); 88| 430| } _ZN7llvm_ks11SmallVectorINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EELj4EEC2Ev: 872| 430| SmallVector() : SmallVectorImpl(N) { 873| 430| } _ZN7llvm_ks15SmallVectorImplINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEEC2Ej: 364| 430| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 430| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EELb1EEC2Em: 281| 430| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairINS2_IPNS_9MCSectionEPKNS_6MCExprEEES8_EEvEC2Em: 78| 430| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvE6setEndEPS1_: 95| 8.87k| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks11SmallVectorINS_9StringRefELj4EEC2Ev: 872| 4.30k| SmallVector() : SmallVectorImpl(N) { 873| 4.30k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_9StringRefELb1EE9push_backERKS1_: 337| 8.87k| void push_back(const T &Elt) { 338| 8.87k| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 8.87k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 40, False: 8.83k] | | ------------------ ------------------ 339| 40| this->grow(); 340| 8.87k| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 8.87k| this->setEnd(this->end()+1); 342| 8.87k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_9StringRefELb1EE4growEm: 333| 40| void grow(size_t MinSize = 0) { 334| 40| this->grow_pod(MinSize*sizeof(T), sizeof(T)); 335| 40| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_9StringRefEvE8grow_podEmm: 80| 40| void grow_pod(size_t MinSizeInBytes, size_t TSize) { 81| 40| SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize); 82| 40| } _ZN7llvm_ks15SmallVectorImplINSt3__14pairIjjEEED2Ev: 368| 2.17k| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 2.17k| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 2.17k| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 2.17k] ------------------ 374| 0| free(this->begin()); 375| 2.17k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairIjjEELb1EE13destroy_rangeEPS3_S5_: 284| 2.17k| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjjEEvE5beginEv: 113| 2.17k| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjjEEvE3endEv: 117| 2.17k| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjjEEvE7isSmallEv: 86| 2.17k| bool isSmall() const { 87| 2.17k| return BeginX == static_cast(&FirstEl); 88| 2.17k| } _ZN7llvm_ks11SmallVectorINSt3__14pairIjjEELj4EEC2Ev: 872| 2.17k| SmallVector() : SmallVectorImpl(N) { 873| 2.17k| } _ZN7llvm_ks15SmallVectorImplINSt3__14pairIjjEEEC2Ej: 364| 2.17k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 2.17k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__14pairIjjEELb1EEC2Em: 281| 2.17k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjjEEvEC2Em: 78| 2.17k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjjEEvE4dataEv: 141| 2.17k| const_pointer data() const { return const_pointer(begin()); } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjjEEvE5beginEv: 115| 4.34k| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjjEEvE4sizeEv: 132| 2.17k| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__14pairIjjEEvE3endEv: 119| 2.17k| const_iterator end() const { return (const_iterator)this->EndX; } _ZN7llvm_ks11SmallVectorINS_7SMFixItELj4EEC2IPKS1_EET_S6_: 881| 2.47k| SmallVector(ItTy S, ItTy E) : SmallVectorImpl(N) { 882| 2.47k| this->append(S, E); 883| 2.47k| } _ZN7llvm_ks15SmallVectorImplINS_7SMFixItEEC2Ej: 364| 2.47k| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 2.47k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_7SMFixItELb0EEC2Em: 178| 2.47k| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvEC2Em: 78| 2.47k| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks15SmallVectorImplINS_7SMFixItEE6appendIPKS1_EEvT_S6_: 423| 2.47k| void append(in_iter in_start, in_iter in_end) { 424| 2.47k| size_type NumInputs = std::distance(in_start, in_end); 425| | // Grow allocated space if needed. 426| 2.47k| if (NumInputs > size_type(this->capacity_ptr()-this->end())) ------------------ | Branch (426:9): [True: 0, False: 2.47k] ------------------ 427| 0| this->grow(this->size()+NumInputs); 428| | 429| | // Copy the new elements over. 430| 2.47k| this->uninitialized_copy(in_start, in_end, this->end()); 431| 2.47k| this->setEnd(this->end() + NumInputs); 432| 2.47k| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_7SMFixItEvE12capacity_ptrEv: 121| 2.47k| iterator capacity_ptr() { return (iterator)this->CapacityX; } _ZN7llvm_ks23SmallVectorTemplateBaseINS_7SMFixItELb0EE18uninitialized_copyIPKS1_PS1_EEvT_S7_T0_: 219| 2.47k| static void uninitialized_copy(It1 I, It1 E, It2 Dest) { 220| 2.47k| std::uninitialized_copy(I, E, Dest); 221| 2.47k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEELb0EE9push_backEOS6_: 236| 33.6k| void push_back(T &&Elt) { 237| 33.6k| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 33.6k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 321, False: 33.3k] | | ------------------ ------------------ 238| 321| this->grow(); 239| 33.6k| ::new ((void*) this->end()) T(::std::move(Elt)); 240| 33.6k| this->setEnd(this->end()+1); 241| 33.6k| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEELb0EE4growEm: 251| 321|void SmallVectorTemplateBase::grow(size_t MinSize) { 252| 321| size_t CurCapacity = this->capacity(); 253| 321| size_t CurSize = this->size(); 254| | // Always grow, even from zero. 255| 321| size_t NewCapacity = size_t(NextPowerOf2(CurCapacity+2)); 256| 321| if (NewCapacity < MinSize) ------------------ | Branch (256:7): [True: 0, False: 321] ------------------ 257| 0| NewCapacity = MinSize; 258| 321| T *NewElts = static_cast(malloc(NewCapacity*sizeof(T))); 259| | 260| | // Move the elements over. 261| 321| this->uninitialized_move(this->begin(), this->end(), NewElts); 262| | 263| | // Destroy the original elements. 264| 321| destroy_range(this->begin(), this->end()); 265| | 266| | // If this wasn't grown from the inline copy, deallocate the old space. 267| 321| if (!this->isSmall()) ------------------ | Branch (267:7): [True: 243, False: 78] ------------------ 268| 243| free(this->begin()); 269| | 270| 321| this->setEnd(NewElts+CurSize); 271| 321| this->BeginX = NewElts; 272| 321| this->CapacityX = this->begin()+NewCapacity; 273| 321|} _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE8capacityEv: 136| 321| size_t capacity() const { return capacity_ptr() - begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE12capacity_ptrEv: 122| 321| const_iterator capacity_ptr() const { return (const_iterator)this->CapacityX;} _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEELb0EE18uninitialized_moveIPS6_S9_EEvT_SA_T0_: 211| 321| static void uninitialized_move(It1 I, It1 E, It2 Dest) { 212| 29.8k| for (; I != E; ++I, ++Dest) ------------------ | Branch (212:12): [True: 29.5k, False: 321] ------------------ 213| 29.5k| ::new ((void*) &*Dest) T(::std::move(*I)); 214| 321| } _ZN7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvE6setEndEPS6_: 95| 34.2k| void setEnd(T *P) { this->EndX = P; } _ZNK7llvm_ks25SmallVectorTemplateCommonINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEvEixEm: 149| 45.2k| const_reference operator[](size_type idx) const { 150| 45.2k| assert(idx < size()); ------------------ | Branch (150:5): [True: 45.2k, False: 0] ------------------ 151| 45.2k| return begin()[idx]; 152| 45.2k| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_5SMLocELb1EE9push_backERKS1_: 337| 695| void push_back(const T &Elt) { 338| 695| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 695|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 13, False: 682] | | ------------------ ------------------ 339| 13| this->grow(); 340| 695| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 695| this->setEnd(this->end()+1); 342| 695| } _ZN7llvm_ks15SmallVectorImplINS_17ConstantPoolEntryEED2Ev: 368| 18| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 18| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 18| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 5, False: 13] ------------------ 374| 5| free(this->begin()); 375| 18| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_17ConstantPoolEntryELb1EE13destroy_rangeEPS1_S3_: 284| 23| static void destroy_range(T *, T *) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_17ConstantPoolEntryEvE5beginEv: 113| 33| iterator begin() { return (iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonINS_17ConstantPoolEntryEvE3endEv: 117| 1.06k| iterator end() { return (iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_17ConstantPoolEntryEvE7isSmallEv: 86| 18| bool isSmall() const { 87| 18| return BeginX == static_cast(&FirstEl); 88| 18| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEELb0EE8pop_backEv: 243| 324| void pop_back() { 244| 324| this->setEnd(this->end()-1); 245| 324| this->end()->~T(); 246| 324| } _ZN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEEE5eraseEPS6_: 462| 324| iterator erase(iterator I) { 463| 324| assert(I >= this->begin() && "Iterator to erase is out of bounds."); ------------------ | Branch (463:5): [True: 324, False: 0] | Branch (463:5): [True: 324, Folded] | Branch (463:5): [True: 324, False: 0] ------------------ 464| 324| assert(I < this->end() && "Erasing at past-the-end iterator."); ------------------ | Branch (464:5): [True: 324, False: 0] | Branch (464:5): [True: 324, Folded] | Branch (464:5): [True: 324, False: 0] ------------------ 465| | 466| 324| iterator N = I; 467| | // Shift all elts down one. 468| 324| this->move(I+1, this->end(), I); 469| | // Drop the last elt. 470| 324| this->pop_back(); 471| 324| return(N); 472| 324| } _ZN7llvm_ks23SmallVectorTemplateBaseINSt3__110unique_ptrINS_18MCParsedAsmOperandENS1_14default_deleteIS3_EEEELb0EE4moveIPS6_S9_EET0_T_SB_SA_: 191| 324| static It2 move(It1 I, It1 E, It2 Dest) { 192| 1.17k| for (; I != E; ++I, ++Dest) ------------------ | Branch (192:12): [True: 853, False: 324] ------------------ 193| 853| *Dest = ::std::move(*I); 194| 324| return Dest; 195| 324| } _ZN7llvm_ks11SmallVectorINS_5SMLocELj4EEaSEOS2_: 910| 5.50k| const SmallVector &operator=(SmallVector &&RHS) { 911| 5.50k| SmallVectorImpl::operator=(::std::move(RHS)); 912| 5.50k| return *this; 913| 5.50k| } _ZN7llvm_ks15SmallVectorImplINS_5SMLocEEaSEOS2_: 787| 5.50k|SmallVectorImpl &SmallVectorImpl::operator=(SmallVectorImpl &&RHS) { 788| | // Avoid self-assignment. 789| 5.50k| if (this == &RHS) return *this; ------------------ | Branch (789:7): [True: 0, False: 5.50k] ------------------ 790| | 791| | // If the RHS isn't small, clear this vector and then steal its buffer. 792| 5.50k| if (!RHS.isSmall()) { ------------------ | Branch (792:7): [True: 0, False: 5.50k] ------------------ 793| 0| this->destroy_range(this->begin(), this->end()); 794| 0| if (!this->isSmall()) free(this->begin()); ------------------ | Branch (794:9): [True: 0, False: 0] ------------------ 795| 0| this->BeginX = RHS.BeginX; 796| 0| this->EndX = RHS.EndX; 797| 0| this->CapacityX = RHS.CapacityX; 798| 0| RHS.resetToSmall(); 799| 0| return *this; 800| 0| } 801| | 802| | // If we already have sufficient space, assign the common elements, then 803| | // destroy any excess. 804| 5.50k| size_t RHSSize = RHS.size(); 805| 5.50k| size_t CurSize = this->size(); 806| 5.50k| if (CurSize >= RHSSize) { ------------------ | Branch (806:7): [True: 5.50k, False: 0] ------------------ 807| | // Assign common elements. 808| 5.50k| iterator NewEnd = this->begin(); 809| 5.50k| if (RHSSize) ------------------ | Branch (809:9): [True: 0, False: 5.50k] ------------------ 810| 0| NewEnd = this->move(RHS.begin(), RHS.end(), NewEnd); 811| | 812| | // Destroy excess elements and trim the bounds. 813| 5.50k| this->destroy_range(NewEnd, this->end()); 814| 5.50k| this->setEnd(NewEnd); 815| | 816| | // Clear the RHS. 817| 5.50k| RHS.clear(); 818| | 819| 5.50k| return *this; 820| 5.50k| } 821| | 822| | // If we have to grow to have enough elements, destroy the current elements. 823| | // This allows us to avoid copying them during the grow. 824| | // FIXME: this may not actually make any sense if we can efficiently move 825| | // elements. 826| 0| if (this->capacity() < RHSSize) { ------------------ | Branch (826:7): [True: 0, False: 0] ------------------ 827| | // Destroy current elements. 828| 0| this->destroy_range(this->begin(), this->end()); 829| 0| this->setEnd(this->begin()); 830| 0| CurSize = 0; 831| 0| this->grow(RHSSize); 832| 0| } else if (CurSize) { ------------------ | Branch (832:14): [True: 0, False: 0] ------------------ 833| | // Otherwise, use assignment for the already-constructed elements. 834| 0| this->move(RHS.begin(), RHS.begin()+CurSize, this->begin()); 835| 0| } 836| | 837| | // Move-construct the new elements in place. 838| 0| this->uninitialized_move(RHS.begin()+CurSize, RHS.end(), 839| 0| this->begin()+CurSize); 840| | 841| | // Set end. 842| 0| this->setEnd(this->begin()+RHSSize); 843| | 844| 0| RHS.clear(); 845| 0| return *this; 846| 5.50k|} _ZN7llvm_ks15SmallVectorImplINS_5SMLocEE5clearEv: 378| 5.50k| void clear() { 379| 5.50k| this->destroy_range(this->begin(), this->end()); 380| 5.50k| this->EndX = this->BeginX; 381| 5.50k| } _ZN7llvm_ks15SmallVectorImplINS_17ConstantPoolEntryEE5clearEv: 378| 5| void clear() { 379| 5| this->destroy_range(this->begin(), this->end()); 380| 5| this->EndX = this->BeginX; 381| 5| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_17ConstantPoolEntryELb1EE9push_backERKS1_: 337| 516| void push_back(const T &Elt) { 338| 516| if (LLVM_UNLIKELY(this->EndX >= this->CapacityX)) ------------------ | | 172| 516|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 24, False: 492] | | ------------------ ------------------ 339| 24| this->grow(); 340| 516| memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); 341| 516| this->setEnd(this->end()+1); 342| 516| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_17ConstantPoolEntryELb1EE4growEm: 333| 24| void grow(size_t MinSize = 0) { 334| 24| this->grow_pod(MinSize*sizeof(T), sizeof(T)); 335| 24| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_17ConstantPoolEntryEvE8grow_podEmm: 80| 24| void grow_pod(size_t MinSizeInBytes, size_t TSize) { 81| 24| SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize); 82| 24| } _ZN7llvm_ks25SmallVectorTemplateCommonINS_17ConstantPoolEntryEvE6setEndEPS1_: 95| 516| void setEnd(T *P) { this->EndX = P; } _ZN7llvm_ks11SmallVectorINS_17ConstantPoolEntryELj4EEC2EOS2_: 905| 12| SmallVector(SmallVector &&RHS) : SmallVectorImpl(N) { 906| 12| if (!RHS.empty()) ------------------ | Branch (906:9): [True: 0, False: 12] ------------------ 907| 0| SmallVectorImpl::operator=(::std::move(RHS)); 908| 12| } _ZN7llvm_ks15SmallVectorImplINS_17ConstantPoolEntryEEC2Ej: 364| 18| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 18| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_17ConstantPoolEntryELb1EEC2Em: 281| 18| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_17ConstantPoolEntryEvEC2Em: 78| 18| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks11SmallVectorINS_17ConstantPoolEntryELj4EEC2Ev: 872| 6| SmallVector() : SmallVectorImpl(N) { 873| 6| } _ZN7llvm_ks11SmallVectorINS_14MCLOHDirectiveELj32EEC2Ev: 872| 430| SmallVector() : SmallVectorImpl(N) { 873| 430| } _ZN7llvm_ks15SmallVectorImplINS_14MCLOHDirectiveEEC2Ej: 364| 430| : SmallVectorTemplateBase::value>(N*sizeof(T)) { 365| 430| } _ZN7llvm_ks23SmallVectorTemplateBaseINS_14MCLOHDirectiveELb0EEC2Em: 178| 430| SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon(Size) {} _ZN7llvm_ks25SmallVectorTemplateCommonINS_14MCLOHDirectiveEvEC2Em: 78| 430| SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size) {} _ZN7llvm_ks15SmallVectorImplINS_14MCLOHDirectiveEED2Ev: 368| 430| ~SmallVectorImpl() { 369| | // Destroy the constructed elements in the vector. 370| 430| this->destroy_range(this->begin(), this->end()); 371| | 372| | // If this wasn't grown from the inline copy, deallocate the old space. 373| 430| if (!this->isSmall()) ------------------ | Branch (373:9): [True: 0, False: 430] ------------------ 374| 0| free(this->begin()); 375| 430| } _ZNK7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvE4sizeEv: 132| 744| size_type size() const { return end()-begin(); } _ZNK7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvE3endEv: 119| 744| const_iterator end() const { return (const_iterator)this->EndX; } _ZNK7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvE5beginEv: 115| 744| const_iterator begin() const { return (const_iterator)this->BeginX; } _ZN7llvm_ks25SmallVectorTemplateCommonIPNS_9MCSectionEvEixEm: 144| 374| reference operator[](size_type idx) { 145| 374| assert(idx < size()); ------------------ | Branch (145:5): [True: 374, False: 0] ------------------ 146| 374| return begin()[idx]; 147| 374| } _ZNK7llvm_ks25SmallVectorTemplateCommonINS_7MCFixupEvE4dataEv: 141| 1.02k| const_pointer data() const { return const_pointer(begin()); } _ZN7llvm_ks15SmallVectorImplINS_7MCFixupEEaSERKS2_: 739| 46| operator=(const SmallVectorImpl &RHS) { 740| | // Avoid self-assignment. 741| 46| if (this == &RHS) return *this; ------------------ | Branch (741:7): [True: 0, False: 46] ------------------ 742| | 743| | // If we already have sufficient space, assign the common elements, then 744| | // destroy any excess. 745| 46| size_t RHSSize = RHS.size(); 746| 46| size_t CurSize = this->size(); 747| 46| if (CurSize >= RHSSize) { ------------------ | Branch (747:7): [True: 46, False: 0] ------------------ 748| | // Assign common elements. 749| 46| iterator NewEnd; 750| 46| if (RHSSize) ------------------ | Branch (750:9): [True: 46, False: 0] ------------------ 751| 46| NewEnd = std::copy(RHS.begin(), RHS.begin()+RHSSize, this->begin()); 752| 0| else 753| 0| NewEnd = this->begin(); 754| | 755| | // Destroy excess elements. 756| 46| this->destroy_range(NewEnd, this->end()); 757| | 758| | // Trim. 759| 46| this->setEnd(NewEnd); 760| 46| return *this; 761| 46| } 762| | 763| | // If we have to grow to have enough elements, destroy the current elements. 764| | // This allows us to avoid copying them during the grow. 765| | // FIXME: don't do this if they're efficiently moveable. 766| 0| if (this->capacity() < RHSSize) { ------------------ | Branch (766:7): [True: 0, False: 0] ------------------ 767| | // Destroy current elements. 768| 0| this->destroy_range(this->begin(), this->end()); 769| 0| this->setEnd(this->begin()); 770| 0| CurSize = 0; 771| 0| this->grow(RHSSize); 772| 0| } else if (CurSize) { ------------------ | Branch (772:14): [True: 0, False: 0] ------------------ 773| | // Otherwise, use assignment for the already-constructed elements. 774| 0| std::copy(RHS.begin(), RHS.begin()+CurSize, this->begin()); 775| 0| } 776| | 777| | // Copy construct the new elements in place. 778| 0| this->uninitialized_copy(RHS.begin()+CurSize, RHS.end(), 779| 0| this->begin()+CurSize); 780| | 781| | // Set end. 782| 0| this->setEnd(this->begin()+RHSSize); 783| 0| return *this; 784| 46|} _ZN7llvm_ks11SmallVectorINS_9StringRefELj3EEC2Ev: 872| 3.19k| SmallVector() : SmallVectorImpl(N) { 873| 3.19k| } APFloat.cpp:_ZN7llvm_ksL13hexDigitValueEc: 40| 15.7k|static inline unsigned hexDigitValue(char C) { 41| 15.7k| if (C >= '0' && C <= '9') return C-'0'; ------------------ | Branch (41:7): [True: 15.7k, False: 0] | Branch (41:19): [True: 14.1k, False: 1.61k] ------------------ 42| 1.61k| if (C >= 'a' && C <= 'f') return C-'a'+10U; ------------------ | Branch (42:7): [True: 690, False: 922] | Branch (42:19): [True: 161, False: 529] ------------------ 43| 1.45k| if (C >= 'A' && C <= 'F') return C-'A'+10U; ------------------ | Branch (43:7): [True: 1.45k, False: 0] | Branch (43:19): [True: 444, False: 1.00k] ------------------ 44| 1.00k| return -1U; 45| 1.45k|} StringMap.cpp:_ZN7llvm_ksL10HashStringENS_9StringRefEj: 112| 152k|static inline unsigned HashString(StringRef Str, unsigned Result = 0) { 113| 1.87M| for (StringRef::size_type i = 0, e = Str.size(); i != e; ++i) ------------------ | Branch (113:52): [True: 1.72M, False: 152k] ------------------ 114| 1.72M| Result = Result * 33 + (unsigned char)Str[i]; 115| 152k| return Result; 116| 152k|} _ZN7llvm_ks18StringMapEntryBaseC2Ej: 35| 100k| explicit StringMapEntryBase(unsigned Len) : StrLen(Len) {} _ZNK7llvm_ks18StringMapEntryBase12getKeyLengthEv: 37| 130k| unsigned getKeyLength() const { return StrLen; } _ZN7llvm_ks13StringMapImplC2Ej: 55| 3.87k| : TheTable(nullptr), 56| | // Initialize the map with zero buckets to allocation. 57| 3.87k| NumBuckets(0), NumItems(0), NumTombstones(0), ItemSize(itemSize) {} _ZN7llvm_ks13StringMapImpl15getTombstoneValEv: 95| 679k| static StringMapEntryBase *getTombstoneVal() { 96| 679k| return (StringMapEntryBase*)-1; 97| 679k| } _ZNK7llvm_ks13StringMapImpl5emptyEv: 102| 6.02k| bool empty() const { return NumItems == 0; } _ZN7llvm_ks14StringMapEntryIjE7DestroyINS_15MallocAllocatorEEEvRT_: 198| 5.89k| void Destroy(AllocatorTy &Allocator) { 199| | // Free memory referenced by the item. 200| 5.89k| unsigned AllocSize = 201| 5.89k| static_cast(sizeof(StringMapEntry)) + getKeyLength() + 1; 202| 5.89k| this->~StringMapEntry(); 203| 5.89k| Allocator.Deallocate(static_cast(this), AllocSize); 204| 5.89k| } _ZNK7llvm_ks14StringMapEntryIbE5firstEv: 143| 134| StringRef first() const { return StringRef(getKeyData(), getKeyLength()); } _ZNK7llvm_ks14StringMapEntryIbE10getKeyDataEv: 141| 11.8k| const char *getKeyData() const {return reinterpret_cast(this+1);} _ZN7llvm_ks9StringMapIjNS_15MallocAllocatorEEC2Ev: 224| 860| StringMap() : StringMapImpl(static_cast(sizeof(MapEntryTy))) {} _ZN7llvm_ks9StringMapIjNS_15MallocAllocatorEED2Ev: 385| 860| ~StringMap() { 386| | // Delete all the elements in the map, but don't reset the elements 387| | // to default values. This is a copy of clear(), but avoids unnecessary 388| | // work not required in the destructor. 389| 860| if (!empty()) { ------------------ | Branch (389:9): [True: 0, False: 860] ------------------ 390| 0| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (390:44): [True: 0, False: 0] ------------------ 391| 0| StringMapEntryBase *Bucket = TheTable[I]; 392| 0| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (392:13): [True: 0, False: 0] | Branch (392:23): [True: 0, False: 0] ------------------ 393| 0| static_cast(Bucket)->Destroy(Allocator); 394| 0| } 395| 0| } 396| 0| } 397| 860| free(TheTable); 398| 860| } _ZN7llvm_ks9StringMapIPNS_8MCSymbolERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEEC2ES6_: 229| 430| : StringMapImpl(static_cast(sizeof(MapEntryTy))), Allocator(A) {} _ZN7llvm_ks9StringMapIbRNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEEC2ES4_: 229| 430| : StringMapImpl(static_cast(sizeof(MapEntryTy))), Allocator(A) {} _ZN7llvm_ks9StringMapIPNS_14MCSectionMachOENS_15MallocAllocatorEEC2Ev: 224| 430| StringMap() : StringMapImpl(static_cast(sizeof(MapEntryTy))) {} _ZN7llvm_ks9StringMapIbNS_15MallocAllocatorEEC2Ev: 224| 430| StringMap() : StringMapImpl(static_cast(sizeof(MapEntryTy))) {} _ZN7llvm_ks9StringMapIPNS_8MCSymbolERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEED2Ev: 385| 430| ~StringMap() { 386| | // Delete all the elements in the map, but don't reset the elements 387| | // to default values. This is a copy of clear(), but avoids unnecessary 388| | // work not required in the destructor. 389| 430| if (!empty()) { ------------------ | Branch (389:9): [True: 0, False: 430] ------------------ 390| 0| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (390:44): [True: 0, False: 0] ------------------ 391| 0| StringMapEntryBase *Bucket = TheTable[I]; 392| 0| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (392:13): [True: 0, False: 0] | Branch (392:23): [True: 0, False: 0] ------------------ 393| 0| static_cast(Bucket)->Destroy(Allocator); 394| 0| } 395| 0| } 396| 0| } 397| 430| free(TheTable); 398| 430| } _ZN7llvm_ks14StringMapEntryIPNS_8MCSymbolEE7DestroyINS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEEEvRT_: 198| 1.94k| void Destroy(AllocatorTy &Allocator) { 199| | // Free memory referenced by the item. 200| 1.94k| unsigned AllocSize = 201| 1.94k| static_cast(sizeof(StringMapEntry)) + getKeyLength() + 1; 202| 1.94k| this->~StringMapEntry(); 203| 1.94k| Allocator.Deallocate(static_cast(this), AllocSize); 204| 1.94k| } _ZN7llvm_ks9StringMapIbRNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEED2Ev: 385| 430| ~StringMap() { 386| | // Delete all the elements in the map, but don't reset the elements 387| | // to default values. This is a copy of clear(), but avoids unnecessary 388| | // work not required in the destructor. 389| 430| if (!empty()) { ------------------ | Branch (389:9): [True: 0, False: 430] ------------------ 390| 0| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (390:44): [True: 0, False: 0] ------------------ 391| 0| StringMapEntryBase *Bucket = TheTable[I]; 392| 0| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (392:13): [True: 0, False: 0] | Branch (392:23): [True: 0, False: 0] ------------------ 393| 0| static_cast(Bucket)->Destroy(Allocator); 394| 0| } 395| 0| } 396| 0| } 397| 430| free(TheTable); 398| 430| } _ZN7llvm_ks14StringMapEntryIbE7DestroyINS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEEEvRT_: 198| 11.7k| void Destroy(AllocatorTy &Allocator) { 199| | // Free memory referenced by the item. 200| 11.7k| unsigned AllocSize = 201| 11.7k| static_cast(sizeof(StringMapEntry)) + getKeyLength() + 1; 202| 11.7k| this->~StringMapEntry(); 203| 11.7k| Allocator.Deallocate(static_cast(this), AllocSize); 204| 11.7k| } _ZN7llvm_ks9StringMapIPNS_14MCSectionMachOENS_15MallocAllocatorEED2Ev: 385| 430| ~StringMap() { 386| | // Delete all the elements in the map, but don't reset the elements 387| | // to default values. This is a copy of clear(), but avoids unnecessary 388| | // work not required in the destructor. 389| 430| if (!empty()) { ------------------ | Branch (389:9): [True: 0, False: 430] ------------------ 390| 0| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (390:44): [True: 0, False: 0] ------------------ 391| 0| StringMapEntryBase *Bucket = TheTable[I]; 392| 0| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (392:13): [True: 0, False: 0] | Branch (392:23): [True: 0, False: 0] ------------------ 393| 0| static_cast(Bucket)->Destroy(Allocator); 394| 0| } 395| 0| } 396| 0| } 397| 430| free(TheTable); 398| 430| } _ZN7llvm_ks14StringMapEntryIPNS_14MCSectionMachOEE7DestroyINS_15MallocAllocatorEEEvRT_: 198| 4| void Destroy(AllocatorTy &Allocator) { 199| | // Free memory referenced by the item. 200| 4| unsigned AllocSize = 201| 4| static_cast(sizeof(StringMapEntry)) + getKeyLength() + 1; 202| 4| this->~StringMapEntry(); 203| 4| Allocator.Deallocate(static_cast(this), AllocSize); 204| 4| } _ZN7llvm_ks9StringMapIbNS_15MallocAllocatorEED2Ev: 385| 430| ~StringMap() { 386| | // Delete all the elements in the map, but don't reset the elements 387| | // to default values. This is a copy of clear(), but avoids unnecessary 388| | // work not required in the destructor. 389| 430| if (!empty()) { ------------------ | Branch (389:9): [True: 25, False: 405] ------------------ 390| 425| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (390:44): [True: 400, False: 25] ------------------ 391| 400| StringMapEntryBase *Bucket = TheTable[I]; 392| 400| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (392:13): [True: 25, False: 375] | Branch (392:23): [True: 25, False: 0] ------------------ 393| 25| static_cast(Bucket)->Destroy(Allocator); 394| 25| } 395| 400| } 396| 25| } 397| 430| free(TheTable); 398| 430| } _ZN7llvm_ks14StringMapEntryIbE7DestroyINS_15MallocAllocatorEEEvRT_: 198| 25| void Destroy(AllocatorTy &Allocator) { 199| | // Free memory referenced by the item. 200| 25| unsigned AllocSize = 201| 25| static_cast(sizeof(StringMapEntry)) + getKeyLength() + 1; 202| 25| this->~StringMapEntry(); 203| 25| Allocator.Deallocate(static_cast(this), AllocSize); 204| 25| } _ZN7llvm_ks9StringMapIbRNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE5clearEv: 349| 430| void clear() { 350| 430| if (empty()) return; ------------------ | Branch (350:9): [True: 0, False: 430] ------------------ 351| | 352| | // Zap all values, resetting the keys back to non-present (not tombstone), 353| | // which is safe because we're removing all elements. 354| 22.3k| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (354:42): [True: 21.9k, False: 430] ------------------ 355| 21.9k| StringMapEntryBase *&Bucket = TheTable[I]; 356| 21.9k| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (356:11): [True: 11.7k, False: 10.2k] | Branch (356:21): [True: 11.7k, False: 0] ------------------ 357| 11.7k| static_cast(Bucket)->Destroy(Allocator); 358| 11.7k| } 359| 21.9k| Bucket = nullptr; 360| 21.9k| } 361| | 362| 430| NumItems = 0; 363| 430| NumTombstones = 0; 364| 430| } _ZN7llvm_ks9StringMapIPNS_8MCSymbolERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE5clearEv: 349| 430| void clear() { 350| 430| if (empty()) return; ------------------ | Branch (350:9): [True: 0, False: 430] ------------------ 351| | 352| | // Zap all values, resetting the keys back to non-present (not tombstone), 353| | // which is safe because we're removing all elements. 354| 9.23k| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (354:42): [True: 8.80k, False: 430] ------------------ 355| 8.80k| StringMapEntryBase *&Bucket = TheTable[I]; 356| 8.80k| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (356:11): [True: 1.94k, False: 6.85k] | Branch (356:21): [True: 1.94k, False: 0] ------------------ 357| 1.94k| static_cast(Bucket)->Destroy(Allocator); 358| 1.94k| } 359| 8.80k| Bucket = nullptr; 360| 8.80k| } 361| | 362| 430| NumItems = 0; 363| 430| NumTombstones = 0; 364| 430| } _ZN7llvm_ks9StringMapIPNS_14MCSectionMachOENS_15MallocAllocatorEE5clearEv: 349| 430| void clear() { 350| 430| if (empty()) return; ------------------ | Branch (350:9): [True: 427, False: 3] ------------------ 351| | 352| | // Zap all values, resetting the keys back to non-present (not tombstone), 353| | // which is safe because we're removing all elements. 354| 51| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (354:42): [True: 48, False: 3] ------------------ 355| 48| StringMapEntryBase *&Bucket = TheTable[I]; 356| 48| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (356:11): [True: 4, False: 44] | Branch (356:21): [True: 4, False: 0] ------------------ 357| 4| static_cast(Bucket)->Destroy(Allocator); 358| 4| } 359| 48| Bucket = nullptr; 360| 48| } 361| | 362| 3| NumItems = 0; 363| 3| NumTombstones = 0; 364| 3| } _ZN7llvm_ks9StringMapIjNS_15MallocAllocatorEE5clearEv: 349| 430| void clear() { 350| 430| if (empty()) return; ------------------ | Branch (350:9): [True: 0, False: 430] ------------------ 351| | 352| | // Zap all values, resetting the keys back to non-present (not tombstone), 353| | // which is safe because we're removing all elements. 354| 10.5k| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (354:42): [True: 10.1k, False: 430] ------------------ 355| 10.1k| StringMapEntryBase *&Bucket = TheTable[I]; 356| 10.1k| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (356:11): [True: 5.89k, False: 4.21k] | Branch (356:21): [True: 5.89k, False: 0] ------------------ 357| 5.89k| static_cast(Bucket)->Destroy(Allocator); 358| 5.89k| } 359| 10.1k| Bucket = nullptr; 360| 10.1k| } 361| | 362| 430| NumItems = 0; 363| 430| NumTombstones = 0; 364| 430| } _ZN7llvm_ks9StringMapIPNS_8MCSymbolERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEEixENS_9StringRefE: 298| 14.3k| ValueTy &operator[](StringRef Key) { 299| 14.3k| return insert(std::make_pair(Key, ValueTy())).first->second; 300| 14.3k| } _ZN7llvm_ks9StringMapIPNS_8MCSymbolERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE6insertENSt3__14pairINS_9StringRefES2_EE: 330| 14.3k| std::pair insert(std::pair KV) { 331| 14.3k| unsigned BucketNo = LookupBucketFor(KV.first); 332| 14.3k| StringMapEntryBase *&Bucket = TheTable[BucketNo]; 333| 14.3k| if (Bucket && Bucket != getTombstoneVal()) ------------------ | Branch (333:9): [True: 12.4k, False: 1.94k] | Branch (333:19): [True: 12.4k, False: 0] ------------------ 334| 12.4k| return std::make_pair(iterator(TheTable + BucketNo, false), 335| 12.4k| false); // Already exists in map. 336| | 337| 1.94k| if (Bucket == getTombstoneVal()) ------------------ | Branch (337:9): [True: 0, False: 1.94k] ------------------ 338| 0| --NumTombstones; 339| 1.94k| Bucket = 340| 1.94k| MapEntryTy::Create(KV.first, Allocator, std::move(KV.second)); 341| 1.94k| ++NumItems; 342| 1.94k| assert(NumItems + NumTombstones <= NumBuckets); ------------------ | Branch (342:5): [True: 1.94k, False: 0] ------------------ 343| | 344| 1.94k| BucketNo = RehashTable(BucketNo); 345| 1.94k| return std::make_pair(iterator(TheTable + BucketNo, false), true); 346| 1.94k| } _ZN7llvm_ks17StringMapIteratorIPNS_8MCSymbolEEC2EPPNS_18StringMapEntryBaseEb: 452| 14.3k| : StringMapConstIterator(Bucket, NoAdvance) { 453| 14.3k| } _ZN7llvm_ks22StringMapConstIteratorIPNS_8MCSymbolEEC2EPPNS_18StringMapEntryBaseEb: 412| 15.9k| : Ptr(Bucket) { 413| 15.9k| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (413:9): [True: 14.3k, False: 1.56k] ------------------ 414| 15.9k| } _ZN7llvm_ks22StringMapConstIteratorIPNS_8MCSymbolEE23AdvancePastEmptyBucketsEv: 440| 14.3k| void AdvancePastEmptyBuckets() { 441| 14.3k| while (*Ptr == nullptr || *Ptr == StringMapImpl::getTombstoneVal()) ------------------ | Branch (441:12): [True: 0, False: 14.3k] | Branch (441:31): [True: 0, False: 14.3k] ------------------ 442| 0| ++Ptr; 443| 14.3k| } _ZN7llvm_ks14StringMapEntryIPNS_8MCSymbolEE6CreateINS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEES2_EEPS3_NS_9StringRefERT_OT0_: 149| 1.94k| InitType &&InitVal) { 150| 1.94k| unsigned KeyLength = Key.size(); 151| | 152| | // Allocate a new item with space for the string at the end and a null 153| | // terminator. 154| 1.94k| unsigned AllocSize = static_cast(sizeof(StringMapEntry))+ 155| 1.94k| KeyLength+1; 156| 1.94k| unsigned Alignment = alignOf(); 157| | 158| 1.94k| StringMapEntry *NewItem = 159| 1.94k| static_cast(Allocator.Allocate(AllocSize,Alignment)); 160| | 161| | // Default construct the value. 162| 1.94k| new (NewItem) StringMapEntry(KeyLength, std::forward(InitVal)); 163| | 164| | // Copy the string information. 165| 1.94k| char *StrBuffer = const_cast(NewItem->getKeyData()); 166| 1.94k| if (KeyLength > 0) ------------------ | Branch (166:9): [True: 1.93k, False: 3] ------------------ 167| 1.93k| memcpy(StrBuffer, Key.data(), KeyLength); 168| 1.94k| StrBuffer[KeyLength] = 0; // Null terminate for convenience of clients. 169| 1.94k| return NewItem; 170| 1.94k| } _ZN7llvm_ks14StringMapEntryIPNS_8MCSymbolEEC2IS2_EEjOT_: 127| 1.94k| : StringMapEntryBase(strLen), second(std::forward(V)) {} _ZNK7llvm_ks14StringMapEntryIPNS_8MCSymbolEE10getKeyDataEv: 141| 1.94k| const char *getKeyData() const {return reinterpret_cast(this+1);} _ZNK7llvm_ks17StringMapIteratorIPNS_8MCSymbolEEptEv: 457| 14.3k| StringMapEntry *operator->() const { 458| 14.3k| return static_cast*>(*this->Ptr); 459| 14.3k| } _ZN7llvm_ks9StringMapIbRNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE6insertENSt3__14pairINS_9StringRefEbEE: 330| 11.7k| std::pair insert(std::pair KV) { 331| 11.7k| unsigned BucketNo = LookupBucketFor(KV.first); 332| 11.7k| StringMapEntryBase *&Bucket = TheTable[BucketNo]; 333| 11.7k| if (Bucket && Bucket != getTombstoneVal()) ------------------ | Branch (333:9): [True: 1, False: 11.7k] | Branch (333:19): [True: 1, False: 0] ------------------ 334| 1| return std::make_pair(iterator(TheTable + BucketNo, false), 335| 1| false); // Already exists in map. 336| | 337| 11.7k| if (Bucket == getTombstoneVal()) ------------------ | Branch (337:9): [True: 0, False: 11.7k] ------------------ 338| 0| --NumTombstones; 339| 11.7k| Bucket = 340| 11.7k| MapEntryTy::Create(KV.first, Allocator, std::move(KV.second)); 341| 11.7k| ++NumItems; 342| 11.7k| assert(NumItems + NumTombstones <= NumBuckets); ------------------ | Branch (342:5): [True: 11.7k, False: 0] ------------------ 343| | 344| 11.7k| BucketNo = RehashTable(BucketNo); 345| 11.7k| return std::make_pair(iterator(TheTable + BucketNo, false), true); 346| 11.7k| } _ZN7llvm_ks17StringMapIteratorIbEC2EPPNS_18StringMapEntryBaseEb: 452| 11.7k| : StringMapConstIterator(Bucket, NoAdvance) { 453| 11.7k| } _ZN7llvm_ks22StringMapConstIteratorIbEC2EPPNS_18StringMapEntryBaseEb: 412| 11.7k| : Ptr(Bucket) { 413| 11.7k| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (413:9): [True: 11.7k, False: 0] ------------------ 414| 11.7k| } _ZN7llvm_ks22StringMapConstIteratorIbE23AdvancePastEmptyBucketsEv: 440| 11.7k| void AdvancePastEmptyBuckets() { 441| 11.7k| while (*Ptr == nullptr || *Ptr == StringMapImpl::getTombstoneVal()) ------------------ | Branch (441:12): [True: 0, False: 11.7k] | Branch (441:31): [True: 0, False: 11.7k] ------------------ 442| 0| ++Ptr; 443| 11.7k| } _ZN7llvm_ks14StringMapEntryIbE6CreateINS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEbEEPS1_NS_9StringRefERT_OT0_: 149| 11.7k| InitType &&InitVal) { 150| 11.7k| unsigned KeyLength = Key.size(); 151| | 152| | // Allocate a new item with space for the string at the end and a null 153| | // terminator. 154| 11.7k| unsigned AllocSize = static_cast(sizeof(StringMapEntry))+ 155| 11.7k| KeyLength+1; 156| 11.7k| unsigned Alignment = alignOf(); 157| | 158| 11.7k| StringMapEntry *NewItem = 159| 11.7k| static_cast(Allocator.Allocate(AllocSize,Alignment)); 160| | 161| | // Default construct the value. 162| 11.7k| new (NewItem) StringMapEntry(KeyLength, std::forward(InitVal)); 163| | 164| | // Copy the string information. 165| 11.7k| char *StrBuffer = const_cast(NewItem->getKeyData()); 166| 11.7k| if (KeyLength > 0) ------------------ | Branch (166:9): [True: 11.7k, False: 3] ------------------ 167| 11.7k| memcpy(StrBuffer, Key.data(), KeyLength); 168| 11.7k| StrBuffer[KeyLength] = 0; // Null terminate for convenience of clients. 169| 11.7k| return NewItem; 170| 11.7k| } _ZN7llvm_ks14StringMapEntryIbEC2IbEEjOT_: 127| 11.7k| : StringMapEntryBase(strLen), second(std::forward(V)) {} _ZNK7llvm_ks17StringMapIteratorIbEdeEv: 454| 12.1k| StringMapEntry &operator*() const { 455| 12.1k| return *static_cast*>(*this->Ptr); 456| 12.1k| } _ZN7llvm_ks9StringMapIjNS_15MallocAllocatorEEixENS_9StringRefE: 298| 11.2k| ValueTy &operator[](StringRef Key) { 299| 11.2k| return insert(std::make_pair(Key, ValueTy())).first->second; 300| 11.2k| } _ZN7llvm_ks9StringMapIjNS_15MallocAllocatorEE6insertENSt3__14pairINS_9StringRefEjEE: 330| 11.2k| std::pair insert(std::pair KV) { 331| 11.2k| unsigned BucketNo = LookupBucketFor(KV.first); 332| 11.2k| StringMapEntryBase *&Bucket = TheTable[BucketNo]; 333| 11.2k| if (Bucket && Bucket != getTombstoneVal()) ------------------ | Branch (333:9): [True: 5.37k, False: 5.89k] | Branch (333:19): [True: 5.37k, False: 0] ------------------ 334| 5.37k| return std::make_pair(iterator(TheTable + BucketNo, false), 335| 5.37k| false); // Already exists in map. 336| | 337| 5.89k| if (Bucket == getTombstoneVal()) ------------------ | Branch (337:9): [True: 0, False: 5.89k] ------------------ 338| 0| --NumTombstones; 339| 5.89k| Bucket = 340| 5.89k| MapEntryTy::Create(KV.first, Allocator, std::move(KV.second)); 341| 5.89k| ++NumItems; 342| 5.89k| assert(NumItems + NumTombstones <= NumBuckets); ------------------ | Branch (342:5): [True: 5.89k, False: 0] ------------------ 343| | 344| 5.89k| BucketNo = RehashTable(BucketNo); 345| 5.89k| return std::make_pair(iterator(TheTable + BucketNo, false), true); 346| 5.89k| } _ZN7llvm_ks17StringMapIteratorIjEC2EPPNS_18StringMapEntryBaseEb: 452| 38.4k| : StringMapConstIterator(Bucket, NoAdvance) { 453| 38.4k| } _ZN7llvm_ks22StringMapConstIteratorIjEC2EPPNS_18StringMapEntryBaseEb: 412| 38.4k| : Ptr(Bucket) { 413| 38.4k| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (413:9): [True: 11.2k, False: 27.2k] ------------------ 414| 38.4k| } _ZN7llvm_ks22StringMapConstIteratorIjE23AdvancePastEmptyBucketsEv: 440| 11.2k| void AdvancePastEmptyBuckets() { 441| 11.2k| while (*Ptr == nullptr || *Ptr == StringMapImpl::getTombstoneVal()) ------------------ | Branch (441:12): [True: 0, False: 11.2k] | Branch (441:31): [True: 0, False: 11.2k] ------------------ 442| 0| ++Ptr; 443| 11.2k| } _ZN7llvm_ks14StringMapEntryIjE6CreateINS_15MallocAllocatorEjEEPS1_NS_9StringRefERT_OT0_: 149| 5.89k| InitType &&InitVal) { 150| 5.89k| unsigned KeyLength = Key.size(); 151| | 152| | // Allocate a new item with space for the string at the end and a null 153| | // terminator. 154| 5.89k| unsigned AllocSize = static_cast(sizeof(StringMapEntry))+ 155| 5.89k| KeyLength+1; 156| 5.89k| unsigned Alignment = alignOf(); 157| | 158| 5.89k| StringMapEntry *NewItem = 159| 5.89k| static_cast(Allocator.Allocate(AllocSize,Alignment)); 160| | 161| | // Default construct the value. 162| 5.89k| new (NewItem) StringMapEntry(KeyLength, std::forward(InitVal)); 163| | 164| | // Copy the string information. 165| 5.89k| char *StrBuffer = const_cast(NewItem->getKeyData()); 166| 5.89k| if (KeyLength > 0) ------------------ | Branch (166:9): [True: 5.89k, False: 0] ------------------ 167| 5.89k| memcpy(StrBuffer, Key.data(), KeyLength); 168| 5.89k| StrBuffer[KeyLength] = 0; // Null terminate for convenience of clients. 169| 5.89k| return NewItem; 170| 5.89k| } _ZN7llvm_ks14StringMapEntryIjEC2IjEEjOT_: 127| 5.89k| : StringMapEntryBase(strLen), second(std::forward(V)) {} _ZNK7llvm_ks14StringMapEntryIjE10getKeyDataEv: 141| 5.89k| const char *getKeyData() const {return reinterpret_cast(this+1);} _ZNK7llvm_ks17StringMapIteratorIjEptEv: 457| 11.2k| StringMapEntry *operator->() const { 458| 11.2k| return static_cast*>(*this->Ptr); 459| 11.2k| } _ZNK7llvm_ks9StringMapIPNS_8MCSymbolERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE6lookupENS_9StringRefE: 291| 783| ValueTy lookup(StringRef Key) const { 292| 783| const_iterator it = find(Key); 293| 783| if (it != end()) ------------------ | Branch (293:9): [True: 311, False: 472] ------------------ 294| 311| return it->second; 295| 472| return ValueTy(); 296| 783| } _ZNK7llvm_ks9StringMapIPNS_8MCSymbolERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE4findENS_9StringRefE: 283| 783| const_iterator find(StringRef Key) const { 284| 783| int Bucket = FindKey(Key); 285| 783| if (Bucket == -1) return end(); ------------------ | Branch (285:9): [True: 472, False: 311] ------------------ 286| 311| return const_iterator(TheTable+Bucket, true); 287| 783| } _ZNK7llvm_ks22StringMapConstIteratorIPNS_8MCSymbolEEneERKS3_: 426| 783| bool operator!=(const StringMapConstIterator &RHS) const { 427| 783| return Ptr != RHS.Ptr; 428| 783| } _ZNK7llvm_ks9StringMapIPNS_8MCSymbolERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE3endEv: 273| 1.25k| const_iterator end() const { 274| 1.25k| return const_iterator(TheTable+NumBuckets, true); 275| 1.25k| } _ZNK7llvm_ks22StringMapConstIteratorIPNS_8MCSymbolEEptEv: 419| 311| const value_type *operator->() const { 420| 311| return static_cast*>(*Ptr); 421| 311| } _ZN7llvm_ks9StringMapIPNS_14MCSectionMachOENS_15MallocAllocatorEEixENS_9StringRefE: 298| 143| ValueTy &operator[](StringRef Key) { 299| 143| return insert(std::make_pair(Key, ValueTy())).first->second; 300| 143| } _ZN7llvm_ks9StringMapIPNS_14MCSectionMachOENS_15MallocAllocatorEE6insertENSt3__14pairINS_9StringRefES2_EE: 330| 143| std::pair insert(std::pair KV) { 331| 143| unsigned BucketNo = LookupBucketFor(KV.first); 332| 143| StringMapEntryBase *&Bucket = TheTable[BucketNo]; 333| 143| if (Bucket && Bucket != getTombstoneVal()) ------------------ | Branch (333:9): [True: 139, False: 4] | Branch (333:19): [True: 139, False: 0] ------------------ 334| 139| return std::make_pair(iterator(TheTable + BucketNo, false), 335| 139| false); // Already exists in map. 336| | 337| 4| if (Bucket == getTombstoneVal()) ------------------ | Branch (337:9): [True: 0, False: 4] ------------------ 338| 0| --NumTombstones; 339| 4| Bucket = 340| 4| MapEntryTy::Create(KV.first, Allocator, std::move(KV.second)); 341| 4| ++NumItems; 342| 4| assert(NumItems + NumTombstones <= NumBuckets); ------------------ | Branch (342:5): [True: 4, False: 0] ------------------ 343| | 344| 4| BucketNo = RehashTable(BucketNo); 345| 4| return std::make_pair(iterator(TheTable + BucketNo, false), true); 346| 4| } _ZN7llvm_ks17StringMapIteratorIPNS_14MCSectionMachOEEC2EPPNS_18StringMapEntryBaseEb: 452| 143| : StringMapConstIterator(Bucket, NoAdvance) { 453| 143| } _ZN7llvm_ks22StringMapConstIteratorIPNS_14MCSectionMachOEEC2EPPNS_18StringMapEntryBaseEb: 412| 143| : Ptr(Bucket) { 413| 143| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (413:9): [True: 143, False: 0] ------------------ 414| 143| } _ZN7llvm_ks22StringMapConstIteratorIPNS_14MCSectionMachOEE23AdvancePastEmptyBucketsEv: 440| 143| void AdvancePastEmptyBuckets() { 441| 143| while (*Ptr == nullptr || *Ptr == StringMapImpl::getTombstoneVal()) ------------------ | Branch (441:12): [True: 0, False: 143] | Branch (441:31): [True: 0, False: 143] ------------------ 442| 0| ++Ptr; 443| 143| } _ZN7llvm_ks14StringMapEntryIPNS_14MCSectionMachOEE6CreateINS_15MallocAllocatorES2_EEPS3_NS_9StringRefERT_OT0_: 149| 4| InitType &&InitVal) { 150| 4| unsigned KeyLength = Key.size(); 151| | 152| | // Allocate a new item with space for the string at the end and a null 153| | // terminator. 154| 4| unsigned AllocSize = static_cast(sizeof(StringMapEntry))+ 155| 4| KeyLength+1; 156| 4| unsigned Alignment = alignOf(); 157| | 158| 4| StringMapEntry *NewItem = 159| 4| static_cast(Allocator.Allocate(AllocSize,Alignment)); 160| | 161| | // Default construct the value. 162| 4| new (NewItem) StringMapEntry(KeyLength, std::forward(InitVal)); 163| | 164| | // Copy the string information. 165| 4| char *StrBuffer = const_cast(NewItem->getKeyData()); 166| 4| if (KeyLength > 0) ------------------ | Branch (166:9): [True: 4, False: 0] ------------------ 167| 4| memcpy(StrBuffer, Key.data(), KeyLength); 168| 4| StrBuffer[KeyLength] = 0; // Null terminate for convenience of clients. 169| 4| return NewItem; 170| 4| } _ZN7llvm_ks14StringMapEntryIPNS_14MCSectionMachOEEC2IS2_EEjOT_: 127| 4| : StringMapEntryBase(strLen), second(std::forward(V)) {} _ZNK7llvm_ks14StringMapEntryIPNS_14MCSectionMachOEE10getKeyDataEv: 141| 4| const char *getKeyData() const {return reinterpret_cast(this+1);} _ZNK7llvm_ks17StringMapIteratorIPNS_14MCSectionMachOEEptEv: 457| 143| StringMapEntry *operator->() const { 458| 143| return static_cast*>(*this->Ptr); 459| 143| } _ZN7llvm_ks17StringMapIteratorIbEC2Ev: 449| 25| StringMapIterator() {} _ZN7llvm_ks22StringMapConstIteratorIbEC2Ev: 408| 25| StringMapConstIterator() : Ptr(nullptr) { } _ZN7llvm_ks9StringMapIbNS_15MallocAllocatorEE6insertENSt3__14pairINS_9StringRefEbEE: 330| 25| std::pair insert(std::pair KV) { 331| 25| unsigned BucketNo = LookupBucketFor(KV.first); 332| 25| StringMapEntryBase *&Bucket = TheTable[BucketNo]; 333| 25| if (Bucket && Bucket != getTombstoneVal()) ------------------ | Branch (333:9): [True: 0, False: 25] | Branch (333:19): [True: 0, False: 0] ------------------ 334| 0| return std::make_pair(iterator(TheTable + BucketNo, false), 335| 0| false); // Already exists in map. 336| | 337| 25| if (Bucket == getTombstoneVal()) ------------------ | Branch (337:9): [True: 0, False: 25] ------------------ 338| 0| --NumTombstones; 339| 25| Bucket = 340| 25| MapEntryTy::Create(KV.first, Allocator, std::move(KV.second)); 341| 25| ++NumItems; 342| 25| assert(NumItems + NumTombstones <= NumBuckets); ------------------ | Branch (342:5): [True: 25, False: 0] ------------------ 343| | 344| 25| BucketNo = RehashTable(BucketNo); 345| 25| return std::make_pair(iterator(TheTable + BucketNo, false), true); 346| 25| } _ZN7llvm_ks14StringMapEntryIbE6CreateINS_15MallocAllocatorEbEEPS1_NS_9StringRefERT_OT0_: 149| 25| InitType &&InitVal) { 150| 25| unsigned KeyLength = Key.size(); 151| | 152| | // Allocate a new item with space for the string at the end and a null 153| | // terminator. 154| 25| unsigned AllocSize = static_cast(sizeof(StringMapEntry))+ 155| 25| KeyLength+1; 156| 25| unsigned Alignment = alignOf(); 157| | 158| 25| StringMapEntry *NewItem = 159| 25| static_cast(Allocator.Allocate(AllocSize,Alignment)); 160| | 161| | // Default construct the value. 162| 25| new (NewItem) StringMapEntry(KeyLength, std::forward(InitVal)); 163| | 164| | // Copy the string information. 165| 25| char *StrBuffer = const_cast(NewItem->getKeyData()); 166| 25| if (KeyLength > 0) ------------------ | Branch (166:9): [True: 25, False: 0] ------------------ 167| 25| memcpy(StrBuffer, Key.data(), KeyLength); 168| 25| StrBuffer[KeyLength] = 0; // Null terminate for convenience of clients. 169| 25| return NewItem; 170| 25| } _ZNK7llvm_ks17StringMapIteratorIbEptEv: 457| 25| StringMapEntry *operator->() const { 458| 25| return static_cast*>(*this->Ptr); 459| 25| } _ZNK7llvm_ks14StringMapEntryIbE6getKeyEv: 129| 25| StringRef getKey() const { 130| 25| return StringRef(getKeyData(), getKeyLength()); 131| 25| } _ZN7llvm_ks9StringMapINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEENS_15MallocAllocatorEEC2Ev: 224| 430| StringMap() : StringMapImpl(static_cast(sizeof(MapEntryTy))) {} AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_110MCAsmMacroENS_15MallocAllocatorEEC2Ev: 224| 430| StringMap() : StringMapImpl(static_cast(sizeof(MapEntryTy))) {} AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_19AsmParser13DirectiveKindENS_15MallocAllocatorEEC2Ev: 224| 430| StringMap() : StringMapImpl(static_cast(sizeof(MapEntryTy))) {} AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_19AsmParser13DirectiveKindENS_15MallocAllocatorEED2Ev: 385| 430| ~StringMap() { 386| | // Delete all the elements in the map, but don't reset the elements 387| | // to default values. This is a copy of clear(), but avoids unnecessary 388| | // work not required in the destructor. 389| 430| if (!empty()) { ------------------ | Branch (389:9): [True: 430, False: 0] ------------------ 390| 110k| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (390:44): [True: 110k, False: 430] ------------------ 391| 110k| StringMapEntryBase *Bucket = TheTable[I]; 392| 110k| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (392:13): [True: 52.4k, False: 57.6k] | Branch (392:23): [True: 52.4k, False: 0] ------------------ 393| 52.4k| static_cast(Bucket)->Destroy(Allocator); 394| 52.4k| } 395| 110k| } 396| 430| } 397| 430| free(TheTable); 398| 430| } AsmParser.cpp:_ZN7llvm_ks14StringMapEntryIN12_GLOBAL__N_19AsmParser13DirectiveKindEE7DestroyINS_15MallocAllocatorEEEvRT_: 198| 52.4k| void Destroy(AllocatorTy &Allocator) { 199| | // Free memory referenced by the item. 200| 52.4k| unsigned AllocSize = 201| 52.4k| static_cast(sizeof(StringMapEntry)) + getKeyLength() + 1; 202| 52.4k| this->~StringMapEntry(); 203| 52.4k| Allocator.Deallocate(static_cast(this), AllocSize); 204| 52.4k| } AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_110MCAsmMacroENS_15MallocAllocatorEED2Ev: 385| 430| ~StringMap() { 386| | // Delete all the elements in the map, but don't reset the elements 387| | // to default values. This is a copy of clear(), but avoids unnecessary 388| | // work not required in the destructor. 389| 430| if (!empty()) { ------------------ | Branch (389:9): [True: 15, False: 415] ------------------ 390| 255| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (390:44): [True: 240, False: 15] ------------------ 391| 240| StringMapEntryBase *Bucket = TheTable[I]; 392| 240| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (392:13): [True: 15, False: 225] | Branch (392:23): [True: 15, False: 0] ------------------ 393| 15| static_cast(Bucket)->Destroy(Allocator); 394| 15| } 395| 240| } 396| 15| } 397| 430| free(TheTable); 398| 430| } AsmParser.cpp:_ZN7llvm_ks14StringMapEntryIN12_GLOBAL__N_110MCAsmMacroEE7DestroyINS_15MallocAllocatorEEEvRT_: 198| 15| void Destroy(AllocatorTy &Allocator) { 199| | // Free memory referenced by the item. 200| 15| unsigned AllocSize = 201| 15| static_cast(sizeof(StringMapEntry)) + getKeyLength() + 1; 202| 15| this->~StringMapEntry(); 203| 15| Allocator.Deallocate(static_cast(this), AllocSize); 204| 15| } _ZN7llvm_ks9StringMapINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEENS_15MallocAllocatorEED2Ev: 385| 430| ~StringMap() { 386| | // Delete all the elements in the map, but don't reset the elements 387| | // to default values. This is a copy of clear(), but avoids unnecessary 388| | // work not required in the destructor. 389| 430| if (!empty()) { ------------------ | Branch (389:9): [True: 430, False: 0] ------------------ 390| 55.4k| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (390:44): [True: 55.0k, False: 430] ------------------ 391| 55.0k| StringMapEntryBase *Bucket = TheTable[I]; 392| 55.0k| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (392:13): [True: 28.3k, False: 26.6k] | Branch (392:23): [True: 28.3k, False: 0] ------------------ 393| 28.3k| static_cast(Bucket)->Destroy(Allocator); 394| 28.3k| } 395| 55.0k| } 396| 430| } 397| 430| free(TheTable); 398| 430| } _ZN7llvm_ks14StringMapEntryINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEE7DestroyINS_15MallocAllocatorEEEvRT_: 198| 28.3k| void Destroy(AllocatorTy &Allocator) { 199| | // Free memory referenced by the item. 200| 28.3k| unsigned AllocSize = 201| 28.3k| static_cast(sizeof(StringMapEntry)) + getKeyLength() + 1; 202| 28.3k| this->~StringMapEntry(); 203| 28.3k| Allocator.Deallocate(static_cast(this), AllocSize); 204| 28.3k| } _ZN7llvm_ks9StringMapINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEENS_15MallocAllocatorEEixES5_: 298| 28.3k| ValueTy &operator[](StringRef Key) { 299| 28.3k| return insert(std::make_pair(Key, ValueTy())).first->second; 300| 28.3k| } _ZN7llvm_ks9StringMapINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEENS_15MallocAllocatorEE6insertENS2_IS5_S9_EE: 330| 28.3k| std::pair insert(std::pair KV) { 331| 28.3k| unsigned BucketNo = LookupBucketFor(KV.first); 332| 28.3k| StringMapEntryBase *&Bucket = TheTable[BucketNo]; 333| 28.3k| if (Bucket && Bucket != getTombstoneVal()) ------------------ | Branch (333:9): [True: 0, False: 28.3k] | Branch (333:19): [True: 0, False: 0] ------------------ 334| 0| return std::make_pair(iterator(TheTable + BucketNo, false), 335| 0| false); // Already exists in map. 336| | 337| 28.3k| if (Bucket == getTombstoneVal()) ------------------ | Branch (337:9): [True: 0, False: 28.3k] ------------------ 338| 0| --NumTombstones; 339| 28.3k| Bucket = 340| 28.3k| MapEntryTy::Create(KV.first, Allocator, std::move(KV.second)); 341| 28.3k| ++NumItems; 342| 28.3k| assert(NumItems + NumTombstones <= NumBuckets); ------------------ | Branch (342:5): [True: 28.3k, False: 0] ------------------ 343| | 344| 28.3k| BucketNo = RehashTable(BucketNo); 345| 28.3k| return std::make_pair(iterator(TheTable + BucketNo, false), true); 346| 28.3k| } _ZN7llvm_ks17StringMapIteratorINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEEC2EPPNS_18StringMapEntryBaseEb: 452| 28.3k| : StringMapConstIterator(Bucket, NoAdvance) { 453| 28.3k| } _ZN7llvm_ks22StringMapConstIteratorINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEEC2EPPNS_18StringMapEntryBaseEb: 412| 45.4k| : Ptr(Bucket) { 413| 45.4k| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (413:9): [True: 28.3k, False: 17.0k] ------------------ 414| 45.4k| } _ZN7llvm_ks22StringMapConstIteratorINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEE23AdvancePastEmptyBucketsEv: 440| 28.3k| void AdvancePastEmptyBuckets() { 441| 28.3k| while (*Ptr == nullptr || *Ptr == StringMapImpl::getTombstoneVal()) ------------------ | Branch (441:12): [True: 0, False: 28.3k] | Branch (441:31): [True: 0, False: 28.3k] ------------------ 442| 0| ++Ptr; 443| 28.3k| } _ZN7llvm_ks14StringMapEntryINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEE6CreateINS_15MallocAllocatorES9_EEPSA_S5_RT_OT0_: 149| 28.3k| InitType &&InitVal) { 150| 28.3k| unsigned KeyLength = Key.size(); 151| | 152| | // Allocate a new item with space for the string at the end and a null 153| | // terminator. 154| 28.3k| unsigned AllocSize = static_cast(sizeof(StringMapEntry))+ 155| 28.3k| KeyLength+1; 156| 28.3k| unsigned Alignment = alignOf(); 157| | 158| 28.3k| StringMapEntry *NewItem = 159| 28.3k| static_cast(Allocator.Allocate(AllocSize,Alignment)); 160| | 161| | // Default construct the value. 162| 28.3k| new (NewItem) StringMapEntry(KeyLength, std::forward(InitVal)); 163| | 164| | // Copy the string information. 165| 28.3k| char *StrBuffer = const_cast(NewItem->getKeyData()); 166| 28.3k| if (KeyLength > 0) ------------------ | Branch (166:9): [True: 28.3k, False: 0] ------------------ 167| 28.3k| memcpy(StrBuffer, Key.data(), KeyLength); 168| 28.3k| StrBuffer[KeyLength] = 0; // Null terminate for convenience of clients. 169| 28.3k| return NewItem; 170| 28.3k| } _ZN7llvm_ks14StringMapEntryINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEEC2IS9_EEjOT_: 127| 28.3k| : StringMapEntryBase(strLen), second(std::forward(V)) {} _ZNK7llvm_ks14StringMapEntryINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEE10getKeyDataEv: 141| 28.3k| const char *getKeyData() const {return reinterpret_cast(this+1);} _ZNK7llvm_ks17StringMapIteratorINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEEptEv: 457| 28.3k| StringMapEntry *operator->() const { 458| 28.3k| return static_cast*>(*this->Ptr); 459| 28.3k| } AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_19AsmParser13DirectiveKindENS_15MallocAllocatorEEixENS_9StringRefE: 298| 52.4k| ValueTy &operator[](StringRef Key) { 299| 52.4k| return insert(std::make_pair(Key, ValueTy())).first->second; 300| 52.4k| } AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_19AsmParser13DirectiveKindENS_15MallocAllocatorEE6insertENSt3__14pairINS_9StringRefES3_EE: 330| 52.4k| std::pair insert(std::pair KV) { 331| 52.4k| unsigned BucketNo = LookupBucketFor(KV.first); 332| 52.4k| StringMapEntryBase *&Bucket = TheTable[BucketNo]; 333| 52.4k| if (Bucket && Bucket != getTombstoneVal()) ------------------ | Branch (333:9): [True: 0, False: 52.4k] | Branch (333:19): [True: 0, False: 0] ------------------ 334| 0| return std::make_pair(iterator(TheTable + BucketNo, false), 335| 0| false); // Already exists in map. 336| | 337| 52.4k| if (Bucket == getTombstoneVal()) ------------------ | Branch (337:9): [True: 0, False: 52.4k] ------------------ 338| 0| --NumTombstones; 339| 52.4k| Bucket = 340| 52.4k| MapEntryTy::Create(KV.first, Allocator, std::move(KV.second)); 341| 52.4k| ++NumItems; 342| 52.4k| assert(NumItems + NumTombstones <= NumBuckets); ------------------ | Branch (342:5): [True: 52.4k, False: 0] ------------------ 343| | 344| 52.4k| BucketNo = RehashTable(BucketNo); 345| 52.4k| return std::make_pair(iterator(TheTable + BucketNo, false), true); 346| 52.4k| } AsmParser.cpp:_ZN7llvm_ks17StringMapIteratorIN12_GLOBAL__N_19AsmParser13DirectiveKindEEC2EPPNS_18StringMapEntryBaseEb: 452| 100k| : StringMapConstIterator(Bucket, NoAdvance) { 453| 100k| } AsmParser.cpp:_ZN7llvm_ks22StringMapConstIteratorIN12_GLOBAL__N_19AsmParser13DirectiveKindEEC2EPPNS_18StringMapEntryBaseEb: 412| 100k| : Ptr(Bucket) { 413| 100k| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (413:9): [True: 52.4k, False: 47.9k] ------------------ 414| 100k| } AsmParser.cpp:_ZN7llvm_ks22StringMapConstIteratorIN12_GLOBAL__N_19AsmParser13DirectiveKindEE23AdvancePastEmptyBucketsEv: 440| 52.4k| void AdvancePastEmptyBuckets() { 441| 52.4k| while (*Ptr == nullptr || *Ptr == StringMapImpl::getTombstoneVal()) ------------------ | Branch (441:12): [True: 0, False: 52.4k] | Branch (441:31): [True: 0, False: 52.4k] ------------------ 442| 0| ++Ptr; 443| 52.4k| } AsmParser.cpp:_ZN7llvm_ks14StringMapEntryIN12_GLOBAL__N_19AsmParser13DirectiveKindEE6CreateINS_15MallocAllocatorES3_EEPS4_NS_9StringRefERT_OT0_: 149| 52.4k| InitType &&InitVal) { 150| 52.4k| unsigned KeyLength = Key.size(); 151| | 152| | // Allocate a new item with space for the string at the end and a null 153| | // terminator. 154| 52.4k| unsigned AllocSize = static_cast(sizeof(StringMapEntry))+ 155| 52.4k| KeyLength+1; 156| 52.4k| unsigned Alignment = alignOf(); 157| | 158| 52.4k| StringMapEntry *NewItem = 159| 52.4k| static_cast(Allocator.Allocate(AllocSize,Alignment)); 160| | 161| | // Default construct the value. 162| 52.4k| new (NewItem) StringMapEntry(KeyLength, std::forward(InitVal)); 163| | 164| | // Copy the string information. 165| 52.4k| char *StrBuffer = const_cast(NewItem->getKeyData()); 166| 52.4k| if (KeyLength > 0) ------------------ | Branch (166:9): [True: 52.4k, False: 0] ------------------ 167| 52.4k| memcpy(StrBuffer, Key.data(), KeyLength); 168| 52.4k| StrBuffer[KeyLength] = 0; // Null terminate for convenience of clients. 169| 52.4k| return NewItem; 170| 52.4k| } AsmParser.cpp:_ZN7llvm_ks14StringMapEntryIN12_GLOBAL__N_19AsmParser13DirectiveKindEEC2IS3_EEjOT_: 127| 52.4k| : StringMapEntryBase(strLen), second(std::forward(V)) {} AsmParser.cpp:_ZNK7llvm_ks14StringMapEntryIN12_GLOBAL__N_19AsmParser13DirectiveKindEE10getKeyDataEv: 141| 52.4k| const char *getKeyData() const {return reinterpret_cast(this+1);} AsmParser.cpp:_ZNK7llvm_ks17StringMapIteratorIN12_GLOBAL__N_19AsmParser13DirectiveKindEEptEv: 457| 52.4k| StringMapEntry *operator->() const { 458| 52.4k| return static_cast*>(*this->Ptr); 459| 52.4k| } AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_19AsmParser13DirectiveKindENS_15MallocAllocatorEE4findENS_9StringRefE: 277| 23.9k| iterator find(StringRef Key) { 278| 23.9k| int Bucket = FindKey(Key); 279| 23.9k| if (Bucket == -1) return end(); ------------------ | Branch (279:9): [True: 13.6k, False: 10.2k] ------------------ 280| 10.2k| return iterator(TheTable+Bucket, true); 281| 23.9k| } AsmParser.cpp:_ZNK7llvm_ks22StringMapConstIteratorIN12_GLOBAL__N_19AsmParser13DirectiveKindEEeqERKS4_: 423| 23.9k| bool operator==(const StringMapConstIterator &RHS) const { 424| 23.9k| return Ptr == RHS.Ptr; 425| 23.9k| } AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_19AsmParser13DirectiveKindENS_15MallocAllocatorEE3endEv: 267| 37.6k| iterator end() { 268| 37.6k| return iterator(TheTable+NumBuckets, true); 269| 37.6k| } AsmParser.cpp:_ZNK7llvm_ks22StringMapConstIteratorIN12_GLOBAL__N_19AsmParser13DirectiveKindEEptEv: 419| 10.2k| const value_type *operator->() const { 420| 10.2k| return static_cast*>(*Ptr); 421| 10.2k| } AsmParser.cpp:_ZNK7llvm_ks14StringMapEntryIN12_GLOBAL__N_19AsmParser13DirectiveKindEE8getValueEv: 133| 10.2k| const ValueTy &getValue() const { return second; } AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_110MCAsmMacroENS_15MallocAllocatorEE4findENS_9StringRefE: 277| 17.9k| iterator find(StringRef Key) { 278| 17.9k| int Bucket = FindKey(Key); 279| 17.9k| if (Bucket == -1) return end(); ------------------ | Branch (279:9): [True: 17.7k, False: 225] ------------------ 280| 225| return iterator(TheTable+Bucket, true); 281| 17.9k| } AsmParser.cpp:_ZN7llvm_ks17StringMapIteratorIN12_GLOBAL__N_110MCAsmMacroEEC2EPPNS_18StringMapEntryBaseEb: 452| 35.8k| : StringMapConstIterator(Bucket, NoAdvance) { 453| 35.8k| } AsmParser.cpp:_ZN7llvm_ks22StringMapConstIteratorIN12_GLOBAL__N_110MCAsmMacroEEC2EPPNS_18StringMapEntryBaseEb: 412| 35.8k| : Ptr(Bucket) { 413| 35.8k| if (!NoAdvance) AdvancePastEmptyBuckets(); ------------------ | Branch (413:9): [True: 15, False: 35.8k] ------------------ 414| 35.8k| } AsmParser.cpp:_ZN7llvm_ks22StringMapConstIteratorIN12_GLOBAL__N_110MCAsmMacroEE23AdvancePastEmptyBucketsEv: 440| 15| void AdvancePastEmptyBuckets() { 441| 15| while (*Ptr == nullptr || *Ptr == StringMapImpl::getTombstoneVal()) ------------------ | Branch (441:12): [True: 0, False: 15] | Branch (441:31): [True: 0, False: 15] ------------------ 442| 0| ++Ptr; 443| 15| } AsmParser.cpp:_ZNK7llvm_ks22StringMapConstIteratorIN12_GLOBAL__N_110MCAsmMacroEEeqERKS3_: 423| 17.9k| bool operator==(const StringMapConstIterator &RHS) const { 424| 17.9k| return Ptr == RHS.Ptr; 425| 17.9k| } AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_110MCAsmMacroENS_15MallocAllocatorEE3endEv: 267| 35.6k| iterator end() { 268| 35.6k| return iterator(TheTable+NumBuckets, true); 269| 35.6k| } AsmParser.cpp:_ZNK7llvm_ks17StringMapIteratorIN12_GLOBAL__N_110MCAsmMacroEEptEv: 457| 225| StringMapEntry *operator->() const { 458| 225| return static_cast*>(*this->Ptr); 459| 225| } AsmParser.cpp:_ZN7llvm_ks14StringMapEntryIN12_GLOBAL__N_110MCAsmMacroEE8getValueEv: 134| 225| ValueTy &getValue() { return second; } _ZNK7llvm_ks9StringMapINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEENS_15MallocAllocatorEE6lookupES5_: 291| 8.54k| ValueTy lookup(StringRef Key) const { 292| 8.54k| const_iterator it = find(Key); 293| 8.54k| if (it != end()) ------------------ | Branch (293:9): [True: 847, False: 7.69k] ------------------ 294| 847| return it->second; 295| 7.69k| return ValueTy(); 296| 8.54k| } _ZNK7llvm_ks9StringMapINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEENS_15MallocAllocatorEE4findES5_: 283| 8.54k| const_iterator find(StringRef Key) const { 284| 8.54k| int Bucket = FindKey(Key); 285| 8.54k| if (Bucket == -1) return end(); ------------------ | Branch (285:9): [True: 7.69k, False: 847] ------------------ 286| 847| return const_iterator(TheTable+Bucket, true); 287| 8.54k| } _ZNK7llvm_ks22StringMapConstIteratorINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEEneERKSA_: 426| 8.54k| bool operator!=(const StringMapConstIterator &RHS) const { 427| 8.54k| return Ptr != RHS.Ptr; 428| 8.54k| } _ZNK7llvm_ks9StringMapINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEENS_15MallocAllocatorEE3endEv: 273| 16.2k| const_iterator end() const { 274| 16.2k| return const_iterator(TheTable+NumBuckets, true); 275| 16.2k| } _ZNK7llvm_ks22StringMapConstIteratorINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS4_NS_9StringRefENS_5SMLocEEEEEptEv: 419| 847| const value_type *operator->() const { 420| 847| return static_cast*>(*Ptr); 421| 847| } AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_110MCAsmMacroENS_15MallocAllocatorEE6insertENSt3__14pairINS_9StringRefES2_EE: 330| 15| std::pair insert(std::pair KV) { 331| 15| unsigned BucketNo = LookupBucketFor(KV.first); 332| 15| StringMapEntryBase *&Bucket = TheTable[BucketNo]; 333| 15| if (Bucket && Bucket != getTombstoneVal()) ------------------ | Branch (333:9): [True: 0, False: 15] | Branch (333:19): [True: 0, False: 0] ------------------ 334| 0| return std::make_pair(iterator(TheTable + BucketNo, false), 335| 0| false); // Already exists in map. 336| | 337| 15| if (Bucket == getTombstoneVal()) ------------------ | Branch (337:9): [True: 0, False: 15] ------------------ 338| 0| --NumTombstones; 339| 15| Bucket = 340| 15| MapEntryTy::Create(KV.first, Allocator, std::move(KV.second)); 341| 15| ++NumItems; 342| 15| assert(NumItems + NumTombstones <= NumBuckets); ------------------ | Branch (342:5): [True: 15, False: 0] ------------------ 343| | 344| 15| BucketNo = RehashTable(BucketNo); 345| 15| return std::make_pair(iterator(TheTable + BucketNo, false), true); 346| 15| } AsmParser.cpp:_ZN7llvm_ks14StringMapEntryIN12_GLOBAL__N_110MCAsmMacroEE6CreateINS_15MallocAllocatorES2_EEPS3_NS_9StringRefERT_OT0_: 149| 15| InitType &&InitVal) { 150| 15| unsigned KeyLength = Key.size(); 151| | 152| | // Allocate a new item with space for the string at the end and a null 153| | // terminator. 154| 15| unsigned AllocSize = static_cast(sizeof(StringMapEntry))+ 155| 15| KeyLength+1; 156| 15| unsigned Alignment = alignOf(); 157| | 158| 15| StringMapEntry *NewItem = 159| 15| static_cast(Allocator.Allocate(AllocSize,Alignment)); 160| | 161| | // Default construct the value. 162| 15| new (NewItem) StringMapEntry(KeyLength, std::forward(InitVal)); 163| | 164| | // Copy the string information. 165| 15| char *StrBuffer = const_cast(NewItem->getKeyData()); 166| 15| if (KeyLength > 0) ------------------ | Branch (166:9): [True: 14, False: 1] ------------------ 167| 14| memcpy(StrBuffer, Key.data(), KeyLength); 168| 15| StrBuffer[KeyLength] = 0; // Null terminate for convenience of clients. 169| 15| return NewItem; 170| 15| } AsmParser.cpp:_ZN7llvm_ks14StringMapEntryIN12_GLOBAL__N_110MCAsmMacroEEC2IS2_EEjOT_: 127| 15| : StringMapEntryBase(strLen), second(std::forward(V)) {} AsmParser.cpp:_ZNK7llvm_ks14StringMapEntryIN12_GLOBAL__N_110MCAsmMacroEE10getKeyDataEv: 141| 15| const char *getKeyData() const {return reinterpret_cast(this+1);} AsmParser.cpp:_ZN7llvm_ks9StringMapIN12_GLOBAL__N_19AsmParser13DirectiveKindENS_15MallocAllocatorEE5clearEv: 349| 430| void clear() { 350| 430| if (empty()) return; ------------------ | Branch (350:9): [True: 430, False: 0] ------------------ 351| | 352| | // Zap all values, resetting the keys back to non-present (not tombstone), 353| | // which is safe because we're removing all elements. 354| 0| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (354:42): [True: 0, False: 0] ------------------ 355| 0| StringMapEntryBase *&Bucket = TheTable[I]; 356| 0| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (356:11): [True: 0, False: 0] | Branch (356:21): [True: 0, False: 0] ------------------ 357| 0| static_cast(Bucket)->Destroy(Allocator); 358| 0| } 359| 0| Bucket = nullptr; 360| 0| } 361| | 362| 0| NumItems = 0; 363| 0| NumTombstones = 0; 364| 0| } _ZN7llvm_ks9StringMapIjNS_15MallocAllocatorEE4findENS_9StringRefE: 277| 13.6k| iterator find(StringRef Key) { 278| 13.6k| int Bucket = FindKey(Key); 279| 13.6k| if (Bucket == -1) return end(); ------------------ | Branch (279:9): [True: 13.6k, False: 0] ------------------ 280| 0| return iterator(TheTable+Bucket, true); 281| 13.6k| } _ZNK7llvm_ks22StringMapConstIteratorIjEeqERKS1_: 423| 13.6k| bool operator==(const StringMapConstIterator &RHS) const { 424| 13.6k| return Ptr == RHS.Ptr; 425| 13.6k| } _ZN7llvm_ks9StringMapIjNS_15MallocAllocatorEE3endEv: 267| 27.2k| iterator end() { 268| 27.2k| return iterator(TheTable+NumBuckets, true); 269| 27.2k| } _ZN7llvm_ks9StringRefC2ERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE: 91| 135k| : Data(Str.data()), Length(Str.length()) {} _ZN7llvm_ks9StringRefC2EPKc: 72| 2.84M| : Data(Str) { 73| | //assert(Str && "StringRef cannot be built from a NULL argument"); 74| 2.84M| if (!Str) ------------------ | Branch (74:13): [True: 0, False: 2.84M] ------------------ 75| 0| Length = 0; 76| 2.84M| else 77| 2.84M| Length = ::strlen(Str); // invoking strlen(NULL) is undefined behavior 78| 2.84M| } _ZN7llvm_ks9StringRef13compareMemoryEPKcS2_m: 58| 1.91M| static int compareMemory(const char *Lhs, const char *Rhs, size_t Length) { 59| 1.91M| if (Length == 0) { return 0; } ------------------ | Branch (59:11): [True: 770, False: 1.91M] ------------------ 60| 1.91M| return ::memcmp(Lhs,Rhs,Length); 61| 1.91M| } _ZN7llvm_ks9StringRefC2Ev: 68| 101k| /*implicit*/ StringRef() : Data(nullptr), Length(0) {} _ZN7llvm_ks9StringRefC2EPKcm: 83| 1.52M| : Data(data), Length(length) { 84| | assert((data || length == 0) && ------------------ | Branch (84:9): [True: 1.52M, False: 0] | Branch (84:9): [True: 0, False: 0] | Branch (84:9): [True: 1.52M, Folded] | Branch (84:9): [True: 1.52M, False: 0] ------------------ 85| 1.52M| "StringRef cannot be built from a NULL argument with non-null length"); 86| 1.52M| } _ZNK7llvm_ks9StringRef5beginEv: 97| 28.0k| iterator begin() const { return Data; } _ZNK7llvm_ks9StringRef3endEv: 99| 374k| iterator end() const { return Data + Length; } _ZNK7llvm_ks9StringRef4dataEv: 115| 549k| const char *data() const { return Data; } _ZNK7llvm_ks9StringRef5emptyEv: 119| 301k| bool empty() const { return Length == 0; } _ZNK7llvm_ks9StringRef4sizeEv: 123| 1.53M| size_t size() const { return Length; } _ZNK7llvm_ks9StringRef5frontEv: 126| 22.7k| char front() const { 127| 22.7k| assert(!empty()); ------------------ | Branch (127:7): [True: 22.7k, False: 0] ------------------ 128| 22.7k| return Data[0]; 129| 22.7k| } _ZNK7llvm_ks9StringRef6equalsES0_: 147| 1.38M| bool equals(StringRef RHS) const { 148| 1.38M| return (Length == RHS.Length && ------------------ | Branch (148:15): [True: 523k, False: 857k] ------------------ 149| 523k| compareMemory(Data, RHS.Data, RHS.Length) == 0); ------------------ | Branch (149:15): [True: 344k, False: 179k] ------------------ 150| 1.38M| } _ZNK7llvm_ks9StringRef7compareES0_: 160| 974k| int compare(StringRef RHS) const { 161| | // Check the prefix for a mismatch. 162| 974k| if (int Res = compareMemory(Data, RHS.Data, std::min(Length, RHS.Length))) ------------------ | Branch (162:15): [True: 752k, False: 221k] ------------------ 163| 752k| return Res < 0 ? -1 : 1; ------------------ | Branch (163:16): [True: 221k, False: 531k] ------------------ 164| | 165| | // Otherwise the prefixes match, so we only need to check the lengths. 166| 221k| if (Length == RHS.Length) ------------------ | Branch (166:11): [True: 90.5k, False: 131k] ------------------ 167| 90.5k| return 0; 168| 131k| return Length < RHS.Length ? -1 : 1; ------------------ | Branch (168:14): [True: 31.5k, False: 99.9k] ------------------ 169| 221k| } _ZNK7llvm_ks9StringRef3strEv: 200| 43.4k| std::string str() const { 201| 43.4k| if (!Data) return std::string(); ------------------ | Branch (201:11): [True: 0, False: 43.4k] ------------------ 202| 43.4k| return std::string(Data, Length); 203| 43.4k| } _ZNK7llvm_ks9StringRefixEm: 209| 2.33M| char operator[](size_t Index) const { 210| 2.33M| assert(Index < Length && "Invalid index!"); ------------------ | Branch (210:7): [True: 2.33M, False: 0] | Branch (210:7): [True: 2.33M, Folded] | Branch (210:7): [True: 2.33M, False: 0] ------------------ 211| 2.33M| return Data[Index]; 212| 2.33M| } _ZNK7llvm_ks9StringRefcvNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEEEv: 218| 36.3k| operator std::string() const { 219| 36.3k| return str(); 220| 36.3k| } _ZNK7llvm_ks9StringRef10startswithES0_: 228| 200k| bool startswith(StringRef Prefix) const { 229| 200k| return Length >= Prefix.Length && ------------------ | Branch (229:14): [True: 85.3k, False: 115k] ------------------ 230| 85.3k| compareMemory(Data, Prefix.Data, Prefix.Length) == 0; ------------------ | Branch (230:14): [True: 19.2k, False: 66.0k] ------------------ 231| 200k| } _ZNK7llvm_ks9StringRef8endswithES0_: 238| 338k| bool endswith(StringRef Suffix) const { 239| 338k| return Length >= Suffix.Length && ------------------ | Branch (239:14): [True: 335k, False: 2.64k] ------------------ 240| 335k| compareMemory(end() - Suffix.Length, Suffix.Data, Suffix.Length) == 0; ------------------ | Branch (240:9): [True: 29.3k, False: 306k] ------------------ 241| 338k| } _ZNK7llvm_ks9StringRef4findEcm: 255| 20.2k| size_t find(char C, size_t From = 0) const { 256| 20.2k| size_t FindBegin = std::min(From, Length); 257| 20.2k| if (FindBegin < Length) { // Avoid calling memchr with nullptr. ------------------ | Branch (257:11): [True: 20.2k, False: 68] ------------------ 258| | // Just forward to memchr, which is faster than a hand-rolled loop. 259| 20.2k| if (const void *P = ::memchr(Data + FindBegin, C, Length - FindBegin)) ------------------ | Branch (259:25): [True: 6.55k, False: 13.6k] ------------------ 260| 6.55k| return static_cast(P) - Data; 261| 20.2k| } 262| 13.7k| return npos; 263| 20.2k| } _ZNK7llvm_ks9StringRef6substrEmm: 421| 122k| StringRef substr(size_t Start, size_t N = npos) const { 422| 122k| Start = std::min(Start, Length); 423| 122k| return StringRef(Data + Start, std::min(N, Length - Start)); 424| 122k| } _ZNK7llvm_ks9StringRef10drop_frontEm: 429| 3.28k| StringRef drop_front(size_t N = 1) const { 430| 3.28k| assert(size() >= N && "Dropping more elements than exist"); ------------------ | Branch (430:7): [True: 3.28k, False: 0] | Branch (430:7): [True: 3.28k, Folded] | Branch (430:7): [True: 3.28k, False: 0] ------------------ 431| 3.28k| return substr(N); 432| 3.28k| } _ZNK7llvm_ks9StringRef9drop_backEm: 437| 3.28k| StringRef drop_back(size_t N = 1) const { 438| 3.28k| assert(size() >= N && "Dropping more elements than exist"); ------------------ | Branch (438:7): [True: 3.28k, False: 0] | Branch (438:7): [True: 3.28k, Folded] | Branch (438:7): [True: 3.28k, False: 0] ------------------ 439| 3.28k| return substr(0, size()-N); 440| 3.28k| } _ZNK7llvm_ks9StringRef5sliceEmm: 453| 13.7k| StringRef slice(size_t Start, size_t End) const { 454| 13.7k| Start = std::min(Start, Length); 455| 13.7k| End = std::min(std::max(Start, End), Length); 456| 13.7k| return StringRef(Data + Start, End - Start); 457| 13.7k| } _ZNK7llvm_ks9StringRef5splitEc: 469| 2.72k| std::pair split(char Separator) const { 470| 2.72k| size_t Idx = find(Separator); 471| 2.72k| if (Idx == npos) ------------------ | Branch (471:11): [True: 2.72k, False: 0] ------------------ 472| 2.72k| return std::make_pair(*this, StringRef()); 473| 0| return std::make_pair(slice(0, Idx), slice(Idx+1, npos)); 474| 2.72k| } _ZNK7llvm_ks9StringRef5ltrimES0_: 547| 3.28k| StringRef ltrim(StringRef Chars = " \t\n\v\f\r") const { 548| 3.28k| return drop_front(std::min(Length, find_first_not_of(Chars))); 549| 3.28k| } _ZNK7llvm_ks9StringRef5rtrimES0_: 553| 3.28k| StringRef rtrim(StringRef Chars = " \t\n\v\f\r") const { 554| 3.28k| return drop_back(Length - std::min(Length, find_last_not_of(Chars) + 1)); 555| 3.28k| } _ZNK7llvm_ks9StringRef4trimES0_: 559| 3.28k| StringRef trim(StringRef Chars = " \t\n\v\f\r") const { 560| 3.28k| return ltrim(Chars).rtrim(Chars); 561| 3.28k| } _ZN7llvm_kseqENS_9StringRefES0_: 579| 1.35M| inline bool operator==(StringRef LHS, StringRef RHS) { 580| 1.35M| return LHS.equals(RHS); 581| 1.35M| } _ZN7llvm_ksneENS_9StringRefES0_: 584| 68.8k| inline bool operator!=(StringRef LHS, StringRef RHS) { 585| 68.8k| return !(LHS == RHS); 586| 68.8k| } _ZN7llvm_ksltENS_9StringRefES0_: 588| 974k| inline bool operator<(StringRef LHS, StringRef RHS) { 589| 974k| return LHS.compare(RHS) == -1; 590| 974k| } _ZN7llvm_kspLERNSt3__112basic_stringIcNS0_11char_traitsIcEENS0_9allocatorIcEEEENS_9StringRefE: 604| 455| inline std::string &operator+=(std::string &buffer, StringRef string) { 605| 455| return buffer.append(string.data(), string.size()); 606| 455| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_EC2ENS_9StringRefE: 54| 228| : Str(S), Result(nullptr) { } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj4EEERS3_RAT__KcRKS2_: 58| 912| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 912| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 912, False: 0] | Branch (59:20): [True: 0, False: 912] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 912| return *this; 65| 912| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj7EEERS3_RAT__KcRKS2_: 58| 2.73k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 2.73k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 2.73k, False: 0] | Branch (59:20): [True: 828, False: 1.90k] ------------------ 60| 828| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 828] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 2.73k| return *this; 65| 2.73k| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj9EEERS3_RAT__KcRKS2_: 58| 2.05k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 2.05k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 2.05k, False: 0] | Branch (59:20): [True: 0, False: 2.05k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 2.05k| return *this; 65| 2.05k| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj10EEERS3_RAT__KcRKS2_: 58| 1.36k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 1.36k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 1.36k, False: 0] | Branch (59:20): [True: 120, False: 1.24k] ------------------ 60| 120| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 120] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 1.36k| return *this; 65| 1.36k| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj6EEERS3_RAT__KcRKS2_: 58| 3.64k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 3.64k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 3.64k, False: 0] | Branch (59:20): [True: 32, False: 3.61k] ------------------ 60| 32| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 32] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 3.64k| return *this; 65| 3.64k| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj5EEERS3_RAT__KcRKS2_: 58| 912| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 912| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 912, False: 0] | Branch (59:20): [True: 8, False: 904] ------------------ 60| 8| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 8] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 912| return *this; 65| 912| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj12EEERS3_RAT__KcRKS2_: 58| 1.59k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 1.59k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 1.59k, False: 0] | Branch (59:20): [True: 0, False: 1.59k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 1.59k| return *this; 65| 1.59k| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj8EEERS3_RAT__KcRKS2_: 58| 2.50k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 2.50k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 2.50k, False: 0] | Branch (59:20): [True: 440, False: 2.06k] ------------------ 60| 440| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 440] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 2.50k| return *this; 65| 2.50k| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj11EEERS3_RAT__KcRKS2_: 58| 456| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 456| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 456, False: 0] | Branch (59:20): [True: 0, False: 456] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 456| return *this; 65| 456| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj2EEERS3_RAT__KcRKS2_: 58| 456| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 456| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 456, False: 0] | Branch (59:20): [True: 0, False: 456] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 456| return *this; 65| 456| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj3EEERS3_RAT__KcRKS2_: 58| 456| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 456| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 456, False: 0] | Branch (59:20): [True: 0, False: 456] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 456| return *this; 65| 456| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj13EEERS3_RAT__KcRKS2_: 58| 1.36k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 1.36k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 1.36k, False: 0] | Branch (59:20): [True: 0, False: 1.36k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 1.36k| return *this; 65| 1.36k| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj14EEERS3_RAT__KcRKS2_: 58| 912| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 912| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 912, False: 0] | Branch (59:20): [True: 32, False: 880] ------------------ 60| 32| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 32] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 912| return *this; 65| 912| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj15EEERS3_RAT__KcRKS2_: 58| 684| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 684| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 684, False: 0] | Branch (59:20): [True: 0, False: 684] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 684| return *this; 65| 684| } _ZN7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E4CaseILj16EEERS3_RAT__KcRKS2_: 58| 228| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 228| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 228, False: 0] | Branch (59:20): [True: 0, False: 228] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 228| return *this; 65| 228| } _ZNK7llvm_ks12StringSwitchINS_15MCSymbolRefExpr11VariantKindES2_E7DefaultERKS2_: 150| 228| R Default(const T& Value) const { 151| 228| if (Result) ------------------ | Branch (151:9): [True: 0, False: 228] ------------------ 152| 0| return *Result; 153| | 154| 228| return Value; 155| 228| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_EC2ES1_: 54| 16.2k| : Str(S), Result(nullptr) { } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E4CaseILj14EEERS2_RAT__KcRKS1_: 58| 26| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 26| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 26, False: 0] | Branch (59:20): [True: 0, False: 26] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 26| return *this; 65| 26| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E4CaseILj13EEERS2_RAT__KcRKS1_: 58| 13| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 13| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 13, False: 0] | Branch (59:20): [True: 0, False: 13] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 13| return *this; 65| 13| } _ZNK7llvm_ks12StringSwitchINS_9StringRefES1_E7DefaultERKS1_: 150| 16.2k| R Default(const T& Value) const { 151| 16.2k| if (Result) ------------------ | Branch (151:9): [True: 15.5k, False: 665] ------------------ 152| 15.5k| return *Result; 153| | 154| 665| return Value; 155| 16.2k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj5ELj5ELj5ELj5EEERS3_RAT__KcRAT0__S6_RAT1__S6_RAT2__S6_RKS2_: 120| 4.30k| const T& Value) { 121| 4.30k| if (!Result && ( ------------------ | Branch (121:9): [True: 4.30k, False: 0] ------------------ 122| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (122:10): [True: 0, False: 4.30k] | Branch (122:32): [True: 0, False: 0] ------------------ 123| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (123:10): [True: 0, False: 4.30k] | Branch (123:32): [True: 0, False: 0] ------------------ 124| 4.30k| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0) || ------------------ | Branch (124:10): [True: 0, False: 4.30k] | Branch (124:32): [True: 0, False: 0] ------------------ 125| 4.30k| (N3-1 == Str.size() && std::memcmp(S3, Str.data(), N3-1) == 0))) { ------------------ | Branch (125:10): [True: 0, False: 4.30k] | Branch (125:32): [True: 0, False: 0] ------------------ 126| 0| Result = &Value; 127| 0| } 128| | 129| 4.30k| return *this; 130| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj5ELj5ELj5EEERS3_RAT__KcRAT0__S6_RAT1__S6_RKS2_: 105| 4.30k| const char (&S2)[N2], const T& Value) { 106| 4.30k| if (!Result && ( ------------------ | Branch (106:9): [True: 4.30k, False: 0] ------------------ 107| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (107:10): [True: 0, False: 4.30k] | Branch (107:32): [True: 0, False: 0] ------------------ 108| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (108:10): [True: 0, False: 4.30k] | Branch (108:32): [True: 0, False: 0] ------------------ 109| 4.30k| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0))) { ------------------ | Branch (109:10): [True: 0, False: 4.30k] | Branch (109:32): [True: 0, False: 0] ------------------ 110| 0| Result = &Value; 111| 0| } 112| | 113| 4.30k| return *this; 114| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj6ELj7ELj8EEERS3_RAT__KcRAT0__S6_RAT1__S6_RKS2_: 105| 4.30k| const char (&S2)[N2], const T& Value) { 106| 4.30k| if (!Result && ( ------------------ | Branch (106:9): [True: 4.30k, False: 0] ------------------ 107| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (107:10): [True: 0, False: 4.30k] | Branch (107:32): [True: 0, False: 0] ------------------ 108| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (108:10): [True: 0, False: 4.30k] | Branch (108:32): [True: 0, False: 0] ------------------ 109| 4.30k| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0))) { ------------------ | Branch (109:10): [True: 0, False: 4.30k] | Branch (109:32): [True: 0, False: 0] ------------------ 110| 0| Result = &Value; 111| 0| } 112| | 113| 4.30k| return *this; 114| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj8ELj6EEERS3_RAT__KcRAT0__S6_RKS2_: 92| 4.30k| const T& Value) { 93| 4.30k| if (!Result && ( ------------------ | Branch (93:9): [True: 4.30k, False: 0] ------------------ 94| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 0, False: 4.30k] | Branch (94:32): [True: 0, False: 0] ------------------ 95| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 0, False: 4.30k] | Branch (95:32): [True: 0, False: 0] ------------------ 96| 0| Result = &Value; 97| 0| } 98| | 99| 4.30k| return *this; 100| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj10ELj4ELj6EEERS3_RAT__KcRAT0__S6_RAT1__S6_RKS2_: 105| 4.30k| const char (&S2)[N2], const T& Value) { 106| 4.30k| if (!Result && ( ------------------ | Branch (106:9): [True: 4.30k, False: 0] ------------------ 107| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (107:10): [True: 4.30k, False: 0] | Branch (107:32): [True: 0, False: 4.30k] ------------------ 108| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (108:10): [True: 0, False: 4.30k] | Branch (108:32): [True: 0, False: 0] ------------------ 109| 4.30k| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0))) { ------------------ | Branch (109:10): [True: 0, False: 4.30k] | Branch (109:32): [True: 0, False: 0] ------------------ 110| 0| Result = &Value; 111| 0| } 112| | 113| 4.30k| return *this; 114| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj12ELj8EEERS3_RAT__KcRAT0__S6_RKS2_: 92| 4.30k| const T& Value) { 93| 4.30k| if (!Result && ( ------------------ | Branch (93:9): [True: 4.30k, False: 0] ------------------ 94| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 0, False: 4.30k] | Branch (94:32): [True: 0, False: 0] ------------------ 95| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 0, False: 4.30k] | Branch (95:32): [True: 0, False: 0] ------------------ 96| 0| Result = &Value; 97| 0| } 98| | 99| 4.30k| return *this; 100| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj5ELj7ELj13EEERS3_RAT__KcRAT0__S6_RAT1__S6_RKS2_: 105| 4.30k| const char (&S2)[N2], const T& Value) { 106| 4.30k| if (!Result && ( ------------------ | Branch (106:9): [True: 4.30k, False: 0] ------------------ 107| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (107:10): [True: 0, False: 4.30k] | Branch (107:32): [True: 0, False: 0] ------------------ 108| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (108:10): [True: 0, False: 4.30k] | Branch (108:32): [True: 0, False: 0] ------------------ 109| 4.30k| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0))) { ------------------ | Branch (109:10): [True: 0, False: 4.30k] | Branch (109:32): [True: 0, False: 0] ------------------ 110| 0| Result = &Value; 111| 0| } 112| | 113| 4.30k| return *this; 114| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj7ELj15EEERS3_RAT__KcRAT0__S6_RKS2_: 92| 4.30k| const T& Value) { 93| 4.30k| if (!Result && ( ------------------ | Branch (93:9): [True: 4.30k, False: 0] ------------------ 94| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 0, False: 4.30k] | Branch (94:32): [True: 0, False: 0] ------------------ 95| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 0, False: 4.30k] | Branch (95:32): [True: 0, False: 0] ------------------ 96| 0| Result = &Value; 97| 0| } 98| | 99| 4.30k| return *this; 100| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj7ELj9EEERS3_RAT__KcRAT0__S6_RKS2_: 92| 4.30k| const T& Value) { 93| 4.30k| if (!Result && ( ------------------ | Branch (93:9): [True: 4.30k, False: 0] ------------------ 94| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 0, False: 4.30k] | Branch (94:32): [True: 0, False: 0] ------------------ 95| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 0, False: 4.30k] | Branch (95:32): [True: 0, False: 0] ------------------ 96| 0| Result = &Value; 97| 0| } 98| | 99| 4.30k| return *this; 100| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj6ELj8EEERS3_RAT__KcRAT0__S6_RKS2_: 92| 4.30k| const T& Value) { 93| 4.30k| if (!Result && ( ------------------ | Branch (93:9): [True: 4.30k, False: 0] ------------------ 94| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 0, False: 4.30k] | Branch (94:32): [True: 0, False: 0] ------------------ 95| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 0, False: 4.30k] | Branch (95:32): [True: 0, False: 0] ------------------ 96| 0| Result = &Value; 97| 0| } 98| | 99| 4.30k| return *this; 100| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E5CasesILj8ELj8EEERS3_RAT__KcRAT0__S6_RKS2_: 92| 4.30k| const T& Value) { 93| 4.30k| if (!Result && ( ------------------ | Branch (93:9): [True: 4.30k, False: 0] ------------------ 94| 4.30k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 0, False: 4.30k] | Branch (94:32): [True: 0, False: 0] ------------------ 95| 4.30k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 0, False: 4.30k] | Branch (95:32): [True: 0, False: 0] ------------------ 96| 0| Result = &Value; 97| 0| } 98| | 99| 4.30k| return *this; 100| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E10StartsWithILj8EEERS3_RAT__KcRKS2_: 80| 4.30k| StringSwitch& StartsWith(const char (&S)[N], const T &Value) { 81| 4.30k| if (!Result && Str.size() >= N-1 && ------------------ | Branch (81:9): [True: 4.30k, False: 0] | Branch (81:20): [True: 4.30k, False: 0] ------------------ 82| 4.30k| std::memcmp(S, Str.data(), N-1) == 0) { ------------------ | Branch (82:9): [True: 0, False: 4.30k] ------------------ 83| 0| Result = &Value; 84| 0| } 85| | 86| 4.30k| return *this; 87| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_EC2ENS_9StringRefE: 54| 4.30k| : Str(S), Result(nullptr) { } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E4CaseILj8EEERS3_RAT__KcRKS2_: 58| 38.7k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 38.7k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 38.7k, False: 0] | Branch (59:20): [True: 0, False: 38.7k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 38.7k| return *this; 65| 38.7k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E4CaseILj11EEERS3_RAT__KcRKS2_: 58| 4.30k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 4.30k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 4.30k, False: 0] | Branch (59:20): [True: 0, False: 4.30k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 4.30k| return *this; 65| 4.30k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E4CaseILj6EEERS3_RAT__KcRKS2_: 58| 38.7k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 38.7k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 38.7k, False: 0] | Branch (59:20): [True: 0, False: 38.7k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 38.7k| return *this; 65| 38.7k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E4CaseILj4EEERS3_RAT__KcRKS2_: 58| 12.9k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 12.9k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 12.9k, False: 0] | Branch (59:20): [True: 0, False: 12.9k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 12.9k| return *this; 65| 12.9k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E4CaseILj5EEERS3_RAT__KcRKS2_: 58| 17.2k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 17.2k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 17.2k, False: 0] | Branch (59:20): [True: 0, False: 17.2k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 17.2k| return *this; 65| 17.2k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E4CaseILj7EEERS3_RAT__KcRKS2_: 58| 25.8k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 25.8k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 25.8k, False: 0] | Branch (59:20): [True: 0, False: 25.8k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 25.8k| return *this; 65| 25.8k| } _ZN7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E4CaseILj9EEERS3_RAT__KcRKS2_: 58| 8.60k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 8.60k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 8.60k, False: 0] | Branch (59:20): [True: 0, False: 8.60k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 8.60k| return *this; 65| 8.60k| } _ZNK7llvm_ks12StringSwitchINS_6Triple8ArchTypeES2_E7DefaultERKS2_: 150| 4.30k| R Default(const T& Value) const { 151| 4.30k| if (Result) ------------------ | Branch (151:9): [True: 0, False: 4.30k] ------------------ 152| 0| return *Result; 153| | 154| 4.30k| return Value; 155| 4.30k| } _ZN7llvm_ks12StringSwitchIjjEC2ENS_9StringRefE: 54| 23.3k| : Str(S), Result(nullptr) { } _ZN7llvm_ks12StringSwitchIjjE4CaseILj3EEERS1_RAT__KcRKj: 58| 300k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 300k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 282k, False: 18.2k] | Branch (59:20): [True: 124k, False: 158k] ------------------ 60| 124k| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 1.72k, False: 122k] ------------------ 61| 1.72k| Result = &Value; 62| 1.72k| } 63| | 64| 300k| return *this; 65| 300k| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj4EEERS1_RAT__KcRKj: 58| 45.9k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 45.9k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 45.5k, False: 442] | Branch (59:20): [True: 5.42k, False: 40.1k] ------------------ 60| 5.42k| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 222, False: 5.20k] ------------------ 61| 222| Result = &Value; 62| 222| } 63| | 64| 45.9k| return *this; 65| 45.9k| } _ZNK7llvm_ks12StringSwitchIjjE7DefaultERKj: 150| 23.3k| R Default(const T& Value) const { 151| 23.3k| if (Result) ------------------ | Branch (151:9): [True: 6.43k, False: 16.9k] ------------------ 152| 6.43k| return *Result; 153| | 154| 16.9k| return Value; 155| 23.3k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E4CaseILj4EEERS2_RAT__KcRKS1_: 58| 63.9k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 63.9k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 57.3k, False: 6.58k] | Branch (59:20): [True: 3.02k, False: 54.2k] ------------------ 60| 3.02k| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 2.19k, False: 832] ------------------ 61| 2.19k| Result = &Value; 62| 2.19k| } 63| | 64| 63.9k| return *this; 65| 63.9k| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj7EEERS1_RAT__KcRKj: 58| 2.06k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 2.06k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 2.06k, False: 0] | Branch (59:20): [True: 19, False: 2.05k] ------------------ 60| 19| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 19] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 2.06k| return *this; 65| 2.06k| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj8EEERS1_RAT__KcRKj: 58| 1.04k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 1.04k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 1.04k, False: 0] | Branch (59:20): [True: 0, False: 1.04k] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 1.04k| return *this; 65| 1.04k| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj9EEERS1_RAT__KcRKj: 58| 539| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 539| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 539, False: 0] | Branch (59:20): [True: 0, False: 539] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 539| return *this; 65| 539| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj5EEERS1_RAT__KcRKj: 58| 412| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 412| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 412, False: 0] | Branch (59:20): [True: 0, False: 412] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 412| return *this; 65| 412| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj11EEERS1_RAT__KcRKj: 58| 505| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 505| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 505, False: 0] | Branch (59:20): [True: 0, False: 505] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 505| return *this; 65| 505| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj12EEERS1_RAT__KcRKj: 58| 505| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 505| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 505, False: 0] | Branch (59:20): [True: 0, False: 505] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 505| return *this; 65| 505| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj6EEERS1_RAT__KcRKj: 58| 428| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 428| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 428, False: 0] | Branch (59:20): [True: 24, False: 404] ------------------ 60| 24| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 24] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 428| return *this; 65| 428| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj13EEERS1_RAT__KcRKj: 58| 303| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 303| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 303, False: 0] | Branch (59:20): [True: 0, False: 303] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 303| return *this; 65| 303| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj10EEERS1_RAT__KcRKj: 58| 303| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 303| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 303, False: 0] | Branch (59:20): [True: 0, False: 303] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 303| return *this; 65| 303| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj15EEERS1_RAT__KcRKj: 58| 101| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 101| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 101, False: 0] | Branch (59:20): [True: 0, False: 101] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 101| return *this; 65| 101| } _ZN7llvm_ks12StringSwitchIjjE4CaseILj2EEERS1_RAT__KcRKj: 58| 1.07k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 1.07k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 825, False: 253] | Branch (59:20): [True: 825, False: 0] ------------------ 60| 825| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 188, False: 637] ------------------ 61| 188| Result = &Value; 62| 188| } 63| | 64| 1.07k| return *this; 65| 1.07k| } _ZN7llvm_ks12StringSwitchINS_6ARM_AM8ShiftOpcES2_EC2ENS_9StringRefE: 54| 11.4k| : Str(S), Result(nullptr) { } _ZN7llvm_ks12StringSwitchINS_6ARM_AM8ShiftOpcES2_E4CaseILj4EEERS3_RAT__KcRKS2_: 58| 68.7k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 68.7k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 68.7k, False: 0] | Branch (59:20): [True: 7.87k, False: 60.8k] ------------------ 60| 7.87k| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 7.87k] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 68.7k| return *this; 65| 68.7k| } _ZNK7llvm_ks12StringSwitchINS_6ARM_AM8ShiftOpcES2_E7DefaultERKS2_: 150| 11.4k| R Default(const T& Value) const { 151| 11.4k| if (Result) ------------------ | Branch (151:9): [True: 0, False: 11.4k] ------------------ 152| 0| return *Result; 153| | 154| 11.4k| return Value; 155| 11.4k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E4CaseILj3EEERS2_RAT__KcRKS1_: 58| 15.9k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 15.9k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 15.9k, False: 0] | Branch (59:20): [True: 13.4k, False: 2.55k] ------------------ 60| 13.4k| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 13.4k] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 15.9k| return *this; 65| 15.9k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E4CaseILj6EEERS2_RAT__KcRKS1_: 58| 31.9k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 31.9k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 900, False: 31.0k] | Branch (59:20): [True: 0, False: 900] ------------------ 60| 0| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 0] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 31.9k| return *this; 65| 31.9k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E4CaseILj9EEERS2_RAT__KcRKS1_: 58| 32.3k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 32.3k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 1.32k, False: 31.0k] | Branch (59:20): [True: 26, False: 1.30k] ------------------ 60| 26| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 0, False: 26] ------------------ 61| 0| Result = &Value; 62| 0| } 63| | 64| 32.3k| return *this; 65| 32.3k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E5CasesILj4ELj5ELj5ELj9EEERS2_RAT__KcRAT0__S5_RAT1__S5_RAT2__S5_RKS1_: 120| 213| const T& Value) { 121| 213| if (!Result && ( ------------------ | Branch (121:9): [True: 213, False: 0] ------------------ 122| 213| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (122:10): [True: 33, False: 180] | Branch (122:32): [True: 0, False: 33] ------------------ 123| 213| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (123:10): [True: 35, False: 178] | Branch (123:32): [True: 0, False: 35] ------------------ 124| 213| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0) || ------------------ | Branch (124:10): [True: 35, False: 178] | Branch (124:32): [True: 0, False: 35] ------------------ 125| 213| (N3-1 == Str.size() && std::memcmp(S3, Str.data(), N3-1) == 0))) { ------------------ | Branch (125:10): [True: 11, False: 202] | Branch (125:32): [True: 0, False: 11] ------------------ 126| 0| Result = &Value; 127| 0| } 128| | 129| 213| return *this; 130| 213| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E4CaseILj5EEERS2_RAT__KcRKS1_: 58| 32.5k| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 32.5k| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 28.2k, False: 4.38k] | Branch (59:20): [True: 129, False: 28.0k] ------------------ 60| 129| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 1, False: 128] ------------------ 61| 1| Result = &Value; 62| 1| } 63| | 64| 32.5k| return *this; 65| 32.5k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E5CasesILj11ELj13EEERS2_RAT__KcRAT0__S5_RKS1_: 92| 213| const T& Value) { 93| 213| if (!Result && ( ------------------ | Branch (93:9): [True: 213, False: 0] ------------------ 94| 213| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 11, False: 202] | Branch (94:32): [True: 5, False: 6] ------------------ 95| 208| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 12, False: 196] | Branch (95:32): [True: 0, False: 12] ------------------ 96| 5| Result = &Value; 97| 5| } 98| | 99| 213| return *this; 100| 213| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E5CasesILj11ELj12EEERS2_RAT__KcRAT0__S5_RKS1_: 92| 426| const T& Value) { 93| 426| if (!Result && ( ------------------ | Branch (93:9): [True: 410, False: 16] ------------------ 94| 410| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 6, False: 404] | Branch (94:32): [True: 0, False: 6] ------------------ 95| 410| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 0, False: 410] | Branch (95:32): [True: 0, False: 0] ------------------ 96| 0| Result = &Value; 97| 0| } 98| | 99| 426| return *this; 100| 426| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E4CaseILj11EEERS2_RAT__KcRKS1_: 58| 426| StringSwitch& Case(const char (&S)[N], const T& Value) { 59| 426| if (!Result && N-1 == Str.size() && ------------------ | Branch (59:9): [True: 410, False: 16] | Branch (59:20): [True: 6, False: 404] ------------------ 60| 6| (std::memcmp(S, Str.data(), N-1) == 0)) { ------------------ | Branch (60:9): [True: 6, False: 0] ------------------ 61| 6| Result = &Value; 62| 6| } 63| | 64| 426| return *this; 65| 426| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E5CasesILj4ELj5ELj6EEERS2_RAT__KcRAT0__S5_RAT1__S5_RKS1_: 105| 15.9k| const char (&S2)[N2], const T& Value) { 106| 15.9k| if (!Result && ( ------------------ | Branch (106:9): [True: 13.7k, False: 2.19k] ------------------ 107| 13.7k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (107:10): [True: 209, False: 13.5k] | Branch (107:32): [True: 0, False: 209] ------------------ 108| 13.7k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (108:10): [True: 12, False: 13.7k] | Branch (108:32): [True: 0, False: 12] ------------------ 109| 13.7k| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0))) { ------------------ | Branch (109:10): [True: 0, False: 13.7k] | Branch (109:32): [True: 0, False: 0] ------------------ 110| 0| Result = &Value; 111| 0| } 112| | 113| 15.9k| return *this; 114| 15.9k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E5CasesILj4ELj5EEERS2_RAT__KcRAT0__S5_RKS1_: 92| 15.9k| const T& Value) { 93| 15.9k| if (!Result && ( ------------------ | Branch (93:9): [True: 13.7k, False: 2.19k] ------------------ 94| 13.7k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (94:10): [True: 209, False: 13.5k] | Branch (94:32): [True: 0, False: 209] ------------------ 95| 13.7k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0))) { ------------------ | Branch (95:10): [True: 12, False: 13.7k] | Branch (95:32): [True: 0, False: 12] ------------------ 96| 0| Result = &Value; 97| 0| } 98| | 99| 15.9k| return *this; 100| 15.9k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E5CasesILj3ELj4ELj5ELj4EEERS2_RAT__KcRAT0__S5_RAT1__S5_RAT2__S5_RKS1_: 120| 15.9k| const T& Value) { 121| 15.9k| if (!Result && ( ------------------ | Branch (121:9): [True: 13.7k, False: 2.19k] ------------------ 122| 13.7k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (122:10): [True: 13.4k, False: 360] | Branch (122:32): [True: 0, False: 13.4k] ------------------ 123| 13.7k| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (123:10): [True: 209, False: 13.5k] | Branch (123:32): [True: 0, False: 209] ------------------ 124| 13.7k| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0) || ------------------ | Branch (124:10): [True: 12, False: 13.7k] | Branch (124:32): [True: 0, False: 12] ------------------ 125| 13.7k| (N3-1 == Str.size() && std::memcmp(S3, Str.data(), N3-1) == 0))) { ------------------ | Branch (125:10): [True: 209, False: 13.5k] | Branch (125:32): [True: 0, False: 209] ------------------ 126| 0| Result = &Value; 127| 0| } 128| | 129| 15.9k| return *this; 130| 15.9k| } _ZN7llvm_ks12StringSwitchINS_9StringRefES1_E5CasesILj3ELj4ELj8ELj6EEERS2_RAT__KcRAT0__S5_RAT1__S5_RAT2__S5_RKS1_: 120| 15.9k| const T& Value) { 121| 15.9k| if (!Result && ( ------------------ | Branch (121:9): [True: 13.7k, False: 2.19k] ------------------ 122| 13.7k| (N0-1 == Str.size() && std::memcmp(S0, Str.data(), N0-1) == 0) || ------------------ | Branch (122:10): [True: 13.4k, False: 357] | Branch (122:32): [True: 13.3k, False: 93] ------------------ 123| 450| (N1-1 == Str.size() && std::memcmp(S1, Str.data(), N1-1) == 0) || ------------------ | Branch (123:10): [True: 207, False: 243] | Branch (123:32): [True: 0, False: 207] ------------------ 124| 450| (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0) || ------------------ | Branch (124:10): [True: 1, False: 449] | Branch (124:32): [True: 0, False: 1] ------------------ 125| 13.3k| (N3-1 == Str.size() && std::memcmp(S3, Str.data(), N3-1) == 0))) { ------------------ | Branch (125:10): [True: 0, False: 450] | Branch (125:32): [True: 0, False: 0] ------------------ 126| 13.3k| Result = &Value; 127| 13.3k| } 128| | 129| 15.9k| return *this; 130| 15.9k| } _ZN7llvm_ks12StringSwitchIjjE10StartsWithILj8EEERS1_RAT__KcRKj: 80| 4.30k| StringSwitch& StartsWith(const char (&S)[N], const T &Value) { 81| 4.30k| if (!Result && Str.size() >= N-1 && ------------------ | Branch (81:9): [True: 4.30k, False: 0] | Branch (81:20): [True: 4.30k, False: 0] ------------------ 82| 4.30k| std::memcmp(S, Str.data(), N-1) == 0) { ------------------ | Branch (82:9): [True: 0, False: 4.30k] ------------------ 83| 0| Result = &Value; 84| 0| } 85| | 86| 4.30k| return *this; 87| 4.30k| } _ZN7llvm_ks12StringSwitchIjjE10StartsWithILj6EEERS1_RAT__KcRKj: 80| 8.60k| StringSwitch& StartsWith(const char (&S)[N], const T &Value) { 81| 8.60k| if (!Result && Str.size() >= N-1 && ------------------ | Branch (81:9): [True: 8.60k, False: 0] | Branch (81:20): [True: 8.60k, False: 0] ------------------ 82| 8.60k| std::memcmp(S, Str.data(), N-1) == 0) { ------------------ | Branch (82:9): [True: 4.30k, False: 4.30k] ------------------ 83| 4.30k| Result = &Value; 84| 4.30k| } 85| | 86| 8.60k| return *this; 87| 8.60k| } _ZN7llvm_ks12StringSwitchIjjE10StartsWithILj4EEERS1_RAT__KcRKj: 80| 4.30k| StringSwitch& StartsWith(const char (&S)[N], const T &Value) { 81| 4.30k| if (!Result && Str.size() >= N-1 && ------------------ | Branch (81:9): [True: 0, False: 4.30k] | Branch (81:20): [True: 0, False: 0] ------------------ 82| 0| std::memcmp(S, Str.data(), N-1) == 0) { ------------------ | Branch (82:9): [True: 0, False: 0] ------------------ 83| 0| Result = &Value; 84| 0| } 85| | 86| 4.30k| return *this; 87| 4.30k| } _ZN7llvm_ks6TripleC2Ev: 223| 2.73k| Triple() : Data(), Arch(), Vendor(), OS(), Environment(), ObjectFormat() {} _ZNK7llvm_ks6Triple15getObjectFormatEv: 285| 2.15k| ObjectFormatType getObjectFormat() const { return ObjectFormat; } _ZNK7llvm_ks6Triple7getArchEv: 255| 8.18k| ArchType getArch() const { return Arch; } _ZNK7llvm_ks6Triple5getOSEv: 264| 5.16k| OSType getOS() const { return OS; } _ZNK7llvm_ks6Triple9getTripleEv: 326| 430| const std::string &getTriple() const { return Data; } _ZNK7llvm_ks6Triple8isMacOSXEv: 412| 430| bool isMacOSX() const { 413| 430| return getOS() == Triple::Darwin || getOS() == Triple::MacOSX; ------------------ | Branch (413:12): [True: 0, False: 430] | Branch (413:41): [True: 0, False: 430] ------------------ 414| 430| } _ZNK7llvm_ks6Triple5isiOSEv: 421| 430| bool isiOS() const { 422| 430| return getOS() == Triple::IOS || isTvOS(); ------------------ | Branch (422:12): [True: 0, False: 430] | Branch (422:38): [True: 0, False: 430] ------------------ 423| 430| } _ZNK7llvm_ks6Triple6isTvOSEv: 426| 430| bool isTvOS() const { 427| 430| return getOS() == Triple::TvOS; 428| 430| } _ZNK7llvm_ks6Triple9isWatchOSEv: 431| 430| bool isWatchOS() const { 432| 430| return getOS() == Triple::WatchOS; 433| 430| } _ZNK7llvm_ks6Triple10isOSDarwinEv: 440| 430| bool isOSDarwin() const { 441| 430| return isMacOSX() || isiOS() || isWatchOS(); ------------------ | Branch (441:12): [True: 0, False: 430] | Branch (441:26): [True: 0, False: 430] | Branch (441:37): [True: 0, False: 430] ------------------ 442| 430| } _ZNK7llvm_ks6Triple11isOSSolarisEv: 458| 430| bool isOSSolaris() const { 459| 430| return getOS() == Triple::Solaris; 460| 430| } _ZNK7llvm_ks6Triple24isWindowsMSVCEnvironmentEv: 471| 430| bool isWindowsMSVCEnvironment() const { 472| 430| return getOS() == Triple::Win32 && ------------------ | Branch (472:12): [True: 0, False: 430] ------------------ 473| 0| (getEnvironment() == Triple::UnknownEnvironment || ------------------ | Branch (473:13): [True: 0, False: 0] ------------------ 474| 0| getEnvironment() == Triple::MSVC); ------------------ | Branch (474:13): [True: 0, False: 0] ------------------ 475| 430| } _ZNK7llvm_ks6Triple11isOSWindowsEv: 510| 430| bool isOSWindows() const { 511| 430| return getOS() == Triple::Win32; 512| 430| } _ZNK7llvm_ks6Triple8isOSNaClEv: 515| 860| bool isOSNaCl() const { 516| 860| return getOS() == Triple::NaCl; 517| 860| } _ZNK7llvm_ks6Triple16isOSBinFormatELFEv: 525| 430| bool isOSBinFormatELF() const { 526| 430| return getObjectFormat() == Triple::ELF; 527| 430| } _ZNK7llvm_ks6Triple18isOSBinFormatMachOEv: 535| 430| bool isOSBinFormatMachO() const { 536| 430| return getObjectFormat() == Triple::MachO; 537| 430| } _ZN7llvm_ks5TwineC2ERKNS_9StringRefE: 286| 18.1k| : LHSKind(StringRefKind), RHSKind(EmptyKind) { 287| 18.1k| LHS.stringRef = &Str; 288| | assert(isValid() && "Invalid twine!"); ------------------ | Branch (288:7): [True: 18.1k, False: 0] | Branch (288:7): [True: 18.1k, Folded] | Branch (288:7): [True: 18.1k, False: 0] ------------------ 289| 18.1k| } _ZNK7llvm_ks5Twine7isValidEv: 213| 38.5k| bool isValid() const { 214| | // Nullary twines always have Empty on the RHS. 215| 38.5k| if (isNullary() && getRHSKind() != EmptyKind) ------------------ | Branch (215:11): [True: 0, False: 38.5k] | Branch (215:26): [True: 0, False: 0] ------------------ 216| 0| return false; 217| | 218| | // Null should never appear on the RHS. 219| 38.5k| if (getRHSKind() == NullKind) ------------------ | Branch (219:11): [True: 0, False: 38.5k] ------------------ 220| 0| return false; 221| | 222| | // The RHS cannot be non-empty if the LHS is empty. 223| 38.5k| if (getRHSKind() != EmptyKind && getLHSKind() == EmptyKind) ------------------ | Branch (223:11): [True: 3.17k, False: 35.3k] | Branch (223:40): [True: 0, False: 3.17k] ------------------ 224| 0| return false; 225| | 226| | // A twine child should always be binary. 227| 38.5k| if (getLHSKind() == TwineKind && ------------------ | Branch (227:11): [True: 2, False: 38.5k] ------------------ 228| 2| !LHS.twine->isBinary()) ------------------ | Branch (228:11): [True: 0, False: 2] ------------------ 229| 0| return false; 230| 38.5k| if (getRHSKind() == TwineKind && ------------------ | Branch (230:11): [True: 0, False: 38.5k] ------------------ 231| 0| !RHS.twine->isBinary()) ------------------ | Branch (231:11): [True: 0, False: 0] ------------------ 232| 0| return false; 233| | 234| 38.5k| return true; 235| 38.5k| } _ZNK7llvm_ks5Twine9isNullaryEv: 197| 41.1k| bool isNullary() const { 198| 41.1k| return isNull() || isEmpty(); ------------------ | Branch (198:14): [True: 0, False: 41.1k] | Branch (198:26): [True: 0, False: 41.1k] ------------------ 199| 41.1k| } _ZNK7llvm_ks5Twine6isNullEv: 187| 42.8k| bool isNull() const { 188| 42.8k| return getLHSKind() == NullKind; 189| 42.8k| } _ZNK7llvm_ks5Twine7isEmptyEv: 192| 42.8k| bool isEmpty() const { 193| 42.8k| return getLHSKind() == EmptyKind; 194| 42.8k| } _ZNK7llvm_ks5Twine10getRHSKindEv: 241| 176k| NodeKind getRHSKind() const { return RHSKind; } _ZNK7llvm_ks5Twine10getLHSKindEv: 238| 205k| NodeKind getLHSKind() const { return LHSKind; } _ZNK7llvm_ks5Twine8isBinaryEv: 207| 2| bool isBinary() const { 208| 2| return getLHSKind() != NullKind && getRHSKind() != EmptyKind; ------------------ | Branch (208:14): [True: 2, False: 0] | Branch (208:42): [True: 2, False: 0] ------------------ 209| 2| } _ZN7llvm_ks5TwineC2ERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE: 279| 3.01k| : LHSKind(StdStringKind), RHSKind(EmptyKind) { 280| 3.01k| LHS.stdString = &Str; 281| | assert(isValid() && "Invalid twine!"); ------------------ | Branch (281:7): [True: 3.01k, False: 0] | Branch (281:7): [True: 3.01k, Folded] | Branch (281:7): [True: 3.01k, False: 0] ------------------ 282| 3.01k| } _ZN7llvm_ks5TwineC2ENS0_5ChildENS0_8NodeKindES1_S2_: 178| 864| : LHS(LHS), RHS(RHS), LHSKind(LHSKind), RHSKind(RHSKind) { 179| | assert(isValid() && "Invalid twine!"); ------------------ | Branch (179:7): [True: 864, False: 0] | Branch (179:7): [True: 864, Folded] | Branch (179:7): [True: 864, False: 0] ------------------ 180| 864| } _ZNK7llvm_ks5Twine7isUnaryEv: 202| 2.58k| bool isUnary() const { 203| 2.58k| return getRHSKind() == EmptyKind && !isNullary(); ------------------ | Branch (203:14): [True: 2.58k, False: 2] | Branch (203:43): [True: 2.58k, False: 0] ------------------ 204| 2.58k| } _ZN7llvm_ks5TwineC2EPKc: 267| 14.1k| : RHSKind(EmptyKind) { 268| 14.1k| if (Str[0] != '\0') { ------------------ | Branch (268:11): [True: 14.1k, False: 0] ------------------ 269| 14.1k| LHS.cString = Str; 270| 14.1k| LHSKind = CStringKind; 271| 14.1k| } else 272| 0| LHSKind = EmptyKind; 273| | 274| | assert(isValid() && "Invalid twine!"); ------------------ | Branch (274:7): [True: 14.1k, False: 0] | Branch (274:7): [True: 14.1k, Folded] | Branch (274:7): [True: 14.1k, False: 0] ------------------ 275| 14.1k| } _ZN7llvm_ks5TwineC2EPKcRKNS_9StringRefE: 359| 2.30k| : LHSKind(CStringKind), RHSKind(StringRefKind) { 360| 2.30k| this->LHS.cString = LHS; 361| 2.30k| this->RHS.stringRef = &RHS; 362| | assert(isValid() && "Invalid twine!"); ------------------ | Branch (362:7): [True: 2.30k, False: 0] | Branch (362:7): [True: 2.30k, Folded] | Branch (362:7): [True: 2.30k, False: 0] ------------------ 363| 2.30k| } _ZNK7llvm_ks5Twine17isSingleStringRefEv: 403| 44.8k| bool isSingleStringRef() const { 404| 44.8k| if (getRHSKind() != EmptyKind) return false; ------------------ | Branch (404:11): [True: 3.17k, False: 41.7k] ------------------ 405| | 406| 41.7k| switch (getLHSKind()) { 407| 0| case EmptyKind: ------------------ | Branch (407:7): [True: 0, False: 41.7k] ------------------ 408| 7.06k| case CStringKind: ------------------ | Branch (408:7): [True: 7.06k, False: 34.6k] ------------------ 409| 7.06k| case StdStringKind: ------------------ | Branch (409:7): [True: 0, False: 41.7k] ------------------ 410| 41.7k| case StringRefKind: ------------------ | Branch (410:7): [True: 34.6k, False: 7.06k] ------------------ 411| 41.7k| case SmallStringKind: ------------------ | Branch (411:7): [True: 0, False: 41.7k] ------------------ 412| 41.7k| return true; 413| 0| default: ------------------ | Branch (413:7): [True: 0, False: 41.7k] ------------------ 414| 0| return false; 415| 41.7k| } 416| 41.7k| } _ZNK7llvm_ks5Twine18getSingleStringRefEv: 436| 20.8k| StringRef getSingleStringRef() const { 437| 20.8k| assert(isSingleStringRef() &&"This cannot be had as a single stringref!"); ------------------ | Branch (437:7): [True: 20.8k, False: 0] | Branch (437:7): [True: 20.8k, Folded] | Branch (437:7): [True: 20.8k, False: 0] ------------------ 438| 20.8k| switch (getLHSKind()) { 439| 0| default: llvm_unreachable("Out of sync with isSingleStringRef"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ | Branch (439:7): [True: 0, False: 20.8k] ------------------ 440| 0| case EmptyKind: return StringRef(); ------------------ | Branch (440:7): [True: 0, False: 20.8k] ------------------ 441| 3.53k| case CStringKind: return StringRef(LHS.cString); ------------------ | Branch (441:7): [True: 3.53k, False: 17.3k] ------------------ 442| 0| case StdStringKind: return StringRef(*LHS.stdString); ------------------ | Branch (442:7): [True: 0, False: 20.8k] ------------------ 443| 17.3k| case StringRefKind: return *LHS.stringRef; ------------------ | Branch (443:7): [True: 17.3k, False: 3.53k] ------------------ 444| 0| case SmallStringKind: ------------------ | Branch (444:7): [True: 0, False: 20.8k] ------------------ 445| 0| return StringRef(LHS.smallString->data(), LHS.smallString->size()); 446| 20.8k| } 447| 20.8k| } _ZNK7llvm_ks5Twine11toStringRefERNS_15SmallVectorImplIcEE: 452| 24.0k| StringRef toStringRef(SmallVectorImpl &Out) const { 453| 24.0k| if (isSingleStringRef()) ------------------ | Branch (453:11): [True: 20.8k, False: 3.17k] ------------------ 454| 20.8k| return getSingleStringRef(); 455| 3.17k| toVector(Out); 456| 3.17k| return StringRef(Out.data(), Out.size()); 457| 24.0k| } _ZNK7llvm_ks5Twine6concatERKS0_: 485| 864| inline Twine Twine::concat(const Twine &Suffix) const { 486| | // Concatenation with null is null. 487| 864| if (isNull() || Suffix.isNull()) ------------------ | Branch (487:9): [True: 0, False: 864] | Branch (487:21): [True: 0, False: 864] ------------------ 488| 0| return Twine(NullKind); 489| | 490| | // Concatenation with empty yields the other side. 491| 864| if (isEmpty()) ------------------ | Branch (491:9): [True: 0, False: 864] ------------------ 492| 0| return Suffix; 493| 864| if (Suffix.isEmpty()) ------------------ | Branch (493:9): [True: 0, False: 864] ------------------ 494| 0| return *this; 495| | 496| | // Otherwise we need to create a new node, taking care to fold in unary 497| | // twines. 498| 864| Child NewLHS, NewRHS; 499| 864| NewLHS.twine = this; 500| 864| NewRHS.twine = &Suffix; 501| 864| NodeKind NewLHSKind = TwineKind, NewRHSKind = TwineKind; 502| 864| if (isUnary()) { ------------------ | Branch (502:9): [True: 862, False: 2] ------------------ 503| 862| NewLHS = LHS; 504| 862| NewLHSKind = getLHSKind(); 505| 862| } 506| 864| if (Suffix.isUnary()) { ------------------ | Branch (506:9): [True: 864, False: 0] ------------------ 507| 864| NewRHS = Suffix.LHS; 508| 864| NewRHSKind = Suffix.getLHSKind(); 509| 864| } 510| | 511| 864| return Twine(NewLHS, NewLHSKind, NewRHS, NewRHSKind); 512| 864| } _ZN7llvm_ksplERKNS_5TwineES2_: 514| 864| inline Twine operator+(const Twine &LHS, const Twine &RHS) { 515| 864| return LHS.concat(RHS); 516| 864| } _ZN7llvm_ksplEPKcRKNS_9StringRefE: 521| 2.30k| inline Twine operator+(const char *LHS, const StringRef &RHS) { 522| 2.30k| return Twine(LHS, RHS); 523| 2.30k| } _ZN7llvm_kslsERNS_11raw_ostreamERKNS_5TwineE: 532| 9.76k| inline raw_ostream &operator<<(raw_ostream &OS, const Twine &RHS) { 533| 9.76k| RHS.print(OS); 534| 9.76k| return OS; 535| 9.76k| } _ZNK7llvm_ks14ilist_iteratorINS_10MCFragmentEE19getNodePtrUncheckedEv: 283| 53.8k| pointer getNodePtrUnchecked() const { return NodePtr; } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE6insertENS_14ilist_iteratorIS1_EEPS1_: 461| 2.82k| iterator insert(iterator where, NodeTy *New) { 462| 2.82k| NodeTy *CurNode = where.getNodePtrUnchecked(); 463| 2.82k| NodeTy *PrevNode = this->getPrev(CurNode); 464| 2.82k| this->setNext(New, CurNode); 465| 2.82k| this->setPrev(New, PrevNode); 466| | 467| 2.82k| if (CurNode != Head) // Is PrevNode off the beginning of the list? ------------------ | Branch (467:9): [True: 2.60k, False: 222] ------------------ 468| 2.60k| this->setNext(PrevNode, New); 469| 222| else 470| 222| Head = New; 471| 2.82k| this->setPrev(CurNode, New); 472| | 473| 2.82k| this->addNodeToList(New); // Notify traits that we added a node... 474| 2.82k| return iterator(New); 475| 2.82k| } _ZN7llvm_ks21ilist_nextprev_traitsINS_10MCFragmentEE7getPrevEPS1_: 57| 71.9k| static NodeTy *getPrev(NodeTy *N) { return N->getPrev(); } _ZN7llvm_ks21ilist_nextprev_traitsINS_10MCFragmentEE7setNextEPS1_S3_: 63| 8.69k| static void setNext(NodeTy *N, NodeTy *Next) { N->setNext(Next); } _ZN7llvm_ks21ilist_nextprev_traitsINS_10MCFragmentEE7setPrevEPS1_S3_: 62| 11.7k| static void setPrev(NodeTy *N, NodeTy *Prev) { N->setPrev(Prev); } _ZN7llvm_ks14ilist_iteratorINS_10MCFragmentEEC2EPS1_: 223| 52.3k| explicit ilist_iterator(pointer NP) : NodePtr(NP) {} _ZNK7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE11getPrevNodeERS1_: 692| 2.50k| NodeTy *getPrevNode(NodeTy &N) const { 693| 2.50k| auto I = N.getIterator(); 694| 2.50k| if (I == begin()) ------------------ | Branch (694:9): [True: 189, False: 2.31k] ------------------ 695| 189| return nullptr; 696| 2.31k| return &*std::prev(I); 697| 2.50k| } _ZNK7llvm_ks14ilist_iteratorINS_10MCFragmentEEeqIKS1_EEbRKNS0_IT_EE: 254| 2.50k| template bool operator==(const ilist_iterator &RHS) const { 255| 2.50k| return NodePtr == RHS.getNodePtrUnchecked(); 256| 2.50k| } _ZNK7llvm_ks14ilist_iteratorIKNS_10MCFragmentEE19getNodePtrUncheckedEv: 283| 4.38k| pointer getNodePtrUnchecked() const { return NodePtr; } _ZNK7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE5beginEv: 412| 2.50k| const_iterator begin() const { 413| 2.50k| CreateLazySentinel(); 414| 2.50k| return const_iterator(Head); 415| 2.50k| } _ZNK7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE18CreateLazySentinelEv: 375| 45.3k| void CreateLazySentinel() const { 376| 45.3k| this->ensureHead(Head); 377| 45.3k| } _ZN7llvm_ks21ilist_sentinel_traitsINS_10MCFragmentEE10ensureHeadERPS1_: 91| 53.0k| static NodeTy *ensureHead(NodeTy *&Head) { 92| 53.0k| if (!Head) { ------------------ | Branch (92:9): [True: 434, False: 52.6k] ------------------ 93| 434| Head = ilist_traits::createSentinel(); 94| 434| ilist_traits::noteHead(Head, Head); 95| 434| ilist_traits::setNext(Head, nullptr); 96| 434| return Head; 97| 434| } 98| 52.6k| return ilist_traits::getPrev(Head); 99| 53.0k| } _ZN7llvm_ks21ilist_sentinel_traitsINS_10MCFragmentEE14createSentinelEv: 78| 434| static NodeTy *createSentinel() { return new NodeTy(); } _ZN7llvm_ks21ilist_sentinel_traitsINS_10MCFragmentEE8noteHeadEPS1_S3_: 102| 434| static void noteHead(NodeTy *NewHead, NodeTy *Sentinel) { 103| 434| ilist_traits::setPrev(NewHead, Sentinel); 104| 434| } _ZN7llvm_ks14ilist_iteratorIKNS_10MCFragmentEEC2EPS2_: 223| 2.50k| explicit ilist_iterator(pointer NP) : NodePtr(NP) {} _ZN7llvm_ks14ilist_iteratorINS_10MCFragmentEEmmEv: 262| 13.6k| ilist_iterator &operator--() { // predecrement - Back up 263| 13.6k| NodePtr = Traits::getPrev(NodePtr); 264| 13.6k| assert(NodePtr && "--'d off the beginning of an ilist!"); ------------------ | Branch (264:5): [True: 13.6k, False: 0] | Branch (264:5): [True: 13.6k, Folded] | Branch (264:5): [True: 13.6k, False: 0] ------------------ 265| 13.6k| return *this; 266| 13.6k| } _ZN7llvm_ks14ilist_iteratorINS_10MCFragmentEEC2Ev: 225| 4.82k| ilist_iterator() : NodePtr(nullptr) {} _ZN7llvm_ks14ilist_iteratorINS_10MCFragmentEEppEv: 267| 13.8k| ilist_iterator &operator++() { // preincrement - Advance 268| 13.8k| NodePtr = Traits::getNext(NodePtr); 269| 13.8k| return *this; 270| 13.8k| } _ZN7llvm_ks21ilist_nextprev_traitsINS_10MCFragmentEE7getNextEPS1_: 58| 16.6k| static NodeTy *getNext(NodeTy *N) { return N->getNext(); } _ZNK7llvm_ks14ilist_iteratorINS_10MCFragmentEEeqIS1_EEbRKNS0_IT_EE: 254| 2.50k| template bool operator==(const ilist_iterator &RHS) const { 255| 2.50k| return NodePtr == RHS.getNodePtrUnchecked(); 256| 2.50k| } _ZNK7llvm_ks14ilist_iteratorINS_10MCFragmentEEdeEv: 248| 27.6k| reference operator*() const { 249| 27.6k| return *NodePtr; 250| 27.6k| } _ZNK7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE5emptyEv: 434| 187| bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const { 435| 187| return !Head || Head == getTail(); ------------------ | Branch (435:12): [True: 0, False: 187] | Branch (435:21): [True: 0, False: 187] ------------------ 436| 187| } _ZNK7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE7getTailEv: 370| 187| const NodeTy *getTail() const { return this->ensureHead(Head); } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE3endEv: 416| 7.13k| iterator end() { 417| 7.13k| CreateLazySentinel(); 418| 7.13k| return iterator(getTail()); 419| 7.13k| } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE7getTailEv: 369| 7.56k| NodeTy *getTail() { return this->ensureHead(Head); } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE5beginEv: 408| 35.6k| iterator begin() { 409| 35.6k| CreateLazySentinel(); 410| 35.6k| return iterator(Head); 411| 35.6k| } _ZNK7llvm_ks14ilist_iteratorINS_10MCFragmentEEneIS1_EEbRKNS0_IT_EE: 257| 48.1k| template bool operator!=(const ilist_iterator &RHS) const { 258| 48.1k| return NodePtr != RHS.getNodePtrUnchecked(); 259| 48.1k| } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEEC2Ev: 400| 18.6k| iplist() : Head(this->provideInitialHead()) {} _ZN7llvm_ks21ilist_sentinel_traitsINS_10MCFragmentEE18provideInitialHeadEv: 86| 18.6k| static NodeTy *provideInitialHead() { return nullptr; } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEED2Ev: 401| 18.6k| ~iplist() { 402| 18.6k| if (!Head) return; ------------------ | Branch (402:9): [True: 18.2k, False: 434] ------------------ 403| 434| clear(); 404| 434| Traits::destroySentinel(getTail()); 405| 434| } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE5clearEv: 605| 434| void clear() { if (Head) erase(begin(), end()); } ------------------ | Branch (605:22): [True: 434, False: 0] ------------------ _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE5eraseENS_14ilist_iteratorIS1_EES6_: 599| 434| iterator erase(iterator first, iterator last) { 600| 3.26k| while (first != last) ------------------ | Branch (600:12): [True: 2.82k, False: 434] ------------------ 601| 2.82k| first = erase(first); 602| 434| return last; 603| 434| } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE5eraseENS_14ilist_iteratorIS1_EE: 517| 2.82k| iterator erase(iterator where) { 518| 2.82k| this->deleteNode(remove(where)); 519| 2.82k| return where; 520| 2.82k| } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE6removeERNS_14ilist_iteratorIS1_EE: 484| 2.82k| NodeTy *remove(iterator &IT) { 485| 2.82k| assert(IT != end() && "Cannot remove end of list!"); ------------------ | Branch (485:5): [True: 2.82k, False: 0] | Branch (485:5): [True: 2.82k, Folded] | Branch (485:5): [True: 2.82k, False: 0] ------------------ 486| 2.82k| NodeTy *Node = &*IT; 487| 2.82k| NodeTy *NextNode = this->getNext(Node); 488| 2.82k| NodeTy *PrevNode = this->getPrev(Node); 489| | 490| 2.82k| if (Node != Head) // Is PrevNode off the beginning of the list? ------------------ | Branch (490:9): [True: 0, False: 2.82k] ------------------ 491| 0| this->setNext(PrevNode, NextNode); 492| 2.82k| else 493| 2.82k| Head = NextNode; 494| 2.82k| this->setPrev(NextNode, PrevNode); 495| 2.82k| IT.reset(NextNode); 496| 2.82k| this->removeNodeFromList(Node); // Notify traits that we removed a node... 497| | 498| | // Set the next/prev pointers of the current node to null. This isn't 499| | // strictly required, but this catches errors where a node is removed from 500| | // an ilist (and potentially deleted) with iterators still pointing at it. 501| | // When those iterators are incremented or decremented, they will assert on 502| | // the null next/prev pointer instead of "usually working". 503| 2.82k| this->setNext(Node, nullptr); 504| 2.82k| this->setPrev(Node, nullptr); 505| 2.82k| return Node; 506| 2.82k| } _ZN7llvm_ks14ilist_iteratorINS_10MCFragmentEE5resetEPS1_: 241| 2.82k| void reset(pointer NP) { NodePtr = NP; } _ZN7llvm_ks21ilist_sentinel_traitsINS_10MCFragmentEE15destroySentinelEPS1_: 81| 434| static void destroySentinel(NodeTy *N) { delete N; } _ZNK7llvm_ks14ilist_iteratorINS_10MCFragmentEEptEv: 251| 2.64k| pointer operator->() const { return &operator*(); } _ZN7llvm_ks6iplistINS_10MCFragmentENS_12ilist_traitsIS1_EEE6rbeginEv: 426| 187| reverse_iterator rbegin() { return reverse_iterator(end()); } _ZN7llvm_ks14ilist_iteratorIKNS_10MCFragmentEEC2IS1_EERKNS0_IT_EE: 231| 356| : NodePtr(RHS.getNodePtrUnchecked()) {} _ZNK7llvm_ks14ilist_iteratorIKNS_10MCFragmentEEneIS2_EEbRKNS0_IT_EE: 257| 1.88k| template bool operator!=(const ilist_iterator &RHS) const { 258| 1.88k| return NodePtr != RHS.getNodePtrUnchecked(); 259| 1.88k| } _ZN7llvm_ks14ilist_iteratorIKNS_10MCFragmentEEppEv: 267| 1.70k| ilist_iterator &operator++() { // preincrement - Advance 268| 1.70k| NodePtr = Traits::getNext(NodePtr); 269| 1.70k| return *this; 270| 1.70k| } _ZN7llvm_ks21ilist_nextprev_traitsINS_10MCFragmentEE7getNextEPKS1_: 60| 1.70k| static const NodeTy *getNext(const NodeTy *N) { return N->getNext(); } _ZNK7llvm_ks14ilist_iteratorIKNS_10MCFragmentEEdeEv: 248| 1.70k| reference operator*() const { 249| 1.70k| return *NodePtr; 250| 1.70k| } _ZN7llvm_ks13simplify_typeIKNS_14ilist_iteratorINS_10MCFragmentEEEE18getSimplifiedValueERS4_: 333| 758| static SimpleType getSimplifiedValue(const ilist_iterator &Node) { 334| 758| return &*Node; 335| 758| } _ZN7llvm_ks13simplify_typeINS_14ilist_iteratorINS_10MCFragmentEEEE18getSimplifiedValueERS3_: 326| 758| static SimpleType getSimplifiedValue(ilist_iterator &Node) { 327| 758| return &*Node; 328| 758| } _ZN7llvm_ks15ilist_half_nodeINS_10MCFragmentEE7getPrevEv: 33| 71.9k| NodeTy *getPrev() { return Prev; } _ZN7llvm_ks10ilist_nodeINS_10MCFragmentEE7setNextEPS1_: 56| 8.69k| void setNext(NodeTy *N) { Next = N; } _ZN7llvm_ks15ilist_half_nodeINS_10MCFragmentEE7setPrevEPS1_: 35| 11.7k| void setPrev(NodeTy *P) { Prev = P; } _ZN7llvm_ks22ilist_node_with_parentINS_10MCFragmentENS_9MCSectionEEC2Ev: 78| 21.9k| ilist_node_with_parent() = default; _ZN7llvm_ks10ilist_nodeINS_10MCFragmentEEC2Ev: 58| 21.9k| ilist_node() : Next(nullptr) {} _ZN7llvm_ks15ilist_half_nodeINS_10MCFragmentEEC2Ev: 36| 21.9k| ilist_half_node() : Prev(nullptr) {} _ZN7llvm_ks22ilist_node_with_parentINS_10MCFragmentENS_9MCSectionEE11getPrevNodeEv: 94| 2.50k| NodeTy *getPrevNode() { 95| | // Should be separated to a reused function, but then we couldn't use auto 96| | // (and would need the type of the list). 97| 2.50k| const auto &List = 98| 2.50k| getNodeParent()->*(ParentTy::getSublistAccess((NodeTy *)nullptr)); 99| 2.50k| return List.getPrevNode(*static_cast(this)); 100| 2.50k| } _ZNK7llvm_ks22ilist_node_with_parentINS_10MCFragmentENS_9MCSectionEE13getNodeParentEv: 86| 2.50k| const ParentTy *getNodeParent() const { 87| 2.50k| return static_cast(this)->getParent(); 88| 2.50k| } _ZN7llvm_ks10ilist_nodeINS_10MCFragmentEE11getIteratorEv: 61| 2.50k| ilist_iterator getIterator() { 62| | // FIXME: Stop downcasting to create the iterator (potential UB). 63| 2.50k| return ilist_iterator(static_cast(this)); 64| 2.50k| } _ZN7llvm_ks10ilist_nodeINS_10MCFragmentEE7getNextEv: 54| 16.6k| NodeTy *getNext() { return Next; } _ZNK7llvm_ks10ilist_nodeINS_10MCFragmentEE7getNextEv: 55| 1.70k| const NodeTy *getNext() const { return Next; } _ZN7llvm_ks16pointee_iteratorINSt3__111__wrap_iterIPPNS_9MCSectionEEES3_EC2IS6_EEOT_: 239| 2.20k| : pointee_iterator::iterator_adaptor_base(std::forward(u)) {} _ZN7llvm_ks21iterator_adaptor_baseINS_16pointee_iteratorINSt3__111__wrap_iterIPPNS_9MCSectionEEES4_EES7_NS2_26random_access_iterator_tagES4_lS5_RS4_NS2_15iterator_traitsIS7_EEEC2IS7_EEOT_NS2_9enable_ifIXntsr3std10is_base_ofINS2_9remove_cvINS2_16remove_referenceISF_E4typeEE4typeES8_EE5valueEiE4typeE: 163| 2.20k| : I(std::forward(u)) {} _ZN7llvm_ks16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES4_EC2IS7_EEOT_: 239| 370| : pointee_iterator::iterator_adaptor_base(std::forward(u)) {} _ZN7llvm_ks21iterator_adaptor_baseINS_16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES5_EES8_NS2_26random_access_iterator_tagES5_lS6_RS5_NS2_15iterator_traitsIS8_EEEC2IS8_EEOT_NS2_9enable_ifIXntsr3std10is_base_ofINS2_9remove_cvINS2_16remove_referenceISG_E4typeEE4typeES9_EE5valueEiE4typeE: 163| 370| : I(std::forward(u)) {} _ZNK7llvm_ks20iterator_facade_baseINS_16pointee_iteratorINSt3__111__wrap_iterIPPNS_9MCSectionEEES4_EENS2_26random_access_iterator_tagES4_lS5_RS4_EneERKS8_: 96| 2.20k| bool operator!=(const DerivedT &RHS) const { 97| 2.20k| return !static_cast(this)->operator==(RHS); 98| 2.20k| } _ZNK7llvm_ks21iterator_adaptor_baseINS_16pointee_iteratorINSt3__111__wrap_iterIPPNS_9MCSectionEEES4_EES7_NS2_26random_access_iterator_tagES4_lS5_RS4_NS2_15iterator_traitsIS7_EEEeqERKS8_: 208| 2.20k| bool operator==(const DerivedT &RHS) const { return I == RHS.I; } _ZN7llvm_ks21iterator_adaptor_baseINS_16pointee_iteratorINSt3__111__wrap_iterIPPNS_9MCSectionEEES4_EES7_NS2_26random_access_iterator_tagES4_lS5_RS4_NS2_15iterator_traitsIS7_EEEppEv: 195| 1.10k| DerivedT &operator++() { 196| 1.10k| ++I; 197| 1.10k| return *static_cast(this); 198| 1.10k| } _ZNK7llvm_ks16pointee_iteratorINSt3__111__wrap_iterIPPNS_9MCSectionEEES3_EdeEv: 241| 1.11k| T &operator*() const { return **this->I; } _ZNK7llvm_ks20iterator_facade_baseINS_16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES5_EENS2_26random_access_iterator_tagES5_lS6_RS5_EneERKS9_: 96| 1.39k| bool operator!=(const DerivedT &RHS) const { 97| 1.39k| return !static_cast(this)->operator==(RHS); 98| 1.39k| } _ZNK7llvm_ks21iterator_adaptor_baseINS_16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES5_EES8_NS2_26random_access_iterator_tagES5_lS6_RS5_NS2_15iterator_traitsIS8_EEEeqERKS9_: 208| 1.39k| bool operator==(const DerivedT &RHS) const { return I == RHS.I; } _ZN7llvm_ks21iterator_adaptor_baseINS_16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES5_EES8_NS2_26random_access_iterator_tagES5_lS6_RS5_NS2_15iterator_traitsIS8_EEEppEv: 195| 1.20k| DerivedT &operator++() { 196| 1.20k| ++I; 197| 1.20k| return *static_cast(this); 198| 1.20k| } _ZNK7llvm_ks16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES4_EdeEv: 241| 1.20k| T &operator*() const { return **this->I; } _ZN7llvm_ks10make_rangeINS_16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES5_EEEENS_14iterator_rangeIT_EESB_SB_: 54| 185|template iterator_range make_range(T x, T y) { 55| 185| return iterator_range(std::move(x), std::move(y)); 56| 185|} _ZN7llvm_ks10make_rangeINS_14TargetRegistry8iteratorEEENS_14iterator_rangeIT_EES4_S4_: 54| 3.01k|template iterator_range make_range(T x, T y) { 55| 3.01k| return iterator_range(std::move(x), std::move(y)); 56| 3.01k|} _ZN7llvm_ks14iterator_rangeINS_14TargetRegistry8iteratorEEC2ES2_S2_: 43| 3.01k| : begin_iterator(std::move(begin_iterator)), 44| 3.01k| end_iterator(std::move(end_iterator)) {} _ZNK7llvm_ks14iterator_rangeINS_14TargetRegistry8iteratorEE5beginEv: 46| 860| IteratorT begin() const { return begin_iterator; } _ZNK7llvm_ks14iterator_rangeINS_14TargetRegistry8iteratorEE3endEv: 47| 2.15k| IteratorT end() const { return end_iterator; } _ZN7llvm_ks14iterator_rangeINS_16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES5_EEEC2ES9_S9_: 43| 185| : begin_iterator(std::move(begin_iterator)), 44| 185| end_iterator(std::move(end_iterator)) {} _ZNK7llvm_ks14iterator_rangeINS_16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES5_EEE5beginEv: 46| 185| IteratorT begin() const { return begin_iterator; } _ZNK7llvm_ks14iterator_rangeINS_16pointee_iteratorINSt3__111__wrap_iterIPPKNS_8MCSymbolEEES5_EEE3endEv: 47| 185| IteratorT end() const { return end_iterator; } _ZN7llvm_ks17ConstantPoolEntryC2EPNS_8MCSymbolEPKNS_6MCExprEjNS_5SMLocE: 31| 516| : Label(L), Value(Val), Size(Sz), Loc(Loc_) {} _ZN7llvm_ks12ConstantPoolC2Ev: 46| 6| ConstantPool() {} _ZN7llvm_ks12MCAsmBackend7setArchEi: 145| 430| void setArch(int arch) { KsArch = arch; } _ZNK7llvm_ks12MCAsmBackend17getMinimumNopSizeEv: 128| 265| virtual unsigned getMinimumNopSize() const { return 1; } _ZN7llvm_ks12MCAsmBackend7getArchEv: 146| 6| int getArch() { return KsArch; } _ZN7llvm_ks9MCAsmInfo8setRadixEj: 480| 430| void setRadix(unsigned v) { Radix = v; } _ZNK7llvm_ks9MCAsmInfo14isLittleEndianEv: 379| 4.87k| bool isLittleEndian() const { return IsLittleEndian; } _ZNK7llvm_ks9MCAsmInfo24hasSubsectionsViaSymbolsEv: 384| 18.7k| bool hasSubsectionsViaSymbols() const { return HasSubsectionsViaSymbols; } _ZNK7llvm_ks9MCAsmInfo18getSeparatorStringEv: 451| 590k| const char *getSeparatorString() const { return SeparatorString; } _ZNK7llvm_ks9MCAsmInfo16getCommentStringEv: 457| 283k| const char *getCommentString() const { return CommentString; } _ZNK7llvm_ks9MCAsmInfo22getPrivateGlobalPrefixEv: 463| 11.2k| const char *getPrivateGlobalPrefix() const { return PrivateGlobalPrefix; } _ZNK7llvm_ks9MCAsmInfo19getAssemblerDialectEv: 478| 3.40k| unsigned getAssemblerDialect() const { return AssemblerDialect; } _ZNK7llvm_ks9MCAsmInfo8getRadixEv: 481| 430| unsigned getRadix() const { return Radix; } _ZNK7llvm_ks9MCAsmInfo17doesAllowAtInNameEv: 482| 228| bool doesAllowAtInName() const { return AllowAtInName; } _ZNK7llvm_ks9MCAsmInfo21getAlignmentIsInBytesEv: 490| 131| bool getAlignmentIsInBytes() const { return AlignmentIsInBytes; } _ZNK7llvm_ks9MCAsmInfo34getCOMMDirectiveAlignmentIsInBytesEv: 497| 64| bool getCOMMDirectiveAlignmentIsInBytes() const { 498| 64| return COMMDirectiveAlignmentIsInBytes; 499| 64| } _ZNK7llvm_ks9MCAsmInfo30getLCOMMDirectiveAlignmentTypeEv: 500| 64| LCOMM::LCOMMType getLCOMMDirectiveAlignmentType() const { 501| 64| return LCOMMDirectiveAlignmentType; 502| 64| } _ZNK7llvm_ks9MCAsmInfo24getExceptionHandlingTypeEv: 527| 430| ExceptionHandling getExceptionHandlingType() const { return ExceptionsType; } _ZNK7llvm_ks9MCAsmInfo25useParensForSymbolVariantEv: 548| 31.8k| bool useParensForSymbolVariant() const { return UseParensForSymbolVariant; } _ZNK7llvm_ks9MCAsmInfo21compressDebugSectionsEv: 566| 178| bool compressDebugSections() const { return CompressDebugSections; } _ZNK7llvm_ks9MCAsmInfo19shouldUseLogicalShrEv: 572| 30.0k| bool shouldUseLogicalShr() const { return UseLogicalShr; } _ZNK7llvm_ks11MCAsmLayout12getAssemblerEv: 51| 4.12k| MCAssembler &getAssembler() const { return Assembler; } _ZN7llvm_ks11MCAsmLayout15getSectionOrderEv: 66| 744| llvm_ks::SmallVectorImpl &getSectionOrder() { return SectionOrder; } _ZNK7llvm_ks11MCAssembler8setErrorEj: 64| 179| void setError(unsigned E) const { KsError = E; } _ZNK7llvm_ks11MCAssembler8getErrorEv: 65| 2.05k| unsigned getError() const { return KsError; } _ZNK7llvm_ks11MCAssembler14setSymResolverEPv: 67| 185| void setSymResolver(void *h) const { KsSymResolver = h; } _ZNK7llvm_ks11MCAssembler10getContextEv: 264| 1.99k| MCContext &getContext() const { return Context; } _ZNK7llvm_ks11MCAssembler10getBackendEv: 266| 5.29k| MCAsmBackend &getBackend() const { return Backend; } _ZNK7llvm_ks11MCAssembler10getEmitterEv: 268| 2.24k| MCCodeEmitter &getEmitter() const { return Emitter; } _ZNK7llvm_ks11MCAssembler9getWriterEv: 270| 3.96k| MCObjectWriter &getWriter() const { return Writer; } _ZNK7llvm_ks11MCAssembler11getRelaxAllEv: 294| 2.45k| bool getRelaxAll() const { return RelaxAll; } _ZNK7llvm_ks11MCAssembler17isBundlingEnabledEv: 297| 12.4k| bool isBundlingEnabled() const { return BundleAlignSize != 0; } _ZN7llvm_ks11MCAssembler5beginEv: 310| 1.10k| iterator begin() { return Sections.begin(); } _ZN7llvm_ks11MCAssembler3endEv: 313| 1.10k| iterator end() { return Sections.end(); } _ZN7llvm_ks11MCAssembler12symbol_beginEv: 321| 185| symbol_iterator symbol_begin() { return Symbols.begin(); } _ZN7llvm_ks11MCAssembler10symbol_endEv: 324| 185| symbol_iterator symbol_end() { return Symbols.end(); } _ZN7llvm_ks11MCAssembler7symbolsEv: 327| 185| symbol_range symbols() { return make_range(symbol_begin(), symbol_end()); } _ZN7llvm_ks11MCAssembler11addFileNameENS_9StringRefE: 411| 303| void addFileName(StringRef FileName) { 412| 303| if (std::find(FileNames.begin(), FileNames.end(), FileName) == ------------------ | Branch (412:9): [True: 127, False: 176] ------------------ 413| 303| FileNames.end()) 414| 127| FileNames.push_back(FileName); 415| 303| } _ZN7llvm_ks7MCCVLocC2Ejjjjbb: 43| 430| : FunctionId(functionid), FileNum(fileNum), Line(line), Column(column), 44| 430| PrologueEnd(prologueend), IsStmt(isstmt) {} _ZN7llvm_ks9MCContext13ELFSectionKeyC2ENS_9StringRefES2_j: 183| 18.6k| : SectionName(SectionName), GroupName(GroupName), UniqueID(UniqueID) { 184| 18.6k| } _ZNK7llvm_ks9MCContext13ELFSectionKeyltERKS1_: 185| 126k| bool operator<(const ELFSectionKey &Other) const { 186| 126k| if (SectionName != Other.SectionName) ------------------ | Branch (186:13): [True: 126k, False: 0] ------------------ 187| 126k| return SectionName < Other.SectionName; 188| 0| if (GroupName != Other.GroupName) ------------------ | Branch (188:13): [True: 0, False: 0] ------------------ 189| 0| return GroupName < Other.GroupName; 190| 0| return UniqueID < Other.UniqueID; 191| 0| } _ZNK7llvm_ks9MCContext10getAsmInfoEv: 242| 23.8k| const MCAsmInfo *getAsmInfo() const { return MAI; } _ZNK7llvm_ks9MCContext15getRegisterInfoEv: 244| 2.72k| const MCRegisterInfo *getRegisterInfo() const { return MRI; } _ZNK7llvm_ks9MCContext17getObjectFileInfoEv: 246| 14.7k| const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; } _ZN7llvm_ks9MCContext14getBaseAddressEv: 251| 188| uint64_t getBaseAddress() { return BaseAddress; } _ZN7llvm_ks9MCContext13getELFSectionENS_9StringRefEjj: 331| 12.2k| unsigned Flags) { 332| 12.2k| return getELFSection(Section, Type, Flags, nullptr); 333| 12.2k| } _ZN7llvm_ks9MCContext13getELFSectionENS_9StringRefEjjPKc: 336| 16.5k| unsigned Flags, const char *BeginSymName) { 337| 16.5k| return getELFSection(Section, Type, Flags, 0, "", BeginSymName); 338| 16.5k| } _ZN7llvm_ks9MCContext13getELFSectionENS_9StringRefEjjjS1_: 342| 2.15k| StringRef Group) { 343| 2.15k| return getELFSection(Section, Type, Flags, EntrySize, Group, nullptr); 344| 2.15k| } _ZN7llvm_ks9MCContext13getELFSectionENS_9StringRefEjjjS1_PKc: 348| 18.6k| StringRef Group, const char *BeginSymName) { 349| 18.6k| return getELFSection(Section, Type, Flags, EntrySize, Group, ~0, 350| 18.6k| BeginSymName); 351| 18.6k| } _ZN7llvm_ks9MCContext22getGenDwarfForAssemblyEv: 486| 428| bool getGenDwarfForAssembly() { return GenDwarfForAssembly; } _ZN7llvm_ks9MCContext8allocateEjj: 555| 53.7k| void *allocate(unsigned Size, unsigned Align = 8) { 556| 53.7k| return Allocator.Allocate(Size, Align); 557| 53.7k| } _ZnwmRN7llvm_ks9MCContextEm: 596| 42.0k| size_t Alignment = 8) LLVM_NOEXCEPT { 597| 42.0k| return C.allocate(Bytes, Alignment); 598| 42.0k|} _ZN7llvm_ks10MCDwarfLocC2Ejjjjjj: 78| 860| : FileNum(fileNum), Line(line), Column(column), Flags(flags), Isa(isa), 79| 860| Discriminator(discriminator) {} _ZN7llvm_ks23MCELFObjectTargetWriter8getOSABIENS_6Triple6OSTypeE: 54| 430| static uint8_t getOSABI(Triple::OSType OSType) { 55| 430| switch (OSType) { 56| 0| case Triple::CloudABI: ------------------ | Branch (56:7): [True: 0, False: 430] ------------------ 57| 0| return ELF::ELFOSABI_CLOUDABI; 58| 0| case Triple::PS4: ------------------ | Branch (58:7): [True: 0, False: 430] ------------------ 59| 0| case Triple::FreeBSD: ------------------ | Branch (59:7): [True: 0, False: 430] ------------------ 60| 0| return ELF::ELFOSABI_FREEBSD; 61| 430| default: ------------------ | Branch (61:7): [True: 430, False: 0] ------------------ 62| 430| return ELF::ELFOSABI_NONE; 63| 430| } 64| 430| } _ZN7llvm_ks18ELFRelocationEntryC2EmPKNS_11MCSymbolELFEjm: 37| 30| : Offset(Offset), Symbol(Symbol), Type(Type), Addend(Addend) {} _ZN7llvm_ks23MCELFObjectTargetWriterD2Ev: 66| 430| virtual ~MCELFObjectTargetWriter() {} _ZNK7llvm_ks23MCELFObjectTargetWriter7is64BitEv: 82| 50| bool is64Bit() const { return Is64Bit; } _ZN7llvm_ks13MCELFStreamerC2ERNS_9MCContextERNS_12MCAsmBackendERNS_17raw_pwrite_streamEPNS_13MCCodeEmitterE: 32| 430| : MCObjectStreamer(Context, TAB, OS, Emitter), SeenIdent(false) {} _ZN7llvm_ks6MCExprC2ENS0_8ExprKindE: 59| 42.0k| explicit MCExpr(ExprKind Kind) : Kind(Kind) {} _ZNK7llvm_ks6MCExpr7getKindEv: 70| 133k| ExprKind getKind() const { return Kind; } _ZN7llvm_ks14MCConstantExprC2El: 134| 15.7k| : MCExpr(MCExpr::Constant), Value(Value) {} _ZNK7llvm_ks14MCConstantExpr8getValueEv: 146| 15.4k| int64_t getValue() const { return Value; } _ZN7llvm_ks14MCConstantExpr7classofEPKNS_6MCExprE: 150| 48.1k| static bool classof(const MCExpr *E) { 151| 48.1k| return E->getKind() == MCExpr::Constant; 152| 48.1k| } _ZN7llvm_ks15MCSymbolRefExpr6createEPKNS_8MCSymbolERNS_9MCContextE: 320| 516| static const MCSymbolRefExpr *create(const MCSymbol *Symbol, MCContext &Ctx) { 321| 516| return MCSymbolRefExpr::create(Symbol, VK_None, Ctx); 322| 516| } _ZNK7llvm_ks15MCSymbolRefExpr9getSymbolEv: 333| 25.2k| const MCSymbol &getSymbol() const { return *Symbol; } _ZNK7llvm_ks15MCSymbolRefExpr7getKindEv: 335| 3.01k| VariantKind getKind() const { return Kind; } _ZNK7llvm_ks15MCSymbolRefExpr24hasSubsectionsViaSymbolsEv: 339| 6| bool hasSubsectionsViaSymbols() const { return HasSubsectionsViaSymbols; } _ZN7llvm_ks15MCSymbolRefExpr7classofEPKNS_6MCExprE: 351| 24.9k| static bool classof(const MCExpr *E) { 352| 24.9k| return E->getKind() == MCExpr::SymbolRef; 353| 24.9k| } _ZN7llvm_ks11MCUnaryExprC2ENS0_6OpcodeEPKNS_6MCExprE: 371| 4.65k| : MCExpr(MCExpr::Unary), Op(Op), Expr(Expr) {} _ZN7llvm_ks11MCUnaryExpr10createLNotEPKNS_6MCExprERNS_9MCContextE: 379| 2.32k| static const MCUnaryExpr *createLNot(const MCExpr *Expr, MCContext &Ctx) { 380| 2.32k| return create(LNot, Expr, Ctx); 381| 2.32k| } _ZN7llvm_ks11MCUnaryExpr11createMinusEPKNS_6MCExprERNS_9MCContextE: 382| 2.12k| static const MCUnaryExpr *createMinus(const MCExpr *Expr, MCContext &Ctx) { 383| 2.12k| return create(Minus, Expr, Ctx); 384| 2.12k| } _ZN7llvm_ks11MCUnaryExpr9createNotEPKNS_6MCExprERNS_9MCContextE: 385| 8| static const MCUnaryExpr *createNot(const MCExpr *Expr, MCContext &Ctx) { 386| 8| return create(Not, Expr, Ctx); 387| 8| } _ZN7llvm_ks11MCUnaryExpr10createPlusEPKNS_6MCExprERNS_9MCContextE: 388| 197| static const MCUnaryExpr *createPlus(const MCExpr *Expr, MCContext &Ctx) { 389| 197| return create(Plus, Expr, Ctx); 390| 197| } _ZNK7llvm_ks11MCUnaryExpr9getOpcodeEv: 397| 2.83k| Opcode getOpcode() const { return Op; } _ZNK7llvm_ks11MCUnaryExpr10getSubExprEv: 400| 10.7k| const MCExpr *getSubExpr() const { return Expr; } _ZN7llvm_ks11MCUnaryExpr7classofEPKNS_6MCExprE: 404| 10.7k| static bool classof(const MCExpr *E) { 405| 10.7k| return E->getKind() == MCExpr::Unary; 406| 10.7k| } _ZN7llvm_ks12MCBinaryExprC2ENS0_6OpcodeEPKNS_6MCExprES4_: 443| 3.13k| : MCExpr(MCExpr::Binary), Op(Op), LHS(LHS), RHS(RHS) {} _ZNK7llvm_ks12MCBinaryExpr9getOpcodeEv: 533| 1.61k| Opcode getOpcode() const { return Op; } _ZNK7llvm_ks12MCBinaryExpr6getLHSEv: 536| 5.38k| const MCExpr *getLHS() const { return LHS; } _ZNK7llvm_ks12MCBinaryExpr6getRHSEv: 539| 3.54k| const MCExpr *getRHS() const { return RHS; } _ZN7llvm_ks12MCBinaryExpr7classofEPKNS_6MCExprE: 543| 5.38k| static bool classof(const MCExpr *E) { 544| 5.38k| return E->getKind() == MCExpr::Binary; 545| 5.38k| } _ZN7llvm_ks7MCFixup6createEjPKNS_6MCExprENS_11MCFixupKindENS_5SMLocE: 87| 1.18k| MCFixupKind Kind, SMLoc Loc = SMLoc()) { 88| 1.18k| assert(unsigned(Kind) < MaxTargetFixupKind && "Kind out of range!"); ------------------ | Branch (88:5): [True: 1.18k, False: 0] | Branch (88:5): [True: 1.18k, Folded] | Branch (88:5): [True: 1.18k, False: 0] ------------------ 89| 1.18k| MCFixup FI; 90| 1.18k| FI.Value = Value; 91| 1.18k| FI.Offset = Offset; 92| 1.18k| FI.Kind = unsigned(Kind); 93| 1.18k| FI.Loc = Loc; 94| 1.18k| return FI; 95| 1.18k| } _ZNK7llvm_ks7MCFixup7getKindEv: 119| 17.6k| MCFixupKind getKind() const { return MCFixupKind(Kind); } _ZNK7llvm_ks7MCFixup9getOffsetEv: 121| 2.40k| uint32_t getOffset() const { return Offset; } _ZN7llvm_ks7MCFixup9setOffsetEj: 122| 251| void setOffset(uint32_t Value) { Offset = Value; } _ZNK7llvm_ks7MCFixup8getValueEv: 124| 2.34k| const MCExpr *getValue() const { return Value; } _ZN7llvm_ks7MCFixup14getKindForSizeEjb: 128| 180| static MCFixupKind getKindForSize(unsigned Size, bool isPCRel) { 129| 180| switch (Size) { 130| 0| default: llvm_unreachable("Invalid generic fixup size!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ | Branch (130:5): [True: 0, False: 180] ------------------ 131| 131| case 1: return isPCRel ? FK_PCRel_1 : FK_Data_1; ------------------ | Branch (131:5): [True: 131, False: 49] | Branch (131:20): [True: 0, False: 131] ------------------ 132| 5| case 2: return isPCRel ? FK_PCRel_2 : FK_Data_2; ------------------ | Branch (132:5): [True: 5, False: 175] | Branch (132:20): [True: 0, False: 5] ------------------ 133| 44| case 4: return isPCRel ? FK_PCRel_4 : FK_Data_4; ------------------ | Branch (133:5): [True: 44, False: 136] | Branch (133:20): [True: 0, False: 44] ------------------ 134| 0| case 8: return isPCRel ? FK_PCRel_8 : FK_Data_8; ------------------ | Branch (134:5): [True: 0, False: 180] | Branch (134:20): [True: 0, False: 0] ------------------ 135| 180| } 136| 180| } _ZNK7llvm_ks7MCFixup6getLocEv: 162| 106| SMLoc getLoc() const { return Loc; } _ZNK7llvm_ks10MCFragment7getKindEv: 97| 42.7k| FragmentType getKind() const { return Kind; } _ZNK7llvm_ks10MCFragment9getParentEv: 99| 35.1k| MCSection *getParent() const { return Parent; } _ZN7llvm_ks10MCFragment9setParentEPNS_9MCSectionE: 100| 2.82k| void setParent(MCSection *Value) { Parent = Value; } _ZNK7llvm_ks10MCFragment14getLayoutOrderEv: 105| 22.6k| unsigned getLayoutOrder() const { return LayoutOrder; } _ZN7llvm_ks10MCFragment14setLayoutOrderEj: 106| 2.51k| void setLayoutOrder(unsigned Value) { LayoutOrder = Value; } _ZNK7llvm_ks10MCFragment16getBundlePaddingEv: 121| 1.62k| uint8_t getBundlePadding() const { return BundlePadding; } _ZNK7llvm_ks10MCFragment7isDummyEv: 128| 18.6k| bool isDummy() const { return Kind == FT_Dummy; } _ZN7llvm_ks15MCDummyFragmentC2EPNS_9MCSectionE: 136| 18.6k| : MCFragment(FT_Dummy, false, 0, Sec){}; _ZN7llvm_ks17MCEncodedFragmentC2ENS_10MCFragment12FragmentTypeEbPNS_9MCSectionE: 147| 1.62k| : MCFragment(FType, HasInstructions, 0, Sec) {} _ZN7llvm_ks17MCEncodedFragment7classofEPKNS_10MCFragmentE: 150| 3.01k| static bool classof(const MCFragment *F) { 151| 3.01k| MCFragment::FragmentType Kind = F->getKind(); 152| 3.01k| switch (Kind) { 153| 964| default: ------------------ | Branch (153:5): [True: 964, False: 2.04k] ------------------ 154| 964| return false; 155| 1.18k| case MCFragment::FT_Relaxable: ------------------ | Branch (155:5): [True: 1.18k, False: 1.82k] ------------------ 156| 1.18k| case MCFragment::FT_CompactEncodedInst: ------------------ | Branch (156:5): [True: 0, False: 3.01k] ------------------ 157| 2.04k| case MCFragment::FT_Data: ------------------ | Branch (157:5): [True: 860, False: 2.15k] ------------------ 158| 2.04k| return true; 159| 3.01k| } 160| 3.01k| } _ZN7llvm_ks14MCDataFragmentC2EPNS_9MCSectionE: 222| 779| : MCEncodedFragmentWithFixups<32, 4>(FT_Data, false, Sec) {} _ZN7llvm_ks14MCDataFragment18setHasInstructionsEb: 224| 1.34k| void setHasInstructions(bool V) { HasInstructions = V; } _ZN7llvm_ks14MCDataFragment7classofEPKNS_10MCFragmentE: 226| 20.6k| static bool classof(const MCFragment *F) { 227| 20.6k| return F->getKind() == MCFragment::FT_Data; 228| 20.6k| } _ZN7llvm_ks28MCCompactEncodedInstFragment7classofEPKNS_10MCFragmentE: 242| 1.02k| static bool classof(const MCFragment *F) { 243| 1.02k| return F->getKind() == MCFragment::FT_CompactEncodedInst; 244| 1.02k| } _ZN7llvm_ks19MCRelaxableFragmentC2ERKNS_6MCInstERKNS_15MCSubtargetInfoEPNS_9MCSectionE: 261| 850| : MCEncodedFragmentWithFixups(FT_Relaxable, true, Sec), 262| 850| Inst(Inst), STI(STI) {} _ZNK7llvm_ks19MCRelaxableFragment7getInstEv: 264| 804| const MCInst &getInst() const { return Inst; } _ZN7llvm_ks19MCRelaxableFragment7setInstERKNS_6MCInstE: 265| 46| void setInst(const MCInst &Value) { Inst = Value; } _ZN7llvm_ks19MCRelaxableFragment16getSubtargetInfoEv: 267| 46| const MCSubtargetInfo &getSubtargetInfo() { return STI; } _ZN7llvm_ks19MCRelaxableFragment7classofEPKNS_10MCFragmentE: 269| 5.05k| static bool classof(const MCFragment *F) { 270| 5.05k| return F->getKind() == MCFragment::FT_Relaxable; 271| 5.05k| } _ZN7llvm_ks15MCAlignFragmentC2EjljjPNS_9MCSectionE: 297| 732| : MCFragment(FT_Align, false, 0, Sec), Alignment(Alignment), 298| 732| EmitNops(false), Value(Value), 299| 732| ValueSize(ValueSize), MaxBytesToEmit(MaxBytesToEmit) {} _ZNK7llvm_ks15MCAlignFragment12getAlignmentEv: 304| 1.22k| unsigned getAlignment() const { return Alignment; } _ZNK7llvm_ks15MCAlignFragment12getValueSizeEv: 308| 1.48k| unsigned getValueSize() const { return ValueSize; } _ZNK7llvm_ks15MCAlignFragment17getMaxBytesToEmitEv: 310| 1.22k| unsigned getMaxBytesToEmit() const { return MaxBytesToEmit; } _ZNK7llvm_ks15MCAlignFragment11hasEmitNopsEv: 312| 760| bool hasEmitNops() const { return EmitNops; } _ZN7llvm_ks15MCAlignFragment11setEmitNopsEb: 313| 732| void setEmitNops(bool Value) { EmitNops = Value; } _ZN7llvm_ks15MCAlignFragment7classofEPKNS_10MCFragmentE: 317| 3.18k| static bool classof(const MCFragment *F) { 318| 3.18k| return F->getKind() == MCFragment::FT_Align; 319| 3.18k| } _ZN7llvm_ks14MCFillFragmentC2EhmPNS_9MCSectionE: 332| 292| : MCFragment(FT_Fill, false, 0, Sec), Value(Value), Size(Size) {} _ZNK7llvm_ks14MCFillFragment8getValueEv: 334| 292| uint8_t getValue() const { return Value; } _ZNK7llvm_ks14MCFillFragment7getSizeEv: 335| 871| uint64_t getSize() const { return Size; } _ZN7llvm_ks14MCFillFragment7classofEPKNS_10MCFragmentE: 337| 1.16k| static bool classof(const MCFragment *F) { 338| 1.16k| return F->getKind() == MCFragment::FT_Fill; 339| 1.16k| } _ZN7llvm_ks13MCOrgFragmentC2ERKNS_6MCExprEaPNS_9MCSectionE: 352| 174| : MCFragment(FT_Org, false, 0, Sec), Offset(&Offset), Value(Value) {} _ZNK7llvm_ks13MCOrgFragment9getOffsetEv: 357| 192| const MCExpr &getOffset() const { return *Offset; } _ZNK7llvm_ks13MCOrgFragment8getValueEv: 359| 39| uint8_t getValue() const { return Value; } _ZN7llvm_ks13MCOrgFragment7classofEPKNS_10MCFragmentE: 363| 461| static bool classof(const MCFragment *F) { 364| 461| return F->getKind() == MCFragment::FT_Org; 365| 461| } _ZN7llvm_ks27MCEncodedFragmentWithFixupsILj32ELj4EEC2ENS_10MCFragment12FragmentTypeEbPNS_9MCSectionE: 195| 779| : MCEncodedFragmentWithContents(FType, HasInstructions, 196| 779| Sec) {} _ZN7llvm_ks29MCEncodedFragmentWithContentsILj32EEC2ENS_10MCFragment12FragmentTypeEbPNS_9MCSectionE: 174| 779| : MCEncodedFragment(FType, HasInstructions, Sec) {} _ZN7llvm_ks29MCEncodedFragmentWithContentsILj32EE11getContentsEv: 177| 14.2k| SmallVectorImpl &getContents() { return Contents; } _ZN7llvm_ks27MCEncodedFragmentWithFixupsILj32ELj4EE9getFixupsEv: 202| 861| SmallVectorImpl &getFixups() { return Fixups; } _ZN7llvm_ks27MCEncodedFragmentWithFixupsILj8ELj1EE9getFixupsEv: 202| 3.04k| SmallVectorImpl &getFixups() { return Fixups; } _ZNK7llvm_ks29MCEncodedFragmentWithContentsILj32EE11getContentsEv: 178| 1.28k| const SmallVectorImpl &getContents() const { return Contents; } _ZN7llvm_ks27MCEncodedFragmentWithFixupsILj8ELj1EEC2ENS_10MCFragment12FragmentTypeEbPNS_9MCSectionE: 195| 850| : MCEncodedFragmentWithContents(FType, HasInstructions, 196| 850| Sec) {} _ZN7llvm_ks29MCEncodedFragmentWithContentsILj8EEC2ENS_10MCFragment12FragmentTypeEbPNS_9MCSectionE: 174| 850| : MCEncodedFragment(FType, HasInstructions, Sec) {} _ZN7llvm_ks29MCEncodedFragmentWithContentsILj8EE11getContentsEv: 177| 1.48k| SmallVectorImpl &getContents() { return Contents; } _ZNK7llvm_ks29MCEncodedFragmentWithContentsILj8EE11getContentsEv: 178| 1.41k| const SmallVectorImpl &getContents() const { return Contents; } _ZNK7llvm_ks27MCEncodedFragmentWithFixupsILj8ELj1EE9getFixupsEv: 203| 666| const SmallVectorImpl &getFixups() const { return Fixups; } _ZN7llvm_ks9MCOperandC2Ev: 52| 10.2k| MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} _ZNK7llvm_ks9MCOperand5isRegEv: 55| 7.36k| bool isReg() const { return Kind == kRegister; } _ZNK7llvm_ks9MCOperand5isImmEv: 56| 6.03k| bool isImm() const { return Kind == kImmediate; } _ZNK7llvm_ks9MCOperand6isExprEv: 58| 13.6k| bool isExpr() const { return Kind == kExpr; } _ZNK7llvm_ks9MCOperand6getRegEv: 62| 4.34k| unsigned getReg() const { 63| 4.34k| assert(isReg() && "This is not a register operand!"); ------------------ | Branch (63:5): [True: 4.34k, False: 0] | Branch (63:5): [True: 4.34k, Folded] | Branch (63:5): [True: 4.34k, False: 0] ------------------ 64| 4.34k| return RegVal; 65| 4.34k| } _ZNK7llvm_ks9MCOperand6getImmEv: 73| 4.15k| int64_t getImm() const { 74| 4.15k| assert(isImm() && "This is not an immediate"); ------------------ | Branch (74:5): [True: 4.15k, False: 0] | Branch (74:5): [True: 4.15k, Folded] | Branch (74:5): [True: 4.15k, False: 0] ------------------ 75| 4.15k| return ImmVal; 76| 4.15k| } _ZN7llvm_ks9MCOperand6setImmEl: 77| 66| void setImm(int64_t Val) { 78| 66| assert(isImm() && "This is not an immediate"); ------------------ | Branch (78:5): [True: 66, False: 0] | Branch (78:5): [True: 66, Folded] | Branch (78:5): [True: 66, False: 0] ------------------ 79| 66| ImmVal = Val; 80| 66| } _ZNK7llvm_ks9MCOperand7getExprEv: 92| 1.95k| const MCExpr *getExpr() const { 93| 1.95k| assert(isExpr() && "This is not an expression"); ------------------ | Branch (93:5): [True: 1.95k, False: 0] | Branch (93:5): [True: 1.95k, Folded] | Branch (93:5): [True: 1.95k, False: 0] ------------------ 94| 1.95k| return ExprVal; 95| 1.95k| } _ZN7llvm_ks9MCOperand9createRegEj: 110| 5.57k| static MCOperand createReg(unsigned Reg) { 111| 5.57k| MCOperand Op; 112| 5.57k| Op.Kind = kRegister; 113| 5.57k| Op.RegVal = Reg; 114| 5.57k| return Op; 115| 5.57k| } _ZN7llvm_ks9MCOperand9createImmEl: 116| 3.72k| static MCOperand createImm(int64_t Val) { 117| 3.72k| MCOperand Op; 118| 3.72k| Op.Kind = kImmediate; 119| 3.72k| Op.ImmVal = Val; 120| 3.72k| return Op; 121| 3.72k| } _ZN7llvm_ks9MCOperand10createExprEPKNS_6MCExprE: 128| 957| static MCOperand createExpr(const MCExpr *Val) { 129| 957| MCOperand Op; 130| 957| Op.Kind = kExpr; 131| 957| Op.ExprVal = Val; 132| 957| return Op; 133| 957| } _ZN7llvm_ks6MCInstC2Em: 158| 2.52k| MCInst(uint64_t addr = 0) : Opcode(0), Address(addr) {} _ZN7llvm_ks6MCInst9setOpcodeEj: 160| 3.03k| void setOpcode(unsigned Op) { Opcode = Op; } _ZNK7llvm_ks6MCInst9getOpcodeEv: 161| 25.8k| unsigned getOpcode() const { return Opcode; } _ZN7llvm_ks6MCInst10setAddressEm: 163| 2.24k| void setAddress(uint64_t addr) { Address = addr; } _ZNK7llvm_ks6MCInst10getAddressEv: 164| 5.65k| uint64_t getAddress() const { return Address; } _ZN7llvm_ks6MCInst6setLocENS_5SMLocE: 166| 2.19k| void setLoc(SMLoc loc) { Loc = loc; } _ZNK7llvm_ks6MCInst6getLocEv: 167| 1.00k| SMLoc getLoc() const { return Loc; } _ZNK7llvm_ks6MCInst10getOperandEj: 169| 6.36k| const MCOperand &getOperand(unsigned i) const { return Operands[i]; } _ZN7llvm_ks6MCInst10getOperandEj: 170| 15.4k| MCOperand &getOperand(unsigned i) { return Operands[i]; } _ZNK7llvm_ks6MCInst14getNumOperandsEv: 171| 2.58k| unsigned getNumOperands() const { return Operands.size(); } _ZN7llvm_ks6MCInst10addOperandERKNS_9MCOperandE: 173| 11.2k| void addOperand(const MCOperand &Op) { Operands.push_back(Op); } _ZN7llvm_ks6MCInst5clearEv: 177| 2.57k| void clear() { Operands.clear(); } _ZNK7llvm_ks13MCOperandInfo11isPredicateEv: 91| 5.40k| bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } _ZNK7llvm_ks13MCOperandInfo13isOptionalDefEv: 94| 564| bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } _ZNK7llvm_ks11MCInstrDesc14getNumOperandsEv: 203| 1.80k| unsigned getNumOperands() const { return NumOperands; } _ZNK7llvm_ks11MCInstrDesc12isPredicableEv: 238| 3.60k| bool isPredicable() const { return Flags & (1 << MCID::Predicable); } _ZNK7llvm_ks11MCInstrDesc7getSizeEv: 324| 5.63k| unsigned getSize() const { return Size; } _ZNK7llvm_ks11MCInstrDesc23findFirstPredOperandIdxEv: 329| 1.80k| int findFirstPredOperandIdx() const { 330| 1.80k| if (isPredicable()) { ------------------ | Branch (330:9): [True: 1.80k, False: 0] ------------------ 331| 5.40k| for (unsigned i = 0, e = getNumOperands(); i != e; ++i) ------------------ | Branch (331:50): [True: 5.40k, False: 0] ------------------ 332| 5.40k| if (OpInfo[i].isPredicate()) ------------------ | Branch (332:13): [True: 1.80k, False: 3.60k] ------------------ 333| 1.80k| return i; 334| 1.80k| } 335| 0| return -1; 336| 1.80k| } _ZN7llvm_ks11MCInstrInfo15InitMCInstrInfoEPKNS_11MCInstrDescEPKjPKcj: 34| 430| unsigned NO) { 35| 430| Desc = D; 36| 430| InstrNameIndices = NI; 37| 430| InstrNameData = ND; 38| 430| NumOpcodes = NO; 39| 430| } _ZNK7llvm_ks11MCInstrInfo3getEj: 45| 9.18k| const MCInstrDesc &get(unsigned Opcode) const { 46| 9.18k| assert(Opcode < NumOpcodes && "Invalid opcode!"); ------------------ | Branch (46:5): [True: 9.18k, False: 0] | Branch (46:5): [True: 9.18k, Folded] | Branch (46:5): [True: 9.18k, False: 0] ------------------ 47| 9.18k| return Desc[Opcode]; 48| 9.18k| } _ZN7llvm_ks14MCLOHContainerC2Ev: 128| 430| MCLOHContainer() : EmitSize(0) {} _ZNK7llvm_ks16MCObjectFileInfo14getTextSectionEv: 219| 430| MCSection *getTextSection() const { return TextSection; } _ZNK7llvm_ks16MCObjectFileInfo17getObjectFileTypeEv: 339| 25.5k| Environment getObjectFileType() const { return Env; } _ZNK7llvm_ks16MCObjectFileInfo15getTargetTripleEv: 352| 13| const Triple &getTargetTriple() const { return TT; } _ZN7llvm_ks16MCObjectStreamer6insertEPNS_10MCFragmentE: 64| 2.69k| void insert(MCFragment *F) { 65| 2.69k| flushPendingLabels(F); 66| 2.69k| MCSection *CurSection = getCurrentSectionOnly(); 67| 2.69k| CurSection->getFragmentList().insert(CurInsertionPoint, F); 68| 2.69k| F->setParent(CurSection); 69| 2.69k| } _ZN7llvm_ks16MCObjectStreamer12getAssemblerEv: 87| 14.4k| MCAssembler &getAssembler() { return *Assembler; } _ZN7llvm_ks14MCObjectWriterC2ERNS_17raw_pwrite_streamEb: 51| 430| : OS(&OS), IsLittleEndian(IsLittleEndian) {} _ZN7llvm_ks14MCObjectWriter9getStreamEv: 65| 3.95k| raw_pwrite_stream &getStream() { return *OS; } _ZN7llvm_ks14MCObjectWriter6write8Eh: 127| 42| void write8(uint8_t Value) { *OS << char(Value); } _ZN7llvm_ks14MCObjectWriter9writeBE16Et: 141| 9| void writeBE16(uint16_t Value) { 142| 9| support::endian::Writer(*OS).write(Value); 143| 9| } _ZN7llvm_ks14MCObjectWriter7write16Et: 153| 9| void write16(uint16_t Value) { 154| 9| if (IsLittleEndian) ------------------ | Branch (154:9): [True: 0, False: 9] ------------------ 155| 0| writeLE16(Value); 156| 9| else 157| 9| writeBE16(Value); 158| 9| } _ZN7llvm_ks14MCObjectWriter10WriteZerosEj: 174| 178| void WriteZeros(unsigned N) { 175| 178| const char Zeros[16] = {0}; 176| | 177| 178| for (unsigned i = 0, e = N / 16; i != e; ++i) ------------------ | Branch (177:38): [True: 0, False: 178] ------------------ 178| 0| *OS << StringRef(Zeros, 16); 179| | 180| 178| *OS << StringRef(Zeros, N % 16); 181| 178| } _ZN7llvm_ks14MCObjectWriter10writeBytesERKNS_15SmallVectorImplIcEEj: 184| 742| unsigned ZeroFillSize = 0) { 185| 742| writeBytes(StringRef(ByteVec.data(), ByteVec.size()), ZeroFillSize); 186| 742| } _ZN7llvm_ks14MCObjectWriter10writeBytesENS_9StringRefEj: 188| 13.9k| void writeBytes(StringRef Str, unsigned ZeroFillSize = 0) { 189| | // TODO: this version may need to go away once all fragment contents are 190| | // converted to SmallVector 191| 13.9k| assert( ------------------ | Branch (191:5): [True: 13.9k, False: 0] | Branch (191:5): [True: 0, False: 0] | Branch (191:5): [True: 13.9k, Folded] | Branch (191:5): [True: 13.9k, False: 0] ------------------ 192| 13.9k| (ZeroFillSize == 0 || Str.size() <= ZeroFillSize) && 193| 13.9k| "data size greater than fill size, unexpected large write will occur"); 194| 13.9k| *OS << Str; 195| 13.9k| if (ZeroFillSize) ------------------ | Branch (195:9): [True: 0, False: 13.9k] ------------------ 196| 0| WriteZeros(ZeroFillSize - Str.size()); 197| 13.9k| } _ZN7llvm_ks7AsmCondC2Ev: 35| 430| AsmCond() : TheCond(NoCond), CondMet(false), Ignore(false) {} _ZNK7llvm_ks8AsmLexer6getMAIEv: 57| 128| const MCAsmInfo &getMAI() const { return MAI; } _ZN7llvm_ks8AsmTokenC2Ev: 65| 1.48k| AsmToken() {} _ZN7llvm_ks8AsmTokenC2ENS0_9TokenKindENS_9StringRefENS_5APIntE: 67| 11.9k| : Kind(Kind), Str(Str), IntVal(IntVal) {} _ZN7llvm_ks8AsmTokenC2ENS0_9TokenKindENS_9StringRefEl: 69| 242k| : Kind(Kind), Str(Str), IntVal(64, IntVal, true) {} _ZNK7llvm_ks8AsmToken7getKindEv: 71| 178k| TokenKind getKind() const { return Kind; } _ZNK7llvm_ks8AsmToken2isENS0_9TokenKindE: 72| 757k| bool is(TokenKind K) const { return Kind == K; } _ZNK7llvm_ks8AsmToken5isNotENS0_9TokenKindE: 73| 249k| bool isNot(TokenKind K) const { return Kind != K; } _ZNK7llvm_ks8AsmToken17getStringContentsERb: 80| 1.61k| StringRef getStringContents(bool &valid) const { 81| | //assert(Kind == String && "This token isn't a string!"); 82| 1.61k| if (Kind != String) { ------------------ | Branch (82:9): [True: 0, False: 1.61k] ------------------ 83| 0| valid = false; 84| 0| return nullptr; 85| 0| } 86| 1.61k| valid = true; 87| 1.61k| return Str.slice(1, Str.size() - 1); 88| 1.61k| } _ZNK7llvm_ks8AsmToken13getIdentifierEv: 94| 59.7k| StringRef getIdentifier() const { 95| 59.7k| if (Kind == Identifier) ------------------ | Branch (95:9): [True: 59.1k, False: 668] ------------------ 96| 59.1k| return getString(); 97| 668| bool valid; 98| 668| return getStringContents(valid); 99| 59.7k| } _ZNK7llvm_ks8AsmToken9getStringEv: 106| 95.4k| StringRef getString() const { return Str; } _ZNK7llvm_ks8AsmToken9getIntValERb: 111| 7.29k| int64_t getIntVal(bool &valid) const { 112| | //assert(Kind == Integer && "This token isn't an integer!"); 113| 7.29k| if (Kind != Integer) { ------------------ | Branch (113:9): [True: 0, False: 7.29k] ------------------ 114| 0| valid = false; 115| 0| return -1; 116| 0| } 117| 7.29k| valid = true; 118| 7.29k| return IntVal.getZExtValue(); 119| 7.29k| } _ZNK7llvm_ks8AsmToken11getAPIntValERb: 121| 334| APInt getAPIntVal(bool &valid) const { 122| | //assert((Kind == Integer || Kind == BigNum) && 123| | // "This token isn't an integer!"); 124| 334| if (Kind != Integer && Kind != BigNum) { ------------------ | Branch (124:9): [True: 148, False: 186] | Branch (124:28): [True: 0, False: 148] ------------------ 125| 0| valid = false; 126| | //return APInt(-1); 127| 0| } 128| 334| valid = true; 129| 334| return IntVal; 130| 334| } _ZN7llvm_ks10MCAsmLexer8SetErrorENS_5SMLocERKNSt3__112basic_stringIcNS2_11char_traitsIcEENS2_9allocatorIcEEEE: 154| 321| void SetError(SMLoc errLoc, const std::string &err) { 155| 321| ErrLoc = errLoc; 156| 321| Err = err; 157| 321| } _ZN7llvm_ks10MCAsmLexer3LexEv: 166| 253k| const AsmToken &Lex() { 167| 253k| assert(!CurTok.empty()); ------------------ | Branch (167:5): [True: 253k, False: 0] ------------------ 168| 253k| CurTok.erase(CurTok.begin()); 169| 253k| if (CurTok.empty()) ------------------ | Branch (169:9): [True: 253k, False: 0] ------------------ 170| 253k| CurTok.emplace_back(LexToken()); 171| 253k| return CurTok.front(); 172| 253k| } _ZNK7llvm_ks10MCAsmLexer6getTokEv: 184| 1.12M| const AsmToken &getTok() const { 185| 1.12M| return CurTok[0]; 186| 1.12M| } _ZN7llvm_ks10MCAsmLexer7peekTokEb: 189| 321| const AsmToken peekTok(bool ShouldSkipSpace = true) { 190| 321| AsmToken Tok; 191| | 192| 321| MutableArrayRef Buf(Tok); 193| 321| if (peekTokens(Buf, ShouldSkipSpace) != 1) ------------------ | Branch (193:9): [True: 0, False: 321] ------------------ 194| 0| return AsmToken(AsmToken::Error, nullptr); 195| | 196| 321| return Tok; 197| 321| } _ZN7llvm_ks10MCAsmLexer9getErrLocEv: 204| 321| SMLoc getErrLoc() { 205| 321| return ErrLoc; 206| 321| } _ZN7llvm_ks10MCAsmLexer6getErrEv: 209| 321| const std::string &getErr() { 210| 321| return Err; 211| 321| } _ZNK7llvm_ks10MCAsmLexer7getKindEv: 214| 178k| AsmToken::TokenKind getKind() const { return getTok().getKind(); } _ZNK7llvm_ks10MCAsmLexer2isENS_8AsmToken9TokenKindE: 217| 489k| bool is(AsmToken::TokenKind K) const { return getTok().is(K); } _ZNK7llvm_ks10MCAsmLexer5isNotENS_8AsmToken9TokenKindE: 220| 217k| bool isNot(AsmToken::TokenKind K) const { return getTok().isNot(K); } _ZN7llvm_ks10MCAsmLexer12setSkipSpaceEb: 223| 37.5k| void setSkipSpace(bool val) { SkipSpace = val; } _ZNK7llvm_ks11MCAsmParser8getLexerEv: 93| 225k| const MCAsmLexer &getLexer() const { 94| 225k| return const_cast(this)->getLexer(); 95| 225k| } _ZNK7llvm_ks11MCAsmParser15getTargetParserEv: 102| 22.7k| MCTargetAsmParser &getTargetParser() const { return *TargetParser; } _ZN7llvm_ks20MCAsmParserExtension10getContextEv: 54| 17.5k| MCContext &getContext() { return getParser().getContext(); } _ZN7llvm_ks20MCAsmParserExtension8getLexerEv: 56| 52.2k| MCAsmLexer &getLexer() { return getParser().getLexer(); } _ZN7llvm_ks20MCAsmParserExtension9getParserEv: 61| 210k| MCAsmParser &getParser() { return *Parser; } _ZN7llvm_ks20MCAsmParserExtension11getStreamerEv: 67| 292| MCStreamer &getStreamer() { return getParser().getStreamer(); } _ZN7llvm_ks20MCAsmParserExtension7WarningENS_5SMLocERKNS_5TwineE: 68| 509| bool Warning(SMLoc L, const Twine &Msg) { 69| 509| return getParser().Warning(L, Msg); 70| 509| } _ZN7llvm_ks20MCAsmParserExtension5ErrorENS_5SMLocERKNS_5TwineE: 71| 3| bool Error(SMLoc L, const Twine &Msg) { 72| 3| return getParser().Error(L, Msg); 73| 3| } _ZN7llvm_ks20MCAsmParserExtension8TokErrorERKNS_5TwineE: 77| 7| bool TokError(const Twine &Msg) { 78| 7| return getParser().TokError(Msg); 79| 7| } _ZN7llvm_ks20MCAsmParserExtension3LexEv: 81| 1.21k| const AsmToken &Lex() { return getParser().Lex(); } DarwinAsmParser.cpp:_ZN7llvm_ks20MCAsmParserExtension15HandleDirectiveIN12_GLOBAL__N_115DarwinAsmParserETnMT_FbNS_9StringRefENS_5SMLocEEXadL_ZNS3_24parseDirectiveDumpOrLoadES5_S6_EEEEbPS0_S5_S6_: 36| 510| SMLoc DirectiveLoc) { 37| 510| T *Obj = static_cast(Target); 38| 510| return (Obj->*Handler)(Directive, DirectiveLoc); 39| 510| } DarwinAsmParser.cpp:_ZN7llvm_ks20MCAsmParserExtension15HandleDirectiveIN12_GLOBAL__N_115DarwinAsmParserETnMT_FbNS_9StringRefENS_5SMLocEEXadL_ZNS3_21parseDirectiveSectionES5_S6_EEEEbPS0_S5_S6_: 36| 16| SMLoc DirectiveLoc) { 37| 16| T *Obj = static_cast(Target); 38| 16| return (Obj->*Handler)(Directive, DirectiveLoc); 39| 16| } DarwinAsmParser.cpp:_ZN7llvm_ks20MCAsmParserExtension15HandleDirectiveIN12_GLOBAL__N_115DarwinAsmParserETnMT_FbNS_9StringRefENS_5SMLocEEXadL_ZNS3_18parseDirectiveTBSSES5_S6_EEEEbPS0_S5_S6_: 36| 39| SMLoc DirectiveLoc) { 37| 39| T *Obj = static_cast(Target); 38| 39| return (Obj->*Handler)(Directive, DirectiveLoc); 39| 39| } DarwinAsmParser.cpp:_ZN7llvm_ks20MCAsmParserExtension15HandleDirectiveIN12_GLOBAL__N_115DarwinAsmParserETnMT_FbNS_9StringRefENS_5SMLocEEXadL_ZNS3_25parseSectionDirectiveDataES5_S6_EEEEbPS0_S5_S6_: 36| 130| SMLoc DirectiveLoc) { 37| 130| T *Obj = static_cast(Target); 38| 130| return (Obj->*Handler)(Directive, DirectiveLoc); 39| 130| } DarwinAsmParser.cpp:_ZN7llvm_ks20MCAsmParserExtension15HandleDirectiveIN12_GLOBAL__N_115DarwinAsmParserETnMT_FbNS_9StringRefENS_5SMLocEEXadL_ZNS3_26parseSectionDirectiveIdentES5_S6_EEEEbPS0_S5_S6_: 36| 152| SMLoc DirectiveLoc) { 37| 152| T *Obj = static_cast(Target); 38| 152| return (Obj->*Handler)(Directive, DirectiveLoc); 39| 152| } _ZN7llvm_ks18MCParsedAsmOperandD2Ev: 43| 33.6k| virtual ~MCParsedAsmOperand() {} _ZN7llvm_ks18MCParsedAsmOperandC2Ev: 40| 33.6k| MCParsedAsmOperand() = default; _ZN7llvm_ks20ParseInstructionInfoC2EPNS_15SmallVectorImplINS_10AsmRewriteEEE: 81| 3.40k| : AsmRewrites(rewrites) {} _ZNK7llvm_ks17MCTargetAsmParser20getAvailableFeaturesEv: 129| 28.2k| uint64_t getAvailableFeatures() const { return AvailableFeatures; } _ZN7llvm_ks17MCTargetAsmParser20setAvailableFeaturesEm: 131| 3.10k| void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; } _ZNK7llvm_ks17MCTargetAsmParser16getTargetOptionsEv: 137| 1.63k| MCTargetOptions getTargetOptions() const { return MCOptions; } _ZN7llvm_ks17MCTargetAsmParser16ParseInstructionERNS_20ParseInstructionInfoENS_9StringRefENS_8AsmTokenERNS_15SmallVectorImplINSt3__110unique_ptrINS_18MCParsedAsmOperandENS6_14default_deleteIS8_EEEEEERj: 165| 3.40k| AsmToken Token, OperandVector &Operands, unsigned int &ErrorCode) { 166| 3.40k| return ParseInstruction(Info, Name, Token.getLoc(), Operands, ErrorCode); 167| 3.40k| } _ZN7llvm_ks17MCTargetAsmParser20equalIsAsmAssignmentEv: 214| 1.01k| virtual bool equalIsAsmAssignment() { return true; }; _ZN7llvm_ks17MCTargetAsmParser7isLabelERNS_8AsmTokenERb: 216| 16| virtual bool isLabel(AsmToken &Token, bool &valid) { valid = true; return true; }; _ZN7llvm_ks14MCRegisterInfo18InitMCRegisterInfoEPKNS_14MCRegisterDescEjjjPKNS_15MCRegisterClassEjPA2_KtjPS7_PKjPKcSE_SA_jPKNS0_17SubRegCoveredBitsESA_: 256| 430| const uint16_t *RET) { 257| 430| Desc = D; 258| 430| NumRegs = NR; 259| 430| RAReg = RA; 260| 430| PCReg = PC; 261| 430| Classes = C; 262| 430| DiffLists = DL; 263| 430| RegUnitMaskSequences = RUMS; 264| 430| RegStrings = Strings; 265| 430| RegClassStrings = ClassStrings; 266| 430| NumClasses = NC; 267| 430| RegUnitRoots = RURoots; 268| 430| NumRegUnits = NRU; 269| 430| SubRegIndices = SubIndices; 270| 430| NumSubRegIndices = NumIndices; 271| 430| SubRegIdxRanges = SubIdxRanges; 272| 430| RegEncodingTable = RET; 273| 430| } _ZN7llvm_ks14MCRegisterInfo22mapLLVMRegsToDwarfRegsEPKNS0_16DwarfLLVMRegPairEjb: 279| 860| bool isEH) { 280| 860| if (isEH) { ------------------ | Branch (280:9): [True: 430, False: 430] ------------------ 281| 430| EHL2DwarfRegs = Map; 282| 430| EHL2DwarfRegsSize = Size; 283| 430| } else { 284| 430| L2DwarfRegs = Map; 285| 430| L2DwarfRegsSize = Size; 286| 430| } 287| 860| } _ZN7llvm_ks14MCRegisterInfo22mapDwarfRegsToLLVMRegsEPKNS0_16DwarfLLVMRegPairEjb: 293| 860| bool isEH) { 294| 860| if (isEH) { ------------------ | Branch (294:9): [True: 430, False: 430] ------------------ 295| 430| EHDwarf2LRegs = Map; 296| 430| EHDwarf2LRegsSize = Size; 297| 430| } else { 298| 430| Dwarf2LRegs = Map; 299| 430| Dwarf2LRegsSize = Size; 300| 430| } 301| 860| } _ZNK7llvm_ks14MCRegisterInfo16getEncodingValueEj: 418| 2.29k| uint16_t getEncodingValue(unsigned RegNo) const { 419| 2.29k| assert(RegNo < NumRegs && ------------------ | Branch (419:5): [True: 2.29k, False: 0] | Branch (419:5): [True: 2.29k, Folded] | Branch (419:5): [True: 2.29k, False: 0] ------------------ 420| 2.29k| "Attempting to get encoding for invalid register number!"); 421| 2.29k| return RegEncodingTable[RegNo]; 422| 2.29k| } _ZN7llvm_ks17ilist_node_traitsINS_10MCFragmentEE13addNodeToListEPS1_: 40| 2.82k| void addNodeToList(MCFragment *) {} _ZN7llvm_ks17ilist_node_traitsINS_10MCFragmentEE18removeNodeFromListEPS1_: 41| 2.82k| void removeNodeFromList(MCFragment *) {} _ZNK7llvm_ks9MCSection10getVariantEv: 113| 140| SectionVariant getVariant() const { return Variant; } _ZN7llvm_ks9MCSection14getBeginSymbolEv: 115| 869| MCSymbol *getBeginSymbol() { return Begin; } _ZNK7llvm_ks9MCSection14getBeginSymbolEv: 116| 1| const MCSymbol *getBeginSymbol() const { 117| 1| return const_cast(this)->getBeginSymbol(); 118| 1| } _ZN7llvm_ks9MCSection14setBeginSymbolEPNS_8MCSymbolE: 119| 434| void setBeginSymbol(MCSymbol *Sym) { 120| 434| assert(!Begin); ------------------ | Branch (120:5): [True: 434, False: 0] ------------------ 121| 434| Begin = Sym; 122| 434| } _ZNK7llvm_ks9MCSection12getAlignmentEv: 126| 910| unsigned getAlignment() const { return Alignment; } _ZN7llvm_ks9MCSection12setAlignmentEj: 127| 34| void setAlignment(unsigned Value) { Alignment = Value; } _ZN7llvm_ks9MCSection10setOrdinalEj: 130| 187| void setOrdinal(unsigned Value) { Ordinal = Value; } _ZN7llvm_ks9MCSection14setLayoutOrderEj: 133| 187| void setLayoutOrder(unsigned Value) { LayoutOrder = Value; } _ZNK7llvm_ks9MCSection14isBundleLockedEv: 137| 1.34k| bool isBundleLocked() const { return BundleLockState != NotBundleLocked; } _ZN7llvm_ks9MCSection18setHasInstructionsEb: 147| 2.19k| void setHasInstructions(bool Value) { HasInstructions = Value; } _ZNK7llvm_ks9MCSection12isRegisteredEv: 149| 434| bool isRegistered() const { return IsRegistered; } _ZN7llvm_ks9MCSection15setIsRegisteredEb: 150| 434| void setIsRegistered(bool Value) { IsRegistered = Value; } _ZN7llvm_ks9MCSection15getFragmentListEv: 152| 37.3k| MCSection::FragmentListType &getFragmentList() { return Fragments; } _ZN7llvm_ks9MCSection16getSublistAccessEPNS_10MCFragmentE: 158| 2.50k| static FragmentListType MCSection::*getSublistAccess(MCFragment *) { 159| 2.50k| return &MCSection::Fragments; 160| 2.50k| } _ZN7llvm_ks9MCSection16getDummyFragmentEv: 163| 5.85k| MCDummyFragment &getDummyFragment() { return DummyFragment; } _ZNK7llvm_ks9MCSection5beginEv: 166| 178| MCSection::const_iterator begin() const { 167| 178| return const_cast(this)->begin(); 168| 178| } _ZNK7llvm_ks9MCSection3endEv: 171| 178| MCSection::const_iterator end() const { 172| 178| return const_cast(this)->end(); 173| 178| } _ZNK7llvm_ks12MCSectionELF14getSectionNameEv: 74| 1.01k| StringRef getSectionName() const { return SectionName; } _ZNK7llvm_ks12MCSectionELF8getGroupEv: 78| 637| const MCSymbolELF *getGroup() const { return Group; } _ZN7llvm_ks12MCSectionELFC2ENS_9StringRefEjjNS_11SectionKindEjPKNS_11MCSymbolELFEjPNS_8MCSymbolEPKS0_: 58| 18.6k| : MCSection(SV_ELF, K, Begin), SectionName(Section), Type(type), 59| 18.6k| Flags(flags), UniqueID(UniqueID), EntrySize(entrySize), Group(group), 60| 18.6k| Associated(Associated) { 61| 18.6k| if (Group) ------------------ | Branch (61:9): [True: 0, False: 18.6k] ------------------ 62| 0| Group->setIsSignature(); 63| 18.6k| } _ZNK7llvm_ks12MCSectionELF7getTypeEv: 75| 546| unsigned getType() const { return Type; } _ZNK7llvm_ks12MCSectionELF8getFlagsEv: 76| 6.17k| unsigned getFlags() const { return Flags; } _ZN7llvm_ks12MCSectionELF7classofEPKNS_9MCSectionE: 90| 140| static bool classof(const MCSection *S) { 91| 140| return S->getVariant() == SV_ELF; 92| 140| } _ZNK7llvm_ks14MCSectionMachO7getTypeEv: 58| 18| MachO::SectionType getType() const { 59| 18| return static_cast(TypeAndAttributes & 60| 18| MachO::SECTION_TYPE); 61| 18| } _ZNK7llvm_ks10MCStreamer14setSymResolverEPv: 201| 430| void setSymResolver(void *h) const { KsSymResolver = h; } _ZNK7llvm_ks10MCStreamer14getSymResolverEv: 202| 185| void *getSymResolver() const { return KsSymResolver; } _ZN7llvm_ks10MCStreamer17setTargetStreamerEPNS_16MCTargetStreamerE: 207| 430| void setTargetStreamer(MCTargetStreamer *TS) { 208| 430| TargetStreamer.reset(TS); 209| 430| } _ZNK7llvm_ks10MCStreamer10getContextEv: 215| 1.96k| MCContext &getContext() const { return Context; } _ZN7llvm_ks10MCStreamer17getTargetStreamerEv: 217| 15.0k| MCTargetStreamer *getTargetStreamer() { 218| 15.0k| return TargetStreamer.get(); 219| 15.0k| } _ZN7llvm_ks10MCStreamer19getNumWinFrameInfosEv: 226| 430| unsigned getNumWinFrameInfos() { return WinFrameInfos.size(); } _ZN7llvm_ks10MCStreamer12AddBlankLineEv: 275| 17.9k| virtual void AddBlankLine() {} _ZNK7llvm_ks10MCStreamer17getCurrentSectionEv: 283| 95.1k| MCSectionSubPair getCurrentSection() const { 284| 95.1k| if (!SectionStack.empty()) ------------------ | Branch (284:9): [True: 95.1k, False: 0] ------------------ 285| 95.1k| return SectionStack.back().first; 286| 0| return MCSectionSubPair(); 287| 95.1k| } _ZNK7llvm_ks10MCStreamer21getCurrentSectionOnlyEv: 288| 87.3k| MCSection *getCurrentSectionOnly() const { return getCurrentSection().first; } _ZN7llvm_ks10MCStreamer14EmitDataRegionENS_16MCDataRegionTypeE: 394| 10| virtual void EmitDataRegion(MCDataRegionType Kind) {} _ZNK7llvm_ks15MCSubtargetInfo14getFeatureBitsEv: 63| 79.2k| const FeatureBitset& getFeatureBits() const { 64| 79.2k| return FeatureBits; 65| 79.2k| } _ZNK7llvm_ks15MCSubtargetInfo16isCPUStringValidENS_9StringRefE: 112| 124| bool isCPUStringValid(StringRef CPU) const { 113| 124| auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU); 114| 124| return Found != ProcDesc.end() && StringRef(Found->Key) == CPU; ------------------ | Branch (114:12): [True: 91, False: 33] | Branch (114:39): [True: 25, False: 66] ------------------ 115| 124| } _ZN7llvm_ks15MCSubtargetInfoC2ERKS0_: 47| 2.67k| MCSubtargetInfo(const MCSubtargetInfo &) = default; _ZN7llvm_ks8MCSymbolC2ENS0_10SymbolKindEPKNS_14StringMapEntryIbEEb: 150| 11.7k| : IsTemporary(isTemporary), IsRedefinable(false), IsUsed(false), 151| 11.7k| IsRegistered(false), IsExternal(false), IsPrivateExtern(false), 152| 11.7k| Kind(Kind), IsUsedInReloc(false), SymbolContents(SymContentsUnset), 153| 11.7k| CommonAlignLog2(0), Flags(0) { 154| 11.7k| Offset = 0; 155| 11.7k| FragmentAndHasName.setInt(!!Name); 156| 11.7k| if (Name) ------------------ | Branch (156:9): [True: 11.7k, False: 0] ------------------ 157| 11.7k| getNameEntryPtr() = Name; 158| 11.7k| } _ZNK7llvm_ks8MCSymbol13getSectionPtrEb: 179| 1.27k| MCSection *getSectionPtr(bool SetUsed = true) const { 180| 1.27k| if (MCFragment *F = getFragment(SetUsed)) { ------------------ | Branch (180:21): [True: 1.27k, False: 0] ------------------ 181| 1.27k| assert(F != AbsolutePseudoFragment); ------------------ | Branch (181:7): [True: 1.27k, False: 0] ------------------ 182| 1.27k| return F->getParent(); 183| 1.27k| } 184| 0| return nullptr; 185| 1.27k| } _ZN7llvm_ks8MCSymbol15getNameEntryPtrEv: 188| 11.8k| const StringMapEntry *&getNameEntryPtr() { 189| 11.8k| assert(FragmentAndHasName.getInt() && "Name is required"); ------------------ | Branch (189:5): [True: 11.8k, False: 0] | Branch (189:5): [True: 11.8k, Folded] | Branch (189:5): [True: 11.8k, False: 0] ------------------ 190| 11.8k| NameEntryStorageTy *Name = reinterpret_cast(this); 191| 11.8k| return (*(Name - 1)).NameEntry; 192| 11.8k| } _ZNK7llvm_ks8MCSymbol15getNameEntryPtrEv: 193| 134| const StringMapEntry *&getNameEntryPtr() const { 194| 134| return const_cast(this)->getNameEntryPtr(); 195| 134| } _ZNK7llvm_ks8MCSymbol7getNameEv: 199| 134| StringRef getName() const { 200| 134| if (!FragmentAndHasName.getInt()) ------------------ | Branch (200:9): [True: 0, False: 134] ------------------ 201| 0| return StringRef(); 202| | 203| 134| return getNameEntryPtr()->first(); 204| 134| } _ZNK7llvm_ks8MCSymbol12isRegisteredEv: 206| 8.57k| bool isRegistered() const { return IsRegistered; } _ZNK7llvm_ks8MCSymbol15setIsRegisteredEb: 207| 6.21k| void setIsRegistered(bool Value) const { IsRegistered = Value; } _ZNK7llvm_ks8MCSymbol14setUsedInRelocEv: 209| 23| void setUsedInReloc() const { IsUsedInReloc = true; } _ZNK7llvm_ks8MCSymbol13isUsedInRelocEv: 210| 122| bool isUsedInReloc() const { return IsUsedInReloc; } _ZNK7llvm_ks8MCSymbol6isUsedEv: 219| 97| bool isUsed() const { return IsUsed; } _ZN7llvm_ks8MCSymbol14setRedefinableEb: 225| 203| void setRedefinable(bool Value) { IsRedefinable = Value; } _ZN7llvm_ks8MCSymbol18redefineIfPossibleEv: 227| 16| void redefineIfPossible() { 228| 16| if (IsRedefinable) { ------------------ | Branch (228:9): [True: 0, False: 16] ------------------ 229| 0| if (SymbolContents == SymContentsVariable) { ------------------ | Branch (229:11): [True: 0, False: 0] ------------------ 230| 0| Value = nullptr; 231| 0| SymbolContents = SymContentsUnset; 232| 0| } 233| 0| setUndefined(); 234| 0| IsRedefinable = false; 235| 0| } 236| 16| } _ZNK7llvm_ks8MCSymbol9isDefinedEb: 245| 13.6k| bool isDefined(bool SetUsed = true) const { 246| 13.6k| return getFragment(SetUsed) != nullptr; 247| 13.6k| } _ZNK7llvm_ks8MCSymbol11isInSectionEb: 251| 1.81k| bool isInSection(bool SetUsed = true) const { 252| 1.81k| return isDefined(SetUsed) && !isAbsolute(SetUsed); ------------------ | Branch (252:12): [True: 1.37k, False: 434] | Branch (252:34): [True: 1.37k, False: 6] ------------------ 253| 1.81k| } _ZNK7llvm_ks8MCSymbol11isUndefinedEb: 256| 9.06k| bool isUndefined(bool SetUsed = true) const { return !isDefined(SetUsed); } _ZNK7llvm_ks8MCSymbol10isAbsoluteEb: 259| 1.37k| bool isAbsolute(bool SetUsed = true) const { 260| 1.37k| return getFragment(SetUsed) == AbsolutePseudoFragment; 261| 1.37k| } _ZNK7llvm_ks8MCSymbol10getSectionEb: 264| 1.27k| MCSection &getSection(bool SetUsed = true) const { 265| 1.27k| assert(isInSection(SetUsed) && "Invalid accessor!"); ------------------ | Branch (265:5): [True: 1.27k, False: 0] | Branch (265:5): [True: 1.27k, Folded] | Branch (265:5): [True: 1.27k, False: 0] ------------------ 266| 1.27k| return *getSectionPtr(SetUsed); 267| 1.27k| } _ZNK7llvm_ks8MCSymbol11setFragmentEPNS_10MCFragmentE: 270| 6.84k| void setFragment(MCFragment *F) const { 271| 6.84k| assert(!isVariable() && "Cannot set fragment of variable"); ------------------ | Branch (271:5): [True: 6.84k, False: 0] | Branch (271:5): [True: 6.84k, Folded] | Branch (271:5): [True: 6.84k, False: 0] ------------------ 272| 6.84k| FragmentAndHasName.setPointer(F); 273| 6.84k| } _ZN7llvm_ks8MCSymbol12setUndefinedEv: 276| 203| void setUndefined() { FragmentAndHasName.setPointer(nullptr); } _ZNK7llvm_ks8MCSymbol5isELFEv: 278| 9.10k| bool isELF() const { return Kind == SymbolKindELF; } _ZNK7llvm_ks8MCSymbol10isVariableEv: 289| 62.9k| bool isVariable() const { 290| 62.9k| return SymbolContents == SymContentsVariable; 291| 62.9k| } _ZNK7llvm_ks8MCSymbol16getVariableValueEb: 294| 392| const MCExpr *getVariableValue(bool SetUsed = true) const { 295| 392| assert(isVariable() && "Invalid accessor!"); ------------------ | Branch (295:5): [True: 392, False: 0] | Branch (295:5): [True: 392, Folded] | Branch (295:5): [True: 392, False: 0] ------------------ 296| 392| IsUsed |= SetUsed; 297| 392| return Value; 298| 392| } _ZNK7llvm_ks8MCSymbol9getOffsetEv: 314| 1.36k| uint64_t getOffset() const { 315| 1.36k| assert((SymbolContents == SymContentsUnset || ------------------ | Branch (315:5): [True: 20, False: 1.34k] | Branch (315:5): [True: 1.34k, False: 0] | Branch (315:5): [True: 1.36k, Folded] | Branch (315:5): [True: 1.36k, False: 0] ------------------ 316| 1.36k| SymbolContents == SymContentsOffset) && 317| 1.36k| "Cannot get offset for a common/variable symbol"); 318| 1.36k| return Offset; 319| 1.36k| } _ZN7llvm_ks8MCSymbol9setOffsetEm: 320| 991| void setOffset(uint64_t Value) { 321| 991| assert((SymbolContents == SymContentsUnset || ------------------ | Branch (321:5): [True: 991, False: 0] | Branch (321:5): [True: 0, False: 0] | Branch (321:5): [True: 991, Folded] | Branch (321:5): [True: 991, False: 0] ------------------ 322| 991| SymbolContents == SymContentsOffset) && 323| 991| "Cannot set offset for a common/variable symbol"); 324| 991| Offset = Value; 325| 991| SymbolContents = SymContentsOffset; 326| 991| } _ZN7llvm_ks8MCSymbol9setCommonEmj: 338| 10| void setCommon(uint64_t Size, unsigned Align) { 339| 10| assert(getOffset() == 0); ------------------ | Branch (339:5): [True: 10, False: 0] ------------------ 340| 10| CommonSize = Size; 341| 10| SymbolContents = SymContentsCommon; 342| | 343| 10| assert((!Align || isPowerOf2_32(Align)) && ------------------ | Branch (343:5): [True: 0, False: 10] | Branch (343:5): [True: 10, False: 0] | Branch (343:5): [True: 10, Folded] | Branch (343:5): [True: 10, False: 0] ------------------ 344| 10| "Alignment must be a power of 2"); 345| 10| unsigned Log2Align = Log2_32(Align) + 1; 346| 10| assert(Log2Align < (1U << NumCommonAlignmentBits) && ------------------ | Branch (346:5): [True: 10, False: 0] | Branch (346:5): [True: 10, Folded] | Branch (346:5): [True: 10, False: 0] ------------------ 347| 10| "Out of range alignment"); 348| 10| CommonAlignLog2 = Log2Align; 349| 10| } _ZNK7llvm_ks8MCSymbol18getCommonAlignmentEv: 352| 579| unsigned getCommonAlignment() const { 353| 579| assert(isCommon() && "Not a 'common' symbol!"); ------------------ | Branch (353:5): [True: 579, False: 0] | Branch (353:5): [True: 579, Folded] | Branch (353:5): [True: 579, False: 0] ------------------ 354| 579| return CommonAlignLog2 ? (1U << (CommonAlignLog2 - 1)) : 0; ------------------ | Branch (354:12): [True: 579, False: 0] ------------------ 355| 579| } _ZN7llvm_ks8MCSymbol13declareCommonEmj: 362| 589| bool declareCommon(uint64_t Size, unsigned Align) { 363| 589| assert(isCommon() || getOffset() == 0); ------------------ | Branch (363:5): [True: 579, False: 10] | Branch (363:5): [True: 10, False: 0] | Branch (363:5): [True: 589, False: 0] ------------------ 364| 589| if(isCommon()) { ------------------ | Branch (364:8): [True: 579, False: 10] ------------------ 365| 579| if(CommonSize != Size || getCommonAlignment() != Align) ------------------ | Branch (365:10): [True: 0, False: 579] | Branch (365:32): [True: 0, False: 579] ------------------ 366| 0| return true; 367| 579| } else 368| 10| setCommon(Size, Align); 369| 589| return false; 370| 589| } _ZNK7llvm_ks8MCSymbol8isCommonEv: 373| 1.75k| bool isCommon() const { 374| 1.75k| return SymbolContents == SymContentsCommon; 375| 1.75k| } _ZNK7llvm_ks8MCSymbol11getFragmentEb: 377| 24.8k| MCFragment *getFragment(bool SetUsed = true) const { 378| 24.8k| MCFragment *Fragment = FragmentAndHasName.getPointer(); 379| 24.8k| if (Fragment || !isVariable()) ------------------ | Branch (379:9): [True: 11.0k, False: 13.8k] | Branch (379:21): [True: 13.7k, False: 45] ------------------ 380| 24.8k| return Fragment; 381| 45| Fragment = getVariableValue(SetUsed)->findAssociatedFragment(); 382| 45| FragmentAndHasName.setPointer(Fragment); 383| 45| return Fragment; 384| 24.8k| } _ZNK7llvm_ks8MCSymbol10isExternalEv: 386| 145| bool isExternal() const { return IsExternal; } _ZNK7llvm_ks8MCSymbol11setExternalEb: 387| 133| void setExternal(bool Value) const { IsExternal = Value; } _ZNK7llvm_ks8MCSymbol8getFlagsEv: 400| 5.94k| uint32_t getFlags() const { return Flags; } _ZNK7llvm_ks8MCSymbol8setFlagsEj: 403| 1.28k| void setFlags(uint32_t Value) const { 404| 1.28k| assert(Value < (1U << NumFlagsBits) && "Out of range flags"); ------------------ | Branch (404:5): [True: 1.28k, False: 0] | Branch (404:5): [True: 1.28k, Folded] | Branch (404:5): [True: 1.28k, False: 0] ------------------ 405| 1.28k| Flags = Value; 406| 1.28k| } _ZN7llvm_ks11MCSymbolELFC2EPKNS_14StringMapEntryIbEEb: 22| 11.7k| : MCSymbol(SymbolKindELF, Name, isTemporary) {} _ZN7llvm_ks11MCSymbolELF7classofEPKNS_8MCSymbolE: 47| 9.10k| static bool classof(const MCSymbol *S) { return S->isELF(); } _ZN7llvm_ks11MCSymbolELF7setSizeEPKNS_6MCExprE: 23| 589| void setSize(const MCExpr *SS) { SymbolSize = SS; } ks.cpp:_ZL28InitMCTargetOptionsFromFlagsv: 34| 430|static inline MCTargetOptions InitMCTargetOptionsFromFlags() { 35| 430| MCTargetOptions Options; 36| 430| Options.MCRelaxAll = RelaxAll; 37| 430| Options.DwarfVersion = DwarfVersion; 38| 430| Options.ABIName = ABIName; 39| 430| Options.MCFatalWarnings = FatalWarnings; 40| 430| Options.MCNoWarn = NoWarn; 41| 430| return Options; 42| 430|} _ZNK7llvm_ks7MCValue11getConstantEv: 46| 26.5k| int64_t getConstant() const { return Cst; } _ZNK7llvm_ks7MCValue7getSymAEv: 47| 10.4k| const MCSymbolRefExpr *getSymA() const { return SymA; } _ZNK7llvm_ks7MCValue7getSymBEv: 48| 6.15k| const MCSymbolRefExpr *getSymB() const { return SymB; } _ZNK7llvm_ks7MCValue10isAbsoluteEv: 52| 22.4k| bool isAbsolute() const { return !SymA && !SymB; } ------------------ | Branch (52:36): [True: 4.82k, False: 17.6k] | Branch (52:45): [True: 4.65k, False: 168] ------------------ _ZN7llvm_ks7MCValue3getEPKNS_15MCSymbolRefExprES3_lj: 64| 21.4k| int64_t Val = 0, uint32_t RefKind = 0) { 65| 21.4k| MCValue R; 66| 21.4k| R.Cst = Val; 67| 21.4k| R.SymA = SymA; 68| 21.4k| R.SymB = SymB; 69| 21.4k| R.RefKind = RefKind; 70| 21.4k| return R; 71| 21.4k| } _ZN7llvm_ks7MCValue3getEl: 73| 5.01k| static MCValue get(int64_t Val) { 74| 5.01k| MCValue R; 75| 5.01k| R.Cst = Val; 76| 5.01k| R.SymA = nullptr; 77| 5.01k| R.SymB = nullptr; 78| 5.01k| R.RefKind = 0; 79| 5.01k| return R; 80| 5.01k| } _ZN7llvm_ks11SectionKind3getENS0_4KindE: 161| 18.8k| static SectionKind get(Kind K) { 162| 18.8k| SectionKind Res; 163| 18.8k| Res.K = K; 164| 18.8k| return Res; 165| 18.8k| } _ZN7llvm_ks11SectionKind7getTextEv: 169| 430| static SectionKind getText() { return get(Text); } _ZN7llvm_ks11SectionKind11getReadOnlyEv: 170| 18.2k| static SectionKind getReadOnly() { return get(ReadOnly); } _ZN7llvm_ks11SectionKind7getDataEv: 189| 143| static SectionKind getData() { return get(Data); } _ZNK7llvm_ks18StringTableBuilder11isFinalizedEv: 64| 378| bool isFinalized() const { 65| 378| return !StringTable.empty(); 66| 378| } _ZN7llvm_ks13FeatureBitsetC2Ev: 37| 7.13k| FeatureBitset() : bitset() {} _ZN7llvm_ks13FeatureBitsetC2ERKNSt3__16bitsetILm128EEE: 39| 264| FeatureBitset(const bitset& B) : bitset(B) {} _ZN7llvm_ks13FeatureBitsetC2ESt16initializer_listIjE: 41| 1.44k| FeatureBitset(std::initializer_list Init) : bitset() { 42| 1.44k| for (auto I : Init) ------------------ | Branch (42:17): [True: 3.58k, False: 1.44k] ------------------ 43| 3.58k| set(I); 44| 1.44k| } _ZNK7llvm_ks18SubtargetFeatureKVltENS_9StringRefE: 59| 32.7k| bool operator<(StringRef S) const { 60| 32.7k| return StringRef(Key) < S; 61| 32.7k| } _ZNK7llvm_ks18SubtargetFeatureKVltERKS0_: 64| 533k| bool operator<(const SubtargetFeatureKV &Other) const { 65| 533k| return StringRef(Key) < StringRef(Other.Key); 66| 533k| } _ZN7llvm_ks7alignOfINS_12MCSectionELFEEEjv: 106| 3.44k|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks7alignOfINS_14MCSectionMachOEEEjv: 106| 12|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks7alignOfINS_15MCSubtargetInfoEEEjv: 106| 320|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks7alignOfINS_14StringMapEntryIPNS_8MCSymbolEEEEEjv: 106| 1.94k|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks7alignOfINS_14StringMapEntryIbEEEEjv: 106| 11.7k|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks7alignOfINS_14StringMapEntryIjEEEEjv: 106| 5.89k|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks7alignOfINS_14StringMapEntryIPNS_14MCSectionMachOEEEEEjv: 106| 4|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks7alignOfINS_14StringMapEntryINSt3__14pairIPNS_20MCAsmParserExtensionEPFbS5_NS_9StringRefENS_5SMLocEEEEEEEEjv: 106| 28.3k|inline unsigned alignOf() { return AlignOf::Alignment; } AsmParser.cpp:_ZN7llvm_ks7alignOfINS_14StringMapEntryIN12_GLOBAL__N_19AsmParser13DirectiveKindEEEEEjv: 106| 52.4k|inline unsigned alignOf() { return AlignOf::Alignment; } AsmParser.cpp:_ZN7llvm_ks7alignOfINS_14StringMapEntryIN12_GLOBAL__N_110MCAsmMacroEEEEEjv: 106| 15|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks7alignOfINS_8MCSymbol18NameEntryStorageTyEEEjv: 106| 11.7k|inline unsigned alignOf() { return AlignOf::Alignment; } _ZN7llvm_ks15MallocAllocator8AllocateEmm: 94| 88.9k| size_t /*Alignment*/) { 95| 88.9k| return malloc(Size); 96| 88.9k| } _ZN7llvm_ks15MallocAllocator10DeallocateEPKvm: 101| 88.9k| void Deallocate(const void *Ptr, size_t /*Size*/) { 102| 88.9k| free(const_cast(Ptr)); 103| 88.9k| } _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EE8AllocateEmm: 209| 88.7k| Allocate(size_t Size, size_t Alignment) { 210| 88.7k| assert(Alignment > 0 && "0-byte alignnment is not allowed. Use 1 instead."); ------------------ | Branch (210:5): [True: 88.7k, False: 0] | Branch (210:5): [True: 88.7k, Folded] | Branch (210:5): [True: 88.7k, False: 0] ------------------ 211| | 212| | // Keep track of how many bytes we've allocated. 213| 88.7k| BytesAllocated += Size; 214| | 215| 88.7k| size_t Adjustment = alignmentAdjustment(CurPtr, Alignment); 216| 88.7k| assert(Adjustment + Size >= Size && "Adjustment + Size must not overflow"); ------------------ | Branch (216:5): [True: 88.7k, False: 0] | Branch (216:5): [True: 88.7k, Folded] | Branch (216:5): [True: 88.7k, False: 0] ------------------ 217| | 218| | // Check if we have enough space. 219| 88.7k| if (Adjustment + Size <= size_t(End - CurPtr)) { ------------------ | Branch (219:9): [True: 86.6k, False: 2.12k] ------------------ 220| 86.6k| char *AlignedPtr = CurPtr + Adjustment; 221| 86.6k| CurPtr = AlignedPtr + Size; 222| | // Update the allocation point of this memory block in MemorySanitizer. 223| | // Without this, MemorySanitizer messages for values originated from here 224| | // will point to the allocation of the entire slab. 225| 86.6k| __msan_allocated_memory(AlignedPtr, Size); 226| | // Similarly, tell ASan about this space. 227| 86.6k| __asan_unpoison_memory_region(AlignedPtr, Size); 228| 86.6k| return AlignedPtr; 229| 86.6k| } 230| | 231| | // If Size is really big, allocate a separate slab for it. 232| 2.12k| size_t PaddedSize = Size + Alignment - 1; 233| 2.12k| if (PaddedSize > SizeThreshold) { ------------------ | Branch (233:9): [True: 10, False: 2.11k] ------------------ 234| 10| void *NewSlab = Allocator.Allocate(PaddedSize, 0); 235| | // We own the new slab and don't want anyone reading anyting other than 236| | // pieces returned from this method. So poison the whole slab. 237| 10| __asan_poison_memory_region(NewSlab, PaddedSize); 238| 10| CustomSizedSlabs.push_back(std::make_pair(NewSlab, PaddedSize)); 239| | 240| 10| uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); 241| 10| assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); ------------------ | Branch (241:7): [True: 10, False: 0] ------------------ 242| 10| char *AlignedPtr = (char*)AlignedAddr; 243| 10| __msan_allocated_memory(AlignedPtr, Size); 244| 10| __asan_unpoison_memory_region(AlignedPtr, Size); 245| 10| return AlignedPtr; 246| 10| } 247| | 248| | // Otherwise, start a new slab and try again. 249| 2.11k| StartNewSlab(); 250| 2.11k| uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); 251| 2.11k| assert(AlignedAddr + Size <= (uintptr_t)End && ------------------ | Branch (251:5): [True: 2.11k, False: 0] | Branch (251:5): [True: 2.11k, Folded] | Branch (251:5): [True: 2.11k, False: 0] ------------------ 252| 2.11k| "Unable to allocate memory!"); 253| 2.11k| char *AlignedPtr = (char*)AlignedAddr; 254| 2.11k| CurPtr = AlignedPtr + Size; 255| 2.11k| __msan_allocated_memory(AlignedPtr, Size); 256| 2.11k| __asan_unpoison_memory_region(AlignedPtr, Size); 257| 2.11k| return AlignedPtr; 258| 2.11k| } _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EE12StartNewSlabEv: 319| 2.11k| void StartNewSlab() { 320| 2.11k| size_t AllocatedSlabSize = computeSlabSize(Slabs.size()); 321| | 322| 2.11k| void *NewSlab = Allocator.Allocate(AllocatedSlabSize, 0); 323| | // We own the new slab and don't want anyone reading anything other than 324| | // pieces returned from this method. So poison the whole slab. 325| 2.11k| __asan_poison_memory_region(NewSlab, AllocatedSlabSize); 326| | 327| 2.11k| Slabs.push_back(NewSlab); 328| 2.11k| CurPtr = (char *)(NewSlab); 329| 2.11k| End = ((char *)NewSlab) + AllocatedSlabSize; 330| 2.11k| } _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EE15computeSlabSizeEj: 309| 6.11k| static size_t computeSlabSize(unsigned SlabIdx) { 310| | // Scale the actual allocated slab size based on the number of slabs 311| | // allocated. Every 128 slabs allocated, we double the allocated size to 312| | // reduce allocation frequency, but saturate at multiplying the slab size by 313| | // 2^30. 314| 6.11k| return SlabSize * ((size_t)1 << std::min(30, SlabIdx / 128)); 315| 6.11k| } _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEC2Ev: 145| 2.58k| : CurPtr(nullptr), End(nullptr), BytesAllocated(0), Allocator() {} _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_13MCSectionCOFFEEC2Ev: 367| 430| SpecificBumpPtrAllocator() : Allocator() {} _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_12MCSectionELFEEC2Ev: 367| 430| SpecificBumpPtrAllocator() : Allocator() {} _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_14MCSectionMachOEEC2Ev: 367| 430| SpecificBumpPtrAllocator() : Allocator() {} _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_15MCSubtargetInfoEEC2Ev: 367| 430| SpecificBumpPtrAllocator() : Allocator() {} _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EED2Ev: 164| 2.58k| ~BumpPtrAllocatorImpl() { 165| 2.58k| DeallocateSlabs(Slabs.begin(), Slabs.end()); 166| 2.58k| DeallocateCustomSizedSlabs(); 167| 2.58k| } _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EE15DeallocateSlabsEPPvS4_: 334| 3.95k| SmallVectorImpl::iterator E) { 335| 6.06k| for (; I != E; ++I) { ------------------ | Branch (335:12): [True: 2.11k, False: 3.95k] ------------------ 336| 2.11k| size_t AllocatedSlabSize = 337| 2.11k| computeSlabSize(std::distance(Slabs.begin(), I)); 338| 2.11k| Allocator.Deallocate(*I, AllocatedSlabSize); 339| 2.11k| } 340| 3.95k| } _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EE26DeallocateCustomSizedSlabsEv: 343| 6.45k| void DeallocateCustomSizedSlabs() { 344| 6.45k| for (auto &PtrAndSize : CustomSizedSlabs) { ------------------ | Branch (344:27): [True: 10, False: 6.45k] ------------------ 345| 10| void *Ptr = PtrAndSize.first; 346| 10| size_t Size = PtrAndSize.second; 347| 10| Allocator.Deallocate(Ptr, Size); 348| 10| } 349| 6.45k| } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_13MCSectionCOFFEED2Ev: 370| 430| ~SpecificBumpPtrAllocator() { DestroyAll(); } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_12MCSectionELFEED2Ev: 370| 430| ~SpecificBumpPtrAllocator() { DestroyAll(); } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_14MCSectionMachOEED2Ev: 370| 430| ~SpecificBumpPtrAllocator() { DestroyAll(); } _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EE10DeallocateEPKvm: 263| 13.6k| void Deallocate(const void *Ptr, size_t Size) { 264| 13.6k| __asan_poison_memory_region(Ptr, Size); 265| 13.6k| } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_15MCSubtargetInfoEED2Ev: 370| 430| ~SpecificBumpPtrAllocator() { DestroyAll(); } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_13MCSectionCOFFEE10DestroyAllEv: 380| 860| void DestroyAll() { 381| 860| auto DestroyElements = [](char *Begin, char *End) { 382| 860| assert(Begin == (char*)alignAddr(Begin, alignOf())); 383| 860| for (char *Ptr = Begin; Ptr + sizeof(T) <= End; Ptr += sizeof(T)) 384| 860| reinterpret_cast(Ptr)->~T(); 385| 860| }; 386| | 387| 860| for (auto I = Allocator.Slabs.begin(), E = Allocator.Slabs.end(); I != E; ------------------ | Branch (387:71): [True: 0, False: 860] ------------------ 388| 860| ++I) { 389| 0| size_t AllocatedSlabSize = BumpPtrAllocator::computeSlabSize( 390| 0| std::distance(Allocator.Slabs.begin(), I)); 391| 0| char *Begin = (char*)alignAddr(*I, alignOf()); 392| 0| char *End = *I == Allocator.Slabs.back() ? Allocator.CurPtr ------------------ | Branch (392:19): [True: 0, False: 0] ------------------ 393| 0| : (char *)*I + AllocatedSlabSize; 394| | 395| 0| DestroyElements(Begin, End); 396| 0| } 397| | 398| 860| for (auto &PtrAndSize : Allocator.CustomSizedSlabs) { ------------------ | Branch (398:27): [True: 0, False: 860] ------------------ 399| 0| void *Ptr = PtrAndSize.first; 400| 0| size_t Size = PtrAndSize.second; 401| 0| DestroyElements((char*)alignAddr(Ptr, alignOf()), (char *)Ptr + Size); 402| 0| } 403| | 404| 860| Allocator.Reset(); 405| 860| } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_12MCSectionELFEE10DestroyAllEv: 380| 860| void DestroyAll() { 381| 860| auto DestroyElements = [](char *Begin, char *End) { 382| 860| assert(Begin == (char*)alignAddr(Begin, alignOf())); 383| 860| for (char *Ptr = Begin; Ptr + sizeof(T) <= End; Ptr += sizeof(T)) 384| 860| reinterpret_cast(Ptr)->~T(); 385| 860| }; 386| | 387| 2.58k| for (auto I = Allocator.Slabs.begin(), E = Allocator.Slabs.end(); I != E; ------------------ | Branch (387:71): [True: 1.72k, False: 860] ------------------ 388| 1.72k| ++I) { 389| 1.72k| size_t AllocatedSlabSize = BumpPtrAllocator::computeSlabSize( 390| 1.72k| std::distance(Allocator.Slabs.begin(), I)); 391| 1.72k| char *Begin = (char*)alignAddr(*I, alignOf()); 392| 1.72k| char *End = *I == Allocator.Slabs.back() ? Allocator.CurPtr ------------------ | Branch (392:19): [True: 860, False: 860] ------------------ 393| 1.72k| : (char *)*I + AllocatedSlabSize; 394| | 395| 1.72k| DestroyElements(Begin, End); 396| 1.72k| } 397| | 398| 860| for (auto &PtrAndSize : Allocator.CustomSizedSlabs) { ------------------ | Branch (398:27): [True: 0, False: 860] ------------------ 399| 0| void *Ptr = PtrAndSize.first; 400| 0| size_t Size = PtrAndSize.second; 401| 0| DestroyElements((char*)alignAddr(Ptr, alignOf()), (char *)Ptr + Size); 402| 0| } 403| | 404| 860| Allocator.Reset(); 405| 860| } _ZZN7llvm_ks24SpecificBumpPtrAllocatorINS_12MCSectionELFEE10DestroyAllEvENKUlPcS3_E_clES3_S3_: 381| 1.72k| auto DestroyElements = [](char *Begin, char *End) { 382| 1.72k| assert(Begin == (char*)alignAddr(Begin, alignOf())); ------------------ | Branch (382:7): [True: 1.72k, False: 0] ------------------ 383| 20.4k| for (char *Ptr = Begin; Ptr + sizeof(T) <= End; Ptr += sizeof(T)) ------------------ | Branch (383:31): [True: 18.6k, False: 1.72k] ------------------ 384| 18.6k| reinterpret_cast(Ptr)->~T(); 385| 1.72k| }; _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_14MCSectionMachOEE10DestroyAllEv: 380| 860| void DestroyAll() { 381| 860| auto DestroyElements = [](char *Begin, char *End) { 382| 860| assert(Begin == (char*)alignAddr(Begin, alignOf())); 383| 860| for (char *Ptr = Begin; Ptr + sizeof(T) <= End; Ptr += sizeof(T)) 384| 860| reinterpret_cast(Ptr)->~T(); 385| 860| }; 386| | 387| 866| for (auto I = Allocator.Slabs.begin(), E = Allocator.Slabs.end(); I != E; ------------------ | Branch (387:71): [True: 6, False: 860] ------------------ 388| 860| ++I) { 389| 6| size_t AllocatedSlabSize = BumpPtrAllocator::computeSlabSize( 390| 6| std::distance(Allocator.Slabs.begin(), I)); 391| 6| char *Begin = (char*)alignAddr(*I, alignOf()); 392| 6| char *End = *I == Allocator.Slabs.back() ? Allocator.CurPtr ------------------ | Branch (392:19): [True: 6, False: 0] ------------------ 393| 6| : (char *)*I + AllocatedSlabSize; 394| | 395| 6| DestroyElements(Begin, End); 396| 6| } 397| | 398| 860| for (auto &PtrAndSize : Allocator.CustomSizedSlabs) { ------------------ | Branch (398:27): [True: 0, False: 860] ------------------ 399| 0| void *Ptr = PtrAndSize.first; 400| 0| size_t Size = PtrAndSize.second; 401| 0| DestroyElements((char*)alignAddr(Ptr, alignOf()), (char *)Ptr + Size); 402| 0| } 403| | 404| 860| Allocator.Reset(); 405| 860| } _ZZN7llvm_ks24SpecificBumpPtrAllocatorINS_14MCSectionMachOEE10DestroyAllEvENKUlPcS3_E_clES3_S3_: 381| 6| auto DestroyElements = [](char *Begin, char *End) { 382| 6| assert(Begin == (char*)alignAddr(Begin, alignOf())); ------------------ | Branch (382:7): [True: 6, False: 0] ------------------ 383| 10| for (char *Ptr = Begin; Ptr + sizeof(T) <= End; Ptr += sizeof(T)) ------------------ | Branch (383:31): [True: 4, False: 6] ------------------ 384| 4| reinterpret_cast(Ptr)->~T(); 385| 6| }; _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_15MCSubtargetInfoEE10DestroyAllEv: 380| 860| void DestroyAll() { 381| 860| auto DestroyElements = [](char *Begin, char *End) { 382| 860| assert(Begin == (char*)alignAddr(Begin, alignOf())); 383| 860| for (char *Ptr = Begin; Ptr + sizeof(T) <= End; Ptr += sizeof(T)) 384| 860| reinterpret_cast(Ptr)->~T(); 385| 860| }; 386| | 387| 1.02k| for (auto I = Allocator.Slabs.begin(), E = Allocator.Slabs.end(); I != E; ------------------ | Branch (387:71): [True: 160, False: 860] ------------------ 388| 860| ++I) { 389| 160| size_t AllocatedSlabSize = BumpPtrAllocator::computeSlabSize( 390| 160| std::distance(Allocator.Slabs.begin(), I)); 391| 160| char *Begin = (char*)alignAddr(*I, alignOf()); 392| 160| char *End = *I == Allocator.Slabs.back() ? Allocator.CurPtr ------------------ | Branch (392:19): [True: 78, False: 82] ------------------ 393| 160| : (char *)*I + AllocatedSlabSize; 394| | 395| 160| DestroyElements(Begin, End); 396| 160| } 397| | 398| 860| for (auto &PtrAndSize : Allocator.CustomSizedSlabs) { ------------------ | Branch (398:27): [True: 0, False: 860] ------------------ 399| 0| void *Ptr = PtrAndSize.first; 400| 0| size_t Size = PtrAndSize.second; 401| 0| DestroyElements((char*)alignAddr(Ptr, alignOf()), (char *)Ptr + Size); 402| 0| } 403| | 404| 860| Allocator.Reset(); 405| 860| } _ZZN7llvm_ks24SpecificBumpPtrAllocatorINS_15MCSubtargetInfoEE10DestroyAllEvENKUlPcS3_E_clES3_S3_: 381| 160| auto DestroyElements = [](char *Begin, char *End) { 382| 160| assert(Begin == (char*)alignAddr(Begin, alignOf())); ------------------ | Branch (382:7): [True: 160, False: 0] ------------------ 383| 2.83k| for (char *Ptr = Begin; Ptr + sizeof(T) <= End; Ptr += sizeof(T)) ------------------ | Branch (383:31): [True: 2.67k, False: 160] ------------------ 384| 2.67k| reinterpret_cast(Ptr)->~T(); 385| 160| }; _ZN7llvm_ks20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EE5ResetEv: 189| 3.87k| void Reset() { 190| | // Deallocate all but the first slab, and deallocate all custom-sized slabs. 191| 3.87k| DeallocateCustomSizedSlabs(); 192| 3.87k| CustomSizedSlabs.clear(); 193| | 194| 3.87k| if (Slabs.empty()) ------------------ | Branch (194:9): [True: 2.49k, False: 1.37k] ------------------ 195| 2.49k| return; 196| | 197| | // Reset the state. 198| 1.37k| BytesAllocated = 0; 199| 1.37k| CurPtr = (char *)Slabs.front(); 200| 1.37k| End = CurPtr + SlabSize; 201| | 202| 1.37k| __asan_poison_memory_region(*Slabs.begin(), computeSlabSize(0)); 203| 1.37k| DeallocateSlabs(std::next(Slabs.begin()), Slabs.end()); 204| 1.37k| Slabs.erase(std::next(Slabs.begin()), Slabs.end()); 205| 1.37k| } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_14MCSectionMachOEE8AllocateEm: 408| 4| T *Allocate(size_t num = 1) { return Allocator.Allocate(num); } _ZN7llvm_ks13AllocatorBaseINS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE8AllocateINS_14MCSectionMachOEEEPT_m: 76| 4| template T *Allocate(size_t Num = 1) { 77| 4| return static_cast(Allocate(Num * sizeof(T), AlignOf::Alignment)); 78| 4| } _ZN7llvm_ks13AllocatorBaseINS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE8AllocateEmm: 46| 21.3k| void *Allocate(size_t Size, size_t Alignment) { 47| 21.3k|#ifdef __clang__ 48| 21.3k| static_assert(static_cast( 49| 21.3k| &AllocatorBase::Allocate) != 50| 21.3k| static_cast( 51| 21.3k| &DerivedT::Allocate), 52| 21.3k| "Class derives from AllocatorBase without implementing the " 53| 21.3k| "core Allocate(size_t, size_t) overload!"); 54| 21.3k|#endif 55| 21.3k| return static_cast(this)->Allocate(Size, Alignment); 56| 21.3k| } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_12MCSectionELFEE8AllocateEm: 408| 18.6k| T *Allocate(size_t num = 1) { return Allocator.Allocate(num); } _ZN7llvm_ks13AllocatorBaseINS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE8AllocateINS_12MCSectionELFEEEPT_m: 76| 18.6k| template T *Allocate(size_t Num = 1) { 77| 18.6k| return static_cast(Allocate(Num * sizeof(T), AlignOf::Alignment)); 78| 18.6k| } _ZN7llvm_ks24SpecificBumpPtrAllocatorINS_15MCSubtargetInfoEE8AllocateEm: 408| 2.67k| T *Allocate(size_t num = 1) { return Allocator.Allocate(num); } _ZN7llvm_ks13AllocatorBaseINS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEEE8AllocateINS_15MCSubtargetInfoEEEPT_m: 76| 2.67k| template T *Allocate(size_t Num = 1) { 77| 2.67k| return static_cast(Allocate(Num * sizeof(T), AlignOf::Alignment)); 78| 2.67k| } _ZN7llvm_ks4castINS_11MCSymbolELFENS_8MCSymbolEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 6.44k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 6.44k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 6.44k, False: 0] | Branch (237:3): [True: 6.44k, Folded] | Branch (237:3): [True: 6.44k, False: 0] ------------------ 238| 6.44k| return cast_convert_val::SimpleType>::doit(Val); 240| 6.44k|} _ZN7llvm_ks3isaINS_11MCSymbolELFEPNS_8MCSymbolEEEbRKT0_: 132| 6.44k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 6.44k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 6.44k|} _ZN7llvm_ks13isa_impl_wrapINS_11MCSymbolELFEKPNS_8MCSymbolEPKS2_E4doitERS4_: 111| 6.44k| static bool doit(const From &Val) { 112| 6.44k| return isa_impl_wrap::SimpleType>::doit( 114| 6.44k| simplify_type::getSimplifiedValue(Val)); 115| 6.44k| } _ZN7llvm_ks13isa_impl_wrapINS_11MCSymbolELFEPKNS_8MCSymbolES4_E4doitERKS4_: 121| 6.51k| static bool doit(const FromTy &Val) { 122| 6.51k| return isa_impl_cl::doit(Val); 123| 6.51k| } _ZN7llvm_ks11isa_impl_clINS_11MCSymbolELFEPKNS_8MCSymbolEE4doitES4_: 94| 6.51k| static inline bool doit(const From *Val) { 95| 6.51k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 6.51k, False: 0] | Branch (95:5): [True: 6.51k, Folded] | Branch (95:5): [True: 6.51k, False: 0] ------------------ 96| 6.51k| return isa_impl::doit(*Val); 97| 6.51k| } _ZN7llvm_ks8isa_implINS_11MCSymbolELFENS_8MCSymbolEvE4doitERKS2_: 55| 9.10k| static inline bool doit(const From &Val) { 56| 9.10k| return To::classof(&Val); 57| 9.10k| } _ZN7llvm_ks13simplify_typeIKPNS_8MCSymbolEE18getSimplifiedValueERS3_: 45| 6.44k| static RetType getSimplifiedValue(const From& Val) { 46| 6.44k| return simplify_type::getSimplifiedValue(const_cast(Val)); 47| 6.44k| } _ZN7llvm_ks13simplify_typeIPNS_8MCSymbolEE18getSimplifiedValueERS2_: 36| 6.44k| static SimpleType &getSimplifiedValue(From &Val) { return Val; } _ZN7llvm_ks16cast_convert_valINS_11MCSymbolELFEPNS_8MCSymbolES3_E4doitERKS3_: 200| 6.44k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 6.44k| typename cast_retty::ret_type Res2 202| 6.44k| = (typename cast_retty::ret_type)const_cast(Val); 203| 6.44k| return Res2; 204| 6.44k| } _ZN7llvm_ks12cast_or_nullINS_11MCSymbolELFENS_8MCSymbolEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 267| 434|cast_or_null(Y *Val) { 268| 434| if (!Val) return nullptr; ------------------ | Branch (268:7): [True: 434, False: 0] ------------------ 269| 434| assert(isa(Val) && "cast_or_null() argument of incompatible type!"); ------------------ | Branch (269:3): [True: 0, False: 0] | Branch (269:3): [True: 0, Folded] | Branch (269:3): [True: 0, False: 0] ------------------ 270| 0| return cast(Val); 271| 0|} _ZN7llvm_ks4castINS_11MCSymbolELFES1_EENS_10cast_rettyIT_PT0_E8ret_typeES5_: 236| 589|inline typename cast_retty::ret_type cast(Y *Val) { 237| 589| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 589, False: 0] | Branch (237:3): [True: 589, Folded] | Branch (237:3): [True: 589, False: 0] ------------------ 238| 589| return cast_convert_val::SimpleType>::doit(Val); 240| 589|} _ZN7llvm_ks3isaINS_11MCSymbolELFEPS1_EEbRKT0_: 132| 589|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 589| return isa_impl_wrap::SimpleType>::doit(Val); 135| 589|} _ZN7llvm_ks13isa_impl_wrapINS_11MCSymbolELFEKPS1_PKS1_E4doitERS3_: 111| 589| static bool doit(const From &Val) { 112| 589| return isa_impl_wrap::SimpleType>::doit( 114| 589| simplify_type::getSimplifiedValue(Val)); 115| 589| } _ZN7llvm_ks13isa_impl_wrapINS_11MCSymbolELFEPKS1_S3_E4doitERKS3_: 121| 589| static bool doit(const FromTy &Val) { 122| 589| return isa_impl_cl::doit(Val); 123| 589| } _ZN7llvm_ks11isa_impl_clINS_11MCSymbolELFEPKS1_E4doitES3_: 94| 589| static inline bool doit(const From *Val) { 95| 589| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 589, False: 0] | Branch (95:5): [True: 589, Folded] | Branch (95:5): [True: 589, False: 0] ------------------ 96| 589| return isa_impl::doit(*Val); 97| 589| } _ZN7llvm_ks8isa_implINS_11MCSymbolELFES1_vE4doitERKS1_: 64| 589| static inline bool doit(const From &) { return true; } _ZN7llvm_ks13simplify_typeIKPNS_11MCSymbolELFEE18getSimplifiedValueERS3_: 45| 589| static RetType getSimplifiedValue(const From& Val) { 46| 589| return simplify_type::getSimplifiedValue(const_cast(Val)); 47| 589| } _ZN7llvm_ks13simplify_typeIPNS_11MCSymbolELFEE18getSimplifiedValueERS2_: 36| 589| static SimpleType &getSimplifiedValue(From &Val) { return Val; } _ZN7llvm_ks16cast_convert_valINS_11MCSymbolELFEPS1_S2_E4doitERKS2_: 200| 589| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 589| typename cast_retty::ret_type Res2 202| 589| = (typename cast_retty::ret_type)const_cast(Val); 203| 589| return Res2; 204| 589| } _ZN7llvm_ks13simplify_typeIKPKNS_6MCExprEE18getSimplifiedValueERS4_: 45| 84.5k| static RetType getSimplifiedValue(const From& Val) { 46| 84.5k| return simplify_type::getSimplifiedValue(const_cast(Val)); 47| 84.5k| } _ZN7llvm_ks13simplify_typeIPKNS_6MCExprEE18getSimplifiedValueERS3_: 36| 84.5k| static SimpleType &getSimplifiedValue(From &Val) { return Val; } _ZN7llvm_ks4castINS_12MCBinaryExprEKNS_6MCExprEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 236| 4.42k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 4.42k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 4.42k, False: 0] | Branch (237:3): [True: 4.42k, Folded] | Branch (237:3): [True: 4.42k, False: 0] ------------------ 238| 4.42k| return cast_convert_val::SimpleType>::doit(Val); 240| 4.42k|} _ZN7llvm_ks3isaINS_12MCBinaryExprEPKNS_6MCExprEEEbRKT0_: 132| 4.42k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 4.42k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 4.42k|} _ZN7llvm_ks13isa_impl_wrapINS_12MCBinaryExprEKPKNS_6MCExprES4_E4doitERS5_: 111| 4.42k| static bool doit(const From &Val) { 112| 4.42k| return isa_impl_wrap::SimpleType>::doit( 114| 4.42k| simplify_type::getSimplifiedValue(Val)); 115| 4.42k| } _ZN7llvm_ks13isa_impl_wrapINS_12MCBinaryExprEPKNS_6MCExprES4_E4doitERKS4_: 121| 4.42k| static bool doit(const FromTy &Val) { 122| 4.42k| return isa_impl_cl::doit(Val); 123| 4.42k| } _ZN7llvm_ks11isa_impl_clINS_12MCBinaryExprEPKNS_6MCExprEE4doitES4_: 94| 4.42k| static inline bool doit(const From *Val) { 95| 4.42k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 4.42k, False: 0] | Branch (95:5): [True: 4.42k, Folded] | Branch (95:5): [True: 4.42k, False: 0] ------------------ 96| 4.42k| return isa_impl::doit(*Val); 97| 4.42k| } _ZN7llvm_ks8isa_implINS_12MCBinaryExprENS_6MCExprEvE4doitERKS2_: 55| 5.38k| static inline bool doit(const From &Val) { 56| 5.38k| return To::classof(&Val); 57| 5.38k| } _ZN7llvm_ks16cast_convert_valINS_12MCBinaryExprEPKNS_6MCExprES4_E4doitERKS4_: 200| 4.42k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 4.42k| typename cast_retty::ret_type Res2 202| 4.42k| = (typename cast_retty::ret_type)const_cast(Val); 203| 4.42k| return Res2; 204| 4.42k| } _ZN7llvm_ks4castINS_15MCSymbolRefExprEKNS_6MCExprEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 236| 21.3k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 21.3k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 21.3k, False: 0] | Branch (237:3): [True: 21.3k, Folded] | Branch (237:3): [True: 21.3k, False: 0] ------------------ 238| 21.3k| return cast_convert_val::SimpleType>::doit(Val); 240| 21.3k|} _ZN7llvm_ks3isaINS_15MCSymbolRefExprEPKNS_6MCExprEEEbRKT0_: 132| 23.4k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 23.4k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 23.4k|} _ZN7llvm_ks13isa_impl_wrapINS_15MCSymbolRefExprEKPKNS_6MCExprES4_E4doitERS5_: 111| 23.4k| static bool doit(const From &Val) { 112| 23.4k| return isa_impl_wrap::SimpleType>::doit( 114| 23.4k| simplify_type::getSimplifiedValue(Val)); 115| 23.4k| } _ZN7llvm_ks13isa_impl_wrapINS_15MCSymbolRefExprEPKNS_6MCExprES4_E4doitERKS4_: 121| 23.4k| static bool doit(const FromTy &Val) { 122| 23.4k| return isa_impl_cl::doit(Val); 123| 23.4k| } _ZN7llvm_ks11isa_impl_clINS_15MCSymbolRefExprEPKNS_6MCExprEE4doitES4_: 94| 23.4k| static inline bool doit(const From *Val) { 95| 23.4k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 23.4k, False: 0] | Branch (95:5): [True: 23.4k, Folded] | Branch (95:5): [True: 23.4k, False: 0] ------------------ 96| 23.4k| return isa_impl::doit(*Val); 97| 23.4k| } _ZN7llvm_ks8isa_implINS_15MCSymbolRefExprENS_6MCExprEvE4doitERKS2_: 55| 24.9k| static inline bool doit(const From &Val) { 56| 24.9k| return To::classof(&Val); 57| 24.9k| } _ZN7llvm_ks16cast_convert_valINS_15MCSymbolRefExprEPKNS_6MCExprES4_E4doitERKS4_: 200| 21.3k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 21.3k| typename cast_retty::ret_type Res2 202| 21.3k| = (typename cast_retty::ret_type)const_cast(Val); 203| 21.3k| return Res2; 204| 21.3k| } _ZN7llvm_ks4castINS_11MCSymbolELFEKNS_8MCSymbolEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 2.59k|inline typename cast_retty::ret_type cast(Y &Val) { 230| 2.59k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 2.59k, False: 0] | Branch (230:3): [True: 2.59k, Folded] | Branch (230:3): [True: 2.59k, False: 0] ------------------ 231| 2.59k| return cast_convert_val::SimpleType>::doit(Val); 233| 2.59k|} _ZN7llvm_ks3isaINS_11MCSymbolELFENS_8MCSymbolEEEbRKT0_: 132| 2.59k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 2.59k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 2.59k|} _ZN7llvm_ks13isa_impl_wrapINS_11MCSymbolELFEKNS_8MCSymbolES3_E4doitERS3_: 121| 2.59k| static bool doit(const FromTy &Val) { 122| 2.59k| return isa_impl_cl::doit(Val); 123| 2.59k| } _ZN7llvm_ks11isa_impl_clINS_11MCSymbolELFEKNS_8MCSymbolEE4doitERS3_: 74| 2.59k| static inline bool doit(const From &Val) { 75| 2.59k| return isa_impl::doit(Val); 76| 2.59k| } _ZN7llvm_ks16cast_convert_valINS_11MCSymbolELFEKNS_8MCSymbolES3_E4doitERS3_: 200| 2.59k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 2.59k| typename cast_retty::ret_type Res2 202| 2.59k| = (typename cast_retty::ret_type)const_cast(Val); 203| 2.59k| return Res2; 204| 2.59k| } _ZN7llvm_ks4castINS_11MCUnaryExprEKNS_6MCExprEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 236| 8.53k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 8.53k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 8.53k, False: 0] | Branch (237:3): [True: 8.53k, Folded] | Branch (237:3): [True: 8.53k, False: 0] ------------------ 238| 8.53k| return cast_convert_val::SimpleType>::doit(Val); 240| 8.53k|} _ZN7llvm_ks3isaINS_11MCUnaryExprEPKNS_6MCExprEEEbRKT0_: 132| 8.53k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 8.53k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 8.53k|} _ZN7llvm_ks13isa_impl_wrapINS_11MCUnaryExprEKPKNS_6MCExprES4_E4doitERS5_: 111| 8.53k| static bool doit(const From &Val) { 112| 8.53k| return isa_impl_wrap::SimpleType>::doit( 114| 8.53k| simplify_type::getSimplifiedValue(Val)); 115| 8.53k| } _ZN7llvm_ks13isa_impl_wrapINS_11MCUnaryExprEPKNS_6MCExprES4_E4doitERKS4_: 121| 8.53k| static bool doit(const FromTy &Val) { 122| 8.53k| return isa_impl_cl::doit(Val); 123| 8.53k| } _ZN7llvm_ks11isa_impl_clINS_11MCUnaryExprEPKNS_6MCExprEE4doitES4_: 94| 8.53k| static inline bool doit(const From *Val) { 95| 8.53k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 8.53k, False: 0] | Branch (95:5): [True: 8.53k, Folded] | Branch (95:5): [True: 8.53k, False: 0] ------------------ 96| 8.53k| return isa_impl::doit(*Val); 97| 8.53k| } _ZN7llvm_ks8isa_implINS_11MCUnaryExprENS_6MCExprEvE4doitERKS2_: 55| 10.7k| static inline bool doit(const From &Val) { 56| 10.7k| return To::classof(&Val); 57| 10.7k| } _ZN7llvm_ks16cast_convert_valINS_11MCUnaryExprEPKNS_6MCExprES4_E4doitERKS4_: 200| 8.53k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 8.53k| typename cast_retty::ret_type Res2 202| 8.53k| = (typename cast_retty::ret_type)const_cast(Val); 203| 8.53k| return Res2; 204| 8.53k| } _ZN7llvm_ks4castINS_19MCRelaxableFragmentENS_10MCFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 1.70k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 1.70k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 1.70k, False: 0] | Branch (237:3): [True: 1.70k, Folded] | Branch (237:3): [True: 1.70k, False: 0] ------------------ 238| 1.70k| return cast_convert_val::SimpleType>::doit(Val); 240| 1.70k|} _ZN7llvm_ks3isaINS_19MCRelaxableFragmentEPNS_10MCFragmentEEEbRKT0_: 132| 1.70k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.70k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.70k|} _ZN7llvm_ks13isa_impl_wrapINS_19MCRelaxableFragmentEKPNS_10MCFragmentEPKS2_E4doitERS4_: 111| 1.70k| static bool doit(const From &Val) { 112| 1.70k| return isa_impl_wrap::SimpleType>::doit( 114| 1.70k| simplify_type::getSimplifiedValue(Val)); 115| 1.70k| } _ZN7llvm_ks13isa_impl_wrapINS_19MCRelaxableFragmentEPKNS_10MCFragmentES4_E4doitERKS4_: 121| 1.70k| static bool doit(const FromTy &Val) { 122| 1.70k| return isa_impl_cl::doit(Val); 123| 1.70k| } _ZN7llvm_ks11isa_impl_clINS_19MCRelaxableFragmentEPKNS_10MCFragmentEE4doitES4_: 94| 1.70k| static inline bool doit(const From *Val) { 95| 1.70k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 1.70k, False: 0] | Branch (95:5): [True: 1.70k, Folded] | Branch (95:5): [True: 1.70k, False: 0] ------------------ 96| 1.70k| return isa_impl::doit(*Val); 97| 1.70k| } _ZN7llvm_ks8isa_implINS_19MCRelaxableFragmentENS_10MCFragmentEvE4doitERKS2_: 55| 3.86k| static inline bool doit(const From &Val) { 56| 3.86k| return To::classof(&Val); 57| 3.86k| } _ZN7llvm_ks13simplify_typeIKPNS_10MCFragmentEE18getSimplifiedValueERS3_: 45| 24.5k| static RetType getSimplifiedValue(const From& Val) { 46| 24.5k| return simplify_type::getSimplifiedValue(const_cast(Val)); 47| 24.5k| } _ZN7llvm_ks13simplify_typeIPNS_10MCFragmentEE18getSimplifiedValueERS2_: 36| 24.5k| static SimpleType &getSimplifiedValue(From &Val) { return Val; } _ZN7llvm_ks16cast_convert_valINS_19MCRelaxableFragmentEPNS_10MCFragmentES3_E4doitERKS3_: 200| 2.45k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 2.45k| typename cast_retty::ret_type Res2 202| 2.45k| = (typename cast_retty::ret_type)const_cast(Val); 203| 2.45k| return Res2; 204| 2.45k| } _ZN7llvm_ks4castINS_14MCDataFragmentENS_10MCFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 8.31k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 8.31k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 8.31k, False: 0] | Branch (237:3): [True: 8.31k, Folded] | Branch (237:3): [True: 8.31k, False: 0] ------------------ 238| 8.31k| return cast_convert_val::SimpleType>::doit(Val); 240| 8.31k|} _ZN7llvm_ks3isaINS_14MCDataFragmentEPNS_10MCFragmentEEEbRKT0_: 132| 17.9k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 17.9k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 17.9k|} _ZN7llvm_ks13isa_impl_wrapINS_14MCDataFragmentEKPNS_10MCFragmentEPKS2_E4doitERS4_: 111| 17.9k| static bool doit(const From &Val) { 112| 17.9k| return isa_impl_wrap::SimpleType>::doit( 114| 17.9k| simplify_type::getSimplifiedValue(Val)); 115| 17.9k| } _ZN7llvm_ks13isa_impl_wrapINS_14MCDataFragmentEPKNS_10MCFragmentES4_E4doitERKS4_: 121| 17.9k| static bool doit(const FromTy &Val) { 122| 17.9k| return isa_impl_cl::doit(Val); 123| 17.9k| } _ZN7llvm_ks11isa_impl_clINS_14MCDataFragmentEPKNS_10MCFragmentEE4doitES4_: 94| 17.9k| static inline bool doit(const From *Val) { 95| 17.9k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 17.9k, False: 0] | Branch (95:5): [True: 17.9k, Folded] | Branch (95:5): [True: 17.9k, False: 0] ------------------ 96| 17.9k| return isa_impl::doit(*Val); 97| 17.9k| } _ZN7llvm_ks8isa_implINS_14MCDataFragmentENS_10MCFragmentEvE4doitERKS2_: 55| 19.2k| static inline bool doit(const From &Val) { 56| 19.2k| return To::classof(&Val); 57| 19.2k| } _ZN7llvm_ks16cast_convert_valINS_14MCDataFragmentEPNS_10MCFragmentES3_E4doitERKS3_: 200| 8.31k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 8.31k| typename cast_retty::ret_type Res2 202| 8.31k| = (typename cast_retty::ret_type)const_cast(Val); 203| 8.31k| return Res2; 204| 8.31k| } _ZN7llvm_ks8dyn_castINS_15MCSymbolRefExprEKNS_6MCExprEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 297| 822|dyn_cast(Y *Val) { 298| 822| return isa(Val) ? cast(Val) : nullptr; ------------------ | Branch (298:10): [True: 806, False: 16] ------------------ 299| 822|} _ZN7llvm_ks8isa_implINS_14MCConstantExprENS_6MCExprEvE4doitERKS2_: 55| 48.1k| static inline bool doit(const From &Val) { 56| 48.1k| return To::classof(&Val); 57| 48.1k| } _ZN7llvm_ks4castINS_15MCSymbolRefExprEKNS_6MCExprEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 1.49k|inline typename cast_retty::ret_type cast(Y &Val) { 230| 1.49k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 1.49k, False: 0] | Branch (230:3): [True: 1.49k, Folded] | Branch (230:3): [True: 1.49k, False: 0] ------------------ 231| 1.49k| return cast_convert_val::SimpleType>::doit(Val); 233| 1.49k|} _ZN7llvm_ks3isaINS_15MCSymbolRefExprENS_6MCExprEEEbRKT0_: 132| 1.49k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.49k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.49k|} _ZN7llvm_ks13isa_impl_wrapINS_15MCSymbolRefExprEKNS_6MCExprES3_E4doitERS3_: 121| 1.49k| static bool doit(const FromTy &Val) { 122| 1.49k| return isa_impl_cl::doit(Val); 123| 1.49k| } _ZN7llvm_ks11isa_impl_clINS_15MCSymbolRefExprEKNS_6MCExprEE4doitERS3_: 74| 1.49k| static inline bool doit(const From &Val) { 75| 1.49k| return isa_impl::doit(Val); 76| 1.49k| } _ZN7llvm_ks16cast_convert_valINS_15MCSymbolRefExprEKNS_6MCExprES3_E4doitERS3_: 200| 1.49k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 1.49k| typename cast_retty::ret_type Res2 202| 1.49k| = (typename cast_retty::ret_type)const_cast(Val); 203| 1.49k| return Res2; 204| 1.49k| } _ZN7llvm_ks4castINS_11MCUnaryExprEKNS_6MCExprEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 2.18k|inline typename cast_retty::ret_type cast(Y &Val) { 230| 2.18k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 2.18k, False: 0] | Branch (230:3): [True: 2.18k, Folded] | Branch (230:3): [True: 2.18k, False: 0] ------------------ 231| 2.18k| return cast_convert_val::SimpleType>::doit(Val); 233| 2.18k|} _ZN7llvm_ks3isaINS_11MCUnaryExprENS_6MCExprEEEbRKT0_: 132| 2.18k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 2.18k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 2.18k|} _ZN7llvm_ks13isa_impl_wrapINS_11MCUnaryExprEKNS_6MCExprES3_E4doitERS3_: 121| 2.18k| static bool doit(const FromTy &Val) { 122| 2.18k| return isa_impl_cl::doit(Val); 123| 2.18k| } _ZN7llvm_ks11isa_impl_clINS_11MCUnaryExprEKNS_6MCExprEE4doitERS3_: 74| 2.18k| static inline bool doit(const From &Val) { 75| 2.18k| return isa_impl::doit(Val); 76| 2.18k| } _ZN7llvm_ks16cast_convert_valINS_11MCUnaryExprEKNS_6MCExprES3_E4doitERS3_: 200| 2.18k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 2.18k| typename cast_retty::ret_type Res2 202| 2.18k| = (typename cast_retty::ret_type)const_cast(Val); 203| 2.18k| return Res2; 204| 2.18k| } _ZN7llvm_ks4castINS_12MCBinaryExprEKNS_6MCExprEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 961|inline typename cast_retty::ret_type cast(Y &Val) { 230| 961| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 961, False: 0] | Branch (230:3): [True: 961, Folded] | Branch (230:3): [True: 961, False: 0] ------------------ 231| 961| return cast_convert_val::SimpleType>::doit(Val); 233| 961|} _ZN7llvm_ks3isaINS_12MCBinaryExprENS_6MCExprEEEbRKT0_: 132| 961|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 961| return isa_impl_wrap::SimpleType>::doit(Val); 135| 961|} _ZN7llvm_ks13isa_impl_wrapINS_12MCBinaryExprEKNS_6MCExprES3_E4doitERS3_: 121| 961| static bool doit(const FromTy &Val) { 122| 961| return isa_impl_cl::doit(Val); 123| 961| } _ZN7llvm_ks11isa_impl_clINS_12MCBinaryExprEKNS_6MCExprEE4doitERS3_: 74| 961| static inline bool doit(const From &Val) { 75| 961| return isa_impl::doit(Val); 76| 961| } _ZN7llvm_ks16cast_convert_valINS_12MCBinaryExprEKNS_6MCExprES3_E4doitERS3_: 200| 961| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 961| typename cast_retty::ret_type Res2 202| 961| = (typename cast_retty::ret_type)const_cast(Val); 203| 961| return Res2; 204| 961| } _ZN7llvm_ks3isaINS_14MCConstantExprEPKNS_6MCExprEEEbRKT0_: 132| 48.1k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 48.1k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 48.1k|} _ZN7llvm_ks13isa_impl_wrapINS_14MCConstantExprEKPKNS_6MCExprES4_E4doitERS5_: 111| 48.1k| static bool doit(const From &Val) { 112| 48.1k| return isa_impl_wrap::SimpleType>::doit( 114| 48.1k| simplify_type::getSimplifiedValue(Val)); 115| 48.1k| } _ZN7llvm_ks13isa_impl_wrapINS_14MCConstantExprEPKNS_6MCExprES4_E4doitERKS4_: 121| 48.1k| static bool doit(const FromTy &Val) { 122| 48.1k| return isa_impl_cl::doit(Val); 123| 48.1k| } _ZN7llvm_ks11isa_impl_clINS_14MCConstantExprEPKNS_6MCExprEE4doitES4_: 94| 48.1k| static inline bool doit(const From *Val) { 95| 48.1k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 48.1k, False: 0] | Branch (95:5): [True: 48.1k, Folded] | Branch (95:5): [True: 48.1k, False: 0] ------------------ 96| 48.1k| return isa_impl::doit(*Val); 97| 48.1k| } _ZN7llvm_ks8dyn_castINS_14MCConstantExprEKNS_6MCExprEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 297| 32.5k|dyn_cast(Y *Val) { 298| 32.5k| return isa(Val) ? cast(Val) : nullptr; ------------------ | Branch (298:10): [True: 11.7k, False: 20.8k] ------------------ 299| 32.5k|} _ZN7llvm_ks4castINS_14MCConstantExprEKNS_6MCExprEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 236| 15.4k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 15.4k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 15.4k, False: 0] | Branch (237:3): [True: 15.4k, Folded] | Branch (237:3): [True: 15.4k, False: 0] ------------------ 238| 15.4k| return cast_convert_val::SimpleType>::doit(Val); 240| 15.4k|} _ZN7llvm_ks16cast_convert_valINS_14MCConstantExprEPKNS_6MCExprES4_E4doitERKS4_: 200| 15.4k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 15.4k| typename cast_retty::ret_type Res2 202| 15.4k| = (typename cast_retty::ret_type)const_cast(Val); 203| 15.4k| return Res2; 204| 15.4k| } _ZN7llvm_ks4castINS_15MCAlignFragmentENS_10MCFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 1.46k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 1.46k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 1.46k, False: 0] | Branch (237:3): [True: 1.46k, Folded] | Branch (237:3): [True: 1.46k, False: 0] ------------------ 238| 1.46k| return cast_convert_val::SimpleType>::doit(Val); 240| 1.46k|} _ZN7llvm_ks3isaINS_15MCAlignFragmentEPNS_10MCFragmentEEEbRKT0_: 132| 1.46k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.46k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.46k|} _ZN7llvm_ks13isa_impl_wrapINS_15MCAlignFragmentEKPNS_10MCFragmentEPKS2_E4doitERS4_: 111| 1.46k| static bool doit(const From &Val) { 112| 1.46k| return isa_impl_wrap::SimpleType>::doit( 114| 1.46k| simplify_type::getSimplifiedValue(Val)); 115| 1.46k| } _ZN7llvm_ks13isa_impl_wrapINS_15MCAlignFragmentEPKNS_10MCFragmentES4_E4doitERKS4_: 121| 1.46k| static bool doit(const FromTy &Val) { 122| 1.46k| return isa_impl_cl::doit(Val); 123| 1.46k| } _ZN7llvm_ks11isa_impl_clINS_15MCAlignFragmentEPKNS_10MCFragmentEE4doitES4_: 94| 1.46k| static inline bool doit(const From *Val) { 95| 1.46k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 1.46k, False: 0] | Branch (95:5): [True: 1.46k, Folded] | Branch (95:5): [True: 1.46k, False: 0] ------------------ 96| 1.46k| return isa_impl::doit(*Val); 97| 1.46k| } _ZN7llvm_ks8isa_implINS_15MCAlignFragmentENS_10MCFragmentEvE4doitERKS2_: 55| 3.18k| static inline bool doit(const From &Val) { 56| 3.18k| return To::classof(&Val); 57| 3.18k| } _ZN7llvm_ks16cast_convert_valINS_15MCAlignFragmentEPNS_10MCFragmentES3_E4doitERKS3_: 200| 1.46k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 1.46k| typename cast_retty::ret_type Res2 202| 1.46k| = (typename cast_retty::ret_type)const_cast(Val); 203| 1.46k| return Res2; 204| 1.46k| } _ZN7llvm_ks4castINS_14MCFillFragmentENS_10MCFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 292|inline typename cast_retty::ret_type cast(Y *Val) { 237| 292| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 292, False: 0] | Branch (237:3): [True: 292, Folded] | Branch (237:3): [True: 292, False: 0] ------------------ 238| 292| return cast_convert_val::SimpleType>::doit(Val); 240| 292|} _ZN7llvm_ks3isaINS_14MCFillFragmentEPNS_10MCFragmentEEEbRKT0_: 132| 292|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 292| return isa_impl_wrap::SimpleType>::doit(Val); 135| 292|} _ZN7llvm_ks13isa_impl_wrapINS_14MCFillFragmentEKPNS_10MCFragmentEPKS2_E4doitERS4_: 111| 292| static bool doit(const From &Val) { 112| 292| return isa_impl_wrap::SimpleType>::doit( 114| 292| simplify_type::getSimplifiedValue(Val)); 115| 292| } _ZN7llvm_ks13isa_impl_wrapINS_14MCFillFragmentEPKNS_10MCFragmentES4_E4doitERKS4_: 121| 292| static bool doit(const FromTy &Val) { 122| 292| return isa_impl_cl::doit(Val); 123| 292| } _ZN7llvm_ks11isa_impl_clINS_14MCFillFragmentEPKNS_10MCFragmentEE4doitES4_: 94| 292| static inline bool doit(const From *Val) { 95| 292| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 292, False: 0] | Branch (95:5): [True: 292, Folded] | Branch (95:5): [True: 292, False: 0] ------------------ 96| 292| return isa_impl::doit(*Val); 97| 292| } _ZN7llvm_ks8isa_implINS_14MCFillFragmentENS_10MCFragmentEvE4doitERKS2_: 55| 1.16k| static inline bool doit(const From &Val) { 56| 1.16k| return To::classof(&Val); 57| 1.16k| } _ZN7llvm_ks16cast_convert_valINS_14MCFillFragmentEPNS_10MCFragmentES3_E4doitERKS3_: 200| 292| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 292| typename cast_retty::ret_type Res2 202| 292| = (typename cast_retty::ret_type)const_cast(Val); 203| 292| return Res2; 204| 292| } _ZN7llvm_ks4castINS_13MCOrgFragmentENS_10MCFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 174|inline typename cast_retty::ret_type cast(Y *Val) { 237| 174| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 174, False: 0] | Branch (237:3): [True: 174, Folded] | Branch (237:3): [True: 174, False: 0] ------------------ 238| 174| return cast_convert_val::SimpleType>::doit(Val); 240| 174|} _ZN7llvm_ks3isaINS_13MCOrgFragmentEPNS_10MCFragmentEEEbRKT0_: 132| 174|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 174| return isa_impl_wrap::SimpleType>::doit(Val); 135| 174|} _ZN7llvm_ks13isa_impl_wrapINS_13MCOrgFragmentEKPNS_10MCFragmentEPKS2_E4doitERS4_: 111| 174| static bool doit(const From &Val) { 112| 174| return isa_impl_wrap::SimpleType>::doit( 114| 174| simplify_type::getSimplifiedValue(Val)); 115| 174| } _ZN7llvm_ks13isa_impl_wrapINS_13MCOrgFragmentEPKNS_10MCFragmentES4_E4doitERKS4_: 121| 174| static bool doit(const FromTy &Val) { 122| 174| return isa_impl_cl::doit(Val); 123| 174| } _ZN7llvm_ks11isa_impl_clINS_13MCOrgFragmentEPKNS_10MCFragmentEE4doitES4_: 94| 174| static inline bool doit(const From *Val) { 95| 174| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 174, False: 0] | Branch (95:5): [True: 174, Folded] | Branch (95:5): [True: 174, False: 0] ------------------ 96| 174| return isa_impl::doit(*Val); 97| 174| } _ZN7llvm_ks8isa_implINS_13MCOrgFragmentENS_10MCFragmentEvE4doitERKS2_: 55| 461| static inline bool doit(const From &Val) { 56| 461| return To::classof(&Val); 57| 461| } _ZN7llvm_ks16cast_convert_valINS_13MCOrgFragmentEPNS_10MCFragmentES3_E4doitERKS3_: 200| 174| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 174| typename cast_retty::ret_type Res2 202| 174| = (typename cast_retty::ret_type)const_cast(Val); 203| 174| return Res2; 204| 174| } _ZN7llvm_ks16dyn_cast_or_nullINS_14MCDataFragmentENS_10MCFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 320| 32.7k|dyn_cast_or_null(Y *Val) { 321| 32.7k| return (Val && isa(Val)) ? cast(Val) : nullptr; ------------------ | Branch (321:11): [True: 9.60k, False: 23.1k] | Branch (321:18): [True: 7.53k, False: 2.06k] ------------------ 322| 32.7k|} _ZN7llvm_ks16dyn_cast_or_nullINS_14MCConstantExprEKNS_6MCExprEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 320| 128|dyn_cast_or_null(Y *Val) { 321| 128| return (Val && isa(Val)) ? cast(Val) : nullptr; ------------------ | Branch (321:11): [True: 128, False: 0] | Branch (321:18): [True: 0, False: 128] ------------------ 322| 128|} _ZN7llvm_ks4castINS_14MCDataFragmentEKNS_10MCFragmentEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 1.28k|inline typename cast_retty::ret_type cast(Y &Val) { 230| 1.28k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 1.28k, False: 0] | Branch (230:3): [True: 1.28k, Folded] | Branch (230:3): [True: 1.28k, False: 0] ------------------ 231| 1.28k| return cast_convert_val::SimpleType>::doit(Val); 233| 1.28k|} _ZN7llvm_ks3isaINS_14MCDataFragmentENS_10MCFragmentEEEbRKT0_: 132| 1.28k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.28k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.28k|} _ZN7llvm_ks13isa_impl_wrapINS_14MCDataFragmentEKNS_10MCFragmentES3_E4doitERS3_: 121| 1.28k| static bool doit(const FromTy &Val) { 122| 1.28k| return isa_impl_cl::doit(Val); 123| 1.28k| } _ZN7llvm_ks11isa_impl_clINS_14MCDataFragmentEKNS_10MCFragmentEE4doitERS3_: 74| 1.28k| static inline bool doit(const From &Val) { 75| 1.28k| return isa_impl::doit(Val); 76| 1.28k| } _ZN7llvm_ks16cast_convert_valINS_14MCDataFragmentEKNS_10MCFragmentES3_E4doitERS3_: 200| 1.28k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 1.28k| typename cast_retty::ret_type Res2 202| 1.28k| = (typename cast_retty::ret_type)const_cast(Val); 203| 1.28k| return Res2; 204| 1.28k| } _ZN7llvm_ks4castINS_19MCRelaxableFragmentEKNS_10MCFragmentEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 1.41k|inline typename cast_retty::ret_type cast(Y &Val) { 230| 1.41k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 1.41k, False: 0] | Branch (230:3): [True: 1.41k, Folded] | Branch (230:3): [True: 1.41k, False: 0] ------------------ 231| 1.41k| return cast_convert_val::SimpleType>::doit(Val); 233| 1.41k|} _ZN7llvm_ks3isaINS_19MCRelaxableFragmentENS_10MCFragmentEEEbRKT0_: 132| 1.41k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.41k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.41k|} _ZN7llvm_ks13isa_impl_wrapINS_19MCRelaxableFragmentEKNS_10MCFragmentES3_E4doitERS3_: 121| 1.41k| static bool doit(const FromTy &Val) { 122| 1.41k| return isa_impl_cl::doit(Val); 123| 1.41k| } _ZN7llvm_ks11isa_impl_clINS_19MCRelaxableFragmentEKNS_10MCFragmentEE4doitERS3_: 74| 1.41k| static inline bool doit(const From &Val) { 75| 1.41k| return isa_impl::doit(Val); 76| 1.41k| } _ZN7llvm_ks16cast_convert_valINS_19MCRelaxableFragmentEKNS_10MCFragmentES3_E4doitERS3_: 200| 1.41k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 1.41k| typename cast_retty::ret_type Res2 202| 1.41k| = (typename cast_retty::ret_type)const_cast(Val); 203| 1.41k| return Res2; 204| 1.41k| } _ZN7llvm_ks4castINS_14MCFillFragmentEKNS_10MCFragmentEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 871|inline typename cast_retty::ret_type cast(Y &Val) { 230| 871| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 871, False: 0] | Branch (230:3): [True: 871, Folded] | Branch (230:3): [True: 871, False: 0] ------------------ 231| 871| return cast_convert_val::SimpleType>::doit(Val); 233| 871|} _ZN7llvm_ks3isaINS_14MCFillFragmentENS_10MCFragmentEEEbRKT0_: 132| 871|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 871| return isa_impl_wrap::SimpleType>::doit(Val); 135| 871|} _ZN7llvm_ks13isa_impl_wrapINS_14MCFillFragmentEKNS_10MCFragmentES3_E4doitERS3_: 121| 871| static bool doit(const FromTy &Val) { 122| 871| return isa_impl_cl::doit(Val); 123| 871| } _ZN7llvm_ks11isa_impl_clINS_14MCFillFragmentEKNS_10MCFragmentEE4doitERS3_: 74| 871| static inline bool doit(const From &Val) { 75| 871| return isa_impl::doit(Val); 76| 871| } _ZN7llvm_ks16cast_convert_valINS_14MCFillFragmentEKNS_10MCFragmentES3_E4doitERS3_: 200| 871| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 871| typename cast_retty::ret_type Res2 202| 871| = (typename cast_retty::ret_type)const_cast(Val); 203| 871| return Res2; 204| 871| } _ZN7llvm_ks4castINS_15MCAlignFragmentEKNS_10MCFragmentEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 1.71k|inline typename cast_retty::ret_type cast(Y &Val) { 230| 1.71k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 1.71k, False: 0] | Branch (230:3): [True: 1.71k, Folded] | Branch (230:3): [True: 1.71k, False: 0] ------------------ 231| 1.71k| return cast_convert_val::SimpleType>::doit(Val); 233| 1.71k|} _ZN7llvm_ks3isaINS_15MCAlignFragmentENS_10MCFragmentEEEbRKT0_: 132| 1.71k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.71k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.71k|} _ZN7llvm_ks13isa_impl_wrapINS_15MCAlignFragmentEKNS_10MCFragmentES3_E4doitERS3_: 121| 1.71k| static bool doit(const FromTy &Val) { 122| 1.71k| return isa_impl_cl::doit(Val); 123| 1.71k| } _ZN7llvm_ks11isa_impl_clINS_15MCAlignFragmentEKNS_10MCFragmentEE4doitERS3_: 74| 1.71k| static inline bool doit(const From &Val) { 75| 1.71k| return isa_impl::doit(Val); 76| 1.71k| } _ZN7llvm_ks16cast_convert_valINS_15MCAlignFragmentEKNS_10MCFragmentES3_E4doitERS3_: 200| 1.71k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 1.71k| typename cast_retty::ret_type Res2 202| 1.71k| = (typename cast_retty::ret_type)const_cast(Val); 203| 1.71k| return Res2; 204| 1.71k| } _ZN7llvm_ks4castINS_13MCOrgFragmentEKNS_10MCFragmentEEENS_10cast_rettyIT_T0_E8ret_typeERS6_: 229| 287|inline typename cast_retty::ret_type cast(Y &Val) { 230| 287| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 287, False: 0] | Branch (230:3): [True: 287, Folded] | Branch (230:3): [True: 287, False: 0] ------------------ 231| 287| return cast_convert_val::SimpleType>::doit(Val); 233| 287|} _ZN7llvm_ks3isaINS_13MCOrgFragmentENS_10MCFragmentEEEbRKT0_: 132| 287|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 287| return isa_impl_wrap::SimpleType>::doit(Val); 135| 287|} _ZN7llvm_ks13isa_impl_wrapINS_13MCOrgFragmentEKNS_10MCFragmentES3_E4doitERS3_: 121| 287| static bool doit(const FromTy &Val) { 122| 287| return isa_impl_cl::doit(Val); 123| 287| } _ZN7llvm_ks11isa_impl_clINS_13MCOrgFragmentEKNS_10MCFragmentEE4doitERS3_: 74| 287| static inline bool doit(const From &Val) { 75| 287| return isa_impl::doit(Val); 76| 287| } _ZN7llvm_ks16cast_convert_valINS_13MCOrgFragmentEKNS_10MCFragmentES3_E4doitERS3_: 200| 287| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 287| typename cast_retty::ret_type Res2 202| 287| = (typename cast_retty::ret_type)const_cast(Val); 203| 287| return Res2; 204| 287| } _ZN7llvm_ks3isaINS_17MCEncodedFragmentEPNS_10MCFragmentEEEbRKT0_: 132| 3.01k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 3.01k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 3.01k|} _ZN7llvm_ks13isa_impl_wrapINS_17MCEncodedFragmentEKPNS_10MCFragmentEPKS2_E4doitERS4_: 111| 3.01k| static bool doit(const From &Val) { 112| 3.01k| return isa_impl_wrap::SimpleType>::doit( 114| 3.01k| simplify_type::getSimplifiedValue(Val)); 115| 3.01k| } _ZN7llvm_ks13isa_impl_wrapINS_17MCEncodedFragmentEPKNS_10MCFragmentES4_E4doitERKS4_: 121| 3.01k| static bool doit(const FromTy &Val) { 122| 3.01k| return isa_impl_cl::doit(Val); 123| 3.01k| } _ZN7llvm_ks11isa_impl_clINS_17MCEncodedFragmentEPKNS_10MCFragmentEE4doitES4_: 94| 3.01k| static inline bool doit(const From *Val) { 95| 3.01k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 3.01k, False: 0] | Branch (95:5): [True: 3.01k, Folded] | Branch (95:5): [True: 3.01k, False: 0] ------------------ 96| 3.01k| return isa_impl::doit(*Val); 97| 3.01k| } _ZN7llvm_ks8isa_implINS_17MCEncodedFragmentENS_10MCFragmentEvE4doitERKS2_: 55| 3.01k| static inline bool doit(const From &Val) { 56| 3.01k| return To::classof(&Val); 57| 3.01k| } _ZN7llvm_ks13simplify_typeIKPKNS_9MCSectionEE18getSimplifiedValueERS4_: 45| 2| static RetType getSimplifiedValue(const From& Val) { 46| 2| return simplify_type::getSimplifiedValue(const_cast(Val)); 47| 2| } _ZN7llvm_ks13simplify_typeIPKNS_9MCSectionEE18getSimplifiedValueERS3_: 36| 2| static SimpleType &getSimplifiedValue(From &Val) { return Val; } _ZN7llvm_ks8dyn_castINS_17MCEncodedFragmentENS_10MCFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 297| 1.98k|dyn_cast(Y *Val) { 298| 1.98k| return isa(Val) ? cast(Val) : nullptr; ------------------ | Branch (298:10): [True: 1.02k, False: 964] ------------------ 299| 1.98k|} _ZN7llvm_ks4castINS_17MCEncodedFragmentENS_10MCFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 1.02k|inline typename cast_retty::ret_type cast(Y *Val) { 237| 1.02k| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 1.02k, False: 0] | Branch (237:3): [True: 1.02k, Folded] | Branch (237:3): [True: 1.02k, False: 0] ------------------ 238| 1.02k| return cast_convert_val::SimpleType>::doit(Val); 240| 1.02k|} _ZN7llvm_ks16cast_convert_valINS_17MCEncodedFragmentEPNS_10MCFragmentES3_E4doitERKS3_: 200| 1.02k| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 1.02k| typename cast_retty::ret_type Res2 202| 1.02k| = (typename cast_retty::ret_type)const_cast(Val); 203| 1.02k| return Res2; 204| 1.02k| } _ZN7llvm_ks3isaINS_28MCCompactEncodedInstFragmentEPNS_17MCEncodedFragmentEEEbRKT0_: 132| 1.02k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.02k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.02k|} _ZN7llvm_ks13isa_impl_wrapINS_28MCCompactEncodedInstFragmentEKPNS_17MCEncodedFragmentEPKS2_E4doitERS4_: 111| 1.02k| static bool doit(const From &Val) { 112| 1.02k| return isa_impl_wrap::SimpleType>::doit( 114| 1.02k| simplify_type::getSimplifiedValue(Val)); 115| 1.02k| } _ZN7llvm_ks13isa_impl_wrapINS_28MCCompactEncodedInstFragmentEPKNS_17MCEncodedFragmentES4_E4doitERKS4_: 121| 1.02k| static bool doit(const FromTy &Val) { 122| 1.02k| return isa_impl_cl::doit(Val); 123| 1.02k| } _ZN7llvm_ks11isa_impl_clINS_28MCCompactEncodedInstFragmentEPKNS_17MCEncodedFragmentEE4doitES4_: 94| 1.02k| static inline bool doit(const From *Val) { 95| 1.02k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 1.02k, False: 0] | Branch (95:5): [True: 1.02k, Folded] | Branch (95:5): [True: 1.02k, False: 0] ------------------ 96| 1.02k| return isa_impl::doit(*Val); 97| 1.02k| } _ZN7llvm_ks8isa_implINS_28MCCompactEncodedInstFragmentENS_17MCEncodedFragmentEvE4doitERKS2_: 55| 1.02k| static inline bool doit(const From &Val) { 56| 1.02k| return To::classof(&Val); 57| 1.02k| } _ZN7llvm_ks13simplify_typeIKPNS_17MCEncodedFragmentEE18getSimplifiedValueERS3_: 45| 3.66k| static RetType getSimplifiedValue(const From& Val) { 46| 3.66k| return simplify_type::getSimplifiedValue(const_cast(Val)); 47| 3.66k| } _ZN7llvm_ks13simplify_typeIPNS_17MCEncodedFragmentEE18getSimplifiedValueERS2_: 36| 3.66k| static SimpleType &getSimplifiedValue(From &Val) { return Val; } _ZN7llvm_ks8dyn_castINS_14MCDataFragmentENS_17MCEncodedFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 297| 1.02k|dyn_cast(Y *Val) { 298| 1.02k| return isa(Val) ? cast(Val) : nullptr; ------------------ | Branch (298:10): [True: 430, False: 593] ------------------ 299| 1.02k|} _ZN7llvm_ks3isaINS_14MCDataFragmentEPNS_17MCEncodedFragmentEEEbRKT0_: 132| 1.45k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.45k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.45k|} _ZN7llvm_ks13isa_impl_wrapINS_14MCDataFragmentEKPNS_17MCEncodedFragmentEPKS2_E4doitERS4_: 111| 1.45k| static bool doit(const From &Val) { 112| 1.45k| return isa_impl_wrap::SimpleType>::doit( 114| 1.45k| simplify_type::getSimplifiedValue(Val)); 115| 1.45k| } _ZN7llvm_ks13isa_impl_wrapINS_14MCDataFragmentEPKNS_17MCEncodedFragmentES4_E4doitERKS4_: 121| 1.45k| static bool doit(const FromTy &Val) { 122| 1.45k| return isa_impl_cl::doit(Val); 123| 1.45k| } _ZN7llvm_ks11isa_impl_clINS_14MCDataFragmentEPKNS_17MCEncodedFragmentEE4doitES4_: 94| 1.45k| static inline bool doit(const From *Val) { 95| 1.45k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 1.45k, False: 0] | Branch (95:5): [True: 1.45k, Folded] | Branch (95:5): [True: 1.45k, False: 0] ------------------ 96| 1.45k| return isa_impl::doit(*Val); 97| 1.45k| } _ZN7llvm_ks8isa_implINS_14MCDataFragmentENS_17MCEncodedFragmentEvE4doitERKS2_: 55| 1.45k| static inline bool doit(const From &Val) { 56| 1.45k| return To::classof(&Val); 57| 1.45k| } _ZN7llvm_ks4castINS_14MCDataFragmentENS_17MCEncodedFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 430|inline typename cast_retty::ret_type cast(Y *Val) { 237| 430| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 430, False: 0] | Branch (237:3): [True: 430, Folded] | Branch (237:3): [True: 430, False: 0] ------------------ 238| 430| return cast_convert_val::SimpleType>::doit(Val); 240| 430|} _ZN7llvm_ks16cast_convert_valINS_14MCDataFragmentEPNS_17MCEncodedFragmentES3_E4doitERKS3_: 200| 430| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 430| typename cast_retty::ret_type Res2 202| 430| = (typename cast_retty::ret_type)const_cast(Val); 203| 430| return Res2; 204| 430| } _ZN7llvm_ks8dyn_castINS_19MCRelaxableFragmentENS_17MCEncodedFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 297| 593|dyn_cast(Y *Val) { 298| 593| return isa(Val) ? cast(Val) : nullptr; ------------------ | Branch (298:10): [True: 593, False: 0] ------------------ 299| 593|} _ZN7llvm_ks3isaINS_19MCRelaxableFragmentEPNS_17MCEncodedFragmentEEEbRKT0_: 132| 1.18k|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 1.18k| return isa_impl_wrap::SimpleType>::doit(Val); 135| 1.18k|} _ZN7llvm_ks13isa_impl_wrapINS_19MCRelaxableFragmentEKPNS_17MCEncodedFragmentEPKS2_E4doitERS4_: 111| 1.18k| static bool doit(const From &Val) { 112| 1.18k| return isa_impl_wrap::SimpleType>::doit( 114| 1.18k| simplify_type::getSimplifiedValue(Val)); 115| 1.18k| } _ZN7llvm_ks13isa_impl_wrapINS_19MCRelaxableFragmentEPKNS_17MCEncodedFragmentES4_E4doitERKS4_: 121| 1.18k| static bool doit(const FromTy &Val) { 122| 1.18k| return isa_impl_cl::doit(Val); 123| 1.18k| } _ZN7llvm_ks11isa_impl_clINS_19MCRelaxableFragmentEPKNS_17MCEncodedFragmentEE4doitES4_: 94| 1.18k| static inline bool doit(const From *Val) { 95| 1.18k| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 1.18k, False: 0] | Branch (95:5): [True: 1.18k, Folded] | Branch (95:5): [True: 1.18k, False: 0] ------------------ 96| 1.18k| return isa_impl::doit(*Val); 97| 1.18k| } _ZN7llvm_ks8isa_implINS_19MCRelaxableFragmentENS_17MCEncodedFragmentEvE4doitERKS2_: 55| 1.18k| static inline bool doit(const From &Val) { 56| 1.18k| return To::classof(&Val); 57| 1.18k| } _ZN7llvm_ks4castINS_19MCRelaxableFragmentENS_17MCEncodedFragmentEEENS_10cast_rettyIT_PT0_E8ret_typeES6_: 236| 593|inline typename cast_retty::ret_type cast(Y *Val) { 237| 593| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 593, False: 0] | Branch (237:3): [True: 593, Folded] | Branch (237:3): [True: 593, False: 0] ------------------ 238| 593| return cast_convert_val::SimpleType>::doit(Val); 240| 593|} _ZN7llvm_ks16cast_convert_valINS_19MCRelaxableFragmentEPNS_17MCEncodedFragmentES3_E4doitERKS3_: 200| 593| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 593| typename cast_retty::ret_type Res2 202| 593| = (typename cast_retty::ret_type)const_cast(Val); 203| 593| return Res2; 204| 593| } _ZN7llvm_ks4castINS_19MCRelaxableFragmentENS_14ilist_iteratorINS_10MCFragmentEEEEENS_10cast_rettyIT_T0_E8ret_typeERS7_: 229| 758|inline typename cast_retty::ret_type cast(Y &Val) { 230| 758| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 758, False: 0] | Branch (230:3): [True: 758, Folded] | Branch (230:3): [True: 758, False: 0] ------------------ 231| 758| return cast_convert_val::SimpleType>::doit(Val); 233| 758|} _ZN7llvm_ks3isaINS_19MCRelaxableFragmentENS_14ilist_iteratorINS_10MCFragmentEEEEEbRKT0_: 132| 758|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 758| return isa_impl_wrap::SimpleType>::doit(Val); 135| 758|} _ZN7llvm_ks13isa_impl_wrapINS_19MCRelaxableFragmentEKNS_14ilist_iteratorINS_10MCFragmentEEEPS3_E4doitERS5_: 111| 758| static bool doit(const From &Val) { 112| 758| return isa_impl_wrap::SimpleType>::doit( 114| 758| simplify_type::getSimplifiedValue(Val)); 115| 758| } _ZN7llvm_ks13isa_impl_wrapINS_19MCRelaxableFragmentEPNS_10MCFragmentES3_E4doitERKS3_: 121| 758| static bool doit(const FromTy &Val) { 122| 758| return isa_impl_cl::doit(Val); 123| 758| } _ZN7llvm_ks11isa_impl_clINS_19MCRelaxableFragmentEPNS_10MCFragmentEE4doitEPKS2_: 80| 758| static inline bool doit(const From *Val) { 81| 758| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (81:5): [True: 758, False: 0] | Branch (81:5): [True: 758, Folded] | Branch (81:5): [True: 758, False: 0] ------------------ 82| 758| return isa_impl::doit(*Val); 83| 758| } _ZN7llvm_ks16cast_convert_valINS_19MCRelaxableFragmentENS_14ilist_iteratorINS_10MCFragmentEEEPS3_E4doitERS4_: 191| 758| static typename cast_retty::ret_type doit(From &Val) { 192| 758| return cast_convert_val::SimpleType>::doit( 194| 758| simplify_type::getSimplifiedValue(Val)); 195| 758| } _ZN7llvm_ks3isaINS_11MCSymbolELFEPKNS_8MCSymbolEEEbRKT0_: 132| 70|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 70| return isa_impl_wrap::SimpleType>::doit(Val); 135| 70|} _ZN7llvm_ks13isa_impl_wrapINS_11MCSymbolELFEKPKNS_8MCSymbolES4_E4doitERS5_: 111| 70| static bool doit(const From &Val) { 112| 70| return isa_impl_wrap::SimpleType>::doit( 114| 70| simplify_type::getSimplifiedValue(Val)); 115| 70| } _ZN7llvm_ks13simplify_typeIKPKNS_8MCSymbolEE18getSimplifiedValueERS4_: 45| 70| static RetType getSimplifiedValue(const From& Val) { 46| 70| return simplify_type::getSimplifiedValue(const_cast(Val)); 47| 70| } _ZN7llvm_ks13simplify_typeIPKNS_8MCSymbolEE18getSimplifiedValueERS3_: 36| 70| static SimpleType &getSimplifiedValue(From &Val) { return Val; } _ZN7llvm_ks4castINS_11MCSymbolELFEKNS_8MCSymbolEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 236| 47|inline typename cast_retty::ret_type cast(Y *Val) { 237| 47| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 47, False: 0] | Branch (237:3): [True: 47, Folded] | Branch (237:3): [True: 47, False: 0] ------------------ 238| 47| return cast_convert_val::SimpleType>::doit(Val); 240| 47|} _ZN7llvm_ks16cast_convert_valINS_11MCSymbolELFEPKNS_8MCSymbolES4_E4doitERKS4_: 200| 47| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 47| typename cast_retty::ret_type Res2 202| 47| = (typename cast_retty::ret_type)const_cast(Val); 203| 47| return Res2; 204| 47| } _ZN7llvm_ks4castINS_12MCSectionELFENS_9MCSectionEEENS_10cast_rettyIT_T0_E8ret_typeERS5_: 229| 138|inline typename cast_retty::ret_type cast(Y &Val) { 230| 138| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (230:3): [True: 138, False: 0] | Branch (230:3): [True: 138, Folded] | Branch (230:3): [True: 138, False: 0] ------------------ 231| 138| return cast_convert_val::SimpleType>::doit(Val); 233| 138|} _ZN7llvm_ks3isaINS_12MCSectionELFENS_9MCSectionEEEbRKT0_: 132| 138|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 138| return isa_impl_wrap::SimpleType>::doit(Val); 135| 138|} _ZN7llvm_ks13isa_impl_wrapINS_12MCSectionELFEKNS_9MCSectionES3_E4doitERS3_: 121| 138| static bool doit(const FromTy &Val) { 122| 138| return isa_impl_cl::doit(Val); 123| 138| } _ZN7llvm_ks11isa_impl_clINS_12MCSectionELFEKNS_9MCSectionEE4doitERS3_: 74| 138| static inline bool doit(const From &Val) { 75| 138| return isa_impl::doit(Val); 76| 138| } _ZN7llvm_ks8isa_implINS_12MCSectionELFENS_9MCSectionEvE4doitERKS2_: 55| 140| static inline bool doit(const From &Val) { 56| 140| return To::classof(&Val); 57| 140| } _ZN7llvm_ks16cast_convert_valINS_12MCSectionELFENS_9MCSectionES2_E4doitERKS2_: 200| 138| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 138| typename cast_retty::ret_type Res2 202| 138| = (typename cast_retty::ret_type)const_cast(Val); 203| 138| return Res2; 204| 138| } _ZN7llvm_ks12cast_or_nullINS_11MCSymbolELFEKNS_8MCSymbolEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 267| 30|cast_or_null(Y *Val) { 268| 30| if (!Val) return nullptr; ------------------ | Branch (268:7): [True: 7, False: 23] ------------------ 269| 30| assert(isa(Val) && "cast_or_null() argument of incompatible type!"); ------------------ | Branch (269:3): [True: 23, False: 0] | Branch (269:3): [True: 23, Folded] | Branch (269:3): [True: 23, False: 0] ------------------ 270| 23| return cast(Val); 271| 23|} _ZN7llvm_ks12cast_or_nullINS_12MCSectionELFEKNS_9MCSectionEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 267| 8|cast_or_null(Y *Val) { 268| 8| if (!Val) return nullptr; ------------------ | Branch (268:7): [True: 7, False: 1] ------------------ 269| 8| assert(isa(Val) && "cast_or_null() argument of incompatible type!"); ------------------ | Branch (269:3): [True: 1, False: 0] | Branch (269:3): [True: 1, Folded] | Branch (269:3): [True: 1, False: 0] ------------------ 270| 1| return cast(Val); 271| 1|} _ZN7llvm_ks3isaINS_12MCSectionELFEPKNS_9MCSectionEEEbRKT0_: 132| 2|LLVM_ATTRIBUTE_UNUSED_RESULT inline bool isa(const Y &Val) { 133| 2| return isa_impl_wrap::SimpleType>::doit(Val); 135| 2|} _ZN7llvm_ks13isa_impl_wrapINS_12MCSectionELFEKPKNS_9MCSectionES4_E4doitERS5_: 111| 2| static bool doit(const From &Val) { 112| 2| return isa_impl_wrap::SimpleType>::doit( 114| 2| simplify_type::getSimplifiedValue(Val)); 115| 2| } _ZN7llvm_ks13isa_impl_wrapINS_12MCSectionELFEPKNS_9MCSectionES4_E4doitERKS4_: 121| 2| static bool doit(const FromTy &Val) { 122| 2| return isa_impl_cl::doit(Val); 123| 2| } _ZN7llvm_ks11isa_impl_clINS_12MCSectionELFEPKNS_9MCSectionEE4doitES4_: 94| 2| static inline bool doit(const From *Val) { 95| 2| assert(Val && "isa<> used on a null pointer"); ------------------ | Branch (95:5): [True: 2, False: 0] | Branch (95:5): [True: 2, Folded] | Branch (95:5): [True: 2, False: 0] ------------------ 96| 2| return isa_impl::doit(*Val); 97| 2| } _ZN7llvm_ks4castINS_12MCSectionELFEKNS_9MCSectionEEENS_10cast_rettyIT_PT0_E8ret_typeES7_: 236| 1|inline typename cast_retty::ret_type cast(Y *Val) { 237| 1| assert(isa(Val) && "cast() argument of incompatible type!"); ------------------ | Branch (237:3): [True: 1, False: 0] | Branch (237:3): [True: 1, Folded] | Branch (237:3): [True: 1, False: 0] ------------------ 238| 1| return cast_convert_val::SimpleType>::doit(Val); 240| 1|} _ZN7llvm_ks16cast_convert_valINS_12MCSectionELFEPKNS_9MCSectionES4_E4doitERKS4_: 200| 1| static typename cast_retty::ret_type doit(const FromTy &Val) { 201| 1| typename cast_retty::ret_type Res2 202| 1| = (typename cast_retty::ret_type)const_cast(Val); 203| 1| return Res2; 204| 1| } _ZN7llvm_ks7support6endian9byte_swapItLNS0_10endiannessE0EEET_S4_: 39| 9|inline value_type byte_swap(value_type value) { 40| 9| if (endian != native && sys::IsBigEndianHost != (endian == big)) ------------------ | Branch (40:7): [True: 0, Folded] | Branch (40:27): [True: 0, Folded] ------------------ 41| 9| sys::swapByteOrder(value); 42| 9| return value; 43| 9|} _ZN7llvm_ks7support6endian6WriterILNS0_10endiannessE0EE5writeItEEvT_: 34| 9| template void write(value_type Val) { 35| 9| Val = byte_swap(Val); 36| 9| OS.write((const char *)&Val, sizeof(value_type)); 37| 9| } _ZN7llvm_ks7support6endian6WriterILNS0_10endiannessE0EEC2ERNS_11raw_ostreamE: 29| 9| Writer(raw_ostream &OS) : OS(OS) {} _ZN7llvm_ks7ErrorOrINSt3__110unique_ptrINS_12MemoryBufferENS1_14default_deleteIS3_EEEEEC2ES6_: 110| 430| ErrorOr(T Val) : HasError(false) { 111| 430| new (getStorage()) storage_type(moveIfMoveConstructible(Val)); 112| 430| } _ZN7llvm_ks7ErrorOrINSt3__110unique_ptrINS_12MemoryBufferENS1_14default_deleteIS3_EEEEE10getStorageEv: 262| 1.29k| storage_type *getStorage() { 263| 1.29k| assert(!HasError && "Cannot get value when an error exists!"); ------------------ | Branch (263:5): [True: 1.29k, False: 0] | Branch (263:5): [True: 1.29k, Folded] | Branch (263:5): [True: 1.29k, False: 0] ------------------ 264| 1.29k| return reinterpret_cast(TStorage.buffer); 265| 1.29k| } _ZN7llvm_ks23moveIfMoveConstructibleINSt3__110unique_ptrINS_12MemoryBufferENS1_14default_deleteIS3_EEEES6_EEONS1_9enable_ifIXsr3std16is_constructibleIT_T0_EE5valueENS1_16remove_referenceIS9_E4typeEE4typeERS9_: 29| 430| moveIfMoveConstructible(V &Val) { 30| 430| return std::move(Val); 31| 430|} _ZN7llvm_ks7ErrorOrINSt3__110unique_ptrINS_12MemoryBufferENS1_14default_deleteIS3_EEEEED2Ev: 166| 430| ~ErrorOr() { 167| 430| if (!HasError) ------------------ | Branch (167:9): [True: 430, False: 0] ------------------ 168| 430| getStorage()->~storage_type(); 169| 430| } _ZNK7llvm_ks7ErrorOrINSt3__110unique_ptrINS_12MemoryBufferENS1_14default_deleteIS3_EEEEE8getErrorEv: 179| 430| std::error_code getError() const { 180| 430| return HasError ? *getErrorStorage() : std::error_code(); ------------------ | Branch (180:12): [True: 0, False: 430] ------------------ 181| 430| } _ZN7llvm_ks7ErrorOrINSt3__110unique_ptrINS_12MemoryBufferENS1_14default_deleteIS3_EEEEEdeEv: 189| 430| reference operator *() { 190| 430| return *getStorage(); 191| 430| } _ZN7llvm_ks3sys2fs8UniqueIDC2Emm: 123| 860| UniqueID(uint64_t Device, uint64_t File) : Device(Device), File(File) {} _ZNK7llvm_ks3sys2fs8UniqueIDeqERKS2_: 124| 430| bool operator==(const UniqueID &Other) const { 125| 430| return Device == Other.Device && File == Other.File; ------------------ | Branch (125:12): [True: 430, False: 0] | Branch (125:38): [True: 430, False: 0] ------------------ 126| 430| } _ZN7llvm_ks3sys2fs11file_statusC2Ev: 161| 860| file_status() : fs_st_dev(0), fs_st_ino(0), fs_st_mtime(0), 162| 860| fs_st_uid(0), fs_st_gid(0), fs_st_size(0), 163| 860| Type(file_type::status_error), Perms(perms_not_known) {} _ZN7llvm_ks3sys2fs11file_statusC2ENS1_9file_typeENS1_5permsEmmljjl: 171| 860| : fs_st_dev(Dev), fs_st_ino(Ino), fs_st_mtime(MTime), fs_st_uid(UID), 172| 860| fs_st_gid(GID), fs_st_size(Size), Type(Type), Perms(Perms) {} _ZN7llvm_ks6isUIntILj32EEEbm: 302| 288|inline bool isUInt<32>(uint64_t x) { 303| 288| return static_cast(x) == x; 304| 288|} _ZN7llvm_ks7isUIntNEjm: 315| 4.53k|inline bool isUIntN(unsigned N, uint64_t x) { 316| 4.53k| return N >= 64 || x < (UINT64_C(1)<<(N)); ------------------ | Branch (316:10): [True: 668, False: 3.87k] | Branch (316:21): [True: 3.86k, False: 2] ------------------ 317| 4.53k|} _ZN7llvm_ks6isIntNEjl: 321| 2|inline bool isIntN(unsigned N, int64_t x) { 322| 2| return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1))); ------------------ | Branch (322:10): [True: 0, False: 2] | Branch (322:22): [True: 0, False: 2] | Branch (322:51): [True: 0, False: 0] ------------------ 323| 2|} _ZN7llvm_ks13isPowerOf2_32Ej: 354| 10|inline bool isPowerOf2_32(uint32_t Value) { 355| 10| return Value && !(Value & (Value - 1)); ------------------ | Branch (355:10): [True: 10, False: 0] | Branch (355:19): [True: 10, False: 0] ------------------ 356| 10|} _ZN7llvm_ks13isPowerOf2_64Em: 360| 94.8k|inline bool isPowerOf2_64(uint64_t Value) { 361| 94.8k| return Value && !(Value & (Value - int64_t(1L))); ------------------ | Branch (361:10): [True: 94.8k, False: 0] | Branch (361:19): [True: 94.7k, False: 64] ------------------ 362| 94.8k|} _ZN7llvm_ks7Log2_32Ej: 468| 10|inline unsigned Log2_32(uint32_t Value) { 469| 10| return 31 - countLeadingZeros(Value); 470| 10|} _ZN7llvm_ks9alignAddrEPKvm: 565| 94.6k|inline uintptr_t alignAddr(const void *Addr, size_t Alignment) { 566| 94.6k| assert(Alignment && isPowerOf2_64((uint64_t)Alignment) && ------------------ | Branch (566:3): [True: 94.6k, False: 0] | Branch (566:3): [True: 94.6k, False: 0] | Branch (566:3): [True: 94.6k, Folded] | Branch (566:3): [True: 94.6k, False: 0] ------------------ 567| 94.6k| "Alignment is not a power of two!"); 568| | 569| 94.6k| assert((uintptr_t)Addr + Alignment - 1 >= (uintptr_t)Addr); ------------------ | Branch (569:3): [True: 94.6k, False: 0] ------------------ 570| | 571| 94.6k| return (((uintptr_t)Addr + Alignment - 1) & ~(uintptr_t)(Alignment - 1)); 572| 94.6k|} _ZN7llvm_ks19alignmentAdjustmentEPKvm: 576| 88.7k|inline size_t alignmentAdjustment(const void *Ptr, size_t Alignment) { 577| 88.7k| return alignAddr(Ptr, Alignment) - (uintptr_t)Ptr; 578| 88.7k|} _ZN7llvm_ks12NextPowerOf2Em: 582| 1.47k|inline uint64_t NextPowerOf2(uint64_t A) { 583| 1.47k| A |= (A >> 1); 584| 1.47k| A |= (A >> 2); 585| 1.47k| A |= (A >> 4); 586| 1.47k| A |= (A >> 8); 587| 1.47k| A |= (A >> 16); 588| 1.47k| A |= (A >> 32); 589| 1.47k| return A + 1; 590| 1.47k|} _ZN7llvm_ks7alignToEmmm: 619| 2.33k|inline uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew = 0) { 620| 2.33k| Skew %= Align; 621| 2.33k| return (Value + Align - 1 - Skew) / Align * Align + Skew; 622| 2.33k|} _ZN7llvm_ks17OffsetToAlignmentEmm: 627| 1.40k|inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) { 628| 1.40k| return alignTo(Value, Align) - Value; 629| 1.40k|} _ZN7llvm_ks17countLeadingZerosIjEEmT_NS_12ZeroBehaviorE: 178| 52|std::size_t countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) { 179| 52| static_assert(std::numeric_limits::is_integer && 180| 52| !std::numeric_limits::is_signed, 181| 52| "Only unsigned integral types are allowed."); 182| 52| return detail::LeadingZerosCounter::count(Val, ZB); 183| 52|} _ZN7llvm_ks6detail19LeadingZerosCounterIjLm4EE5countEjNS_12ZeroBehaviorE: 137| 52| static std::size_t count(T Val, ZeroBehavior ZB) { 138| 52| if (ZB != ZB_Undefined && Val == 0) ------------------ | Branch (138:9): [True: 52, False: 0] | Branch (138:31): [True: 0, False: 52] ------------------ 139| 0| return 32; 140| | 141| 52|#if __has_builtin(__builtin_clz) || LLVM_GNUC_PREREQ(4, 0, 0) 142| 52| return __builtin_clz(Val); 143| |#elif defined(_MSC_VER) 144| | unsigned long Index; 145| | _BitScanReverse(&Index, Val); 146| | return Index ^ 31; 147| |#endif 148| 52| } _ZN7llvm_ks17countLeadingZerosImEEmT_NS_12ZeroBehaviorE: 178| 37.4k|std::size_t countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) { 179| 37.4k| static_assert(std::numeric_limits::is_integer && 180| 37.4k| !std::numeric_limits::is_signed, 181| 37.4k| "Only unsigned integral types are allowed."); 182| 37.4k| return detail::LeadingZerosCounter::count(Val, ZB); 183| 37.4k|} _ZN7llvm_ks6detail19LeadingZerosCounterImLm8EE5countEmNS_12ZeroBehaviorE: 153| 37.4k| static std::size_t count(T Val, ZeroBehavior ZB) { 154| 37.4k| if (ZB != ZB_Undefined && Val == 0) ------------------ | Branch (154:9): [True: 21.0k, False: 16.3k] | Branch (154:31): [True: 2.11k, False: 18.9k] ------------------ 155| 2.11k| return 64; 156| | 157| 35.3k|#if __has_builtin(__builtin_clzll) || LLVM_GNUC_PREREQ(4, 0, 0) 158| 35.3k| return __builtin_clzll(Val); 159| |#elif defined(_MSC_VER) 160| | unsigned long Index; 161| | _BitScanReverse64(&Index, Val); 162| | return Index ^ 63; 163| |#endif 164| 37.4k| } _ZN7llvm_ks18countTrailingZerosImEEmT_NS_12ZeroBehaviorE: 109| 4.00k|std::size_t countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) { 110| 4.00k| static_assert(std::numeric_limits::is_integer && 111| 4.00k| !std::numeric_limits::is_signed, 112| 4.00k| "Only unsigned integral types are allowed."); 113| 4.00k| return detail::TrailingZerosCounter::count(Val, ZB); 114| 4.00k|} _ZN7llvm_ks6detail20TrailingZerosCounterImLm8EE5countEmNS_12ZeroBehaviorE: 84| 4.00k| static std::size_t count(T Val, ZeroBehavior ZB) { 85| 4.00k| if (ZB != ZB_Undefined && Val == 0) ------------------ | Branch (85:9): [True: 0, False: 4.00k] | Branch (85:31): [True: 0, False: 0] ------------------ 86| 0| return 64; 87| | 88| 4.00k|#if __has_builtin(__builtin_ctzll) || LLVM_GNUC_PREREQ(4, 0, 0) 89| 4.00k| return __builtin_ctzll(Val); 90| |#elif defined(_MSC_VER) 91| | unsigned long Index; 92| | _BitScanForward64(&Index, Val); 93| | return Index; 94| |#endif 95| 4.00k| } _ZN7llvm_ks15countPopulationImEEjT_: 449| 1.45k|inline unsigned countPopulation(T Value) { 450| 1.45k| static_assert(std::numeric_limits::is_integer && 451| 1.45k| !std::numeric_limits::is_signed, 452| 1.45k| "Only unsigned integral types are allowed."); 453| 1.45k| return detail::PopulationCounter::count(Value); 454| 1.45k|} _ZN7llvm_ks6detail17PopulationCounterImLm8EE5countEm: 431| 1.45k| static unsigned count(T Value) { 432| 1.45k|#if __GNUC__ >= 4 433| 1.45k| return __builtin_popcountll(Value); 434| |#else 435| | uint64_t v = Value; 436| | v = v - ((v >> 1) & 0x5555555555555555ULL); 437| | v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL); 438| | v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL; 439| | return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56); 440| |#endif 441| 1.45k| } _ZN7llvm_ks12findFirstSetImEET_S1_NS_12ZeroBehaviorE: 192| 4.00k|template T findFirstSet(T Val, ZeroBehavior ZB = ZB_Max) { 193| 4.00k| if (ZB == ZB_Max && Val == 0) ------------------ | Branch (193:7): [True: 4.00k, False: 0] | Branch (193:23): [True: 0, False: 4.00k] ------------------ 194| 0| return std::numeric_limits::max(); 195| | 196| 4.00k| return countTrailingZeros(Val, ZB_Undefined); 197| 4.00k|} _ZN7llvm_ks11findLastSetImEET_S1_NS_12ZeroBehaviorE: 206| 16.3k|template T findLastSet(T Val, ZeroBehavior ZB = ZB_Max) { 207| 16.3k| if (ZB == ZB_Max && Val == 0) ------------------ | Branch (207:7): [True: 16.3k, False: 0] | Branch (207:23): [True: 0, False: 16.3k] ------------------ 208| 0| return std::numeric_limits::max(); 209| | 210| | // Use ^ instead of - because both gcc and llvm can remove the associated ^ 211| | // in the __builtin_clz intrinsic on x86. 212| 16.3k| return countLeadingZeros(Val, ZB_Undefined) ^ 213| 16.3k| (std::numeric_limits::digits - 1); 214| 16.3k|} _ZN7llvm_ks18countTrailingZerosIjEEmT_NS_12ZeroBehaviorE: 109| 198|std::size_t countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) { 110| 198| static_assert(std::numeric_limits::is_integer && 111| 198| !std::numeric_limits::is_signed, 112| 198| "Only unsigned integral types are allowed."); 113| 198| return detail::TrailingZerosCounter::count(Val, ZB); 114| 198|} _ZN7llvm_ks6detail20TrailingZerosCounterIjLm4EE5countEjNS_12ZeroBehaviorE: 68| 198| static std::size_t count(T Val, ZeroBehavior ZB) { 69| 198| if (ZB != ZB_Undefined && Val == 0) ------------------ | Branch (69:9): [True: 198, False: 0] | Branch (69:31): [True: 0, False: 198] ------------------ 70| 0| return 32; 71| | 72| 198|#if __has_builtin(__builtin_ctz) || LLVM_GNUC_PREREQ(4, 0, 0) 73| 198| return __builtin_ctz(Val); 74| |#elif defined(_MSC_VER) 75| | unsigned long Index; 76| | _BitScanForward(&Index, Val); 77| | return Index; 78| |#endif 79| 198| } _ZN7llvm_ks12MemoryBufferC2Ev: 43| 1.36k| MemoryBuffer() {} _ZNK7llvm_ks12MemoryBuffer14getBufferStartEv: 49| 14.9k| const char *getBufferStart() const { return BufferStart; } _ZNK7llvm_ks12MemoryBuffer12getBufferEndEv: 50| 9.00k| const char *getBufferEnd() const { return BufferEnd; } _ZNK7llvm_ks12MemoryBuffer13getBufferSizeEv: 51| 2.29k| size_t getBufferSize() const { return BufferEnd-BufferStart; } _ZNK7llvm_ks12MemoryBuffer9getBufferEv: 53| 2.29k| StringRef getBuffer() const { 54| 2.29k| return StringRef(BufferStart, getBufferSize()); 55| 2.29k| } _ZNK7llvm_ks3sys4path14const_iteratordeEv: 61| 860| reference operator*() const { return Component; } _ZNK7llvm_ks3sys4path14const_iteratorptEv: 62| 430| pointer operator->() const { return &Component; } _ZNK7llvm_ks3sys4path14const_iteratorneERKS2_: 65| 430| bool operator!=(const const_iterator &RHS) const { return !(*this == RHS); } _ZN7llvm_ks21PointerLikeTypeTraitsIPNS_10MCFragmentEE16getAsVoidPointerES2_: 41| 7.09k| static inline void *getAsVoidPointer(T *P) { return P; } _ZN7llvm_ks21PointerLikeTypeTraitsIPNS_10MCFragmentEE18getFromVoidPointerEPv: 42| 24.8k| static inline T *getFromVoidPointer(void *P) { return static_cast(P); } _ZN7llvm_ks21PointerLikeTypeTraitsIPKNS_8MCSymbolEE16getAsVoidPointerES3_: 68| 319| static inline const void *getAsVoidPointer(const T *P) { 69| 319| return NonConst::getAsVoidPointer(const_cast(P)); 70| 319| } _ZN7llvm_ks21PointerLikeTypeTraitsIPNS_8MCSymbolEE16getAsVoidPointerES2_: 41| 319| static inline void *getAsVoidPointer(T *P) { return P; } _ZN7llvm_ks5SMLocC2Ev: 27| 818k| SMLoc() : Ptr(nullptr) {} _ZNK7llvm_ks5SMLoc7isValidEv: 29| 2.44k| bool isValid() const { return Ptr != nullptr; } _ZNK7llvm_ks5SMLoceqERKS0_: 31| 99| bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; } _ZNK7llvm_ks5SMLocneERKS0_: 32| 335k| bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; } _ZNK7llvm_ks5SMLoc10getPointerEv: 34| 62.6k| const char *getPointer() const { return Ptr; } _ZN7llvm_ks5SMLoc14getFromPointerEPKc: 36| 574k| static SMLoc getFromPointer(const char *Ptr) { 37| 574k| SMLoc L; 38| 574k| L.Ptr = Ptr; 39| 574k| return L; 40| 574k| } _ZN7llvm_ks9SourceMgrC2Ev: 80| 430| : LineNoCache(nullptr), DiagHandler(nullptr), DiagContext(nullptr) {} _ZN7llvm_ks9SourceMgr12clearBuffersEv: 121| 430| void clearBuffers() { 122| 430| Buffers.clear(); 123| 430| } _ZN7llvm_ks9SourceMgr18AddNewSourceBufferENSt3__110unique_ptrINS_12MemoryBufferENS1_14default_deleteIS3_EEEENS_5SMLocE: 128| 1.36k| SMLoc IncludeLoc) { 129| 1.36k| SrcBuffer NB; 130| 1.36k| NB.Buffer = std::move(F); 131| 1.36k| NB.IncludeLoc = IncludeLoc; 132| 1.36k| Buffers.push_back(std::move(NB)); 133| 1.36k| return Buffers.size(); 134| 1.36k| } _ZN7llvm_ks9SourceMgr9SrcBufferC2Ev: 55| 1.36k| SrcBuffer() {} _ZN7llvm_ks9SourceMgr9SrcBufferC2EOS1_: 58| 2.79k| : Buffer(std::move(O.Buffer)), IncludeLoc(O.IncludeLoc) {} _ZNK7llvm_ks9SourceMgr15isValidBufferIDEj: 74| 7.70k| bool isValidBufferID(unsigned i) const { return i && i <= Buffers.size(); } ------------------ | Branch (74:51): [True: 7.70k, False: 0] | Branch (74:56): [True: 7.70k, False: 0] ------------------ _ZN7llvm_ks9SourceMgr14setDiagHandlerEPFvRKNS_12SMDiagnosticEPvES4_: 89| 860| void setDiagHandler(DiagHandlerTy DH, void *Ctx = nullptr) { 90| 860| DiagHandler = DH; 91| 860| DiagContext = Ctx; 92| 860| } _ZNK7llvm_ks9SourceMgr14getDiagHandlerEv: 94| 430| DiagHandlerTy getDiagHandler() const { return DiagHandler; } _ZNK7llvm_ks9SourceMgr14getDiagContextEv: 95| 430| void *getDiagContext() const { return DiagContext; } _ZNK7llvm_ks9SourceMgr15getMemoryBufferEj: 102| 7.25k| const MemoryBuffer *getMemoryBuffer(unsigned i) const { 103| 7.25k| assert(isValidBufferID(i)); ------------------ | Branch (103:5): [True: 7.25k, False: 0] ------------------ 104| 7.25k| return Buffers[i - 1].Buffer.get(); 105| 7.25k| } _ZNK7llvm_ks9SourceMgr13getNumBuffersEv: 107| 3.03k| unsigned getNumBuffers() const { 108| 3.03k| return Buffers.size(); 109| 3.03k| } _ZNK7llvm_ks9SourceMgr13getMainFileIDEv: 111| 2.60k| unsigned getMainFileID() const { 112| 2.60k| assert(getNumBuffers()); ------------------ | Branch (112:5): [True: 2.60k, False: 0] ------------------ 113| 2.60k| return 1; 114| 2.60k| } _ZNK7llvm_ks9SourceMgr19getParentIncludeLocEj: 116| 458| SMLoc getParentIncludeLoc(unsigned i) const { 117| 458| assert(isValidBufferID(i)); ------------------ | Branch (117:5): [True: 458, False: 0] ------------------ 118| 458| return Buffers[i - 1].IncludeLoc; 119| 458| } _ZNK7llvm_ks9SourceMgr14FindLineNumberENS_5SMLocEj: 152| 608| unsigned FindLineNumber(SMLoc Loc, unsigned BufferID = 0) const { 153| 608| return getLineAndColumn(Loc, BufferID).first; 154| 608| } _ZNK7llvm_ks12SMDiagnostic12getSourceMgrEv: 263| 2.47k| const SourceMgr *getSourceMgr() const { return SM; } _ZNK7llvm_ks12SMDiagnostic6getLocEv: 264| 2.47k| SMLoc getLoc() const { return Loc; } _ZNK7llvm_ks12SMDiagnostic11getColumnNoEv: 267| 304| int getColumnNo() const { return ColumnNo; } _ZNK7llvm_ks12SMDiagnostic7getKindEv: 268| 304| SourceMgr::DiagKind getKind() const { return Kind; } _ZNK7llvm_ks12SMDiagnostic10getMessageEv: 269| 304| StringRef getMessage() const { return Message; } _ZNK7llvm_ks12SMDiagnostic15getLineContentsEv: 270| 304| StringRef getLineContents() const { return LineContents; } _ZNK7llvm_ks12SMDiagnostic9getRangesEv: 271| 304| ArrayRef > getRanges() const { 272| 304| return Ranges; 273| 304| } _ZN7llvm_ks11StringSaverC2ERNS_20BumpPtrAllocatorImplINS_15MallocAllocatorELm4096ELm4096EEE: 25| 430| StringSaver(BumpPtrAllocator &Alloc) : Alloc(Alloc) {} _ZN7llvm_ks3sys16SwapByteOrder_16Et: 28| 9|inline uint16_t SwapByteOrder_16(uint16_t value) { 29| |#if defined(_MSC_VER) && !defined(_DEBUG) 30| | // The DLL version of the runtime lacks these functions (bug!?), but in a 31| | // release build they're replaced with BSWAP instructions anyway. 32| | return _byteswap_ushort(value); 33| |#else 34| 9| uint16_t Hi = value << 8; 35| 9| uint16_t Lo = value >> 8; 36| 9| return Hi | Lo; 37| 9|#endif 38| 9|} _ZN7llvm_ks3sys15getSwappedBytesEt: 74| 9|inline unsigned short getSwappedBytes(unsigned short C) { return SwapByteOrder_16(C); } _ZN7llvm_ks3sys13swapByteOrderItEEvRT_: 118| 9|inline void swapByteOrder(T &Value) { 119| 9| Value = getSwappedBytes(Value); 120| 9|} _ZNK7llvm_ks6Target15createMCRegInfoENS_9StringRefE: 260| 430| MCRegisterInfo *createMCRegInfo(StringRef TT) const { 261| 430| if (!MCRegInfoCtorFn) ------------------ | Branch (261:9): [True: 0, False: 430] ------------------ 262| 0| return nullptr; 263| 430| return MCRegInfoCtorFn(Triple(TT)); 264| 430| } _ZNK7llvm_ks6Target15createMCAsmInfoERKNS_14MCRegisterInfoENS_9StringRefE: 236| 430| StringRef TheTriple) const { 237| 430| if (!MCAsmInfoCtorFn) ------------------ | Branch (237:9): [True: 0, False: 430] ------------------ 238| 0| return nullptr; 239| 430| return MCAsmInfoCtorFn(MRI, Triple(TheTriple)); 240| 430| } _ZNK7llvm_ks6Target17createMCInstrInfoEv: 244| 430| MCInstrInfo *createMCInstrInfo() const { 245| 430| if (!MCInstrInfoCtorFn) ------------------ | Branch (245:9): [True: 0, False: 430] ------------------ 246| 0| return nullptr; 247| 430| return MCInstrInfoCtorFn(); 248| 430| } _ZNK7llvm_ks6Target21createMCSubtargetInfoENS_9StringRefES1_S1_: 276| 430| StringRef Features) const { 277| 430| if (!MCSubtargetInfoCtorFn) ------------------ | Branch (277:9): [True: 0, False: 430] ------------------ 278| 0| return nullptr; 279| 430| return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features); 280| 430| } _ZNK7llvm_ks6Target18createMCAsmBackendERKNS_14MCRegisterInfoENS_9StringRefES4_: 301| 430| StringRef TheTriple, StringRef CPU) const { 302| 430| if (!MCAsmBackendCtorFn) ------------------ | Branch (302:9): [True: 0, False: 430] ------------------ 303| 0| return nullptr; 304| 430| return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU); 305| 430| } _ZNK7llvm_ks6Target19createMCCodeEmitterERKNS_11MCInstrInfoERKNS_14MCRegisterInfoERNS_9MCContextE: 338| 430| MCContext &Ctx) const { 339| 430| if (!MCCodeEmitterCtorFn) ------------------ | Branch (339:9): [True: 0, False: 430] ------------------ 340| 0| return nullptr; 341| 430| return MCCodeEmitterCtorFn(II, MRI, Ctx); 342| 430| } _ZNK7llvm_ks6Target22createMCObjectStreamerERKNS_6TripleERNS_9MCContextERNS_12MCAsmBackendERNS_17raw_pwrite_streamEPNS_13MCCodeEmitterERKNS_15MCSubtargetInfoEbb: 356| 430| bool DWARFMustBeAtTheEnd) const { 357| 430| MCStreamer *S; 358| 430| switch (T.getObjectFormat()) { 359| 0| default: ------------------ | Branch (359:5): [True: 0, False: 430] ------------------ 360| 0| llvm_unreachable("Unknown object format"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 361| 430| case Triple::ELF: ------------------ | Branch (361:5): [True: 430, False: 0] ------------------ 362| 430| if (ELFStreamerCtorFn) ------------------ | Branch (362:11): [True: 0, False: 430] ------------------ 363| 0| S = ELFStreamerCtorFn(T, Ctx, TAB, OS, Emitter, RelaxAll); 364| 430| else 365| 430| S = createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll); 366| 430| break; 367| 430| } 368| 430| if (ObjectTargetStreamerCtorFn) ------------------ | Branch (368:9): [True: 0, False: 430] ------------------ 369| 0| ObjectTargetStreamerCtorFn(*S, STI); 370| 430| return S; 371| 430| } _ZNK7llvm_ks6Target17createMCAsmParserERKNS_15MCSubtargetInfoERNS_11MCAsmParserERKNS_11MCInstrInfoERKNS_15MCTargetOptionsE: 320| 430| const MCTargetOptions &Options) const { 321| 430| if (!MCAsmParserCtorFn) ------------------ | Branch (321:9): [True: 0, False: 430] ------------------ 322| 0| return nullptr; 323| 430| return MCAsmParserCtorFn(STI, Parser, MII, Options); 324| 430| } _ZN7llvm_ks6TargetC2Ev: 198| 46| : ELFStreamerCtorFn(nullptr), NullTargetStreamerCtorFn(nullptr), 199| 46| AsmTargetStreamerCtorFn(nullptr), ObjectTargetStreamerCtorFn(nullptr), 200| 46| MCRelocationInfoCtorFn(nullptr) {} _ZNK7llvm_ks6Target7getNextEv: 206| 9.89k| const Target *getNext() const { return Next; } _ZN7llvm_ks14TargetRegistry8iteratorC2EPNS_6TargetE: 420| 3.01k| explicit iterator(Target *T) : Current(T) {} _ZN7llvm_ks14TargetRegistry8iteratorC2Ev: 424| 3.01k| iterator() : Current(nullptr) {} _ZNK7llvm_ks14TargetRegistry8iteratoreqERKS1_: 426| 11.6k| bool operator==(const iterator &x) const { return Current == x.Current; } _ZNK7llvm_ks14TargetRegistry8iteratorneERKS1_: 427| 10.7k| bool operator!=(const iterator &x) const { return !operator==(x); } _ZN7llvm_ks14TargetRegistry8iteratorppEv: 430| 9.89k| iterator &operator++() { // Preincrement 431| 9.89k| assert(Current && "Cannot increment end iterator!"); ------------------ | Branch (431:7): [True: 9.89k, False: 0] | Branch (431:7): [True: 9.89k, Folded] | Branch (431:7): [True: 9.89k, False: 0] ------------------ 432| 9.89k| Current = Current->getNext(); 433| 9.89k| return *this; 434| 9.89k| } _ZNK7llvm_ks14TargetRegistry8iteratordeEv: 441| 10.3k| const Target &operator*() const { 442| 10.3k| assert(Current && "Cannot dereference end iterator!"); ------------------ | Branch (442:7): [True: 10.3k, False: 0] | Branch (442:7): [True: 10.3k, Folded] | Branch (442:7): [True: 10.3k, False: 0] ------------------ 443| 10.3k| return *Current; 444| 10.3k| } _ZN7llvm_ks14TargetRegistry17RegisterMCAsmInfoERNS_6TargetEPFPNS_9MCAsmInfoERKNS_14MCRegisterInfoERKNS_6TripleEE: 508| 23| static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) { 509| 23| T.MCAsmInfoCtorFn = Fn; 510| 23| } _ZN7llvm_ks14TargetRegistry19RegisterMCInstrInfoERNS_6TargetEPFPNS_11MCInstrInfoEvE: 521| 23| static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) { 522| 23| T.MCInstrInfoCtorFn = Fn; 523| 23| } _ZN7llvm_ks14TargetRegistry17RegisterMCRegInfoERNS_6TargetEPFPNS_14MCRegisterInfoERKNS_6TripleEE: 541| 23| static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) { 542| 23| T.MCRegInfoCtorFn = Fn; 543| 23| } _ZN7llvm_ks14TargetRegistry23RegisterMCSubtargetInfoERNS_6TargetEPFPNS_15MCSubtargetInfoERKNS_6TripleENS_9StringRefES8_E: 555| 23| Target::MCSubtargetInfoCtorFnTy Fn) { 556| 23| T.MCSubtargetInfoCtorFn = Fn; 557| 23| } _ZN7llvm_ks14TargetRegistry20RegisterMCAsmBackendERNS_6TargetEPFPNS_12MCAsmBackendERKS1_RKNS_14MCRegisterInfoERKNS_6TripleENS_9StringRefEE: 581| 21| static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) { 582| 21| T.MCAsmBackendCtorFn = Fn; 583| 21| } _ZN7llvm_ks14TargetRegistry21RegisterMCAsmBackend2ERNS_6TargetEPFPNS_12MCAsmBackendERKS1_RKNS_14MCRegisterInfoERKNS_6TripleENS_9StringRefERKNS_15MCSubtargetInfoERKNS_15MCTargetOptionsEE: 584| 2| static void RegisterMCAsmBackend2(Target &T, Target::MCAsmBackendCtorTy2 Fn) { 585| 2| T.MCAsmBackendCtorFn2 = Fn; 586| 2| } _ZN7llvm_ks14TargetRegistry19RegisterMCAsmParserERNS_6TargetEPFPNS_17MCTargetAsmParserERKNS_15MCSubtargetInfoERNS_11MCAsmParserERKNS_11MCInstrInfoERKNS_15MCTargetOptionsEE: 597| 23| static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn) { 598| 23| T.MCAsmParserCtorFn = Fn; 599| 23| } _ZN7llvm_ks14TargetRegistry21RegisterMCCodeEmitterERNS_6TargetEPFPNS_13MCCodeEmitterERKNS_11MCInstrInfoERKNS_14MCRegisterInfoERNS_9MCContextEE: 623| 23| static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn) { 624| 23| T.MCCodeEmitterCtorFn = Fn; 625| 23| } _ZN7llvm_ks14TargetRegistry25RegisterAsmTargetStreamerERNS_6TargetEPFPNS_16MCTargetStreamerERNS_10MCStreamerERNS_21formatted_raw_ostreamEE: 637| 2| Target::AsmTargetStreamerCtorTy Fn) { 638| 2| T.AsmTargetStreamerCtorFn = Fn; 639| 2| } _ZN7llvm_ks14TargetRegistry28RegisterObjectTargetStreamerERNS_6TargetEPFPNS_16MCTargetStreamerERNS_10MCStreamerERKNS_15MCSubtargetInfoEE: 643| 2| Target::ObjectTargetStreamerCtorTy Fn) { 644| 2| T.ObjectTargetStreamerCtorFn = Fn; 645| 2| } _ZN7llvm_ks14TargetRegistry24RegisterMCRelocationInfoERNS_6TargetEPFPNS_16MCRelocationInfoERKNS_6TripleERNS_9MCContextEE: 657| 2| Target::MCRelocationInfoCtorTy Fn) { 658| 2| T.MCRelocationInfoCtorFn = Fn; 659| 2| } _ZN7llvm_ks19RegisterMCAsmInfoFnC2ERNS_6TargetEPFPNS_9MCAsmInfoERKNS_14MCRegisterInfoERKNS_6TripleEE: 715| 20| RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) { 716| 20| TargetRegistry::RegisterMCAsmInfo(T, Fn); 717| 20| } AArch64AsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_116AArch64AsmParserEEC2ERNS_6TargetE: 900| 3| RegisterMCAsmParser(Target &T) { 901| 3| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 3| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE3EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE3EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE4EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE4EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } ARMAsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_112ARMAsmParserEEC2ERNS_6TargetE: 900| 4| RegisterMCAsmParser(Target &T) { 901| 4| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 4| } ARMAsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_112ARMAsmParserEE9AllocatorERKNS_15MCSubtargetInfoERNS_11MCAsmParserERKNS_11MCInstrInfoERKNS_15MCTargetOptionsE: 907| 430| const MCTargetOptions &Options) { 908| 430| return new MCAsmParserImpl(STI, P, MII, Options); 909| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE1EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE1EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE2EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE2EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE26EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE26EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE27EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE27EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } HexagonAsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_116HexagonAsmParserEEC2ERNS_6TargetE: 900| 1| RegisterMCAsmParser(Target &T) { 901| 1| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE8EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE8EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } MipsAsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_113MipsAsmParserEEC2ERNS_6TargetE: 900| 4| RegisterMCAsmParser(Target &T) { 901| 4| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 4| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE9EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE9EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE10EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE10EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE11EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE11EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE12EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE12EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } PPCAsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_112PPCAsmParserEEC2ERNS_6TargetE: 900| 3| RegisterMCAsmParser(Target &T) { 901| 3| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 3| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE14EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE14EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE15EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE15EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE16EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE16EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } SparcAsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_114SparcAsmParserEEC2ERNS_6TargetE: 900| 3| RegisterMCAsmParser(Target &T) { 901| 3| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 3| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE21EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE21EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE22EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE22EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE23EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE23EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } SystemZAsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_116SystemZAsmParserEEC2ERNS_6TargetE: 900| 1| RegisterMCAsmParser(Target &T) { 901| 1| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE24EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE24EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } X86AsmParser.cpp:_ZN7llvm_ks19RegisterMCAsmParserIN12_GLOBAL__N_112X86AsmParserEEC2ERNS_6TargetE: 900| 2| RegisterMCAsmParser(Target &T) { 901| 2| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 2| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE28EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE28EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE29EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE29EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks19RegisterMCAsmParserINS_14RISCVAsmParserEEC2ERNS_6TargetE: 900| 2| RegisterMCAsmParser(Target &T) { 901| 2| TargetRegistry::RegisterMCAsmParser(T, &Allocator); 902| 2| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE18EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE18EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE19EEC2ERNS_6TargetEPKcS7_: 677| 1| RegisterTarget(Target &T, const char *Name, const char *Desc) { 678| 1| TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch); 679| 1| } _ZN7llvm_ks14RegisterTargetILNS_6Triple8ArchTypeE19EE12getArchMatchES2_: 681| 430| static bool getArchMatch(Triple::ArchType Arch) { 682| 430| return Arch == TargetArchType; 683| 430| } _ZN7llvm_ks24InitializeAllTargetInfosEv: 44| 1| inline void InitializeAllTargetInfos() { 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); 46| 1|#include "llvm/Config/Targets.def" ------------------ | | 1| |/*===- llvm/Config/Targets.def - LLVM Target Architectures ------*- C++ -*-===*\ | | 2| ||* *| | | 3| ||* The LLVM Compiler Infrastructure *| | | 4| ||* *| | | 5| ||* This file is distributed under the University of Illinois Open Source *| | | 6| ||* License. See LICENSE.TXT for details. *| | | 7| ||* *| | | 8| ||*===----------------------------------------------------------------------===*| | | 9| ||* *| | | 10| ||* This file enumerates all of the target architectures supported by *| | | 11| ||* this build of LLVM. Clients of this file should define the *| | | 12| ||* LLVM_TARGET macro to be a function-like macro with a single *| | | 13| ||* parameter (the name of the target); including this file will then *| | | 14| ||* enumerate all of the targets. *| | | 15| ||* *| | | 16| ||* The set of targets supported by LLVM is generated at configuration *| | | 17| ||* time, at which point this header is generated. Do not modify this *| | | 18| ||* header directly. *| | | 19| ||* *| | | 20| |\*===----------------------------------------------------------------------===*/ | | 21| | | | 22| |#ifndef LLVM_TARGET | | 23| |# error Please define the macro LLVM_TARGET(TargetName) | | 24| |#endif | | 25| | | | 26| 1|LLVM_TARGET(AArch64) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 27| 1|LLVM_TARGET(ARM) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 28| 1|LLVM_TARGET(Hexagon) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 29| 1|LLVM_TARGET(Mips) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 30| 1|LLVM_TARGET(PowerPC) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 31| 1|LLVM_TARGET(Sparc) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 32| 1|LLVM_TARGET(SystemZ) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 33| 1|LLVM_TARGET(X86) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 34| 1|LLVM_TARGET(RISCV) | | ------------------ | | | | 45| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); | | ------------------ | | 35| | | | 36| | | | 37| 1|#undef LLVM_TARGET ------------------ 47| 1| } _ZN7llvm_ks22InitializeAllTargetMCsEv: 67| 1| inline void InitializeAllTargetMCs() { 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); 69| 1|#include "llvm/Config/Targets.def" ------------------ | | 1| |/*===- llvm/Config/Targets.def - LLVM Target Architectures ------*- C++ -*-===*\ | | 2| ||* *| | | 3| ||* The LLVM Compiler Infrastructure *| | | 4| ||* *| | | 5| ||* This file is distributed under the University of Illinois Open Source *| | | 6| ||* License. See LICENSE.TXT for details. *| | | 7| ||* *| | | 8| ||*===----------------------------------------------------------------------===*| | | 9| ||* *| | | 10| ||* This file enumerates all of the target architectures supported by *| | | 11| ||* this build of LLVM. Clients of this file should define the *| | | 12| ||* LLVM_TARGET macro to be a function-like macro with a single *| | | 13| ||* parameter (the name of the target); including this file will then *| | | 14| ||* enumerate all of the targets. *| | | 15| ||* *| | | 16| ||* The set of targets supported by LLVM is generated at configuration *| | | 17| ||* time, at which point this header is generated. Do not modify this *| | | 18| ||* header directly. *| | | 19| ||* *| | | 20| |\*===----------------------------------------------------------------------===*/ | | 21| | | | 22| |#ifndef LLVM_TARGET | | 23| |# error Please define the macro LLVM_TARGET(TargetName) | | 24| |#endif | | 25| | | | 26| 1|LLVM_TARGET(AArch64) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 27| 1|LLVM_TARGET(ARM) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 28| 1|LLVM_TARGET(Hexagon) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 29| 1|LLVM_TARGET(Mips) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 30| 1|LLVM_TARGET(PowerPC) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 31| 1|LLVM_TARGET(Sparc) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 32| 1|LLVM_TARGET(SystemZ) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 33| 1|LLVM_TARGET(X86) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 34| 1|LLVM_TARGET(RISCV) | | ------------------ | | | | 68| 1|#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); | | ------------------ | | 35| | | | 36| | | | 37| 1|#undef LLVM_TARGET ------------------ 70| 1| } _ZN7llvm_ks23InitializeAllAsmParsersEv: 85| 1| inline void InitializeAllAsmParsers() { 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); 87| 1|#include "llvm/Config/AsmParsers.def" ------------------ | | 1| |/*===- llvm/Config/AsmParsers.def - LLVM Assembly Parsers -------*- C++ -*-===*\ | | 2| ||* *| | | 3| ||* The LLVM Compiler Infrastructure *| | | 4| ||* *| | | 5| ||* This file is distributed under the University of Illinois Open Source *| | | 6| ||* License. See LICENSE.TXT for details. *| | | 7| ||* *| | | 8| ||*===----------------------------------------------------------------------===*| | | 9| ||* *| | | 10| ||* This file enumerates all of the assembly-language parsers *| | | 11| ||* supported by this build of LLVM. Clients of this file should define *| | | 12| ||* the LLVM_ASM_PARSER macro to be a function-like macro with a *| | | 13| ||* single parameter (the name of the target whose assembly can be *| | | 14| ||* generated); including this file will then enumerate all of the *| | | 15| ||* targets with assembly parsers. *| | | 16| ||* *| | | 17| ||* The set of targets supported by LLVM is generated at configuration *| | | 18| ||* time, at which point this header is generated. Do not modify this *| | | 19| ||* header directly. *| | | 20| ||* *| | | 21| |\*===----------------------------------------------------------------------===*/ | | 22| | | | 23| |#ifndef LLVM_ASM_PARSER | | 24| |# error Please define the macro LLVM_ASM_PARSER(TargetName) | | 25| |#endif | | 26| | | | 27| 1|LLVM_ASM_PARSER(AArch64) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 28| 1|LLVM_ASM_PARSER(ARM) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 29| 1|LLVM_ASM_PARSER(Hexagon) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 30| 1|LLVM_ASM_PARSER(Mips) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 31| 1|LLVM_ASM_PARSER(PowerPC) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 32| 1|LLVM_ASM_PARSER(Sparc) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 33| 1|LLVM_ASM_PARSER(SystemZ) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 34| 1|LLVM_ASM_PARSER(X86) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 35| 1|LLVM_ASM_PARSER(RISCV) | | ------------------ | | | | 86| 1|#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); | | ------------------ | | 36| | | | 37| | | | 38| 1|#undef LLVM_ASM_PARSER ------------------ 88| 1| } _ZN7llvm_ks19raw_svector_ostreamC2ERNS_15SmallVectorImplIcEE: 493| 21.9k| explicit raw_svector_ostream(SmallVectorImpl &O) : OS(O) { 494| 21.9k| SetUnbuffered(); 495| 21.9k| } _ZN7llvm_ks17raw_pwrite_streamC2Eb: 325| 21.9k| : raw_ostream(Unbuffered) {} _ZN7llvm_ks11raw_ostreamC2Eb: 84| 21.9k| : BufferMode(unbuffered ? Unbuffered : InternalBuffer) { ------------------ | Branch (84:20): [True: 1, False: 21.9k] ------------------ 85| | // Start out ready to flush. 86| 21.9k| OutBufStart = OutBufEnd = OutBufCur = nullptr; 87| 21.9k| } _ZN7llvm_ks11raw_ostream13SetUnbufferedEv: 121| 21.9k| void SetUnbuffered() { 122| 21.9k| flush(); 123| 21.9k| SetBufferAndMode(nullptr, 0, Unbuffered); 124| 21.9k| } _ZN7llvm_ks11raw_ostream5flushEv: 134| 21.9k| void flush() { 135| 21.9k| if (OutBufCur != OutBufStart) ------------------ | Branch (135:9): [True: 0, False: 21.9k] ------------------ 136| 0| flush_nonempty(); 137| 21.9k| } _ZNK7llvm_ks11raw_ostream4tellEv: 92| 3.95k| uint64_t tell() const { return current_pos() + GetNumBytesInBuffer(); } _ZNK7llvm_ks11raw_ostream19GetNumBytesInBufferEv: 126| 25.9k| size_t GetNumBytesInBuffer() const { 127| 25.9k| return OutBufCur - OutBufStart; 128| 25.9k| } _ZN7llvm_ks11raw_ostreamlsEc: 139| 79.0k| raw_ostream &operator<<(char C) { 140| 79.0k| if (OutBufCur >= OutBufEnd) ------------------ | Branch (140:9): [True: 79.0k, False: 0] ------------------ 141| 79.0k| return write(C); 142| 0| *OutBufCur++ = C; 143| 0| return *this; 144| 79.0k| } _ZN7llvm_ks11raw_ostreamlsENS_9StringRefE: 160| 42.4k| raw_ostream &operator<<(StringRef Str) { 161| | // Inline fast path, particularly for strings with a known length. 162| 42.4k| size_t Size = Str.size(); 163| | 164| | // Make sure we can use the fast path. 165| 42.4k| if (Size > (size_t)(OutBufEnd - OutBufCur)) ------------------ | Branch (165:9): [True: 42.1k, False: 328] ------------------ 166| 42.1k| return write(Str.data(), Size); 167| | 168| 328| if (Size) { ------------------ | Branch (168:9): [True: 0, False: 328] ------------------ 169| 0| memcpy(OutBufCur, Str.data(), Size); 170| 0| OutBufCur += Size; 171| 0| } 172| 328| return *this; 173| 42.4k| } _ZN7llvm_ks11raw_ostreamlsEPKc: 175| 25.0k| raw_ostream &operator<<(const char *Str) { 176| | // Inline fast path, particularly for constant strings where a sufficiently 177| | // smart compiler will simplify strlen. 178| | 179| 25.0k| return this->operator<<(StringRef(Str)); 180| 25.0k| } _ZN7llvm_ks11raw_ostreamlsERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE: 182| 3.13k| raw_ostream &operator<<(const std::string &Str) { 183| | // Avoid the fast path, it would only increase code size for a marginal win. 184| 3.13k| return write(Str.data(), Str.length()); 185| 3.13k| } _ZN7llvm_ks11raw_ostreamlsEj: 196| 5.46k| raw_ostream &operator<<(unsigned int N) { 197| 5.46k| return this->operator<<(static_cast(N)); 198| 5.46k| } _ZN7llvm_ks11raw_ostreamlsEi: 200| 198| raw_ostream &operator<<(int N) { 201| 198| return this->operator<<(static_cast(N)); 202| 198| } _ZNK7llvm_ks14raw_fd_ostream9has_errorEv: 415| 1| bool has_error() const { 416| 1| return Error; 417| 1| } _ZN7llvm_ks19raw_svector_ostream3strEv: 501| 932| StringRef str() { return StringRef(OS.data(), OS.size()); } ks_errno: 42| 286|{ 43| 286| return (ks_err)ks->errnum; 44| 286|} ks_open: 261| 430|{ 262| 430| struct ks_struct *ks; 263| 430| std::string TripleName = ""; 264| | 265| 430| if (arch < KS_ARCH_MAX) { ------------------ | Branch (265:9): [True: 430, False: 0] ------------------ 266| | // LLVM-based architectures 267| 430| ks = new (std::nothrow) ks_struct(arch, mode, KS_ERR_OK, KS_OPT_SYNTAX_INTEL); 268| | 269| 430| if (!ks) { ------------------ | Branch (269:13): [True: 0, False: 430] ------------------ 270| | // memory insufficient 271| 0| return KS_ERR_NOMEM; 272| 0| } 273| | 274| 430| switch(arch) { 275| 0| default: break; ------------------ | Branch (275:13): [True: 0, False: 430] ------------------ 276| | 277| 0|#ifdef LLVM_ENABLE_ARCH_ARM 278| 430| case KS_ARCH_ARM: ------------------ | Branch (278:13): [True: 430, False: 0] ------------------ 279| 430| if (mode & ~KS_MODE_ARM_MASK) { ------------------ | | 23| 430|#define KS_MODE_ARM_MASK (KS_MODE_ARM|KS_MODE_THUMB|KS_MODE_LITTLE_ENDIAN|KS_MODE_BIG_ENDIAN|KS_MODE_V8) ------------------ | Branch (279:21): [True: 0, False: 430] ------------------ 280| 0| delete ks; 281| 0| return KS_ERR_MODE; 282| 0| } 283| | 284| 430| switch(mode) { 285| 0| default: ------------------ | Branch (285:21): [True: 0, False: 430] ------------------ 286| 0| return KS_ERR_MODE; 287| | // big-endian 288| 0| case KS_MODE_BIG_ENDIAN | KS_MODE_V8 | KS_MODE_ARM: ------------------ | Branch (288:21): [True: 0, False: 430] ------------------ 289| 0| TripleName = "armv8eb"; 290| 0| break; 291| 430| case KS_MODE_BIG_ENDIAN | KS_MODE_V8 | KS_MODE_THUMB: ------------------ | Branch (291:21): [True: 430, False: 0] ------------------ 292| 430| TripleName = "thumbv8eb"; 293| 430| break; 294| 0| case KS_MODE_BIG_ENDIAN | KS_MODE_ARM: ------------------ | Branch (294:21): [True: 0, False: 430] ------------------ 295| 0| TripleName = "armv7eb"; 296| 0| break; 297| 0| case KS_MODE_BIG_ENDIAN | KS_MODE_THUMB: ------------------ | Branch (297:21): [True: 0, False: 430] ------------------ 298| 0| TripleName = "thumbebv7"; 299| 0| break; 300| | 301| | // little-endian 302| 0| case KS_MODE_LITTLE_ENDIAN | KS_MODE_V8 | KS_MODE_ARM: ------------------ | Branch (302:21): [True: 0, False: 430] ------------------ 303| 0| TripleName = "armv8"; 304| 0| break; 305| 0| case KS_MODE_LITTLE_ENDIAN | KS_MODE_V8 | KS_MODE_THUMB: ------------------ | Branch (305:21): [True: 0, False: 430] ------------------ 306| 0| TripleName = "thumbv8"; 307| 0| break; 308| 0| case KS_MODE_LITTLE_ENDIAN | KS_MODE_ARM: ------------------ | Branch (308:21): [True: 0, False: 430] ------------------ 309| 0| TripleName = "armv7"; 310| 0| break; 311| 0| case KS_MODE_LITTLE_ENDIAN | KS_MODE_THUMB: ------------------ | Branch (311:21): [True: 0, False: 430] ------------------ 312| 0| TripleName = "thumbv7"; 313| 0| break; 314| 430| } 315| | 316| 430| InitKs(arch, ks, TripleName); 317| | 318| | //ks->init_arch = arm_ks_init; 319| 430| break; 320| 0|#endif 321| | 322| 0|#ifdef LLVM_ENABLE_ARCH_AArch64 323| 0| case KS_ARCH_ARM64: ------------------ | Branch (323:13): [True: 0, False: 430] ------------------ 324| 0| if (mode != KS_MODE_LITTLE_ENDIAN) { ------------------ | Branch (324:21): [True: 0, False: 0] ------------------ 325| 0| delete ks; 326| 0| return KS_ERR_MODE; 327| 0| } 328| | 329| 0| TripleName = "aarch64"; 330| 0| InitKs(arch, ks, TripleName); 331| | 332| | //ks->init_arch = arm64_ks_init; 333| 0| break; 334| 0|#endif 335| | 336| 0|#ifdef LLVM_ENABLE_ARCH_Hexagon 337| 0| case KS_ARCH_HEXAGON: ------------------ | Branch (337:13): [True: 0, False: 430] ------------------ 338| 0| if (mode & ~KS_MODE_HEXAGON_MASK) { ------------------ | | 28| 0|#define KS_MODE_HEXAGON_MASK (KS_MODE_BIG_ENDIAN) ------------------ | Branch (338:21): [True: 0, False: 0] ------------------ 339| 0| delete ks; 340| 0| return KS_ERR_MODE; 341| 0| } 342| | 343| 0| TripleName = "hexagon"; 344| | 345| 0| InitKs(arch, ks, TripleName); 346| | 347| | //ks->init_arch = arm_ks_init; 348| 0| break; 349| 0|#endif 350| | 351| 0|#ifdef LLVM_ENABLE_ARCH_SystemZ 352| 0| case KS_ARCH_SYSTEMZ: ------------------ | Branch (352:13): [True: 0, False: 430] ------------------ 353| 0| if (mode & ~KS_MODE_SYSTEMZ_MASK) { ------------------ | | 29| 0|#define KS_MODE_SYSTEMZ_MASK (KS_MODE_BIG_ENDIAN) ------------------ | Branch (353:21): [True: 0, False: 0] ------------------ 354| 0| delete ks; 355| 0| return KS_ERR_MODE; 356| 0| } 357| | 358| 0| TripleName = "s390x"; 359| | 360| 0| InitKs(arch, ks, TripleName); 361| | 362| | //ks->init_arch = arm_ks_init; 363| 0| break; 364| 0|#endif 365| | 366| 0|#ifdef LLVM_ENABLE_ARCH_Sparc 367| 0| case KS_ARCH_SPARC: ------------------ | Branch (367:13): [True: 0, False: 430] ------------------ 368| 0| if ((mode & ~KS_MODE_SPARC_MASK) || ------------------ | | 27| 0|#define KS_MODE_SPARC_MASK (KS_MODE_V9|KS_MODE_SPARC32|KS_MODE_SPARC64|KS_MODE_LITTLE_ENDIAN|KS_MODE_BIG_ENDIAN) ------------------ | Branch (368:21): [True: 0, False: 0] ------------------ 369| 0| !(mode & (KS_MODE_SPARC32|KS_MODE_SPARC64))) { ------------------ | Branch (369:25): [True: 0, False: 0] ------------------ 370| 0| delete ks; 371| 0| return KS_ERR_MODE; 372| 0| } 373| 0| if (mode & KS_MODE_BIG_ENDIAN) { ------------------ | Branch (373:21): [True: 0, False: 0] ------------------ 374| | // big endian 375| 0| if (mode & KS_MODE_SPARC64) ------------------ | Branch (375:25): [True: 0, False: 0] ------------------ 376| 0| TripleName = "sparc64"; 377| 0| else 378| 0| TripleName = "sparc"; 379| 0| } else { 380| | // little endian 381| 0| if (mode & KS_MODE_SPARC64) { ------------------ | Branch (381:25): [True: 0, False: 0] ------------------ 382| | // TripleName = "sparc64el"; 383| | // FIXME 384| 0| delete ks; 385| 0| return KS_ERR_MODE; 386| 0| } else 387| 0| TripleName = "sparcel"; 388| 0| } 389| | 390| 0| InitKs(arch, ks, TripleName); 391| | 392| 0| break; 393| 0|#endif 394| | 395| 0|#ifdef LLVM_ENABLE_ARCH_RISCV 396| 0| case KS_ARCH_RISCV: { ------------------ | Branch (396:13): [True: 0, False: 430] ------------------ 397| 0| if ((mode & ~KS_MODE_RISCV_MASK) || ------------------ | | 32| 0|#define KS_MODE_RISCV_MASK (KS_MODE_RISCV32|KS_MODE_RISCV64|KS_MODE_LITTLE_ENDIAN) ------------------ | Branch (397:21): [True: 0, False: 0] ------------------ 398| 0| (mode & KS_MODE_BIG_ENDIAN) || ------------------ | Branch (398:25): [True: 0, False: 0] ------------------ 399| 0| !(mode & (KS_MODE_RISCV32|KS_MODE_RISCV64))) { ------------------ | Branch (399:25): [True: 0, False: 0] ------------------ 400| 0| delete ks; 401| 0| return KS_ERR_MODE; 402| 0| } 403| | 404| 0| switch(mode) { 405| 0| default: break; ------------------ | Branch (405:21): [True: 0, False: 0] ------------------ 406| 0| case KS_MODE_RISCV32: ------------------ | Branch (406:21): [True: 0, False: 0] ------------------ 407| 0| TripleName = "riscv32"; 408| 0| break; 409| 0| case KS_MODE_RISCV64: ------------------ | Branch (409:21): [True: 0, False: 0] ------------------ 410| 0| TripleName = "riscv64"; 411| 0| break; 412| 0| } 413| | 414| 0| InitKs(arch, ks, TripleName); 415| | 416| 0| break; 417| 0| } 418| 0|#endif 419| | 420| 0|#ifdef LLVM_ENABLE_ARCH_Mips 421| 0| case KS_ARCH_MIPS: ------------------ | Branch (421:13): [True: 0, False: 430] ------------------ 422| 0| if ((mode & ~KS_MODE_MIPS_MASK) || ------------------ | | 24| 0|#define KS_MODE_MIPS_MASK (KS_MODE_MIPS32|KS_MODE_MIPS64|KS_MODE_LITTLE_ENDIAN|KS_MODE_BIG_ENDIAN) ------------------ | Branch (422:21): [True: 0, False: 0] ------------------ 423| 0| !(mode & (KS_MODE_MIPS32|KS_MODE_MIPS64))) { ------------------ | Branch (423:25): [True: 0, False: 0] ------------------ 424| 0| delete ks; 425| 0| return KS_ERR_MODE; 426| 0| } 427| 0| if (mode & KS_MODE_BIG_ENDIAN) { ------------------ | Branch (427:21): [True: 0, False: 0] ------------------ 428| | // big endian 429| 0| if (mode & KS_MODE_MIPS32) ------------------ | Branch (429:25): [True: 0, False: 0] ------------------ 430| 0| TripleName = "mips"; 431| 0| if (mode & KS_MODE_MIPS64) ------------------ | Branch (431:25): [True: 0, False: 0] ------------------ 432| 0| TripleName = "mips64"; 433| 0| } else { // little endian 434| 0| if (mode & KS_MODE_MIPS32) ------------------ | Branch (434:25): [True: 0, False: 0] ------------------ 435| 0| TripleName = "mipsel"; 436| 0| if (mode & KS_MODE_MIPS64) ------------------ | Branch (436:25): [True: 0, False: 0] ------------------ 437| 0| TripleName = "mips64el"; 438| 0| } 439| | 440| 0| InitKs(arch, ks, TripleName); 441| | 442| 0| break; 443| 0|#endif 444| | 445| 0|#ifdef LLVM_ENABLE_ARCH_PowerPC 446| 0| case KS_ARCH_PPC: ------------------ | Branch (446:13): [True: 0, False: 430] ------------------ 447| 0| if ((mode & ~KS_MODE_PPC_MASK) || ------------------ | | 26| 0|#define KS_MODE_PPC_MASK (KS_MODE_PPC32|KS_MODE_PPC64|KS_MODE_LITTLE_ENDIAN|KS_MODE_BIG_ENDIAN) ------------------ | Branch (447:21): [True: 0, False: 0] ------------------ 448| 0| !(mode & (KS_MODE_PPC32|KS_MODE_PPC64))) { ------------------ | Branch (448:25): [True: 0, False: 0] ------------------ 449| 0| delete ks; 450| 0| return KS_ERR_MODE; 451| 0| } 452| | 453| 0| if (mode & KS_MODE_BIG_ENDIAN) { ------------------ | Branch (453:21): [True: 0, False: 0] ------------------ 454| | // big endian 455| 0| if (mode & KS_MODE_PPC32) ------------------ | Branch (455:25): [True: 0, False: 0] ------------------ 456| 0| TripleName = "ppc32"; 457| 0| if (mode & KS_MODE_PPC64) ------------------ | Branch (457:25): [True: 0, False: 0] ------------------ 458| 0| TripleName = "ppc64"; 459| 0| } else { // little endian 460| 0| if (mode & KS_MODE_PPC32) { ------------------ | Branch (460:25): [True: 0, False: 0] ------------------ 461| | // do not support this mode 462| 0| delete ks; 463| 0| return KS_ERR_MODE; 464| 0| } 465| 0| if (mode & KS_MODE_MIPS64) ------------------ | Branch (465:25): [True: 0, False: 0] ------------------ 466| 0| TripleName = "ppc64le"; 467| 0| } 468| | 469| 0| InitKs(arch, ks, TripleName); 470| | 471| | //ks->init_arch = ppc_ks_init; 472| 0| break; 473| 0|#endif 474| | 475| 0|#ifdef LLVM_ENABLE_ARCH_X86 476| 0| case KS_ARCH_X86: { ------------------ | Branch (476:13): [True: 0, False: 430] ------------------ 477| 0| if ((mode & ~KS_MODE_X86_MASK) || ------------------ | | 25| 0|#define KS_MODE_X86_MASK (KS_MODE_16|KS_MODE_32|KS_MODE_64|KS_MODE_LITTLE_ENDIAN) ------------------ | Branch (477:21): [True: 0, False: 0] ------------------ 478| 0| (mode & KS_MODE_BIG_ENDIAN) || ------------------ | Branch (478:25): [True: 0, False: 0] ------------------ 479| 0| !(mode & (KS_MODE_16|KS_MODE_32|KS_MODE_64))) { ------------------ | Branch (479:25): [True: 0, False: 0] ------------------ 480| 0| delete ks; 481| 0| return KS_ERR_MODE; 482| 0| } 483| | 484| 0| switch(mode) { 485| 0| default: break; ------------------ | Branch (485:21): [True: 0, False: 0] ------------------ 486| 0| case KS_MODE_16: ------------------ | Branch (486:21): [True: 0, False: 0] ------------------ 487| | // FIXME 488| 0| TripleName = "i386-unknown-unknown-code16"; 489| 0| break; 490| 0| case KS_MODE_32: ------------------ | Branch (490:21): [True: 0, False: 0] ------------------ 491| | // FIXME 492| 0| TripleName = "i386"; 493| 0| break; 494| 0| case KS_MODE_64: ------------------ | Branch (494:21): [True: 0, False: 0] ------------------ 495| | // FIXME 496| 0| TripleName = "x86_64"; 497| 0| break; 498| 0| } 499| | 500| 0| InitKs(arch, ks, TripleName); 501| | 502| | //ks->init_arch = x86_ks_init; 503| 0| break; 504| 0| } 505| 0|#endif 506| 0|#ifdef LLVM_ENABLE_ARCH_EVM 507| 0| case KS_ARCH_EVM: { ------------------ | Branch (507:13): [True: 0, False: 430] ------------------ 508| 0| *result = ks; 509| 0| return KS_ERR_OK; 510| 0| } 511| 430|#endif 512| 430| } 513| | 514| 430| if (TripleName.empty()) { ------------------ | Branch (514:13): [True: 0, False: 430] ------------------ 515| | // this arch is not supported 516| 0| delete ks; 517| 0| return KS_ERR_ARCH; 518| 0| } 519| | 520| 430| *result = ks; 521| | 522| 430| return KS_ERR_OK; 523| 430| } else 524| 0| return KS_ERR_ARCH; 525| 430|} ks_close: 530| 430|{ 531| 430| if (!ks) ------------------ | Branch (531:9): [True: 0, False: 430] ------------------ 532| 0| return KS_ERR_HANDLE; 533| | 534| 430| if (ks->arch == KS_ARCH_EVM) { ------------------ | Branch (534:9): [True: 0, False: 430] ------------------ 535| | // handle EVM differently 536| 0| delete ks; 537| 0| return KS_ERR_OK; 538| 0| } 539| | 540| | // LLVM-based architectures 541| 430| delete ks->STI; 542| 430| delete ks->MCII; 543| 430| delete ks->MAI; 544| 430| delete ks->MRI; 545| 430| delete ks->MAB; 546| | 547| | // finally, free ks itself. 548| 430| delete ks; 549| | 550| 430| return KS_ERR_OK; 551| 430|} ks_option: 556| 430|{ 557| 430| ks->MAI->setRadix(16); 558| 430| switch(type) { ------------------ | Branch (558:12): [True: 430, False: 0] ------------------ 559| 430| case KS_OPT_SYNTAX: ------------------ | Branch (559:9): [True: 430, False: 0] ------------------ 560| 430| if (ks->arch != KS_ARCH_X86) ------------------ | Branch (560:17): [True: 430, False: 0] ------------------ 561| 430| return KS_ERR_OPT_INVALID; 562| 0| switch(value) { 563| 0| default: ------------------ | Branch (563:17): [True: 0, False: 0] ------------------ 564| 0| return KS_ERR_OPT_INVALID; 565| 0| case KS_OPT_SYNTAX_RADIX16: // default syntax is Intel ------------------ | Branch (565:17): [True: 0, False: 0] ------------------ 566| 0| case KS_OPT_SYNTAX_NASM | KS_OPT_SYNTAX_RADIX16: ------------------ | Branch (566:17): [True: 0, False: 0] ------------------ 567| 0| case KS_OPT_SYNTAX_INTEL | KS_OPT_SYNTAX_RADIX16: ------------------ | Branch (567:17): [True: 0, False: 0] ------------------ 568| 0| ks->MAI->setRadix(16); 569| 0| case KS_OPT_SYNTAX_NASM: ------------------ | Branch (569:17): [True: 0, False: 0] ------------------ 570| 0| case KS_OPT_SYNTAX_INTEL: ------------------ | Branch (570:17): [True: 0, False: 0] ------------------ 571| 0| ks->syntax = (ks_opt_value)value; 572| 0| ks->MAI->setAssemblerDialect(1); 573| 0| break; 574| 0| case KS_OPT_SYNTAX_GAS | KS_OPT_SYNTAX_RADIX16: ------------------ | Branch (574:17): [True: 0, False: 0] ------------------ 575| 0| case KS_OPT_SYNTAX_ATT | KS_OPT_SYNTAX_RADIX16: ------------------ | Branch (575:17): [True: 0, False: 0] ------------------ 576| 0| ks->MAI->setRadix(16); 577| 0| case KS_OPT_SYNTAX_GAS: ------------------ | Branch (577:17): [True: 0, False: 0] ------------------ 578| 0| case KS_OPT_SYNTAX_ATT: ------------------ | Branch (578:17): [True: 0, False: 0] ------------------ 579| 0| ks->syntax = (ks_opt_value)value; 580| 0| ks->MAI->setAssemblerDialect(0); 581| 0| break; 582| 0| } 583| | 584| 0| return KS_ERR_OK; 585| 0| case KS_OPT_SYM_RESOLVER: ------------------ | Branch (585:9): [True: 0, False: 430] ------------------ 586| 0| ks->sym_resolver = (ks_sym_resolver)value; 587| 0| return KS_ERR_OK; 588| 430| } 589| | 590| 0| return KS_ERR_OPT_INVALID; 591| 430|} ks_free: 596| 144|{ 597| 144| free(p); 598| 144|} ks_asm: 610| 430|{ 611| 430| MCCodeEmitter *CE; 612| 430| MCStreamer *Streamer; 613| 430| unsigned char *encoding; 614| 430| SmallString<1024> Msg; 615| 430| raw_svector_ostream OS(Msg); 616| | 617| 430| if (ks->arch == KS_ARCH_EVM) { ------------------ | Branch (617:9): [True: 0, False: 430] ------------------ 618| | // handle EVM differently 619| 0| unsigned short opcode = EVM_opcode(assembly); 620| 0| if (opcode == (unsigned short)-1) { ------------------ | Branch (620:13): [True: 0, False: 0] ------------------ 621| | // invalid instruction 622| 0| return -1; 623| 0| } 624| | 625| 0| *insn_size = 1; 626| 0| *stat_count = 1; 627| 0| encoding = (unsigned char *)malloc(*insn_size); 628| 0| encoding[0] = opcode; 629| 0| *insn = encoding; 630| 0| return 0; 631| 0| } 632| | 633| 430| *insn = NULL; 634| 430| *insn_size = 0; 635| | 636| 430| MCContext Ctx(ks->MAI, ks->MRI, &ks->MOFI, &ks->SrcMgr, true, address); 637| 430| ks->MOFI.InitMCObjectFileInfo(Triple(ks->TripleName), Ctx); 638| 430| CE = ks->TheTarget->createMCCodeEmitter(*ks->MCII, *ks->MRI, Ctx); 639| 430| if (!CE) { ------------------ | Branch (639:9): [True: 0, False: 430] ------------------ 640| | // memory insufficient 641| 0| return KS_ERR_NOMEM; 642| 0| } 643| 430| Streamer = ks->TheTarget->createMCObjectStreamer( 644| 430| Triple(ks->TripleName), Ctx, *ks->MAB, OS, CE, *ks->STI, ks->MCOptions.MCRelaxAll, 645| 430| /*DWARFMustBeAtTheEnd*/ false); 646| | 647| 430| if (!Streamer) { ------------------ | Branch (647:9): [True: 0, False: 430] ------------------ 648| | // memory insufficient 649| 0| delete CE; 650| 0| return KS_ERR_NOMEM; 651| 0| } 652| | 653| | // Tell SrcMgr about this buffer, which is what the parser will pick up. 654| 430| ErrorOr> BufferPtr = MemoryBuffer::getMemBuffer(assembly); 655| 430| if (BufferPtr.getError()) { ------------------ | Branch (655:9): [True: 0, False: 430] ------------------ 656| 0| delete Streamer; 657| 0| delete CE; 658| 0| return KS_ERR_NOMEM; 659| 0| } 660| | 661| 430| ks->SrcMgr.clearBuffers(); 662| 430| ks->SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc()); 663| | 664| 430| Streamer->setSymResolver((void *)(ks->sym_resolver)); 665| | 666| 430| MCAsmParser *Parser = createMCAsmParser(ks->SrcMgr, Ctx, *Streamer, *ks->MAI); 667| 430| if (!Parser) { ------------------ | Branch (667:9): [True: 0, False: 430] ------------------ 668| 0| delete Streamer; 669| 0| delete CE; 670| | // memory insufficient 671| 0| return KS_ERR_NOMEM; 672| 0| } 673| 430| MCTargetAsmParser *TAP = ks->TheTarget->createMCAsmParser(*ks->STI, *Parser, *ks->MCII, ks->MCOptions); 674| 430| if (!TAP) { ------------------ | Branch (674:9): [True: 0, False: 430] ------------------ 675| | // memory insufficient 676| 0| delete Parser; 677| 0| delete Streamer; 678| 0| delete CE; 679| 0| return KS_ERR_NOMEM; 680| 0| } 681| 430| TAP->KsSyntax = ks->syntax; 682| | 683| 430| Parser->setTargetParser(*TAP); 684| | 685| | // TODO: optimize this to avoid setting up NASM every time we call ks_asm() 686| 430| if (ks->arch == KS_ARCH_X86 && ks->syntax == KS_OPT_SYNTAX_NASM) { ------------------ | Branch (686:9): [True: 0, False: 430] | Branch (686:36): [True: 0, False: 0] ------------------ 687| 0| Parser->initializeDirectiveKindMap(KS_OPT_SYNTAX_NASM); 688| 0| ks->MAI->setCommentString(";"); 689| 0| } 690| | 691| 430| *stat_count = Parser->Run(false, address); 692| | 693| | // PPC counts empty statement 694| 430| if (ks->arch == KS_ARCH_PPC) ------------------ | Branch (694:9): [True: 0, False: 430] ------------------ 695| 0| *stat_count = *stat_count / 2; 696| | 697| 430| ks->errnum = Parser->KsError; 698| | 699| 430| delete TAP; 700| 430| delete Parser; 701| 430| delete CE; 702| 430| delete Streamer; 703| | 704| 430| if (ks->errnum >= KS_ERR_ASM) ------------------ | | 103| 430|#define KS_ERR_ASM 128 ------------------ | Branch (704:9): [True: 286, False: 144] ------------------ 705| 286| return -1; 706| 144| else { 707| 144| *insn_size = Msg.size(); 708| 144| encoding = (unsigned char *)malloc(*insn_size); 709| 144| if (!encoding) { ------------------ | Branch (709:13): [True: 0, False: 144] ------------------ 710| 0| return KS_ERR_NOMEM; 711| 0| } 712| 144| memcpy(encoding, Msg.data(), *insn_size); 713| 144| *insn = encoding; 714| 144| return 0; 715| 144| } 716| 430|} ks.cpp:_ZL6InitKsiP9ks_structNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE: 204| 430|{ 205| 430| static bool initialized = false; 206| 430| std::string MCPU = ""; 207| | 208| 430| if (!initialized) { ------------------ | Branch (208:9): [True: 1, False: 429] ------------------ 209| 1| initialized = true; 210| | // Initialize targets and assembly parsers. 211| 1| llvm_ks::InitializeAllTargetInfos(); 212| 1| llvm_ks::InitializeAllTargetMCs(); 213| 1| llvm_ks::InitializeAllAsmParsers(); 214| 1| } 215| | 216| 430| ks->TripleName = Triple::normalize(TripleName); 217| 430| ks->TheTarget = GetTarget(ks->TripleName); 218| 430| if (!ks->TheTarget) ------------------ | Branch (218:9): [True: 0, False: 430] ------------------ 219| 0| return KS_ERR_MODE; // FIXME 220| | 221| | // Now that GetTarget() has (potentially) replaced TripleName, it's safe to 222| | // construct the Triple object. 223| 430| Triple TheTriple(ks->TripleName); 224| | 225| 430| ks->MRI = ks->TheTarget->createMCRegInfo(ks->TripleName); 226| 430| assert(ks->MRI && "Unable to create target register info!"); ------------------ | Branch (226:5): [True: 430, False: 0] | Branch (226:5): [True: 430, Folded] | Branch (226:5): [True: 430, False: 0] ------------------ 227| | 228| | // Package up features to be passed to target/subtarget 229| |#if 0 230| | if (MAttrs.size()) { 231| | SubtargetFeatures Features; 232| | for (unsigned i = 0; i != MAttrs.size(); ++i) 233| | Features.AddFeature(MAttrs[i]); 234| | ks->FeaturesStr = Features.getString(); 235| | } 236| |#endif 237| | 238| 430| ks->MAI = ks->TheTarget->createMCAsmInfo(*ks->MRI, ks->TripleName); 239| 430| assert(ks->MAI && "Unable to create target asm info!"); ------------------ | Branch (239:5): [True: 430, False: 0] | Branch (239:5): [True: 430, Folded] | Branch (239:5): [True: 430, False: 0] ------------------ 240| | 241| | // enable Knights Landing architecture for X86 242| 430| if (ks->arch == KS_ARCH_X86) ------------------ | Branch (242:9): [True: 0, False: 430] ------------------ 243| 0| MCPU = "knl"; 244| | 245| 430| ks->MCII = ks->TheTarget->createMCInstrInfo(); 246| 430| ks->STI = ks->TheTarget->createMCSubtargetInfo(ks->TripleName, MCPU, ks->FeaturesStr); 247| 430| if(ks->TripleName.rfind("riscv",0)==0){ ------------------ | Branch (247:8): [True: 0, False: 430] ------------------ 248| 0| ks->MAB = ks->TheTarget->createMCAsmBackend2(*ks->MRI, ks->TripleName, MCPU, *ks->STI, ks->MCOptions); 249| 430| } else { 250| 430| ks->MAB = ks->TheTarget->createMCAsmBackend(*ks->MRI, ks->TripleName, MCPU); 251| 430| } 252| 430| ks->MAB->setArch(arch); 253| 430| ks->MCOptions = InitMCTargetOptionsFromFlags(); 254| | 255| 430| return KS_ERR_OK; 256| 430|} ks.cpp:_ZL9GetTargetNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEE: 192| 430|{ 193| | // Figure out the target triple. 194| 430| Triple TheTriple(TripleName); 195| | 196| | // Get the target specific parser. 197| 430| std::string Error; 198| | 199| 430| return TargetRegistry::lookupTarget("", TheTriple, Error); 200| 430|} _ZN9ks_structC2E7ks_archij12ks_opt_value: 63| 430| : arch(arch), mode(mode), errnum(errnum), syntax(syntax) { } _ZN7llvm_ks12ConstantPool11emitEntriesERNS_10MCStreamerE: 24| 5|void ConstantPool::emitEntries(MCStreamer &Streamer) { 25| 5| if (Entries.empty()) ------------------ | Branch (25:7): [True: 0, False: 5] ------------------ 26| 0| return; 27| 5| Streamer.EmitDataRegion(MCDR_DataRegion); 28| 5| for (EntryVecTy::const_iterator I = Entries.begin(), E = Entries.end(); 29| 464| I != E; ++I) { ------------------ | Branch (29:8): [True: 459, False: 5] ------------------ 30| 459| Streamer.EmitCodeAlignment(I->Size); // align naturally 31| 459| Streamer.EmitLabel(I->Label); 32| 459| Streamer.EmitValue(I->Value, I->Size, I->Loc); 33| 459| } 34| 5| Streamer.EmitDataRegion(MCDR_DataRegionEnd); 35| 5| Entries.clear(); 36| 5|} _ZN7llvm_ks12ConstantPool8addEntryEPKNS_6MCExprERNS_9MCContextEjNS_5SMLocE: 39| 516| unsigned Size, SMLoc Loc) { 40| 516| MCSymbol *CPEntryLabel = Context.createTempSymbol(); 41| | 42| 516| Entries.push_back(ConstantPoolEntry(CPEntryLabel, Value, Size, Loc)); 43| 516| return MCSymbolRefExpr::create(CPEntryLabel, Context); 44| 516|} _ZN7llvm_ks12ConstantPool5emptyEv: 46| 5|bool ConstantPool::empty() { return Entries.empty(); } _ZN7llvm_ks22AssemblerConstantPools23getOrCreateConstantPoolEPNS_9MCSectionE: 60| 516|AssemblerConstantPools::getOrCreateConstantPool(MCSection *Section) { 61| 516| return ConstantPools[Section]; 62| 516|} _ZN7llvm_ks22AssemblerConstantPools7emitAllERNS_10MCStreamerE: 72| 185|void AssemblerConstantPools::emitAll(MCStreamer &Streamer) { 73| | // Dump contents of assembler constant pools. 74| 185| for (ConstantPoolMapTy::iterator CPI = ConstantPools.begin(), 75| 185| CPE = ConstantPools.end(); 76| 190| CPI != CPE; ++CPI) { ------------------ | Branch (76:8): [True: 5, False: 185] ------------------ 77| 5| MCSection *Section = CPI->first; 78| 5| ConstantPool &CP = CPI->second; 79| | 80| 5| emitConstantPool(Streamer, Section, CP); 81| 5| } 82| 185|} _ZN7llvm_ks22AssemblerConstantPools8addEntryERNS_10MCStreamerEPKNS_6MCExprEjNS_5SMLocE: 93| 516| unsigned Size, SMLoc Loc) { 94| 516| MCSection *Section = Streamer.getCurrentSection().first; 95| 516| return getOrCreateConstantPool(Section).addEntry(Expr, Streamer.getContext(), 96| 516| Size, Loc); 97| 516|} ConstantPools.cpp:_ZL16emitConstantPoolRN7llvm_ks10MCStreamerEPNS_9MCSectionERNS_12ConstantPoolE: 65| 5| ConstantPool &CP) { 66| 5| if (!CP.empty()) { ------------------ | Branch (66:7): [True: 5, False: 0] ------------------ 67| 5| Streamer.SwitchSection(Section); 68| 5| CP.emitEntries(Streamer); 69| 5| } 70| 5|} _ZN7llvm_ks21createELFObjectWriterEPNS_23MCELFObjectTargetWriterERNS_17raw_pwrite_streamEb: 1271| 430| bool IsLittleEndian) { 1272| 430| return new ELFObjectWriter(MOTW, OS, IsLittleEndian); 1273| 430|} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriterC2EPN7llvm_ks23MCELFObjectTargetWriterERNS1_17raw_pwrite_streamEb: 142| 430| : MCObjectWriter(OS, IsLittleEndian), TargetObjectWriter(MOTW) {} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriterD2Ev: 297| 430|{} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriter24executePostLayoutBindingERN7llvm_ks11MCAssemblerERKNS1_11MCAsmLayoutE: 316| 185| const MCAsmLayout &Layout) { 317| | // The presence of symbol versions causes undefined symbols and 318| | // versions declared with @@@ to be renamed. 319| | 320| 1.20k| for (const MCSymbol &A : Asm.symbols()) { ------------------ | Branch (320:26): [True: 1.20k, False: 185] ------------------ 321| 1.20k| const auto &Alias = cast(A); 322| | // Not an alias. 323| 1.20k| if (!Alias.isVariable()) ------------------ | Branch (323:9): [True: 1.06k, False: 142] ------------------ 324| 1.06k| continue; 325| 142| auto *Ref = dyn_cast(Alias.getVariableValue()); 326| 142| if (!Ref) ------------------ | Branch (326:9): [True: 10, False: 132] ------------------ 327| 10| continue; 328| 132| const auto &Symbol = cast(Ref->getSymbol()); 329| | 330| 132| StringRef AliasName = Alias.getName(); 331| 132| size_t Pos = AliasName.find('@'); 332| 132| if (Pos == StringRef::npos) ------------------ | Branch (332:9): [True: 9, False: 123] ------------------ 333| 9| continue; 334| | 335| | // Aliases defined with .symvar copy the binding from the symbol they alias. 336| | // This is the first place we are able to copy this information. 337| 123| Alias.setExternal(Symbol.isExternal()); 338| 123| Alias.setBinding(Symbol.getBinding()); 339| | 340| 123| StringRef Rest = AliasName.substr(Pos); 341| 123| if (!Symbol.isUndefined() && !Rest.startswith("@@@")) ------------------ | Branch (341:9): [True: 1, False: 122] | Branch (341:9): [True: 1, False: 122] | Branch (341:34): [True: 1, False: 0] ------------------ 342| 1| continue; 343| | 344| | // FIXME: produce a better error message. 345| 122| if (Symbol.isUndefined() && Rest.startswith("@@") && ------------------ | Branch (345:9): [True: 122, False: 0] | Branch (345:9): [True: 0, False: 122] | Branch (345:33): [True: 1, False: 121] ------------------ 346| 1| !Rest.startswith("@@@")) ------------------ | Branch (346:9): [True: 0, False: 1] ------------------ 347| 0| report_fatal_error("A @@ version cannot be undefined"); 348| | 349| 122| Renames.insert(std::make_pair(&Symbol, &Alias)); 350| 122| } 351| 185|} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriter16recordRelocationERN7llvm_ks11MCAssemblerERKNS1_11MCAsmLayoutEPKNS1_10MCFragmentERKNS1_7MCFixupENS1_7MCValueERbRm: 557| 115|{ 558| 115| const MCSectionELF &FixupSection = cast(*Fragment->getParent()); 559| 115| uint64_t C = Target.getConstant(); 560| 115| bool valid; 561| 115| uint64_t FixupOffset = Layout.getFragmentOffset(Fragment, valid) + Fixup.getOffset(); 562| 115| MCContext &Ctx = Asm.getContext(); 563| | 564| 115| if (const MCSymbolRefExpr *RefB = Target.getSymB()) { ------------------ | Branch (564:30): [True: 86, False: 29] ------------------ 565| 86| assert(RefB->getKind() == MCSymbolRefExpr::VK_None && ------------------ | Branch (565:5): [True: 86, False: 0] | Branch (565:5): [True: 86, Folded] | Branch (565:5): [True: 86, False: 0] ------------------ 566| 86| "Should not have constructed this"); 567| | 568| | // Let A, B and C being the components of Target and R be the location of 569| | // the fixup. If the fixup is not pcrel, we want to compute (A - B + C). 570| | // If it is pcrel, we want to compute (A - B + C - R). 571| | 572| | // In general, ELF has no relocations for -B. It can only represent (A + C) 573| | // or (A + C - R). If B = R + K and the relocation is not pcrel, we can 574| | // replace B to implement it: (A - R - K + C) 575| 86| if (IsPCRel) { ------------------ | Branch (575:9): [True: 83, False: 3] ------------------ 576| 83| Ctx.reportError( 577| 83| Fixup.getLoc(), 578| 83| "No relocation available to represent this relative expression"); 579| 83| return; 580| 83| } 581| | 582| 3| const auto &SymB = cast(RefB->getSymbol()); 583| | 584| 3| if (SymB.isUndefined()) { ------------------ | Branch (584:9): [True: 2, False: 1] ------------------ 585| 2| Ctx.reportError(Fixup.getLoc(), 586| 2| Twine("symbol '") + SymB.getName() + 587| 2| "' can not be undefined in a subtraction expression"); 588| 2| return; 589| 2| } 590| | 591| 3| assert(!SymB.isAbsolute() && "Should have been folded"); ------------------ | Branch (591:5): [True: 1, False: 0] | Branch (591:5): [True: 1, Folded] | Branch (591:5): [True: 1, False: 0] ------------------ 592| 1| const MCSection &SecB = SymB.getSection(); 593| 1| if (&SecB != &FixupSection) { ------------------ | Branch (593:9): [True: 0, False: 1] ------------------ 594| 0| Ctx.reportError(Fixup.getLoc(), 595| 0| "Cannot represent a difference across sections"); 596| 0| return; 597| 0| } 598| | 599| 1| bool valid; 600| 1| uint64_t SymBOffset = Layout.getSymbolOffset(SymB, valid); 601| 1| uint64_t K = SymBOffset - FixupOffset; 602| 1| IsPCRel = true; 603| 1| C -= K; 604| 1| } 605| | 606| | // We either rejected the fixup or folded B into C at this point. 607| 30| const MCSymbolRefExpr *RefA = Target.getSymA(); 608| 30| const auto *SymA = RefA ? cast(&RefA->getSymbol()) : nullptr; ------------------ | Branch (608:22): [True: 23, False: 7] ------------------ 609| | 610| 30| bool ViaWeakRef = false; 611| 30| if (SymA && SymA->isVariable()) { ------------------ | Branch (611:7): [True: 23, False: 7] | Branch (611:15): [True: 0, False: 23] ------------------ 612| 0| const MCExpr *Expr = SymA->getVariableValue(); 613| 0| if (const auto *Inner = dyn_cast(Expr)) { ------------------ | Branch (613:21): [True: 0, False: 0] ------------------ 614| 0| if (Inner->getKind() == MCSymbolRefExpr::VK_WEAKREF) { ------------------ | Branch (614:11): [True: 0, False: 0] ------------------ 615| 0| SymA = cast(&Inner->getSymbol()); 616| 0| ViaWeakRef = true; 617| 0| } 618| 0| } 619| 0| } 620| | 621| 30| unsigned Type = getRelocType(Ctx, Target, Fixup, IsPCRel); 622| 30| bool RelocateWithSymbol = shouldRelocateWithSymbol(Asm, RefA, SymA, C, Type); 623| 30| if (!RelocateWithSymbol && SymA && !SymA->isUndefined()) { ------------------ | Branch (623:7): [True: 8, False: 22] | Branch (623:30): [True: 1, False: 7] | Branch (623:38): [True: 1, False: 0] ------------------ 624| 1| bool valid; 625| 1| C += Layout.getSymbolOffset(*SymA, valid); 626| 1| } 627| | 628| 30| uint64_t Addend = 0; 629| 30| if (hasRelocationAddend()) { ------------------ | Branch (629:7): [True: 0, False: 30] ------------------ 630| 0| Addend = C; 631| 0| C = 0; 632| 0| } 633| | 634| 30| FixedValue = C; 635| | 636| 30| if (!RelocateWithSymbol) { ------------------ | Branch (636:7): [True: 8, False: 22] ------------------ 637| 8| const MCSection *SecA = 638| 8| (SymA && !SymA->isUndefined()) ? &SymA->getSection() : nullptr; ------------------ | Branch (638:10): [True: 1, False: 7] | Branch (638:18): [True: 1, False: 0] ------------------ 639| 8| auto *ELFSec = cast_or_null(SecA); 640| 8| const auto *SectionSymbol = 641| 8| ELFSec ? cast(ELFSec->getBeginSymbol()) : nullptr; ------------------ | Branch (641:9): [True: 1, False: 7] ------------------ 642| 8| if (SectionSymbol) ------------------ | Branch (642:9): [True: 1, False: 7] ------------------ 643| 1| SectionSymbol->setUsedInReloc(); 644| 8| ELFRelocationEntry Rec(FixupOffset, SectionSymbol, Type, Addend); 645| 8| Relocations[&FixupSection].push_back(Rec); 646| 8| return; 647| 8| } 648| | 649| 22| if (SymA) { ------------------ | Branch (649:7): [True: 22, False: 0] ------------------ 650| 22| if (const MCSymbolELF *R = Renames.lookup(SymA)) ------------------ | Branch (650:28): [True: 0, False: 22] ------------------ 651| 0| SymA = R; 652| | 653| 22| if (ViaWeakRef) ------------------ | Branch (653:9): [True: 0, False: 22] ------------------ 654| 0| SymA->setIsWeakrefUsedInReloc(); 655| 22| else 656| 22| SymA->setUsedInReloc(); 657| 22| } 658| 22| ELFRelocationEntry Rec(FixupOffset, SymA, Type, Addend); 659| 22| Relocations[&FixupSection].push_back(Rec); 660| 22| return; 661| 30|} ELFObjectWriter.cpp:_ZNK12_GLOBAL__N_115ELFObjectWriter12getRelocTypeERN7llvm_ks9MCContextERKNS1_7MCValueERKNS1_7MCFixupEb: 133| 30| const MCFixup &Fixup, bool IsPCRel) const { 134| 30| return TargetObjectWriter->getRelocType(Ctx, Target, Fixup, IsPCRel); 135| 30| } ELFObjectWriter.cpp:_ZNK12_GLOBAL__N_115ELFObjectWriter24shouldRelocateWithSymbolERKN7llvm_ks11MCAssemblerEPKNS1_15MCSymbolRefExprEPKNS1_8MCSymbolEmj: 437| 30| unsigned Type) const { 438| 30| const auto *Sym = cast_or_null(S); 439| | // A PCRel relocation to an absolute value has no symbol (or section). We 440| | // represent that with a relocation to a null section. 441| 30| if (!RefA) ------------------ | Branch (441:7): [True: 7, False: 23] ------------------ 442| 7| return false; 443| | 444| 23| MCSymbolRefExpr::VariantKind Kind = RefA->getKind(); 445| 23| switch (Kind) { 446| 23| default: ------------------ | Branch (446:3): [True: 23, False: 0] ------------------ 447| 23| break; 448| | // The .odp creation emits a relocation against the symbol ".TOC." which 449| | // create a R_PPC64_TOC relocation. However the relocation symbol name 450| | // in final object creation should be NULL, since the symbol does not 451| | // really exist, it is just the reference to TOC base for the current 452| | // object file. Since the symbol is undefined, returning false results 453| | // in a relocation with a null section which is the desired result. 454| 23| case MCSymbolRefExpr::VK_PPC_TOCBASE: ------------------ | Branch (454:3): [True: 0, False: 23] ------------------ 455| 0| return false; 456| | 457| | // These VariantKind cause the relocation to refer to something other than 458| | // the symbol itself, like a linker generated table. Since the address of 459| | // symbol is not relevant, we cannot replace the symbol with the 460| | // section and patch the difference in the addend. 461| 0| case MCSymbolRefExpr::VK_GOT: ------------------ | Branch (461:3): [True: 0, False: 23] ------------------ 462| 0| case MCSymbolRefExpr::VK_PLT: ------------------ | Branch (462:3): [True: 0, False: 23] ------------------ 463| 0| case MCSymbolRefExpr::VK_GOTPCREL: ------------------ | Branch (463:3): [True: 0, False: 23] ------------------ 464| 0| case MCSymbolRefExpr::VK_Mips_GOT: ------------------ | Branch (464:3): [True: 0, False: 23] ------------------ 465| 0| case MCSymbolRefExpr::VK_PPC_GOT_LO: ------------------ | Branch (465:3): [True: 0, False: 23] ------------------ 466| 0| case MCSymbolRefExpr::VK_PPC_GOT_HI: ------------------ | Branch (466:3): [True: 0, False: 23] ------------------ 467| 0| case MCSymbolRefExpr::VK_PPC_GOT_HA: ------------------ | Branch (467:3): [True: 0, False: 23] ------------------ 468| 0| return true; 469| 23| } 470| | 471| | // An undefined symbol is not in any section, so the relocation has to point 472| | // to the symbol itself. 473| 23| assert(Sym && "Expected a symbol"); ------------------ | Branch (473:3): [True: 23, False: 0] | Branch (473:3): [True: 23, Folded] | Branch (473:3): [True: 23, False: 0] ------------------ 474| 23| if (Sym->isUndefined()) ------------------ | Branch (474:7): [True: 0, False: 23] ------------------ 475| 0| return true; 476| | 477| 23| unsigned Binding = Sym->getBinding(); 478| 23| switch(Binding) { 479| 0| default: ------------------ | Branch (479:3): [True: 0, False: 23] ------------------ 480| 0| llvm_unreachable("Invalid Binding"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 481| 23| case ELF::STB_LOCAL: ------------------ | Branch (481:3): [True: 23, False: 0] ------------------ 482| 23| break; 483| 0| case ELF::STB_WEAK: ------------------ | Branch (483:3): [True: 0, False: 23] ------------------ 484| | // If the symbol is weak, it might be overridden by a symbol in another 485| | // file. The relocation has to point to the symbol so that the linker 486| | // can update it. 487| 0| return true; 488| 0| case ELF::STB_GLOBAL: ------------------ | Branch (488:3): [True: 0, False: 23] ------------------ 489| | // Global ELF symbols can be preempted by the dynamic linker. The relocation 490| | // has to point to the symbol for a reason analogous to the STB_WEAK case. 491| 0| return true; 492| 23| } 493| | 494| | // If a relocation points to a mergeable section, we have to be careful. 495| | // If the offset is zero, a relocation with the section will encode the 496| | // same information. With a non-zero offset, the situation is different. 497| | // For example, a relocation can point 42 bytes past the end of a string. 498| | // If we change such a relocation to use the section, the linker would think 499| | // that it pointed to another string and subtracting 42 at runtime will 500| | // produce the wrong value. 501| 23| auto &Sec = cast(Sym->getSection()); 502| 23| unsigned Flags = Sec.getFlags(); 503| 23| if (Flags & ELF::SHF_MERGE) { ------------------ | Branch (503:7): [True: 0, False: 23] ------------------ 504| 0| if (C != 0) ------------------ | Branch (504:9): [True: 0, False: 0] ------------------ 505| 0| return true; 506| | 507| | // It looks like gold has a bug (http://sourceware.org/PR16794) and can 508| | // only handle section relocations to mergeable sections if using RELA. 509| 0| if (!hasRelocationAddend()) ------------------ | Branch (509:9): [True: 0, False: 0] ------------------ 510| 0| return true; 511| 0| } 512| | 513| | // Most TLS relocations use a got, so they need the symbol. Even those that 514| | // are just an offset (@tpoff), require a symbol in gold versions before 515| | // 5efeedf61e4fe720fd3e9a08e6c91c10abb66d42 (2014-09-26) which fixed 516| | // http://sourceware.org/PR16773. 517| 23| if (Flags & ELF::SHF_TLS) ------------------ | Branch (517:7): [True: 0, False: 23] ------------------ 518| 0| return true; 519| | 520| | // If the symbol is a thumb function the final relocation must set the lowest 521| | // bit. With a symbol that is done by just having the symbol have that bit 522| | // set, so we would lose the bit if we relocated with the section. 523| | // FIXME: We could use the section but add the bit to the relocation value. 524| 23| if (Asm.isThumbFunc(Sym)) ------------------ | Branch (524:7): [True: 0, False: 23] ------------------ 525| 0| return true; 526| | 527| 23| if (TargetObjectWriter->needsRelocateWithSymbol(*Sym, Type)) ------------------ | Branch (527:7): [True: 22, False: 1] ------------------ 528| 22| return true; 529| 1| return false; 530| 23|} ELFObjectWriter.cpp:_ZNK12_GLOBAL__N_115ELFObjectWriter19hasRelocationAddendEv: 127| 105| bool hasRelocationAddend() const { 128| | // Keystone doesn't want relocation addends. 129| | /* return TargetObjectWriter->hasRelocationAddend(); */ 130| 105| return false; 131| 105| } ELFObjectWriter.cpp:_ZNK12_GLOBAL__N_115ELFObjectWriter38isSymbolRefDifferenceFullyResolvedImplERKN7llvm_ks11MCAssemblerERKNS1_8MCSymbolERKNS1_10MCFragmentEbb: 1237| 1.25k| bool InSet, bool IsPCRel) const { 1238| 1.25k| const auto &SymA = cast(SA); 1239| 1.25k| if (IsPCRel) { ------------------ | Branch (1239:7): [True: 1.24k, False: 4] ------------------ 1240| 1.24k| assert(!InSet); ------------------ | Branch (1240:5): [True: 1.24k, False: 0] ------------------ 1241| 1.24k| if (::isWeak(SymA)) ------------------ | Branch (1241:9): [True: 0, False: 1.24k] ------------------ 1242| 0| return false; 1243| 1.24k| } 1244| 1.25k| return MCObjectWriter::isSymbolRefDifferenceFullyResolvedImpl(Asm, SymA, FB, 1245| 1.25k| InSet, IsPCRel); 1246| 1.25k|} ELFObjectWriter.cpp:_ZL6isWeakRKN7llvm_ks11MCSymbolELFE: 535| 1.24k|static bool isWeak(const MCSymbolELF &Sym) { 536| 1.24k| if (Sym.getType() == ELF::STT_GNU_IFUNC) ------------------ | Branch (536:7): [True: 0, False: 1.24k] ------------------ 537| 0| return true; 538| | 539| 1.24k| switch (Sym.getBinding()) { 540| 0| default: ------------------ | Branch (540:3): [True: 0, False: 1.24k] ------------------ 541| 0| llvm_unreachable("Unknown binding"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 542| 1.24k| case ELF::STB_LOCAL: ------------------ | Branch (542:3): [True: 1.24k, False: 0] ------------------ 543| 1.24k| return false; 544| 0| case ELF::STB_GLOBAL: ------------------ | Branch (544:3): [True: 0, False: 1.24k] ------------------ 545| 0| return false; 546| 0| case ELF::STB_WEAK: ------------------ | Branch (546:3): [True: 0, False: 1.24k] ------------------ 547| 0| case ELF::STB_GNU_UNIQUE: ------------------ | Branch (547:3): [True: 0, False: 1.24k] ------------------ 548| 0| return true; 549| 1.24k| } 550| 1.24k|} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriter11writeObjectERN7llvm_ks11MCAssemblerERKNS1_11MCAsmLayoutE: 1103| 176|{ 1104| 176| MCContext &Ctx = Asm.getContext(); 1105| 176| MCSectionELF *StrtabSection = 1106| 176| Ctx.getELFSection(".strtab", ELF::SHT_STRTAB, 0); 1107| 176| StringTableIndex = addToSectionTable(StrtabSection); 1108| | 1109| 176| RevGroupMapTy RevGroupMap; 1110| 176| SectionIndexMapTy SectionIndexMap; 1111| | 1112| 176| std::map> GroupMembers; 1113| | 1114| | // ... then the sections ... 1115| 176| SectionOffsetsTy SectionOffsets; 1116| 176| std::vector Groups; 1117| 176| std::vector Relocations; 1118| 178| for (MCSection &Sec : Asm) { ------------------ | Branch (1118:23): [True: 178, False: 175] ------------------ 1119| 178| MCSectionELF &Section = static_cast(Sec); 1120| | 1121| 178| align(Section.getAlignment()); 1122| | 1123| | // Remember the offset into the file for this section. 1124| 178| uint64_t SecStart = getStream().tell(); 1125| | 1126| 178| const MCSymbolELF *SignatureSymbol = Section.getGroup(); 1127| 178| writeSectionData(Asm, Section, Layout); 1128| 178| if (Asm.getError()) ------------------ | Branch (1128:9): [True: 1, False: 177] ------------------ 1129| 1| return; 1130| | 1131| 177| uint64_t SecEnd = getStream().tell(); 1132| 177| SectionOffsets[&Section] = std::make_pair(SecStart, SecEnd); 1133| | 1134| 177| MCSectionELF *RelSection = createRelocationSection(Ctx, Section); 1135| | 1136| 177| if (SignatureSymbol) { ------------------ | Branch (1136:9): [True: 0, False: 177] ------------------ 1137| 0| Asm.registerSymbol(*SignatureSymbol); 1138| 0| unsigned &GroupIdx = RevGroupMap[SignatureSymbol]; 1139| 0| if (!GroupIdx) { ------------------ | Branch (1139:11): [True: 0, False: 0] ------------------ 1140| 0| MCSectionELF *Group = Ctx.createELFGroupSection(SignatureSymbol); 1141| 0| GroupIdx = addToSectionTable(Group); 1142| 0| Group->setAlignment(4); 1143| 0| Groups.push_back(Group); 1144| 0| } 1145| 0| std::vector &Members = 1146| 0| GroupMembers[SignatureSymbol]; 1147| 0| Members.push_back(&Section); 1148| 0| if (RelSection) ------------------ | Branch (1148:11): [True: 0, False: 0] ------------------ 1149| 0| Members.push_back(RelSection); 1150| 0| } 1151| | 1152| 177| SectionIndexMap[&Section] = addToSectionTable(&Section); 1153| 177| if (RelSection) { ------------------ | Branch (1153:9): [True: 25, False: 152] ------------------ 1154| 25| SectionIndexMap[RelSection] = addToSectionTable(RelSection); 1155| 25| Relocations.push_back(RelSection); 1156| 25| } 1157| 177| } 1158| | 1159| 175|return; 1160| | 1161| 175| for (MCSectionELF *Group : Groups) { ------------------ | Branch (1161:28): [True: 0, False: 0] ------------------ 1162| 0| align(Group->getAlignment()); 1163| | 1164| | // Remember the offset into the file for this section. 1165| 0| uint64_t SecStart = getStream().tell(); 1166| | 1167| 0| const MCSymbol *SignatureSymbol = Group->getGroup(); 1168| 0| assert(SignatureSymbol); ------------------ | Branch (1168:5): [True: 0, False: 0] ------------------ 1169| 0| write(uint32_t(ELF::GRP_COMDAT)); 1170| 0| for (const MCSectionELF *Member : GroupMembers[SignatureSymbol]) { ------------------ | Branch (1170:37): [True: 0, False: 0] ------------------ 1171| 0| uint32_t SecIndex = SectionIndexMap.lookup(Member); 1172| 0| write(SecIndex); 1173| 0| } 1174| | 1175| 0| uint64_t SecEnd = getStream().tell(); 1176| 0| SectionOffsets[Group] = std::make_pair(SecStart, SecEnd); 1177| 0| } 1178| | 1179| | // Compute symbol table information. 1180| 0| computeSymbolTable(Asm, Layout, SectionIndexMap, RevGroupMap, SectionOffsets); 1181| | 1182| 0| for (MCSectionELF *RelSection : Relocations) { ------------------ | Branch (1182:33): [True: 0, False: 0] ------------------ 1183| 0| align(RelSection->getAlignment()); 1184| | 1185| | // Remember the offset into the file for this section. 1186| 0| uint64_t SecStart = getStream().tell(); 1187| | 1188| 0| writeRelocations(Asm, *RelSection->getAssociatedSection()); // qq 1189| | 1190| 0| uint64_t SecEnd = getStream().tell(); 1191| 0| SectionOffsets[RelSection] = std::make_pair(SecStart, SecEnd); 1192| 0| } 1193| | 1194| 0| { 1195| 0| uint64_t SecStart = getStream().tell(); 1196| 0| const MCSectionELF *Sec = createStringTable(Ctx); 1197| 0| uint64_t SecEnd = getStream().tell(); 1198| 0| SectionOffsets[Sec] = std::make_pair(SecStart, SecEnd); 1199| 0| } 1200| | 1201| 0| uint64_t NaturalAlignment = is64Bit() ? 8 : 4; ------------------ | Branch (1201:31): [True: 0, False: 0] ------------------ 1202| 0| align(NaturalAlignment); 1203| | 1204| 0| const uint64_t SectionHeaderOffset = getStream().tell(); 1205| | 1206| | // ... then the section header table ... 1207| 0| writeSectionHeader(Layout, SectionIndexMap, SectionOffsets); 1208| | 1209| 0| uint16_t NumSections = (SectionTable.size() + 1 >= ELF::SHN_LORESERVE) ------------------ | Branch (1209:26): [True: 0, False: 0] ------------------ 1210| 0| ? (uint16_t)ELF::SHN_UNDEF 1211| 0| : SectionTable.size() + 1; 1212| 0| if (sys::IsLittleEndianHost != IsLittleEndian) ------------------ | Branch (1212:7): [True: 0, False: 0] ------------------ 1213| 0| sys::swapByteOrder(NumSections); 1214| 0| unsigned NumSectionsOffset; 1215| | 1216| 0| if (is64Bit()) { ------------------ | Branch (1216:7): [True: 0, False: 0] ------------------ 1217| 0| uint64_t Val = SectionHeaderOffset; 1218| 0| if (sys::IsLittleEndianHost != IsLittleEndian) ------------------ | Branch (1218:9): [True: 0, False: 0] ------------------ 1219| 0| sys::swapByteOrder(Val); 1220| 0| getStream().pwrite(reinterpret_cast(&Val), sizeof(Val), 1221| 0| offsetof(ELF::Elf64_Ehdr, e_shoff)); 1222| 0| NumSectionsOffset = offsetof(ELF::Elf64_Ehdr, e_shnum); 1223| 0| } else { 1224| 0| uint32_t Val = SectionHeaderOffset; 1225| 0| if (sys::IsLittleEndianHost != IsLittleEndian) ------------------ | Branch (1225:9): [True: 0, False: 0] ------------------ 1226| 0| sys::swapByteOrder(Val); 1227| 0| getStream().pwrite(reinterpret_cast(&Val), sizeof(Val), 1228| 0| offsetof(ELF::Elf32_Ehdr, e_shoff)); 1229| | NumSectionsOffset = offsetof(ELF::Elf32_Ehdr, e_shnum); 1230| 0| } 1231| 0| getStream().pwrite(reinterpret_cast(&NumSections), 1232| 0| sizeof(NumSections), NumSectionsOffset); 1233| 0|} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriter17addToSectionTableEPKN7llvm_ks12MCSectionELFE: 240| 378|unsigned ELFObjectWriter::addToSectionTable(const MCSectionELF *Sec) { 241| 378| SectionTable.push_back(Sec); 242| 378| StrTabBuilder.add(Sec->getSectionName()); 243| 378| return SectionTable.size(); 244| 378|} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriter5alignEj: 235| 178|void ELFObjectWriter::align(unsigned Alignment) { 236| 178| uint64_t Padding = OffsetToAlignment(getStream().tell(), Alignment); 237| 178| WriteZeros(Padding); 238| 178|} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriter16writeSectionDataERKN7llvm_ks11MCAssemblerERNS1_9MCSectionERKNS1_11MCAsmLayoutE: 911| 178| const MCAsmLayout &Layout) { 912| 178| MCSectionELF &Section = static_cast(Sec); 913| 178| StringRef SectionName = Section.getSectionName(); 914| | 915| | // Compressing debug_frame requires handling alignment fragments which is 916| | // more work (possibly generalizing MCAssembler.cpp:writeFragment to allow 917| | // for writing to arbitrary buffers) for little benefit. 918| 178| if (!Asm.getContext().getAsmInfo()->compressDebugSections() || ------------------ | Branch (918:7): [True: 178, False: 0] | Branch (918:7): [True: 178, False: 0] ------------------ 919| 178| !SectionName.startswith(".debug_") || SectionName == ".debug_frame") { ------------------ | Branch (919:7): [True: 0, False: 0] | Branch (919:45): [True: 0, False: 0] ------------------ 920| 178| Asm.writeSectionData(&Section, Layout); 921| 178| return; 922| 178| } 923| | 924| 0| SmallVector UncompressedData; 925| 0| raw_svector_ostream VecOS(UncompressedData); 926| 0| raw_pwrite_stream &OldStream = getStream(); 927| 0| setStream(VecOS); 928| 0| Asm.writeSectionData(&Section, Layout); 929| 0| setStream(OldStream); 930| | 931| |#if 0 932| | SmallVector CompressedContents; 933| | zlib::Status Success = zlib::compress( 934| | StringRef(UncompressedData.data(), UncompressedData.size()), 935| | CompressedContents); 936| | if (Success != zlib::StatusOK) { 937| | getStream() << UncompressedData; 938| | return; 939| | } 940| | 941| | if (!prependCompressionHeader(UncompressedData.size(), CompressedContents)) { 942| | getStream() << UncompressedData; 943| | return; 944| | } 945| | Asm.getContext().renameELFSection(&Section, 946| | (".z" + SectionName.drop_front(1)).str()); 947| | getStream() << CompressedContents; 948| |#endif 949| 0|} ELFObjectWriter.cpp:_ZN12_GLOBAL__N_115ELFObjectWriter23createRelocationSectionERN7llvm_ks9MCContextERKNS1_12MCSectionELFE: 885| 177| const MCSectionELF &Sec) { 886| 177| if (Relocations[&Sec].empty()) ------------------ | Branch (886:7): [True: 152, False: 25] ------------------ 887| 152| return nullptr; 888| | 889| 25| const StringRef SectionName = Sec.getSectionName(); 890| 25| std::string RelaSectionName = hasRelocationAddend() ? ".rela" : ".rel"; ------------------ | Branch (890:33): [True: 0, False: 25] ------------------ 891| 25| RelaSectionName += SectionName; 892| | 893| 25| unsigned EntrySize; 894| 25| if (hasRelocationAddend()) ------------------ | Branch (894:7): [True: 0, False: 25] ------------------ 895| 0| EntrySize = is64Bit() ? sizeof(ELF::Elf64_Rela) : sizeof(ELF::Elf32_Rela); ------------------ | Branch (895:17): [True: 0, False: 0] ------------------ 896| 25| else 897| 25| EntrySize = is64Bit() ? sizeof(ELF::Elf64_Rel) : sizeof(ELF::Elf32_Rel); ------------------ | Branch (897:17): [True: 0, False: 25] ------------------ 898| | 899| 25| unsigned Flags = 0; 900| 25| if (Sec.getFlags() & ELF::SHF_GROUP) ------------------ | Branch (900:7): [True: 0, False: 25] ------------------ 901| 0| Flags = ELF::SHF_GROUP; 902| | 903| 25| MCSectionELF *RelaSection = Ctx.createELFRelSection( 904| 25| RelaSectionName, hasRelocationAddend() ? ELF::SHT_RELA : ELF::SHT_REL, ------------------ | Branch (904:24): [True: 0, False: 25] ------------------ 905| 25| Flags, EntrySize, Sec.getGroup(), &Sec); 906| 25| RelaSection->setAlignment(is64Bit() ? 8 : 4); ------------------ | Branch (906:29): [True: 0, False: 25] ------------------ 907| 25| return RelaSection; 908| 177|} ELFObjectWriter.cpp:_ZNK12_GLOBAL__N_115ELFObjectWriter7is64BitEv: 126| 50| bool is64Bit() const { return TargetObjectWriter->is64Bit(); } _ZN7llvm_ks12MCAsmBackendC2Ev: 15| 430|MCAsmBackend::MCAsmBackend() : HasDataInCodeSupport(false) {} _ZN7llvm_ks12MCAsmBackendD2Ev: 17| 430|MCAsmBackend::~MCAsmBackend() {} _ZNK7llvm_ks12MCAsmBackend16getFixupKindInfoENS_11MCFixupKindE: 23| 20|const MCFixupKindInfo &MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { 24| 20| static const MCFixupKindInfo Builtins[] = { 25| 20| {"FK_Data_1", 0, 8, 0}, 26| 20| {"FK_Data_2", 0, 16, 0}, 27| 20| {"FK_Data_4", 0, 32, 0}, 28| 20| {"FK_Data_8", 0, 64, 0}, 29| 20| {"FK_PCRel_1", 0, 8, MCFixupKindInfo::FKF_IsPCRel}, 30| 20| {"FK_PCRel_2", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 31| 20| {"FK_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 32| 20| {"FK_PCRel_8", 0, 64, MCFixupKindInfo::FKF_IsPCRel}, 33| 20| {"FK_GPRel_1", 0, 8, 0}, 34| 20| {"FK_GPRel_2", 0, 16, 0}, 35| 20| {"FK_GPRel_4", 0, 32, 0}, 36| 20| {"FK_GPRel_8", 0, 64, 0}, 37| 20| {"FK_SecRel_1", 0, 8, 0}, 38| 20| {"FK_SecRel_2", 0, 16, 0}, 39| 20| {"FK_SecRel_4", 0, 32, 0}, 40| 20| {"FK_SecRel_8", 0, 64, 0}}; 41| | 42| 20| assert((size_t)Kind <= array_lengthof(Builtins) && "Unknown fixup kind"); ------------------ | Branch (42:3): [True: 20, False: 0] | Branch (42:3): [True: 20, Folded] | Branch (42:3): [True: 20, False: 0] ------------------ 43| 20| return Builtins[Kind]; 44| 20|} _ZNK7llvm_ks12MCAsmBackend28fixupNeedsRelaxationAdvancedERKNS_7MCFixupEbmPKNS_19MCRelaxableFragmentERKNS_11MCAsmLayoutE: 48| 636| const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const { 49| 636| if (!Resolved) ------------------ | Branch (49:7): [True: 0, False: 636] ------------------ 50| 0| return true; 51| 636| unsigned KsError; 52| 636| return fixupNeedsRelaxation(Fixup, Value, DF, Layout, KsError); 53| 636|} _ZN7llvm_ks9MCAsmInfoC2Ev: 25| 430|MCAsmInfo::MCAsmInfo() { 26| 430| PointerSize = 4; 27| 430| CalleeSaveStackSlotSize = 4; 28| | 29| 430| IsLittleEndian = true; 30| 430| StackGrowsUp = false; 31| 430| HasSubsectionsViaSymbols = false; 32| 430| HasMachoZeroFillDirective = false; 33| 430| HasMachoTBSSDirective = false; 34| 430| HasStaticCtorDtorReferenceInStaticMode = false; 35| 430| MaxInstLength = 4; 36| 430| MinInstAlignment = 1; 37| 430| DollarIsPC = false; 38| 430| SeparatorString = ";"; 39| 430| CommentString = "#"; 40| 430| LabelSuffix = ":"; 41| 430| UseAssignmentForEHBegin = false; 42| 430| NeedsLocalForSize = false; 43| 430| PrivateGlobalPrefix = "L"; 44| 430| PrivateLabelPrefix = PrivateGlobalPrefix; 45| 430| LinkerPrivateGlobalPrefix = ""; 46| 430| InlineAsmStart = "APP"; 47| 430| InlineAsmEnd = "NO_APP"; 48| 430| Code16Directive = ".code16"; 49| 430| Code32Directive = ".code32"; 50| 430| Code64Directive = ".code64"; 51| 430| AssemblerDialect = 0; 52| 430| AllowAtInName = false; 53| 430| SupportsQuotedNames = true; 54| 430| UseDataRegionDirectives = false; 55| 430| ZeroDirective = "\t.zero\t"; 56| 430| AsciiDirective = "\t.ascii\t"; 57| 430| AscizDirective = "\t.asciz\t"; 58| 430| Data8bitsDirective = "\t.byte\t"; 59| 430| Data16bitsDirective = "\t.short\t"; 60| 430| Data32bitsDirective = "\t.long\t"; 61| 430| Data64bitsDirective = "\t.quad\t"; 62| 430| SunStyleELFSectionSwitchSyntax = false; 63| 430| UsesELFSectionDirectiveForBSS = false; 64| 430| AlignmentIsInBytes = true; 65| 430| TextAlignFillValue = 0; 66| 430| GPRel64Directive = nullptr; 67| 430| GPRel32Directive = nullptr; 68| 430| GlobalDirective = "\t.globl\t"; 69| 430| SetDirectiveSuppressesReloc = false; 70| 430| HasAggressiveSymbolFolding = true; 71| 430| COMMDirectiveAlignmentIsInBytes = true; 72| 430| LCOMMDirectiveAlignmentType = LCOMM::NoAlignment; 73| 430| HasFunctionAlignment = true; 74| 430| HasDotTypeDotSizeDirective = true; 75| 430| HasSingleParameterDotFile = true; 76| 430| HasIdentDirective = false; 77| 430| HasNoDeadStrip = false; 78| 430| WeakDirective = "\t.weak\t"; 79| 430| WeakRefDirective = nullptr; 80| 430| HasWeakDefDirective = false; 81| 430| HasWeakDefCanBeHiddenDirective = false; 82| 430| HasLinkOnceDirective = false; 83| 430| HiddenVisibilityAttr = MCSA_Hidden; 84| 430| HiddenDeclarationVisibilityAttr = MCSA_Hidden; 85| 430| ProtectedVisibilityAttr = MCSA_Protected; 86| 430| SupportsDebugInformation = false; 87| 430| ExceptionsType = ExceptionHandling::None; 88| 430| WinEHEncodingType = WinEH::EncodingType::Invalid; 89| 430| DwarfUsesRelocationsAcrossSections = true; 90| 430| DwarfFDESymbolsUseAbsDiff = false; 91| 430| DwarfRegNumForCFI = false; 92| 430| NeedsDwarfSectionOffsetDirective = false; 93| 430| UseParensForSymbolVariant = false; 94| 430| UseLogicalShr = true; 95| | 96| | // FIXME: Clang's logic should be synced with the logic used to initialize 97| | // this member and the two implementations should be merged. 98| | // For reference: 99| | // - Solaris always enables the integrated assembler by default 100| | // - SparcELFMCAsmInfo and X86ELFMCAsmInfo are handling this case 101| | // - Windows always enables the integrated assembler by default 102| | // - MCAsmInfoCOFF is handling this case, should it be MCAsmInfoMicrosoft? 103| | // - MachO targets always enables the integrated assembler by default 104| | // - MCAsmInfoDarwin is handling this case 105| | // - Generic_GCC toolchains enable the integrated assembler on a per 106| | // architecture basis. 107| | // - The target subclasses for AArch64, ARM, and X86 handle these cases 108| 430| UseIntegratedAssembler = false; 109| | 110| 430| CompressDebugSections = false; 111| 430|} _ZN7llvm_ks9MCAsmInfoD2Ev: 113| 430|MCAsmInfo::~MCAsmInfo() { 114| 430|} _ZN7llvm_ks12MCAsmInfoELFC2Ev: 27| 430|MCAsmInfoELF::MCAsmInfoELF() { 28| 430| HasIdentDirective = true; 29| 430| WeakRefDirective = "\t.weak\t"; 30| 430| PrivateGlobalPrefix = ".L"; 31| 430| PrivateLabelPrefix = ".L"; 32| 430| UsesNonexecutableStackSection = true; 33| 430|} _ZN7llvm_ks11MCAssemblerC2ERNS_9MCContextERNS_12MCAsmBackendERNS_13MCCodeEmitterERNS_14MCObjectWriterE: 48| 430| : Context(Context_), Backend(Backend_), Emitter(Emitter_), Writer(Writer_), 49| 430| BundleAlignSize(0), RelaxAll(false), SubsectionsViaSymbols(false), 50| 430| IncrementalLinkerCompatible(false), ELFHeaderEFlags(0) { 51| 430| VersionMinInfo.Major = 0; // Major version == 0 for "none specified" 52| 430|} _ZN7llvm_ks11MCAssemblerD2Ev: 54| 430|MCAssembler::~MCAssembler() { 55| 430|} _ZN7llvm_ks11MCAssembler15registerSectionERNS_9MCSectionE: 80| 434|bool MCAssembler::registerSection(MCSection &Section) { 81| 434| if (Section.isRegistered()) ------------------ | Branch (81:7): [True: 0, False: 434] ------------------ 82| 0| return false; 83| 434| Sections.push_back(&Section); 84| 434| Section.setIsRegistered(true); 85| 434| return true; 86| 434|} _ZNK7llvm_ks11MCAssembler11isThumbFuncEPKNS_8MCSymbolE: 88| 319|bool MCAssembler::isThumbFunc(const MCSymbol *Symbol) const { 89| 319| if (ThumbFuncs.count(Symbol)) ------------------ | Branch (89:7): [True: 0, False: 319] ------------------ 90| 0| return true; 91| | 92| 319| if (!Symbol->isVariable()) ------------------ | Branch (92:7): [True: 319, False: 0] ------------------ 93| 319| return false; 94| | 95| | // FIXME: It looks like gas supports some cases of the form "foo + 2". It 96| | // is not clear if that is a bug or a feature. 97| 0| const MCExpr *Expr = Symbol->getVariableValue(); 98| 0| const MCSymbolRefExpr *Ref = dyn_cast(Expr); 99| 0| if (!Ref) ------------------ | Branch (99:7): [True: 0, False: 0] ------------------ 100| 0| return false; 101| | 102| 0| if (Ref->getKind() != MCSymbolRefExpr::VK_None) ------------------ | Branch (102:7): [True: 0, False: 0] ------------------ 103| 0| return false; 104| | 105| 0| const MCSymbol &Sym = Ref->getSymbol(); 106| 0| if (!isThumbFunc(&Sym)) ------------------ | Branch (106:7): [True: 0, False: 0] ------------------ 107| 0| return false; 108| | 109| 0| ThumbFuncs.insert(Symbol); // Cache it. 110| 0| return true; 111| 0|} _ZNK7llvm_ks11MCAssembler13evaluateFixupERKNS_11MCAsmLayoutERKNS_7MCFixupEPKNS_10MCFragmentERNS_7MCValueERmRj: 150| 1.37k|{ 151| 1.37k| KsError = 0; 152| | 153| | // FIXME: This code has some duplication with recordRelocation. We should 154| | // probably merge the two into a single callback that tries to evaluate a 155| | // fixup and records a relocation if one is needed. 156| 1.37k| const MCExpr *Expr = Fixup.getValue(); 157| 1.37k| if (!Expr->evaluateAsRelocatable(Target, &Layout, &Fixup)) { ------------------ | Branch (157:7): [True: 5, False: 1.37k] ------------------ 158| | // getContext().reportError(Fixup.getLoc(), "expected relocatable expression"); 159| | // Claim to have completely evaluated the fixup, to prevent any further 160| | // processing from being done. 161| | // return true; 162| 5| Value = 0; 163| 5| KsError = KS_ERR_ASM_INVALIDOPERAND; 164| 5| return false; 165| 5| } 166| | 167| 1.37k| bool IsPCRel = Backend.getFixupKindInfo( 168| 1.37k| Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsPCRel; 169| | 170| 1.37k| bool IsResolved; 171| 1.37k| if (IsPCRel) { ------------------ | Branch (171:7): [True: 1.36k, False: 6] ------------------ 172| 1.36k| if (Target.getSymB()) { ------------------ | Branch (172:9): [True: 83, False: 1.28k] ------------------ 173| 83| IsResolved = false; 174| 1.28k| } else if (!Target.getSymA()) { ------------------ | Branch (174:16): [True: 6, False: 1.27k] ------------------ 175| 6| if (getBackend().getArch() == KS_ARCH_X86) ------------------ | Branch (175:11): [True: 0, False: 6] ------------------ 176| 0| IsResolved = true; 177| 6| else 178| 6| IsResolved = false; 179| 1.27k| } else { 180| 1.27k| const MCSymbolRefExpr *A = Target.getSymA(); 181| 1.27k| const MCSymbol &SA = A->getSymbol(); 182| 1.27k| if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined()) { ------------------ | Branch (182:11): [True: 0, False: 1.27k] | Branch (182:55): [True: 30, False: 1.24k] ------------------ 183| 30| IsResolved = false; 184| 1.24k| } else { 185| 1.24k| IsResolved = getWriter().isSymbolRefDifferenceFullyResolvedImpl( 186| 1.24k| *this, SA, *DF, false, true); 187| 1.24k| } 188| 1.27k| } 189| 1.36k| } else { 190| 6| IsResolved = Target.isAbsolute(); 191| 6| } 192| | 193| 1.37k| Value = Target.getConstant(); 194| | 195| 1.37k| if (const MCSymbolRefExpr *A = Target.getSymA()) { ------------------ | Branch (195:30): [True: 1.28k, False: 87] ------------------ 196| 1.28k| const MCSymbol &Sym = A->getSymbol(); 197| 1.28k| bool valid; 198| 1.28k| if (Sym.isDefined()) { ------------------ | Branch (198:9): [True: 1.25k, False: 32] ------------------ 199| 1.25k| Value += Layout.getSymbolOffset(Sym, valid); 200| 1.25k| if (!valid) { ------------------ | Branch (200:11): [True: 0, False: 1.25k] ------------------ 201| 0| KsError = KS_ERR_ASM_FIXUP_INVALID; 202| 0| return false; 203| 0| } 204| 1.25k| } else { 205| | // a missing symbol. is there any resolver registered? 206| 32| if (KsSymResolver) { ------------------ | Branch (206:13): [True: 0, False: 32] ------------------ 207| 0| uint64_t imm; 208| 0| ks_sym_resolver resolver = (ks_sym_resolver)KsSymResolver; 209| 0| if (resolver(Sym.getName().str().c_str(), &imm)) { ------------------ | Branch (209:17): [True: 0, False: 0] ------------------ 210| | // resolver handled this symbol 211| 0| Value = imm; 212| 0| IsResolved = true; 213| 0| } else { 214| | // resolver did not handle this symbol 215| 0| KsError = KS_ERR_ASM_SYMBOL_MISSING; 216| 0| return false; 217| 0| } 218| 32| } else { 219| | // no resolver registered 220| 32| KsError = KS_ERR_ASM_SYMBOL_MISSING; 221| 32| return false; 222| 32| } 223| 32| } 224| 1.28k| } 225| | 226| 1.34k| if (const MCSymbolRefExpr *B = Target.getSymB()) { ------------------ | Branch (226:30): [True: 86, False: 1.25k] ------------------ 227| 86| const MCSymbol &Sym = B->getSymbol(); 228| 86| bool valid; 229| 86| if (Sym.isDefined()) { ------------------ | Branch (229:9): [True: 1, False: 85] ------------------ 230| 1| Value -= Layout.getSymbolOffset(Sym, valid); 231| 1| if (!valid) { ------------------ | Branch (231:11): [True: 0, False: 1] ------------------ 232| 0| KsError = KS_ERR_ASM_FIXUP_INVALID; 233| 0| return false; 234| 0| } 235| 1| } 236| 86| } 237| | 238| 1.34k| bool ShouldAlignPC = Backend.getFixupKindInfo(Fixup.getKind()).Flags & 239| 1.34k| MCFixupKindInfo::FKF_IsAlignedDownTo32Bits; 240| 1.34k| assert((ShouldAlignPC ? IsPCRel : true) && ------------------ | Branch (240:3): [True: 1.03k, False: 301] | Branch (240:3): [True: 1.34k, False: 0] | Branch (240:3): [True: 1.34k, Folded] | Branch (240:3): [True: 1.34k, False: 0] ------------------ 241| 1.34k| "FKF_IsAlignedDownTo32Bits is only allowed on PC-relative fixups!"); 242| | 243| 1.34k| if (IsPCRel) { ------------------ | Branch (243:7): [True: 1.33k, False: 4] ------------------ 244| 1.33k| bool valid; 245| 1.33k| uint64_t Offset = Layout.getFragmentOffset(DF, valid) + Fixup.getOffset(); 246| 1.33k| if (!valid) { ------------------ | Branch (246:9): [True: 0, False: 1.33k] ------------------ 247| 0| KsError = KS_ERR_ASM_FRAGMENT_INVALID; 248| 0| return false; 249| 0| } 250| | 251| | // A number of ARM fixups in Thumb mode require that the effective PC 252| | // address be determined as the 32-bit aligned version of the actual offset. 253| 1.33k| if (ShouldAlignPC) Offset &= ~0x3; ------------------ | Branch (253:9): [True: 1.03k, False: 297] ------------------ 254| 1.33k| Value -= Offset; 255| 1.33k| } 256| | 257| | // Let the backend adjust the fixup value if necessary, including whether 258| | // we need a relocation. 259| 1.34k| Backend.processFixupValue(*this, Layout, Fixup, DF, Target, Value, 260| 1.34k| IsResolved); 261| | 262| 1.34k| return IsResolved; 263| 1.34k|} _ZNK7llvm_ks11MCAssembler19computeFragmentSizeERKNS_11MCAsmLayoutERKNS_10MCFragmentERb: 267| 3.94k|{ 268| 3.94k| valid = true; 269| 3.94k| switch (F.getKind()) { ------------------ | Branch (269:11): [True: 3.94k, False: 0] ------------------ 270| 893| case MCFragment::FT_Data: ------------------ | Branch (270:3): [True: 893, False: 3.05k] ------------------ 271| 893| return cast(F).getContents().size(); 272| 1.05k| case MCFragment::FT_Relaxable: ------------------ | Branch (272:3): [True: 1.05k, False: 2.88k] ------------------ 273| 1.05k| return cast(F).getContents().size(); 274| 0| case MCFragment::FT_CompactEncodedInst: ------------------ | Branch (274:3): [True: 0, False: 3.94k] ------------------ 275| 0| return cast(F).getContents().size(); 276| 579| case MCFragment::FT_Fill: ------------------ | Branch (276:3): [True: 579, False: 3.36k] ------------------ 277| 579| return cast(F).getSize(); 278| | 279| 0| case MCFragment::FT_LEB: ------------------ | Branch (279:3): [True: 0, False: 3.94k] ------------------ 280| 0| return cast(F).getContents().size(); 281| | 282| 0| case MCFragment::FT_SafeSEH: ------------------ | Branch (282:3): [True: 0, False: 3.94k] ------------------ 283| 0| return 4; 284| | 285| 1.22k| case MCFragment::FT_Align: { ------------------ | Branch (285:3): [True: 1.22k, False: 2.72k] ------------------ 286| 1.22k| const MCAlignFragment &AF = cast(F); 287| 1.22k| unsigned Offset = Layout.getFragmentOffset(&AF, valid); 288| 1.22k| if (!valid) { ------------------ | Branch (288:9): [True: 0, False: 1.22k] ------------------ 289| 0| return 0; 290| 0| } 291| 1.22k| unsigned Size = OffsetToAlignment(Offset, AF.getAlignment()); 292| | // If we are padding with nops, force the padding to be larger than the 293| | // minimum nop size. 294| 1.22k| if (Size > 0 && AF.hasEmitNops()) { ------------------ | Branch (294:9): [True: 265, False: 958] | Branch (294:21): [True: 265, False: 0] ------------------ 295| 265| while (Size % getBackend().getMinimumNopSize()) ------------------ | Branch (295:14): [True: 0, False: 265] ------------------ 296| 0| Size += AF.getAlignment(); 297| 265| } 298| 1.22k| if (Size > AF.getMaxBytesToEmit()) ------------------ | Branch (298:9): [True: 250, False: 973] ------------------ 299| 250| return 0; 300| 973| return Size; 301| 1.22k| } 302| | 303| 192| case MCFragment::FT_Org: { ------------------ | Branch (303:3): [True: 192, False: 3.75k] ------------------ 304| 192| const MCOrgFragment &OF = cast(F); 305| 192| MCValue Value; 306| 192| if (!OF.getOffset().evaluateAsValue(Value, Layout)) { ------------------ | Branch (306:9): [True: 0, False: 192] ------------------ 307| | //report_fatal_error("expected assembly-time absolute expression"); 308| 0| valid = false; 309| 0| return 0; 310| 0| } 311| | 312| | // FIXME: We need a way to communicate this error. 313| 192| uint64_t FragmentOffset = Layout.getFragmentOffset(&OF, valid); 314| 192| if (!valid) { ------------------ | Branch (314:9): [True: 0, False: 192] ------------------ 315| 0| return 0; 316| 0| } 317| 192| int64_t TargetLocation = Value.getConstant(); 318| 192| if (const MCSymbolRefExpr *A = Value.getSymA()) { ------------------ | Branch (318:32): [True: 82, False: 110] ------------------ 319| 82| uint64_t Val; 320| 82| if (!Layout.getSymbolOffset(A->getSymbol(), Val, valid)) { ------------------ | Branch (320:11): [True: 0, False: 82] ------------------ 321| | //report_fatal_error("expected absolute expression"); 322| 0| valid = false; 323| 0| return 0; 324| 0| } 325| 82| TargetLocation += Val; 326| 82| } 327| 192| int64_t Size = TargetLocation - FragmentOffset; 328| 192| if (Size < 0 || Size >= 0x40000000) { ------------------ | Branch (328:9): [True: 2, False: 190] | Branch (328:21): [True: 0, False: 190] ------------------ 329| | //report_fatal_error("invalid .org offset '" + Twine(TargetLocation) + 330| | // "' (at offset '" + Twine(FragmentOffset) + "')"); 331| 2| valid = false; 332| 2| return 0; 333| 2| } 334| 190| return Size; 335| 192| } 336| | 337| 0| case MCFragment::FT_Dwarf: ------------------ | Branch (337:3): [True: 0, False: 3.94k] ------------------ 338| 0| return cast(F).getContents().size(); 339| 0| case MCFragment::FT_DwarfFrame: ------------------ | Branch (339:3): [True: 0, False: 3.94k] ------------------ 340| 0| return cast(F).getContents().size(); 341| 0| case MCFragment::FT_Dummy: ------------------ | Branch (341:3): [True: 0, False: 3.94k] ------------------ 342| 0| llvm_unreachable("Should not have been added"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 343| 3.94k| } 344| | 345| 0| llvm_unreachable("invalid fragment kind"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 346| 3.94k|} _ZN7llvm_ks11MCAsmLayout14layoutFragmentEPNS_10MCFragmentE: 349| 2.50k|{ 350| 2.50k| MCFragment *Prev = F->getPrevNode(); 351| | 352| | // We should never try to recompute something which is valid. 353| | //assert(!isFragmentValid(F) && "Attempt to recompute a valid fragment!"); 354| 2.50k| if (isFragmentValid(F)) ------------------ | Branch (354:7): [True: 0, False: 2.50k] ------------------ 355| 0| return true; 356| | 357| | // We should never try to compute the fragment layout if its predecessor 358| | // isn't valid. 359| | //assert((!Prev || isFragmentValid(Prev)) && 360| | // "Attempt to compute fragment before its predecessor!"); 361| 2.50k| if (Prev && !isFragmentValid(Prev)) ------------------ | Branch (361:7): [True: 2.31k, False: 188] | Branch (361:15): [True: 1, False: 2.31k] ------------------ 362| 1| return true; 363| | 364| 2.50k| bool valid = true; 365| | // Compute fragment offset and size. 366| 2.50k| if (Prev) ------------------ | Branch (366:7): [True: 2.31k, False: 188] ------------------ 367| 2.31k| F->Offset = Prev->Offset + getAssembler().computeFragmentSize(*this, *Prev, valid); 368| 188| else 369| 188| F->Offset = getAssembler().getContext().getBaseAddress(); 370| 2.50k| if (!valid) { ------------------ | Branch (370:7): [True: 1, False: 2.50k] ------------------ 371| 1| return false; 372| 1| } 373| 2.50k| LastValidFragment[F->getParent()] = F; 374| | 375| | // If bundling is enabled and this fragment has instructions in it, it has to 376| | // obey the bundling restrictions. With padding, we'll have: 377| | // 378| | // 379| | // BundlePadding 380| | // ||| 381| | // ------------------------------------- 382| | // Prev |##########| F | 383| | // ------------------------------------- 384| | // ^ 385| | // | 386| | // F->Offset 387| | // 388| | // The fragment's offset will point to after the padding, and its computed 389| | // size won't include the padding. 390| | // 391| | // When the -mc-relax-all flag is used, we optimize bundling by writting the 392| | // padding directly into fragments when the instructions are emitted inside 393| | // the streamer. When the fragment is larger than the bundle size, we need to 394| | // ensure that it's bundle aligned. This means that if we end up with 395| | // multiple fragments, we must emit bundle padding between fragments. 396| | // 397| | // ".align N" is an example of a directive that introduces multiple 398| | // fragments. We could add a special case to handle ".align N" by emitting 399| | // within-fragment padding (which would produce less padding when N is less 400| | // than the bundle size), but for now we don't. 401| | // 402| 2.50k| if (Assembler.isBundlingEnabled() && F->hasInstructions()) { ------------------ | Branch (402:7): [True: 0, False: 2.50k] | Branch (402:40): [True: 0, False: 0] ------------------ 403| 0| assert(isa(F) && ------------------ | Branch (403:5): [True: 0, False: 0] | Branch (403:5): [True: 0, Folded] | Branch (403:5): [True: 0, False: 0] ------------------ 404| 0| "Only MCEncodedFragment implementations have instructions"); 405| 0| if (!isa(F)) ------------------ | Branch (405:9): [True: 0, False: 0] ------------------ 406| 0| return true; 407| | 408| 0| bool valid; 409| 0| uint64_t FSize = Assembler.computeFragmentSize(*this, *F, valid); 410| 0| if (!valid) ------------------ | Branch (410:9): [True: 0, False: 0] ------------------ 411| 0| return true; 412| | 413| 0| if (!Assembler.getRelaxAll() && FSize > Assembler.getBundleAlignSize()) ------------------ | Branch (413:9): [True: 0, False: 0] | Branch (413:37): [True: 0, False: 0] ------------------ 414| | //report_fatal_error("Fragment can't be larger than a bundle size"); 415| 0| return true; 416| | 417| 0| uint64_t RequiredBundlePadding = computeBundlePadding(Assembler, F, 418| 0| F->Offset, FSize); 419| 0| if (RequiredBundlePadding > UINT8_MAX) ------------------ | Branch (419:9): [True: 0, False: 0] ------------------ 420| | //report_fatal_error("Padding cannot exceed 255 bytes"); 421| 0| return true; 422| | 423| 0| F->setBundlePadding(static_cast(RequiredBundlePadding)); 424| 0| F->Offset += RequiredBundlePadding; 425| 0| } 426| | 427| 2.50k| return false; 428| 2.50k|} _ZN7llvm_ks11MCAssembler14registerSymbolERKNS_8MCSymbolEPb: 430| 8.57k|void MCAssembler::registerSymbol(const MCSymbol &Symbol, bool *Created) { 431| 8.57k| bool New = !Symbol.isRegistered(); 432| 8.57k| if (Created) ------------------ | Branch (432:7): [True: 0, False: 8.57k] ------------------ 433| 0| *Created = New; 434| 8.57k| if (New) { ------------------ | Branch (434:7): [True: 6.21k, False: 2.36k] ------------------ 435| 6.21k| Symbol.setIsRegistered(true); 436| 6.21k| Symbols.push_back(&Symbol); 437| 6.21k| } 438| 8.57k|} _ZNK7llvm_ks11MCAssembler20writeFragmentPaddingERKNS_10MCFragmentEmPNS_14MCObjectWriterE: 441| 1.62k| MCObjectWriter *OW) const { 442| | // Should NOP padding be written out before this fragment? 443| 1.62k| unsigned BundlePadding = F.getBundlePadding(); 444| 1.62k| if (BundlePadding > 0) { ------------------ | Branch (444:7): [True: 0, False: 1.62k] ------------------ 445| 0| assert(isBundlingEnabled() && ------------------ | Branch (445:5): [True: 0, False: 0] | Branch (445:5): [True: 0, Folded] | Branch (445:5): [True: 0, False: 0] ------------------ 446| 0| "Writing bundle padding with disabled bundling"); 447| 0| assert(F.hasInstructions() && ------------------ | Branch (447:5): [True: 0, False: 0] | Branch (447:5): [True: 0, Folded] | Branch (447:5): [True: 0, False: 0] ------------------ 448| 0| "Writing bundle padding for a fragment without instructions"); 449| | 450| 0| unsigned TotalLength = BundlePadding + static_cast(FSize); 451| 0| if (F.alignToBundleEnd() && TotalLength > getBundleAlignSize()) { ------------------ | Branch (451:9): [True: 0, False: 0] | Branch (451:33): [True: 0, False: 0] ------------------ 452| | // If the padding itself crosses a bundle boundary, it must be emitted 453| | // in 2 pieces, since even nop instructions must not cross boundaries. 454| | // v--------------v <- BundleAlignSize 455| | // v---------v <- BundlePadding 456| | // ---------------------------- 457| | // | Prev |####|####| F | 458| | // ---------------------------- 459| | // ^-------------------^ <- TotalLength 460| 0| unsigned DistanceToBoundary = TotalLength - getBundleAlignSize(); 461| 0| if (!getBackend().writeNopData(DistanceToBoundary, OW)) ------------------ | Branch (461:11): [True: 0, False: 0] ------------------ 462| 0| report_fatal_error("unable to write NOP sequence of " + 463| 0| Twine(DistanceToBoundary) + " bytes"); 464| 0| BundlePadding -= DistanceToBoundary; 465| 0| } 466| 0| if (!getBackend().writeNopData(BundlePadding, OW)) ------------------ | Branch (466:9): [True: 0, False: 0] ------------------ 467| 0| report_fatal_error("unable to write NOP sequence of " + 468| 0| Twine(BundlePadding) + " bytes"); 469| 0| } 470| 1.62k|} _ZNK7llvm_ks11MCAssembler16writeSectionDataEPKNS_9MCSectionERKNS_11MCAsmLayoutE: 608| 178|{ 609| | // Ignore virtual sections. 610| 178| if (Sec->isVirtualSection()) { ------------------ | Branch (610:7): [True: 0, False: 178] ------------------ 611| 0| assert(Layout.getSectionFileSize(Sec) == 0 && "Invalid size for section!"); ------------------ | Branch (611:5): [True: 0, False: 0] | Branch (611:5): [True: 0, Folded] | Branch (611:5): [True: 0, False: 0] ------------------ 612| | 613| | // Check that contents are only things legal inside a virtual section. 614| 0| for (const MCFragment &F : *Sec) { ------------------ | Branch (614:30): [True: 0, False: 0] ------------------ 615| 0| switch (F.getKind()) { 616| 0| default: llvm_unreachable("Invalid fragment in virtual section!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ | Branch (616:7): [True: 0, False: 0] ------------------ 617| 0| case MCFragment::FT_Data: { ------------------ | Branch (617:7): [True: 0, False: 0] ------------------ 618| | // Check that we aren't trying to write a non-zero contents (or fixups) 619| | // into a virtual section. This is to support clients which use standard 620| | // directives to fill the contents of virtual sections. 621| 0| const MCDataFragment &DF = cast(F); 622| 0| assert(DF.fixup_begin() == DF.fixup_end() && ------------------ | Branch (622:9): [True: 0, False: 0] | Branch (622:9): [True: 0, Folded] | Branch (622:9): [True: 0, False: 0] ------------------ 623| 0| "Cannot have fixups in virtual section!"); 624| 0| for (unsigned i = 0, e = DF.getContents().size(); i != e; ++i) ------------------ | Branch (624:59): [True: 0, False: 0] ------------------ 625| 0| if (DF.getContents()[i]) { ------------------ | Branch (625:15): [True: 0, False: 0] ------------------ 626| 0| if (auto *ELFSec = dyn_cast(Sec)) ------------------ | Branch (626:23): [True: 0, False: 0] ------------------ 627| 0| report_fatal_error("non-zero initializer found in section '" + 628| 0| ELFSec->getSectionName() + "'"); 629| 0| else 630| 0| report_fatal_error("non-zero initializer found in virtual section"); 631| 0| } 632| 0| break; 633| 0| } 634| 0| case MCFragment::FT_Align: ------------------ | Branch (634:7): [True: 0, False: 0] ------------------ 635| | // Check that we aren't trying to write a non-zero value into a virtual 636| | // section. 637| 0| assert((cast(F).getValueSize() == 0 || ------------------ | Branch (637:9): [True: 0, False: 0] | Branch (637:9): [True: 0, False: 0] | Branch (637:9): [True: 0, Folded] | Branch (637:9): [True: 0, False: 0] ------------------ 638| 0| cast(F).getValue() == 0) && 639| 0| "Invalid align in virtual section!"); 640| 0| break; 641| 0| case MCFragment::FT_Fill: ------------------ | Branch (641:7): [True: 0, False: 0] ------------------ 642| 0| assert((cast(F).getValue() == 0) && ------------------ | Branch (642:9): [True: 0, False: 0] | Branch (642:9): [True: 0, Folded] | Branch (642:9): [True: 0, False: 0] ------------------ 643| 0| "Invalid fill in virtual section!"); 644| 0| break; 645| 0| } 646| 0| } 647| | 648| 0| return; 649| 0| } 650| | 651| 178| uint64_t Start = getWriter().getStream().tell(); 652| 178| (void)Start; 653| | 654| 178| setError(0); 655| 178| for (const MCFragment &F : *Sec) ------------------ | Branch (655:28): [True: 1.70k, False: 178] ------------------ 656| 1.70k| writeFragment(*this, Layout, F); 657| | 658| | //assert(getWriter().getStream().tell() - Start == 659| | // Layout.getSectionAddressSize(Sec)); 660| 178|} _ZN7llvm_ks11MCAssembler11handleFixupERKNS_11MCAsmLayoutERNS_10MCFragmentERKNS_7MCFixupERj: 664| 713| const MCFixup &Fixup, unsigned int &KsError) { 665| | // Evaluate the fixup. 666| 713| MCValue Target; 667| 713| uint64_t FixedValue; 668| 713| bool IsPCRel = Backend.getFixupKindInfo(Fixup.getKind()).Flags & 669| 713| MCFixupKindInfo::FKF_IsPCRel; 670| 713| if (!evaluateFixup(Layout, Fixup, &F, Target, FixedValue, KsError)) { ------------------ | Branch (670:7): [True: 124, False: 589] ------------------ 671| 124| if (KsError) { ------------------ | Branch (671:9): [True: 9, False: 115] ------------------ 672| | // return a dummy value 673| 9| return std::make_pair(0, false); 674| 9| } 675| | // The fixup was unresolved, we need a relocation. Inform the object 676| | // writer of the relocation, and give it an opportunity to adjust the 677| | // fixup value if need be. 678| 115| if (const MCSymbolRefExpr *RefB = Target.getSymB()) { ------------------ | Branch (678:32): [True: 86, False: 29] ------------------ 679| 86| if (RefB->getKind() != MCSymbolRefExpr::VK_None) { ------------------ | Branch (679:13): [True: 0, False: 86] ------------------ 680| 0| KsError = KS_ERR_ASM_FIXUP_INVALID; 681| | // return a dummy value 682| 0| return std::make_pair(0, false); 683| 0| } 684| 86| } 685| 115| getWriter().recordRelocation(*this, Layout, &F, Fixup, Target, IsPCRel, 686| 115| FixedValue); 687| 115| } 688| | 689| 704| return std::make_pair(FixedValue, IsPCRel); 690| 713|} _ZN7llvm_ks11MCAssembler6layoutERNS_11MCAsmLayoutERj: 693| 185|{ 694| 185| DEBUG_WITH_TYPE("mc-dump", { 695| 185| llvm_ks::errs() << "assembler backend - pre-layout\n--\n"; 696| 185| dump(); }); 697| | 698| | // Create dummy fragments and assign section ordinals. 699| 185| unsigned SectionIndex = 0; 700| 187| for (MCSection &Sec : *this) { ------------------ | Branch (700:23): [True: 187, False: 185] ------------------ 701| | // Create dummy fragments to eliminate any empty sections, this simplifies 702| | // layout. 703| 187| if (Sec.getFragmentList().empty()) ------------------ | Branch (703:9): [True: 0, False: 187] ------------------ 704| 0| new MCDataFragment(&Sec); 705| | 706| 187| Sec.setOrdinal(SectionIndex++); 707| 187| } 708| | 709| | // Assign layout order indices to sections and fragments. 710| 372| for (unsigned i = 0, e = Layout.getSectionOrder().size(); i != e; ++i) { ------------------ | Branch (710:61): [True: 187, False: 185] ------------------ 711| 187| MCSection *Sec = Layout.getSectionOrder()[i]; 712| 187| Sec->setLayoutOrder(i); 713| | 714| 187| unsigned FragmentIndex = 0; 715| 187| for (MCFragment &Frag : *Sec) ------------------ | Branch (715:27): [True: 2.51k, False: 187] ------------------ 716| 2.51k| Frag.setLayoutOrder(FragmentIndex++); 717| 187| } 718| | 719| | // Layout until everything fits. 720| 186| while (layoutOnce(Layout)) ------------------ | Branch (720:10): [True: 1, False: 185] ------------------ 721| 1| continue; 722| | 723| 185| DEBUG_WITH_TYPE("mc-dump", { 724| 185| llvm_ks::errs() << "assembler backend - post-relaxation\n--\n"; 725| 185| dump(); }); 726| | 727| | // Finalize the layout, including fragment lowering. 728| 185| finishLayout(Layout); 729| | 730| 185| DEBUG_WITH_TYPE("mc-dump", { 731| 185| llvm_ks::errs() << "assembler backend - final-layout\n--\n"; 732| 185| dump(); }); 733| | 734| | // Allow the object writer a chance to perform post-layout binding (for 735| | // example, to set the index fields in the symbol data). 736| 185| getWriter().executePostLayoutBinding(*this, Layout); 737| | 738| | // Evaluate and apply the fixups, generating relocation entries as necessary. 739| 187| for (MCSection &Sec : *this) { ------------------ | Branch (739:23): [True: 187, False: 176] ------------------ 740| 1.98k| for (MCFragment &Frag : Sec) { ------------------ | Branch (740:27): [True: 1.98k, False: 178] ------------------ 741| 1.98k| MCEncodedFragment *F = dyn_cast(&Frag); 742| | // Data and relaxable fragments both have fixups. So only process 743| | // those here. 744| | // FIXME: Is there a better way to do this? MCEncodedFragmentWithFixups 745| | // being templated makes this tricky. 746| 1.98k| if (!F || isa(F)) ------------------ | Branch (746:11): [True: 964, False: 1.02k] | Branch (746:17): [True: 0, False: 1.02k] ------------------ 747| 964| continue; 748| 1.02k| ArrayRef Fixups; 749| 1.02k| MutableArrayRef Contents; 750| 1.02k| if (auto *FragWithFixups = dyn_cast(F)) { ------------------ | Branch (750:17): [True: 430, False: 593] ------------------ 751| 430| Fixups = FragWithFixups->getFixups(); 752| 430| Contents = FragWithFixups->getContents(); 753| 593| } else if (auto *FragWithFixups = dyn_cast(F)) { ------------------ | Branch (753:24): [True: 593, False: 0] ------------------ 754| 593| Fixups = FragWithFixups->getFixups(); 755| 593| Contents = FragWithFixups->getContents(); 756| 593| } else 757| 0| llvm_unreachable("Unknown fragment with fixups!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 758| 1.02k| for (const MCFixup &Fixup : Fixups) { ------------------ | Branch (758:33): [True: 713, False: 1.01k] ------------------ 759| 713| uint64_t FixedValue; 760| 713| bool IsPCRel; 761| 713| std::tie(FixedValue, IsPCRel) = handleFixup(Layout, *F, Fixup, KsError); 762| 713| if (KsError) ------------------ | Branch (762:13): [True: 9, False: 704] ------------------ 763| 9| return; 764| 704| getBackend().applyFixup(Fixup, Contents.data(), 765| 704| Contents.size(), FixedValue, IsPCRel, KsError); 766| 704| if (KsError) ------------------ | Branch (766:13): [True: 0, False: 704] ------------------ 767| 0| return; 768| 704| } 769| 1.02k| } 770| 187| } 771| 185|} _ZN7llvm_ks11MCAssembler6FinishERj: 773| 185|void MCAssembler::Finish(unsigned int &KsError) { 774| | // Create the layout object. 775| 185| MCAsmLayout Layout(*this); 776| 185| layout(Layout, KsError); 777| | 778| | // Write the object file. 779| 185| if (!KsError) { ------------------ | Branch (779:7): [True: 176, False: 9] ------------------ 780| 176| getWriter().writeObject(*this, Layout); 781| 176| KsError = getError(); 782| 176| } 783| 185|} _ZNK7llvm_ks11MCAssembler20fixupNeedsRelaxationERKNS_7MCFixupEPKNS_19MCRelaxableFragmentERKNS_11MCAsmLayoutERj: 788| 664|{ 789| 664| MCValue Target; 790| 664| uint64_t Value; 791| 664| bool Resolved = evaluateFixup(Layout, Fixup, DF, Target, Value, KsError); 792| 664| if (KsError) { ------------------ | Branch (792:7): [True: 28, False: 636] ------------------ 793| 28| KsError = KS_ERR_ASM_FIXUP_INVALID; 794| | // return a dummy value 795| 28| return false; 796| 28| } 797| 636| return getBackend().fixupNeedsRelaxationAdvanced(Fixup, Resolved, Value, DF, 798| 636| Layout); 799| 664|} _ZNK7llvm_ks11MCAssembler23fragmentNeedsRelaxationEPKNS_19MCRelaxableFragmentERKNS_11MCAsmLayoutERj: 803| 758|{ 804| | // If this inst doesn't ever need relaxation, ignore it. This occurs when we 805| | // are intentionally pushing out inst fragments, or because we relaxed a 806| | // previous instruction to one that doesn't need relaxation. 807| 758| if (!getBackend().mayNeedRelaxation(F->getInst())) ------------------ | Branch (807:7): [True: 92, False: 666] ------------------ 808| 92| return false; 809| | 810| 666| for (const MCFixup &Fixup : F->getFixups()) ------------------ | Branch (810:29): [True: 664, False: 620] ------------------ 811| 664| if (fixupNeedsRelaxation(Fixup, F, Layout, KsError)) ------------------ | Branch (811:9): [True: 46, False: 618] ------------------ 812| 46| return true; 813| | 814| 620| return false; 815| 666|} _ZN7llvm_ks11MCAssembler16relaxInstructionERNS_11MCAsmLayoutERNS_19MCRelaxableFragmentE: 819| 758|{ 820| 758| unsigned KsError = 0; 821| 758| if (!fragmentNeedsRelaxation(&F, Layout, KsError)) ------------------ | Branch (821:7): [True: 712, False: 46] ------------------ 822| 712| return false; 823| | 824| | // FIXME-PERF: We could immediately lower out instructions if we can tell 825| | // they are fully resolved, to avoid retesting on later passes. 826| | 827| | // Relax the fragment. 828| | 829| 46| MCInst Relaxed; 830| 46| getBackend().relaxInstruction(F.getInst(), Relaxed); 831| | 832| | // Encode the new instruction. 833| | // 834| | // FIXME-PERF: If it matters, we could let the target do this. It can 835| | // probably do so more efficiently in many cases. 836| 46| SmallVector Fixups; 837| 46| SmallString<256> Code; 838| 46| raw_svector_ostream VecOS(Code); 839| 46| getEmitter().encodeInstruction(Relaxed, VecOS, Fixups, F.getSubtargetInfo(), KsError); 840| | 841| | // Update the fragment. 842| 46| F.setInst(Relaxed); 843| 46| F.getContents() = Code; 844| 46| F.getFixups() = Fixups; 845| | 846| 46| return true; 847| 758|} _ZN7llvm_ks11MCAssembler17layoutSectionOnceERNS_11MCAsmLayoutERNS_9MCSectionE: 876| 189|{ 877| | // Holds the first fragment which needed relaxing during this layout. It will 878| | // remain NULL if none were relaxed. 879| | // When a fragment is relaxed, all the fragments following it should get 880| | // invalidated because their offset is going to change. 881| 189| MCFragment *FirstRelaxedFragment = nullptr; 882| | 883| | // Attempt to relax all the fragments in the section. 884| 2.83k| for (MCSection::iterator I = Sec.begin(), IE = Sec.end(); I != IE; ++I) { ------------------ | Branch (884:61): [True: 2.64k, False: 189] ------------------ 885| | // Check if this is a fragment that needs relaxation. 886| 2.64k| bool RelaxedFrag = false; 887| 2.64k| switch(I->getKind()) { 888| 1.88k| default: ------------------ | Branch (888:5): [True: 1.88k, False: 758] ------------------ 889| 1.88k| break; 890| 1.88k| case MCFragment::FT_Relaxable: ------------------ | Branch (890:5): [True: 758, False: 1.88k] ------------------ 891| 758| assert(!getRelaxAll() && ------------------ | Branch (891:7): [True: 758, False: 0] | Branch (891:7): [True: 758, Folded] | Branch (891:7): [True: 758, False: 0] ------------------ 892| 758| "Did not expect a MCRelaxableFragment in RelaxAll mode"); 893| 758| RelaxedFrag = relaxInstruction(Layout, *cast(I)); 894| 758| break; 895| 0| case MCFragment::FT_Dwarf: ------------------ | Branch (895:5): [True: 0, False: 2.64k] ------------------ 896| 0| RelaxedFrag = relaxDwarfLineAddr(Layout, 897| 0| *cast(I)); 898| 0| break; 899| 0| case MCFragment::FT_DwarfFrame: ------------------ | Branch (899:5): [True: 0, False: 2.64k] ------------------ 900| 0| RelaxedFrag = 901| 0| relaxDwarfCallFrameFragment(Layout, 902| 0| *cast(I)); 903| 0| break; 904| 0| case MCFragment::FT_LEB: ------------------ | Branch (904:5): [True: 0, False: 2.64k] ------------------ 905| 0| RelaxedFrag = relaxLEB(Layout, *cast(I)); 906| 0| break; 907| 2.64k| } 908| 2.64k| if (RelaxedFrag && !FirstRelaxedFragment) ------------------ | Branch (908:9): [True: 46, False: 2.60k] | Branch (908:24): [True: 1, False: 45] ------------------ 909| 1| FirstRelaxedFragment = &*I; 910| 2.64k| } 911| 189| if (FirstRelaxedFragment) { ------------------ | Branch (911:7): [True: 1, False: 188] ------------------ 912| 1| Layout.invalidateFragmentsFrom(FirstRelaxedFragment); 913| 1| return true; 914| 1| } 915| 188| return false; 916| 189|} _ZN7llvm_ks11MCAssembler10layoutOnceERNS_11MCAsmLayoutE: 919| 186|{ 920| 186| bool WasRelaxed = false; 921| 374| for (iterator it = begin(), ie = end(); it != ie; ++it) { ------------------ | Branch (921:43): [True: 188, False: 186] ------------------ 922| 188| MCSection &Sec = *it; 923| 189| while (layoutSectionOnce(Layout, Sec)) ------------------ | Branch (923:12): [True: 1, False: 188] ------------------ 924| 1| WasRelaxed = true; 925| 188| } 926| | 927| 186| return WasRelaxed; 928| 186|} _ZN7llvm_ks11MCAssembler12finishLayoutERNS_11MCAsmLayoutE: 930| 185|void MCAssembler::finishLayout(MCAsmLayout &Layout) { 931| | // The layout is done. Mark every fragment as valid. 932| 372| for (unsigned int i = 0, n = Layout.getSectionOrder().size(); i != n; ++i) { ------------------ | Branch (932:65): [True: 187, False: 185] ------------------ 933| 187| bool valid; 934| 187| Layout.getFragmentOffset(&*Layout.getSectionOrder()[i]->rbegin(), valid); 935| 187| } 936| 185|} MCAssembler.cpp:_ZL13writeFragmentRKN7llvm_ks11MCAssemblerERKNS_11MCAsmLayoutERKNS_10MCFragmentE: 475| 1.70k|{ 476| 1.70k| if (Asm.getError()) ------------------ | Branch (476:7): [True: 78, False: 1.62k] ------------------ 477| 78| return; 478| | 479| 1.62k| MCObjectWriter *OW = &Asm.getWriter(); 480| | 481| 1.62k| bool valid; 482| | // FIXME: Embed in fragments instead? 483| 1.62k| uint64_t FragmentSize = Asm.computeFragmentSize(Layout, F, valid); 484| 1.62k| if (!valid) { ------------------ | Branch (484:7): [True: 1, False: 1.62k] ------------------ 485| 1| Asm.setError(KS_ERR_ASM_FRAGMENT_INVALID); 486| 1| return; 487| 1| } 488| | 489| 1.62k| Asm.writeFragmentPadding(F, FragmentSize, OW); 490| | 491| | // This variable (and its dummy usage) is to participate in the assert at 492| | // the end of the function. 493| 1.62k| uint64_t Start = OW->getStream().tell(); 494| 1.62k| (void) Start; 495| | 496| 1.62k| switch (F.getKind()) { ------------------ | Branch (496:11): [True: 1.62k, False: 0] ------------------ 497| 495| case MCFragment::FT_Align: { ------------------ | Branch (497:3): [True: 495, False: 1.12k] ------------------ 498| 495| const MCAlignFragment &AF = cast(F); 499| 495| assert(AF.getValueSize() && "Invalid virtual align in concrete fragment!"); ------------------ | Branch (499:5): [True: 495, False: 0] | Branch (499:5): [True: 495, Folded] | Branch (499:5): [True: 495, False: 0] ------------------ 500| | 501| 495| uint64_t Count = FragmentSize / AF.getValueSize(); 502| | 503| | // FIXME: This error shouldn't actually occur (the front end should emit 504| | // multiple .align directives to enforce the semantics it wants), but is 505| | // severe enough that we want to report it. How to handle this? 506| 495| if (Count * AF.getValueSize() != FragmentSize) ------------------ | Branch (506:9): [True: 0, False: 495] ------------------ 507| 0| report_fatal_error("undefined .align directive, value size '" + 508| 0| Twine(AF.getValueSize()) + 509| 0| "' is not a divisor of padding size '" + 510| 0| Twine(FragmentSize) + "'"); 511| | 512| | // See if we are aligning with nops, and if so do that first to try to fill 513| | // the Count bytes. Then if that did not fill any bytes or there are any 514| | // bytes left to fill use the Value and ValueSize to fill the rest. 515| | // If we are aligning with nops, ask that target to emit the right data. 516| 495| if (AF.hasEmitNops()) { ------------------ | Branch (516:9): [True: 495, False: 0] ------------------ 517| 495| if (!Asm.getBackend().writeNopData(Count, OW)) ------------------ | Branch (517:11): [True: 0, False: 495] ------------------ 518| 0| report_fatal_error("unable to write nop sequence of " + 519| 0| Twine(Count) + " bytes"); 520| 495| break; 521| 495| } 522| | 523| | // Otherwise, write out in multiples of the value size. 524| 0| for (uint64_t i = 0; i != Count; ++i) { ------------------ | Branch (524:26): [True: 0, False: 0] ------------------ 525| 0| switch (AF.getValueSize()) { 526| 0| default: llvm_unreachable("Invalid size!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ | Branch (526:7): [True: 0, False: 0] ------------------ 527| 0| case 1: OW->write8 (uint8_t (AF.getValue())); break; ------------------ | Branch (527:7): [True: 0, False: 0] ------------------ 528| 0| case 2: OW->write16(uint16_t(AF.getValue())); break; ------------------ | Branch (528:7): [True: 0, False: 0] ------------------ 529| 0| case 4: OW->write32(uint32_t(AF.getValue())); break; ------------------ | Branch (529:7): [True: 0, False: 0] ------------------ 530| 0| case 8: OW->write64(uint64_t(AF.getValue())); break; ------------------ | Branch (530:7): [True: 0, False: 0] ------------------ 531| 0| } 532| 0| } 533| 0| break; 534| 0| } 535| | 536| 387| case MCFragment::FT_Data: ------------------ | Branch (536:3): [True: 387, False: 1.23k] ------------------ 537| 387| OW->writeBytes(cast(F).getContents()); 538| 387| break; 539| | 540| 355| case MCFragment::FT_Relaxable: ------------------ | Branch (540:3): [True: 355, False: 1.26k] ------------------ 541| 355| OW->writeBytes(cast(F).getContents()); 542| 355| break; 543| | 544| 0| case MCFragment::FT_CompactEncodedInst: ------------------ | Branch (544:3): [True: 0, False: 1.62k] ------------------ 545| 0| OW->writeBytes(cast(F).getContents()); 546| 0| break; 547| | 548| 292| case MCFragment::FT_Fill: { ------------------ | Branch (548:3): [True: 292, False: 1.33k] ------------------ 549| 292| const MCFillFragment &FF = cast(F); 550| 292| uint8_t V = FF.getValue(); 551| 292| const unsigned MaxChunkSize = 16; 552| 292| char Data[MaxChunkSize]; 553| 292| memcpy(Data, &V, 1); 554| 4.67k| for (unsigned I = 1; I < MaxChunkSize; ++I) ------------------ | Branch (554:26): [True: 4.38k, False: 292] ------------------ 555| 4.38k| Data[I] = Data[0]; 556| | 557| 292| uint64_t Size = FF.getSize(); 558| 1.75k| for (unsigned ChunkSize = MaxChunkSize; ChunkSize; ChunkSize /= 2) { ------------------ | Branch (558:45): [True: 1.46k, False: 292] ------------------ 559| 1.46k| StringRef Ref(Data, ChunkSize); 560| 14.6k| for (uint64_t I = 0, E = Size / ChunkSize; I != E; ++I) ------------------ | Branch (560:50): [True: 13.2k, False: 1.46k] ------------------ 561| 13.2k| OW->writeBytes(Ref); 562| 1.46k| Size = Size % ChunkSize; 563| 1.46k| } 564| 292| break; 565| 0| } 566| | 567| 0| case MCFragment::FT_LEB: { ------------------ | Branch (567:3): [True: 0, False: 1.62k] ------------------ 568| 0| const MCLEBFragment &LF = cast(F); 569| 0| OW->writeBytes(LF.getContents()); 570| 0| break; 571| 0| } 572| | 573| 0| case MCFragment::FT_SafeSEH: { ------------------ | Branch (573:3): [True: 0, False: 1.62k] ------------------ 574| 0| const MCSafeSEHFragment &SF = cast(F); 575| 0| OW->write32(SF.getSymbol()->getIndex()); 576| 0| break; 577| 0| } 578| | 579| 95| case MCFragment::FT_Org: { ------------------ | Branch (579:3): [True: 95, False: 1.52k] ------------------ 580| 95| const MCOrgFragment &OF = cast(F); 581| | 582| 134| for (uint64_t i = 0, e = FragmentSize; i != e; ++i) ------------------ | Branch (582:44): [True: 39, False: 95] ------------------ 583| 39| OW->write8(uint8_t(OF.getValue())); 584| | 585| 95| break; 586| 0| } 587| | 588| 0| case MCFragment::FT_Dwarf: { ------------------ | Branch (588:3): [True: 0, False: 1.62k] ------------------ 589| 0| const MCDwarfLineAddrFragment &OF = cast(F); 590| 0| OW->writeBytes(OF.getContents()); 591| 0| break; 592| 0| } 593| 0| case MCFragment::FT_DwarfFrame: { ------------------ | Branch (593:3): [True: 0, False: 1.62k] ------------------ 594| 0| const MCDwarfCallFrameFragment &CF = cast(F); 595| 0| OW->writeBytes(CF.getContents()); 596| 0| break; 597| 0| } 598| 0| case MCFragment::FT_Dummy: ------------------ | Branch (598:3): [True: 0, False: 1.62k] ------------------ 599| 0| llvm_unreachable("Should not have been added"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 600| 1.62k| } 601| | 602| 1.62k| assert(OW->getStream().tell() - Start == FragmentSize && ------------------ | Branch (602:3): [True: 1.62k, False: 0] | Branch (602:3): [True: 1.62k, Folded] | Branch (602:3): [True: 1.62k, False: 0] ------------------ 603| 1.62k| "The stream should advance by fragment size"); 604| 1.62k|} _ZN7llvm_ks13MCCodeEmitterC2Ev: 14| 430|MCCodeEmitter::MCCodeEmitter() { 15| 430|} _ZN7llvm_ks13MCCodeEmitterD2Ev: 17| 430|MCCodeEmitter::~MCCodeEmitter() { 18| 430|} _ZN7llvm_ks9MCContextC2EPKNS_9MCAsmInfoEPKNS_14MCRegisterInfoEPKNS_16MCObjectFileInfoEPKNS_9SourceMgrEbm: 40| 430| : SrcMgr(mgr), MAI(mai), MRI(mri), MOFI(mofi), Allocator(), 41| 430| Symbols(Allocator), UsedNames(Allocator), 42| 430| CurrentDwarfLoc(0, 0, 0, DWARF2_FLAG_IS_STMT, 0, 0), DwarfLocSeen(false), ------------------ | | 68| 430|#define DWARF2_FLAG_IS_STMT (1 << 0) ------------------ 43| 430| GenDwarfForAssembly(false), GenDwarfFileNumber(0), DwarfVersion(4), 44| 430| AllowTemporaryLabels(true), DwarfCompileUnitID(0), 45| 430| AutoReset(DoAutoReset), HadError(false), BaseAddress(BaseAddr) { 46| | 47| 430| std::error_code EC = llvm_ks::sys::fs::current_path(CompilationDir); 48| 430| if (EC) ------------------ | Branch (48:7): [True: 0, False: 430] ------------------ 49| 0| CompilationDir.clear(); 50| | 51| 430| SecureLogFile = getenv("AS_SECURE_LOG_FILE"); 52| 430| SecureLog = nullptr; 53| 430| SecureLogUsed = false; 54| | 55| 430| if (SrcMgr && SrcMgr->getNumBuffers()) ------------------ | Branch (55:7): [True: 430, False: 0] | Branch (55:17): [True: 0, False: 430] ------------------ 56| 0| MainFileName = 57| 0| SrcMgr->getMemoryBuffer(SrcMgr->getMainFileID())->getBufferIdentifier(); 58| 430|} _ZN7llvm_ks9MCContextD2Ev: 60| 430|MCContext::~MCContext() { 61| 430| if (AutoReset) ------------------ | Branch (61:7): [True: 430, False: 0] ------------------ 62| 430| reset(); 63| | 64| | // NOTE: The symbols are all allocated out of a bump pointer allocator, 65| | // we don't need to free them here. 66| 430|} _ZN7llvm_ks9MCContext5resetEv: 72| 430|void MCContext::reset() { 73| | // Call the destructors so the fragments are freed 74| 430| COFFAllocator.DestroyAll(); 75| 430| ELFAllocator.DestroyAll(); 76| 430| MachOAllocator.DestroyAll(); 77| | 78| 430| MCSubtargetAllocator.DestroyAll(); 79| 430| UsedNames.clear(); 80| 430| Symbols.clear(); 81| 430| SectionSymbols.clear(); 82| 430| Allocator.Reset(); 83| 430| Instances.clear(); 84| 430| CompilationDir.clear(); 85| 430| MainFileName.clear(); 86| 430| MCDwarfLineTablesCUMap.clear(); 87| 430| SectionsForRanges.clear(); 88| 430| MCGenDwarfLabelEntries.clear(); 89| 430| DwarfDebugFlags = StringRef(); 90| 430| DwarfCompileUnitID = 0; 91| 430| CurrentDwarfLoc = MCDwarfLoc(0, 0, 0, DWARF2_FLAG_IS_STMT, 0, 0); ------------------ | | 68| 430|#define DWARF2_FLAG_IS_STMT (1 << 0) ------------------ 92| | 93| 430| MachOUniquingMap.clear(); 94| 430| ELFUniquingMap.clear(); 95| 430| COFFUniquingMap.clear(); 96| | 97| 430| NextID.clear(); 98| 430| AllowTemporaryLabels = true; 99| 430| DwarfLocSeen = false; 100| 430| GenDwarfForAssembly = false; 101| 430| GenDwarfFileNumber = 0; 102| | 103| 430| HadError = false; 104| 430|} _ZN7llvm_ks9MCContext17getOrCreateSymbolERKNS_5TwineE: 110| 13.9k|MCSymbol *MCContext::getOrCreateSymbol(const Twine &Name) { 111| 13.9k| SmallString<128> NameSV; 112| 13.9k| StringRef NameRef = Name.toStringRef(NameSV); 113| | 114| 13.9k| assert(!NameRef.empty() && "Normal symbols cannot be unnamed!"); ------------------ | Branch (114:3): [True: 13.9k, False: 0] | Branch (114:3): [True: 13.9k, Folded] | Branch (114:3): [True: 13.9k, False: 0] ------------------ 115| | 116| 13.9k| MCSymbol *&Sym = Symbols[NameRef]; 117| 13.9k| if (!Sym) ------------------ | Branch (117:7): [True: 1.50k, False: 12.4k] ------------------ 118| 1.50k| Sym = createSymbol(NameRef, false, false); 119| | 120| 13.9k| return Sym; 121| 13.9k|} _ZN7llvm_ks9MCContext24getOrCreateSectionSymbolERKNS_12MCSectionELFE: 123| 434|MCSymbolELF *MCContext::getOrCreateSectionSymbol(const MCSectionELF &Section) { 124| 434| MCSymbolELF *&Sym = SectionSymbols[&Section]; 125| 434| if (Sym) ------------------ | Branch (125:7): [True: 0, False: 434] ------------------ 126| 0| return Sym; 127| | 128| 434| StringRef Name = Section.getSectionName(); 129| | 130| 434| MCSymbol *&OldSym = Symbols[Name]; 131| 434| if (OldSym && OldSym->isUndefined()) { ------------------ | Branch (131:7): [True: 1, False: 433] | Branch (131:17): [True: 0, False: 1] ------------------ 132| 0| Sym = cast(OldSym); 133| 0| return Sym; 134| 0| } 135| | 136| 434| auto NameIter = UsedNames.insert(std::make_pair(Name, true)).first; 137| 434| Sym = new (&*NameIter, *this) MCSymbolELF(&*NameIter, /*isTemporary*/ false); 138| | 139| 434| if (!OldSym) ------------------ | Branch (139:7): [True: 433, False: 1] ------------------ 140| 433| OldSym = Sym; 141| | 142| 434| return Sym; 143| 434|} _ZN7llvm_ks9MCContext16createSymbolImplEPKNS_14StringMapEntryIbEEb: 162| 11.2k| bool IsTemporary) { 163| 11.2k| if (MOFI) { ------------------ | Branch (163:7): [True: 11.2k, False: 0] ------------------ 164| 11.2k| switch (MOFI->getObjectFileType()) { ------------------ | Branch (164:13): [True: 11.2k, False: 0] ------------------ 165| 0| case MCObjectFileInfo::IsCOFF: ------------------ | Branch (165:5): [True: 0, False: 11.2k] ------------------ 166| 0| return new (Name, *this) MCSymbolCOFF(Name, IsTemporary); 167| 11.2k| case MCObjectFileInfo::IsELF: ------------------ | Branch (167:5): [True: 11.2k, False: 0] ------------------ 168| 11.2k| return new (Name, *this) MCSymbolELF(Name, IsTemporary); 169| 0| case MCObjectFileInfo::IsMachO: ------------------ | Branch (169:5): [True: 0, False: 11.2k] ------------------ 170| 0| return new (Name, *this) MCSymbolMachO(Name, IsTemporary); 171| 11.2k| } 172| 11.2k| } 173| 0| return new (Name, *this) MCSymbol(MCSymbol::SymbolKindUnset, Name, 174| 0| IsTemporary); 175| 11.2k|} _ZN7llvm_ks9MCContext12createSymbolENS_9StringRefEbb: 178| 11.2k| bool CanBeUnnamed) { 179| 11.2k| if (CanBeUnnamed && !UseNamesOnTempLabels) ------------------ | Branch (179:7): [True: 9.76k, False: 1.50k] | Branch (179:23): [True: 0, False: 9.76k] ------------------ 180| 0| return createSymbolImpl(nullptr, true); 181| | 182| | // Determine whether this is an user writter assembler temporary or normal 183| | // label, if used. 184| 11.2k| bool IsTemporary = CanBeUnnamed; 185| 11.2k| if (AllowTemporaryLabels && !IsTemporary) ------------------ | Branch (185:7): [True: 11.2k, False: 0] | Branch (185:31): [True: 1.50k, False: 9.76k] ------------------ 186| 1.50k| IsTemporary = Name.startswith(MAI->getPrivateGlobalPrefix()); 187| | 188| 11.2k| SmallString<128> NewName = Name; 189| 11.2k| bool AddSuffix = AlwaysAddSuffix; 190| 11.2k| unsigned &NextUniqueID = NextID[Name]; 191| 11.2k| for (;;) { 192| 11.2k| if (AddSuffix) { ------------------ | Branch (192:9): [True: 5.46k, False: 5.80k] ------------------ 193| 5.46k| NewName.resize(Name.size()); 194| 5.46k| raw_svector_ostream(NewName) << NextUniqueID++; 195| 5.46k| } 196| 11.2k| auto NameEntry = UsedNames.insert(std::make_pair(NewName, true)); 197| 11.2k| if (NameEntry.second) { ------------------ | Branch (197:9): [True: 11.2k, False: 0] ------------------ 198| | // Ok, we found a name. Have the MCSymbol object itself refer to the copy 199| | // of the string that is embedded in the UsedNames entry. 200| 11.2k| return createSymbolImpl(&*NameEntry.first, IsTemporary); 201| 11.2k| } 202| 11.2k| assert(IsTemporary && "Cannot rename non-temporary symbols"); ------------------ | Branch (202:5): [True: 0, False: 0] | Branch (202:5): [True: 0, Folded] | Branch (202:5): [True: 0, False: 0] ------------------ 203| 0| AddSuffix = true; 204| 0| } 205| 0| llvm_unreachable("Infinite loop"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 206| 11.2k|} _ZN7llvm_ks9MCContext16createTempSymbolERKNS_5TwineEbb: 209| 9.76k| bool CanBeUnnamed) { 210| 9.76k| SmallString<128> NameSV; 211| 9.76k| raw_svector_ostream(NameSV) << MAI->getPrivateGlobalPrefix() << Name; 212| 9.76k| return createSymbol(NameSV, AlwaysAddSuffix, CanBeUnnamed); 213| 9.76k|} _ZN7llvm_ks9MCContext16createTempSymbolEb: 221| 5.46k|MCSymbol *MCContext::createTempSymbol(bool CanBeUnnamed) { 222| 5.46k| return createTempSymbol("tmp", true, CanBeUnnamed); 223| 5.46k|} _ZN7llvm_ks9MCContext11GetInstanceEjRb: 238| 2|{ 239| 2| if (LocalLabelVal >= Instances.size()) { ------------------ | Branch (239:7): [True: 2, False: 0] ------------------ 240| 2| valid = false; 241| 2| return 0; 242| 2| } 243| 0| MCLabel *&Label = Instances[LocalLabelVal]; 244| 0| if (!Label) ------------------ | Branch (244:7): [True: 0, False: 0] ------------------ 245| 0| Label = new (*this) MCLabel(0); 246| 0| return Label->getInstance(); 247| 2|} _ZN7llvm_ks9MCContext25getDirectionalLocalSymbolEjbRb: 268| 2|{ 269| 2| valid = true; 270| 2| unsigned Instance = GetInstance(LocalLabelVal, valid); 271| 2| if (!valid) ------------------ | Branch (271:7): [True: 2, False: 0] ------------------ 272| 2| return nullptr; 273| 0| if (!Before) ------------------ | Branch (273:7): [True: 0, False: 0] ------------------ 274| 0| ++Instance; 275| 0| return getOrCreateDirectionalLocalSymbol(LocalLabelVal, Instance); 276| 2|} _ZNK7llvm_ks9MCContext12lookupSymbolERKNS_5TwineE: 278| 783|MCSymbol *MCContext::lookupSymbol(const Twine &Name) const { 279| 783| SmallString<128> NameSV; 280| 783| StringRef NameRef = Name.toStringRef(NameSV); 281| 783| return Symbols.lookup(NameRef); 282| 783|} _ZN7llvm_ks9MCContext15getMachOSectionENS_9StringRefES1_jjNS_11SectionKindEPKc: 291| 143| const char *BeginSymName) { 292| | 293| | // We unique sections by their segment/section pair. The returned section 294| | // may not have the same flags as the requested section, if so this should be 295| | // diagnosed by the client as an error. 296| | 297| | // Form the name to look up. 298| 143| SmallString<64> Name; 299| 143| Name += Segment; 300| 143| Name.push_back(','); 301| 143| Name += Section; 302| | 303| | // Do the lookup, if we have a hit, return it. 304| 143| MCSectionMachO *&Entry = MachOUniquingMap[Name]; 305| 143| if (Entry) ------------------ | Branch (305:7): [True: 139, False: 4] ------------------ 306| 139| return Entry; 307| | 308| 4| MCSymbol *Begin = nullptr; 309| 4| if (BeginSymName) ------------------ | Branch (309:7): [True: 0, False: 4] ------------------ 310| 0| Begin = createTempSymbol(BeginSymName, false); 311| | 312| | // Otherwise, return a new section. 313| 4| return Entry = new (MachOAllocator.Allocate()) MCSectionMachO( 314| 4| Segment, Section, TypeAndAttributes, Reserved2, Kind, Begin); 315| 143|} _ZN7llvm_ks9MCContext19createELFRelSectionENS_9StringRefEjjjPKNS_11MCSymbolELFEPKNS_12MCSectionELFE: 336| 25| const MCSectionELF *Associated) { 337| 25| StringMap::iterator I; 338| 25| bool Inserted; 339| 25| std::tie(I, Inserted) = ELFRelSecNames.insert(std::make_pair(Name, true)); 340| | 341| 25| return new (ELFAllocator.Allocate()) 342| 25| MCSectionELF(I->getKey(), Type, Flags, SectionKind::getReadOnly(), 343| 25| EntrySize, Group, true, nullptr, Associated); 344| 25|} _ZN7llvm_ks9MCContext13getELFSectionENS_9StringRefEjjjS1_jPKc: 349| 18.6k| const char *BeginSymName) { 350| 18.6k| MCSymbolELF *GroupSym = nullptr; 351| 18.6k| if (!Group.empty()) ------------------ | Branch (351:7): [True: 0, False: 18.6k] ------------------ 352| 0| GroupSym = cast(getOrCreateSymbol(Group)); 353| | 354| 18.6k| return getELFSection(Section, Type, Flags, EntrySize, GroupSym, UniqueID, 355| 18.6k| BeginSymName, nullptr); 356| 18.6k|} _ZN7llvm_ks9MCContext13getELFSectionENS_9StringRefEjjjPKNS_11MCSymbolELFEjPKcPKNS_12MCSectionELFE: 363| 18.6k| const MCSectionELF *Associated) { 364| 18.6k| StringRef Group = ""; 365| 18.6k| if (GroupSym) ------------------ | Branch (365:7): [True: 0, False: 18.6k] ------------------ 366| 0| Group = GroupSym->getName(); 367| | // Do the lookup, if we have a hit, return it. 368| 18.6k| auto IterBool = ELFUniquingMap.insert( 369| 18.6k| std::make_pair(ELFSectionKey{Section, Group, UniqueID}, nullptr)); 370| 18.6k| auto &Entry = *IterBool.first; 371| 18.6k| if (!IterBool.second) ------------------ | Branch (371:7): [True: 0, False: 18.6k] ------------------ 372| 0| return Entry.second; 373| | 374| 18.6k| StringRef CachedName = Entry.first.SectionName; 375| | 376| 18.6k| SectionKind Kind; 377| 18.6k| if (Flags & ELF::SHF_EXECINSTR) ------------------ | Branch (377:7): [True: 430, False: 18.2k] ------------------ 378| 430| Kind = SectionKind::getText(); 379| 18.2k| else 380| 18.2k| Kind = SectionKind::getReadOnly(); 381| | 382| 18.6k| MCSymbol *Begin = nullptr; 383| 18.6k| if (BeginSymName) ------------------ | Branch (383:7): [True: 4.30k, False: 14.3k] ------------------ 384| 4.30k| Begin = createTempSymbol(BeginSymName, false); 385| | 386| 18.6k| MCSectionELF *Result = new (ELFAllocator.Allocate()) 387| 18.6k| MCSectionELF(CachedName, Type, Flags, Kind, EntrySize, GroupSym, UniqueID, 388| 18.6k| Begin, Associated); 389| 18.6k| Entry.second = Result; 390| 18.6k| return Result; 391| 18.6k|} _ZN7llvm_ks9MCContext16getSubtargetCopyERKNS_15MCSubtargetInfoE: 460| 2.67k|MCSubtargetInfo &MCContext::getSubtargetCopy(const MCSubtargetInfo &STI) { 461| 2.67k| return *new (MCSubtargetAllocator.Allocate()) MCSubtargetInfo(STI); 462| 2.67k|} _ZN7llvm_ks9MCContext11reportErrorENS_5SMLocERKNS_5TwineE: 506| 106|void MCContext::reportError(SMLoc Loc, const Twine &Msg) { 507| 106| HadError = true; 508| | 509| | // If we have a source manager use it. Otherwise just use the generic 510| | // report_fatal_error(). 511| 106| if (!SrcMgr) ------------------ | Branch (511:7): [True: 0, False: 106] ------------------ 512| 0| report_fatal_error(Msg, false); 513| | 514| | // Use the source manager to print the message. 515| 106| SrcMgr->PrintMessage(Loc, SourceMgr::DK_Error, Msg); 516| 106|} _ZN7llvm_ks23MCELFObjectTargetWriterC2Ebhtbb: 22| 430| : OSABI(OSABI_), EMachine(EMachine_), 23| 430| HasRelocationAddend(HasRelocationAddend_), Is64Bit(Is64Bit_), 24| 430| IsN64(IsN64_){ 25| 430|} _ZNK7llvm_ks13MCELFStreamer14isBundleLockedEv: 43| 1.34k|bool MCELFStreamer::isBundleLocked() const { 44| 1.34k| return getCurrentSectionOnly()->isBundleLocked(); 45| 1.34k|} _ZN7llvm_ks13MCELFStreamerD2Ev: 47| 430|MCELFStreamer::~MCELFStreamer() { 48| 430|} _ZN7llvm_ks13MCELFStreamer12InitSectionsEb: 91| 430|void MCELFStreamer::InitSections(bool NoExecStack) { 92| 430| MCContext &Ctx = getContext(); 93| 430| SwitchSection(Ctx.getObjectFileInfo()->getTextSection()); 94| | 95| 430| if (NoExecStack) ------------------ | Branch (95:7): [True: 0, False: 430] ------------------ 96| 0| SwitchSection(Ctx.getAsmInfo()->getNonexecutableStackSection(Ctx)); 97| 430|} _ZN7llvm_ks13MCELFStreamer9EmitLabelEPNS_8MCSymbolE: 99| 5.85k|void MCELFStreamer::EmitLabel(MCSymbol *S) { 100| 5.85k| auto *Symbol = cast(S); 101| 5.85k| assert(Symbol->isUndefined() && "Cannot define a symbol twice!"); ------------------ | Branch (101:3): [True: 5.85k, False: 0] | Branch (101:3): [True: 5.85k, Folded] | Branch (101:3): [True: 5.85k, False: 0] ------------------ 102| | 103| 5.85k| MCObjectStreamer::EmitLabel(Symbol); 104| | 105| 5.85k| const MCSectionELF &Section = 106| 5.85k| static_cast(*getCurrentSectionOnly()); 107| 5.85k| if (Section.getFlags() & ELF::SHF_TLS) ------------------ | Branch (107:7): [True: 0, False: 5.85k] ------------------ 108| 0| Symbol->setType(ELF::STT_TLS); 109| 5.85k|} _ZN7llvm_ks13MCELFStreamer17EmitAssemblerFlagENS_15MCAssemblerFlagE: 111| 191|void MCELFStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { 112| | // Let the target do whatever target specific stuff it needs to do. 113| 191| getAssembler().getBackend().handleAssemblerFlag(Flag); 114| | // Do any generic stuff we need to do. 115| 191| switch (Flag) { ------------------ | Branch (115:11): [True: 191, False: 0] ------------------ 116| 0| case MCAF_SyntaxUnified: return; // no-op here. ------------------ | Branch (116:3): [True: 0, False: 191] ------------------ 117| 56| case MCAF_Code16: return; // Change parsing mode; no-op here. ------------------ | Branch (117:3): [True: 56, False: 135] ------------------ 118| 135| case MCAF_Code32: return; // Change parsing mode; no-op here. ------------------ | Branch (118:3): [True: 135, False: 56] ------------------ 119| 0| case MCAF_Code64: return; // Change parsing mode; no-op here. ------------------ | Branch (119:3): [True: 0, False: 191] ------------------ 120| 0| case MCAF_SubsectionsViaSymbols: ------------------ | Branch (120:3): [True: 0, False: 191] ------------------ 121| 0| getAssembler().setSubsectionsViaSymbols(true); 122| 0| return; 123| 191| } 124| | 125| 0| llvm_unreachable("invalid assembler flag!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 126| 191|} _ZN7llvm_ks13MCELFStreamer13ChangeSectionEPNS_9MCSectionEPKNS_6MCExprE: 138| 434| const MCExpr *Subsection) { 139| 434| MCSection *CurSection = getCurrentSectionOnly(); 140| 434| if (CurSection && isBundleLocked()) ------------------ | Branch (140:7): [True: 4, False: 430] | Branch (140:21): [True: 0, False: 4] ------------------ 141| 0| report_fatal_error("Unterminated .bundle_lock when changing a section"); 142| | 143| 434| MCAssembler &Asm = getAssembler(); 144| | // Ensure the previous section gets aligned if necessary. 145| 434| setSectionAlignmentForBundling(Asm, CurSection); 146| 434| auto *SectionELF = static_cast(Section); 147| 434| const MCSymbol *Grp = SectionELF->getGroup(); 148| 434| if (Grp) ------------------ | Branch (148:7): [True: 0, False: 434] ------------------ 149| 0| Asm.registerSymbol(*Grp); 150| | 151| 434| this->MCObjectStreamer::ChangeSection(Section, Subsection); 152| 434| MCContext &Ctx = getContext(); 153| 434| auto *Begin = cast_or_null(Section->getBeginSymbol()); 154| 434| if (!Begin) { ------------------ | Branch (154:7): [True: 434, False: 0] ------------------ 155| 434| Begin = Ctx.getOrCreateSectionSymbol(*SectionELF); 156| 434| Section->setBeginSymbol(Begin); 157| 434| } 158| 434| if (Begin->isUndefined()) { ------------------ | Branch (158:7): [True: 434, False: 0] ------------------ 159| 434| Asm.registerSymbol(*Begin); 160| 434| Begin->setType(ELF::STT_SECTION); 161| 434| } 162| 434|} _ZN7llvm_ks13MCELFStreamer16EmitCommonSymbolEPNS_8MCSymbolEmj: 297| 589| unsigned ByteAlignment) { 298| 589| auto *Symbol = cast(S); 299| 589| getAssembler().registerSymbol(*Symbol); 300| | 301| 589| if (!Symbol->isBindingSet()) { ------------------ | Branch (301:7): [True: 10, False: 579] ------------------ 302| 10| Symbol->setBinding(ELF::STB_GLOBAL); 303| 10| Symbol->setExternal(true); 304| 10| } 305| | 306| 589| Symbol->setType(ELF::STT_OBJECT); 307| | 308| 589| if (Symbol->getBinding() == ELF::STB_LOCAL) { ------------------ | Branch (308:7): [True: 0, False: 589] ------------------ 309| 0| MCSection &Section = *getAssembler().getContext().getELFSection( 310| 0| ".bss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); 311| 0| MCSectionSubPair P = getCurrentSection(); 312| 0| SwitchSection(&Section); 313| | 314| 0| EmitValueToAlignment(ByteAlignment, 0, 1, 0); 315| 0| EmitLabel(Symbol); 316| 0| EmitZeros(Size); 317| | 318| | // Update the maximum alignment of the section if necessary. 319| 0| if (ByteAlignment > Section.getAlignment()) ------------------ | Branch (319:9): [True: 0, False: 0] ------------------ 320| 0| Section.setAlignment(ByteAlignment); 321| | 322| 0| SwitchSection(P.first, P.second); 323| 589| } else { 324| 589| if(Symbol->declareCommon(Size, ByteAlignment)) ------------------ | Branch (324:8): [True: 0, False: 589] ------------------ 325| 0| report_fatal_error("Symbol: " + Symbol->getName() + 326| 0| " redeclared as different type"); 327| 589| } 328| | 329| 589| cast(Symbol) 330| 589| ->setSize(MCConstantExpr::create(Size, getContext())); 331| 589|} _ZN7llvm_ks13MCELFStreamer13EmitValueImplEPKNS_6MCExprEjNS_5SMLocE: 348| 610| SMLoc Loc) { 349| 610| if (isBundleLocked()) ------------------ | Branch (349:7): [True: 0, False: 610] ------------------ 350| 0| report_fatal_error("Emitting values inside a locked bundle is forbidden"); 351| 610| fixSymbolsInTLSFixups(Value); 352| 610| MCObjectStreamer::EmitValueImpl(Value, Size, Loc); 353| 610|} _ZN7llvm_ks13MCELFStreamer20EmitValueToAlignmentEjljj: 358| 732| unsigned MaxBytesToEmit) { 359| 732| if (isBundleLocked()) ------------------ | Branch (359:7): [True: 0, False: 732] ------------------ 360| 0| report_fatal_error("Emitting values inside a locked bundle is forbidden"); 361| 732| MCObjectStreamer::EmitValueToAlignment(ByteAlignment, Value, 362| 732| ValueSize, MaxBytesToEmit); 363| 732|} _ZN7llvm_ks13MCELFStreamer17EmitFileDirectiveENS_9StringRefE: 368| 303|void MCELFStreamer::EmitFileDirective(StringRef Filename) { 369| 303| getAssembler().addFileName(Filename); 370| 303|} _ZN7llvm_ks13MCELFStreamer21fixSymbolsInTLSFixupsEPKNS_6MCExprE: 387| 5.64k|void MCELFStreamer::fixSymbolsInTLSFixups(const MCExpr *expr) { 388| 5.64k| switch (expr->getKind()) { ------------------ | Branch (388:11): [True: 5.64k, False: 0] ------------------ 389| 0| case MCExpr::Target: ------------------ | Branch (389:3): [True: 0, False: 5.64k] ------------------ 390| 0| cast(expr)->fixELFSymbolsInTLSFixups(getAssembler()); 391| 0| break; 392| 1.21k| case MCExpr::Constant: ------------------ | Branch (392:3): [True: 1.21k, False: 4.43k] ------------------ 393| 1.21k| break; 394| | 395| 960| case MCExpr::Binary: { ------------------ | Branch (395:3): [True: 960, False: 4.68k] ------------------ 396| 960| const MCBinaryExpr *be = cast(expr); 397| 960| fixSymbolsInTLSFixups(be->getLHS()); 398| 960| fixSymbolsInTLSFixups(be->getRHS()); 399| 960| break; 400| 0| } 401| | 402| 1.30k| case MCExpr::SymbolRef: { ------------------ | Branch (402:3): [True: 1.30k, False: 4.34k] ------------------ 403| 1.30k| const MCSymbolRefExpr &symRef = *cast(expr); 404| 1.30k| switch (symRef.getKind()) { 405| 1.30k| default: ------------------ | Branch (405:5): [True: 1.30k, False: 0] ------------------ 406| 1.30k| return; 407| 1.30k| case MCSymbolRefExpr::VK_GOTTPOFF: ------------------ | Branch (407:5): [True: 0, False: 1.30k] ------------------ 408| 0| case MCSymbolRefExpr::VK_INDNTPOFF: ------------------ | Branch (408:5): [True: 0, False: 1.30k] ------------------ 409| 0| case MCSymbolRefExpr::VK_NTPOFF: ------------------ | Branch (409:5): [True: 0, False: 1.30k] ------------------ 410| 0| case MCSymbolRefExpr::VK_GOTNTPOFF: ------------------ | Branch (410:5): [True: 0, False: 1.30k] ------------------ 411| 0| case MCSymbolRefExpr::VK_TLSGD: ------------------ | Branch (411:5): [True: 0, False: 1.30k] ------------------ 412| 0| case MCSymbolRefExpr::VK_TLSLD: ------------------ | Branch (412:5): [True: 0, False: 1.30k] ------------------ 413| 0| case MCSymbolRefExpr::VK_TLSLDM: ------------------ | Branch (413:5): [True: 0, False: 1.30k] ------------------ 414| 0| case MCSymbolRefExpr::VK_TPOFF: ------------------ | Branch (414:5): [True: 0, False: 1.30k] ------------------ 415| 0| case MCSymbolRefExpr::VK_TPREL: ------------------ | Branch (415:5): [True: 0, False: 1.30k] ------------------ 416| 0| case MCSymbolRefExpr::VK_DTPOFF: ------------------ | Branch (416:5): [True: 0, False: 1.30k] ------------------ 417| 0| case MCSymbolRefExpr::VK_DTPREL: ------------------ | Branch (417:5): [True: 0, False: 1.30k] ------------------ 418| 0| case MCSymbolRefExpr::VK_Mips_TLSGD: ------------------ | Branch (418:5): [True: 0, False: 1.30k] ------------------ 419| 0| case MCSymbolRefExpr::VK_Mips_GOTTPREL: ------------------ | Branch (419:5): [True: 0, False: 1.30k] ------------------ 420| 0| case MCSymbolRefExpr::VK_Mips_TPREL_HI: ------------------ | Branch (420:5): [True: 0, False: 1.30k] ------------------ 421| 0| case MCSymbolRefExpr::VK_Mips_TPREL_LO: ------------------ | Branch (421:5): [True: 0, False: 1.30k] ------------------ 422| 0| case MCSymbolRefExpr::VK_PPC_DTPMOD: ------------------ | Branch (422:5): [True: 0, False: 1.30k] ------------------ 423| 0| case MCSymbolRefExpr::VK_PPC_TPREL_LO: ------------------ | Branch (423:5): [True: 0, False: 1.30k] ------------------ 424| 0| case MCSymbolRefExpr::VK_PPC_TPREL_HI: ------------------ | Branch (424:5): [True: 0, False: 1.30k] ------------------ 425| 0| case MCSymbolRefExpr::VK_PPC_TPREL_HA: ------------------ | Branch (425:5): [True: 0, False: 1.30k] ------------------ 426| 0| case MCSymbolRefExpr::VK_PPC_TPREL_HIGHER: ------------------ | Branch (426:5): [True: 0, False: 1.30k] ------------------ 427| 0| case MCSymbolRefExpr::VK_PPC_TPREL_HIGHERA: ------------------ | Branch (427:5): [True: 0, False: 1.30k] ------------------ 428| 0| case MCSymbolRefExpr::VK_PPC_TPREL_HIGHEST: ------------------ | Branch (428:5): [True: 0, False: 1.30k] ------------------ 429| 0| case MCSymbolRefExpr::VK_PPC_TPREL_HIGHESTA: ------------------ | Branch (429:5): [True: 0, False: 1.30k] ------------------ 430| 0| case MCSymbolRefExpr::VK_PPC_DTPREL_LO: ------------------ | Branch (430:5): [True: 0, False: 1.30k] ------------------ 431| 0| case MCSymbolRefExpr::VK_PPC_DTPREL_HI: ------------------ | Branch (431:5): [True: 0, False: 1.30k] ------------------ 432| 0| case MCSymbolRefExpr::VK_PPC_DTPREL_HA: ------------------ | Branch (432:5): [True: 0, False: 1.30k] ------------------ 433| 0| case MCSymbolRefExpr::VK_PPC_DTPREL_HIGHER: ------------------ | Branch (433:5): [True: 0, False: 1.30k] ------------------ 434| 0| case MCSymbolRefExpr::VK_PPC_DTPREL_HIGHERA: ------------------ | Branch (434:5): [True: 0, False: 1.30k] ------------------ 435| 0| case MCSymbolRefExpr::VK_PPC_DTPREL_HIGHEST: ------------------ | Branch (435:5): [True: 0, False: 1.30k] ------------------ 436| 0| case MCSymbolRefExpr::VK_PPC_DTPREL_HIGHESTA: ------------------ | Branch (436:5): [True: 0, False: 1.30k] ------------------ 437| 0| case MCSymbolRefExpr::VK_PPC_GOT_TPREL: ------------------ | Branch (437:5): [True: 0, False: 1.30k] ------------------ 438| 0| case MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO: ------------------ | Branch (438:5): [True: 0, False: 1.30k] ------------------ 439| 0| case MCSymbolRefExpr::VK_PPC_GOT_TPREL_HI: ------------------ | Branch (439:5): [True: 0, False: 1.30k] ------------------ 440| 0| case MCSymbolRefExpr::VK_PPC_GOT_TPREL_HA: ------------------ | Branch (440:5): [True: 0, False: 1.30k] ------------------ 441| 0| case MCSymbolRefExpr::VK_PPC_GOT_DTPREL: ------------------ | Branch (441:5): [True: 0, False: 1.30k] ------------------ 442| 0| case MCSymbolRefExpr::VK_PPC_GOT_DTPREL_LO: ------------------ | Branch (442:5): [True: 0, False: 1.30k] ------------------ 443| 0| case MCSymbolRefExpr::VK_PPC_GOT_DTPREL_HI: ------------------ | Branch (443:5): [True: 0, False: 1.30k] ------------------ 444| 0| case MCSymbolRefExpr::VK_PPC_GOT_DTPREL_HA: ------------------ | Branch (444:5): [True: 0, False: 1.30k] ------------------ 445| 0| case MCSymbolRefExpr::VK_PPC_TLS: ------------------ | Branch (445:5): [True: 0, False: 1.30k] ------------------ 446| 0| case MCSymbolRefExpr::VK_PPC_GOT_TLSGD: ------------------ | Branch (446:5): [True: 0, False: 1.30k] ------------------ 447| 0| case MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO: ------------------ | Branch (447:5): [True: 0, False: 1.30k] ------------------ 448| 0| case MCSymbolRefExpr::VK_PPC_GOT_TLSGD_HI: ------------------ | Branch (448:5): [True: 0, False: 1.30k] ------------------ 449| 0| case MCSymbolRefExpr::VK_PPC_GOT_TLSGD_HA: ------------------ | Branch (449:5): [True: 0, False: 1.30k] ------------------ 450| 0| case MCSymbolRefExpr::VK_PPC_TLSGD: ------------------ | Branch (450:5): [True: 0, False: 1.30k] ------------------ 451| 0| case MCSymbolRefExpr::VK_PPC_GOT_TLSLD: ------------------ | Branch (451:5): [True: 0, False: 1.30k] ------------------ 452| 0| case MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO: ------------------ | Branch (452:5): [True: 0, False: 1.30k] ------------------ 453| 0| case MCSymbolRefExpr::VK_PPC_GOT_TLSLD_HI: ------------------ | Branch (453:5): [True: 0, False: 1.30k] ------------------ 454| 0| case MCSymbolRefExpr::VK_PPC_GOT_TLSLD_HA: ------------------ | Branch (454:5): [True: 0, False: 1.30k] ------------------ 455| 0| case MCSymbolRefExpr::VK_PPC_TLSLD: ------------------ | Branch (455:5): [True: 0, False: 1.30k] ------------------ 456| 0| break; 457| 1.30k| } 458| 0| getAssembler().registerSymbol(symRef.getSymbol()); 459| 0| cast(symRef.getSymbol()).setType(ELF::STT_TLS); 460| 0| break; 461| 1.30k| } 462| | 463| 2.16k| case MCExpr::Unary: ------------------ | Branch (463:3): [True: 2.16k, False: 3.48k] ------------------ 464| 2.16k| fixSymbolsInTLSFixups(cast(expr)->getSubExpr()); 465| 2.16k| break; 466| 5.64k| } 467| 5.64k|} _ZN7llvm_ks13MCELFStreamer18EmitInstToFragmentERNS_6MCInstERKNS_15MCSubtargetInfoE: 470| 850| const MCSubtargetInfo &STI) { 471| 850| this->MCObjectStreamer::EmitInstToFragment(Inst, STI); 472| 850| MCRelaxableFragment &F = *cast(getCurrentFragment()); 473| | 474| 1.55k| for (unsigned i = 0, e = F.getFixups().size(); i != e; ++i) ------------------ | Branch (474:50): [True: 703, False: 850] ------------------ 475| 703| fixSymbolsInTLSFixups(F.getFixups()[i].getValue()); 476| 850|} _ZN7llvm_ks13MCELFStreamer14EmitInstToDataERNS_6MCInstERKNS_15MCSubtargetInfoERj: 481| 1.34k|{ 482| 1.34k| MCAssembler &Assembler = getAssembler(); 483| 1.34k| SmallVector Fixups; 484| 1.34k| SmallString<256> Code; 485| 1.34k| raw_svector_ostream VecOS(Code); 486| 1.34k| Assembler.getEmitter().encodeInstruction(Inst, VecOS, Fixups, STI, KsError); 487| 1.34k| if (KsError) ------------------ | Branch (487:7): [True: 0, False: 1.34k] ------------------ 488| 0| return; 489| | 490| 1.59k| for (unsigned i = 0, e = Fixups.size(); i != e; ++i) ------------------ | Branch (490:43): [True: 251, False: 1.34k] ------------------ 491| 251| fixSymbolsInTLSFixups(Fixups[i].getValue()); 492| | 493| | // There are several possibilities here: 494| | // 495| | // If bundling is disabled, append the encoded instruction to the current data 496| | // fragment (or create a new such fragment if the current fragment is not a 497| | // data fragment). 498| | // 499| | // If bundling is enabled: 500| | // - If we're not in a bundle-locked group, emit the instruction into a 501| | // fragment of its own. If there are no fixups registered for the 502| | // instruction, emit a MCCompactEncodedInstFragment. Otherwise, emit a 503| | // MCDataFragment. 504| | // - If we're in a bundle-locked group, append the instruction to the current 505| | // data fragment because we want all the instructions in a group to get into 506| | // the same fragment. Be careful not to do that for the first instruction in 507| | // the group, though. 508| 1.34k| MCDataFragment *DF; 509| | 510| 1.34k| if (Assembler.isBundlingEnabled()) { ------------------ | Branch (510:7): [True: 0, False: 1.34k] ------------------ 511| 0| MCSection &Sec = *getCurrentSectionOnly(); 512| 0| if (Assembler.getRelaxAll() && isBundleLocked()) ------------------ | Branch (512:9): [True: 0, False: 0] | Branch (512:36): [True: 0, False: 0] ------------------ 513| | // If the -mc-relax-all flag is used and we are bundle-locked, we re-use 514| | // the current bundle group. 515| 0| DF = BundleGroups.back(); 516| 0| else if (Assembler.getRelaxAll() && !isBundleLocked()) ------------------ | Branch (516:14): [True: 0, False: 0] | Branch (516:41): [True: 0, False: 0] ------------------ 517| | // When not in a bundle-locked group and the -mc-relax-all flag is used, 518| | // we create a new temporary fragment which will be later merged into 519| | // the current fragment. 520| 0| DF = new MCDataFragment(); 521| 0| else if (isBundleLocked() && !Sec.isBundleGroupBeforeFirstInst()) ------------------ | Branch (521:14): [True: 0, False: 0] | Branch (521:34): [True: 0, False: 0] ------------------ 522| | // If we are bundle-locked, we re-use the current fragment. 523| | // The bundle-locking directive ensures this is a new data fragment. 524| 0| DF = cast(getCurrentFragment()); 525| 0| else if (!isBundleLocked() && Fixups.size() == 0) { ------------------ | Branch (525:14): [True: 0, False: 0] | Branch (525:35): [True: 0, False: 0] ------------------ 526| | // Optimize memory usage by emitting the instruction to a 527| | // MCCompactEncodedInstFragment when not in a bundle-locked group and 528| | // there are no fixups registered. 529| 0| MCCompactEncodedInstFragment *CEIF = new MCCompactEncodedInstFragment(); 530| 0| insert(CEIF); 531| 0| CEIF->getContents().append(Code.begin(), Code.end()); 532| 0| return; 533| 0| } else { 534| 0| DF = new MCDataFragment(); 535| 0| insert(DF); 536| 0| } 537| 0| if (Sec.getBundleLockState() == MCSection::BundleLockedAlignToEnd) { ------------------ | Branch (537:9): [True: 0, False: 0] ------------------ 538| | // If this fragment is for a group marked "align_to_end", set a flag 539| | // in the fragment. This can happen after the fragment has already been 540| | // created if there are nested bundle_align groups and an inner one 541| | // is the one marked align_to_end. 542| 0| DF->setAlignToBundleEnd(true); 543| 0| } 544| | 545| | // We're now emitting an instruction in a bundle group, so this flag has 546| | // to be turned off. 547| 0| Sec.setBundleGroupBeforeFirstInst(false); 548| 1.34k| } else { 549| 1.34k| DF = getOrCreateDataFragment(); 550| 1.34k| } 551| | 552| | // Add the fixups and data. 553| 1.59k| for (unsigned i = 0, e = Fixups.size(); i != e; ++i) { ------------------ | Branch (553:43): [True: 251, False: 1.34k] ------------------ 554| 251| Fixups[i].setOffset(Fixups[i].getOffset() + DF->getContents().size()); 555| 251| DF->getFixups().push_back(Fixups[i]); 556| 251| } 557| 1.34k| DF->setHasInstructions(true); 558| 1.34k| DF->getContents().append(Code.begin(), Code.end()); 559| | 560| 1.34k| if (Assembler.isBundlingEnabled() && Assembler.getRelaxAll()) { ------------------ | Branch (560:7): [True: 0, False: 1.34k] | Branch (560:40): [True: 0, False: 0] ------------------ 561| 0| if (!isBundleLocked()) { ------------------ | Branch (561:9): [True: 0, False: 0] ------------------ 562| 0| mergeFragment(getOrCreateDataFragment(), DF); 563| 0| delete DF; 564| 0| } 565| 0| } 566| 1.34k|} _ZN7llvm_ks13MCELFStreamer10FinishImplEv: 634| 185|{ 635| | // Ensure the last section gets aligned if necessary. 636| 185| MCSection *CurSection = getCurrentSectionOnly(); 637| 185| setSectionAlignmentForBundling(getAssembler(), CurSection); 638| | 639| 185| EmitFrames(nullptr); 640| 185| return this->MCObjectStreamer::FinishImpl(); 641| 185|} _ZN7llvm_ks17createELFStreamerERNS_9MCContextERNS_12MCAsmBackendERNS_17raw_pwrite_streamEPNS_13MCCodeEmitterEb: 645| 430| bool RelaxAll) { 646| 430| MCELFStreamer *S = new MCELFStreamer(Context, MAB, OS, CE); 647| 430| if (RelaxAll) ------------------ | Branch (647:7): [True: 0, False: 430] ------------------ 648| 0| S->getAssembler().setRelaxAll(true); 649| 430| return S; 650| 430|} MCELFStreamer.cpp:_ZL30setSectionAlignmentForBundlingRKN7llvm_ks11MCAssemblerEPNS_9MCSectionE: 131| 619| MCSection *Section) { 132| 619| if (Section && Assembler.isBundlingEnabled() && Section->hasInstructions() && ------------------ | Branch (132:7): [True: 189, False: 430] | Branch (132:18): [True: 0, False: 189] | Branch (132:51): [True: 0, False: 0] ------------------ 133| 0| Section->getAlignment() < Assembler.getBundleAlignSize()) ------------------ | Branch (133:7): [True: 0, False: 0] ------------------ 134| 0| Section->setAlignment(Assembler.getBundleAlignSize()); 135| 619|} _ZN7llvm_ks12MCBinaryExpr6createENS0_6OpcodeEPKNS_6MCExprES4_RNS_9MCContextE: 133| 3.13k| const MCExpr *RHS, MCContext &Ctx) { 134| 3.13k| return new (Ctx) MCBinaryExpr(Opc, LHS, RHS); 135| 3.13k|} _ZN7llvm_ks11MCUnaryExpr6createENS0_6OpcodeEPKNS_6MCExprERNS_9MCContextE: 138| 4.65k| MCContext &Ctx) { 139| 4.65k| return new (Ctx) MCUnaryExpr(Opc, Expr); 140| 4.65k|} _ZN7llvm_ks14MCConstantExpr6createElRNS_9MCContextE: 142| 15.7k|const MCConstantExpr *MCConstantExpr::create(int64_t Value, MCContext &Ctx) { 143| 15.7k| return new (Ctx) MCConstantExpr(Value); 144| 15.7k|} _ZN7llvm_ks15MCSymbolRefExprC2EPKNS_8MCSymbolENS0_11VariantKindEPKNS_9MCAsmInfoE: 150| 18.5k| : MCExpr(MCExpr::SymbolRef), Kind(Kind), 151| 18.5k| UseParensForSymbolVariant(MAI->useParensForSymbolVariant()), 152| 18.5k| HasSubsectionsViaSymbols(MAI->hasSubsectionsViaSymbols()), 153| 18.5k| Symbol(Symbol) { 154| | assert(Symbol); ------------------ | Branch (154:3): [True: 18.5k, False: 0] ------------------ 155| 18.5k|} _ZN7llvm_ks15MCSymbolRefExpr6createEPKNS_8MCSymbolENS0_11VariantKindERNS_9MCContextE: 159| 18.5k| MCContext &Ctx) { 160| 18.5k| return new (Ctx) MCSymbolRefExpr(Sym, Kind, Ctx.getAsmInfo()); 161| 18.5k|} _ZN7llvm_ks15MCSymbolRefExpr21getVariantKindForNameENS_9StringRefE: 303| 228|MCSymbolRefExpr::getVariantKindForName(StringRef Name) { 304| 228| return StringSwitch(Name.lower()) 305| 228| .Case("got", VK_GOT) 306| 228| .Case("gotoff", VK_GOTOFF) 307| 228| .Case("gotpcrel", VK_GOTPCREL) 308| 228| .Case("gottpoff", VK_GOTTPOFF) 309| 228| .Case("indntpoff", VK_INDNTPOFF) 310| 228| .Case("ntpoff", VK_NTPOFF) 311| 228| .Case("gotntpoff", VK_GOTNTPOFF) 312| 228| .Case("plt", VK_PLT) 313| 228| .Case("tlsgd", VK_TLSGD) 314| 228| .Case("tlsld", VK_TLSLD) 315| 228| .Case("tlsldm", VK_TLSLDM) 316| 228| .Case("tpoff", VK_TPOFF) 317| 228| .Case("dtpoff", VK_DTPOFF) 318| 228| .Case("tlvp", VK_TLVP) 319| 228| .Case("tlvppage", VK_TLVPPAGE) 320| 228| .Case("tlvppageoff", VK_TLVPPAGEOFF) 321| 228| .Case("page", VK_PAGE) 322| 228| .Case("pageoff", VK_PAGEOFF) 323| 228| .Case("gotpage", VK_GOTPAGE) 324| 228| .Case("gotpageoff", VK_GOTPAGEOFF) 325| 228| .Case("imgrel", VK_COFF_IMGREL32) 326| 228| .Case("secrel32", VK_SECREL) 327| 228| .Case("size", VK_SIZE) 328| 228| .Case("l", VK_PPC_LO) 329| 228| .Case("h", VK_PPC_HI) 330| 228| .Case("ha", VK_PPC_HA) 331| 228| .Case("higher", VK_PPC_HIGHER) 332| 228| .Case("highera", VK_PPC_HIGHERA) 333| 228| .Case("highest", VK_PPC_HIGHEST) 334| 228| .Case("highesta", VK_PPC_HIGHESTA) 335| 228| .Case("got@l", VK_PPC_GOT_LO) 336| 228| .Case("got@h", VK_PPC_GOT_HI) 337| 228| .Case("got@ha", VK_PPC_GOT_HA) 338| 228| .Case("local", VK_PPC_LOCAL) 339| 228| .Case("tocbase", VK_PPC_TOCBASE) 340| 228| .Case("toc", VK_PPC_TOC) 341| 228| .Case("toc@l", VK_PPC_TOC_LO) 342| 228| .Case("toc@h", VK_PPC_TOC_HI) 343| 228| .Case("toc@ha", VK_PPC_TOC_HA) 344| 228| .Case("tls", VK_PPC_TLS) 345| 228| .Case("dtpmod", VK_PPC_DTPMOD) 346| 228| .Case("tprel", VK_PPC_TPREL) 347| 228| .Case("tprel@l", VK_PPC_TPREL_LO) 348| 228| .Case("tprel@h", VK_PPC_TPREL_HI) 349| 228| .Case("tprel@ha", VK_PPC_TPREL_HA) 350| 228| .Case("tprel@higher", VK_PPC_TPREL_HIGHER) 351| 228| .Case("tprel@highera", VK_PPC_TPREL_HIGHERA) 352| 228| .Case("tprel@highest", VK_PPC_TPREL_HIGHEST) 353| 228| .Case("tprel@highesta", VK_PPC_TPREL_HIGHESTA) 354| 228| .Case("dtprel", VK_PPC_DTPREL) 355| 228| .Case("dtprel@l", VK_PPC_DTPREL_LO) 356| 228| .Case("dtprel@h", VK_PPC_DTPREL_HI) 357| 228| .Case("dtprel@ha", VK_PPC_DTPREL_HA) 358| 228| .Case("dtprel@higher", VK_PPC_DTPREL_HIGHER) 359| 228| .Case("dtprel@highera", VK_PPC_DTPREL_HIGHERA) 360| 228| .Case("dtprel@highest", VK_PPC_DTPREL_HIGHEST) 361| 228| .Case("dtprel@highesta", VK_PPC_DTPREL_HIGHESTA) 362| 228| .Case("got@tprel", VK_PPC_GOT_TPREL) 363| 228| .Case("got@tprel@l", VK_PPC_GOT_TPREL_LO) 364| 228| .Case("got@tprel@h", VK_PPC_GOT_TPREL_HI) 365| 228| .Case("got@tprel@ha", VK_PPC_GOT_TPREL_HA) 366| 228| .Case("got@dtprel", VK_PPC_GOT_DTPREL) 367| 228| .Case("got@dtprel@l", VK_PPC_GOT_DTPREL_LO) 368| 228| .Case("got@dtprel@h", VK_PPC_GOT_DTPREL_HI) 369| 228| .Case("got@dtprel@ha", VK_PPC_GOT_DTPREL_HA) 370| 228| .Case("got@tlsgd", VK_PPC_GOT_TLSGD) 371| 228| .Case("got@tlsgd@l", VK_PPC_GOT_TLSGD_LO) 372| 228| .Case("got@tlsgd@h", VK_PPC_GOT_TLSGD_HI) 373| 228| .Case("got@tlsgd@ha", VK_PPC_GOT_TLSGD_HA) 374| 228| .Case("got@tlsld", VK_PPC_GOT_TLSLD) 375| 228| .Case("got@tlsld@l", VK_PPC_GOT_TLSLD_LO) 376| 228| .Case("got@tlsld@h", VK_PPC_GOT_TLSLD_HI) 377| 228| .Case("got@tlsld@ha", VK_PPC_GOT_TLSLD_HA) 378| 228| .Case("gdgot", VK_Hexagon_GD_GOT) 379| 228| .Case("gdplt", VK_Hexagon_GD_PLT) 380| 228| .Case("iegot", VK_Hexagon_IE_GOT) 381| 228| .Case("ie", VK_Hexagon_IE) 382| 228| .Case("ldgot", VK_Hexagon_LD_GOT) 383| 228| .Case("ldplt", VK_Hexagon_LD_PLT) 384| 228| .Case("pcrel", VK_Hexagon_PCREL) 385| 228| .Case("none", VK_ARM_NONE) 386| 228| .Case("got_prel", VK_ARM_GOT_PREL) 387| 228| .Case("target1", VK_ARM_TARGET1) 388| 228| .Case("target2", VK_ARM_TARGET2) 389| 228| .Case("prel31", VK_ARM_PREL31) 390| 228| .Case("sbrel", VK_ARM_SBREL) 391| 228| .Case("tlsldo", VK_ARM_TLSLDO) 392| 228| .Case("tlscall", VK_ARM_TLSCALL) 393| 228| .Case("tlsdesc", VK_ARM_TLSDESC) 394| 228| .Default(VK_Invalid); 395| 228|} _ZNK7llvm_ks6MCExpr18evaluateAsAbsoluteERl: 406| 27.7k|bool MCExpr::evaluateAsAbsolute(int64_t &Res) const { 407| 27.7k| return evaluateAsAbsolute(Res, nullptr, nullptr, nullptr); 408| 27.7k|} _ZNK7llvm_ks6MCExpr18evaluateAsAbsoluteERlRKNS_11MCAssemblerE: 421| 610|bool MCExpr::evaluateAsAbsolute(int64_t &Res, const MCAssembler &Asm) const { 422| 610| return evaluateAsAbsolute(Res, &Asm, nullptr, nullptr); 423| 610|} _ZNK7llvm_ks6MCExpr18evaluateAsAbsoluteERlPKNS_11MCAssemblerEPKNS_11MCAsmLayoutEPKNS_8DenseMapIPKNS_9MCSectionEmNS_12DenseMapInfoISB_EENS_6detail12DenseMapPairISB_mEEEE: 433| 28.3k| const SectionAddrMap *Addrs) const { 434| | // FIXME: The use if InSet = Addrs is a hack. Setting InSet causes us 435| | // absolutize differences across sections and that is what the MachO writer 436| | // uses Addrs for. 437| 28.3k| return evaluateAsAbsolute(Res, Asm, Layout, Addrs, Addrs); 438| 28.3k|} _ZNK7llvm_ks6MCExpr18evaluateAsAbsoluteERlPKNS_11MCAssemblerEPKNS_11MCAsmLayoutEPKNS_8DenseMapIPKNS_9MCSectionEmNS_12DenseMapInfoISB_EENS_6detail12DenseMapPairISB_mEEEEb: 443| 28.3k|{ 444| 28.3k| MCValue Value; 445| | 446| | // Fast path constants. 447| 28.3k| if (const MCConstantExpr *CE = dyn_cast(this)) { ------------------ | Branch (447:29): [True: 8.79k, False: 19.5k] ------------------ 448| 8.79k| Res = CE->getValue(); 449| 8.79k| return true; 450| 8.79k| } 451| | 452| 19.5k| bool valid; 453| 19.5k| bool IsRelocatable = 454| 19.5k| evaluateAsRelocatableImpl(Value, Asm, Layout, nullptr, Addrs, InSet, valid); 455| | 456| | // Record the current value. 457| 19.5k| Res = Value.getConstant(); 458| | 459| 19.5k| return IsRelocatable && Value.isAbsolute(); ------------------ | Branch (459:10): [True: 19.0k, False: 542] | Branch (459:27): [True: 2.18k, False: 16.8k] ------------------ 460| 28.3k|} _ZNK7llvm_ks6MCExpr21evaluateAsRelocatableERNS_7MCValueEPKNS_11MCAsmLayoutEPKNS_7MCFixupE: 606| 1.37k|{ 607| 1.37k| MCAssembler *Assembler = Layout ? &Layout->getAssembler() : nullptr; ------------------ | Branch (607:28): [True: 1.37k, False: 0] ------------------ 608| 1.37k| bool valid; 609| 1.37k| return evaluateAsRelocatableImpl(Res, Assembler, Layout, Fixup, nullptr, 610| 1.37k| false, valid); 611| 1.37k|} _ZNK7llvm_ks6MCExpr15evaluateAsValueERNS_7MCValueERKNS_11MCAsmLayoutE: 614| 243|{ 615| 243| MCAssembler *Assembler = &Layout.getAssembler(); 616| 243| bool valid; 617| 243| return evaluateAsRelocatableImpl(Res, Assembler, &Layout, nullptr, nullptr, 618| 243| true, valid); 619| 243|} _ZNK7llvm_ks6MCExpr25evaluateAsRelocatableImplERNS_7MCValueEPKNS_11MCAssemblerEPKNS_11MCAsmLayoutEPKNS_7MCFixupEPKNS_8DenseMapIPKNS_9MCSectionEmNS_12DenseMapInfoISF_EENS_6detail12DenseMapPairISF_mEEEEbRb: 639| 32.6k|{ 640| 32.6k| switch (getKind()) { ------------------ | Branch (640:11): [True: 32.6k, False: 0] ------------------ 641| 0| case Target: ------------------ | Branch (641:3): [True: 0, False: 32.6k] ------------------ 642| 0| return cast(this)->evaluateAsRelocatableImpl(Res, Layout, 643| 0| Fixup); 644| | 645| 3.66k| case Constant: ------------------ | Branch (645:3): [True: 3.66k, False: 28.9k] ------------------ 646| 3.66k| Res = MCValue::get(cast(this)->getValue()); 647| 3.66k| return true; 648| | 649| 19.1k| case SymbolRef: { ------------------ | Branch (649:3): [True: 19.1k, False: 13.4k] ------------------ 650| 19.1k| const MCSymbolRefExpr *SRE = cast(this); 651| 19.1k| const MCSymbol &Sym = SRE->getSymbol(); 652| | 653| | // Evaluate recursively if this is a variable. 654| 19.1k| if (Sym.isVariable() && SRE->getKind() == MCSymbolRefExpr::VK_None && ------------------ | Branch (654:9): [True: 97, False: 19.0k] | Branch (654:29): [True: 97, False: 0] ------------------ 655| 97| canExpand(Sym, InSet)) { ------------------ | Branch (655:9): [True: 6, False: 91] ------------------ 656| 6| bool IsMachO = SRE->hasSubsectionsViaSymbols(); 657| 6| bool valid; 658| 6| if (Sym.getVariableValue()->evaluateAsRelocatableImpl( ------------------ | Branch (658:11): [True: 6, False: 0] ------------------ 659| 6| Res, Asm, Layout, Fixup, Addrs, InSet || IsMachO, valid)) { ------------------ | Branch (659:47): [True: 0, False: 6] | Branch (659:56): [True: 0, False: 6] ------------------ 660| 6| if (!IsMachO) ------------------ | Branch (660:13): [True: 6, False: 0] ------------------ 661| 6| return true; 662| | 663| 0| const MCSymbolRefExpr *A = Res.getSymA(); 664| 0| const MCSymbolRefExpr *B = Res.getSymB(); 665| | // FIXME: This is small hack. Given 666| | // a = b + 4 667| | // .long a 668| | // the OS X assembler will completely drop the 4. We should probably 669| | // include it in the relocation or produce an error if that is not 670| | // possible. 671| 0| if (!A && !B) ------------------ | Branch (671:13): [True: 0, False: 0] | Branch (671:19): [True: 0, False: 0] ------------------ 672| 0| return true; 673| 0| } 674| 6| } 675| | 676| 19.1k| Res = MCValue::get(SRE, nullptr, 0); 677| 19.1k| return true; 678| 19.1k| } 679| | 680| 6.34k| case Unary: { ------------------ | Branch (680:3): [True: 6.34k, False: 26.2k] ------------------ 681| 6.34k| const MCUnaryExpr *AUE = cast(this); 682| 6.34k| MCValue Value; 683| | 684| 6.34k| bool valid; 685| 6.34k| if (!AUE->getSubExpr()->evaluateAsRelocatableImpl(Value, Asm, Layout, Fixup, ------------------ | Branch (685:9): [True: 3.51k, False: 2.83k] ------------------ 686| 6.34k| Addrs, InSet, valid)) 687| 3.51k| return false; 688| | 689| 2.83k| switch (AUE->getOpcode()) { ------------------ | Branch (689:13): [True: 2.83k, False: 0] ------------------ 690| 702| case MCUnaryExpr::LNot: ------------------ | Branch (690:5): [True: 702, False: 2.12k] ------------------ 691| 702| if (!Value.isAbsolute()) ------------------ | Branch (691:11): [True: 260, False: 442] ------------------ 692| 260| return false; 693| 442| Res = MCValue::get(!Value.getConstant()); 694| 442| break; 695| 1.92k| case MCUnaryExpr::Minus: ------------------ | Branch (695:5): [True: 1.92k, False: 906] ------------------ 696| | /// -(a - b + const) ==> (b - a - const) 697| 1.92k| if (Value.getSymA() && !Value.getSymB()) ------------------ | Branch (697:11): [True: 159, False: 1.76k] | Branch (697:30): [True: 159, False: 0] ------------------ 698| 159| return false; 699| 1.76k| Res = MCValue::get(Value.getSymB(), Value.getSymA(), 700| 1.76k| -Value.getConstant()); 701| 1.76k| break; 702| 10| case MCUnaryExpr::Not: ------------------ | Branch (702:5): [True: 10, False: 2.82k] ------------------ 703| 10| if (!Value.isAbsolute()) ------------------ | Branch (703:11): [True: 0, False: 10] ------------------ 704| 0| return false; 705| 10| Res = MCValue::get(~Value.getConstant()); 706| 10| break; 707| 194| case MCUnaryExpr::Plus: ------------------ | Branch (707:5): [True: 194, False: 2.63k] ------------------ 708| 194| Res = Value; 709| 194| break; 710| 2.83k| } 711| | 712| 2.41k| return true; 713| 2.83k| } 714| | 715| 3.46k| case Binary: { ------------------ | Branch (715:3): [True: 3.46k, False: 29.1k] ------------------ 716| 3.46k| const MCBinaryExpr *ABE = cast(this); 717| 3.46k| MCValue LHSValue, RHSValue; 718| 3.46k| bool valid; 719| | 720| 3.46k| if (!ABE->getLHS()->evaluateAsRelocatableImpl(LHSValue, Asm, Layout, Fixup, ------------------ | Branch (720:9): [True: 1.84k, False: 1.62k] ------------------ 721| 3.46k| Addrs, InSet, valid) || 722| 1.62k| !ABE->getRHS()->evaluateAsRelocatableImpl(RHSValue, Asm, Layout, Fixup, ------------------ | Branch (722:9): [True: 12, False: 1.61k] ------------------ 723| 1.62k| Addrs, InSet, valid)) 724| 1.85k| return false; 725| | 726| | // We only support a few operations on non-constant expressions, handle 727| | // those first. 728| 1.61k| if (!LHSValue.isAbsolute() || !RHSValue.isAbsolute()) { ------------------ | Branch (728:9): [True: 487, False: 1.12k] | Branch (728:35): [True: 225, False: 899] ------------------ 729| 712| switch (ABE->getOpcode()) { 730| 104| default: ------------------ | Branch (730:7): [True: 104, False: 608] ------------------ 731| 104| return false; 732| 470| case MCBinaryExpr::Sub: ------------------ | Branch (732:7): [True: 470, False: 242] ------------------ 733| | // Negate RHS and add. 734| 470| return EvaluateSymbolicAdd(Asm, Layout, Addrs, InSet, LHSValue, 735| 470| RHSValue.getSymB(), RHSValue.getSymA(), 736| 470| -RHSValue.getConstant(), Res, valid); 737| | 738| 138| case MCBinaryExpr::Add: ------------------ | Branch (738:7): [True: 138, False: 574] ------------------ 739| 138| return EvaluateSymbolicAdd(Asm, Layout, Addrs, InSet, LHSValue, 740| 138| RHSValue.getSymA(), RHSValue.getSymB(), 741| 138| RHSValue.getConstant(), Res, valid); 742| 712| } 743| 712| } 744| | 745| | // FIXME: We need target hooks for the evaluation. It may be limited in 746| | // width, and gas defines the result of comparisons differently from 747| | // Apple as. 748| 899| int64_t LHS = LHSValue.getConstant(), RHS = RHSValue.getConstant(); 749| 899| int64_t Result = 0; 750| 899| switch (ABE->getOpcode()) { ------------------ | Branch (750:13): [True: 899, False: 0] ------------------ 751| 0| case MCBinaryExpr::AShr: Result = LHS >> RHS; break; ------------------ | Branch (751:5): [True: 0, False: 899] ------------------ 752| 10| case MCBinaryExpr::Add: Result = LHS + RHS; break; ------------------ | Branch (752:5): [True: 10, False: 889] ------------------ 753| 56| case MCBinaryExpr::And: Result = LHS & RHS; break; ------------------ | Branch (753:5): [True: 56, False: 843] ------------------ 754| 61| case MCBinaryExpr::Div: ------------------ | Branch (754:5): [True: 61, False: 838] ------------------ 755| | // Handle division by zero. gas just emits a warning and keeps going, 756| | // we try to be stricter. 757| | // FIXME: Currently the caller of this function has no way to understand 758| | // we're bailing out because of 'division by zero'. Therefore, it will 759| | // emit a 'expected relocatable expression' error. It would be nice to 760| | // change this code to emit a better diagnostic. 761| 61| if (RHS == 0) ------------------ | Branch (761:11): [True: 0, False: 61] ------------------ 762| 0| return false; 763| 61| Result = LHS / RHS; 764| 61| break; 765| 136| case MCBinaryExpr::EQ: Result = LHS == RHS; break; ------------------ | Branch (765:5): [True: 136, False: 763] ------------------ 766| 128| case MCBinaryExpr::GT: Result = LHS > RHS; break; ------------------ | Branch (766:5): [True: 128, False: 771] ------------------ 767| 0| case MCBinaryExpr::GTE: Result = LHS >= RHS; break; ------------------ | Branch (767:5): [True: 0, False: 899] ------------------ 768| 0| case MCBinaryExpr::LAnd: Result = LHS && RHS; break; ------------------ | Branch (768:5): [True: 0, False: 899] | Branch (768:39): [True: 0, False: 0] | Branch (768:46): [True: 0, False: 0] ------------------ 769| 2| case MCBinaryExpr::LOr: Result = LHS || RHS; break; ------------------ | Branch (769:5): [True: 2, False: 897] | Branch (769:39): [True: 2, False: 0] | Branch (769:46): [True: 0, False: 0] ------------------ 770| 0| case MCBinaryExpr::LShr: Result = uint64_t(LHS) >> uint64_t(RHS); break; ------------------ | Branch (770:5): [True: 0, False: 899] ------------------ 771| 0| case MCBinaryExpr::LT: Result = LHS < RHS; break; ------------------ | Branch (771:5): [True: 0, False: 899] ------------------ 772| 0| case MCBinaryExpr::LTE: Result = LHS <= RHS; break; ------------------ | Branch (772:5): [True: 0, False: 899] ------------------ 773| 17| case MCBinaryExpr::Mod: ------------------ | Branch (773:5): [True: 17, False: 882] ------------------ 774| | // Handle division by zero. gas just emits a warning and keeps going, 775| | // we try to be stricter. 776| | // FIXME: Currently the caller of this function has no way to understand 777| | // we're bailing out because of 'division by zero'. Therefore, it will 778| | // emit a 'expected relocatable expression' error. It would be nice to 779| | // change this code to emit a better diagnostic. 780| 17| if (RHS == 0) ------------------ | Branch (780:11): [True: 1, False: 16] ------------------ 781| 1| return false; 782| 16| Result = LHS % RHS; 783| 16| break; 784| 207| case MCBinaryExpr::Mul: Result = LHS * RHS; break; ------------------ | Branch (784:5): [True: 207, False: 692] ------------------ 785| 0| case MCBinaryExpr::NE: Result = LHS != RHS; break; ------------------ | Branch (785:5): [True: 0, False: 899] ------------------ 786| 0| case MCBinaryExpr::Or: Result = LHS | RHS; break; ------------------ | Branch (786:5): [True: 0, False: 899] ------------------ 787| 0| case MCBinaryExpr::Shl: Result = uint64_t(LHS) << uint64_t(RHS); break; ------------------ | Branch (787:5): [True: 0, False: 899] ------------------ 788| 270| case MCBinaryExpr::Sub: Result = LHS - RHS; break; ------------------ | Branch (788:5): [True: 270, False: 629] ------------------ 789| 12| case MCBinaryExpr::Xor: Result = LHS ^ RHS; break; ------------------ | Branch (789:5): [True: 12, False: 887] ------------------ 790| 899| } 791| | 792| 898| Res = MCValue::get(Result); 793| 898| return true; 794| 899| } 795| 32.6k| } 796| | 797| 0| llvm_unreachable("Invalid assembly expression kind!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 798| 32.6k|} _ZNK7llvm_ks6MCExpr22findAssociatedFragmentEv: 800| 64|MCFragment *MCExpr::findAssociatedFragment() const { 801| 64| switch (getKind()) { ------------------ | Branch (801:11): [True: 64, False: 0] ------------------ 802| 0| case Target: ------------------ | Branch (802:3): [True: 0, False: 64] ------------------ 803| | // We never look through target specific expressions. 804| 0| return cast(this)->findAssociatedFragment(); 805| | 806| 3| case Constant: ------------------ | Branch (806:3): [True: 3, False: 61] ------------------ 807| 3| return MCSymbol::AbsolutePseudoFragment; 808| | 809| 42| case SymbolRef: { ------------------ | Branch (809:3): [True: 42, False: 22] ------------------ 810| 42| const MCSymbolRefExpr *SRE = cast(this); 811| 42| const MCSymbol &Sym = SRE->getSymbol(); 812| 42| return Sym.getFragment(); 813| 0| } 814| | 815| 19| case Unary: ------------------ | Branch (815:3): [True: 19, False: 45] ------------------ 816| 19| return cast(this)->getSubExpr()->findAssociatedFragment(); 817| | 818| 0| case Binary: { ------------------ | Branch (818:3): [True: 0, False: 64] ------------------ 819| 0| const MCBinaryExpr *BE = cast(this); 820| 0| MCFragment *LHS_F = BE->getLHS()->findAssociatedFragment(); 821| 0| MCFragment *RHS_F = BE->getRHS()->findAssociatedFragment(); 822| | 823| | // If either is absolute, return the other. 824| 0| if (LHS_F == MCSymbol::AbsolutePseudoFragment) ------------------ | Branch (824:9): [True: 0, False: 0] ------------------ 825| 0| return RHS_F; 826| 0| if (RHS_F == MCSymbol::AbsolutePseudoFragment) ------------------ | Branch (826:9): [True: 0, False: 0] ------------------ 827| 0| return LHS_F; 828| | 829| | // Not always correct, but probably the best we can do without more context. 830| 0| if (BE->getOpcode() == MCBinaryExpr::Sub) ------------------ | Branch (830:9): [True: 0, False: 0] ------------------ 831| 0| return MCSymbol::AbsolutePseudoFragment; 832| | 833| | // Otherwise, return the first non-null fragment. 834| 0| return LHS_F ? LHS_F : RHS_F; ------------------ | Branch (834:12): [True: 0, False: 0] ------------------ 835| 0| } 836| 64| } 837| | 838| 0| llvm_unreachable("Invalid assembly expression kind!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 839| 64|} MCExpr.cpp:_ZL9canExpandRKN7llvm_ks8MCSymbolEb: 621| 97|static bool canExpand(const MCSymbol &Sym, bool InSet) { 622| 97| const MCExpr *Expr = Sym.getVariableValue(); 623| 97| const auto *Inner = dyn_cast(Expr); 624| 97| if (Inner) { ------------------ | Branch (624:7): [True: 91, False: 6] ------------------ 625| 91| if (Inner->getKind() == MCSymbolRefExpr::VK_WEAKREF) ------------------ | Branch (625:9): [True: 0, False: 91] ------------------ 626| 0| return false; 627| 91| } 628| | 629| 97| if (InSet) ------------------ | Branch (629:7): [True: 0, False: 97] ------------------ 630| 0| return true; 631| 97| return !Sym.isInSection(); 632| 97|} MCExpr.cpp:_ZL19EvaluateSymbolicAddPKN7llvm_ks11MCAssemblerEPKNS_11MCAsmLayoutEPKNS_8DenseMapIPKNS_9MCSectionEmNS_12DenseMapInfoIS9_EENS_6detail12DenseMapPairIS9_mEEEEbRKNS_7MCValueEPKNS_15MCSymbolRefExprESN_lRSI_Rb: 547| 608|{ 548| | // FIXME: This routine (and other evaluation parts) are *incredibly* sloppy 549| | // about dealing with modifiers. This will ultimately bite us, one day. 550| 608| const MCSymbolRefExpr *LHS_A = LHS.getSymA(); 551| 608| const MCSymbolRefExpr *LHS_B = LHS.getSymB(); 552| 608| int64_t LHS_Cst = LHS.getConstant(); 553| | 554| | // Fold the result constant immediately. 555| 608| int64_t Result_Cst = LHS_Cst + RHS_Cst; 556| | 557| 608| assert((!Layout || Asm) && ------------------ | Branch (557:3): [True: 404, False: 204] | Branch (557:3): [True: 204, False: 0] | Branch (557:3): [True: 608, Folded] | Branch (557:3): [True: 608, False: 0] ------------------ 558| 608| "Must have an assembler object if layout is given!"); 559| | 560| | // If we have a layout, we can fold resolved differences. 561| 608| if (Asm) { ------------------ | Branch (561:7): [True: 235, False: 373] ------------------ 562| | // First, fold out any differences which are fully resolved. By 563| | // reassociating terms in 564| | // Result = (LHS_A - LHS_B + LHS_Cst) + (RHS_A - RHS_B + RHS_Cst). 565| | // we have the four possible differences: 566| | // (LHS_A - LHS_B), 567| | // (LHS_A - RHS_B), 568| | // (RHS_A - LHS_B), 569| | // (RHS_A - RHS_B). 570| | // Since we are attempting to be as aggressive as possible about folding, we 571| | // attempt to evaluate each possible alternative. 572| 235| AttemptToFoldSymbolOffsetDifference(Asm, Layout, Addrs, InSet, LHS_A, LHS_B, 573| 235| Result_Cst, valid); 574| 235| if (!valid) ------------------ | Branch (574:9): [True: 0, False: 235] ------------------ 575| 0| return false; 576| 235| AttemptToFoldSymbolOffsetDifference(Asm, Layout, Addrs, InSet, LHS_A, RHS_B, 577| 235| Result_Cst, valid); 578| 235| if (!valid) ------------------ | Branch (578:9): [True: 0, False: 235] ------------------ 579| 0| return false; 580| 235| AttemptToFoldSymbolOffsetDifference(Asm, Layout, Addrs, InSet, RHS_A, LHS_B, 581| 235| Result_Cst, valid); 582| 235| if (!valid) ------------------ | Branch (582:9): [True: 0, False: 235] ------------------ 583| 0| return false; 584| 235| AttemptToFoldSymbolOffsetDifference(Asm, Layout, Addrs, InSet, RHS_A, RHS_B, 585| 235| Result_Cst, valid); 586| 235| if (!valid) ------------------ | Branch (586:9): [True: 0, False: 235] ------------------ 587| 0| return false; 588| 235| } 589| | 590| | // We can't represent the addition or subtraction of two symbols. 591| 608| if ((LHS_A && RHS_A) || (LHS_B && RHS_B)) ------------------ | Branch (591:8): [True: 346, False: 262] | Branch (591:17): [True: 7, False: 339] | Branch (591:28): [True: 61, False: 540] | Branch (591:37): [True: 16, False: 45] ------------------ 592| 23| return false; 593| | 594| | // At this point, we have at most one additive symbol and one subtractive 595| | // symbol -- find them. 596| 585| const MCSymbolRefExpr *A = LHS_A ? LHS_A : RHS_A; ------------------ | Branch (596:30): [True: 333, False: 252] ------------------ 597| 585| const MCSymbolRefExpr *B = LHS_B ? LHS_B : RHS_B; ------------------ | Branch (597:30): [True: 45, False: 540] ------------------ 598| | 599| 585| Res = MCValue::get(A, B, Result_Cst); 600| 585| return true; 601| 608|} MCExpr.cpp:_ZL35AttemptToFoldSymbolOffsetDifferencePKN7llvm_ks11MCAssemblerEPKNS_11MCAsmLayoutEPKNS_8DenseMapIPKNS_9MCSectionEmNS_12DenseMapInfoIS9_EENS_6detail12DenseMapPairIS9_mEEEEbRPKNS_15MCSymbolRefExprESL_RlRb: 466| 940| const MCSymbolRefExpr *&B, int64_t &Addend, bool &valid) { 467| 940| valid = true; 468| 940| if (!A || !B) ------------------ | Branch (468:7): [True: 692, False: 248] | Branch (468:13): [True: 226, False: 22] ------------------ 469| 918| return; 470| | 471| 22| const MCSymbol &SA = A->getSymbol(); 472| 22| const MCSymbol &SB = B->getSymbol(); 473| | 474| 22| if (SA.isUndefined() || SB.isUndefined()) ------------------ | Branch (474:7): [True: 10, False: 12] | Branch (474:27): [True: 8, False: 4] ------------------ 475| 18| return; 476| | 477| 4| if (!Asm->getWriter().isSymbolRefDifferenceFullyResolved(*Asm, A, B, InSet, valid)) ------------------ | Branch (477:7): [True: 0, False: 4] ------------------ 478| 0| return; 479| 4| if (!valid) ------------------ | Branch (479:7): [True: 0, False: 4] ------------------ 480| 0| return; 481| | 482| 4| if (SA.getFragment() == SB.getFragment() && !SA.isVariable() && ------------------ | Branch (482:7): [True: 4, False: 0] | Branch (482:47): [True: 4, False: 0] ------------------ 483| 4| !SB.isVariable()) { ------------------ | Branch (483:7): [True: 4, False: 0] ------------------ 484| 4| Addend += (SA.getOffset() - SB.getOffset()); 485| | 486| | // Pointers to Thumb symbols need to have their low-bit set to allow 487| | // for interworking. 488| 4| if (Asm->isThumbFunc(&SA)) ------------------ | Branch (488:9): [True: 0, False: 4] ------------------ 489| 0| Addend |= 1; 490| | 491| | // Clear the symbol expr pointers to indicate we have folded these 492| | // operands. 493| 4| A = B = nullptr; 494| 4| return; 495| 4| } 496| | 497| 0| if (!Layout) ------------------ | Branch (497:7): [True: 0, False: 0] ------------------ 498| 0| return; 499| | 500| 0| const MCSection &SecA = *SA.getFragment()->getParent(); 501| 0| const MCSection &SecB = *SB.getFragment()->getParent(); 502| | 503| 0| if ((&SecA != &SecB) && !Addrs) ------------------ | Branch (503:7): [True: 0, False: 0] | Branch (503:27): [True: 0, False: 0] ------------------ 504| 0| return; 505| | 506| | // Eagerly evaluate. 507| 0| bool valid1, valid2; 508| 0| Addend += Layout->getSymbolOffset(A->getSymbol(), valid1) - 509| 0| Layout->getSymbolOffset(B->getSymbol(), valid2); 510| 0| if (Addrs && (&SecA != &SecB)) ------------------ | Branch (510:7): [True: 0, False: 0] | Branch (510:16): [True: 0, False: 0] ------------------ 511| 0| Addend += (Addrs->lookup(&SecA) - Addrs->lookup(&SecB)); 512| | 513| | // Pointers to Thumb symbols need to have their low-bit set to allow 514| | // for interworking. 515| 0| if (Asm->isThumbFunc(&SA)) ------------------ | Branch (515:7): [True: 0, False: 0] ------------------ 516| 0| Addend |= 1; 517| | 518| | // Clear the symbol expr pointers to indicate we have folded these 519| | // operands. 520| 0| A = B = nullptr; 521| 0|} _ZN7llvm_ks11MCAsmLayoutC2ERNS_11MCAssemblerE: 32| 185| : Assembler(Asm), LastValidFragment() 33| 185| { 34| | // Compute the section layout order. Virtual sections must go last. 35| 185| for (MCSection &Sec : Asm) ------------------ | Branch (35:23): [True: 187, False: 185] ------------------ 36| 187| if (!Sec.isVirtualSection()) ------------------ | Branch (36:9): [True: 187, False: 0] ------------------ 37| 187| SectionOrder.push_back(&Sec); 38| 185| for (MCSection &Sec : Asm) ------------------ | Branch (38:23): [True: 187, False: 185] ------------------ 39| 187| if (Sec.isVirtualSection()) ------------------ | Branch (39:9): [True: 0, False: 187] ------------------ 40| 0| SectionOrder.push_back(&Sec); 41| 185|} _ZNK7llvm_ks11MCAsmLayout15isFragmentValidEPKNS_10MCFragmentE: 43| 11.7k|bool MCAsmLayout::isFragmentValid(const MCFragment *F) const { 44| 11.7k| const MCSection *Sec = F->getParent(); 45| 11.7k| const MCFragment *LastValid = LastValidFragment.lookup(Sec); 46| 11.7k| if (!LastValid) ------------------ | Branch (46:7): [True: 376, False: 11.3k] ------------------ 47| 376| return false; 48| 11.7k| assert(LastValid->getParent() == Sec); ------------------ | Branch (48:3): [True: 11.3k, False: 0] ------------------ 49| 11.3k| return F->getLayoutOrder() <= LastValid->getLayoutOrder(); 50| 11.3k|} _ZN7llvm_ks11MCAsmLayout23invalidateFragmentsFromEPNS_10MCFragmentE: 52| 1|void MCAsmLayout::invalidateFragmentsFrom(MCFragment *F) { 53| | // If this fragment wasn't already valid, we don't need to do anything. 54| 1| if (!isFragmentValid(F)) ------------------ | Branch (54:7): [True: 0, False: 1] ------------------ 55| 0| return; 56| | 57| | // Otherwise, reset the last valid fragment to the previous fragment 58| | // (if this is the first fragment, it will be NULL). 59| 1| LastValidFragment[F->getParent()] = F->getPrevNode(); 60| 1|} _ZNK7llvm_ks11MCAsmLayout11ensureValidEPKNS_10MCFragmentE: 63| 4.39k|{ 64| 4.39k| MCSection *Sec = F->getParent(); 65| 4.39k| MCSection::iterator I; 66| 4.39k| if (MCFragment *Cur = LastValidFragment[Sec]) ------------------ | Branch (66:19): [True: 4.20k, False: 188] ------------------ 67| 4.20k| I = ++MCSection::iterator(Cur); 68| 188| else 69| 188| I = Sec->begin(); 70| | 71| | // Advance the layout position until the fragment is valid. 72| 6.89k| while (!isFragmentValid(F)) { ------------------ | Branch (72:10): [True: 2.50k, False: 4.39k] ------------------ 73| | //assert(I != Sec->end() && "Layout bookkeeping error"); 74| 2.50k| if (I == Sec->end()) ------------------ | Branch (74:9): [True: 0, False: 2.50k] ------------------ 75| 0| return false; 76| 2.50k| if (const_cast(this)->layoutFragment(&*I)) ------------------ | Branch (76:9): [True: 1, False: 2.50k] ------------------ 77| 1| return false; 78| 2.50k| ++I; 79| 2.50k| } 80| | 81| 4.39k| return true; 82| 4.39k|} _ZNK7llvm_ks11MCAsmLayout17getFragmentOffsetEPKNS_10MCFragmentERb: 85| 4.39k|{ 86| 4.39k| valid = true; 87| 4.39k| if (!ensureValid(F)) { ------------------ | Branch (87:7): [True: 1, False: 4.39k] ------------------ 88| 1| valid = false; 89| 1| return 0; 90| 1| } 91| | //assert(F->Offset != ~UINT64_C(0) && "Address not set!"); 92| 4.39k| if (F->Offset == ~UINT64_C(0)) { ------------------ | Branch (92:7): [True: 0, False: 4.39k] ------------------ 93| 0| valid = false; 94| 0| return 0; 95| 0| } 96| | 97| 4.39k| return F->Offset; 98| 4.39k|} _ZNK7llvm_ks11MCAsmLayout15getSymbolOffsetERKNS_8MCSymbolERmRb: 156| 82|{ 157| 82| return getSymbolOffsetImpl(*this, S, false, Val, valid); 158| 82|} _ZNK7llvm_ks11MCAsmLayout15getSymbolOffsetERKNS_8MCSymbolERb: 161| 1.25k|{ 162| 1.25k| uint64_t Val; 163| 1.25k| getSymbolOffsetImpl(*this, S, true, Val, valid); 164| 1.25k| return Val; 165| 1.25k|} _ZN7llvm_ks17ilist_node_traitsINS_10MCFragmentEE10deleteNodeEPS1_: 264| 2.82k|void ilist_node_traits::deleteNode(MCFragment *V) { 265| 2.82k| V->destroy(); 266| 2.82k|} _ZN7llvm_ks10MCFragmentC2Ev: 268| 434|MCFragment::MCFragment() : Kind(FragmentType(~0)), HasInstructions(false), 269| 434| AlignToBundleEnd(false), BundlePadding(0) { 270| 434|} _ZN7llvm_ks10MCFragmentD2Ev: 272| 21.9k|MCFragment::~MCFragment() { } _ZN7llvm_ks10MCFragmentC2ENS0_12FragmentTypeEbhPNS_9MCSectionE: 276| 21.5k| : Kind(Kind), HasInstructions(HasInstructions), AlignToBundleEnd(false), 277| 21.5k| BundlePadding(BundlePadding), Parent(Parent), Atom(nullptr), 278| 21.5k| Offset(~UINT64_C(0)) { 279| 21.5k| if (Parent && !isDummy()) ------------------ | Branch (279:7): [True: 18.6k, False: 2.82k] | Branch (279:17): [True: 0, False: 18.6k] ------------------ 280| 0| Parent->getFragmentList().push_back(this); 281| 21.5k|} _ZN7llvm_ks10MCFragment7destroyEv: 283| 2.82k|void MCFragment::destroy() { 284| | // First check if we are the sentinal. 285| 2.82k| if (Kind == FragmentType(~0)) { ------------------ | Branch (285:7): [True: 0, False: 2.82k] ------------------ 286| 0| delete this; 287| 0| return; 288| 0| } 289| | 290| 2.82k| switch (Kind) { ------------------ | Branch (290:11): [True: 2.82k, False: 0] ------------------ 291| 732| case FT_Align: ------------------ | Branch (291:5): [True: 732, False: 2.09k] ------------------ 292| 732| delete cast(this); 293| 732| return; 294| 779| case FT_Data: ------------------ | Branch (294:5): [True: 779, False: 2.04k] ------------------ 295| 779| delete cast(this); 296| 779| return; 297| 0| case FT_CompactEncodedInst: ------------------ | Branch (297:5): [True: 0, False: 2.82k] ------------------ 298| 0| delete cast(this); 299| 0| return; 300| 292| case FT_Fill: ------------------ | Branch (300:5): [True: 292, False: 2.53k] ------------------ 301| 292| delete cast(this); 302| 292| return; 303| 850| case FT_Relaxable: ------------------ | Branch (303:5): [True: 850, False: 1.97k] ------------------ 304| 850| delete cast(this); 305| 850| return; 306| 174| case FT_Org: ------------------ | Branch (306:5): [True: 174, False: 2.65k] ------------------ 307| 174| delete cast(this); 308| 174| return; 309| 0| case FT_Dwarf: ------------------ | Branch (309:5): [True: 0, False: 2.82k] ------------------ 310| 0| delete cast(this); 311| 0| return; 312| 0| case FT_DwarfFrame: ------------------ | Branch (312:5): [True: 0, False: 2.82k] ------------------ 313| 0| delete cast(this); 314| 0| return; 315| 0| case FT_LEB: ------------------ | Branch (315:5): [True: 0, False: 2.82k] ------------------ 316| 0| delete cast(this); 317| 0| return; 318| 0| case FT_SafeSEH: ------------------ | Branch (318:5): [True: 0, False: 2.82k] ------------------ 319| 0| delete cast(this); 320| 0| return; 321| 0| case FT_Dummy: ------------------ | Branch (321:5): [True: 0, False: 2.82k] ------------------ 322| 0| delete cast(this); 323| 0| return; 324| 2.82k| } 325| 2.82k|} MCFragment.cpp:_ZL19getSymbolOffsetImplRKN7llvm_ks11MCAsmLayoutERKNS_8MCSymbolEbRmRb: 119| 1.33k|{ 120| 1.33k| valid = true; 121| 1.33k| if (!S.isVariable()) ------------------ | Branch (121:7): [True: 1.28k, False: 51] ------------------ 122| 1.28k| return getLabelOffset(Layout, S, ReportError, Val); 123| | 124| | // If SD is a variable, evaluate it. 125| 51| MCValue Target; 126| 51| if (!S.getVariableValue()->evaluateAsValue(Target, Layout)) { ------------------ | Branch (126:7): [True: 0, False: 51] ------------------ 127| | //report_fatal_error("unable to evaluate offset for variable '" + 128| | // S.getName() + "'"); 129| 0| valid = false; 130| 0| return false; 131| 0| } 132| | 133| 51| uint64_t Offset = Target.getConstant(); 134| | 135| 51| const MCSymbolRefExpr *A = Target.getSymA(); 136| 51| if (A) { ------------------ | Branch (136:7): [True: 51, False: 0] ------------------ 137| 51| uint64_t ValA; 138| 51| if (!getLabelOffset(Layout, A->getSymbol(), ReportError, ValA)) ------------------ | Branch (138:9): [True: 0, False: 51] ------------------ 139| 0| return false; 140| 51| Offset += ValA; 141| 51| } 142| | 143| 51| const MCSymbolRefExpr *B = Target.getSymB(); 144| 51| if (B) { ------------------ | Branch (144:7): [True: 0, False: 51] ------------------ 145| 0| uint64_t ValB; 146| 0| if (!getLabelOffset(Layout, B->getSymbol(), ReportError, ValB)) ------------------ | Branch (146:9): [True: 0, False: 0] ------------------ 147| 0| return false; 148| 0| Offset -= ValB; 149| 0| } 150| | 151| 51| Val = Offset; 152| 51| return true; 153| 51|} MCFragment.cpp:_ZL14getLabelOffsetRKN7llvm_ks11MCAsmLayoutERKNS_8MCSymbolEbRm: 103| 1.33k|{ 104| 1.33k| if (!S.getFragment()) { ------------------ | Branch (104:7): [True: 0, False: 1.33k] ------------------ 105| 0| if (ReportError) ------------------ | Branch (105:9): [True: 0, False: 0] ------------------ 106| 0| report_fatal_error("unable to evaluate offset to undefined symbol '" + 107| 0| S.getName() + "'"); 108| 0| return false; 109| 0| } 110| | 111| 1.33k| bool valid; 112| 1.33k| Val = Layout.getFragmentOffset(S.getFragment(), valid) + S.getOffset(); 113| | 114| 1.33k| return valid; 115| 1.33k|} _ZNK7llvm_ks11MCInstrDesc17getDeprecatedInfoERNS_6MCInstERKNS_15MCSubtargetInfoERNSt3__112basic_stringIcNS6_11char_traitsIcEENS6_9allocatorIcEEEE: 23| 2.26k| std::string &Info) const { 24| 2.26k| if (ComplexDeprecationInfo) ------------------ | Branch (24:7): [True: 66, False: 2.19k] ------------------ 25| 66| return ComplexDeprecationInfo(MI, STI, Info); 26| 2.19k| if (DeprecatedFeature != -1 && STI.getFeatureBits()[DeprecatedFeature]) { ------------------ | Branch (26:7): [True: 0, False: 2.19k] | Branch (26:7): [True: 0, False: 2.19k] | Branch (26:34): [True: 0, False: 0] ------------------ 27| | // FIXME: it would be nice to include the subtarget feature here. 28| 0| Info = "deprecated"; 29| 0| return true; 30| 0| } 31| 2.19k| return false; 32| 2.19k|} _ZN7llvm_ks16MCObjectFileInfo23initELFMCObjectFileInfoENS_6TripleE: 267| 430|void MCObjectFileInfo::initELFMCObjectFileInfo(Triple T) { 268| 430| switch (T.getArch()) { 269| 0| case Triple::mips: ------------------ | Branch (269:3): [True: 0, False: 430] ------------------ 270| 0| case Triple::mipsel: ------------------ | Branch (270:3): [True: 0, False: 430] ------------------ 271| 0| FDECFIEncoding = dwarf::DW_EH_PE_sdata4; 272| 0| break; 273| 0| case Triple::mips64: ------------------ | Branch (273:3): [True: 0, False: 430] ------------------ 274| 0| case Triple::mips64el: ------------------ | Branch (274:3): [True: 0, False: 430] ------------------ 275| 0| FDECFIEncoding = dwarf::DW_EH_PE_sdata8; 276| 0| break; 277| 0| case Triple::x86_64: ------------------ | Branch (277:3): [True: 0, False: 430] ------------------ 278| 0| break; 279| 430| default: ------------------ | Branch (279:3): [True: 430, False: 0] ------------------ 280| 430| FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; 281| 430| break; 282| 430| } 283| | 284| 430| switch (T.getArch()) { 285| 0| case Triple::arm: ------------------ | Branch (285:3): [True: 0, False: 430] ------------------ 286| 0| case Triple::armeb: ------------------ | Branch (286:3): [True: 0, False: 430] ------------------ 287| 0| case Triple::thumb: ------------------ | Branch (287:3): [True: 0, False: 430] ------------------ 288| 430| case Triple::thumbeb: ------------------ | Branch (288:3): [True: 430, False: 0] ------------------ 289| 430| if (Ctx->getAsmInfo()->getExceptionHandlingType() == ExceptionHandling::ARM) ------------------ | Branch (289:9): [True: 430, False: 0] ------------------ 290| 430| break; 291| | // Fallthrough if not using EHABI 292| 0| case Triple::ppc: ------------------ | Branch (292:3): [True: 0, False: 430] ------------------ 293| 0| case Triple::x86: ------------------ | Branch (293:3): [True: 0, False: 430] ------------------ 294| 0| break; 295| 0| case Triple::x86_64: ------------------ | Branch (295:3): [True: 0, False: 430] ------------------ 296| 0| break; 297| 0| case Triple::aarch64: ------------------ | Branch (297:3): [True: 0, False: 430] ------------------ 298| 0| case Triple::aarch64_be: ------------------ | Branch (298:3): [True: 0, False: 430] ------------------ 299| | // The small model guarantees static code/data size < 4GB, but not where it 300| | // will be in memory. Most of these could end up >2GB away so even a signed 301| | // pc-relative 32-bit address is insufficient, theoretically. 302| 0| break; 303| 0| case Triple::mips: ------------------ | Branch (303:3): [True: 0, False: 430] ------------------ 304| 0| case Triple::mipsel: ------------------ | Branch (304:3): [True: 0, False: 430] ------------------ 305| 0| case Triple::mips64: ------------------ | Branch (305:3): [True: 0, False: 430] ------------------ 306| 0| case Triple::mips64el: ------------------ | Branch (306:3): [True: 0, False: 430] ------------------ 307| | // MIPS uses indirect pointer to refer personality functions and types, so 308| | // that the eh_frame section can be read-only. DW.ref.personality will be 309| | // generated for relocation. 310| 0| PersonalityEncoding = dwarf::DW_EH_PE_indirect; 311| | // FIXME: The N64 ABI probably ought to use DW_EH_PE_sdata8 but we can't 312| | // identify N64 from just a triple. 313| 0| TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | 314| 0| dwarf::DW_EH_PE_sdata4; 315| | // We don't support PC-relative LSDA references in GAS so we use the default 316| | // DW_EH_PE_absptr for those. 317| 0| break; 318| 0| case Triple::ppc64: ------------------ | Branch (318:3): [True: 0, False: 430] ------------------ 319| 0| case Triple::ppc64le: ------------------ | Branch (319:3): [True: 0, False: 430] ------------------ 320| 0| PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | 321| 0| dwarf::DW_EH_PE_udata8; 322| 0| LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8; 323| 0| TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | 324| 0| dwarf::DW_EH_PE_udata8; 325| 0| break; 326| 0| case Triple::sparcel: ------------------ | Branch (326:3): [True: 0, False: 430] ------------------ 327| 0| case Triple::sparc: ------------------ | Branch (327:3): [True: 0, False: 430] ------------------ 328| 0| break; 329| 0| case Triple::sparcv9: ------------------ | Branch (329:3): [True: 0, False: 430] ------------------ 330| 0| LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; 331| 0| break; 332| 0| case Triple::systemz: ------------------ | Branch (332:3): [True: 0, False: 430] ------------------ 333| | // All currently-defined code models guarantee that 4-byte PC-relative 334| | // values will be in range. 335| 0| break; 336| 0| default: ------------------ | Branch (336:3): [True: 0, False: 430] ------------------ 337| 0| break; 338| 430| } 339| | 340| 430| unsigned EHSectionType = T.getArch() == Triple::x86_64 ------------------ | Branch (340:28): [True: 0, False: 430] ------------------ 341| 430| ? ELF::SHT_X86_64_UNWIND 342| 430| : ELF::SHT_PROGBITS; 343| | 344| | // Solaris requires different flags for .eh_frame to seemingly every other 345| | // platform. 346| 430| unsigned EHSectionFlags = ELF::SHF_ALLOC; 347| 430| if (T.isOSSolaris() && T.getArch() != Triple::x86_64) ------------------ | Branch (347:7): [True: 0, False: 430] | Branch (347:26): [True: 0, False: 0] ------------------ 348| 0| EHSectionFlags |= ELF::SHF_WRITE; 349| | 350| | // ELF 351| 430| BSSSection = Ctx->getELFSection(".bss", ELF::SHT_NOBITS, 352| 430| ELF::SHF_WRITE | ELF::SHF_ALLOC); 353| | 354| 430| TextSection = Ctx->getELFSection(".text", ELF::SHT_PROGBITS, 355| 430| ELF::SHF_EXECINSTR | ELF::SHF_ALLOC); 356| | 357| 430| DataSection = Ctx->getELFSection(".data", ELF::SHT_PROGBITS, 358| 430| ELF::SHF_WRITE | ELF::SHF_ALLOC); 359| | 360| 430| ReadOnlySection = 361| 430| Ctx->getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); 362| | 363| 430| TLSDataSection = 364| 430| Ctx->getELFSection(".tdata", ELF::SHT_PROGBITS, 365| 430| ELF::SHF_ALLOC | ELF::SHF_TLS | ELF::SHF_WRITE); 366| | 367| 430| TLSBSSSection = Ctx->getELFSection( 368| 430| ".tbss", ELF::SHT_NOBITS, ELF::SHF_ALLOC | ELF::SHF_TLS | ELF::SHF_WRITE); 369| | 370| 430| DataRelROSection = Ctx->getELFSection(".data.rel.ro", ELF::SHT_PROGBITS, 371| 430| ELF::SHF_ALLOC | ELF::SHF_WRITE); 372| | 373| 430| MergeableConst4Section = 374| 430| Ctx->getELFSection(".rodata.cst4", ELF::SHT_PROGBITS, 375| 430| ELF::SHF_ALLOC | ELF::SHF_MERGE, 4, ""); 376| | 377| 430| MergeableConst8Section = 378| 430| Ctx->getELFSection(".rodata.cst8", ELF::SHT_PROGBITS, 379| 430| ELF::SHF_ALLOC | ELF::SHF_MERGE, 8, ""); 380| | 381| 430| MergeableConst16Section = 382| 430| Ctx->getELFSection(".rodata.cst16", ELF::SHT_PROGBITS, 383| 430| ELF::SHF_ALLOC | ELF::SHF_MERGE, 16, ""); 384| | 385| 430| StaticCtorSection = Ctx->getELFSection(".ctors", ELF::SHT_PROGBITS, 386| 430| ELF::SHF_ALLOC | ELF::SHF_WRITE); 387| | 388| 430| StaticDtorSection = Ctx->getELFSection(".dtors", ELF::SHT_PROGBITS, 389| 430| ELF::SHF_ALLOC | ELF::SHF_WRITE); 390| | 391| | // Exception Handling Sections. 392| | 393| | // FIXME: We're emitting LSDA info into a readonly section on ELF, even though 394| | // it contains relocatable pointers. In PIC mode, this is probably a big 395| | // runtime hit for C++ apps. Either the contents of the LSDA need to be 396| | // adjusted or this should be a data section. 397| 430| LSDASection = Ctx->getELFSection(".gcc_except_table", ELF::SHT_PROGBITS, 398| 430| ELF::SHF_ALLOC); 399| | 400| 430| COFFDebugSymbolsSection = nullptr; 401| 430| COFFDebugTypesSection = nullptr; 402| | 403| | // Debug Info Sections. 404| 430| DwarfAbbrevSection = Ctx->getELFSection(".debug_abbrev", ELF::SHT_PROGBITS, 0, 405| 430| "section_abbrev"); 406| 430| DwarfInfoSection = 407| 430| Ctx->getELFSection(".debug_info", ELF::SHT_PROGBITS, 0, "section_info"); 408| 430| DwarfLineSection = Ctx->getELFSection(".debug_line", ELF::SHT_PROGBITS, 0); 409| 430| DwarfFrameSection = Ctx->getELFSection(".debug_frame", ELF::SHT_PROGBITS, 0); 410| 430| DwarfPubNamesSection = 411| 430| Ctx->getELFSection(".debug_pubnames", ELF::SHT_PROGBITS, 0); 412| 430| DwarfPubTypesSection = 413| 430| Ctx->getELFSection(".debug_pubtypes", ELF::SHT_PROGBITS, 0); 414| 430| DwarfGnuPubNamesSection = 415| 430| Ctx->getELFSection(".debug_gnu_pubnames", ELF::SHT_PROGBITS, 0); 416| 430| DwarfGnuPubTypesSection = 417| 430| Ctx->getELFSection(".debug_gnu_pubtypes", ELF::SHT_PROGBITS, 0); 418| 430| DwarfStrSection = 419| 430| Ctx->getELFSection(".debug_str", ELF::SHT_PROGBITS, 420| 430| ELF::SHF_MERGE | ELF::SHF_STRINGS, 1, ""); 421| 430| DwarfLocSection = Ctx->getELFSection(".debug_loc", ELF::SHT_PROGBITS, 0); 422| 430| DwarfARangesSection = 423| 430| Ctx->getELFSection(".debug_aranges", ELF::SHT_PROGBITS, 0); 424| 430| DwarfRangesSection = 425| 430| Ctx->getELFSection(".debug_ranges", ELF::SHT_PROGBITS, 0, "debug_range"); 426| 430| DwarfMacinfoSection = Ctx->getELFSection(".debug_macinfo", ELF::SHT_PROGBITS, 427| 430| 0, "debug_macinfo"); 428| | 429| | // DWARF5 Experimental Debug Info 430| | 431| | // Accelerator Tables 432| 430| DwarfAccelNamesSection = 433| 430| Ctx->getELFSection(".apple_names", ELF::SHT_PROGBITS, 0, "names_begin"); 434| 430| DwarfAccelObjCSection = 435| 430| Ctx->getELFSection(".apple_objc", ELF::SHT_PROGBITS, 0, "objc_begin"); 436| 430| DwarfAccelNamespaceSection = Ctx->getELFSection( 437| 430| ".apple_namespaces", ELF::SHT_PROGBITS, 0, "namespac_begin"); 438| 430| DwarfAccelTypesSection = 439| 430| Ctx->getELFSection(".apple_types", ELF::SHT_PROGBITS, 0, "types_begin"); 440| | 441| | // Fission Sections 442| 430| DwarfInfoDWOSection = 443| 430| Ctx->getELFSection(".debug_info.dwo", ELF::SHT_PROGBITS, 0); 444| 430| DwarfTypesDWOSection = 445| 430| Ctx->getELFSection(".debug_types.dwo", ELF::SHT_PROGBITS, 0); 446| 430| DwarfAbbrevDWOSection = 447| 430| Ctx->getELFSection(".debug_abbrev.dwo", ELF::SHT_PROGBITS, 0); 448| 430| DwarfStrDWOSection = 449| 430| Ctx->getELFSection(".debug_str.dwo", ELF::SHT_PROGBITS, 450| 430| ELF::SHF_MERGE | ELF::SHF_STRINGS, 1, ""); 451| 430| DwarfLineDWOSection = 452| 430| Ctx->getELFSection(".debug_line.dwo", ELF::SHT_PROGBITS, 0); 453| 430| DwarfLocDWOSection = 454| 430| Ctx->getELFSection(".debug_loc.dwo", ELF::SHT_PROGBITS, 0, "skel_loc"); 455| 430| DwarfStrOffDWOSection = 456| 430| Ctx->getELFSection(".debug_str_offsets.dwo", ELF::SHT_PROGBITS, 0); 457| 430| DwarfAddrSection = 458| 430| Ctx->getELFSection(".debug_addr", ELF::SHT_PROGBITS, 0, "addr_sec"); 459| | 460| | // DWP Sections 461| 430| DwarfCUIndexSection = 462| 430| Ctx->getELFSection(".debug_cu_index", ELF::SHT_PROGBITS, 0); 463| 430| DwarfTUIndexSection = 464| 430| Ctx->getELFSection(".debug_tu_index", ELF::SHT_PROGBITS, 0); 465| | 466| 430| StackMapSection = 467| 430| Ctx->getELFSection(".llvm_stackmaps", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); 468| | 469| 430| FaultMapSection = 470| 430| Ctx->getELFSection(".llvm_faultmaps", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); 471| | 472| 430| EHFrameSection = 473| 430| Ctx->getELFSection(".eh_frame", EHSectionType, EHSectionFlags); 474| 430|} _ZN7llvm_ks16MCObjectFileInfo20InitMCObjectFileInfoERKNS_6TripleERNS_9MCContextE: 715| 430| MCContext &ctx) { 716| 430| Ctx = &ctx; 717| | 718| | // Common. 719| 430| CommDirectiveSupportsAlignment = true; 720| 430| SupportsWeakOmittedEHFrame = true; 721| 430| SupportsCompactUnwindWithoutEHFrame = false; 722| 430| OmitDwarfIfHaveCompactUnwind = false; 723| | 724| 430| PersonalityEncoding = LSDAEncoding = FDECFIEncoding = TTypeEncoding = 725| 430| dwarf::DW_EH_PE_absptr; 726| | 727| 430| CompactUnwindDwarfEHFrameOnly = 0; 728| | 729| 430| EHFrameSection = nullptr; // Created on demand. 730| 430| CompactUnwindSection = nullptr; // Used only by selected targets. 731| 430| DwarfAccelNamesSection = nullptr; // Used only by selected targets. 732| 430| DwarfAccelObjCSection = nullptr; // Used only by selected targets. 733| 430| DwarfAccelNamespaceSection = nullptr; // Used only by selected targets. 734| 430| DwarfAccelTypesSection = nullptr; // Used only by selected targets. 735| | 736| 430| TT = TheTriple; 737| | 738| 430| switch (TT.getObjectFormat()) { ------------------ | Branch (738:11): [True: 430, False: 0] ------------------ 739| 0| case Triple::MachO: ------------------ | Branch (739:3): [True: 0, False: 430] ------------------ 740| 0| Env = IsMachO; 741| 0| initMachOMCObjectFileInfo(TT); 742| 0| break; 743| 0| case Triple::COFF: ------------------ | Branch (743:3): [True: 0, False: 430] ------------------ 744| 0| if (!TT.isOSWindows()) ------------------ | Branch (744:9): [True: 0, False: 0] ------------------ 745| 0| report_fatal_error( 746| 0| "Cannot initialize MC for non-Windows COFF object files."); 747| | 748| 0| Env = IsCOFF; 749| 0| initCOFFMCObjectFileInfo(TT); 750| 0| break; 751| 430| case Triple::ELF: ------------------ | Branch (751:3): [True: 430, False: 0] ------------------ 752| 430| Env = IsELF; 753| 430| initELFMCObjectFileInfo(TT); 754| 430| break; 755| 0| case Triple::UnknownObjectFormat: ------------------ | Branch (755:3): [True: 0, False: 430] ------------------ 756| 0| report_fatal_error("Cannot initialize MC for unknown object file format."); 757| 0| break; 758| 430| } 759| 430|} _ZN7llvm_ks16MCObjectStreamerC2ERNS_9MCContextERNS_12MCAsmBackendERNS_17raw_pwrite_streamEPNS_13MCCodeEmitterE: 32| 430| : MCStreamer(Context), 33| 430| Assembler(new MCAssembler(Context, TAB, *Emitter_, 34| 430| *TAB.createObjectWriter(OS))), 35| 430| EmitEHFrame(true), EmitDebugFrame(false) {} _ZN7llvm_ks16MCObjectStreamerD2Ev: 37| 430|MCObjectStreamer::~MCObjectStreamer() { 38| 430| delete &Assembler->getWriter(); 39| 430| delete Assembler; 40| 430|} _ZN7llvm_ks16MCObjectStreamer18flushPendingLabelsEPNS_10MCFragmentEm: 42| 8.81k|void MCObjectStreamer::flushPendingLabels(MCFragment *F, uint64_t FOffset) { 43| 8.81k| if (PendingLabels.empty()) ------------------ | Branch (43:7): [True: 7.96k, False: 852] ------------------ 44| 7.96k| return; 45| 852| if (!F) { ------------------ | Branch (45:7): [True: 130, False: 722] ------------------ 46| 130| F = new MCDataFragment(); 47| 130| MCSection *CurSection = getCurrentSectionOnly(); 48| 130| CurSection->getFragmentList().insert(CurInsertionPoint, F); 49| 130| F->setParent(CurSection); 50| 130| } 51| 974| for (MCSymbol *Sym : PendingLabels) { ------------------ | Branch (51:22): [True: 974, False: 852] ------------------ 52| 974| Sym->setFragment(F); 53| 974| Sym->setOffset(FOffset); 54| 974| } 55| 852| PendingLabels.clear(); 56| 852|} _ZN7llvm_ks16MCObjectStreamer10EmitFramesEPNS_12MCAsmBackendE: 83| 185|void MCObjectStreamer::EmitFrames(MCAsmBackend *MAB) { 84| |#if 0 85| | if (!getNumFrameInfos()) 86| | return; 87| | 88| | if (EmitEHFrame) 89| | MCDwarfFrameEmitter::Emit(*this, MAB, true); 90| | 91| | if (EmitDebugFrame) 92| | MCDwarfFrameEmitter::Emit(*this, MAB, false); 93| |#endif 94| 185|} _ZNK7llvm_ks16MCObjectStreamer18getCurrentFragmentEv: 96| 34.3k|MCFragment *MCObjectStreamer::getCurrentFragment() const { 97| 34.3k| assert(getCurrentSectionOnly() && "No current section!"); ------------------ | Branch (97:3): [True: 34.3k, False: 0] | Branch (97:3): [True: 34.3k, Folded] | Branch (97:3): [True: 34.3k, False: 0] ------------------ 98| | 99| 34.3k| if (CurInsertionPoint != getCurrentSectionOnly()->getFragmentList().begin()) ------------------ | Branch (99:7): [True: 11.1k, False: 23.1k] ------------------ 100| 11.1k| return &*std::prev(CurInsertionPoint); 101| | 102| 23.1k| return nullptr; 103| 34.3k|} _ZN7llvm_ks16MCObjectStreamer23getOrCreateDataFragmentEv: 105| 6.84k|MCDataFragment *MCObjectStreamer::getOrCreateDataFragment() { 106| 6.84k| MCDataFragment *F = dyn_cast_or_null(getCurrentFragment()); 107| | // When bundling is enabled, we don't want to add data to a fragment that 108| | // already has instructions (see MCELFStreamer::EmitInstToData for details) 109| 6.84k| if (!F || (Assembler->isBundlingEnabled() && !Assembler->getRelaxAll() && ------------------ | Branch (109:7): [True: 649, False: 6.19k] | Branch (109:14): [True: 0, False: 6.19k] | Branch (109:48): [True: 0, False: 0] ------------------ 110| 649| F->hasInstructions())) { ------------------ | Branch (110:14): [True: 0, False: 0] ------------------ 111| 649| F = new MCDataFragment(); 112| 649| insert(F); 113| 649| } 114| 6.84k| return F; 115| 6.84k|} _ZN7llvm_ks16MCObjectStreamer15visitUsedSymbolERKNS_8MCSymbolE: 117| 1.49k|void MCObjectStreamer::visitUsedSymbol(const MCSymbol &Sym) { 118| 1.49k| Assembler->registerSymbol(Sym); 119| 1.49k|} _ZN7llvm_ks16MCObjectStreamer13EmitValueImplEPKNS_6MCExprEjNS_5SMLocE: 129| 610|{ 130| 610| MCStreamer::EmitValueImpl(Value, Size, Loc); 131| 610| MCDataFragment *DF = getOrCreateDataFragment(); 132| 610| flushPendingLabels(DF, DF->getContents().size()); 133| | 134| | // This makes the symbol's name (label) end up literally in the output stream 135| | //if (Value->getKind() == MCExpr::SymbolRef) { 136| | // // Keystone: record data in the same section 137| | // const MCSymbolRefExpr &SRE = cast(*Value); 138| | // const StringRef Sym = SRE.getSymbol().getName(); 139| | // DF->getContents().append(Sym.begin(), Sym.end()); 140| | // 141| | // return; 142| | //} 143| | 144| | //MCCVLineEntry::Make(this); 145| | //MCDwarfLineEntry::Make(this, getCurrentSection().first); 146| | 147| | // Avoid fixups when possible. 148| 610| int64_t AbsValue; 149| 610| bool Error; 150| 610| if (Value->evaluateAsAbsolute(AbsValue, getAssembler())) { ------------------ | Branch (150:7): [True: 430, False: 180] ------------------ 151| | // TODO: hande Error? 152| 430| EmitIntValue(AbsValue, Size, Error); 153| 430| return; 154| 430| } 155| 180| DF->getFixups().push_back( 156| 180| MCFixup::create(DF->getContents().size(), Value, 157| 180| MCFixup::getKindForSize(Size, false), Loc)); 158| 180| DF->getContents().resize(DF->getContents().size() + Size, 0); 159| 180|} _ZN7llvm_ks16MCObjectStreamer9EmitLabelEPNS_8MCSymbolE: 172| 5.85k|void MCObjectStreamer::EmitLabel(MCSymbol *Symbol) { 173| 5.85k| MCStreamer::EmitLabel(Symbol); 174| | 175| 5.85k| getAssembler().registerSymbol(*Symbol); 176| | 177| | // If there is a current fragment, mark the symbol as pointing into it. 178| | // Otherwise queue the label and set its fragment pointer when we emit the 179| | // next fragment. 180| 5.85k| auto *F = dyn_cast_or_null(getCurrentFragment()); 181| 5.85k| if (F && !(getAssembler().isBundlingEnabled() && ------------------ | Branch (181:7): [True: 17, False: 5.83k] | Branch (181:14): [True: 0, False: 17] ------------------ 182| 17| getAssembler().getRelaxAll())) { ------------------ | Branch (182:14): [True: 0, False: 0] ------------------ 183| 17| Symbol->setFragment(F); 184| 17| Symbol->setOffset(F->getContents().size()); 185| 5.83k| } else { 186| 5.83k| PendingLabels.push_back(Symbol); 187| 5.83k| } 188| 5.85k|} _ZN7llvm_ks16MCObjectStreamer13ChangeSectionEPNS_9MCSectionEPKNS_6MCExprE: 214| 434| const MCExpr *Subsection) { 215| 434| changeSectionImpl(Section, Subsection); 216| 434|} _ZN7llvm_ks16MCObjectStreamer17changeSectionImplEPNS_9MCSectionEPKNS_6MCExprE: 219| 434| const MCExpr *Subsection) { 220| 434| assert(Section && "Cannot switch to a null section!"); ------------------ | Branch (220:3): [True: 434, False: 0] | Branch (220:3): [True: 434, Folded] | Branch (220:3): [True: 434, False: 0] ------------------ 221| 434| flushPendingLabels(nullptr); 222| | 223| 434| bool Created = getAssembler().registerSection(*Section); 224| | 225| 434| int64_t IntSubsection = 0; 226| 434| if (Subsection && ------------------ | Branch (226:7): [True: 0, False: 434] ------------------ 227| 0| !Subsection->evaluateAsAbsolute(IntSubsection, getAssembler())) ------------------ | Branch (227:7): [True: 0, False: 0] ------------------ 228| 0| report_fatal_error("Cannot evaluate subsection number"); 229| 434| if (IntSubsection < 0 || IntSubsection > 8192) ------------------ | Branch (229:7): [True: 0, False: 434] | Branch (229:28): [True: 0, False: 434] ------------------ 230| 0| report_fatal_error("Subsection number out of range"); 231| 434| CurInsertionPoint = 232| 434| Section->getSubsectionInsertionPoint(unsigned(IntSubsection)); 233| 434| return Created; 234| 434|} _ZN7llvm_ks16MCObjectStreamer14EmitAssignmentEPNS_8MCSymbolEPKNS_6MCExprE: 236| 203|bool MCObjectStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { 237| 203| getAssembler().registerSymbol(*Symbol); 238| 203| return MCStreamer::EmitAssignment(Symbol, Value); 239| 203|} _ZN7llvm_ks16MCObjectStreamer15EmitInstructionERNS_6MCInstERKNS_15MCSubtargetInfoERj: 248| 2.19k|{ 249| 2.19k| MCStreamer::EmitInstruction(Inst, STI, KsError); 250| | 251| 2.19k| MCSection *Sec = getCurrentSectionOnly(); 252| 2.19k| Sec->setHasInstructions(true); 253| | 254| | // Now that a machine instruction has been assembled into this section, make 255| | // a line entry for any .loc directive that has been seen. 256| | //MCCVLineEntry::Make(this); 257| | //MCDwarfLineEntry::Make(this, getCurrentSection().first); 258| | 259| | // If this instruction doesn't need relaxation, just emit it as data. 260| 2.19k| MCAssembler &Assembler = getAssembler(); 261| 2.19k| if (!Assembler.getBackend().mayNeedRelaxation(Inst)) { ------------------ | Branch (261:7): [True: 1.34k, False: 850] ------------------ 262| 1.34k| EmitInstToData(Inst, STI, KsError); 263| 1.34k| return; 264| 1.34k| } 265| | 266| | // Otherwise, relax and emit it as data if either: 267| | // - The RelaxAll flag was passed 268| | // - Bundling is enabled and this instruction is inside a bundle-locked 269| | // group. We want to emit all such instructions into the same data 270| | // fragment. 271| 850| if (Assembler.getRelaxAll() || ------------------ | Branch (271:7): [True: 0, False: 850] ------------------ 272| 850| (Assembler.isBundlingEnabled() && Sec->isBundleLocked())) { ------------------ | Branch (272:8): [True: 0, False: 850] | Branch (272:41): [True: 0, False: 0] ------------------ 273| 0| MCInst Relaxed(Inst.getAddress()); 274| 0| getAssembler().getBackend().relaxInstruction(Inst, Relaxed); 275| 0| while (getAssembler().getBackend().mayNeedRelaxation(Relaxed)) ------------------ | Branch (275:12): [True: 0, False: 0] ------------------ 276| 0| getAssembler().getBackend().relaxInstruction(Relaxed, Relaxed); 277| 0| EmitInstToData(Relaxed, STI, KsError); 278| 0| return; 279| 0| } 280| | 281| | // Otherwise emit to a separate fragment. 282| 850| EmitInstToFragment(Inst, STI); 283| 850|} _ZN7llvm_ks16MCObjectStreamer18EmitInstToFragmentERNS_6MCInstERKNS_15MCSubtargetInfoE: 287| 850|{ 288| 850| if (getAssembler().getRelaxAll() && getAssembler().isBundlingEnabled()) ------------------ | Branch (288:7): [True: 0, False: 850] | Branch (288:39): [True: 0, False: 0] ------------------ 289| 0| llvm_unreachable("All instructions should have already been relaxed"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 290| | 291| | // Always create a new, separate fragment here, because its size can change 292| | // during relaxation. 293| 850| MCRelaxableFragment *IF = new MCRelaxableFragment(Inst, STI); 294| 850| insert(IF); 295| | 296| 850| SmallString<128> Code; 297| 850| raw_svector_ostream VecOS(Code); 298| 850| unsigned int KsError; 299| 850| getAssembler().getEmitter().encodeInstruction(Inst, VecOS, IF->getFixups(), 300| 850| STI, KsError); 301| 850| IF->getContents().append(Code.begin(), Code.end()); 302| 850|} _ZN7llvm_ks16MCObjectStreamer9EmitBytesENS_9StringRefE: 428| 4.88k|void MCObjectStreamer::EmitBytes(StringRef Data) { 429| | //MCCVLineEntry::Make(this); 430| | //MCDwarfLineEntry::Make(this, getCurrentSection().first); 431| 4.88k| MCDataFragment *DF = getOrCreateDataFragment(); 432| 4.88k| flushPendingLabels(DF, DF->getContents().size()); 433| 4.88k| DF->getContents().append(Data.begin(), Data.end()); 434| 4.88k|} _ZN7llvm_ks16MCObjectStreamer20EmitValueToAlignmentEjljj: 439| 732| unsigned MaxBytesToEmit) { 440| 732| if (MaxBytesToEmit == 0) ------------------ | Branch (440:7): [True: 605, False: 127] ------------------ 441| 605| MaxBytesToEmit = ByteAlignment; 442| 732| insert(new MCAlignFragment(ByteAlignment, Value, ValueSize, MaxBytesToEmit)); 443| | 444| | // Update the maximum alignment on the current section if necessary. 445| 732| MCSection *CurSec = getCurrentSection().first; 446| 732| if (ByteAlignment > CurSec->getAlignment()) ------------------ | Branch (446:7): [True: 9, False: 723] ------------------ 447| 9| CurSec->setAlignment(ByteAlignment); 448| 732|} _ZN7llvm_ks16MCObjectStreamer17EmitCodeAlignmentEjj: 451| 732| unsigned MaxBytesToEmit) { 452| 732| EmitValueToAlignment(ByteAlignment, 0, 1, MaxBytesToEmit); 453| 732| cast(getCurrentFragment())->setEmitNops(true); 454| 732|} _ZN7llvm_ks16MCObjectStreamer17emitValueToOffsetEPKNS_6MCExprEh: 457| 174| unsigned char Value) { 458| 174| insert(new MCOrgFragment(*Offset, Value)); 459| 174|} _ZN7llvm_ks16MCObjectStreamer8EmitFillEmh: 506| 292|void MCObjectStreamer::EmitFill(uint64_t NumBytes, uint8_t FillValue) { 507| 292| const MCSection *Sec = getCurrentSection().first; 508| 292| (void)Sec; 509| 292| assert(Sec && "need a section"); ------------------ | Branch (509:3): [True: 292, False: 0] | Branch (509:3): [True: 292, Folded] | Branch (509:3): [True: 292, False: 0] ------------------ 510| 292| insert(new MCFillFragment(FillValue, NumBytes)); 511| 292|} _ZN7llvm_ks16MCObjectStreamer10FinishImplEv: 514| 185|{ 515| 185| unsigned int KsError = 0; 516| | // If we are generating dwarf for assembly source files dump out the sections. 517| | //if (getContext().getGenDwarfForAssembly()) 518| | // MCGenDwarfInfo::Emit(this); 519| | 520| | // Dump out the dwarf file & directory tables and line tables. 521| | //MCDwarfLineTable::Emit(this, getAssembler().getDWARFLinetableParams()); 522| | 523| 185| flushPendingLabels(nullptr); 524| 185| getAssembler().setSymResolver(getSymResolver()); 525| 185| getAssembler().Finish(KsError); 526| | 527| 185| return KsError; 528| 185|} _ZN7llvm_ks16MCObjectStreamer22getCurrentFragmentSizeEv: 530| 20.0k|uint64_t MCObjectStreamer::getCurrentFragmentSize() { 531| 20.0k| auto *F = dyn_cast_or_null(getCurrentFragment()); 532| 20.0k| if (nullptr != F) ------------------ | Branch (532:7): [True: 1.32k, False: 18.7k] ------------------ 533| 1.32k| return F->getContents().size(); 534| 18.7k| return 0; 535| 20.0k|} _ZN7llvm_ks14MCObjectWriterD2Ev: 17| 430|MCObjectWriter::~MCObjectWriter() { 18| 430|} _ZNK7llvm_ks14MCObjectWriter34isSymbolRefDifferenceFullyResolvedERKNS_11MCAssemblerEPKNS_15MCSymbolRefExprES6_bRb: 23| 4|{ 24| 4| valid = true; 25| | // Modified symbol references cannot be resolved. 26| 4| if (A->getKind() != MCSymbolRefExpr::VK_None || ------------------ | Branch (26:7): [True: 0, False: 4] ------------------ 27| 4| B->getKind() != MCSymbolRefExpr::VK_None) ------------------ | Branch (27:7): [True: 0, False: 4] ------------------ 28| 0| return false; 29| | 30| 4| const MCSymbol &SA = A->getSymbol(); 31| 4| const MCSymbol &SB = B->getSymbol(); 32| 4| if (SA.isUndefined() || SB.isUndefined()) ------------------ | Branch (32:7): [True: 0, False: 4] | Branch (32:27): [True: 0, False: 4] ------------------ 33| 0| return false; 34| | 35| 4| if (!SA.getFragment() || !SB.getFragment()) ------------------ | Branch (35:7): [True: 0, False: 4] | Branch (35:28): [True: 0, False: 4] ------------------ 36| 0| return false; 37| | 38| 4| if (!SA.isInSection()) { ------------------ | Branch (38:7): [True: 0, False: 4] ------------------ 39| 0| valid = false; 40| 0| return false; 41| 0| } 42| 4| return isSymbolRefDifferenceFullyResolvedImpl(Asm, SA, SB, InSet); 43| 4|} _ZNK7llvm_ks14MCObjectWriter38isSymbolRefDifferenceFullyResolvedImplERKNS_11MCAssemblerERKNS_8MCSymbolES6_b: 47| 4| bool InSet) const { 48| 4| return isSymbolRefDifferenceFullyResolvedImpl(Asm, A, *B.getFragment(), InSet, 49| 4| false); 50| 4|} _ZNK7llvm_ks14MCObjectWriter38isSymbolRefDifferenceFullyResolvedImplERKNS_11MCAssemblerERKNS_8MCSymbolERKNS_10MCFragmentEbb: 54| 1.25k| bool InSet, bool IsPCRel) const { 55| 1.25k| const MCSection &SecA = SymA.getSection(); 56| 1.25k| const MCSection &SecB = *FB.getParent(); 57| | // On ELF and COFF A - B is absolute if A and B are in the same section. 58| 1.25k| return &SecA == &SecB; 59| 1.25k|} _ZN7llvm_ks8AsmLexerC2ERKNS_9MCAsmInfoE: 24| 430|AsmLexer::AsmLexer(const MCAsmInfo &MAI) : MAI(MAI) { 25| 430| CurPtr = nullptr; 26| 430| isAtStartOfLine = true; 27| 430| AllowAtInIdentifier = !StringRef(MAI.getCommentString()).startswith("@"); 28| 430| defaultRadix = MAI.getRadix(); 29| 430|} _ZN7llvm_ks8AsmLexerD2Ev: 31| 430|AsmLexer::~AsmLexer() { 32| 430|} _ZN7llvm_ks8AsmLexer9setBufferENS_9StringRefEPKc: 34| 2.29k|void AsmLexer::setBuffer(StringRef Buf, const char *ptr) { 35| 2.29k| CurBuf = Buf; 36| | 37| 2.29k| if (ptr) ------------------ | Branch (37:7): [True: 932, False: 1.36k] ------------------ 38| 932| CurPtr = ptr; 39| 1.36k| else 40| 1.36k| CurPtr = CurBuf.begin(); 41| | 42| 2.29k| TokStart = nullptr; 43| 2.29k|} _ZN7llvm_ks8AsmLexer11ReturnErrorEPKcRKNSt3__112basic_stringIcNS3_11char_traitsIcEENS3_9allocatorIcEEEE: 48| 18.6k|{ 49| | //SetError(SMLoc::getFromPointer(Loc), Msg); 50| | 51| 18.6k| return AsmToken(AsmToken::Error, StringRef(Loc, 0)); 52| 18.6k|} _ZN7llvm_ks8AsmLexer11getNextCharEv: 54| 409k|int AsmLexer::getNextChar() { 55| 409k| char CurChar = *CurPtr++; 56| 409k| switch (CurChar) { 57| 408k| default: ------------------ | Branch (57:3): [True: 408k, False: 707] ------------------ 58| 408k| return (unsigned char)CurChar; 59| 707| case 0: ------------------ | Branch (59:3): [True: 707, False: 408k] ------------------ 60| | // A nul character in the stream is either the end of the current buffer or 61| | // a random nul in the file. Disambiguate that here. 62| 707| if (CurPtr - 1 != CurBuf.end()) ------------------ | Branch (62:9): [True: 0, False: 707] ------------------ 63| 0| return 0; // Just whitespace. 64| | 65| | // Otherwise, return end of file. 66| 707| --CurPtr; // Another call to lex will return EOF again. 67| | return EOF; 68| 409k| } 69| 409k|} _ZN7llvm_ks8AsmLexer15LexFloatLiteralEv: 76| 1.46k|AsmToken AsmLexer::LexFloatLiteral() { 77| | // Skip the fractional digit sequence. 78| 1.46k| while (isdigit(*CurPtr)) ------------------ | Branch (78:10): [True: 0, False: 1.46k] ------------------ 79| 0| ++CurPtr; 80| | 81| | // Check for exponent; we intentionally accept a slighlty wider set of 82| | // literals here and rely on the upstream client to reject invalid ones (e.g., 83| | // "1e+"). 84| 1.46k| if (*CurPtr == 'e' || *CurPtr == 'E') { ------------------ | Branch (84:7): [True: 454, False: 1.01k] | Branch (84:25): [True: 237, False: 777] ------------------ 85| 691| ++CurPtr; 86| 691| if (*CurPtr == '-' || *CurPtr == '+') ------------------ | Branch (86:9): [True: 357, False: 334] | Branch (86:27): [True: 252, False: 82] ------------------ 87| 609| ++CurPtr; 88| 2.30k| while (isdigit(*CurPtr)) ------------------ | Branch (88:12): [True: 1.61k, False: 691] ------------------ 89| 1.61k| ++CurPtr; 90| 691| } 91| | 92| 1.46k| return AsmToken(AsmToken::Real, 93| 1.46k| StringRef(TokStart, CurPtr - TokStart)); 94| 1.46k|} _ZN7llvm_ks8AsmLexer18LexHexFloatLiteralEb: 103| 1.10k|{ 104| 1.10k| assert((*CurPtr == 'p' || *CurPtr == 'P' || *CurPtr == '.') && ------------------ | Branch (104:3): [True: 292, False: 817] | Branch (104:3): [True: 379, False: 438] | Branch (104:3): [True: 438, False: 0] | Branch (104:3): [True: 1.10k, Folded] | Branch (104:3): [True: 1.10k, False: 0] ------------------ 105| 1.10k| "unexpected parse state in floating hex"); 106| 1.10k| bool NoFracDigits = true; 107| | 108| | // Skip the fractional part if there is one 109| 1.10k| if (*CurPtr == '.') { ------------------ | Branch (109:7): [True: 438, False: 671] ------------------ 110| 438| ++CurPtr; 111| | 112| 438| const char *FracStart = CurPtr; 113| 4.11k| while (isxdigit(*CurPtr)) ------------------ | Branch (113:12): [True: 3.67k, False: 438] ------------------ 114| 3.67k| ++CurPtr; 115| | 116| 438| NoFracDigits = CurPtr == FracStart; 117| 438| } 118| | 119| 1.10k| if (NoIntDigits && NoFracDigits) ------------------ | Branch (119:7): [True: 198, False: 911] | Branch (119:22): [True: 0, False: 198] ------------------ 120| 0| return ReturnError(TokStart, "invalid hexadecimal floating-point constant: " 121| 0| "expected at least one significand digit"); 122| | 123| | // Make sure we do have some kind of proper exponent part 124| 1.10k| if (*CurPtr != 'p' && *CurPtr != 'P') ------------------ | Branch (124:7): [True: 639, False: 470] | Branch (124:25): [True: 1, False: 638] ------------------ 125| 1| return ReturnError(TokStart, "invalid hexadecimal floating-point constant: " 126| 1| "expected exponent part 'p'"); 127| 1.10k| ++CurPtr; 128| | 129| 1.10k| if (*CurPtr == '+' || *CurPtr == '-') ------------------ | Branch (129:7): [True: 382, False: 726] | Branch (129:25): [True: 8, False: 718] ------------------ 130| 390| ++CurPtr; 131| | 132| | // N.b. exponent digits are *not* hex 133| 1.10k| const char *ExpStart = CurPtr; 134| 3.69k| while (isdigit(*CurPtr)) ------------------ | Branch (134:10): [True: 2.58k, False: 1.10k] ------------------ 135| 2.58k| ++CurPtr; 136| | 137| 1.10k| if (CurPtr == ExpStart) ------------------ | Branch (137:7): [True: 2, False: 1.10k] ------------------ 138| 2| return ReturnError(TokStart, "invalid hexadecimal floating-point constant: " 139| 2| "expected at least one exponent digit"); 140| | 141| 1.10k| return AsmToken(AsmToken::Real, StringRef(TokStart, CurPtr - TokStart)); 142| 1.10k|} _ZN7llvm_ks8AsmLexer13LexIdentifierEv: 149| 64.5k|AsmToken AsmLexer::LexIdentifier() { 150| | // Check for floating point literals. 151| 64.5k| if (CurPtr[-1] == '.' && isdigit(*CurPtr)) { ------------------ | Branch (151:7): [True: 30.3k, False: 34.2k] | Branch (151:28): [True: 2.07k, False: 28.3k] ------------------ 152| | // Disambiguate a .1243foo identifier from a floating literal. 153| 74.5k| while (isdigit(*CurPtr)) ------------------ | Branch (153:12): [True: 72.4k, False: 2.07k] ------------------ 154| 72.4k| ++CurPtr; 155| 2.07k| if (*CurPtr == 'e' || *CurPtr == 'E' || ------------------ | Branch (155:9): [True: 454, False: 1.61k] | Branch (155:27): [True: 237, False: 1.38k] ------------------ 156| 1.38k| !IsIdentifierChar(*CurPtr, AllowAtInIdentifier)) ------------------ | Branch (156:9): [True: 777, False: 604] ------------------ 157| 1.46k| return LexFloatLiteral(); 158| 2.07k| } 159| | 160| 407k| while (IsIdentifierChar(*CurPtr, AllowAtInIdentifier)) ------------------ | Branch (160:10): [True: 343k, False: 63.1k] ------------------ 161| 343k| ++CurPtr; 162| | 163| | // Handle . as a special case. 164| 63.1k| if (CurPtr == TokStart+1 && TokStart[0] == '.') ------------------ | Branch (164:7): [True: 16.4k, False: 46.6k] | Branch (164:31): [True: 5.70k, False: 10.7k] ------------------ 165| 5.70k| return AsmToken(AsmToken::Dot, StringRef(TokStart, 1)); 166| | 167| 57.4k| return AsmToken(AsmToken::Identifier, StringRef(TokStart, CurPtr - TokStart)); 168| 63.1k|} _ZN7llvm_ks8AsmLexer8LexSlashEv: 173| 166|{ 174| 166| switch (*CurPtr) { 175| 1| case '*': break; // C style comment. ------------------ | Branch (175:3): [True: 1, False: 165] ------------------ 176| 25| case '/': return ++CurPtr, LexLineComment(); ------------------ | Branch (176:3): [True: 25, False: 141] ------------------ 177| 140| default: return AsmToken(AsmToken::Slash, StringRef(CurPtr-1, 1)); ------------------ | Branch (177:3): [True: 140, False: 26] ------------------ 178| 166| } 179| | 180| | // C Style comment. 181| 1| ++CurPtr; // skip the star. 182| 3| while (1) { ------------------ | Branch (182:10): [True: 3, Folded] ------------------ 183| 3| int CurChar = getNextChar(); 184| 3| switch (CurChar) { ------------------ | Branch (184:13): [True: 2, False: 1] ------------------ 185| 0| case EOF: ------------------ | Branch (185:5): [True: 0, False: 3] ------------------ 186| 0| return ReturnError(TokStart, "unterminated comment"); 187| 2| case '*': ------------------ | Branch (187:5): [True: 2, False: 1] ------------------ 188| | // End of the comment? 189| 2| if (CurPtr[0] != '/') break; ------------------ | Branch (189:11): [True: 1, False: 1] ------------------ 190| | 191| 1| ++CurPtr; // End the */. 192| 1| return LexToken(); 193| 3| } 194| 3| } 195| 1|} _ZN7llvm_ks8AsmLexer14LexLineCommentEv: 199| 1.24k|AsmToken AsmLexer::LexLineComment() { 200| | // FIXME: This is broken if we happen to a comment at the end of a file, which 201| | // was .included, and which doesn't end with a newline. 202| 1.24k| int CurChar = getNextChar(); 203| 16.5k| while (CurChar != '\n' && CurChar != '\r' && CurChar != EOF) ------------------ | Branch (203:10): [True: 15.7k, False: 844] | Branch (203:29): [True: 15.3k, False: 387] | Branch (203:48): [True: 15.3k, False: 14] ------------------ 204| 15.3k| CurChar = getNextChar(); 205| | 206| 1.24k| if (CurChar == EOF) ------------------ | Branch (206:7): [True: 14, False: 1.23k] ------------------ 207| 14| return AsmToken(AsmToken::Eof, StringRef(TokStart, 0)); 208| 1.23k| return AsmToken(AsmToken::EndOfStatement, StringRef(TokStart, 0)); 209| 1.24k|} _ZN7llvm_ks8AsmLexer8LexDigitEv: 259| 13.1k|{ 260| | // Decimal integer: [1-9][0-9]* 261| 13.1k| if (CurPtr[-1] != '0' || CurPtr[0] == '.') { ------------------ | Branch (261:7): [True: 9.47k, False: 3.63k] | Branch (261:28): [True: 125, False: 3.51k] ------------------ 262| 9.60k| unsigned Radix = doLookAhead(CurPtr, 10); 263| | 264| 9.60k| if (defaultRadix == 16) ------------------ | Branch (264:9): [True: 9.60k, False: 0] ------------------ 265| 9.60k| Radix = 16; 266| | 267| 9.60k| bool isHex = Radix == 16; 268| | // Check for floating point literals. 269| 9.60k| if (!isHex && (*CurPtr == '.' || *CurPtr == 'e')) { ------------------ | Branch (269:9): [True: 0, False: 9.60k] | Branch (269:20): [True: 0, False: 0] | Branch (269:38): [True: 0, False: 0] ------------------ 270| 0| ++CurPtr; 271| 0| return LexFloatLiteral(); 272| 0| } 273| | 274| 9.60k| StringRef Result(TokStart, CurPtr - TokStart); 275| | 276| 9.60k| APInt Value(128, 0, true); 277| 9.60k| if (Result.getAsInteger(Radix, Value)) ------------------ | Branch (277:9): [True: 0, False: 9.60k] ------------------ 278| 0| return ReturnError(TokStart, !isHex ? "invalid decimal number" : ------------------ | Branch (278:36): [True: 0, False: 0] ------------------ 279| 0| "invalid hexdecimal number"); 280| | 281| | // Consume the [bB][hH]. 282| 9.60k| if (defaultRadix != 16) { ------------------ | Branch (282:9): [True: 0, False: 9.60k] ------------------ 283| 0| if (Radix == 2 || Radix == 16) ------------------ | Branch (283:11): [True: 0, False: 0] | Branch (283:25): [True: 0, False: 0] ------------------ 284| 0| ++CurPtr; 285| 0| } 286| | 287| | // The darwin/x86 (and x86-64) assembler accepts and ignores type 288| | // suffices on integer literals. 289| 9.60k| SkipIgnoredIntegerSuffix(CurPtr); 290| | 291| 9.60k| return intToken(Result, Value); 292| 9.60k| } 293| | 294| 3.51k| if (*CurPtr == 'b') { ------------------ | Branch (294:7): [True: 4, False: 3.50k] ------------------ 295| 4| ++CurPtr; 296| | // See if we actually have "0b" as part of something like "jmp 0b\n" 297| 4| if (!isdigit(CurPtr[0])) { ------------------ | Branch (297:9): [True: 4, False: 0] ------------------ 298| 4| --CurPtr; 299| 4| StringRef Result(TokStart, CurPtr - TokStart); 300| 4| return AsmToken(AsmToken::Integer, Result, 0); 301| 4| } 302| 0| const char *NumStart = CurPtr; 303| 0| while (CurPtr[0] == '0' || CurPtr[0] == '1') ------------------ | Branch (303:12): [True: 0, False: 0] | Branch (303:32): [True: 0, False: 0] ------------------ 304| 0| ++CurPtr; 305| | 306| | // Requires at least one binary digit. 307| 0| if (CurPtr == NumStart) ------------------ | Branch (307:9): [True: 0, False: 0] ------------------ 308| 0| return ReturnError(TokStart, "invalid binary number"); 309| | 310| 0| StringRef Result(TokStart, CurPtr - TokStart); 311| | 312| 0| APInt Value(128, 0, true); 313| 0| if (Result.substr(2).getAsInteger(2, Value)) ------------------ | Branch (313:9): [True: 0, False: 0] ------------------ 314| 0| return ReturnError(TokStart, "invalid binary number"); 315| | 316| | // The darwin/x86 (and x86-64) assembler accepts and ignores ULL and LL 317| | // suffixes on integer literals. 318| 0| SkipIgnoredIntegerSuffix(CurPtr); 319| | 320| 0| return intToken(Result, Value); 321| 0| } 322| | 323| 3.50k| if (*CurPtr == 'x' || *CurPtr == 'X') { ------------------ | Branch (323:7): [True: 1.04k, False: 2.46k] | Branch (323:25): [True: 340, False: 2.12k] ------------------ 324| 1.38k| ++CurPtr; 325| 1.38k| const char *NumStart = CurPtr; 326| 34.9k| while (isxdigit(CurPtr[0])) ------------------ | Branch (326:12): [True: 33.5k, False: 1.38k] ------------------ 327| 33.5k| ++CurPtr; 328| | 329| | // "0x.0p0" is valid, and "0x0p0" (but not "0xp0" for example, which will be 330| | // diagnosed by LexHexFloatLiteral). 331| 1.38k| if (CurPtr[0] == '.' || CurPtr[0] == 'p' || CurPtr[0] == 'P') ------------------ | Branch (331:9): [True: 438, False: 947] | Branch (331:29): [True: 292, False: 655] | Branch (331:49): [True: 379, False: 276] ------------------ 332| 1.10k| return LexHexFloatLiteral(NumStart == CurPtr); 333| | 334| | // Otherwise requires at least one hex digit. 335| 276| if (CurPtr == NumStart) ------------------ | Branch (335:9): [True: 2, False: 274] ------------------ 336| 2| return ReturnError(CurPtr-2, "invalid hexadecimal number"); 337| | 338| 274| APInt Result(128, 0); 339| 274| if (StringRef(TokStart, CurPtr - TokStart).getAsInteger(0, Result)) ------------------ | Branch (339:9): [True: 0, False: 274] ------------------ 340| 0| return ReturnError(TokStart, "invalid hexadecimal number"); 341| | 342| | // Consume the optional [hH]. 343| 274| if (*CurPtr == 'h' || *CurPtr == 'H') ------------------ | Branch (343:9): [True: 0, False: 274] | Branch (343:27): [True: 0, False: 274] ------------------ 344| 0| ++CurPtr; 345| | 346| | // The darwin/x86 (and x86-64) assembler accepts and ignores ULL and LL 347| | // suffixes on integer literals. 348| 274| SkipIgnoredIntegerSuffix(CurPtr); 349| | 350| 274| return intToken(StringRef(TokStart, CurPtr - TokStart), Result); 351| 274| } 352| | 353| | // Either octal or hexadecimal. 354| 2.12k| APInt Value(128, 0, true); 355| 2.12k| unsigned Radix = doLookAhead(CurPtr, 8); 356| 2.12k| bool isHex = Radix == 16; 357| 2.12k| StringRef Result(TokStart, CurPtr - TokStart); 358| 2.12k| if (Result.getAsInteger(Radix, Value)) ------------------ | Branch (358:7): [True: 12, False: 2.11k] ------------------ 359| 12| return ReturnError(TokStart, !isHex ? "invalid octal number" : ------------------ | Branch (359:34): [True: 12, False: 0] ------------------ 360| 12| "invalid hexdecimal number"); 361| | 362| | // Consume the [hH]. 363| 2.11k| if (Radix == 16) ------------------ | Branch (363:7): [True: 0, False: 2.11k] ------------------ 364| 0| ++CurPtr; 365| | 366| | // The darwin/x86 (and x86-64) assembler accepts and ignores ULL and LL 367| | // suffixes on integer literals. 368| 2.11k| SkipIgnoredIntegerSuffix(CurPtr); 369| | 370| 2.11k| return intToken(Result, Value); 371| 2.12k|} _ZN7llvm_ks8AsmLexer14LexSingleQuoteEv: 375| 539|{ 376| 539| int CurChar = getNextChar(); 377| | 378| 539| if (CurChar == '\\') ------------------ | Branch (378:7): [True: 381, False: 158] ------------------ 379| 381| CurChar = getNextChar(); 380| | 381| 539| if (CurChar == EOF) ------------------ | Branch (381:7): [True: 0, False: 539] ------------------ 382| 0| return ReturnError(TokStart, "unterminated single quote"); 383| | 384| 539| CurChar = getNextChar(); 385| | 386| 539| if (CurChar != '\'') ------------------ | Branch (386:7): [True: 146, False: 393] ------------------ 387| 146| return ReturnError(TokStart, "single quote way too long"); 388| | 389| | // The idea here being that 'c' is basically just an integral 390| | // constant. 391| 393| StringRef Res = StringRef(TokStart,CurPtr - TokStart); 392| 393| long long Value; 393| | 394| 393| if (Res.startswith("\'\\")) { ------------------ | Branch (394:7): [True: 342, False: 51] ------------------ 395| 342| char theChar = Res[2]; 396| 342| switch (theChar) { 397| 168| default: Value = theChar; break; ------------------ | Branch (397:7): [True: 168, False: 174] ------------------ 398| 46| case '\'': Value = '\''; break; ------------------ | Branch (398:7): [True: 46, False: 296] ------------------ 399| 0| case 't': Value = '\t'; break; ------------------ | Branch (399:7): [True: 0, False: 342] ------------------ 400| 128| case 'n': Value = '\n'; break; ------------------ | Branch (400:7): [True: 128, False: 214] ------------------ 401| 0| case 'b': Value = '\b'; break; ------------------ | Branch (401:7): [True: 0, False: 342] ------------------ 402| 342| } 403| 342| } else 404| 51| Value = TokStart[1]; 405| | 406| 393| return AsmToken(AsmToken::Integer, Res, Value); 407| 393|} _ZN7llvm_ks8AsmLexer8LexQuoteEv: 412| 2.46k|{ 413| 2.46k| int CurChar = getNextChar(); 414| | // TODO: does gas allow multiline string constants? 415| 111k| while (CurChar != '"') { ------------------ | Branch (415:10): [True: 109k, False: 2.45k] ------------------ 416| 109k| if (CurChar == '\\') { ------------------ | Branch (416:9): [True: 4.40k, False: 104k] ------------------ 417| | // Allow \", etc. 418| 4.40k| CurChar = getNextChar(); 419| 4.40k| } 420| | 421| 109k| if (CurChar == EOF) ------------------ | Branch (421:9): [True: 10, False: 109k] ------------------ 422| 10| return ReturnError(TokStart, "unterminated string constant"); 423| | 424| 109k| CurChar = getNextChar(); 425| 109k| } 426| | 427| 2.45k| return AsmToken(AsmToken::String, StringRef(TokStart, CurPtr - TokStart)); 428| 2.46k|} _ZN7llvm_ks8AsmLexer22LexUntilEndOfStatementEv: 430| 16|StringRef AsmLexer::LexUntilEndOfStatement() { 431| 16| TokStart = CurPtr; 432| | 433| 7.73k| while (!isAtStartOfComment(CurPtr) && // Start of line comment. ------------------ | Branch (433:10): [True: 7.73k, False: 0] ------------------ 434| 7.73k| !isAtStatementSeparator(CurPtr) && // End of statement marker. ------------------ | Branch (434:10): [True: 7.72k, False: 13] ------------------ 435| 7.72k| *CurPtr != '\n' && *CurPtr != '\r' && ------------------ | Branch (435:10): [True: 7.72k, False: 0] | Branch (435:29): [True: 7.72k, False: 0] ------------------ 436| 7.72k| (*CurPtr != 0 || CurPtr != CurBuf.end())) { ------------------ | Branch (436:11): [True: 7.71k, False: 3] | Branch (436:27): [True: 0, False: 3] ------------------ 437| 7.71k| ++CurPtr; 438| 7.71k| } 439| 16| return StringRef(TokStart, CurPtr-TokStart); 440| 16|} _ZN7llvm_ks8AsmLexer17LexUntilEndOfLineEv: 442| 956|StringRef AsmLexer::LexUntilEndOfLine() { 443| 956| TokStart = CurPtr; 444| | 445| 7.60k| while (*CurPtr != '\n' && *CurPtr != '\r' && ------------------ | Branch (445:10): [True: 7.28k, False: 321] | Branch (445:29): [True: 6.64k, False: 635] ------------------ 446| 6.64k| (*CurPtr != 0 || CurPtr != CurBuf.end())) { ------------------ | Branch (446:11): [True: 6.64k, False: 0] | Branch (446:27): [True: 0, False: 0] ------------------ 447| 6.64k| ++CurPtr; 448| 6.64k| } 449| 956| return StringRef(TokStart, CurPtr-TokStart); 450| 956|} _ZN7llvm_ks8AsmLexer10peekTokensENS_15MutableArrayRefINS_8AsmTokenEEEb: 454| 321|{ 455| 321| const char *SavedTokStart = TokStart; 456| 321| const char *SavedCurPtr = CurPtr; 457| 321| bool SavedAtStartOfLine = isAtStartOfLine; 458| 321| bool SavedSkipSpace = SkipSpace; 459| | 460| 321| std::string SavedErr = getErr(); 461| 321| SMLoc SavedErrLoc = getErrLoc(); 462| | 463| 321| SkipSpace = ShouldSkipSpace; 464| | 465| 321| size_t ReadCount; 466| 642| for (ReadCount = 0; ReadCount < Buf.size(); ++ReadCount) { ------------------ | Branch (466:23): [True: 321, False: 321] ------------------ 467| 321| AsmToken Token = LexToken(); 468| | 469| 321| Buf[ReadCount] = Token; 470| | 471| 321| if (Token.is(AsmToken::Eof)) ------------------ | Branch (471:9): [True: 0, False: 321] ------------------ 472| 0| break; 473| 321| } 474| | 475| 321| SetError(SavedErrLoc, SavedErr); 476| | 477| 321| SkipSpace = SavedSkipSpace; 478| 321| isAtStartOfLine = SavedAtStartOfLine; 479| 321| CurPtr = SavedCurPtr; 480| 321| TokStart = SavedTokStart; 481| | 482| 321| return ReadCount; 483| 321|} _ZN7llvm_ks8AsmLexer18isAtStartOfCommentEPKc: 485| 283k|bool AsmLexer::isAtStartOfComment(const char *Ptr) { 486| 283k| const char *CommentString = MAI.getCommentString(); 487| | 488| 283k| if (CommentString[1] == '\0') ------------------ | Branch (488:7): [True: 283k, False: 0] ------------------ 489| 283k| return CommentString[0] == Ptr[0]; 490| | 491| | // FIXME: special case for the bogus "##" comment string in X86MCAsmInfoDarwin 492| 0| if (CommentString[1] == '#') ------------------ | Branch (492:7): [True: 0, False: 0] ------------------ 493| 0| return CommentString[0] == Ptr[0]; 494| | 495| 0| return strncmp(Ptr, CommentString, strlen(CommentString)) == 0; 496| 0|} _ZN7llvm_ks8AsmLexer22isAtStatementSeparatorEPKc: 498| 281k|bool AsmLexer::isAtStatementSeparator(const char *Ptr) { 499| 281k| return strncmp(Ptr, MAI.getSeparatorString(), 500| 281k| strlen(MAI.getSeparatorString())) == 0; 501| 281k|} _ZN7llvm_ks8AsmLexer8LexTokenEv: 504| 275k|{ 505| 275k| TokStart = CurPtr; 506| | // This always consumes at least one character. 507| 275k| int CurChar = getNextChar(); 508| | 509| 275k| if (isAtStartOfComment(TokStart)) { ------------------ | Branch (509:7): [True: 1.22k, False: 274k] ------------------ 510| | // If this comment starts with a '#', then return the Hash token and let 511| | // the assembler parser see if it can be parsed as a cpp line filename 512| | // comment. We do this only if we are at the start of a line. 513| 1.22k| if (CurChar == '#' && isAtStartOfLine) ------------------ | Branch (513:9): [True: 0, False: 1.22k] | Branch (513:27): [True: 0, False: 0] ------------------ 514| 0| return AsmToken(AsmToken::Hash, StringRef(TokStart, 1)); 515| 1.22k| isAtStartOfLine = true; 516| 1.22k| return LexLineComment(); 517| 1.22k| } 518| 274k| if (isAtStatementSeparator(TokStart)) { ------------------ | Branch (518:7): [True: 13.4k, False: 260k] ------------------ 519| 13.4k| CurPtr += strlen(MAI.getSeparatorString()) - 1; 520| 13.4k| return AsmToken(AsmToken::EndOfStatement, 521| 13.4k| StringRef(TokStart, strlen(MAI.getSeparatorString()))); 522| 13.4k| } 523| | 524| | // If we're missing a newline at EOF, make sure we still get an 525| | // EndOfStatement token before the Eof token. 526| 260k| if (CurChar == EOF && !isAtStartOfLine) { ------------------ | Branch (526:7): [True: 683, False: 259k] | Branch (526:25): [True: 337, False: 346] ------------------ 527| 337| isAtStartOfLine = true; 528| 337| return AsmToken(AsmToken::EndOfStatement, StringRef(TokStart, 1)); 529| 337| } 530| | 531| 260k| isAtStartOfLine = false; 532| 260k| switch (CurChar) { 533| 83.1k| default: ------------------ | Branch (533:3): [True: 83.1k, False: 177k] ------------------ 534| | // Handle identifier: [a-zA-Z_.][a-zA-Z0-9_$.@]* 535| 83.1k| if (isalpha(CurChar) || CurChar == '_' || CurChar == '.') ------------------ | Branch (535:9): [True: 34.0k, False: 49.0k] | Branch (535:29): [True: 213, False: 48.8k] | Branch (535:47): [True: 30.3k, False: 18.5k] ------------------ 536| 64.5k| return LexIdentifier(); 537| | 538| | // Unknown character, emit an error. 539| 18.5k| return ReturnError(TokStart, "invalid character in input"); 540| 346| case EOF: return AsmToken(AsmToken::Eof, StringRef(TokStart, 0)); ------------------ | Branch (540:3): [True: 346, False: 259k] ------------------ 541| 0| case 0: ------------------ | Branch (541:3): [True: 0, False: 260k] ------------------ 542| 16.8k| case ' ': ------------------ | Branch (542:3): [True: 16.8k, False: 243k] ------------------ 543| 21.1k| case '\t': ------------------ | Branch (543:3): [True: 4.31k, False: 255k] ------------------ 544| 21.1k| if (SkipSpace) { ------------------ | Branch (544:9): [True: 21.1k, False: 0] ------------------ 545| | // Ignore whitespace. 546| 21.1k| return LexToken(); 547| 21.1k| } else { 548| 0| int len = 1; 549| 0| while (*CurPtr==' ' || *CurPtr=='\t') { ------------------ | Branch (549:14): [True: 0, False: 0] | Branch (549:30): [True: 0, False: 0] ------------------ 550| 0| CurPtr++; 551| 0| len++; 552| 0| } 553| 0| return AsmToken(AsmToken::Space, StringRef(TokStart, len)); 554| 0| } 555| 9.32k| case '\n': // FALL THROUGH. ------------------ | Branch (555:3): [True: 9.32k, False: 250k] ------------------ 556| 18.6k| case '\r': ------------------ | Branch (556:3): [True: 9.28k, False: 251k] ------------------ 557| 18.6k| isAtStartOfLine = true; 558| 18.6k| return AsmToken(AsmToken::EndOfStatement, StringRef(TokStart, 1)); 559| 563| case ':': return AsmToken(AsmToken::Colon, StringRef(TokStart, 1)); ------------------ | Branch (559:3): [True: 563, False: 259k] ------------------ 560| 2.75k| case '+': return AsmToken(AsmToken::Plus, StringRef(TokStart, 1)); ------------------ | Branch (560:3): [True: 2.75k, False: 257k] ------------------ 561| 5.86k| case '-': return AsmToken(AsmToken::Minus, StringRef(TokStart, 1)); ------------------ | Branch (561:3): [True: 5.86k, False: 254k] ------------------ 562| 95| case '~': return AsmToken(AsmToken::Tilde, StringRef(TokStart, 1)); ------------------ | Branch (562:3): [True: 95, False: 260k] ------------------ 563| 46.0k| case '(': return AsmToken(AsmToken::LParen, StringRef(TokStart, 1)); ------------------ | Branch (563:3): [True: 46.0k, False: 214k] ------------------ 564| 1.43k| case ')': return AsmToken(AsmToken::RParen, StringRef(TokStart, 1)); ------------------ | Branch (564:3): [True: 1.43k, False: 258k] ------------------ 565| 220| case '[': return AsmToken(AsmToken::LBrac, StringRef(TokStart, 1)); ------------------ | Branch (565:3): [True: 220, False: 260k] ------------------ 566| 30| case ']': return AsmToken(AsmToken::RBrac, StringRef(TokStart, 1)); ------------------ | Branch (566:3): [True: 30, False: 260k] ------------------ 567| 1.44k| case '{': return AsmToken(AsmToken::LCurly, StringRef(TokStart, 1)); ------------------ | Branch (567:3): [True: 1.44k, False: 258k] ------------------ 568| 346| case '}': return AsmToken(AsmToken::RCurly, StringRef(TokStart, 1)); ------------------ | Branch (568:3): [True: 346, False: 259k] ------------------ 569| 560| case '*': return AsmToken(AsmToken::Star, StringRef(TokStart, 1)); ------------------ | Branch (569:3): [True: 560, False: 259k] ------------------ 570| 46.9k| case ',': return AsmToken(AsmToken::Comma, StringRef(TokStart, 1)); ------------------ | Branch (570:3): [True: 46.9k, False: 213k] ------------------ 571| 517| case '$': return AsmToken(AsmToken::Dollar, StringRef(TokStart, 1)); ------------------ | Branch (571:3): [True: 517, False: 259k] ------------------ 572| 0| case '@': return AsmToken(AsmToken::At, StringRef(TokStart, 1)); ------------------ | Branch (572:3): [True: 0, False: 260k] ------------------ 573| 2.66k| case '\\': return AsmToken(AsmToken::BackSlash, StringRef(TokStart, 1)); ------------------ | Branch (573:3): [True: 2.66k, False: 257k] ------------------ 574| 2.77k| case '=': ------------------ | Branch (574:3): [True: 2.77k, False: 257k] ------------------ 575| 2.77k| if (*CurPtr == '=') ------------------ | Branch (575:9): [True: 468, False: 2.31k] ------------------ 576| 468| return ++CurPtr, AsmToken(AsmToken::EqualEqual, StringRef(TokStart, 2)); 577| 2.31k| return AsmToken(AsmToken::Equal, StringRef(TokStart, 1)); 578| 21| case '|': ------------------ | Branch (578:3): [True: 21, False: 260k] ------------------ 579| 21| if (*CurPtr == '|') ------------------ | Branch (579:9): [True: 4, False: 17] ------------------ 580| 4| return ++CurPtr, AsmToken(AsmToken::PipePipe, StringRef(TokStart, 2)); 581| 17| return AsmToken(AsmToken::Pipe, StringRef(TokStart, 1)); 582| 368| case '^': return AsmToken(AsmToken::Caret, StringRef(TokStart, 1)); ------------------ | Branch (582:3): [True: 368, False: 259k] ------------------ 583| 522| case '&': ------------------ | Branch (583:3): [True: 522, False: 259k] ------------------ 584| 522| if (*CurPtr == '&') ------------------ | Branch (584:9): [True: 2, False: 520] ------------------ 585| 2| return ++CurPtr, AsmToken(AsmToken::AmpAmp, StringRef(TokStart, 2)); 586| 520| return AsmToken(AsmToken::Amp, StringRef(TokStart, 1)); 587| 2.59k| case '!': ------------------ | Branch (587:3): [True: 2.59k, False: 257k] ------------------ 588| 2.59k| if (*CurPtr == '=') ------------------ | Branch (588:9): [True: 57, False: 2.53k] ------------------ 589| 57| return ++CurPtr, AsmToken(AsmToken::ExclaimEqual, StringRef(TokStart, 2)); 590| 2.53k| return AsmToken(AsmToken::Exclaim, StringRef(TokStart, 1)); 591| 1.21k| case '%': return AsmToken(AsmToken::Percent, StringRef(TokStart, 1)); ------------------ | Branch (591:3): [True: 1.21k, False: 259k] ------------------ 592| 166| case '/': return LexSlash(); ------------------ | Branch (592:3): [True: 166, False: 260k] ------------------ 593| 3.40k| case '#': return AsmToken(AsmToken::Hash, StringRef(TokStart, 1)); ------------------ | Branch (593:3): [True: 3.40k, False: 256k] ------------------ 594| 539| case '\'': return LexSingleQuote(); ------------------ | Branch (594:3): [True: 539, False: 259k] ------------------ 595| 2.46k| case '"': return LexQuote(); ------------------ | Branch (595:3): [True: 2.46k, False: 257k] ------------------ 596| 9.66k| case '0': case '1': case '2': case '3': case '4': ------------------ | Branch (596:3): [True: 3.63k, False: 256k] | Branch (596:13): [True: 2.28k, False: 258k] | Branch (596:23): [True: 1.76k, False: 258k] | Branch (596:33): [True: 934, False: 259k] | Branch (596:43): [True: 1.05k, False: 259k] ------------------ 597| 13.1k| case '5': case '6': case '7': case '8': case '9': ------------------ | Branch (597:3): [True: 464, False: 259k] | Branch (597:13): [True: 1.70k, False: 258k] | Branch (597:23): [True: 270, False: 260k] | Branch (597:33): [True: 440, False: 259k] | Branch (597:43): [True: 572, False: 259k] ------------------ 598| 13.1k| return LexDigit(); 599| 217| case '<': ------------------ | Branch (599:3): [True: 217, False: 260k] ------------------ 600| 217| switch (*CurPtr) { 601| 9| case '<': return ++CurPtr, AsmToken(AsmToken::LessLess, ------------------ | Branch (601:5): [True: 9, False: 208] ------------------ 602| 9| StringRef(TokStart, 2)); 603| 0| case '=': return ++CurPtr, AsmToken(AsmToken::LessEqual, ------------------ | Branch (603:5): [True: 0, False: 217] ------------------ 604| 0| StringRef(TokStart, 2)); 605| 18| case '>': return ++CurPtr, AsmToken(AsmToken::LessGreater, ------------------ | Branch (605:5): [True: 18, False: 199] ------------------ 606| 18| StringRef(TokStart, 2)); 607| 190| default: return AsmToken(AsmToken::Less, StringRef(TokStart, 1)); ------------------ | Branch (607:5): [True: 190, False: 27] ------------------ 608| 217| } 609| 227| case '>': ------------------ | Branch (609:3): [True: 227, False: 260k] ------------------ 610| 227| switch (*CurPtr) { 611| 0| case '>': return ++CurPtr, AsmToken(AsmToken::GreaterGreater, ------------------ | Branch (611:5): [True: 0, False: 227] ------------------ 612| 0| StringRef(TokStart, 2)); 613| 5| case '=': return ++CurPtr, AsmToken(AsmToken::GreaterEqual, ------------------ | Branch (613:5): [True: 5, False: 222] ------------------ 614| 5| StringRef(TokStart, 2)); 615| 222| default: return AsmToken(AsmToken::Greater, StringRef(TokStart, 1)); ------------------ | Branch (615:5): [True: 222, False: 5] ------------------ 616| 227| } 617| | 618| | // TODO: Quoted identifiers (objc methods etc) 619| | // local labels: [0-9][:] 620| | // Forward/backward labels: [0-9][fb] 621| | // Integers, fp constants, character constants. 622| 260k| } 623| 260k|} AsmLexer.cpp:_ZL16IsIdentifierCharcb: 145| 408k|static bool IsIdentifierChar(char c, bool AllowAt) { 146| 408k| return isalnum(c) || c == '_' || c == '$' || c == '.' || ------------------ | Branch (146:10): [True: 328k, False: 80.3k] | Branch (146:24): [True: 2.77k, False: 77.5k] | Branch (146:36): [True: 1.02k, False: 76.5k] | Branch (146:48): [True: 12.5k, False: 63.9k] ------------------ 147| 63.9k| (c == '@' && AllowAt) || c == '?'; ------------------ | Branch (147:11): [True: 544, False: 63.4k] | Branch (147:23): [True: 0, False: 544] | Branch (147:35): [True: 57, False: 63.9k] ------------------ 148| 408k|} AsmLexer.cpp:_ZL11doLookAheadRPKcj: 223| 11.7k|static unsigned doLookAhead(const char *&CurPtr, unsigned DefaultRadix) { 224| 11.7k| const char *FirstHex = nullptr; 225| 11.7k| const char *LookAhead = CurPtr; 226| 61.1k| while (1) { ------------------ | Branch (226:10): [True: 61.1k, Folded] ------------------ 227| 61.1k| if (isdigit(*LookAhead)) { ------------------ | Branch (227:9): [True: 49.0k, False: 12.0k] ------------------ 228| 49.0k| ++LookAhead; 229| 49.0k| } else if (isxdigit(*LookAhead)) { ------------------ | Branch (229:16): [True: 362, False: 11.7k] ------------------ 230| 362| if (!FirstHex) ------------------ | Branch (230:11): [True: 294, False: 68] ------------------ 231| 294| FirstHex = LookAhead; 232| 362| ++LookAhead; 233| 11.7k| } else { 234| 11.7k| break; 235| 11.7k| } 236| 61.1k| } 237| 11.7k| bool isHex = *LookAhead == 'h' || *LookAhead == 'H'; ------------------ | Branch (237:16): [True: 1, False: 11.7k] | Branch (237:37): [True: 1, False: 11.7k] ------------------ 238| 11.7k| CurPtr = isHex || !FirstHex ? LookAhead : FirstHex; ------------------ | Branch (238:12): [True: 2, False: 11.7k] | Branch (238:21): [True: 11.4k, False: 294] ------------------ 239| 11.7k| if (isHex) ------------------ | Branch (239:7): [True: 2, False: 11.7k] ------------------ 240| 2| return 16; 241| 11.7k| return DefaultRadix; 242| 11.7k|} AsmLexer.cpp:_ZL24SkipIgnoredIntegerSuffixRPKc: 211| 11.9k|static void SkipIgnoredIntegerSuffix(const char *&CurPtr) { 212| | // Skip ULL, UL, U, L and LL suffices. 213| 11.9k| if (CurPtr[0] == 'U') ------------------ | Branch (213:7): [True: 80, False: 11.9k] ------------------ 214| 80| ++CurPtr; 215| 11.9k| if (CurPtr[0] == 'L') ------------------ | Branch (215:7): [True: 3, False: 11.9k] ------------------ 216| 3| ++CurPtr; 217| 11.9k| if (CurPtr[0] == 'L') ------------------ | Branch (217:7): [True: 0, False: 11.9k] ------------------ 218| 0| ++CurPtr; 219| 11.9k|} AsmLexer.cpp:_ZL8intTokenN7llvm_ks9StringRefERNS_5APIntE: 245| 11.9k|{ 246| 11.9k| if (Value.isIntN(64)) ------------------ | Branch (246:7): [True: 11.7k, False: 237] ------------------ 247| 11.7k| return AsmToken(AsmToken::Integer, Ref, Value); 248| 237| return AsmToken(AsmToken::BigNum, Ref, Value); 249| 11.9k|} _ZN7llvm_ks13MCParserUtils25parseAssignmentExpressionENS_9StringRefEbRNS_11MCAsmParserERPNS_8MCSymbolERPKNS_6MCExprE: 6074| 1.01k|{ 6075| 1.01k| MCAsmLexer &Lexer = Parser.getLexer(); 6076| | 6077| | // FIXME: Use better location, we should use proper tokens. 6078| | //SMLoc EqualLoc = Lexer.getLoc(); 6079| | 6080| 1.01k| if (Parser.parseExpression(Value)) { ------------------ | Branch (6080:7): [True: 129, False: 883] ------------------ 6081| | //Parser.TokError("missing expression"); 6082| 129| Parser.eatToEndOfStatement(); 6083| 129| return true; 6084| 129| } 6085| | 6086| | // Note: we don't count b as used in "a = b". This is to allow 6087| | // a = b 6088| | // b = c 6089| | 6090| 883| if (Lexer.isNot(AsmToken::EndOfStatement)) ------------------ | Branch (6090:7): [True: 240, False: 643] ------------------ 6091| | //return Parser.TokError("unexpected token in assignment"); 6092| 240| return true; 6093| | 6094| | // Eat the end of statement marker. 6095| 643| Parser.Lex(); 6096| | 6097| | // Validate that the LHS is allowed to be a variable (either it has not been 6098| | // used as a symbol, or it is an absolute symbol). 6099| 643| Sym = Parser.getContext().lookupSymbol(Name); 6100| 643| if (Sym) { ------------------ | Branch (6100:7): [True: 311, False: 332] ------------------ 6101| | // Diagnose assignment to a label. 6102| | // 6103| | // FIXME: Diagnostics. Note the location of the definition as a label. 6104| | // FIXME: Diagnose assignment to protected identifier (e.g., register name). 6105| 311| if (isSymbolUsedInExpression(Sym, Value)) ------------------ | Branch (6105:9): [True: 0, False: 311] ------------------ 6106| | //return Parser.Error(EqualLoc, "Recursive use of '" + Name + "'"); 6107| 0| return true; 6108| 311| else if (Sym->isUndefined(/*SetUsed*/ false) && !Sym->isUsed() && ------------------ | Branch (6108:14): [True: 43, False: 268] | Branch (6108:53): [True: 43, False: 0] ------------------ 6109| 43| !Sym->isVariable()) ------------------ | Branch (6109:14): [True: 2, False: 41] ------------------ 6110| 2| ; // Allow redefinitions of undefined symbols only used in directives. 6111| 309| else if (Sym->isVariable() && !Sym->isUsed() && allow_redef) ------------------ | Branch (6111:14): [True: 54, False: 255] | Branch (6111:35): [True: 43, False: 11] | Branch (6111:53): [True: 43, False: 0] ------------------ 6112| 43| ; // Allow redefinitions of variables that haven't yet been used. 6113| 266| else if (!Sym->isUndefined() && (!Sym->isVariable() || !allow_redef)) ------------------ | Branch (6113:14): [True: 266, False: 0] | Branch (6113:38): [True: 255, False: 11] | Branch (6113:60): [True: 0, False: 11] ------------------ 6114| | //return Parser.Error(EqualLoc, "redefinition of '" + Name + "'"); 6115| 255| return true; 6116| 11| else if (!Sym->isVariable()) ------------------ | Branch (6116:14): [True: 0, False: 11] ------------------ 6117| | //return Parser.Error(EqualLoc, "invalid assignment to '" + Name + "'"); 6118| 0| return true; 6119| 11| else if (!isa(Sym->getVariableValue())) ------------------ | Branch (6119:14): [True: 11, False: 0] ------------------ 6120| | //return Parser.Error(EqualLoc, 6121| | // "invalid reassignment of non-absolute variable '" + 6122| | // Name + "'"); 6123| 11| return true; 6124| 332| } else if (Name == ".") { ------------------ | Branch (6124:14): [True: 174, False: 158] ------------------ 6125| 174| Parser.getStreamer().emitValueToOffset(Value, 0); 6126| 174| return false; 6127| 174| } else { 6128| 158| if (Name.empty()) { ------------------ | Branch (6128:9): [True: 0, False: 158] ------------------ 6129| 0| return true; 6130| 0| } 6131| 158| Sym = Parser.getContext().getOrCreateSymbol(Name); 6132| 158| } 6133| | 6134| 203| Sym->setRedefinable(allow_redef); 6135| | 6136| 203| return false; 6137| 643|} _ZN7llvm_ks17createMCAsmParserERNS_9SourceMgrERNS_9MCContextERNS_10MCStreamerERKNS_9MCAsmInfoE: 6144| 430| MCStreamer &Out, const MCAsmInfo &MAI) { 6145| 430| return new AsmParser(SM, C, Out, MAI); 6146| 430|} AsmParser.cpp:_ZN7llvm_ks13MCParserUtilsL24isSymbolUsedInExpressionEPKNS_8MCSymbolEPKNS_6MCExprE: 6046| 330|static bool isSymbolUsedInExpression(const MCSymbol *Sym, const MCExpr *Value) { 6047| 330| switch (Value->getKind()) { ------------------ | Branch (6047:11): [True: 330, False: 0] ------------------ 6048| 0| case MCExpr::Binary: { ------------------ | Branch (6048:3): [True: 0, False: 330] ------------------ 6049| 0| const MCBinaryExpr *BE = static_cast(Value); 6050| 0| return isSymbolUsedInExpression(Sym, BE->getLHS()) || ------------------ | Branch (6050:12): [True: 0, False: 0] ------------------ 6051| 0| isSymbolUsedInExpression(Sym, BE->getRHS()); ------------------ | Branch (6051:12): [True: 0, False: 0] ------------------ 6052| 0| } 6053| 0| case MCExpr::Target: ------------------ | Branch (6053:3): [True: 0, False: 330] ------------------ 6054| 3| case MCExpr::Constant: ------------------ | Branch (6054:3): [True: 3, False: 327] ------------------ 6055| 3| return false; 6056| 308| case MCExpr::SymbolRef: { ------------------ | Branch (6056:3): [True: 308, False: 22] ------------------ 6057| 308| const MCSymbol &S = 6058| 308| static_cast(Value)->getSymbol(); 6059| 308| if (S.isVariable()) ------------------ | Branch (6059:9): [True: 0, False: 308] ------------------ 6060| 0| return isSymbolUsedInExpression(Sym, S.getVariableValue()); 6061| 308| return &S == Sym; 6062| 308| } 6063| 19| case MCExpr::Unary: ------------------ | Branch (6063:3): [True: 19, False: 311] ------------------ 6064| 19| return isSymbolUsedInExpression( 6065| 19| Sym, static_cast(Value)->getSubExpr()); 6066| 330| } 6067| | 6068| 0| llvm_unreachable("Unknown expr kind!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 6069| 330|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParserC2ERN7llvm_ks9SourceMgrERNS1_9MCContextERNS1_10MCStreamerERKNS1_9MCAsmInfoE: 545| 430| : Lexer(MAI), Ctx(Ctx), Out(Out), MAI(MAI), SrcMgr(SM), 546| 430| PlatformParser(nullptr), CurBuffer(SM.getMainFileID()), 547| 430| MacrosEnabledFlag(true), HadError(false), CppHashLineNumber(0), 548| 430| AssemblerDialect(~0U), IsDarwin(false), ParsingInlineAsm(false), 549| 430| NasmDefaultRel(false) { 550| | // Save the old handler. 551| 430| SavedDiagHandler = SrcMgr.getDiagHandler(); 552| 430| SavedDiagContext = SrcMgr.getDiagContext(); 553| | // Set our own handler which calls the saved handler. 554| 430| SrcMgr.setDiagHandler(DiagHandler, this); 555| 430| Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer()); 556| | 557| | // Initialize the platform / file format parser. 558| 430| PlatformParser.reset(createDarwinAsmParser()); 559| 430| IsDarwin = true; 560| |#if 0 561| | switch (Ctx.getObjectFileInfo()->getObjectFileType()) { 562| | case MCObjectFileInfo::IsCOFF: 563| | PlatformParser.reset(createCOFFAsmParser()); 564| | break; 565| | case MCObjectFileInfo::IsMachO: 566| | PlatformParser.reset(createDarwinAsmParser()); 567| | IsDarwin = true; 568| | break; 569| | case MCObjectFileInfo::IsELF: 570| | PlatformParser.reset(createELFAsmParser()); 571| | break; 572| | } 573| |#endif 574| | 575| 430| PlatformParser->Initialize(*this); 576| 430| initializeDirectiveKindMap(0); 577| | 578| 430| NumOfMacroInstantiations = 0; 579| 430|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser11DiagHandlerERKN7llvm_ks12SMDiagnosticEPv: 2025| 2.17k|void AsmParser::DiagHandler(const SMDiagnostic &Diag, void *Context) { 2026| 2.17k| const AsmParser *Parser = static_cast(Context); 2027| 2.17k| raw_ostream &OS = errs(); 2028| | 2029| 2.17k| const SourceMgr &DiagSrcMgr = *Diag.getSourceMgr(); 2030| 2.17k| SMLoc DiagLoc = Diag.getLoc(); 2031| 2.17k| unsigned DiagBuf = DiagSrcMgr.FindBufferContainingLoc(DiagLoc); 2032| 2.17k| unsigned CppHashBuf = 2033| 2.17k| Parser->SrcMgr.FindBufferContainingLoc(Parser->CppHashLoc); 2034| | 2035| | // Like SourceMgr::printMessage() we need to print the include stack if any 2036| | // before printing the message. 2037| 2.17k| unsigned DiagCurBuffer = DiagSrcMgr.FindBufferContainingLoc(DiagLoc); 2038| 2.17k| if (!Parser->SavedDiagHandler && DiagCurBuffer && ------------------ | Branch (2038:7): [True: 2.17k, False: 0] | Branch (2038:36): [True: 2.17k, False: 0] ------------------ 2039| 2.17k| DiagCurBuffer != DiagSrcMgr.getMainFileID()) { ------------------ | Branch (2039:7): [True: 99, False: 2.07k] ------------------ 2040| 99| SMLoc ParentIncludeLoc = DiagSrcMgr.getParentIncludeLoc(DiagCurBuffer); 2041| 99| DiagSrcMgr.PrintIncludeStack(ParentIncludeLoc, OS); 2042| 99| } 2043| | 2044| | // If we have not parsed a cpp hash line filename comment or the source 2045| | // manager changed or buffer changed (like in a nested include) then just 2046| | // print the normal diagnostic using its Filename and LineNo. 2047| 2.17k| if (!Parser->CppHashLineNumber || &DiagSrcMgr != &Parser->SrcMgr || ------------------ | Branch (2047:7): [True: 1.87k, False: 304] | Branch (2047:37): [True: 0, False: 304] ------------------ 2048| 1.87k| DiagBuf != CppHashBuf) { ------------------ | Branch (2048:7): [True: 0, False: 304] ------------------ 2049| 1.87k| if (Parser->SavedDiagHandler) ------------------ | Branch (2049:9): [True: 0, False: 1.87k] ------------------ 2050| 0| Parser->SavedDiagHandler(Diag, Parser->SavedDiagContext); 2051| 1.87k| else 2052| 1.87k| Diag.print(nullptr, OS); 2053| 1.87k| return; 2054| 1.87k| } 2055| | 2056| | // Use the CppHashFilename and calculate a line number based on the 2057| | // CppHashLoc and CppHashLineNumber relative to this Diag's SMLoc for 2058| | // the diagnostic. 2059| 304| const std::string &Filename = Parser->CppHashFilename; 2060| | 2061| 304| int DiagLocLineNo = DiagSrcMgr.FindLineNumber(DiagLoc, DiagBuf); 2062| 304| int CppHashLocLineNo = 2063| 304| Parser->SrcMgr.FindLineNumber(Parser->CppHashLoc, CppHashBuf); 2064| 304| int LineNo = 2065| 304| Parser->CppHashLineNumber - 1 + (DiagLocLineNo - CppHashLocLineNo); 2066| | 2067| 304| SMDiagnostic NewDiag(*Diag.getSourceMgr(), Diag.getLoc(), Filename, LineNo, 2068| 304| Diag.getColumnNo(), Diag.getKind(), Diag.getMessage(), 2069| 304| Diag.getLineContents(), Diag.getRanges()); 2070| | 2071| 304| if (Parser->SavedDiagHandler) ------------------ | Branch (2071:7): [True: 0, False: 304] ------------------ 2072| 0| Parser->SavedDiagHandler(NewDiag, Parser->SavedDiagContext); 2073| 304| else 2074| 304| NewDiag.print(nullptr, OS); 2075| 304|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParserD2Ev: 581| 430|AsmParser::~AsmParser() { 582| 430| assert((HadError || ActiveMacros.empty()) && ------------------ | Branch (582:3): [True: 5, False: 425] | Branch (582:3): [True: 425, False: 0] | Branch (582:3): [True: 430, Folded] | Branch (582:3): [True: 430, False: 0] ------------------ 583| 430| "Unexpected active macro instantiation!"); 584| | 585| | // Restore the saved diagnostics handler and context for use during 586| | // finalization 587| 430| SrcMgr.setDiagHandler(SavedDiagHandler, SavedDiagContext); 588| 430|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19addDirectiveHandlerEN7llvm_ks9StringRefENSt3__14pairIPNS1_20MCAsmParserExtensionEPFbS6_S2_NS1_5SMLocEEEE: 197| 28.3k| ExtensionDirectiveHandler Handler) override { 198| 28.3k| ExtensionDirectiveMap[Directive] = Handler; 199| 28.3k| } AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser8getLexerEv: 210| 394k| MCAsmLexer &getLexer() override { return Lexer; } AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser10getContextEv: 211| 73.7k| MCContext &getContext() override { return Ctx; } AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser11getStreamerEv: 212| 35.8k| MCStreamer &getStreamer() override { return Out; } AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19getAssemblerDialectEv: 213| 3.40k| unsigned getAssemblerDialect() override { 214| 3.40k| if (AssemblerDialect == ~0U) ------------------ | Branch (214:9): [True: 3.40k, False: 0] ------------------ 215| 3.40k| return MAI.getAssemblerDialect(); 216| 0| else 217| 0| return AssemblerDialect; 218| 3.40k| } AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser3RunEbmb: 675| 430|{ 676| | // count number of statement 677| 430| size_t count = 0; 678| | 679| | // Create the initial section, if requested. 680| 430| if (!NoInitialTextSection) ------------------ | Branch (680:7): [True: 430, False: 0] ------------------ 681| 430| Out.InitSections(false); 682| | 683| | // Prime the lexer. 684| 430| Lex(); 685| 430| if (!Lexer.isNot(AsmToken::Error)) { ------------------ | Branch (685:7): [True: 2, False: 428] ------------------ 686| 2| KsError = KS_ERR_ASM_TOKEN_INVALID; 687| 2| return 0; 688| 2| } 689| | 690| 428| HadError = false; 691| 428| AsmCond StartingCondState = TheCondState; 692| | 693| | // If we are generating dwarf for assembly source files save the initial text 694| | // section and generate a .file directive. 695| 428| if (getContext().getGenDwarfForAssembly()) { ------------------ | Branch (695:7): [True: 0, False: 428] ------------------ 696| 0| MCSection *Sec = getStreamer().getCurrentSection().first; 697| 0| if (!Sec->getBeginSymbol()) { ------------------ | Branch (697:9): [True: 0, False: 0] ------------------ 698| 0| MCSymbol *SectionStartSym = getContext().createTempSymbol(); 699| 0| getStreamer().EmitLabel(SectionStartSym); 700| 0| Sec->setBeginSymbol(SectionStartSym); 701| 0| } 702| 0| bool InsertResult = getContext().addGenDwarfSection(Sec); 703| 0| assert(InsertResult && ".text section should not have debug info yet"); ------------------ | Branch (703:5): [True: 0, False: 0] | Branch (703:5): [True: 0, Folded] | Branch (703:5): [True: 0, False: 0] ------------------ 704| 0| (void)InsertResult; 705| 0| getContext().setGenDwarfFileNumber(getStreamer().EmitDwarfFileDirective( 706| 0| 0, StringRef(), getContext().getMainFileName())); 707| 0| } 708| | 709| | // While we have input, parse each statement. 710| 43.2k| while (Lexer.isNot(AsmToken::Eof)) { ------------------ | Branch (710:10): [True: 43.0k, False: 214] ------------------ 711| 43.0k| ParseStatementInfo Info; 712| 43.0k| if (!parseStatement(Info, nullptr, Address)) { ------------------ | Branch (712:9): [True: 36.2k, False: 6.79k] ------------------ 713| 36.2k| count++; 714| 36.2k| continue; 715| 36.2k| } 716| | 717| | //printf(">> 222 error = %u\n", Info.KsError); 718| 6.79k| if (!KsError) { ------------------ | Branch (718:9): [True: 214, False: 6.58k] ------------------ 719| 214| KsError = Info.KsError; 720| 214| return 0; 721| 214| } 722| | 723| | // We had an error, validate that one was emitted and recover by skipping to 724| | // the next line. 725| | // assert(HadError && "Parse statement returned an error, but none emitted!"); 726| | 727| | //eatToEndOfStatement(); 728| 6.79k| } 729| | 730| 214| if (TheCondState.TheCond != StartingCondState.TheCond || ------------------ | Branch (730:7): [True: 29, False: 185] ------------------ 731| 185| TheCondState.Ignore != StartingCondState.Ignore) { ------------------ | Branch (731:7): [True: 0, False: 185] ------------------ 732| | //return TokError("unmatched .ifs or .elses"); 733| 29| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 734| 29| return 0; 735| 29| } 736| | 737| | // Check to see that all assembler local symbols were actually defined. 738| | // Targets that don't do subsections via symbols may not want this, though, 739| | // so conservatively exclude them. Only do this if we're finalizing, though, 740| | // as otherwise we won't necessarilly have seen everything yet. 741| 185| if (!NoFinalize && MAI.hasSubsectionsViaSymbols()) { ------------------ | Branch (741:7): [True: 185, False: 0] | Branch (741:22): [True: 0, False: 185] ------------------ 742| 0| for (const auto &TableEntry : getContext().getSymbols()) { ------------------ | Branch (742:33): [True: 0, False: 0] ------------------ 743| 0| MCSymbol *Sym = TableEntry.getValue(); 744| | // Variable symbols may not be marked as defined, so check those 745| | // explicitly. If we know it's a variable, we have a definition for 746| | // the purposes of this check. 747| 0| if (Sym->isTemporary() && !Sym->isVariable() && !Sym->isDefined()) { ------------------ | Branch (747:11): [True: 0, False: 0] | Branch (747:33): [True: 0, False: 0] | Branch (747:55): [True: 0, False: 0] ------------------ 748| | // FIXME: We would really like to refer back to where the symbol was 749| | // first referenced for a source location. We need to add something 750| | // to track that. Currently, we just point to the end of the file. 751| | //return Error(getLexer().getLoc(), "assembler local symbol '" + 752| | // Sym->getName() + "' not defined"); // qq: set KsError, then return 0 753| 0| KsError = KS_ERR_ASM_SYMBOL_MISSING; 754| 0| return 0; 755| 0| } 756| 0| } 757| 0| } 758| | 759| | // Finalize the output stream if there are no errors and if the client wants 760| | // us to. 761| 185| if (!KsError) { ------------------ | Branch (761:7): [True: 134, False: 51] ------------------ 762| 134| if (!HadError && !NoFinalize) ------------------ | Branch (762:11): [True: 134, False: 0] | Branch (762:24): [True: 134, False: 0] ------------------ 763| 134| KsError = Out.Finish(); 764| 134| } else 765| 51| Out.Finish(); 766| | 767| | //return HadError || getContext().hadError(); 768| 185| return count; 769| 185|} AsmParser.cpp:_ZN12_GLOBAL__N_118ParseStatementInfoC2Ev: 114| 43.0k| ParseStatementInfo() : KsError(0), Opcode(~0U), ParseError(false), AsmRewrites(nullptr) {} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser14parseStatementERNS_18ParseStatementInfoEPN7llvm_ks23MCAsmParserSemaCallbackERm: 1449| 43.0k|{ 1450| 43.0k| KsError = 0; 1451| 43.0k| if (Lexer.is(AsmToken::EndOfStatement)) { ------------------ | Branch (1451:7): [True: 17.9k, False: 25.0k] ------------------ 1452| 17.9k| Out.AddBlankLine(); 1453| 17.9k| Lex(); 1454| 17.9k| return false; 1455| 17.9k| } 1456| | 1457| | // Statements always start with an identifier or are a full line comment. 1458| 25.0k| AsmToken ID = getTok(); 1459| | //printf(">>> parseStatement:ID = %s\n", ID.getString().str().c_str()); 1460| 25.0k| SMLoc IDLoc = ID.getLoc(); 1461| 25.0k| StringRef IDVal; 1462| 25.0k| int64_t LocalLabelVal = -1; 1463| | // A full line comment is a '#' as the first token. 1464| 25.0k| if (Lexer.is(AsmToken::Hash)) ------------------ | Branch (1464:7): [True: 1.08k, False: 23.9k] ------------------ 1465| 1.08k| return parseCppHashLineFilenameComment(IDLoc); 1466| | 1467| | // Allow an integer followed by a ':' as a directional local label. 1468| 23.9k| if (Lexer.is(AsmToken::Integer)) { ------------------ | Branch (1468:7): [True: 283, False: 23.7k] ------------------ 1469| 283| bool valid; 1470| 283| LocalLabelVal = getTok().getIntVal(valid); 1471| 283| if (!valid) { ------------------ | Branch (1471:9): [True: 0, False: 283] ------------------ 1472| 0| return true; 1473| 0| } 1474| 283| if (LocalLabelVal < 0) { ------------------ | Branch (1474:9): [True: 0, False: 283] ------------------ 1475| 0| if (!TheCondState.Ignore) { ------------------ | Branch (1475:11): [True: 0, False: 0] ------------------ 1476| | // return TokError("unexpected token at start of statement"); 1477| 0| Info.KsError = KS_ERR_ASM_STAT_TOKEN; 1478| 0| return true; 1479| 0| } 1480| 0| IDVal = ""; 1481| 283| } else { 1482| 283| IDVal = getTok().getString(); 1483| 283| Lex(); // Consume the integer token to be used as an identifier token. 1484| 283| if (Lexer.getKind() != AsmToken::Colon) { ------------------ | Branch (1484:11): [True: 149, False: 134] ------------------ 1485| 149| if (!TheCondState.Ignore) { ------------------ | Branch (1485:13): [True: 15, False: 134] ------------------ 1486| | // return TokError("unexpected token at start of statement"); 1487| 15| Info.KsError = KS_ERR_ASM_STAT_TOKEN; 1488| 15| return true; 1489| 15| } 1490| 149| } 1491| 283| } 1492| 23.7k| } else if (Lexer.is(AsmToken::Dot)) { ------------------ | Branch (1492:14): [True: 308, False: 23.3k] ------------------ 1493| | // Treat '.' as a valid identifier in this context. 1494| 308| Lex(); 1495| 308| IDVal = "."; 1496| 23.3k| } else if (Lexer.is(AsmToken::LCurly)) { ------------------ | Branch (1496:14): [True: 76, False: 23.3k] ------------------ 1497| | // Treat '{' as a valid identifier in this context. 1498| 76| Lex(); 1499| 76| IDVal = "{"; 1500| 23.3k| } else if (Lexer.is(AsmToken::RCurly)) { ------------------ | Branch (1500:14): [True: 0, False: 23.3k] ------------------ 1501| | // Treat '}' as a valid identifier in this context. 1502| 0| Lex(); 1503| 0| IDVal = "}"; 1504| 23.3k| } else if (KsSyntax == KS_OPT_SYNTAX_NASM && Lexer.is(AsmToken::LBrac)) { ------------------ | Branch (1504:14): [True: 0, False: 23.3k] | Branch (1504:48): [True: 0, False: 0] ------------------ 1505| | // [bits xx] 1506| 0| Lex(); 1507| 0| ID = Lexer.getTok(); 1508| 0| if (ID.getString().lower() == "bits") { ------------------ | Branch (1508:9): [True: 0, False: 0] ------------------ 1509| 0| Lex(); 1510| 0| if (parseNasmDirectiveBits()) { ------------------ | Branch (1510:13): [True: 0, False: 0] ------------------ 1511| 0| Info.KsError = KS_ERR_ASM_DIRECTIVE_ID; 1512| 0| return true; 1513| 0| } else { 1514| 0| return false; 1515| 0| } 1516| 0| } else { 1517| 0| Info.KsError = KS_ERR_ASM_DIRECTIVE_ID; 1518| 0| return true; 1519| 0| } 1520| 23.3k| } else if (KsSyntax == KS_OPT_SYNTAX_NASM && isNasmDirective(ID.getString())) { ------------------ | Branch (1520:14): [True: 0, False: 23.3k] | Branch (1520:14): [True: 0, False: 23.3k] | Branch (1520:48): [True: 0, False: 0] ------------------ 1521| 0| Lex(); 1522| 0| IDVal = ID.getString(); 1523| 23.3k| } else if (parseIdentifier(IDVal)) { ------------------ | Branch (1523:14): [True: 554, False: 22.7k] ------------------ 1524| 554| if (!TheCondState.Ignore) { ------------------ | Branch (1524:9): [True: 6, False: 548] ------------------ 1525| | // return TokError("unexpected token at start of statement"); 1526| 6| Info.KsError = KS_ERR_ASM_STAT_TOKEN; 1527| 6| return true; 1528| 6| } 1529| 548| IDVal = ""; 1530| 548| } 1531| | 1532| | // Handle conditional assembly here before checking for skipping. We 1533| | // have to do this so that .endif isn't skipped in a ".if 0" block for 1534| | // example. 1535| | 1536| 23.9k| StringMap::const_iterator DirKindIt = 1537| 23.9k| DirectiveKindMap.find(IDVal.lower()); 1538| 23.9k| DirectiveKind DirKind = (DirKindIt == DirectiveKindMap.end()) ------------------ | Branch (1538:27): [True: 13.6k, False: 10.2k] ------------------ 1539| 23.9k| ? DK_NO_DIRECTIVE 1540| 23.9k| : DirKindIt->getValue(); 1541| 23.9k| switch (DirKind) { 1542| 20.0k| default: ------------------ | Branch (1542:3): [True: 20.0k, False: 3.91k] ------------------ 1543| 20.0k| break; 1544| 20.0k| case DK_IF: ------------------ | Branch (1544:3): [True: 574, False: 23.3k] ------------------ 1545| 705| case DK_IFEQ: ------------------ | Branch (1545:3): [True: 131, False: 23.8k] ------------------ 1546| 835| case DK_IFGE: ------------------ | Branch (1546:3): [True: 130, False: 23.8k] ------------------ 1547| 1.00k| case DK_IFGT: ------------------ | Branch (1547:3): [True: 172, False: 23.7k] ------------------ 1548| 1.14k| case DK_IFLE: ------------------ | Branch (1548:3): [True: 140, False: 23.8k] ------------------ 1549| 1.14k| case DK_IFLT: ------------------ | Branch (1549:3): [True: 0, False: 23.9k] ------------------ 1550| 1.15k| case DK_IFNE: ------------------ | Branch (1550:3): [True: 3, False: 23.9k] ------------------ 1551| 1.15k| return parseDirectiveIf(IDLoc, DirKind); 1552| 282| case DK_IFB: ------------------ | Branch (1552:3): [True: 282, False: 23.6k] ------------------ 1553| 282| return parseDirectiveIfb(IDLoc, true); 1554| 0| case DK_IFNB: ------------------ | Branch (1554:3): [True: 0, False: 23.9k] ------------------ 1555| 0| return parseDirectiveIfb(IDLoc, false); 1556| 346| case DK_IFC: ------------------ | Branch (1556:3): [True: 346, False: 23.6k] ------------------ 1557| 346| return parseDirectiveIfc(IDLoc, true); 1558| 0| case DK_IFEQS: ------------------ | Branch (1558:3): [True: 0, False: 23.9k] ------------------ 1559| 0| return parseDirectiveIfeqs(IDLoc, true); 1560| 0| case DK_IFNC: ------------------ | Branch (1560:3): [True: 0, False: 23.9k] ------------------ 1561| 0| return parseDirectiveIfc(IDLoc, false); 1562| 295| case DK_IFNES: ------------------ | Branch (1562:3): [True: 295, False: 23.6k] ------------------ 1563| 295| return parseDirectiveIfeqs(IDLoc, false); 1564| 222| case DK_IFDEF: ------------------ | Branch (1564:3): [True: 222, False: 23.7k] ------------------ 1565| 222| return parseDirectiveIfdef(IDLoc, true); 1566| 138| case DK_IFNDEF: ------------------ | Branch (1566:3): [True: 138, False: 23.8k] ------------------ 1567| 138| case DK_IFNOTDEF: ------------------ | Branch (1567:3): [True: 0, False: 23.9k] ------------------ 1568| 138| return parseDirectiveIfdef(IDLoc, false); 1569| 690| case DK_ELSEIF: ------------------ | Branch (1569:3): [True: 690, False: 23.2k] ------------------ 1570| 690| return parseDirectiveElseIf(IDLoc); 1571| 526| case DK_ELSE: ------------------ | Branch (1571:3): [True: 526, False: 23.4k] ------------------ 1572| 526| return parseDirectiveElse(IDLoc); 1573| 264| case DK_ENDIF: ------------------ | Branch (1573:3): [True: 264, False: 23.6k] ------------------ 1574| 264| return parseDirectiveEndIf(IDLoc); 1575| 23.9k| } 1576| | 1577| | // Ignore the statement if in the middle of inactive conditional 1578| | // (e.g. ".if 0"). 1579| 20.0k| if (TheCondState.Ignore) { ------------------ | Branch (1579:7): [True: 1.29k, False: 18.7k] ------------------ 1580| 1.29k| eatToEndOfStatement(); 1581| 1.29k| return false; 1582| 1.29k| } 1583| | 1584| | // FIXME: Recurse on local labels? 1585| | 1586| | // See what kind of statement we have. 1587| 18.7k| switch (Lexer.getKind()) { 1588| 16| case AsmToken::Colon: { ------------------ | Branch (1588:3): [True: 16, False: 18.7k] ------------------ 1589| 16| bool valid; 1590| 16| if (!getTargetParser().isLabel(ID, valid)) ------------------ | Branch (1590:9): [True: 0, False: 16] ------------------ 1591| 0| break; 1592| 16| if (!valid) { ------------------ | Branch (1592:9): [True: 0, False: 16] ------------------ 1593| 0| Info.KsError = KS_ERR_ASM_LABEL_INVALID; 1594| 0| return true; 1595| 0| } 1596| 16| checkForValidSection(); 1597| | 1598| | // identifier ':' -> Label. 1599| 16| Lex(); 1600| | 1601| | // Diagnose attempt to use '.' as a label. 1602| 16| if (IDVal == ".") { ------------------ | Branch (1602:9): [True: 0, False: 16] ------------------ 1603| | //return Error(IDLoc, "invalid use of pseudo-symbol '.' as a label"); 1604| 0| KsError = KS_ERR_ASM_INVALIDOPERAND; 1605| 0| return true; 1606| 0| } 1607| | 1608| | // Diagnose attempt to use a variable as a label. 1609| | // 1610| | // FIXME: Diagnostics. Note the location of the definition as a label. 1611| | // FIXME: This doesn't diagnose assignment to a symbol which has been 1612| | // implicitly marked as external. 1613| 16| MCSymbol *Sym; 1614| 16| if (LocalLabelVal == -1) { ------------------ | Branch (1614:9): [True: 16, False: 0] ------------------ 1615| 16| if (ParsingInlineAsm && SI) { ------------------ | Branch (1615:11): [True: 0, False: 16] | Branch (1615:31): [True: 0, False: 0] ------------------ 1616| 0| StringRef RewrittenLabel = 1617| 0| SI->LookupInlineAsmLabel(IDVal, getSourceManager(), IDLoc, true); 1618| 0| assert(RewrittenLabel.size() && ------------------ | Branch (1618:9): [True: 0, False: 0] | Branch (1618:9): [True: 0, Folded] | Branch (1618:9): [True: 0, False: 0] ------------------ 1619| 0| "We should have an internal name here."); 1620| 0| Info.AsmRewrites->emplace_back(AOK_Label, IDLoc, IDVal.size(), 1621| 0| RewrittenLabel); 1622| 0| IDVal = RewrittenLabel; 1623| 0| } 1624| 16| if (IDVal.empty()) { ------------------ | Branch (1624:11): [True: 0, False: 16] ------------------ 1625| 0| return true; 1626| 0| } 1627| 16| Sym = getContext().getOrCreateSymbol(IDVal); 1628| 16| } else { 1629| 0| bool valid; 1630| 0| Sym = Ctx.createDirectionalLocalSymbol(LocalLabelVal, valid); 1631| 0| if (!valid) { ------------------ | Branch (1631:11): [True: 0, False: 0] ------------------ 1632| 0| Info.KsError = KS_ERR_ASM_LABEL_INVALID; 1633| 0| return true; 1634| 0| } 1635| 0| } 1636| | 1637| 16| Sym->redefineIfPossible(); 1638| | 1639| 16| if (!Sym->isUndefined() || Sym->isVariable()) { ------------------ | Branch (1639:9): [True: 0, False: 16] | Branch (1639:32): [True: 0, False: 16] ------------------ 1640| | //return Error(IDLoc, "invalid symbol redefinition"); 1641| 0| Info.KsError = KS_ERR_ASM_SYMBOL_REDEFINED; 1642| 0| return true; 1643| 0| } 1644| | 1645| | // Emit the label. 1646| 16| if (!ParsingInlineAsm) ------------------ | Branch (1646:9): [True: 16, False: 0] ------------------ 1647| 16| Out.EmitLabel(Sym); 1648| | 1649| 16| getTargetParser().onLabelParsed(Sym); 1650| | 1651| | // Consume any end of statement token, if present, to avoid spurious 1652| | // AddBlankLine calls(). 1653| 16| if (Lexer.is(AsmToken::EndOfStatement)) { ------------------ | Branch (1653:9): [True: 0, False: 16] ------------------ 1654| 0| Lex(); 1655| 0| if (Lexer.is(AsmToken::Eof)) ------------------ | Branch (1655:11): [True: 0, False: 0] ------------------ 1656| 0| return false; 1657| 0| } 1658| | 1659| 16| return false; 1660| 16| } 1661| | 1662| 1.01k| case AsmToken::Equal: ------------------ | Branch (1662:3): [True: 1.01k, False: 17.7k] ------------------ 1663| 1.01k| if (!getTargetParser().equalIsAsmAssignment()) ------------------ | Branch (1663:9): [True: 0, False: 1.01k] ------------------ 1664| 0| break; 1665| | // identifier '=' ... -> assignment statement 1666| 1.01k| Lex(); 1667| | 1668| 1.01k| if (parseAssignment(IDVal, true)) { ------------------ | Branch (1668:9): [True: 635, False: 377] ------------------ 1669| 635| Info.KsError = KS_ERR_ASM_DIRECTIVE_EQU; 1670| 635| return true; 1671| 635| } 1672| 377| return false; 1673| | 1674| 17.7k| default: // Normal instruction or directive. ------------------ | Branch (1674:3): [True: 17.7k, False: 1.02k] ------------------ 1675| 17.7k| break; 1676| 18.7k| } 1677| | 1678| | // If macros are enabled, check to see if this is a macro instantiation. 1679| 17.7k| if (areMacrosEnabled()) ------------------ | Branch (1679:7): [True: 17.7k, False: 0] ------------------ 1680| 17.7k| if (const MCAsmMacro *M = lookupMacro(IDVal)) { ------------------ | Branch (1680:27): [True: 27, False: 17.6k] ------------------ 1681| 27| return handleMacroEntry(M, IDLoc); 1682| 27| } 1683| | 1684| | // Otherwise, we have a normal instruction or directive. 1685| 17.6k| if (isDirective(IDVal)) { ------------------ | Branch (1685:7): [True: 14.2k, False: 3.40k] ------------------ 1686| | // There are several entities interested in parsing directives: 1687| | // 1688| | // 1. The target-specific assembly parser. Some directives are target 1689| | // specific or may potentially behave differently on certain targets. 1690| | // 2. Asm parser extensions. For example, platform-specific parsers 1691| | // (like the ELF parser) register themselves as extensions. 1692| | // 3. The generic directive parser implemented by this class. These are 1693| | // all the directives that behave in a target and platform independent 1694| | // manner, or at least have a default behavior that's shared between 1695| | // all targets and platforms. 1696| | 1697| | // First query the target-specific parser. It will return 'true' if it 1698| | // isn't interested in this directive. 1699| 14.2k| uint64_t BytesInFragment = getStreamer().getCurrentFragmentSize(); 1700| 14.2k| if (!getTargetParser().ParseDirective(ID)){ ------------------ | Branch (1700:11): [True: 5.74k, False: 8.54k] ------------------ 1701| | // increment the address for the next statement if the directive 1702| | // has emitted any value to the streamer. 1703| 5.74k| Address += getStreamer().getCurrentFragmentSize() - BytesInFragment; 1704| 5.74k| return false; 1705| 5.74k| } 1706| | 1707| | // Next, check the extension directive map to see if any extension has 1708| | // registered itself to parse this directive. 1709| 8.54k| std::pair Handler = 1710| 8.54k| ExtensionDirectiveMap.lookup(IDVal); 1711| 8.54k| if (Handler.first) ------------------ | Branch (1711:9): [True: 847, False: 7.69k] ------------------ 1712| 847| return (*Handler.second)(Handler.first, IDVal, IDLoc); 1713| | 1714| | // Finally, if no one else is interested in this directive, it must be 1715| | // generic and familiar to this class. 1716| 7.69k| switch (DirKind) { 1717| 1.34k| default: ------------------ | Branch (1717:5): [True: 1.34k, False: 6.35k] ------------------ 1718| 1.34k| break; 1719| 1.34k| case DK_SET: ------------------ | Branch (1719:5): [True: 0, False: 7.69k] ------------------ 1720| 0| case DK_EQU: ------------------ | Branch (1720:5): [True: 0, False: 7.69k] ------------------ 1721| 0| return parseDirectiveSet(IDVal, true); 1722| 0| case DK_EQUIV: ------------------ | Branch (1722:5): [True: 0, False: 7.69k] ------------------ 1723| 0| return parseDirectiveSet(IDVal, false); 1724| 30| case DK_ASCII: ------------------ | Branch (1724:5): [True: 30, False: 7.66k] ------------------ 1725| 30| return parseDirectiveAscii(IDVal, false); 1726| 100| case DK_ASCIZ: ------------------ | Branch (1726:5): [True: 100, False: 7.59k] ------------------ 1727| 223| case DK_STRING: ------------------ | Branch (1727:5): [True: 123, False: 7.57k] ------------------ 1728| 223| return parseDirectiveAscii(IDVal, true); 1729| 131| case DK_BYTE: ------------------ | Branch (1729:5): [True: 131, False: 7.56k] ------------------ 1730| 131| return parseDirectiveValue(1, Info.KsError); 1731| 0| case DK_SHORT: ------------------ | Branch (1731:5): [True: 0, False: 7.69k] ------------------ 1732| 0| case DK_VALUE: ------------------ | Branch (1732:5): [True: 0, False: 7.69k] ------------------ 1733| 0| case DK_2BYTE: ------------------ | Branch (1733:5): [True: 0, False: 7.69k] ------------------ 1734| 0| return parseDirectiveValue(2, Info.KsError); 1735| 0| case DK_LONG: ------------------ | Branch (1735:5): [True: 0, False: 7.69k] ------------------ 1736| 4| case DK_INT: ------------------ | Branch (1736:5): [True: 4, False: 7.69k] ------------------ 1737| 4| case DK_4BYTE: ------------------ | Branch (1737:5): [True: 0, False: 7.69k] ------------------ 1738| 4| return parseDirectiveValue(4, Info.KsError); 1739| 0| case DK_QUAD: ------------------ | Branch (1739:5): [True: 0, False: 7.69k] ------------------ 1740| 143| case DK_8BYTE: ------------------ | Branch (1740:5): [True: 143, False: 7.55k] ------------------ 1741| 143| return parseDirectiveValue(8, Info.KsError); 1742| 2| case DK_OCTA: ------------------ | Branch (1742:5): [True: 2, False: 7.69k] ------------------ 1743| 2| return parseDirectiveOctaValue(Info.KsError); 1744| 0| case DK_SINGLE: ------------------ | Branch (1744:5): [True: 0, False: 7.69k] ------------------ 1745| 283| case DK_FLOAT: ------------------ | Branch (1745:5): [True: 283, False: 7.41k] ------------------ 1746| 283| return parseDirectiveRealValue(APFloat::IEEEsingle); 1747| 0| case DK_DOUBLE: ------------------ | Branch (1747:5): [True: 0, False: 7.69k] ------------------ 1748| 0| return parseDirectiveRealValue(APFloat::IEEEdouble); 1749| 131| case DK_ALIGN: { ------------------ | Branch (1749:5): [True: 131, False: 7.56k] ------------------ 1750| 131| bool IsPow2 = !getContext().getAsmInfo()->getAlignmentIsInBytes(); 1751| 131| return parseDirectiveAlign(IsPow2, /*ExprSize=*/1); 1752| 0| } 1753| 0| case DK_ALIGN32: { ------------------ | Branch (1753:5): [True: 0, False: 7.69k] ------------------ 1754| 0| bool IsPow2 = !getContext().getAsmInfo()->getAlignmentIsInBytes(); 1755| 0| return parseDirectiveAlign(IsPow2, /*ExprSize=*/4); 1756| 0| } 1757| 146| case DK_BALIGN: ------------------ | Branch (1757:5): [True: 146, False: 7.55k] ------------------ 1758| 146| return parseDirectiveAlign(/*IsPow2=*/false, /*ExprSize=*/1); 1759| 0| case DK_BALIGNW: ------------------ | Branch (1759:5): [True: 0, False: 7.69k] ------------------ 1760| 0| return parseDirectiveAlign(/*IsPow2=*/false, /*ExprSize=*/2); 1761| 0| case DK_BALIGNL: ------------------ | Branch (1761:5): [True: 0, False: 7.69k] ------------------ 1762| 0| return parseDirectiveAlign(/*IsPow2=*/false, /*ExprSize=*/4); 1763| 0| case DK_P2ALIGN: ------------------ | Branch (1763:5): [True: 0, False: 7.69k] ------------------ 1764| 0| return parseDirectiveAlign(/*IsPow2=*/true, /*ExprSize=*/1); 1765| 0| case DK_P2ALIGNW: ------------------ | Branch (1765:5): [True: 0, False: 7.69k] ------------------ 1766| 0| return parseDirectiveAlign(/*IsPow2=*/true, /*ExprSize=*/2); 1767| 0| case DK_P2ALIGNL: ------------------ | Branch (1767:5): [True: 0, False: 7.69k] ------------------ 1768| 0| return parseDirectiveAlign(/*IsPow2=*/true, /*ExprSize=*/4); 1769| 0| case DK_ORG: ------------------ | Branch (1769:5): [True: 0, False: 7.69k] ------------------ 1770| 0| return parseDirectiveOrg(); 1771| 426| case DK_FILL: ------------------ | Branch (1771:5): [True: 426, False: 7.27k] ------------------ 1772| 426| return parseDirectiveFill(); 1773| 153| case DK_ZERO: ------------------ | Branch (1773:5): [True: 153, False: 7.54k] ------------------ 1774| 153| return parseDirectiveZero(); 1775| 0| case DK_EXTERN: ------------------ | Branch (1775:5): [True: 0, False: 7.69k] ------------------ 1776| 0| eatToEndOfStatement(); // .extern is the default, ignore it. 1777| 0| return false; 1778| 0| case DK_GLOBL: ------------------ | Branch (1778:5): [True: 0, False: 7.69k] ------------------ 1779| 0| case DK_GLOBAL: ------------------ | Branch (1779:5): [True: 0, False: 7.69k] ------------------ 1780| 0| return parseDirectiveSymbolAttribute(MCSA_Global); 1781| 0| case DK_LAZY_REFERENCE: ------------------ | Branch (1781:5): [True: 0, False: 7.69k] ------------------ 1782| 0| return parseDirectiveSymbolAttribute(MCSA_LazyReference); 1783| 0| case DK_NO_DEAD_STRIP: ------------------ | Branch (1783:5): [True: 0, False: 7.69k] ------------------ 1784| 0| return parseDirectiveSymbolAttribute(MCSA_NoDeadStrip); 1785| 0| case DK_SYMBOL_RESOLVER: ------------------ | Branch (1785:5): [True: 0, False: 7.69k] ------------------ 1786| 0| return parseDirectiveSymbolAttribute(MCSA_SymbolResolver); 1787| 0| case DK_PRIVATE_EXTERN: ------------------ | Branch (1787:5): [True: 0, False: 7.69k] ------------------ 1788| 0| return parseDirectiveSymbolAttribute(MCSA_PrivateExtern); 1789| 0| case DK_REFERENCE: ------------------ | Branch (1789:5): [True: 0, False: 7.69k] ------------------ 1790| 0| return parseDirectiveSymbolAttribute(MCSA_Reference); 1791| 0| case DK_WEAK_DEFINITION: ------------------ | Branch (1791:5): [True: 0, False: 7.69k] ------------------ 1792| 0| return parseDirectiveSymbolAttribute(MCSA_WeakDefinition); 1793| 0| case DK_WEAK_REFERENCE: ------------------ | Branch (1793:5): [True: 0, False: 7.69k] ------------------ 1794| 0| return parseDirectiveSymbolAttribute(MCSA_WeakReference); 1795| 0| case DK_WEAK_DEF_CAN_BE_HIDDEN: ------------------ | Branch (1795:5): [True: 0, False: 7.69k] ------------------ 1796| 0| return parseDirectiveSymbolAttribute(MCSA_WeakDefAutoPrivate); 1797| 816| case DK_COMM: ------------------ | Branch (1797:5): [True: 816, False: 6.88k] ------------------ 1798| 816| case DK_COMMON: ------------------ | Branch (1798:5): [True: 0, False: 7.69k] ------------------ 1799| 816| return parseDirectiveComm(/*IsLocal=*/false); 1800| 0| case DK_LCOMM: ------------------ | Branch (1800:5): [True: 0, False: 7.69k] ------------------ 1801| 0| return parseDirectiveComm(/*IsLocal=*/true); 1802| 0| case DK_ABORT: ------------------ | Branch (1802:5): [True: 0, False: 7.69k] ------------------ 1803| 0| return parseDirectiveAbort(); 1804| 1| case DK_INCLUDE: ------------------ | Branch (1804:5): [True: 1, False: 7.69k] ------------------ 1805| 1| return parseDirectiveInclude(); 1806| 0| case DK_INCBIN: ------------------ | Branch (1806:5): [True: 0, False: 7.69k] ------------------ 1807| 0| return parseDirectiveIncbin(); 1808| 0| case DK_CODE16: ------------------ | Branch (1808:5): [True: 0, False: 7.69k] ------------------ 1809| 0| case DK_CODE16GCC: ------------------ | Branch (1809:5): [True: 0, False: 7.69k] ------------------ 1810| | // return TokError(Twine(IDVal) + " not supported yet"); 1811| 0| Info.KsError = KS_ERR_ASM_UNSUPPORTED; 1812| 0| return true; 1813| 793| case DK_REPT: ------------------ | Branch (1813:5): [True: 793, False: 6.90k] ------------------ 1814| 793| return parseDirectiveRept(IDLoc, IDVal); 1815| 556| case DK_IRP: ------------------ | Branch (1815:5): [True: 556, False: 7.14k] ------------------ 1816| 556| return parseDirectiveIrp(IDLoc); 1817| 11| case DK_IRPC: ------------------ | Branch (1817:5): [True: 11, False: 7.68k] ------------------ 1818| 11| return parseDirectiveIrpc(IDLoc); 1819| 919| case DK_ENDR: ------------------ | Branch (1819:5): [True: 919, False: 6.77k] ------------------ 1820| 919| return parseDirectiveEndr(IDLoc); 1821| 0| case DK_BUNDLE_ALIGN_MODE: ------------------ | Branch (1821:5): [True: 0, False: 7.69k] ------------------ 1822| 0| return parseDirectiveBundleAlignMode(); 1823| 0| case DK_BUNDLE_LOCK: ------------------ | Branch (1823:5): [True: 0, False: 7.69k] ------------------ 1824| 0| return parseDirectiveBundleLock(); 1825| 0| case DK_BUNDLE_UNLOCK: ------------------ | Branch (1825:5): [True: 0, False: 7.69k] ------------------ 1826| 0| return parseDirectiveBundleUnlock(); 1827| 0| case DK_SLEB128: ------------------ | Branch (1827:5): [True: 0, False: 7.69k] ------------------ 1828| 0| return parseDirectiveLEB128(true); 1829| 0| case DK_ULEB128: ------------------ | Branch (1829:5): [True: 0, False: 7.69k] ------------------ 1830| 0| return parseDirectiveLEB128(false); 1831| 151| case DK_SPACE: ------------------ | Branch (1831:5): [True: 151, False: 7.54k] ------------------ 1832| 629| case DK_SKIP: ------------------ | Branch (1832:5): [True: 478, False: 7.22k] ------------------ 1833| 629| return parseDirectiveSpace(IDVal); 1834| 681| case DK_FILE: ------------------ | Branch (1834:5): [True: 681, False: 7.01k] ------------------ 1835| 681| return parseDirectiveFile(IDLoc); 1836| 0| case DK_LINE: ------------------ | Branch (1836:5): [True: 0, False: 7.69k] ------------------ 1837| 0| return parseDirectiveLine(); 1838| 0| case DK_LOC: ------------------ | Branch (1838:5): [True: 0, False: 7.69k] ------------------ 1839| 0| return parseDirectiveLoc(); 1840| 0| case DK_STABS: ------------------ | Branch (1840:5): [True: 0, False: 7.69k] ------------------ 1841| 0| return parseDirectiveStabs(); 1842| 0| case DK_CV_FILE: ------------------ | Branch (1842:5): [True: 0, False: 7.69k] ------------------ 1843| 0| return parseDirectiveCVFile(); 1844| 0| case DK_CV_LOC: ------------------ | Branch (1844:5): [True: 0, False: 7.69k] ------------------ 1845| 0| return parseDirectiveCVLoc(); 1846| 0| case DK_CV_LINETABLE: ------------------ | Branch (1846:5): [True: 0, False: 7.69k] ------------------ 1847| 0| return parseDirectiveCVLinetable(); 1848| 0| case DK_CV_INLINE_LINETABLE: ------------------ | Branch (1848:5): [True: 0, False: 7.69k] ------------------ 1849| 0| return parseDirectiveCVInlineLinetable(); 1850| 0| case DK_CV_STRINGTABLE: ------------------ | Branch (1850:5): [True: 0, False: 7.69k] ------------------ 1851| 0| return parseDirectiveCVStringTable(); 1852| 0| case DK_CV_FILECHECKSUMS: ------------------ | Branch (1852:5): [True: 0, False: 7.69k] ------------------ 1853| 0| return parseDirectiveCVFileChecksums(); 1854| 0| case DK_CFI_SECTIONS: ------------------ | Branch (1854:5): [True: 0, False: 7.69k] ------------------ 1855| 0| return parseDirectiveCFISections(); 1856| 0| case DK_CFI_STARTPROC: ------------------ | Branch (1856:5): [True: 0, False: 7.69k] ------------------ 1857| 0| return parseDirectiveCFIStartProc(); 1858| 0| case DK_CFI_ENDPROC: ------------------ | Branch (1858:5): [True: 0, False: 7.69k] ------------------ 1859| 0| return parseDirectiveCFIEndProc(); 1860| 0| case DK_CFI_DEF_CFA: ------------------ | Branch (1860:5): [True: 0, False: 7.69k] ------------------ 1861| 0| return parseDirectiveCFIDefCfa(IDLoc); 1862| 0| case DK_CFI_DEF_CFA_OFFSET: ------------------ | Branch (1862:5): [True: 0, False: 7.69k] ------------------ 1863| 0| return parseDirectiveCFIDefCfaOffset(); 1864| 0| case DK_CFI_ADJUST_CFA_OFFSET: ------------------ | Branch (1864:5): [True: 0, False: 7.69k] ------------------ 1865| 0| return parseDirectiveCFIAdjustCfaOffset(); 1866| 0| case DK_CFI_DEF_CFA_REGISTER: ------------------ | Branch (1866:5): [True: 0, False: 7.69k] ------------------ 1867| 0| return parseDirectiveCFIDefCfaRegister(IDLoc); 1868| 0| case DK_CFI_OFFSET: ------------------ | Branch (1868:5): [True: 0, False: 7.69k] ------------------ 1869| 0| return parseDirectiveCFIOffset(IDLoc); 1870| 0| case DK_CFI_REL_OFFSET: ------------------ | Branch (1870:5): [True: 0, False: 7.69k] ------------------ 1871| 0| return parseDirectiveCFIRelOffset(IDLoc); 1872| 0| case DK_CFI_PERSONALITY: ------------------ | Branch (1872:5): [True: 0, False: 7.69k] ------------------ 1873| 0| return parseDirectiveCFIPersonalityOrLsda(true); 1874| 0| case DK_CFI_LSDA: ------------------ | Branch (1874:5): [True: 0, False: 7.69k] ------------------ 1875| 0| return parseDirectiveCFIPersonalityOrLsda(false); 1876| 0| case DK_CFI_REMEMBER_STATE: ------------------ | Branch (1876:5): [True: 0, False: 7.69k] ------------------ 1877| 0| return parseDirectiveCFIRememberState(); 1878| 0| case DK_CFI_RESTORE_STATE: ------------------ | Branch (1878:5): [True: 0, False: 7.69k] ------------------ 1879| 0| return parseDirectiveCFIRestoreState(); 1880| 0| case DK_CFI_SAME_VALUE: ------------------ | Branch (1880:5): [True: 0, False: 7.69k] ------------------ 1881| 0| return parseDirectiveCFISameValue(IDLoc); 1882| 0| case DK_CFI_RESTORE: ------------------ | Branch (1882:5): [True: 0, False: 7.69k] ------------------ 1883| 0| return parseDirectiveCFIRestore(IDLoc); 1884| 0| case DK_CFI_ESCAPE: ------------------ | Branch (1884:5): [True: 0, False: 7.69k] ------------------ 1885| 0| return parseDirectiveCFIEscape(); 1886| 0| case DK_CFI_SIGNAL_FRAME: ------------------ | Branch (1886:5): [True: 0, False: 7.69k] ------------------ 1887| 0| return parseDirectiveCFISignalFrame(); 1888| 0| case DK_CFI_UNDEFINED: ------------------ | Branch (1888:5): [True: 0, False: 7.69k] ------------------ 1889| 0| return parseDirectiveCFIUndefined(IDLoc); 1890| 0| case DK_CFI_REGISTER: ------------------ | Branch (1890:5): [True: 0, False: 7.69k] ------------------ 1891| 0| return parseDirectiveCFIRegister(IDLoc); 1892| 0| case DK_CFI_WINDOW_SAVE: ------------------ | Branch (1892:5): [True: 0, False: 7.69k] ------------------ 1893| 0| return parseDirectiveCFIWindowSave(); 1894| 0| case DK_MACROS_ON: ------------------ | Branch (1894:5): [True: 0, False: 7.69k] ------------------ 1895| 0| case DK_MACROS_OFF: ------------------ | Branch (1895:5): [True: 0, False: 7.69k] ------------------ 1896| 0| return parseDirectiveMacrosOnOff(IDVal); 1897| 217| case DK_MACRO: ------------------ | Branch (1897:5): [True: 217, False: 7.48k] ------------------ 1898| 217| return parseDirectiveMacro(IDLoc); 1899| 0| case DK_EXITM: ------------------ | Branch (1899:5): [True: 0, False: 7.69k] ------------------ 1900| 0| return parseDirectiveExitMacro(IDVal); 1901| 12| case DK_ENDM: ------------------ | Branch (1901:5): [True: 12, False: 7.68k] ------------------ 1902| 32| case DK_ENDMACRO: ------------------ | Branch (1902:5): [True: 20, False: 7.67k] ------------------ 1903| 32| return parseDirectiveEndMacro(IDVal); 1904| 0| case DK_PURGEM: ------------------ | Branch (1904:5): [True: 0, False: 7.69k] ------------------ 1905| 0| return parseDirectivePurgeMacro(IDLoc); 1906| 0| case DK_END: ------------------ | Branch (1906:5): [True: 0, False: 7.69k] ------------------ 1907| 0| return parseDirectiveEnd(IDLoc); 1908| 6| case DK_ERR: ------------------ | Branch (1908:5): [True: 6, False: 7.69k] ------------------ 1909| 6| return parseDirectiveError(IDLoc, false); 1910| 20| case DK_ERROR: ------------------ | Branch (1910:5): [True: 20, False: 7.67k] ------------------ 1911| 20| return parseDirectiveError(IDLoc, true); 1912| 0| case DK_WARNING: ------------------ | Branch (1912:5): [True: 0, False: 7.69k] ------------------ 1913| 0| return parseDirectiveWarning(IDLoc); 1914| 1| case DK_RELOC: ------------------ | Branch (1914:5): [True: 1, False: 7.69k] ------------------ 1915| 1| return parseDirectiveReloc(IDLoc); 1916| 0| case DK_NASM_BITS: ------------------ | Branch (1916:5): [True: 0, False: 7.69k] ------------------ 1917| 0| if (parseNasmDirectiveBits()) { ------------------ | Branch (1917:11): [True: 0, False: 0] ------------------ 1918| 0| Info.KsError = KS_ERR_ASM_DIRECTIVE_ID; 1919| 0| return true; 1920| 0| } else { 1921| 0| return false; 1922| 0| } 1923| 0| case DK_NASM_USE32: ------------------ | Branch (1923:5): [True: 0, False: 7.69k] ------------------ 1924| 0| return parseNasmDirectiveUse32(); 1925| 0| case DK_NASM_DEFAULT: ------------------ | Branch (1925:5): [True: 0, False: 7.69k] ------------------ 1926| 0| if (parseNasmDirectiveDefault()) { ------------------ | Branch (1926:11): [True: 0, False: 0] ------------------ 1927| 0| Info.KsError = KS_ERR_ASM_DIRECTIVE_ID; 1928| 0| return true; 1929| 0| } else { 1930| 0| return false; 1931| 0| } 1932| 7.69k| } 1933| | 1934| | //return Error(IDLoc, "unknown directive"); 1935| 1.34k| KsError = KS_ERR_ASM_DIRECTIVE_UNKNOWN; 1936| 1.34k| return true; 1937| 7.69k| } 1938| | 1939| | // __asm _emit or __asm __emit 1940| 3.40k| if (ParsingInlineAsm && (IDVal == "_emit" || IDVal == "__emit" || ------------------ | Branch (1940:7): [True: 0, False: 3.40k] | Branch (1940:7): [True: 0, False: 3.40k] | Branch (1940:28): [True: 0, False: 0] | Branch (1940:48): [True: 0, False: 0] ------------------ 1941| 0| IDVal == "_EMIT" || IDVal == "__EMIT")) ------------------ | Branch (1941:28): [True: 0, False: 0] | Branch (1941:48): [True: 0, False: 0] ------------------ 1942| 0| return parseDirectiveMSEmit(IDLoc, Info, IDVal.size()); 1943| | 1944| | // __asm align 1945| 3.40k| if (ParsingInlineAsm && (IDVal == "align" || IDVal == "ALIGN")) ------------------ | Branch (1945:7): [True: 0, False: 3.40k] | Branch (1945:7): [True: 0, False: 3.40k] | Branch (1945:28): [True: 0, False: 0] | Branch (1945:48): [True: 0, False: 0] ------------------ 1946| 0| return parseDirectiveMSAlign(IDLoc, Info); 1947| | 1948| 3.40k| if (ParsingInlineAsm && (IDVal == "even")) ------------------ | Branch (1948:7): [True: 0, False: 3.40k] | Branch (1948:7): [True: 0, False: 3.40k] | Branch (1948:27): [True: 0, False: 0] ------------------ 1949| 0| Info.AsmRewrites->emplace_back(AOK_EVEN, IDLoc, 4); 1950| 3.40k| checkForValidSection(); 1951| | 1952| | // Canonicalize the opcode to lower case. 1953| 3.40k| std::string OpcodeStr = IDVal.lower(); 1954| 3.40k| ParseInstructionInfo IInfo(Info.AsmRewrites); 1955| | //printf(">> Going to ParseInstruction()\n"); 1956| 3.40k| bool HadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID, 1957| 3.40k| Info.ParsedOperands, Info.KsError); 1958| 3.40k| Info.ParseError = HadError; 1959| | 1960| | // If parsing succeeded, match the instruction. 1961| 3.40k| if (!HadError) { ------------------ | Branch (1961:7): [True: 2.34k, False: 1.06k] ------------------ 1962| 2.34k| uint64_t ErrorInfo; 1963| | //printf(">> Going to MatchAndEmitInstruction()\n"); 1964| 2.34k| return getTargetParser().MatchAndEmitInstruction(IDLoc, Info.Opcode, 1965| 2.34k| Info.ParsedOperands, Out, 1966| 2.34k| ErrorInfo, ParsingInlineAsm, 1967| 2.34k| Info.KsError, Address); 1968| 2.34k| } 1969| | 1970| 1.06k| return true; 1971| 3.40k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser31parseCppHashLineFilenameCommentEN7llvm_ks5SMLocE: 1986| 1.08k|bool AsmParser::parseCppHashLineFilenameComment(SMLoc L) { 1987| 1.08k| Lex(); // Eat the hash token. 1988| | 1989| 1.08k| if (getLexer().isNot(AsmToken::Integer)) { ------------------ | Branch (1989:7): [True: 1.06k, False: 25] ------------------ 1990| | // Consume the line since in cases it is not a well-formed line directive, 1991| | // as if were simply a full line comment. 1992| 1.06k| eatToEndOfLine(); 1993| 1.06k| return false; 1994| 1.06k| } 1995| | 1996| 25| bool valid; 1997| 25| int64_t LineNumber = getTok().getIntVal(valid); 1998| 25| if (!valid) { ------------------ | Branch (1998:7): [True: 0, False: 25] ------------------ 1999| 0| return true; 2000| 0| } 2001| 25| Lex(); 2002| | 2003| 25| if (getLexer().isNot(AsmToken::String)) { ------------------ | Branch (2003:7): [True: 19, False: 6] ------------------ 2004| 19| eatToEndOfLine(); 2005| 19| return false; 2006| 19| } 2007| | 2008| 6| StringRef Filename = getTok().getString(); 2009| | // Get rid of the enclosing quotes. 2010| 6| Filename = Filename.substr(1, Filename.size() - 2); 2011| | 2012| | // Save the SMLoc, Filename and LineNumber for later use by diagnostics. 2013| 6| CppHashLoc = L; 2014| 6| CppHashFilename = Filename; 2015| 6| CppHashLineNumber = LineNumber; 2016| 6| CppHashBuf = CurBuffer; 2017| | 2018| | // Ignore any trailing characters, they're just comment. 2019| 6| eatToEndOfLine(); 2020| 6| return false; 2021| 25|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser14eatToEndOfLineEv: 1976| 1.08k|{ 1977| 1.08k| if (!Lexer.is(AsmToken::EndOfStatement)) ------------------ | Branch (1977:7): [True: 956, False: 131] ------------------ 1978| 956| Lexer.LexUntilEndOfLine(); 1979| | // Eat EOL. 1980| 1.08k| Lex(); 1981| 1.08k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser16parseDirectiveIfEN7llvm_ks5SMLocENS0_13DirectiveKindE: 4909| 1.15k|{ 4910| 1.15k| TheCondStack.push_back(TheCondState); 4911| 1.15k| TheCondState.TheCond = AsmCond::IfCond; 4912| 1.15k| if (TheCondState.Ignore) { ------------------ | Branch (4912:7): [True: 271, False: 879] ------------------ 4913| 271| eatToEndOfStatement(); 4914| 879| } else { 4915| 879| int64_t ExprValue; 4916| 879| if (parseAbsoluteExpression(ExprValue)) { ------------------ | Branch (4916:9): [True: 4, False: 875] ------------------ 4917| 4| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4918| 4| return true; 4919| 4| } 4920| | 4921| 875| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (4921:9): [True: 623, False: 252] ------------------ 4922| | //return TokError("unexpected token in '.if' directive"); 4923| 623| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4924| 623| return true; 4925| 623| } 4926| | 4927| 252| Lex(); 4928| | 4929| 252| switch (DirKind) { 4930| 0| default: ------------------ | Branch (4930:5): [True: 0, False: 252] ------------------ 4931| 0| llvm_unreachable("unsupported directive"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 4932| 3| case DK_IF: ------------------ | Branch (4932:5): [True: 3, False: 249] ------------------ 4933| 3| case DK_IFNE: ------------------ | Branch (4933:5): [True: 0, False: 252] ------------------ 4934| 3| break; 4935| 116| case DK_IFEQ: ------------------ | Branch (4935:5): [True: 116, False: 136] ------------------ 4936| 116| ExprValue = ExprValue == 0; 4937| 116| break; 4938| 130| case DK_IFGE: ------------------ | Branch (4938:5): [True: 130, False: 122] ------------------ 4939| 130| ExprValue = ExprValue >= 0; 4940| 130| break; 4941| 2| case DK_IFGT: ------------------ | Branch (4941:5): [True: 2, False: 250] ------------------ 4942| 2| ExprValue = ExprValue > 0; 4943| 2| break; 4944| 1| case DK_IFLE: ------------------ | Branch (4944:5): [True: 1, False: 251] ------------------ 4945| 1| ExprValue = ExprValue <= 0; 4946| 1| break; 4947| 0| case DK_IFLT: ------------------ | Branch (4947:5): [True: 0, False: 252] ------------------ 4948| 0| ExprValue = ExprValue < 0; 4949| 0| break; 4950| 252| } 4951| | 4952| 252| TheCondState.CondMet = ExprValue; 4953| 252| TheCondState.Ignore = !TheCondState.CondMet; 4954| 252| } 4955| | 4956| 523| return false; 4957| 1.15k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser17parseDirectiveIfbEN7llvm_ks5SMLocEb: 4962| 282|{ 4963| 282| TheCondStack.push_back(TheCondState); 4964| 282| TheCondState.TheCond = AsmCond::IfCond; 4965| | 4966| 282| if (TheCondState.Ignore) { ------------------ | Branch (4966:7): [True: 146, False: 136] ------------------ 4967| 146| eatToEndOfStatement(); 4968| 146| } else { 4969| 136| StringRef Str = parseStringToEndOfStatement(); 4970| | 4971| 136| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (4971:9): [True: 0, False: 136] ------------------ 4972| | //return TokError("unexpected token in '.ifb' directive"); 4973| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4974| 0| return true; 4975| 0| } 4976| | 4977| 136| Lex(); 4978| | 4979| 136| TheCondState.CondMet = ExpectBlank == Str.empty(); 4980| 136| TheCondState.Ignore = !TheCondState.CondMet; 4981| 136| } 4982| | 4983| 282| return false; 4984| 282|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser17parseDirectiveIfcEN7llvm_ks5SMLocEb: 4990| 346|{ 4991| 346| TheCondStack.push_back(TheCondState); 4992| 346| TheCondState.TheCond = AsmCond::IfCond; 4993| | 4994| 346| if (TheCondState.Ignore) { ------------------ | Branch (4994:7): [True: 233, False: 113] ------------------ 4995| 233| eatToEndOfStatement(); 4996| 233| } else { 4997| 113| StringRef Str1 = parseStringToComma(); 4998| | 4999| 113| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (4999:9): [True: 1, False: 112] ------------------ 5000| | //return TokError("unexpected token in '.ifc' directive"); 5001| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5002| 1| return true; 5003| 1| } 5004| | 5005| 112| Lex(); 5006| | 5007| 112| StringRef Str2 = parseStringToEndOfStatement(); 5008| | 5009| 112| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (5009:9): [True: 0, False: 112] ------------------ 5010| | //return TokError("unexpected token in '.ifc' directive"); 5011| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5012| 0| return true; 5013| 0| } 5014| | 5015| 112| Lex(); 5016| | 5017| 112| TheCondState.CondMet = ExpectEqual == (Str1.trim() == Str2.trim()); 5018| 112| TheCondState.Ignore = !TheCondState.CondMet; 5019| 112| } 5020| | 5021| 345| return false; 5022| 346|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseStringToCommaEv: 802| 113|StringRef AsmParser::parseStringToComma() { 803| 113| const char *Start = getTok().getLoc().getPointer(); 804| | 805| 125| while (Lexer.isNot(AsmToken::EndOfStatement) && ------------------ | Branch (805:10): [True: 124, False: 1] ------------------ 806| 124| Lexer.isNot(AsmToken::Comma) && Lexer.isNot(AsmToken::Eof)) ------------------ | Branch (806:10): [True: 12, False: 112] | Branch (806:42): [True: 12, False: 0] ------------------ 807| 12| Lex(); 808| | 809| 113| const char *End = getTok().getLoc().getPointer(); 810| 113| return StringRef(Start, End - Start); 811| 113|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveIfeqsEN7llvm_ks5SMLocEb: 5027| 295|{ 5028| 295| if (Lexer.isNot(AsmToken::String)) { ------------------ | Branch (5028:7): [True: 43, False: 252] ------------------ 5029| | //if (ExpectEqual) 5030| | // TokError("expected string parameter for '.ifeqs' directive"); 5031| | //else 5032| | // TokError("expected string parameter for '.ifnes' directive"); 5033| 43| eatToEndOfStatement(); 5034| 43| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5035| 43| return true; 5036| 43| } 5037| | 5038| 252| bool valid; 5039| 252| StringRef String1 = getTok().getStringContents(valid); 5040| 252| if (!valid) { ------------------ | Branch (5040:7): [True: 0, False: 252] ------------------ 5041| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5042| 0| return true; 5043| 0| } 5044| | 5045| 252| Lex(); 5046| | 5047| 252| if (Lexer.isNot(AsmToken::Comma)) { ------------------ | Branch (5047:7): [True: 2, False: 250] ------------------ 5048| | //if (ExpectEqual) 5049| | // TokError("expected comma after first string for '.ifeqs' directive"); 5050| | //else 5051| | // TokError("expected comma after first string for '.ifnes' directive"); 5052| 2| eatToEndOfStatement(); 5053| 2| return true; 5054| 2| } 5055| | 5056| 250| Lex(); 5057| | 5058| 250| if (Lexer.isNot(AsmToken::String)) { ------------------ | Branch (5058:7): [True: 85, False: 165] ------------------ 5059| | //if (ExpectEqual) 5060| | // TokError("expected string parameter for '.ifeqs' directive"); 5061| | //else 5062| | // TokError("expected string parameter for '.ifnes' directive"); 5063| 85| eatToEndOfStatement(); 5064| 85| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5065| 85| return true; 5066| 85| } 5067| | 5068| 165| StringRef String2 = getTok().getStringContents(valid); 5069| 165| if (!valid) { ------------------ | Branch (5069:7): [True: 0, False: 165] ------------------ 5070| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5071| 0| return true; 5072| 0| } 5073| | 5074| 165| Lex(); 5075| | 5076| 165| TheCondStack.push_back(TheCondState); 5077| 165| TheCondState.TheCond = AsmCond::IfCond; 5078| 165| TheCondState.CondMet = ExpectEqual == (String1 == String2); 5079| 165| TheCondState.Ignore = !TheCondState.CondMet; 5080| | 5081| 165| return false; 5082| 165|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveIfdefEN7llvm_ks5SMLocEb: 5086| 360|bool AsmParser::parseDirectiveIfdef(SMLoc DirectiveLoc, bool expect_defined) { 5087| 360| StringRef Name; 5088| 360| TheCondStack.push_back(TheCondState); 5089| 360| TheCondState.TheCond = AsmCond::IfCond; 5090| | 5091| 360| if (TheCondState.Ignore) { ------------------ | Branch (5091:7): [True: 220, False: 140] ------------------ 5092| 220| eatToEndOfStatement(); 5093| 220| } else { 5094| 140| if (parseIdentifier(Name)) { ------------------ | Branch (5094:9): [True: 0, False: 140] ------------------ 5095| | //return TokError("expected identifier after '.ifdef'"); 5096| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5097| 0| return true; 5098| 0| } 5099| | 5100| 140| Lex(); 5101| | 5102| 140| MCSymbol *Sym = getContext().lookupSymbol(Name); 5103| | 5104| 140| if (expect_defined) ------------------ | Branch (5104:9): [True: 2, False: 138] ------------------ 5105| 2| TheCondState.CondMet = (Sym && !Sym->isUndefined()); ------------------ | Branch (5105:31): [True: 0, False: 2] | Branch (5105:38): [True: 0, False: 0] ------------------ 5106| 138| else 5107| 138| TheCondState.CondMet = (!Sym || Sym->isUndefined()); ------------------ | Branch (5107:31): [True: 138, False: 0] | Branch (5107:39): [True: 0, False: 0] ------------------ 5108| 140| TheCondState.Ignore = !TheCondState.CondMet; 5109| 140| } 5110| | 5111| 360| return false; 5112| 360|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser20parseDirectiveElseIfEN7llvm_ks5SMLocE: 5117| 690|{ 5118| 690| if (TheCondState.TheCond != AsmCond::IfCond && ------------------ | Branch (5118:7): [True: 547, False: 143] ------------------ 5119| 547| TheCondState.TheCond != AsmCond::ElseIfCond) { ------------------ | Branch (5119:7): [True: 1, False: 546] ------------------ 5120| | //Error(DirectiveLoc, "Encountered a .elseif that doesn't follow a .if or " 5121| | // " an .elseif"); 5122| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5123| 1| return true; 5124| 1| } 5125| | 5126| 689| TheCondState.TheCond = AsmCond::ElseIfCond; 5127| | 5128| 689| bool LastIgnoreState = false; 5129| 689| if (!TheCondStack.empty()) ------------------ | Branch (5129:7): [True: 689, False: 0] ------------------ 5130| 689| LastIgnoreState = TheCondStack.back().Ignore; 5131| 689| if (LastIgnoreState || TheCondState.CondMet) { ------------------ | Branch (5131:7): [True: 385, False: 304] | Branch (5131:26): [True: 165, False: 139] ------------------ 5132| 550| TheCondState.Ignore = true; 5133| 550| eatToEndOfStatement(); 5134| 550| } else { 5135| 139| int64_t ExprValue; 5136| 139| if (parseAbsoluteExpression(ExprValue)) { ------------------ | Branch (5136:9): [True: 139, False: 0] ------------------ 5137| 139| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5138| 139| return true; 5139| 139| } 5140| | 5141| 0| if (getLexer().isNot(AsmToken::EndOfStatement)) ------------------ | Branch (5141:9): [True: 0, False: 0] ------------------ 5142| | //return TokError("unexpected token in '.elseif' directive"); 5143| 0| return true; 5144| | 5145| 0| Lex(); 5146| 0| TheCondState.CondMet = ExprValue; 5147| 0| TheCondState.Ignore = !TheCondState.CondMet; 5148| 0| } 5149| | 5150| 550| return false; 5151| 689|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseDirectiveElseEN7llvm_ks5SMLocE: 5156| 526|{ 5157| 526| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (5157:7): [True: 140, False: 386] ------------------ 5158| | //return TokError("unexpected token in '.else' directive"); 5159| 140| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5160| 140| return true; 5161| 140| } 5162| | 5163| 386| Lex(); 5164| | 5165| 386| if (TheCondState.TheCond != AsmCond::IfCond && ------------------ | Branch (5165:7): [True: 126, False: 260] ------------------ 5166| 126| TheCondState.TheCond != AsmCond::ElseIfCond) { ------------------ | Branch (5166:7): [True: 1, False: 125] ------------------ 5167| | //Error(DirectiveLoc, "Encountered a .else that doesn't follow a .if or an " 5168| | // ".elseif"); 5169| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5170| 1| return true; 5171| 1| } 5172| 385| TheCondState.TheCond = AsmCond::ElseCond; 5173| 385| bool LastIgnoreState = false; 5174| 385| if (!TheCondStack.empty()) ------------------ | Branch (5174:7): [True: 385, False: 0] ------------------ 5175| 385| LastIgnoreState = TheCondStack.back().Ignore; 5176| 385| if (LastIgnoreState || TheCondState.CondMet) ------------------ | Branch (5176:7): [True: 256, False: 129] | Branch (5176:26): [True: 1, False: 128] ------------------ 5177| 257| TheCondState.Ignore = true; 5178| 128| else 5179| 128| TheCondState.Ignore = false; 5180| | 5181| 385| return false; 5182| 386|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveEndIfEN7llvm_ks5SMLocE: 5332| 264|{ 5333| 264| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (5333:7): [True: 0, False: 264] ------------------ 5334| | //return TokError("unexpected token in '.endif' directive"); 5335| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5336| 0| return true; 5337| 0| } 5338| | 5339| 264| Lex(); 5340| | 5341| 264| if ((TheCondState.TheCond == AsmCond::NoCond) || TheCondStack.empty()) { ------------------ | Branch (5341:7): [True: 133, False: 131] | Branch (5341:52): [True: 0, False: 131] ------------------ 5342| | //Error(DirectiveLoc, "Encountered a .endif that doesn't follow a .if or " 5343| | // ".else"); 5344| 133| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5345| 133| return true; 5346| 133| } 5347| 131| if (!TheCondStack.empty()) { ------------------ | Branch (5347:7): [True: 131, False: 0] ------------------ 5348| 131| TheCondState = TheCondStack.back(); 5349| 131| TheCondStack.pop_back(); 5350| 131| } 5351| | 5352| 131| return false; 5353| 264|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser15parseAssignmentEN7llvm_ks9StringRefEbb: 2518| 1.01k| bool NoDeadStrip) { 2519| 1.01k| MCSymbol *Sym; 2520| 1.01k| const MCExpr *Value; 2521| 1.01k| if (MCParserUtils::parseAssignmentExpression(Name, allow_redef, *this, Sym, ------------------ | Branch (2521:7): [True: 635, False: 377] ------------------ 2522| 1.01k| Value)) { 2523| 635| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2524| 635| return true; 2525| 635| } 2526| | 2527| 377| if (!Sym) { ------------------ | Branch (2527:7): [True: 174, False: 203] ------------------ 2528| | // In the case where we parse an expression starting with a '.', we will 2529| | // not generate an error, nor will we create a symbol. In this case we 2530| | // should just return out. 2531| 174| return false; 2532| 174| } 2533| | 2534| | // Do the assignment. 2535| 203| if (!Out.EmitAssignment(Sym, Value)) { ------------------ | Branch (2535:7): [True: 0, False: 203] ------------------ 2536| 0| KsError = KS_ERR_ASM_DIRECTIVE_ID; 2537| 0| return true; 2538| 0| } 2539| 203| if (NoDeadStrip) ------------------ | Branch (2539:7): [True: 0, False: 203] ------------------ 2540| 0| Out.EmitSymbolAttribute(Sym, MCSA_NoDeadStrip); 2541| | 2542| 203| return false; 2543| 203|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser16areMacrosEnabledEv: 280| 17.7k| bool areMacrosEnabled() {return MacrosEnabledFlag;} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser11lookupMacroEN7llvm_ks9StringRefE: 2446| 17.9k|const MCAsmMacro *AsmParser::lookupMacro(StringRef Name) { 2447| 17.9k| StringMap::iterator I = MacroMap.find(Name); 2448| 17.9k| return (I == MacroMap.end()) ? nullptr : &I->getValue(); ------------------ | Branch (2448:10): [True: 17.7k, False: 225] ------------------ 2449| 17.9k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser16handleMacroEntryEPKNS_10MCAsmMacroEN7llvm_ks5SMLocE: 2458| 27|{ 2459| | // Arbitrarily limit macro nesting depth, to match 'as'. We can eliminate 2460| | // this, although we should protect against infinite loops. 2461| 27| if (ActiveMacros.size() == 20) { ------------------ | Branch (2461:7): [True: 0, False: 27] ------------------ 2462| | // return TokError("macros cannot be nested more than 20 levels deep"); 2463| 0| KsError = KS_ERR_ASM_MACRO_LEVELS_EXCEED; 2464| 0| return true; 2465| 0| } 2466| | 2467| 27| MCAsmMacroArguments A; 2468| 27| if (parseMacroArguments(M, A)) { ------------------ | Branch (2468:7): [True: 7, False: 20] ------------------ 2469| 7| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2470| 7| return true; 2471| 7| } 2472| | 2473| | // Macro instantiation is lexical, unfortunately. We construct a new buffer 2474| | // to hold the macro body with substitutions. 2475| 20| SmallString<256> Buf; 2476| 20| StringRef Body = M->Body; 2477| 20| raw_svector_ostream OS(Buf); 2478| | 2479| 20| if (expandMacro(OS, Body, M->Parameters, A, true, getTok().getLoc())) { ------------------ | Branch (2479:7): [True: 0, False: 20] ------------------ 2480| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2481| 0| return true; 2482| 0| } 2483| | 2484| | // We include the .endmacro in the buffer as our cue to exit the macro 2485| | // instantiation. 2486| 20| OS << ".endmacro\n"; 2487| | 2488| 20| std::unique_ptr Instantiation = 2489| 20| MemoryBuffer::getMemBufferCopy(OS.str(), ""); 2490| | 2491| | // Create the macro instantiation object and add to the current macro 2492| | // instantiation stack. 2493| 20| MacroInstantiation *MI = new MacroInstantiation( 2494| 20| NameLoc, CurBuffer, getTok().getLoc(), TheCondStack.size()); 2495| 20| ActiveMacros.push_back(MI); 2496| | 2497| 20| ++NumOfMacroInstantiations; 2498| | 2499| | // Jump to the macro instantiation and prime the lexer. 2500| 20| CurBuffer = SrcMgr.AddNewSourceBuffer(std::move(Instantiation), SMLoc()); 2501| 20| Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer()); 2502| 20| Lex(); 2503| | 2504| 20| return false; 2505| 20|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseMacroArgumentsEPKNS_10MCAsmMacroERNSt3__16vectorINS5_IN7llvm_ks8AsmTokenENS4_9allocatorIS7_EEEENS8_ISA_EEEE: 2337| 590|{ 2338| 590| const unsigned NParameters = M ? M->Parameters.size() : 0; ------------------ | Branch (2338:32): [True: 27, False: 563] ------------------ 2339| 590| bool NamedParametersFound = false; 2340| 590| SmallVector FALocs; 2341| | 2342| 590| A.resize(NParameters); 2343| 590| FALocs.resize(NParameters); 2344| | 2345| | // Parse two kinds of macro invocations: 2346| | // - macros defined without any parameters accept an arbitrary number of them 2347| | // - macros defined with parameters accept at most that many of them 2348| 590| bool HasVararg = NParameters ? M->Parameters.back().Vararg : false; ------------------ | Branch (2348:20): [True: 27, False: 563] ------------------ 2349| 18.7k| for (unsigned Parameter = 0; !NParameters || Parameter < NParameters; ------------------ | Branch (2349:32): [True: 18.4k, False: 251] | Branch (2349:48): [True: 249, False: 2] ------------------ 2350| 18.7k| ++Parameter) { 2351| | //SMLoc IDLoc = Lexer.getLoc(); 2352| 18.7k| MCAsmMacroParameter FA; 2353| | 2354| 18.7k| if (Lexer.is(AsmToken::Identifier) && Lexer.peekTok().is(AsmToken::Equal)) { ------------------ | Branch (2354:9): [True: 321, False: 18.3k] | Branch (2354:9): [True: 215, False: 18.4k] | Branch (2354:43): [True: 215, False: 106] ------------------ 2355| 215| if (parseIdentifier(FA.Name)) { ------------------ | Branch (2355:11): [True: 0, False: 215] ------------------ 2356| | //Error(IDLoc, "invalid argument identifier for formal argument"); 2357| 0| eatToEndOfStatement(); 2358| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2359| 0| return true; 2360| 0| } 2361| | 2362| 215| if (!Lexer.is(AsmToken::Equal)) { ------------------ | Branch (2362:11): [True: 0, False: 215] ------------------ 2363| | //TokError("expected '=' after formal parameter identifier"); 2364| 0| eatToEndOfStatement(); 2365| 0| KsError = KS_ERR_ASM_MACRO_EQU; 2366| 0| return true; 2367| 0| } 2368| 215| Lex(); 2369| | 2370| 215| NamedParametersFound = true; 2371| 215| } 2372| | 2373| 18.7k| if (NamedParametersFound && FA.Name.empty()) { ------------------ | Branch (2373:9): [True: 220, False: 18.4k] | Branch (2373:33): [True: 5, False: 215] ------------------ 2374| | //Error(IDLoc, "cannot mix positional and keyword arguments"); 2375| 5| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2376| 5| eatToEndOfStatement(); 2377| 5| return true; 2378| 5| } 2379| | 2380| 18.7k| bool Vararg = HasVararg && Parameter == (NParameters - 1); ------------------ | Branch (2380:19): [True: 0, False: 18.7k] | Branch (2380:32): [True: 0, False: 0] ------------------ 2381| 18.7k| if (parseMacroArgument(FA.Value, Vararg)) { ------------------ | Branch (2381:9): [True: 4, False: 18.7k] ------------------ 2382| 4| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2383| 4| return true; 2384| 4| } 2385| | 2386| 18.7k| unsigned PI = Parameter; 2387| 18.7k| if (!FA.Name.empty()) { ------------------ | Branch (2387:9): [True: 215, False: 18.4k] ------------------ 2388| 215| unsigned FAI = 0; 2389| 1.20k| for (FAI = 0; FAI < NParameters; ++FAI) ------------------ | Branch (2389:21): [True: 1.20k, False: 0] ------------------ 2390| 1.20k| if (M->Parameters[FAI].Name == FA.Name) ------------------ | Branch (2390:13): [True: 215, False: 988] ------------------ 2391| 215| break; 2392| | 2393| 215| if (FAI >= NParameters) { ------------------ | Branch (2393:11): [True: 0, False: 215] ------------------ 2394| | //assert(M && "expected macro to be defined"); 2395| | //Error(IDLoc, 2396| | // "parameter named '" + FA.Name + "' does not exist for macro '" + 2397| | // M->Name + "'"); 2398| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2399| 0| return true; 2400| 0| } 2401| 215| PI = FAI; 2402| 215| } 2403| | 2404| 18.7k| if (!FA.Value.empty()) { ------------------ | Branch (2404:9): [True: 441, False: 18.2k] ------------------ 2405| 441| if (A.size() <= PI) ------------------ | Branch (2405:11): [True: 224, False: 217] ------------------ 2406| 224| A.resize(PI + 1); 2407| 441| A[PI] = FA.Value; 2408| | 2409| 441| if (FALocs.size() <= PI) ------------------ | Branch (2409:11): [True: 224, False: 217] ------------------ 2410| 224| FALocs.resize(PI + 1); 2411| | 2412| 441| FALocs[PI] = Lexer.getLoc(); 2413| 441| } 2414| | 2415| | // At the end of the statement, fill in remaining arguments that have 2416| | // default values. If there aren't any, then the next argument is 2417| | // required but missing 2418| 18.7k| if (Lexer.is(AsmToken::EndOfStatement)) { ------------------ | Branch (2418:9): [True: 579, False: 18.1k] ------------------ 2419| 579| bool Failure = false; 2420| 2.33k| for (unsigned FAI = 0; FAI < NParameters; ++FAI) { ------------------ | Branch (2420:30): [True: 1.76k, False: 579] ------------------ 2421| 1.76k| if (A[FAI].empty()) { ------------------ | Branch (2421:13): [True: 1.74k, False: 19] ------------------ 2422| 1.74k| if (M->Parameters[FAI].Required) { ------------------ | Branch (2422:15): [True: 0, False: 1.74k] ------------------ 2423| | //Error(FALocs[FAI].isValid() ? FALocs[FAI] : Lexer.getLoc(), 2424| | // "missing value for required parameter " 2425| | // "'" + M->Parameters[FAI].Name + "' in macro '" + M->Name + "'"); 2426| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2427| 0| Failure = true; 2428| 0| } 2429| | 2430| 1.74k| if (!M->Parameters[FAI].Value.empty()) ------------------ | Branch (2430:15): [True: 221, False: 1.52k] ------------------ 2431| 221| A[FAI] = M->Parameters[FAI].Value; 2432| 1.74k| } 2433| 1.76k| } 2434| 579| return Failure; 2435| 579| } 2436| | 2437| 18.1k| if (Lexer.is(AsmToken::Comma)) ------------------ | Branch (2437:9): [True: 18.1k, False: 0] ------------------ 2438| 18.1k| Lex(); 2439| 18.1k| } 2440| | 2441| | // return TokError("too many positional arguments"); 2442| 2| KsError = KS_ERR_ASM_MACRO_ARGS; 2443| 2| return true; 2444| 590|} AsmParser.cpp:_ZN12_GLOBAL__N_119MCAsmMacroParameterC2Ev: 65| 21.1k| MCAsmMacroParameter() : Required(false), Vararg(false) {} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseMacroArgumentERNSt3__16vectorIN7llvm_ks8AsmTokenENS1_9allocatorIS4_EEEEb: 2261| 18.7k|{ 2262| | 2263| 18.7k| if (Vararg) { ------------------ | Branch (2263:7): [True: 0, False: 18.7k] ------------------ 2264| 0| if (Lexer.isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (2264:9): [True: 0, False: 0] ------------------ 2265| 0| StringRef Str = parseStringToEndOfStatement(); 2266| 0| MA.emplace_back(AsmToken::String, Str); 2267| 0| } 2268| 0| return false; 2269| 0| } 2270| | 2271| 18.7k| unsigned ParenLevel = 0; 2272| 18.7k| unsigned AddTokens = 0; 2273| | 2274| | // Darwin doesn't use spaces to delmit arguments. 2275| 18.7k| AsmLexerSkipSpaceRAII ScopedSkipSpace(Lexer, IsDarwin); 2276| | 2277| 28.7k| for (;;) { 2278| 28.7k| if (Lexer.is(AsmToken::Eof) || Lexer.is(AsmToken::Equal)) { ------------------ | Branch (2278:9): [True: 3, False: 28.7k] | Branch (2278:36): [True: 0, False: 28.7k] ------------------ 2279| | // return TokError("unexpected token in macro instantiation"); 2280| 3| KsError = KS_ERR_ASM_MACRO_TOKEN; 2281| 3| return true; 2282| 3| } 2283| | 2284| 28.7k| if (ParenLevel == 0 && Lexer.is(AsmToken::Comma)) ------------------ | Branch (2284:9): [True: 25.0k, False: 3.66k] | Branch (2284:28): [True: 18.1k, False: 6.86k] ------------------ 2285| 18.1k| break; 2286| | 2287| 10.5k| if (Lexer.is(AsmToken::Space)) { ------------------ | Branch (2287:9): [True: 0, False: 10.5k] ------------------ 2288| 0| Lex(); // Eat spaces 2289| | 2290| | // Spaces can delimit parameters, but could also be part an expression. 2291| | // If the token after a space is an operator, add the token and the next 2292| | // one into this argument 2293| 0| if (!IsDarwin) { ------------------ | Branch (2293:11): [True: 0, False: 0] ------------------ 2294| 0| if (isOperator(Lexer.getKind())) { ------------------ | Branch (2294:13): [True: 0, False: 0] ------------------ 2295| | // Check to see whether the token is used as an operator, 2296| | // or part of an identifier 2297| 0| const char *NextChar = getTok().getEndLoc().getPointer(); 2298| 0| if (*NextChar == ' ') ------------------ | Branch (2298:15): [True: 0, False: 0] ------------------ 2299| 0| AddTokens = 2; 2300| 0| } 2301| | 2302| 0| if (!AddTokens && ParenLevel == 0) { ------------------ | Branch (2302:13): [True: 0, False: 0] | Branch (2302:27): [True: 0, False: 0] ------------------ 2303| 0| break; 2304| 0| } 2305| 0| } 2306| 0| } 2307| | 2308| | // handleMacroEntry relies on not advancing the lexer here 2309| | // to be able to fill in the remaining default parameter values 2310| 10.5k| if (Lexer.is(AsmToken::EndOfStatement)) ------------------ | Branch (2310:9): [True: 588, False: 9.94k] ------------------ 2311| 588| break; 2312| | 2313| | // Adjust the current parentheses level. 2314| 9.94k| if (Lexer.is(AsmToken::LParen)) ------------------ | Branch (2314:9): [True: 2, False: 9.93k] ------------------ 2315| 2| ++ParenLevel; 2316| 9.93k| else if (Lexer.is(AsmToken::RParen) && ParenLevel) ------------------ | Branch (2316:14): [True: 1, False: 9.93k] | Branch (2316:44): [True: 1, False: 0] ------------------ 2317| 1| --ParenLevel; 2318| | 2319| | // Append the token to the current argument list. 2320| 9.94k| MA.push_back(getTok()); 2321| 9.94k| if (AddTokens) ------------------ | Branch (2321:9): [True: 0, False: 9.94k] ------------------ 2322| 0| AddTokens--; 2323| 9.94k| Lex(); 2324| 9.94k| } 2325| | 2326| 18.7k| if (ParenLevel != 0) { ------------------ | Branch (2326:7): [True: 1, False: 18.7k] ------------------ 2327| | // return TokError("unbalanced parentheses in macro argument"); 2328| 1| KsError = KS_ERR_ASM_MACRO_PAREN; 2329| 1| return true; 2330| 1| } 2331| 18.7k| return false; 2332| 18.7k|} AsmParser.cpp:_ZN12_GLOBAL__N_121AsmLexerSkipSpaceRAIIC2ERN7llvm_ks8AsmLexerEb: 2247| 18.7k| AsmLexerSkipSpaceRAII(AsmLexer &Lexer, bool SkipSpace) : Lexer(Lexer) { 2248| 18.7k| Lexer.setSkipSpace(SkipSpace); 2249| 18.7k| } AsmParser.cpp:_ZN12_GLOBAL__N_121AsmLexerSkipSpaceRAIID2Ev: 2251| 18.7k| ~AsmLexerSkipSpaceRAII() { 2252| 18.7k| Lexer.setSkipSpace(true); 2253| 18.7k| } AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser11expandMacroERN7llvm_ks19raw_svector_ostreamENS1_9StringRefENS1_8ArrayRefINS_19MCAsmMacroParameterEEENS5_INSt3__16vectorINS1_8AsmTokenENS8_9allocatorISA_EEEEEEbNS1_5SMLocE: 2090| 426|{ 2091| 426| unsigned NParameters = Parameters.size(); 2092| 426| bool HasVararg = NParameters ? Parameters.back().Vararg : false; ------------------ | Branch (2092:20): [True: 36, False: 390] ------------------ 2093| 426| if ((!IsDarwin || NParameters != 0) && NParameters != A.size()) ------------------ | Branch (2093:8): [True: 0, False: 426] | Branch (2093:21): [True: 36, False: 390] | Branch (2093:42): [True: 0, False: 36] ------------------ 2094| | //return Error(L, "Wrong number of arguments"); 2095| 0| return true; 2096| | 2097| | // A macro without parameters is handled differently on Darwin: 2098| | // gas accepts no arguments and does no substitutions 2099| 441| while (!Body.empty()) { ------------------ | Branch (2099:10): [True: 106, False: 335] ------------------ 2100| | // Scan for the next substitution. 2101| 106| std::size_t End = Body.size(), Pos = 0; 2102| 32.4k| for (; Pos != End; ++Pos) { ------------------ | Branch (2102:12): [True: 32.3k, False: 91] ------------------ 2103| | // Check for a substitution or escape. 2104| 32.3k| if (IsDarwin && !NParameters) { ------------------ | Branch (2104:11): [True: 32.3k, False: 0] | Branch (2104:23): [True: 525, False: 31.8k] ------------------ 2105| | // This macro has no parameters, look for $0, $1, etc. 2106| 525| if (Body[Pos] != '$' || Pos + 1 == End) ------------------ | Branch (2106:13): [True: 525, False: 0] | Branch (2106:33): [True: 0, False: 0] ------------------ 2107| 525| continue; 2108| | 2109| 0| char Next = Body[Pos + 1]; 2110| 0| if (Next == '$' || Next == 'n' || ------------------ | Branch (2110:13): [True: 0, False: 0] | Branch (2110:28): [True: 0, False: 0] ------------------ 2111| 0| isdigit(static_cast(Next))) ------------------ | Branch (2111:13): [True: 0, False: 0] ------------------ 2112| 0| break; 2113| 31.8k| } else { 2114| | // This macro has parameters, look for \foo, \bar, etc. 2115| 31.8k| if (Body[Pos] == '\\' && Pos + 1 != End) ------------------ | Branch (2115:13): [True: 15, False: 31.8k] | Branch (2115:34): [True: 15, False: 0] ------------------ 2116| 15| break; 2117| 31.8k| } 2118| 32.3k| } 2119| | 2120| | // Add the prefix. 2121| 106| OS << Body.slice(0, Pos); 2122| | 2123| | // Check if we reached the end. 2124| 106| if (Pos == End) ------------------ | Branch (2124:9): [True: 91, False: 15] ------------------ 2125| 91| break; 2126| | 2127| 15| if (IsDarwin && !NParameters) { ------------------ | Branch (2127:9): [True: 15, False: 0] | Branch (2127:21): [True: 0, False: 15] ------------------ 2128| 0| switch (Body[Pos + 1]) { 2129| | // $$ => $ 2130| 0| case '$': ------------------ | Branch (2130:7): [True: 0, False: 0] ------------------ 2131| 0| OS << '$'; 2132| 0| break; 2133| | 2134| | // $n => number of arguments 2135| 0| case 'n': ------------------ | Branch (2135:7): [True: 0, False: 0] ------------------ 2136| 0| OS << A.size(); 2137| 0| break; 2138| | 2139| | // $[0-9] => argument 2140| 0| default: { ------------------ | Branch (2140:7): [True: 0, False: 0] ------------------ 2141| | // Missing arguments are ignored. 2142| 0| unsigned Index = Body[Pos + 1] - '0'; 2143| 0| if (Index >= A.size()) ------------------ | Branch (2143:13): [True: 0, False: 0] ------------------ 2144| 0| break; 2145| | 2146| | // Otherwise substitute with the token values, with spaces eliminated. 2147| 0| for (const AsmToken &Token : A[Index]) ------------------ | Branch (2147:36): [True: 0, False: 0] ------------------ 2148| 0| OS << Token.getString(); 2149| 0| break; 2150| 0| } 2151| 0| } 2152| 0| Pos += 2; 2153| 15| } else { 2154| 15| unsigned I = Pos + 1; 2155| | 2156| | // Check for the \@ pseudo-variable. 2157| 15| if (EnableAtPseudoVariable && Body[I] == '@' && I + 1 != End) ------------------ | Branch (2157:11): [True: 15, False: 0] | Branch (2157:37): [True: 0, False: 15] | Branch (2157:55): [True: 0, False: 0] ------------------ 2158| 0| ++I; 2159| 15| else 2160| 15| while (isIdentifierChar(Body[I]) && I + 1 != End) ------------------ | Branch (2160:16): [True: 0, False: 15] | Branch (2160:45): [True: 0, False: 0] ------------------ 2161| 0| ++I; 2162| | 2163| 15| const char *Begin = Body.data() + Pos + 1; 2164| 15| StringRef Argument(Begin, I - (Pos + 1)); 2165| 15| unsigned Index = 0; 2166| | 2167| 15| if (Argument == "@") { ------------------ | Branch (2167:11): [True: 0, False: 15] ------------------ 2168| 0| OS << NumOfMacroInstantiations; 2169| 0| Pos += 2; 2170| 15| } else { 2171| 30| for (; Index < NParameters; ++Index) ------------------ | Branch (2171:16): [True: 15, False: 15] ------------------ 2172| 15| if (Parameters[Index].Name == Argument) ------------------ | Branch (2172:15): [True: 0, False: 15] ------------------ 2173| 0| break; 2174| | 2175| 15| if (Index == NParameters) { ------------------ | Branch (2175:13): [True: 15, False: 0] ------------------ 2176| 15| if (Body[Pos + 1] == '(' && Body[Pos + 2] == ')') ------------------ | Branch (2176:15): [True: 0, False: 15] | Branch (2176:39): [True: 0, False: 0] ------------------ 2177| 0| Pos += 3; 2178| 15| else { 2179| 15| OS << '\\' << Argument; 2180| 15| Pos = I; 2181| 15| } 2182| 15| } else { 2183| 0| bool VarargParameter = HasVararg && Index == (NParameters - 1); ------------------ | Branch (2183:34): [True: 0, False: 0] | Branch (2183:47): [True: 0, False: 0] ------------------ 2184| 0| for (const AsmToken &Token : A[Index]) ------------------ | Branch (2184:38): [True: 0, False: 0] ------------------ 2185| | // We expect no quotes around the string's contents when 2186| | // parsing for varargs. 2187| 0| if (Token.getKind() != AsmToken::String || VarargParameter) ------------------ | Branch (2187:17): [True: 0, False: 0] | Branch (2187:56): [True: 0, False: 0] ------------------ 2188| 0| OS << Token.getString(); 2189| 0| else { 2190| 0| bool valid; 2191| 0| OS << Token.getStringContents(valid); 2192| 0| if (!valid) { ------------------ | Branch (2192:19): [True: 0, False: 0] ------------------ 2193| 0| return true; 2194| 0| } 2195| 0| } 2196| | 2197| 0| Pos += 1 + Argument.size(); 2198| 0| } 2199| 15| } 2200| 15| } 2201| | // Update the scan point. 2202| 15| Body = Body.substr(Pos); 2203| 15| } 2204| | 2205| 426| return false; 2206| 426|} AsmParser.cpp:_ZL16isIdentifierCharc: 2081| 6.02k|static bool isIdentifierChar(char c) { 2082| 6.02k| return isalnum(static_cast(c)) || c == '_' || c == '$' || ------------------ | Branch (2082:10): [True: 2.68k, False: 3.34k] | Branch (2082:52): [True: 39, False: 3.30k] | Branch (2082:64): [True: 597, False: 2.71k] ------------------ 2083| 2.71k| c == '.'; ------------------ | Branch (2083:10): [True: 1, False: 2.71k] ------------------ 2084| 6.02k|} AsmParser.cpp:_ZN12_GLOBAL__N_118MacroInstantiationC2EN7llvm_ks5SMLocEiS2_m: 2210| 932| : InstantiationLoc(IL), ExitBuffer(EB), ExitLoc(EL), 2211| 932| CondStackDepth(CondStackDepth) {} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser11isDirectiveEN7llvm_ks9StringRefE: 1435| 17.6k|{ 1436| 17.6k| if (KsSyntax == KS_OPT_SYNTAX_NASM) ------------------ | Branch (1436:9): [True: 0, False: 17.6k] ------------------ 1437| 0| return isNasmDirective(IDVal); 1438| 17.6k| else // Directives start with "." 1439| 17.6k| return (!IDVal.empty() && IDVal[0] == '.' && IDVal != "."); ------------------ | Branch (1439:17): [True: 17.6k, False: 5] | Branch (1439:35): [True: 14.3k, False: 3.39k] | Branch (1439:54): [True: 14.2k, False: 6] ------------------ 1440| 17.6k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveAsciiEN7llvm_ks9StringRefEb: 2692| 253|{ 2693| 253| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (2693:7): [True: 253, False: 0] ------------------ 2694| 253| checkForValidSection(); 2695| | 2696| 382| for (;;) { 2697| 382| if (getLexer().isNot(AsmToken::String)) { ------------------ | Branch (2697:11): [True: 195, False: 187] ------------------ 2698| | // return TokError("expected string in '" + Twine(IDVal) + "' directive"); 2699| 195| KsError = KS_ERR_ASM_DIRECTIVE_STR; 2700| 195| return true; 2701| 195| } 2702| | 2703| 187| std::string Data; 2704| 187| if (parseEscapedString(Data)) { ------------------ | Branch (2704:11): [True: 12, False: 175] ------------------ 2705| 12| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2706| 12| return true; 2707| 12| } 2708| | 2709| 175| getStreamer().EmitBytes(Data); 2710| 175| if (ZeroTerminated) ------------------ | Branch (2710:11): [True: 175, False: 0] ------------------ 2711| 175| getStreamer().EmitBytes(StringRef("\0", 1)); 2712| | 2713| 175| Lex(); 2714| | 2715| 175| if (getLexer().is(AsmToken::EndOfStatement)) ------------------ | Branch (2715:11): [True: 45, False: 130] ------------------ 2716| 45| break; 2717| | 2718| 130| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (2718:11): [True: 1, False: 129] ------------------ 2719| | // return TokError("unexpected token in '" + Twine(IDVal) + "' directive"); 2720| 1| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 2721| 1| return true; 2722| 1| } 2723| 129| Lex(); 2724| 129| } 2725| 253| } 2726| | 2727| 45| Lex(); 2728| 45| return false; 2729| 253|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveValueEjRj: 2808| 278|{ 2809| 278| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (2809:7): [True: 135, False: 143] ------------------ 2810| 135| checkForValidSection(); 2811| | 2812| 135| for (;;) { 2813| 135| const MCExpr *Value; 2814| 135| SMLoc ExprLoc = getLexer().getLoc(); 2815| 135| if (parseExpression(Value)) { ------------------ | Branch (2815:11): [True: 0, False: 135] ------------------ 2816| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2817| 0| return true; 2818| 0| } 2819| | 2820| | // Special case constant expressions to match code generator. 2821| 135| if (const MCConstantExpr *MCE = dyn_cast(Value)) { ------------------ | Branch (2821:33): [True: 0, False: 135] ------------------ 2822| 0| assert(Size <= 8 && "Invalid size"); ------------------ | Branch (2822:9): [True: 0, False: 0] | Branch (2822:9): [True: 0, Folded] | Branch (2822:9): [True: 0, False: 0] ------------------ 2823| 0| uint64_t IntValue = MCE->getValue(); 2824| 0| if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) { ------------------ | Branch (2824:13): [True: 0, False: 0] | Branch (2824:45): [True: 0, False: 0] ------------------ 2825| | // return Error(ExprLoc, "literal value out of range for directive"); 2826| 0| KsError = KS_ERR_ASM_DIRECTIVE_VALUE_RANGE; 2827| 0| return true; 2828| 0| } 2829| 0| bool Error; 2830| 0| getStreamer().EmitIntValue(IntValue, Size, Error); 2831| 0| if (Error) { ------------------ | Branch (2831:13): [True: 0, False: 0] ------------------ 2832| 0| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 2833| 0| return true; 2834| 0| } 2835| 0| } else 2836| 135| getStreamer().EmitValue(Value, Size, ExprLoc); 2837| | 2838| 135| if (getLexer().is(AsmToken::EndOfStatement)) ------------------ | Branch (2838:11): [True: 132, False: 3] ------------------ 2839| 132| break; 2840| | 2841| | // FIXME: Improve diagnostic. 2842| 3| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (2842:11): [True: 3, False: 0] ------------------ 2843| | // return TokError("unexpected token in directive"); 2844| 3| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 2845| 3| return true; 2846| 3| } 2847| 0| Lex(); 2848| 0| } 2849| 135| } 2850| | 2851| 275| Lex(); 2852| 275| return false; 2853| 278|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser15parseExpressionERPKN7llvm_ks6MCExprE: 1076| 48.3k|bool AsmParser::parseExpression(const MCExpr *&Res) { 1077| 48.3k| SMLoc EndLoc; 1078| 48.3k| return parseExpression(Res, EndLoc); 1079| 48.3k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser23parseDirectiveOctaValueERj: 2858| 2|{ 2859| 2| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (2859:7): [True: 2, False: 0] ------------------ 2860| 2| checkForValidSection(); 2861| | 2862| 334| for (;;) { 2863| 334| if (Lexer.getKind() == AsmToken::Error) { ------------------ | Branch (2863:11): [True: 0, False: 334] ------------------ 2864| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2865| 0| return true; 2866| 0| } 2867| 334| if (Lexer.getKind() != AsmToken::Integer && ------------------ | Branch (2867:11): [True: 148, False: 186] ------------------ 2868| 148| Lexer.getKind() != AsmToken::BigNum) { ------------------ | Branch (2868:11): [True: 0, False: 148] ------------------ 2869| | // return TokError("unknown token in expression"); 2870| 0| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 2871| 0| return true; 2872| 0| } 2873| | 2874| | // SMLoc ExprLoc = getLexer().getLoc(); 2875| 334| bool valid; 2876| 334| APInt IntValue = getTok().getAPIntVal(valid); 2877| 334| if (!valid) { ------------------ | Branch (2877:11): [True: 0, False: 334] ------------------ 2878| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2879| 0| return true; 2880| 0| } 2881| 334| Lex(); 2882| | 2883| 334| uint64_t hi, lo; 2884| 334| if (IntValue.isIntN(64)) { ------------------ | Branch (2884:11): [True: 186, False: 148] ------------------ 2885| 186| hi = 0; 2886| 186| lo = IntValue.getZExtValue(); 2887| 186| } else if (IntValue.isIntN(128)) { ------------------ | Branch (2887:18): [True: 148, False: 0] ------------------ 2888| | // It might actually have more than 128 bits, but the top ones are zero. 2889| 148| hi = IntValue.getHiBits(IntValue.getBitWidth() - 64).getZExtValue(); 2890| 148| lo = IntValue.getLoBits(64).getZExtValue(); 2891| 148| } else { 2892| | // return Error(ExprLoc, "literal value out of range for directive"); 2893| 0| KsError = KS_ERR_ASM_DIRECTIVE_VALUE_RANGE; 2894| 0| return true; 2895| 0| } 2896| | 2897| 334| bool Error; 2898| 334| if (MAI.isLittleEndian()) { ------------------ | Branch (2898:11): [True: 0, False: 334] ------------------ 2899| 0| getStreamer().EmitIntValue(lo, 8, Error); 2900| 0| getStreamer().EmitIntValue(hi, 8, Error); 2901| 334| } else { 2902| 334| getStreamer().EmitIntValue(hi, 8, Error); 2903| 334| getStreamer().EmitIntValue(lo, 8, Error); 2904| 334| } 2905| | 2906| 334| if (getLexer().is(AsmToken::EndOfStatement)) ------------------ | Branch (2906:11): [True: 0, False: 334] ------------------ 2907| 0| break; 2908| | 2909| | // FIXME: Improve diagnostic. 2910| 334| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (2910:11): [True: 2, False: 332] ------------------ 2911| | // return TokError("unexpected token in directive"); 2912| 2| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 2913| 2| return true; 2914| 2| } 2915| 332| Lex(); 2916| 332| } 2917| 2| } 2918| | 2919| 0| Lex(); 2920| 0| return false; 2921| 2|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser23parseDirectiveRealValueERKN7llvm_ks12fltSemanticsE: 2926| 283|{ 2927| 283| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (2927:7): [True: 282, False: 1] ------------------ 2928| 282| checkForValidSection(); 2929| | 2930| 2.42k| for (;;) { 2931| | // We don't truly support arithmetic on floating point expressions, so we 2932| | // have to manually parse unary prefixes. 2933| 2.42k| bool IsNeg = false; 2934| 2.42k| if (getLexer().is(AsmToken::Minus)) { ------------------ | Branch (2934:11): [True: 930, False: 1.49k] ------------------ 2935| 930| Lex(); 2936| 930| IsNeg = true; 2937| 1.49k| } else if (getLexer().is(AsmToken::Plus)) ------------------ | Branch (2937:18): [True: 536, False: 962] ------------------ 2938| 536| Lex(); 2939| | 2940| 2.42k| if (getLexer().isNot(AsmToken::Integer) && ------------------ | Branch (2940:11): [True: 1.26k, False: 1.16k] ------------------ 2941| 1.26k| getLexer().isNot(AsmToken::Real) && ------------------ | Branch (2941:11): [True: 1.13k, False: 130] ------------------ 2942| 1.13k| getLexer().isNot(AsmToken::Identifier)) { ------------------ | Branch (2942:11): [True: 0, False: 1.13k] ------------------ 2943| | // return TokError("unexpected token in directive"); 2944| 0| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 2945| 0| return true; 2946| 0| } 2947| | 2948| | // Convert to an APFloat. 2949| 2.42k| APFloat Value(Semantics); 2950| 2.42k| StringRef IDVal = getTok().getString(); 2951| 2.42k| if (getLexer().is(AsmToken::Identifier)) { ------------------ | Branch (2951:11): [True: 1.13k, False: 1.29k] ------------------ 2952| 1.13k| if (!IDVal.compare_lower("infinity") || !IDVal.compare_lower("inf")) ------------------ | Branch (2952:13): [True: 0, False: 1.13k] | Branch (2952:13): [True: 678, False: 455] | Branch (2952:49): [True: 678, False: 455] ------------------ 2953| 678| Value = APFloat::getInf(Semantics); 2954| 455| else if (!IDVal.compare_lower("nan")) ------------------ | Branch (2954:18): [True: 240, False: 215] ------------------ 2955| 240| Value = APFloat::getNaN(Semantics, false, ~0); 2956| 215| else { 2957| | // return TokError("invalid floating point literal"); 2958| 215| KsError = KS_ERR_ASM_DIRECTIVE_FPOINT; 2959| 215| return true; 2960| 215| } 2961| 1.29k| } else if (Value.convertFromString(IDVal, APFloat::rmNearestTiesToEven) == ------------------ | Branch (2961:18): [True: 0, False: 1.29k] ------------------ 2962| 1.29k| APFloat::opInvalidOp) { 2963| | // return TokError("invalid floating point literal"); 2964| 0| KsError = KS_ERR_ASM_DIRECTIVE_FPOINT; 2965| 0| return true; 2966| 0| } 2967| 2.21k| if (IsNeg) ------------------ | Branch (2967:11): [True: 929, False: 1.28k] ------------------ 2968| 929| Value.changeSign(); 2969| | 2970| | // Consume the numeric token. 2971| 2.21k| Lex(); 2972| | 2973| | // Emit the value as an integer. 2974| 2.21k| APInt AsInt = Value.bitcastToAPInt(); 2975| 2.21k| bool Error; 2976| 2.21k| getStreamer().EmitIntValue(AsInt.getLimitedValue(), 2977| 2.21k| AsInt.getBitWidth() / 8, Error); 2978| 2.21k| if (Error) { ------------------ | Branch (2978:11): [True: 0, False: 2.21k] ------------------ 2979| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2980| 0| return true; 2981| 0| } 2982| | 2983| 2.21k| if (getLexer().is(AsmToken::EndOfStatement)) ------------------ | Branch (2983:11): [True: 2, False: 2.21k] ------------------ 2984| 2| break; 2985| | 2986| 2.21k| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (2986:11): [True: 65, False: 2.14k] ------------------ 2987| | // return TokError("unexpected token in directive"); 2988| 65| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 2989| 65| return true; 2990| 65| } 2991| 2.14k| Lex(); 2992| 2.14k| } 2993| 282| } 2994| | 2995| 3| Lex(); 2996| 3| return false; 2997| 283|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveAlignEbj: 3170| 277|{ 3171| 277| checkForValidSection(); 3172| | 3173| | //SMLoc AlignmentLoc = getLexer().getLoc(); 3174| 277| int64_t Alignment; 3175| 277| if (parseAbsoluteExpression(Alignment)) { ------------------ | Branch (3175:7): [True: 0, False: 277] ------------------ 3176| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3177| 0| return true; 3178| 0| } 3179| | 3180| 277| SMLoc MaxBytesLoc; 3181| 277| bool HasFillExpr = false; 3182| 277| int64_t FillExpr = 0; 3183| 277| int64_t MaxBytesToFill = 0; 3184| 277| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (3184:7): [True: 136, False: 141] ------------------ 3185| 136| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (3185:9): [True: 6, False: 130] ------------------ 3186| | // return TokError("unexpected token in directive"); 3187| 6| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 3188| 6| return true; 3189| 6| } 3190| 130| Lex(); 3191| | 3192| | // The fill expression can be omitted while specifying a maximum number of 3193| | // alignment bytes, e.g: 3194| | // .align 3,,4 3195| 130| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (3195:9): [True: 0, False: 130] ------------------ 3196| 0| HasFillExpr = true; 3197| 0| if (parseAbsoluteExpression(FillExpr)) { ------------------ | Branch (3197:11): [True: 0, False: 0] ------------------ 3198| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3199| 0| return true; 3200| 0| } 3201| 0| } 3202| | 3203| 130| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (3203:9): [True: 130, False: 0] ------------------ 3204| 130| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (3204:11): [True: 0, False: 130] ------------------ 3205| | // return TokError("unexpected token in directive"); 3206| 0| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 3207| 0| return true; 3208| 0| } 3209| 130| Lex(); 3210| | 3211| 130| MaxBytesLoc = getLexer().getLoc(); 3212| 130| if (parseAbsoluteExpression(MaxBytesToFill)) { ------------------ | Branch (3212:11): [True: 2, False: 128] ------------------ 3213| 2| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3214| 2| return true; 3215| 2| } 3216| | 3217| 128| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (3217:11): [True: 0, False: 128] ------------------ 3218| | // return TokError("unexpected token in directive"); 3219| 0| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 3220| 0| return true; 3221| 0| } 3222| 128| } 3223| 130| } 3224| | 3225| 269| Lex(); 3226| | 3227| 269| if (!HasFillExpr) ------------------ | Branch (3227:7): [True: 269, False: 0] ------------------ 3228| 269| FillExpr = 0; 3229| | 3230| | // Compute alignment in bytes. 3231| 269| if (IsPow2) { ------------------ | Branch (3231:7): [True: 129, False: 140] ------------------ 3232| | // FIXME: Diagnose overflow. 3233| 129| if (Alignment >= 32) { ------------------ | Branch (3233:9): [True: 127, False: 2] ------------------ 3234| | //Error(AlignmentLoc, "invalid alignment value"); 3235| 127| Alignment = 31; 3236| 127| } 3237| | 3238| 129| Alignment = 1ULL << Alignment; 3239| 140| } else { 3240| | // Reject alignments that aren't either a power of two or zero, 3241| | // for gas compatibility. Alignment of zero is silently rounded 3242| | // up to one. 3243| 140| if (Alignment == 0) ------------------ | Branch (3243:9): [True: 113, False: 27] ------------------ 3244| 113| Alignment = 1; 3245| 140| if (!isPowerOf2_64(Alignment)) { ------------------ | Branch (3245:9): [True: 0, False: 140] ------------------ 3246| | //Error(AlignmentLoc, "alignment must be a power of 2"); 3247| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3248| 0| return true; 3249| 0| } 3250| 140| } 3251| | 3252| | // Diagnose non-sensical max bytes to align. 3253| 269| if (MaxBytesLoc.isValid()) { ------------------ | Branch (3253:7): [True: 128, False: 141] ------------------ 3254| 128| if (MaxBytesToFill < 1) { ------------------ | Branch (3254:9): [True: 0, False: 128] ------------------ 3255| | //Error(MaxBytesLoc, "alignment directive can never be satisfied in this " 3256| | // "many bytes, ignoring maximum bytes expression"); 3257| 0| MaxBytesToFill = 0; 3258| 0| } 3259| | 3260| 128| if (MaxBytesToFill >= Alignment) { ------------------ | Branch (3260:9): [True: 1, False: 127] ------------------ 3261| 1| Warning(MaxBytesLoc, "maximum bytes expression exceeds alignment and " 3262| 1| "has no effect"); 3263| 1| MaxBytesToFill = 0; 3264| 1| } 3265| 128| } 3266| | 3267| | // Check whether we should use optimal code alignment for this .align 3268| | // directive. 3269| 269| const MCSection *Section = getStreamer().getCurrentSection().first; 3270| 269| assert(Section && "must have section to emit alignment"); ------------------ | Branch (3270:3): [True: 269, False: 0] | Branch (3270:3): [True: 269, Folded] | Branch (3270:3): [True: 269, False: 0] ------------------ 3271| 269| bool UseCodeAlign = Section->UseCodeAlign(); 3272| 269| if ((!HasFillExpr || Lexer.getMAI().getTextAlignFillValue() == FillExpr) && ------------------ | Branch (3272:8): [True: 269, False: 0] | Branch (3272:24): [True: 0, False: 0] ------------------ 3273| 269| ValueSize == 1 && UseCodeAlign) { ------------------ | Branch (3273:7): [True: 269, False: 0] | Branch (3273:25): [True: 269, False: 0] ------------------ 3274| 269| getStreamer().EmitCodeAlignment(Alignment, MaxBytesToFill); 3275| 269| } else { 3276| | // FIXME: Target specific behavior about how the "extra" bytes are filled. 3277| 0| getStreamer().EmitValueToAlignment(Alignment, FillExpr, ValueSize, 3278| 0| MaxBytesToFill); 3279| 0| } 3280| | 3281| 269| return false; 3282| 269|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseDirectiveFillEv: 3036| 426|{ 3037| 426| checkForValidSection(); 3038| | 3039| 426| SMLoc RepeatLoc = getLexer().getLoc(); 3040| 426| int64_t NumValues; 3041| 426| if (parseAbsoluteExpression(NumValues)) { ------------------ | Branch (3041:7): [True: 0, False: 426] ------------------ 3042| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3043| 0| return true; 3044| 0| } 3045| | 3046| 426| if (NumValues < 0) { ------------------ | Branch (3046:7): [True: 153, False: 273] ------------------ 3047| 153| Warning(RepeatLoc, 3048| 153| "'.fill' directive with negative repeat count has no effect"); 3049| 153| NumValues = 0; 3050| 153| } 3051| | 3052| 426| int64_t FillSize = 1; 3053| 426| int64_t FillExpr = 0; 3054| | 3055| 426| SMLoc SizeLoc, ExprLoc; 3056| 426| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (3056:7): [True: 292, False: 134] ------------------ 3057| 292| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (3057:9): [True: 136, False: 156] ------------------ 3058| | // return TokError("unexpected token in '.fill' directive"); 3059| 136| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 3060| 136| return true; 3061| 136| } 3062| 156| Lex(); 3063| | 3064| 156| SizeLoc = getLexer().getLoc(); 3065| 156| if (parseAbsoluteExpression(FillSize)) { ------------------ | Branch (3065:9): [True: 2, False: 154] ------------------ 3066| 2| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3067| 2| return true; 3068| 2| } 3069| | 3070| 154| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (3070:9): [True: 74, False: 80] ------------------ 3071| 74| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (3071:11): [True: 0, False: 74] ------------------ 3072| | // return TokError("unexpected token in '.fill' directive"); 3073| 0| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 3074| 0| return true; 3075| 0| } 3076| 74| Lex(); 3077| | 3078| 74| ExprLoc = getLexer().getLoc(); 3079| 74| if (parseAbsoluteExpression(FillExpr)) { ------------------ | Branch (3079:11): [True: 0, False: 74] ------------------ 3080| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3081| 0| return true; 3082| 0| } 3083| | 3084| 74| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (3084:11): [True: 0, False: 74] ------------------ 3085| | // return TokError("unexpected token in '.fill' directive"); 3086| 0| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 3087| 0| return true; 3088| 0| } 3089| | 3090| 74| Lex(); 3091| 74| } 3092| 154| } 3093| | 3094| 288| if (FillSize < 0) { ------------------ | Branch (3094:7): [True: 74, False: 214] ------------------ 3095| 74| Warning(SizeLoc, "'.fill' directive with negative size has no effect"); 3096| 74| NumValues = 0; 3097| 74| } 3098| 288| if (FillSize > 8) { ------------------ | Branch (3098:7): [True: 78, False: 210] ------------------ 3099| 78| Warning(SizeLoc, "'.fill' directive with size greater than 8 has been truncated to 8"); 3100| 78| FillSize = 8; 3101| 78| } 3102| | 3103| 288| if (!isUInt<32>(FillExpr) && FillSize > 4) ------------------ | Branch (3103:7): [True: 1, False: 287] | Branch (3103:32): [True: 0, False: 1] ------------------ 3104| 0| Warning(ExprLoc, "'.fill' directive pattern has been truncated to 32-bits"); 3105| | 3106| 288| if (NumValues > 0) { ------------------ | Branch (3106:7): [True: 129, False: 159] ------------------ 3107| 129| int64_t NonZeroFillSize = FillSize > 4 ? 4 : FillSize; ------------------ | Branch (3107:31): [True: 0, False: 129] ------------------ 3108| 129| FillExpr &= ~0ULL >> (64 - NonZeroFillSize * 8); 3109| 129| bool Error; 3110| 1.35k| for (uint64_t i = 0, e = NumValues; i != e; ++i) { ------------------ | Branch (3110:41): [True: 1.22k, False: 128] ------------------ 3111| 1.22k| getStreamer().EmitIntValue(FillExpr, NonZeroFillSize, Error); 3112| 1.22k| if (Error) { ------------------ | Branch (3112:11): [True: 1, False: 1.22k] ------------------ 3113| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3114| 1| return true; 3115| 1| } 3116| 1.22k| if (NonZeroFillSize < FillSize) { ------------------ | Branch (3116:11): [True: 0, False: 1.22k] ------------------ 3117| 0| getStreamer().EmitIntValue(0, FillSize - NonZeroFillSize, Error); 3118| 0| if (Error) { ------------------ | Branch (3118:13): [True: 0, False: 0] ------------------ 3119| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3120| 0| return true; 3121| 0| } 3122| 0| } 3123| 1.22k| } 3124| 129| } 3125| | 3126| 287| return false; 3127| 288|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseDirectiveZeroEv: 3002| 153|{ 3003| 153| checkForValidSection(); 3004| | 3005| 153| int64_t NumBytes; 3006| 153| if (parseAbsoluteExpression(NumBytes)) { ------------------ | Branch (3006:7): [True: 3, False: 150] ------------------ 3007| 3| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3008| 3| return true; 3009| 3| } 3010| | 3011| 150| int64_t Val = 0; 3012| 150| if (getLexer().is(AsmToken::Comma)) { ------------------ | Branch (3012:7): [True: 1, False: 149] ------------------ 3013| 1| Lex(); 3014| 1| if (parseAbsoluteExpression(Val)) { ------------------ | Branch (3014:9): [True: 1, False: 0] ------------------ 3015| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3016| 1| return true; 3017| 1| } 3018| 1| } 3019| | 3020| 149| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (3020:7): [True: 132, False: 17] ------------------ 3021| | // return TokError("unexpected token in '.zero' directive"); 3022| 132| KsError = KS_ERR_ASM_DIRECTIVE_TOKEN; 3023| 132| return true; 3024| 132| } 3025| | 3026| 17| Lex(); 3027| | 3028| 17| getStreamer().EmitFill(NumBytes, Val); 3029| | 3030| 17| return false; 3031| 149|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseDirectiveCommEb: 4700| 816|{ 4701| 816| checkForValidSection(); 4702| | 4703| | //SMLoc IDLoc = getLexer().getLoc(); 4704| 816| StringRef Name; 4705| 816| if (parseIdentifier(Name)) { ------------------ | Branch (4705:7): [True: 130, False: 686] ------------------ 4706| | //return TokError("expected identifier in directive"); 4707| 130| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4708| 130| return true; 4709| 130| } 4710| | 4711| 686| if (Name.empty()) { ------------------ | Branch (4711:7): [True: 0, False: 686] ------------------ 4712| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4713| 0| return true; 4714| 0| } 4715| | // Handle the identifier as the key symbol. 4716| 686| MCSymbol *Sym = getContext().getOrCreateSymbol(Name); 4717| | 4718| 686| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (4718:7): [True: 3, False: 683] ------------------ 4719| | //return TokError("unexpected token in directive"); 4720| 3| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4721| 3| return true; 4722| 3| } 4723| 683| Lex(); 4724| | 4725| 683| int64_t Size; 4726| | //SMLoc SizeLoc = getLexer().getLoc(); 4727| 683| if (parseAbsoluteExpression(Size)) { ------------------ | Branch (4727:7): [True: 30, False: 653] ------------------ 4728| 30| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4729| 30| return true; 4730| 30| } 4731| | 4732| 653| int64_t Pow2Alignment = 0; 4733| 653| SMLoc Pow2AlignmentLoc; 4734| 653| if (getLexer().is(AsmToken::Comma)) { ------------------ | Branch (4734:7): [True: 64, False: 589] ------------------ 4735| 64| Lex(); 4736| 64| Pow2AlignmentLoc = getLexer().getLoc(); 4737| 64| if (parseAbsoluteExpression(Pow2Alignment)) { ------------------ | Branch (4737:9): [True: 0, False: 64] ------------------ 4738| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4739| 0| return true; 4740| 0| } 4741| | 4742| 64| LCOMM::LCOMMType LCOMM = Lexer.getMAI().getLCOMMDirectiveAlignmentType(); 4743| 64| if (IsLocal && LCOMM == LCOMM::NoAlignment) { ------------------ | Branch (4743:9): [True: 0, False: 64] | Branch (4743:20): [True: 0, False: 0] ------------------ 4744| | //return Error(Pow2AlignmentLoc, "alignment not supported on this target"); 4745| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4746| 0| return true; 4747| 0| } 4748| | 4749| | // If this target takes alignments in bytes (not log) validate and convert. 4750| 64| if ((!IsLocal && Lexer.getMAI().getCOMMDirectiveAlignmentIsInBytes()) || ------------------ | Branch (4750:10): [True: 64, False: 0] | Branch (4750:22): [True: 64, False: 0] ------------------ 4751| 64| (IsLocal && LCOMM == LCOMM::ByteAlignment)) { ------------------ | Branch (4751:10): [True: 0, False: 0] | Branch (4751:21): [True: 0, False: 0] ------------------ 4752| 64| if (!isPowerOf2_64(Pow2Alignment)) { ------------------ | Branch (4752:11): [True: 64, False: 0] ------------------ 4753| | //return Error(Pow2AlignmentLoc, "alignment must be a power of 2"); 4754| 64| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4755| 64| return true; 4756| 64| } 4757| 0| Pow2Alignment = Log2_64(Pow2Alignment); 4758| 0| } 4759| 64| } 4760| | 4761| 589| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (4761:7): [True: 0, False: 589] ------------------ 4762| | //return TokError("unexpected token in '.comm' or '.lcomm' directive"); 4763| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4764| 0| return true; 4765| 0| } 4766| | 4767| 589| Lex(); 4768| | 4769| | // NOTE: a size of zero for a .comm should create a undefined symbol 4770| | // but a size of .lcomm creates a bss symbol of size zero. 4771| 589| if (Size < 0) { ------------------ | Branch (4771:7): [True: 0, False: 589] ------------------ 4772| | //return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't " 4773| | // "be less than zero"); 4774| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4775| 0| return true; 4776| 0| } 4777| | 4778| | // NOTE: The alignment in the directive is a power of 2 value, the assembler 4779| | // may internally end up wanting an alignment in bytes. 4780| | // FIXME: Diagnose overflow. 4781| 589| if (Pow2Alignment < 0) { ------------------ | Branch (4781:7): [True: 0, False: 589] ------------------ 4782| | //return Error(Pow2AlignmentLoc, "invalid '.comm' or '.lcomm' directive " 4783| | // "alignment, can't be less than zero"); 4784| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4785| 0| return true; 4786| 0| } 4787| | 4788| 589| if (!Sym->isUndefined()) { ------------------ | Branch (4788:7): [True: 0, False: 589] ------------------ 4789| | //return Error(IDLoc, "invalid symbol redefinition"); 4790| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4791| 0| return true; 4792| 0| } 4793| | 4794| | // Create the Symbol as a common or local common with Size and Pow2Alignment 4795| 589| if (IsLocal) { ------------------ | Branch (4795:7): [True: 0, False: 589] ------------------ 4796| 0| getStreamer().EmitLocalCommonSymbol(Sym, Size, 1 << Pow2Alignment); 4797| 0| return false; 4798| 0| } 4799| | 4800| 589| getStreamer().EmitCommonSymbol(Sym, Size, 1 << Pow2Alignment); 4801| 589| return false; 4802| 589|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser21parseDirectiveIncludeEv: 4838| 1|{ 4839| 1| if (getLexer().isNot(AsmToken::String)) { ------------------ | Branch (4839:7): [True: 1, False: 0] ------------------ 4840| | //return TokError("expected string in '.include' directive"); 4841| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4842| 1| return true; 4843| 1| } 4844| | 4845| | // Allow the strings to have escaped octal character sequence. 4846| 0| std::string Filename; 4847| 0| if (parseEscapedString(Filename)) { ------------------ | Branch (4847:7): [True: 0, False: 0] ------------------ 4848| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4849| 0| return true; 4850| 0| } 4851| | //SMLoc IncludeLoc = getLexer().getLoc(); 4852| 0| Lex(); 4853| | 4854| 0| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (4854:7): [True: 0, False: 0] ------------------ 4855| | //return TokError("unexpected token in '.include' directive"); 4856| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4857| 0| return true; 4858| 0| } 4859| | 4860| | // Attempt to switch the lexer to the included file before consuming the end 4861| | // of statement to avoid losing it when we switch. 4862| 0| if (enterIncludeFile(Filename)) { ------------------ | Branch (4862:7): [True: 0, False: 0] ------------------ 4863| | //Error(IncludeLoc, "Could not find include file '" + Filename + "'"); 4864| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4865| 0| return true; 4866| 0| } 4867| | 4868| 0| return false; 4869| 0|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseDirectiveReptEN7llvm_ks5SMLocENS1_9StringRefE: 5563| 793|{ 5564| 793| const MCExpr *CountExpr; 5565| | //SMLoc CountLoc = getTok().getLoc(); 5566| 793| if (parseExpression(CountExpr)) { ------------------ | Branch (5566:7): [True: 1, False: 792] ------------------ 5567| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5568| 1| return true; 5569| 1| } 5570| | 5571| 792| int64_t Count; 5572| 792| if (!CountExpr->evaluateAsAbsolute(Count)) { ------------------ | Branch (5572:7): [True: 8, False: 784] ------------------ 5573| 8| eatToEndOfStatement(); 5574| | //return Error(CountLoc, "unexpected token in '" + Dir + "' directive"); 5575| 8| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5576| 8| return true; 5577| 8| } 5578| | 5579| 784| if (Count < 0) { ------------------ | Branch (5579:7): [True: 261, False: 523] ------------------ 5580| | //return Error(CountLoc, "Count is negative"); 5581| 261| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5582| 261| return true; 5583| 261| } 5584| | 5585| 523| if (Lexer.isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (5585:7): [True: 130, False: 393] ------------------ 5586| | //return TokError("unexpected token in '" + Dir + "' directive"); 5587| 130| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5588| 130| return true; 5589| 130| } 5590| | 5591| | // Eat the end of statement. 5592| 393| Lex(); 5593| | 5594| | // Lex the rept definition. 5595| 393| MCAsmMacro *M = parseMacroLikeBody(DirectiveLoc); 5596| 393| if (!M) { ------------------ | Branch (5596:7): [True: 1, False: 392] ------------------ 5597| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5598| 1| return true; 5599| 1| } 5600| | 5601| | // Macro instantiation is lexical, unfortunately. We construct a new buffer 5602| | // to hold the macro body with substitutions. 5603| 392| SmallString<256> Buf; 5604| 392| raw_svector_ostream OS(Buf); 5605| 782| while (Count--) { ------------------ | Branch (5605:10): [True: 390, False: 392] ------------------ 5606| | // Note that the AtPseudoVariable is disabled for instantiations of .rep(t). 5607| 390| if (expandMacro(OS, M->Body, None, None, false, getTok().getLoc())) { ------------------ | Branch (5607:9): [True: 0, False: 390] ------------------ 5608| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5609| 0| return true; 5610| 0| } 5611| 390| } 5612| 392| instantiateMacroLikeBody(M, DirectiveLoc, OS); 5613| | 5614| 392| return false; 5615| 392|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseMacroLikeBodyEN7llvm_ks5SMLocE: 5498| 945|MCAsmMacro *AsmParser::parseMacroLikeBody(SMLoc DirectiveLoc) { 5499| 945| AsmToken EndToken, StartToken = getTok(); 5500| | 5501| 945| unsigned NestLevel = 0; 5502| 1.76k| for (;;) { 5503| | // Check whether we have reached the end of the file. 5504| 1.76k| if (getLexer().is(AsmToken::Eof)) { ------------------ | Branch (5504:9): [True: 5, False: 1.75k] ------------------ 5505| | //Error(DirectiveLoc, "no matching '.endr' in definition"); 5506| 5| return nullptr; 5507| 5| } 5508| | 5509| 1.75k| if (Lexer.is(AsmToken::Identifier) && ------------------ | Branch (5509:9): [True: 1.49k, False: 265] | Branch (5509:9): [True: 186, False: 1.57k] ------------------ 5510| 1.49k| (getTok().getIdentifier() == ".rept")) { ------------------ | Branch (5510:9): [True: 186, False: 1.30k] ------------------ 5511| 186| ++NestLevel; 5512| 186| } 5513| | 5514| | // Otherwise, check whether we have reached the .endr. 5515| 1.75k| if (Lexer.is(AsmToken::Identifier) && getTok().getIdentifier() == ".endr") { ------------------ | Branch (5515:9): [True: 1.49k, False: 265] | Branch (5515:9): [True: 974, False: 785] | Branch (5515:43): [True: 974, False: 520] ------------------ 5516| 974| if (NestLevel == 0) { ------------------ | Branch (5516:11): [True: 940, False: 34] ------------------ 5517| 940| EndToken = getTok(); 5518| 940| Lex(); 5519| 940| if (Lexer.isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (5519:13): [True: 28, False: 912] ------------------ 5520| | //TokError("unexpected token in '.endr' directive"); 5521| 28| return nullptr; 5522| 28| } 5523| 912| break; 5524| 940| } 5525| 34| --NestLevel; 5526| 34| } 5527| | 5528| | // Otherwise, scan till the end of the statement. 5529| 819| eatToEndOfStatement(); 5530| 819| } 5531| | 5532| 912| const char *BodyStart = StartToken.getLoc().getPointer(); 5533| 912| const char *BodyEnd = EndToken.getLoc().getPointer(); 5534| 912| StringRef Body = StringRef(BodyStart, BodyEnd - BodyStart); 5535| | 5536| | // We Are Anonymous. 5537| 912| MacroLikeBodies.emplace_back(StringRef(), Body, MCAsmMacroParameters()); 5538| 912| return &MacroLikeBodies.back(); 5539| 945|} AsmParser.cpp:_ZN12_GLOBAL__N_110MCAsmMacroC2EN7llvm_ks9StringRefES2_NSt3__16vectorINS_19MCAsmMacroParameterENS3_9allocatorIS5_EEEE: 77| 927| : Name(N), Body(B), Parameters(std::move(P)) {} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser24instantiateMacroLikeBodyEPNS_10MCAsmMacroEN7llvm_ks5SMLocERNS3_19raw_svector_ostreamE: 5542| 912| raw_svector_ostream &OS) { 5543| 912| OS << ".endr\n"; 5544| | 5545| 912| std::unique_ptr Instantiation = 5546| 912| MemoryBuffer::getMemBufferCopy(OS.str(), ""); 5547| | 5548| | // Create the macro instantiation object and add to the current macro 5549| | // instantiation stack. 5550| 912| MacroInstantiation *MI = new MacroInstantiation( 5551| 912| DirectiveLoc, CurBuffer, getTok().getLoc(), TheCondStack.size()); 5552| 912| ActiveMacros.push_back(MI); 5553| | 5554| | // Jump to the macro instantiation and prime the lexer. 5555| 912| CurBuffer = SrcMgr.AddNewSourceBuffer(std::move(Instantiation), SMLoc()); 5556| 912| Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer()); 5557| 912| Lex(); 5558| 912|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser17parseDirectiveIrpEN7llvm_ks5SMLocE: 5620| 556|{ 5621| 556| MCAsmMacroParameter Parameter; 5622| | 5623| 556| if (parseIdentifier(Parameter.Name)) { ------------------ | Branch (5623:7): [True: 0, False: 556] ------------------ 5624| | //return TokError("expected identifier in '.irp' directive"); 5625| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5626| 0| return true; 5627| 0| } 5628| | 5629| 556| if (Lexer.isNot(AsmToken::Comma)) { ------------------ | Branch (5629:7): [True: 4, False: 552] ------------------ 5630| | //return TokError("expected comma in '.irp' directive"); 5631| 4| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5632| 4| return true; 5633| 4| } 5634| | 5635| 552| Lex(); 5636| | 5637| 552| MCAsmMacroArguments A; 5638| 552| if (parseMacroArguments(nullptr, A)) { ------------------ | Branch (5638:7): [True: 0, False: 552] ------------------ 5639| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5640| 0| return true; 5641| 0| } 5642| | 5643| | // Eat the end of statement. 5644| 552| Lex(); 5645| | 5646| | // Lex the irp definition. 5647| 552| MCAsmMacro *M = parseMacroLikeBody(DirectiveLoc); 5648| 552| if (!M) { ------------------ | Branch (5648:7): [True: 32, False: 520] ------------------ 5649| 32| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5650| 32| return true; 5651| 32| } 5652| | 5653| | // Macro instantiation is lexical, unfortunately. We construct a new buffer 5654| | // to hold the macro body with substitutions. 5655| 520| SmallString<256> Buf; 5656| 520| raw_svector_ostream OS(Buf); 5657| | 5658| 520| for (const MCAsmMacroArgument &Arg : A) { ------------------ | Branch (5658:38): [True: 16, False: 520] ------------------ 5659| | // Note that the AtPseudoVariable is enabled for instantiations of .irp. 5660| | // This is undocumented, but GAS seems to support it. 5661| 16| if (expandMacro(OS, M->Body, Parameter, Arg, true, getTok().getLoc())) { ------------------ | Branch (5661:9): [True: 0, False: 16] ------------------ 5662| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5663| 0| return true; 5664| 0| } 5665| 16| } 5666| | 5667| 520| instantiateMacroLikeBody(M, DirectiveLoc, OS); 5668| | 5669| 520| return false; 5670| 520|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseDirectiveIrpcEN7llvm_ks5SMLocE: 5675| 11|{ 5676| 11| MCAsmMacroParameter Parameter; 5677| | 5678| 11| if (parseIdentifier(Parameter.Name)) { ------------------ | Branch (5678:7): [True: 0, False: 11] ------------------ 5679| | //return TokError("expected identifier in '.irpc' directive"); 5680| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5681| 0| return true; 5682| 0| } 5683| | 5684| 11| if (Lexer.isNot(AsmToken::Comma)) { ------------------ | Branch (5684:7): [True: 0, False: 11] ------------------ 5685| | //return TokError("expected comma in '.irpc' directive"); 5686| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5687| 0| return true; 5688| 0| } 5689| | 5690| 11| Lex(); 5691| | 5692| 11| MCAsmMacroArguments A; 5693| 11| if (parseMacroArguments(nullptr, A)) { ------------------ | Branch (5693:7): [True: 4, False: 7] ------------------ 5694| 4| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5695| 4| return true; 5696| 4| } 5697| | 5698| 7| if (A.size() != 1 || A.front().size() != 1) { ------------------ | Branch (5698:7): [True: 7, False: 0] | Branch (5698:24): [True: 0, False: 0] ------------------ 5699| | //return TokError("unexpected token in '.irpc' directive"); 5700| 7| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5701| 7| return true; 5702| 7| } 5703| | 5704| | // Eat the end of statement. 5705| 0| Lex(); 5706| | 5707| | // Lex the irpc definition. 5708| 0| MCAsmMacro *M = parseMacroLikeBody(DirectiveLoc); 5709| 0| if (!M) { ------------------ | Branch (5709:7): [True: 0, False: 0] ------------------ 5710| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5711| 0| return true; 5712| 0| } 5713| | 5714| | // Macro instantiation is lexical, unfortunately. We construct a new buffer 5715| | // to hold the macro body with substitutions. 5716| 0| SmallString<256> Buf; 5717| 0| raw_svector_ostream OS(Buf); 5718| | 5719| 0| StringRef Values = A.front().front().getString(); 5720| 0| for (std::size_t I = 0, End = Values.size(); I != End; ++I) { ------------------ | Branch (5720:48): [True: 0, False: 0] ------------------ 5721| 0| MCAsmMacroArgument Arg; 5722| 0| Arg.emplace_back(AsmToken::Identifier, Values.slice(I, I + 1)); 5723| | 5724| | // Note that the AtPseudoVariable is enabled for instantiations of .irpc. 5725| | // This is undocumented, but GAS seems to support it. 5726| 0| if (expandMacro(OS, M->Body, Parameter, Arg, true, getTok().getLoc())) { ------------------ | Branch (5726:9): [True: 0, False: 0] ------------------ 5727| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5728| 0| return true; 5729| 0| } 5730| 0| } 5731| | 5732| 0| instantiateMacroLikeBody(M, DirectiveLoc, OS); 5733| | 5734| 0| return false; 5735| 0|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseDirectiveEndrEN7llvm_ks5SMLocE: 5738| 919|{ 5739| 919| if (ActiveMacros.empty()) { ------------------ | Branch (5739:7): [True: 7, False: 912] ------------------ 5740| | //return TokError("unmatched '.endr' directive"); 5741| 7| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5742| 7| return true; 5743| 7| } 5744| | 5745| | // The only .repl that should get here are the ones created by 5746| | // instantiateMacroLikeBody. 5747| 919| assert(getLexer().is(AsmToken::EndOfStatement)); ------------------ | Branch (5747:3): [True: 912, False: 0] ------------------ 5748| | 5749| 912| handleMacroExit(); 5750| 912| return false; 5751| 912|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser15handleMacroExitEv: 2507| 932|void AsmParser::handleMacroExit() { 2508| | // Jump to the EndOfStatement we should return to, and consume it. 2509| 932| jumpToLoc(ActiveMacros.back()->ExitLoc, ActiveMacros.back()->ExitBuffer); 2510| 932| Lex(); 2511| | 2512| | // Pop the instantiation entry. 2513| 932| delete ActiveMacros.back(); 2514| 932| ActiveMacros.pop_back(); 2515| 932|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser9jumpToLocEN7llvm_ks5SMLocEj: 649| 932|void AsmParser::jumpToLoc(SMLoc Loc, unsigned InBuffer) { 650| 932| CurBuffer = InBuffer ? InBuffer : SrcMgr.FindBufferContainingLoc(Loc); ------------------ | Branch (650:15): [True: 932, False: 0] ------------------ 651| 932| Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer(), 652| 932| Loc.getPointer()); 653| 932|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveSpaceEN7llvm_ks9StringRefE: 4574| 629|{ 4575| 629| checkForValidSection(); 4576| | 4577| 629| int64_t NumBytes; 4578| 629| if (parseAbsoluteExpression(NumBytes)) { ------------------ | Branch (4578:7): [True: 4, False: 625] ------------------ 4579| 4| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4580| 4| return true; 4581| 4| } 4582| | 4583| 625| int64_t FillExpr = 0; 4584| 625| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (4584:7): [True: 134, False: 491] ------------------ 4585| 134| if (getLexer().isNot(AsmToken::Comma)) { ------------------ | Branch (4585:9): [True: 134, False: 0] ------------------ 4586| | //return TokError("unexpected token in '" + Twine(IDVal) + "' directive"); 4587| 134| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4588| 134| return true; 4589| 134| } 4590| 0| Lex(); 4591| | 4592| 0| if (parseAbsoluteExpression(FillExpr)) ------------------ | Branch (4592:9): [True: 0, False: 0] ------------------ 4593| 0| return true; 4594| | 4595| 0| if (getLexer().isNot(AsmToken::EndOfStatement)) ------------------ | Branch (4595:9): [True: 0, False: 0] ------------------ 4596| | //return TokError("unexpected token in '" + Twine(IDVal) + "' directive"); 4597| 0| return true; 4598| 0| } 4599| | 4600| 491| Lex(); 4601| | 4602| 491| if (NumBytes <= 0) { ------------------ | Branch (4602:7): [True: 216, False: 275] ------------------ 4603| | //return TokError("invalid number of bytes in '" + Twine(IDVal) + 4604| | // "' directive"); 4605| 216| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4606| 216| return true; 4607| 216| } 4608| | 4609| | // FIXME: Sometimes the fill expr is 'nop' if it isn't supplied, instead of 0. 4610| 275| getStreamer().EmitFill(NumBytes, FillExpr); 4611| | 4612| 275| return false; 4613| 491|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseDirectiveFileEN7llvm_ks5SMLocE: 3288| 681|{ 3289| | // FIXME: I'm not sure what this is. 3290| 681| int64_t FileNumber = -1; 3291| | //SMLoc FileNumberLoc = getLexer().getLoc(); 3292| 681| if (getLexer().is(AsmToken::Integer)) { ------------------ | Branch (3292:7): [True: 320, False: 361] ------------------ 3293| 320| bool valid; 3294| 320| FileNumber = getTok().getIntVal(valid); 3295| 320| if (!valid) { ------------------ | Branch (3295:9): [True: 0, False: 320] ------------------ 3296| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3297| 0| return true; 3298| 0| } 3299| 320| Lex(); 3300| | 3301| 320| if (FileNumber < 1) { ------------------ | Branch (3301:9): [True: 62, False: 258] ------------------ 3302| | //return TokError("file number less than one"); 3303| 62| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3304| 62| return true; 3305| 62| } 3306| 320| } 3307| | 3308| 619| if (getLexer().isNot(AsmToken::String)) { ------------------ | Branch (3308:7): [True: 281, False: 338] ------------------ 3309| | //return TokError("unexpected token in '.file' directive"); 3310| 281| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 3311| 281| return true; 3312| 281| } 3313| | 3314| | // Usually the directory and filename together, otherwise just the directory. 3315| | // Allow the strings to have escaped octal character sequence. 3316| 338| std::string Path = getTok().getString(); 3317| 338| if (parseEscapedString(Path)) ------------------ | Branch (3317:7): [True: 24, False: 314] ------------------ 3318| 24| return true; 3319| 314| Lex(); 3320| | 3321| 314| StringRef Directory; 3322| 314| StringRef Filename; 3323| 314| std::string FilenameData; 3324| 314| if (getLexer().is(AsmToken::String)) { ------------------ | Branch (3324:7): [True: 6, False: 308] ------------------ 3325| 6| if (FileNumber == -1) ------------------ | Branch (3325:9): [True: 0, False: 6] ------------------ 3326| | //return TokError("explicit path specified, but no file number"); 3327| 0| return true; 3328| 6| if (parseEscapedString(FilenameData)) ------------------ | Branch (3328:9): [True: 1, False: 5] ------------------ 3329| 1| return true; 3330| 5| Filename = FilenameData; 3331| 5| Directory = Path; 3332| 5| Lex(); 3333| 308| } else { 3334| 308| Filename = Path; 3335| 308| } 3336| | 3337| 313| if (getLexer().isNot(AsmToken::EndOfStatement)) ------------------ | Branch (3337:7): [True: 10, False: 303] ------------------ 3338| | //return TokError("unexpected token in '.file' directive"); 3339| 10| return true; 3340| | 3341| 303| if (FileNumber == -1) ------------------ | Branch (3341:7): [True: 303, False: 0] ------------------ 3342| 303| getStreamer().EmitFileDirective(Filename); 3343| 0| else { 3344| 0| if (getContext().getGenDwarfForAssembly()) ------------------ | Branch (3344:9): [True: 0, False: 0] ------------------ 3345| | //Error(DirectiveLoc, 3346| | // "input can't have .file dwarf directives when -g is " 3347| | // "used to generate dwarf debug info for assembly code"); 3348| 0| return true; 3349| | 3350| 0| if (getStreamer().EmitDwarfFileDirective(FileNumber, Directory, Filename) == ------------------ | Branch (3350:9): [True: 0, False: 0] ------------------ 3351| 0| 0) 3352| | //Error(FileNumberLoc, "file number already allocated"); 3353| 0| return true; 3354| 0| } 3355| | 3356| 303| return false; 3357| 303|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveMacroEN7llvm_ks5SMLocE: 4166| 217|{ 4167| 217| StringRef Name; 4168| 217| if (parseIdentifier(Name)) { ------------------ | Branch (4168:7): [True: 1, False: 216] ------------------ 4169| | //return TokError("expected identifier in '.macro' directive"); 4170| 1| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4171| 1| return true; 4172| 1| } 4173| | 4174| 216| if (getLexer().is(AsmToken::Comma)) ------------------ | Branch (4174:7): [True: 211, False: 5] ------------------ 4175| 211| Lex(); 4176| | 4177| 216| MCAsmMacroParameters Parameters; 4178| 2.05k| while (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (4178:10): [True: 1.83k, False: 216] ------------------ 4179| | 4180| 1.83k| if (!Parameters.empty() && Parameters.back().Vararg) { ------------------ | Branch (4180:9): [True: 1.61k, False: 216] | Branch (4180:32): [True: 0, False: 1.61k] ------------------ 4181| | //return Error(Lexer.getLoc(), 4182| | // "Vararg parameter '" + Parameters.back().Name + 4183| | // "' should be last one in the list of parameters."); 4184| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4185| 0| return true; 4186| 0| } 4187| | 4188| 1.83k| MCAsmMacroParameter Parameter; 4189| 1.83k| if (parseIdentifier(Parameter.Name)) { ------------------ | Branch (4189:9): [True: 0, False: 1.83k] ------------------ 4190| | //return TokError("expected identifier in '.macro' directive"); 4191| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4192| 0| return true; 4193| 0| } 4194| | 4195| 1.83k| if (Lexer.is(AsmToken::Colon)) { ------------------ | Branch (4195:9): [True: 0, False: 1.83k] ------------------ 4196| 0| Lex(); // consume ':' 4197| | 4198| 0| SMLoc QualLoc; 4199| 0| StringRef Qualifier; 4200| | 4201| 0| QualLoc = Lexer.getLoc(); 4202| 0| if (parseIdentifier(Qualifier)) { ------------------ | Branch (4202:11): [True: 0, False: 0] ------------------ 4203| | //return Error(QualLoc, "missing parameter qualifier for " 4204| | // "'" + Parameter.Name + "' in macro '" + Name + "'"); 4205| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4206| 0| return true; 4207| 0| } 4208| | 4209| 0| if (Qualifier == "req") ------------------ | Branch (4209:11): [True: 0, False: 0] ------------------ 4210| 0| Parameter.Required = true; 4211| 0| else if (Qualifier == "vararg") ------------------ | Branch (4211:16): [True: 0, False: 0] ------------------ 4212| 0| Parameter.Vararg = true; 4213| 0| else { 4214| | //return Error(QualLoc, Qualifier + " is not a valid parameter qualifier " 4215| | // "for '" + Parameter.Name + "' in macro '" + Name + "'"); 4216| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4217| 0| return true; 4218| 0| } 4219| 0| } 4220| | 4221| 1.83k| if (getLexer().is(AsmToken::Equal)) { ------------------ | Branch (4221:9): [True: 85, False: 1.75k] ------------------ 4222| 85| Lex(); 4223| | 4224| 85| SMLoc ParamLoc; 4225| | 4226| 85| ParamLoc = Lexer.getLoc(); 4227| 85| if (parseMacroArgument(Parameter.Value, /*Vararg=*/false )) { ------------------ | Branch (4227:11): [True: 0, False: 85] ------------------ 4228| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4229| 0| return true; 4230| 0| } 4231| | 4232| 85| if (Parameter.Required) ------------------ | Branch (4232:11): [True: 0, False: 85] ------------------ 4233| 0| Warning(ParamLoc, "pointless default value for required parameter " 4234| 0| "'" + Parameter.Name + "' in macro '" + Name + "'"); 4235| 85| } 4236| | 4237| 1.83k| Parameters.push_back(std::move(Parameter)); 4238| | 4239| 1.83k| if (getLexer().is(AsmToken::Comma)) ------------------ | Branch (4239:9): [True: 672, False: 1.16k] ------------------ 4240| 672| Lex(); 4241| 1.83k| } 4242| | 4243| | // Eat the end of statement. 4244| 216| Lex(); 4245| | 4246| 216| AsmToken EndToken, StartToken = getTok(); 4247| 216| unsigned MacroDepth = 0; 4248| | 4249| | // Lex the macro definition. 4250| 588| for (;;) { 4251| | // Check whether we have reached the end of the file. 4252| 588| if (getLexer().is(AsmToken::Eof)) { ------------------ | Branch (4252:9): [True: 3, False: 585] ------------------ 4253| | //return Error(DirectiveLoc, "no matching '.endmacro' in definition"); 4254| 3| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4255| 3| return true; 4256| 3| } 4257| | 4258| | // Otherwise, check whether we have reach the .endmacro. 4259| 585| if (getLexer().is(AsmToken::Identifier)) { ------------------ | Branch (4259:9): [True: 270, False: 315] ------------------ 4260| 270| if (getTok().getIdentifier() == ".endm" || ------------------ | Branch (4260:11): [True: 213, False: 57] | Branch (4260:11): [True: 213, False: 57] ------------------ 4261| 213| getTok().getIdentifier() == ".endmacro") { ------------------ | Branch (4261:11): [True: 0, False: 57] ------------------ 4262| 213| if (MacroDepth == 0) { // Outermost macro. ------------------ | Branch (4262:13): [True: 213, False: 0] ------------------ 4263| 213| EndToken = getTok(); 4264| 213| Lex(); 4265| 213| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (4265:15): [True: 0, False: 213] ------------------ 4266| | //return TokError("unexpected token in '" + EndToken.getIdentifier() + 4267| | // "' directive"); 4268| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4269| 0| return true; 4270| 0| } 4271| 213| break; 4272| 213| } else { 4273| | // Otherwise we just found the end of an inner macro. 4274| 0| --MacroDepth; 4275| 0| } 4276| 213| } else if (getTok().getIdentifier() == ".macro") { ------------------ | Branch (4276:18): [True: 1, False: 56] ------------------ 4277| | // We allow nested macros. Those aren't instantiated until the outermost 4278| | // macro is expanded so just ignore them for now. 4279| 1| ++MacroDepth; 4280| 1| } 4281| 270| } 4282| | 4283| | // Otherwise, scan til the end of the statement. 4284| 372| eatToEndOfStatement(); 4285| 372| } 4286| | 4287| 213| if (lookupMacro(Name)) { ------------------ | Branch (4287:7): [True: 198, False: 15] ------------------ 4288| | //return Error(DirectiveLoc, "macro '" + Name + "' is already defined"); 4289| 198| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4290| 198| return true; 4291| 198| } 4292| | 4293| 15| const char *BodyStart = StartToken.getLoc().getPointer(); 4294| 15| const char *BodyEnd = EndToken.getLoc().getPointer(); 4295| 15| StringRef Body = StringRef(BodyStart, BodyEnd - BodyStart); 4296| 15| checkForBadMacro(DirectiveLoc, Name, Body, Parameters); 4297| 15| defineMacro(Name, MCAsmMacro(Name, Body, std::move(Parameters))); 4298| 15| return false; 4299| 213|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser16checkForBadMacroEN7llvm_ks5SMLocENS1_9StringRefES3_NS1_8ArrayRefINS_19MCAsmMacroParameterEEE: 4317| 15| ArrayRef Parameters) { 4318| | // If this macro is not defined with named parameters the warning we are 4319| | // checking for here doesn't apply. 4320| 15| unsigned NParameters = Parameters.size(); 4321| 15| if (NParameters == 0) ------------------ | Branch (4321:7): [True: 0, False: 15] ------------------ 4322| 0| return; 4323| | 4324| 15| bool NamedParametersFound = false; 4325| 15| bool PositionalParametersFound = false; 4326| | 4327| | // Look at the body of the macro for use of both the named parameters and what 4328| | // are likely to be positional parameters. This is what expandMacro() is 4329| | // doing when it finds the parameters in the body. 4330| 3.00k| while (!Body.empty()) { ------------------ | Branch (4330:10): [True: 2.99k, False: 6] ------------------ 4331| | // Scan for the next possible parameter. 4332| 2.99k| std::size_t End = Body.size(), Pos = 0; 4333| 10.2k| for (; Pos != End; ++Pos) { ------------------ | Branch (4333:12): [True: 10.2k, False: 9] ------------------ 4334| | // Check for a substitution or escape. 4335| | // This macro is defined with parameters, look for \foo, \bar, etc. 4336| 10.2k| if (Body[Pos] == '\\' && Pos + 1 != End) ------------------ | Branch (4336:11): [True: 2.69k, False: 7.59k] | Branch (4336:32): [True: 2.69k, False: 0] ------------------ 4337| 2.69k| break; 4338| | 4339| | // This macro should have parameters, but look for $0, $1, ..., $n too. 4340| 7.59k| if (Body[Pos] != '$' || Pos + 1 == End) ------------------ | Branch (4340:11): [True: 6.83k, False: 753] | Branch (4340:31): [True: 0, False: 753] ------------------ 4341| 6.83k| continue; 4342| 753| char Next = Body[Pos + 1]; 4343| 753| if (Next == '$' || Next == 'n' || ------------------ | Branch (4343:11): [True: 4, False: 749] | Branch (4343:26): [True: 282, False: 467] ------------------ 4344| 467| isdigit(static_cast(Next))) ------------------ | Branch (4344:11): [True: 4, False: 463] ------------------ 4345| 290| break; 4346| 753| } 4347| | 4348| | // Check if we reached the end. 4349| 2.99k| if (Pos == End) ------------------ | Branch (4349:9): [True: 9, False: 2.98k] ------------------ 4350| 9| break; 4351| | 4352| 2.98k| if (Body[Pos] == '$') { ------------------ | Branch (4352:9): [True: 290, False: 2.69k] ------------------ 4353| 290| switch (Body[Pos + 1]) { 4354| | // $$ => $ 4355| 4| case '$': ------------------ | Branch (4355:7): [True: 4, False: 286] ------------------ 4356| 4| break; 4357| | 4358| | // $n => number of arguments 4359| 282| case 'n': ------------------ | Branch (4359:7): [True: 282, False: 8] ------------------ 4360| 282| PositionalParametersFound = true; 4361| 282| break; 4362| | 4363| | // $[0-9] => argument 4364| 4| default: { ------------------ | Branch (4364:7): [True: 4, False: 286] ------------------ 4365| 4| PositionalParametersFound = true; 4366| 4| break; 4367| 0| } 4368| 290| } 4369| 290| Pos += 2; 4370| 2.69k| } else { 4371| 2.69k| unsigned I = Pos + 1; 4372| 6.01k| while (isIdentifierChar(Body[I]) && I + 1 != End) ------------------ | Branch (4372:14): [True: 3.31k, False: 2.69k] | Branch (4372:43): [True: 3.31k, False: 0] ------------------ 4373| 3.31k| ++I; 4374| | 4375| 2.69k| const char *Begin = Body.data() + Pos + 1; 4376| 2.69k| StringRef Argument(Begin, I - (Pos + 1)); 4377| 2.69k| unsigned Index = 0; 4378| 6.51k| for (; Index < NParameters; ++Index) ------------------ | Branch (4378:14): [True: 3.85k, False: 2.65k] ------------------ 4379| 3.85k| if (Parameters[Index].Name == Argument) ------------------ | Branch (4379:13): [True: 38, False: 3.82k] ------------------ 4380| 38| break; 4381| | 4382| 2.69k| if (Index == NParameters) { ------------------ | Branch (4382:11): [True: 2.65k, False: 38] ------------------ 4383| 2.65k| if (Body[Pos + 1] == '(' && Body[Pos + 2] == ')') ------------------ | Branch (4383:13): [True: 269, False: 2.38k] | Branch (4383:37): [True: 36, False: 233] ------------------ 4384| 36| Pos += 3; 4385| 2.62k| else { 4386| 2.62k| Pos = I; 4387| 2.62k| } 4388| 2.65k| } else { 4389| 38| NamedParametersFound = true; 4390| 38| Pos += 1 + Argument.size(); 4391| 38| } 4392| 2.69k| } 4393| | // Update the scan point. 4394| 2.98k| Body = Body.substr(Pos); 4395| 2.98k| } 4396| | 4397| 15| if (!NamedParametersFound && PositionalParametersFound) ------------------ | Branch (4397:7): [True: 11, False: 4] | Branch (4397:32): [True: 0, False: 11] ------------------ 4398| 0| Warning(DirectiveLoc, "macro defined with named parameters which are not " 4399| 0| "used in macro body, possible positional parameter " 4400| 0| "found in body which will have no effect"); 4401| 15|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser11defineMacroEN7llvm_ks9StringRefENS_10MCAsmMacroE: 2451| 15|void AsmParser::defineMacro(StringRef Name, MCAsmMacro Macro) { 2452| 15| MacroMap.insert(std::make_pair(Name, std::move(Macro))); 2453| 15|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser26isInsideMacroInstantiationEv: 297| 32| bool isInsideMacroInstantiation() {return !ActiveMacros.empty();} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser22parseDirectiveEndMacroEN7llvm_ks9StringRefE: 4434| 32|{ 4435| 32| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (4435:7): [True: 0, False: 32] ------------------ 4436| | //return TokError("unexpected token in '" + Directive + "' directive"); 4437| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4438| 0| return true; 4439| 0| } 4440| | 4441| | // If we are inside a macro instantiation, terminate the current 4442| | // instantiation. 4443| 32| if (isInsideMacroInstantiation()) { ------------------ | Branch (4443:7): [True: 20, False: 12] ------------------ 4444| 20| handleMacroExit(); 4445| 20| return false; 4446| 20| } 4447| | 4448| | // Otherwise, this .endmacro is a stray entry in the file; well formed 4449| | // .endmacro directives are handled during the macro definition parsing. 4450| | //return TokError("unexpected '" + Directive + "' in file, " 4451| | // "no current macro definition"); 4452| 12| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 4453| 12| return true; 4454| 32|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveErrorEN7llvm_ks5SMLocEb: 5206| 26|{ 5207| 26| if (!TheCondStack.empty()) { ------------------ | Branch (5207:7): [True: 19, False: 7] ------------------ 5208| 19| if (TheCondStack.back().Ignore) { ------------------ | Branch (5208:9): [True: 0, False: 19] ------------------ 5209| 0| eatToEndOfStatement(); 5210| 0| return false; 5211| 0| } 5212| 19| } 5213| | 5214| 26| if (!WithMessage) { ------------------ | Branch (5214:7): [True: 6, False: 20] ------------------ 5215| | //return Error(L, ".err encountered"); 5216| 6| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5217| 6| return true; 5218| 6| } 5219| | 5220| 20| StringRef Message = ".error directive invoked in source file"; 5221| 20| if (Lexer.isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (5221:7): [True: 20, False: 0] ------------------ 5222| 20| if (Lexer.isNot(AsmToken::String)) { ------------------ | Branch (5222:9): [True: 20, False: 0] ------------------ 5223| | //TokError(".error argument must be a string"); 5224| 20| eatToEndOfStatement(); 5225| 20| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5226| 20| return true; 5227| 20| } 5228| | 5229| 0| bool valid; 5230| 0| Message = getTok().getStringContents(valid); 5231| 0| if (!valid) { ------------------ | Branch (5231:9): [True: 0, False: 0] ------------------ 5232| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5233| 0| return true; 5234| 0| } 5235| 0| Lex(); 5236| 0| } 5237| | 5238| | //Error(L, Message); 5239| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 5240| 0| return true; 5241| 20|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parseDirectiveRelocEN7llvm_ks5SMLocE: 2734| 1|{ 2735| 1| const MCExpr *Offset; 2736| 1| const MCExpr *Expr = nullptr; 2737| | 2738| | //SMLoc OffsetLoc = Lexer.getTok().getLoc(); 2739| 1| if (parseExpression(Offset)) { ------------------ | Branch (2739:7): [True: 0, False: 1] ------------------ 2740| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2741| 0| return true; 2742| 0| } 2743| | 2744| | // We can only deal with constant expressions at the moment. 2745| 1| int64_t OffsetValue; 2746| 1| if (!Offset->evaluateAsAbsolute(OffsetValue)) { ------------------ | Branch (2746:7): [True: 0, False: 1] ------------------ 2747| | //return Error(OffsetLoc, "expression is not a constant value"); 2748| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2749| 0| return true; 2750| 0| } 2751| | 2752| 1| if (OffsetValue < 0) { ------------------ | Branch (2752:7): [True: 0, False: 1] ------------------ 2753| | //return Error(OffsetLoc, "expression is negative"); 2754| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2755| 0| return true; 2756| 0| } 2757| | 2758| 1| if (Lexer.isNot(AsmToken::Comma)) { ------------------ | Branch (2758:7): [True: 1, False: 0] ------------------ 2759| | // return TokError("expected comma"); 2760| 1| KsError = KS_ERR_ASM_DIRECTIVE_COMMA; 2761| 1| return true; 2762| 1| } 2763| 0| Lexer.Lex(); 2764| | 2765| 0| if (Lexer.isNot(AsmToken::Identifier)) { ------------------ | Branch (2765:7): [True: 0, False: 0] ------------------ 2766| | // return TokError("expected relocation name"); 2767| 0| KsError = KS_ERR_ASM_DIRECTIVE_RELOC_NAME; 2768| 0| return true; 2769| 0| } 2770| | //SMLoc NameLoc = Lexer.getTok().getLoc(); 2771| 0| StringRef Name = Lexer.getTok().getIdentifier(); 2772| 0| Lexer.Lex(); 2773| | 2774| 0| if (Lexer.is(AsmToken::Comma)) { ------------------ | Branch (2774:7): [True: 0, False: 0] ------------------ 2775| 0| Lexer.Lex(); 2776| | //SMLoc ExprLoc = Lexer.getLoc(); 2777| 0| if (parseExpression(Expr)) { ------------------ | Branch (2777:9): [True: 0, False: 0] ------------------ 2778| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2779| 0| return true; 2780| 0| } 2781| | 2782| 0| MCValue Value; 2783| 0| if (!Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) { ------------------ | Branch (2783:9): [True: 0, False: 0] ------------------ 2784| | //return Error(ExprLoc, "expression must be relocatable"); 2785| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2786| 0| return true; 2787| 0| } 2788| 0| } 2789| | 2790| 0| if (Lexer.isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (2790:7): [True: 0, False: 0] ------------------ 2791| | // return TokError("unexpected token in .reloc directive"); 2792| 0| KsError = KS_ERR_ASM_DIRECTIVE_RELOC_TOKEN; 2793| 0| return true; 2794| 0| } 2795| | 2796| 0| if (getStreamer().EmitRelocDirective(*Offset, Name, Expr, DirectiveLoc)) { ------------------ | Branch (2796:7): [True: 0, False: 0] ------------------ 2797| | //return Error(NameLoc, "unknown relocation name"); 2798| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2799| 0| return true; 2800| 0| } 2801| | 2802| 0| return false; 2803| 0|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser4NoteEN7llvm_ks5SMLocERKNS1_5TwineENS1_8ArrayRefINS1_7SMRangeEEE: 600| 1.24k|void AsmParser::Note(SMLoc L, const Twine &Msg, ArrayRef Ranges) { 601| 1.24k| printMessage(L, SourceMgr::DK_Note, Msg, Ranges); 602| 1.24k| printMacroInstantiations(); 603| 1.24k|} AsmParser.cpp:_ZNK12_GLOBAL__N_19AsmParser12printMessageEN7llvm_ks5SMLocENS1_9SourceMgr8DiagKindERKNS1_5TwineENS1_8ArrayRefINS1_7SMRangeEEE: 316| 2.06k| ArrayRef Ranges = None) const { 317| 2.06k| SrcMgr.PrintMessage(Loc, Kind, Msg, Ranges); 318| 2.06k| } AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser24printMacroInstantiationsEv: 590| 2.06k|void AsmParser::printMacroInstantiations() { 591| | // Print the active macro instantiation stack. 592| 2.06k| for (std::vector::const_reverse_iterator 593| 2.06k| it = ActiveMacros.rbegin(), 594| 2.06k| ie = ActiveMacros.rend(); 595| 2.06k| it != ie; ++it) ------------------ | Branch (595:8): [True: 0, False: 2.06k] ------------------ 596| 0| printMessage((*it)->InstantiationLoc, SourceMgr::DK_Note, 597| 0| "while in macro instantiation"); 598| 2.06k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser7WarningEN7llvm_ks5SMLocERKNS1_5TwineENS1_8ArrayRefINS1_7SMRangeEEE: 605| 815|bool AsmParser::Warning(SMLoc L, const Twine &Msg, ArrayRef Ranges) { 606| 815| if(getTargetParser().getTargetOptions().MCNoWarn) ------------------ | Branch (606:6): [True: 0, False: 815] ------------------ 607| 0| return false; 608| 815| if (getTargetParser().getTargetOptions().MCFatalWarnings) ------------------ | Branch (608:7): [True: 0, False: 815] ------------------ 609| 0| return Error(L, Msg, Ranges); 610| 815| printMessage(L, SourceMgr::DK_Warning, Msg, Ranges); 611| 815| printMacroInstantiations(); 612| 815| return false; 613| 815|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser5ErrorEN7llvm_ks5SMLocERKNS1_5TwineENS1_8ArrayRefINS1_7SMRangeEEE: 615| 10|bool AsmParser::Error(SMLoc L, const Twine &Msg, ArrayRef Ranges) { 616| 10| HadError = true; 617| 10| printMessage(L, SourceMgr::DK_Error, Msg, Ranges); 618| 10| printMacroInstantiations(); 619| 10| return true; 620| 10|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser3LexEv: 655| 252k|const AsmToken &AsmParser::Lex() { 656| 252k| const AsmToken *tok = &Lexer.Lex(); 657| | 658| 252k| if (tok->is(AsmToken::Eof)) { ------------------ | Branch (658:7): [True: 359, False: 252k] ------------------ 659| | // If this is the end of an included file, pop the parent file off the 660| | // include stack. 661| 359| SMLoc ParentIncludeLoc = SrcMgr.getParentIncludeLoc(CurBuffer); 662| 359| if (ParentIncludeLoc != SMLoc()) { ------------------ | Branch (662:9): [True: 0, False: 359] ------------------ 663| 0| jumpToLoc(ParentIncludeLoc); 664| 0| tok = &Lexer.Lex(); // qq 665| 0| } 666| 359| } 667| | 668| | //if (tok->is(AsmToken::Error)) 669| | // Error(Lexer.getErrLoc(), Lexer.getErr()); 670| | 671| 252k| return *tok; 672| 252k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser15parseIdentifierERN7llvm_ks9StringRefE: 2549| 40.8k|{ 2550| | // The assembler has relaxed rules for accepting identifiers, in particular we 2551| | // allow things like '.globl $foo' and '.def @feat.00', which would normally be 2552| | // separate tokens. At this level, we have already lexed so we cannot (currently) 2553| | // handle this as a context dependent token, instead we detect adjacent tokens 2554| | // and return the combined identifier. 2555| 40.8k| if (Lexer.is(AsmToken::Dollar) || Lexer.is(AsmToken::At)) { ------------------ | Branch (2555:7): [True: 7, False: 40.8k] | Branch (2555:37): [True: 0, False: 40.8k] ------------------ 2556| 7| SMLoc PrefixLoc = getLexer().getLoc(); 2557| | 2558| | // Consume the prefix character, and check for a following identifier. 2559| 7| Lex(); 2560| 7| if (Lexer.isNot(AsmToken::Identifier)) { ------------------ | Branch (2560:9): [True: 6, False: 1] ------------------ 2561| 6| KsError = KS_ERR_ASM_MACRO_INVALID; 2562| 6| return true; 2563| 6| } 2564| | 2565| | // We have a '$' or '@' followed by an identifier, make sure they are adjacent. 2566| 1| if (PrefixLoc.getPointer() + 1 != getTok().getLoc().getPointer()) { ------------------ | Branch (2566:9): [True: 0, False: 1] ------------------ 2567| 0| KsError = KS_ERR_ASM_MACRO_INVALID; 2568| 0| return true; 2569| 0| } 2570| | 2571| | // Construct the joined identifier and consume the token. 2572| 1| Res = 2573| 1| StringRef(PrefixLoc.getPointer(), getTok().getIdentifier().size() + 1); 2574| 1| Lex(); 2575| 1| return false; 2576| 1| } 2577| | 2578| 40.8k| if (Lexer.isNot(AsmToken::Identifier) && Lexer.isNot(AsmToken::String)) { ------------------ | Branch (2578:7): [True: 1.38k, False: 39.4k] | Branch (2578:44): [True: 760, False: 628] ------------------ 2579| 760| KsError = KS_ERR_ASM_MACRO_INVALID; 2580| 760| return true; 2581| 760| } 2582| | 2583| 40.0k| Res = getTok().getIdentifier(); 2584| | 2585| 40.0k| Lex(); // Consume the identifier token. 2586| | 2587| 40.0k| return false; 2588| 40.8k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser27parseStringToEndOfStatementEv: 792| 3.23k|StringRef AsmParser::parseStringToEndOfStatement() { 793| 3.23k| const char *Start = getTok().getLoc().getPointer(); 794| | 795| 17.5k| while (Lexer.isNot(AsmToken::EndOfStatement) && Lexer.isNot(AsmToken::Eof)) ------------------ | Branch (795:10): [True: 14.3k, False: 3.23k] | Branch (795:51): [True: 14.3k, False: 0] ------------------ 796| 14.3k| Lex(); 797| | 798| 3.23k| const char *End = getTok().getLoc().getPointer(); 799| 3.23k| return StringRef(Start, End - Start); 800| 3.23k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18parseEscapedStringERNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE: 2614| 531|{ 2615| 531| if (!getLexer().is(AsmToken::String)) { ------------------ | Branch (2615:7): [True: 0, False: 531] ------------------ 2616| 0| KsError = KS_ERR_ASM_ESC_STR; 2617| 0| return true; 2618| 0| } 2619| | 2620| 531| Data = ""; 2621| 531| bool valid; 2622| 531| StringRef Str = getTok().getStringContents(valid); 2623| 531| if (!valid) { ------------------ | Branch (2623:7): [True: 0, False: 531] ------------------ 2624| 0| KsError = KS_ERR_ASM_DIRECTIVE_INVALID; 2625| 0| return true; 2626| 0| } 2627| | 2628| 32.8k| for (unsigned i = 0, e = Str.size(); i != e; ++i) { ------------------ | Branch (2628:40): [True: 32.3k, False: 494] ------------------ 2629| 32.3k| if (Str[i] != '\\') { ------------------ | Branch (2629:9): [True: 28.5k, False: 3.85k] ------------------ 2630| 28.5k| Data += Str[i]; 2631| 28.5k| continue; 2632| 28.5k| } 2633| | 2634| | // Recognize escaped characters. Note that this escape semantics currently 2635| | // loosely follows Darwin 'as'. Notably, it doesn't support hex escapes. 2636| 3.85k| ++i; 2637| 3.85k| if (i == e) { ------------------ | Branch (2637:9): [True: 0, False: 3.85k] ------------------ 2638| | // return TokError("unexpected backslash at end of string"); 2639| 0| KsError = KS_ERR_ASM_ESC_BACKSLASH; 2640| 0| return true; 2641| 0| } 2642| | 2643| | // Recognize octal sequences. 2644| 3.85k| if ((unsigned)(Str[i] - '0') <= 7) { ------------------ | Branch (2644:9): [True: 1.40k, False: 2.44k] ------------------ 2645| | // Consume up to three octal characters. 2646| 1.40k| unsigned Value = Str[i] - '0'; 2647| | 2648| 1.40k| if (i + 1 != e && ((unsigned)(Str[i + 1] - '0')) <= 7) { ------------------ | Branch (2648:11): [True: 1.39k, False: 8] | Branch (2648:25): [True: 942, False: 456] ------------------ 2649| 942| ++i; 2650| 942| Value = Value * 8 + (Str[i] - '0'); 2651| | 2652| 942| if (i + 1 != e && ((unsigned)(Str[i + 1] - '0')) <= 7) { ------------------ | Branch (2652:13): [True: 887, False: 55] | Branch (2652:27): [True: 256, False: 631] ------------------ 2653| 256| ++i; 2654| 256| Value = Value * 8 + (Str[i] - '0'); 2655| 256| } 2656| 942| } 2657| | 2658| 1.40k| if (Value > 255) { ------------------ | Branch (2658:11): [True: 17, False: 1.38k] ------------------ 2659| | // return TokError("invalid octal escape sequence (out of range)"); 2660| 17| KsError = KS_ERR_ASM_ESC_BACKSLASH; 2661| 17| return true; 2662| 17| } 2663| | 2664| 1.38k| Data += (unsigned char)Value; 2665| 1.38k| continue; 2666| 1.40k| } 2667| | 2668| | // Otherwise recognize individual escapes. 2669| 2.44k| switch (Str[i]) { 2670| 20| default: ------------------ | Branch (2670:5): [True: 20, False: 2.42k] ------------------ 2671| | // Just reject invalid escape sequences for now. 2672| | // return TokError("invalid escape sequence (unrecognized character)"); 2673| 20| KsError = KS_ERR_ASM_ESC_SEQUENCE; 2674| 20| return true; 2675| | 2676| 427| case 'b': Data += '\b'; break; ------------------ | Branch (2676:5): [True: 427, False: 2.02k] ------------------ 2677| 51| case 'f': Data += '\f'; break; ------------------ | Branch (2677:5): [True: 51, False: 2.39k] ------------------ 2678| 62| case 'n': Data += '\n'; break; ------------------ | Branch (2678:5): [True: 62, False: 2.38k] ------------------ 2679| 136| case 'r': Data += '\r'; break; ------------------ | Branch (2679:5): [True: 136, False: 2.31k] ------------------ 2680| 560| case 't': Data += '\t'; break; ------------------ | Branch (2680:5): [True: 560, False: 1.88k] ------------------ 2681| 453| case '"': Data += '"'; break; ------------------ | Branch (2681:5): [True: 453, False: 1.99k] ------------------ 2682| 738| case '\\': Data += '\\'; break; ------------------ | Branch (2682:5): [True: 738, False: 1.70k] ------------------ 2683| 2.44k| } 2684| 2.44k| } 2685| | 2686| 494| return false; 2687| 531|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19eatToEndOfStatementEv: 783| 5.68k|{ 784| 36.5k| while (Lexer.isNot(AsmToken::EndOfStatement) && Lexer.isNot(AsmToken::Eof)) ------------------ | Branch (784:10): [True: 30.9k, False: 5.67k] | Branch (784:51): [True: 30.9k, False: 6] ------------------ 785| 30.9k| Lex(); 786| | 787| | // Eat EOL. 788| 5.68k| if (Lexer.is(AsmToken::EndOfStatement)) ------------------ | Branch (788:7): [True: 5.67k, False: 6] ------------------ 789| 5.67k| Lex(); 790| 5.68k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser15parseExpressionERPKN7llvm_ks6MCExprERNS1_5SMLocE: 1145| 68.4k|bool AsmParser::parseExpression(const MCExpr *&Res, SMLoc &EndLoc) { 1146| | // Parse the expression. 1147| 68.4k| Res = nullptr; 1148| 68.4k| if (parsePrimaryExpr(Res, EndLoc) || parseBinOpRHS(1, Res, EndLoc)) ------------------ | Branch (1148:7): [True: 44.8k, False: 23.6k] | Branch (1148:40): [True: 196, False: 23.4k] ------------------ 1149| 45.0k| return true; 1150| | 1151| | // As a special case, we support 'a op b @ modifier' by rewriting the 1152| | // expression to include the modifier. This is inefficient, but in general we 1153| | // expect users to use 'a@modifier op b'. 1154| 23.4k| if (Lexer.getKind() == AsmToken::At) { ------------------ | Branch (1154:7): [True: 0, False: 23.4k] ------------------ 1155| 0| Lex(); 1156| | 1157| 0| if (Lexer.isNot(AsmToken::Identifier)) { ------------------ | Branch (1157:9): [True: 0, False: 0] ------------------ 1158| | // return TokError("unexpected symbol modifier following '@'"); 1159| 0| KsError = KS_ERR_ASM_SYMBOL_MODIFIER; 1160| 0| return true; 1161| 0| } 1162| | 1163| 0| MCSymbolRefExpr::VariantKind Variant = 1164| 0| MCSymbolRefExpr::getVariantKindForName(getTok().getIdentifier()); 1165| 0| if (Variant == MCSymbolRefExpr::VK_Invalid) { ------------------ | Branch (1165:9): [True: 0, False: 0] ------------------ 1166| | // return TokError("invalid variant '" + getTok().getIdentifier() + "'"); 1167| 0| KsError = KS_ERR_ASM_VARIANT_INVALID; 1168| 0| return true; 1169| 0| } 1170| | 1171| 0| const MCExpr *ModifiedRes = applyModifierToExpr(Res, Variant); 1172| 0| if (!ModifiedRes) { ------------------ | Branch (1172:9): [True: 0, False: 0] ------------------ 1173| | // return TokError("invalid modifier '" + getTok().getIdentifier() + 1174| | // "' (no symbols present)"); 1175| 0| KsError = KS_ERR_ASM_VARIANT_INVALID; 1176| 0| return true; 1177| 0| } 1178| | 1179| 0| Res = ModifiedRes; 1180| 0| Lex(); 1181| 0| } 1182| | 1183| | // Try to constant fold it up front, if possible. 1184| 23.4k| int64_t Value; 1185| 23.4k| if (Res->evaluateAsAbsolute(Value)) ------------------ | Branch (1185:7): [True: 6.34k, False: 17.1k] ------------------ 1186| 6.34k| Res = MCConstantExpr::create(Value, getContext()); 1187| | 1188| 23.4k| return false; 1189| 23.4k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser13parseBinOpRHSEjRPKN7llvm_ks6MCExprERNS1_5SMLocE: 1400| 23.7k| SMLoc &EndLoc) { 1401| 26.9k| while (1) { ------------------ | Branch (1401:10): [True: 26.9k, Folded] ------------------ 1402| 26.9k| MCBinaryExpr::Opcode Kind = MCBinaryExpr::Add; 1403| 26.9k| unsigned TokPrec = getBinOpPrecedence(Lexer.getKind(), Kind); 1404| | 1405| | // If the next token is lower precedence than we are allowed to eat, return 1406| | // successfully with what we ate already. 1407| 26.9k| if (TokPrec < Precedence) ------------------ | Branch (1407:9): [True: 23.5k, False: 3.33k] ------------------ 1408| 23.5k| return false; 1409| | 1410| 3.33k| Lex(); 1411| | 1412| | // Eat the next primary expression. 1413| 3.33k| const MCExpr *RHS; 1414| 3.33k| if (parsePrimaryExpr(RHS, EndLoc)) ------------------ | Branch (1414:9): [True: 196, False: 3.13k] ------------------ 1415| 196| return true; 1416| | 1417| | // If BinOp binds less tightly with RHS than the operator after RHS, let 1418| | // the pending operator take RHS as its LHS. 1419| 3.13k| MCBinaryExpr::Opcode Dummy; 1420| 3.13k| unsigned NextTokPrec = getBinOpPrecedence(Lexer.getKind(), Dummy); 1421| 3.13k| if (TokPrec < NextTokPrec && parseBinOpRHS(TokPrec + 1, RHS, EndLoc)) ------------------ | Branch (1421:9): [True: 135, False: 3.00k] | Branch (1421:34): [True: 4, False: 131] ------------------ 1422| 4| return true; 1423| | 1424| | // Merge LHS and RHS according to operator. 1425| 3.13k| Res = MCBinaryExpr::create(Kind, Res, RHS, getContext()); 1426| 3.13k| } 1427| 23.7k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser18getBinOpPrecedenceEN7llvm_ks8AsmToken9TokenKindERNS1_12MCBinaryExpr6OpcodeE: 1391| 30.0k| MCBinaryExpr::Opcode &Kind) { 1392| 30.0k| bool ShouldUseLogicalShr = MAI.shouldUseLogicalShr(); 1393| 30.0k| return IsDarwin ? getDarwinBinOpPrecedence(K, Kind, ShouldUseLogicalShr) ------------------ | Branch (1393:10): [True: 30.0k, False: 0] ------------------ 1394| 30.0k| : getGNUBinOpPrecedence(K, Kind, ShouldUseLogicalShr); 1395| 30.0k|} AsmParser.cpp:_ZL24getDarwinBinOpPrecedenceN7llvm_ks8AsmToken9TokenKindERNS_12MCBinaryExpr6OpcodeEb: 1238| 30.0k| bool ShouldUseLogicalShr) { 1239| 30.0k| switch (K) { 1240| 24.4k| default: ------------------ | Branch (1240:3): [True: 24.4k, False: 5.59k] ------------------ 1241| 24.4k| return 0; // not a binop. 1242| | 1243| | // Lowest Precedence: &&, || 1244| 0| case AsmToken::AmpAmp: ------------------ | Branch (1244:3): [True: 0, False: 30.0k] ------------------ 1245| 0| Kind = MCBinaryExpr::LAnd; 1246| 0| return 1; 1247| 6| case AsmToken::PipePipe: ------------------ | Branch (1247:3): [True: 6, False: 30.0k] ------------------ 1248| 6| Kind = MCBinaryExpr::LOr; 1249| 6| return 1; 1250| | 1251| | // Low Precedence: |, &, ^ 1252| | // 1253| | // FIXME: gas seems to support '!' as an infix operator? 1254| 14| case AsmToken::Pipe: ------------------ | Branch (1254:3): [True: 14, False: 30.0k] ------------------ 1255| 14| Kind = MCBinaryExpr::Or; 1256| 14| return 2; 1257| 91| case AsmToken::Caret: ------------------ | Branch (1257:3): [True: 91, False: 29.9k] ------------------ 1258| 91| Kind = MCBinaryExpr::Xor; 1259| 91| return 2; 1260| 661| case AsmToken::Amp: ------------------ | Branch (1260:3): [True: 661, False: 29.4k] ------------------ 1261| 661| Kind = MCBinaryExpr::And; 1262| 661| return 2; 1263| | 1264| | // Low Intermediate Precedence: ==, !=, <>, <, <=, >, >= 1265| 136| case AsmToken::EqualEqual: ------------------ | Branch (1265:3): [True: 136, False: 29.9k] ------------------ 1266| 136| Kind = MCBinaryExpr::EQ; 1267| 136| return 3; 1268| 46| case AsmToken::ExclaimEqual: ------------------ | Branch (1268:3): [True: 46, False: 30.0k] ------------------ 1269| 46| case AsmToken::LessGreater: ------------------ | Branch (1269:3): [True: 0, False: 30.0k] ------------------ 1270| 46| Kind = MCBinaryExpr::NE; 1271| 46| return 3; 1272| 66| case AsmToken::Less: ------------------ | Branch (1272:3): [True: 66, False: 29.9k] ------------------ 1273| 66| Kind = MCBinaryExpr::LT; 1274| 66| return 3; 1275| 0| case AsmToken::LessEqual: ------------------ | Branch (1275:3): [True: 0, False: 30.0k] ------------------ 1276| 0| Kind = MCBinaryExpr::LTE; 1277| 0| return 3; 1278| 132| case AsmToken::Greater: ------------------ | Branch (1278:3): [True: 132, False: 29.9k] ------------------ 1279| 132| Kind = MCBinaryExpr::GT; 1280| 132| return 3; 1281| 0| case AsmToken::GreaterEqual: ------------------ | Branch (1281:3): [True: 0, False: 30.0k] ------------------ 1282| 0| Kind = MCBinaryExpr::GTE; 1283| 0| return 3; 1284| | 1285| | // Intermediate Precedence: <<, >> 1286| 0| case AsmToken::LessLess: ------------------ | Branch (1286:3): [True: 0, False: 30.0k] ------------------ 1287| 0| Kind = MCBinaryExpr::Shl; 1288| 0| return 4; 1289| 0| case AsmToken::GreaterGreater: ------------------ | Branch (1289:3): [True: 0, False: 30.0k] ------------------ 1290| 0| Kind = ShouldUseLogicalShr ? MCBinaryExpr::LShr : MCBinaryExpr::AShr; ------------------ | Branch (1290:12): [True: 0, False: 0] ------------------ 1291| 0| return 4; 1292| | 1293| | // High Intermediate Precedence: +, - 1294| 1.04k| case AsmToken::Plus: ------------------ | Branch (1294:3): [True: 1.04k, False: 29.0k] ------------------ 1295| 1.04k| Kind = MCBinaryExpr::Add; 1296| 1.04k| return 5; 1297| 1.74k| case AsmToken::Minus: ------------------ | Branch (1297:3): [True: 1.74k, False: 28.3k] ------------------ 1298| 1.74k| Kind = MCBinaryExpr::Sub; 1299| 1.74k| return 5; 1300| | 1301| | // Highest Precedence: *, /, % 1302| 341| case AsmToken::Star: ------------------ | Branch (1302:3): [True: 341, False: 29.7k] ------------------ 1303| 341| Kind = MCBinaryExpr::Mul; 1304| 341| return 6; 1305| 126| case AsmToken::Slash: ------------------ | Branch (1305:3): [True: 126, False: 29.9k] ------------------ 1306| 126| Kind = MCBinaryExpr::Div; 1307| 126| return 6; 1308| 1.18k| case AsmToken::Percent: ------------------ | Branch (1308:3): [True: 1.18k, False: 28.8k] ------------------ 1309| 1.18k| Kind = MCBinaryExpr::Mod; 1310| 1.18k| return 6; 1311| 30.0k| } 1312| 30.0k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser16parsePrimaryExprERPKN7llvm_ks6MCExprERNS1_5SMLocE: 1072| 71.8k|{ 1073| 71.8k| return parsePrimaryExprAux(Res, EndLoc, 0); 1074| 71.8k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser19parsePrimaryExprAuxERPKN7llvm_ks6MCExprERNS1_5SMLocEj: 848| 76.5k|{ 849| 76.5k| if (depth > 0x100) { ------------------ | Branch (849:7): [True: 0, False: 76.5k] ------------------ 850| 0| KsError = KS_ERR_ASM_EXPR_TOKEN; 851| 0| return true; 852| 0| } 853| 76.5k| SMLoc FirstTokenLoc = getLexer().getLoc(); 854| 76.5k| AsmToken::TokenKind FirstTokenKind = Lexer.getKind(); 855| 76.5k| switch (FirstTokenKind) { 856| 909| default: ------------------ | Branch (856:3): [True: 909, False: 75.6k] ------------------ 857| | //return TokError("unknown token in expression"); 858| 909| KsError = KS_ERR_ASM_EXPR_TOKEN; 859| 909| return true; 860| | // If we have an error assume that we've already handled it. 861| 27| case AsmToken::Error: ------------------ | Branch (861:3): [True: 27, False: 76.5k] ------------------ 862| 27| return true; 863| 2.32k| case AsmToken::Exclaim: ------------------ | Branch (863:3): [True: 2.32k, False: 74.2k] ------------------ 864| 2.32k| Lex(); // Eat the operator. 865| 2.32k| if (parsePrimaryExprAux(Res, EndLoc, depth+1)) ------------------ | Branch (865:9): [True: 1, False: 2.32k] ------------------ 866| 1| return true; 867| 2.32k| Res = MCUnaryExpr::createLNot(Res, getContext()); 868| 2.32k| return false; 869| 0| case AsmToken::Dollar: ------------------ | Branch (869:3): [True: 0, False: 76.5k] ------------------ 870| 0| case AsmToken::At: ------------------ | Branch (870:3): [True: 0, False: 76.5k] ------------------ 871| 8| case AsmToken::String: ------------------ | Branch (871:3): [True: 8, False: 76.5k] ------------------ 872| 13.3k| case AsmToken::Identifier: { ------------------ | Branch (872:3): [True: 13.3k, False: 63.1k] ------------------ 873| 13.3k| StringRef Identifier; 874| 13.3k| if (parseIdentifier(Identifier)) { ------------------ | Branch (874:9): [True: 0, False: 13.3k] ------------------ 875| 0| if (FirstTokenKind == AsmToken::Dollar) { ------------------ | Branch (875:11): [True: 0, False: 0] ------------------ 876| 0| if (Lexer.getMAI().getDollarIsPC()) { ------------------ | Branch (876:13): [True: 0, False: 0] ------------------ 877| | // This is a '$' reference, which references the current PC. Emit a 878| | // temporary label to the streamer and refer to it. 879| 0| MCSymbol *Sym = Ctx.createTempSymbol(); 880| 0| Out.EmitLabel(Sym); 881| 0| Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, 882| 0| getContext()); 883| 0| EndLoc = FirstTokenLoc; 884| 0| return false; 885| 0| } 886| | //return Error(FirstTokenLoc, "invalid token in expression"); 887| 0| KsError = KS_ERR_ASM_INVALIDOPERAND; 888| 0| return true; 889| 0| } 890| 0| } 891| | // Parse symbol variant 892| 13.3k| std::pair Split; 893| 13.3k| if (!MAI.useParensForSymbolVariant()) { ------------------ | Branch (893:9): [True: 0, False: 13.3k] ------------------ 894| 0| if (FirstTokenKind == AsmToken::String) { ------------------ | Branch (894:11): [True: 0, False: 0] ------------------ 895| 0| if (Lexer.is(AsmToken::At)) { ------------------ | Branch (895:13): [True: 0, False: 0] ------------------ 896| 0| Lexer.Lex(); // eat @ 897| | //SMLoc AtLoc = getLexer().getLoc(); 898| 0| StringRef VName; 899| 0| if (parseIdentifier(VName)) { ------------------ | Branch (899:15): [True: 0, False: 0] ------------------ 900| | //return Error(AtLoc, "expected symbol variant after '@'"); 901| 0| KsError = KS_ERR_ASM_INVALIDOPERAND; 902| 0| return true; 903| 0| } 904| | 905| 0| Split = std::make_pair(Identifier, VName); 906| 0| } 907| 0| } else { 908| 0| Split = Identifier.split('@'); 909| 0| } 910| 13.3k| } else if (Lexer.is(AsmToken::LParen)) { ------------------ | Branch (910:16): [True: 318, False: 13.0k] ------------------ 911| 318| Lexer.Lex(); // eat ( 912| 318| StringRef VName; 913| 318| parseIdentifier(VName); 914| 318| if (Lexer.isNot(AsmToken::RParen)) { ------------------ | Branch (914:11): [True: 49, False: 269] ------------------ 915| | //return Error(Lexer.getTok().getLoc(), 916| | // "unexpected token in variant, expected ')'"); 917| 49| KsError = KS_ERR_ASM_INVALIDOPERAND; 918| 49| return true; 919| 49| } 920| 269| Lexer.Lex(); // eat ) 921| 269| Split = std::make_pair(Identifier, VName); 922| 269| } 923| | 924| 13.2k| EndLoc = SMLoc::getFromPointer(Identifier.end()); 925| | 926| | // This is a symbol reference. 927| 13.2k| StringRef SymbolName = Identifier; 928| 13.2k| MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 929| | 930| | // Lookup the symbol variant if used. 931| 13.2k| if (Split.second.size()) { ------------------ | Branch (931:9): [True: 228, False: 13.0k] ------------------ 932| 228| Variant = MCSymbolRefExpr::getVariantKindForName(Split.second); 933| 228| if (Variant != MCSymbolRefExpr::VK_Invalid) { ------------------ | Branch (933:11): [True: 0, False: 228] ------------------ 934| 0| SymbolName = Split.first; 935| 228| } else if (MAI.doesAllowAtInName() && !MAI.useParensForSymbolVariant()) { ------------------ | Branch (935:18): [True: 0, False: 228] | Branch (935:45): [True: 0, False: 0] ------------------ 936| 0| Variant = MCSymbolRefExpr::VK_None; 937| 228| } else { 938| | //return Error(SMLoc::getFromPointer(Split.second.begin()), 939| | // "invalid variant '" + Split.second + "'"); 940| 228| KsError = KS_ERR_ASM_INVALIDOPERAND; 941| 228| return true; 942| 228| } 943| 228| } 944| | 945| 13.0k| if (SymbolName.empty()) { ------------------ | Branch (945:9): [True: 2, False: 13.0k] ------------------ 946| 2| return true; 947| 2| } 948| 13.0k| MCSymbol *Sym = getContext().getOrCreateSymbol(SymbolName); 949| | 950| | // If this is an absolute variable reference, substitute it now to preserve 951| | // semantics in the face of reassignment. 952| 13.0k| if (Sym->isVariable() && ------------------ | Branch (952:9): [True: 40, False: 13.0k] | Branch (952:9): [True: 0, False: 13.0k] ------------------ 953| 40| isa(Sym->getVariableValue(/*SetUsed*/ false))) { ------------------ | Branch (953:9): [True: 0, False: 40] ------------------ 954| 0| if (Variant) { ------------------ | Branch (954:11): [True: 0, False: 0] ------------------ 955| | //return Error(EndLoc, "unexpected modifier on variable reference"); 956| 0| KsError = KS_ERR_ASM_INVALIDOPERAND; 957| 0| return true; 958| 0| } 959| | 960| 0| Res = Sym->getVariableValue(/*SetUsed*/ false); 961| 0| return false; 962| 0| } 963| | 964| | // Otherwise create a symbol ref. 965| 13.0k| Res = MCSymbolRefExpr::create(Sym, Variant, getContext()); 966| 13.0k| return false; 967| 13.0k| } 968| 6| case AsmToken::BigNum: ------------------ | Branch (968:3): [True: 6, False: 76.5k] ------------------ 969| | // return TokError("literal value out of range for directive"); 970| 6| KsError = KS_ERR_ASM_DIRECTIVE_VALUE_RANGE; 971| 6| return true; 972| 6.66k| case AsmToken::Integer: { ------------------ | Branch (972:3): [True: 6.66k, False: 69.8k] ------------------ 973| | //SMLoc Loc = getTok().getLoc(); 974| 6.66k| bool valid; 975| 6.66k| int64_t IntVal = getTok().getIntVal(valid); 976| 6.66k| if (!valid) { ------------------ | Branch (976:9): [True: 0, False: 6.66k] ------------------ 977| 0| return true; 978| 0| } 979| 6.66k| Res = MCConstantExpr::create(IntVal, getContext()); 980| 6.66k| EndLoc = Lexer.getTok().getEndLoc(); 981| 6.66k| Lex(); // Eat token. 982| | // Look for 'b' or 'f' following an Integer as a directional label 983| 6.66k| if (Lexer.getKind() == AsmToken::Identifier) { ------------------ | Branch (983:9): [True: 1.43k, False: 5.23k] ------------------ 984| 1.43k| StringRef IDVal = getTok().getString(); 985| | // Lookup the symbol variant if used. 986| 1.43k| std::pair Split = IDVal.split('@'); 987| 1.43k| MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 988| 1.43k| if (Split.first.size() != IDVal.size()) { ------------------ | Branch (988:11): [True: 0, False: 1.43k] ------------------ 989| 0| Variant = MCSymbolRefExpr::getVariantKindForName(Split.second); 990| 0| if (Variant == MCSymbolRefExpr::VK_Invalid) { ------------------ | Branch (990:13): [True: 0, False: 0] ------------------ 991| | // return TokError("invalid variant '" + Split.second + "'"); 992| 0| KsError = KS_ERR_ASM_VARIANT_INVALID; 993| 0| return true; 994| 0| } 995| 0| IDVal = Split.first; 996| 0| } 997| 1.43k| if (IDVal == "f" || IDVal == "b") { ------------------ | Branch (997:11): [True: 0, False: 1.43k] | Branch (997:11): [True: 2, False: 1.43k] | Branch (997:27): [True: 2, False: 1.43k] ------------------ 998| 2| bool valid; 999| 2| MCSymbol *Sym = 1000| 2| Ctx.getDirectionalLocalSymbol(IntVal, IDVal == "b", valid); 1001| 2| if (!valid) ------------------ | Branch (1001:13): [True: 2, False: 0] ------------------ 1002| 2| return true; 1003| 0| Res = MCSymbolRefExpr::create(Sym, Variant, getContext()); 1004| 0| if (IDVal == "b" && Sym->isUndefined()) { ------------------ | Branch (1004:13): [True: 0, False: 0] | Branch (1004:13): [True: 0, False: 0] | Branch (1004:29): [True: 0, False: 0] ------------------ 1005| | //return Error(Loc, "invalid reference to undefined symbol"); 1006| 0| KsError = KS_ERR_ASM_INVALIDOPERAND; 1007| 0| return true; 1008| 0| } 1009| 0| EndLoc = Lexer.getTok().getEndLoc(); 1010| 0| Lex(); // Eat identifier. 1011| 0| } 1012| 1.43k| } 1013| 6.66k| return false; 1014| 6.66k| } 1015| 2.11k| case AsmToken::Real: { ------------------ | Branch (1015:3): [True: 2.11k, False: 74.4k] ------------------ 1016| 2.11k| APFloat RealVal(APFloat::IEEEdouble, getTok().getString()); 1017| 2.11k| uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 1018| 2.11k| Res = MCConstantExpr::create(IntVal, getContext()); 1019| 2.11k| EndLoc = Lexer.getTok().getEndLoc(); 1020| 2.11k| Lex(); // Eat token. 1021| 2.11k| return false; 1022| 6.66k| } 1023| 4.94k| case AsmToken::Dot: { ------------------ | Branch (1023:3): [True: 4.94k, False: 71.5k] ------------------ 1024| | // This is a '.' reference, which references the current PC. Emit a 1025| | // temporary label to the streamer and refer to it. 1026| 4.94k| MCSymbol *Sym = Ctx.createTempSymbol(); 1027| 4.94k| Out.EmitLabel(Sym); 1028| 4.94k| Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 1029| 4.94k| EndLoc = Lexer.getTok().getEndLoc(); 1030| 4.94k| Lex(); // Eat identifier. 1031| 4.94k| return false; 1032| 6.66k| } 1033| 43.7k| case AsmToken::LParen: ------------------ | Branch (1033:3): [True: 43.7k, False: 32.7k] ------------------ 1034| 43.7k| Lex(); // Eat the '('. 1035| 43.7k| return parseParenExpr(Res, EndLoc); 1036| 0| case AsmToken::LBrac: ------------------ | Branch (1036:3): [True: 0, False: 76.5k] ------------------ 1037| 0| if (!PlatformParser->HasBracketExpressions()) { ------------------ | Branch (1037:9): [True: 0, False: 0] ------------------ 1038| | // return TokError("brackets expression not supported on this target"); 1039| 0| KsError = KS_ERR_ASM_EXPR_BRACKET; 1040| 0| return true; 1041| 0| } 1042| 0| Lex(); // Eat the '['. 1043| 0| return parseBracketExpr(Res, EndLoc); 1044| 2.18k| case AsmToken::Minus: ------------------ | Branch (1044:3): [True: 2.18k, False: 74.3k] ------------------ 1045| 2.18k| Lex(); // Eat the operator. 1046| 2.18k| if (parsePrimaryExprAux(Res, EndLoc, depth+1)) ------------------ | Branch (1046:9): [True: 58, False: 2.12k] ------------------ 1047| 58| return true; 1048| 2.12k| Res = MCUnaryExpr::createMinus(Res, getContext()); 1049| 2.12k| return false; 1050| 215| case AsmToken::Plus: ------------------ | Branch (1050:3): [True: 215, False: 76.3k] ------------------ 1051| 215| Lex(); // Eat the operator. 1052| 215| if (parsePrimaryExprAux(Res, EndLoc, depth+1)) ------------------ | Branch (1052:9): [True: 18, False: 197] ------------------ 1053| 18| return true; 1054| 197| Res = MCUnaryExpr::createPlus(Res, getContext()); 1055| 197| return false; 1056| 8| case AsmToken::Tilde: ------------------ | Branch (1056:3): [True: 8, False: 76.5k] ------------------ 1057| 8| Lex(); // Eat the operator. 1058| 8| if (parsePrimaryExprAux(Res, EndLoc, depth+1)) ------------------ | Branch (1058:9): [True: 0, False: 8] ------------------ 1059| 0| return true; 1060| 8| Res = MCUnaryExpr::createNot(Res, getContext()); 1061| 8| return false; 1062| 76.5k| } 1063| 76.5k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser14parseParenExprERPKN7llvm_ks6MCExprERNS1_5SMLocE: 818| 43.7k|bool AsmParser::parseParenExpr(const MCExpr *&Res, SMLoc &EndLoc) { 819| 43.7k| if (parseExpression(Res)) ------------------ | Branch (819:7): [True: 43.7k, False: 8] ------------------ 820| 43.7k| return true; 821| 8| if (Lexer.isNot(AsmToken::RParen)) ------------------ | Branch (821:7): [True: 8, False: 0] ------------------ 822| | //return TokError("expected ')' in parentheses expression"); 823| 8| return true; 824| 0| EndLoc = Lexer.getTok().getEndLoc(); 825| 0| Lex(); 826| 0| return false; 827| 8|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser23parseAbsoluteExpressionERl: 1220| 3.64k|bool AsmParser::parseAbsoluteExpression(int64_t &Res) { 1221| 3.64k| const MCExpr *Expr; 1222| | 1223| | //SMLoc StartLoc = Lexer.getLoc(); 1224| 3.64k| if (parseExpression(Expr)) ------------------ | Branch (1224:7): [True: 147, False: 3.49k] ------------------ 1225| 147| return true; 1226| | 1227| 3.49k| if (!Expr->evaluateAsAbsolute(Res)) { ------------------ | Branch (1227:7): [True: 71, False: 3.42k] ------------------ 1228| | //return Error(StartLoc, "expected absolute expression"); 1229| 71| KsError = KS_ERR_ASM_INVALIDOPERAND; 1230| 71| return true; 1231| 71| } 1232| | 1233| 3.42k| return false; 1234| 3.49k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser20checkForValidSectionEv: 772| 6.39k|{ 773| |#if 0 774| | if (!ParsingInlineAsm && !getStreamer().getCurrentSection().first) { 775| | TokError("expected section directive before assembly directive"); 776| | Out.InitSections(false); 777| | } 778| |#endif 779| 6.39k|} AsmParser.cpp:_ZN12_GLOBAL__N_19AsmParser26initializeDirectiveKindMapEi: 5356| 430|{ 5357| 430| KsSyntax = syntax; 5358| 430| if (syntax == KS_OPT_SYNTAX_NASM) { ------------------ | Branch (5358:9): [True: 0, False: 430] ------------------ 5359| | // NASM syntax 5360| 0| DirectiveKindMap.clear(); 5361| 0| DirectiveKindMap["db"] = DK_BYTE; 5362| 0| DirectiveKindMap["dw"] = DK_SHORT; 5363| 0| DirectiveKindMap["dd"] = DK_INT; 5364| 0| DirectiveKindMap["dq"] = DK_QUAD; 5365| 0| DirectiveKindMap["use16"] = DK_CODE16; 5366| 0| DirectiveKindMap["use32"] = DK_NASM_USE32; 5367| 0| DirectiveKindMap["global"] = DK_GLOBAL; 5368| 0| DirectiveKindMap["bits"] = DK_NASM_BITS; 5369| 0| DirectiveKindMap["default"] = DK_NASM_DEFAULT; 5370| 430| } else { 5371| | // default LLVM syntax 5372| 430| DirectiveKindMap.clear(); 5373| 430| DirectiveKindMap[".set"] = DK_SET; 5374| 430| DirectiveKindMap[".equ"] = DK_EQU; 5375| 430| DirectiveKindMap[".equiv"] = DK_EQUIV; 5376| 430| DirectiveKindMap[".ascii"] = DK_ASCII; 5377| 430| DirectiveKindMap[".asciz"] = DK_ASCIZ; 5378| 430| DirectiveKindMap[".string"] = DK_STRING; 5379| 430| DirectiveKindMap[".byte"] = DK_BYTE; 5380| 430| DirectiveKindMap[".short"] = DK_SHORT; 5381| 430| DirectiveKindMap[".value"] = DK_VALUE; 5382| 430| DirectiveKindMap[".2byte"] = DK_2BYTE; 5383| 430| DirectiveKindMap[".long"] = DK_LONG; 5384| 430| DirectiveKindMap[".int"] = DK_INT; 5385| 430| DirectiveKindMap[".4byte"] = DK_4BYTE; 5386| 430| DirectiveKindMap[".quad"] = DK_QUAD; 5387| 430| DirectiveKindMap[".8byte"] = DK_8BYTE; 5388| 430| DirectiveKindMap[".octa"] = DK_OCTA; 5389| 430| DirectiveKindMap[".single"] = DK_SINGLE; 5390| 430| DirectiveKindMap[".float"] = DK_FLOAT; 5391| 430| DirectiveKindMap[".double"] = DK_DOUBLE; 5392| 430| DirectiveKindMap[".align"] = DK_ALIGN; 5393| 430| DirectiveKindMap[".align32"] = DK_ALIGN32; 5394| 430| DirectiveKindMap[".balign"] = DK_BALIGN; 5395| 430| DirectiveKindMap[".balignw"] = DK_BALIGNW; 5396| 430| DirectiveKindMap[".balignl"] = DK_BALIGNL; 5397| 430| DirectiveKindMap[".p2align"] = DK_P2ALIGN; 5398| 430| DirectiveKindMap[".p2alignw"] = DK_P2ALIGNW; 5399| 430| DirectiveKindMap[".p2alignl"] = DK_P2ALIGNL; 5400| 430| DirectiveKindMap[".org"] = DK_ORG; 5401| 430| DirectiveKindMap[".fill"] = DK_FILL; 5402| 430| DirectiveKindMap[".zero"] = DK_ZERO; 5403| 430| DirectiveKindMap[".extern"] = DK_EXTERN; 5404| 430| DirectiveKindMap[".globl"] = DK_GLOBL; 5405| 430| DirectiveKindMap[".global"] = DK_GLOBAL; 5406| 430| DirectiveKindMap[".lazy_reference"] = DK_LAZY_REFERENCE; 5407| 430| DirectiveKindMap[".no_dead_strip"] = DK_NO_DEAD_STRIP; 5408| 430| DirectiveKindMap[".symbol_resolver"] = DK_SYMBOL_RESOLVER; 5409| 430| DirectiveKindMap[".private_extern"] = DK_PRIVATE_EXTERN; 5410| 430| DirectiveKindMap[".reference"] = DK_REFERENCE; 5411| 430| DirectiveKindMap[".weak_definition"] = DK_WEAK_DEFINITION; 5412| 430| DirectiveKindMap[".weak_reference"] = DK_WEAK_REFERENCE; 5413| 430| DirectiveKindMap[".weak_def_can_be_hidden"] = DK_WEAK_DEF_CAN_BE_HIDDEN; 5414| 430| DirectiveKindMap[".comm"] = DK_COMM; 5415| 430| DirectiveKindMap[".common"] = DK_COMMON; 5416| 430| DirectiveKindMap[".lcomm"] = DK_LCOMM; 5417| 430| DirectiveKindMap[".abort"] = DK_ABORT; 5418| 430| DirectiveKindMap[".include"] = DK_INCLUDE; 5419| 430| DirectiveKindMap[".incbin"] = DK_INCBIN; 5420| 430| DirectiveKindMap[".code16"] = DK_CODE16; 5421| 430| DirectiveKindMap[".code16gcc"] = DK_CODE16GCC; 5422| 430| DirectiveKindMap[".rept"] = DK_REPT; 5423| 430| DirectiveKindMap[".rep"] = DK_REPT; 5424| 430| DirectiveKindMap[".irp"] = DK_IRP; 5425| 430| DirectiveKindMap[".irpc"] = DK_IRPC; 5426| 430| DirectiveKindMap[".endr"] = DK_ENDR; 5427| 430| DirectiveKindMap[".bundle_align_mode"] = DK_BUNDLE_ALIGN_MODE; 5428| 430| DirectiveKindMap[".bundle_lock"] = DK_BUNDLE_LOCK; 5429| 430| DirectiveKindMap[".bundle_unlock"] = DK_BUNDLE_UNLOCK; 5430| 430| DirectiveKindMap[".if"] = DK_IF; 5431| 430| DirectiveKindMap[".ifeq"] = DK_IFEQ; 5432| 430| DirectiveKindMap[".ifge"] = DK_IFGE; 5433| 430| DirectiveKindMap[".ifgt"] = DK_IFGT; 5434| 430| DirectiveKindMap[".ifle"] = DK_IFLE; 5435| 430| DirectiveKindMap[".iflt"] = DK_IFLT; 5436| 430| DirectiveKindMap[".ifne"] = DK_IFNE; 5437| 430| DirectiveKindMap[".ifb"] = DK_IFB; 5438| 430| DirectiveKindMap[".ifnb"] = DK_IFNB; 5439| 430| DirectiveKindMap[".ifc"] = DK_IFC; 5440| 430| DirectiveKindMap[".ifeqs"] = DK_IFEQS; 5441| 430| DirectiveKindMap[".ifnc"] = DK_IFNC; 5442| 430| DirectiveKindMap[".ifnes"] = DK_IFNES; 5443| 430| DirectiveKindMap[".ifdef"] = DK_IFDEF; 5444| 430| DirectiveKindMap[".ifndef"] = DK_IFNDEF; 5445| 430| DirectiveKindMap[".ifnotdef"] = DK_IFNOTDEF; 5446| 430| DirectiveKindMap[".elseif"] = DK_ELSEIF; 5447| 430| DirectiveKindMap[".else"] = DK_ELSE; 5448| 430| DirectiveKindMap[".end"] = DK_END; 5449| 430| DirectiveKindMap[".endif"] = DK_ENDIF; 5450| 430| DirectiveKindMap[".skip"] = DK_SKIP; 5451| 430| DirectiveKindMap[".space"] = DK_SPACE; 5452| 430| DirectiveKindMap[".file"] = DK_FILE; 5453| 430| DirectiveKindMap[".line"] = DK_LINE; 5454| 430| DirectiveKindMap[".loc"] = DK_LOC; 5455| 430| DirectiveKindMap[".stabs"] = DK_STABS; 5456| 430| DirectiveKindMap[".cv_file"] = DK_CV_FILE; 5457| 430| DirectiveKindMap[".cv_loc"] = DK_CV_LOC; 5458| 430| DirectiveKindMap[".cv_linetable"] = DK_CV_LINETABLE; 5459| 430| DirectiveKindMap[".cv_inline_linetable"] = DK_CV_INLINE_LINETABLE; 5460| 430| DirectiveKindMap[".cv_stringtable"] = DK_CV_STRINGTABLE; 5461| 430| DirectiveKindMap[".cv_filechecksums"] = DK_CV_FILECHECKSUMS; 5462| 430| DirectiveKindMap[".sleb128"] = DK_SLEB128; 5463| 430| DirectiveKindMap[".uleb128"] = DK_ULEB128; 5464| 430| DirectiveKindMap[".cfi_sections"] = DK_CFI_SECTIONS; 5465| 430| DirectiveKindMap[".cfi_startproc"] = DK_CFI_STARTPROC; 5466| 430| DirectiveKindMap[".cfi_endproc"] = DK_CFI_ENDPROC; 5467| 430| DirectiveKindMap[".cfi_def_cfa"] = DK_CFI_DEF_CFA; 5468| 430| DirectiveKindMap[".cfi_def_cfa_offset"] = DK_CFI_DEF_CFA_OFFSET; 5469| 430| DirectiveKindMap[".cfi_adjust_cfa_offset"] = DK_CFI_ADJUST_CFA_OFFSET; 5470| 430| DirectiveKindMap[".cfi_def_cfa_register"] = DK_CFI_DEF_CFA_REGISTER; 5471| 430| DirectiveKindMap[".cfi_offset"] = DK_CFI_OFFSET; 5472| 430| DirectiveKindMap[".cfi_rel_offset"] = DK_CFI_REL_OFFSET; 5473| 430| DirectiveKindMap[".cfi_personality"] = DK_CFI_PERSONALITY; 5474| 430| DirectiveKindMap[".cfi_lsda"] = DK_CFI_LSDA; 5475| 430| DirectiveKindMap[".cfi_remember_state"] = DK_CFI_REMEMBER_STATE; 5476| 430| DirectiveKindMap[".cfi_restore_state"] = DK_CFI_RESTORE_STATE; 5477| 430| DirectiveKindMap[".cfi_same_value"] = DK_CFI_SAME_VALUE; 5478| 430| DirectiveKindMap[".cfi_restore"] = DK_CFI_RESTORE; 5479| 430| DirectiveKindMap[".cfi_escape"] = DK_CFI_ESCAPE; 5480| 430| DirectiveKindMap[".cfi_signal_frame"] = DK_CFI_SIGNAL_FRAME; 5481| 430| DirectiveKindMap[".cfi_undefined"] = DK_CFI_UNDEFINED; 5482| 430| DirectiveKindMap[".cfi_register"] = DK_CFI_REGISTER; 5483| 430| DirectiveKindMap[".cfi_window_save"] = DK_CFI_WINDOW_SAVE; 5484| 430| DirectiveKindMap[".macros_on"] = DK_MACROS_ON; 5485| 430| DirectiveKindMap[".macros_off"] = DK_MACROS_OFF; 5486| 430| DirectiveKindMap[".macro"] = DK_MACRO; 5487| 430| DirectiveKindMap[".exitm"] = DK_EXITM; 5488| 430| DirectiveKindMap[".endm"] = DK_ENDM; 5489| 430| DirectiveKindMap[".endmacro"] = DK_ENDMACRO; 5490| 430| DirectiveKindMap[".purgem"] = DK_PURGEM; 5491| 430| DirectiveKindMap[".err"] = DK_ERR; 5492| 430| DirectiveKindMap[".error"] = DK_ERROR; 5493| 430| DirectiveKindMap[".warning"] = DK_WARNING; 5494| 430| DirectiveKindMap[".reloc"] = DK_RELOC; 5495| 430| } 5496| 430|} _ZN7llvm_ks21createDarwinAsmParserEv: 964| 430|MCAsmParserExtension *createDarwinAsmParser() { 965| 430| return new DarwinAsmParser; 966| 430|} DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParserC2Ev: 47| 430| DarwinAsmParser() {} DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser10InitializeERN7llvm_ks11MCAsmParserE: 49| 430| void Initialize(MCAsmParser &Parser) override { 50| | // Call the base implementation. 51| 430| this->MCAsmParserExtension::Initialize(Parser); 52| | 53| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveDesc>(".desc"); 54| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveIndirectSymbol>( 55| 430| ".indirect_symbol"); 56| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveLsym>(".lsym"); 57| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveSubsectionsViaSymbols>( 58| 430| ".subsections_via_symbols"); 59| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveDumpOrLoad>(".dump"); 60| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveDumpOrLoad>(".load"); 61| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveSection>(".section"); 62| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectivePushSection>( 63| 430| ".pushsection"); 64| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectivePopSection>( 65| 430| ".popsection"); 66| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectivePrevious>(".previous"); 67| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveSecureLogUnique>( 68| 430| ".secure_log_unique"); 69| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveSecureLogReset>( 70| 430| ".secure_log_reset"); 71| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveTBSS>(".tbss"); 72| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveZerofill>(".zerofill"); 73| | 74| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveDataRegion>( 75| 430| ".data_region"); 76| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveDataRegionEnd>( 77| 430| ".end_data_region"); 78| | 79| | // Special section directives. 80| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveBss>(".bss"); 81| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveConst>(".const"); 82| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveConstData>( 83| 430| ".const_data"); 84| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveConstructor>( 85| 430| ".constructor"); 86| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveCString>( 87| 430| ".cstring"); 88| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveData>(".data"); 89| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveDestructor>( 90| 430| ".destructor"); 91| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveDyld>(".dyld"); 92| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveFVMLibInit0>( 93| 430| ".fvmlib_init0"); 94| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveFVMLibInit1>( 95| 430| ".fvmlib_init1"); 96| 430| addDirectiveHandler< 97| 430| &DarwinAsmParser::parseSectionDirectiveLazySymbolPointers>( 98| 430| ".lazy_symbol_pointer"); 99| 430| addDirectiveHandler<&DarwinAsmParser::parseDirectiveLinkerOption>( 100| 430| ".linker_option"); 101| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveLiteral16>( 102| 430| ".literal16"); 103| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveLiteral4>( 104| 430| ".literal4"); 105| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveLiteral8>( 106| 430| ".literal8"); 107| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveModInitFunc>( 108| 430| ".mod_init_func"); 109| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveModTermFunc>( 110| 430| ".mod_term_func"); 111| 430| addDirectiveHandler< 112| 430| &DarwinAsmParser::parseSectionDirectiveNonLazySymbolPointers>( 113| 430| ".non_lazy_symbol_pointer"); 114| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCCatClsMeth>( 115| 430| ".objc_cat_cls_meth"); 116| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCCatInstMeth>( 117| 430| ".objc_cat_inst_meth"); 118| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCCategory>( 119| 430| ".objc_category"); 120| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCClass>( 121| 430| ".objc_class"); 122| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCClassNames>( 123| 430| ".objc_class_names"); 124| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCClassVars>( 125| 430| ".objc_class_vars"); 126| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCClsMeth>( 127| 430| ".objc_cls_meth"); 128| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCClsRefs>( 129| 430| ".objc_cls_refs"); 130| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCInstMeth>( 131| 430| ".objc_inst_meth"); 132| 430| addDirectiveHandler< 133| 430| &DarwinAsmParser::parseSectionDirectiveObjCInstanceVars>( 134| 430| ".objc_instance_vars"); 135| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCMessageRefs>( 136| 430| ".objc_message_refs"); 137| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCMetaClass>( 138| 430| ".objc_meta_class"); 139| 430| addDirectiveHandler< 140| 430| &DarwinAsmParser::parseSectionDirectiveObjCMethVarNames>( 141| 430| ".objc_meth_var_names"); 142| 430| addDirectiveHandler< 143| 430| &DarwinAsmParser::parseSectionDirectiveObjCMethVarTypes>( 144| 430| ".objc_meth_var_types"); 145| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCModuleInfo>( 146| 430| ".objc_module_info"); 147| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCProtocol>( 148| 430| ".objc_protocol"); 149| 430| addDirectiveHandler< 150| 430| &DarwinAsmParser::parseSectionDirectiveObjCSelectorStrs>( 151| 430| ".objc_selector_strs"); 152| 430| addDirectiveHandler< 153| 430| &DarwinAsmParser::parseSectionDirectiveObjCStringObject>( 154| 430| ".objc_string_object"); 155| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveObjCSymbols>( 156| 430| ".objc_symbols"); 157| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectivePICSymbolStub>( 158| 430| ".picsymbol_stub"); 159| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveStaticConst>( 160| 430| ".static_const"); 161| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveStaticData>( 162| 430| ".static_data"); 163| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveSymbolStub>( 164| 430| ".symbol_stub"); 165| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveTData>(".tdata"); 166| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveText>(".text"); 167| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveThreadInitFunc>( 168| 430| ".thread_init_func"); 169| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveTLV>(".tlv"); 170| | 171| 430| addDirectiveHandler<&DarwinAsmParser::parseSectionDirectiveIdent>(".ident"); 172| 430| addDirectiveHandler<&DarwinAsmParser::parseVersionMin>( 173| 430| ".watchos_version_min"); 174| 430| addDirectiveHandler<&DarwinAsmParser::parseVersionMin>(".tvos_version_min"); 175| 430| addDirectiveHandler<&DarwinAsmParser::parseVersionMin>(".ios_version_min"); 176| 430| addDirectiveHandler<&DarwinAsmParser::parseVersionMin>( 177| 430| ".macosx_version_min"); 178| | 179| 430| LastVersionMinDirective = SMLoc(); 180| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_18parseDirectiveDescEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_28parseDirectiveIndirectSymbolEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_18parseDirectiveLsymEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_35parseDirectiveSubsectionsViaSymbolsEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_24parseDirectiveDumpOrLoadEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 860| void addDirectiveHandler(StringRef Directive) { 35| 860| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 860| this, HandleDirective); 37| 860| getParser().addDirectiveHandler(Directive, Handler); 38| 860| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser24parseDirectiveDumpOrLoadEN7llvm_ks9StringRefENS1_5SMLocE: 476| 510| SMLoc IDLoc) { 477| 510| bool IsDump = Directive == ".dump"; 478| 510| if (getLexer().isNot(AsmToken::String)) ------------------ | Branch (478:7): [True: 0, False: 510] ------------------ 479| 0| return TokError("expected string in '.dump' or '.load' directive"); 480| | 481| 510| Lex(); 482| | 483| 510| if (getLexer().isNot(AsmToken::EndOfStatement)) ------------------ | Branch (483:7): [True: 1, False: 509] ------------------ 484| 1| return TokError("unexpected token in '.dump' or '.load' directive"); 485| | 486| 509| Lex(); 487| | 488| | // FIXME: If/when .dump and .load are implemented they will be done in the 489| | // the assembly parser and not have any need for an MCStreamer API. 490| 509| if (IsDump) ------------------ | Branch (490:7): [True: 380, False: 129] ------------------ 491| 380| return Warning(IDLoc, "ignoring directive .dump for now"); 492| 129| else 493| 129| return Warning(IDLoc, "ignoring directive .load for now"); 494| 509|} DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_21parseDirectiveSectionEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser21parseDirectiveSectionEN7llvm_ks9StringRefENS1_5SMLocE: 555| 16|bool DarwinAsmParser::parseDirectiveSection(StringRef, SMLoc) { 556| 16| SMLoc Loc = getLexer().getLoc(); 557| | 558| 16| StringRef SectionName; 559| 16| if (getParser().parseIdentifier(SectionName)) ------------------ | Branch (559:7): [True: 0, False: 16] ------------------ 560| 0| return Error(Loc, "expected identifier after '.section' directive"); 561| | 562| | // Verify there is a following comma. 563| 16| if (!getLexer().is(AsmToken::Comma)) ------------------ | Branch (563:7): [True: 0, False: 16] ------------------ 564| 0| return TokError("unexpected token in '.section' directive"); 565| | 566| 16| std::string SectionSpec = SectionName; 567| 16| SectionSpec += ","; 568| | 569| | // Add all the tokens until the end of the line, ParseSectionSpecifier will 570| | // handle this. 571| 16| StringRef EOL = getLexer().LexUntilEndOfStatement(); 572| 16| SectionSpec.append(EOL.begin(), EOL.end()); 573| | 574| 16| Lex(); 575| 16| if (getLexer().isNot(AsmToken::EndOfStatement)) ------------------ | Branch (575:7): [True: 0, False: 16] ------------------ 576| 0| return TokError("unexpected token in '.section' directive"); 577| 16| Lex(); 578| | 579| | 580| 16| StringRef Segment, Section; 581| 16| unsigned StubSize; 582| 16| unsigned TAA; 583| 16| bool TAAParsed; 584| 16| std::string ErrorStr = 585| 16| MCSectionMachO::ParseSectionSpecifier(SectionSpec, Segment, Section, 586| 16| TAA, TAAParsed, StubSize); 587| | 588| 16| if (!ErrorStr.empty()) ------------------ | Branch (588:7): [True: 3, False: 13] ------------------ 589| 3| return Error(Loc, ErrorStr.c_str()); 590| | 591| | // Issue a warning if the target is not powerpc and Section is a *coal* section. 592| 13| Triple TT = getParser().getContext().getObjectFileInfo()->getTargetTriple(); 593| 13| Triple::ArchType ArchTy = TT.getArch(); 594| | 595| 13| if (ArchTy != Triple::ppc && ArchTy != Triple::ppc64) { ------------------ | Branch (595:7): [True: 13, False: 0] | Branch (595:32): [True: 13, False: 0] ------------------ 596| 13| StringRef NonCoalSection = StringSwitch(Section) 597| 13| .Case("__textcoal_nt", "__text") 598| 13| .Case("__const_coal", "__const") 599| 13| .Case("__datacoal_nt", "__data") 600| 13| .Default(Section); 601| | 602| 13| if (!Section.equals(NonCoalSection)) { ------------------ | Branch (602:9): [True: 0, False: 13] ------------------ 603| 0| StringRef SectionVal(Loc.getPointer()); 604| 0| size_t B = SectionVal.find(',') + 1, E = SectionVal.find(',', B); 605| 0| SMLoc BLoc = SMLoc::getFromPointer(SectionVal.data() + B); 606| 0| SMLoc ELoc = SMLoc::getFromPointer(SectionVal.data() + E); 607| 0| getParser().Warning(Loc, "section \"" + Section + "\" is deprecated", 608| 0| SMRange(BLoc, ELoc)); 609| 0| getParser().Note(Loc, "change section name to \"" + NonCoalSection + 610| 0| "\"", SMRange(BLoc, ELoc)); 611| 0| } 612| 13| } 613| | 614| | // FIXME: Arch specific. 615| 13| bool isText = Segment == "__TEXT"; // FIXME: Hack. 616| 13| getStreamer().SwitchSection(getContext().getMachOSection( 617| 13| Segment, Section, TAA, StubSize, 618| 13| isText ? SectionKind::getText() : SectionKind::getData())); ------------------ | Branch (618:7): [True: 0, False: 13] ------------------ 619| 13| return false; 620| 16|} DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_25parseDirectivePushSectionEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_24parseDirectivePopSectionEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_22parseDirectivePreviousEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_29parseDirectiveSecureLogUniqueEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_28parseDirectiveSecureLogResetEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_18parseDirectiveTBSSEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser18parseDirectiveTBSSEN7llvm_ks9StringRefENS1_5SMLocE: 721| 39|bool DarwinAsmParser::parseDirectiveTBSS(StringRef, SMLoc) { 722| 39| SMLoc IDLoc = getLexer().getLoc(); 723| 39| StringRef Name; 724| 39| if (getParser().parseIdentifier(Name)) ------------------ | Branch (724:7): [True: 6, False: 33] ------------------ 725| 6| return TokError("expected identifier in directive"); 726| | 727| | // Handle the identifier as the key symbol. 728| 33| MCSymbol *Sym = getContext().getOrCreateSymbol(Name); 729| | 730| 33| if (getLexer().isNot(AsmToken::Comma)) ------------------ | Branch (730:7): [True: 0, False: 33] ------------------ 731| 0| return TokError("unexpected token in directive"); 732| 33| Lex(); 733| | 734| 33| int64_t Size; 735| 33| SMLoc SizeLoc = getLexer().getLoc(); 736| 33| if (getParser().parseAbsoluteExpression(Size)) ------------------ | Branch (736:7): [True: 33, False: 0] ------------------ 737| 33| return true; 738| | 739| 0| int64_t Pow2Alignment = 0; 740| 0| SMLoc Pow2AlignmentLoc; 741| 0| if (getLexer().is(AsmToken::Comma)) { ------------------ | Branch (741:7): [True: 0, False: 0] ------------------ 742| 0| Lex(); 743| 0| Pow2AlignmentLoc = getLexer().getLoc(); 744| 0| if (getParser().parseAbsoluteExpression(Pow2Alignment)) ------------------ | Branch (744:9): [True: 0, False: 0] ------------------ 745| 0| return true; 746| 0| } 747| | 748| 0| if (getLexer().isNot(AsmToken::EndOfStatement)) ------------------ | Branch (748:7): [True: 0, False: 0] ------------------ 749| 0| return TokError("unexpected token in '.tbss' directive"); 750| | 751| 0| Lex(); 752| | 753| 0| if (Size < 0) ------------------ | Branch (753:7): [True: 0, False: 0] ------------------ 754| 0| return Error(SizeLoc, "invalid '.tbss' directive size, can't be less than" 755| 0| "zero"); 756| | 757| | // FIXME: Diagnose overflow. 758| 0| if (Pow2Alignment < 0) ------------------ | Branch (758:7): [True: 0, False: 0] ------------------ 759| 0| return Error(Pow2AlignmentLoc, "invalid '.tbss' alignment, can't be less" 760| 0| "than zero"); 761| | 762| 0| if (!Sym->isUndefined()) ------------------ | Branch (762:7): [True: 0, False: 0] ------------------ 763| 0| return Error(IDLoc, "invalid symbol redefinition"); 764| | 765| 0| getStreamer().EmitTBSSSymbol(getContext().getMachOSection( 766| 0| "__DATA", "__thread_bss", 767| 0| MachO::S_THREAD_LOCAL_ZEROFILL, 768| 0| 0, SectionKind::getThreadBSS()), 769| 0| Sym, Size, 1 << Pow2Alignment); 770| | 771| 0| return false; 772| 0|} DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_22parseDirectiveZerofillEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_24parseDirectiveDataRegionEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_27parseDirectiveDataRegionEndEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_24parseSectionDirectiveBssEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser18parseSectionSwitchEPKcS2_jjj: 386| 130| unsigned StubSize) { 387| 130| if (getLexer().isNot(AsmToken::EndOfStatement)) ------------------ | Branch (387:7): [True: 0, False: 130] ------------------ 388| 0| return TokError("unexpected token in section switching directive"); 389| 130| Lex(); 390| | 391| | // FIXME: Arch specific. 392| 130| bool isText = TAA & MachO::S_ATTR_PURE_INSTRUCTIONS; 393| 130| getStreamer().SwitchSection(getContext().getMachOSection( 394| 130| Segment, Section, TAA, StubSize, 395| 130| isText ? SectionKind::getText() : SectionKind::getData())); ------------------ | Branch (395:7): [True: 0, False: 130] ------------------ 396| | 397| | // Set the implicit alignment, if any. 398| | // 399| | // FIXME: This isn't really what 'as' does; I think it just uses the implicit 400| | // alignment on the section (e.g., if one manually inserts bytes into the 401| | // section, then just issuing the section switch directive will not realign 402| | // the section. However, this is arguably more reasonable behavior, and there 403| | // is no good reason for someone to intentionally emit incorrectly sized 404| | // values into the implicitly aligned sections. 405| 130| if (Align) ------------------ | Branch (405:7): [True: 0, False: 130] ------------------ 406| 0| getStreamer().EmitValueToAlignment(Align); 407| | 408| 130| return false; 409| 130|} DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_26parseSectionDirectiveConstEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_30parseSectionDirectiveConstDataEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveConstructorEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_28parseSectionDirectiveCStringEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_25parseSectionDirectiveDataEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser25parseSectionDirectiveDataEN7llvm_ks9StringRefENS1_5SMLocE: 250| 130| bool parseSectionDirectiveData(StringRef, SMLoc) { 251| 130| return parseSectionSwitch("__DATA", "__data"); 252| 130| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_31parseSectionDirectiveDestructorEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_25parseSectionDirectiveDyldEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveFVMLibInit0EN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveFVMLibInit1EN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_39parseSectionDirectiveLazySymbolPointersEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_26parseDirectiveLinkerOptionEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_30parseSectionDirectiveLiteral16EN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_29parseSectionDirectiveLiteral4EN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_29parseSectionDirectiveLiteral8EN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveModInitFuncEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveModTermFuncEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_42parseSectionDirectiveNonLazySymbolPointersEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_35parseSectionDirectiveObjCCatClsMethEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_36parseSectionDirectiveObjCCatInstMethEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_33parseSectionDirectiveObjCCategoryEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_30parseSectionDirectiveObjCClassEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_35parseSectionDirectiveObjCClassNamesEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_34parseSectionDirectiveObjCClassVarsEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveObjCClsMethEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveObjCClsRefsEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_33parseSectionDirectiveObjCInstMethEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_37parseSectionDirectiveObjCInstanceVarsEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_36parseSectionDirectiveObjCMessageRefsEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_34parseSectionDirectiveObjCMetaClassEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_37parseSectionDirectiveObjCMethVarNamesEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_37parseSectionDirectiveObjCMethVarTypesEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_35parseSectionDirectiveObjCModuleInfoEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_33parseSectionDirectiveObjCProtocolEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_37parseSectionDirectiveObjCSelectorStrsEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_37parseSectionDirectiveObjCStringObjectEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveObjCSymbolsEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_34parseSectionDirectivePICSymbolStubEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_32parseSectionDirectiveStaticConstEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_31parseSectionDirectiveStaticDataEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_31parseSectionDirectiveSymbolStubEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_26parseSectionDirectiveTDataEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_25parseSectionDirectiveTextEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_35parseSectionDirectiveThreadInitFuncEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_24parseSectionDirectiveTLVEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_26parseSectionDirectiveIdentEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 430| void addDirectiveHandler(StringRef Directive) { 35| 430| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 430| this, HandleDirective); 37| 430| getParser().addDirectiveHandler(Directive, Handler); 38| 430| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser26parseSectionDirectiveIdentEN7llvm_ks9StringRefENS1_5SMLocE: 368| 152| bool parseSectionDirectiveIdent(StringRef, SMLoc) { 369| | // Darwin silently ignores the .ident directive. 370| 152| getParser().eatToEndOfStatement(); 371| 152| return false; 372| 152| } DarwinAsmParser.cpp:_ZN12_GLOBAL__N_115DarwinAsmParser19addDirectiveHandlerIXadL_ZNS0_15parseVersionMinEN7llvm_ks9StringRefENS2_5SMLocEEEEEvS3_: 34| 1.72k| void addDirectiveHandler(StringRef Directive) { 35| 1.72k| MCAsmParser::ExtensionDirectiveHandler Handler = std::make_pair( 36| 1.72k| this, HandleDirective); 37| 1.72k| getParser().addDirectiveHandler(Directive, Handler); 38| 1.72k| } _ZN7llvm_ks10MCAsmLexerC2Ev: 15| 430|MCAsmLexer::MCAsmLexer() : TokStart(nullptr), SkipSpace(true) { 16| 430| CurTok.emplace_back(AsmToken::Error, StringRef()); 17| 430|} _ZN7llvm_ks10MCAsmLexerD2Ev: 19| 430|MCAsmLexer::~MCAsmLexer() { 20| 430|} _ZNK7llvm_ks10MCAsmLexer6getLocEv: 22| 78.1k|SMLoc MCAsmLexer::getLoc() const { 23| 78.1k| return SMLoc::getFromPointer(TokStart); 24| 78.1k|} _ZNK7llvm_ks8AsmToken6getLocEv: 26| 101k|SMLoc AsmToken::getLoc() const { 27| 101k| return SMLoc::getFromPointer(Str.data()); 28| 101k|} _ZNK7llvm_ks8AsmToken9getEndLocEv: 30| 18.8k|SMLoc AsmToken::getEndLoc() const { 31| 18.8k| return SMLoc::getFromPointer(Str.data() + Str.size()); 32| 18.8k|} _ZN7llvm_ks11MCAsmParserC2Ev: 20| 430|MCAsmParser::MCAsmParser() : TargetParser(nullptr), KsError(0) { 21| 430|} _ZN7llvm_ks11MCAsmParserD2Ev: 23| 430|MCAsmParser::~MCAsmParser() { 24| 430|} _ZN7llvm_ks11MCAsmParser15setTargetParserERNS_17MCTargetAsmParserE: 26| 430|void MCAsmParser::setTargetParser(MCTargetAsmParser &P) { 27| 430| assert(!TargetParser && "Target parser is already initialized!"); ------------------ | Branch (27:3): [True: 430, False: 0] | Branch (27:3): [True: 430, Folded] | Branch (27:3): [True: 430, False: 0] ------------------ 28| 430| TargetParser = &P; 29| 430| TargetParser->Initialize(*this); 30| 430|} _ZNK7llvm_ks11MCAsmParser6getTokEv: 32| 225k|const AsmToken &MCAsmParser::getTok() const { 33| 225k| return getLexer().getTok(); 34| 225k|} _ZN7llvm_ks11MCAsmParser8TokErrorERKNS_5TwineENS_8ArrayRefINS_7SMRangeEEE: 36| 7|bool MCAsmParser::TokError(const Twine &Msg, ArrayRef Ranges) { 37| 7| Error(getLexer().getLoc(), Msg, Ranges); 38| 7| return true; 39| 7|} _ZN7llvm_ks11MCAsmParser15parseExpressionERPKNS_6MCExprE: 41| 20.1k|bool MCAsmParser::parseExpression(const MCExpr *&Res) { 42| 20.1k| SMLoc L; 43| 20.1k| return parseExpression(Res, L); 44| 20.1k|} _ZN7llvm_ks20MCAsmParserExtensionC2Ev: 14| 860| BracketExpressionsSupported(false) { 15| 860|} _ZN7llvm_ks20MCAsmParserExtensionD2Ev: 17| 860|MCAsmParserExtension::~MCAsmParserExtension() { 18| 860|} _ZN7llvm_ks20MCAsmParserExtension10InitializeERNS_11MCAsmParserE: 20| 1.29k|void MCAsmParserExtension::Initialize(MCAsmParser &Parser) { 21| 1.29k| this->Parser = &Parser; 22| 1.29k|} _ZN7llvm_ks17MCTargetAsmParserC2ERKNS_15MCTargetOptionsERKNS_15MCSubtargetInfoE: 16| 430| : AvailableFeatures(0),AvailableFeaturesFB(), ParsingInlineAsm(false), MCOptions(MCOptions), 17| 430| STI(&STI) 18| 430|{ 19| 430|} _ZN7llvm_ks17MCTargetAsmParserD2Ev: 21| 430|MCTargetAsmParser::~MCTargetAsmParser() { 22| 430|} _ZN7llvm_ks17MCTargetAsmParser7copySTIEv: 24| 2.67k|MCSubtargetInfo &MCTargetAsmParser::copySTI() { 25| 2.67k| MCSubtargetInfo &STICopy = getContext().getSubtargetCopy(getSTI()); 26| 2.67k| STI = &STICopy; 27| 2.67k| return STICopy; 28| 2.67k|} _ZNK7llvm_ks17MCTargetAsmParser6getSTIEv: 30| 73.2k|const MCSubtargetInfo &MCTargetAsmParser::getSTI() const { 31| 73.2k| return *STI; 32| 73.2k|} _ZN7llvm_ks9MCSectionC2ENS0_14SectionVariantENS_11SectionKindEPNS_8MCSymbolE: 23| 18.6k| : Begin(Begin), BundleGroupBeforeFirstInst(false), HasInstructions(false), 24| 18.6k| IsRegistered(false), DummyFragment(this), Variant(V), Kind(K) {} _ZNK7llvm_ks9MCSection8hasEndedEv: 32| 434|bool MCSection::hasEnded() const { return End && End->isInSection(); } ------------------ | Branch (32:43): [True: 0, False: 434] | Branch (32:50): [True: 0, False: 0] ------------------ _ZN7llvm_ks9MCSectionD2Ev: 34| 18.6k|MCSection::~MCSection() { 35| 18.6k|} _ZN7llvm_ks9MCSection27getSubsectionInsertionPointEj: 57| 434|MCSection::getSubsectionInsertionPoint(unsigned Subsection) { 58| 434| if (Subsection == 0 && SubsectionFragmentMap.empty()) ------------------ | Branch (58:7): [True: 434, False: 0] | Branch (58:26): [True: 434, False: 0] ------------------ 59| 434| return end(); 60| | 61| 0| SmallVectorImpl>::iterator MI = 62| 0| std::lower_bound(SubsectionFragmentMap.begin(), 63| 0| SubsectionFragmentMap.end(), 64| 0| std::make_pair(Subsection, (MCFragment *)nullptr)); 65| 0| bool ExactMatch = false; 66| 0| if (MI != SubsectionFragmentMap.end()) { ------------------ | Branch (66:7): [True: 0, False: 0] ------------------ 67| 0| ExactMatch = MI->first == Subsection; 68| 0| if (ExactMatch) ------------------ | Branch (68:9): [True: 0, False: 0] ------------------ 69| 0| ++MI; 70| 0| } 71| 0| iterator IP; 72| 0| if (MI == SubsectionFragmentMap.end()) ------------------ | Branch (72:7): [True: 0, False: 0] ------------------ 73| 0| IP = end(); 74| 0| else 75| 0| IP = MI->second->getIterator(); 76| 0| if (!ExactMatch && Subsection != 0) { ------------------ | Branch (76:7): [True: 0, False: 0] | Branch (76:22): [True: 0, False: 0] ------------------ 77| | // The GNU as documentation claims that subsections have an alignment of 4, 78| | // although this appears not to be the case. 79| 0| MCFragment *F = new MCDataFragment(); 80| 0| SubsectionFragmentMap.insert(MI, std::make_pair(Subsection, F)); 81| 0| getFragmentList().insert(IP, F); 82| 0| F->setParent(this); 83| 0| } 84| | 85| 0| return IP; 86| 434|} _ZN7llvm_ks9MCSection5beginEv: 103| 929|MCSection::iterator MCSection::begin() { return Fragments.begin(); } _ZN7llvm_ks9MCSection3endEv: 105| 3.68k|MCSection::iterator MCSection::end() { return Fragments.end(); } _ZN7llvm_ks9MCSection6rbeginEv: 107| 187|MCSection::reverse_iterator MCSection::rbegin() { return Fragments.rbegin(); } _ZN7llvm_ks12MCSectionELFD2Ev: 20| 18.6k|MCSectionELF::~MCSectionELF() {} // anchor. _ZNK7llvm_ks12MCSectionELF12UseCodeAlignEv: 162| 273|bool MCSectionELF::UseCodeAlign() const { 163| 273| return getFlags() & ELF::SHF_EXECINSTR; 164| 273|} _ZNK7llvm_ks12MCSectionELF16isVirtualSectionEv: 166| 546|bool MCSectionELF::isVirtualSection() const { 167| 546| return getType() == ELF::SHT_NOBITS; 168| 546|} _ZN7llvm_ks14MCSectionMachOC2ENS_9StringRefES1_jjNS_11SectionKindEPNS_8MCSymbolE: 75| 4| : MCSection(SV_MachO, K, Begin), TypeAndAttributes(TAA), 76| 4| Reserved2(reserved2) { 77| 4| assert(Segment.size() <= 16 && Section.size() <= 16 && ------------------ | Branch (77:3): [True: 4, False: 0] | Branch (77:3): [True: 4, False: 0] | Branch (77:3): [True: 4, Folded] | Branch (77:3): [True: 4, False: 0] ------------------ 78| 4| "Segment or section string too long"); 79| 68| for (unsigned i = 0; i != 16; ++i) { ------------------ | Branch (79:24): [True: 64, False: 4] ------------------ 80| 64| if (i < Segment.size()) ------------------ | Branch (80:9): [True: 20, False: 44] ------------------ 81| 20| SegmentName[i] = Segment[i]; 82| 44| else 83| 44| SegmentName[i] = 0; 84| | 85| 64| if (i < Section.size()) ------------------ | Branch (85:9): [True: 14, False: 50] ------------------ 86| 14| SectionName[i] = Section[i]; 87| 50| else 88| 50| SectionName[i] = 0; 89| 64| } 90| 4|} _ZNK7llvm_ks14MCSectionMachO16isVirtualSectionEv: 160| 6|bool MCSectionMachO::isVirtualSection() const { 161| 6| return (getType() == MachO::S_ZEROFILL || ------------------ | Branch (161:11): [True: 0, False: 6] ------------------ 162| 6| getType() == MachO::S_GB_ZEROFILL || ------------------ | Branch (162:11): [True: 0, False: 6] ------------------ 163| 6| getType() == MachO::S_THREAD_LOCAL_ZEROFILL); ------------------ | Branch (163:11): [True: 0, False: 6] ------------------ 164| 6|} _ZN7llvm_ks14MCSectionMachO21ParseSectionSpecifierENS_9StringRefERS1_S2_RjRbS3_: 176| 16| unsigned &StubSize) { // Out. 177| 16| TAAParsed = false; 178| | 179| 16| SmallVector SplitSpec; 180| 16| Spec.split(SplitSpec, ','); 181| | // Remove leading and trailing whitespace. 182| 16| auto GetEmptyOrTrim = [&SplitSpec](size_t Idx) -> StringRef { 183| 16| return SplitSpec.size() > Idx ? SplitSpec[Idx].trim() : StringRef(); 184| 16| }; 185| 16| Segment = GetEmptyOrTrim(0); 186| 16| Section = GetEmptyOrTrim(1); 187| 16| StringRef SectionType = GetEmptyOrTrim(2); 188| 16| StringRef Attrs = GetEmptyOrTrim(3); 189| 16| StringRef StubSizeStr = GetEmptyOrTrim(4); 190| | 191| | // Verify that the segment is present and not too long. 192| 16| if (Segment.empty() || Segment.size() > 16) ------------------ | Branch (192:7): [True: 0, False: 16] | Branch (192:26): [True: 0, False: 16] ------------------ 193| 0| return "mach-o section specifier requires a segment whose length is " 194| 0| "between 1 and 16 characters"; 195| | 196| | // Verify that the section is present and not too long. 197| 16| if (Section.empty()) ------------------ | Branch (197:7): [True: 0, False: 16] ------------------ 198| 0| return "mach-o section specifier requires a segment and section " 199| 0| "separated by a comma"; 200| | 201| 16| if (Section.size() > 16) ------------------ | Branch (201:7): [True: 0, False: 16] ------------------ 202| 0| return "mach-o section specifier requires a section whose length is " 203| 0| "between 1 and 16 characters"; 204| | 205| | // If there is no comma after the section, we're done. 206| 16| TAA = 0; 207| 16| StubSize = 0; 208| 16| if (SectionType.empty()) ------------------ | Branch (208:7): [True: 13, False: 3] ------------------ 209| 13| return ""; 210| | 211| | // Figure out which section type it is. 212| 3| auto TypeDescriptor = std::find_if( 213| 3| std::begin(SectionTypeDescriptors), std::end(SectionTypeDescriptors), 214| 3| [&](decltype(*SectionTypeDescriptors) &Descriptor) { 215| 3| return Descriptor.AssemblerName && 216| 3| SectionType == Descriptor.AssemblerName; 217| 3| }); 218| | 219| | // If we didn't find the section type, reject it. 220| 3| if (TypeDescriptor == std::end(SectionTypeDescriptors)) ------------------ | Branch (220:7): [True: 3, False: 0] ------------------ 221| 3| return "mach-o section specifier uses an unknown section type"; 222| | 223| | // Remember the TypeID. 224| 0| TAA = TypeDescriptor - std::begin(SectionTypeDescriptors); 225| 0| TAAParsed = true; 226| | 227| | // If we have no comma after the section type, there are no attributes. 228| 0| if (Attrs.empty()) { ------------------ | Branch (228:7): [True: 0, False: 0] ------------------ 229| | // S_SYMBOL_STUBS always require a symbol stub size specifier. 230| 0| if (TAA == MachO::S_SYMBOL_STUBS) ------------------ | Branch (230:9): [True: 0, False: 0] ------------------ 231| 0| return "mach-o section specifier of type 'symbol_stubs' requires a size " 232| 0| "specifier"; 233| 0| return ""; 234| 0| } 235| | 236| | // The attribute list is a '+' separated list of attributes. 237| 0| SmallVector SectionAttrs; 238| 0| Attrs.split(SectionAttrs, '+', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 239| | 240| 0| for (StringRef &SectionAttr : SectionAttrs) { ------------------ | Branch (240:31): [True: 0, False: 0] ------------------ 241| 0| auto AttrDescriptorI = std::find_if( 242| 0| std::begin(SectionAttrDescriptors), std::end(SectionAttrDescriptors), 243| 0| [&](decltype(*SectionAttrDescriptors) &Descriptor) { 244| 0| return Descriptor.AssemblerName && 245| 0| SectionAttr.trim() == Descriptor.AssemblerName; 246| 0| }); 247| 0| if (AttrDescriptorI == std::end(SectionAttrDescriptors)) ------------------ | Branch (247:9): [True: 0, False: 0] ------------------ 248| 0| return "mach-o section specifier has invalid attribute"; 249| | 250| 0| TAA |= AttrDescriptorI->AttrFlag; 251| 0| } 252| | 253| | // Okay, we've parsed the section attributes, see if we have a stub size spec. 254| 0| if (StubSizeStr.empty()) { ------------------ | Branch (254:7): [True: 0, False: 0] ------------------ 255| | // S_SYMBOL_STUBS always require a symbol stub size specifier. 256| 0| if (TAA == MachO::S_SYMBOL_STUBS) ------------------ | Branch (256:9): [True: 0, False: 0] ------------------ 257| 0| return "mach-o section specifier of type 'symbol_stubs' requires a size " 258| 0| "specifier"; 259| 0| return ""; 260| 0| } 261| | 262| | // If we have a stub size spec, we must have a sectiontype of S_SYMBOL_STUBS. 263| 0| if ((TAA & MachO::SECTION_TYPE) != MachO::S_SYMBOL_STUBS) ------------------ | Branch (263:7): [True: 0, False: 0] ------------------ 264| 0| return "mach-o section specifier cannot have a stub size specified because " 265| 0| "it does not have type 'symbol_stubs'"; 266| | 267| | // Convert the stub size from a string to an integer. 268| 0| if (StubSizeStr.getAsInteger(0, StubSize)) ------------------ | Branch (268:7): [True: 0, False: 0] ------------------ 269| 0| return "mach-o section specifier has a malformed stub size"; 270| | 271| 0| return ""; 272| 0|} MCSectionMachO.cpp:_ZZN7llvm_ks14MCSectionMachO21ParseSectionSpecifierENS_9StringRefERS1_S2_RjRbS3_ENK3$_0clEm: 182| 80| auto GetEmptyOrTrim = [&SplitSpec](size_t Idx) -> StringRef { 183| 80| return SplitSpec.size() > Idx ? SplitSpec[Idx].trim() : StringRef(); ------------------ | Branch (183:12): [True: 78, False: 2] ------------------ 184| 80| }; MCSectionMachO.cpp:_ZZN7llvm_ks14MCSectionMachO21ParseSectionSpecifierENS_9StringRefERS1_S2_RjRbS3_ENK3$_1clERK3$_0: 214| 66| [&](decltype(*SectionTypeDescriptors) &Descriptor) { 215| 66| return Descriptor.AssemblerName && ------------------ | Branch (215:16): [True: 54, False: 12] ------------------ 216| 54| SectionType == Descriptor.AssemblerName; ------------------ | Branch (216:16): [True: 0, False: 54] ------------------ 217| 66| }); _ZN7llvm_ks16MCTargetStreamerD2Ev: 33| 430|MCTargetStreamer::~MCTargetStreamer() {} _ZN7llvm_ks16MCTargetStreamerC2ERNS_10MCStreamerE: 35| 430|MCTargetStreamer::MCTargetStreamer(MCStreamer &S) : Streamer(S) { 36| 430| S.setTargetStreamer(this); 37| 430|} _ZN7llvm_ks16MCTargetStreamer9emitLabelEPNS_8MCSymbolE: 39| 5.85k|void MCTargetStreamer::emitLabel(MCSymbol *Symbol) {} _ZN7llvm_ks16MCTargetStreamer14emitAssignmentEPNS_8MCSymbolEPKNS_6MCExprE: 43| 203|void MCTargetStreamer::emitAssignment(MCSymbol *Symbol, const MCExpr *Value) {} _ZN7llvm_ks10MCStreamerC2ERNS_9MCContextE: 46| 430| : Context(Ctx), CurrentWinFrameInfo(nullptr) { 47| 430| SectionStack.push_back(std::pair()); 48| 430|} _ZN7llvm_ks10MCStreamerD2Ev: 50| 430|MCStreamer::~MCStreamer() { 51| 430| for (unsigned i = 0; i < getNumWinFrameInfos(); ++i) ------------------ | Branch (51:24): [True: 0, False: 430] ------------------ 52| 0| delete WinFrameInfos[i]; 53| 430|} _ZN7llvm_ks10MCStreamer12EmitIntValueEmjRb: 82| 4.53k|{ 83| 4.53k| Error = false; 84| | //assert(1 <= Size && Size <= 8 && "Invalid size"); 85| 4.53k| if (1 > Size || Size > 8) { ------------------ | Branch (85:7): [True: 1, False: 4.53k] | Branch (85:19): [True: 0, False: 4.53k] ------------------ 86| 1| Error = true; 87| 1| return; 88| 1| } 89| | //assert((isUIntN(8 * Size, Value) || isIntN(8 * Size, Value)) && 90| | // "Invalid size"); 91| 4.53k| if (!isUIntN(8 * Size, Value) && !isIntN(8 * Size, Value)) { ------------------ | Branch (91:7): [True: 2, False: 4.53k] | Branch (91:36): [True: 2, False: 0] ------------------ 92| 2| Error = true; 93| 2| return; 94| 2| } 95| 4.53k| char buf[8]; 96| 4.53k| const bool isLittleEndian = Context.getAsmInfo()->isLittleEndian(); 97| 21.6k| for (unsigned i = 0; i != Size; ++i) { ------------------ | Branch (97:24): [True: 17.1k, False: 4.53k] ------------------ 98| 17.1k| unsigned index = isLittleEndian ? i : (Size - i - 1); ------------------ | Branch (98:22): [True: 0, False: 17.1k] ------------------ 99| 17.1k| buf[i] = uint8_t(Value >> (index * 8)); 100| 17.1k| } 101| 4.53k| EmitBytes(StringRef(buf, Size)); 102| 4.53k|} _ZN7llvm_ks10MCStreamer9EmitValueEPKNS_6MCExprEjNS_5SMLocE: 122| 610|void MCStreamer::EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc) { 123| 610| EmitValueImpl(Value, Size, Loc); 124| 610|} _ZN7llvm_ks10MCStreamer9EmitLabelEPNS_8MCSymbolE: 232| 5.85k|void MCStreamer::EmitLabel(MCSymbol *Symbol) { 233| 5.85k| assert(!Symbol->isVariable() && "Cannot emit a variable symbol!"); ------------------ | Branch (233:3): [True: 5.85k, False: 0] | Branch (233:3): [True: 5.85k, Folded] | Branch (233:3): [True: 5.85k, False: 0] ------------------ 234| 5.85k| assert(getCurrentSection().first && "Cannot emit before setting section!"); ------------------ | Branch (234:3): [True: 5.85k, False: 0] | Branch (234:3): [True: 5.85k, Folded] | Branch (234:3): [True: 5.85k, False: 0] ------------------ 235| 5.85k| assert(!Symbol->getFragment() && "Unexpected fragment on symbol data!"); ------------------ | Branch (235:3): [True: 5.85k, False: 0] | Branch (235:3): [True: 5.85k, Folded] | Branch (235:3): [True: 5.85k, False: 0] ------------------ 236| 5.85k| Symbol->setFragment(&getCurrentSectionOnly()->getDummyFragment()); 237| | 238| 5.85k| MCTargetStreamer *TS = getTargetStreamer(); 239| 5.85k| if (TS) ------------------ | Branch (239:7): [True: 5.85k, False: 0] ------------------ 240| 5.85k| TS->emitLabel(Symbol); 241| 5.85k|} _ZN7llvm_ks10MCStreamer6FinishEv: 625| 185|unsigned int MCStreamer::Finish() { 626| 185| if (!DwarfFrameInfos.empty() && !DwarfFrameInfos.back().End) ------------------ | Branch (626:7): [True: 0, False: 185] | Branch (626:35): [True: 0, False: 0] ------------------ 627| 0| report_fatal_error("Unfinished frame!"); 628| | 629| 185| MCTargetStreamer *TS = getTargetStreamer(); 630| 185| if (TS) ------------------ | Branch (630:7): [True: 185, False: 0] ------------------ 631| 185| TS->finish(); 632| | 633| 185| return FinishImpl(); 634| 185|} _ZN7llvm_ks10MCStreamer14EmitAssignmentEPNS_8MCSymbolEPKNS_6MCExprE: 636| 203|bool MCStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { 637| 203| visitUsedExpr(*Value); 638| 203| bool valid; 639| 203| Symbol->setVariableValue(Value, valid); 640| 203| if (!valid) ------------------ | Branch (640:7): [True: 0, False: 203] ------------------ 641| 0| return false; 642| | 643| 203| MCTargetStreamer *TS = getTargetStreamer(); 644| 203| if (TS) ------------------ | Branch (644:7): [True: 203, False: 0] ------------------ 645| 203| TS->emitAssignment(Symbol, Value); 646| | 647| 203| return true; 648| 203|} _ZN7llvm_ks10MCStreamer13visitUsedExprERKNS_6MCExprE: 653| 5.87k|void MCStreamer::visitUsedExpr(const MCExpr &Expr) { 654| 5.87k| switch (Expr.getKind()) { ------------------ | Branch (654:11): [True: 5.87k, False: 0] ------------------ 655| 0| case MCExpr::Target: ------------------ | Branch (655:3): [True: 0, False: 5.87k] ------------------ 656| 0| cast(Expr).visitUsedExpr(*this); 657| 0| break; 658| | 659| 1.23k| case MCExpr::Constant: ------------------ | Branch (659:3): [True: 1.23k, False: 4.63k] ------------------ 660| 1.23k| break; 661| | 662| 961| case MCExpr::Binary: { ------------------ | Branch (662:3): [True: 961, False: 4.91k] ------------------ 663| 961| const MCBinaryExpr &BE = cast(Expr); 664| 961| visitUsedExpr(*BE.getLHS()); 665| 961| visitUsedExpr(*BE.getRHS()); 666| 961| break; 667| 0| } 668| | 669| 1.49k| case MCExpr::SymbolRef: ------------------ | Branch (669:3): [True: 1.49k, False: 4.38k] ------------------ 670| 1.49k| visitUsedSymbol(cast(Expr).getSymbol()); 671| 1.49k| break; 672| | 673| 2.18k| case MCExpr::Unary: ------------------ | Branch (673:3): [True: 2.18k, False: 3.68k] ------------------ 674| 2.18k| visitUsedExpr(*cast(Expr).getSubExpr()); 675| 2.18k| break; 676| 5.87k| } 677| 5.87k|} _ZN7llvm_ks10MCStreamer15EmitInstructionERNS_6MCInstERKNS_15MCSubtargetInfoERj: 681| 2.19k| unsigned int &KsError) { 682| | // Scan for values. 683| 11.5k| for (unsigned i = Inst.getNumOperands(); i--;) ------------------ | Branch (683:44): [True: 9.34k, False: 2.19k] ------------------ 684| 9.34k| if (Inst.getOperand(i).isExpr()) ------------------ | Branch (684:9): [True: 954, False: 8.38k] ------------------ 685| 954| visitUsedExpr(*Inst.getOperand(i).getExpr()); 686| 2.19k|} _ZN7llvm_ks10MCStreamer13EmitValueImplEPKNS_6MCExprEjNS_5SMLocE: 723| 610|void MCStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) { 724| 610| visitUsedExpr(*Value); 725| 610|} _ZN7llvm_ks10MCStreamer13SwitchSectionEPNS_9MCSectionEPKNS_6MCExprE: 739| 578|void MCStreamer::SwitchSection(MCSection *Section, const MCExpr *Subsection) { 740| 578| assert(Section && "Cannot switch to a null section!"); ------------------ | Branch (740:3): [True: 578, False: 0] | Branch (740:3): [True: 578, Folded] | Branch (740:3): [True: 578, False: 0] ------------------ 741| 578| MCSectionSubPair curSection = SectionStack.back().first; 742| 578| SectionStack.back().second = curSection; 743| 578| if (MCSectionSubPair(Section, Subsection) != curSection) { ------------------ | Branch (743:7): [True: 434, False: 144] ------------------ 744| 434| ChangeSection(Section, Subsection); 745| 434| SectionStack.back().first = MCSectionSubPair(Section, Subsection); 746| 434| assert(!Section->hasEnded() && "Section already ended"); ------------------ | Branch (746:5): [True: 434, False: 0] | Branch (746:5): [True: 434, Folded] | Branch (746:5): [True: 434, False: 0] ------------------ 747| 434| MCSymbol *Sym = Section->getBeginSymbol(); 748| 434| if (Sym && !Sym->isInSection()) ------------------ | Branch (748:9): [True: 434, False: 0] | Branch (748:16): [True: 434, False: 0] ------------------ 749| 434| EmitLabel(Sym); 750| 434| } 751| 578|} _ZN7llvm_ks15MCSubtargetInfo19InitMCProcessorInfoENS_9StringRefES1_: 26| 860|void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) { 27| 860| FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures); 28| 860| if (!CPU.empty() && ProcSchedModels) ------------------ | Branch (28:7): [True: 0, False: 860] | Branch (28:23): [True: 0, False: 0] ------------------ 29| 0| CPUSchedModel = &getSchedModelForCPU(CPU); 30| 860|} _ZN7llvm_ks15MCSubtargetInfo18setDefaultFeaturesENS_9StringRefES1_: 32| 2.33k|void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) { 33| 2.33k| FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures); 34| 2.33k|} _ZN7llvm_ks15MCSubtargetInfoC2ERKNS_6TripleENS_9StringRefES4_NS_8ArrayRefINS_18SubtargetFeatureKVEEES7_PKNS_15SubtargetInfoKVE: 40| 860| : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD), 41| 860| ProcSchedModels(ProcSched) { 42| 860| InitMCProcessorInfo(CPU, FS); 43| 860|} _ZN7llvm_ks15MCSubtargetInfo13ToggleFeatureEm: 47| 8|FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) { 48| 8| FeatureBits.flip(FB); 49| 8| return FeatureBits; 50| 8|} _ZN7llvm_ks15MCSubtargetInfo13ToggleFeatureERKNS_13FeatureBitsetE: 52| 264|FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) { 53| 264| FeatureBits ^= FB; 54| 264| return FeatureBits; 55| 264|} _ZN7llvm_ks15MCSubtargetInfo16ApplyFeatureFlagENS_9StringRefE: 64| 546|FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) { 65| 546| SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures); 66| 546| return FeatureBits; 67| 546|} MCSubtargetInfo.cpp:_ZL11getFeaturesN7llvm_ks9StringRefES0_NS_8ArrayRefINS_18SubtargetFeatureKVEEES3_: 21| 3.19k| ArrayRef ProcFeatures) { 22| 3.19k| SubtargetFeatures Features(FS); 23| 3.19k| return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures); 24| 3.19k|} _ZN7llvm_ks8MCSymbolnwEmPKNS_14StringMapEntryIbEERNS_9MCContextE: 26| 11.7k| MCContext &Ctx) { 27| | // We may need more space for a Name to account for alignment. So allocate 28| | // space for the storage type and not the name pointer. 29| 11.7k| size_t Size = s + (Name ? sizeof(NameEntryStorageTy) : 0); ------------------ | Branch (29:22): [True: 11.7k, False: 0] ------------------ 30| | 31| | // For safety, ensure that the alignment of a pointer is enough for an 32| | // MCSymbol. This also ensures we don't need padding between the name and 33| | // symbol. 34| 11.7k| static_assert((unsigned)AlignOf::Alignment <= 35| 11.7k| AlignOf::Alignment, 36| 11.7k| "Bad alignment of MCSymbol"); 37| 11.7k| void *Storage = Ctx.allocate(Size, alignOf()); 38| 11.7k| NameEntryStorageTy *Start = static_cast(Storage); 39| 11.7k| NameEntryStorageTy *End = Start + (Name ? 1 : 0); ------------------ | Branch (39:38): [True: 11.7k, False: 0] ------------------ 40| 11.7k| return End; 41| 11.7k|} _ZN7llvm_ks8MCSymbol16setVariableValueEPKNS_6MCExprERb: 43| 203|void MCSymbol::setVariableValue(const MCExpr *Value, bool &valid) { 44| 203| valid = true; 45| | //assert(!IsUsed && "Cannot set a variable that has already been used."); 46| | //assert(Value && "Invalid variable value!"); 47| | //assert((SymbolContents == SymContentsUnset || 48| | // SymbolContents == SymContentsVariable) && 49| | // "Cannot give common/offset symbol a variable value"); 50| 203| if (IsUsed || !Value || (SymbolContents != SymContentsUnset && ------------------ | Branch (50:7): [True: 0, False: 203] | Branch (50:17): [True: 0, False: 203] | Branch (50:28): [True: 43, False: 160] ------------------ 51| 43| SymbolContents != SymContentsVariable)) { ------------------ | Branch (51:15): [True: 0, False: 43] ------------------ 52| 0| valid = false; 53| 0| return; 54| 0| } 55| 203| this->Value = Value; 56| 203| SymbolContents = SymContentsVariable; 57| 203| setUndefined(); 58| 203|} _ZNK7llvm_ks11MCSymbolELF10setBindingEj: 43| 133|void MCSymbolELF::setBinding(unsigned Binding) const { 44| 133| setIsBindingSet(); 45| 133| unsigned Val; 46| 133| switch (Binding) { 47| 0| default: ------------------ | Branch (47:3): [True: 0, False: 133] ------------------ 48| 0| llvm_unreachable("Unsupported Binding"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 49| 1| case ELF::STB_LOCAL: ------------------ | Branch (49:3): [True: 1, False: 132] ------------------ 50| 1| Val = 0; 51| 1| break; 52| 132| case ELF::STB_GLOBAL: ------------------ | Branch (52:3): [True: 132, False: 1] ------------------ 53| 132| Val = 1; 54| 132| break; 55| 0| case ELF::STB_WEAK: ------------------ | Branch (55:3): [True: 0, False: 133] ------------------ 56| 0| Val = 2; 57| 0| break; 58| 0| case ELF::STB_GNU_UNIQUE: ------------------ | Branch (58:3): [True: 0, False: 133] ------------------ 59| 0| Val = 3; 60| 0| break; 61| 133| } 62| 133| uint32_t OtherFlags = getFlags() & ~(0x3 << ELF_STB_Shift); 63| 133| setFlags(OtherFlags | (Val << ELF_STB_Shift)); 64| 133|} _ZNK7llvm_ks11MCSymbolELF10getBindingEv: 66| 1.98k|unsigned MCSymbolELF::getBinding() const { 67| 1.98k| if (isBindingSet()) { ------------------ | Branch (67:7): [True: 589, False: 1.39k] ------------------ 68| 589| uint32_t Val = (getFlags() & (0x3 << ELF_STB_Shift)) >> ELF_STB_Shift; 69| 589| switch (Val) { 70| 0| default: ------------------ | Branch (70:5): [True: 0, False: 589] ------------------ 71| 0| llvm_unreachable("Invalid value"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 72| 0| case 0: ------------------ | Branch (72:5): [True: 0, False: 589] ------------------ 73| 0| return ELF::STB_LOCAL; 74| 589| case 1: ------------------ | Branch (74:5): [True: 589, False: 0] ------------------ 75| 589| return ELF::STB_GLOBAL; 76| 0| case 2: ------------------ | Branch (76:5): [True: 0, False: 589] ------------------ 77| 0| return ELF::STB_WEAK; 78| 0| case 3: ------------------ | Branch (78:5): [True: 0, False: 589] ------------------ 79| 0| return ELF::STB_GNU_UNIQUE; 80| 589| } 81| 589| } 82| | 83| 1.39k| if (isDefined()) ------------------ | Branch (83:7): [True: 1.27k, False: 122] ------------------ 84| 1.27k| return ELF::STB_LOCAL; 85| 122| if (isUsedInReloc()) ------------------ | Branch (85:7): [True: 0, False: 122] ------------------ 86| 0| return ELF::STB_GLOBAL; 87| 122| if (isWeakrefUsedInReloc()) ------------------ | Branch (87:7): [True: 0, False: 122] ------------------ 88| 0| return ELF::STB_WEAK; 89| 122| if (isSignature()) ------------------ | Branch (89:7): [True: 0, False: 122] ------------------ 90| 0| return ELF::STB_LOCAL; 91| 122| return ELF::STB_GLOBAL; 92| 122|} _ZNK7llvm_ks11MCSymbolELF7setTypeEj: 94| 1.02k|void MCSymbolELF::setType(unsigned Type) const { 95| 1.02k| unsigned Val; 96| 1.02k| switch (Type) { 97| 0| default: ------------------ | Branch (97:3): [True: 0, False: 1.02k] ------------------ 98| 0| llvm_unreachable("Unsupported Binding"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 99| 0| case ELF::STT_NOTYPE: ------------------ | Branch (99:3): [True: 0, False: 1.02k] ------------------ 100| 0| Val = 0; 101| 0| break; 102| 589| case ELF::STT_OBJECT: ------------------ | Branch (102:3): [True: 589, False: 434] ------------------ 103| 589| Val = 1; 104| 589| break; 105| 0| case ELF::STT_FUNC: ------------------ | Branch (105:3): [True: 0, False: 1.02k] ------------------ 106| 0| Val = 2; 107| 0| break; 108| 434| case ELF::STT_SECTION: ------------------ | Branch (108:3): [True: 434, False: 589] ------------------ 109| 434| Val = 3; 110| 434| break; 111| 0| case ELF::STT_COMMON: ------------------ | Branch (111:3): [True: 0, False: 1.02k] ------------------ 112| 0| Val = 4; 113| 0| break; 114| 0| case ELF::STT_TLS: ------------------ | Branch (114:3): [True: 0, False: 1.02k] ------------------ 115| 0| Val = 5; 116| 0| break; 117| 0| case ELF::STT_GNU_IFUNC: ------------------ | Branch (117:3): [True: 0, False: 1.02k] ------------------ 118| 0| Val = 6; 119| 0| break; 120| 1.02k| } 121| 1.02k| uint32_t OtherFlags = getFlags() & ~(0x7 << ELF_STT_Shift); 122| 1.02k| setFlags(OtherFlags | (Val << ELF_STT_Shift)); 123| 1.02k|} _ZNK7llvm_ks11MCSymbolELF7getTypeEv: 125| 1.24k|unsigned MCSymbolELF::getType() const { 126| 1.24k| uint32_t Val = (getFlags() & (0x7 << ELF_STT_Shift)) >> ELF_STT_Shift; 127| 1.24k| switch (Val) { 128| 0| default: ------------------ | Branch (128:3): [True: 0, False: 1.24k] ------------------ 129| 0| llvm_unreachable("Invalid value"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 130| 1.24k| case 0: ------------------ | Branch (130:3): [True: 1.24k, False: 0] ------------------ 131| 1.24k| return ELF::STT_NOTYPE; 132| 0| case 1: ------------------ | Branch (132:3): [True: 0, False: 1.24k] ------------------ 133| 0| return ELF::STT_OBJECT; 134| 0| case 2: ------------------ | Branch (134:3): [True: 0, False: 1.24k] ------------------ 135| 0| return ELF::STT_FUNC; 136| 0| case 3: ------------------ | Branch (136:3): [True: 0, False: 1.24k] ------------------ 137| 0| return ELF::STT_SECTION; 138| 0| case 4: ------------------ | Branch (138:3): [True: 0, False: 1.24k] ------------------ 139| 0| return ELF::STT_COMMON; 140| 0| case 5: ------------------ | Branch (140:3): [True: 0, False: 1.24k] ------------------ 141| 0| return ELF::STT_TLS; 142| 0| case 6: ------------------ | Branch (142:3): [True: 0, False: 1.24k] ------------------ 143| 0| return ELF::STT_GNU_IFUNC; 144| 1.24k| } 145| 1.24k|} _ZNK7llvm_ks11MCSymbolELF20isWeakrefUsedInRelocEv: 180| 122|bool MCSymbolELF::isWeakrefUsedInReloc() const { 181| 122| return getFlags() & (0x1 << ELF_WeakrefUsedInReloc_Shift); 182| 122|} _ZNK7llvm_ks11MCSymbolELF11isSignatureEv: 189| 122|bool MCSymbolELF::isSignature() const { 190| 122| return getFlags() & (0x1 << ELF_IsSignature_Shift); 191| 122|} _ZNK7llvm_ks11MCSymbolELF15setIsBindingSetEv: 193| 133|void MCSymbolELF::setIsBindingSet() const { 194| 133| uint32_t OtherFlags = getFlags() & ~(0x1 << ELF_BindingSet_Shift); 195| 133| setFlags(OtherFlags | (1 << ELF_BindingSet_Shift)); 196| 133|} _ZNK7llvm_ks11MCSymbolELF12isBindingSetEv: 198| 2.57k|bool MCSymbolELF::isBindingSet() const { 199| 2.57k| return getFlags() & (0x1 << ELF_BindingSet_Shift); 200| 2.57k|} _ZN7llvm_ks15MCTargetOptionsC2Ev: 16| 860| : MCRelaxAll(false), 17| 860| MCFatalWarnings(false), MCNoWarn(false), 18| 860| DwarfVersion(0), ABIName() {} _ZNK7llvm_ks7MCValue16getAccessVariantEv: 45| 30|MCSymbolRefExpr::VariantKind MCValue::getAccessVariant() const { 46| 30| const MCSymbolRefExpr *B = getSymB(); 47| 30| if (B) { ------------------ | Branch (47:7): [True: 1, False: 29] ------------------ 48| 1| if (B->getKind() != MCSymbolRefExpr::VK_None) ------------------ | Branch (48:9): [True: 0, False: 1] ------------------ 49| 0| llvm_unreachable("unsupported"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 50| 1| } 51| | 52| 30| const MCSymbolRefExpr *A = getSymA(); 53| 30| if (!A) ------------------ | Branch (53:7): [True: 7, False: 23] ------------------ 54| 7| return MCSymbolRefExpr::VK_None; 55| | 56| 23| MCSymbolRefExpr::VariantKind Kind = A->getKind(); 57| 23| if (Kind == MCSymbolRefExpr::VK_WEAKREF) ------------------ | Branch (57:7): [True: 0, False: 23] ------------------ 58| 0| return MCSymbolRefExpr::VK_None; 59| 23| return Kind; 60| 23|} _ZN7llvm_ks18StringTableBuilderC2ENS0_4KindE: 19| 430|StringTableBuilder::StringTableBuilder(Kind K) : K(K) { 20| | // Account for leading bytes in table so that offsets returned from add are 21| | // correct. 22| 430| switch (K) { ------------------ | Branch (22:11): [True: 430, False: 0] ------------------ 23| 0| case RAW: ------------------ | Branch (23:3): [True: 0, False: 430] ------------------ 24| 0| Size = 0; 25| 0| break; 26| 0| case MachO: ------------------ | Branch (26:3): [True: 0, False: 430] ------------------ 27| 430| case ELF: ------------------ | Branch (27:3): [True: 430, False: 0] ------------------ 28| 430| Size = 1; 29| 430| break; 30| 0| case WinCOFF: ------------------ | Branch (30:3): [True: 0, False: 430] ------------------ 31| 0| Size = 4; 32| 0| break; 33| 430| } 34| 430|} _ZN7llvm_ks18StringTableBuilder3addENS_9StringRefE: 177| 378|size_t StringTableBuilder::add(StringRef S) { 178| 378| assert(!isFinalized()); ------------------ | Branch (178:3): [True: 378, False: 0] ------------------ 179| 378| auto P = StringIndexMap.insert(std::make_pair(S, Size)); 180| 378| if (P.second) ------------------ | Branch (180:7): [True: 377, False: 1] ------------------ 181| 377| Size += S.size() + (K != RAW); 182| 378| return P.first->second; 183| 378|} _ZN7llvm_ks17SubtargetFeaturesC2ENS_9StringRefE: 120| 3.19k|SubtargetFeatures::SubtargetFeatures(StringRef Initial) { 121| | // Break up string into separate features 122| 3.19k| Split(Features, Initial); 123| 3.19k|} _ZN7llvm_ks17SubtargetFeatures16ApplyFeatureFlagERNS_13FeatureBitsetENS_9StringRefENS_8ArrayRefINS_18SubtargetFeatureKVEEE: 191| 4.57k| ArrayRef FeatureTable) { 192| | 193| 4.57k| assert(hasFlag(Feature)); ------------------ | Branch (193:3): [True: 4.57k, False: 0] ------------------ 194| | 195| | // Find feature in table. 196| 4.57k| const SubtargetFeatureKV *FeatureEntry = 197| 4.57k| Find(StripFlag(Feature), FeatureTable); 198| | // If there is a match 199| 4.57k| if (FeatureEntry) { ------------------ | Branch (199:7): [True: 4.57k, False: 0] ------------------ 200| | // Enable/disable feature in bits 201| 4.57k| if (isEnabled(Feature)) { ------------------ | Branch (201:9): [True: 4.08k, False: 491] ------------------ 202| 4.08k| Bits |= FeatureEntry->Value; 203| | 204| | // For each feature that this implies, set it. 205| 4.08k| SetImpliedBits(Bits, FeatureEntry, FeatureTable); 206| 4.08k| } else { 207| 491| Bits &= ~FeatureEntry->Value; 208| | 209| | // For each feature that implies this, clear it. 210| 491| ClearImpliedBits(Bits, FeatureEntry, FeatureTable); 211| 491| } 212| 4.57k| } else { 213| 0| errs() << "'" << Feature 214| 0| << "' is not a recognized feature for this target" 215| 0| << " (ignoring feature)\n"; 216| 0| } 217| 4.57k|} _ZN7llvm_ks17SubtargetFeatures14getFeatureBitsENS_9StringRefENS_8ArrayRefINS_18SubtargetFeatureKVEEES4_: 225| 3.19k| ArrayRef FeatureTable) { 226| | 227| 3.19k| if (CPUTable.empty() || FeatureTable.empty()) ------------------ | Branch (227:7): [True: 0, False: 3.19k] | Branch (227:27): [True: 0, False: 3.19k] ------------------ 228| 0| return FeatureBitset(); 229| | 230| 3.19k|#ifndef NDEBUG 231| 3.19k| assert(std::is_sorted(std::begin(CPUTable), std::end(CPUTable)) && ------------------ | Branch (231:3): [True: 3.19k, False: 0] | Branch (231:3): [True: 3.19k, Folded] | Branch (231:3): [True: 3.19k, False: 0] ------------------ 232| 3.19k| "CPU table is not sorted"); 233| 3.19k| assert(std::is_sorted(std::begin(FeatureTable), std::end(FeatureTable)) && ------------------ | Branch (233:3): [True: 3.19k, False: 0] | Branch (233:3): [True: 3.19k, Folded] | Branch (233:3): [True: 3.19k, False: 0] ------------------ 234| 3.19k| "CPU features table is not sorted"); 235| 3.19k|#endif 236| | // Resulting bits 237| 3.19k| FeatureBitset Bits; 238| | 239| | // Check if help is needed 240| 3.19k| if (CPU == "help") ------------------ | Branch (240:7): [True: 0, False: 3.19k] ------------------ 241| 0| Help(CPUTable, FeatureTable); 242| | 243| | // Find CPU entry if CPU name is specified. 244| 3.19k| else if (!CPU.empty()) { ------------------ | Branch (244:12): [True: 25, False: 3.16k] ------------------ 245| 25| const SubtargetFeatureKV *CPUEntry = Find(CPU, CPUTable); 246| | 247| | // If there is a match 248| 25| if (CPUEntry) { ------------------ | Branch (248:9): [True: 25, False: 0] ------------------ 249| | // Set base feature bits 250| 25| Bits = CPUEntry->Value; 251| | 252| | // Set the feature implied by this CPU feature, if any. 253| 2.60k| for (auto &FE : FeatureTable) { ------------------ | Branch (253:21): [True: 2.60k, False: 25] ------------------ 254| 2.60k| if ((CPUEntry->Value & FE.Value).any()) ------------------ | Branch (254:13): [True: 175, False: 2.42k] ------------------ 255| 175| SetImpliedBits(Bits, &FE, FeatureTable); 256| 2.60k| } 257| 25| } else { 258| 0| errs() << "'" << CPU 259| 0| << "' is not a recognized processor for this target" 260| 0| << " (ignoring processor)\n"; 261| 0| } 262| 25| } 263| | 264| | // Iterate through each feature 265| 4.02k| for (auto &Feature : Features) { ------------------ | Branch (265:22): [True: 4.02k, False: 3.19k] ------------------ 266| | // Check for help 267| 4.02k| if (Feature == "+help") ------------------ | Branch (267:9): [True: 0, False: 4.02k] ------------------ 268| 0| Help(CPUTable, FeatureTable); 269| | 270| 4.02k| ApplyFeatureFlag(Bits, Feature, FeatureTable); 271| 4.02k| } 272| | 273| 3.19k| return Bits; 274| 3.19k|} SubtargetFeature.cpp:_ZL7hasFlagN7llvm_ks9StringRefE: 31| 9.14k|static inline bool hasFlag(StringRef Feature) { 32| 9.14k| assert(!Feature.empty() && "Empty string"); ------------------ | Branch (32:3): [True: 9.14k, False: 0] | Branch (32:3): [True: 9.14k, Folded] | Branch (32:3): [True: 9.14k, False: 0] ------------------ 33| | // Get first character 34| 9.14k| char Ch = Feature[0]; 35| | // Check if first character is '+' or '-' flag 36| 9.14k| return Ch == '+' || Ch =='-'; ------------------ | Branch (36:10): [True: 8.16k, False: 982] | Branch (36:23): [True: 982, False: 0] ------------------ 37| 9.14k|} SubtargetFeature.cpp:_ZL5SplitRNSt3__16vectorINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEENS4_IS6_EEEEN7llvm_ks9StringRefE: 57| 3.19k|static void Split(std::vector &V, StringRef S) { 58| 3.19k| SmallVector Tmp; 59| 3.19k| S.split(Tmp, ',', -1, false /* KeepEmpty */); 60| 3.19k| V.assign(Tmp.begin(), Tmp.end()); 61| 3.19k|} SubtargetFeature.cpp:_ZL4FindN7llvm_ks9StringRefENS_8ArrayRefINS_18SubtargetFeatureKVEEE: 74| 4.59k| ArrayRef A) { 75| | // Binary search the array 76| 4.59k| auto F = std::lower_bound(A.begin(), A.end(), S); 77| | // If not found then return NULL 78| 4.59k| if (F == A.end() || StringRef(F->Key) != S) return nullptr; ------------------ | Branch (78:7): [True: 0, False: 4.59k] | Branch (78:7): [True: 0, False: 4.59k] | Branch (78:23): [True: 0, False: 4.59k] ------------------ 79| | // Return the found array item 80| 4.59k| return F; 81| 4.59k|} SubtargetFeature.cpp:_ZL9StripFlagN7llvm_ks9StringRefE: 41| 4.57k|static inline std::string StripFlag(StringRef Feature) { 42| 4.57k| return hasFlag(Feature) ? Feature.substr(1) : Feature; ------------------ | Branch (42:10): [True: 4.57k, False: 0] ------------------ 43| 4.57k|} SubtargetFeature.cpp:_ZL16ClearImpliedBitsRN7llvm_ks13FeatureBitsetEPKNS_18SubtargetFeatureKVENS_8ArrayRefIS2_EE: 152| 3.66k| ArrayRef FeatureTable) { 153| 380k| for (auto &FE : FeatureTable) { ------------------ | Branch (153:17): [True: 380k, False: 3.66k] ------------------ 154| 380k| if (FeatureEntry->Value == FE.Value) continue; ------------------ | Branch (154:9): [True: 3.66k, False: 376k] ------------------ 155| | 156| 376k| if ((FE.Implies & FeatureEntry->Value).any()) { ------------------ | Branch (156:9): [True: 3.16k, False: 373k] ------------------ 157| 3.16k| Bits &= ~FE.Value; 158| 3.16k| ClearImpliedBits(Bits, &FE, FeatureTable); 159| 3.16k| } 160| 376k| } 161| 3.66k|} SubtargetFeature.cpp:_ZL14SetImpliedBitsRN7llvm_ks13FeatureBitsetEPKNS_18SubtargetFeatureKVENS_8ArrayRefIS2_EE: 135| 46.3k| ArrayRef FeatureTable) { 136| 4.81M| for (auto &FE : FeatureTable) { ------------------ | Branch (136:17): [True: 4.81M, False: 46.3k] ------------------ 137| 4.81M| if (FeatureEntry->Value == FE.Value) continue; ------------------ | Branch (137:9): [True: 46.3k, False: 4.76M] ------------------ 138| | 139| 4.76M| if ((FeatureEntry->Implies & FE.Value).any()) { ------------------ | Branch (139:9): [True: 42.0k, False: 4.72M] ------------------ 140| 42.0k| Bits |= FE.Value; 141| 42.0k| SetImpliedBits(Bits, &FE, FeatureTable); 142| 42.0k| } 143| 4.76M| } 144| 46.3k|} SubtargetFeature.cpp:_ZL9isEnabledN7llvm_ks9StringRefE: 47| 4.57k|static inline bool isEnabled(StringRef Feature) { 48| 4.57k| assert(!Feature.empty() && "Empty string"); ------------------ | Branch (48:3): [True: 4.57k, False: 0] | Branch (48:3): [True: 4.57k, Folded] | Branch (48:3): [True: 4.57k, False: 0] ------------------ 49| | // Get first character 50| 4.57k| char Ch = Feature[0]; 51| | // Check if first character is '+' for enabled 52| 4.57k| return Ch == '+'; 53| 4.57k|} _Z16interpretDecimalPKcS0_P11decimalInfo: 277| 2.50k|{ 278| 2.50k| StringRef::iterator dot = end; 279| 2.50k| StringRef::iterator p = skipLeadingZeroesAndAnyDot (begin, end, &dot); 280| 2.50k| APFloat::opStatus fp; 281| | 282| 2.50k| D->firstSigDigit = p; 283| 2.50k| D->exponent = 0; 284| 2.50k| D->normalizedExponent = 0; 285| | 286| 67.5k| for (; p != end; ++p) { ------------------ | Branch (286:10): [True: 65.6k, False: 1.86k] ------------------ 287| 65.6k| if (*p == '.') { ------------------ | Branch (287:9): [True: 0, False: 65.6k] ------------------ 288| | //assert(dot == end && "String contains multiple dots"); 289| 0| if (dot != end) ------------------ | Branch (289:11): [True: 0, False: 0] ------------------ 290| 0| return APFloat::opInvalidOp; 291| 0| dot = p++; 292| 0| if (p == end) ------------------ | Branch (292:11): [True: 0, False: 0] ------------------ 293| 0| break; 294| 0| } 295| 65.6k| if (decDigitValue(*p) >= 10U) ------------------ | Branch (295:9): [True: 641, False: 65.0k] ------------------ 296| 641| break; 297| 65.6k| } 298| | 299| 2.50k| if (p != end) { ------------------ | Branch (299:7): [True: 641, False: 1.86k] ------------------ 300| | //assert((*p == 'e' || *p == 'E') && "Invalid character in significand"); 301| 641| if (*p != 'e' && *p != 'E') ------------------ | Branch (301:9): [True: 187, False: 454] | Branch (301:22): [True: 0, False: 187] ------------------ 302| 0| return APFloat::opInvalidOp; 303| | //assert(p != begin && "Significand has no digits"); 304| 641| if (p == begin) ------------------ | Branch (304:9): [True: 0, False: 641] ------------------ 305| 0| return APFloat::opInvalidOp; 306| | //assert((dot == end || p - begin != 1) && "Significand has no digits"); 307| 641| if (dot != end && p - begin == 1) ------------------ | Branch (307:9): [True: 641, False: 0] | Branch (307:23): [True: 0, False: 641] ------------------ 308| 0| return APFloat::opInvalidOp; 309| | 310| | /* p points to the first non-digit in the string */ 311| 641| D->exponent = readExponent(p + 1, end, fp); // qq 312| 641| if (fp) ------------------ | Branch (312:9): [True: 308, False: 333] ------------------ 313| 308| return fp; 314| | 315| | /* Implied decimal point? */ 316| 333| if (dot == end) ------------------ | Branch (316:9): [True: 0, False: 333] ------------------ 317| 0| dot = p; 318| 333| } 319| | 320| | /* If number is all zeroes accept any exponent. */ 321| 2.19k| if (p != D->firstSigDigit) { ------------------ | Branch (321:7): [True: 2.00k, False: 190] ------------------ 322| | /* Drop insignificant trailing zeroes. */ 323| 2.00k| if (p != begin) { ------------------ | Branch (323:9): [True: 2.00k, False: 0] ------------------ 324| 2.00k| do 325| 2.00k| do 326| 4.05k| p--; 327| 4.05k| while (p != begin && *p == '0'); ------------------ | Branch (327:16): [True: 3.32k, False: 729] | Branch (327:30): [True: 2.05k, False: 1.27k] ------------------ 328| 2.00k| while (p != begin && *p == '.'); ------------------ | Branch (328:14): [True: 1.27k, False: 729] | Branch (328:28): [True: 0, False: 1.27k] ------------------ 329| 2.00k| } 330| | 331| | /* Adjust the exponents for any decimal point. */ 332| 2.00k| D->exponent += static_cast((dot - p) - (dot > p)); 333| 2.00k| D->normalizedExponent = (D->exponent + 334| 2.00k| static_cast((p - D->firstSigDigit) 335| 2.00k| - (dot > D->firstSigDigit && dot < p))); ------------------ | Branch (335:42): [True: 1.04k, False: 959] | Branch (335:68): [True: 0, False: 1.04k] ------------------ 336| 2.00k| } 337| | 338| 2.19k| D->lastSigDigit = p; 339| | 340| 2.19k| return APFloat::opOK; 341| 2.50k|} _ZN7llvm_ks7APFloat10initializeEPKNS_12fltSemanticsE: 614| 10.0k|{ 615| 10.0k| unsigned int count; 616| | 617| 10.0k| semantics = ourSemantics; 618| 10.0k| count = partCount(); 619| 10.0k| if (count > 1) ------------------ | Branch (619:7): [True: 848, False: 9.20k] ------------------ 620| 848| significand.parts = new integerPart[count]; 621| 10.0k|} _ZN7llvm_ks7APFloat15freeSignificandEv: 625| 10.9k|{ 626| 10.9k| if (needsCleanup()) ------------------ | Branch (626:7): [True: 848, False: 10.1k] ------------------ 627| 848| delete [] significand.parts; 628| 10.9k|} _ZN7llvm_ks7APFloat7makeNaNEbbPKNS_5APIntE: 656| 240|{ 657| 240| category = fcNaN; 658| 240| sign = Negative; 659| | 660| 240| integerPart *significand = significandParts(); 661| 240| unsigned numParts = partCount(); 662| | 663| | // Set the significand bits to the fill. 664| 240| if (!fill || fill->getNumWords() < numParts) ------------------ | Branch (664:7): [True: 0, False: 240] | Branch (664:16): [True: 0, False: 240] ------------------ 665| 0| APInt::tcSet(significand, 0, numParts); 666| 240| if (fill) { ------------------ | Branch (666:7): [True: 240, False: 0] ------------------ 667| 240| APInt::tcAssign(significand, fill->getRawData(), 668| 240| std::min(fill->getNumWords(), numParts)); 669| | 670| | // Zero out the excess bits of the significand. 671| 240| unsigned bitsToPreserve = semantics->precision - 1; 672| 240| unsigned part = bitsToPreserve / 64; 673| 240| bitsToPreserve %= 64; 674| 240| significand[part] &= ((1ULL << bitsToPreserve) - 1); 675| 240| for (part++; part != numParts; ++part) ------------------ | Branch (675:18): [True: 0, False: 240] ------------------ 676| 0| significand[part] = 0; 677| 240| } 678| | 679| 240| unsigned QNaNBit = semantics->precision - 2; 680| | 681| 240| if (SNaN) { ------------------ | Branch (681:7): [True: 0, False: 240] ------------------ 682| | // We always have to clear the QNaN bit to make it an SNaN. 683| 0| APInt::tcClearBit(significand, QNaNBit); 684| | 685| | // If there are no bits set in the payload, we have to set 686| | // *something* to make it a NaN instead of an infinity; 687| | // conventionally, this is the next bit down from the QNaN bit. 688| 0| if (APInt::tcIsZero(significand, numParts)) ------------------ | Branch (688:9): [True: 0, False: 0] ------------------ 689| 0| APInt::tcSetBit(significand, QNaNBit - 1); 690| 240| } else { 691| | // We always have to set the QNaN bit to make it a QNaN. 692| 240| APInt::tcSetBit(significand, QNaNBit); 693| 240| } 694| | 695| | // For x87 extended precision, we want to make a NaN, not a 696| | // pseudo-NaN. Maybe we should expose the ability to make 697| | // pseudo-NaNs? 698| 240| if (semantics == &APFloat::x87DoubleExtended) ------------------ | Branch (698:7): [True: 0, False: 240] ------------------ 699| 0| APInt::tcSetBit(significand, QNaNBit + 1); 700| 240|} _ZN7llvm_ks7APFloat7makeNaNERKNS_12fltSemanticsEbbPKNS_5APIntE: 703| 240| const APInt *fill) { 704| 240| APFloat value(Sem, uninitialized); 705| 240| value.makeNaN(SNaN, Negative, fill); 706| 240| return value; 707| 240|} _ZN7llvm_ks7APFloataSEOS0_: 724| 918|APFloat::operator=(APFloat &&rhs) { 725| 918| freeSignificand(); 726| | 727| 918| semantics = rhs.semantics; 728| 918| significand = rhs.significand; 729| 918| exponent = rhs.exponent; 730| 918| category = rhs.category; 731| 918| sign = rhs.sign; 732| | 733| 918| rhs.semantics = &Bogus; 734| 918| return *this; 735| 918|} _ZN7llvm_ks7APFloatC2ERKNS_12fltSemanticsE: 842| 4.72k|APFloat::APFloat(const fltSemantics &ourSemantics) { 843| 4.72k| initialize(&ourSemantics); 844| 4.72k| category = fcZero; 845| 4.72k| sign = false; 846| 4.72k|} _ZN7llvm_ks7APFloatC2ERKNS_12fltSemanticsENS0_16uninitializedTagE: 848| 3.21k|APFloat::APFloat(const fltSemantics &ourSemantics, uninitializedTag tag) { 849| | // Allocates storage if necessary but does not initialize it. 850| 3.21k| initialize(&ourSemantics); 851| 3.21k|} _ZN7llvm_ks7APFloatC2ERKNS_12fltSemanticsENS_9StringRefE: 853| 2.11k|APFloat::APFloat(const fltSemantics &ourSemantics, StringRef text) { 854| 2.11k| initialize(&ourSemantics); 855| 2.11k| convertFromString(text, rmNearestTiesToEven); 856| 2.11k|} _ZN7llvm_ks7APFloatD2Ev: 868| 10.0k|{ 869| 10.0k| freeSignificand(); 870| 10.0k|} _ZNK7llvm_ks7APFloat9partCountEv: 879| 100k|{ 880| 100k| return partCountForBits(semantics->precision + 1); 881| 100k|} _ZNK7llvm_ks7APFloat16significandPartsEv: 906| 13.7k|{ 907| 13.7k| return const_cast(this)->significandParts(); 908| 13.7k|} _ZN7llvm_ks7APFloat16significandPartsEv: 912| 45.7k|{ 913| 45.7k| if (partCount() > 1) ------------------ | Branch (913:7): [True: 5.79k, False: 39.9k] ------------------ 914| 5.79k| return significand.parts; 915| 39.9k| else 916| 39.9k| return &significand.part; 917| 45.7k|} _ZN7llvm_ks7APFloat15zeroSignificandEv: 921| 1.03k|{ 922| 1.03k| APInt::tcSet(significandParts(), 0, partCount()); 923| 1.03k|} _ZN7llvm_ks7APFloat20incrementSignificandEv: 928| 918|{ 929| 918| integerPart carry; 930| | 931| 918| carry = APInt::tcIncrement(significandParts(), partCount()); 932| | 933| | /* Our callers should never cause us to overflow. */ 934| 918| assert(carry == 0); ------------------ | Branch (934:3): [True: 918, False: 0] ------------------ 935| 918| (void)carry; 936| 918|} _ZN7llvm_ks7APFloat19multiplySignificandERKS0_PS1_: 973| 1.05k|{ 974| 1.05k| unsigned int omsb; // One, not zero, based MSB. 975| 1.05k| unsigned int partsCount, newPartsCount, precision; 976| 1.05k| integerPart *lhsSignificand; 977| 1.05k| integerPart scratch[4]; 978| 1.05k| integerPart *fullSignificand; 979| 1.05k| lostFraction lost_fraction; 980| 1.05k| bool ignored; 981| | 982| 1.05k| assert(semantics == rhs.semantics); ------------------ | Branch (982:3): [True: 1.05k, False: 0] ------------------ 983| | 984| 1.05k| precision = semantics->precision; 985| | 986| | // Allocate space for twice as many bits as the original significand, plus one 987| | // extra bit for the addition to overflow into. 988| 1.05k| newPartsCount = partCountForBits(precision * 2 + 1); 989| | 990| 1.05k| if (newPartsCount > 4) ------------------ | Branch (990:7): [True: 0, False: 1.05k] ------------------ 991| 0| fullSignificand = new integerPart[newPartsCount]; 992| 1.05k| else 993| 1.05k| fullSignificand = scratch; 994| | 995| 1.05k| lhsSignificand = significandParts(); 996| 1.05k| partsCount = partCount(); 997| | 998| 1.05k| APInt::tcFullMultiply(fullSignificand, lhsSignificand, 999| 1.05k| rhs.significandParts(), partsCount, partsCount); 1000| | 1001| 1.05k| lost_fraction = lfExactlyZero; 1002| 1.05k| omsb = APInt::tcMSB(fullSignificand, newPartsCount) + 1; 1003| 1.05k| exponent += rhs.exponent; 1004| | 1005| | // Assume the operands involved in the multiplication are single-precision 1006| | // FP, and the two multiplicants are: 1007| | // *this = a23 . a22 ... a0 * 2^e1 1008| | // rhs = b23 . b22 ... b0 * 2^e2 1009| | // the result of multiplication is: 1010| | // *this = c48 c47 c46 . c45 ... c0 * 2^(e1+e2) 1011| | // Note that there are three significant bits at the left-hand side of the 1012| | // radix point: two for the multiplication, and an overflow bit for the 1013| | // addition (that will always be zero at this point). Move the radix point 1014| | // toward left by two bits, and adjust exponent accordingly. 1015| 1.05k| exponent += 2; 1016| | 1017| 1.05k| if (addend && addend->isNonZero()) { ------------------ | Branch (1017:7): [True: 0, False: 1.05k] | Branch (1017:17): [True: 0, False: 0] ------------------ 1018| | // The intermediate result of the multiplication has "2 * precision" 1019| | // signicant bit; adjust the addend to be consistent with mul result. 1020| | // 1021| 0| Significand savedSignificand = significand; 1022| 0| const fltSemantics *savedSemantics = semantics; 1023| 0| fltSemantics extendedSemantics; 1024| 0| opStatus status; 1025| 0| unsigned int extendedPrecision; 1026| | 1027| | // Normalize our MSB to one below the top bit to allow for overflow. 1028| 0| extendedPrecision = 2 * precision + 1; 1029| 0| if (omsb != extendedPrecision - 1) { ------------------ | Branch (1029:9): [True: 0, False: 0] ------------------ 1030| 0| assert(extendedPrecision > omsb); ------------------ | Branch (1030:7): [True: 0, False: 0] ------------------ 1031| 0| APInt::tcShiftLeft(fullSignificand, newPartsCount, 1032| 0| (extendedPrecision - 1) - omsb); 1033| 0| exponent -= (extendedPrecision - 1) - omsb; 1034| 0| } 1035| | 1036| | /* Create new semantics. */ 1037| 0| extendedSemantics = *semantics; 1038| 0| extendedSemantics.precision = extendedPrecision; 1039| | 1040| 0| if (newPartsCount == 1) ------------------ | Branch (1040:9): [True: 0, False: 0] ------------------ 1041| 0| significand.part = fullSignificand[0]; 1042| 0| else 1043| 0| significand.parts = fullSignificand; 1044| 0| semantics = &extendedSemantics; 1045| | 1046| 0| APFloat extendedAddend(*addend); 1047| 0| status = extendedAddend.convert(extendedSemantics, rmTowardZero, &ignored); 1048| 0| assert(status == opOK); ------------------ | Branch (1048:5): [True: 0, False: 0] ------------------ 1049| 0| (void)status; 1050| | 1051| | // Shift the significand of the addend right by one bit. This guarantees 1052| | // that the high bit of the significand is zero (same as fullSignificand), 1053| | // so the addition will overflow (if it does overflow at all) into the top bit. 1054| 0| lost_fraction = extendedAddend.shiftSignificandRight(1); 1055| 0| assert(lost_fraction == lfExactlyZero && ------------------ | Branch (1055:5): [True: 0, False: 0] | Branch (1055:5): [True: 0, Folded] | Branch (1055:5): [True: 0, False: 0] ------------------ 1056| 0| "Lost precision while shifting addend for fused-multiply-add."); 1057| | 1058| 0| lost_fraction = addOrSubtractSignificand(extendedAddend, false); 1059| | 1060| | /* Restore our state. */ 1061| 0| if (newPartsCount == 1) ------------------ | Branch (1061:9): [True: 0, False: 0] ------------------ 1062| 0| fullSignificand[0] = significand.part; 1063| 0| significand = savedSignificand; 1064| 0| semantics = savedSemantics; 1065| | 1066| 0| omsb = APInt::tcMSB(fullSignificand, newPartsCount) + 1; 1067| 0| } 1068| | 1069| | // Convert the result having "2 * precision" significant-bits back to the one 1070| | // having "precision" significant-bits. First, move the radix point from 1071| | // poision "2*precision - 1" to "precision - 1". The exponent need to be 1072| | // adjusted by "2*precision - 1" - "precision - 1" = "precision". 1073| 1.05k| exponent -= precision + 1; 1074| | 1075| | // In case MSB resides at the left-hand side of radix point, shift the 1076| | // mantissa right by some amount to make sure the MSB reside right before 1077| | // the radix point (i.e. "MSB . rest-significant-bits"). 1078| | // 1079| | // Note that the result is not normalized when "omsb < precision". So, the 1080| | // caller needs to call APFloat::normalize() if normalized value is expected. 1081| 1.05k| if (omsb > precision) { ------------------ | Branch (1081:7): [True: 1.05k, False: 0] ------------------ 1082| 1.05k| unsigned int bits, significantParts; 1083| 1.05k| lostFraction lf; 1084| | 1085| 1.05k| bits = omsb - precision; 1086| 1.05k| significantParts = partCountForBits(omsb); 1087| 1.05k| lf = shiftRight(fullSignificand, significantParts, bits); 1088| 1.05k| lost_fraction = combineLostFractions(lf, lost_fraction); 1089| 1.05k| exponent += bits; 1090| 1.05k| } 1091| | 1092| 1.05k| APInt::tcAssign(lhsSignificand, fullSignificand, partsCount); 1093| | 1094| 1.05k| if (newPartsCount > 4) ------------------ | Branch (1094:7): [True: 0, False: 1.05k] ------------------ 1095| 0| delete [] fullSignificand; 1096| | 1097| 1.05k| return lost_fraction; 1098| 1.05k|} _ZN7llvm_ks7APFloat17divideSignificandERKS0_: 1103| 1.24k|{ 1104| 1.24k| unsigned int bit, i, partsCount; 1105| 1.24k| const integerPart *rhsSignificand; 1106| 1.24k| integerPart *lhsSignificand, *dividend, *divisor; 1107| 1.24k| integerPart scratch[4]; 1108| 1.24k| lostFraction lost_fraction; 1109| | 1110| 1.24k| assert(semantics == rhs.semantics); ------------------ | Branch (1110:3): [True: 1.24k, False: 0] ------------------ 1111| | 1112| 1.24k| lhsSignificand = significandParts(); 1113| 1.24k| rhsSignificand = rhs.significandParts(); 1114| 1.24k| partsCount = partCount(); 1115| | 1116| 1.24k| if (partsCount > 2) ------------------ | Branch (1116:7): [True: 139, False: 1.10k] ------------------ 1117| 139| dividend = new integerPart[partsCount * 2]; 1118| 1.10k| else 1119| 1.10k| dividend = scratch; 1120| | 1121| 1.24k| divisor = dividend + partsCount; 1122| | 1123| | /* Copy the dividend and divisor as they will be modified in-place. */ 1124| 8.64k| for (i = 0; i < partsCount; i++) { ------------------ | Branch (1124:15): [True: 7.40k, False: 1.24k] ------------------ 1125| 7.40k| dividend[i] = lhsSignificand[i]; 1126| 7.40k| divisor[i] = rhsSignificand[i]; 1127| 7.40k| lhsSignificand[i] = 0; 1128| 7.40k| } 1129| | 1130| 1.24k| exponent -= rhs.exponent; 1131| | 1132| 1.24k| unsigned int precision = semantics->precision; 1133| | 1134| | /* Normalize the divisor. */ 1135| 1.24k| bit = precision - APInt::tcMSB(divisor, partsCount) - 1; 1136| 1.24k| if (bit) { ------------------ | Branch (1136:7): [True: 0, False: 1.24k] ------------------ 1137| 0| exponent += bit; 1138| 0| APInt::tcShiftLeft(divisor, partsCount, bit); 1139| 0| } 1140| | 1141| | /* Normalize the dividend. */ 1142| 1.24k| bit = precision - APInt::tcMSB(dividend, partsCount) - 1; 1143| 1.24k| if (bit) { ------------------ | Branch (1143:7): [True: 0, False: 1.24k] ------------------ 1144| 0| exponent -= bit; 1145| 0| APInt::tcShiftLeft(dividend, partsCount, bit); 1146| 0| } 1147| | 1148| | /* Ensure the dividend >= divisor initially for the loop below. 1149| | Incidentally, this means that the division loop below is 1150| | guaranteed to set the integer bit to one. */ 1151| 1.24k| if (APInt::tcCompare(dividend, divisor, partsCount) < 0) { ------------------ | Branch (1151:7): [True: 676, False: 571] ------------------ 1152| 676| exponent--; 1153| 676| APInt::tcShiftLeft(dividend, partsCount, 1); 1154| 676| assert(APInt::tcCompare(dividend, divisor, partsCount) >= 0); ------------------ | Branch (1154:5): [True: 676, False: 0] ------------------ 1155| 676| } 1156| | 1157| | /* Long division. */ 1158| 473k| for (bit = precision; bit; bit -= 1) { ------------------ | Branch (1158:25): [True: 472k, False: 1.24k] ------------------ 1159| 472k| if (APInt::tcCompare(dividend, divisor, partsCount) >= 0) { ------------------ | Branch (1159:9): [True: 181k, False: 290k] ------------------ 1160| 181k| APInt::tcSubtract(dividend, divisor, 0, partsCount); 1161| 181k| APInt::tcSetBit(lhsSignificand, bit - 1); 1162| 181k| } 1163| | 1164| 472k| APInt::tcShiftLeft(dividend, partsCount, 1); 1165| 472k| } 1166| | 1167| | /* Figure out the lost fraction. */ 1168| 1.24k| int cmp = APInt::tcCompare(dividend, divisor, partsCount); 1169| | 1170| 1.24k| if (cmp > 0) ------------------ | Branch (1170:7): [True: 413, False: 834] ------------------ 1171| 413| lost_fraction = lfMoreThanHalf; 1172| 834| else if (cmp == 0) ------------------ | Branch (1172:12): [True: 0, False: 834] ------------------ 1173| 0| lost_fraction = lfExactlyHalf; 1174| 834| else if (APInt::tcIsZero(dividend, partsCount)) ------------------ | Branch (1174:12): [True: 13, False: 821] ------------------ 1175| 13| lost_fraction = lfExactlyZero; 1176| 821| else 1177| 821| lost_fraction = lfLessThanHalf; 1178| | 1179| 1.24k| if (partsCount > 2) ------------------ | Branch (1179:7): [True: 139, False: 1.10k] ------------------ 1180| 139| delete [] dividend; 1181| | 1182| 1.24k| return lost_fraction; 1183| 1.24k|} _ZNK7llvm_ks7APFloat14significandMSBEv: 1187| 8.42k|{ 1188| 8.42k| return APInt::tcMSB(significandParts(), partCount()); 1189| 8.42k|} _ZN7llvm_ks7APFloat21shiftSignificandRightEj: 1200| 586|{ 1201| | /* Our exponent should not overflow. */ 1202| 586| assert((ExponentType) (exponent + bits) >= exponent); ------------------ | Branch (1202:3): [True: 586, False: 0] ------------------ 1203| | 1204| 586| exponent += bits; 1205| | 1206| 586| return shiftRight(significandParts(), partCount(), bits); 1207| 586|} _ZN7llvm_ks7APFloat20shiftSignificandLeftEj: 1212| 4.10k|{ 1213| 4.10k| assert(bits < semantics->precision); ------------------ | Branch (1213:3): [True: 4.10k, False: 0] ------------------ 1214| | 1215| 4.10k| if (bits) { ------------------ | Branch (1215:7): [True: 4.10k, False: 0] ------------------ 1216| 4.10k| unsigned int partsCount = partCount(); 1217| | 1218| 4.10k| APInt::tcShiftLeft(significandParts(), partsCount, bits); 1219| 4.10k| exponent -= bits; 1220| | 1221| | assert(!APInt::tcIsZero(significandParts(), partsCount)); ------------------ | Branch (1221:5): [True: 4.10k, False: 0] ------------------ 1222| 4.10k| } 1223| 4.10k|} _ZN7llvm_ks7APFloat14handleOverflowENS0_12roundingModeE: 1254| 276|{ 1255| | /* Infinity? */ 1256| 276| if (rounding_mode == rmNearestTiesToEven || ------------------ | Branch (1256:7): [True: 276, False: 0] ------------------ 1257| 0| rounding_mode == rmNearestTiesToAway || ------------------ | Branch (1257:7): [True: 0, False: 0] ------------------ 1258| 0| (rounding_mode == rmTowardPositive && !sign) || ------------------ | Branch (1258:8): [True: 0, False: 0] | Branch (1258:45): [True: 0, False: 0] ------------------ 1259| 276| (rounding_mode == rmTowardNegative && sign)) { ------------------ | Branch (1259:8): [True: 0, False: 0] | Branch (1259:45): [True: 0, False: 0] ------------------ 1260| 276| category = fcInfinity; 1261| 276| return (opStatus) (opOverflow | opInexact); 1262| 276| } 1263| | 1264| | /* Otherwise we become the largest finite number. */ 1265| 0| category = fcNormal; 1266| 0| exponent = semantics->maxExponent; 1267| 0| APInt::tcSetLeastSignificantBits(significandParts(), partCount(), 1268| 0| semantics->precision); 1269| | 1270| 0| return opInexact; 1271| 276|} _ZNK7llvm_ks7APFloat17roundAwayFromZeroENS0_12roundingModeENS_12lostFractionEj: 1282| 1.82k|{ 1283| | /* NaNs and infinities should not have lost fractions. */ 1284| 1.82k| assert(isFiniteNonZero() || category == fcZero); ------------------ | Branch (1284:3): [True: 1.82k, False: 0] | Branch (1284:3): [True: 0, False: 0] | Branch (1284:3): [True: 1.82k, False: 0] ------------------ 1285| | 1286| | /* Current callers never pass this so we don't handle it. */ 1287| 1.82k| assert(lost_fraction != lfExactlyZero); ------------------ | Branch (1287:3): [True: 1.82k, False: 0] ------------------ 1288| | 1289| 1.82k| switch (rounding_mode) { ------------------ | Branch (1289:11): [True: 1.82k, False: 0] ------------------ 1290| 0| case rmNearestTiesToAway: ------------------ | Branch (1290:3): [True: 0, False: 1.82k] ------------------ 1291| 0| return lost_fraction == lfExactlyHalf || lost_fraction == lfMoreThanHalf; ------------------ | Branch (1291:12): [True: 0, False: 0] | Branch (1291:46): [True: 0, False: 0] ------------------ 1292| | 1293| 1.82k| case rmNearestTiesToEven: ------------------ | Branch (1293:3): [True: 1.82k, False: 0] ------------------ 1294| 1.82k| if (lost_fraction == lfMoreThanHalf) ------------------ | Branch (1294:9): [True: 909, False: 912] ------------------ 1295| 909| return true; 1296| | 1297| | /* Our zeroes don't have a significand to test. */ 1298| 912| if (lost_fraction == lfExactlyHalf && category != fcZero) ------------------ | Branch (1298:9): [True: 9, False: 903] | Branch (1298:43): [True: 9, False: 0] ------------------ 1299| 9| return APInt::tcExtractBit(significandParts(), bit); 1300| | 1301| 903| return false; 1302| | 1303| 0| case rmTowardZero: ------------------ | Branch (1303:3): [True: 0, False: 1.82k] ------------------ 1304| 0| return false; 1305| | 1306| 0| case rmTowardPositive: ------------------ | Branch (1306:3): [True: 0, False: 1.82k] ------------------ 1307| 0| return !sign; 1308| | 1309| 0| case rmTowardNegative: ------------------ | Branch (1309:3): [True: 0, False: 1.82k] ------------------ 1310| 0| return sign; 1311| 1.82k| } 1312| 0| llvm_unreachable("Invalid rounding mode found"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 1313| 1.82k|} _ZN7llvm_ks7APFloat9normalizeENS0_12roundingModeENS_12lostFractionE: 1318| 7.50k|{ 1319| 7.50k| unsigned int omsb; /* One, not zero, based MSB. */ 1320| 7.50k| int exponentChange; 1321| | 1322| 7.50k| if (!isFiniteNonZero()) ------------------ | Branch (1322:7): [True: 0, False: 7.50k] ------------------ 1323| 0| return opOK; 1324| | 1325| | /* Before rounding normalize the exponent of fcNormal numbers. */ 1326| 7.50k| omsb = significandMSB() + 1; 1327| | 1328| 7.50k| if (omsb) { ------------------ | Branch (1328:7): [True: 7.33k, False: 175] ------------------ 1329| | /* OMSB is numbered from 1. We want to place it in the integer 1330| | bit numbered PRECISION if possible, with a compensating change in 1331| | the exponent. */ 1332| 7.33k| exponentChange = omsb - semantics->precision; 1333| | 1334| | /* If the resulting exponent is too high, overflow according to 1335| | the rounding mode. */ 1336| 7.33k| if (exponent + exponentChange > semantics->maxExponent) ------------------ | Branch (1336:9): [True: 275, False: 7.05k] ------------------ 1337| 275| return handleOverflow(rounding_mode); 1338| | 1339| | /* Subnormal numbers have exponent minExponent, and their MSB 1340| | is forced based on that. */ 1341| 7.05k| if (exponent + exponentChange < semantics->minExponent) ------------------ | Branch (1341:9): [True: 11, False: 7.04k] ------------------ 1342| 11| exponentChange = semantics->minExponent - exponent; 1343| | 1344| | /* Shifting left is easy as we don't lose precision. */ 1345| 7.05k| if (exponentChange < 0) { ------------------ | Branch (1345:9): [True: 4.10k, False: 2.94k] ------------------ 1346| 4.10k| assert(lost_fraction == lfExactlyZero); ------------------ | Branch (1346:7): [True: 4.10k, False: 0] ------------------ 1347| | 1348| 4.10k| shiftSignificandLeft(-exponentChange); 1349| | 1350| 4.10k| return opOK; 1351| 4.10k| } 1352| | 1353| 2.94k| if (exponentChange > 0) { ------------------ | Branch (1353:9): [True: 585, False: 2.36k] ------------------ 1354| 585| lostFraction lf; 1355| | 1356| | /* Shift right and capture any new lost fraction. */ 1357| 585| lf = shiftSignificandRight(exponentChange); 1358| | 1359| 585| lost_fraction = combineLostFractions(lf, lost_fraction); 1360| | 1361| | /* Keep OMSB up-to-date. */ 1362| 585| if (omsb > (unsigned) exponentChange) ------------------ | Branch (1362:11): [True: 577, False: 8] ------------------ 1363| 577| omsb -= exponentChange; 1364| 8| else 1365| 8| omsb = 0; 1366| 585| } 1367| 2.94k| } 1368| | 1369| | /* Now round the number according to rounding_mode given the lost 1370| | fraction. */ 1371| | 1372| | /* As specified in IEEE 754, since we do not trap we do not report 1373| | underflow for exact results. */ 1374| 3.12k| if (lost_fraction == lfExactlyZero) { ------------------ | Branch (1374:7): [True: 1.30k, False: 1.82k] ------------------ 1375| | /* Canonicalize zeroes. */ 1376| 1.30k| if (omsb == 0) ------------------ | Branch (1376:9): [True: 44, False: 1.25k] ------------------ 1377| 44| category = fcZero; 1378| | 1379| 1.30k| return opOK; 1380| 1.30k| } 1381| | 1382| | /* Increment the significand if we're rounding away from zero. */ 1383| 1.82k| if (roundAwayFromZero(rounding_mode, lost_fraction, 0)) { ------------------ | Branch (1383:7): [True: 918, False: 903] ------------------ 1384| 918| if (omsb == 0) ------------------ | Branch (1384:9): [True: 0, False: 918] ------------------ 1385| 0| exponent = semantics->minExponent; 1386| | 1387| 918| incrementSignificand(); 1388| 918| omsb = significandMSB() + 1; 1389| | 1390| | /* Did the significand increment overflow? */ 1391| 918| if (omsb == (unsigned) semantics->precision + 1) { ------------------ | Branch (1391:9): [True: 1, False: 917] ------------------ 1392| | /* Renormalize by incrementing the exponent and shifting our 1393| | significand right one. However if we already have the 1394| | maximum exponent we overflow to infinity. */ 1395| 1| if (exponent == semantics->maxExponent) { ------------------ | Branch (1395:11): [True: 0, False: 1] ------------------ 1396| 0| category = fcInfinity; 1397| | 1398| 0| return (opStatus) (opOverflow | opInexact); 1399| 0| } 1400| | 1401| 1| shiftSignificandRight(1); 1402| | 1403| 1| return opInexact; 1404| 1| } 1405| 918| } 1406| | 1407| | /* The normal case - we were and are not denormal, and any 1408| | significand increment above didn't overflow. */ 1409| 1.82k| if (omsb == semantics->precision) ------------------ | Branch (1409:7): [True: 1.67k, False: 142] ------------------ 1410| 1.67k| return opInexact; 1411| | 1412| | /* We have a non-zero denormal. */ 1413| 1.82k| assert(omsb < semantics->precision); ------------------ | Branch (1413:3): [True: 142, False: 0] ------------------ 1414| | 1415| | /* Canonicalize zeroes. */ 1416| 142| if (omsb == 0) ------------------ | Branch (1416:7): [True: 139, False: 3] ------------------ 1417| 139| category = fcZero; 1418| | 1419| | /* The fcZero case is a denormal that underflowed to zero. */ 1420| 142| return (opStatus) (opUnderflow | opInexact); 1421| 142|} _ZN7llvm_ks7APFloat10changeSignEv: 1677| 929|{ 1678| | /* Look mummy, this one's easy. */ 1679| 929| sign = !sign; 1680| 929|} _ZN7llvm_ks7APFloat24convertFromUnsignedPartsEPKmjNS0_12roundingModeE: 2297| 4.59k|{ 2298| 4.59k| unsigned int omsb, precision, dstCount; 2299| 4.59k| integerPart *dst; 2300| 4.59k| lostFraction lost_fraction; 2301| | 2302| 4.59k| category = fcNormal; 2303| 4.59k| omsb = APInt::tcMSB(src, srcCount) + 1; 2304| 4.59k| dst = significandParts(); 2305| 4.59k| dstCount = partCount(); 2306| 4.59k| precision = semantics->precision; 2307| | 2308| | /* We want the most significant PRECISION bits of SRC. There may not 2309| | be that many; extract what we can. */ 2310| 4.59k| if (precision <= omsb) { ------------------ | Branch (2310:7): [True: 490, False: 4.10k] ------------------ 2311| 490| exponent = omsb - 1; 2312| 490| lost_fraction = lostFractionThroughTruncation(src, srcCount, 2313| 490| omsb - precision); 2314| 490| APInt::tcExtract(dst, dstCount, src, precision, omsb - precision); 2315| 4.10k| } else { 2316| 4.10k| exponent = precision - 1; 2317| 4.10k| lost_fraction = lfExactlyZero; 2318| 4.10k| APInt::tcExtract(dst, dstCount, src, omsb, 0); 2319| 4.10k| } 2320| | 2321| 4.59k| return normalize(rounding_mode, lost_fraction); 2322| 4.59k|} _ZN7llvm_ks7APFloat28convertFromHexadecimalStringENS_9StringRefENS0_12roundingModeE: 2391| 904|{ 2392| 904| lostFraction lost_fraction = lfExactlyZero; 2393| | 2394| 904| category = fcNormal; 2395| 904| zeroSignificand(); 2396| 904| exponent = 0; 2397| | 2398| 904| integerPart *significand = significandParts(); 2399| 904| unsigned partsCount = partCount(); 2400| 904| unsigned bitPos = partsCount * integerPartWidth; 2401| 904| bool computedTrailingFraction = false; 2402| | 2403| | // Skip leading zeroes and any (hexa)decimal point. 2404| 904| StringRef::iterator begin = s.begin(); 2405| 904| StringRef::iterator end = s.end(); 2406| 904| StringRef::iterator dot; 2407| 904| StringRef::iterator p = skipLeadingZeroesAndAnyDot(begin, end, &dot); 2408| 904| StringRef::iterator firstSignificantDigit = p; 2409| | 2410| 15.6k| while (p != end) { ------------------ | Branch (2410:10): [True: 15.6k, False: 0] ------------------ 2411| 15.6k| integerPart hex_value; 2412| | 2413| 15.6k| if (*p == '.') { ------------------ | Branch (2413:9): [True: 239, False: 15.4k] ------------------ 2414| 239| assert(dot == end && "String contains multiple dots"); ------------------ | Branch (2414:7): [True: 239, False: 0] | Branch (2414:7): [True: 239, Folded] | Branch (2414:7): [True: 239, False: 0] ------------------ 2415| 239| dot = p++; 2416| 239| continue; 2417| 239| } 2418| | 2419| 15.4k| hex_value = hexDigitValue(*p); 2420| 15.4k| if (hex_value == -1U) ------------------ | Branch (2420:9): [True: 904, False: 14.5k] ------------------ 2421| 904| break; 2422| | 2423| 14.5k| p++; 2424| | 2425| | // Store the number while we have space. 2426| 14.5k| if (bitPos) { ------------------ | Branch (2426:9): [True: 10.9k, False: 3.57k] ------------------ 2427| 10.9k| bitPos -= 4; 2428| 10.9k| hex_value <<= bitPos % integerPartWidth; 2429| 10.9k| significand[bitPos / integerPartWidth] |= hex_value; 2430| 10.9k| } else if (!computedTrailingFraction) { ------------------ | Branch (2430:16): [True: 449, False: 3.12k] ------------------ 2431| 449| lost_fraction = trailingHexadecimalFraction(p, end, hex_value); 2432| 449| computedTrailingFraction = true; 2433| 449| } 2434| 14.5k| } 2435| | 2436| | /* Hex floats require an exponent but not a hexadecimal point. */ 2437| 904| assert(p != end && "Hex strings require an exponent"); ------------------ | Branch (2437:3): [True: 904, False: 0] | Branch (2437:3): [True: 904, Folded] | Branch (2437:3): [True: 904, False: 0] ------------------ 2438| 904| assert((*p == 'p' || *p == 'P') && "Invalid character in significand"); ------------------ | Branch (2438:3): [True: 470, False: 434] | Branch (2438:3): [True: 434, False: 0] | Branch (2438:3): [True: 904, Folded] | Branch (2438:3): [True: 904, False: 0] ------------------ 2439| 904| assert(p != begin && "Significand has no digits"); ------------------ | Branch (2439:3): [True: 904, False: 0] | Branch (2439:3): [True: 904, Folded] | Branch (2439:3): [True: 904, False: 0] ------------------ 2440| 904| assert((dot == end || p - begin != 1) && "Significand has no digits"); ------------------ | Branch (2440:3): [True: 471, False: 433] | Branch (2440:3): [True: 433, False: 0] | Branch (2440:3): [True: 904, Folded] | Branch (2440:3): [True: 904, False: 0] ------------------ 2441| | 2442| | /* Ignore the exponent if we are zero. */ 2443| 904| if (p != firstSignificantDigit) { ------------------ | Branch (2443:7): [True: 860, False: 44] ------------------ 2444| 860| int expAdjustment; 2445| | 2446| | /* Implicit hexadecimal point? */ 2447| 860| if (dot == end) ------------------ | Branch (2447:9): [True: 469, False: 391] ------------------ 2448| 469| dot = p; 2449| | 2450| | /* Calculate the exponent adjustment implicit in the number of 2451| | significant digits. */ 2452| 860| expAdjustment = static_cast(dot - firstSignificantDigit); 2453| 860| if (expAdjustment < 0) ------------------ | Branch (2453:9): [True: 152, False: 708] ------------------ 2454| 152| expAdjustment++; 2455| 860| expAdjustment = expAdjustment * 4 - 1; 2456| | 2457| | /* Adjust for writing the significand starting at the most 2458| | significant nibble. */ 2459| 860| expAdjustment += semantics->precision; 2460| 860| expAdjustment -= partsCount * integerPartWidth; 2461| | 2462| | /* Adjust for the given exponent. */ 2463| 860| exponent = totalExponent(p + 1, end, expAdjustment); 2464| 860| } 2465| | 2466| 904| return normalize(rounding_mode, lost_fraction); 2467| 904|} _ZN7llvm_ks7APFloat28roundSignificandWithExponentEPKmjiNS0_12roundingModeE: 2473| 1.87k|{ 2474| 1.87k| unsigned int parts, pow5PartCount; 2475| 1.87k| fltSemantics calcSemantics = { 32767, -32767, 0, 0 }; 2476| 1.87k| integerPart pow5Parts[maxPowerOfFiveParts]; 2477| 1.87k| bool isNearest; 2478| | 2479| 1.87k| isNearest = (rounding_mode == rmNearestTiesToEven || ------------------ | Branch (2479:16): [True: 1.87k, False: 0] ------------------ 2480| 0| rounding_mode == rmNearestTiesToAway); ------------------ | Branch (2480:16): [True: 0, False: 0] ------------------ 2481| | 2482| 1.87k| parts = partCountForBits(semantics->precision + 11); 2483| | 2484| | /* Calculate pow(5, abs(exp)). */ 2485| 1.87k| pow5PartCount = powerOf5(pow5Parts, exp >= 0 ? exp: -exp); ------------------ | Branch (2485:39): [True: 1.05k, False: 823] ------------------ 2486| | 2487| 2.29k| for (;; parts *= 2) { 2488| 2.29k| opStatus sigStatus, powStatus; 2489| 2.29k| unsigned int excessPrecision, truncatedBits; 2490| | 2491| 2.29k| calcSemantics.precision = parts * integerPartWidth - 1; 2492| 2.29k| excessPrecision = calcSemantics.precision - semantics->precision; 2493| 2.29k| truncatedBits = excessPrecision; 2494| | 2495| 2.29k| APFloat decSig = APFloat::getZero(calcSemantics, sign); 2496| 2.29k| APFloat pow5(calcSemantics); 2497| | 2498| 2.29k| sigStatus = decSig.convertFromUnsignedParts(decSigParts, sigPartCount, 2499| 2.29k| rmNearestTiesToEven); 2500| 2.29k| powStatus = pow5.convertFromUnsignedParts(pow5Parts, pow5PartCount, 2501| 2.29k| rmNearestTiesToEven); 2502| | /* Add exp, as 10^n = 5^n * 2^n. */ 2503| 2.29k| decSig.exponent += exp; 2504| | 2505| 2.29k| lostFraction calcLostFraction; 2506| 2.29k| integerPart HUerr, HUdistance; 2507| 2.29k| unsigned int powHUerr; 2508| | 2509| 2.29k| if (exp >= 0) { ------------------ | Branch (2509:9): [True: 1.05k, False: 1.24k] ------------------ 2510| | /* multiplySignificand leaves the precision-th bit set to 1. */ 2511| 1.05k| calcLostFraction = decSig.multiplySignificand(pow5, nullptr); 2512| 1.05k| powHUerr = powStatus != opOK; 2513| 1.24k| } else { 2514| 1.24k| calcLostFraction = decSig.divideSignificand(pow5); 2515| | /* Denormal numbers have less precision. */ 2516| 1.24k| if (decSig.exponent < semantics->minExponent) { ------------------ | Branch (2516:11): [True: 3, False: 1.24k] ------------------ 2517| 3| excessPrecision += (semantics->minExponent - decSig.exponent); 2518| 3| truncatedBits = excessPrecision; 2519| 3| if (excessPrecision > calcSemantics.precision) ------------------ | Branch (2519:13): [True: 0, False: 3] ------------------ 2520| 0| excessPrecision = calcSemantics.precision; 2521| 3| } 2522| | /* Extra half-ulp lost in reciprocal of exponent. */ 2523| 1.24k| powHUerr = (powStatus == opOK && calcLostFraction == lfExactlyZero) ? 0:2; ------------------ | Branch (2523:19): [True: 938, False: 309] | Branch (2523:40): [True: 13, False: 925] ------------------ 2524| 1.24k| } 2525| | 2526| | /* Both multiplySignificand and divideSignificand return the 2527| | result with the integer bit set. */ 2528| 2.29k| assert(APInt::tcExtractBit ------------------ | Branch (2528:5): [True: 2.29k, False: 0] ------------------ 2529| 2.29k| (decSig.significandParts(), calcSemantics.precision - 1) == 1); 2530| | 2531| 2.29k| HUerr = HUerrBound(calcLostFraction != lfExactlyZero, sigStatus != opOK, 2532| 2.29k| powHUerr); 2533| 2.29k| HUdistance = 2 * ulpsFromBoundary(decSig.significandParts(), 2534| 2.29k| excessPrecision, isNearest); 2535| | 2536| | /* Are we guaranteed to round correctly if we truncate? */ 2537| 2.29k| if (HUdistance >= HUerr) { ------------------ | Branch (2537:9): [True: 1.87k, False: 424] ------------------ 2538| 1.87k| APInt::tcExtract(significandParts(), partCount(), decSig.significandParts(), 2539| 1.87k| calcSemantics.precision - excessPrecision, 2540| 1.87k| excessPrecision); 2541| | /* Take the exponent of decSig. If we tcExtract-ed less bits 2542| | above we must adjust our exponent to compensate for the 2543| | implicit right shift. */ 2544| 1.87k| exponent = (decSig.exponent + semantics->precision 2545| 1.87k| - (calcSemantics.precision - excessPrecision)); 2546| 1.87k| calcLostFraction = lostFractionThroughTruncation(decSig.significandParts(), 2547| 1.87k| decSig.partCount(), 2548| 1.87k| truncatedBits); 2549| 1.87k| return normalize(rounding_mode, calcLostFraction); 2550| 1.87k| } 2551| 2.29k| } 2552| 1.87k|} _ZN7llvm_ks7APFloat24convertFromDecimalStringENS_9StringRefENS0_12roundingModeE: 2556| 2.50k|{ 2557| 2.50k| decimalInfo D; 2558| 2.50k| opStatus fs; 2559| | 2560| | /* Scan the text. */ 2561| 2.50k| StringRef::iterator p = str.begin(); 2562| 2.50k| fs = interpretDecimal(p, str.end(), &D); 2563| 2.50k| if (fs != opOK) ------------------ | Branch (2563:7): [True: 308, False: 2.19k] ------------------ 2564| 308| return fs; 2565| | 2566| | /* Handle the quick cases. First the case of no significant digits, 2567| | i.e. zero, and then exponents that are obviously too large or too 2568| | small. Writing L for log 10 / log 2, a number d.ddddd*10^exp 2569| | definitely overflows if 2570| | 2571| | (exp - 1) * L >= maxExponent 2572| | 2573| | and definitely underflows to zero where 2574| | 2575| | (exp + 1) * L <= minExponent - precision 2576| | 2577| | With integer arithmetic the tightest bounds for L are 2578| | 2579| | 93/28 < L < 196/59 [ numerator <= 256 ] 2580| | 42039/12655 < L < 28738/8651 [ numerator <= 65536 ] 2581| | */ 2582| | 2583| | // Test if we have a zero number allowing for strings with no null terminators 2584| | // and zero decimals with non-zero exponents. 2585| | // 2586| | // We computed firstSigDigit by ignoring all zeros and dots. Thus if 2587| | // D->firstSigDigit equals str.end(), every digit must be a zero and there can 2588| | // be at most one dot. On the other hand, if we have a zero with a non-zero 2589| | // exponent, then we know that D.firstSigDigit will be non-numeric. 2590| 2.19k| if (D.firstSigDigit == str.end() || decDigitValue(*D.firstSigDigit) >= 10U) { ------------------ | Branch (2590:7): [True: 190, False: 2.00k] | Branch (2590:39): [True: 0, False: 2.00k] ------------------ 2591| 190| category = fcZero; 2592| 190| fs = opOK; 2593| | 2594| | /* Check whether the normalized exponent is high enough to overflow 2595| | max during the log-rebasing in the max-exponent check below. */ 2596| 2.00k| } else if (D.normalizedExponent - 1 > INT_MAX / 42039) { ------------------ | Branch (2596:14): [True: 0, False: 2.00k] ------------------ 2597| 0| fs = handleOverflow(rounding_mode); 2598| | 2599| | /* If it wasn't, then it also wasn't high enough to overflow max 2600| | during the log-rebasing in the min-exponent check. Check that it 2601| | won't overflow min in either check, then perform the min-exponent 2602| | check. */ 2603| 2.00k| } else if (D.normalizedExponent - 1 < INT_MIN / 42039 || ------------------ | Branch (2603:14): [True: 1, False: 2.00k] ------------------ 2604| 2.00k| (D.normalizedExponent + 1) * 28738 <= ------------------ | Branch (2604:14): [True: 130, False: 1.87k] ------------------ 2605| 2.00k| 8651 * (semantics->minExponent - (int) semantics->precision)) { 2606| | /* Underflow to zero and round. */ 2607| 131| category = fcNormal; 2608| 131| zeroSignificand(); 2609| 131| fs = normalize(rounding_mode, lfLessThanHalf); 2610| | 2611| | /* We can finally safely perform the max-exponent check. */ 2612| 1.87k| } else if ((D.normalizedExponent - 1) * 42039 ------------------ | Branch (2612:14): [True: 1, False: 1.87k] ------------------ 2613| 1.87k| >= 12655 * semantics->maxExponent) { 2614| | /* Overflow and round. */ 2615| 1| fs = handleOverflow(rounding_mode); 2616| 1.87k| } else { 2617| 1.87k| integerPart *decSignificand; 2618| 1.87k| unsigned int partCount; 2619| | 2620| | /* A tight upper bound on number of bits required to hold an 2621| | N-digit decimal integer is N * 196 / 59. Allocate enough space 2622| | to hold the full significand, and an extra part required by 2623| | tcMultiplyPart. */ 2624| 1.87k| partCount = static_cast(D.lastSigDigit - D.firstSigDigit) + 1; 2625| 1.87k| partCount = partCountForBits(1 + 196 * partCount / 59); 2626| 1.87k| decSignificand = new integerPart[partCount + 1]; 2627| 1.87k| partCount = 0; 2628| | 2629| | /* Convert to binary efficiently - we do almost all multiplication 2630| | in an integerPart. When this would overflow do we do a single 2631| | bignum multiplication, and then revert again to multiplication 2632| | in an integerPart. */ 2633| 5.05k| do { 2634| 5.05k| integerPart decValue, val, multiplier; 2635| | 2636| 5.05k| val = 0; 2637| 5.05k| multiplier = 1; 2638| | 2639| 64.8k| do { 2640| 64.8k| if (*p == '.') { ------------------ | Branch (2640:13): [True: 827, False: 63.9k] ------------------ 2641| 827| p++; 2642| 827| if (p == str.end()) { ------------------ | Branch (2642:15): [True: 0, False: 827] ------------------ 2643| 0| break; 2644| 0| } 2645| 827| } 2646| 64.8k| decValue = decDigitValue(*p++); 2647| 64.8k| assert(decValue < 10U && "Invalid character in significand"); ------------------ | Branch (2647:9): [True: 64.8k, False: 0] | Branch (2647:9): [True: 64.8k, Folded] | Branch (2647:9): [True: 64.8k, False: 0] ------------------ 2648| 64.8k| multiplier *= 10; 2649| 64.8k| val = val * 10 + decValue; 2650| | /* The maximum number that can be multiplied by ten with any 2651| | digit added without overflowing an integerPart. */ 2652| 64.8k| } while (p <= D.lastSigDigit && multiplier <= (~ (integerPart) 0 - 9) / 10); ------------------ | Branch (2652:16): [True: 62.9k, False: 1.87k] | Branch (2652:39): [True: 59.7k, False: 3.17k] ------------------ 2653| | 2654| | /* Multiply out the current part. */ 2655| 5.05k| APInt::tcMultiplyPart(decSignificand, decSignificand, multiplier, val, 2656| 5.05k| partCount, partCount + 1, false); 2657| | 2658| | /* If we used another part (likely but not guaranteed), increase 2659| | the count. */ 2660| 5.05k| if (decSignificand[partCount]) ------------------ | Branch (2660:11): [True: 4.91k, False: 131] ------------------ 2661| 4.91k| partCount++; 2662| 5.05k| } while (p <= D.lastSigDigit); ------------------ | Branch (2662:14): [True: 3.17k, False: 1.87k] ------------------ 2663| | 2664| 1.87k| category = fcNormal; 2665| 1.87k| fs = roundSignificandWithExponent(decSignificand, partCount, 2666| 1.87k| D.exponent, rounding_mode); 2667| | 2668| 1.87k| delete [] decSignificand; 2669| 1.87k| } 2670| | 2671| 2.19k| return fs; 2672| 2.19k|} _ZN7llvm_ks7APFloat25convertFromStringSpecialsENS_9StringRefE: 2675| 3.40k|APFloat::convertFromStringSpecials(StringRef str) { 2676| 3.40k| if (str.equals("inf") || str.equals("INFINITY")) { ------------------ | Branch (2676:7): [True: 0, False: 3.40k] | Branch (2676:7): [True: 0, False: 3.40k] | Branch (2676:28): [True: 0, False: 3.40k] ------------------ 2677| 0| makeInf(false); 2678| 0| return true; 2679| 0| } 2680| | 2681| 3.40k| if (str.equals("-inf") || str.equals("-INFINITY")) { ------------------ | Branch (2681:7): [True: 0, False: 3.40k] | Branch (2681:7): [True: 0, False: 3.40k] | Branch (2681:29): [True: 0, False: 3.40k] ------------------ 2682| 0| makeInf(true); 2683| 0| return true; 2684| 0| } 2685| | 2686| 3.40k| if (str.equals("nan") || str.equals("NaN")) { ------------------ | Branch (2686:7): [True: 0, False: 3.40k] | Branch (2686:7): [True: 0, False: 3.40k] | Branch (2686:28): [True: 0, False: 3.40k] ------------------ 2687| 0| makeNaN(false, false); 2688| 0| return true; 2689| 0| } 2690| | 2691| 3.40k| if (str.equals("-nan") || str.equals("-NaN")) { ------------------ | Branch (2691:7): [True: 0, False: 3.40k] | Branch (2691:7): [True: 0, False: 3.40k] | Branch (2691:29): [True: 0, False: 3.40k] ------------------ 2692| 0| makeNaN(false, true); 2693| 0| return true; 2694| 0| } 2695| | 2696| 3.40k| return false; 2697| 3.40k|} _ZN7llvm_ks7APFloat17convertFromStringENS_9StringRefENS0_12roundingModeE: 2701| 3.40k|{ 2702| 3.40k| assert(!str.empty() && "Invalid string length"); ------------------ | Branch (2702:3): [True: 3.40k, False: 0] | Branch (2702:3): [True: 3.40k, Folded] | Branch (2702:3): [True: 3.40k, False: 0] ------------------ 2703| | 2704| | // Handle special cases. 2705| 3.40k| if (convertFromStringSpecials(str)) ------------------ | Branch (2705:7): [True: 0, False: 3.40k] ------------------ 2706| 0| return opOK; 2707| | 2708| | /* Handle a leading minus sign. */ 2709| 3.40k| StringRef::iterator p = str.begin(); 2710| 3.40k| size_t slen = str.size(); 2711| 3.40k| sign = *p == '-' ? 1 : 0; ------------------ | Branch (2711:10): [True: 0, False: 3.40k] ------------------ 2712| 3.40k| if (*p == '-' || *p == '+') { ------------------ | Branch (2712:7): [True: 0, False: 3.40k] | Branch (2712:20): [True: 0, False: 3.40k] ------------------ 2713| 0| p++; 2714| 0| slen--; 2715| 0| assert(slen && "String has no digits"); ------------------ | Branch (2715:5): [True: 0, False: 0] | Branch (2715:5): [True: 0, Folded] | Branch (2715:5): [True: 0, False: 0] ------------------ 2716| 0| } 2717| | 2718| 3.40k| if (slen >= 2 && p[0] == '0' && (p[1] == 'x' || p[1] == 'X')) { ------------------ | Branch (2718:7): [True: 2.61k, False: 794] | Branch (2718:20): [True: 1.05k, False: 1.56k] | Branch (2718:36): [True: 853, False: 198] | Branch (2718:51): [True: 51, False: 147] ------------------ 2719| 904| assert(slen - 2 && "Invalid string"); ------------------ | Branch (2719:5): [True: 904, False: 0] | Branch (2719:5): [True: 904, Folded] | Branch (2719:5): [True: 904, False: 0] ------------------ 2720| 904| return convertFromHexadecimalString(StringRef(p + 2, slen - 2), 2721| 904| rounding_mode); 2722| 904| } 2723| | 2724| 2.50k| return convertFromDecimalString(StringRef(p, slen), rounding_mode); 2725| 3.40k|} _ZNK7llvm_ks7APFloat27convertDoubleAPFloatToAPIntEv: 3048| 2.11k|{ 3049| 2.11k| assert(semantics == (const llvm_ks::fltSemantics*)&IEEEdouble); ------------------ | Branch (3049:3): [True: 2.11k, False: 0] ------------------ 3050| 2.11k| assert(partCount()==1); ------------------ | Branch (3050:3): [True: 2.11k, False: 0] ------------------ 3051| | 3052| 2.11k| uint64_t myexponent, mysignificand; 3053| | 3054| 2.11k| if (isFiniteNonZero()) { ------------------ | Branch (3054:7): [True: 1.34k, False: 769] ------------------ 3055| 1.34k| myexponent = exponent+1023; //bias 3056| 1.34k| mysignificand = *significandParts(); 3057| 1.34k| if (myexponent==1 && !(mysignificand & 0x10000000000000LL)) ------------------ | Branch (3057:9): [True: 111, False: 1.23k] | Branch (3057:26): [True: 3, False: 108] ------------------ 3058| 3| myexponent = 0; // denormal 3059| 1.34k| } else if (category==fcZero) { ------------------ | Branch (3059:14): [True: 188, False: 581] ------------------ 3060| 188| myexponent = 0; 3061| 188| mysignificand = 0; 3062| 581| } else if (category==fcInfinity) { ------------------ | Branch (3062:14): [True: 282, False: 299] ------------------ 3063| 282| myexponent = 0x7ff; 3064| 282| mysignificand = 0; 3065| 299| } else { 3066| 299| assert(category == fcNaN && "Unknown category!"); ------------------ | Branch (3066:5): [True: 299, False: 0] | Branch (3066:5): [True: 299, Folded] | Branch (3066:5): [True: 299, False: 0] ------------------ 3067| 299| myexponent = 0x7ff; 3068| 299| mysignificand = *significandParts(); 3069| 299| } 3070| | 3071| 2.11k| return APInt(64, ((((uint64_t)(sign & 1) << 63) | 3072| 2.11k| ((myexponent & 0x7ff) << 52) | 3073| 2.11k| (mysignificand & 0xfffffffffffffLL)))); 3074| 2.11k|} _ZNK7llvm_ks7APFloat26convertFloatAPFloatToAPIntEv: 3078| 2.21k|{ 3079| 2.21k| assert(semantics == (const llvm_ks::fltSemantics*)&IEEEsingle); ------------------ | Branch (3079:3): [True: 2.21k, False: 0] ------------------ 3080| 2.21k| assert(partCount()==1); ------------------ | Branch (3080:3): [True: 2.21k, False: 0] ------------------ 3081| | 3082| 2.21k| uint32_t myexponent, mysignificand; 3083| | 3084| 2.21k| if (isFiniteNonZero()) { ------------------ | Branch (3084:7): [True: 1.10k, False: 1.10k] ------------------ 3085| 1.10k| myexponent = exponent+127; //bias 3086| 1.10k| mysignificand = (uint32_t)*significandParts(); 3087| 1.10k| if (myexponent == 1 && !(mysignificand & 0x800000)) ------------------ | Branch (3087:9): [True: 0, False: 1.10k] | Branch (3087:28): [True: 0, False: 0] ------------------ 3088| 0| myexponent = 0; // denormal 3089| 1.10k| } else if (category==fcZero) { ------------------ | Branch (3089:14): [True: 186, False: 918] ------------------ 3090| 186| myexponent = 0; 3091| 186| mysignificand = 0; 3092| 918| } else if (category==fcInfinity) { ------------------ | Branch (3092:14): [True: 678, False: 240] ------------------ 3093| 678| myexponent = 0xff; 3094| 678| mysignificand = 0; 3095| 678| } else { 3096| 240| assert(category == fcNaN && "Unknown category!"); ------------------ | Branch (3096:5): [True: 240, False: 0] | Branch (3096:5): [True: 240, Folded] | Branch (3096:5): [True: 240, False: 0] ------------------ 3097| 240| myexponent = 0xff; 3098| 240| mysignificand = (uint32_t)*significandParts(); 3099| 240| } 3100| | 3101| 2.21k| return APInt(32, (((sign&1) << 31) | ((myexponent&0xff) << 23) | 3102| 2.21k| (mysignificand & 0x7fffff))); 3103| 2.21k|} _ZNK7llvm_ks7APFloat14bitcastToAPIntEv: 3140| 4.32k|{ 3141| 4.32k| if (semantics == (const llvm_ks::fltSemantics*)&IEEEhalf) ------------------ | Branch (3141:7): [True: 0, False: 4.32k] ------------------ 3142| 0| return convertHalfAPFloatToAPInt(); 3143| | 3144| 4.32k| if (semantics == (const llvm_ks::fltSemantics*)&IEEEsingle) ------------------ | Branch (3144:7): [True: 2.21k, False: 2.11k] ------------------ 3145| 2.21k| return convertFloatAPFloatToAPInt(); 3146| | 3147| 2.11k| if (semantics == (const llvm_ks::fltSemantics*)&IEEEdouble) ------------------ | Branch (3147:7): [True: 2.11k, False: 0] ------------------ 3148| 2.11k| return convertDoubleAPFloatToAPInt(); 3149| | 3150| 0| if (semantics == (const llvm_ks::fltSemantics*)&IEEEquad) ------------------ | Branch (3150:7): [True: 0, False: 0] ------------------ 3151| 0| return convertQuadrupleAPFloatToAPInt(); 3152| | 3153| 0| if (semantics == (const llvm_ks::fltSemantics*)&PPCDoubleDouble) ------------------ | Branch (3153:7): [True: 0, False: 0] ------------------ 3154| 0| return convertPPCDoubleDoubleAPFloatToAPInt(); 3155| | 3156| 0| assert(semantics == (const llvm_ks::fltSemantics*)&x87DoubleExtended && ------------------ | Branch (3156:3): [True: 0, False: 0] | Branch (3156:3): [True: 0, Folded] | Branch (3156:3): [True: 0, False: 0] ------------------ 3157| 0| "unknown format!"); 3158| 0| return convertF80LongDoubleAPFloatToAPInt(); 3159| 0|} _ZN7llvm_ks7APFloat7makeInfEb: 3968| 678|APFloat::makeInf(bool Negative) { 3969| 678| category = fcInfinity; 3970| 678| sign = Negative; 3971| 678| exponent = semantics->maxExponent + 1; 3972| 678| APInt::tcSet(significandParts(), 0, partCount()); 3973| 678|} _ZN7llvm_ks7APFloat8makeZeroEb: 3976| 2.29k|APFloat::makeZero(bool Negative) { 3977| 2.29k| category = fcZero; 3978| 2.29k| sign = Negative; 3979| 2.29k| exponent = semantics->minExponent-1; 3980| 2.29k| APInt::tcSet(significandParts(), 0, partCount()); 3981| 2.29k|} APFloat.cpp:_ZL26skipLeadingZeroesAndAnyDotPKcS0_PS0_: 236| 3.40k|{ 237| 3.40k| StringRef::iterator p = begin; 238| 3.40k| *dot = end; 239| 4.18k| while (p != end && *p == '0') ------------------ | Branch (239:10): [True: 4.06k, False: 118] | Branch (239:22): [True: 773, False: 3.29k] ------------------ 240| 773| p++; 241| | 242| 3.40k| if (p != end && *p == '.') { ------------------ | Branch (242:7): [True: 3.29k, False: 118] | Branch (242:19): [True: 1.53k, False: 1.75k] ------------------ 243| 1.53k| *dot = p++; 244| | 245| 1.53k| assert(end - begin != 1 && "Significand has no digits"); ------------------ | Branch (245:5): [True: 1.53k, False: 0] | Branch (245:5): [True: 1.53k, Folded] | Branch (245:5): [True: 1.53k, False: 0] ------------------ 246| | 247| 4.38k| while (p != end && *p == '0') ------------------ | Branch (247:12): [True: 4.30k, False: 72] | Branch (247:24): [True: 2.84k, False: 1.46k] ------------------ 248| 2.84k| p++; 249| 1.53k| } 250| | 251| 3.40k| return p; 252| 3.40k|} APFloat.cpp:_ZL13decDigitValuej: 109| 136k|{ 110| 136k| return c - '0'; 111| 136k|} APFloat.cpp:_ZL12readExponentPKcS0_RN7llvm_ks7APFloat8opStatusE: 120| 641|{ 121| 641| bool isNegative; 122| 641| unsigned int absExponent; 123| 641| const unsigned int overlargeExponent = 24000; /* FIXME. */ 124| 641| StringRef::iterator p = begin; 125| | 126| 641| fp = APFloat::opOK; 127| | 128| | //assert(p != end && "Exponent has no digits"); // qq 129| 641| if (p == end) { ------------------ | Branch (129:7): [True: 2, False: 639] ------------------ 130| 2| fp = APFloat::opInvalidOp; 131| 2| return 0; 132| 2| } 133| | 134| 639| isNegative = (*p == '-'); 135| 639| if (*p == '-' || *p == '+') { ------------------ | Branch (135:7): [True: 348, False: 291] | Branch (135:20): [True: 252, False: 39] ------------------ 136| 600| p++; 137| | //assert(p != end && "Exponent has no digits"); 138| 600| if (p == end) { ------------------ | Branch (138:9): [True: 306, False: 294] ------------------ 139| 306| fp = APFloat::opInvalidOp; 140| 306| return 0; 141| 306| } 142| 600| } 143| | 144| 333| absExponent = decDigitValue(*p++); 145| | //assert(absExponent < 10U && "Invalid character in exponent"); 146| 333| if (absExponent >= 10U) { ------------------ | Branch (146:7): [True: 0, False: 333] ------------------ 147| 0| fp = APFloat::opInvalidOp; 148| 0| return 0; 149| 0| } 150| | 151| 1.40k| for (; p != end; ++p) { ------------------ | Branch (151:10): [True: 1.20k, False: 203] ------------------ 152| 1.20k| unsigned int value; 153| | 154| 1.20k| value = decDigitValue(*p); 155| | //assert(value < 10U && "Invalid character in exponent"); 156| 1.20k| if (value >= 10U) { ------------------ | Branch (156:9): [True: 0, False: 1.20k] ------------------ 157| 0| fp = APFloat::opInvalidOp; 158| 0| return 0; 159| 0| } 160| | 161| 1.20k| value += absExponent * 10; 162| 1.20k| if (absExponent >= overlargeExponent) { ------------------ | Branch (162:9): [True: 130, False: 1.07k] ------------------ 163| 130| absExponent = overlargeExponent; 164| 130| p = end; /* outwit assert below */ 165| 130| break; 166| 130| } 167| 1.07k| absExponent = value; 168| 1.07k| } 169| | 170| | //assert(p == end && "Invalid exponent in exponent"); 171| 333| if (p != end) { ------------------ | Branch (171:7): [True: 0, False: 333] ------------------ 172| 0| fp = APFloat::opInvalidOp; 173| 0| return 0; 174| 0| } 175| | 176| 333| if (isNegative) ------------------ | Branch (176:7): [True: 294, False: 39] ------------------ 177| 294| return -(int) absExponent; 178| 39| else 179| 39| return (int) absExponent; 180| 333|} APFloat.cpp:_ZL16partCountForBitsj: 102| 106k|{ 103| 106k| return ((bits) + integerPartWidth - 1) / integerPartWidth; 104| 106k|} APFloat.cpp:_ZL10shiftRightPmjj: 401| 1.63k|{ 402| 1.63k| lostFraction lost_fraction; 403| | 404| 1.63k| lost_fraction = lostFractionThroughTruncation(dst, parts, bits); 405| | 406| 1.63k| APInt::tcShiftRight(dst, parts, bits); 407| | 408| 1.63k| return lost_fraction; 409| 1.63k|} APFloat.cpp:_ZL20combineLostFractionsN7llvm_ks12lostFractionES0_: 415| 1.63k|{ 416| 1.63k| if (lessSignificant != lfExactlyZero) { ------------------ | Branch (416:7): [True: 298, False: 1.33k] ------------------ 417| 298| if (moreSignificant == lfExactlyZero) ------------------ | Branch (417:9): [True: 85, False: 213] ------------------ 418| 85| moreSignificant = lfLessThanHalf; 419| 213| else if (moreSignificant == lfExactlyHalf) ------------------ | Branch (419:14): [True: 0, False: 213] ------------------ 420| 0| moreSignificant = lfMoreThanHalf; 421| 298| } 422| | 423| 1.63k| return moreSignificant; 424| 1.63k|} APFloat.cpp:_ZL29lostFractionThroughTruncationPKmjj: 381| 4.00k|{ 382| 4.00k| unsigned int lsb; 383| | 384| 4.00k| lsb = APInt::tcLSB(parts, partCount); 385| | 386| | /* Note this is guaranteed true if bits == 0, or LSB == -1U. */ 387| 4.00k| if (bits <= lsb) ------------------ | Branch (387:7): [True: 2.39k, False: 1.60k] ------------------ 388| 2.39k| return lfExactlyZero; 389| 1.60k| if (bits == lsb + 1) ------------------ | Branch (389:7): [True: 9, False: 1.59k] ------------------ 390| 9| return lfExactlyHalf; 391| 1.59k| if (bits <= partCount * integerPartWidth && ------------------ | Branch (391:7): [True: 1.59k, False: 8] ------------------ 392| 1.59k| APInt::tcExtractBit(parts, bits - 1)) ------------------ | Branch (392:7): [True: 910, False: 681] ------------------ 393| 910| return lfMoreThanHalf; 394| | 395| 689| return lfLessThanHalf; 396| 1.59k|} APFloat.cpp:_ZL27trailingHexadecimalFractionPKcS0_j: 349| 449|{ 350| 449| unsigned int hexDigit; 351| | 352| | /* If the first trailing digit isn't 0 or 8 we can work out the 353| | fraction immediately. */ 354| 449| if (digitValue > 8) ------------------ | Branch (354:7): [True: 15, False: 434] ------------------ 355| 15| return lfMoreThanHalf; 356| 434| else if (digitValue < 8 && digitValue > 0) ------------------ | Branch (356:12): [True: 329, False: 105] | Branch (356:30): [True: 152, False: 177] ------------------ 357| 152| return lfLessThanHalf; 358| | 359| | // Otherwise we need to find the first non-zero digit. 360| 1.41k| while (p != end && (*p == '0' || *p == '.')) ------------------ | Branch (360:10): [True: 1.41k, False: 0] | Branch (360:23): [True: 1.09k, False: 314] | Branch (360:36): [True: 32, False: 282] ------------------ 361| 1.13k| p++; 362| | 363| 282| assert(p != end && "Invalid trailing hexadecimal fraction!"); ------------------ | Branch (363:3): [True: 282, False: 0] | Branch (363:3): [True: 282, Folded] | Branch (363:3): [True: 282, False: 0] ------------------ 364| | 365| 282| hexDigit = hexDigitValue(*p); 366| | 367| | /* If we ran off the end it is exactly zero or one-half, otherwise 368| | a little more. */ 369| 282| if (hexDigit == -1U) ------------------ | Branch (369:7): [True: 103, False: 179] ------------------ 370| 103| return digitValue == 0 ? lfExactlyZero: lfExactlyHalf; ------------------ | Branch (370:12): [True: 76, False: 27] ------------------ 371| 179| else 372| 179| return digitValue == 0 ? lfLessThanHalf: lfMoreThanHalf; ------------------ | Branch (372:12): [True: 101, False: 78] ------------------ 373| 282|} APFloat.cpp:_ZL13totalExponentPKcS0_i: 187| 860|{ 188| 860| int unsignedExponent; 189| 860| bool negative, overflow; 190| 860| int exponent = 0; 191| | 192| 860| assert(p != end && "Exponent has no digits"); ------------------ | Branch (192:3): [True: 860, False: 0] | Branch (192:3): [True: 860, Folded] | Branch (192:3): [True: 860, False: 0] ------------------ 193| | 194| 860| negative = *p == '-'; 195| 860| if (*p == '-' || *p == '+') { ------------------ | Branch (195:7): [True: 8, False: 852] | Branch (195:20): [True: 214, False: 638] ------------------ 196| 222| p++; 197| 222| assert(p != end && "Exponent has no digits"); ------------------ | Branch (197:5): [True: 222, False: 0] | Branch (197:5): [True: 222, Folded] | Branch (197:5): [True: 222, False: 0] ------------------ 198| 222| } 199| | 200| 860| unsignedExponent = 0; 201| 860| overflow = false; 202| 2.75k| for (; p != end; ++p) { ------------------ | Branch (202:10): [True: 1.97k, False: 786] ------------------ 203| 1.97k| unsigned int value; 204| | 205| 1.97k| value = decDigitValue(*p); 206| 1.97k| assert(value < 10U && "Invalid character in exponent"); ------------------ | Branch (206:5): [True: 1.97k, False: 0] | Branch (206:5): [True: 1.97k, Folded] | Branch (206:5): [True: 1.97k, False: 0] ------------------ 207| | 208| 1.97k| unsignedExponent = unsignedExponent * 10 + value; 209| 1.97k| if (unsignedExponent > 32767) { ------------------ | Branch (209:9): [True: 74, False: 1.89k] ------------------ 210| 74| overflow = true; 211| 74| break; 212| 74| } 213| 1.97k| } 214| | 215| 860| if (exponentAdjustment > 32767 || exponentAdjustment < -32768) ------------------ | Branch (215:7): [True: 0, False: 860] | Branch (215:37): [True: 0, False: 860] ------------------ 216| 0| overflow = true; 217| | 218| 860| if (!overflow) { ------------------ | Branch (218:7): [True: 786, False: 74] ------------------ 219| 786| exponent = unsignedExponent; 220| 786| if (negative) ------------------ | Branch (220:9): [True: 8, False: 778] ------------------ 221| 8| exponent = -exponent; 222| 786| exponent += exponentAdjustment; 223| 786| if (exponent > 32767 || exponent < -32768) ------------------ | Branch (223:9): [True: 0, False: 786] | Branch (223:29): [True: 0, False: 786] ------------------ 224| 0| overflow = true; 225| 786| } 226| | 227| 860| if (overflow) ------------------ | Branch (227:7): [True: 74, False: 786] ------------------ 228| 74| exponent = negative ? -32768: 32767; ------------------ | Branch (228:16): [True: 0, False: 74] ------------------ 229| | 230| 860| return exponent; 231| 860|} APFloat.cpp:_ZL8powerOf5Pmj: 494| 1.87k|{ 495| 1.87k| static const integerPart firstEightPowers[] = { 1, 5, 25, 125, 625, 3125, 496| 1.87k| 15625, 78125 }; 497| 1.87k| integerPart pow5s[maxPowerOfFiveParts * 2 + 5]; 498| 1.87k| pow5s[0] = 78125 * 5; 499| | 500| 1.87k| unsigned int partsCount[16] = { 1 }; 501| 1.87k| integerPart scratch[maxPowerOfFiveParts], *p1, *p2, *pow5; 502| 1.87k| unsigned int result; 503| 1.87k| assert(power <= maxExponent); ------------------ | Branch (503:3): [True: 1.87k, False: 0] ------------------ 504| | 505| 1.87k| p1 = dst; 506| 1.87k| p2 = scratch; 507| | 508| 1.87k| *p1 = firstEightPowers[power & 7]; 509| 1.87k| power >>= 3; 510| | 511| 1.87k| result = 1; 512| 1.87k| pow5 = pow5s; 513| | 514| 3.01k| for (unsigned int n = 0; power; power >>= 1, n++) { ------------------ | Branch (514:28): [True: 1.13k, False: 1.87k] ------------------ 515| 1.13k| unsigned int pc; 516| | 517| 1.13k| pc = partsCount[n]; 518| | 519| | /* Calculate pow(5,pow(2,n+3)) if we haven't yet. */ 520| 1.13k| if (pc == 0) { ------------------ | Branch (520:9): [True: 937, False: 199] ------------------ 521| 937| pc = partsCount[n - 1]; 522| 937| APInt::tcFullMultiply(pow5, pow5 - pc, pow5 - pc, pc, pc); 523| 937| pc *= 2; 524| 937| if (pow5[pc - 1] == 0) ------------------ | Branch (524:11): [True: 565, False: 372] ------------------ 525| 565| pc--; 526| 937| partsCount[n] = pc; 527| 937| } 528| | 529| 1.13k| if (power & 1) { ------------------ | Branch (529:9): [True: 609, False: 527] ------------------ 530| 609| integerPart *tmp; 531| | 532| 609| APInt::tcFullMultiply(p2, p1, pow5, result, pc); 533| 609| result += pc; 534| 609| if (p2[result - 1] == 0) ------------------ | Branch (534:11): [True: 429, False: 180] ------------------ 535| 429| result--; 536| | 537| | /* Now result is in p1 with partsCount parts and p2 is scratch 538| | space. */ 539| 609| tmp = p1, p1 = p2, p2 = tmp; 540| 609| } 541| | 542| 1.13k| pow5 += pc; 543| 1.13k| } 544| | 545| 1.87k| if (p1 != dst) ------------------ | Branch (545:7): [True: 185, False: 1.68k] ------------------ 546| 185| APInt::tcAssign(dst, p1, result); 547| | 548| 1.87k| return result; 549| 1.87k|} APFloat.cpp:_ZL10HUerrBoundbjj: 435| 2.29k|{ 436| 2.29k| assert(HUerr1 < 2 || HUerr2 < 2 || (HUerr1 + HUerr2 < 8)); ------------------ | Branch (436:3): [True: 2.29k, False: 0] | Branch (436:3): [True: 0, False: 0] | Branch (436:3): [True: 0, False: 0] | Branch (436:3): [True: 2.29k, False: 0] ------------------ 437| | 438| 2.29k| if (HUerr1 + HUerr2 == 0) ------------------ | Branch (438:7): [True: 1.05k, False: 1.24k] ------------------ 439| 1.05k| return inexactMultiply * 2; /* <= inexactMultiply half-ulps. */ 440| 1.24k| else 441| 1.24k| return inexactMultiply + 2 * (HUerr1 + HUerr2); 442| 2.29k|} APFloat.cpp:_ZL16ulpsFromBoundaryPKmjb: 449| 2.29k|{ 450| 2.29k| unsigned int count, partBits; 451| 2.29k| integerPart part, boundary; 452| | 453| 2.29k| assert(bits != 0); ------------------ | Branch (453:3): [True: 2.29k, False: 0] ------------------ 454| | 455| 2.29k| bits--; 456| 2.29k| count = bits / integerPartWidth; 457| 2.29k| partBits = bits % integerPartWidth + 1; 458| | 459| 2.29k| part = parts[count] & (~(integerPart) 0 >> (integerPartWidth - partBits)); 460| | 461| 2.29k| if (isNearest) ------------------ | Branch (461:7): [True: 2.29k, False: 0] ------------------ 462| 2.29k| boundary = (integerPart) 1 << (partBits - 1); 463| 0| else 464| 0| boundary = 0; 465| | 466| 2.29k| if (count == 0) { ------------------ | Branch (466:7): [True: 1.87k, False: 424] ------------------ 467| 1.87k| if (part - boundary <= boundary - part) ------------------ | Branch (467:9): [True: 545, False: 1.32k] ------------------ 468| 545| return part - boundary; 469| 1.32k| else 470| 1.32k| return boundary - part; 471| 1.87k| } 472| | 473| 424| if (part == boundary) { ------------------ | Branch (473:7): [True: 93, False: 331] ------------------ 474| 3.32k| while (--count) ------------------ | Branch (474:12): [True: 3.25k, False: 75] ------------------ 475| 3.25k| if (parts[count]) ------------------ | Branch (475:11): [True: 18, False: 3.23k] ------------------ 476| 18| return ~(integerPart) 0; /* A lot. */ 477| | 478| 75| return parts[0]; 479| 331| } else if (part == boundary - 1) { ------------------ | Branch (479:14): [True: 202, False: 129] ------------------ 480| 1.63k| while (--count) ------------------ | Branch (480:12): [True: 1.43k, False: 196] ------------------ 481| 1.43k| if (~parts[count]) ------------------ | Branch (481:11): [True: 6, False: 1.43k] ------------------ 482| 6| return ~(integerPart) 0; /* A lot. */ 483| | 484| 196| return -parts[0]; 485| 202| } 486| | 487| 129| return ~(integerPart) 0; /* A lot. */ 488| 424|} _ZN7llvm_ks5APInt12initSlowCaseEjmb: 77| 12.0k|void APInt::initSlowCase(unsigned numBits, uint64_t val, bool isSigned) { 78| 12.0k| pVal = getClearedMemory(getNumWords()); 79| 12.0k| pVal[0] = val; 80| 12.0k| if (isSigned && int64_t(val) < 0) ------------------ | Branch (80:7): [True: 11.7k, False: 274] | Branch (80:19): [True: 0, False: 11.7k] ------------------ 81| 0| for (unsigned i = 1; i < getNumWords(); ++i) ------------------ | Branch (81:26): [True: 0, False: 0] ------------------ 82| 0| pVal[i] = -1ULL; 83| 12.0k|} _ZN7llvm_ks5APInt12initSlowCaseERKS0_: 85| 22.1k|void APInt::initSlowCase(const APInt& that) { 86| 22.1k| pVal = getMemory(getNumWords()); 87| 22.1k| memcpy(pVal, that.pVal, getNumWords() * APINT_WORD_SIZE); 88| 22.1k|} _ZN7llvm_ks5APInt14AssignSlowCaseERKS0_: 123| 279|APInt& APInt::AssignSlowCase(const APInt& RHS) { 124| | // Don't do anything for X = X 125| 279| if (this == &RHS) ------------------ | Branch (125:7): [True: 0, False: 279] ------------------ 126| 0| return *this; 127| | 128| 279| if (BitWidth == RHS.getBitWidth()) { ------------------ | Branch (128:7): [True: 61, False: 218] ------------------ 129| | // assume same bit-width single-word case is already handled 130| 61| assert(!isSingleWord()); ------------------ | Branch (130:5): [True: 61, False: 0] ------------------ 131| 61| memcpy(pVal, RHS.pVal, getNumWords() * APINT_WORD_SIZE); 132| 61| return *this; 133| 61| } 134| | 135| 218| if (isSingleWord()) { ------------------ | Branch (135:7): [True: 109, False: 109] ------------------ 136| | // assume case where both are single words is already handled 137| 109| assert(!RHS.isSingleWord()); ------------------ | Branch (137:5): [True: 109, False: 0] ------------------ 138| 109| VAL = 0; 139| 109| pVal = getMemory(RHS.getNumWords()); 140| 109| memcpy(pVal, RHS.pVal, RHS.getNumWords() * APINT_WORD_SIZE); 141| 109| } else if (getNumWords() == RHS.getNumWords()) ------------------ | Branch (141:14): [True: 0, False: 109] ------------------ 142| 0| memcpy(pVal, RHS.pVal, RHS.getNumWords() * APINT_WORD_SIZE); 143| 109| else if (RHS.isSingleWord()) { ------------------ | Branch (143:12): [True: 109, False: 0] ------------------ 144| 109| delete [] pVal; 145| 109| VAL = RHS.VAL; 146| 109| } else { 147| 0| delete [] pVal; 148| 0| pVal = getMemory(RHS.getNumWords()); 149| 0| memcpy(pVal, RHS.pVal, RHS.getNumWords() * APINT_WORD_SIZE); 150| 0| } 151| 218| BitWidth = RHS.BitWidth; 152| 218| return clearUnusedBits(); 153| 218|} _ZN7llvm_ks5APIntaSEm: 155| 10.0k|APInt& APInt::operator=(uint64_t RHS) { 156| 10.0k| if (isSingleWord()) ------------------ | Branch (156:7): [True: 0, False: 10.0k] ------------------ 157| 0| VAL = RHS; 158| 10.0k| else { 159| 10.0k| pVal[0] = RHS; 160| 10.0k| memset(pVal+1, 0, (getNumWords() - 1) * APINT_WORD_SIZE); 161| 10.0k| } 162| 10.0k| return clearUnusedBits(); 163| 10.0k|} _ZNK7llvm_ks5APInt9getHiBitsEj: 686| 148|APInt APInt::getHiBits(unsigned numBits) const { 687| 148| return APIntOps::lshr(*this, BitWidth - numBits); 688| 148|} _ZNK7llvm_ks5APInt9getLoBitsEj: 691| 148|APInt APInt::getLoBits(unsigned numBits) const { 692| 148| return APIntOps::lshr(APIntOps::shl(*this, BitWidth - numBits), 693| 148| BitWidth - numBits); 694| 148|} _ZNK7llvm_ks5APInt25countLeadingZerosSlowCaseEv: 696| 16.9k|unsigned APInt::countLeadingZerosSlowCase() const { 697| | // Treat the most significand word differently because it might have 698| | // meaningless bits set beyond the precision. 699| 16.9k| unsigned BitsInMSW = BitWidth % APINT_BITS_PER_WORD; 700| 16.9k| integerPart MSWMask; 701| 16.9k| if (BitsInMSW) MSWMask = (integerPart(1) << BitsInMSW) - 1; ------------------ | Branch (701:7): [True: 33, False: 16.9k] ------------------ 702| 16.9k| else { 703| 16.9k| MSWMask = ~integerPart(0); 704| 16.9k| BitsInMSW = APINT_BITS_PER_WORD; 705| 16.9k| } 706| | 707| 16.9k| unsigned i = getNumWords(); 708| 16.9k| integerPart MSW = pVal[i-1] & MSWMask; 709| 16.9k| if (MSW) ------------------ | Branch (709:7): [True: 533, False: 16.4k] ------------------ 710| 533| return llvm_ks::countLeadingZeros(MSW) - (APINT_BITS_PER_WORD - BitsInMSW); 711| | 712| 16.4k| unsigned Count = BitsInMSW; 713| 16.5k| for (--i; i > 0u; --i) { ------------------ | Branch (713:13): [True: 16.4k, False: 136] ------------------ 714| 16.4k| if (pVal[i-1] == 0) ------------------ | Branch (714:9): [True: 136, False: 16.2k] ------------------ 715| 136| Count += APINT_BITS_PER_WORD; 716| 16.2k| else { 717| 16.2k| Count += llvm_ks::countLeadingZeros(pVal[i-1]); 718| 16.2k| break; 719| 16.2k| } 720| 16.4k| } 721| 16.4k| return Count; 722| 16.9k|} _ZNK7llvm_ks5APInt4zextEj: 998| 42|APInt APInt::zext(unsigned width) const { 999| 42| assert(width > BitWidth && "Invalid APInt ZeroExtend request"); ------------------ | Branch (999:3): [True: 42, False: 0] | Branch (999:3): [True: 42, Folded] | Branch (999:3): [True: 42, False: 0] ------------------ 1000| | 1001| 42| if (width <= APINT_BITS_PER_WORD) ------------------ | Branch (1001:7): [True: 0, False: 42] ------------------ 1002| 0| return APInt(width, VAL); 1003| | 1004| 42| APInt Result(getMemory(getNumWords(width)), width); 1005| | 1006| | // Copy words. 1007| 42| unsigned i; 1008| 126| for (i = 0; i != getNumWords(); i++) ------------------ | Branch (1008:15): [True: 84, False: 42] ------------------ 1009| 84| Result.pVal[i] = getRawData()[i]; 1010| | 1011| | // Zero remaining words. 1012| 42| memset(&Result.pVal[i], 0, (Result.getNumWords() - i) * APINT_WORD_SIZE); 1013| | 1014| 42| return Result; 1015| 42|} _ZNK7llvm_ks5APInt4lshrEj: 1144| 296|APInt APInt::lshr(unsigned shiftAmt) const { 1145| 296| if (isSingleWord()) { ------------------ | Branch (1145:7): [True: 0, False: 296] ------------------ 1146| 0| if (shiftAmt >= BitWidth) ------------------ | Branch (1146:9): [True: 0, False: 0] ------------------ 1147| 0| return APInt(BitWidth, 0); 1148| 0| else 1149| 0| return APInt(BitWidth, this->VAL >> shiftAmt); 1150| 0| } 1151| | 1152| | // If all the bits were shifted out, the result is 0. This avoids issues 1153| | // with shifting by the size of the integer type, which produces undefined 1154| | // results. We define these "undefined results" to always be 0. 1155| 296| if (shiftAmt >= BitWidth) ------------------ | Branch (1155:7): [True: 0, False: 296] ------------------ 1156| 0| return APInt(BitWidth, 0); 1157| | 1158| | // If none of the bits are shifted out, the result is *this. This avoids 1159| | // issues with shifting by the size of the integer type, which produces 1160| | // undefined results in the code below. This is also an optimization. 1161| 296| if (shiftAmt == 0) ------------------ | Branch (1161:7): [True: 0, False: 296] ------------------ 1162| 0| return *this; 1163| | 1164| | // Create some space for the result. 1165| 296| uint64_t * val = new uint64_t[getNumWords()]; 1166| | 1167| | // If we are shifting less than a word, compute the shift with a simple carry 1168| 296| if (shiftAmt < APINT_BITS_PER_WORD) { ------------------ | Branch (1168:7): [True: 0, False: 296] ------------------ 1169| 0| lshrNear(val, pVal, getNumWords(), shiftAmt); 1170| 0| APInt Result(val, BitWidth); 1171| 0| Result.clearUnusedBits(); 1172| 0| return Result; 1173| 0| } 1174| | 1175| | // Compute some values needed by the remaining shift algorithms 1176| 296| unsigned wordShift = shiftAmt % APINT_BITS_PER_WORD; 1177| 296| unsigned offset = shiftAmt / APINT_BITS_PER_WORD; 1178| | 1179| | // If we are shifting whole words, just move whole words 1180| 296| if (wordShift == 0) { ------------------ | Branch (1180:7): [True: 296, False: 0] ------------------ 1181| 592| for (unsigned i = 0; i < getNumWords() - offset; ++i) ------------------ | Branch (1181:26): [True: 296, False: 296] ------------------ 1182| 296| val[i] = pVal[i+offset]; 1183| 592| for (unsigned i = getNumWords()-offset; i < getNumWords(); i++) ------------------ | Branch (1183:45): [True: 296, False: 296] ------------------ 1184| 296| val[i] = 0; 1185| 296| APInt Result(val, BitWidth); 1186| 296| Result.clearUnusedBits(); 1187| 296| return Result; 1188| 296| } 1189| | 1190| | // Shift the low order words 1191| 0| unsigned breakWord = getNumWords() - offset -1; 1192| 0| for (unsigned i = 0; i < breakWord; ++i) ------------------ | Branch (1192:24): [True: 0, False: 0] ------------------ 1193| 0| val[i] = (pVal[i+offset] >> wordShift) | 1194| 0| (pVal[i+offset+1] << (APINT_BITS_PER_WORD - wordShift)); 1195| | // Shift the break word. 1196| 0| val[breakWord] = pVal[breakWord+offset] >> wordShift; 1197| | 1198| | // Remaining words are 0 1199| 0| for (unsigned i = breakWord+1; i < getNumWords(); ++i) ------------------ | Branch (1199:34): [True: 0, False: 0] ------------------ 1200| 0| val[i] = 0; 1201| 0| APInt Result(val, BitWidth); 1202| 0| Result.clearUnusedBits(); 1203| 0| return Result; 1204| 296|} _ZNK7llvm_ks5APInt11shlSlowCaseEj: 1213| 64.6k|APInt APInt::shlSlowCase(unsigned shiftAmt) const { 1214| | // If all the bits were shifted out, the result is 0. This avoids issues 1215| | // with shifting by the size of the integer type, which produces undefined 1216| | // results. We define these "undefined results" to always be 0. 1217| 64.6k| if (shiftAmt == BitWidth) ------------------ | Branch (1217:7): [True: 0, False: 64.6k] ------------------ 1218| 0| return APInt(BitWidth, 0); 1219| | 1220| | // If none of the bits are shifted out, the result is *this. This avoids a 1221| | // lshr by the words size in the loop below which can produce incorrect 1222| | // results. It also avoids the expensive computation below for a common case. 1223| 64.6k| if (shiftAmt == 0) ------------------ | Branch (1223:7): [True: 0, False: 64.6k] ------------------ 1224| 0| return *this; 1225| | 1226| | // Create some space for the result. 1227| 64.6k| uint64_t * val = new uint64_t[getNumWords()]; 1228| | 1229| | // If we are shifting less than a word, do it the easy way 1230| 64.6k| if (shiftAmt < APINT_BITS_PER_WORD) { ------------------ | Branch (1230:7): [True: 64.5k, False: 148] ------------------ 1231| 64.5k| uint64_t carry = 0; 1232| 5.57M| for (unsigned i = 0; i < getNumWords(); i++) { ------------------ | Branch (1232:26): [True: 5.50M, False: 64.5k] ------------------ 1233| 5.50M| val[i] = pVal[i] << shiftAmt | carry; 1234| 5.50M| carry = pVal[i] >> (APINT_BITS_PER_WORD - shiftAmt); 1235| 5.50M| } 1236| 64.5k| APInt Result(val, BitWidth); 1237| 64.5k| Result.clearUnusedBits(); 1238| 64.5k| return Result; 1239| 64.5k| } 1240| | 1241| | // Compute some values needed by the remaining shift algorithms 1242| 148| unsigned wordShift = shiftAmt % APINT_BITS_PER_WORD; 1243| 148| unsigned offset = shiftAmt / APINT_BITS_PER_WORD; 1244| | 1245| | // If we are shifting whole words, just move whole words 1246| 148| if (wordShift == 0) { ------------------ | Branch (1246:7): [True: 148, False: 0] ------------------ 1247| 296| for (unsigned i = 0; i < offset; i++) ------------------ | Branch (1247:26): [True: 148, False: 148] ------------------ 1248| 148| val[i] = 0; 1249| 296| for (unsigned i = offset; i < getNumWords(); i++) ------------------ | Branch (1249:31): [True: 148, False: 148] ------------------ 1250| 148| val[i] = pVal[i-offset]; 1251| 148| APInt Result(val, BitWidth); 1252| 148| Result.clearUnusedBits(); 1253| 148| return Result; 1254| 148| } 1255| | 1256| | // Copy whole words from this to Result. 1257| 0| unsigned i = getNumWords() - 1; 1258| 0| for (; i > offset; --i) ------------------ | Branch (1258:10): [True: 0, False: 0] ------------------ 1259| 0| val[i] = pVal[i-offset] << wordShift | 1260| 0| pVal[i-offset-1] >> (APINT_BITS_PER_WORD - wordShift); 1261| 0| val[offset] = pVal[0] << wordShift; 1262| 0| for (i = 0; i < offset; ++i) ------------------ | Branch (1262:15): [True: 0, False: 0] ------------------ 1263| 0| val[i] = 0; 1264| 0| APInt Result(val, BitWidth); 1265| 0| Result.clearUnusedBits(); 1266| 0| return Result; 1267| 148|} _ZN7llvm_ks5APInt5tcSetEPmmj: 2307| 6.60k|{ 2308| 6.60k| unsigned int i; 2309| | 2310| 6.60k| assert(parts > 0); ------------------ | Branch (2310:3): [True: 6.60k, False: 0] ------------------ 2311| | 2312| 6.60k| dst[0] = part; 2313| 18.4k| for (i = 1; i < parts; i++) ------------------ | Branch (2313:15): [True: 11.8k, False: 6.60k] ------------------ 2314| 11.8k| dst[i] = 0; 2315| 6.60k|} _ZN7llvm_ks5APInt8tcAssignEPmPKmj: 2320| 7.94k|{ 2321| 7.94k| unsigned int i; 2322| | 2323| 27.7k| for (i = 0; i < parts; i++) ------------------ | Branch (2323:15): [True: 19.7k, False: 7.94k] ------------------ 2324| 19.7k| dst[i] = src[i]; 2325| 7.94k|} _ZN7llvm_ks5APInt8tcIsZeroEPKmj: 2330| 4.94k|{ 2331| 4.94k| unsigned int i; 2332| | 2333| 10.7k| for (i = 0; i < parts; i++) ------------------ | Branch (2333:15): [True: 10.7k, False: 13] ------------------ 2334| 10.7k| if (src[i]) ------------------ | Branch (2334:9): [True: 4.92k, False: 5.80k] ------------------ 2335| 4.92k| return false; 2336| | 2337| 13| return true; 2338| 4.94k|} _ZN7llvm_ks5APInt12tcExtractBitEPKmj: 2343| 3.89k|{ 2344| 3.89k| return (parts[bit / integerPartWidth] & 2345| 3.89k| ((integerPart) 1 << bit % integerPartWidth)) != 0; 2346| 3.89k|} _ZN7llvm_ks5APInt8tcSetBitEPmj: 2351| 181k|{ 2352| 181k| parts[bit / integerPartWidth] |= (integerPart) 1 << (bit % integerPartWidth); 2353| 181k|} _ZN7llvm_ks5APInt5tcLSBEPKmj: 2367| 4.00k|{ 2368| 4.00k| unsigned int i, lsb; 2369| | 2370| 5.04k| for (i = 0; i < n; i++) { ------------------ | Branch (2370:15): [True: 5.04k, False: 0] ------------------ 2371| 5.04k| if (parts[i] != 0) { ------------------ | Branch (2371:11): [True: 4.00k, False: 1.04k] ------------------ 2372| 4.00k| lsb = partLSB(parts[i]); 2373| | 2374| 4.00k| return lsb + i * integerPartWidth; 2375| 4.00k| } 2376| 5.04k| } 2377| | 2378| 0| return -1U; 2379| 4.00k|} _ZN7llvm_ks5APInt5tcMSBEPKmj: 2385| 16.5k|{ 2386| 16.5k| unsigned int msb; 2387| | 2388| 19.7k| do { 2389| 19.7k| --n; 2390| | 2391| 19.7k| if (parts[n] != 0) { ------------------ | Branch (2391:9): [True: 16.3k, False: 3.37k] ------------------ 2392| 16.3k| msb = partMSB(parts[n]); 2393| | 2394| 16.3k| return msb + n * integerPartWidth; 2395| 16.3k| } 2396| 19.7k| } while (n); ------------------ | Branch (2396:12): [True: 3.19k, False: 175] ------------------ 2397| | 2398| 175| return -1U; 2399| 16.5k|} _ZN7llvm_ks5APInt9tcExtractEPmjPKmjj: 2408| 6.47k|{ 2409| 6.47k| unsigned int firstSrcPart, dstParts, shift, n; 2410| | 2411| 6.47k| dstParts = (srcBits + integerPartWidth - 1) / integerPartWidth; 2412| 6.47k| assert(dstParts <= dstCount); ------------------ | Branch (2412:3): [True: 6.47k, False: 0] ------------------ 2413| | 2414| 6.47k| firstSrcPart = srcLSB / integerPartWidth; 2415| 6.47k| tcAssign (dst, src + firstSrcPart, dstParts); 2416| | 2417| 6.47k| shift = srcLSB % integerPartWidth; 2418| 6.47k| tcShiftRight (dst, dstParts, shift); 2419| | 2420| | /* We now have (dstParts * integerPartWidth - shift) bits from SRC 2421| | in DST. If this is less that srcBits, append the rest, else 2422| | clear the high bits. */ 2423| 6.47k| n = dstParts * integerPartWidth - shift; 2424| 6.47k| if (n < srcBits) { ------------------ | Branch (2424:7): [True: 440, False: 6.03k] ------------------ 2425| 440| integerPart mask = lowBitMask (srcBits - n); 2426| 440| dst[dstParts - 1] |= ((src[firstSrcPart + dstParts] & mask) 2427| 440| << n % integerPartWidth); 2428| 6.03k| } else if (n > srcBits) { ------------------ | Branch (2428:14): [True: 6.01k, False: 19] ------------------ 2429| 6.01k| if (srcBits % integerPartWidth) ------------------ | Branch (2429:9): [True: 6.01k, False: 0] ------------------ 2430| 6.01k| dst[dstParts - 1] &= lowBitMask (srcBits % integerPartWidth); 2431| 6.01k| } 2432| | 2433| | /* Clear high parts. */ 2434| 9.66k| while (dstParts < dstCount) ------------------ | Branch (2434:10): [True: 3.19k, False: 6.47k] ------------------ 2435| 3.19k| dst[dstParts++] = 0; 2436| 6.47k|} _ZN7llvm_ks5APInt10tcSubtractEPmPKmmj: 2467| 181k|{ 2468| 181k| unsigned int i; 2469| | 2470| 181k| assert(c <= 1); ------------------ | Branch (2470:3): [True: 181k, False: 0] ------------------ 2471| | 2472| 13.1M| for (i = 0; i < parts; i++) { ------------------ | Branch (2472:15): [True: 12.9M, False: 181k] ------------------ 2473| 12.9M| integerPart l; 2474| | 2475| 12.9M| l = dst[i]; 2476| 12.9M| if (c) { ------------------ | Branch (2476:9): [True: 3.59M, False: 9.36M] ------------------ 2477| 3.59M| dst[i] -= rhs[i] + 1; 2478| 3.59M| c = (dst[i] >= l); 2479| 9.36M| } else { 2480| 9.36M| dst[i] -= rhs[i]; 2481| 9.36M| c = (dst[i] > l); 2482| 9.36M| } 2483| 12.9M| } 2484| | 2485| 181k| return c; 2486| 181k|} _ZN7llvm_ks5APInt14tcMultiplyPartEPmPKmmmjjb: 2512| 11.0k|{ 2513| 11.0k| unsigned int i, n; 2514| | 2515| | /* Otherwise our writes of DST kill our later reads of SRC. */ 2516| 11.0k| assert(dst <= src || dst >= src + srcParts); ------------------ | Branch (2516:3): [True: 6.75k, False: 4.32k] | Branch (2516:3): [True: 4.32k, False: 0] | Branch (2516:3): [True: 11.0k, False: 0] ------------------ 2517| 11.0k| assert(dstParts <= srcParts + 1); ------------------ | Branch (2517:3): [True: 11.0k, False: 0] ------------------ 2518| | 2519| | /* N loops; minimum of dstParts and srcParts. */ 2520| 11.0k| n = dstParts < srcParts ? dstParts: srcParts; ------------------ | Branch (2520:7): [True: 0, False: 11.0k] ------------------ 2521| | 2522| 276k| for (i = 0; i < n; i++) { ------------------ | Branch (2522:15): [True: 265k, False: 11.0k] ------------------ 2523| 265k| integerPart low, mid, high, srcPart; 2524| | 2525| | /* [ LOW, HIGH ] = MULTIPLIER * SRC[i] + DST[i] + CARRY. 2526| | 2527| | This cannot overflow, because 2528| | 2529| | (n - 1) * (n - 1) + 2 (n - 1) = (n - 1) * (n + 1) 2530| | 2531| | which is less than n^2. */ 2532| | 2533| 265k| srcPart = src[i]; 2534| | 2535| 265k| if (multiplier == 0 || srcPart == 0) { ------------------ | Branch (2535:9): [True: 0, False: 265k] | Branch (2535:28): [True: 42.6k, False: 222k] ------------------ 2536| 42.6k| low = carry; 2537| 42.6k| high = 0; 2538| 222k| } else { 2539| 222k| low = lowHalf(srcPart) * lowHalf(multiplier); 2540| 222k| high = highHalf(srcPart) * highHalf(multiplier); 2541| | 2542| 222k| mid = lowHalf(srcPart) * highHalf(multiplier); 2543| 222k| high += highHalf(mid); 2544| 222k| mid <<= integerPartWidth / 2; 2545| 222k| if (low + mid < low) ------------------ | Branch (2545:11): [True: 54.1k, False: 168k] ------------------ 2546| 54.1k| high++; 2547| 222k| low += mid; 2548| | 2549| 222k| mid = highHalf(srcPart) * lowHalf(multiplier); 2550| 222k| high += highHalf(mid); 2551| 222k| mid <<= integerPartWidth / 2; 2552| 222k| if (low + mid < low) ------------------ | Branch (2552:11): [True: 109k, False: 113k] ------------------ 2553| 109k| high++; 2554| 222k| low += mid; 2555| | 2556| | /* Now add carry. */ 2557| 222k| if (low + carry < low) ------------------ | Branch (2557:11): [True: 53.6k, False: 169k] ------------------ 2558| 53.6k| high++; 2559| 222k| low += carry; 2560| 222k| } 2561| | 2562| 265k| if (add) { ------------------ | Branch (2562:9): [True: 81.1k, False: 184k] ------------------ 2563| | /* And now DST[i], and store the new low part there. */ 2564| 81.1k| if (low + dst[i] < low) ------------------ | Branch (2564:11): [True: 34.8k, False: 46.2k] ------------------ 2565| 34.8k| high++; 2566| 81.1k| dst[i] += low; 2567| 81.1k| } else 2568| 184k| dst[i] = low; 2569| | 2570| 265k| carry = high; 2571| 265k| } 2572| | 2573| 11.0k| if (i < dstParts) { ------------------ | Branch (2573:7): [True: 11.0k, False: 0] ------------------ 2574| | /* Full multiplication, there is no overflow. */ 2575| 11.0k| assert(i + 1 == dstParts); ------------------ | Branch (2575:5): [True: 11.0k, False: 0] ------------------ 2576| 11.0k| dst[i] = carry; 2577| 11.0k| return 0; 2578| 11.0k| } else { 2579| | /* We overflowed if there is carry. */ 2580| 0| if (carry) ------------------ | Branch (2580:9): [True: 0, False: 0] ------------------ 2581| 0| return 1; 2582| | 2583| | /* We would overflow if any significant unwritten parts would be 2584| | non-zero. This is true if any remaining src parts are non-zero 2585| | and the multiplier is non-zero. */ 2586| 0| if (multiplier) ------------------ | Branch (2586:9): [True: 0, False: 0] ------------------ 2587| 0| for (; i < srcParts; i++) ------------------ | Branch (2587:14): [True: 0, False: 0] ------------------ 2588| 0| if (src[i]) ------------------ | Branch (2588:13): [True: 0, False: 0] ------------------ 2589| 0| return 1; 2590| | 2591| | /* We fitted in the narrow destination. */ 2592| 0| return 0; 2593| 0| } 2594| 11.0k|} _ZN7llvm_ks5APInt14tcFullMultiplyEPmPKmS3_jj: 2627| 2.59k|{ 2628| | /* Put the narrower number on the LHS for less loops below. */ 2629| 2.59k| if (lhsParts > rhsParts) { ------------------ | Branch (2629:7): [True: 0, False: 2.59k] ------------------ 2630| 0| return tcFullMultiply (dst, rhs, lhs, rhsParts, lhsParts); 2631| 2.59k| } else { 2632| 2.59k| unsigned int n; 2633| | 2634| 2.59k| assert(dst != lhs && dst != rhs); ------------------ | Branch (2634:5): [True: 2.59k, False: 0] | Branch (2634:5): [True: 2.59k, False: 0] | Branch (2634:5): [True: 2.59k, False: 0] ------------------ 2635| | 2636| 2.59k| tcSet(dst, 0, rhsParts); 2637| | 2638| 8.62k| for (n = 0; n < lhsParts; n++) ------------------ | Branch (2638:17): [True: 6.03k, False: 2.59k] ------------------ 2639| 6.03k| tcMultiplyPart(&dst[n], rhs, lhs[n], 0, rhsParts, rhsParts + 1, true); 2640| | 2641| 2.59k| n = lhsParts + rhsParts; 2642| | 2643| 2.59k| return n - (dst[n - 1] == 0); 2644| 2.59k| } 2645| 2.59k|} _ZN7llvm_ks5APInt11tcShiftLeftEPmjj: 2706| 477k|{ 2707| 477k| if (count) { ------------------ | Branch (2707:7): [True: 477k, False: 0] ------------------ 2708| 477k| unsigned int jump, shift; 2709| | 2710| | /* Jump is the inter-part jump; shift is is intra-part shift. */ 2711| 477k| jump = count / integerPartWidth; 2712| 477k| shift = count % integerPartWidth; 2713| | 2714| 42.9M| while (parts > jump) { ------------------ | Branch (2714:12): [True: 42.5M, False: 477k] ------------------ 2715| 42.5M| integerPart part; 2716| | 2717| 42.5M| parts--; 2718| | 2719| | /* dst[i] comes from the two parts src[i - jump] and, if we have 2720| | an intra-part shift, src[i - jump - 1]. */ 2721| 42.5M| part = dst[parts - jump]; 2722| 42.5M| if (shift) { ------------------ | Branch (2722:11): [True: 42.5M, False: 647] ------------------ 2723| 42.5M| part <<= shift; 2724| 42.5M| if (parts >= jump + 1) ------------------ | Branch (2724:13): [True: 42.0M, False: 477k] ------------------ 2725| 42.0M| part |= dst[parts - jump - 1] >> (integerPartWidth - shift); 2726| 42.5M| } 2727| | 2728| 42.5M| dst[parts] = part; 2729| 42.5M| } 2730| | 2731| 480k| while (parts > 0) ------------------ | Branch (2731:12): [True: 3.19k, False: 477k] ------------------ 2732| 3.19k| dst[--parts] = 0; 2733| 477k| } 2734| 477k|} _ZN7llvm_ks5APInt12tcShiftRightEPmjj: 2740| 8.10k|{ 2741| 8.10k| if (count) { ------------------ | Branch (2741:7): [True: 3.96k, False: 4.14k] ------------------ 2742| 3.96k| unsigned int i, jump, shift; 2743| | 2744| | /* Jump is the inter-part jump; shift is is intra-part shift. */ 2745| 3.96k| jump = count / integerPartWidth; 2746| 3.96k| shift = count % integerPartWidth; 2747| | 2748| | /* Perform the shift. This leaves the most significant COUNT bits 2749| | of the result at zero. */ 2750| 13.5k| for (i = 0; i < parts; i++) { ------------------ | Branch (2750:17): [True: 9.57k, False: 3.96k] ------------------ 2751| 9.57k| integerPart part; 2752| | 2753| 9.57k| if (i + jump >= parts) { ------------------ | Branch (2753:11): [True: 8, False: 9.56k] ------------------ 2754| 8| part = 0; 2755| 9.56k| } else { 2756| 9.56k| part = dst[i + jump]; 2757| 9.56k| if (shift) { ------------------ | Branch (2757:13): [True: 9.56k, False: 0] ------------------ 2758| 9.56k| part >>= shift; 2759| 9.56k| if (i + jump + 1 < parts) ------------------ | Branch (2759:15): [True: 5.60k, False: 3.95k] ------------------ 2760| 5.60k| part |= dst[i + jump + 1] << (integerPartWidth - shift); 2761| 9.56k| } 2762| 9.56k| } 2763| | 2764| 9.57k| dst[i] = part; 2765| 9.57k| } 2766| 3.96k| } 2767| 8.10k|} _ZN7llvm_ks5APInt9tcCompareEPKmS2_j: 2813| 475k|{ 2814| 480k| while (parts) { ------------------ | Branch (2814:10): [True: 480k, False: 15] ------------------ 2815| 480k| parts--; 2816| 480k| if (lhs[parts] == rhs[parts]) ------------------ | Branch (2816:11): [True: 4.73k, False: 475k] ------------------ 2817| 4.73k| continue; 2818| | 2819| 475k| if (lhs[parts] > rhs[parts]) ------------------ | Branch (2819:11): [True: 183k, False: 292k] ------------------ 2820| 183k| return 1; 2821| 292k| else 2822| 292k| return -1; 2823| 475k| } 2824| | 2825| 15| return 0; 2826| 475k|} _ZN7llvm_ks5APInt11tcIncrementEPmj: 2831| 918|{ 2832| 918| unsigned int i; 2833| | 2834| 966| for (i = 0; i < parts; i++) ------------------ | Branch (2834:15): [True: 966, False: 0] ------------------ 2835| 966| if (++dst[i] != 0) ------------------ | Branch (2835:9): [True: 918, False: 48] ------------------ 2836| 918| break; 2837| | 2838| 918| return i == parts; 2839| 918|} APInt.cpp:_ZL16getClearedMemoryj: 34| 12.0k|inline static uint64_t* getClearedMemory(unsigned numWords) { 35| 12.0k| uint64_t * result = new uint64_t[numWords]; 36| 12.0k| assert(result && "APInt memory allocation fails!"); ------------------ | Branch (36:3): [True: 12.0k, False: 0] | Branch (36:3): [True: 12.0k, Folded] | Branch (36:3): [True: 12.0k, False: 0] ------------------ 37| 12.0k| memset(result, 0, numWords * sizeof(uint64_t)); 38| 12.0k| return result; 39| 12.0k|} APInt.cpp:_ZL9getMemoryj: 43| 22.3k|inline static uint64_t* getMemory(unsigned numWords) { 44| 22.3k| uint64_t * result = new uint64_t[numWords]; 45| 22.3k| assert(result && "APInt memory allocation fails!"); ------------------ | Branch (45:3): [True: 22.3k, False: 0] | Branch (45:3): [True: 22.3k, Folded] | Branch (45:3): [True: 22.3k, False: 0] ------------------ 46| 22.3k| return result; 47| 22.3k|} APInt.cpp:_ZN12_GLOBAL__N_17partLSBEm: 2298| 4.00k| { 2299| 4.00k| return findFirstSet(value, ZB_Max); 2300| 4.00k| } APInt.cpp:_ZN12_GLOBAL__N_17partMSBEm: 2290| 16.3k| { 2291| 16.3k| return findLastSet(value, ZB_Max); 2292| 16.3k| } APInt.cpp:_ZN12_GLOBAL__N_110lowBitMaskEj: 2266| 896k| { 2267| 896k| assert(bits != 0 && bits <= integerPartWidth); ------------------ | Branch (2267:5): [True: 896k, False: 0] | Branch (2267:5): [True: 896k, False: 0] | Branch (2267:5): [True: 896k, False: 0] ------------------ 2268| | 2269| 896k| return ~(integerPart) 0 >> (integerPartWidth - bits); 2270| 896k| } APInt.cpp:_ZN12_GLOBAL__N_17lowHalfEm: 2275| 890k| { 2276| 890k| return part & lowBitMask(integerPartWidth / 2); 2277| 890k| } APInt.cpp:_ZN12_GLOBAL__N_18highHalfEm: 2282| 1.33M| { 2283| 1.33M| return part >> (integerPartWidth / 2); 2284| 1.33M| } _ZN7llvm_ks13ARMBuildAttrs18AttrTypeFromStringENS_9StringRefE: 86| 5|int AttrTypeFromString(StringRef Tag) { 87| 5| bool HasTagPrefix = Tag.startswith("Tag_"); 88| 5| for (unsigned TI = 0, TE = sizeof(ARMAttributeTags) / sizeof(*ARMAttributeTags); 89| 240| TI != TE; ++TI) ------------------ | Branch (89:8): [True: 235, False: 5] ------------------ 90| 235| if (StringRef(ARMAttributeTags[TI].TagName + (HasTagPrefix ? 0 : 4)) == Tag) ------------------ | Branch (90:9): [True: 0, False: 235] | Branch (90:51): [True: 0, False: 235] ------------------ 91| 0| return ARMAttributeTags[TI].Attr; 92| 5| return -1; 93| 5|} _ZN7llvm_ks12MemoryBufferD2Ev: 39| 1.36k|MemoryBuffer::~MemoryBuffer() { } _ZN7llvm_ks12MemoryBuffer4initEPKcS2_b: 44| 1.36k| bool RequiresNullTerminator) { 45| 1.36k| assert((!RequiresNullTerminator || BufEnd[0] == 0) && ------------------ | Branch (45:3): [True: 0, False: 1.36k] | Branch (45:3): [True: 1.36k, False: 0] | Branch (45:3): [True: 1.36k, Folded] | Branch (45:3): [True: 1.36k, False: 0] ------------------ 46| 1.36k| "Buffer is not null terminated!"); 47| 1.36k| BufferStart = BufStart; 48| 1.36k| BufferEnd = BufEnd; 49| 1.36k|} _ZN7llvm_ks12MemoryBuffer12getMemBufferENS_9StringRefES1_b: 104| 430| bool RequiresNullTerminator) { 105| 430| auto *Ret = new (NamedBufferAlloc(BufferName)) 106| 430| MemoryBufferMem(InputData, RequiresNullTerminator); 107| 430| return std::unique_ptr(Ret); 108| 430|} _ZN7llvm_ks12MemoryBuffer16getMemBufferCopyENS_9StringRefERKNS_5TwineE: 117| 932|MemoryBuffer::getMemBufferCopy(StringRef InputData, const Twine &BufferName) { 118| 932| std::unique_ptr Buf = 119| 932| getNewUninitMemBuffer(InputData.size(), BufferName); 120| 932| if (!Buf) ------------------ | Branch (120:7): [True: 0, False: 932] ------------------ 121| 0| return nullptr; 122| 932| memcpy(const_cast(Buf->getBufferStart()), InputData.data(), 123| 932| InputData.size()); 124| 932| return Buf; 125| 932|} _ZN7llvm_ks12MemoryBuffer21getNewUninitMemBufferEmRKNS_5TwineE: 128| 932|MemoryBuffer::getNewUninitMemBuffer(size_t Size, const Twine &BufferName) { 129| | // Allocate space for the MemoryBuffer, the data and the name. It is important 130| | // that MemoryBuffer and data are aligned so PointerIntPair works with them. 131| | // TODO: Is 16-byte alignment enough? We copy small object files with large 132| | // alignment expectations into this buffer. 133| 932| SmallString<256> NameBuf; 134| 932| StringRef NameRef = BufferName.toStringRef(NameBuf); 135| 932| size_t AlignedStringLen = 136| 932| alignTo(sizeof(MemoryBufferMem) + NameRef.size() + 1, 16); 137| 932| size_t RealLen = AlignedStringLen + Size + 1; 138| 932| char *Mem = static_cast(operator new(RealLen, std::nothrow)); 139| 932| if (!Mem) ------------------ | Branch (139:7): [True: 0, False: 932] ------------------ 140| 0| return nullptr; 141| | 142| | // The name is stored after the class itself. 143| 932| CopyStringRef(Mem + sizeof(MemoryBufferMem), NameRef); 144| | 145| | // The buffer begins after the name and must be aligned. 146| 932| char *Buf = Mem + AlignedStringLen; 147| 932| Buf[Size] = 0; // Null terminate buffer. 148| | 149| 932| auto *Ret = new (Mem) MemoryBufferMem(StringRef(Buf, Size), true); 150| 932| return std::unique_ptr(Ret); 151| 932|} MemoryBuffer.cpp:_ZN12_GLOBAL__N_116NamedBufferAllocC2ERKN7llvm_ks5TwineE: 66| 430| NamedBufferAlloc(const Twine &Name) : Name(Name) {} MemoryBuffer.cpp:_ZnwmRKN12_GLOBAL__N_116NamedBufferAllocE: 70| 430|void *operator new(size_t N, const NamedBufferAlloc &Alloc) { 71| 430| SmallString<256> NameBuf; 72| 430| StringRef NameRef = Alloc.Name.toStringRef(NameBuf); 73| | 74| 430| char *Mem = static_cast(operator new(N + NameRef.size() + 1)); 75| 430| CopyStringRef(Mem + N, NameRef); 76| 430| return Mem; 77| 430|} MemoryBuffer.cpp:_ZN12_GLOBAL__N_115MemoryBufferMemC2EN7llvm_ks9StringRefEb: 83| 1.36k| MemoryBufferMem(StringRef InputData, bool RequiresNullTerminator) { 84| 1.36k| init(InputData.begin(), InputData.end(), RequiresNullTerminator); 85| 1.36k| } MemoryBuffer.cpp:_ZNK12_GLOBAL__N_115MemoryBufferMem19getBufferIdentifierEv: 87| 2.17k| const char *getBufferIdentifier() const override { 88| | // The name is stored after the class itself. 89| 2.17k| return reinterpret_cast(this + 1); 90| 2.17k| } MemoryBuffer.cpp:_ZL13CopyStringRefPcN7llvm_ks9StringRefE: 57| 1.36k|static void CopyStringRef(char *Memory, StringRef Data) { 58| 1.36k| if (!Data.empty()) ------------------ | Branch (58:7): [True: 932, False: 430] ------------------ 59| 932| memcpy(Memory, Data.data(), Data.size()); 60| 1.36k| Memory[Data.size()] = 0; // Null terminate string. 61| 1.36k|} _ZN7llvm_ks3sys4path5beginENS_9StringRefE: 232| 430|const_iterator begin(StringRef path) { 233| 430| const_iterator i; 234| 430| i.Path = path; 235| 430| i.Component = find_first_component(path); 236| 430| i.Position = 0; 237| 430| return i; 238| 430|} _ZN7llvm_ks3sys4path3endENS_9StringRefE: 240| 430|const_iterator end(StringRef path) { 241| 430| const_iterator i; 242| 430| i.Path = path; 243| 430| i.Position = path.size(); 244| 430| return i; 245| 430|} _ZNK7llvm_ks3sys4path14const_iteratoreqERKS2_: 300| 430|bool const_iterator::operator==(const const_iterator &RHS) const { 301| 430| return Path.begin() == RHS.Path.begin() && Position == RHS.Position; ------------------ | Branch (301:10): [True: 430, False: 0] | Branch (301:46): [True: 0, False: 430] ------------------ 302| 430|} _ZN7llvm_ks3sys4path14root_directoryENS_9StringRefE: 409| 430|StringRef root_directory(StringRef path) { 410| 430| const_iterator b = begin(path), 411| 430| pos = b, 412| 430| e = end(path); 413| 430| if (b != e) { ------------------ | Branch (413:7): [True: 430, False: 0] ------------------ 414| 430| bool has_net = b->size() > 2 && is_separator((*b)[0]) && (*b)[1] == (*b)[0]; ------------------ | Branch (414:20): [True: 0, False: 430] | Branch (414:37): [True: 0, False: 0] | Branch (414:62): [True: 0, False: 0] ------------------ 415| 430| bool has_drive = 416| |#ifdef LLVM_ON_WIN32 417| | b->endswith(":"); 418| |#else 419| 430| false; 420| 430|#endif 421| | 422| 430| if ((has_net || has_drive) && ------------------ | Branch (422:10): [True: 0, False: 430] | Branch (422:21): [True: 0, False: 430] ------------------ 423| | // {C:,//net}, skip to the next component. 424| 0| (++pos != e) && is_separator((*pos)[0])) { ------------------ | Branch (424:9): [True: 0, False: 0] | Branch (424:25): [True: 0, False: 0] ------------------ 425| 0| return *pos; 426| 0| } 427| | 428| | // POSIX style root directory. 429| 430| if (!has_net && is_separator((*b)[0])) { ------------------ | Branch (429:9): [True: 430, False: 0] | Branch (429:21): [True: 430, False: 0] ------------------ 430| 430| return *b; 431| 430| } 432| 430| } 433| | 434| | // No path or no root. 435| 0| return StringRef(); 436| 430|} _ZN7llvm_ks3sys4path12is_separatorEc: 576| 1.29k|bool is_separator(char value) { 577| 1.29k| switch(value) { 578| |#ifdef LLVM_ON_WIN32 579| | case '\\': // fall through 580| |#endif 581| 1.29k| case '/': return true; ------------------ | Branch (581:5): [True: 1.29k, False: 0] ------------------ 582| 0| default: return false; ------------------ | Branch (582:5): [True: 0, False: 1.29k] ------------------ 583| 1.29k| } 584| 1.29k|} _ZN7llvm_ks3sys4path18has_root_directoryERKNS_5TwineE: 599| 430|bool has_root_directory(const Twine &path) { 600| 430| SmallString<128> path_storage; 601| 430| StringRef p = path.toStringRef(path_storage); 602| | 603| 430| return !root_directory(p).empty(); 604| 430|} _ZN7llvm_ks3sys4path11is_absoluteERKNS_5TwineE: 648| 430|bool is_absolute(const Twine &path) { 649| 430| SmallString<128> path_storage; 650| 430| StringRef p = path.toStringRef(path_storage); 651| | 652| 430| bool rootDir = has_root_directory(p), 653| |#ifdef LLVM_ON_WIN32 654| | rootName = has_root_name(p); 655| |#else 656| 430| rootName = true; 657| 430|#endif 658| | 659| 430| return rootDir && rootName; ------------------ | Branch (659:10): [True: 430, False: 0] | Branch (659:21): [True: 430, False: 0] ------------------ 660| 430|} Path.cpp:_ZN12_GLOBAL__N_120find_first_componentEN7llvm_ks9StringRefE: 45| 430| StringRef find_first_component(StringRef path) { 46| | // Look for this first component in the following order. 47| | // * empty (in this case we return an empty string) 48| | // * either C: or {//,\\}net. 49| | // * {/,\} 50| | // * {file,directory}name 51| | 52| 430| if (path.empty()) ------------------ | Branch (52:9): [True: 0, False: 430] ------------------ 53| 0| return path; 54| | 55| |#ifdef LLVM_ON_WIN32 56| | // C: 57| | if (path.size() >= 2 && std::isalpha(static_cast(path[0])) && 58| | path[1] == ':') 59| | return path.substr(0, 2); 60| |#endif 61| | 62| | // //net 63| 430| if ((path.size() > 2) && ------------------ | Branch (63:9): [True: 430, False: 0] ------------------ 64| 430| is_separator(path[0]) && ------------------ | Branch (64:9): [True: 430, False: 0] ------------------ 65| 430| path[0] == path[1] && ------------------ | Branch (65:9): [True: 0, False: 430] ------------------ 66| 0| !is_separator(path[2])) { ------------------ | Branch (66:9): [True: 0, False: 0] ------------------ 67| | // Find the next directory separator. 68| 0| size_t end = path.find_first_of(separators, 2); 69| 0| return path.substr(0, end); 70| 0| } 71| | 72| | // {/,\} 73| 430| if (is_separator(path[0])) ------------------ | Branch (73:9): [True: 430, False: 0] ------------------ 74| 430| return path.substr(0, 1); 75| | 76| | // * {file,directory}name 77| 0| size_t end = path.find_first_of(separators); 78| 0| return path.substr(0, end); 79| 430| } _ZN7llvm_ks15SmallVectorBase8grow_podEPvmm: 20| 608| size_t TSize) { 21| 608| size_t CurSizeBytes = size_in_bytes(); 22| 608| size_t NewCapacityInBytes = 2 * capacity_in_bytes() + TSize; // Always grow. 23| 608| if (NewCapacityInBytes < MinSizeInBytes) ------------------ | Branch (23:7): [True: 118, False: 490] ------------------ 24| 118| NewCapacityInBytes = MinSizeInBytes; 25| | 26| 608| void *NewElts; 27| 608| if (BeginX == FirstEl) { ------------------ | Branch (27:7): [True: 276, False: 332] ------------------ 28| 276| NewElts = malloc(NewCapacityInBytes); 29| | 30| | // Copy the elements over. No need to run dtors on PODs. 31| 276| memcpy(NewElts, this->BeginX, CurSizeBytes); 32| 332| } else { 33| | // If this wasn't grown from the inline copy, grow the allocated space. 34| 332| NewElts = realloc(this->BeginX, NewCapacityInBytes); 35| 332| } 36| 608| assert(NewElts && "Out of memory"); ------------------ | Branch (36:3): [True: 608, False: 0] | Branch (36:3): [True: 608, Folded] | Branch (36:3): [True: 608, False: 0] ------------------ 37| | 38| 608| this->EndX = (char*)NewElts+CurSizeBytes; 39| 608| this->BeginX = NewElts; 40| 608| this->CapacityX = (char*)this->BeginX + NewCapacityInBytes; 41| 608|} _ZN7llvm_ks9SourceMgrD2Ev: 38| 430|SourceMgr::~SourceMgr() { 39| | // Delete the line # cache if allocated. 40| 430| if (LineNoCacheTy *Cache = getCache(LineNoCache)) ------------------ | Branch (40:22): [True: 30, False: 400] ------------------ 41| 30| delete Cache; 42| 430|} _ZNK7llvm_ks9SourceMgr23FindBufferContainingLocENS_5SMLocE: 65| 8.69k|unsigned SourceMgr::FindBufferContainingLoc(SMLoc Loc) const { 66| 10.9k| for (unsigned i = 0, e = Buffers.size(); i != e; ++i) ------------------ | Branch (66:44): [True: 9.09k, False: 1.87k] ------------------ 67| 9.09k| if (Loc.getPointer() >= Buffers[i].Buffer->getBufferStart() && ------------------ | Branch (67:9): [True: 6.82k, False: 2.26k] ------------------ 68| | // Use <= here so that a pointer to the null at the end of the buffer 69| | // is included as part of the buffer. 70| 6.82k| Loc.getPointer() <= Buffers[i].Buffer->getBufferEnd()) ------------------ | Branch (70:9): [True: 6.82k, False: 0] ------------------ 71| 6.82k| return i + 1; 72| 1.87k| return 0; 73| 8.69k|} _ZNK7llvm_ks9SourceMgr16getLineAndColumnENS_5SMLocEj: 76| 2.78k|SourceMgr::getLineAndColumn(SMLoc Loc, unsigned BufferID) const { 77| 2.78k| if (!BufferID) ------------------ | Branch (77:7): [True: 0, False: 2.78k] ------------------ 78| 0| BufferID = FindBufferContainingLoc(Loc); 79| 2.78k| assert(BufferID && "Invalid Location!"); ------------------ | Branch (79:3): [True: 2.78k, False: 0] | Branch (79:3): [True: 2.78k, Folded] | Branch (79:3): [True: 2.78k, False: 0] ------------------ 80| | 81| 2.78k| const MemoryBuffer *Buff = getMemoryBuffer(BufferID); 82| | 83| | // Count the number of \n's between the start of the file and the specified 84| | // location. 85| 2.78k| unsigned LineNo = 1; 86| | 87| 2.78k| const char *BufStart = Buff->getBufferStart(); 88| 2.78k| const char *Ptr = BufStart; 89| | 90| | // If we have a line number cache, and if the query is to a later point in the 91| | // same file, start searching from the last query location. This optimizes 92| | // for the case when multiple diagnostics come out of one file in order. 93| 2.78k| if (LineNoCacheTy *Cache = getCache(LineNoCache)) ------------------ | Branch (93:22): [True: 2.75k, False: 30] ------------------ 94| 2.75k| if (Cache->LastQueryBufferID == BufferID && ------------------ | Branch (94:9): [True: 2.75k, False: 0] ------------------ 95| 2.75k| Cache->LastQuery <= Loc.getPointer()) { ------------------ | Branch (95:9): [True: 2.37k, False: 378] ------------------ 96| 2.37k| Ptr = Cache->LastQuery; 97| 2.37k| LineNo = Cache->LineNoOfQuery; 98| 2.37k| } 99| | 100| | // Scan for the location being queried, keeping track of the number of lines 101| | // we see. 102| 335k| for (; SMLoc::getFromPointer(Ptr) != Loc; ++Ptr) ------------------ | Branch (102:10): [True: 332k, False: 2.78k] ------------------ 103| 332k| if (*Ptr == '\n') ++LineNo; ------------------ | Branch (103:9): [True: 15.2k, False: 317k] ------------------ 104| | 105| | // Allocate the line number cache if it doesn't exist. 106| 2.78k| if (!LineNoCache) ------------------ | Branch (106:7): [True: 30, False: 2.75k] ------------------ 107| 30| LineNoCache = new LineNoCacheTy(); 108| | 109| | // Update the line # cache. 110| 2.78k| LineNoCacheTy &Cache = *getCache(LineNoCache); 111| 2.78k| Cache.LastQueryBufferID = BufferID; 112| 2.78k| Cache.LastQuery = Ptr; 113| 2.78k| Cache.LineNoOfQuery = LineNo; 114| | 115| 2.78k| size_t NewlineOffs = StringRef(BufStart, Ptr-BufStart).find_last_of("\n\r"); 116| 2.78k| if (NewlineOffs == StringRef::npos) NewlineOffs = ~(size_t)0; ------------------ | Branch (116:7): [True: 316, False: 2.46k] ------------------ 117| 2.78k| return std::make_pair(LineNo, Ptr-BufStart-NewlineOffs); 118| 2.78k|} _ZNK7llvm_ks9SourceMgr17PrintIncludeStackENS_5SMLocERNS_11raw_ostreamE: 120| 99|void SourceMgr::PrintIncludeStack(SMLoc IncludeLoc, raw_ostream &OS) const { 121| 99| if (IncludeLoc == SMLoc()) return; // Top of stack. ------------------ | Branch (121:7): [True: 99, False: 0] ------------------ 122| | 123| 0| unsigned CurBuf = FindBufferContainingLoc(IncludeLoc); 124| 0| assert(CurBuf && "Invalid or unspecified location!"); ------------------ | Branch (124:3): [True: 0, False: 0] | Branch (124:3): [True: 0, Folded] | Branch (124:3): [True: 0, False: 0] ------------------ 125| | 126| 0| PrintIncludeStack(getBufferInfo(CurBuf).IncludeLoc, OS); 127| | 128| 0| OS << "Included from " 129| 0| << getBufferInfo(CurBuf).Buffer->getBufferIdentifier() 130| 0| << ":" << FindLineNumber(IncludeLoc, CurBuf) << ":\n"; 131| 0|} _ZNK7llvm_ks9SourceMgr10GetMessageENS_5SMLocENS0_8DiagKindERKNS_5TwineENS_8ArrayRefINS_7SMRangeEEENS6_INS_7SMFixItEEE: 137| 2.17k| ArrayRef FixIts) const { 138| | 139| | // First thing to do: find the current buffer containing the specified 140| | // location to pull out the source line. 141| 2.17k| SmallVector, 4> ColRanges; 142| 2.17k| std::pair LineAndCol; 143| 2.17k| const char *BufferID = ""; 144| 2.17k| std::string LineStr; 145| | 146| 2.17k| if (Loc.isValid()) { ------------------ | Branch (146:7): [True: 2.17k, False: 0] ------------------ 147| 2.17k| unsigned CurBuf = FindBufferContainingLoc(Loc); 148| 2.17k| assert(CurBuf && "Invalid or unspecified location!"); ------------------ | Branch (148:5): [True: 2.17k, False: 0] | Branch (148:5): [True: 2.17k, Folded] | Branch (148:5): [True: 2.17k, False: 0] ------------------ 149| | 150| 2.17k| const MemoryBuffer *CurMB = getMemoryBuffer(CurBuf); 151| 2.17k| BufferID = CurMB->getBufferIdentifier(); 152| | 153| | // Scan backward to find the start of the line. 154| 2.17k| const char *LineStart = Loc.getPointer(); 155| 2.17k| const char *BufStart = CurMB->getBufferStart(); 156| 5.72k| while (LineStart != BufStart && LineStart[-1] != '\n' && ------------------ | Branch (156:12): [True: 5.71k, False: 12] | Branch (156:37): [True: 4.76k, False: 954] ------------------ 157| 4.76k| LineStart[-1] != '\r') ------------------ | Branch (157:12): [True: 3.55k, False: 1.20k] ------------------ 158| 3.55k| --LineStart; 159| | 160| | // Get the end of the line. 161| 2.17k| const char *LineEnd = Loc.getPointer(); 162| 2.17k| const char *BufEnd = CurMB->getBufferEnd(); 163| 58.2k| while (LineEnd != BufEnd && LineEnd[0] != '\n' && LineEnd[0] != '\r') ------------------ | Branch (163:12): [True: 58.2k, False: 12] | Branch (163:33): [True: 57.3k, False: 955] | Branch (163:55): [True: 56.1k, False: 1.20k] ------------------ 164| 56.1k| ++LineEnd; 165| 2.17k| LineStr = std::string(LineStart, LineEnd); 166| | 167| | // Convert any ranges to column ranges that only intersect the line of the 168| | // location. 169| 2.17k| for (unsigned i = 0, e = Ranges.size(); i != e; ++i) { ------------------ | Branch (169:45): [True: 0, False: 2.17k] ------------------ 170| 0| SMRange R = Ranges[i]; 171| 0| if (!R.isValid()) continue; ------------------ | Branch (171:11): [True: 0, False: 0] ------------------ 172| | 173| | // If the line doesn't contain any part of the range, then ignore it. 174| 0| if (R.Start.getPointer() > LineEnd || R.End.getPointer() < LineStart) ------------------ | Branch (174:11): [True: 0, False: 0] | Branch (174:45): [True: 0, False: 0] ------------------ 175| 0| continue; 176| | 177| | // Ignore pieces of the range that go onto other lines. 178| 0| if (R.Start.getPointer() < LineStart) ------------------ | Branch (178:11): [True: 0, False: 0] ------------------ 179| 0| R.Start = SMLoc::getFromPointer(LineStart); 180| 0| if (R.End.getPointer() > LineEnd) ------------------ | Branch (180:11): [True: 0, False: 0] ------------------ 181| 0| R.End = SMLoc::getFromPointer(LineEnd); 182| | 183| | // Translate from SMLoc ranges to column ranges. 184| | // FIXME: Handle multibyte characters. 185| 0| ColRanges.push_back(std::make_pair(R.Start.getPointer()-LineStart, 186| 0| R.End.getPointer()-LineStart)); 187| 0| } 188| | 189| 2.17k| LineAndCol = getLineAndColumn(Loc, CurBuf); 190| 2.17k| } 191| | 192| 2.17k| return SMDiagnostic(*this, Loc, BufferID, LineAndCol.first, 193| 2.17k| LineAndCol.second-1, Kind, Msg.str(), 194| 2.17k| LineStr, ColRanges, FixIts); 195| 2.17k|} _ZNK7llvm_ks9SourceMgr12PrintMessageERNS_11raw_ostreamERKNS_12SMDiagnosticEb: 198| 2.17k| bool ShowColors) const { 199| | // Report the message with the diagnostic handler if present. 200| 2.17k| if (DiagHandler) { ------------------ | Branch (200:7): [True: 2.17k, False: 0] ------------------ 201| 2.17k| DiagHandler(Diagnostic, DiagContext); 202| 2.17k| return; 203| 2.17k| } 204| | 205| 0| if (Diagnostic.getLoc().isValid()) { ------------------ | Branch (205:7): [True: 0, False: 0] ------------------ 206| 0| unsigned CurBuf = FindBufferContainingLoc(Diagnostic.getLoc()); 207| 0| assert(CurBuf && "Invalid or unspecified location!"); ------------------ | Branch (207:5): [True: 0, False: 0] | Branch (207:5): [True: 0, Folded] | Branch (207:5): [True: 0, False: 0] ------------------ 208| 0| PrintIncludeStack(getBufferInfo(CurBuf).IncludeLoc, OS); 209| 0| } 210| | 211| 0| Diagnostic.print(nullptr, OS, ShowColors); 212| 0|} _ZNK7llvm_ks9SourceMgr12PrintMessageERNS_11raw_ostreamENS_5SMLocENS0_8DiagKindERKNS_5TwineENS_8ArrayRefINS_7SMRangeEEENS8_INS_7SMFixItEEEb: 217| 2.17k| ArrayRef FixIts, bool ShowColors) const { 218| 2.17k| PrintMessage(OS, GetMessage(Loc, Kind, Msg, Ranges, FixIts), ShowColors); 219| 2.17k|} _ZNK7llvm_ks9SourceMgr12PrintMessageENS_5SMLocENS0_8DiagKindERKNS_5TwineENS_8ArrayRefINS_7SMRangeEEENS6_INS_7SMFixItEEEb: 223| 2.17k| ArrayRef FixIts, bool ShowColors) const { 224| 2.17k| PrintMessage(llvm_ks::errs(), Loc, Kind, Msg, Ranges, FixIts, ShowColors); 225| 2.17k|} _ZN7llvm_ks12SMDiagnosticC2ERKNS_9SourceMgrENS_5SMLocENS_9StringRefEiiNS1_8DiagKindES5_S5_NS_8ArrayRefINSt3__14pairIjjEEEENS7_INS_7SMFixItEEE: 236| 2.47k| : SM(&sm), Loc(L), Filename(FN), LineNo(Line), ColumnNo(Col), Kind(Kind), 237| 2.47k| Message(Msg), LineContents(LineStr), Ranges(Ranges.vec()), 238| 2.47k| FixIts(Hints.begin(), Hints.end()) { 239| 2.47k| std::sort(FixIts.begin(), FixIts.end()); 240| 2.47k|} _ZNK7llvm_ks12SMDiagnostic5printEPKcRNS_11raw_ostreamEbb: 329| 2.17k| bool ShowKindLabel) const { 330| | // Display colors only if OS supports colors. 331| 2.17k| ShowColors &= S.has_colors(); 332| | 333| 2.17k| if (ShowColors) ------------------ | Branch (333:7): [True: 2.17k, False: 0] ------------------ 334| 2.17k| S.changeColor(raw_ostream::SAVEDCOLOR, true); 335| | 336| 2.17k| if (ProgName && ProgName[0]) ------------------ | Branch (336:7): [True: 0, False: 2.17k] | Branch (336:19): [True: 0, False: 0] ------------------ 337| 0| S << ProgName << ": "; 338| | 339| 2.17k| if (!Filename.empty()) { ------------------ | Branch (339:7): [True: 99, False: 2.07k] ------------------ 340| 99| if (Filename == "-") ------------------ | Branch (340:9): [True: 0, False: 99] ------------------ 341| 0| S << ""; 342| 99| else 343| 99| S << Filename; 344| | 345| 99| if (LineNo != -1) { ------------------ | Branch (345:9): [True: 99, False: 0] ------------------ 346| 99| S << ':' << LineNo; 347| 99| if (ColumnNo != -1) ------------------ | Branch (347:11): [True: 99, False: 0] ------------------ 348| 99| S << ':' << (ColumnNo+1); 349| 99| } 350| 99| S << ": "; 351| 99| } 352| | 353| 2.17k| if (ShowKindLabel) { ------------------ | Branch (353:7): [True: 2.17k, False: 0] ------------------ 354| 2.17k| switch (Kind) { ------------------ | Branch (354:13): [True: 2.17k, False: 0] ------------------ 355| 116| case SourceMgr::DK_Error: ------------------ | Branch (355:5): [True: 116, False: 2.05k] ------------------ 356| 116| if (ShowColors) ------------------ | Branch (356:11): [True: 116, False: 0] ------------------ 357| 116| S.changeColor(raw_ostream::RED, true); 358| 116| S << "error: "; 359| 116| break; 360| 815| case SourceMgr::DK_Warning: ------------------ | Branch (360:5): [True: 815, False: 1.35k] ------------------ 361| 815| if (ShowColors) ------------------ | Branch (361:11): [True: 815, False: 0] ------------------ 362| 815| S.changeColor(raw_ostream::MAGENTA, true); 363| 815| S << "warning: "; 364| 815| break; 365| 1.24k| case SourceMgr::DK_Note: ------------------ | Branch (365:5): [True: 1.24k, False: 931] ------------------ 366| 1.24k| if (ShowColors) ------------------ | Branch (366:11): [True: 1.24k, False: 0] ------------------ 367| 1.24k| S.changeColor(raw_ostream::BLACK, true); 368| 1.24k| S << "note: "; 369| 1.24k| break; 370| 2.17k| } 371| | 372| 2.17k| if (ShowColors) { ------------------ | Branch (372:9): [True: 2.17k, False: 0] ------------------ 373| 2.17k| S.resetColor(); 374| 2.17k| S.changeColor(raw_ostream::SAVEDCOLOR, true); 375| 2.17k| } 376| 2.17k| } 377| | 378| 2.17k| S << Message << '\n'; 379| | 380| 2.17k| if (ShowColors) ------------------ | Branch (380:7): [True: 2.17k, False: 0] ------------------ 381| 2.17k| S.resetColor(); 382| | 383| 2.17k| if (LineNo == -1 || ColumnNo == -1) ------------------ | Branch (383:7): [True: 0, False: 2.17k] | Branch (383:23): [True: 0, False: 2.17k] ------------------ 384| 0| return; 385| | 386| | // FIXME: If there are multibyte or multi-column characters in the source, all 387| | // our ranges will be wrong. To do this properly, we'll need a byte-to-column 388| | // map like Clang's TextDiagnostic. For now, we'll just handle tabs by 389| | // expanding them later, and bail out rather than show incorrect ranges and 390| | // misaligned fixits for any other odd characters. 391| 2.17k| if (std::find_if(LineContents.begin(), LineContents.end(), isNonASCII) != ------------------ | Branch (391:7): [True: 669, False: 1.50k] ------------------ 392| 2.17k| LineContents.end()) { 393| 669| printSourceLine(S, LineContents); 394| 669| return; 395| 669| } 396| 1.50k| size_t NumColumns = LineContents.size(); 397| | 398| | // Build the line with the caret and ranges. 399| 1.50k| std::string CaretLine(NumColumns+1, ' '); 400| | 401| | // Expand any ranges. 402| 1.50k| for (unsigned r = 0, e = Ranges.size(); r != e; ++r) { ------------------ | Branch (402:43): [True: 0, False: 1.50k] ------------------ 403| 0| std::pair R = Ranges[r]; 404| 0| std::fill(&CaretLine[R.first], 405| 0| &CaretLine[std::min((size_t)R.second, CaretLine.size())], 406| 0| '~'); 407| 0| } 408| | 409| | // Add any fix-its. 410| | // FIXME: Find the beginning of the line properly for multibyte characters. 411| 1.50k| std::string FixItInsertionLine; 412| 1.50k| buildFixItLine(CaretLine, FixItInsertionLine, FixIts, 413| 1.50k| makeArrayRef(Loc.getPointer() - ColumnNo, 414| 1.50k| LineContents.size())); 415| | 416| | // Finally, plop on the caret. 417| 1.50k| if (unsigned(ColumnNo) <= NumColumns) ------------------ | Branch (417:7): [True: 1.50k, False: 0] ------------------ 418| 1.50k| CaretLine[ColumnNo] = '^'; 419| 0| else 420| 0| CaretLine[NumColumns] = '^'; 421| | 422| | // ... and remove trailing whitespace so the output doesn't wrap for it. We 423| | // know that the line isn't completely empty because it has the caret in it at 424| | // least. 425| 1.50k| CaretLine.erase(CaretLine.find_last_not_of(' ')+1); 426| | 427| 1.50k| printSourceLine(S, LineContents); 428| | 429| 1.50k| if (ShowColors) ------------------ | Branch (429:7): [True: 1.50k, False: 0] ------------------ 430| 1.50k| S.changeColor(raw_ostream::GREEN, true); 431| | 432| | // Print out the caret line, matching tabs in the source line. 433| 6.51k| for (unsigned i = 0, e = CaretLine.size(), OutCol = 0; i != e; ++i) { ------------------ | Branch (433:58): [True: 5.00k, False: 1.50k] ------------------ 434| 5.00k| if (i >= LineContents.size() || LineContents[i] != '\t') { ------------------ | Branch (434:9): [True: 0, False: 5.00k] | Branch (434:37): [True: 4.93k, False: 71] ------------------ 435| 4.93k| S << CaretLine[i]; 436| 4.93k| ++OutCol; 437| 4.93k| continue; 438| 4.93k| } 439| | 440| | // Okay, we have a tab. Insert the appropriate number of characters. 441| 172| do { 442| 172| S << CaretLine[i]; 443| 172| ++OutCol; 444| 172| } while ((OutCol % TabStop) != 0); ------------------ | Branch (444:14): [True: 101, False: 71] ------------------ 445| 71| } 446| 1.50k| S << '\n'; 447| | 448| 1.50k| if (ShowColors) ------------------ | Branch (448:7): [True: 1.50k, False: 0] ------------------ 449| 1.50k| S.resetColor(); 450| | 451| | // Print out the replacement line, matching tabs in the source line. 452| 1.50k| if (FixItInsertionLine.empty()) ------------------ | Branch (452:7): [True: 1.50k, False: 0] ------------------ 453| 1.50k| return; 454| | 455| 0| for (size_t i = 0, e = FixItInsertionLine.size(), OutCol = 0; i < e; ++i) { ------------------ | Branch (455:65): [True: 0, False: 0] ------------------ 456| 0| if (i >= LineContents.size() || LineContents[i] != '\t') { ------------------ | Branch (456:9): [True: 0, False: 0] | Branch (456:37): [True: 0, False: 0] ------------------ 457| 0| S << FixItInsertionLine[i]; 458| 0| ++OutCol; 459| 0| continue; 460| 0| } 461| | 462| | // Okay, we have a tab. Insert the appropriate number of characters. 463| 0| do { 464| 0| S << FixItInsertionLine[i]; 465| | // FIXME: This is trying not to break up replacements, but then to re-sync 466| | // with the tabs between replacements. This will fail, though, if two 467| | // fix-it replacements are exactly adjacent, or if a fix-it contains a 468| | // space. Really we should be precomputing column widths, which we'll 469| | // need anyway for multibyte chars. 470| 0| if (FixItInsertionLine[i] != ' ') ------------------ | Branch (470:11): [True: 0, False: 0] ------------------ 471| 0| ++i; 472| 0| ++OutCol; 473| 0| } while (((OutCol % TabStop) != 0) && i != e); ------------------ | Branch (473:14): [True: 0, False: 0] | Branch (473:43): [True: 0, False: 0] ------------------ 474| 0| } 475| 0| S << '\n'; 476| 0|} SourceMgr.cpp:_ZL8getCachePv: 33| 5.99k|static LineNoCacheTy *getCache(void *Ptr) { 34| 5.99k| return (LineNoCacheTy*)Ptr; 35| 5.99k|} SourceMgr.cpp:_ZL10isNonASCIIc: 324| 49.2k|static bool isNonASCII(char c) { 325| 49.2k| return c & 0x80; 326| 49.2k|} SourceMgr.cpp:_ZL15printSourceLineRN7llvm_ks11raw_ostreamENS_9StringRefE: 306| 2.17k|static void printSourceLine(raw_ostream &S, StringRef LineContents) { 307| | // Print out the source line one character at a time, so we can expand tabs. 308| 61.8k| for (unsigned i = 0, e = LineContents.size(), OutCol = 0; i != e; ++i) { ------------------ | Branch (308:61): [True: 59.6k, False: 2.17k] ------------------ 309| 59.6k| if (LineContents[i] != '\t') { ------------------ | Branch (309:9): [True: 59.0k, False: 619] ------------------ 310| 59.0k| S << LineContents[i]; 311| 59.0k| ++OutCol; 312| 59.0k| continue; 313| 59.0k| } 314| | 315| | // If we have a tab, emit at least one space, then round up to 8 columns. 316| 1.97k| do { 317| 1.97k| S << ' '; 318| 1.97k| ++OutCol; 319| 1.97k| } while ((OutCol % TabStop) != 0); ------------------ | Branch (319:14): [True: 1.35k, False: 619] ------------------ 320| 619| } 321| 2.17k| S << '\n'; 322| 2.17k|} SourceMgr.cpp:_ZL14buildFixItLineRNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEES6_N7llvm_ks8ArrayRefINS7_7SMFixItEEENS8_IcEE: 243| 1.50k| ArrayRef FixIts, ArrayRef SourceLine){ 244| 1.50k| if (FixIts.empty()) ------------------ | Branch (244:7): [True: 1.50k, False: 0] ------------------ 245| 1.50k| return; 246| | 247| 0| const char *LineStart = SourceLine.begin(); 248| 0| const char *LineEnd = SourceLine.end(); 249| | 250| 0| size_t PrevHintEndCol = 0; 251| | 252| 0| for (ArrayRef::iterator I = FixIts.begin(), E = FixIts.end(); 253| 0| I != E; ++I) { ------------------ | Branch (253:8): [True: 0, False: 0] ------------------ 254| | // If the fixit contains a newline or tab, ignore it. 255| 0| if (I->getText().find_first_of("\n\r\t") != StringRef::npos) ------------------ | Branch (255:9): [True: 0, False: 0] ------------------ 256| 0| continue; 257| | 258| 0| SMRange R = I->getRange(); 259| | 260| | // If the line doesn't contain any part of the range, then ignore it. 261| 0| if (R.Start.getPointer() > LineEnd || R.End.getPointer() < LineStart) ------------------ | Branch (261:9): [True: 0, False: 0] | Branch (261:43): [True: 0, False: 0] ------------------ 262| 0| continue; 263| | 264| | // Translate from SMLoc to column. 265| | // Ignore pieces of the range that go onto other lines. 266| | // FIXME: Handle multibyte characters in the source line. 267| 0| unsigned FirstCol; 268| 0| if (R.Start.getPointer() < LineStart) ------------------ | Branch (268:9): [True: 0, False: 0] ------------------ 269| 0| FirstCol = 0; 270| 0| else 271| 0| FirstCol = R.Start.getPointer() - LineStart; 272| | 273| | // If we inserted a long previous hint, push this one forwards, and add 274| | // an extra space to show that this is not part of the previous 275| | // completion. This is sort of the best we can do when two hints appear 276| | // to overlap. 277| | // 278| | // Note that if this hint is located immediately after the previous 279| | // hint, no space will be added, since the location is more important. 280| 0| unsigned HintCol = FirstCol; 281| 0| if (HintCol < PrevHintEndCol) ------------------ | Branch (281:9): [True: 0, False: 0] ------------------ 282| 0| HintCol = PrevHintEndCol + 1; 283| | 284| | // This relies on one byte per column in our fixit hints. 285| 0| unsigned LastColumnModified = HintCol + I->getText().size(); 286| 0| if (LastColumnModified > FixItLine.size()) ------------------ | Branch (286:9): [True: 0, False: 0] ------------------ 287| 0| FixItLine.resize(LastColumnModified, ' '); 288| | 289| 0| std::copy(I->getText().begin(), I->getText().end(), 290| 0| FixItLine.begin() + HintCol); 291| | 292| 0| PrevHintEndCol = LastColumnModified; 293| | 294| | // For replacements, mark the removal range with '~'. 295| | // FIXME: Handle multibyte characters in the source line. 296| 0| unsigned LastCol; 297| 0| if (R.End.getPointer() >= LineEnd) ------------------ | Branch (297:9): [True: 0, False: 0] ------------------ 298| 0| LastCol = LineEnd - LineStart; 299| 0| else 300| 0| LastCol = R.End.getPointer() - LineStart; 301| | 302| 0| std::fill(&CaretLine[FirstCol], &CaretLine[LastCol], '~'); 303| 0| } 304| 0|} _ZN7llvm_ks13StringMapImpl4initEj: 36| 2.19k|void StringMapImpl::init(unsigned InitSize) { 37| 2.19k| assert((InitSize & (InitSize-1)) == 0 && ------------------ | Branch (37:3): [True: 2.19k, False: 0] | Branch (37:3): [True: 2.19k, Folded] | Branch (37:3): [True: 2.19k, False: 0] ------------------ 38| 2.19k| "Init Size must be a power of 2 or zero!"); 39| 2.19k| NumBuckets = InitSize ? InitSize : 16; ------------------ | Branch (39:16): [True: 2.19k, False: 0] ------------------ 40| 2.19k| NumItems = 0; 41| 2.19k| NumTombstones = 0; 42| | 43| 2.19k| TheTable = (StringMapEntryBase **)calloc(NumBuckets+1, 44| 2.19k| sizeof(StringMapEntryBase **) + 45| 2.19k| sizeof(unsigned)); 46| | 47| | // Allocate one extra bucket, set it to look filled so the iterators stop at 48| | // end. 49| 2.19k| TheTable[NumBuckets] = (StringMapEntryBase*)2; 50| 2.19k|} _ZN7llvm_ks13StringMapImpl15LookupBucketForENS_9StringRefE: 58| 118k|unsigned StringMapImpl::LookupBucketFor(StringRef Name) { 59| 118k| unsigned HTSize = NumBuckets; 60| 118k| if (HTSize == 0) { // Hash table unallocated so far? ------------------ | Branch (60:7): [True: 2.19k, False: 116k] ------------------ 61| 2.19k| init(16); 62| 2.19k| HTSize = NumBuckets; 63| 2.19k| } 64| 118k| unsigned FullHashValue = HashString(Name); 65| 118k| unsigned BucketNo = FullHashValue & (HTSize-1); 66| 118k| unsigned *HashTable = (unsigned *)(TheTable + NumBuckets + 1); 67| | 68| 118k| unsigned ProbeAmt = 1; 69| 118k| int FirstTombstone = -1; 70| 274k| while (1) { ------------------ | Branch (70:10): [True: 274k, Folded] ------------------ 71| 274k| StringMapEntryBase *BucketItem = TheTable[BucketNo]; 72| | // If we found an empty bucket, this key isn't in the table yet, return it. 73| 274k| if (LLVM_LIKELY(!BucketItem)) { ------------------ | | 171| 274k|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 100k, False: 173k] | | ------------------ ------------------ 74| | // If we found a tombstone, we want to reuse the tombstone instead of an 75| | // empty bucket. This reduces probing. 76| 100k| if (FirstTombstone != -1) { ------------------ | Branch (76:11): [True: 0, False: 100k] ------------------ 77| 0| HashTable[FirstTombstone] = FullHashValue; 78| 0| return FirstTombstone; 79| 0| } 80| | 81| 100k| HashTable[BucketNo] = FullHashValue; 82| 100k| return BucketNo; 83| 100k| } 84| | 85| 173k| if (BucketItem == getTombstoneVal()) { ------------------ | Branch (85:9): [True: 0, False: 173k] ------------------ 86| | // Skip over tombstones. However, remember the first one we see. 87| 0| if (FirstTombstone == -1) FirstTombstone = BucketNo; ------------------ | Branch (87:11): [True: 0, False: 0] ------------------ 88| 173k| } else if (LLVM_LIKELY(HashTable[BucketNo] == FullHashValue)) { ------------------ | | 171| 173k|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 17.9k, False: 155k] | | ------------------ ------------------ 89| | // If the full hash value matches, check deeply for a match. The common 90| | // case here is that we are only looking at the buckets (for item info 91| | // being non-null and for the full hash value) not at the items. This 92| | // is important for cache locality. 93| | 94| | // Do the comparison like this because Name isn't necessarily 95| | // null-terminated! 96| 17.9k| char *ItemStr = (char*)BucketItem+ItemSize; 97| 17.9k| if (Name == StringRef(ItemStr, BucketItem->getKeyLength())) { ------------------ | Branch (97:11): [True: 17.9k, False: 0] ------------------ 98| | // We found a match! 99| 17.9k| return BucketNo; 100| 17.9k| } 101| 17.9k| } 102| | 103| | // Okay, we didn't find the item. Probe to the next bucket. 104| 155k| BucketNo = (BucketNo+ProbeAmt) & (HTSize-1); 105| | 106| | // Use quadratic probing, it has fewer clumping artifacts than linear 107| | // probing and has good cache behavior in the common case. 108| 155k| ++ProbeAmt; 109| 155k| } 110| 118k|} _ZNK7llvm_ks13StringMapImpl7FindKeyENS_9StringRefE: 116| 64.8k|int StringMapImpl::FindKey(StringRef Key) const { 117| 64.8k| unsigned HTSize = NumBuckets; 118| 64.8k| if (HTSize == 0) return -1; // Really empty table? ------------------ | Branch (118:7): [True: 31.0k, False: 33.7k] ------------------ 119| 33.7k| unsigned FullHashValue = HashString(Key); 120| 33.7k| unsigned BucketNo = FullHashValue & (HTSize-1); 121| 33.7k| unsigned *HashTable = (unsigned *)(TheTable + NumBuckets + 1); 122| | 123| 33.7k| unsigned ProbeAmt = 1; 124| 58.7k| while (1) { ------------------ | Branch (124:10): [True: 58.7k, Folded] ------------------ 125| 58.7k| StringMapEntryBase *BucketItem = TheTable[BucketNo]; 126| | // If we found an empty bucket, this key isn't in the table yet, return. 127| 58.7k| if (LLVM_LIKELY(!BucketItem)) ------------------ | | 171| 58.7k|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 22.1k, False: 36.6k] | | ------------------ ------------------ 128| 22.1k| return -1; 129| | 130| 36.6k| if (BucketItem == getTombstoneVal()) { ------------------ | Branch (130:9): [True: 0, False: 36.6k] ------------------ 131| | // Ignore tombstones. 132| 36.6k| } else if (LLVM_LIKELY(HashTable[BucketNo] == FullHashValue)) { ------------------ | | 171| 36.6k|#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true) | | ------------------ | | | Branch (171:27): [True: 11.7k, False: 24.8k] | | ------------------ ------------------ 133| | // If the full hash value matches, check deeply for a match. The common 134| | // case here is that we are only looking at the buckets (for item info 135| | // being non-null and for the full hash value) not at the items. This 136| | // is important for cache locality. 137| | 138| | // Do the comparison like this because NameStart isn't necessarily 139| | // null-terminated! 140| 11.7k| char *ItemStr = (char*)BucketItem+ItemSize; 141| 11.7k| if (Key == StringRef(ItemStr, BucketItem->getKeyLength())) { ------------------ | Branch (141:11): [True: 11.6k, False: 128] ------------------ 142| | // We found a match! 143| 11.6k| return BucketNo; 144| 11.6k| } 145| 11.7k| } 146| | 147| | // Okay, we didn't find the item. Probe to the next bucket. 148| 25.0k| BucketNo = (BucketNo+ProbeAmt) & (HTSize-1); 149| | 150| | // Use quadratic probing, it has fewer clumping artifacts than linear 151| | // probing and has good cache behavior in the common case. 152| 25.0k| ++ProbeAmt; 153| 25.0k| } 154| 33.7k|} _ZN7llvm_ks13StringMapImpl11RehashTableEj: 184| 100k|unsigned StringMapImpl::RehashTable(unsigned BucketNo) { 185| 100k| unsigned NewSize; 186| 100k| unsigned *HashTable = (unsigned *)(TheTable + NumBuckets + 1); 187| | 188| | // If the hash table is now more than 3/4 full, or if fewer than 1/8 of 189| | // the buckets are empty (meaning that many are filled with tombstones), 190| | // grow/rehash the table. 191| 100k| if (LLVM_UNLIKELY(NumItems * 4 > NumBuckets * 3)) { ------------------ | | 172| 100k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 3.41k, False: 97.0k] | | ------------------ ------------------ 192| 3.41k| NewSize = NumBuckets*2; 193| 97.0k| } else if (LLVM_UNLIKELY(NumBuckets - (NumItems + NumTombstones) <= ------------------ | | 172| 97.0k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 97.0k] | | ------------------ ------------------ 194| 97.0k| NumBuckets / 8)) { 195| 0| NewSize = NumBuckets; 196| 97.0k| } else { 197| 97.0k| return BucketNo; 198| 97.0k| } 199| | 200| 3.41k| unsigned NewBucketNo = BucketNo; 201| | // Allocate one extra bucket which will always be non-empty. This allows the 202| | // iterators to stop at end. 203| 3.41k| StringMapEntryBase **NewTableArray = 204| 3.41k| (StringMapEntryBase **)calloc(NewSize+1, sizeof(StringMapEntryBase *) + 205| 3.41k| sizeof(unsigned)); 206| 3.41k| unsigned *NewHashArray = (unsigned *)(NewTableArray + NewSize + 1); 207| 3.41k| NewTableArray[NewSize] = (StringMapEntryBase*)2; 208| | 209| | // Rehash all the items into their new buckets. Luckily :) we already have 210| | // the hash values available, so we don't have to rehash any strings. 211| 174k| for (unsigned I = 0, E = NumBuckets; I != E; ++I) { ------------------ | Branch (211:40): [True: 171k, False: 3.41k] ------------------ 212| 171k| StringMapEntryBase *Bucket = TheTable[I]; 213| 171k| if (Bucket && Bucket != getTombstoneVal()) { ------------------ | Branch (213:9): [True: 132k, False: 39.4k] | Branch (213:19): [True: 132k, False: 0] ------------------ 214| | // Fast case, bucket available. 215| 132k| unsigned FullHash = HashTable[I]; 216| 132k| unsigned NewBucket = FullHash & (NewSize-1); 217| 132k| if (!NewTableArray[NewBucket]) { ------------------ | Branch (217:11): [True: 103k, False: 28.7k] ------------------ 218| 103k| NewTableArray[FullHash & (NewSize-1)] = Bucket; 219| 103k| NewHashArray[FullHash & (NewSize-1)] = FullHash; 220| 103k| if (I == BucketNo) ------------------ | Branch (220:13): [True: 2.91k, False: 100k] ------------------ 221| 2.91k| NewBucketNo = NewBucket; 222| 103k| continue; 223| 103k| } 224| | 225| | // Otherwise probe for a spot. 226| 28.7k| unsigned ProbeSize = 1; 227| 42.8k| do { 228| 42.8k| NewBucket = (NewBucket + ProbeSize++) & (NewSize-1); 229| 42.8k| } while (NewTableArray[NewBucket]); ------------------ | Branch (229:16): [True: 14.1k, False: 28.7k] ------------------ 230| | 231| | // Finally found a slot. Fill it in. 232| 28.7k| NewTableArray[NewBucket] = Bucket; 233| 28.7k| NewHashArray[NewBucket] = FullHash; 234| 28.7k| if (I == BucketNo) ------------------ | Branch (234:11): [True: 506, False: 28.2k] ------------------ 235| 506| NewBucketNo = NewBucket; 236| 28.7k| } 237| 171k| } 238| | 239| 3.41k| free(TheTable); 240| | 241| 3.41k| TheTable = NewTableArray; 242| 3.41k| NumBuckets = NewSize; 243| 3.41k| NumTombstones = 0; 244| 3.41k| return NewBucketNo; 245| 100k|} _ZNK7llvm_ks9StringRef13compare_lowerES0_: 52| 2.72k|int StringRef::compare_lower(StringRef RHS) const { 53| 2.72k| if (int Res = ascii_strncasecmp(Data, RHS.Data, std::min(Length, RHS.Length))) ------------------ | Branch (53:11): [True: 1.12k, False: 1.59k] ------------------ 54| 1.12k| return Res; 55| 1.59k| if (Length == RHS.Length) ------------------ | Branch (55:7): [True: 918, False: 681] ------------------ 56| 918| return 0; 57| 681| return Length < RHS.Length ? -1 : 1; ------------------ | Branch (57:10): [True: 681, False: 0] ------------------ 58| 1.59k|} _ZNK7llvm_ks9StringRef16startswith_lowerES0_: 61| 704|bool StringRef::startswith_lower(StringRef Prefix) const { 62| 704| return Length >= Prefix.Length && ------------------ | Branch (62:10): [True: 513, False: 191] ------------------ 63| 513| ascii_strncasecmp(Data, Prefix.Data, Prefix.Length) == 0; ------------------ | Branch (63:7): [True: 0, False: 513] ------------------ 64| 704|} _ZNK7llvm_ks9StringRef5lowerEv: 117| 55.9k|std::string StringRef::lower() const { 118| 55.9k| std::string Result(size(), char()); 119| 672k| for (size_type i = 0, e = size(); i != e; ++i) { ------------------ | Branch (119:37): [True: 616k, False: 55.9k] ------------------ 120| 616k| Result[i] = ascii_tolower(Data[i]); 121| 616k| } 122| 55.9k| return Result; 123| 55.9k|} _ZNK7llvm_ks9StringRef4findES0_m: 142| 9.03k|size_t StringRef::find(StringRef Str, size_t From) const { 143| 9.03k| if (From > Length) ------------------ | Branch (143:7): [True: 0, False: 9.03k] ------------------ 144| 0| return npos; 145| | 146| 9.03k| const char *Needle = Str.data(); 147| 9.03k| size_t N = Str.size(); 148| 9.03k| if (N == 0) ------------------ | Branch (148:7): [True: 0, False: 9.03k] ------------------ 149| 0| return From; 150| | 151| 9.03k| size_t Size = Length - From; 152| 9.03k| if (Size < N) ------------------ | Branch (152:7): [True: 0, False: 9.03k] ------------------ 153| 0| return npos; 154| | 155| 9.03k| const char *Start = Data + From; 156| 9.03k| const char *Stop = Start + (Size - N + 1); 157| | 158| | // For short haystacks or unsupported needles fall back to the naive algorithm 159| 9.03k| if (Size < 16 || N > 255) { ------------------ | Branch (159:7): [True: 9.03k, False: 2] | Branch (159:20): [True: 0, False: 2] ------------------ 160| 9.03k| do { 161| 9.03k| if (std::memcmp(Start, Needle, N) == 0) ------------------ | Branch (161:11): [True: 0, False: 9.03k] ------------------ 162| 0| return Start - Data; 163| 9.03k| ++Start; 164| 9.03k| } while (Start < Stop); ------------------ | Branch (164:14): [True: 0, False: 9.03k] ------------------ 165| 9.03k| return npos; 166| 9.03k| } 167| | 168| | // Build the bad char heuristic table, with uint8_t to reduce cache thrashing. 169| 2| uint8_t BadCharSkip[256]; 170| 2| std::memset(BadCharSkip, N, 256); 171| 4| for (unsigned i = 0; i != N-1; ++i) ------------------ | Branch (171:24): [True: 2, False: 2] ------------------ 172| 2| BadCharSkip[(uint8_t)Str[i]] = N-1-i; 173| | 174| 2.03k| do { 175| 2.03k| if (std::memcmp(Start, Needle, N) == 0) ------------------ | Branch (175:9): [True: 0, False: 2.03k] ------------------ 176| 0| return Start - Data; 177| | 178| | // Otherwise skip the appropriate number of bytes. 179| 2.03k| Start += BadCharSkip[(uint8_t)Start[N-1]]; 180| 2.03k| } while (Start < Stop); ------------------ | Branch (180:12): [True: 2.03k, False: 2] ------------------ 181| | 182| 2| return npos; 183| 2|} _ZNK7llvm_ks9StringRef17find_first_not_ofES0_m: 231| 3.28k| size_t From) const { 232| 3.28k| std::bitset<1 << CHAR_BIT> CharBits; 233| 22.9k| for (size_type i = 0; i != Chars.size(); ++i) ------------------ | Branch (233:25): [True: 19.7k, False: 3.28k] ------------------ 234| 19.7k| CharBits.set((unsigned char)Chars[i]); 235| | 236| 5.97k| for (size_type i = std::min(From, Length), e = Length; i != e; ++i) ------------------ | Branch (236:58): [True: 5.72k, False: 257] ------------------ 237| 5.72k| if (!CharBits.test((unsigned char)Data[i])) ------------------ | Branch (237:9): [True: 3.02k, False: 2.69k] ------------------ 238| 3.02k| return i; 239| 257| return npos; 240| 3.28k|} _ZNK7llvm_ks9StringRef12find_last_ofES0_m: 247| 2.78k| size_t From) const { 248| 2.78k| std::bitset<1 << CHAR_BIT> CharBits; 249| 8.34k| for (size_type i = 0; i != Chars.size(); ++i) ------------------ | Branch (249:25): [True: 5.56k, False: 2.78k] ------------------ 250| 5.56k| CharBits.set((unsigned char)Chars[i]); 251| | 252| 9.63k| for (size_type i = std::min(From, Length) - 1, e = -1; i != e; --i) ------------------ | Branch (252:58): [True: 9.31k, False: 316] ------------------ 253| 9.31k| if (CharBits.test((unsigned char)Data[i])) ------------------ | Branch (253:9): [True: 2.46k, False: 6.84k] ------------------ 254| 2.46k| return i; 255| 316| return npos; 256| 2.78k|} _ZNK7llvm_ks9StringRef16find_last_not_ofES0_m: 272| 3.28k| size_t From) const { 273| 3.28k| std::bitset<1 << CHAR_BIT> CharBits; 274| 22.9k| for (size_type i = 0, e = Chars.size(); i != e; ++i) ------------------ | Branch (274:43): [True: 19.7k, False: 3.28k] ------------------ 275| 19.7k| CharBits.set((unsigned char)Chars[i]); 276| | 277| 3.44k| for (size_type i = std::min(From, Length) - 1, e = -1; i != e; --i) ------------------ | Branch (277:58): [True: 3.19k, False: 257] ------------------ 278| 3.19k| if (!CharBits.test((unsigned char)Data[i])) ------------------ | Branch (278:9): [True: 3.02k, False: 164] ------------------ 279| 3.02k| return i; 280| 257| return npos; 281| 3.28k|} _ZNK7llvm_ks9StringRef5splitERNS_15SmallVectorImplIS0_EEcib: 311| 7.50k| int MaxSplit, bool KeepEmpty) const { 312| 7.50k| StringRef S = *this; 313| | 314| | // Count down from MaxSplit. When MaxSplit is -1, this will just split 315| | // "forever". This doesn't support splitting more than 2^31 times 316| | // intentionally; if we ever want that we can make MaxSplit a 64-bit integer 317| | // but that seems unlikely to be useful. 318| 8.89k| while (MaxSplit-- != 0) { ------------------ | Branch (318:10): [True: 8.89k, False: 0] ------------------ 319| 8.89k| size_t Idx = S.find(Separator); 320| 8.89k| if (Idx == npos) ------------------ | Branch (320:9): [True: 7.50k, False: 1.38k] ------------------ 321| 7.50k| break; 322| | 323| | // Push this split. 324| 1.38k| if (KeepEmpty || Idx > 0) ------------------ | Branch (324:9): [True: 527, False: 860] | Branch (324:22): [True: 860, False: 0] ------------------ 325| 1.38k| A.push_back(S.slice(0, Idx)); 326| | 327| | // Jump forward. 328| 1.38k| S = S.slice(Idx + 1, npos); 329| 1.38k| } 330| | 331| | // Push the tail. 332| 7.50k| if (KeepEmpty || !S.empty()) ------------------ | Branch (332:7): [True: 4.31k, False: 3.19k] | Branch (332:20): [True: 3.16k, False: 25] ------------------ 333| 7.48k| A.push_back(S); 334| 7.50k|} _ZNK7llvm_ks9StringRef12getAsIntegerEjRNS_5APIntE: 445| 12.0k|bool StringRef::getAsInteger(unsigned Radix, APInt &Result) const { 446| 12.0k| StringRef Str = *this; 447| | 448| | // Autosense radix if not specified. 449| 12.0k| if (Radix == 0) ------------------ | Branch (449:7): [True: 274, False: 11.7k] ------------------ 450| 274| Radix = GetAutoSenseRadix(Str); 451| | 452| 12.0k| assert(Radix > 1 && Radix <= 36); ------------------ | Branch (452:3): [True: 12.0k, False: 0] | Branch (452:3): [True: 12.0k, False: 0] | Branch (452:3): [True: 12.0k, False: 0] ------------------ 453| | 454| | // Empty strings (after the radix autosense) are invalid. 455| 12.0k| if (Str.empty()) return true; ------------------ | Branch (455:7): [True: 0, False: 12.0k] ------------------ 456| | 457| | // Skip leading zeroes. This can be a significant improvement if 458| | // it means we don't need > 64 bits. 459| 24.6k| while (!Str.empty() && Str.front() == '0') ------------------ | Branch (459:10): [True: 22.7k, False: 1.97k] | Branch (459:26): [True: 12.6k, False: 10.0k] ------------------ 460| 12.6k| Str = Str.substr(1); 461| | 462| | // If it was nothing but zeroes.... 463| 12.0k| if (Str.empty()) { ------------------ | Branch (463:7): [True: 1.97k, False: 10.0k] ------------------ 464| 1.97k| Result = APInt(64, 0); 465| 1.97k| return false; 466| 1.97k| } 467| | 468| | // (Over-)estimate the required number of bits. 469| 10.0k| unsigned Log2Radix = 0; 470| 49.7k| while ((1U << Log2Radix) < Radix) Log2Radix++; ------------------ | Branch (470:10): [True: 39.7k, False: 10.0k] ------------------ 471| 10.0k| bool IsPowerOf2Radix = ((1U << Log2Radix) == Radix); 472| | 473| 10.0k| unsigned BitWidth = Log2Radix * Str.size(); 474| 10.0k| if (BitWidth < Result.getBitWidth()) ------------------ | Branch (474:7): [True: 9.97k, False: 52] ------------------ 475| 9.97k| BitWidth = Result.getBitWidth(); // don't shrink the result 476| 52| else if (BitWidth > Result.getBitWidth()) ------------------ | Branch (476:12): [True: 42, False: 10] ------------------ 477| 42| Result = Result.zext(BitWidth); 478| | 479| 10.0k| APInt RadixAP, CharAP; // unused unless !IsPowerOf2Radix 480| 10.0k| if (!IsPowerOf2Radix) { ------------------ | Branch (480:7): [True: 0, False: 10.0k] ------------------ 481| | // These must have the same bit-width as Result. 482| 0| RadixAP = APInt(BitWidth, Radix); 483| 0| CharAP = APInt(BitWidth, 0); 484| 0| } 485| | 486| | // Parse all the bytes of the string given this radix. 487| 10.0k| Result = 0; 488| 74.5k| while (!Str.empty()) { ------------------ | Branch (488:10): [True: 64.5k, False: 10.0k] ------------------ 489| 64.5k| unsigned CharVal; 490| 64.5k| if (Str[0] >= '0' && Str[0] <= '9') ------------------ | Branch (490:9): [True: 64.5k, False: 0] | Branch (490:26): [True: 43.9k, False: 20.5k] ------------------ 491| 43.9k| CharVal = Str[0]-'0'; 492| 20.5k| else if (Str[0] >= 'a' && Str[0] <= 'z') ------------------ | Branch (492:14): [True: 20.1k, False: 396] | Branch (492:31): [True: 20.1k, False: 0] ------------------ 493| 20.1k| CharVal = Str[0]-'a'+10; 494| 396| else if (Str[0] >= 'A' && Str[0] <= 'Z') ------------------ | Branch (494:14): [True: 396, False: 0] | Branch (494:31): [True: 396, False: 0] ------------------ 495| 396| CharVal = Str[0]-'A'+10; 496| 0| else 497| 0| return true; 498| | 499| | // If the parsed value is larger than the integer radix, the string is 500| | // invalid. 501| 64.5k| if (CharVal >= Radix) ------------------ | Branch (501:9): [True: 12, False: 64.5k] ------------------ 502| 12| return true; 503| | 504| | // Add in this character. 505| 64.5k| if (IsPowerOf2Radix) { ------------------ | Branch (505:9): [True: 64.5k, False: 0] ------------------ 506| 64.5k| Result <<= Log2Radix; 507| 64.5k| Result |= CharVal; 508| 64.5k| } else { 509| 0| Result *= RadixAP; 510| 0| CharAP = CharVal; 511| 0| Result += CharAP; 512| 0| } 513| | 514| 64.5k| Str = Str.substr(1); 515| 64.5k| } 516| | 517| 10.0k| return false; 518| 10.0k|} _ZN7llvm_ks10hash_valueENS_9StringRefE: 522| 378|hash_code llvm_ks::hash_value(StringRef S) { 523| 378| return hash_combine_range(S.begin(), S.end()); 524| 378|} StringRef.cpp:_ZL17ascii_strncasecmpPKcS0_m: 41| 3.23k|static int ascii_strncasecmp(const char *LHS, const char *RHS, size_t Length) { 42| 8.02k| for (size_t I = 0; I < Length; ++I) { ------------------ | Branch (42:22): [True: 6.43k, False: 1.59k] ------------------ 43| 6.43k| unsigned char LHC = ascii_tolower(LHS[I]); 44| 6.43k| unsigned char RHC = ascii_tolower(RHS[I]); 45| 6.43k| if (LHC != RHC) ------------------ | Branch (45:9): [True: 1.63k, False: 4.79k] ------------------ 46| 1.63k| return LHC < RHC ? -1 : 1; ------------------ | Branch (46:14): [True: 1.15k, False: 482] ------------------ 47| 6.43k| } 48| 1.59k| return 0; 49| 3.23k|} StringRef.cpp:_ZL13ascii_tolowerc: 23| 629k|static char ascii_tolower(char x) { 24| 629k| if (x >= 'A' && x <= 'Z') ------------------ | Branch (24:7): [True: 481k, False: 147k] | Branch (24:19): [True: 63.2k, False: 418k] ------------------ 25| 63.2k| return x - 'A' + 'a'; 26| 566k| return x; 27| 629k|} StringRef.cpp:_ZL17GetAutoSenseRadixRN7llvm_ks9StringRefE: 353| 274|static unsigned GetAutoSenseRadix(StringRef &Str) { 354| 274| if (Str.startswith("0x") || Str.startswith("0X")) { ------------------ | Branch (354:7): [True: 131, False: 143] | Branch (354:7): [True: 274, False: 0] | Branch (354:31): [True: 143, False: 0] ------------------ 355| 274| Str = Str.substr(2); 356| 274| return 16; 357| 274| } 358| | 359| 0| if (Str.startswith("0b")) { ------------------ | Branch (359:7): [True: 0, False: 0] ------------------ 360| 0| Str = Str.substr(2); 361| 0| return 2; 362| 0| } 363| | 364| 0| if (Str.startswith("0o")) { ------------------ | Branch (364:7): [True: 0, False: 0] ------------------ 365| 0| Str = Str.substr(2); 366| 0| return 8; 367| 0| } 368| | 369| 0| if (Str.startswith("0")) ------------------ | Branch (369:7): [True: 0, False: 0] ------------------ 370| 0| return 8; 371| | 372| 0| return 10; 373| 0|} _ZN7llvm_ks3ARM14getFPUFeaturesEjRNSt3__16vectorIPKcNS1_9allocatorIS4_EEEE: 220| 213| std::vector &Features) { 221| | 222| 213| if (FPUKind >= ARM::FK_LAST || FPUKind == ARM::FK_INVALID) ------------------ | Branch (222:7): [True: 0, False: 213] | Branch (222:34): [True: 148, False: 65] ------------------ 223| 148| return false; 224| | 225| | // fp-only-sp and d16 subtarget features are independent of each other, so we 226| | // must enable/disable both. 227| 65| switch (FPUNames[FPUKind].Restriction) { ------------------ | Branch (227:11): [True: 65, False: 0] ------------------ 228| 11| case ARM::FR_SP_D16: ------------------ | Branch (228:3): [True: 11, False: 54] ------------------ 229| 11| Features.push_back("+fp-only-sp"); 230| 11| Features.push_back("+d16"); 231| 11| break; 232| 0| case ARM::FR_D16: ------------------ | Branch (232:3): [True: 0, False: 65] ------------------ 233| 0| Features.push_back("-fp-only-sp"); 234| 0| Features.push_back("+d16"); 235| 0| break; 236| 54| case ARM::FR_None: ------------------ | Branch (236:3): [True: 54, False: 11] ------------------ 237| 54| Features.push_back("-fp-only-sp"); 238| 54| Features.push_back("-d16"); 239| 54| break; 240| 65| } 241| | 242| | // FPU version subtarget features are inclusive of lower-numbered ones, so 243| | // enable the one corresponding to this version and disable all that are 244| | // higher. We also have to make sure to disable fp16 when vfp4 is disabled, 245| | // as +vfp4 implies +fp16 but -vfp4 does not imply -fp16. 246| 65| switch (FPUNames[FPUKind].FPUVersion) { ------------------ | Branch (246:11): [True: 65, False: 0] ------------------ 247| 6| case ARM::FV_VFPV5: ------------------ | Branch (247:3): [True: 6, False: 59] ------------------ 248| 6| Features.push_back("+fp-armv8"); 249| 6| break; 250| 5| case ARM::FV_VFPV4: ------------------ | Branch (250:3): [True: 5, False: 60] ------------------ 251| 5| Features.push_back("+vfp4"); 252| 5| Features.push_back("-fp-armv8"); 253| 5| break; 254| 0| case ARM::FV_VFPV3_FP16: ------------------ | Branch (254:3): [True: 0, False: 65] ------------------ 255| 0| Features.push_back("+vfp3"); 256| 0| Features.push_back("+fp16"); 257| 0| Features.push_back("-vfp4"); 258| 0| Features.push_back("-fp-armv8"); 259| 0| break; 260| 0| case ARM::FV_VFPV3: ------------------ | Branch (260:3): [True: 0, False: 65] ------------------ 261| 0| Features.push_back("+vfp3"); 262| 0| Features.push_back("-fp16"); 263| 0| Features.push_back("-vfp4"); 264| 0| Features.push_back("-fp-armv8"); 265| 0| break; 266| 22| case ARM::FV_VFPV2: ------------------ | Branch (266:3): [True: 22, False: 43] ------------------ 267| 22| Features.push_back("+vfp2"); 268| 22| Features.push_back("-vfp3"); 269| 22| Features.push_back("-fp16"); 270| 22| Features.push_back("-vfp4"); 271| 22| Features.push_back("-fp-armv8"); 272| 22| break; 273| 32| case ARM::FV_NONE: ------------------ | Branch (273:3): [True: 32, False: 33] ------------------ 274| 32| Features.push_back("-vfp2"); 275| 32| Features.push_back("-vfp3"); 276| 32| Features.push_back("-fp16"); 277| 32| Features.push_back("-vfp4"); 278| 32| Features.push_back("-fp-armv8"); 279| 32| break; 280| 65| } 281| | 282| | // crypto includes neon, so we handle this similarly to FPU version. 283| 65| switch (FPUNames[FPUKind].NeonSupport) { ------------------ | Branch (283:11): [True: 65, False: 0] ------------------ 284| 0| case ARM::NS_Crypto: ------------------ | Branch (284:3): [True: 0, False: 65] ------------------ 285| 0| Features.push_back("+neon"); 286| 0| Features.push_back("+crypto"); 287| 0| break; 288| 0| case ARM::NS_Neon: ------------------ | Branch (288:3): [True: 0, False: 65] ------------------ 289| 0| Features.push_back("+neon"); 290| 0| Features.push_back("-crypto"); 291| 0| break; 292| 65| case ARM::NS_None: ------------------ | Branch (292:3): [True: 65, False: 0] ------------------ 293| 65| Features.push_back("-neon"); 294| 65| Features.push_back("-crypto"); 295| 65| break; 296| 65| } 297| | 298| 65| return true; 299| 65|} _ZN7llvm_ks3ARM11getArchNameEj: 301| 3.16k|StringRef llvm_ks::ARM::getArchName(unsigned ArchKind) { 302| 3.16k| if (ArchKind >= ARM::AK_LAST) ------------------ | Branch (302:7): [True: 0, False: 3.16k] ------------------ 303| 0| return StringRef(); 304| 3.16k| return ARCHNames[ArchKind].getName(); 305| 3.16k|} _ZN7llvm_ks3ARM20getCanonicalArchNameENS_9StringRefE: 423| 32.7k|StringRef llvm_ks::ARM::getCanonicalArchName(StringRef Arch) { 424| 32.7k| size_t offset = StringRef::npos; 425| 32.7k| StringRef A = Arch; 426| 32.7k| StringRef Error = ""; 427| | 428| | // Begins with "arm" / "thumb", move past it. 429| 32.7k| if (A.startswith("arm64")) ------------------ | Branch (429:7): [True: 0, False: 32.7k] ------------------ 430| 0| offset = 5; 431| 32.7k| else if (A.startswith("arm")) ------------------ | Branch (431:12): [True: 2, False: 32.7k] ------------------ 432| 2| offset = 3; 433| 32.7k| else if (A.startswith("thumb")) ------------------ | Branch (433:12): [True: 9.03k, False: 23.7k] ------------------ 434| 9.03k| offset = 5; 435| 23.7k| else if (A.startswith("aarch64")) { ------------------ | Branch (435:12): [True: 0, False: 23.7k] ------------------ 436| 0| offset = 7; 437| | // AArch64 uses "_be", not "eb" suffix. 438| 0| if (A.find("eb") != StringRef::npos) ------------------ | Branch (438:9): [True: 0, False: 0] ------------------ 439| 0| return Error; 440| 0| if (A.substr(offset, 3) == "_be") ------------------ | Branch (440:9): [True: 0, False: 0] ------------------ 441| 0| offset += 3; 442| 0| } 443| | 444| | // Ex. "armebv7", move past the "eb". 445| 32.7k| if (offset != StringRef::npos && A.substr(offset, 2) == "eb") ------------------ | Branch (445:7): [True: 9.03k, False: 23.7k] | Branch (445:7): [True: 0, False: 32.7k] | Branch (445:36): [True: 0, False: 9.03k] ------------------ 446| 0| offset += 2; 447| | // Or, if it ends with eb ("armv7eb"), chop it off. 448| 32.7k| else if (A.endswith("eb")) ------------------ | Branch (448:12): [True: 9.03k, False: 23.7k] ------------------ 449| 9.03k| A = A.substr(0, A.size() - 2); 450| | // Trim the head 451| 32.7k| if (offset != StringRef::npos) ------------------ | Branch (451:7): [True: 9.03k, False: 23.7k] ------------------ 452| 9.03k| A = A.substr(offset); 453| | 454| | // Empty string means offset reached the end, which means it's valid. 455| 32.7k| if (A.empty()) ------------------ | Branch (455:7): [True: 2, False: 32.7k] ------------------ 456| 2| return Arch; 457| | 458| | // Only match non-marketing names 459| 32.7k| if (offset != StringRef::npos) { ------------------ | Branch (459:7): [True: 9.03k, False: 23.7k] ------------------ 460| | // Must start with 'vN'. 461| 9.03k| if (A[0] != 'v' || !std::isdigit(A[1])) ------------------ | Branch (461:9): [True: 0, False: 9.03k] | Branch (461:24): [True: 0, False: 9.03k] ------------------ 462| 0| return Error; 463| | // Can't have an extra 'eb'. 464| 9.03k| if (A.find("eb") != StringRef::npos) ------------------ | Branch (464:9): [True: 0, False: 9.03k] ------------------ 465| 0| return Error; 466| 9.03k| } 467| | 468| | // Arch will either be a 'v' name (v7a) or a marketing name (xscale). 469| 32.7k| return A; 470| 32.7k|} _ZN7llvm_ks3ARM8parseFPUENS_9StringRefE: 481| 213|unsigned llvm_ks::ARM::parseFPU(StringRef FPU) { 482| 213| StringRef Syn = getFPUSynonym(FPU); 483| 4.18k| for (const auto F : FPUNames) { ------------------ | Branch (483:21): [True: 4.18k, False: 148] ------------------ 484| 4.18k| if (Syn == F.getName()) ------------------ | Branch (484:9): [True: 65, False: 4.11k] ------------------ 485| 65| return F.ID; 486| 4.18k| } 487| 148| return ARM::FK_INVALID; 488| 213|} _ZN7llvm_ks3ARM9parseArchENS_9StringRefE: 491| 15.9k|unsigned llvm_ks::ARM::parseArch(StringRef Arch) { 492| 15.9k| Arch = getCanonicalArchName(Arch); 493| 15.9k| StringRef Syn = getArchSynonym(Arch); 494| 297k| for (const auto A : ARCHNames) { ------------------ | Branch (494:21): [True: 297k, False: 336] ------------------ 495| 297k| if (A.getName().endswith(Syn)) ------------------ | Branch (495:9): [True: 15.6k, False: 281k] ------------------ 496| 15.6k| return A.ID; 497| 297k| } 498| 336| return ARM::AK_INVALID; 499| 15.9k|} _ZN7llvm_ks3ARM12parseArchExtENS_9StringRefE: 501| 704|unsigned llvm_ks::ARM::parseArchExt(StringRef ArchExt) { 502| 7.40k| for (const auto A : ARCHExtNames) { ------------------ | Branch (502:21): [True: 7.40k, False: 197] ------------------ 503| 7.40k| if (ArchExt == A.getName()) ------------------ | Branch (503:9): [True: 507, False: 6.89k] ------------------ 504| 507| return A.ID; 505| 7.40k| } 506| 197| return ARM::AEK_INVALID; 507| 704|} _ZN7llvm_ks3ARM12parseArchISAENS_9StringRefE: 518| 4.30k|unsigned llvm_ks::ARM::parseArchISA(StringRef Arch) { 519| 4.30k| return StringSwitch(Arch) 520| 4.30k| .StartsWith("aarch64", ARM::IK_AARCH64) 521| 4.30k| .StartsWith("arm64", ARM::IK_AARCH64) 522| 4.30k| .StartsWith("thumb", ARM::IK_THUMB) 523| 4.30k| .StartsWith("arm", ARM::IK_ARM) 524| 4.30k| .Default(ARM::EK_INVALID); 525| 4.30k|} _ZN7llvm_ks3ARM15parseArchEndianENS_9StringRefE: 528| 4.30k|unsigned llvm_ks::ARM::parseArchEndian(StringRef Arch) { 529| 4.30k| if (Arch.startswith("armeb") || Arch.startswith("thumbeb") || ------------------ | Branch (529:7): [True: 0, False: 4.30k] | Branch (529:7): [True: 0, False: 4.30k] | Branch (529:35): [True: 0, False: 4.30k] ------------------ 530| 4.30k| Arch.startswith("aarch64_be")) ------------------ | Branch (530:7): [True: 0, False: 4.30k] ------------------ 531| 0| return ARM::EK_BIG; 532| | 533| 4.30k| if (Arch.startswith("arm") || Arch.startswith("thumb")) { ------------------ | Branch (533:7): [True: 0, False: 4.30k] | Branch (533:7): [True: 4.30k, False: 0] | Branch (533:33): [True: 4.30k, False: 0] ------------------ 534| 4.30k| if (Arch.endswith("eb")) ------------------ | Branch (534:9): [True: 4.30k, False: 0] ------------------ 535| 4.30k| return ARM::EK_BIG; 536| 0| else 537| 0| return ARM::EK_LITTLE; 538| 4.30k| } 539| | 540| 0| if (Arch.startswith("aarch64")) ------------------ | Branch (540:7): [True: 0, False: 0] ------------------ 541| 0| return ARM::EK_LITTLE; 542| | 543| 0| return ARM::EK_INVALID; 544| 0|} _ZN7llvm_ks3ARM16parseArchProfileENS_9StringRefE: 547| 4.30k|unsigned llvm_ks::ARM::parseArchProfile(StringRef Arch) { 548| 4.30k| Arch = getCanonicalArchName(Arch); 549| 4.30k| switch (parseArch(Arch)) { ------------------ | Branch (549:11): [True: 4.30k, False: 0] ------------------ 550| 0| case ARM::AK_ARMV6M: ------------------ | Branch (550:3): [True: 0, False: 4.30k] ------------------ 551| 0| case ARM::AK_ARMV7M: ------------------ | Branch (551:3): [True: 0, False: 4.30k] ------------------ 552| 0| case ARM::AK_ARMV7EM: ------------------ | Branch (552:3): [True: 0, False: 4.30k] ------------------ 553| 0| case ARM::AK_ARMV8MMainline: ------------------ | Branch (553:3): [True: 0, False: 4.30k] ------------------ 554| 0| case ARM::AK_ARMV8MBaseline: ------------------ | Branch (554:3): [True: 0, False: 4.30k] ------------------ 555| 0| return ARM::PK_M; 556| 0| case ARM::AK_ARMV7R: ------------------ | Branch (556:3): [True: 0, False: 4.30k] ------------------ 557| 0| return ARM::PK_R; 558| 0| case ARM::AK_ARMV7A: ------------------ | Branch (558:3): [True: 0, False: 4.30k] ------------------ 559| 0| case ARM::AK_ARMV7K: ------------------ | Branch (559:3): [True: 0, False: 4.30k] ------------------ 560| 4.30k| case ARM::AK_ARMV8A: ------------------ | Branch (560:3): [True: 4.30k, False: 0] ------------------ 561| 4.30k| case ARM::AK_ARMV8_1A: ------------------ | Branch (561:3): [True: 0, False: 4.30k] ------------------ 562| 4.30k| case ARM::AK_ARMV8_2A: ------------------ | Branch (562:3): [True: 0, False: 4.30k] ------------------ 563| 4.30k| return ARM::PK_A; 564| 4.30k| } 565| 0| return ARM::PK_INVALID; 566| 4.30k|} _ZN7llvm_ks3ARM16parseArchVersionENS_9StringRefE: 569| 4.30k|unsigned llvm_ks::ARM::parseArchVersion(StringRef Arch) { 570| 4.30k| Arch = getCanonicalArchName(Arch); 571| 4.30k| switch (parseArch(Arch)) { ------------------ | Branch (571:11): [True: 4.30k, False: 0] ------------------ 572| 0| case ARM::AK_ARMV2: ------------------ | Branch (572:3): [True: 0, False: 4.30k] ------------------ 573| 0| case ARM::AK_ARMV2A: ------------------ | Branch (573:3): [True: 0, False: 4.30k] ------------------ 574| 0| return 2; 575| 0| case ARM::AK_ARMV3: ------------------ | Branch (575:3): [True: 0, False: 4.30k] ------------------ 576| 0| case ARM::AK_ARMV3M: ------------------ | Branch (576:3): [True: 0, False: 4.30k] ------------------ 577| 0| return 3; 578| 0| case ARM::AK_ARMV4: ------------------ | Branch (578:3): [True: 0, False: 4.30k] ------------------ 579| 0| case ARM::AK_ARMV4T: ------------------ | Branch (579:3): [True: 0, False: 4.30k] ------------------ 580| 0| return 4; 581| 0| case ARM::AK_ARMV5T: ------------------ | Branch (581:3): [True: 0, False: 4.30k] ------------------ 582| 0| case ARM::AK_ARMV5TE: ------------------ | Branch (582:3): [True: 0, False: 4.30k] ------------------ 583| 0| case ARM::AK_IWMMXT: ------------------ | Branch (583:3): [True: 0, False: 4.30k] ------------------ 584| 0| case ARM::AK_IWMMXT2: ------------------ | Branch (584:3): [True: 0, False: 4.30k] ------------------ 585| 0| case ARM::AK_XSCALE: ------------------ | Branch (585:3): [True: 0, False: 4.30k] ------------------ 586| 0| case ARM::AK_ARMV5TEJ: ------------------ | Branch (586:3): [True: 0, False: 4.30k] ------------------ 587| 0| return 5; 588| 0| case ARM::AK_ARMV6: ------------------ | Branch (588:3): [True: 0, False: 4.30k] ------------------ 589| 0| case ARM::AK_ARMV6K: ------------------ | Branch (589:3): [True: 0, False: 4.30k] ------------------ 590| 0| case ARM::AK_ARMV6T2: ------------------ | Branch (590:3): [True: 0, False: 4.30k] ------------------ 591| 0| case ARM::AK_ARMV6KZ: ------------------ | Branch (591:3): [True: 0, False: 4.30k] ------------------ 592| 0| case ARM::AK_ARMV6M: ------------------ | Branch (592:3): [True: 0, False: 4.30k] ------------------ 593| 0| return 6; 594| 0| case ARM::AK_ARMV7A: ------------------ | Branch (594:3): [True: 0, False: 4.30k] ------------------ 595| 0| case ARM::AK_ARMV7R: ------------------ | Branch (595:3): [True: 0, False: 4.30k] ------------------ 596| 0| case ARM::AK_ARMV7M: ------------------ | Branch (596:3): [True: 0, False: 4.30k] ------------------ 597| 0| case ARM::AK_ARMV7S: ------------------ | Branch (597:3): [True: 0, False: 4.30k] ------------------ 598| 0| case ARM::AK_ARMV7EM: ------------------ | Branch (598:3): [True: 0, False: 4.30k] ------------------ 599| 0| case ARM::AK_ARMV7K: ------------------ | Branch (599:3): [True: 0, False: 4.30k] ------------------ 600| 0| return 7; 601| 4.30k| case ARM::AK_ARMV8A: ------------------ | Branch (601:3): [True: 4.30k, False: 0] ------------------ 602| 4.30k| case ARM::AK_ARMV8_1A: ------------------ | Branch (602:3): [True: 0, False: 4.30k] ------------------ 603| 4.30k| case ARM::AK_ARMV8_2A: ------------------ | Branch (603:3): [True: 0, False: 4.30k] ------------------ 604| 4.30k| case ARM::AK_ARMV8MBaseline: ------------------ | Branch (604:3): [True: 0, False: 4.30k] ------------------ 605| 4.30k| case ARM::AK_ARMV8MMainline: ------------------ | Branch (605:3): [True: 0, False: 4.30k] ------------------ 606| 4.30k| return 8; 607| 4.30k| } 608| 0| return 0; 609| 4.30k|} TargetParser.cpp:_ZNK12_GLOBAL__N_13$_07getNameEv: 39| 4.18k| StringRef getName() const { return StringRef(NameCStr, NameLength); } TargetParser.cpp:_ZNK12_GLOBAL__N_13$_17getNameEv: 66| 300k| StringRef getName() const { return StringRef(NameCStr, NameLength); } TargetParser.cpp:_ZNK12_GLOBAL__N_13$_27getNameEv: 89| 7.40k| StringRef getName() const { return StringRef(NameCStr, NameLength); } TargetParser.cpp:_ZL13getFPUSynonymN7llvm_ks9StringRefE: 382| 213|static StringRef getFPUSynonym(StringRef FPU) { 383| 213| return StringSwitch(FPU) 384| 213| .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported 385| 213| .Case("vfp2", "vfpv2") 386| 213| .Case("vfp3", "vfpv3") 387| 213| .Case("vfp4", "vfpv4") 388| 213| .Case("vfp3-d16", "vfpv3-d16") 389| 213| .Case("vfp4-d16", "vfpv4-d16") 390| 213| .Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16") 391| 213| .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16") 392| 213| .Case("fp5-sp-d16", "fpv5-sp-d16") 393| 213| .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16") 394| | // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3. 395| 213| .Case("neon-vfpv3", "neon") 396| 213| .Default(FPU); 397| 213|} TargetParser.cpp:_ZL14getArchSynonymN7llvm_ks9StringRefE: 399| 15.9k|static StringRef getArchSynonym(StringRef Arch) { 400| 15.9k| return StringSwitch(Arch) 401| 15.9k| .Case("v5", "v5t") 402| 15.9k| .Case("v5e", "v5te") 403| 15.9k| .Case("v6j", "v6") 404| 15.9k| .Case("v6hl", "v6k") 405| 15.9k| .Cases("v6m", "v6sm", "v6s-m", "v6-m") 406| 15.9k| .Cases("v6z", "v6zk", "v6kz") 407| 15.9k| .Cases("v7", "v7a", "v7hl", "v7l", "v7-a") 408| 15.9k| .Case("v7r", "v7-r") 409| 15.9k| .Case("v7m", "v7-m") 410| 15.9k| .Case("v7em", "v7e-m") 411| 15.9k| .Cases("v8", "v8a", "aarch64", "arm64", "v8-a") 412| 15.9k| .Case("v8.1a", "v8.1-a") 413| 15.9k| .Case("v8.2a", "v8.2-a") 414| 15.9k| .Case("v8m.base", "v8-m.base") 415| 15.9k| .Case("v8m.main", "v8-m.main") 416| 15.9k| .Default(Arch); 417| 15.9k|} _ZN7llvm_ks14TargetRegistry7targetsEv: 21| 3.01k|iterator_range TargetRegistry::targets() { 22| 3.01k| return make_range(iterator(FirstTarget), iterator()); 23| 3.01k|} _ZN7llvm_ks14TargetRegistry12lookupTargetERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEERNS_6TripleERS7_: 27| 430| std::string &Error) { 28| | // Allocate target machine. First, check whether the user has explicitly 29| | // specified an architecture to compile for. If so we have to look it up by 30| | // name, because it might be a backend that has no mapping to a target triple. 31| 430| const Target *TheTarget = nullptr; 32| 430| if (!ArchName.empty()) { ------------------ | Branch (32:7): [True: 0, False: 430] ------------------ 33| 0| auto I = 34| 0| std::find_if(targets().begin(), targets().end(), 35| 0| [&](const Target &T) { return ArchName == T.getName(); }); 36| | 37| 0| if (I == targets().end()) { ------------------ | Branch (37:9): [True: 0, False: 0] ------------------ 38| 0| Error = "error: invalid target '" + ArchName + "'.\n"; 39| 0| return nullptr; 40| 0| } 41| | 42| 0| TheTarget = &*I; 43| | 44| | // Adjust the triple to match (if known), otherwise stick with the 45| | // given triple. 46| 0| Triple::ArchType Type = Triple::getArchTypeForLLVMName(ArchName); 47| 0| if (Type != Triple::UnknownArch) ------------------ | Branch (47:9): [True: 0, False: 0] ------------------ 48| 0| TheTriple.setArch(Type); 49| 430| } else { 50| | // Get the target specific parser. 51| 430| std::string TempError; 52| 430| TheTarget = TargetRegistry::lookupTarget(TheTriple.getTriple(), TempError); 53| 430| if (!TheTarget) { ------------------ | Branch (53:9): [True: 0, False: 430] ------------------ 54| 0| Error = ": error: unable to get target for '" 55| 0| + TheTriple.getTriple() 56| 0| + "', see --version and --triple.\n"; 57| 0| return nullptr; 58| 0| } 59| 430| } 60| | 61| 430| return TheTarget; 62| 430|} _ZN7llvm_ks14TargetRegistry12lookupTargetERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEERS7_: 65| 430| std::string &Error) { 66| | // Provide special warning when no targets are initialized. 67| 430| if (targets().begin() == targets().end()) { ------------------ | Branch (67:7): [True: 0, False: 430] ------------------ 68| 0| Error = "Unable to find target for this triple (no targets are registered)"; 69| 0| return nullptr; 70| 0| } 71| 430| Triple::ArchType Arch = Triple(TT).getArch(); 72| 430| auto ArchMatch = [&](const Target &T) { return T.ArchMatchFn(Arch); }; 73| 430| auto I = std::find_if(targets().begin(), targets().end(), ArchMatch); 74| | 75| 430| if (I == targets().end()) { ------------------ | Branch (75:7): [True: 0, False: 430] ------------------ 76| 0| Error = "No available targets are compatible with this triple."; 77| 0| return nullptr; 78| 0| } 79| | 80| 430| auto J = std::find_if(std::next(I), targets().end(), ArchMatch); 81| 430| if (J != targets().end()) { ------------------ | Branch (81:7): [True: 0, False: 430] ------------------ 82| 0| Error = std::string("Cannot choose between targets \"") + I->Name + 83| 0| "\" and \"" + J->Name + "\""; 84| 0| return nullptr; 85| 0| } 86| | 87| 430| return &*I; 88| 430|} _ZN7llvm_ks14TargetRegistry14RegisterTargetERNS_6TargetEPKcS4_PFbNS_6Triple8ArchTypeEE: 93| 23| Target::ArchMatchFnTy ArchMatchFn) { 94| 23| assert(Name && ShortDesc && ArchMatchFn && ------------------ | Branch (94:3): [True: 23, False: 0] | Branch (94:3): [True: 23, False: 0] | Branch (94:3): [True: 23, False: 0] | Branch (94:3): [True: 23, Folded] | Branch (94:3): [True: 23, False: 0] ------------------ 95| 23| "Missing required target information!"); 96| | 97| | // Check if this target has already been initialized, we allow this as a 98| | // convenience to some clients. 99| 23| if (T.Name) ------------------ | Branch (99:7): [True: 0, False: 23] ------------------ 100| 0| return; 101| | 102| | // Add to the list of targets. 103| 23| T.Next = FirstTarget; 104| 23| FirstTarget = &T; 105| | 106| 23| T.Name = Name; 107| 23| T.ShortDesc = ShortDesc; 108| 23| T.ArchMatchFn = ArchMatchFn; 109| 23|} TargetRegistry.cpp:_ZZN7llvm_ks14TargetRegistry12lookupTargetERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEERS7_ENK3$_0clERKNS_6TargetE: 72| 9.89k| auto ArchMatch = [&](const Target &T) { return T.ArchMatchFn(Arch); }; _ZN7llvm_ks6TripleC2ERKNS_5TwineE: 618| 3.87k| : Data(Str.str()), Arch(UnknownArch), SubArch(NoSubArch), 619| 3.87k| Vendor(UnknownVendor), OS(UnknownOS), Environment(UnknownEnvironment), 620| 3.87k| ObjectFormat(UnknownObjectFormat) { 621| | // Do minimal parsing by hand here. 622| 3.87k| SmallVector Components; 623| 3.87k| StringRef(Data).split(Components, '-', /*MaxSplit*/ 3); 624| 3.87k| if (Components.size() > 0) { ------------------ | Branch (624:7): [True: 3.87k, False: 0] ------------------ 625| 3.87k| Arch = parseArch(Components[0]); 626| 3.87k| SubArch = parseSubArch(Components[0]); 627| 3.87k| if (Components.size() > 1) { ------------------ | Branch (627:9): [True: 0, False: 3.87k] ------------------ 628| 0| Vendor = parseVendor(Components[1]); 629| 0| if (Components.size() > 2) { ------------------ | Branch (629:11): [True: 0, False: 0] ------------------ 630| 0| OS = parseOS(Components[2]); 631| 0| if (Components.size() > 3) { ------------------ | Branch (631:13): [True: 0, False: 0] ------------------ 632| 0| Environment = parseEnvironment(Components[3]); 633| 0| ObjectFormat = parseFormat(Components[3]); 634| 0| } 635| 0| } 636| 0| } 637| 3.87k| } 638| 3.87k| if (ObjectFormat == UnknownObjectFormat) ------------------ | Branch (638:7): [True: 3.87k, False: 0] ------------------ 639| 3.87k| ObjectFormat = getDefaultFormat(*this); 640| 3.87k|} _ZN7llvm_ks6Triple9normalizeENS_9StringRefE: 677| 430|std::string Triple::normalize(StringRef Str) { 678| 430| bool IsMinGW32 = false; 679| 430| bool IsCygwin = false; 680| | 681| | // Parse into components. 682| 430| SmallVector Components; 683| 430| Str.split(Components, '-'); 684| | 685| | // If the first component corresponds to a known architecture, preferentially 686| | // use it for the architecture. If the second component corresponds to a 687| | // known vendor, preferentially use it for the vendor, etc. This avoids silly 688| | // component movement when a component parses as (eg) both a valid arch and a 689| | // valid os. 690| 430| ArchType Arch = UnknownArch; 691| 430| if (Components.size() > 0) ------------------ | Branch (691:7): [True: 430, False: 0] ------------------ 692| 430| Arch = parseArch(Components[0]); 693| 430| VendorType Vendor = UnknownVendor; 694| 430| if (Components.size() > 1) ------------------ | Branch (694:7): [True: 0, False: 430] ------------------ 695| 0| Vendor = parseVendor(Components[1]); 696| 430| OSType OS = UnknownOS; 697| 430| if (Components.size() > 2) { ------------------ | Branch (697:7): [True: 0, False: 430] ------------------ 698| 0| OS = parseOS(Components[2]); 699| 0| IsCygwin = Components[2].startswith("cygwin"); 700| 0| IsMinGW32 = Components[2].startswith("mingw"); 701| 0| } 702| 430| EnvironmentType Environment = UnknownEnvironment; 703| 430| if (Components.size() > 3) ------------------ | Branch (703:7): [True: 0, False: 430] ------------------ 704| 0| Environment = parseEnvironment(Components[3]); 705| 430| ObjectFormatType ObjectFormat = UnknownObjectFormat; 706| 430| if (Components.size() > 4) ------------------ | Branch (706:7): [True: 0, False: 430] ------------------ 707| 0| ObjectFormat = parseFormat(Components[4]); 708| | 709| | // Note which components are already in their final position. These will not 710| | // be moved. 711| 430| bool Found[4]; 712| 430| Found[0] = Arch != UnknownArch; 713| 430| Found[1] = Vendor != UnknownVendor; 714| 430| Found[2] = OS != UnknownOS; 715| 430| Found[3] = Environment != UnknownEnvironment; 716| | 717| | // If they are not there already, permute the components into their canonical 718| | // positions by seeing if they parse as a valid architecture, and if so moving 719| | // the component to the architecture position etc. 720| 2.15k| for (unsigned Pos = 0; Pos != array_lengthof(Found); ++Pos) { ------------------ | Branch (720:26): [True: 1.72k, False: 430] ------------------ 721| 1.72k| if (Found[Pos]) ------------------ | Branch (721:9): [True: 430, False: 1.29k] ------------------ 722| 430| continue; // Already in the canonical position. 723| | 724| 2.58k| for (unsigned Idx = 0; Idx != Components.size(); ++Idx) { ------------------ | Branch (724:28): [True: 1.29k, False: 1.29k] ------------------ 725| | // Do not reparse any components that already matched. 726| 1.29k| if (Idx < array_lengthof(Found) && Found[Idx]) ------------------ | Branch (726:11): [True: 1.29k, False: 0] | Branch (726:42): [True: 1.29k, False: 0] ------------------ 727| 1.29k| continue; 728| | 729| | // Does this component parse as valid for the target position? 730| 0| bool Valid = false; 731| 0| StringRef Comp = Components[Idx]; 732| 0| switch (Pos) { 733| 0| default: llvm_unreachable("unexpected component type!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ | Branch (733:7): [True: 0, False: 0] ------------------ 734| 0| case 0: ------------------ | Branch (734:7): [True: 0, False: 0] ------------------ 735| 0| Arch = parseArch(Comp); 736| 0| Valid = Arch != UnknownArch; 737| 0| break; 738| 0| case 1: ------------------ | Branch (738:7): [True: 0, False: 0] ------------------ 739| 0| Vendor = parseVendor(Comp); 740| 0| Valid = Vendor != UnknownVendor; 741| 0| break; 742| 0| case 2: ------------------ | Branch (742:7): [True: 0, False: 0] ------------------ 743| 0| OS = parseOS(Comp); 744| 0| IsCygwin = Comp.startswith("cygwin"); 745| 0| IsMinGW32 = Comp.startswith("mingw"); 746| 0| Valid = OS != UnknownOS || IsCygwin || IsMinGW32; ------------------ | Branch (746:17): [True: 0, False: 0] | Branch (746:36): [True: 0, False: 0] | Branch (746:48): [True: 0, False: 0] ------------------ 747| 0| break; 748| 0| case 3: ------------------ | Branch (748:7): [True: 0, False: 0] ------------------ 749| 0| Environment = parseEnvironment(Comp); 750| 0| Valid = Environment != UnknownEnvironment; 751| 0| if (!Valid) { ------------------ | Branch (751:13): [True: 0, False: 0] ------------------ 752| 0| ObjectFormat = parseFormat(Comp); 753| 0| Valid = ObjectFormat != UnknownObjectFormat; 754| 0| } 755| 0| break; 756| 0| } 757| 0| if (!Valid) ------------------ | Branch (757:11): [True: 0, False: 0] ------------------ 758| 0| continue; // Nope, try the next component. 759| | 760| | // Move the component to the target position, pushing any non-fixed 761| | // components that are in the way to the right. This tends to give 762| | // good results in the common cases of a forgotten vendor component 763| | // or a wrongly positioned environment. 764| 0| if (Pos < Idx) { ------------------ | Branch (764:11): [True: 0, False: 0] ------------------ 765| | // Insert left, pushing the existing components to the right. For 766| | // example, a-b-i386 -> i386-a-b when moving i386 to the front. 767| 0| StringRef CurrentComponent(""); // The empty component. 768| | // Replace the component we are moving with an empty component. 769| 0| std::swap(CurrentComponent, Components[Idx]); 770| | // Insert the component being moved at Pos, displacing any existing 771| | // components to the right. 772| 0| for (unsigned i = Pos; !CurrentComponent.empty(); ++i) { ------------------ | Branch (772:32): [True: 0, False: 0] ------------------ 773| | // Skip over any fixed components. 774| 0| while (i < array_lengthof(Found) && Found[i]) ------------------ | Branch (774:18): [True: 0, False: 0] | Branch (774:47): [True: 0, False: 0] ------------------ 775| 0| ++i; 776| | // Place the component at the new position, getting the component 777| | // that was at this position - it will be moved right. 778| 0| std::swap(CurrentComponent, Components[i]); 779| 0| } 780| 0| } else if (Pos > Idx) { ------------------ | Branch (780:18): [True: 0, False: 0] ------------------ 781| | // Push right by inserting empty components until the component at Idx 782| | // reaches the target position Pos. For example, pc-a -> -pc-a when 783| | // moving pc to the second position. 784| 0| do { 785| | // Insert one empty component at Idx. 786| 0| StringRef CurrentComponent(""); // The empty component. 787| 0| for (unsigned i = Idx; i < Components.size();) { ------------------ | Branch (787:34): [True: 0, False: 0] ------------------ 788| | // Place the component at the new position, getting the component 789| | // that was at this position - it will be moved right. 790| 0| std::swap(CurrentComponent, Components[i]); 791| | // If it was placed on top of an empty component then we are done. 792| 0| if (CurrentComponent.empty()) ------------------ | Branch (792:17): [True: 0, False: 0] ------------------ 793| 0| break; 794| | // Advance to the next component, skipping any fixed components. 795| 0| while (++i < array_lengthof(Found) && Found[i]) ------------------ | Branch (795:20): [True: 0, False: 0] | Branch (795:51): [True: 0, False: 0] ------------------ 796| 0| ; 797| 0| } 798| | // The last component was pushed off the end - append it. 799| 0| if (!CurrentComponent.empty()) ------------------ | Branch (799:15): [True: 0, False: 0] ------------------ 800| 0| Components.push_back(CurrentComponent); 801| | 802| | // Advance Idx to the component's new position. 803| 0| while (++Idx < array_lengthof(Found) && Found[Idx]) ------------------ | Branch (803:18): [True: 0, False: 0] | Branch (803:51): [True: 0, False: 0] ------------------ 804| 0| ; 805| 0| } while (Idx < Pos); // Add more until the final position is reached. ------------------ | Branch (805:18): [True: 0, False: 0] ------------------ 806| 0| } 807| 0| assert(Pos < Components.size() && Components[Pos] == Comp && ------------------ | Branch (807:7): [True: 0, False: 0] | Branch (807:7): [True: 0, False: 0] | Branch (807:7): [True: 0, Folded] | Branch (807:7): [True: 0, False: 0] ------------------ 808| 0| "Component moved wrong!"); 809| 0| Found[Pos] = true; 810| 0| break; 811| 0| } 812| 1.29k| } 813| | 814| | // Special case logic goes here. At this point Arch, Vendor and OS have the 815| | // correct values for the computed components. 816| 430| std::string NormalizedEnvironment; 817| 430| if (Environment == Triple::Android && Components[3].startswith("androideabi")) { ------------------ | Branch (817:7): [True: 0, False: 430] | Branch (817:7): [True: 0, False: 430] | Branch (817:41): [True: 0, False: 0] ------------------ 818| 0| StringRef AndroidVersion = Components[3].drop_front(strlen("androideabi")); 819| 0| if (AndroidVersion.empty()) { ------------------ | Branch (819:9): [True: 0, False: 0] ------------------ 820| 0| Components[3] = "android"; 821| 0| } else { 822| 0| NormalizedEnvironment = Twine("android", AndroidVersion).str(); 823| 0| Components[3] = NormalizedEnvironment; 824| 0| } 825| 0| } 826| | 827| 430| if (OS == Triple::Win32) { ------------------ | Branch (827:7): [True: 0, False: 430] ------------------ 828| 0| Components.resize(4); 829| 0| Components[2] = "windows"; 830| 0| if (Environment == UnknownEnvironment) { ------------------ | Branch (830:9): [True: 0, False: 0] ------------------ 831| 0| if (ObjectFormat == UnknownObjectFormat || ObjectFormat == Triple::COFF) ------------------ | Branch (831:11): [True: 0, False: 0] | Branch (831:50): [True: 0, False: 0] ------------------ 832| 0| Components[3] = "msvc"; 833| 0| else 834| 0| Components[3] = getObjectFormatTypeName(ObjectFormat); 835| 0| } 836| 430| } else if (IsMinGW32) { ------------------ | Branch (836:14): [True: 0, False: 430] ------------------ 837| 0| Components.resize(4); 838| 0| Components[2] = "windows"; 839| 0| Components[3] = "gnu"; 840| 430| } else if (IsCygwin) { ------------------ | Branch (840:14): [True: 0, False: 430] ------------------ 841| 0| Components.resize(4); 842| 0| Components[2] = "windows"; 843| 0| Components[3] = "cygnus"; 844| 0| } 845| 430| if (IsMinGW32 || IsCygwin || ------------------ | Branch (845:7): [True: 0, False: 430] | Branch (845:20): [True: 0, False: 430] ------------------ 846| 430| (OS == Triple::Win32 && Environment != UnknownEnvironment)) { ------------------ | Branch (846:8): [True: 0, False: 430] | Branch (846:31): [True: 0, False: 0] ------------------ 847| 0| if (ObjectFormat != UnknownObjectFormat && ObjectFormat != Triple::COFF) { ------------------ | Branch (847:9): [True: 0, False: 0] | Branch (847:48): [True: 0, False: 0] ------------------ 848| 0| Components.resize(5); 849| 0| Components[4] = getObjectFormatTypeName(ObjectFormat); 850| 0| } 851| 0| } 852| | 853| | // Stick the corrected components back together to form the normalized string. 854| 430| std::string Normalized; 855| 860| for (unsigned i = 0, e = Components.size(); i != e; ++i) { ------------------ | Branch (855:47): [True: 430, False: 430] ------------------ 856| 430| if (i) Normalized += '-'; ------------------ | Branch (856:9): [True: 0, False: 430] ------------------ 857| 430| Normalized += Components[i]; 858| 430| } 859| 430| return Normalized; 860| 430|} _ZNK7llvm_ks6Triple11getArchNameEv: 862| 1.29k|StringRef Triple::getArchName() const { 863| 1.29k| return StringRef(Data).split('-').first; // Isolate first component 864| 1.29k|} Triple.cpp:_ZL9parseArchN7llvm_ks9StringRefE: 341| 4.30k|static Triple::ArchType parseArch(StringRef ArchName) { 342| 4.30k| auto AT = StringSwitch(ArchName) 343| 4.30k| .Cases("i386", "i486", "i586", "i686", Triple::x86) 344| | // FIXME: Do we need to support these? 345| 4.30k| .Cases("i786", "i886", "i986", Triple::x86) 346| 4.30k| .Cases("amd64", "x86_64", "x86_64h", Triple::x86_64) 347| 4.30k| .Cases("powerpc", "ppc32", Triple::ppc) 348| 4.30k| .Cases("powerpc64", "ppu", "ppc64", Triple::ppc64) 349| 4.30k| .Cases("powerpc64le", "ppc64le", Triple::ppc64le) 350| 4.30k| .Case("xscale", Triple::arm) 351| 4.30k| .Case("xscaleeb", Triple::armeb) 352| 4.30k| .Case("aarch64", Triple::aarch64) 353| 4.30k| .Case("aarch64_be", Triple::aarch64_be) 354| 4.30k| .Case("arm64", Triple::aarch64) 355| 4.30k| .Case("arm", Triple::arm) 356| 4.30k| .Case("armeb", Triple::armeb) 357| 4.30k| .Case("thumb", Triple::thumb) 358| 4.30k| .Case("thumbeb", Triple::thumbeb) 359| 4.30k| .Case("avr", Triple::avr) 360| 4.30k| .Case("msp430", Triple::msp430) 361| 4.30k| .Cases("mips", "mipseb", "mipsallegrex", Triple::mips) 362| 4.30k| .Cases("mipsel", "mipsallegrexel", Triple::mipsel) 363| 4.30k| .Cases("mips64", "mips64eb", Triple::mips64) 364| 4.30k| .Case("mips64el", Triple::mips64el) 365| 4.30k| .Case("r600", Triple::r600) 366| 4.30k| .Case("amdgcn", Triple::amdgcn) 367| 4.30k| .Case("riscv32", Triple::riscv32) 368| 4.30k| .Case("riscv64", Triple::riscv64) 369| 4.30k| .Case("hexagon", Triple::hexagon) 370| 4.30k| .Cases("s390x", "systemz", Triple::systemz) 371| 4.30k| .Case("sparc", Triple::sparc) 372| 4.30k| .Case("sparcel", Triple::sparcel) 373| 4.30k| .Cases("sparcv9", "sparc64", Triple::sparcv9) 374| 4.30k| .Case("tce", Triple::tce) 375| 4.30k| .Case("xcore", Triple::xcore) 376| 4.30k| .Case("nvptx", Triple::nvptx) 377| 4.30k| .Case("nvptx64", Triple::nvptx64) 378| 4.30k| .Case("le32", Triple::le32) 379| 4.30k| .Case("le64", Triple::le64) 380| 4.30k| .Case("amdil", Triple::amdil) 381| 4.30k| .Case("amdil64", Triple::amdil64) 382| 4.30k| .Case("hsail", Triple::hsail) 383| 4.30k| .Case("hsail64", Triple::hsail64) 384| 4.30k| .Case("spir", Triple::spir) 385| 4.30k| .Case("spir64", Triple::spir64) 386| 4.30k| .StartsWith("kalimba", Triple::kalimba) 387| 4.30k| .Case("shave", Triple::shave) 388| 4.30k| .Case("wasm32", Triple::wasm32) 389| 4.30k| .Case("wasm64", Triple::wasm64) 390| 4.30k| .Default(Triple::UnknownArch); 391| | 392| | // Some architectures require special parsing logic just to compute the 393| | // ArchType result. 394| 4.30k| if (AT == Triple::UnknownArch) { ------------------ | Branch (394:7): [True: 4.30k, False: 0] ------------------ 395| 4.30k| if (ArchName.startswith("arm") || ArchName.startswith("thumb") || ------------------ | Branch (395:9): [True: 0, False: 4.30k] | Branch (395:9): [True: 4.30k, False: 0] | Branch (395:39): [True: 4.30k, False: 0] ------------------ 396| 0| ArchName.startswith("aarch64")) ------------------ | Branch (396:9): [True: 0, False: 0] ------------------ 397| 4.30k| return parseARMArch(ArchName); 398| 0| if (ArchName.startswith("bpf")) ------------------ | Branch (398:9): [True: 0, False: 0] ------------------ 399| 0| return parseBPFArch(ArchName); 400| 0| } 401| | 402| 0| return AT; 403| 4.30k|} Triple.cpp:_ZL12parseARMArchN7llvm_ks9StringRefE: 283| 4.30k|static Triple::ArchType parseARMArch(StringRef ArchName) { 284| 4.30k| unsigned ISA = ARM::parseArchISA(ArchName); 285| 4.30k| unsigned ENDIAN = ARM::parseArchEndian(ArchName); 286| | 287| 4.30k| Triple::ArchType arch = Triple::UnknownArch; 288| 4.30k| switch (ENDIAN) { ------------------ | Branch (288:11): [True: 4.30k, False: 0] ------------------ 289| 0| case ARM::EK_LITTLE: { ------------------ | Branch (289:3): [True: 0, False: 4.30k] ------------------ 290| 0| switch (ISA) { ------------------ | Branch (290:13): [True: 0, False: 0] ------------------ 291| 0| case ARM::IK_ARM: ------------------ | Branch (291:5): [True: 0, False: 0] ------------------ 292| 0| arch = Triple::arm; 293| 0| break; 294| 0| case ARM::IK_THUMB: ------------------ | Branch (294:5): [True: 0, False: 0] ------------------ 295| 0| arch = Triple::thumb; 296| 0| break; 297| 0| case ARM::IK_AARCH64: ------------------ | Branch (297:5): [True: 0, False: 0] ------------------ 298| 0| arch = Triple::aarch64; 299| 0| break; 300| 0| } 301| 0| break; 302| 0| } 303| 4.30k| case ARM::EK_BIG: { ------------------ | Branch (303:3): [True: 4.30k, False: 0] ------------------ 304| 4.30k| switch (ISA) { ------------------ | Branch (304:13): [True: 4.30k, False: 0] ------------------ 305| 0| case ARM::IK_ARM: ------------------ | Branch (305:5): [True: 0, False: 4.30k] ------------------ 306| 0| arch = Triple::armeb; 307| 0| break; 308| 4.30k| case ARM::IK_THUMB: ------------------ | Branch (308:5): [True: 4.30k, False: 0] ------------------ 309| 4.30k| arch = Triple::thumbeb; 310| 4.30k| break; 311| 0| case ARM::IK_AARCH64: ------------------ | Branch (311:5): [True: 0, False: 4.30k] ------------------ 312| 0| arch = Triple::aarch64_be; 313| 0| break; 314| 4.30k| } 315| 4.30k| break; 316| 4.30k| } 317| 4.30k| } 318| | 319| 4.30k| ArchName = ARM::getCanonicalArchName(ArchName); 320| 4.30k| if (ArchName.empty()) ------------------ | Branch (320:7): [True: 0, False: 4.30k] ------------------ 321| 0| return Triple::UnknownArch; 322| | 323| | // Thumb only exists in v4+ 324| 4.30k| if (ISA == ARM::IK_THUMB && ------------------ | Branch (324:7): [True: 4.30k, False: 0] | Branch (324:7): [True: 0, False: 4.30k] ------------------ 325| 4.30k| (ArchName.startswith("v2") || ArchName.startswith("v3"))) ------------------ | Branch (325:8): [True: 0, False: 4.30k] | Branch (325:37): [True: 0, False: 4.30k] ------------------ 326| 0| return Triple::UnknownArch; 327| | 328| | // Thumb only for v6m 329| 4.30k| unsigned Profile = ARM::parseArchProfile(ArchName); 330| 4.30k| unsigned Version = ARM::parseArchVersion(ArchName); 331| 4.30k| if (Profile == ARM::PK_M && Version == 6) { ------------------ | Branch (331:7): [True: 0, False: 4.30k] | Branch (331:31): [True: 0, False: 0] ------------------ 332| 0| if (ENDIAN == ARM::EK_BIG) ------------------ | Branch (332:9): [True: 0, False: 0] ------------------ 333| 0| return Triple::thumbeb; 334| 0| else 335| 0| return Triple::thumb; 336| 0| } 337| | 338| 4.30k| return arch; 339| 4.30k|} Triple.cpp:_ZL12parseSubArchN7llvm_ks9StringRefE: 481| 3.87k|static Triple::SubArchType parseSubArch(StringRef SubArchName) { 482| 3.87k| StringRef ARMSubArch = ARM::getCanonicalArchName(SubArchName); 483| | 484| | // For now, this is the small part. Early return. 485| 3.87k| if (ARMSubArch.empty()) ------------------ | Branch (485:7): [True: 0, False: 3.87k] ------------------ 486| 0| return StringSwitch(SubArchName) 487| 0| .EndsWith("kalimba3", Triple::KalimbaSubArch_v3) 488| 0| .EndsWith("kalimba4", Triple::KalimbaSubArch_v4) 489| 0| .EndsWith("kalimba5", Triple::KalimbaSubArch_v5) 490| 0| .Default(Triple::NoSubArch); 491| | 492| | // ARM sub arch. 493| 3.87k| switch(ARM::parseArch(ARMSubArch)) { 494| 0| case ARM::AK_ARMV4: ------------------ | Branch (494:3): [True: 0, False: 3.87k] ------------------ 495| 0| return Triple::NoSubArch; 496| 0| case ARM::AK_ARMV4T: ------------------ | Branch (496:3): [True: 0, False: 3.87k] ------------------ 497| 0| return Triple::ARMSubArch_v4t; 498| 0| case ARM::AK_ARMV5T: ------------------ | Branch (498:3): [True: 0, False: 3.87k] ------------------ 499| 0| return Triple::ARMSubArch_v5; 500| 0| case ARM::AK_ARMV5TE: ------------------ | Branch (500:3): [True: 0, False: 3.87k] ------------------ 501| 0| case ARM::AK_IWMMXT: ------------------ | Branch (501:3): [True: 0, False: 3.87k] ------------------ 502| 0| case ARM::AK_IWMMXT2: ------------------ | Branch (502:3): [True: 0, False: 3.87k] ------------------ 503| 0| case ARM::AK_XSCALE: ------------------ | Branch (503:3): [True: 0, False: 3.87k] ------------------ 504| 0| case ARM::AK_ARMV5TEJ: ------------------ | Branch (504:3): [True: 0, False: 3.87k] ------------------ 505| 0| return Triple::ARMSubArch_v5te; 506| 0| case ARM::AK_ARMV6: ------------------ | Branch (506:3): [True: 0, False: 3.87k] ------------------ 507| 0| return Triple::ARMSubArch_v6; 508| 0| case ARM::AK_ARMV6K: ------------------ | Branch (508:3): [True: 0, False: 3.87k] ------------------ 509| 0| case ARM::AK_ARMV6KZ: ------------------ | Branch (509:3): [True: 0, False: 3.87k] ------------------ 510| 0| return Triple::ARMSubArch_v6k; 511| 0| case ARM::AK_ARMV6T2: ------------------ | Branch (511:3): [True: 0, False: 3.87k] ------------------ 512| 0| return Triple::ARMSubArch_v6t2; 513| 0| case ARM::AK_ARMV6M: ------------------ | Branch (513:3): [True: 0, False: 3.87k] ------------------ 514| 0| return Triple::ARMSubArch_v6m; 515| 0| case ARM::AK_ARMV7A: ------------------ | Branch (515:3): [True: 0, False: 3.87k] ------------------ 516| 0| case ARM::AK_ARMV7R: ------------------ | Branch (516:3): [True: 0, False: 3.87k] ------------------ 517| 0| return Triple::ARMSubArch_v7; 518| 0| case ARM::AK_ARMV7K: ------------------ | Branch (518:3): [True: 0, False: 3.87k] ------------------ 519| 0| return Triple::ARMSubArch_v7k; 520| 0| case ARM::AK_ARMV7M: ------------------ | Branch (520:3): [True: 0, False: 3.87k] ------------------ 521| 0| return Triple::ARMSubArch_v7m; 522| 0| case ARM::AK_ARMV7S: ------------------ | Branch (522:3): [True: 0, False: 3.87k] ------------------ 523| 0| return Triple::ARMSubArch_v7s; 524| 0| case ARM::AK_ARMV7EM: ------------------ | Branch (524:3): [True: 0, False: 3.87k] ------------------ 525| 0| return Triple::ARMSubArch_v7em; 526| 3.87k| case ARM::AK_ARMV8A: ------------------ | Branch (526:3): [True: 3.87k, False: 0] ------------------ 527| 3.87k| return Triple::ARMSubArch_v8; 528| 0| case ARM::AK_ARMV8_1A: ------------------ | Branch (528:3): [True: 0, False: 3.87k] ------------------ 529| 0| return Triple::ARMSubArch_v8_1a; 530| 0| case ARM::AK_ARMV8_2A: ------------------ | Branch (530:3): [True: 0, False: 3.87k] ------------------ 531| 0| return Triple::ARMSubArch_v8_2a; 532| 0| case ARM::AK_ARMV8MBaseline: ------------------ | Branch (532:3): [True: 0, False: 3.87k] ------------------ 533| 0| return Triple::ARMSubArch_v8m_baseline; 534| 0| case ARM::AK_ARMV8MMainline: ------------------ | Branch (534:3): [True: 0, False: 3.87k] ------------------ 535| 0| return Triple::ARMSubArch_v8m_mainline; 536| 0| default: ------------------ | Branch (536:3): [True: 0, False: 3.87k] ------------------ 537| 0| return Triple::NoSubArch; 538| 3.87k| } 539| 3.87k|} Triple.cpp:_ZL16getDefaultFormatRKN7llvm_ks6TripleE: 551| 3.87k|static Triple::ObjectFormatType getDefaultFormat(const Triple &T) { 552| 3.87k| switch (T.getArch()) { ------------------ | Branch (552:11): [True: 3.87k, False: 0] ------------------ 553| 0| case Triple::UnknownArch: ------------------ | Branch (553:3): [True: 0, False: 3.87k] ------------------ 554| 0| case Triple::aarch64: ------------------ | Branch (554:3): [True: 0, False: 3.87k] ------------------ 555| 0| case Triple::arm: ------------------ | Branch (555:3): [True: 0, False: 3.87k] ------------------ 556| 0| case Triple::thumb: ------------------ | Branch (556:3): [True: 0, False: 3.87k] ------------------ 557| 0| case Triple::x86: ------------------ | Branch (557:3): [True: 0, False: 3.87k] ------------------ 558| 0| case Triple::x86_64: ------------------ | Branch (558:3): [True: 0, False: 3.87k] ------------------ 559| 0| if (T.isOSDarwin()) ------------------ | Branch (559:9): [True: 0, False: 0] ------------------ 560| 0| return Triple::MachO; 561| 0| else if (T.isOSWindows()) ------------------ | Branch (561:14): [True: 0, False: 0] ------------------ 562| 0| return Triple::COFF; 563| 0| return Triple::ELF; 564| | 565| 0| case Triple::aarch64_be: ------------------ | Branch (565:3): [True: 0, False: 3.87k] ------------------ 566| 0| case Triple::amdgcn: ------------------ | Branch (566:3): [True: 0, False: 3.87k] ------------------ 567| 0| case Triple::amdil: ------------------ | Branch (567:3): [True: 0, False: 3.87k] ------------------ 568| 0| case Triple::amdil64: ------------------ | Branch (568:3): [True: 0, False: 3.87k] ------------------ 569| 0| case Triple::armeb: ------------------ | Branch (569:3): [True: 0, False: 3.87k] ------------------ 570| 0| case Triple::avr: ------------------ | Branch (570:3): [True: 0, False: 3.87k] ------------------ 571| 0| case Triple::bpfeb: ------------------ | Branch (571:3): [True: 0, False: 3.87k] ------------------ 572| 0| case Triple::bpfel: ------------------ | Branch (572:3): [True: 0, False: 3.87k] ------------------ 573| 0| case Triple::hexagon: ------------------ | Branch (573:3): [True: 0, False: 3.87k] ------------------ 574| 0| case Triple::hsail: ------------------ | Branch (574:3): [True: 0, False: 3.87k] ------------------ 575| 0| case Triple::hsail64: ------------------ | Branch (575:3): [True: 0, False: 3.87k] ------------------ 576| 0| case Triple::kalimba: ------------------ | Branch (576:3): [True: 0, False: 3.87k] ------------------ 577| 0| case Triple::le32: ------------------ | Branch (577:3): [True: 0, False: 3.87k] ------------------ 578| 0| case Triple::le64: ------------------ | Branch (578:3): [True: 0, False: 3.87k] ------------------ 579| 0| case Triple::mips: ------------------ | Branch (579:3): [True: 0, False: 3.87k] ------------------ 580| 0| case Triple::mips64: ------------------ | Branch (580:3): [True: 0, False: 3.87k] ------------------ 581| 0| case Triple::mips64el: ------------------ | Branch (581:3): [True: 0, False: 3.87k] ------------------ 582| 0| case Triple::mipsel: ------------------ | Branch (582:3): [True: 0, False: 3.87k] ------------------ 583| 0| case Triple::msp430: ------------------ | Branch (583:3): [True: 0, False: 3.87k] ------------------ 584| 0| case Triple::nvptx: ------------------ | Branch (584:3): [True: 0, False: 3.87k] ------------------ 585| 0| case Triple::nvptx64: ------------------ | Branch (585:3): [True: 0, False: 3.87k] ------------------ 586| 0| case Triple::ppc64le: ------------------ | Branch (586:3): [True: 0, False: 3.87k] ------------------ 587| 0| case Triple::r600: ------------------ | Branch (587:3): [True: 0, False: 3.87k] ------------------ 588| 0| case Triple::riscv32: ------------------ | Branch (588:3): [True: 0, False: 3.87k] ------------------ 589| 0| case Triple::riscv64: ------------------ | Branch (589:3): [True: 0, False: 3.87k] ------------------ 590| 0| case Triple::shave: ------------------ | Branch (590:3): [True: 0, False: 3.87k] ------------------ 591| 0| case Triple::sparc: ------------------ | Branch (591:3): [True: 0, False: 3.87k] ------------------ 592| 0| case Triple::sparcel: ------------------ | Branch (592:3): [True: 0, False: 3.87k] ------------------ 593| 0| case Triple::sparcv9: ------------------ | Branch (593:3): [True: 0, False: 3.87k] ------------------ 594| 0| case Triple::spir: ------------------ | Branch (594:3): [True: 0, False: 3.87k] ------------------ 595| 0| case Triple::spir64: ------------------ | Branch (595:3): [True: 0, False: 3.87k] ------------------ 596| 0| case Triple::systemz: ------------------ | Branch (596:3): [True: 0, False: 3.87k] ------------------ 597| 0| case Triple::tce: ------------------ | Branch (597:3): [True: 0, False: 3.87k] ------------------ 598| 3.87k| case Triple::thumbeb: ------------------ | Branch (598:3): [True: 3.87k, False: 0] ------------------ 599| 3.87k| case Triple::wasm32: ------------------ | Branch (599:3): [True: 0, False: 3.87k] ------------------ 600| 3.87k| case Triple::wasm64: ------------------ | Branch (600:3): [True: 0, False: 3.87k] ------------------ 601| 3.87k| case Triple::xcore: ------------------ | Branch (601:3): [True: 0, False: 3.87k] ------------------ 602| 3.87k| return Triple::ELF; 603| | 604| 0| case Triple::ppc: ------------------ | Branch (604:3): [True: 0, False: 3.87k] ------------------ 605| 0| case Triple::ppc64: ------------------ | Branch (605:3): [True: 0, False: 3.87k] ------------------ 606| 0| if (T.isOSDarwin()) ------------------ | Branch (606:9): [True: 0, False: 0] ------------------ 607| 0| return Triple::MachO; 608| 0| return Triple::ELF; 609| 3.87k| } 610| 0| llvm_unreachable("unknown architecture"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 611| 3.87k|} _ZNK7llvm_ks5Twine3strEv: 16| 9.21k|std::string Twine::str() const { 17| | // If we're storing only a std::string, just return it. 18| 9.21k| if (LHSKind == StdStringKind && RHSKind == EmptyKind) ------------------ | Branch (18:7): [True: 3.01k, False: 6.20k] | Branch (18:35): [True: 2.15k, False: 860] ------------------ 19| 2.15k| return *LHS.stdString; 20| | 21| | // Otherwise, flatten and copy the contents first. 22| 7.06k| SmallString<256> Vec; 23| 7.06k| return toStringRef(Vec).str(); 24| 9.21k|} _ZNK7llvm_ks5Twine8toVectorERNS_15SmallVectorImplIcEE: 26| 3.17k|void Twine::toVector(SmallVectorImpl &Out) const { 27| 3.17k| raw_svector_ostream OS(Out); 28| 3.17k| print(OS); 29| 3.17k|} _ZNK7llvm_ks5Twine25toNullTerminatedStringRefERNS_15SmallVectorImplIcEE: 31| 860|StringRef Twine::toNullTerminatedStringRef(SmallVectorImpl &Out) const { 32| 860| if (isUnary()) { ------------------ | Branch (32:7): [True: 860, False: 0] ------------------ 33| 860| switch (getLHSKind()) { 34| 860| case CStringKind: ------------------ | Branch (34:5): [True: 860, False: 0] ------------------ 35| | // Already null terminated, yay! 36| 860| return StringRef(LHS.cString); 37| 0| case StdStringKind: { ------------------ | Branch (37:5): [True: 0, False: 860] ------------------ 38| 0| const std::string *str = LHS.stdString; 39| 0| return StringRef(str->c_str(), str->size()); 40| 0| } 41| 0| default: ------------------ | Branch (41:5): [True: 0, False: 860] ------------------ 42| 0| break; 43| 860| } 44| 860| } 45| 0| toVector(Out); 46| 0| Out.push_back(0); 47| 0| Out.pop_back(); 48| 0| return StringRef(Out.data(), Out.size()); 49| 860|} _ZNK7llvm_ks5Twine13printOneChildERNS_11raw_ostreamENS0_5ChildENS0_8NodeKindE: 52| 25.8k| NodeKind Kind) const { 53| 25.8k| switch (Kind) { ------------------ | Branch (53:11): [True: 25.8k, False: 0] ------------------ 54| 0| case Twine::NullKind: break; ------------------ | Branch (54:3): [True: 0, False: 25.8k] ------------------ 55| 9.76k| case Twine::EmptyKind: break; ------------------ | Branch (55:3): [True: 9.76k, False: 16.1k] ------------------ 56| 2| case Twine::TwineKind: ------------------ | Branch (56:3): [True: 2, False: 25.8k] ------------------ 57| 2| Ptr.twine->print(OS); 58| 2| break; 59| 12.0k| case Twine::CStringKind: ------------------ | Branch (59:3): [True: 12.0k, False: 13.7k] ------------------ 60| 12.0k| OS << Ptr.cString; 61| 12.0k| break; 62| 860| case Twine::StdStringKind: ------------------ | Branch (62:3): [True: 860, False: 25.0k] ------------------ 63| 860| OS << *Ptr.stdString; 64| 860| break; 65| 3.17k| case Twine::StringRefKind: ------------------ | Branch (65:3): [True: 3.17k, False: 22.7k] ------------------ 66| 3.17k| OS << *Ptr.stringRef; 67| 3.17k| break; 68| 0| case Twine::SmallStringKind: ------------------ | Branch (68:3): [True: 0, False: 25.8k] ------------------ 69| 0| OS << *Ptr.smallString; 70| 0| break; 71| 0| case Twine::CharKind: ------------------ | Branch (71:3): [True: 0, False: 25.8k] ------------------ 72| 0| OS << Ptr.character; 73| 0| break; 74| 0| case Twine::DecUIKind: ------------------ | Branch (74:3): [True: 0, False: 25.8k] ------------------ 75| 0| OS << Ptr.decUI; 76| 0| break; 77| 0| case Twine::DecIKind: ------------------ | Branch (77:3): [True: 0, False: 25.8k] ------------------ 78| 0| OS << Ptr.decI; 79| 0| break; 80| 0| case Twine::DecULKind: ------------------ | Branch (80:3): [True: 0, False: 25.8k] ------------------ 81| 0| OS << *Ptr.decUL; 82| 0| break; 83| 0| case Twine::DecLKind: ------------------ | Branch (83:3): [True: 0, False: 25.8k] ------------------ 84| 0| OS << *Ptr.decL; 85| 0| break; 86| 0| case Twine::DecULLKind: ------------------ | Branch (86:3): [True: 0, False: 25.8k] ------------------ 87| 0| OS << *Ptr.decULL; 88| 0| break; 89| 0| case Twine::DecLLKind: ------------------ | Branch (89:3): [True: 0, False: 25.8k] ------------------ 90| 0| OS << *Ptr.decLL; 91| 0| break; 92| 0| case Twine::UHexKind: ------------------ | Branch (92:3): [True: 0, False: 25.8k] ------------------ 93| 0| OS.write_hex(*Ptr.uHex); 94| 0| break; 95| 25.8k| } 96| 25.8k|} _ZNK7llvm_ks5Twine5printERNS_11raw_ostreamE: 151| 12.9k|void Twine::print(raw_ostream &OS) const { 152| 12.9k| printOneChild(OS, LHS, getLHSKind()); 153| 12.9k| printOneChild(OS, RHS, getRHSKind()); 154| 12.9k|} _ZNK7llvm_ks3sys2fs11file_status11getUniqueIDEv: 177| 860|UniqueID file_status::getUniqueID() const { 178| 860| return UniqueID(fs_st_dev, fs_st_ino); 179| 860|} _ZN7llvm_ks3sys2fs12current_pathERNS_15SmallVectorImplIcEE: 181| 430|std::error_code current_path(SmallVectorImpl &result) { 182| 430| result.clear(); 183| | 184| 430| const char *pwd = ::getenv("PWD"); 185| 430| llvm_ks::sys::fs::file_status PWDStatus, DotStatus; 186| 430| if (pwd && llvm_ks::sys::path::is_absolute(pwd) && ------------------ | Branch (186:7): [True: 430, False: 0] | Branch (186:7): [True: 430, False: 0] | Branch (186:14): [True: 430, False: 0] ------------------ 187| 430| !llvm_ks::sys::fs::status(pwd, PWDStatus) && ------------------ | Branch (187:7): [True: 430, False: 0] ------------------ 188| 430| !llvm_ks::sys::fs::status(".", DotStatus) && ------------------ | Branch (188:7): [True: 430, False: 0] ------------------ 189| 430| PWDStatus.getUniqueID() == DotStatus.getUniqueID()) { ------------------ | Branch (189:7): [True: 430, False: 0] ------------------ 190| 430| result.append(pwd, pwd + strlen(pwd)); 191| 430| return std::error_code(); 192| 430| } 193| | 194| 0|#ifdef MAXPATHLEN 195| 0| result.reserve(MAXPATHLEN); 196| |#else 197| |// For GNU Hurd 198| | result.reserve(1024); 199| |#endif 200| | 201| 0| while (true) { ------------------ | Branch (201:10): [True: 0, Folded] ------------------ 202| 0| if (::getcwd(result.data(), result.capacity()) == nullptr) { ------------------ | Branch (202:9): [True: 0, False: 0] ------------------ 203| | // See if there was a real error. 204| 0| if (errno != ENOMEM) ------------------ | Branch (204:11): [True: 0, False: 0] ------------------ 205| 0| return std::error_code(errno, std::generic_category()); 206| | // Otherwise there just wasn't enough space. 207| 0| result.reserve(result.capacity() * 2); 208| 0| } else 209| 0| break; 210| 0| } 211| | 212| 0| result.set_size(strlen(result.data())); 213| 0| return std::error_code(); 214| 0|} _ZN7llvm_ks3sys2fs6statusERKNS_5TwineERNS1_11file_statusE: 376| 860|std::error_code status(const Twine &Path, file_status &Result) { 377| 860| SmallString<128> PathStorage; 378| 860| StringRef P = Path.toNullTerminatedStringRef(PathStorage); 379| | 380| 860| struct stat Status; 381| 860| int StatRet = ::stat(P.begin(), &Status); 382| 860| return fillStatus(StatRet, Status, Result); 383| 860|} Path.cpp:_ZN7llvm_ks3sys2fsL10fillStatusEiRK4statRNS1_11file_statusE: 343| 860| file_status &Result) { 344| 860| if (StatRet != 0) { ------------------ | Branch (344:7): [True: 0, False: 860] ------------------ 345| 0| std::error_code ec(errno, std::generic_category()); 346| 0| if (ec == errc::no_such_file_or_directory) ------------------ | Branch (346:9): [True: 0, False: 0] ------------------ 347| 0| Result = file_status(file_type::file_not_found); 348| 0| else 349| 0| Result = file_status(file_type::status_error); 350| 0| return ec; 351| 0| } 352| | 353| 860| file_type Type = file_type::type_unknown; 354| | 355| 860| if (S_ISDIR(Status.st_mode)) ------------------ | Branch (355:7): [True: 860, False: 0] ------------------ 356| 860| Type = file_type::directory_file; 357| 0| else if (S_ISREG(Status.st_mode)) ------------------ | Branch (357:12): [True: 0, False: 0] ------------------ 358| 0| Type = file_type::regular_file; 359| 0| else if (S_ISBLK(Status.st_mode)) ------------------ | Branch (359:12): [True: 0, False: 0] ------------------ 360| 0| Type = file_type::block_file; 361| 0| else if (S_ISCHR(Status.st_mode)) ------------------ | Branch (361:12): [True: 0, False: 0] ------------------ 362| 0| Type = file_type::character_file; 363| 0| else if (S_ISFIFO(Status.st_mode)) ------------------ | Branch (363:12): [True: 0, False: 0] ------------------ 364| 0| Type = file_type::fifo_file; 365| 0| else if (S_ISSOCK(Status.st_mode)) ------------------ | Branch (365:12): [True: 0, False: 0] ------------------ 366| 0| Type = file_type::socket_file; 367| | 368| 860| perms Perms = static_cast(Status.st_mode); 369| 860| Result = 370| 860| file_status(Type, Perms, Status.st_dev, Status.st_ino, Status.st_mtime, 371| 860| Status.st_uid, Status.st_gid, Status.st_size); 372| | 373| 860| return std::error_code(); 374| 860|} _ZN7llvm_ks11raw_ostreamD2Ev: 64| 21.9k|raw_ostream::~raw_ostream() { 65| | // raw_ostream's subclasses should take care to flush the buffer 66| | // in their destructors. 67| 21.9k| assert(OutBufCur == OutBufStart && ------------------ | Branch (67:3): [True: 21.9k, False: 0] | Branch (67:3): [True: 21.9k, Folded] | Branch (67:3): [True: 21.9k, False: 0] ------------------ 68| 21.9k| "raw_ostream destructor called with non-empty buffer!"); 69| | 70| 21.9k| if (BufferMode == InternalBuffer) ------------------ | Branch (70:7): [True: 0, False: 21.9k] ------------------ 71| 0| delete [] OutBufStart; 72| 21.9k|} _ZN7llvm_ks11raw_ostream16SetBufferAndModeEPcmNS0_10BufferKindE: 92| 21.9k| BufferKind Mode) { 93| 21.9k| assert(((Mode == Unbuffered && !BufferStart && Size == 0) || ------------------ | Branch (93:3): [True: 21.9k, False: 0] | Branch (93:3): [True: 21.9k, False: 0] | Branch (93:3): [True: 21.9k, False: 0] | Branch (93:3): [True: 0, False: 0] | Branch (93:3): [True: 0, False: 0] | Branch (93:3): [True: 0, False: 0] | Branch (93:3): [True: 21.9k, Folded] | Branch (93:3): [True: 21.9k, False: 0] ------------------ 94| 21.9k| (Mode != Unbuffered && BufferStart && Size != 0)) && 95| 21.9k| "stream must be unbuffered or have at least one byte"); 96| | // Make sure the current buffer is free of content (we can't flush here; the 97| | // child buffer management logic will be in write_impl). 98| 21.9k| assert(GetNumBytesInBuffer() == 0 && "Current buffer is non-empty!"); ------------------ | Branch (98:3): [True: 21.9k, False: 0] | Branch (98:3): [True: 21.9k, Folded] | Branch (98:3): [True: 21.9k, False: 0] ------------------ 99| | 100| 21.9k| if (BufferMode == InternalBuffer) ------------------ | Branch (100:7): [True: 21.9k, False: 0] ------------------ 101| 21.9k| delete [] OutBufStart; 102| 21.9k| OutBufStart = BufferStart; 103| 21.9k| OutBufEnd = OutBufStart+Size; 104| 21.9k| OutBufCur = OutBufStart; 105| 21.9k| BufferMode = Mode; 106| | 107| | assert(OutBufStart <= OutBufEnd && "Invalid size!"); ------------------ | Branch (107:3): [True: 21.9k, False: 0] | Branch (107:3): [True: 21.9k, Folded] | Branch (107:3): [True: 21.9k, False: 0] ------------------ 108| 21.9k|} _ZN7llvm_ks11raw_ostreamlsEm: 110| 5.66k|raw_ostream &raw_ostream::operator<<(unsigned long N) { 111| | // Zero is a special case. 112| 5.66k| if (N == 0) ------------------ | Branch (112:7): [True: 86, False: 5.57k] ------------------ 113| 86| return *this << '0'; 114| | 115| 5.57k| char NumberBuffer[20]; 116| 5.57k| char *EndPtr = NumberBuffer+sizeof(NumberBuffer); 117| 5.57k| char *CurPtr = EndPtr; 118| | 119| 19.3k| while (N) { ------------------ | Branch (119:10): [True: 13.8k, False: 5.57k] ------------------ 120| 13.8k| *--CurPtr = '0' + char(N % 10); 121| 13.8k| N /= 10; 122| 13.8k| } 123| 5.57k| return write(CurPtr, EndPtr-CurPtr); 124| 5.66k|} _ZN7llvm_ks11raw_ostreamlsEl: 126| 198|raw_ostream &raw_ostream::operator<<(long N) { 127| 198| if (N < 0) { ------------------ | Branch (127:7): [True: 0, False: 198] ------------------ 128| 0| *this << '-'; 129| | // Avoid undefined behavior on LONG_MIN with a cast. 130| 0| N = -(unsigned long)N; 131| 0| } 132| | 133| 198| return this->operator<<(static_cast(N)); 134| 198|} _ZN7llvm_ks11raw_ostream5writeEh: 278| 79.0k|raw_ostream &raw_ostream::write(unsigned char C) { 279| | // Group exceptional cases into a single branch. 280| 79.0k| if (LLVM_UNLIKELY(OutBufCur >= OutBufEnd)) { ------------------ | | 172| 79.0k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 79.0k, False: 0] | | ------------------ ------------------ 281| 79.0k| if (LLVM_UNLIKELY(!OutBufStart)) { ------------------ | | 172| 79.0k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 79.0k, False: 0] | | ------------------ ------------------ 282| 79.0k| if (BufferMode == Unbuffered) { ------------------ | Branch (282:11): [True: 79.0k, False: 0] ------------------ 283| 79.0k| write_impl(reinterpret_cast(&C), 1); 284| 79.0k| return *this; 285| 79.0k| } 286| | // Set up a buffer and start over. 287| 0| SetBuffered(); 288| 0| return write(C); 289| 79.0k| } 290| | 291| 0| flush_nonempty(); 292| 0| } 293| | 294| 0| *OutBufCur++ = C; 295| 0| return *this; 296| 79.0k|} _ZN7llvm_ks11raw_ostream5writeEPKcm: 298| 50.8k|raw_ostream &raw_ostream::write(const char *Ptr, size_t Size) { 299| | // Group exceptional cases into a single branch. 300| 50.8k| if (LLVM_UNLIKELY(size_t(OutBufEnd - OutBufCur) < Size)) { ------------------ | | 172| 50.8k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 50.8k, False: 0] | | ------------------ ------------------ 301| 50.8k| if (LLVM_UNLIKELY(!OutBufStart)) { ------------------ | | 172| 50.8k|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 50.8k, False: 0] | | ------------------ ------------------ 302| 50.8k| if (BufferMode == Unbuffered) { ------------------ | Branch (302:11): [True: 50.8k, False: 0] ------------------ 303| 50.8k| write_impl(Ptr, Size); 304| 50.8k| return *this; 305| 50.8k| } 306| | // Set up a buffer and start over. 307| 0| SetBuffered(); 308| 0| return write(Ptr, Size); 309| 50.8k| } 310| | 311| 0| size_t NumBytes = OutBufEnd - OutBufCur; 312| | 313| | // If the buffer is empty at this point we have a string that is larger 314| | // than the buffer. Directly write the chunk that is a multiple of the 315| | // preferred buffer size and put the remainder in the buffer. 316| 0| if (LLVM_UNLIKELY(OutBufCur == OutBufStart)) { ------------------ | | 172| 0|#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false) | | ------------------ | | | Branch (172:29): [True: 0, False: 0] | | ------------------ ------------------ 317| 0| assert(NumBytes != 0 && "undefined behavior"); ------------------ | Branch (317:7): [True: 0, False: 0] | Branch (317:7): [True: 0, Folded] | Branch (317:7): [True: 0, False: 0] ------------------ 318| 0| size_t BytesToWrite = Size - (Size % NumBytes); 319| 0| write_impl(Ptr, BytesToWrite); 320| 0| size_t BytesRemaining = Size - BytesToWrite; 321| 0| if (BytesRemaining > size_t(OutBufEnd - OutBufCur)) { ------------------ | Branch (321:11): [True: 0, False: 0] ------------------ 322| | // Too much left over to copy into our buffer. 323| 0| return write(Ptr + BytesToWrite, BytesRemaining); 324| 0| } 325| 0| copy_to_buffer(Ptr + BytesToWrite, BytesRemaining); 326| 0| return *this; 327| 0| } 328| | 329| | // We don't have enough space in the buffer to fit the string in. Insert as 330| | // much as possible, flush and start over with the remainder. 331| 0| copy_to_buffer(Ptr, NumBytes); 332| 0| flush_nonempty(); 333| 0| return write(Ptr + NumBytes, Size - NumBytes); 334| 0| } 335| | 336| 0| copy_to_buffer(Ptr, Size); 337| | 338| 0| return *this; 339| 50.8k|} _ZN7llvm_ks14raw_fd_ostreamC2Eibb: 517| 1| : raw_pwrite_stream(unbuffered), FD(fd), ShouldClose(shouldClose), 518| 1| Error(false) { 519| 1| if (FD < 0 ) { ------------------ | Branch (519:7): [True: 0, False: 1] ------------------ 520| 0| ShouldClose = false; 521| 0| return; 522| 0| } 523| | 524| | // Get the starting position. 525| 1| off_t loc = ::lseek(FD, 0, SEEK_CUR); 526| |#ifdef LLVM_ON_WIN32 527| | // MSVCRT's _lseek(SEEK_CUR) doesn't return -1 for pipes. 528| | sys::fs::file_status Status; 529| | std::error_code EC = status(FD, Status); 530| | SupportsSeeking = !EC && Status.type() == sys::fs::file_type::regular_file; 531| |#else 532| 1| SupportsSeeking = loc != (off_t)-1; 533| 1|#endif 534| 1| if (!SupportsSeeking) ------------------ | Branch (534:7): [True: 0, False: 1] ------------------ 535| 0| pos = 0; 536| 1| else 537| 1| pos = static_cast(loc); 538| 1|} _ZN7llvm_ks14raw_fd_ostreamD2Ev: 540| 1|raw_fd_ostream::~raw_fd_ostream() { 541| 1| if (FD >= 0) { ------------------ | Branch (541:7): [True: 1, False: 0] ------------------ 542| 1| flush(); 543| 1| } 544| | 545| |#ifdef __MINGW32__ 546| | // On mingw, global dtors should not call exit(). 547| | // report_fatal_error() invokes exit(). We know report_fatal_error() 548| | // might not write messages to stderr when any errors were detected 549| | // on FD == 2. 550| | if (FD == 2) return; 551| |#endif 552| | 553| | // If there are any pending errors, report them now. Clients wishing 554| | // to avoid report_fatal_error calls should check for errors with 555| | // has_error() and clear the error flag with clear_error() before 556| | // destructing raw_ostream objects which may have errors. 557| 1| if (has_error()) ------------------ | Branch (557:7): [True: 0, False: 1] ------------------ 558| 0| report_fatal_error("IO failure on output stream.", /*GenCrashDiag=*/false); 559| 1|} _ZN7llvm_ks14raw_fd_ostream10write_implEPKcm: 562| 76.9k|void raw_fd_ostream::write_impl(const char *Ptr, size_t Size) { 563| 76.9k| assert(FD >= 0 && "File already closed."); ------------------ | Branch (563:3): [True: 76.9k, False: 0] | Branch (563:3): [True: 76.9k, Folded] | Branch (563:3): [True: 76.9k, False: 0] ------------------ 564| 76.9k| pos += Size; 565| | 566| 76.9k|#ifndef LLVM_ON_WIN32 567| 76.9k| bool ShouldWriteInChunks = false; 568| |#else 569| | // Writing a large size of output to Windows console returns ENOMEM. It seems 570| | // that, prior to Windows 8, WriteFile() is redirecting to WriteConsole(), and 571| | // the latter has a size limit (66000 bytes or less, depending on heap usage). 572| | bool ShouldWriteInChunks = !!::_isatty(FD) && !RunningWindows8OrGreater(); 573| |#endif 574| | 575| 76.9k| do { 576| 76.9k| size_t ChunkSize = Size; 577| 76.9k| if (ChunkSize > 32767 && ShouldWriteInChunks) ------------------ | Branch (577:9): [True: 0, False: 76.9k] | Branch (577:30): [True: 0, False: 0] ------------------ 578| 0| ChunkSize = 32767; 579| | 580| 76.9k| ssize_t ret = ::write(FD, Ptr, ChunkSize); 581| | 582| 76.9k| if (ret < 0) { ------------------ | Branch (582:9): [True: 0, False: 76.9k] ------------------ 583| | // If it's a recoverable error, swallow it and retry the write. 584| | // 585| | // Ideally we wouldn't ever see EAGAIN or EWOULDBLOCK here, since 586| | // raw_ostream isn't designed to do non-blocking I/O. However, some 587| | // programs, such as old versions of bjam, have mistakenly used 588| | // O_NONBLOCK. For compatibility, emulate blocking semantics by 589| | // spinning until the write succeeds. If you don't want spinning, 590| | // don't use O_NONBLOCK file descriptors with raw_ostream. 591| 0| if (errno == EINTR || errno == EAGAIN ------------------ | Branch (591:11): [True: 0, False: 0] | Branch (591:29): [True: 0, False: 0] ------------------ 592| 0|#ifdef EWOULDBLOCK 593| 0| || errno == EWOULDBLOCK ------------------ | Branch (593:14): [True: 0, False: 0] ------------------ 594| 0|#endif 595| 0| ) 596| 0| continue; 597| | 598| | // Otherwise it's a non-recoverable error. Note it and quit. 599| 0| error_detected(); 600| 0| break; 601| 0| } 602| | 603| | // The write may have written some or all of the data. Update the 604| | // size and buffer pointer to reflect the remainder that needs 605| | // to be written. If there are no bytes left, we're done. 606| 76.9k| Ptr += ret; 607| 76.9k| Size -= ret; 608| 76.9k| } while (Size > 0); ------------------ | Branch (608:12): [True: 0, False: 76.9k] ------------------ 609| 76.9k|} _ZN7llvm_ks14raw_fd_ostream11changeColorENS_11raw_ostream6ColorsEbb: 655| 8.02k| bool bg) { 656| 8.02k| return *this; 657| 8.02k|} _ZN7llvm_ks14raw_fd_ostream10resetColorEv: 659| 5.85k|raw_ostream &raw_fd_ostream::resetColor() { 660| 5.85k| return *this; 661| 5.85k|} _ZNK7llvm_ks14raw_fd_ostream10has_colorsEv: 671| 2.17k|bool raw_fd_ostream::has_colors() const { 672| 2.17k| return true; 673| 2.17k|} _ZN7llvm_ks4errsEv: 693| 4.34k|raw_ostream &llvm_ks::errs() { 694| | // Set standard error to be unbuffered by default. 695| | static raw_fd_ostream S(STDERR_FILENO, false, true); 696| 4.34k| return S; 697| 4.34k|} _ZNK7llvm_ks19raw_svector_ostream11current_posEv: 722| 3.95k|uint64_t raw_svector_ostream::current_pos() const { return OS.size(); } _ZN7llvm_ks19raw_svector_ostream10write_implEPKcm: 724| 53.0k|void raw_svector_ostream::write_impl(const char *Ptr, size_t Size) { 725| 53.0k| OS.append(Ptr, Ptr + Size); 726| 53.0k|} LLVMInitializeAArch64AsmParser: 4658| 1|extern "C" void LLVMInitializeAArch64AsmParser() { 4659| 1| RegisterMCAsmParser X(TheAArch64leTarget); 4660| 1| RegisterMCAsmParser Y(TheAArch64beTarget); 4661| 1| RegisterMCAsmParser Z(TheARM64Target); 4662| 1|} LLVMInitializeAArch64TargetMC: 75| 1|extern "C" void LLVMInitializeAArch64TargetMC() { 76| 1| for (Target *T : ------------------ | Branch (76:18): [True: 3, False: 1] ------------------ 77| 3| {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) { 78| | // Register the MC asm info. 79| 3| RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); 80| | 81| | // Register the MC instruction info. 82| 3| TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); 83| | 84| | // Register the MC register info. 85| 3| TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo); 86| | 87| | // Register the MC subtarget info. 88| 3| TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo); 89| | 90| | // Register the MC Code Emitter 91| 3| TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter); 92| 3| } 93| | 94| | // Register the asm backend. 95| 1| for (Target *T : {&TheAArch64leTarget, &TheARM64Target}) ------------------ | Branch (95:18): [True: 2, False: 1] ------------------ 96| 2| TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); 97| 1| TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget, 98| 1| createAArch64beAsmBackend); 99| 1|} LLVMInitializeAArch64TargetInfo: 20| 1|extern "C" void LLVMInitializeAArch64TargetInfo() { 21| | // Now register the "arm64" name for use with "-march". We don't want it to 22| | // take possession of the Triple::aarch64 tag though. 23| 1| TargetRegistry::RegisterTarget(TheARM64Target, "arm64", 24| 1| "ARM64 (little endian)", 25| 1| [](Triple::ArchType) { return false; }); 26| | 27| 1| RegisterTarget Z( 28| 1| TheAArch64leTarget, "aarch64", "AArch64 (little endian)"); 29| 1| RegisterTarget W( 30| 1| TheAArch64beTarget, "aarch64_be", "AArch64 (big endian)"); 31| | 32| 1|} AArch64TargetInfo.cpp:_ZZ31LLVMInitializeAArch64TargetInfoENK3$_0clEN7llvm_ks6Triple8ArchTypeE: 25| 430| [](Triple::ArchType) { return false; }); ARMAsmParser.cpp:_ZNK12_GLOBAL__N_112ARMAsmParser24ComputeAvailableFeaturesERKN7llvm_ks13FeatureBitsetE: 6536| 3.10k|ComputeAvailableFeatures(const FeatureBitset& FB) const { 6537| 3.10k| uint64_t Features = 0; 6538| 3.10k| if ((FB[ARM::HasV4TOps])) ------------------ | Branch (6538:7): [True: 3.04k, False: 53] ------------------ 6539| 3.04k| Features |= Feature_HasV4T; 6540| 3.10k| if ((FB[ARM::HasV5TOps])) ------------------ | Branch (6540:7): [True: 3.03k, False: 66] ------------------ 6541| 3.03k| Features |= Feature_HasV5T; 6542| 3.10k| if ((FB[ARM::HasV5TEOps])) ------------------ | Branch (6542:7): [True: 3.03k, False: 66] ------------------ 6543| 3.03k| Features |= Feature_HasV5TE; 6544| 3.10k| if ((FB[ARM::HasV6Ops])) ------------------ | Branch (6544:7): [True: 840, False: 2.26k] ------------------ 6545| 840| Features |= Feature_HasV6; 6546| 3.10k| if ((FB[ARM::HasV6MOps])) ------------------ | Branch (6546:7): [True: 834, False: 2.26k] ------------------ 6547| 834| Features |= Feature_HasV6M; 6548| 3.10k| if ((FB[ARM::HasV8MBaselineOps])) ------------------ | Branch (6548:7): [True: 817, False: 2.28k] ------------------ 6549| 817| Features |= Feature_HasV8MBaseline; 6550| 3.10k| if ((FB[ARM::HasV8MMainlineOps])) ------------------ | Branch (6550:7): [True: 0, False: 3.10k] ------------------ 6551| 0| Features |= Feature_HasV8MMainline; 6552| 3.10k| if ((FB[ARM::HasV6T2Ops])) ------------------ | Branch (6552:7): [True: 817, False: 2.28k] ------------------ 6553| 817| Features |= Feature_HasV6T2; 6554| 3.10k| if ((FB[ARM::HasV6KOps])) ------------------ | Branch (6554:7): [True: 817, False: 2.28k] ------------------ 6555| 817| Features |= Feature_HasV6K; 6556| 3.10k| if ((FB[ARM::HasV7Ops])) ------------------ | Branch (6556:7): [True: 817, False: 2.28k] ------------------ 6557| 817| Features |= Feature_HasV7; 6558| 3.10k| if ((FB[ARM::HasV8Ops])) ------------------ | Branch (6558:7): [True: 788, False: 2.31k] ------------------ 6559| 788| Features |= Feature_HasV8; 6560| 3.10k| if ((!FB[ARM::HasV8Ops])) ------------------ | Branch (6560:7): [True: 2.31k, False: 788] ------------------ 6561| 2.31k| Features |= Feature_PreV8; 6562| 3.10k| if ((FB[ARM::HasV8_1aOps])) ------------------ | Branch (6562:7): [True: 0, False: 3.10k] ------------------ 6563| 0| Features |= Feature_HasV8_1a; 6564| 3.10k| if ((FB[ARM::HasV8_2aOps])) ------------------ | Branch (6564:7): [True: 0, False: 3.10k] ------------------ 6565| 0| Features |= Feature_HasV8_2a; 6566| 3.10k| if ((FB[ARM::FeatureVFP2])) ------------------ | Branch (6566:7): [True: 782, False: 2.31k] ------------------ 6567| 782| Features |= Feature_HasVFP2; 6568| 3.10k| if ((FB[ARM::FeatureVFP3])) ------------------ | Branch (6568:7): [True: 760, False: 2.34k] ------------------ 6569| 760| Features |= Feature_HasVFP3; 6570| 3.10k| if ((FB[ARM::FeatureVFP4])) ------------------ | Branch (6570:7): [True: 734, False: 2.36k] ------------------ 6571| 734| Features |= Feature_HasVFP4; 6572| 3.10k| if ((!FB[ARM::FeatureVFPOnlySP])) ------------------ | Branch (6572:7): [True: 3.08k, False: 11] ------------------ 6573| 3.08k| Features |= Feature_HasDPVFP; 6574| 3.10k| if ((FB[ARM::FeatureFPARMv8])) ------------------ | Branch (6574:7): [True: 729, False: 2.37k] ------------------ 6575| 729| Features |= Feature_HasFPARMv8; 6576| 3.10k| if ((FB[ARM::FeatureNEON])) ------------------ | Branch (6576:7): [True: 749, False: 2.35k] ------------------ 6577| 749| Features |= Feature_HasNEON; 6578| 3.10k| if ((FB[ARM::FeatureCrypto])) ------------------ | Branch (6578:7): [True: 723, False: 2.37k] ------------------ 6579| 723| Features |= Feature_HasCrypto; 6580| 3.10k| if ((FB[ARM::FeatureCRC])) ------------------ | Branch (6580:7): [True: 788, False: 2.31k] ------------------ 6581| 788| Features |= Feature_HasCRC; 6582| 3.10k| if ((FB[ARM::FeatureFP16])) ------------------ | Branch (6582:7): [True: 734, False: 2.36k] ------------------ 6583| 734| Features |= Feature_HasFP16; 6584| 3.10k| if ((FB[ARM::FeatureFullFP16])) ------------------ | Branch (6584:7): [True: 0, False: 3.10k] ------------------ 6585| 0| Features |= Feature_HasFullFP16; 6586| 3.10k| if ((FB[ARM::FeatureHWDiv])) ------------------ | Branch (6586:7): [True: 791, False: 2.30k] ------------------ 6587| 791| Features |= Feature_HasDivide; 6588| 3.10k| if ((FB[ARM::FeatureHWDivARM])) ------------------ | Branch (6588:7): [True: 788, False: 2.31k] ------------------ 6589| 788| Features |= Feature_HasDivideInARM; 6590| 3.10k| if ((FB[ARM::FeatureT2XtPk])) ------------------ | Branch (6590:7): [True: 26, False: 3.07k] ------------------ 6591| 26| Features |= Feature_HasT2ExtractPack; 6592| 3.10k| if ((FB[ARM::FeatureDSP])) ------------------ | Branch (6592:7): [True: 817, False: 2.28k] ------------------ 6593| 817| Features |= Feature_HasDSP; 6594| 3.10k| if ((FB[ARM::FeatureDB])) ------------------ | Branch (6594:7): [True: 834, False: 2.26k] ------------------ 6595| 834| Features |= Feature_HasDB; 6596| 3.10k| if ((FB[ARM::FeatureV7Clrex])) ------------------ | Branch (6596:7): [True: 817, False: 2.28k] ------------------ 6597| 817| Features |= Feature_HasV7Clrex; 6598| 3.10k| if ((FB[ARM::FeatureAcquireRelease])) ------------------ | Branch (6598:7): [True: 788, False: 2.31k] ------------------ 6599| 788| Features |= Feature_HasAcquireRelease; 6600| 3.10k| if ((FB[ARM::FeatureMP])) ------------------ | Branch (6600:7): [True: 788, False: 2.31k] ------------------ 6601| 788| Features |= Feature_HasMP; 6602| 3.10k| if ((FB[ARM::FeatureVirtualization])) ------------------ | Branch (6602:7): [True: 788, False: 2.31k] ------------------ 6603| 788| Features |= Feature_HasVirtualization; 6604| 3.10k| if ((FB[ARM::FeatureTrustZone])) ------------------ | Branch (6604:7): [True: 788, False: 2.31k] ------------------ 6605| 788| Features |= Feature_HasTrustZone; 6606| 3.10k| if ((FB[ARM::Feature8MSecExt])) ------------------ | Branch (6606:7): [True: 0, False: 3.10k] ------------------ 6607| 0| Features |= Feature_Has8MSecExt; 6608| 3.10k| if ((FB[ARM::ModeThumb])) ------------------ | Branch (6608:7): [True: 749, False: 2.35k] ------------------ 6609| 749| Features |= Feature_IsThumb; 6610| 3.10k| if ((FB[ARM::ModeThumb]) && (FB[ARM::FeatureThumb2])) ------------------ | Branch (6610:7): [True: 749, False: 2.35k] | Branch (6610:7): [True: 728, False: 2.37k] | Branch (6610:31): [True: 728, False: 21] ------------------ 6611| 728| Features |= Feature_IsThumb2; 6612| 3.10k| if ((FB[ARM::FeatureMClass])) ------------------ | Branch (6612:7): [True: 18, False: 3.08k] ------------------ 6613| 18| Features |= Feature_IsMClass; 6614| 3.10k| if ((!FB[ARM::FeatureMClass])) ------------------ | Branch (6614:7): [True: 3.08k, False: 18] ------------------ 6615| 3.08k| Features |= Feature_IsNotMClass; 6616| 3.10k| if ((!FB[ARM::ModeThumb])) ------------------ | Branch (6616:7): [True: 2.35k, False: 749] ------------------ 6617| 2.35k| Features |= Feature_IsARM; 6618| 3.10k| if ((FB[ARM::FeatureNaClTrap])) ------------------ | Branch (6618:7): [True: 0, False: 3.10k] ------------------ 6619| 0| Features |= Feature_UseNaClTrap; 6620| 3.10k| return Features; 6621| 3.10k|} ARMAsmParser.cpp:_ZL17MatchRegisterNameN7llvm_ks9StringRefE: 108| 16.5k|static unsigned MatchRegisterName(StringRef Name) { 109| 16.5k| switch (Name.size()) { 110| 5.21k| default: break; ------------------ | Branch (110:3): [True: 5.21k, False: 11.3k] ------------------ 111| 7.09k| case 2: // 43 strings to match. ------------------ | Branch (111:3): [True: 7.09k, False: 9.47k] ------------------ 112| 7.09k| switch (Name[0]) { 113| 4.77k| default: break; ------------------ | Branch (113:5): [True: 4.77k, False: 2.32k] ------------------ 114| 4.77k| case 'd': // 10 strings to match. ------------------ | Branch (114:5): [True: 11, False: 7.08k] ------------------ 115| 11| switch (Name[1]) { 116| 4| default: break; ------------------ | Branch (116:7): [True: 4, False: 7] ------------------ 117| 4| case '0': // 1 string to match. ------------------ | Branch (117:7): [True: 1, False: 10] ------------------ 118| 1| return 14; // "d0" 119| 0| case '1': // 1 string to match. ------------------ | Branch (119:7): [True: 0, False: 11] ------------------ 120| 0| return 15; // "d1" 121| 0| case '2': // 1 string to match. ------------------ | Branch (121:7): [True: 0, False: 11] ------------------ 122| 0| return 16; // "d2" 123| 0| case '3': // 1 string to match. ------------------ | Branch (123:7): [True: 0, False: 11] ------------------ 124| 0| return 17; // "d3" 125| 0| case '4': // 1 string to match. ------------------ | Branch (125:7): [True: 0, False: 11] ------------------ 126| 0| return 18; // "d4" 127| 0| case '5': // 1 string to match. ------------------ | Branch (127:7): [True: 0, False: 11] ------------------ 128| 0| return 19; // "d5" 129| 0| case '6': // 1 string to match. ------------------ | Branch (129:7): [True: 0, False: 11] ------------------ 130| 0| return 20; // "d6" 131| 0| case '7': // 1 string to match. ------------------ | Branch (131:7): [True: 0, False: 11] ------------------ 132| 0| return 21; // "d7" 133| 6| case '8': // 1 string to match. ------------------ | Branch (133:7): [True: 6, False: 5] ------------------ 134| 6| return 22; // "d8" 135| 0| case '9': // 1 string to match. ------------------ | Branch (135:7): [True: 0, False: 11] ------------------ 136| 0| return 23; // "d9" 137| 11| } 138| 4| break; 139| 11| case 'l': // 1 string to match. ------------------ | Branch (139:5): [True: 11, False: 7.08k] ------------------ 140| 11| if (Name[1] != 'r') ------------------ | Branch (140:11): [True: 9, False: 2] ------------------ 141| 9| break; 142| 2| return 10; // "lr" 143| 4| case 'p': // 1 string to match. ------------------ | Branch (143:5): [True: 4, False: 7.09k] ------------------ 144| 4| if (Name[1] != 'c') ------------------ | Branch (144:11): [True: 4, False: 0] ------------------ 145| 4| break; 146| 0| return 11; // "pc" 147| 594| case 'q': // 10 strings to match. ------------------ | Branch (147:5): [True: 594, False: 6.50k] ------------------ 148| 594| switch (Name[1]) { 149| 594| default: break; ------------------ | Branch (149:7): [True: 594, False: 0] ------------------ 150| 594| case '0': // 1 string to match. ------------------ | Branch (150:7): [True: 0, False: 594] ------------------ 151| 0| return 50; // "q0" 152| 0| case '1': // 1 string to match. ------------------ | Branch (152:7): [True: 0, False: 594] ------------------ 153| 0| return 51; // "q1" 154| 0| case '2': // 1 string to match. ------------------ | Branch (154:7): [True: 0, False: 594] ------------------ 155| 0| return 52; // "q2" 156| 0| case '3': // 1 string to match. ------------------ | Branch (156:7): [True: 0, False: 594] ------------------ 157| 0| return 53; // "q3" 158| 0| case '4': // 1 string to match. ------------------ | Branch (158:7): [True: 0, False: 594] ------------------ 159| 0| return 54; // "q4" 160| 0| case '5': // 1 string to match. ------------------ | Branch (160:7): [True: 0, False: 594] ------------------ 161| 0| return 55; // "q5" 162| 0| case '6': // 1 string to match. ------------------ | Branch (162:7): [True: 0, False: 594] ------------------ 163| 0| return 56; // "q6" 164| 0| case '7': // 1 string to match. ------------------ | Branch (164:7): [True: 0, False: 594] ------------------ 165| 0| return 57; // "q7" 166| 0| case '8': // 1 string to match. ------------------ | Branch (166:7): [True: 0, False: 594] ------------------ 167| 0| return 58; // "q8" 168| 0| case '9': // 1 string to match. ------------------ | Branch (168:7): [True: 0, False: 594] ------------------ 169| 0| return 59; // "q9" 170| 594| } 171| 594| break; 172| 1.47k| case 'r': // 10 strings to match. ------------------ | Branch (172:5): [True: 1.47k, False: 5.62k] ------------------ 173| 1.47k| switch (Name[1]) { 174| 308| default: break; ------------------ | Branch (174:7): [True: 308, False: 1.16k] ------------------ 175| 308| case '0': // 1 string to match. ------------------ | Branch (175:7): [True: 108, False: 1.36k] ------------------ 176| 108| return 66; // "r0" 177| 88| case '1': // 1 string to match. ------------------ | Branch (177:7): [True: 88, False: 1.38k] ------------------ 178| 88| return 67; // "r1" 179| 4| case '2': // 1 string to match. ------------------ | Branch (179:7): [True: 4, False: 1.46k] ------------------ 180| 4| return 68; // "r2" 181| 68| case '3': // 1 string to match. ------------------ | Branch (181:7): [True: 68, False: 1.40k] ------------------ 182| 68| return 69; // "r3" 183| 50| case '4': // 1 string to match. ------------------ | Branch (183:7): [True: 50, False: 1.42k] ------------------ 184| 50| return 70; // "r4" 185| 124| case '5': // 1 string to match. ------------------ | Branch (185:7): [True: 124, False: 1.34k] ------------------ 186| 124| return 71; // "r5" 187| 596| case '6': // 1 string to match. ------------------ | Branch (187:7): [True: 596, False: 877] ------------------ 188| 596| return 72; // "r6" 189| 27| case '7': // 1 string to match. ------------------ | Branch (189:7): [True: 27, False: 1.44k] ------------------ 190| 27| return 73; // "r7" 191| 100| case '8': // 1 string to match. ------------------ | Branch (191:7): [True: 100, False: 1.37k] ------------------ 192| 100| return 74; // "r8" 193| 0| case '9': // 1 string to match. ------------------ | Branch (193:7): [True: 0, False: 1.47k] ------------------ 194| 0| return 75; // "r9" 195| 1.47k| } 196| 308| break; 197| 308| case 's': // 11 strings to match. ------------------ | Branch (197:5): [True: 228, False: 6.86k] ------------------ 198| 228| switch (Name[1]) { 199| 88| default: break; ------------------ | Branch (199:7): [True: 88, False: 140] ------------------ 200| 88| case '0': // 1 string to match. ------------------ | Branch (200:7): [True: 5, False: 223] ------------------ 201| 5| return 79; // "s0" 202| 8| case '1': // 1 string to match. ------------------ | Branch (202:7): [True: 8, False: 220] ------------------ 203| 8| return 80; // "s1" 204| 1| case '2': // 1 string to match. ------------------ | Branch (204:7): [True: 1, False: 227] ------------------ 205| 1| return 81; // "s2" 206| 0| case '3': // 1 string to match. ------------------ | Branch (206:7): [True: 0, False: 228] ------------------ 207| 0| return 82; // "s3" 208| 6| case '4': // 1 string to match. ------------------ | Branch (208:7): [True: 6, False: 222] ------------------ 209| 6| return 83; // "s4" 210| 0| case '5': // 1 string to match. ------------------ | Branch (210:7): [True: 0, False: 228] ------------------ 211| 0| return 84; // "s5" 212| 19| case '6': // 1 string to match. ------------------ | Branch (212:7): [True: 19, False: 209] ------------------ 213| 19| return 85; // "s6" 214| 29| case '7': // 1 string to match. ------------------ | Branch (214:7): [True: 29, False: 199] ------------------ 215| 29| return 86; // "s7" 216| 0| case '8': // 1 string to match. ------------------ | Branch (216:7): [True: 0, False: 228] ------------------ 217| 0| return 87; // "s8" 218| 0| case '9': // 1 string to match. ------------------ | Branch (218:7): [True: 0, False: 228] ------------------ 219| 0| return 88; // "s9" 220| 72| case 'p': // 1 string to match. ------------------ | Branch (220:7): [True: 72, False: 156] ------------------ 221| 72| return 12; // "sp" 222| 228| } 223| 88| break; 224| 7.09k| } 225| 5.78k| break; 226| 5.78k| case 3: // 53 strings to match. ------------------ | Branch (226:3): [True: 1.94k, False: 14.6k] ------------------ 227| 1.94k| switch (Name[0]) { 228| 1.00k| default: break; ------------------ | Branch (228:5): [True: 1.00k, False: 943] ------------------ 229| 1.00k| case 'd': // 22 strings to match. ------------------ | Branch (229:5): [True: 33, False: 1.91k] ------------------ 230| 33| switch (Name[1]) { 231| 33| default: break; ------------------ | Branch (231:7): [True: 33, False: 0] ------------------ 232| 33| case '1': // 10 strings to match. ------------------ | Branch (232:7): [True: 0, False: 33] ------------------ 233| 0| switch (Name[2]) { 234| 0| default: break; ------------------ | Branch (234:9): [True: 0, False: 0] ------------------ 235| 0| case '0': // 1 string to match. ------------------ | Branch (235:9): [True: 0, False: 0] ------------------ 236| 0| return 24; // "d10" 237| 0| case '1': // 1 string to match. ------------------ | Branch (237:9): [True: 0, False: 0] ------------------ 238| 0| return 25; // "d11" 239| 0| case '2': // 1 string to match. ------------------ | Branch (239:9): [True: 0, False: 0] ------------------ 240| 0| return 26; // "d12" 241| 0| case '3': // 1 string to match. ------------------ | Branch (241:9): [True: 0, False: 0] ------------------ 242| 0| return 27; // "d13" 243| 0| case '4': // 1 string to match. ------------------ | Branch (243:9): [True: 0, False: 0] ------------------ 244| 0| return 28; // "d14" 245| 0| case '5': // 1 string to match. ------------------ | Branch (245:9): [True: 0, False: 0] ------------------ 246| 0| return 29; // "d15" 247| 0| case '6': // 1 string to match. ------------------ | Branch (247:9): [True: 0, False: 0] ------------------ 248| 0| return 30; // "d16" 249| 0| case '7': // 1 string to match. ------------------ | Branch (249:9): [True: 0, False: 0] ------------------ 250| 0| return 31; // "d17" 251| 0| case '8': // 1 string to match. ------------------ | Branch (251:9): [True: 0, False: 0] ------------------ 252| 0| return 32; // "d18" 253| 0| case '9': // 1 string to match. ------------------ | Branch (253:9): [True: 0, False: 0] ------------------ 254| 0| return 33; // "d19" 255| 0| } 256| 0| break; 257| 0| case '2': // 10 strings to match. ------------------ | Branch (257:7): [True: 0, False: 33] ------------------ 258| 0| switch (Name[2]) { 259| 0| default: break; ------------------ | Branch (259:9): [True: 0, False: 0] ------------------ 260| 0| case '0': // 1 string to match. ------------------ | Branch (260:9): [True: 0, False: 0] ------------------ 261| 0| return 34; // "d20" 262| 0| case '1': // 1 string to match. ------------------ | Branch (262:9): [True: 0, False: 0] ------------------ 263| 0| return 35; // "d21" 264| 0| case '2': // 1 string to match. ------------------ | Branch (264:9): [True: 0, False: 0] ------------------ 265| 0| return 36; // "d22" 266| 0| case '3': // 1 string to match. ------------------ | Branch (266:9): [True: 0, False: 0] ------------------ 267| 0| return 37; // "d23" 268| 0| case '4': // 1 string to match. ------------------ | Branch (268:9): [True: 0, False: 0] ------------------ 269| 0| return 38; // "d24" 270| 0| case '5': // 1 string to match. ------------------ | Branch (270:9): [True: 0, False: 0] ------------------ 271| 0| return 39; // "d25" 272| 0| case '6': // 1 string to match. ------------------ | Branch (272:9): [True: 0, False: 0] ------------------ 273| 0| return 40; // "d26" 274| 0| case '7': // 1 string to match. ------------------ | Branch (274:9): [True: 0, False: 0] ------------------ 275| 0| return 41; // "d27" 276| 0| case '8': // 1 string to match. ------------------ | Branch (276:9): [True: 0, False: 0] ------------------ 277| 0| return 42; // "d28" 278| 0| case '9': // 1 string to match. ------------------ | Branch (278:9): [True: 0, False: 0] ------------------ 279| 0| return 43; // "d29" 280| 0| } 281| 0| break; 282| 0| case '3': // 2 strings to match. ------------------ | Branch (282:7): [True: 0, False: 33] ------------------ 283| 0| switch (Name[2]) { 284| 0| default: break; ------------------ | Branch (284:9): [True: 0, False: 0] ------------------ 285| 0| case '0': // 1 string to match. ------------------ | Branch (285:9): [True: 0, False: 0] ------------------ 286| 0| return 44; // "d30" 287| 0| case '1': // 1 string to match. ------------------ | Branch (287:9): [True: 0, False: 0] ------------------ 288| 0| return 45; // "d31" 289| 0| } 290| 0| break; 291| 33| } 292| 33| break; 293| 46| case 'q': // 6 strings to match. ------------------ | Branch (293:5): [True: 46, False: 1.89k] ------------------ 294| 46| if (Name[1] != '1') ------------------ | Branch (294:11): [True: 46, False: 0] ------------------ 295| 46| break; 296| 0| switch (Name[2]) { 297| 0| default: break; ------------------ | Branch (297:7): [True: 0, False: 0] ------------------ 298| 0| case '0': // 1 string to match. ------------------ | Branch (298:7): [True: 0, False: 0] ------------------ 299| 0| return 60; // "q10" 300| 0| case '1': // 1 string to match. ------------------ | Branch (300:7): [True: 0, False: 0] ------------------ 301| 0| return 61; // "q11" 302| 0| case '2': // 1 string to match. ------------------ | Branch (302:7): [True: 0, False: 0] ------------------ 303| 0| return 62; // "q12" 304| 0| case '3': // 1 string to match. ------------------ | Branch (304:7): [True: 0, False: 0] ------------------ 305| 0| return 63; // "q13" 306| 0| case '4': // 1 string to match. ------------------ | Branch (306:7): [True: 0, False: 0] ------------------ 307| 0| return 64; // "q14" 308| 0| case '5': // 1 string to match. ------------------ | Branch (308:7): [True: 0, False: 0] ------------------ 309| 0| return 65; // "q15" 310| 0| } 311| 0| break; 312| 310| case 'r': // 3 strings to match. ------------------ | Branch (312:5): [True: 310, False: 1.63k] ------------------ 313| 310| if (Name[1] != '1') ------------------ | Branch (313:11): [True: 85, False: 225] ------------------ 314| 85| break; 315| 225| switch (Name[2]) { 316| 222| default: break; ------------------ | Branch (316:7): [True: 222, False: 3] ------------------ 317| 222| case '0': // 1 string to match. ------------------ | Branch (317:7): [True: 0, False: 225] ------------------ 318| 0| return 76; // "r10" 319| 0| case '1': // 1 string to match. ------------------ | Branch (319:7): [True: 0, False: 225] ------------------ 320| 0| return 77; // "r11" 321| 3| case '2': // 1 string to match. ------------------ | Branch (321:7): [True: 3, False: 222] ------------------ 322| 3| return 78; // "r12" 323| 225| } 324| 222| break; 325| 554| case 's': // 22 strings to match. ------------------ | Branch (325:5): [True: 554, False: 1.38k] ------------------ 326| 554| switch (Name[1]) { 327| 553| default: break; ------------------ | Branch (327:7): [True: 553, False: 1] ------------------ 328| 553| case '1': // 10 strings to match. ------------------ | Branch (328:7): [True: 0, False: 554] ------------------ 329| 0| switch (Name[2]) { 330| 0| default: break; ------------------ | Branch (330:9): [True: 0, False: 0] ------------------ 331| 0| case '0': // 1 string to match. ------------------ | Branch (331:9): [True: 0, False: 0] ------------------ 332| 0| return 89; // "s10" 333| 0| case '1': // 1 string to match. ------------------ | Branch (333:9): [True: 0, False: 0] ------------------ 334| 0| return 90; // "s11" 335| 0| case '2': // 1 string to match. ------------------ | Branch (335:9): [True: 0, False: 0] ------------------ 336| 0| return 91; // "s12" 337| 0| case '3': // 1 string to match. ------------------ | Branch (337:9): [True: 0, False: 0] ------------------ 338| 0| return 92; // "s13" 339| 0| case '4': // 1 string to match. ------------------ | Branch (339:9): [True: 0, False: 0] ------------------ 340| 0| return 93; // "s14" 341| 0| case '5': // 1 string to match. ------------------ | Branch (341:9): [True: 0, False: 0] ------------------ 342| 0| return 94; // "s15" 343| 0| case '6': // 1 string to match. ------------------ | Branch (343:9): [True: 0, False: 0] ------------------ 344| 0| return 95; // "s16" 345| 0| case '7': // 1 string to match. ------------------ | Branch (345:9): [True: 0, False: 0] ------------------ 346| 0| return 96; // "s17" 347| 0| case '8': // 1 string to match. ------------------ | Branch (347:9): [True: 0, False: 0] ------------------ 348| 0| return 97; // "s18" 349| 0| case '9': // 1 string to match. ------------------ | Branch (349:9): [True: 0, False: 0] ------------------ 350| 0| return 98; // "s19" 351| 0| } 352| 0| break; 353| 1| case '2': // 10 strings to match. ------------------ | Branch (353:7): [True: 1, False: 553] ------------------ 354| 1| switch (Name[2]) { 355| 1| default: break; ------------------ | Branch (355:9): [True: 1, False: 0] ------------------ 356| 1| case '0': // 1 string to match. ------------------ | Branch (356:9): [True: 0, False: 1] ------------------ 357| 0| return 99; // "s20" 358| 0| case '1': // 1 string to match. ------------------ | Branch (358:9): [True: 0, False: 1] ------------------ 359| 0| return 100; // "s21" 360| 0| case '2': // 1 string to match. ------------------ | Branch (360:9): [True: 0, False: 1] ------------------ 361| 0| return 101; // "s22" 362| 0| case '3': // 1 string to match. ------------------ | Branch (362:9): [True: 0, False: 1] ------------------ 363| 0| return 102; // "s23" 364| 0| case '4': // 1 string to match. ------------------ | Branch (364:9): [True: 0, False: 1] ------------------ 365| 0| return 103; // "s24" 366| 0| case '5': // 1 string to match. ------------------ | Branch (366:9): [True: 0, False: 1] ------------------ 367| 0| return 104; // "s25" 368| 0| case '6': // 1 string to match. ------------------ | Branch (368:9): [True: 0, False: 1] ------------------ 369| 0| return 105; // "s26" 370| 0| case '7': // 1 string to match. ------------------ | Branch (370:9): [True: 0, False: 1] ------------------ 371| 0| return 106; // "s27" 372| 0| case '8': // 1 string to match. ------------------ | Branch (372:9): [True: 0, False: 1] ------------------ 373| 0| return 107; // "s28" 374| 0| case '9': // 1 string to match. ------------------ | Branch (374:9): [True: 0, False: 1] ------------------ 375| 0| return 108; // "s29" 376| 1| } 377| 1| break; 378| 1| case '3': // 2 strings to match. ------------------ | Branch (378:7): [True: 0, False: 554] ------------------ 379| 0| switch (Name[2]) { 380| 0| default: break; ------------------ | Branch (380:9): [True: 0, False: 0] ------------------ 381| 0| case '0': // 1 string to match. ------------------ | Branch (381:9): [True: 0, False: 0] ------------------ 382| 0| return 109; // "s30" 383| 0| case '1': // 1 string to match. ------------------ | Branch (383:9): [True: 0, False: 0] ------------------ 384| 0| return 110; // "s31" 385| 0| } 386| 0| break; 387| 554| } 388| 554| break; 389| 1.94k| } 390| 1.94k| break; 391| 1.94k| case 4: // 3 strings to match. ------------------ | Branch (391:3): [True: 1.48k, False: 15.0k] ------------------ 392| 1.48k| switch (Name[0]) { 393| 1.42k| default: break; ------------------ | Branch (393:5): [True: 1.42k, False: 58] ------------------ 394| 1.42k| case 'a': // 1 string to match. ------------------ | Branch (394:5): [True: 11, False: 1.46k] ------------------ 395| 11| if (memcmp(Name.data()+1, "psr", 3)) ------------------ | Branch (395:11): [True: 11, False: 0] ------------------ 396| 11| break; 397| 0| return 1; // "apsr" 398| 0| case 'c': // 1 string to match. ------------------ | Branch (398:5): [True: 0, False: 1.48k] ------------------ 399| 0| if (memcmp(Name.data()+1, "psr", 3)) ------------------ | Branch (399:11): [True: 0, False: 0] ------------------ 400| 0| break; 401| 0| return 3; // "cpsr" 402| 47| case 's': // 1 string to match. ------------------ | Branch (402:5): [True: 47, False: 1.43k] ------------------ 403| 47| if (memcmp(Name.data()+1, "psr", 3)) ------------------ | Branch (403:11): [True: 47, False: 0] ------------------ 404| 47| break; 405| 0| return 13; // "spsr" 406| 1.48k| } 407| 1.48k| break; 408| 1.48k| case 5: // 6 strings to match. ------------------ | Branch (408:3): [True: 475, False: 16.0k] ------------------ 409| 475| switch (Name[0]) { 410| 466| default: break; ------------------ | Branch (410:5): [True: 466, False: 9] ------------------ 411| 466| case 'f': // 3 strings to match. ------------------ | Branch (411:5): [True: 9, False: 466] ------------------ 412| 9| if (Name[1] != 'p') ------------------ | Branch (412:11): [True: 9, False: 0] ------------------ 413| 9| break; 414| 0| switch (Name[2]) { 415| 0| default: break; ------------------ | Branch (415:7): [True: 0, False: 0] ------------------ 416| 0| case 'e': // 1 string to match. ------------------ | Branch (416:7): [True: 0, False: 0] ------------------ 417| 0| if (memcmp(Name.data()+3, "xc", 2)) ------------------ | Branch (417:13): [True: 0, False: 0] ------------------ 418| 0| break; 419| 0| return 4; // "fpexc" 420| 0| case 's': // 2 strings to match. ------------------ | Branch (420:7): [True: 0, False: 0] ------------------ 421| 0| switch (Name[3]) { 422| 0| default: break; ------------------ | Branch (422:9): [True: 0, False: 0] ------------------ 423| 0| case 'c': // 1 string to match. ------------------ | Branch (423:9): [True: 0, False: 0] ------------------ 424| 0| if (Name[4] != 'r') ------------------ | Branch (424:15): [True: 0, False: 0] ------------------ 425| 0| break; 426| 0| return 6; // "fpscr" 427| 0| case 'i': // 1 string to match. ------------------ | Branch (427:9): [True: 0, False: 0] ------------------ 428| 0| if (Name[4] != 'd') ------------------ | Branch (428:15): [True: 0, False: 0] ------------------ 429| 0| break; 430| 0| return 8; // "fpsid" 431| 0| } 432| 0| break; 433| 0| } 434| 0| break; 435| 0| case 'm': // 3 strings to match. ------------------ | Branch (435:5): [True: 0, False: 475] ------------------ 436| 0| if (memcmp(Name.data()+1, "vfr", 3)) ------------------ | Branch (436:11): [True: 0, False: 0] ------------------ 437| 0| break; 438| 0| switch (Name[4]) { 439| 0| default: break; ------------------ | Branch (439:7): [True: 0, False: 0] ------------------ 440| 0| case '0': // 1 string to match. ------------------ | Branch (440:7): [True: 0, False: 0] ------------------ 441| 0| return 47; // "mvfr0" 442| 0| case '1': // 1 string to match. ------------------ | Branch (442:7): [True: 0, False: 0] ------------------ 443| 0| return 48; // "mvfr1" 444| 0| case '2': // 1 string to match. ------------------ | Branch (444:7): [True: 0, False: 0] ------------------ 445| 0| return 49; // "mvfr2" 446| 0| } 447| 0| break; 448| 475| } 449| 475| break; 450| 475| case 6: // 1 string to match. ------------------ | Branch (450:3): [True: 193, False: 16.3k] ------------------ 451| 193| if (memcmp(Name.data()+0, "fpinst", 6)) ------------------ | Branch (451:9): [True: 193, False: 0] ------------------ 452| 193| break; 453| 0| return 5; // "fpinst" 454| 83| case 7: // 2 strings to match. ------------------ | Branch (454:3): [True: 83, False: 16.4k] ------------------ 455| 83| switch (Name[0]) { 456| 35| default: break; ------------------ | Branch (456:5): [True: 35, False: 48] ------------------ 457| 48| case 'f': // 1 string to match. ------------------ | Branch (457:5): [True: 48, False: 35] ------------------ 458| 48| if (memcmp(Name.data()+1, "pinst2", 6)) ------------------ | Branch (458:11): [True: 48, False: 0] ------------------ 459| 48| break; 460| 0| return 46; // "fpinst2" 461| 0| case 'i': // 1 string to match. ------------------ | Branch (461:5): [True: 0, False: 83] ------------------ 462| 0| if (memcmp(Name.data()+1, "tstate", 6)) ------------------ | Branch (462:11): [True: 0, False: 0] ------------------ 463| 0| break; 464| 0| return 9; // "itstate" 465| 83| } 466| 83| break; 467| 83| case 9: // 1 string to match. ------------------ | Branch (467:3): [True: 34, False: 16.5k] ------------------ 468| 34| if (memcmp(Name.data()+0, "apsr_nzcv", 9)) ------------------ | Branch (468:9): [True: 34, False: 0] ------------------ 469| 34| break; 470| 0| return 2; // "apsr_nzcv" 471| 49| case 10: // 1 string to match. ------------------ | Branch (471:3): [True: 49, False: 16.5k] ------------------ 472| 49| if (memcmp(Name.data()+0, "fpscr_nzcv", 10)) ------------------ | Branch (472:9): [True: 49, False: 0] ------------------ 473| 49| break; 474| 0| return 7; // "fpscr_nzcv" 475| 16.5k| } 476| 15.2k| return 0; 477| 16.5k|} ARMAsmParser.cpp:_ZL20applyMnemonicAliasesRN7llvm_ks9StringRefEmj: 485| 5.72k|static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) { 486| 5.72k| switch (VariantID) { ------------------ | Branch (486:11): [True: 5.72k, False: 0] ------------------ 487| 5.72k| case 0: ------------------ | Branch (487:5): [True: 5.72k, False: 0] ------------------ 488| 5.72k| break; 489| 5.72k| } 490| 5.72k| switch (Mnemonic.size()) { 491| 1.64k| default: break; ------------------ | Branch (491:3): [True: 1.64k, False: 4.08k] ------------------ 492| 2.76k| case 3: // 4 strings to match. ------------------ | Branch (492:3): [True: 2.76k, False: 2.96k] ------------------ 493| 2.76k| switch (Mnemonic[0]) { 494| 2.24k| default: break; ------------------ | Branch (494:5): [True: 2.24k, False: 516] ------------------ 495| 2.24k| case 'r': // 1 string to match. ------------------ | Branch (495:5): [True: 0, False: 2.76k] ------------------ 496| 0| if (memcmp(Mnemonic.data()+1, "fe", 2)) ------------------ | Branch (496:11): [True: 0, False: 0] ------------------ 497| 0| break; 498| 0| Mnemonic = "rfeia"; // "rfe" 499| 0| return; 500| 516| case 's': // 3 strings to match. ------------------ | Branch (500:5): [True: 516, False: 2.24k] ------------------ 501| 516| switch (Mnemonic[1]) { 502| 516| default: break; ------------------ | Branch (502:7): [True: 516, False: 0] ------------------ 503| 516| case 'm': // 1 string to match. ------------------ | Branch (503:7): [True: 0, False: 516] ------------------ 504| 0| if (Mnemonic[2] != 'i') ------------------ | Branch (504:13): [True: 0, False: 0] ------------------ 505| 0| break; 506| 0| Mnemonic = "smc"; // "smi" 507| 0| return; 508| 0| case 'r': // 1 string to match. ------------------ | Branch (508:7): [True: 0, False: 516] ------------------ 509| 0| if (Mnemonic[2] != 's') ------------------ | Branch (509:13): [True: 0, False: 0] ------------------ 510| 0| break; 511| 0| Mnemonic = "srsia"; // "srs" 512| 0| return; 513| 0| case 'w': // 1 string to match. ------------------ | Branch (513:7): [True: 0, False: 516] ------------------ 514| 0| if (Mnemonic[2] != 'i') ------------------ | Branch (514:13): [True: 0, False: 0] ------------------ 515| 0| break; 516| 0| Mnemonic = "svc"; // "swi" 517| 0| return; 518| 516| } 519| 516| break; 520| 2.76k| } 521| 2.76k| break; 522| 2.76k| case 4: // 10 strings to match. ------------------ | Branch (522:3): [True: 426, False: 5.29k] ------------------ 523| 426| switch (Mnemonic[0]) { 524| 425| default: break; ------------------ | Branch (524:5): [True: 425, False: 1] ------------------ 525| 425| case 'f': // 8 strings to match. ------------------ | Branch (525:5): [True: 0, False: 426] ------------------ 526| 0| switch (Mnemonic[1]) { 527| 0| default: break; ------------------ | Branch (527:7): [True: 0, False: 0] ------------------ 528| 0| case 'l': // 2 strings to match. ------------------ | Branch (528:7): [True: 0, False: 0] ------------------ 529| 0| if (Mnemonic[2] != 'd') ------------------ | Branch (529:13): [True: 0, False: 0] ------------------ 530| 0| break; 531| 0| switch (Mnemonic[3]) { 532| 0| default: break; ------------------ | Branch (532:9): [True: 0, False: 0] ------------------ 533| 0| case 'd': // 1 string to match. ------------------ | Branch (533:9): [True: 0, False: 0] ------------------ 534| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldd" ------------------ | Branch (534:15): [True: 0, False: 0] ------------------ 535| 0| Mnemonic = "vldr"; 536| 0| return; 537| 0| case 's': // 1 string to match. ------------------ | Branch (537:9): [True: 0, False: 0] ------------------ 538| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "flds" ------------------ | Branch (538:15): [True: 0, False: 0] ------------------ 539| 0| Mnemonic = "vldr"; 540| 0| return; 541| 0| } 542| 0| break; 543| 0| case 'm': // 4 strings to match. ------------------ | Branch (543:7): [True: 0, False: 0] ------------------ 544| 0| switch (Mnemonic[2]) { 545| 0| default: break; ------------------ | Branch (545:9): [True: 0, False: 0] ------------------ 546| 0| case 'r': // 2 strings to match. ------------------ | Branch (546:9): [True: 0, False: 0] ------------------ 547| 0| switch (Mnemonic[3]) { 548| 0| default: break; ------------------ | Branch (548:11): [True: 0, False: 0] ------------------ 549| 0| case 's': // 1 string to match. ------------------ | Branch (549:11): [True: 0, False: 0] ------------------ 550| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrs" ------------------ | Branch (550:17): [True: 0, False: 0] ------------------ 551| 0| Mnemonic = "vmov"; 552| 0| return; 553| 0| case 'x': // 1 string to match. ------------------ | Branch (553:11): [True: 0, False: 0] ------------------ 554| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrx" ------------------ | Branch (554:17): [True: 0, False: 0] ------------------ 555| 0| Mnemonic = "vmrs"; 556| 0| return; 557| 0| } 558| 0| break; 559| 0| case 's': // 1 string to match. ------------------ | Branch (559:9): [True: 0, False: 0] ------------------ 560| 0| if (Mnemonic[3] != 'r') ------------------ | Branch (560:15): [True: 0, False: 0] ------------------ 561| 0| break; 562| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmsr" ------------------ | Branch (562:15): [True: 0, False: 0] ------------------ 563| 0| Mnemonic = "vmov"; 564| 0| return; 565| 0| case 'x': // 1 string to match. ------------------ | Branch (565:9): [True: 0, False: 0] ------------------ 566| 0| if (Mnemonic[3] != 'r') ------------------ | Branch (566:15): [True: 0, False: 0] ------------------ 567| 0| break; 568| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmxr" ------------------ | Branch (568:15): [True: 0, False: 0] ------------------ 569| 0| Mnemonic = "vmsr"; 570| 0| return; 571| 0| } 572| 0| break; 573| 0| case 's': // 2 strings to match. ------------------ | Branch (573:7): [True: 0, False: 0] ------------------ 574| 0| if (Mnemonic[2] != 't') ------------------ | Branch (574:13): [True: 0, False: 0] ------------------ 575| 0| break; 576| 0| switch (Mnemonic[3]) { 577| 0| default: break; ------------------ | Branch (577:9): [True: 0, False: 0] ------------------ 578| 0| case 'd': // 1 string to match. ------------------ | Branch (578:9): [True: 0, False: 0] ------------------ 579| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstd" ------------------ | Branch (579:15): [True: 0, False: 0] ------------------ 580| 0| Mnemonic = "vstr"; 581| 0| return; 582| 0| case 's': // 1 string to match. ------------------ | Branch (582:9): [True: 0, False: 0] ------------------ 583| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsts" ------------------ | Branch (583:15): [True: 0, False: 0] ------------------ 584| 0| Mnemonic = "vstr"; 585| 0| return; 586| 0| } 587| 0| break; 588| 0| } 589| 0| break; 590| 1| case 'v': // 2 strings to match. ------------------ | Branch (590:5): [True: 1, False: 425] ------------------ 591| 1| switch (Mnemonic[1]) { 592| 1| default: break; ------------------ | Branch (592:7): [True: 1, False: 0] ------------------ 593| 1| case 'l': // 1 string to match. ------------------ | Branch (593:7): [True: 0, False: 1] ------------------ 594| 0| if (memcmp(Mnemonic.data()+2, "dm", 2)) ------------------ | Branch (594:13): [True: 0, False: 0] ------------------ 595| 0| break; 596| 0| Mnemonic = "vldmia"; // "vldm" 597| 0| return; 598| 0| case 's': // 1 string to match. ------------------ | Branch (598:7): [True: 0, False: 1] ------------------ 599| 0| if (memcmp(Mnemonic.data()+2, "tm", 2)) ------------------ | Branch (599:13): [True: 0, False: 0] ------------------ 600| 0| break; 601| 0| Mnemonic = "vstmia"; // "vstm" 602| 0| return; 603| 1| } 604| 1| break; 605| 426| } 606| 426| break; 607| 426| case 5: // 51 strings to match. ------------------ | Branch (607:3): [True: 218, False: 5.50k] ------------------ 608| 218| switch (Mnemonic[0]) { 609| 134| default: break; ------------------ | Branch (609:5): [True: 134, False: 84] ------------------ 610| 134| case 'f': // 18 strings to match. ------------------ | Branch (610:5): [True: 68, False: 150] ------------------ 611| 68| switch (Mnemonic[1]) { 612| 51| default: break; ------------------ | Branch (612:7): [True: 51, False: 17] ------------------ 613| 51| case 'a': // 2 strings to match. ------------------ | Branch (613:7): [True: 0, False: 68] ------------------ 614| 0| if (memcmp(Mnemonic.data()+2, "dd", 2)) ------------------ | Branch (614:13): [True: 0, False: 0] ------------------ 615| 0| break; 616| 0| switch (Mnemonic[4]) { 617| 0| default: break; ------------------ | Branch (617:9): [True: 0, False: 0] ------------------ 618| 0| case 'd': // 1 string to match. ------------------ | Branch (618:9): [True: 0, False: 0] ------------------ 619| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "faddd" ------------------ | Branch (619:15): [True: 0, False: 0] ------------------ 620| 0| Mnemonic = "vadd.f64"; 621| 0| return; 622| 0| case 's': // 1 string to match. ------------------ | Branch (622:9): [True: 0, False: 0] ------------------ 623| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fadds" ------------------ | Branch (623:15): [True: 0, False: 0] ------------------ 624| 0| Mnemonic = "vadd.f32"; 625| 0| return; 626| 0| } 627| 0| break; 628| 1| case 'c': // 4 strings to match. ------------------ | Branch (628:7): [True: 1, False: 67] ------------------ 629| 1| switch (Mnemonic[2]) { 630| 0| default: break; ------------------ | Branch (630:9): [True: 0, False: 1] ------------------ 631| 0| case 'm': // 2 strings to match. ------------------ | Branch (631:9): [True: 0, False: 1] ------------------ 632| 0| if (Mnemonic[3] != 'p') ------------------ | Branch (632:15): [True: 0, False: 0] ------------------ 633| 0| break; 634| 0| switch (Mnemonic[4]) { 635| 0| default: break; ------------------ | Branch (635:11): [True: 0, False: 0] ------------------ 636| 0| case 'd': // 1 string to match. ------------------ | Branch (636:11): [True: 0, False: 0] ------------------ 637| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcmpd" ------------------ | Branch (637:17): [True: 0, False: 0] ------------------ 638| 0| Mnemonic = "vcmp.f64"; 639| 0| return; 640| 0| case 's': // 1 string to match. ------------------ | Branch (640:11): [True: 0, False: 0] ------------------ 641| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcmps" ------------------ | Branch (641:17): [True: 0, False: 0] ------------------ 642| 0| Mnemonic = "vcmp.f32"; 643| 0| return; 644| 0| } 645| 0| break; 646| 1| case 'p': // 2 strings to match. ------------------ | Branch (646:9): [True: 1, False: 0] ------------------ 647| 1| if (Mnemonic[3] != 'y') ------------------ | Branch (647:15): [True: 0, False: 1] ------------------ 648| 0| break; 649| 1| switch (Mnemonic[4]) { 650| 0| default: break; ------------------ | Branch (650:11): [True: 0, False: 1] ------------------ 651| 0| case 'd': // 1 string to match. ------------------ | Branch (651:11): [True: 0, False: 1] ------------------ 652| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcpyd" ------------------ | Branch (652:17): [True: 0, False: 0] ------------------ 653| 0| Mnemonic = "vmov.f64"; 654| 0| return; 655| 1| case 's': // 1 string to match. ------------------ | Branch (655:11): [True: 1, False: 0] ------------------ 656| 1| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcpys" ------------------ | Branch (656:17): [True: 1, False: 0] ------------------ 657| 1| Mnemonic = "vmov.f32"; 658| 1| return; 659| 1| } 660| 0| break; 661| 1| } 662| 0| break; 663| 16| case 'd': // 2 strings to match. ------------------ | Branch (663:7): [True: 16, False: 52] ------------------ 664| 16| if (memcmp(Mnemonic.data()+2, "iv", 2)) ------------------ | Branch (664:13): [True: 16, False: 0] ------------------ 665| 16| break; 666| 0| switch (Mnemonic[4]) { 667| 0| default: break; ------------------ | Branch (667:9): [True: 0, False: 0] ------------------ 668| 0| case 'd': // 1 string to match. ------------------ | Branch (668:9): [True: 0, False: 0] ------------------ 669| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fdivd" ------------------ | Branch (669:15): [True: 0, False: 0] ------------------ 670| 0| Mnemonic = "vdiv.f64"; 671| 0| return; 672| 0| case 's': // 1 string to match. ------------------ | Branch (672:9): [True: 0, False: 0] ------------------ 673| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fdivs" ------------------ | Branch (673:15): [True: 0, False: 0] ------------------ 674| 0| Mnemonic = "vdiv.f32"; 675| 0| return; 676| 0| } 677| 0| break; 678| 0| case 'm': // 8 strings to match. ------------------ | Branch (678:7): [True: 0, False: 68] ------------------ 679| 0| switch (Mnemonic[2]) { 680| 0| default: break; ------------------ | Branch (680:9): [True: 0, False: 0] ------------------ 681| 0| case 'a': // 2 strings to match. ------------------ | Branch (681:9): [True: 0, False: 0] ------------------ 682| 0| if (Mnemonic[3] != 'c') ------------------ | Branch (682:15): [True: 0, False: 0] ------------------ 683| 0| break; 684| 0| switch (Mnemonic[4]) { 685| 0| default: break; ------------------ | Branch (685:11): [True: 0, False: 0] ------------------ 686| 0| case 'd': // 1 string to match. ------------------ | Branch (686:11): [True: 0, False: 0] ------------------ 687| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmacd" ------------------ | Branch (687:17): [True: 0, False: 0] ------------------ 688| 0| Mnemonic = "vmla.f64"; 689| 0| return; 690| 0| case 's': // 1 string to match. ------------------ | Branch (690:11): [True: 0, False: 0] ------------------ 691| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmacs" ------------------ | Branch (691:17): [True: 0, False: 0] ------------------ 692| 0| Mnemonic = "vmla.f32"; 693| 0| return; 694| 0| } 695| 0| break; 696| 0| case 'd': // 1 string to match. ------------------ | Branch (696:9): [True: 0, False: 0] ------------------ 697| 0| if (memcmp(Mnemonic.data()+3, "rr", 2)) ------------------ | Branch (697:15): [True: 0, False: 0] ------------------ 698| 0| break; 699| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmdrr" ------------------ | Branch (699:15): [True: 0, False: 0] ------------------ 700| 0| Mnemonic = "vmov"; 701| 0| return; 702| 0| case 'r': // 3 strings to match. ------------------ | Branch (702:9): [True: 0, False: 0] ------------------ 703| 0| switch (Mnemonic[3]) { 704| 0| default: break; ------------------ | Branch (704:11): [True: 0, False: 0] ------------------ 705| 0| case 'd': // 2 strings to match. ------------------ | Branch (705:11): [True: 0, False: 0] ------------------ 706| 0| switch (Mnemonic[4]) { 707| 0| default: break; ------------------ | Branch (707:13): [True: 0, False: 0] ------------------ 708| 0| case 'd': // 1 string to match. ------------------ | Branch (708:13): [True: 0, False: 0] ------------------ 709| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrdd" ------------------ | Branch (709:19): [True: 0, False: 0] ------------------ 710| 0| Mnemonic = "vmov"; 711| 0| return; 712| 0| case 's': // 1 string to match. ------------------ | Branch (712:13): [True: 0, False: 0] ------------------ 713| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrds" ------------------ | Branch (713:19): [True: 0, False: 0] ------------------ 714| 0| Mnemonic = "vmov"; 715| 0| return; 716| 0| } 717| 0| break; 718| 0| case 'r': // 1 string to match. ------------------ | Branch (718:11): [True: 0, False: 0] ------------------ 719| 0| if (Mnemonic[4] != 'd') ------------------ | Branch (719:17): [True: 0, False: 0] ------------------ 720| 0| break; 721| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrrd" ------------------ | Branch (721:17): [True: 0, False: 0] ------------------ 722| 0| Mnemonic = "vmov"; 723| 0| return; 724| 0| } 725| 0| break; 726| 0| case 'u': // 2 strings to match. ------------------ | Branch (726:9): [True: 0, False: 0] ------------------ 727| 0| if (Mnemonic[3] != 'l') ------------------ | Branch (727:15): [True: 0, False: 0] ------------------ 728| 0| break; 729| 0| switch (Mnemonic[4]) { 730| 0| default: break; ------------------ | Branch (730:11): [True: 0, False: 0] ------------------ 731| 0| case 'd': // 1 string to match. ------------------ | Branch (731:11): [True: 0, False: 0] ------------------ 732| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmuld" ------------------ | Branch (732:17): [True: 0, False: 0] ------------------ 733| 0| Mnemonic = "vmul.f64"; 734| 0| return; 735| 0| case 's': // 1 string to match. ------------------ | Branch (735:11): [True: 0, False: 0] ------------------ 736| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmuls" ------------------ | Branch (736:17): [True: 0, False: 0] ------------------ 737| 0| Mnemonic = "vmul.f32"; 738| 0| return; 739| 0| } 740| 0| break; 741| 0| } 742| 0| break; 743| 0| case 'n': // 2 strings to match. ------------------ | Branch (743:7): [True: 0, False: 68] ------------------ 744| 0| if (memcmp(Mnemonic.data()+2, "eg", 2)) ------------------ | Branch (744:13): [True: 0, False: 0] ------------------ 745| 0| break; 746| 0| switch (Mnemonic[4]) { 747| 0| default: break; ------------------ | Branch (747:9): [True: 0, False: 0] ------------------ 748| 0| case 'd': // 1 string to match. ------------------ | Branch (748:9): [True: 0, False: 0] ------------------ 749| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fnegd" ------------------ | Branch (749:15): [True: 0, False: 0] ------------------ 750| 0| Mnemonic = "vneg.f64"; 751| 0| return; 752| 0| case 's': // 1 string to match. ------------------ | Branch (752:9): [True: 0, False: 0] ------------------ 753| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fnegs" ------------------ | Branch (753:15): [True: 0, False: 0] ------------------ 754| 0| Mnemonic = "vneg.f32"; 755| 0| return; 756| 0| } 757| 0| break; 758| 68| } 759| 67| break; 760| 67| case 'l': // 3 strings to match. ------------------ | Branch (760:5): [True: 3, False: 215] ------------------ 761| 3| if (memcmp(Mnemonic.data()+1, "dm", 2)) ------------------ | Branch (761:11): [True: 3, False: 0] ------------------ 762| 3| break; 763| 0| switch (Mnemonic[3]) { 764| 0| default: break; ------------------ | Branch (764:7): [True: 0, False: 0] ------------------ 765| 0| case 'e': // 1 string to match. ------------------ | Branch (765:7): [True: 0, False: 0] ------------------ 766| 0| if (Mnemonic[4] != 'a') ------------------ | Branch (766:13): [True: 0, False: 0] ------------------ 767| 0| break; 768| 0| Mnemonic = "ldmdb"; // "ldmea" 769| 0| return; 770| 0| case 'f': // 1 string to match. ------------------ | Branch (770:7): [True: 0, False: 0] ------------------ 771| 0| if (Mnemonic[4] != 'd') ------------------ | Branch (771:13): [True: 0, False: 0] ------------------ 772| 0| break; 773| 0| Mnemonic = "ldm"; // "ldmfd" 774| 0| return; 775| 0| case 'i': // 1 string to match. ------------------ | Branch (775:7): [True: 0, False: 0] ------------------ 776| 0| if (Mnemonic[4] != 'a') ------------------ | Branch (776:13): [True: 0, False: 0] ------------------ 777| 0| break; 778| 0| Mnemonic = "ldm"; // "ldmia" 779| 0| return; 780| 0| } 781| 0| break; 782| 3| case 'r': // 4 strings to match. ------------------ | Branch (782:5): [True: 3, False: 215] ------------------ 783| 3| if (memcmp(Mnemonic.data()+1, "fe", 2)) ------------------ | Branch (783:11): [True: 0, False: 3] ------------------ 784| 0| break; 785| 3| switch (Mnemonic[3]) { 786| 0| default: break; ------------------ | Branch (786:7): [True: 0, False: 3] ------------------ 787| 3| case 'e': // 2 strings to match. ------------------ | Branch (787:7): [True: 3, False: 0] ------------------ 788| 3| switch (Mnemonic[4]) { 789| 0| default: break; ------------------ | Branch (789:9): [True: 0, False: 3] ------------------ 790| 3| case 'a': // 1 string to match. ------------------ | Branch (790:9): [True: 3, False: 0] ------------------ 791| 3| Mnemonic = "rfedb"; // "rfeea" 792| 3| return; 793| 0| case 'd': // 1 string to match. ------------------ | Branch (793:9): [True: 0, False: 3] ------------------ 794| 0| Mnemonic = "rfeib"; // "rfeed" 795| 0| return; 796| 3| } 797| 0| break; 798| 0| case 'f': // 2 strings to match. ------------------ | Branch (798:7): [True: 0, False: 3] ------------------ 799| 0| switch (Mnemonic[4]) { 800| 0| default: break; ------------------ | Branch (800:9): [True: 0, False: 0] ------------------ 801| 0| case 'a': // 1 string to match. ------------------ | Branch (801:9): [True: 0, False: 0] ------------------ 802| 0| Mnemonic = "rfeda"; // "rfefa" 803| 0| return; 804| 0| case 'd': // 1 string to match. ------------------ | Branch (804:9): [True: 0, False: 0] ------------------ 805| 0| Mnemonic = "rfeia"; // "rfefd" 806| 0| return; 807| 0| } 808| 0| break; 809| 3| } 810| 0| break; 811| 10| case 's': // 7 strings to match. ------------------ | Branch (811:5): [True: 10, False: 208] ------------------ 812| 10| switch (Mnemonic[1]) { 813| 2| default: break; ------------------ | Branch (813:7): [True: 2, False: 8] ------------------ 814| 2| case 'r': // 4 strings to match. ------------------ | Branch (814:7): [True: 0, False: 10] ------------------ 815| 0| if (Mnemonic[2] != 's') ------------------ | Branch (815:13): [True: 0, False: 0] ------------------ 816| 0| break; 817| 0| switch (Mnemonic[3]) { 818| 0| default: break; ------------------ | Branch (818:9): [True: 0, False: 0] ------------------ 819| 0| case 'e': // 2 strings to match. ------------------ | Branch (819:9): [True: 0, False: 0] ------------------ 820| 0| switch (Mnemonic[4]) { 821| 0| default: break; ------------------ | Branch (821:11): [True: 0, False: 0] ------------------ 822| 0| case 'a': // 1 string to match. ------------------ | Branch (822:11): [True: 0, False: 0] ------------------ 823| 0| Mnemonic = "srsia"; // "srsea" 824| 0| return; 825| 0| case 'd': // 1 string to match. ------------------ | Branch (825:11): [True: 0, False: 0] ------------------ 826| 0| Mnemonic = "srsda"; // "srsed" 827| 0| return; 828| 0| } 829| 0| break; 830| 0| case 'f': // 2 strings to match. ------------------ | Branch (830:9): [True: 0, False: 0] ------------------ 831| 0| switch (Mnemonic[4]) { 832| 0| default: break; ------------------ | Branch (832:11): [True: 0, False: 0] ------------------ 833| 0| case 'a': // 1 string to match. ------------------ | Branch (833:11): [True: 0, False: 0] ------------------ 834| 0| Mnemonic = "srsib"; // "srsfa" 835| 0| return; 836| 0| case 'd': // 1 string to match. ------------------ | Branch (836:11): [True: 0, False: 0] ------------------ 837| 0| Mnemonic = "srsdb"; // "srsfd" 838| 0| return; 839| 0| } 840| 0| break; 841| 0| } 842| 0| break; 843| 8| case 't': // 3 strings to match. ------------------ | Branch (843:7): [True: 8, False: 2] ------------------ 844| 8| if (Mnemonic[2] != 'm') ------------------ | Branch (844:13): [True: 8, False: 0] ------------------ 845| 8| break; 846| 0| switch (Mnemonic[3]) { 847| 0| default: break; ------------------ | Branch (847:9): [True: 0, False: 0] ------------------ 848| 0| case 'e': // 1 string to match. ------------------ | Branch (848:9): [True: 0, False: 0] ------------------ 849| 0| if (Mnemonic[4] != 'a') ------------------ | Branch (849:15): [True: 0, False: 0] ------------------ 850| 0| break; 851| 0| Mnemonic = "stm"; // "stmea" 852| 0| return; 853| 0| case 'f': // 1 string to match. ------------------ | Branch (853:9): [True: 0, False: 0] ------------------ 854| 0| if (Mnemonic[4] != 'd') ------------------ | Branch (854:15): [True: 0, False: 0] ------------------ 855| 0| break; 856| 0| Mnemonic = "stmdb"; // "stmfd" 857| 0| return; 858| 0| case 'i': // 1 string to match. ------------------ | Branch (858:9): [True: 0, False: 0] ------------------ 859| 0| if (Mnemonic[4] != 'a') ------------------ | Branch (859:15): [True: 0, False: 0] ------------------ 860| 0| break; 861| 0| Mnemonic = "stm"; // "stmia" 862| 0| return; 863| 0| } 864| 0| break; 865| 10| } 866| 10| break; 867| 10| case 'v': // 19 strings to match. ------------------ | Branch (867:5): [True: 0, False: 218] ------------------ 868| 0| switch (Mnemonic[1]) { 869| 0| default: break; ------------------ | Branch (869:7): [True: 0, False: 0] ------------------ 870| 0| case 'a': // 3 strings to match. ------------------ | Branch (870:7): [True: 0, False: 0] ------------------ 871| 0| switch (Mnemonic[2]) { 872| 0| default: break; ------------------ | Branch (872:9): [True: 0, False: 0] ------------------ 873| 0| case 'b': // 1 string to match. ------------------ | Branch (873:9): [True: 0, False: 0] ------------------ 874| 0| if (memcmp(Mnemonic.data()+3, "sq", 2)) ------------------ | Branch (874:15): [True: 0, False: 0] ------------------ 875| 0| break; 876| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vabsq" ------------------ | Branch (876:15): [True: 0, False: 0] ------------------ 877| 0| Mnemonic = "vabs"; 878| 0| return; 879| 0| case 'd': // 1 string to match. ------------------ | Branch (879:9): [True: 0, False: 0] ------------------ 880| 0| if (memcmp(Mnemonic.data()+3, "dq", 2)) ------------------ | Branch (880:15): [True: 0, False: 0] ------------------ 881| 0| break; 882| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vaddq" ------------------ | Branch (882:15): [True: 0, False: 0] ------------------ 883| 0| Mnemonic = "vadd"; 884| 0| return; 885| 0| case 'n': // 1 string to match. ------------------ | Branch (885:9): [True: 0, False: 0] ------------------ 886| 0| if (memcmp(Mnemonic.data()+3, "dq", 2)) ------------------ | Branch (886:15): [True: 0, False: 0] ------------------ 887| 0| break; 888| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vandq" ------------------ | Branch (888:15): [True: 0, False: 0] ------------------ 889| 0| Mnemonic = "vand"; 890| 0| return; 891| 0| } 892| 0| break; 893| 0| case 'b': // 1 string to match. ------------------ | Branch (893:7): [True: 0, False: 0] ------------------ 894| 0| if (memcmp(Mnemonic.data()+2, "icq", 3)) ------------------ | Branch (894:13): [True: 0, False: 0] ------------------ 895| 0| break; 896| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vbicq" ------------------ | Branch (896:13): [True: 0, False: 0] ------------------ 897| 0| Mnemonic = "vbic"; 898| 0| return; 899| 0| case 'c': // 3 strings to match. ------------------ | Branch (899:7): [True: 0, False: 0] ------------------ 900| 0| switch (Mnemonic[2]) { 901| 0| default: break; ------------------ | Branch (901:9): [True: 0, False: 0] ------------------ 902| 0| case 'e': // 1 string to match. ------------------ | Branch (902:9): [True: 0, False: 0] ------------------ 903| 0| if (memcmp(Mnemonic.data()+3, "qq", 2)) ------------------ | Branch (903:15): [True: 0, False: 0] ------------------ 904| 0| break; 905| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vceqq" ------------------ | Branch (905:15): [True: 0, False: 0] ------------------ 906| 0| Mnemonic = "vceq"; 907| 0| return; 908| 0| case 'l': // 1 string to match. ------------------ | Branch (908:9): [True: 0, False: 0] ------------------ 909| 0| if (memcmp(Mnemonic.data()+3, "eq", 2)) ------------------ | Branch (909:15): [True: 0, False: 0] ------------------ 910| 0| break; 911| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vcleq" ------------------ | Branch (911:15): [True: 0, False: 0] ------------------ 912| 0| Mnemonic = "vcle"; 913| 0| return; 914| 0| case 'v': // 1 string to match. ------------------ | Branch (914:9): [True: 0, False: 0] ------------------ 915| 0| if (memcmp(Mnemonic.data()+3, "tq", 2)) ------------------ | Branch (915:15): [True: 0, False: 0] ------------------ 916| 0| break; 917| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vcvtq" ------------------ | Branch (917:15): [True: 0, False: 0] ------------------ 918| 0| Mnemonic = "vcvt"; 919| 0| return; 920| 0| } 921| 0| break; 922| 0| case 'e': // 1 string to match. ------------------ | Branch (922:7): [True: 0, False: 0] ------------------ 923| 0| if (memcmp(Mnemonic.data()+2, "orq", 3)) ------------------ | Branch (923:13): [True: 0, False: 0] ------------------ 924| 0| break; 925| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "veorq" ------------------ | Branch (925:13): [True: 0, False: 0] ------------------ 926| 0| Mnemonic = "veor"; 927| 0| return; 928| 0| case 'm': // 5 strings to match. ------------------ | Branch (928:7): [True: 0, False: 0] ------------------ 929| 0| switch (Mnemonic[2]) { 930| 0| default: break; ------------------ | Branch (930:9): [True: 0, False: 0] ------------------ 931| 0| case 'a': // 1 string to match. ------------------ | Branch (931:9): [True: 0, False: 0] ------------------ 932| 0| if (memcmp(Mnemonic.data()+3, "xq", 2)) ------------------ | Branch (932:15): [True: 0, False: 0] ------------------ 933| 0| break; 934| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmaxq" ------------------ | Branch (934:15): [True: 0, False: 0] ------------------ 935| 0| Mnemonic = "vmax"; 936| 0| return; 937| 0| case 'i': // 1 string to match. ------------------ | Branch (937:9): [True: 0, False: 0] ------------------ 938| 0| if (memcmp(Mnemonic.data()+3, "nq", 2)) ------------------ | Branch (938:15): [True: 0, False: 0] ------------------ 939| 0| break; 940| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vminq" ------------------ | Branch (940:15): [True: 0, False: 0] ------------------ 941| 0| Mnemonic = "vmin"; 942| 0| return; 943| 0| case 'o': // 1 string to match. ------------------ | Branch (943:9): [True: 0, False: 0] ------------------ 944| 0| if (memcmp(Mnemonic.data()+3, "vq", 2)) ------------------ | Branch (944:15): [True: 0, False: 0] ------------------ 945| 0| break; 946| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq" ------------------ | Branch (946:15): [True: 0, False: 0] ------------------ 947| 0| Mnemonic = "vmov"; 948| 0| return; 949| 0| case 'u': // 1 string to match. ------------------ | Branch (949:9): [True: 0, False: 0] ------------------ 950| 0| if (memcmp(Mnemonic.data()+3, "lq", 2)) ------------------ | Branch (950:15): [True: 0, False: 0] ------------------ 951| 0| break; 952| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmulq" ------------------ | Branch (952:15): [True: 0, False: 0] ------------------ 953| 0| Mnemonic = "vmul"; 954| 0| return; 955| 0| case 'v': // 1 string to match. ------------------ | Branch (955:9): [True: 0, False: 0] ------------------ 956| 0| if (memcmp(Mnemonic.data()+3, "nq", 2)) ------------------ | Branch (956:15): [True: 0, False: 0] ------------------ 957| 0| break; 958| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmvnq" ------------------ | Branch (958:15): [True: 0, False: 0] ------------------ 959| 0| Mnemonic = "vmvn"; 960| 0| return; 961| 0| } 962| 0| break; 963| 0| case 'o': // 1 string to match. ------------------ | Branch (963:7): [True: 0, False: 0] ------------------ 964| 0| if (memcmp(Mnemonic.data()+2, "rrq", 3)) ------------------ | Branch (964:13): [True: 0, False: 0] ------------------ 965| 0| break; 966| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vorrq" ------------------ | Branch (966:13): [True: 0, False: 0] ------------------ 967| 0| Mnemonic = "vorr"; 968| 0| return; 969| 0| case 's': // 4 strings to match. ------------------ | Branch (969:7): [True: 0, False: 0] ------------------ 970| 0| switch (Mnemonic[2]) { 971| 0| default: break; ------------------ | Branch (971:9): [True: 0, False: 0] ------------------ 972| 0| case 'h': // 2 strings to match. ------------------ | Branch (972:9): [True: 0, False: 0] ------------------ 973| 0| switch (Mnemonic[3]) { 974| 0| default: break; ------------------ | Branch (974:11): [True: 0, False: 0] ------------------ 975| 0| case 'l': // 1 string to match. ------------------ | Branch (975:11): [True: 0, False: 0] ------------------ 976| 0| if (Mnemonic[4] != 'q') ------------------ | Branch (976:17): [True: 0, False: 0] ------------------ 977| 0| break; 978| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vshlq" ------------------ | Branch (978:17): [True: 0, False: 0] ------------------ 979| 0| Mnemonic = "vshl"; 980| 0| return; 981| 0| case 'r': // 1 string to match. ------------------ | Branch (981:11): [True: 0, False: 0] ------------------ 982| 0| if (Mnemonic[4] != 'q') ------------------ | Branch (982:17): [True: 0, False: 0] ------------------ 983| 0| break; 984| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vshrq" ------------------ | Branch (984:17): [True: 0, False: 0] ------------------ 985| 0| Mnemonic = "vshr"; 986| 0| return; 987| 0| } 988| 0| break; 989| 0| case 'u': // 1 string to match. ------------------ | Branch (989:9): [True: 0, False: 0] ------------------ 990| 0| if (memcmp(Mnemonic.data()+3, "bq", 2)) ------------------ | Branch (990:15): [True: 0, False: 0] ------------------ 991| 0| break; 992| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vsubq" ------------------ | Branch (992:15): [True: 0, False: 0] ------------------ 993| 0| Mnemonic = "vsub"; 994| 0| return; 995| 0| case 'w': // 1 string to match. ------------------ | Branch (995:9): [True: 0, False: 0] ------------------ 996| 0| if (memcmp(Mnemonic.data()+3, "pq", 2)) ------------------ | Branch (996:15): [True: 0, False: 0] ------------------ 997| 0| break; 998| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vswpq" ------------------ | Branch (998:15): [True: 0, False: 0] ------------------ 999| 0| Mnemonic = "vswp"; 1000| 0| return; 1001| 0| } 1002| 0| break; 1003| 0| case 'z': // 1 string to match. ------------------ | Branch (1003:7): [True: 0, False: 0] ------------------ 1004| 0| if (memcmp(Mnemonic.data()+2, "ipq", 3)) ------------------ | Branch (1004:13): [True: 0, False: 0] ------------------ 1005| 0| break; 1006| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vzipq" ------------------ | Branch (1006:13): [True: 0, False: 0] ------------------ 1007| 0| Mnemonic = "vzip"; 1008| 0| return; 1009| 0| } 1010| 0| break; 1011| 218| } 1012| 214| break; 1013| 285| case 6: // 10 strings to match. ------------------ | Branch (1013:3): [True: 285, False: 5.43k] ------------------ 1014| 285| if (Mnemonic[0] != 'f') ------------------ | Branch (1014:9): [True: 282, False: 3] ------------------ 1015| 282| break; 1016| 3| switch (Mnemonic[1]) { 1017| 1| default: break; ------------------ | Branch (1017:5): [True: 1, False: 2] ------------------ 1018| 1| case 's': // 4 strings to match. ------------------ | Branch (1018:5): [True: 0, False: 3] ------------------ 1019| 0| switch (Mnemonic[2]) { 1020| 0| default: break; ------------------ | Branch (1020:7): [True: 0, False: 0] ------------------ 1021| 0| case 'i': // 2 strings to match. ------------------ | Branch (1021:7): [True: 0, False: 0] ------------------ 1022| 0| if (memcmp(Mnemonic.data()+3, "to", 2)) ------------------ | Branch (1022:13): [True: 0, False: 0] ------------------ 1023| 0| break; 1024| 0| switch (Mnemonic[5]) { 1025| 0| default: break; ------------------ | Branch (1025:9): [True: 0, False: 0] ------------------ 1026| 0| case 'd': // 1 string to match. ------------------ | Branch (1026:9): [True: 0, False: 0] ------------------ 1027| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsitod" ------------------ | Branch (1027:15): [True: 0, False: 0] ------------------ 1028| 0| Mnemonic = "vcvt.f64.s32"; 1029| 0| return; 1030| 0| case 's': // 1 string to match. ------------------ | Branch (1030:9): [True: 0, False: 0] ------------------ 1031| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsitos" ------------------ | Branch (1031:15): [True: 0, False: 0] ------------------ 1032| 0| Mnemonic = "vcvt.f32.s32"; 1033| 0| return; 1034| 0| } 1035| 0| break; 1036| 0| case 'q': // 2 strings to match. ------------------ | Branch (1036:7): [True: 0, False: 0] ------------------ 1037| 0| if (memcmp(Mnemonic.data()+3, "rt", 2)) ------------------ | Branch (1037:13): [True: 0, False: 0] ------------------ 1038| 0| break; 1039| 0| switch (Mnemonic[5]) { 1040| 0| default: break; ------------------ | Branch (1040:9): [True: 0, False: 0] ------------------ 1041| 0| case 'd': // 1 string to match. ------------------ | Branch (1041:9): [True: 0, False: 0] ------------------ 1042| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsqrtd" ------------------ | Branch (1042:15): [True: 0, False: 0] ------------------ 1043| 0| Mnemonic = "vsqrt"; 1044| 0| return; 1045| 0| case 's': // 1 string to match. ------------------ | Branch (1045:9): [True: 0, False: 0] ------------------ 1046| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsqrts" ------------------ | Branch (1046:15): [True: 0, False: 0] ------------------ 1047| 0| Mnemonic = "vsqrt"; 1048| 0| return; 1049| 0| } 1050| 0| break; 1051| 0| } 1052| 0| break; 1053| 0| case 't': // 4 strings to match. ------------------ | Branch (1053:5): [True: 0, False: 3] ------------------ 1054| 0| if (Mnemonic[2] != 'o') ------------------ | Branch (1054:11): [True: 0, False: 0] ------------------ 1055| 0| break; 1056| 0| switch (Mnemonic[3]) { 1057| 0| default: break; ------------------ | Branch (1057:7): [True: 0, False: 0] ------------------ 1058| 0| case 's': // 2 strings to match. ------------------ | Branch (1058:7): [True: 0, False: 0] ------------------ 1059| 0| if (Mnemonic[4] != 'i') ------------------ | Branch (1059:13): [True: 0, False: 0] ------------------ 1060| 0| break; 1061| 0| switch (Mnemonic[5]) { 1062| 0| default: break; ------------------ | Branch (1062:9): [True: 0, False: 0] ------------------ 1063| 0| case 'd': // 1 string to match. ------------------ | Branch (1063:9): [True: 0, False: 0] ------------------ 1064| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosid" ------------------ | Branch (1064:15): [True: 0, False: 0] ------------------ 1065| 0| Mnemonic = "vcvtr.s32.f64"; 1066| 0| return; 1067| 0| case 's': // 1 string to match. ------------------ | Branch (1067:9): [True: 0, False: 0] ------------------ 1068| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosis" ------------------ | Branch (1068:15): [True: 0, False: 0] ------------------ 1069| 0| Mnemonic = "vcvtr.s32.f32"; 1070| 0| return; 1071| 0| } 1072| 0| break; 1073| 0| case 'u': // 2 strings to match. ------------------ | Branch (1073:7): [True: 0, False: 0] ------------------ 1074| 0| if (Mnemonic[4] != 'i') ------------------ | Branch (1074:13): [True: 0, False: 0] ------------------ 1075| 0| break; 1076| 0| switch (Mnemonic[5]) { 1077| 0| default: break; ------------------ | Branch (1077:9): [True: 0, False: 0] ------------------ 1078| 0| case 'd': // 1 string to match. ------------------ | Branch (1078:9): [True: 0, False: 0] ------------------ 1079| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouid" ------------------ | Branch (1079:15): [True: 0, False: 0] ------------------ 1080| 0| Mnemonic = "vcvtr.u32.f64"; 1081| 0| return; 1082| 0| case 's': // 1 string to match. ------------------ | Branch (1082:9): [True: 0, False: 0] ------------------ 1083| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouis" ------------------ | Branch (1083:15): [True: 0, False: 0] ------------------ 1084| 0| Mnemonic = "vcvtr.u32.f32"; 1085| 0| return; 1086| 0| } 1087| 0| break; 1088| 0| } 1089| 0| break; 1090| 2| case 'u': // 2 strings to match. ------------------ | Branch (1090:5): [True: 2, False: 1] ------------------ 1091| 2| if (memcmp(Mnemonic.data()+2, "ito", 3)) ------------------ | Branch (1091:11): [True: 2, False: 0] ------------------ 1092| 2| break; 1093| 0| switch (Mnemonic[5]) { 1094| 0| default: break; ------------------ | Branch (1094:7): [True: 0, False: 0] ------------------ 1095| 0| case 'd': // 1 string to match. ------------------ | Branch (1095:7): [True: 0, False: 0] ------------------ 1096| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fuitod" ------------------ | Branch (1096:13): [True: 0, False: 0] ------------------ 1097| 0| Mnemonic = "vcvt.f64.u32"; 1098| 0| return; 1099| 0| case 's': // 1 string to match. ------------------ | Branch (1099:7): [True: 0, False: 0] ------------------ 1100| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fuitos" ------------------ | Branch (1100:13): [True: 0, False: 0] ------------------ 1101| 0| Mnemonic = "vcvt.f32.u32"; 1102| 0| return; 1103| 0| } 1104| 0| break; 1105| 3| } 1106| 3| break; 1107| 181| case 7: // 24 strings to match. ------------------ | Branch (1107:3): [True: 181, False: 5.54k] ------------------ 1108| 181| if (Mnemonic[0] != 'f') ------------------ | Branch (1108:9): [True: 84, False: 97] ------------------ 1109| 84| break; 1110| 97| switch (Mnemonic[1]) { 1111| 0| default: break; ------------------ | Branch (1111:5): [True: 0, False: 97] ------------------ 1112| 97| case 'l': // 10 strings to match. ------------------ | Branch (1112:5): [True: 97, False: 0] ------------------ 1113| 97| if (memcmp(Mnemonic.data()+2, "dm", 2)) ------------------ | Branch (1113:11): [True: 9, False: 88] ------------------ 1114| 9| break; 1115| 88| switch (Mnemonic[4]) { 1116| 2| default: break; ------------------ | Branch (1116:7): [True: 2, False: 86] ------------------ 1117| 2| case 'd': // 2 strings to match. ------------------ | Branch (1117:7): [True: 0, False: 88] ------------------ 1118| 0| if (Mnemonic[5] != 'b') ------------------ | Branch (1118:13): [True: 0, False: 0] ------------------ 1119| 0| break; 1120| 0| switch (Mnemonic[6]) { 1121| 0| default: break; ------------------ | Branch (1121:9): [True: 0, False: 0] ------------------ 1122| 0| case 'd': // 1 string to match. ------------------ | Branch (1122:9): [True: 0, False: 0] ------------------ 1123| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmdbd" ------------------ | Branch (1123:15): [True: 0, False: 0] ------------------ 1124| 0| Mnemonic = "vldmdb"; 1125| 0| return; 1126| 0| case 's': // 1 string to match. ------------------ | Branch (1126:9): [True: 0, False: 0] ------------------ 1127| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmdbs" ------------------ | Branch (1127:15): [True: 0, False: 0] ------------------ 1128| 0| Mnemonic = "vldmdb"; 1129| 0| return; 1130| 0| } 1131| 0| break; 1132| 86| case 'e': // 3 strings to match. ------------------ | Branch (1132:7): [True: 86, False: 2] ------------------ 1133| 86| if (Mnemonic[5] != 'a') ------------------ | Branch (1133:13): [True: 46, False: 40] ------------------ 1134| 46| break; 1135| 40| switch (Mnemonic[6]) { 1136| 0| default: break; ------------------ | Branch (1136:9): [True: 0, False: 40] ------------------ 1137| 0| case 'd': // 1 string to match. ------------------ | Branch (1137:9): [True: 0, False: 40] ------------------ 1138| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmead" ------------------ | Branch (1138:15): [True: 0, False: 0] ------------------ 1139| 0| Mnemonic = "vldmdb"; 1140| 0| return; 1141| 1| case 's': // 1 string to match. ------------------ | Branch (1141:9): [True: 1, False: 39] ------------------ 1142| 1| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmeas" ------------------ | Branch (1142:15): [True: 0, False: 1] ------------------ 1143| 0| Mnemonic = "vldmdb"; 1144| 1| return; 1145| 39| case 'x': // 1 string to match. ------------------ | Branch (1145:9): [True: 39, False: 1] ------------------ 1146| 39| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmeax" ------------------ | Branch (1146:15): [True: 39, False: 0] ------------------ 1147| 39| Mnemonic = "fldmdbx"; 1148| 39| return; 1149| 40| } 1150| 0| break; 1151| 0| case 'f': // 3 strings to match. ------------------ | Branch (1151:7): [True: 0, False: 88] ------------------ 1152| 0| if (Mnemonic[5] != 'd') ------------------ | Branch (1152:13): [True: 0, False: 0] ------------------ 1153| 0| break; 1154| 0| switch (Mnemonic[6]) { 1155| 0| default: break; ------------------ | Branch (1155:9): [True: 0, False: 0] ------------------ 1156| 0| case 'd': // 1 string to match. ------------------ | Branch (1156:9): [True: 0, False: 0] ------------------ 1157| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmfdd" ------------------ | Branch (1157:15): [True: 0, False: 0] ------------------ 1158| 0| Mnemonic = "vldmia"; 1159| 0| return; 1160| 0| case 's': // 1 string to match. ------------------ | Branch (1160:9): [True: 0, False: 0] ------------------ 1161| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmfds" ------------------ | Branch (1161:15): [True: 0, False: 0] ------------------ 1162| 0| Mnemonic = "vldmia"; 1163| 0| return; 1164| 0| case 'x': // 1 string to match. ------------------ | Branch (1164:9): [True: 0, False: 0] ------------------ 1165| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmfdx" ------------------ | Branch (1165:15): [True: 0, False: 0] ------------------ 1166| 0| Mnemonic = "fldmiax"; 1167| 0| return; 1168| 0| } 1169| 0| break; 1170| 0| case 'i': // 2 strings to match. ------------------ | Branch (1170:7): [True: 0, False: 88] ------------------ 1171| 0| if (Mnemonic[5] != 'a') ------------------ | Branch (1171:13): [True: 0, False: 0] ------------------ 1172| 0| break; 1173| 0| switch (Mnemonic[6]) { 1174| 0| default: break; ------------------ | Branch (1174:9): [True: 0, False: 0] ------------------ 1175| 0| case 'd': // 1 string to match. ------------------ | Branch (1175:9): [True: 0, False: 0] ------------------ 1176| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmiad" ------------------ | Branch (1176:15): [True: 0, False: 0] ------------------ 1177| 0| Mnemonic = "vldmia"; 1178| 0| return; 1179| 0| case 's': // 1 string to match. ------------------ | Branch (1179:9): [True: 0, False: 0] ------------------ 1180| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmias" ------------------ | Branch (1180:15): [True: 0, False: 0] ------------------ 1181| 0| Mnemonic = "vldmia"; 1182| 0| return; 1183| 0| } 1184| 0| break; 1185| 88| } 1186| 48| break; 1187| 48| case 's': // 10 strings to match. ------------------ | Branch (1187:5): [True: 0, False: 97] ------------------ 1188| 0| if (memcmp(Mnemonic.data()+2, "tm", 2)) ------------------ | Branch (1188:11): [True: 0, False: 0] ------------------ 1189| 0| break; 1190| 0| switch (Mnemonic[4]) { 1191| 0| default: break; ------------------ | Branch (1191:7): [True: 0, False: 0] ------------------ 1192| 0| case 'd': // 2 strings to match. ------------------ | Branch (1192:7): [True: 0, False: 0] ------------------ 1193| 0| if (Mnemonic[5] != 'b') ------------------ | Branch (1193:13): [True: 0, False: 0] ------------------ 1194| 0| break; 1195| 0| switch (Mnemonic[6]) { 1196| 0| default: break; ------------------ | Branch (1196:9): [True: 0, False: 0] ------------------ 1197| 0| case 'd': // 1 string to match. ------------------ | Branch (1197:9): [True: 0, False: 0] ------------------ 1198| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmdbd" ------------------ | Branch (1198:15): [True: 0, False: 0] ------------------ 1199| 0| Mnemonic = "vstmdb"; 1200| 0| return; 1201| 0| case 's': // 1 string to match. ------------------ | Branch (1201:9): [True: 0, False: 0] ------------------ 1202| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmdbs" ------------------ | Branch (1202:15): [True: 0, False: 0] ------------------ 1203| 0| Mnemonic = "vstmdb"; 1204| 0| return; 1205| 0| } 1206| 0| break; 1207| 0| case 'e': // 3 strings to match. ------------------ | Branch (1207:7): [True: 0, False: 0] ------------------ 1208| 0| if (Mnemonic[5] != 'a') ------------------ | Branch (1208:13): [True: 0, False: 0] ------------------ 1209| 0| break; 1210| 0| switch (Mnemonic[6]) { 1211| 0| default: break; ------------------ | Branch (1211:9): [True: 0, False: 0] ------------------ 1212| 0| case 'd': // 1 string to match. ------------------ | Branch (1212:9): [True: 0, False: 0] ------------------ 1213| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmead" ------------------ | Branch (1213:15): [True: 0, False: 0] ------------------ 1214| 0| Mnemonic = "vstmia"; 1215| 0| return; 1216| 0| case 's': // 1 string to match. ------------------ | Branch (1216:9): [True: 0, False: 0] ------------------ 1217| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmeas" ------------------ | Branch (1217:15): [True: 0, False: 0] ------------------ 1218| 0| Mnemonic = "vstmia"; 1219| 0| return; 1220| 0| case 'x': // 1 string to match. ------------------ | Branch (1220:9): [True: 0, False: 0] ------------------ 1221| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmeax" ------------------ | Branch (1221:15): [True: 0, False: 0] ------------------ 1222| 0| Mnemonic = "fstmiax"; 1223| 0| return; 1224| 0| } 1225| 0| break; 1226| 0| case 'f': // 3 strings to match. ------------------ | Branch (1226:7): [True: 0, False: 0] ------------------ 1227| 0| if (Mnemonic[5] != 'd') ------------------ | Branch (1227:13): [True: 0, False: 0] ------------------ 1228| 0| break; 1229| 0| switch (Mnemonic[6]) { 1230| 0| default: break; ------------------ | Branch (1230:9): [True: 0, False: 0] ------------------ 1231| 0| case 'd': // 1 string to match. ------------------ | Branch (1231:9): [True: 0, False: 0] ------------------ 1232| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmfdd" ------------------ | Branch (1232:15): [True: 0, False: 0] ------------------ 1233| 0| Mnemonic = "vstmdb"; 1234| 0| return; 1235| 0| case 's': // 1 string to match. ------------------ | Branch (1235:9): [True: 0, False: 0] ------------------ 1236| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmfds" ------------------ | Branch (1236:15): [True: 0, False: 0] ------------------ 1237| 0| Mnemonic = "vstmdb"; 1238| 0| return; 1239| 0| case 'x': // 1 string to match. ------------------ | Branch (1239:9): [True: 0, False: 0] ------------------ 1240| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmfdx" ------------------ | Branch (1240:15): [True: 0, False: 0] ------------------ 1241| 0| Mnemonic = "fstmdbx"; 1242| 0| return; 1243| 0| } 1244| 0| break; 1245| 0| case 'i': // 2 strings to match. ------------------ | Branch (1245:7): [True: 0, False: 0] ------------------ 1246| 0| if (Mnemonic[5] != 'a') ------------------ | Branch (1246:13): [True: 0, False: 0] ------------------ 1247| 0| break; 1248| 0| switch (Mnemonic[6]) { 1249| 0| default: break; ------------------ | Branch (1249:9): [True: 0, False: 0] ------------------ 1250| 0| case 'd': // 1 string to match. ------------------ | Branch (1250:9): [True: 0, False: 0] ------------------ 1251| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmiad" ------------------ | Branch (1251:15): [True: 0, False: 0] ------------------ 1252| 0| Mnemonic = "vstmia"; 1253| 0| return; 1254| 0| case 's': // 1 string to match. ------------------ | Branch (1254:9): [True: 0, False: 0] ------------------ 1255| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmias" ------------------ | Branch (1255:15): [True: 0, False: 0] ------------------ 1256| 0| Mnemonic = "vstmia"; 1257| 0| return; 1258| 0| } 1259| 0| break; 1260| 0| } 1261| 0| break; 1262| 0| case 't': // 4 strings to match. ------------------ | Branch (1262:5): [True: 0, False: 97] ------------------ 1263| 0| if (Mnemonic[2] != 'o') ------------------ | Branch (1263:11): [True: 0, False: 0] ------------------ 1264| 0| break; 1265| 0| switch (Mnemonic[3]) { 1266| 0| default: break; ------------------ | Branch (1266:7): [True: 0, False: 0] ------------------ 1267| 0| case 's': // 2 strings to match. ------------------ | Branch (1267:7): [True: 0, False: 0] ------------------ 1268| 0| if (memcmp(Mnemonic.data()+4, "iz", 2)) ------------------ | Branch (1268:13): [True: 0, False: 0] ------------------ 1269| 0| break; 1270| 0| switch (Mnemonic[6]) { 1271| 0| default: break; ------------------ | Branch (1271:9): [True: 0, False: 0] ------------------ 1272| 0| case 'd': // 1 string to match. ------------------ | Branch (1272:9): [True: 0, False: 0] ------------------ 1273| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosizd" ------------------ | Branch (1273:15): [True: 0, False: 0] ------------------ 1274| 0| Mnemonic = "vcvt.s32.f64"; 1275| 0| return; 1276| 0| case 's': // 1 string to match. ------------------ | Branch (1276:9): [True: 0, False: 0] ------------------ 1277| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosizs" ------------------ | Branch (1277:15): [True: 0, False: 0] ------------------ 1278| 0| Mnemonic = "vcvt.s32.f32"; 1279| 0| return; 1280| 0| } 1281| 0| break; 1282| 0| case 'u': // 2 strings to match. ------------------ | Branch (1282:7): [True: 0, False: 0] ------------------ 1283| 0| if (memcmp(Mnemonic.data()+4, "iz", 2)) ------------------ | Branch (1283:13): [True: 0, False: 0] ------------------ 1284| 0| break; 1285| 0| switch (Mnemonic[6]) { 1286| 0| default: break; ------------------ | Branch (1286:9): [True: 0, False: 0] ------------------ 1287| 0| case 'd': // 1 string to match. ------------------ | Branch (1287:9): [True: 0, False: 0] ------------------ 1288| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouizd" ------------------ | Branch (1288:15): [True: 0, False: 0] ------------------ 1289| 0| Mnemonic = "vcvt.u32.f64"; 1290| 0| return; 1291| 0| case 's': // 1 string to match. ------------------ | Branch (1291:9): [True: 0, False: 0] ------------------ 1292| 0| if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouizs" ------------------ | Branch (1292:15): [True: 0, False: 0] ------------------ 1293| 0| Mnemonic = "vcvt.u32.f32"; 1294| 0| return; 1295| 0| } 1296| 0| break; 1297| 0| } 1298| 0| break; 1299| 97| } 1300| 57| break; 1301| 83| case 8: // 5 strings to match. ------------------ | Branch (1301:3): [True: 83, False: 5.64k] ------------------ 1302| 83| switch (Mnemonic[0]) { 1303| 83| default: break; ------------------ | Branch (1303:5): [True: 83, False: 0] ------------------ 1304| 83| case 'q': // 1 string to match. ------------------ | Branch (1304:5): [True: 0, False: 83] ------------------ 1305| 0| if (memcmp(Mnemonic.data()+1, "subaddx", 7)) ------------------ | Branch (1305:11): [True: 0, False: 0] ------------------ 1306| 0| break; 1307| 0| Mnemonic = "qsax"; // "qsubaddx" 1308| 0| return; 1309| 0| case 's': // 2 strings to match. ------------------ | Branch (1309:5): [True: 0, False: 83] ------------------ 1310| 0| switch (Mnemonic[1]) { 1311| 0| default: break; ------------------ | Branch (1311:7): [True: 0, False: 0] ------------------ 1312| 0| case 'a': // 1 string to match. ------------------ | Branch (1312:7): [True: 0, False: 0] ------------------ 1313| 0| if (memcmp(Mnemonic.data()+2, "ddsubx", 6)) ------------------ | Branch (1313:13): [True: 0, False: 0] ------------------ 1314| 0| break; 1315| 0| Mnemonic = "sasx"; // "saddsubx" 1316| 0| return; 1317| 0| case 's': // 1 string to match. ------------------ | Branch (1317:7): [True: 0, False: 0] ------------------ 1318| 0| if (memcmp(Mnemonic.data()+2, "ubaddx", 6)) ------------------ | Branch (1318:13): [True: 0, False: 0] ------------------ 1319| 0| break; 1320| 0| Mnemonic = "ssax"; // "ssubaddx" 1321| 0| return; 1322| 0| } 1323| 0| break; 1324| 0| case 'u': // 2 strings to match. ------------------ | Branch (1324:5): [True: 0, False: 83] ------------------ 1325| 0| switch (Mnemonic[1]) { 1326| 0| default: break; ------------------ | Branch (1326:7): [True: 0, False: 0] ------------------ 1327| 0| case 'a': // 1 string to match. ------------------ | Branch (1327:7): [True: 0, False: 0] ------------------ 1328| 0| if (memcmp(Mnemonic.data()+2, "ddsubx", 6)) ------------------ | Branch (1328:13): [True: 0, False: 0] ------------------ 1329| 0| break; 1330| 0| Mnemonic = "uasx"; // "uaddsubx" 1331| 0| return; 1332| 0| case 's': // 1 string to match. ------------------ | Branch (1332:7): [True: 0, False: 0] ------------------ 1333| 0| if (memcmp(Mnemonic.data()+2, "ubaddx", 6)) ------------------ | Branch (1333:13): [True: 0, False: 0] ------------------ 1334| 0| break; 1335| 0| Mnemonic = "usax"; // "usubaddx" 1336| 0| return; 1337| 0| } 1338| 0| break; 1339| 83| } 1340| 83| break; 1341| 128| case 9: // 8 strings to match. ------------------ | Branch (1341:3): [True: 128, False: 5.59k] ------------------ 1342| 128| switch (Mnemonic[0]) { 1343| 128| default: break; ------------------ | Branch (1343:5): [True: 128, False: 0] ------------------ 1344| 128| case 's': // 2 strings to match. ------------------ | Branch (1344:5): [True: 0, False: 128] ------------------ 1345| 0| if (Mnemonic[1] != 'h') ------------------ | Branch (1345:11): [True: 0, False: 0] ------------------ 1346| 0| break; 1347| 0| switch (Mnemonic[2]) { 1348| 0| default: break; ------------------ | Branch (1348:7): [True: 0, False: 0] ------------------ 1349| 0| case 'a': // 1 string to match. ------------------ | Branch (1349:7): [True: 0, False: 0] ------------------ 1350| 0| if (memcmp(Mnemonic.data()+3, "ddsubx", 6)) ------------------ | Branch (1350:13): [True: 0, False: 0] ------------------ 1351| 0| break; 1352| 0| Mnemonic = "shasx"; // "shaddsubx" 1353| 0| return; 1354| 0| case 's': // 1 string to match. ------------------ | Branch (1354:7): [True: 0, False: 0] ------------------ 1355| 0| if (memcmp(Mnemonic.data()+3, "ubaddx", 6)) ------------------ | Branch (1355:13): [True: 0, False: 0] ------------------ 1356| 0| break; 1357| 0| Mnemonic = "shsax"; // "shsubaddx" 1358| 0| return; 1359| 0| } 1360| 0| break; 1361| 0| case 'u': // 4 strings to match. ------------------ | Branch (1361:5): [True: 0, False: 128] ------------------ 1362| 0| switch (Mnemonic[1]) { 1363| 0| default: break; ------------------ | Branch (1363:7): [True: 0, False: 0] ------------------ 1364| 0| case 'h': // 2 strings to match. ------------------ | Branch (1364:7): [True: 0, False: 0] ------------------ 1365| 0| switch (Mnemonic[2]) { 1366| 0| default: break; ------------------ | Branch (1366:9): [True: 0, False: 0] ------------------ 1367| 0| case 'a': // 1 string to match. ------------------ | Branch (1367:9): [True: 0, False: 0] ------------------ 1368| 0| if (memcmp(Mnemonic.data()+3, "ddsubx", 6)) ------------------ | Branch (1368:15): [True: 0, False: 0] ------------------ 1369| 0| break; 1370| 0| Mnemonic = "uhasx"; // "uhaddsubx" 1371| 0| return; 1372| 0| case 's': // 1 string to match. ------------------ | Branch (1372:9): [True: 0, False: 0] ------------------ 1373| 0| if (memcmp(Mnemonic.data()+3, "ubaddx", 6)) ------------------ | Branch (1373:15): [True: 0, False: 0] ------------------ 1374| 0| break; 1375| 0| Mnemonic = "uhsax"; // "uhsubaddx" 1376| 0| return; 1377| 0| } 1378| 0| break; 1379| 0| case 'q': // 2 strings to match. ------------------ | Branch (1379:7): [True: 0, False: 0] ------------------ 1380| 0| switch (Mnemonic[2]) { 1381| 0| default: break; ------------------ | Branch (1381:9): [True: 0, False: 0] ------------------ 1382| 0| case 'a': // 1 string to match. ------------------ | Branch (1382:9): [True: 0, False: 0] ------------------ 1383| 0| if (memcmp(Mnemonic.data()+3, "ddsubx", 6)) ------------------ | Branch (1383:15): [True: 0, False: 0] ------------------ 1384| 0| break; 1385| 0| Mnemonic = "uqasx"; // "uqaddsubx" 1386| 0| return; 1387| 0| case 's': // 1 string to match. ------------------ | Branch (1387:9): [True: 0, False: 0] ------------------ 1388| 0| if (memcmp(Mnemonic.data()+3, "ubaddx", 6)) ------------------ | Branch (1388:15): [True: 0, False: 0] ------------------ 1389| 0| break; 1390| 0| Mnemonic = "uqsax"; // "uqsubaddx" 1391| 0| return; 1392| 0| } 1393| 0| break; 1394| 0| } 1395| 0| break; 1396| 0| case 'v': // 2 strings to match. ------------------ | Branch (1396:5): [True: 0, False: 128] ------------------ 1397| 0| if (memcmp(Mnemonic.data()+1, "movq.f", 6)) ------------------ | Branch (1397:11): [True: 0, False: 0] ------------------ 1398| 0| break; 1399| 0| switch (Mnemonic[7]) { 1400| 0| default: break; ------------------ | Branch (1400:7): [True: 0, False: 0] ------------------ 1401| 0| case '3': // 1 string to match. ------------------ | Branch (1401:7): [True: 0, False: 0] ------------------ 1402| 0| if (Mnemonic[8] != '2') ------------------ | Branch (1402:13): [True: 0, False: 0] ------------------ 1403| 0| break; 1404| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq.f32" ------------------ | Branch (1404:13): [True: 0, False: 0] ------------------ 1405| 0| Mnemonic = "vmov.f32"; 1406| 0| return; 1407| 0| case '6': // 1 string to match. ------------------ | Branch (1407:7): [True: 0, False: 0] ------------------ 1408| 0| if (Mnemonic[8] != '4') ------------------ | Branch (1408:13): [True: 0, False: 0] ------------------ 1409| 0| break; 1410| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq.f64" ------------------ | Branch (1410:13): [True: 0, False: 0] ------------------ 1411| 0| Mnemonic = "vmov.f64"; 1412| 0| return; 1413| 0| } 1414| 0| break; 1415| 128| } 1416| 128| break; 1417| 128| case 11: // 2 strings to match. ------------------ | Branch (1417:3): [True: 0, False: 5.72k] ------------------ 1418| 0| if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8)) ------------------ | Branch (1418:9): [True: 0, False: 0] ------------------ 1419| 0| break; 1420| 0| switch (Mnemonic[8]) { 1421| 0| default: break; ------------------ | Branch (1421:5): [True: 0, False: 0] ------------------ 1422| 0| case 'f': // 1 string to match. ------------------ | Branch (1422:5): [True: 0, False: 0] ------------------ 1423| 0| if (memcmp(Mnemonic.data()+9, "32", 2)) ------------------ | Branch (1423:11): [True: 0, False: 0] ------------------ 1424| 0| break; 1425| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vrecpeq.f32" ------------------ | Branch (1425:11): [True: 0, False: 0] ------------------ 1426| 0| Mnemonic = "vrecpe.f32"; 1427| 0| return; 1428| 0| case 'u': // 1 string to match. ------------------ | Branch (1428:5): [True: 0, False: 0] ------------------ 1429| 0| if (memcmp(Mnemonic.data()+9, "32", 2)) ------------------ | Branch (1429:11): [True: 0, False: 0] ------------------ 1430| 0| break; 1431| 0| if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vrecpeq.u32" ------------------ | Branch (1431:11): [True: 0, False: 0] ------------------ 1432| 0| Mnemonic = "vrecpe.u32"; 1433| 0| return; 1434| 0| } 1435| 0| break; 1436| 5.72k| } 1437| 5.72k|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser22MatchOperandParserImplERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEENS1_9StringRefERj: 11459| 22.0k| StringRef Mnemonic, unsigned int &ErrorCode) { 11460| | // Get the current feature set. 11461| 22.0k| uint64_t AvailableFeatures = getAvailableFeatures(); 11462| | 11463| | // Get the next operand index. 11464| 22.0k| unsigned NextOpNum = Operands.size() - 1; 11465| | // Search the table. 11466| 22.0k| auto MnemonicRange = 11467| 22.0k| std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), 11468| 22.0k| Mnemonic, LessOpcodeOperand()); 11469| | 11470| 22.0k| if (MnemonicRange.first == MnemonicRange.second) ------------------ | Branch (11470:7): [True: 6.08k, False: 15.9k] ------------------ 11471| 6.08k| return MatchOperand_NoMatch; 11472| | 11473| 15.9k| for (const OperandMatchEntry *it = MnemonicRange.first, 11474| 301k| *ie = MnemonicRange.second; it != ie; ++it) { ------------------ | Branch (11474:36): [True: 285k, False: 15.8k] ------------------ 11475| | // equal_range guarantees that instruction mnemonic matches. 11476| 285k| assert(Mnemonic == it->getMnemonic()); ------------------ | Branch (11476:5): [True: 285k, False: 0] ------------------ 11477| | 11478| | // check if the available features match 11479| 285k| if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) { ------------------ | Branch (11479:9): [True: 102k, False: 182k] ------------------ 11480| 102k| continue; 11481| 102k| } 11482| | 11483| | // check if the operand in question has a custom parser. 11484| 182k| if (!(it->OperandMask & (1 << NextOpNum))) ------------------ | Branch (11484:9): [True: 176k, False: 6.20k] ------------------ 11485| 176k| continue; 11486| | 11487| | // call custom parse method to handle the operand 11488| 6.20k| OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class, ErrorCode); 11489| 6.20k| if (Result != MatchOperand_NoMatch) ------------------ | Branch (11489:9): [True: 132, False: 6.07k] ------------------ 11490| 132| return Result; 11491| 6.20k| } 11492| | 11493| | // Okay, we had no match. 11494| 15.8k| return MatchOperand_NoMatch; 11495| 15.9k|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_117LessOpcodeOperandclERKNS_17OperandMatchEntryEN7llvm_ks9StringRefE: 10597| 208k| bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { 10598| 208k| return LHS.getMnemonic() < RHS; 10599| 208k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_117LessOpcodeOperandclEN7llvm_ks9StringRefERKNS_17OperandMatchEntryE: 10600| 149k| bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { 10601| 149k| return LHS < RHS.getMnemonic(); 10602| 149k| } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_117OperandMatchEntry11getMnemonicEv: 10589| 643k| StringRef getMnemonic() const { 10590| 643k| return StringRef(MnemonicTable + Mnemonic + 1, 10591| 643k| MnemonicTable[Mnemonic]); 10592| 643k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser21tryCustomParseOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEEjRj: 11344| 6.20k| unsigned MCK, unsigned int &ErrorCode) { 11345| | 11346| 6.20k| switch(MCK) { 11347| 0| case MCK_AM3Offset: ------------------ | Branch (11347:3): [True: 0, False: 6.20k] ------------------ 11348| 0| return parseAM3Offset(Operands, ErrorCode); 11349| 86| case MCK_BankedReg: ------------------ | Branch (11349:3): [True: 86, False: 6.12k] ------------------ 11350| 86| return parseBankedRegOperand(Operands, ErrorCode); 11351| 0| case MCK_Bitfield: ------------------ | Branch (11351:3): [True: 0, False: 6.20k] ------------------ 11352| 0| return parseBitfield(Operands, ErrorCode); 11353| 312| case MCK_CoprocNum: ------------------ | Branch (11353:3): [True: 312, False: 5.89k] ------------------ 11354| 312| return parseCoprocNumOperand(Operands, ErrorCode); 11355| 81| case MCK_CoprocOption: ------------------ | Branch (11355:3): [True: 81, False: 6.12k] ------------------ 11356| 81| return parseCoprocOptionOperand(Operands, ErrorCode); 11357| 324| case MCK_CoprocReg: ------------------ | Branch (11357:3): [True: 324, False: 5.88k] ------------------ 11358| 324| return parseCoprocRegOperand(Operands, ErrorCode); 11359| 48| case MCK_FPImm: ------------------ | Branch (11359:3): [True: 48, False: 6.16k] ------------------ 11360| 48| return parseFPImm(Operands, ErrorCode); 11361| 0| case MCK_InstSyncBarrierOpt: ------------------ | Branch (11361:3): [True: 0, False: 6.20k] ------------------ 11362| 0| return parseInstSyncBarrierOptOperand(Operands, ErrorCode); 11363| 187| case MCK_MSRMask: ------------------ | Branch (11363:3): [True: 187, False: 6.02k] ------------------ 11364| 187| return parseMSRMaskOperand(Operands, ErrorCode); 11365| 4| case MCK_MemBarrierOpt: ------------------ | Branch (11365:3): [True: 4, False: 6.20k] ------------------ 11366| 4| return parseMemBarrierOptOperand(Operands, ErrorCode); 11367| 75| case MCK_ModImm: ------------------ | Branch (11367:3): [True: 75, False: 6.13k] ------------------ 11368| 75| return parseModImm(Operands, ErrorCode); 11369| 0| case MCK_PKHASRImm: ------------------ | Branch (11369:3): [True: 0, False: 6.20k] ------------------ 11370| 0| return parsePKHASRImm(Operands, ErrorCode); 11371| 0| case MCK_PKHLSLImm: ------------------ | Branch (11371:3): [True: 0, False: 6.20k] ------------------ 11372| 0| return parsePKHLSLImm(Operands, ErrorCode); 11373| 0| case MCK_PostIdxReg: ------------------ | Branch (11373:3): [True: 0, False: 6.20k] ------------------ 11374| 0| return parsePostIdxReg(Operands, ErrorCode); 11375| 0| case MCK_PostIdxRegShifted: ------------------ | Branch (11375:3): [True: 0, False: 6.20k] ------------------ 11376| 0| return parsePostIdxReg(Operands, ErrorCode); 11377| 252| case MCK_ProcIFlags: ------------------ | Branch (11377:3): [True: 252, False: 5.95k] ------------------ 11378| 252| return parseProcIFlagsOperand(Operands, ErrorCode); 11379| 38| case MCK_RotImm: ------------------ | Branch (11379:3): [True: 38, False: 6.17k] ------------------ 11380| 38| return parseRotImm(Operands, ErrorCode); 11381| 0| case MCK_SetEndImm: ------------------ | Branch (11381:3): [True: 0, False: 6.20k] ------------------ 11382| 0| return parseSetEndImm(Operands, ErrorCode); 11383| 0| case MCK_ShifterImm: ------------------ | Branch (11383:3): [True: 0, False: 6.20k] ------------------ 11384| 0| return parseShifterImm(Operands, ErrorCode); 11385| 423| case MCK_VecListDPairAllLanes: ------------------ | Branch (11385:3): [True: 423, False: 5.78k] ------------------ 11386| 423| return parseVectorList(Operands, ErrorCode); 11387| 564| case MCK_VecListDPair: ------------------ | Branch (11387:3): [True: 564, False: 5.64k] ------------------ 11388| 564| return parseVectorList(Operands, ErrorCode); 11389| 0| case MCK_VecListDPairSpacedAllLanes: ------------------ | Branch (11389:3): [True: 0, False: 6.20k] ------------------ 11390| 0| return parseVectorList(Operands, ErrorCode); 11391| 0| case MCK_VecListDPairSpaced: ------------------ | Branch (11391:3): [True: 0, False: 6.20k] ------------------ 11392| 0| return parseVectorList(Operands, ErrorCode); 11393| 0| case MCK_VecListFourDAllLanes: ------------------ | Branch (11393:3): [True: 0, False: 6.20k] ------------------ 11394| 0| return parseVectorList(Operands, ErrorCode); 11395| 564| case MCK_VecListFourD: ------------------ | Branch (11395:3): [True: 564, False: 5.64k] ------------------ 11396| 564| return parseVectorList(Operands, ErrorCode); 11397| 0| case MCK_VecListFourDByteIndexed: ------------------ | Branch (11397:3): [True: 0, False: 6.20k] ------------------ 11398| 0| return parseVectorList(Operands, ErrorCode); 11399| 0| case MCK_VecListFourDHWordIndexed: ------------------ | Branch (11399:3): [True: 0, False: 6.20k] ------------------ 11400| 0| return parseVectorList(Operands, ErrorCode); 11401| 0| case MCK_VecListFourDWordIndexed: ------------------ | Branch (11401:3): [True: 0, False: 6.20k] ------------------ 11402| 0| return parseVectorList(Operands, ErrorCode); 11403| 0| case MCK_VecListFourQAllLanes: ------------------ | Branch (11403:3): [True: 0, False: 6.20k] ------------------ 11404| 0| return parseVectorList(Operands, ErrorCode); 11405| 0| case MCK_VecListFourQ: ------------------ | Branch (11405:3): [True: 0, False: 6.20k] ------------------ 11406| 0| return parseVectorList(Operands, ErrorCode); 11407| 0| case MCK_VecListFourQHWordIndexed: ------------------ | Branch (11407:3): [True: 0, False: 6.20k] ------------------ 11408| 0| return parseVectorList(Operands, ErrorCode); 11409| 0| case MCK_VecListFourQWordIndexed: ------------------ | Branch (11409:3): [True: 0, False: 6.20k] ------------------ 11410| 0| return parseVectorList(Operands, ErrorCode); 11411| 423| case MCK_VecListOneDAllLanes: ------------------ | Branch (11411:3): [True: 423, False: 5.78k] ------------------ 11412| 423| return parseVectorList(Operands, ErrorCode); 11413| 564| case MCK_VecListOneD: ------------------ | Branch (11413:3): [True: 564, False: 5.64k] ------------------ 11414| 564| return parseVectorList(Operands, ErrorCode); 11415| 141| case MCK_VecListOneDByteIndexed: ------------------ | Branch (11415:3): [True: 141, False: 6.06k] ------------------ 11416| 141| return parseVectorList(Operands, ErrorCode); 11417| 141| case MCK_VecListOneDHWordIndexed: ------------------ | Branch (11417:3): [True: 141, False: 6.06k] ------------------ 11418| 141| return parseVectorList(Operands, ErrorCode); 11419| 141| case MCK_VecListOneDWordIndexed: ------------------ | Branch (11419:3): [True: 141, False: 6.06k] ------------------ 11420| 141| return parseVectorList(Operands, ErrorCode); 11421| 207| case MCK_VecListThreeDAllLanes: ------------------ | Branch (11421:3): [True: 207, False: 6.00k] ------------------ 11422| 207| return parseVectorList(Operands, ErrorCode); 11423| 771| case MCK_VecListThreeD: ------------------ | Branch (11423:3): [True: 771, False: 5.43k] ------------------ 11424| 771| return parseVectorList(Operands, ErrorCode); 11425| 69| case MCK_VecListThreeDByteIndexed: ------------------ | Branch (11425:3): [True: 69, False: 6.13k] ------------------ 11426| 69| return parseVectorList(Operands, ErrorCode); 11427| 69| case MCK_VecListThreeDHWordIndexed: ------------------ | Branch (11427:3): [True: 69, False: 6.13k] ------------------ 11428| 69| return parseVectorList(Operands, ErrorCode); 11429| 69| case MCK_VecListThreeDWordIndexed: ------------------ | Branch (11429:3): [True: 69, False: 6.13k] ------------------ 11430| 69| return parseVectorList(Operands, ErrorCode); 11431| 207| case MCK_VecListThreeQAllLanes: ------------------ | Branch (11431:3): [True: 207, False: 6.00k] ------------------ 11432| 207| return parseVectorList(Operands, ErrorCode); 11433| 207| case MCK_VecListThreeQ: ------------------ | Branch (11433:3): [True: 207, False: 6.00k] ------------------ 11434| 207| return parseVectorList(Operands, ErrorCode); 11435| 69| case MCK_VecListThreeQHWordIndexed: ------------------ | Branch (11435:3): [True: 69, False: 6.13k] ------------------ 11436| 69| return parseVectorList(Operands, ErrorCode); 11437| 69| case MCK_VecListThreeQWordIndexed: ------------------ | Branch (11437:3): [True: 69, False: 6.13k] ------------------ 11438| 69| return parseVectorList(Operands, ErrorCode); 11439| 0| case MCK_VecListTwoDByteIndexed: ------------------ | Branch (11439:3): [True: 0, False: 6.20k] ------------------ 11440| 0| return parseVectorList(Operands, ErrorCode); 11441| 0| case MCK_VecListTwoDHWordIndexed: ------------------ | Branch (11441:3): [True: 0, False: 6.20k] ------------------ 11442| 0| return parseVectorList(Operands, ErrorCode); 11443| 0| case MCK_VecListTwoDWordIndexed: ------------------ | Branch (11443:3): [True: 0, False: 6.20k] ------------------ 11444| 0| return parseVectorList(Operands, ErrorCode); 11445| 0| case MCK_VecListTwoQHWordIndexed: ------------------ | Branch (11445:3): [True: 0, False: 6.20k] ------------------ 11446| 0| return parseVectorList(Operands, ErrorCode); 11447| 0| case MCK_VecListTwoQWordIndexed: ------------------ | Branch (11447:3): [True: 0, False: 6.20k] ------------------ 11448| 0| return parseVectorList(Operands, ErrorCode); 11449| 103| case MCK_ITCondCode: ------------------ | Branch (11449:3): [True: 103, False: 6.10k] ------------------ 11450| 103| return parseITCondCode(Operands, ErrorCode); 11451| 0| default: ------------------ | Branch (11451:3): [True: 0, False: 6.20k] ------------------ 11452| 0| return MatchOperand_NoMatch; 11453| 6.20k| } 11454| 0| return MatchOperand_NoMatch; 11455| 6.20k|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser20MatchInstructionImplERKN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERNS1_6MCInstERmbj: 10457| 2.34k| bool matchingInlineAsm, unsigned VariantID) { 10458| | // Eliminate obvious mismatches. 10459| 2.34k| if (Operands.size() > 19) { ------------------ | Branch (10459:7): [True: 22, False: 2.32k] ------------------ 10460| 22| ErrorInfo = 19; 10461| 22| return Match_InvalidOperand; 10462| 22| } 10463| | 10464| | // Get the current feature set. 10465| 2.32k| uint64_t AvailableFeatures = getAvailableFeatures(); 10466| | 10467| | // Get the instruction mnemonic, which is the first token. 10468| 2.32k| StringRef Mnemonic = ((ARMOperand&)*Operands[0]).getToken(); 10469| | 10470| | // Process all MnemonicAliases to remap the mnemonic. 10471| 2.32k| applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); 10472| | 10473| | // Some state to try to produce better error messages. 10474| 2.32k| bool HadMatchOtherThanFeatures = false; 10475| 2.32k| bool HadMatchOtherThanPredicate = false; 10476| 2.32k| unsigned RetCode = Match_InvalidOperand; 10477| 2.32k| uint64_t MissingFeatures = ~0ULL; 10478| | // Set ErrorInfo to the operand that mismatches if it is 10479| | // wrong for all instances of the instruction. 10480| 2.32k| ErrorInfo = ~0ULL; 10481| | // Find the appropriate table for this asm variant. 10482| 2.32k| const MatchEntry *Start, *End; 10483| 2.32k| switch (VariantID) { 10484| 0| default: llvm_unreachable("invalid variant!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ | Branch (10484:3): [True: 0, False: 2.32k] ------------------ 10485| 2.32k| case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; ------------------ | Branch (10485:3): [True: 2.32k, False: 0] ------------------ 10486| 2.32k| } 10487| | // Search the table. 10488| 2.32k| auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 10489| | 10490| | // Return a more specific error code if no mnemonics match. 10491| 2.32k| if (MnemonicRange.first == MnemonicRange.second) ------------------ | Branch (10491:7): [True: 45, False: 2.27k] ------------------ 10492| 45| return Match_MnemonicFail; 10493| | 10494| 2.27k| for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 10495| 11.6k| it != ie; ++it) { ------------------ | Branch (10495:8): [True: 11.6k, False: 13] ------------------ 10496| | // equal_range guarantees that instruction mnemonic matches. 10497| 11.6k| assert(Mnemonic == it->getMnemonic()); ------------------ | Branch (10497:5): [True: 11.6k, False: 0] ------------------ 10498| 11.6k| bool OperandsValid = true; 10499| 37.0k| for (unsigned i = 0; i != 18; ++i) { ------------------ | Branch (10499:26): [True: 37.0k, False: 0] ------------------ 10500| 37.0k| auto Formal = static_cast(it->Classes[i]); 10501| 37.0k| if (i+1 >= Operands.size()) { ------------------ | Branch (10501:11): [True: 3.16k, False: 33.8k] ------------------ 10502| 3.16k| OperandsValid = (Formal == InvalidMatchClass); 10503| 3.16k| if (!OperandsValid) ErrorInfo = i+1; ------------------ | Branch (10503:13): [True: 15, False: 3.14k] ------------------ 10504| 3.16k| break; 10505| 3.16k| } 10506| 33.8k| MCParsedAsmOperand &Actual = *Operands[i+1]; 10507| 33.8k| unsigned Diag = validateOperandClass(Actual, Formal); 10508| 33.8k| if (Diag == Match_Success) ------------------ | Branch (10508:11): [True: 25.3k, False: 8.50k] ------------------ 10509| 25.3k| continue; 10510| | // If the generic handler indicates an invalid operand 10511| | // failure, check for a special case. 10512| 8.50k| if (Diag == Match_InvalidOperand) { ------------------ | Branch (10512:11): [True: 8.50k, False: 0] ------------------ 10513| 8.50k| Diag = validateTargetOperandClass(Actual, Formal); 10514| 8.50k| if (Diag == Match_Success) ------------------ | Branch (10514:13): [True: 9, False: 8.49k] ------------------ 10515| 9| continue; 10516| 8.50k| } 10517| | // If this operand is broken for all of the instances of this 10518| | // mnemonic, keep track of it so we can report loc info. 10519| | // If we already had a match that only failed due to a 10520| | // target predicate, that diagnostic is preferred. 10521| 8.49k| if (!HadMatchOtherThanPredicate && ------------------ | Branch (10521:11): [True: 8.18k, False: 311] ------------------ 10522| 8.18k| (it == MnemonicRange.first || ErrorInfo <= i+1)) { ------------------ | Branch (10522:12): [True: 982, False: 7.20k] | Branch (10522:41): [True: 3.46k, False: 3.73k] ------------------ 10523| 4.44k| ErrorInfo = i+1; 10524| | // InvalidOperand is the default. Prefer specificity. 10525| 4.44k| if (Diag != Match_InvalidOperand) ------------------ | Branch (10525:13): [True: 0, False: 4.44k] ------------------ 10526| 0| RetCode = Diag; 10527| 4.44k| } 10528| | // Otherwise, just reject this instance of the mnemonic. 10529| 8.49k| OperandsValid = false; 10530| 8.49k| break; 10531| 8.50k| } 10532| | 10533| 11.6k| if (!OperandsValid) continue; ------------------ | Branch (10533:9): [True: 8.50k, False: 3.14k] ------------------ 10534| 3.14k| if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) { ------------------ | Branch (10534:9): [True: 727, False: 2.42k] ------------------ 10535| 727| HadMatchOtherThanFeatures = true; 10536| 727| uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures; 10537| 727| if (countPopulation(NewMissingFeatures) <= ------------------ | Branch (10537:11): [True: 727, False: 0] ------------------ 10538| 727| countPopulation(MissingFeatures)) 10539| 727| MissingFeatures = NewMissingFeatures; 10540| 727| continue; 10541| 727| } 10542| | 10543| 2.42k| Inst.clear(); 10544| | 10545| 2.42k| if (matchingInlineAsm) { ------------------ | Branch (10545:9): [True: 0, False: 2.42k] ------------------ 10546| 0| Inst.setOpcode(it->Opcode); 10547| 0| convertToMapAndConstraints(it->ConvertFn, Operands); 10548| 0| return Match_Success; 10549| 0| } 10550| | 10551| | // We have selected a definite instruction, convert the parsed 10552| | // operands into the appropriate MCInst. 10553| 2.42k| convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); 10554| | 10555| | // We have a potential match. Check the target predicate to 10556| | // handle any context sensitive constraints. 10557| 2.42k| unsigned MatchResult; 10558| 2.42k| if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { ------------------ | Branch (10558:9): [True: 157, False: 2.26k] ------------------ 10559| 157| Inst.clear(); 10560| 157| RetCode = MatchResult; 10561| 157| HadMatchOtherThanPredicate = true; 10562| 157| continue; 10563| 157| } 10564| | 10565| 2.26k| std::string Info; 10566| 2.26k| if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) { ------------------ | Branch (10566:9): [True: 0, False: 2.26k] ------------------ 10567| 0| SMLoc Loc = ((ARMOperand&)*Operands[0]).getStartLoc(); 10568| 0| getParser().Warning(Loc, Info, None); 10569| 0| } 10570| 2.26k| return Match_Success; 10571| 2.42k| } 10572| | 10573| | // Okay, we had no match. Try to return a useful error code. 10574| 13| if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) ------------------ | Branch (10574:7): [True: 0, False: 13] | Branch (10574:37): [True: 13, False: 0] ------------------ 10575| 13| return RetCode; 10576| | 10577| | // Missing feature matches return which features were missing 10578| 0| ErrorInfo = MissingFeatures; 10579| 0| return Match_MissingFeature; 10580| 13|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_110LessOpcodeclERKNS_10MatchEntryEN7llvm_ks9StringRefE: 6697| 27.5k| bool operator()(const MatchEntry &LHS, StringRef RHS) { 6698| 27.5k| return LHS.getMnemonic() < RHS; 6699| 27.5k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_110LessOpcodeclEN7llvm_ks9StringRefERKNS_10MatchEntryE: 6700| 23.0k| bool operator()(StringRef LHS, const MatchEntry &RHS) { 6701| 23.0k| return LHS < RHS.getMnemonic(); 6702| 23.0k| } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110MatchEntry11getMnemonicEv: 6689| 62.2k| StringRef getMnemonic() const { 6690| 62.2k| return StringRef(MnemonicTable + Mnemonic + 1, 6691| 62.2k| MnemonicTable[Mnemonic]); 6692| 62.2k| } ARMAsmParser.cpp:_ZL20validateOperandClassRN7llvm_ks18MCParsedAsmOperandEN12_GLOBAL__N_114MatchClassKindE: 5310| 33.8k|static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { 5311| 33.8k| ARMOperand &Operand = (ARMOperand&)GOp; 5312| 33.8k| if (Kind == InvalidMatchClass) ------------------ | Branch (5312:7): [True: 451, False: 33.4k] ------------------ 5313| 451| return MCTargetAsmParser::Match_InvalidOperand; 5314| | 5315| 33.4k| if (Operand.isToken()) ------------------ | Branch (5315:7): [True: 2.68k, False: 30.7k] ------------------ 5316| 2.68k| return isSubclass(matchTokenString(Operand.getToken()), Kind) ? ------------------ | Branch (5316:12): [True: 512, False: 2.17k] ------------------ 5317| 512| MCTargetAsmParser::Match_Success : 5318| 2.68k| MCTargetAsmParser::Match_InvalidOperand; 5319| | 5320| | // 'AM2OffsetImm' class 5321| 30.7k| if (Kind == MCK_AM2OffsetImm) { ------------------ | Branch (5321:7): [True: 0, False: 30.7k] ------------------ 5322| 0| if (Operand.isAM2OffsetImm()) ------------------ | Branch (5322:9): [True: 0, False: 0] ------------------ 5323| 0| return MCTargetAsmParser::Match_Success; 5324| 0| } 5325| | 5326| | // 'AM3Offset' class 5327| 30.7k| if (Kind == MCK_AM3Offset) { ------------------ | Branch (5327:7): [True: 0, False: 30.7k] ------------------ 5328| 0| if (Operand.isAM3Offset()) ------------------ | Branch (5328:9): [True: 0, False: 0] ------------------ 5329| 0| return MCTargetAsmParser::Match_Success; 5330| 0| } 5331| | 5332| | // 'AddrMode2' class 5333| 30.7k| if (Kind == MCK_AddrMode2) { ------------------ | Branch (5333:7): [True: 0, False: 30.7k] ------------------ 5334| 0| if (Operand.isAddrMode2()) ------------------ | Branch (5334:9): [True: 0, False: 0] ------------------ 5335| 0| return MCTargetAsmParser::Match_Success; 5336| 0| } 5337| | 5338| | // 'AddrMode3' class 5339| 30.7k| if (Kind == MCK_AddrMode3) { ------------------ | Branch (5339:7): [True: 0, False: 30.7k] ------------------ 5340| 0| if (Operand.isAddrMode3()) ------------------ | Branch (5340:9): [True: 0, False: 0] ------------------ 5341| 0| return MCTargetAsmParser::Match_Success; 5342| 0| } 5343| | 5344| | // 'AddrMode5' class 5345| 30.7k| if (Kind == MCK_AddrMode5) { ------------------ | Branch (5345:7): [True: 0, False: 30.7k] ------------------ 5346| 0| if (Operand.isAddrMode5()) ------------------ | Branch (5346:9): [True: 0, False: 0] ------------------ 5347| 0| return MCTargetAsmParser::Match_Success; 5348| 0| } 5349| | 5350| | // 'AddrMode5FP16' class 5351| 30.7k| if (Kind == MCK_AddrMode5FP16) { ------------------ | Branch (5351:7): [True: 0, False: 30.7k] ------------------ 5352| 0| if (Operand.isAddrMode5FP16()) ------------------ | Branch (5352:9): [True: 0, False: 0] ------------------ 5353| 0| return MCTargetAsmParser::Match_Success; 5354| 0| } 5355| | 5356| | // 'AlignedMemory16' class 5357| 30.7k| if (Kind == MCK_AlignedMemory16) { ------------------ | Branch (5357:7): [True: 0, False: 30.7k] ------------------ 5358| 0| if (Operand.isAlignedMemory16()) ------------------ | Branch (5358:9): [True: 0, False: 0] ------------------ 5359| 0| return MCTargetAsmParser::Match_Success; 5360| 0| return ARMAsmParser::Match_AlignedMemoryRequires16; 5361| 0| } 5362| | 5363| | // 'AlignedMemory32' class 5364| 30.7k| if (Kind == MCK_AlignedMemory32) { ------------------ | Branch (5364:7): [True: 0, False: 30.7k] ------------------ 5365| 0| if (Operand.isAlignedMemory32()) ------------------ | Branch (5365:9): [True: 0, False: 0] ------------------ 5366| 0| return MCTargetAsmParser::Match_Success; 5367| 0| return ARMAsmParser::Match_AlignedMemoryRequires32; 5368| 0| } 5369| | 5370| | // 'AlignedMemory64' class 5371| 30.7k| if (Kind == MCK_AlignedMemory64) { ------------------ | Branch (5371:7): [True: 0, False: 30.7k] ------------------ 5372| 0| if (Operand.isAlignedMemory64()) ------------------ | Branch (5372:9): [True: 0, False: 0] ------------------ 5373| 0| return MCTargetAsmParser::Match_Success; 5374| 0| return ARMAsmParser::Match_AlignedMemoryRequires64; 5375| 0| } 5376| | 5377| | // 'AlignedMemory64or128' class 5378| 30.7k| if (Kind == MCK_AlignedMemory64or128) { ------------------ | Branch (5378:7): [True: 0, False: 30.7k] ------------------ 5379| 0| if (Operand.isAlignedMemory64or128()) ------------------ | Branch (5379:9): [True: 0, False: 0] ------------------ 5380| 0| return MCTargetAsmParser::Match_Success; 5381| 0| return ARMAsmParser::Match_AlignedMemoryRequires64or128; 5382| 0| } 5383| | 5384| | // 'AlignedMemory64or128or256' class 5385| 30.7k| if (Kind == MCK_AlignedMemory64or128or256) { ------------------ | Branch (5385:7): [True: 0, False: 30.7k] ------------------ 5386| 0| if (Operand.isAlignedMemory64or128or256()) ------------------ | Branch (5386:9): [True: 0, False: 0] ------------------ 5387| 0| return MCTargetAsmParser::Match_Success; 5388| 0| return ARMAsmParser::Match_AlignedMemoryRequires64or128or256; 5389| 0| } 5390| | 5391| | // 'AlignedMemoryNone' class 5392| 30.7k| if (Kind == MCK_AlignedMemoryNone) { ------------------ | Branch (5392:7): [True: 0, False: 30.7k] ------------------ 5393| 0| if (Operand.isAlignedMemoryNone()) ------------------ | Branch (5393:9): [True: 0, False: 0] ------------------ 5394| 0| return MCTargetAsmParser::Match_Success; 5395| 0| return ARMAsmParser::Match_AlignedMemoryRequiresNone; 5396| 0| } 5397| | 5398| | // 'AlignedMemory' class 5399| 30.7k| if (Kind == MCK_AlignedMemory) { ------------------ | Branch (5399:7): [True: 0, False: 30.7k] ------------------ 5400| 0| if (Operand.isAlignedMemory()) ------------------ | Branch (5400:9): [True: 0, False: 0] ------------------ 5401| 0| return MCTargetAsmParser::Match_Success; 5402| 0| } 5403| | 5404| | // 'DupAlignedMemory16' class 5405| 30.7k| if (Kind == MCK_DupAlignedMemory16) { ------------------ | Branch (5405:7): [True: 0, False: 30.7k] ------------------ 5406| 0| if (Operand.isDupAlignedMemory16()) ------------------ | Branch (5406:9): [True: 0, False: 0] ------------------ 5407| 0| return MCTargetAsmParser::Match_Success; 5408| 0| return ARMAsmParser::Match_DupAlignedMemoryRequires16; 5409| 0| } 5410| | 5411| | // 'DupAlignedMemory32' class 5412| 30.7k| if (Kind == MCK_DupAlignedMemory32) { ------------------ | Branch (5412:7): [True: 0, False: 30.7k] ------------------ 5413| 0| if (Operand.isDupAlignedMemory32()) ------------------ | Branch (5413:9): [True: 0, False: 0] ------------------ 5414| 0| return MCTargetAsmParser::Match_Success; 5415| 0| return ARMAsmParser::Match_DupAlignedMemoryRequires32; 5416| 0| } 5417| | 5418| | // 'DupAlignedMemory64' class 5419| 30.7k| if (Kind == MCK_DupAlignedMemory64) { ------------------ | Branch (5419:7): [True: 0, False: 30.7k] ------------------ 5420| 0| if (Operand.isDupAlignedMemory64()) ------------------ | Branch (5420:9): [True: 0, False: 0] ------------------ 5421| 0| return MCTargetAsmParser::Match_Success; 5422| 0| return ARMAsmParser::Match_DupAlignedMemoryRequires64; 5423| 0| } 5424| | 5425| | // 'DupAlignedMemory64or128' class 5426| 30.7k| if (Kind == MCK_DupAlignedMemory64or128) { ------------------ | Branch (5426:7): [True: 0, False: 30.7k] ------------------ 5427| 0| if (Operand.isDupAlignedMemory64or128()) ------------------ | Branch (5427:9): [True: 0, False: 0] ------------------ 5428| 0| return MCTargetAsmParser::Match_Success; 5429| 0| return ARMAsmParser::Match_DupAlignedMemoryRequires64or128; 5430| 0| } 5431| | 5432| | // 'DupAlignedMemoryNone' class 5433| 30.7k| if (Kind == MCK_DupAlignedMemoryNone) { ------------------ | Branch (5433:7): [True: 0, False: 30.7k] ------------------ 5434| 0| if (Operand.isDupAlignedMemoryNone()) ------------------ | Branch (5434:9): [True: 0, False: 0] ------------------ 5435| 0| return MCTargetAsmParser::Match_Success; 5436| 0| return ARMAsmParser::Match_DupAlignedMemoryRequiresNone; 5437| 0| } 5438| | 5439| | // 'AdrLabel' class 5440| 30.7k| if (Kind == MCK_AdrLabel) { ------------------ | Branch (5440:7): [True: 0, False: 30.7k] ------------------ 5441| 0| if (Operand.isAdrLabel()) ------------------ | Branch (5441:9): [True: 0, False: 0] ------------------ 5442| 0| return MCTargetAsmParser::Match_Success; 5443| 0| } 5444| | 5445| | // 'BankedReg' class 5446| 30.7k| if (Kind == MCK_BankedReg) { ------------------ | Branch (5446:7): [True: 142, False: 30.5k] ------------------ 5447| 142| if (Operand.isBankedReg()) ------------------ | Branch (5447:9): [True: 0, False: 142] ------------------ 5448| 0| return MCTargetAsmParser::Match_Success; 5449| 142| } 5450| | 5451| | // 'Bitfield' class 5452| 30.7k| if (Kind == MCK_Bitfield) { ------------------ | Branch (5452:7): [True: 0, False: 30.7k] ------------------ 5453| 0| if (Operand.isBitfield()) ------------------ | Branch (5453:9): [True: 0, False: 0] ------------------ 5454| 0| return MCTargetAsmParser::Match_Success; 5455| 0| } 5456| | 5457| | // 'CCOut' class 5458| 30.7k| if (Kind == MCK_CCOut) { ------------------ | Branch (5458:7): [True: 6.51k, False: 24.2k] ------------------ 5459| 6.51k| if (Operand.isCCOut()) ------------------ | Branch (5459:9): [True: 6.10k, False: 413] ------------------ 5460| 6.10k| return MCTargetAsmParser::Match_Success; 5461| 6.51k| } 5462| | 5463| | // 'CondCode' class 5464| 24.6k| if (Kind == MCK_CondCode) { ------------------ | Branch (5464:7): [True: 11.0k, False: 13.5k] ------------------ 5465| 11.0k| if (Operand.isCondCode()) ------------------ | Branch (5465:9): [True: 9.08k, False: 1.96k] ------------------ 5466| 9.08k| return MCTargetAsmParser::Match_Success; 5467| 11.0k| } 5468| | 5469| | // 'CoprocNum' class 5470| 15.5k| if (Kind == MCK_CoprocNum) { ------------------ | Branch (5470:7): [True: 0, False: 15.5k] ------------------ 5471| 0| if (Operand.isCoprocNum()) ------------------ | Branch (5471:9): [True: 0, False: 0] ------------------ 5472| 0| return MCTargetAsmParser::Match_Success; 5473| 0| } 5474| | 5475| | // 'CoprocOption' class 5476| 15.5k| if (Kind == MCK_CoprocOption) { ------------------ | Branch (5476:7): [True: 0, False: 15.5k] ------------------ 5477| 0| if (Operand.isCoprocOption()) ------------------ | Branch (5477:9): [True: 0, False: 0] ------------------ 5478| 0| return MCTargetAsmParser::Match_Success; 5479| 0| } 5480| | 5481| | // 'CoprocReg' class 5482| 15.5k| if (Kind == MCK_CoprocReg) { ------------------ | Branch (5482:7): [True: 0, False: 15.5k] ------------------ 5483| 0| if (Operand.isCoprocReg()) ------------------ | Branch (5483:9): [True: 0, False: 0] ------------------ 5484| 0| return MCTargetAsmParser::Match_Success; 5485| 0| } 5486| | 5487| | // 'DPRRegList' class 5488| 15.5k| if (Kind == MCK_DPRRegList) { ------------------ | Branch (5488:7): [True: 0, False: 15.5k] ------------------ 5489| 0| if (Operand.isDPRRegList()) ------------------ | Branch (5489:9): [True: 0, False: 0] ------------------ 5490| 0| return MCTargetAsmParser::Match_Success; 5491| 0| } 5492| | 5493| | // 'FPImm' class 5494| 15.5k| if (Kind == MCK_FPImm) { ------------------ | Branch (5494:7): [True: 0, False: 15.5k] ------------------ 5495| 0| if (Operand.isFPImm()) ------------------ | Branch (5495:9): [True: 0, False: 0] ------------------ 5496| 0| return MCTargetAsmParser::Match_Success; 5497| 0| } 5498| | 5499| | // 'Imm0_15' class 5500| 15.5k| if (Kind == MCK_Imm0_15) { ------------------ | Branch (5500:7): [True: 0, False: 15.5k] ------------------ 5501| 0| if (Operand.isImm0_15()) ------------------ | Branch (5501:9): [True: 0, False: 0] ------------------ 5502| 0| return MCTargetAsmParser::Match_Success; 5503| 0| return ARMAsmParser::Match_ImmRange0_15; 5504| 0| } 5505| | 5506| | // 'Imm0_1' class 5507| 15.5k| if (Kind == MCK_Imm0_1) { ------------------ | Branch (5507:7): [True: 0, False: 15.5k] ------------------ 5508| 0| if (Operand.isImm0_1()) ------------------ | Branch (5508:9): [True: 0, False: 0] ------------------ 5509| 0| return MCTargetAsmParser::Match_Success; 5510| 0| } 5511| | 5512| | // 'Imm0_239' class 5513| 15.5k| if (Kind == MCK_Imm0_239) { ------------------ | Branch (5513:7): [True: 0, False: 15.5k] ------------------ 5514| 0| if (Operand.isImm0_239()) ------------------ | Branch (5514:9): [True: 0, False: 0] ------------------ 5515| 0| return MCTargetAsmParser::Match_Success; 5516| 0| return ARMAsmParser::Match_ImmRange0_239; 5517| 0| } 5518| | 5519| | // 'Imm0_255' class 5520| 15.5k| if (Kind == MCK_Imm0_255) { ------------------ | Branch (5520:7): [True: 220, False: 15.3k] ------------------ 5521| 220| if (Operand.isImm0_255()) ------------------ | Branch (5521:9): [True: 128, False: 92] ------------------ 5522| 128| return MCTargetAsmParser::Match_Success; 5523| 220| } 5524| | 5525| | // 'Imm0_31' class 5526| 15.4k| if (Kind == MCK_Imm0_31) { ------------------ | Branch (5526:7): [True: 387, False: 15.0k] ------------------ 5527| 387| if (Operand.isImm0_31()) ------------------ | Branch (5527:9): [True: 387, False: 0] ------------------ 5528| 387| return MCTargetAsmParser::Match_Success; 5529| 387| } 5530| | 5531| | // 'Imm0_32' class 5532| 15.0k| if (Kind == MCK_Imm0_32) { ------------------ | Branch (5532:7): [True: 2, False: 15.0k] ------------------ 5533| 2| if (Operand.isImm0_32()) ------------------ | Branch (5533:9): [True: 0, False: 2] ------------------ 5534| 0| return MCTargetAsmParser::Match_Success; 5535| 2| } 5536| | 5537| | // 'Imm0_3' class 5538| 15.0k| if (Kind == MCK_Imm0_3) { ------------------ | Branch (5538:7): [True: 0, False: 15.0k] ------------------ 5539| 0| if (Operand.isImm0_3()) ------------------ | Branch (5539:9): [True: 0, False: 0] ------------------ 5540| 0| return MCTargetAsmParser::Match_Success; 5541| 0| } 5542| | 5543| | // 'Imm0_63' class 5544| 15.0k| if (Kind == MCK_Imm0_63) { ------------------ | Branch (5544:7): [True: 0, False: 15.0k] ------------------ 5545| 0| if (Operand.isImm0_63()) ------------------ | Branch (5545:9): [True: 0, False: 0] ------------------ 5546| 0| return MCTargetAsmParser::Match_Success; 5547| 0| } 5548| | 5549| | // 'Imm0_65535' class 5550| 15.0k| if (Kind == MCK_Imm0_65535) { ------------------ | Branch (5550:7): [True: 0, False: 15.0k] ------------------ 5551| 0| if (Operand.isImm0_65535()) ------------------ | Branch (5551:9): [True: 0, False: 0] ------------------ 5552| 0| return MCTargetAsmParser::Match_Success; 5553| 0| } 5554| | 5555| | // 'Imm0_65535Expr' class 5556| 15.0k| if (Kind == MCK_Imm0_65535Expr) { ------------------ | Branch (5556:7): [True: 0, False: 15.0k] ------------------ 5557| 0| if (Operand.isImm0_65535Expr()) ------------------ | Branch (5557:9): [True: 0, False: 0] ------------------ 5558| 0| return MCTargetAsmParser::Match_Success; 5559| 0| } 5560| | 5561| | // 'Imm0_7' class 5562| 15.0k| if (Kind == MCK_Imm0_7) { ------------------ | Branch (5562:7): [True: 30, False: 15.0k] ------------------ 5563| 30| if (Operand.isImm0_7()) ------------------ | Branch (5563:9): [True: 27, False: 3] ------------------ 5564| 27| return MCTargetAsmParser::Match_Success; 5565| 30| } 5566| | 5567| | // 'Imm16' class 5568| 15.0k| if (Kind == MCK_Imm16) { ------------------ | Branch (5568:7): [True: 0, False: 15.0k] ------------------ 5569| 0| if (Operand.isImm16()) ------------------ | Branch (5569:9): [True: 0, False: 0] ------------------ 5570| 0| return MCTargetAsmParser::Match_Success; 5571| 0| } 5572| | 5573| | // 'Imm1_15' class 5574| 15.0k| if (Kind == MCK_Imm1_15) { ------------------ | Branch (5574:7): [True: 0, False: 15.0k] ------------------ 5575| 0| if (Operand.isImm1_15()) ------------------ | Branch (5575:9): [True: 0, False: 0] ------------------ 5576| 0| return MCTargetAsmParser::Match_Success; 5577| 0| } 5578| | 5579| | // 'Imm1_16' class 5580| 15.0k| if (Kind == MCK_Imm1_16) { ------------------ | Branch (5580:7): [True: 0, False: 15.0k] ------------------ 5581| 0| if (Operand.isImm1_16()) ------------------ | Branch (5581:9): [True: 0, False: 0] ------------------ 5582| 0| return MCTargetAsmParser::Match_Success; 5583| 0| } 5584| | 5585| | // 'Imm1_31' class 5586| 15.0k| if (Kind == MCK_Imm1_31) { ------------------ | Branch (5586:7): [True: 0, False: 15.0k] ------------------ 5587| 0| if (Operand.isImm1_31()) ------------------ | Branch (5587:9): [True: 0, False: 0] ------------------ 5588| 0| return MCTargetAsmParser::Match_Success; 5589| 0| } 5590| | 5591| | // 'Imm1_32' class 5592| 15.0k| if (Kind == MCK_Imm1_32) { ------------------ | Branch (5592:7): [True: 0, False: 15.0k] ------------------ 5593| 0| if (Operand.isImm1_32()) ------------------ | Branch (5593:9): [True: 0, False: 0] ------------------ 5594| 0| return MCTargetAsmParser::Match_Success; 5595| 0| } 5596| | 5597| | // 'Imm1_7' class 5598| 15.0k| if (Kind == MCK_Imm1_7) { ------------------ | Branch (5598:7): [True: 0, False: 15.0k] ------------------ 5599| 0| if (Operand.isImm1_7()) ------------------ | Branch (5599:9): [True: 0, False: 0] ------------------ 5600| 0| return MCTargetAsmParser::Match_Success; 5601| 0| } 5602| | 5603| | // 'Imm24bit' class 5604| 15.0k| if (Kind == MCK_Imm24bit) { ------------------ | Branch (5604:7): [True: 0, False: 15.0k] ------------------ 5605| 0| if (Operand.isImm24bit()) ------------------ | Branch (5605:9): [True: 0, False: 0] ------------------ 5606| 0| return MCTargetAsmParser::Match_Success; 5607| 0| } 5608| | 5609| | // 'Imm256_65535Expr' class 5610| 15.0k| if (Kind == MCK_Imm256_65535Expr) { ------------------ | Branch (5610:7): [True: 0, False: 15.0k] ------------------ 5611| 0| if (Operand.isImm256_65535Expr()) ------------------ | Branch (5611:9): [True: 0, False: 0] ------------------ 5612| 0| return MCTargetAsmParser::Match_Success; 5613| 0| } 5614| | 5615| | // 'Imm32' class 5616| 15.0k| if (Kind == MCK_Imm32) { ------------------ | Branch (5616:7): [True: 0, False: 15.0k] ------------------ 5617| 0| if (Operand.isImm32()) ------------------ | Branch (5617:9): [True: 0, False: 0] ------------------ 5618| 0| return MCTargetAsmParser::Match_Success; 5619| 0| } 5620| | 5621| | // 'Imm8' class 5622| 15.0k| if (Kind == MCK_Imm8) { ------------------ | Branch (5622:7): [True: 0, False: 15.0k] ------------------ 5623| 0| if (Operand.isImm8()) ------------------ | Branch (5623:9): [True: 0, False: 0] ------------------ 5624| 0| return MCTargetAsmParser::Match_Success; 5625| 0| } 5626| | 5627| | // 'Imm' class 5628| 15.0k| if (Kind == MCK_Imm) { ------------------ | Branch (5628:7): [True: 1.31k, False: 13.6k] ------------------ 5629| 1.31k| if (Operand.isImm()) ------------------ | Branch (5629:9): [True: 1.23k, False: 88] ------------------ 5630| 1.23k| return MCTargetAsmParser::Match_Success; 5631| 1.31k| } 5632| | 5633| | // 'InstSyncBarrierOpt' class 5634| 13.7k| if (Kind == MCK_InstSyncBarrierOpt) { ------------------ | Branch (5634:7): [True: 0, False: 13.7k] ------------------ 5635| 0| if (Operand.isInstSyncBarrierOpt()) ------------------ | Branch (5635:9): [True: 0, False: 0] ------------------ 5636| 0| return MCTargetAsmParser::Match_Success; 5637| 0| } 5638| | 5639| | // 'MSRMask' class 5640| 13.7k| if (Kind == MCK_MSRMask) { ------------------ | Branch (5640:7): [True: 89, False: 13.6k] ------------------ 5641| 89| if (Operand.isMSRMask()) ------------------ | Branch (5641:9): [True: 65, False: 24] ------------------ 5642| 65| return MCTargetAsmParser::Match_Success; 5643| 89| } 5644| | 5645| | // 'MemBarrierOpt' class 5646| 13.7k| if (Kind == MCK_MemBarrierOpt) { ------------------ | Branch (5646:7): [True: 6, False: 13.7k] ------------------ 5647| 6| if (Operand.isMemBarrierOpt()) ------------------ | Branch (5647:9): [True: 0, False: 6] ------------------ 5648| 0| return MCTargetAsmParser::Match_Success; 5649| 6| } 5650| | 5651| | // 'MemImm0_1020s4Offset' class 5652| 13.7k| if (Kind == MCK_MemImm0_1020s4Offset) { ------------------ | Branch (5652:7): [True: 0, False: 13.7k] ------------------ 5653| 0| if (Operand.isMemImm0_1020s4Offset()) ------------------ | Branch (5653:9): [True: 0, False: 0] ------------------ 5654| 0| return MCTargetAsmParser::Match_Success; 5655| 0| } 5656| | 5657| | // 'MemImm12Offset' class 5658| 13.7k| if (Kind == MCK_MemImm12Offset) { ------------------ | Branch (5658:7): [True: 13, False: 13.6k] ------------------ 5659| 13| if (Operand.isMemImm12Offset()) ------------------ | Branch (5659:9): [True: 0, False: 13] ------------------ 5660| 0| return MCTargetAsmParser::Match_Success; 5661| 13| } 5662| | 5663| | // 'MemImm8Offset' class 5664| 13.7k| if (Kind == MCK_MemImm8Offset) { ------------------ | Branch (5664:7): [True: 0, False: 13.7k] ------------------ 5665| 0| if (Operand.isMemImm8Offset()) ------------------ | Branch (5665:9): [True: 0, False: 0] ------------------ 5666| 0| return MCTargetAsmParser::Match_Success; 5667| 0| } 5668| | 5669| | // 'MemImm8s4Offset' class 5670| 13.7k| if (Kind == MCK_MemImm8s4Offset) { ------------------ | Branch (5670:7): [True: 0, False: 13.7k] ------------------ 5671| 0| if (Operand.isMemImm8s4Offset()) ------------------ | Branch (5671:9): [True: 0, False: 0] ------------------ 5672| 0| return MCTargetAsmParser::Match_Success; 5673| 0| } 5674| | 5675| | // 'MemNegImm8Offset' class 5676| 13.7k| if (Kind == MCK_MemNegImm8Offset) { ------------------ | Branch (5676:7): [True: 0, False: 13.7k] ------------------ 5677| 0| if (Operand.isMemNegImm8Offset()) ------------------ | Branch (5677:9): [True: 0, False: 0] ------------------ 5678| 0| return MCTargetAsmParser::Match_Success; 5679| 0| } 5680| | 5681| | // 'MemNoOffset' class 5682| 13.7k| if (Kind == MCK_MemNoOffset) { ------------------ | Branch (5682:7): [True: 0, False: 13.7k] ------------------ 5683| 0| if (Operand.isMemNoOffset()) ------------------ | Branch (5683:9): [True: 0, False: 0] ------------------ 5684| 0| return MCTargetAsmParser::Match_Success; 5685| 0| } 5686| | 5687| | // 'MemPosImm8Offset' class 5688| 13.7k| if (Kind == MCK_MemPosImm8Offset) { ------------------ | Branch (5688:7): [True: 0, False: 13.7k] ------------------ 5689| 0| if (Operand.isMemPosImm8Offset()) ------------------ | Branch (5689:9): [True: 0, False: 0] ------------------ 5690| 0| return MCTargetAsmParser::Match_Success; 5691| 0| } 5692| | 5693| | // 'MemRegOffset' class 5694| 13.7k| if (Kind == MCK_MemRegOffset) { ------------------ | Branch (5694:7): [True: 13, False: 13.6k] ------------------ 5695| 13| if (Operand.isMemRegOffset()) ------------------ | Branch (5695:9): [True: 0, False: 13] ------------------ 5696| 0| return MCTargetAsmParser::Match_Success; 5697| 13| } 5698| | 5699| | // 'ModImm' class 5700| 13.7k| if (Kind == MCK_ModImm) { ------------------ | Branch (5700:7): [True: 136, False: 13.5k] ------------------ 5701| 136| if (Operand.isModImm()) ------------------ | Branch (5701:9): [True: 0, False: 136] ------------------ 5702| 0| return MCTargetAsmParser::Match_Success; 5703| 136| } 5704| | 5705| | // 'ModImmNeg' class 5706| 13.7k| if (Kind == MCK_ModImmNeg) { ------------------ | Branch (5706:7): [True: 71, False: 13.6k] ------------------ 5707| 71| if (Operand.isModImmNeg()) ------------------ | Branch (5707:9): [True: 0, False: 71] ------------------ 5708| 0| return MCTargetAsmParser::Match_Success; 5709| 71| } 5710| | 5711| | // 'ModImmNot' class 5712| 13.7k| if (Kind == MCK_ModImmNot) { ------------------ | Branch (5712:7): [True: 0, False: 13.7k] ------------------ 5713| 0| if (Operand.isModImmNot()) ------------------ | Branch (5713:9): [True: 0, False: 0] ------------------ 5714| 0| return MCTargetAsmParser::Match_Success; 5715| 0| } 5716| | 5717| | // 'PKHASRImm' class 5718| 13.7k| if (Kind == MCK_PKHASRImm) { ------------------ | Branch (5718:7): [True: 0, False: 13.7k] ------------------ 5719| 0| if (Operand.isPKHASRImm()) ------------------ | Branch (5719:9): [True: 0, False: 0] ------------------ 5720| 0| return MCTargetAsmParser::Match_Success; 5721| 0| } 5722| | 5723| | // 'PKHLSLImm' class 5724| 13.7k| if (Kind == MCK_PKHLSLImm) { ------------------ | Branch (5724:7): [True: 0, False: 13.7k] ------------------ 5725| 0| if (Operand.isPKHLSLImm()) ------------------ | Branch (5725:9): [True: 0, False: 0] ------------------ 5726| 0| return MCTargetAsmParser::Match_Success; 5727| 0| } 5728| | 5729| | // 'PostIdxImm8' class 5730| 13.7k| if (Kind == MCK_PostIdxImm8) { ------------------ | Branch (5730:7): [True: 0, False: 13.7k] ------------------ 5731| 0| if (Operand.isPostIdxImm8()) ------------------ | Branch (5731:9): [True: 0, False: 0] ------------------ 5732| 0| return MCTargetAsmParser::Match_Success; 5733| 0| } 5734| | 5735| | // 'PostIdxImm8s4' class 5736| 13.7k| if (Kind == MCK_PostIdxImm8s4) { ------------------ | Branch (5736:7): [True: 0, False: 13.7k] ------------------ 5737| 0| if (Operand.isPostIdxImm8s4()) ------------------ | Branch (5737:9): [True: 0, False: 0] ------------------ 5738| 0| return MCTargetAsmParser::Match_Success; 5739| 0| } 5740| | 5741| | // 'PostIdxReg' class 5742| 13.7k| if (Kind == MCK_PostIdxReg) { ------------------ | Branch (5742:7): [True: 0, False: 13.7k] ------------------ 5743| 0| if (Operand.isPostIdxReg()) ------------------ | Branch (5743:9): [True: 0, False: 0] ------------------ 5744| 0| return MCTargetAsmParser::Match_Success; 5745| 0| } 5746| | 5747| | // 'PostIdxRegShifted' class 5748| 13.7k| if (Kind == MCK_PostIdxRegShifted) { ------------------ | Branch (5748:7): [True: 0, False: 13.7k] ------------------ 5749| 0| if (Operand.isPostIdxRegShifted()) ------------------ | Branch (5749:9): [True: 0, False: 0] ------------------ 5750| 0| return MCTargetAsmParser::Match_Success; 5751| 0| } 5752| | 5753| | // 'ProcIFlags' class 5754| 13.7k| if (Kind == MCK_ProcIFlags) { ------------------ | Branch (5754:7): [True: 0, False: 13.7k] ------------------ 5755| 0| if (Operand.isProcIFlags()) ------------------ | Branch (5755:9): [True: 0, False: 0] ------------------ 5756| 0| return MCTargetAsmParser::Match_Success; 5757| 0| } 5758| | 5759| | // 'RegList' class 5760| 13.7k| if (Kind == MCK_RegList) { ------------------ | Branch (5760:7): [True: 0, False: 13.7k] ------------------ 5761| 0| if (Operand.isRegList()) ------------------ | Branch (5761:9): [True: 0, False: 0] ------------------ 5762| 0| return MCTargetAsmParser::Match_Success; 5763| 0| } 5764| | 5765| | // 'RotImm' class 5766| 13.7k| if (Kind == MCK_RotImm) { ------------------ | Branch (5766:7): [True: 0, False: 13.7k] ------------------ 5767| 0| if (Operand.isRotImm()) ------------------ | Branch (5767:9): [True: 0, False: 0] ------------------ 5768| 0| return MCTargetAsmParser::Match_Success; 5769| 0| } 5770| | 5771| | // 'SPRRegList' class 5772| 13.7k| if (Kind == MCK_SPRRegList) { ------------------ | Branch (5772:7): [True: 0, False: 13.7k] ------------------ 5773| 0| if (Operand.isSPRRegList()) ------------------ | Branch (5773:9): [True: 0, False: 0] ------------------ 5774| 0| return MCTargetAsmParser::Match_Success; 5775| 0| } 5776| | 5777| | // 'SetEndImm' class 5778| 13.7k| if (Kind == MCK_SetEndImm) { ------------------ | Branch (5778:7): [True: 0, False: 13.7k] ------------------ 5779| 0| if (Operand.isSetEndImm()) ------------------ | Branch (5779:9): [True: 0, False: 0] ------------------ 5780| 0| return MCTargetAsmParser::Match_Success; 5781| 0| } 5782| | 5783| | // 'RegShiftedImm' class 5784| 13.7k| if (Kind == MCK_RegShiftedImm) { ------------------ | Branch (5784:7): [True: 601, False: 13.1k] ------------------ 5785| 601| if (Operand.isRegShiftedImm()) ------------------ | Branch (5785:9): [True: 0, False: 601] ------------------ 5786| 0| return MCTargetAsmParser::Match_Success; 5787| 601| } 5788| | 5789| | // 'RegShiftedReg' class 5790| 13.7k| if (Kind == MCK_RegShiftedReg) { ------------------ | Branch (5790:7): [True: 136, False: 13.5k] ------------------ 5791| 136| if (Operand.isRegShiftedReg()) ------------------ | Branch (5791:9): [True: 0, False: 136] ------------------ 5792| 0| return MCTargetAsmParser::Match_Success; 5793| 136| } 5794| | 5795| | // 'ShifterImm' class 5796| 13.7k| if (Kind == MCK_ShifterImm) { ------------------ | Branch (5796:7): [True: 0, False: 13.7k] ------------------ 5797| 0| if (Operand.isShifterImm()) ------------------ | Branch (5797:9): [True: 0, False: 0] ------------------ 5798| 0| return MCTargetAsmParser::Match_Success; 5799| 0| } 5800| | 5801| | // 'ThumbMemPC' class 5802| 13.7k| if (Kind == MCK_ThumbMemPC) { ------------------ | Branch (5802:7): [True: 532, False: 13.1k] ------------------ 5803| 532| if (Operand.isThumbMemPC()) ------------------ | Branch (5803:9): [True: 516, False: 16] ------------------ 5804| 516| return MCTargetAsmParser::Match_Success; 5805| 532| } 5806| | 5807| | // 'ImmThumbSR' class 5808| 13.1k| if (Kind == MCK_ImmThumbSR) { ------------------ | Branch (5808:7): [True: 10, False: 13.1k] ------------------ 5809| 10| if (Operand.isImmThumbSR()) ------------------ | Branch (5809:9): [True: 6, False: 4] ------------------ 5810| 6| return MCTargetAsmParser::Match_Success; 5811| 10| } 5812| | 5813| | // 'UnsignedOffset_b8s2' class 5814| 13.1k| if (Kind == MCK_UnsignedOffset_b8s2) { ------------------ | Branch (5814:7): [True: 74, False: 13.1k] ------------------ 5815| 74| if (Operand.isUnsignedOffset<8, 2>()) ------------------ | Branch (5815:9): [True: 55, False: 19] ------------------ 5816| 55| return MCTargetAsmParser::Match_Success; 5817| 74| } 5818| | 5819| | // 'VecListDPairAllLanes' class 5820| 13.1k| if (Kind == MCK_VecListDPairAllLanes) { ------------------ | Branch (5820:7): [True: 0, False: 13.1k] ------------------ 5821| 0| if (Operand.isVecListDPairAllLanes()) ------------------ | Branch (5821:9): [True: 0, False: 0] ------------------ 5822| 0| return MCTargetAsmParser::Match_Success; 5823| 0| } 5824| | 5825| | // 'VecListDPair' class 5826| 13.1k| if (Kind == MCK_VecListDPair) { ------------------ | Branch (5826:7): [True: 0, False: 13.1k] ------------------ 5827| 0| if (Operand.isVecListDPair()) ------------------ | Branch (5827:9): [True: 0, False: 0] ------------------ 5828| 0| return MCTargetAsmParser::Match_Success; 5829| 0| } 5830| | 5831| | // 'VecListDPairSpacedAllLanes' class 5832| 13.1k| if (Kind == MCK_VecListDPairSpacedAllLanes) { ------------------ | Branch (5832:7): [True: 0, False: 13.1k] ------------------ 5833| 0| if (Operand.isVecListDPairSpacedAllLanes()) ------------------ | Branch (5833:9): [True: 0, False: 0] ------------------ 5834| 0| return MCTargetAsmParser::Match_Success; 5835| 0| } 5836| | 5837| | // 'VecListDPairSpaced' class 5838| 13.1k| if (Kind == MCK_VecListDPairSpaced) { ------------------ | Branch (5838:7): [True: 0, False: 13.1k] ------------------ 5839| 0| if (Operand.isVecListDPairSpaced()) ------------------ | Branch (5839:9): [True: 0, False: 0] ------------------ 5840| 0| return MCTargetAsmParser::Match_Success; 5841| 0| } 5842| | 5843| | // 'VecListFourDAllLanes' class 5844| 13.1k| if (Kind == MCK_VecListFourDAllLanes) { ------------------ | Branch (5844:7): [True: 0, False: 13.1k] ------------------ 5845| 0| if (Operand.isVecListFourDAllLanes()) ------------------ | Branch (5845:9): [True: 0, False: 0] ------------------ 5846| 0| return MCTargetAsmParser::Match_Success; 5847| 0| } 5848| | 5849| | // 'VecListFourD' class 5850| 13.1k| if (Kind == MCK_VecListFourD) { ------------------ | Branch (5850:7): [True: 0, False: 13.1k] ------------------ 5851| 0| if (Operand.isVecListFourD()) ------------------ | Branch (5851:9): [True: 0, False: 0] ------------------ 5852| 0| return MCTargetAsmParser::Match_Success; 5853| 0| } 5854| | 5855| | // 'VecListFourDByteIndexed' class 5856| 13.1k| if (Kind == MCK_VecListFourDByteIndexed) { ------------------ | Branch (5856:7): [True: 0, False: 13.1k] ------------------ 5857| 0| if (Operand.isVecListFourDByteIndexed()) ------------------ | Branch (5857:9): [True: 0, False: 0] ------------------ 5858| 0| return MCTargetAsmParser::Match_Success; 5859| 0| } 5860| | 5861| | // 'VecListFourDHWordIndexed' class 5862| 13.1k| if (Kind == MCK_VecListFourDHWordIndexed) { ------------------ | Branch (5862:7): [True: 0, False: 13.1k] ------------------ 5863| 0| if (Operand.isVecListFourDHWordIndexed()) ------------------ | Branch (5863:9): [True: 0, False: 0] ------------------ 5864| 0| return MCTargetAsmParser::Match_Success; 5865| 0| } 5866| | 5867| | // 'VecListFourDWordIndexed' class 5868| 13.1k| if (Kind == MCK_VecListFourDWordIndexed) { ------------------ | Branch (5868:7): [True: 0, False: 13.1k] ------------------ 5869| 0| if (Operand.isVecListFourDWordIndexed()) ------------------ | Branch (5869:9): [True: 0, False: 0] ------------------ 5870| 0| return MCTargetAsmParser::Match_Success; 5871| 0| } 5872| | 5873| | // 'VecListFourQAllLanes' class 5874| 13.1k| if (Kind == MCK_VecListFourQAllLanes) { ------------------ | Branch (5874:7): [True: 0, False: 13.1k] ------------------ 5875| 0| if (Operand.isVecListFourQAllLanes()) ------------------ | Branch (5875:9): [True: 0, False: 0] ------------------ 5876| 0| return MCTargetAsmParser::Match_Success; 5877| 0| } 5878| | 5879| | // 'VecListFourQ' class 5880| 13.1k| if (Kind == MCK_VecListFourQ) { ------------------ | Branch (5880:7): [True: 0, False: 13.1k] ------------------ 5881| 0| if (Operand.isVecListFourQ()) ------------------ | Branch (5881:9): [True: 0, False: 0] ------------------ 5882| 0| return MCTargetAsmParser::Match_Success; 5883| 0| } 5884| | 5885| | // 'VecListFourQHWordIndexed' class 5886| 13.1k| if (Kind == MCK_VecListFourQHWordIndexed) { ------------------ | Branch (5886:7): [True: 0, False: 13.1k] ------------------ 5887| 0| if (Operand.isVecListFourQHWordIndexed()) ------------------ | Branch (5887:9): [True: 0, False: 0] ------------------ 5888| 0| return MCTargetAsmParser::Match_Success; 5889| 0| } 5890| | 5891| | // 'VecListFourQWordIndexed' class 5892| 13.1k| if (Kind == MCK_VecListFourQWordIndexed) { ------------------ | Branch (5892:7): [True: 0, False: 13.1k] ------------------ 5893| 0| if (Operand.isVecListFourQWordIndexed()) ------------------ | Branch (5893:9): [True: 0, False: 0] ------------------ 5894| 0| return MCTargetAsmParser::Match_Success; 5895| 0| } 5896| | 5897| | // 'VecListOneDAllLanes' class 5898| 13.1k| if (Kind == MCK_VecListOneDAllLanes) { ------------------ | Branch (5898:7): [True: 0, False: 13.1k] ------------------ 5899| 0| if (Operand.isVecListOneDAllLanes()) ------------------ | Branch (5899:9): [True: 0, False: 0] ------------------ 5900| 0| return MCTargetAsmParser::Match_Success; 5901| 0| } 5902| | 5903| | // 'VecListOneD' class 5904| 13.1k| if (Kind == MCK_VecListOneD) { ------------------ | Branch (5904:7): [True: 0, False: 13.1k] ------------------ 5905| 0| if (Operand.isVecListOneD()) ------------------ | Branch (5905:9): [True: 0, False: 0] ------------------ 5906| 0| return MCTargetAsmParser::Match_Success; 5907| 0| } 5908| | 5909| | // 'VecListOneDByteIndexed' class 5910| 13.1k| if (Kind == MCK_VecListOneDByteIndexed) { ------------------ | Branch (5910:7): [True: 0, False: 13.1k] ------------------ 5911| 0| if (Operand.isVecListOneDByteIndexed()) ------------------ | Branch (5911:9): [True: 0, False: 0] ------------------ 5912| 0| return MCTargetAsmParser::Match_Success; 5913| 0| } 5914| | 5915| | // 'VecListOneDHWordIndexed' class 5916| 13.1k| if (Kind == MCK_VecListOneDHWordIndexed) { ------------------ | Branch (5916:7): [True: 0, False: 13.1k] ------------------ 5917| 0| if (Operand.isVecListOneDHWordIndexed()) ------------------ | Branch (5917:9): [True: 0, False: 0] ------------------ 5918| 0| return MCTargetAsmParser::Match_Success; 5919| 0| } 5920| | 5921| | // 'VecListOneDWordIndexed' class 5922| 13.1k| if (Kind == MCK_VecListOneDWordIndexed) { ------------------ | Branch (5922:7): [True: 0, False: 13.1k] ------------------ 5923| 0| if (Operand.isVecListOneDWordIndexed()) ------------------ | Branch (5923:9): [True: 0, False: 0] ------------------ 5924| 0| return MCTargetAsmParser::Match_Success; 5925| 0| } 5926| | 5927| | // 'VecListThreeDAllLanes' class 5928| 13.1k| if (Kind == MCK_VecListThreeDAllLanes) { ------------------ | Branch (5928:7): [True: 0, False: 13.1k] ------------------ 5929| 0| if (Operand.isVecListThreeDAllLanes()) ------------------ | Branch (5929:9): [True: 0, False: 0] ------------------ 5930| 0| return MCTargetAsmParser::Match_Success; 5931| 0| } 5932| | 5933| | // 'VecListThreeD' class 5934| 13.1k| if (Kind == MCK_VecListThreeD) { ------------------ | Branch (5934:7): [True: 0, False: 13.1k] ------------------ 5935| 0| if (Operand.isVecListThreeD()) ------------------ | Branch (5935:9): [True: 0, False: 0] ------------------ 5936| 0| return MCTargetAsmParser::Match_Success; 5937| 0| } 5938| | 5939| | // 'VecListThreeDByteIndexed' class 5940| 13.1k| if (Kind == MCK_VecListThreeDByteIndexed) { ------------------ | Branch (5940:7): [True: 0, False: 13.1k] ------------------ 5941| 0| if (Operand.isVecListThreeDByteIndexed()) ------------------ | Branch (5941:9): [True: 0, False: 0] ------------------ 5942| 0| return MCTargetAsmParser::Match_Success; 5943| 0| } 5944| | 5945| | // 'VecListThreeDHWordIndexed' class 5946| 13.1k| if (Kind == MCK_VecListThreeDHWordIndexed) { ------------------ | Branch (5946:7): [True: 0, False: 13.1k] ------------------ 5947| 0| if (Operand.isVecListThreeDHWordIndexed()) ------------------ | Branch (5947:9): [True: 0, False: 0] ------------------ 5948| 0| return MCTargetAsmParser::Match_Success; 5949| 0| } 5950| | 5951| | // 'VecListThreeDWordIndexed' class 5952| 13.1k| if (Kind == MCK_VecListThreeDWordIndexed) { ------------------ | Branch (5952:7): [True: 0, False: 13.1k] ------------------ 5953| 0| if (Operand.isVecListThreeDWordIndexed()) ------------------ | Branch (5953:9): [True: 0, False: 0] ------------------ 5954| 0| return MCTargetAsmParser::Match_Success; 5955| 0| } 5956| | 5957| | // 'VecListThreeQAllLanes' class 5958| 13.1k| if (Kind == MCK_VecListThreeQAllLanes) { ------------------ | Branch (5958:7): [True: 0, False: 13.1k] ------------------ 5959| 0| if (Operand.isVecListThreeQAllLanes()) ------------------ | Branch (5959:9): [True: 0, False: 0] ------------------ 5960| 0| return MCTargetAsmParser::Match_Success; 5961| 0| } 5962| | 5963| | // 'VecListThreeQ' class 5964| 13.1k| if (Kind == MCK_VecListThreeQ) { ------------------ | Branch (5964:7): [True: 0, False: 13.1k] ------------------ 5965| 0| if (Operand.isVecListThreeQ()) ------------------ | Branch (5965:9): [True: 0, False: 0] ------------------ 5966| 0| return MCTargetAsmParser::Match_Success; 5967| 0| } 5968| | 5969| | // 'VecListThreeQHWordIndexed' class 5970| 13.1k| if (Kind == MCK_VecListThreeQHWordIndexed) { ------------------ | Branch (5970:7): [True: 0, False: 13.1k] ------------------ 5971| 0| if (Operand.isVecListThreeQHWordIndexed()) ------------------ | Branch (5971:9): [True: 0, False: 0] ------------------ 5972| 0| return MCTargetAsmParser::Match_Success; 5973| 0| } 5974| | 5975| | // 'VecListThreeQWordIndexed' class 5976| 13.1k| if (Kind == MCK_VecListThreeQWordIndexed) { ------------------ | Branch (5976:7): [True: 0, False: 13.1k] ------------------ 5977| 0| if (Operand.isVecListThreeQWordIndexed()) ------------------ | Branch (5977:9): [True: 0, False: 0] ------------------ 5978| 0| return MCTargetAsmParser::Match_Success; 5979| 0| } 5980| | 5981| | // 'VecListTwoDByteIndexed' class 5982| 13.1k| if (Kind == MCK_VecListTwoDByteIndexed) { ------------------ | Branch (5982:7): [True: 0, False: 13.1k] ------------------ 5983| 0| if (Operand.isVecListTwoDByteIndexed()) ------------------ | Branch (5983:9): [True: 0, False: 0] ------------------ 5984| 0| return MCTargetAsmParser::Match_Success; 5985| 0| } 5986| | 5987| | // 'VecListTwoDHWordIndexed' class 5988| 13.1k| if (Kind == MCK_VecListTwoDHWordIndexed) { ------------------ | Branch (5988:7): [True: 0, False: 13.1k] ------------------ 5989| 0| if (Operand.isVecListTwoDHWordIndexed()) ------------------ | Branch (5989:9): [True: 0, False: 0] ------------------ 5990| 0| return MCTargetAsmParser::Match_Success; 5991| 0| } 5992| | 5993| | // 'VecListTwoDWordIndexed' class 5994| 13.1k| if (Kind == MCK_VecListTwoDWordIndexed) { ------------------ | Branch (5994:7): [True: 0, False: 13.1k] ------------------ 5995| 0| if (Operand.isVecListTwoDWordIndexed()) ------------------ | Branch (5995:9): [True: 0, False: 0] ------------------ 5996| 0| return MCTargetAsmParser::Match_Success; 5997| 0| } 5998| | 5999| | // 'VecListTwoQHWordIndexed' class 6000| 13.1k| if (Kind == MCK_VecListTwoQHWordIndexed) { ------------------ | Branch (6000:7): [True: 0, False: 13.1k] ------------------ 6001| 0| if (Operand.isVecListTwoQHWordIndexed()) ------------------ | Branch (6001:9): [True: 0, False: 0] ------------------ 6002| 0| return MCTargetAsmParser::Match_Success; 6003| 0| } 6004| | 6005| | // 'VecListTwoQWordIndexed' class 6006| 13.1k| if (Kind == MCK_VecListTwoQWordIndexed) { ------------------ | Branch (6006:7): [True: 0, False: 13.1k] ------------------ 6007| 0| if (Operand.isVecListTwoQWordIndexed()) ------------------ | Branch (6007:9): [True: 0, False: 0] ------------------ 6008| 0| return MCTargetAsmParser::Match_Success; 6009| 0| } 6010| | 6011| | // 'VectorIndex16' class 6012| 13.1k| if (Kind == MCK_VectorIndex16) { ------------------ | Branch (6012:7): [True: 0, False: 13.1k] ------------------ 6013| 0| if (Operand.isVectorIndex16()) ------------------ | Branch (6013:9): [True: 0, False: 0] ------------------ 6014| 0| return MCTargetAsmParser::Match_Success; 6015| 0| } 6016| | 6017| | // 'VectorIndex32' class 6018| 13.1k| if (Kind == MCK_VectorIndex32) { ------------------ | Branch (6018:7): [True: 0, False: 13.1k] ------------------ 6019| 0| if (Operand.isVectorIndex32()) ------------------ | Branch (6019:9): [True: 0, False: 0] ------------------ 6020| 0| return MCTargetAsmParser::Match_Success; 6021| 0| } 6022| | 6023| | // 'VectorIndex8' class 6024| 13.1k| if (Kind == MCK_VectorIndex8) { ------------------ | Branch (6024:7): [True: 0, False: 13.1k] ------------------ 6025| 0| if (Operand.isVectorIndex8()) ------------------ | Branch (6025:9): [True: 0, False: 0] ------------------ 6026| 0| return MCTargetAsmParser::Match_Success; 6027| 0| } 6028| | 6029| | // 'MemTBB' class 6030| 13.1k| if (Kind == MCK_MemTBB) { ------------------ | Branch (6030:7): [True: 0, False: 13.1k] ------------------ 6031| 0| if (Operand.isMemTBB()) ------------------ | Branch (6031:9): [True: 0, False: 0] ------------------ 6032| 0| return MCTargetAsmParser::Match_Success; 6033| 0| } 6034| | 6035| | // 'MemTBH' class 6036| 13.1k| if (Kind == MCK_MemTBH) { ------------------ | Branch (6036:7): [True: 0, False: 13.1k] ------------------ 6037| 0| if (Operand.isMemTBH()) ------------------ | Branch (6037:9): [True: 0, False: 0] ------------------ 6038| 0| return MCTargetAsmParser::Match_Success; 6039| 0| } 6040| | 6041| | // 'FBits16' class 6042| 13.1k| if (Kind == MCK_FBits16) { ------------------ | Branch (6042:7): [True: 0, False: 13.1k] ------------------ 6043| 0| if (Operand.isFBits16()) ------------------ | Branch (6043:9): [True: 0, False: 0] ------------------ 6044| 0| return MCTargetAsmParser::Match_Success; 6045| 0| } 6046| | 6047| | // 'FBits32' class 6048| 13.1k| if (Kind == MCK_FBits32) { ------------------ | Branch (6048:7): [True: 0, False: 13.1k] ------------------ 6049| 0| if (Operand.isFBits32()) ------------------ | Branch (6049:9): [True: 0, False: 0] ------------------ 6050| 0| return MCTargetAsmParser::Match_Success; 6051| 0| } 6052| | 6053| | // 'Imm0_4095' class 6054| 13.1k| if (Kind == MCK_Imm0_4095) { ------------------ | Branch (6054:7): [True: 94, False: 13.0k] ------------------ 6055| 94| if (Operand.isImm0_4095()) ------------------ | Branch (6055:9): [True: 32, False: 62] ------------------ 6056| 32| return MCTargetAsmParser::Match_Success; 6057| 94| } 6058| | 6059| | // 'Imm0_4095Neg' class 6060| 13.0k| if (Kind == MCK_Imm0_4095Neg) { ------------------ | Branch (6060:7): [True: 62, False: 13.0k] ------------------ 6061| 62| if (Operand.isImm0_4095Neg()) ------------------ | Branch (6061:9): [True: 26, False: 36] ------------------ 6062| 26| return MCTargetAsmParser::Match_Success; 6063| 62| } 6064| | 6065| | // 'ITMask' class 6066| 13.0k| if (Kind == MCK_ITMask) { ------------------ | Branch (6066:7): [True: 66, False: 13.0k] ------------------ 6067| 66| if (Operand.isITMask()) ------------------ | Branch (6067:9): [True: 66, False: 0] ------------------ 6068| 66| return MCTargetAsmParser::Match_Success; 6069| 66| } 6070| | 6071| | // 'ITCondCode' class 6072| 13.0k| if (Kind == MCK_ITCondCode) { ------------------ | Branch (6072:7): [True: 66, False: 12.9k] ------------------ 6073| 66| if (Operand.isITCondCode()) ------------------ | Branch (6073:9): [True: 66, False: 0] ------------------ 6074| 66| return MCTargetAsmParser::Match_Success; 6075| 66| } 6076| | 6077| | // 'NEONi16splat' class 6078| 12.9k| if (Kind == MCK_NEONi16splat) { ------------------ | Branch (6078:7): [True: 0, False: 12.9k] ------------------ 6079| 0| if (Operand.isNEONi16splat()) ------------------ | Branch (6079:9): [True: 0, False: 0] ------------------ 6080| 0| return MCTargetAsmParser::Match_Success; 6081| 0| } 6082| | 6083| | // 'NEONi32splat' class 6084| 12.9k| if (Kind == MCK_NEONi32splat) { ------------------ | Branch (6084:7): [True: 0, False: 12.9k] ------------------ 6085| 0| if (Operand.isNEONi32splat()) ------------------ | Branch (6085:9): [True: 0, False: 0] ------------------ 6086| 0| return MCTargetAsmParser::Match_Success; 6087| 0| } 6088| | 6089| | // 'NEONi64splat' class 6090| 12.9k| if (Kind == MCK_NEONi64splat) { ------------------ | Branch (6090:7): [True: 0, False: 12.9k] ------------------ 6091| 0| if (Operand.isNEONi64splat()) ------------------ | Branch (6091:9): [True: 0, False: 0] ------------------ 6092| 0| return MCTargetAsmParser::Match_Success; 6093| 0| } 6094| | 6095| | // 'NEONi8splat' class 6096| 12.9k| if (Kind == MCK_NEONi8splat) { ------------------ | Branch (6096:7): [True: 0, False: 12.9k] ------------------ 6097| 0| if (Operand.isNEONi8splat()) ------------------ | Branch (6097:9): [True: 0, False: 0] ------------------ 6098| 0| return MCTargetAsmParser::Match_Success; 6099| 0| } 6100| | 6101| | // 'NEONi16splatNot' class 6102| 12.9k| if (Kind == MCK_NEONi16splatNot) { ------------------ | Branch (6102:7): [True: 0, False: 12.9k] ------------------ 6103| 0| if (Operand.isNEONi16splatNot()) ------------------ | Branch (6103:9): [True: 0, False: 0] ------------------ 6104| 0| return MCTargetAsmParser::Match_Success; 6105| 0| } 6106| | 6107| | // 'NEONi32splatNot' class 6108| 12.9k| if (Kind == MCK_NEONi32splatNot) { ------------------ | Branch (6108:7): [True: 0, False: 12.9k] ------------------ 6109| 0| if (Operand.isNEONi32splatNot()) ------------------ | Branch (6109:9): [True: 0, False: 0] ------------------ 6110| 0| return MCTargetAsmParser::Match_Success; 6111| 0| } 6112| | 6113| | // 'NEONi16vmovByteReplicate' class 6114| 12.9k| if (Kind == MCK_NEONi16vmovByteReplicate) { ------------------ | Branch (6114:7): [True: 0, False: 12.9k] ------------------ 6115| 0| if (Operand.isNEONi16ByteReplicate()) ------------------ | Branch (6115:9): [True: 0, False: 0] ------------------ 6116| 0| return MCTargetAsmParser::Match_Success; 6117| 0| } 6118| | 6119| | // 'NEONi32vmov' class 6120| 12.9k| if (Kind == MCK_NEONi32vmov) { ------------------ | Branch (6120:7): [True: 0, False: 12.9k] ------------------ 6121| 0| if (Operand.isNEONi32vmov()) ------------------ | Branch (6121:9): [True: 0, False: 0] ------------------ 6122| 0| return MCTargetAsmParser::Match_Success; 6123| 0| } 6124| | 6125| | // 'NEONi32vmovByteReplicate' class 6126| 12.9k| if (Kind == MCK_NEONi32vmovByteReplicate) { ------------------ | Branch (6126:7): [True: 0, False: 12.9k] ------------------ 6127| 0| if (Operand.isNEONi32ByteReplicate()) ------------------ | Branch (6127:9): [True: 0, False: 0] ------------------ 6128| 0| return MCTargetAsmParser::Match_Success; 6129| 0| } 6130| | 6131| | // 'NEONi32vmovNeg' class 6132| 12.9k| if (Kind == MCK_NEONi32vmovNeg) { ------------------ | Branch (6132:7): [True: 0, False: 12.9k] ------------------ 6133| 0| if (Operand.isNEONi32vmovNeg()) ------------------ | Branch (6133:9): [True: 0, False: 0] ------------------ 6134| 0| return MCTargetAsmParser::Match_Success; 6135| 0| } 6136| | 6137| | // 'NEONi16invByteReplicate' class 6138| 12.9k| if (Kind == MCK_NEONi16invByteReplicate) { ------------------ | Branch (6138:7): [True: 0, False: 12.9k] ------------------ 6139| 0| if (Operand.isNEONi16ByteReplicate()) ------------------ | Branch (6139:9): [True: 0, False: 0] ------------------ 6140| 0| return MCTargetAsmParser::Match_Success; 6141| 0| } 6142| | 6143| | // 'NEONi32invByteReplicate' class 6144| 12.9k| if (Kind == MCK_NEONi32invByteReplicate) { ------------------ | Branch (6144:7): [True: 0, False: 12.9k] ------------------ 6145| 0| if (Operand.isNEONi32ByteReplicate()) ------------------ | Branch (6145:9): [True: 0, False: 0] ------------------ 6146| 0| return MCTargetAsmParser::Match_Success; 6147| 0| } 6148| | 6149| | // 'ShrImm16' class 6150| 12.9k| if (Kind == MCK_ShrImm16) { ------------------ | Branch (6150:7): [True: 0, False: 12.9k] ------------------ 6151| 0| if (Operand.isShrImm16()) ------------------ | Branch (6151:9): [True: 0, False: 0] ------------------ 6152| 0| return MCTargetAsmParser::Match_Success; 6153| 0| } 6154| | 6155| | // 'ShrImm32' class 6156| 12.9k| if (Kind == MCK_ShrImm32) { ------------------ | Branch (6156:7): [True: 0, False: 12.9k] ------------------ 6157| 0| if (Operand.isShrImm32()) ------------------ | Branch (6157:9): [True: 0, False: 0] ------------------ 6158| 0| return MCTargetAsmParser::Match_Success; 6159| 0| } 6160| | 6161| | // 'ShrImm64' class 6162| 12.9k| if (Kind == MCK_ShrImm64) { ------------------ | Branch (6162:7): [True: 0, False: 12.9k] ------------------ 6163| 0| if (Operand.isShrImm64()) ------------------ | Branch (6163:9): [True: 0, False: 0] ------------------ 6164| 0| return MCTargetAsmParser::Match_Success; 6165| 0| } 6166| | 6167| | // 'ShrImm8' class 6168| 12.9k| if (Kind == MCK_ShrImm8) { ------------------ | Branch (6168:7): [True: 0, False: 12.9k] ------------------ 6169| 0| if (Operand.isShrImm8()) ------------------ | Branch (6169:9): [True: 0, False: 0] ------------------ 6170| 0| return MCTargetAsmParser::Match_Success; 6171| 0| } 6172| | 6173| | // 'T2SOImm' class 6174| 12.9k| if (Kind == MCK_T2SOImm) { ------------------ | Branch (6174:7): [True: 465, False: 12.4k] ------------------ 6175| 465| if (Operand.isT2SOImm()) ------------------ | Branch (6175:9): [True: 293, False: 172] ------------------ 6176| 293| return MCTargetAsmParser::Match_Success; 6177| 465| } 6178| | 6179| | // 'T2SOImmNeg' class 6180| 12.6k| if (Kind == MCK_T2SOImmNeg) { ------------------ | Branch (6180:7): [True: 214, False: 12.4k] ------------------ 6181| 214| if (Operand.isT2SOImmNeg()) ------------------ | Branch (6181:9): [True: 0, False: 214] ------------------ 6182| 0| return MCTargetAsmParser::Match_Success; 6183| 214| } 6184| | 6185| | // 'T2SOImmNot' class 6186| 12.6k| if (Kind == MCK_T2SOImmNot) { ------------------ | Branch (6186:7): [True: 0, False: 12.6k] ------------------ 6187| 0| if (Operand.isT2SOImmNot()) ------------------ | Branch (6187:9): [True: 0, False: 0] ------------------ 6188| 0| return MCTargetAsmParser::Match_Success; 6189| 0| } 6190| | 6191| | // 'MemUImm12Offset' class 6192| 12.6k| if (Kind == MCK_MemUImm12Offset) { ------------------ | Branch (6192:7): [True: 0, False: 12.6k] ------------------ 6193| 0| if (Operand.isMemUImm12Offset()) ------------------ | Branch (6193:9): [True: 0, False: 0] ------------------ 6194| 0| return MCTargetAsmParser::Match_Success; 6195| 0| } 6196| | 6197| | // 'T2MemRegOffset' class 6198| 12.6k| if (Kind == MCK_T2MemRegOffset) { ------------------ | Branch (6198:7): [True: 0, False: 12.6k] ------------------ 6199| 0| if (Operand.isT2MemRegOffset()) ------------------ | Branch (6199:9): [True: 0, False: 0] ------------------ 6200| 0| return MCTargetAsmParser::Match_Success; 6201| 0| } 6202| | 6203| | // 'Imm8s4' class 6204| 12.6k| if (Kind == MCK_Imm8s4) { ------------------ | Branch (6204:7): [True: 0, False: 12.6k] ------------------ 6205| 0| if (Operand.isImm8s4()) ------------------ | Branch (6205:9): [True: 0, False: 0] ------------------ 6206| 0| return MCTargetAsmParser::Match_Success; 6207| 0| } 6208| | 6209| | // 'MemPCRelImm12' class 6210| 12.6k| if (Kind == MCK_MemPCRelImm12) { ------------------ | Branch (6210:7): [True: 0, False: 12.6k] ------------------ 6211| 0| if (Operand.isMemPCRelImm12()) ------------------ | Branch (6211:9): [True: 0, False: 0] ------------------ 6212| 0| return MCTargetAsmParser::Match_Success; 6213| 0| } 6214| | 6215| | // 'MemThumbRIs1' class 6216| 12.6k| if (Kind == MCK_MemThumbRIs1) { ------------------ | Branch (6216:7): [True: 0, False: 12.6k] ------------------ 6217| 0| if (Operand.isMemThumbRIs1()) ------------------ | Branch (6217:9): [True: 0, False: 0] ------------------ 6218| 0| return MCTargetAsmParser::Match_Success; 6219| 0| } 6220| | 6221| | // 'MemThumbRIs2' class 6222| 12.6k| if (Kind == MCK_MemThumbRIs2) { ------------------ | Branch (6222:7): [True: 72, False: 12.5k] ------------------ 6223| 72| if (Operand.isMemThumbRIs2()) ------------------ | Branch (6223:9): [True: 0, False: 72] ------------------ 6224| 0| return MCTargetAsmParser::Match_Success; 6225| 72| } 6226| | 6227| | // 'MemThumbRIs4' class 6228| 12.6k| if (Kind == MCK_MemThumbRIs4) { ------------------ | Branch (6228:7): [True: 16, False: 12.6k] ------------------ 6229| 16| if (Operand.isMemThumbRIs4()) ------------------ | Branch (6229:9): [True: 0, False: 16] ------------------ 6230| 0| return MCTargetAsmParser::Match_Success; 6231| 16| } 6232| | 6233| | // 'MemThumbRR' class 6234| 12.6k| if (Kind == MCK_MemThumbRR) { ------------------ | Branch (6234:7): [True: 88, False: 12.5k] ------------------ 6235| 88| if (Operand.isMemThumbRR()) ------------------ | Branch (6235:9): [True: 0, False: 88] ------------------ 6236| 0| return MCTargetAsmParser::Match_Success; 6237| 88| } 6238| | 6239| | // 'MemThumbSPI' class 6240| 12.6k| if (Kind == MCK_MemThumbSPI) { ------------------ | Branch (6240:7): [True: 16, False: 12.6k] ------------------ 6241| 16| if (Operand.isMemThumbSPI()) ------------------ | Branch (6241:9): [True: 0, False: 16] ------------------ 6242| 0| return MCTargetAsmParser::Match_Success; 6243| 16| } 6244| | 6245| | // 'Imm0_1020s4' class 6246| 12.6k| if (Kind == MCK_Imm0_1020s4) { ------------------ | Branch (6246:7): [True: 0, False: 12.6k] ------------------ 6247| 0| if (Operand.isImm0_1020s4()) ------------------ | Branch (6247:9): [True: 0, False: 0] ------------------ 6248| 0| return MCTargetAsmParser::Match_Success; 6249| 0| } 6250| | 6251| | // 'Imm0_508s4' class 6252| 12.6k| if (Kind == MCK_Imm0_508s4) { ------------------ | Branch (6252:7): [True: 143, False: 12.5k] ------------------ 6253| 143| if (Operand.isImm0_508s4()) ------------------ | Branch (6253:9): [True: 106, False: 37] ------------------ 6254| 106| return MCTargetAsmParser::Match_Success; 6255| 143| } 6256| | 6257| | // 'Imm0_508s4Neg' class 6258| 12.5k| if (Kind == MCK_Imm0_508s4Neg) { ------------------ | Branch (6258:7): [True: 19, False: 12.5k] ------------------ 6259| 19| if (Operand.isImm0_508s4Neg()) ------------------ | Branch (6259:9): [True: 5, False: 14] ------------------ 6260| 5| return MCTargetAsmParser::Match_Success; 6261| 19| } 6262| | 6263| 12.5k| if (Operand.isReg()) { ------------------ | Branch (6263:7): [True: 8.39k, False: 4.13k] ------------------ 6264| 8.39k| MatchClassKind OpKind; 6265| 8.39k| switch (Operand.getReg()) { 6266| 0| default: OpKind = InvalidMatchClass; break; ------------------ | Branch (6266:5): [True: 0, False: 8.39k] ------------------ 6267| 2.93k| case ARM::R0: OpKind = MCK_Reg0; break; ------------------ | Branch (6267:5): [True: 2.93k, False: 5.46k] ------------------ 6268| 257| case ARM::R1: OpKind = MCK_Reg0; break; ------------------ | Branch (6268:5): [True: 257, False: 8.14k] ------------------ 6269| 100| case ARM::R2: OpKind = MCK_Reg0; break; ------------------ | Branch (6269:5): [True: 100, False: 8.29k] ------------------ 6270| 68| case ARM::R3: OpKind = MCK_Reg0; break; ------------------ | Branch (6270:5): [True: 68, False: 8.33k] ------------------ 6271| 1.15k| case ARM::R4: OpKind = MCK_tGPR; break; ------------------ | Branch (6271:5): [True: 1.15k, False: 7.24k] ------------------ 6272| 656| case ARM::R5: OpKind = MCK_tGPR; break; ------------------ | Branch (6272:5): [True: 656, False: 7.74k] ------------------ 6273| 1.20k| case ARM::R6: OpKind = MCK_tGPR; break; ------------------ | Branch (6273:5): [True: 1.20k, False: 7.19k] ------------------ 6274| 2| case ARM::R7: OpKind = MCK_tGPR; break; ------------------ | Branch (6274:5): [True: 2, False: 8.39k] ------------------ 6275| 22| case ARM::R8: OpKind = MCK_Reg9; break; ------------------ | Branch (6275:5): [True: 22, False: 8.37k] ------------------ 6276| 12| case ARM::R9: OpKind = MCK_Reg9; break; ------------------ | Branch (6276:5): [True: 12, False: 8.38k] ------------------ 6277| 596| case ARM::R10: OpKind = MCK_Reg9; break; ------------------ | Branch (6277:5): [True: 596, False: 7.80k] ------------------ 6278| 0| case ARM::R11: OpKind = MCK_Reg9; break; ------------------ | Branch (6278:5): [True: 0, False: 8.39k] ------------------ 6279| 98| case ARM::R12: OpKind = MCK_Reg10; break; ------------------ | Branch (6279:5): [True: 98, False: 8.30k] ------------------ 6280| 1.27k| case ARM::SP: OpKind = MCK_GPRsp; break; ------------------ | Branch (6280:5): [True: 1.27k, False: 7.12k] ------------------ 6281| 22| case ARM::LR: OpKind = MCK_LR; break; ------------------ | Branch (6281:5): [True: 22, False: 8.37k] ------------------ 6282| 0| case ARM::PC: OpKind = MCK_PC; break; ------------------ | Branch (6282:5): [True: 0, False: 8.39k] ------------------ 6283| 0| case ARM::S0: OpKind = MCK_SPR_8; break; ------------------ | Branch (6283:5): [True: 0, False: 8.39k] ------------------ 6284| 0| case ARM::S1: OpKind = MCK_SPR_8; break; ------------------ | Branch (6284:5): [True: 0, False: 8.39k] ------------------ 6285| 0| case ARM::S2: OpKind = MCK_SPR_8; break; ------------------ | Branch (6285:5): [True: 0, False: 8.39k] ------------------ 6286| 0| case ARM::S3: OpKind = MCK_SPR_8; break; ------------------ | Branch (6286:5): [True: 0, False: 8.39k] ------------------ 6287| 0| case ARM::S4: OpKind = MCK_SPR_8; break; ------------------ | Branch (6287:5): [True: 0, False: 8.39k] ------------------ 6288| 0| case ARM::S5: OpKind = MCK_SPR_8; break; ------------------ | Branch (6288:5): [True: 0, False: 8.39k] ------------------ 6289| 0| case ARM::S6: OpKind = MCK_SPR_8; break; ------------------ | Branch (6289:5): [True: 0, False: 8.39k] ------------------ 6290| 0| case ARM::S7: OpKind = MCK_SPR_8; break; ------------------ | Branch (6290:5): [True: 0, False: 8.39k] ------------------ 6291| 0| case ARM::S8: OpKind = MCK_SPR_8; break; ------------------ | Branch (6291:5): [True: 0, False: 8.39k] ------------------ 6292| 0| case ARM::S9: OpKind = MCK_SPR_8; break; ------------------ | Branch (6292:5): [True: 0, False: 8.39k] ------------------ 6293| 0| case ARM::S10: OpKind = MCK_SPR_8; break; ------------------ | Branch (6293:5): [True: 0, False: 8.39k] ------------------ 6294| 0| case ARM::S11: OpKind = MCK_SPR_8; break; ------------------ | Branch (6294:5): [True: 0, False: 8.39k] ------------------ 6295| 0| case ARM::S12: OpKind = MCK_SPR_8; break; ------------------ | Branch (6295:5): [True: 0, False: 8.39k] ------------------ 6296| 0| case ARM::S13: OpKind = MCK_SPR_8; break; ------------------ | Branch (6296:5): [True: 0, False: 8.39k] ------------------ 6297| 0| case ARM::S14: OpKind = MCK_SPR_8; break; ------------------ | Branch (6297:5): [True: 0, False: 8.39k] ------------------ 6298| 0| case ARM::S15: OpKind = MCK_SPR_8; break; ------------------ | Branch (6298:5): [True: 0, False: 8.39k] ------------------ 6299| 0| case ARM::S16: OpKind = MCK_SPR; break; ------------------ | Branch (6299:5): [True: 0, False: 8.39k] ------------------ 6300| 0| case ARM::S17: OpKind = MCK_SPR; break; ------------------ | Branch (6300:5): [True: 0, False: 8.39k] ------------------ 6301| 0| case ARM::S18: OpKind = MCK_SPR; break; ------------------ | Branch (6301:5): [True: 0, False: 8.39k] ------------------ 6302| 0| case ARM::S19: OpKind = MCK_SPR; break; ------------------ | Branch (6302:5): [True: 0, False: 8.39k] ------------------ 6303| 0| case ARM::S20: OpKind = MCK_SPR; break; ------------------ | Branch (6303:5): [True: 0, False: 8.39k] ------------------ 6304| 0| case ARM::S21: OpKind = MCK_SPR; break; ------------------ | Branch (6304:5): [True: 0, False: 8.39k] ------------------ 6305| 0| case ARM::S22: OpKind = MCK_SPR; break; ------------------ | Branch (6305:5): [True: 0, False: 8.39k] ------------------ 6306| 0| case ARM::S23: OpKind = MCK_SPR; break; ------------------ | Branch (6306:5): [True: 0, False: 8.39k] ------------------ 6307| 0| case ARM::S24: OpKind = MCK_SPR; break; ------------------ | Branch (6307:5): [True: 0, False: 8.39k] ------------------ 6308| 0| case ARM::S25: OpKind = MCK_SPR; break; ------------------ | Branch (6308:5): [True: 0, False: 8.39k] ------------------ 6309| 0| case ARM::S26: OpKind = MCK_SPR; break; ------------------ | Branch (6309:5): [True: 0, False: 8.39k] ------------------ 6310| 0| case ARM::S27: OpKind = MCK_SPR; break; ------------------ | Branch (6310:5): [True: 0, False: 8.39k] ------------------ 6311| 0| case ARM::S28: OpKind = MCK_SPR; break; ------------------ | Branch (6311:5): [True: 0, False: 8.39k] ------------------ 6312| 0| case ARM::S29: OpKind = MCK_SPR; break; ------------------ | Branch (6312:5): [True: 0, False: 8.39k] ------------------ 6313| 0| case ARM::S30: OpKind = MCK_SPR; break; ------------------ | Branch (6313:5): [True: 0, False: 8.39k] ------------------ 6314| 0| case ARM::S31: OpKind = MCK_SPR; break; ------------------ | Branch (6314:5): [True: 0, False: 8.39k] ------------------ 6315| 0| case ARM::D0: OpKind = MCK_DPR_8; break; ------------------ | Branch (6315:5): [True: 0, False: 8.39k] ------------------ 6316| 0| case ARM::D1: OpKind = MCK_DPR_8; break; ------------------ | Branch (6316:5): [True: 0, False: 8.39k] ------------------ 6317| 0| case ARM::D2: OpKind = MCK_DPR_8; break; ------------------ | Branch (6317:5): [True: 0, False: 8.39k] ------------------ 6318| 0| case ARM::D3: OpKind = MCK_DPR_8; break; ------------------ | Branch (6318:5): [True: 0, False: 8.39k] ------------------ 6319| 0| case ARM::D4: OpKind = MCK_DPR_8; break; ------------------ | Branch (6319:5): [True: 0, False: 8.39k] ------------------ 6320| 0| case ARM::D5: OpKind = MCK_DPR_8; break; ------------------ | Branch (6320:5): [True: 0, False: 8.39k] ------------------ 6321| 0| case ARM::D6: OpKind = MCK_DPR_8; break; ------------------ | Branch (6321:5): [True: 0, False: 8.39k] ------------------ 6322| 0| case ARM::D7: OpKind = MCK_DPR_8; break; ------------------ | Branch (6322:5): [True: 0, False: 8.39k] ------------------ 6323| 0| case ARM::D8: OpKind = MCK_DPR_VFP2; break; ------------------ | Branch (6323:5): [True: 0, False: 8.39k] ------------------ 6324| 0| case ARM::D9: OpKind = MCK_DPR_VFP2; break; ------------------ | Branch (6324:5): [True: 0, False: 8.39k] ------------------ 6325| 0| case ARM::D10: OpKind = MCK_DPR_VFP2; break; ------------------ | Branch (6325:5): [True: 0, False: 8.39k] ------------------ 6326| 0| case ARM::D11: OpKind = MCK_DPR_VFP2; break; ------------------ | Branch (6326:5): [True: 0, False: 8.39k] ------------------ 6327| 0| case ARM::D12: OpKind = MCK_DPR_VFP2; break; ------------------ | Branch (6327:5): [True: 0, False: 8.39k] ------------------ 6328| 0| case ARM::D13: OpKind = MCK_DPR_VFP2; break; ------------------ | Branch (6328:5): [True: 0, False: 8.39k] ------------------ 6329| 0| case ARM::D14: OpKind = MCK_DPR_VFP2; break; ------------------ | Branch (6329:5): [True: 0, False: 8.39k] ------------------ 6330| 0| case ARM::D15: OpKind = MCK_DPR_VFP2; break; ------------------ | Branch (6330:5): [True: 0, False: 8.39k] ------------------ 6331| 0| case ARM::D16: OpKind = MCK_DPR; break; ------------------ | Branch (6331:5): [True: 0, False: 8.39k] ------------------ 6332| 0| case ARM::D17: OpKind = MCK_DPR; break; ------------------ | Branch (6332:5): [True: 0, False: 8.39k] ------------------ 6333| 0| case ARM::D18: OpKind = MCK_DPR; break; ------------------ | Branch (6333:5): [True: 0, False: 8.39k] ------------------ 6334| 0| case ARM::D19: OpKind = MCK_DPR; break; ------------------ | Branch (6334:5): [True: 0, False: 8.39k] ------------------ 6335| 0| case ARM::D20: OpKind = MCK_DPR; break; ------------------ | Branch (6335:5): [True: 0, False: 8.39k] ------------------ 6336| 0| case ARM::D21: OpKind = MCK_DPR; break; ------------------ | Branch (6336:5): [True: 0, False: 8.39k] ------------------ 6337| 0| case ARM::D22: OpKind = MCK_DPR; break; ------------------ | Branch (6337:5): [True: 0, False: 8.39k] ------------------ 6338| 0| case ARM::D23: OpKind = MCK_DPR; break; ------------------ | Branch (6338:5): [True: 0, False: 8.39k] ------------------ 6339| 0| case ARM::D24: OpKind = MCK_DPR; break; ------------------ | Branch (6339:5): [True: 0, False: 8.39k] ------------------ 6340| 0| case ARM::D25: OpKind = MCK_DPR; break; ------------------ | Branch (6340:5): [True: 0, False: 8.39k] ------------------ 6341| 0| case ARM::D26: OpKind = MCK_DPR; break; ------------------ | Branch (6341:5): [True: 0, False: 8.39k] ------------------ 6342| 0| case ARM::D27: OpKind = MCK_DPR; break; ------------------ | Branch (6342:5): [True: 0, False: 8.39k] ------------------ 6343| 0| case ARM::D28: OpKind = MCK_DPR; break; ------------------ | Branch (6343:5): [True: 0, False: 8.39k] ------------------ 6344| 0| case ARM::D29: OpKind = MCK_DPR; break; ------------------ | Branch (6344:5): [True: 0, False: 8.39k] ------------------ 6345| 0| case ARM::D30: OpKind = MCK_DPR; break; ------------------ | Branch (6345:5): [True: 0, False: 8.39k] ------------------ 6346| 0| case ARM::D31: OpKind = MCK_DPR; break; ------------------ | Branch (6346:5): [True: 0, False: 8.39k] ------------------ 6347| 0| case ARM::Q0: OpKind = MCK_QPR_8; break; ------------------ | Branch (6347:5): [True: 0, False: 8.39k] ------------------ 6348| 0| case ARM::Q1: OpKind = MCK_QPR_8; break; ------------------ | Branch (6348:5): [True: 0, False: 8.39k] ------------------ 6349| 0| case ARM::Q2: OpKind = MCK_QPR_8; break; ------------------ | Branch (6349:5): [True: 0, False: 8.39k] ------------------ 6350| 0| case ARM::Q3: OpKind = MCK_QPR_8; break; ------------------ | Branch (6350:5): [True: 0, False: 8.39k] ------------------ 6351| 0| case ARM::Q4: OpKind = MCK_QPR_VFP2; break; ------------------ | Branch (6351:5): [True: 0, False: 8.39k] ------------------ 6352| 0| case ARM::Q5: OpKind = MCK_QPR_VFP2; break; ------------------ | Branch (6352:5): [True: 0, False: 8.39k] ------------------ 6353| 0| case ARM::Q6: OpKind = MCK_QPR_VFP2; break; ------------------ | Branch (6353:5): [True: 0, False: 8.39k] ------------------ 6354| 0| case ARM::Q7: OpKind = MCK_QPR_VFP2; break; ------------------ | Branch (6354:5): [True: 0, False: 8.39k] ------------------ 6355| 0| case ARM::Q8: OpKind = MCK_QPR; break; ------------------ | Branch (6355:5): [True: 0, False: 8.39k] ------------------ 6356| 0| case ARM::Q9: OpKind = MCK_QPR; break; ------------------ | Branch (6356:5): [True: 0, False: 8.39k] ------------------ 6357| 0| case ARM::Q10: OpKind = MCK_QPR; break; ------------------ | Branch (6357:5): [True: 0, False: 8.39k] ------------------ 6358| 0| case ARM::Q11: OpKind = MCK_QPR; break; ------------------ | Branch (6358:5): [True: 0, False: 8.39k] ------------------ 6359| 0| case ARM::Q12: OpKind = MCK_QPR; break; ------------------ | Branch (6359:5): [True: 0, False: 8.39k] ------------------ 6360| 0| case ARM::Q13: OpKind = MCK_QPR; break; ------------------ | Branch (6360:5): [True: 0, False: 8.39k] ------------------ 6361| 0| case ARM::Q14: OpKind = MCK_QPR; break; ------------------ | Branch (6361:5): [True: 0, False: 8.39k] ------------------ 6362| 0| case ARM::Q15: OpKind = MCK_QPR; break; ------------------ | Branch (6362:5): [True: 0, False: 8.39k] ------------------ 6363| 0| case ARM::CPSR: OpKind = MCK_CCR; break; ------------------ | Branch (6363:5): [True: 0, False: 8.39k] ------------------ 6364| 0| case ARM::APSR: OpKind = MCK_APSR; break; ------------------ | Branch (6364:5): [True: 0, False: 8.39k] ------------------ 6365| 0| case ARM::APSR_NZCV: OpKind = MCK_APSR_NZCV; break; ------------------ | Branch (6365:5): [True: 0, False: 8.39k] ------------------ 6366| 0| case ARM::SPSR: OpKind = MCK_SPSR; break; ------------------ | Branch (6366:5): [True: 0, False: 8.39k] ------------------ 6367| 0| case ARM::FPSCR: OpKind = MCK_FPSCR; break; ------------------ | Branch (6367:5): [True: 0, False: 8.39k] ------------------ 6368| 0| case ARM::FPSID: OpKind = MCK_FPSID; break; ------------------ | Branch (6368:5): [True: 0, False: 8.39k] ------------------ 6369| 0| case ARM::MVFR2: OpKind = MCK_MVFR2; break; ------------------ | Branch (6369:5): [True: 0, False: 8.39k] ------------------ 6370| 0| case ARM::MVFR1: OpKind = MCK_MVFR1; break; ------------------ | Branch (6370:5): [True: 0, False: 8.39k] ------------------ 6371| 0| case ARM::MVFR0: OpKind = MCK_MVFR0; break; ------------------ | Branch (6371:5): [True: 0, False: 8.39k] ------------------ 6372| 0| case ARM::FPEXC: OpKind = MCK_FPEXC; break; ------------------ | Branch (6372:5): [True: 0, False: 8.39k] ------------------ 6373| 0| case ARM::FPINST: OpKind = MCK_FPINST; break; ------------------ | Branch (6373:5): [True: 0, False: 8.39k] ------------------ 6374| 0| case ARM::FPINST2: OpKind = MCK_FPINST2; break; ------------------ | Branch (6374:5): [True: 0, False: 8.39k] ------------------ 6375| 0| case ARM::D0_D2: OpKind = MCK_Reg39; break; ------------------ | Branch (6375:5): [True: 0, False: 8.39k] ------------------ 6376| 0| case ARM::D1_D3: OpKind = MCK_Reg39; break; ------------------ | Branch (6376:5): [True: 0, False: 8.39k] ------------------ 6377| 0| case ARM::D2_D4: OpKind = MCK_Reg39; break; ------------------ | Branch (6377:5): [True: 0, False: 8.39k] ------------------ 6378| 0| case ARM::D3_D5: OpKind = MCK_Reg39; break; ------------------ | Branch (6378:5): [True: 0, False: 8.39k] ------------------ 6379| 0| case ARM::D4_D6: OpKind = MCK_Reg39; break; ------------------ | Branch (6379:5): [True: 0, False: 8.39k] ------------------ 6380| 0| case ARM::D5_D7: OpKind = MCK_Reg39; break; ------------------ | Branch (6380:5): [True: 0, False: 8.39k] ------------------ 6381| 0| case ARM::D6_D8: OpKind = MCK_Reg40; break; ------------------ | Branch (6381:5): [True: 0, False: 8.39k] ------------------ 6382| 0| case ARM::D7_D9: OpKind = MCK_Reg40; break; ------------------ | Branch (6382:5): [True: 0, False: 8.39k] ------------------ 6383| 0| case ARM::D8_D10: OpKind = MCK_Reg41; break; ------------------ | Branch (6383:5): [True: 0, False: 8.39k] ------------------ 6384| 0| case ARM::D9_D11: OpKind = MCK_Reg41; break; ------------------ | Branch (6384:5): [True: 0, False: 8.39k] ------------------ 6385| 0| case ARM::D10_D12: OpKind = MCK_Reg41; break; ------------------ | Branch (6385:5): [True: 0, False: 8.39k] ------------------ 6386| 0| case ARM::D11_D13: OpKind = MCK_Reg41; break; ------------------ | Branch (6386:5): [True: 0, False: 8.39k] ------------------ 6387| 0| case ARM::D12_D14: OpKind = MCK_Reg41; break; ------------------ | Branch (6387:5): [True: 0, False: 8.39k] ------------------ 6388| 0| case ARM::D13_D15: OpKind = MCK_Reg41; break; ------------------ | Branch (6388:5): [True: 0, False: 8.39k] ------------------ 6389| 0| case ARM::D14_D16: OpKind = MCK_Reg42; break; ------------------ | Branch (6389:5): [True: 0, False: 8.39k] ------------------ 6390| 0| case ARM::D15_D17: OpKind = MCK_Reg42; break; ------------------ | Branch (6390:5): [True: 0, False: 8.39k] ------------------ 6391| 0| case ARM::D16_D18: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6391:5): [True: 0, False: 8.39k] ------------------ 6392| 0| case ARM::D17_D19: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6392:5): [True: 0, False: 8.39k] ------------------ 6393| 0| case ARM::D18_D20: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6393:5): [True: 0, False: 8.39k] ------------------ 6394| 0| case ARM::D19_D21: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6394:5): [True: 0, False: 8.39k] ------------------ 6395| 0| case ARM::D20_D22: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6395:5): [True: 0, False: 8.39k] ------------------ 6396| 0| case ARM::D21_D23: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6396:5): [True: 0, False: 8.39k] ------------------ 6397| 0| case ARM::D22_D24: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6397:5): [True: 0, False: 8.39k] ------------------ 6398| 0| case ARM::D23_D25: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6398:5): [True: 0, False: 8.39k] ------------------ 6399| 0| case ARM::D24_D26: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6399:5): [True: 0, False: 8.39k] ------------------ 6400| 0| case ARM::D25_D27: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6400:5): [True: 0, False: 8.39k] ------------------ 6401| 0| case ARM::D26_D28: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6401:5): [True: 0, False: 8.39k] ------------------ 6402| 0| case ARM::D27_D29: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6402:5): [True: 0, False: 8.39k] ------------------ 6403| 0| case ARM::D28_D30: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6403:5): [True: 0, False: 8.39k] ------------------ 6404| 0| case ARM::D29_D31: OpKind = MCK_DPairSpc; break; ------------------ | Branch (6404:5): [True: 0, False: 8.39k] ------------------ 6405| 0| case ARM::Q0_Q1: OpKind = MCK_Reg44; break; ------------------ | Branch (6405:5): [True: 0, False: 8.39k] ------------------ 6406| 0| case ARM::Q1_Q2: OpKind = MCK_Reg44; break; ------------------ | Branch (6406:5): [True: 0, False: 8.39k] ------------------ 6407| 0| case ARM::Q2_Q3: OpKind = MCK_Reg44; break; ------------------ | Branch (6407:5): [True: 0, False: 8.39k] ------------------ 6408| 0| case ARM::Q3_Q4: OpKind = MCK_Reg45; break; ------------------ | Branch (6408:5): [True: 0, False: 8.39k] ------------------ 6409| 0| case ARM::Q4_Q5: OpKind = MCK_Reg46; break; ------------------ | Branch (6409:5): [True: 0, False: 8.39k] ------------------ 6410| 0| case ARM::Q5_Q6: OpKind = MCK_Reg46; break; ------------------ | Branch (6410:5): [True: 0, False: 8.39k] ------------------ 6411| 0| case ARM::Q6_Q7: OpKind = MCK_Reg46; break; ------------------ | Branch (6411:5): [True: 0, False: 8.39k] ------------------ 6412| 0| case ARM::Q7_Q8: OpKind = MCK_Reg47; break; ------------------ | Branch (6412:5): [True: 0, False: 8.39k] ------------------ 6413| 0| case ARM::Q8_Q9: OpKind = MCK_QQPR; break; ------------------ | Branch (6413:5): [True: 0, False: 8.39k] ------------------ 6414| 0| case ARM::Q9_Q10: OpKind = MCK_QQPR; break; ------------------ | Branch (6414:5): [True: 0, False: 8.39k] ------------------ 6415| 0| case ARM::Q10_Q11: OpKind = MCK_QQPR; break; ------------------ | Branch (6415:5): [True: 0, False: 8.39k] ------------------ 6416| 0| case ARM::Q11_Q12: OpKind = MCK_QQPR; break; ------------------ | Branch (6416:5): [True: 0, False: 8.39k] ------------------ 6417| 0| case ARM::Q12_Q13: OpKind = MCK_QQPR; break; ------------------ | Branch (6417:5): [True: 0, False: 8.39k] ------------------ 6418| 0| case ARM::Q13_Q14: OpKind = MCK_QQPR; break; ------------------ | Branch (6418:5): [True: 0, False: 8.39k] ------------------ 6419| 0| case ARM::Q14_Q15: OpKind = MCK_QQPR; break; ------------------ | Branch (6419:5): [True: 0, False: 8.39k] ------------------ 6420| 0| case ARM::Q0_Q1_Q2_Q3: OpKind = MCK_Reg58; break; ------------------ | Branch (6420:5): [True: 0, False: 8.39k] ------------------ 6421| 0| case ARM::Q1_Q2_Q3_Q4: OpKind = MCK_Reg59; break; ------------------ | Branch (6421:5): [True: 0, False: 8.39k] ------------------ 6422| 0| case ARM::Q2_Q3_Q4_Q5: OpKind = MCK_Reg60; break; ------------------ | Branch (6422:5): [True: 0, False: 8.39k] ------------------ 6423| 0| case ARM::Q3_Q4_Q5_Q6: OpKind = MCK_Reg61; break; ------------------ | Branch (6423:5): [True: 0, False: 8.39k] ------------------ 6424| 0| case ARM::Q4_Q5_Q6_Q7: OpKind = MCK_Reg62; break; ------------------ | Branch (6424:5): [True: 0, False: 8.39k] ------------------ 6425| 0| case ARM::Q5_Q6_Q7_Q8: OpKind = MCK_Reg63; break; ------------------ | Branch (6425:5): [True: 0, False: 8.39k] ------------------ 6426| 0| case ARM::Q6_Q7_Q8_Q9: OpKind = MCK_Reg64; break; ------------------ | Branch (6426:5): [True: 0, False: 8.39k] ------------------ 6427| 0| case ARM::Q7_Q8_Q9_Q10: OpKind = MCK_Reg65; break; ------------------ | Branch (6427:5): [True: 0, False: 8.39k] ------------------ 6428| 0| case ARM::Q8_Q9_Q10_Q11: OpKind = MCK_QQQQPR; break; ------------------ | Branch (6428:5): [True: 0, False: 8.39k] ------------------ 6429| 0| case ARM::Q9_Q10_Q11_Q12: OpKind = MCK_QQQQPR; break; ------------------ | Branch (6429:5): [True: 0, False: 8.39k] ------------------ 6430| 0| case ARM::Q10_Q11_Q12_Q13: OpKind = MCK_QQQQPR; break; ------------------ | Branch (6430:5): [True: 0, False: 8.39k] ------------------ 6431| 0| case ARM::Q11_Q12_Q13_Q14: OpKind = MCK_QQQQPR; break; ------------------ | Branch (6431:5): [True: 0, False: 8.39k] ------------------ 6432| 0| case ARM::Q12_Q13_Q14_Q15: OpKind = MCK_QQQQPR; break; ------------------ | Branch (6432:5): [True: 0, False: 8.39k] ------------------ 6433| 0| case ARM::R0_R1: OpKind = MCK_Reg67; break; ------------------ | Branch (6433:5): [True: 0, False: 8.39k] ------------------ 6434| 0| case ARM::R2_R3: OpKind = MCK_Reg67; break; ------------------ | Branch (6434:5): [True: 0, False: 8.39k] ------------------ 6435| 0| case ARM::R4_R5: OpKind = MCK_Reg68; break; ------------------ | Branch (6435:5): [True: 0, False: 8.39k] ------------------ 6436| 0| case ARM::R6_R7: OpKind = MCK_Reg68; break; ------------------ | Branch (6436:5): [True: 0, False: 8.39k] ------------------ 6437| 0| case ARM::R8_R9: OpKind = MCK_Reg72; break; ------------------ | Branch (6437:5): [True: 0, False: 8.39k] ------------------ 6438| 0| case ARM::R10_R11: OpKind = MCK_Reg72; break; ------------------ | Branch (6438:5): [True: 0, False: 8.39k] ------------------ 6439| 0| case ARM::R12_SP: OpKind = MCK_Reg74; break; ------------------ | Branch (6439:5): [True: 0, False: 8.39k] ------------------ 6440| 0| case ARM::D0_D1_D2: OpKind = MCK_Reg82; break; ------------------ | Branch (6440:5): [True: 0, False: 8.39k] ------------------ 6441| 0| case ARM::D1_D2_D3: OpKind = MCK_Reg87; break; ------------------ | Branch (6441:5): [True: 0, False: 8.39k] ------------------ 6442| 0| case ARM::D2_D3_D4: OpKind = MCK_Reg82; break; ------------------ | Branch (6442:5): [True: 0, False: 8.39k] ------------------ 6443| 0| case ARM::D3_D4_D5: OpKind = MCK_Reg87; break; ------------------ | Branch (6443:5): [True: 0, False: 8.39k] ------------------ 6444| 0| case ARM::D4_D5_D6: OpKind = MCK_Reg82; break; ------------------ | Branch (6444:5): [True: 0, False: 8.39k] ------------------ 6445| 0| case ARM::D5_D6_D7: OpKind = MCK_Reg87; break; ------------------ | Branch (6445:5): [True: 0, False: 8.39k] ------------------ 6446| 0| case ARM::D6_D7_D8: OpKind = MCK_Reg83; break; ------------------ | Branch (6446:5): [True: 0, False: 8.39k] ------------------ 6447| 0| case ARM::D7_D8_D9: OpKind = MCK_Reg88; break; ------------------ | Branch (6447:5): [True: 0, False: 8.39k] ------------------ 6448| 0| case ARM::D8_D9_D10: OpKind = MCK_Reg84; break; ------------------ | Branch (6448:5): [True: 0, False: 8.39k] ------------------ 6449| 0| case ARM::D9_D10_D11: OpKind = MCK_Reg89; break; ------------------ | Branch (6449:5): [True: 0, False: 8.39k] ------------------ 6450| 0| case ARM::D10_D11_D12: OpKind = MCK_Reg84; break; ------------------ | Branch (6450:5): [True: 0, False: 8.39k] ------------------ 6451| 0| case ARM::D11_D12_D13: OpKind = MCK_Reg89; break; ------------------ | Branch (6451:5): [True: 0, False: 8.39k] ------------------ 6452| 0| case ARM::D12_D13_D14: OpKind = MCK_Reg84; break; ------------------ | Branch (6452:5): [True: 0, False: 8.39k] ------------------ 6453| 0| case ARM::D13_D14_D15: OpKind = MCK_Reg89; break; ------------------ | Branch (6453:5): [True: 0, False: 8.39k] ------------------ 6454| 0| case ARM::D14_D15_D16: OpKind = MCK_Reg85; break; ------------------ | Branch (6454:5): [True: 0, False: 8.39k] ------------------ 6455| 0| case ARM::D15_D16_D17: OpKind = MCK_Reg90; break; ------------------ | Branch (6455:5): [True: 0, False: 8.39k] ------------------ 6456| 0| case ARM::D16_D17_D18: OpKind = MCK_Reg86; break; ------------------ | Branch (6456:5): [True: 0, False: 8.39k] ------------------ 6457| 0| case ARM::D17_D18_D19: OpKind = MCK_Reg91; break; ------------------ | Branch (6457:5): [True: 0, False: 8.39k] ------------------ 6458| 0| case ARM::D18_D19_D20: OpKind = MCK_Reg86; break; ------------------ | Branch (6458:5): [True: 0, False: 8.39k] ------------------ 6459| 0| case ARM::D19_D20_D21: OpKind = MCK_Reg91; break; ------------------ | Branch (6459:5): [True: 0, False: 8.39k] ------------------ 6460| 0| case ARM::D20_D21_D22: OpKind = MCK_Reg86; break; ------------------ | Branch (6460:5): [True: 0, False: 8.39k] ------------------ 6461| 0| case ARM::D21_D22_D23: OpKind = MCK_Reg91; break; ------------------ | Branch (6461:5): [True: 0, False: 8.39k] ------------------ 6462| 0| case ARM::D22_D23_D24: OpKind = MCK_Reg86; break; ------------------ | Branch (6462:5): [True: 0, False: 8.39k] ------------------ 6463| 0| case ARM::D23_D24_D25: OpKind = MCK_Reg91; break; ------------------ | Branch (6463:5): [True: 0, False: 8.39k] ------------------ 6464| 0| case ARM::D24_D25_D26: OpKind = MCK_Reg86; break; ------------------ | Branch (6464:5): [True: 0, False: 8.39k] ------------------ 6465| 0| case ARM::D25_D26_D27: OpKind = MCK_Reg91; break; ------------------ | Branch (6465:5): [True: 0, False: 8.39k] ------------------ 6466| 0| case ARM::D26_D27_D28: OpKind = MCK_Reg86; break; ------------------ | Branch (6466:5): [True: 0, False: 8.39k] ------------------ 6467| 0| case ARM::D27_D28_D29: OpKind = MCK_Reg91; break; ------------------ | Branch (6467:5): [True: 0, False: 8.39k] ------------------ 6468| 0| case ARM::D28_D29_D30: OpKind = MCK_Reg86; break; ------------------ | Branch (6468:5): [True: 0, False: 8.39k] ------------------ 6469| 0| case ARM::D29_D30_D31: OpKind = MCK_Reg91; break; ------------------ | Branch (6469:5): [True: 0, False: 8.39k] ------------------ 6470| 0| case ARM::D0_D2_D4: OpKind = MCK_Reg92; break; ------------------ | Branch (6470:5): [True: 0, False: 8.39k] ------------------ 6471| 0| case ARM::D1_D3_D5: OpKind = MCK_Reg92; break; ------------------ | Branch (6471:5): [True: 0, False: 8.39k] ------------------ 6472| 0| case ARM::D2_D4_D6: OpKind = MCK_Reg92; break; ------------------ | Branch (6472:5): [True: 0, False: 8.39k] ------------------ 6473| 0| case ARM::D3_D5_D7: OpKind = MCK_Reg92; break; ------------------ | Branch (6473:5): [True: 0, False: 8.39k] ------------------ 6474| 0| case ARM::D4_D6_D8: OpKind = MCK_Reg93; break; ------------------ | Branch (6474:5): [True: 0, False: 8.39k] ------------------ 6475| 0| case ARM::D5_D7_D9: OpKind = MCK_Reg93; break; ------------------ | Branch (6475:5): [True: 0, False: 8.39k] ------------------ 6476| 0| case ARM::D6_D8_D10: OpKind = MCK_Reg94; break; ------------------ | Branch (6476:5): [True: 0, False: 8.39k] ------------------ 6477| 0| case ARM::D7_D9_D11: OpKind = MCK_Reg94; break; ------------------ | Branch (6477:5): [True: 0, False: 8.39k] ------------------ 6478| 0| case ARM::D8_D10_D12: OpKind = MCK_Reg95; break; ------------------ | Branch (6478:5): [True: 0, False: 8.39k] ------------------ 6479| 0| case ARM::D9_D11_D13: OpKind = MCK_Reg95; break; ------------------ | Branch (6479:5): [True: 0, False: 8.39k] ------------------ 6480| 0| case ARM::D10_D12_D14: OpKind = MCK_Reg95; break; ------------------ | Branch (6480:5): [True: 0, False: 8.39k] ------------------ 6481| 0| case ARM::D11_D13_D15: OpKind = MCK_Reg95; break; ------------------ | Branch (6481:5): [True: 0, False: 8.39k] ------------------ 6482| 0| case ARM::D12_D14_D16: OpKind = MCK_Reg96; break; ------------------ | Branch (6482:5): [True: 0, False: 8.39k] ------------------ 6483| 0| case ARM::D13_D15_D17: OpKind = MCK_Reg96; break; ------------------ | Branch (6483:5): [True: 0, False: 8.39k] ------------------ 6484| 0| case ARM::D14_D16_D18: OpKind = MCK_Reg97; break; ------------------ | Branch (6484:5): [True: 0, False: 8.39k] ------------------ 6485| 0| case ARM::D15_D17_D19: OpKind = MCK_Reg97; break; ------------------ | Branch (6485:5): [True: 0, False: 8.39k] ------------------ 6486| 0| case ARM::D16_D18_D20: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6486:5): [True: 0, False: 8.39k] ------------------ 6487| 0| case ARM::D17_D19_D21: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6487:5): [True: 0, False: 8.39k] ------------------ 6488| 0| case ARM::D18_D20_D22: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6488:5): [True: 0, False: 8.39k] ------------------ 6489| 0| case ARM::D19_D21_D23: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6489:5): [True: 0, False: 8.39k] ------------------ 6490| 0| case ARM::D20_D22_D24: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6490:5): [True: 0, False: 8.39k] ------------------ 6491| 0| case ARM::D21_D23_D25: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6491:5): [True: 0, False: 8.39k] ------------------ 6492| 0| case ARM::D22_D24_D26: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6492:5): [True: 0, False: 8.39k] ------------------ 6493| 0| case ARM::D23_D25_D27: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6493:5): [True: 0, False: 8.39k] ------------------ 6494| 0| case ARM::D24_D26_D28: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6494:5): [True: 0, False: 8.39k] ------------------ 6495| 0| case ARM::D25_D27_D29: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6495:5): [True: 0, False: 8.39k] ------------------ 6496| 0| case ARM::D26_D28_D30: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6496:5): [True: 0, False: 8.39k] ------------------ 6497| 0| case ARM::D27_D29_D31: OpKind = MCK_DTripleSpc; break; ------------------ | Branch (6497:5): [True: 0, False: 8.39k] ------------------ 6498| 0| case ARM::D1_D2: OpKind = MCK_Reg25; break; ------------------ | Branch (6498:5): [True: 0, False: 8.39k] ------------------ 6499| 0| case ARM::D3_D4: OpKind = MCK_Reg25; break; ------------------ | Branch (6499:5): [True: 0, False: 8.39k] ------------------ 6500| 0| case ARM::D5_D6: OpKind = MCK_Reg25; break; ------------------ | Branch (6500:5): [True: 0, False: 8.39k] ------------------ 6501| 0| case ARM::D7_D8: OpKind = MCK_Reg26; break; ------------------ | Branch (6501:5): [True: 0, False: 8.39k] ------------------ 6502| 0| case ARM::D9_D10: OpKind = MCK_Reg23; break; ------------------ | Branch (6502:5): [True: 0, False: 8.39k] ------------------ 6503| 0| case ARM::D11_D12: OpKind = MCK_Reg23; break; ------------------ | Branch (6503:5): [True: 0, False: 8.39k] ------------------ 6504| 0| case ARM::D13_D14: OpKind = MCK_Reg23; break; ------------------ | Branch (6504:5): [True: 0, False: 8.39k] ------------------ 6505| 0| case ARM::D15_D16: OpKind = MCK_Reg24; break; ------------------ | Branch (6505:5): [True: 0, False: 8.39k] ------------------ 6506| 0| case ARM::D17_D18: OpKind = MCK_DPair; break; ------------------ | Branch (6506:5): [True: 0, False: 8.39k] ------------------ 6507| 0| case ARM::D19_D20: OpKind = MCK_DPair; break; ------------------ | Branch (6507:5): [True: 0, False: 8.39k] ------------------ 6508| 0| case ARM::D21_D22: OpKind = MCK_DPair; break; ------------------ | Branch (6508:5): [True: 0, False: 8.39k] ------------------ 6509| 0| case ARM::D23_D24: OpKind = MCK_DPair; break; ------------------ | Branch (6509:5): [True: 0, False: 8.39k] ------------------ 6510| 0| case ARM::D25_D26: OpKind = MCK_DPair; break; ------------------ | Branch (6510:5): [True: 0, False: 8.39k] ------------------ 6511| 0| case ARM::D27_D28: OpKind = MCK_DPair; break; ------------------ | Branch (6511:5): [True: 0, False: 8.39k] ------------------ 6512| 0| case ARM::D29_D30: OpKind = MCK_DPair; break; ------------------ | Branch (6512:5): [True: 0, False: 8.39k] ------------------ 6513| 0| case ARM::D1_D2_D3_D4: OpKind = MCK_Reg99; break; ------------------ | Branch (6513:5): [True: 0, False: 8.39k] ------------------ 6514| 0| case ARM::D3_D4_D5_D6: OpKind = MCK_Reg99; break; ------------------ | Branch (6514:5): [True: 0, False: 8.39k] ------------------ 6515| 0| case ARM::D5_D6_D7_D8: OpKind = MCK_Reg100; break; ------------------ | Branch (6515:5): [True: 0, False: 8.39k] ------------------ 6516| 0| case ARM::D7_D8_D9_D10: OpKind = MCK_Reg101; break; ------------------ | Branch (6516:5): [True: 0, False: 8.39k] ------------------ 6517| 0| case ARM::D9_D10_D11_D12: OpKind = MCK_Reg102; break; ------------------ | Branch (6517:5): [True: 0, False: 8.39k] ------------------ 6518| 0| case ARM::D11_D12_D13_D14: OpKind = MCK_Reg102; break; ------------------ | Branch (6518:5): [True: 0, False: 8.39k] ------------------ 6519| 0| case ARM::D13_D14_D15_D16: OpKind = MCK_Reg103; break; ------------------ | Branch (6519:5): [True: 0, False: 8.39k] ------------------ 6520| 0| case ARM::D15_D16_D17_D18: OpKind = MCK_Reg104; break; ------------------ | Branch (6520:5): [True: 0, False: 8.39k] ------------------ 6521| 0| case ARM::D17_D18_D19_D20: OpKind = MCK_Reg105; break; ------------------ | Branch (6521:5): [True: 0, False: 8.39k] ------------------ 6522| 0| case ARM::D19_D20_D21_D22: OpKind = MCK_Reg105; break; ------------------ | Branch (6522:5): [True: 0, False: 8.39k] ------------------ 6523| 0| case ARM::D21_D22_D23_D24: OpKind = MCK_Reg105; break; ------------------ | Branch (6523:5): [True: 0, False: 8.39k] ------------------ 6524| 0| case ARM::D23_D24_D25_D26: OpKind = MCK_Reg105; break; ------------------ | Branch (6524:5): [True: 0, False: 8.39k] ------------------ 6525| 0| case ARM::D25_D26_D27_D28: OpKind = MCK_Reg105; break; ------------------ | Branch (6525:5): [True: 0, False: 8.39k] ------------------ 6526| 0| case ARM::D27_D28_D29_D30: OpKind = MCK_Reg105; break; ------------------ | Branch (6526:5): [True: 0, False: 8.39k] ------------------ 6527| 8.39k| } 6528| 8.39k| return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success : ------------------ | Branch (6528:12): [True: 6.66k, False: 1.73k] ------------------ 6529| 8.39k| MCTargetAsmParser::Match_InvalidOperand; 6530| 8.39k| } 6531| | 6532| 4.13k| return MCTargetAsmParser::Match_InvalidOperand; 6533| 12.5k|} ARMAsmParser.cpp:_ZL10isSubclassN12_GLOBAL__N_114MatchClassKindES0_: 4471| 11.0k|static bool isSubclass(MatchClassKind A, MatchClassKind B) { 4472| 11.0k| if (A == B) ------------------ | Branch (4472:7): [True: 1.83k, False: 9.25k] ------------------ 4473| 1.83k| return true; 4474| | 4475| 9.25k| switch (A) { 4476| 2.17k| default: ------------------ | Branch (4476:3): [True: 2.17k, False: 7.07k] ------------------ 4477| 2.17k| return false; 4478| | 4479| 0| case MCK__DOT_d: ------------------ | Branch (4479:3): [True: 0, False: 9.25k] ------------------ 4480| 0| switch (B) { 4481| 0| default: return false; ------------------ | Branch (4481:5): [True: 0, False: 0] ------------------ 4482| 0| case MCK__DOT_f64: return true; ------------------ | Branch (4482:5): [True: 0, False: 0] ------------------ 4483| 0| case MCK__DOT_64: return true; ------------------ | Branch (4483:5): [True: 0, False: 0] ------------------ 4484| 0| } 4485| | 4486| 0| case MCK__DOT_f: ------------------ | Branch (4486:3): [True: 0, False: 9.25k] ------------------ 4487| 0| switch (B) { 4488| 0| default: return false; ------------------ | Branch (4488:5): [True: 0, False: 0] ------------------ 4489| 0| case MCK__DOT_f32: return true; ------------------ | Branch (4489:5): [True: 0, False: 0] ------------------ 4490| 0| case MCK__DOT_32: return true; ------------------ | Branch (4490:5): [True: 0, False: 0] ------------------ 4491| 0| } 4492| | 4493| 0| case MCK__DOT_s16: ------------------ | Branch (4493:3): [True: 0, False: 9.25k] ------------------ 4494| 0| switch (B) { 4495| 0| default: return false; ------------------ | Branch (4495:5): [True: 0, False: 0] ------------------ 4496| 0| case MCK__DOT_i16: return true; ------------------ | Branch (4496:5): [True: 0, False: 0] ------------------ 4497| 0| case MCK__DOT_16: return true; ------------------ | Branch (4497:5): [True: 0, False: 0] ------------------ 4498| 0| } 4499| | 4500| 0| case MCK__DOT_s32: ------------------ | Branch (4500:3): [True: 0, False: 9.25k] ------------------ 4501| 0| switch (B) { 4502| 0| default: return false; ------------------ | Branch (4502:5): [True: 0, False: 0] ------------------ 4503| 0| case MCK__DOT_i32: return true; ------------------ | Branch (4503:5): [True: 0, False: 0] ------------------ 4504| 0| case MCK__DOT_32: return true; ------------------ | Branch (4504:5): [True: 0, False: 0] ------------------ 4505| 0| } 4506| | 4507| 0| case MCK__DOT_s64: ------------------ | Branch (4507:3): [True: 0, False: 9.25k] ------------------ 4508| 0| switch (B) { 4509| 0| default: return false; ------------------ | Branch (4509:5): [True: 0, False: 0] ------------------ 4510| 0| case MCK__DOT_i64: return true; ------------------ | Branch (4510:5): [True: 0, False: 0] ------------------ 4511| 0| case MCK__DOT_64: return true; ------------------ | Branch (4511:5): [True: 0, False: 0] ------------------ 4512| 0| } 4513| | 4514| 0| case MCK__DOT_s8: ------------------ | Branch (4514:3): [True: 0, False: 9.25k] ------------------ 4515| 0| switch (B) { 4516| 0| default: return false; ------------------ | Branch (4516:5): [True: 0, False: 0] ------------------ 4517| 0| case MCK__DOT_i8: return true; ------------------ | Branch (4517:5): [True: 0, False: 0] ------------------ 4518| 0| case MCK__DOT_8: return true; ------------------ | Branch (4518:5): [True: 0, False: 0] ------------------ 4519| 0| } 4520| | 4521| 0| case MCK__DOT_u16: ------------------ | Branch (4521:3): [True: 0, False: 9.25k] ------------------ 4522| 0| switch (B) { 4523| 0| default: return false; ------------------ | Branch (4523:5): [True: 0, False: 0] ------------------ 4524| 0| case MCK__DOT_i16: return true; ------------------ | Branch (4524:5): [True: 0, False: 0] ------------------ 4525| 0| case MCK__DOT_16: return true; ------------------ | Branch (4525:5): [True: 0, False: 0] ------------------ 4526| 0| } 4527| | 4528| 0| case MCK__DOT_u32: ------------------ | Branch (4528:3): [True: 0, False: 9.25k] ------------------ 4529| 0| switch (B) { 4530| 0| default: return false; ------------------ | Branch (4530:5): [True: 0, False: 0] ------------------ 4531| 0| case MCK__DOT_i32: return true; ------------------ | Branch (4531:5): [True: 0, False: 0] ------------------ 4532| 0| case MCK__DOT_32: return true; ------------------ | Branch (4532:5): [True: 0, False: 0] ------------------ 4533| 0| } 4534| | 4535| 0| case MCK__DOT_u64: ------------------ | Branch (4535:3): [True: 0, False: 9.25k] ------------------ 4536| 0| switch (B) { 4537| 0| default: return false; ------------------ | Branch (4537:5): [True: 0, False: 0] ------------------ 4538| 0| case MCK__DOT_i64: return true; ------------------ | Branch (4538:5): [True: 0, False: 0] ------------------ 4539| 0| case MCK__DOT_64: return true; ------------------ | Branch (4539:5): [True: 0, False: 0] ------------------ 4540| 0| } 4541| | 4542| 0| case MCK__DOT_u8: ------------------ | Branch (4542:3): [True: 0, False: 9.25k] ------------------ 4543| 0| switch (B) { 4544| 0| default: return false; ------------------ | Branch (4544:5): [True: 0, False: 0] ------------------ 4545| 0| case MCK__DOT_i8: return true; ------------------ | Branch (4545:5): [True: 0, False: 0] ------------------ 4546| 0| case MCK__DOT_8: return true; ------------------ | Branch (4546:5): [True: 0, False: 0] ------------------ 4547| 0| } 4548| | 4549| 0| case MCK__DOT_f32: ------------------ | Branch (4549:3): [True: 0, False: 9.25k] ------------------ 4550| 0| return B == MCK__DOT_32; 4551| | 4552| 0| case MCK__DOT_f64: ------------------ | Branch (4552:3): [True: 0, False: 9.25k] ------------------ 4553| 0| return B == MCK__DOT_64; 4554| | 4555| 0| case MCK__DOT_i16: ------------------ | Branch (4555:3): [True: 0, False: 9.25k] ------------------ 4556| 0| return B == MCK__DOT_16; 4557| | 4558| 0| case MCK__DOT_i32: ------------------ | Branch (4558:3): [True: 0, False: 9.25k] ------------------ 4559| 0| return B == MCK__DOT_32; 4560| | 4561| 0| case MCK__DOT_i64: ------------------ | Branch (4561:3): [True: 0, False: 9.25k] ------------------ 4562| 0| return B == MCK__DOT_64; 4563| | 4564| 0| case MCK__DOT_i8: ------------------ | Branch (4564:3): [True: 0, False: 9.25k] ------------------ 4565| 0| return B == MCK__DOT_8; 4566| | 4567| 0| case MCK__DOT_p16: ------------------ | Branch (4567:3): [True: 0, False: 9.25k] ------------------ 4568| 0| return B == MCK__DOT_16; 4569| | 4570| 0| case MCK__DOT_p8: ------------------ | Branch (4570:3): [True: 0, False: 9.25k] ------------------ 4571| 0| return B == MCK__DOT_8; 4572| | 4573| 0| case MCK_Reg74: ------------------ | Branch (4573:3): [True: 0, False: 9.25k] ------------------ 4574| 0| switch (B) { 4575| 0| default: return false; ------------------ | Branch (4575:5): [True: 0, False: 0] ------------------ 4576| 0| case MCK_Reg73: return true; ------------------ | Branch (4576:5): [True: 0, False: 0] ------------------ 4577| 0| case MCK_Reg71: return true; ------------------ | Branch (4577:5): [True: 0, False: 0] ------------------ 4578| 0| case MCK_GPRPair: return true; ------------------ | Branch (4578:5): [True: 0, False: 0] ------------------ 4579| 0| } 4580| | 4581| 0| case MCK_Reg58: ------------------ | Branch (4581:3): [True: 0, False: 9.25k] ------------------ 4582| 0| switch (B) { 4583| 0| default: return false; ------------------ | Branch (4583:5): [True: 0, False: 0] ------------------ 4584| 0| case MCK_Reg59: return true; ------------------ | Branch (4584:5): [True: 0, False: 0] ------------------ 4585| 0| case MCK_Reg60: return true; ------------------ | Branch (4585:5): [True: 0, False: 0] ------------------ 4586| 0| case MCK_Reg61: return true; ------------------ | Branch (4586:5): [True: 0, False: 0] ------------------ 4587| 0| case MCK_Reg62: return true; ------------------ | Branch (4587:5): [True: 0, False: 0] ------------------ 4588| 0| case MCK_Reg63: return true; ------------------ | Branch (4588:5): [True: 0, False: 0] ------------------ 4589| 0| case MCK_Reg64: return true; ------------------ | Branch (4589:5): [True: 0, False: 0] ------------------ 4590| 0| case MCK_Reg65: return true; ------------------ | Branch (4590:5): [True: 0, False: 0] ------------------ 4591| 0| case MCK_QQQQPR: return true; ------------------ | Branch (4591:5): [True: 0, False: 0] ------------------ 4592| 0| } 4593| | 4594| 98| case MCK_Reg10: ------------------ | Branch (4594:3): [True: 98, False: 9.15k] ------------------ 4595| 98| switch (B) { 4596| 18| default: return false; ------------------ | Branch (4596:5): [True: 18, False: 80] ------------------ 4597| 0| case MCK_tcGPR: return true; ------------------ | Branch (4597:5): [True: 0, False: 98] ------------------ 4598| 0| case MCK_Reg9: return true; ------------------ | Branch (4598:5): [True: 0, False: 98] ------------------ 4599| 0| case MCK_Reg7: return true; ------------------ | Branch (4599:5): [True: 0, False: 98] ------------------ 4600| 0| case MCK_hGPR: return true; ------------------ | Branch (4600:5): [True: 0, False: 98] ------------------ 4601| 68| case MCK_rGPR: return true; ------------------ | Branch (4601:5): [True: 68, False: 30] ------------------ 4602| 9| case MCK_GPRnopc: return true; ------------------ | Branch (4602:5): [True: 9, False: 89] ------------------ 4603| 3| case MCK_GPR: return true; ------------------ | Branch (4603:5): [True: 3, False: 95] ------------------ 4604| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (4604:5): [True: 0, False: 98] ------------------ 4605| 98| } 4606| | 4607| 0| case MCK_APSR_NZCV: ------------------ | Branch (4607:3): [True: 0, False: 9.25k] ------------------ 4608| 0| return B == MCK_GPRwithAPSR; 4609| | 4610| 1.00k| case MCK_GPRsp: ------------------ | Branch (4610:3): [True: 1.00k, False: 8.25k] ------------------ 4611| 1.00k| switch (B) { 4612| 253| default: return false; ------------------ | Branch (4612:5): [True: 253, False: 747] ------------------ 4613| 0| case MCK_Reg7: return true; ------------------ | Branch (4613:5): [True: 0, False: 1.00k] ------------------ 4614| 0| case MCK_hGPR: return true; ------------------ | Branch (4614:5): [True: 0, False: 1.00k] ------------------ 4615| 465| case MCK_GPRnopc: return true; ------------------ | Branch (4615:5): [True: 465, False: 535] ------------------ 4616| 282| case MCK_GPR: return true; ------------------ | Branch (4616:5): [True: 282, False: 718] ------------------ 4617| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (4617:5): [True: 0, False: 1.00k] ------------------ 4618| 1.00k| } 4619| | 4620| 22| case MCK_LR: ------------------ | Branch (4620:3): [True: 22, False: 9.23k] ------------------ 4621| 22| switch (B) { 4622| 12| default: return false; ------------------ | Branch (4622:5): [True: 12, False: 10] ------------------ 4623| 0| case MCK_Reg9: return true; ------------------ | Branch (4623:5): [True: 0, False: 22] ------------------ 4624| 0| case MCK_Reg7: return true; ------------------ | Branch (4624:5): [True: 0, False: 22] ------------------ 4625| 0| case MCK_hGPR: return true; ------------------ | Branch (4625:5): [True: 0, False: 22] ------------------ 4626| 2| case MCK_rGPR: return true; ------------------ | Branch (4626:5): [True: 2, False: 20] ------------------ 4627| 6| case MCK_GPRnopc: return true; ------------------ | Branch (4627:5): [True: 6, False: 16] ------------------ 4628| 2| case MCK_GPR: return true; ------------------ | Branch (4628:5): [True: 2, False: 20] ------------------ 4629| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (4629:5): [True: 0, False: 22] ------------------ 4630| 22| } 4631| | 4632| 0| case MCK_PC: ------------------ | Branch (4632:3): [True: 0, False: 9.25k] ------------------ 4633| 0| switch (B) { 4634| 0| default: return false; ------------------ | Branch (4634:5): [True: 0, False: 0] ------------------ 4635| 0| case MCK_hGPR: return true; ------------------ | Branch (4635:5): [True: 0, False: 0] ------------------ 4636| 0| case MCK_GPR: return true; ------------------ | Branch (4636:5): [True: 0, False: 0] ------------------ 4637| 0| } 4638| | 4639| 0| case MCK_Reg99: ------------------ | Branch (4639:3): [True: 0, False: 9.25k] ------------------ 4640| 0| switch (B) { 4641| 0| default: return false; ------------------ | Branch (4641:5): [True: 0, False: 0] ------------------ 4642| 0| case MCK_Reg100: return true; ------------------ | Branch (4642:5): [True: 0, False: 0] ------------------ 4643| 0| case MCK_Reg101: return true; ------------------ | Branch (4643:5): [True: 0, False: 0] ------------------ 4644| 0| case MCK_Reg56: return true; ------------------ | Branch (4644:5): [True: 0, False: 0] ------------------ 4645| 0| case MCK_Reg102: return true; ------------------ | Branch (4645:5): [True: 0, False: 0] ------------------ 4646| 0| case MCK_Reg57: return true; ------------------ | Branch (4646:5): [True: 0, False: 0] ------------------ 4647| 0| case MCK_Reg103: return true; ------------------ | Branch (4647:5): [True: 0, False: 0] ------------------ 4648| 0| case MCK_Reg54: return true; ------------------ | Branch (4648:5): [True: 0, False: 0] ------------------ 4649| 0| case MCK_Reg104: return true; ------------------ | Branch (4649:5): [True: 0, False: 0] ------------------ 4650| 0| case MCK_Reg55: return true; ------------------ | Branch (4650:5): [True: 0, False: 0] ------------------ 4651| 0| case MCK_Reg52: return true; ------------------ | Branch (4651:5): [True: 0, False: 0] ------------------ 4652| 0| case MCK_Reg105: return true; ------------------ | Branch (4652:5): [True: 0, False: 0] ------------------ 4653| 0| case MCK_Reg53: return true; ------------------ | Branch (4653:5): [True: 0, False: 0] ------------------ 4654| 0| case MCK_Reg50: return true; ------------------ | Branch (4654:5): [True: 0, False: 0] ------------------ 4655| 0| case MCK_Reg51: return true; ------------------ | Branch (4655:5): [True: 0, False: 0] ------------------ 4656| 0| case MCK_DQuad: return true; ------------------ | Branch (4656:5): [True: 0, False: 0] ------------------ 4657| 0| } 4658| | 4659| 0| case MCK_Reg72: ------------------ | Branch (4659:3): [True: 0, False: 9.25k] ------------------ 4660| 0| switch (B) { 4661| 0| default: return false; ------------------ | Branch (4661:5): [True: 0, False: 0] ------------------ 4662| 0| case MCK_Reg73: return true; ------------------ | Branch (4662:5): [True: 0, False: 0] ------------------ 4663| 0| case MCK_Reg69: return true; ------------------ | Branch (4663:5): [True: 0, False: 0] ------------------ 4664| 0| case MCK_GPRPair: return true; ------------------ | Branch (4664:5): [True: 0, False: 0] ------------------ 4665| 0| } 4666| | 4667| 0| case MCK_Reg67: ------------------ | Branch (4667:3): [True: 0, False: 9.25k] ------------------ 4668| 0| switch (B) { 4669| 0| default: return false; ------------------ | Branch (4669:5): [True: 0, False: 0] ------------------ 4670| 0| case MCK_Reg71: return true; ------------------ | Branch (4670:5): [True: 0, False: 0] ------------------ 4671| 0| case MCK_Reg68: return true; ------------------ | Branch (4671:5): [True: 0, False: 0] ------------------ 4672| 0| case MCK_Reg69: return true; ------------------ | Branch (4672:5): [True: 0, False: 0] ------------------ 4673| 0| case MCK_GPRPair: return true; ------------------ | Branch (4673:5): [True: 0, False: 0] ------------------ 4674| 0| } 4675| | 4676| 0| case MCK_Reg59: ------------------ | Branch (4676:3): [True: 0, False: 9.25k] ------------------ 4677| 0| switch (B) { 4678| 0| default: return false; ------------------ | Branch (4678:5): [True: 0, False: 0] ------------------ 4679| 0| case MCK_Reg60: return true; ------------------ | Branch (4679:5): [True: 0, False: 0] ------------------ 4680| 0| case MCK_Reg61: return true; ------------------ | Branch (4680:5): [True: 0, False: 0] ------------------ 4681| 0| case MCK_Reg62: return true; ------------------ | Branch (4681:5): [True: 0, False: 0] ------------------ 4682| 0| case MCK_Reg63: return true; ------------------ | Branch (4682:5): [True: 0, False: 0] ------------------ 4683| 0| case MCK_Reg64: return true; ------------------ | Branch (4683:5): [True: 0, False: 0] ------------------ 4684| 0| case MCK_Reg65: return true; ------------------ | Branch (4684:5): [True: 0, False: 0] ------------------ 4685| 0| case MCK_QQQQPR: return true; ------------------ | Branch (4685:5): [True: 0, False: 0] ------------------ 4686| 0| } 4687| | 4688| 0| case MCK_Reg100: ------------------ | Branch (4688:3): [True: 0, False: 9.25k] ------------------ 4689| 0| switch (B) { 4690| 0| default: return false; ------------------ | Branch (4690:5): [True: 0, False: 0] ------------------ 4691| 0| case MCK_Reg101: return true; ------------------ | Branch (4691:5): [True: 0, False: 0] ------------------ 4692| 0| case MCK_Reg102: return true; ------------------ | Branch (4692:5): [True: 0, False: 0] ------------------ 4693| 0| case MCK_Reg57: return true; ------------------ | Branch (4693:5): [True: 0, False: 0] ------------------ 4694| 0| case MCK_Reg103: return true; ------------------ | Branch (4694:5): [True: 0, False: 0] ------------------ 4695| 0| case MCK_Reg54: return true; ------------------ | Branch (4695:5): [True: 0, False: 0] ------------------ 4696| 0| case MCK_Reg104: return true; ------------------ | Branch (4696:5): [True: 0, False: 0] ------------------ 4697| 0| case MCK_Reg55: return true; ------------------ | Branch (4697:5): [True: 0, False: 0] ------------------ 4698| 0| case MCK_Reg52: return true; ------------------ | Branch (4698:5): [True: 0, False: 0] ------------------ 4699| 0| case MCK_Reg105: return true; ------------------ | Branch (4699:5): [True: 0, False: 0] ------------------ 4700| 0| case MCK_Reg53: return true; ------------------ | Branch (4700:5): [True: 0, False: 0] ------------------ 4701| 0| case MCK_Reg50: return true; ------------------ | Branch (4701:5): [True: 0, False: 0] ------------------ 4702| 0| case MCK_Reg51: return true; ------------------ | Branch (4702:5): [True: 0, False: 0] ------------------ 4703| 0| case MCK_DQuad: return true; ------------------ | Branch (4703:5): [True: 0, False: 0] ------------------ 4704| 0| } 4705| | 4706| 0| case MCK_Reg87: ------------------ | Branch (4706:3): [True: 0, False: 9.25k] ------------------ 4707| 0| switch (B) { 4708| 0| default: return false; ------------------ | Branch (4708:5): [True: 0, False: 0] ------------------ 4709| 0| case MCK_Reg88: return true; ------------------ | Branch (4709:5): [True: 0, False: 0] ------------------ 4710| 0| case MCK_Reg75: return true; ------------------ | Branch (4710:5): [True: 0, False: 0] ------------------ 4711| 0| case MCK_Reg89: return true; ------------------ | Branch (4711:5): [True: 0, False: 0] ------------------ 4712| 0| case MCK_Reg76: return true; ------------------ | Branch (4712:5): [True: 0, False: 0] ------------------ 4713| 0| case MCK_Reg90: return true; ------------------ | Branch (4713:5): [True: 0, False: 0] ------------------ 4714| 0| case MCK_Reg77: return true; ------------------ | Branch (4714:5): [True: 0, False: 0] ------------------ 4715| 0| case MCK_Reg78: return true; ------------------ | Branch (4715:5): [True: 0, False: 0] ------------------ 4716| 0| case MCK_Reg91: return true; ------------------ | Branch (4716:5): [True: 0, False: 0] ------------------ 4717| 0| case MCK_Reg79: return true; ------------------ | Branch (4717:5): [True: 0, False: 0] ------------------ 4718| 0| case MCK_Reg80: return true; ------------------ | Branch (4718:5): [True: 0, False: 0] ------------------ 4719| 0| case MCK_DTriple: return true; ------------------ | Branch (4719:5): [True: 0, False: 0] ------------------ 4720| 0| } 4721| | 4722| 0| case MCK_Reg82: ------------------ | Branch (4722:3): [True: 0, False: 9.25k] ------------------ 4723| 0| switch (B) { 4724| 0| default: return false; ------------------ | Branch (4724:5): [True: 0, False: 0] ------------------ 4725| 0| case MCK_Reg83: return true; ------------------ | Branch (4725:5): [True: 0, False: 0] ------------------ 4726| 0| case MCK_Reg75: return true; ------------------ | Branch (4726:5): [True: 0, False: 0] ------------------ 4727| 0| case MCK_Reg84: return true; ------------------ | Branch (4727:5): [True: 0, False: 0] ------------------ 4728| 0| case MCK_Reg76: return true; ------------------ | Branch (4728:5): [True: 0, False: 0] ------------------ 4729| 0| case MCK_Reg85: return true; ------------------ | Branch (4729:5): [True: 0, False: 0] ------------------ 4730| 0| case MCK_Reg77: return true; ------------------ | Branch (4730:5): [True: 0, False: 0] ------------------ 4731| 0| case MCK_Reg78: return true; ------------------ | Branch (4731:5): [True: 0, False: 0] ------------------ 4732| 0| case MCK_Reg86: return true; ------------------ | Branch (4732:5): [True: 0, False: 0] ------------------ 4733| 0| case MCK_Reg79: return true; ------------------ | Branch (4733:5): [True: 0, False: 0] ------------------ 4734| 0| case MCK_Reg80: return true; ------------------ | Branch (4734:5): [True: 0, False: 0] ------------------ 4735| 0| case MCK_DTriple: return true; ------------------ | Branch (4735:5): [True: 0, False: 0] ------------------ 4736| 0| } 4737| | 4738| 0| case MCK_Reg73: ------------------ | Branch (4738:3): [True: 0, False: 9.25k] ------------------ 4739| 0| return B == MCK_GPRPair; 4740| | 4741| 0| case MCK_Reg71: ------------------ | Branch (4741:3): [True: 0, False: 9.25k] ------------------ 4742| 0| return B == MCK_GPRPair; 4743| | 4744| 0| case MCK_Reg60: ------------------ | Branch (4744:3): [True: 0, False: 9.25k] ------------------ 4745| 0| switch (B) { 4746| 0| default: return false; ------------------ | Branch (4746:5): [True: 0, False: 0] ------------------ 4747| 0| case MCK_Reg61: return true; ------------------ | Branch (4747:5): [True: 0, False: 0] ------------------ 4748| 0| case MCK_Reg62: return true; ------------------ | Branch (4748:5): [True: 0, False: 0] ------------------ 4749| 0| case MCK_Reg63: return true; ------------------ | Branch (4749:5): [True: 0, False: 0] ------------------ 4750| 0| case MCK_Reg64: return true; ------------------ | Branch (4750:5): [True: 0, False: 0] ------------------ 4751| 0| case MCK_Reg65: return true; ------------------ | Branch (4751:5): [True: 0, False: 0] ------------------ 4752| 0| case MCK_QQQQPR: return true; ------------------ | Branch (4752:5): [True: 0, False: 0] ------------------ 4753| 0| } 4754| | 4755| 0| case MCK_Reg44: ------------------ | Branch (4755:3): [True: 0, False: 9.25k] ------------------ 4756| 0| switch (B) { 4757| 0| default: return false; ------------------ | Branch (4757:5): [True: 0, False: 0] ------------------ 4758| 0| case MCK_Reg45: return true; ------------------ | Branch (4758:5): [True: 0, False: 0] ------------------ 4759| 0| case MCK_Reg56: return true; ------------------ | Branch (4759:5): [True: 0, False: 0] ------------------ 4760| 0| case MCK_Reg57: return true; ------------------ | Branch (4760:5): [True: 0, False: 0] ------------------ 4761| 0| case MCK_Reg54: return true; ------------------ | Branch (4761:5): [True: 0, False: 0] ------------------ 4762| 0| case MCK_Reg46: return true; ------------------ | Branch (4762:5): [True: 0, False: 0] ------------------ 4763| 0| case MCK_Reg55: return true; ------------------ | Branch (4763:5): [True: 0, False: 0] ------------------ 4764| 0| case MCK_Reg47: return true; ------------------ | Branch (4764:5): [True: 0, False: 0] ------------------ 4765| 0| case MCK_Reg52: return true; ------------------ | Branch (4765:5): [True: 0, False: 0] ------------------ 4766| 0| case MCK_Reg53: return true; ------------------ | Branch (4766:5): [True: 0, False: 0] ------------------ 4767| 0| case MCK_Reg50: return true; ------------------ | Branch (4767:5): [True: 0, False: 0] ------------------ 4768| 0| case MCK_QQPR: return true; ------------------ | Branch (4768:5): [True: 0, False: 0] ------------------ 4769| 0| case MCK_Reg51: return true; ------------------ | Branch (4769:5): [True: 0, False: 0] ------------------ 4770| 0| case MCK_DQuad: return true; ------------------ | Branch (4770:5): [True: 0, False: 0] ------------------ 4771| 0| } 4772| | 4773| 0| case MCK_Reg101: ------------------ | Branch (4773:3): [True: 0, False: 9.25k] ------------------ 4774| 0| switch (B) { 4775| 0| default: return false; ------------------ | Branch (4775:5): [True: 0, False: 0] ------------------ 4776| 0| case MCK_Reg102: return true; ------------------ | Branch (4776:5): [True: 0, False: 0] ------------------ 4777| 0| case MCK_Reg103: return true; ------------------ | Branch (4777:5): [True: 0, False: 0] ------------------ 4778| 0| case MCK_Reg104: return true; ------------------ | Branch (4778:5): [True: 0, False: 0] ------------------ 4779| 0| case MCK_Reg55: return true; ------------------ | Branch (4779:5): [True: 0, False: 0] ------------------ 4780| 0| case MCK_Reg52: return true; ------------------ | Branch (4780:5): [True: 0, False: 0] ------------------ 4781| 0| case MCK_Reg105: return true; ------------------ | Branch (4781:5): [True: 0, False: 0] ------------------ 4782| 0| case MCK_Reg53: return true; ------------------ | Branch (4782:5): [True: 0, False: 0] ------------------ 4783| 0| case MCK_Reg50: return true; ------------------ | Branch (4783:5): [True: 0, False: 0] ------------------ 4784| 0| case MCK_Reg51: return true; ------------------ | Branch (4784:5): [True: 0, False: 0] ------------------ 4785| 0| case MCK_DQuad: return true; ------------------ | Branch (4785:5): [True: 0, False: 0] ------------------ 4786| 0| } 4787| | 4788| 0| case MCK_Reg92: ------------------ | Branch (4788:3): [True: 0, False: 9.25k] ------------------ 4789| 0| switch (B) { 4790| 0| default: return false; ------------------ | Branch (4790:5): [True: 0, False: 0] ------------------ 4791| 0| case MCK_Reg93: return true; ------------------ | Branch (4791:5): [True: 0, False: 0] ------------------ 4792| 0| case MCK_Reg94: return true; ------------------ | Branch (4792:5): [True: 0, False: 0] ------------------ 4793| 0| case MCK_Reg95: return true; ------------------ | Branch (4793:5): [True: 0, False: 0] ------------------ 4794| 0| case MCK_Reg96: return true; ------------------ | Branch (4794:5): [True: 0, False: 0] ------------------ 4795| 0| case MCK_Reg97: return true; ------------------ | Branch (4795:5): [True: 0, False: 0] ------------------ 4796| 0| case MCK_DTripleSpc: return true; ------------------ | Branch (4796:5): [True: 0, False: 0] ------------------ 4797| 0| } 4798| | 4799| 0| case MCK_Reg88: ------------------ | Branch (4799:3): [True: 0, False: 9.25k] ------------------ 4800| 0| switch (B) { 4801| 0| default: return false; ------------------ | Branch (4801:5): [True: 0, False: 0] ------------------ 4802| 0| case MCK_Reg89: return true; ------------------ | Branch (4802:5): [True: 0, False: 0] ------------------ 4803| 0| case MCK_Reg90: return true; ------------------ | Branch (4803:5): [True: 0, False: 0] ------------------ 4804| 0| case MCK_Reg77: return true; ------------------ | Branch (4804:5): [True: 0, False: 0] ------------------ 4805| 0| case MCK_Reg78: return true; ------------------ | Branch (4805:5): [True: 0, False: 0] ------------------ 4806| 0| case MCK_Reg91: return true; ------------------ | Branch (4806:5): [True: 0, False: 0] ------------------ 4807| 0| case MCK_Reg79: return true; ------------------ | Branch (4807:5): [True: 0, False: 0] ------------------ 4808| 0| case MCK_Reg80: return true; ------------------ | Branch (4808:5): [True: 0, False: 0] ------------------ 4809| 0| case MCK_DTriple: return true; ------------------ | Branch (4809:5): [True: 0, False: 0] ------------------ 4810| 0| } 4811| | 4812| 0| case MCK_Reg83: ------------------ | Branch (4812:3): [True: 0, False: 9.25k] ------------------ 4813| 0| switch (B) { 4814| 0| default: return false; ------------------ | Branch (4814:5): [True: 0, False: 0] ------------------ 4815| 0| case MCK_Reg84: return true; ------------------ | Branch (4815:5): [True: 0, False: 0] ------------------ 4816| 0| case MCK_Reg76: return true; ------------------ | Branch (4816:5): [True: 0, False: 0] ------------------ 4817| 0| case MCK_Reg85: return true; ------------------ | Branch (4817:5): [True: 0, False: 0] ------------------ 4818| 0| case MCK_Reg77: return true; ------------------ | Branch (4818:5): [True: 0, False: 0] ------------------ 4819| 0| case MCK_Reg78: return true; ------------------ | Branch (4819:5): [True: 0, False: 0] ------------------ 4820| 0| case MCK_Reg86: return true; ------------------ | Branch (4820:5): [True: 0, False: 0] ------------------ 4821| 0| case MCK_Reg79: return true; ------------------ | Branch (4821:5): [True: 0, False: 0] ------------------ 4822| 0| case MCK_Reg80: return true; ------------------ | Branch (4822:5): [True: 0, False: 0] ------------------ 4823| 0| case MCK_DTriple: return true; ------------------ | Branch (4823:5): [True: 0, False: 0] ------------------ 4824| 0| } 4825| | 4826| 0| case MCK_Reg68: ------------------ | Branch (4826:3): [True: 0, False: 9.25k] ------------------ 4827| 0| switch (B) { 4828| 0| default: return false; ------------------ | Branch (4828:5): [True: 0, False: 0] ------------------ 4829| 0| case MCK_Reg69: return true; ------------------ | Branch (4829:5): [True: 0, False: 0] ------------------ 4830| 0| case MCK_GPRPair: return true; ------------------ | Branch (4830:5): [True: 0, False: 0] ------------------ 4831| 0| } 4832| | 4833| 0| case MCK_Reg61: ------------------ | Branch (4833:3): [True: 0, False: 9.25k] ------------------ 4834| 0| switch (B) { 4835| 0| default: return false; ------------------ | Branch (4835:5): [True: 0, False: 0] ------------------ 4836| 0| case MCK_Reg62: return true; ------------------ | Branch (4836:5): [True: 0, False: 0] ------------------ 4837| 0| case MCK_Reg63: return true; ------------------ | Branch (4837:5): [True: 0, False: 0] ------------------ 4838| 0| case MCK_Reg64: return true; ------------------ | Branch (4838:5): [True: 0, False: 0] ------------------ 4839| 0| case MCK_Reg65: return true; ------------------ | Branch (4839:5): [True: 0, False: 0] ------------------ 4840| 0| case MCK_QQQQPR: return true; ------------------ | Branch (4840:5): [True: 0, False: 0] ------------------ 4841| 0| } 4842| | 4843| 0| case MCK_Reg45: ------------------ | Branch (4843:3): [True: 0, False: 9.25k] ------------------ 4844| 0| switch (B) { 4845| 0| default: return false; ------------------ | Branch (4845:5): [True: 0, False: 0] ------------------ 4846| 0| case MCK_Reg54: return true; ------------------ | Branch (4846:5): [True: 0, False: 0] ------------------ 4847| 0| case MCK_Reg46: return true; ------------------ | Branch (4847:5): [True: 0, False: 0] ------------------ 4848| 0| case MCK_Reg55: return true; ------------------ | Branch (4848:5): [True: 0, False: 0] ------------------ 4849| 0| case MCK_Reg47: return true; ------------------ | Branch (4849:5): [True: 0, False: 0] ------------------ 4850| 0| case MCK_Reg52: return true; ------------------ | Branch (4850:5): [True: 0, False: 0] ------------------ 4851| 0| case MCK_Reg53: return true; ------------------ | Branch (4851:5): [True: 0, False: 0] ------------------ 4852| 0| case MCK_Reg50: return true; ------------------ | Branch (4852:5): [True: 0, False: 0] ------------------ 4853| 0| case MCK_QQPR: return true; ------------------ | Branch (4853:5): [True: 0, False: 0] ------------------ 4854| 0| case MCK_Reg51: return true; ------------------ | Branch (4854:5): [True: 0, False: 0] ------------------ 4855| 0| case MCK_DQuad: return true; ------------------ | Branch (4855:5): [True: 0, False: 0] ------------------ 4856| 0| } 4857| | 4858| 3.35k| case MCK_Reg0: ------------------ | Branch (4858:3): [True: 3.35k, False: 5.89k] ------------------ 4859| 3.35k| switch (B) { 4860| 800| default: return false; ------------------ | Branch (4860:5): [True: 800, False: 2.55k] ------------------ 4861| 0| case MCK_tcGPR: return true; ------------------ | Branch (4861:5): [True: 0, False: 3.35k] ------------------ 4862| 711| case MCK_tGPR: return true; ------------------ | Branch (4862:5): [True: 711, False: 2.64k] ------------------ 4863| 239| case MCK_rGPR: return true; ------------------ | Branch (4863:5): [True: 239, False: 3.11k] ------------------ 4864| 1.07k| case MCK_GPRnopc: return true; ------------------ | Branch (4864:5): [True: 1.07k, False: 2.28k] ------------------ 4865| 533| case MCK_GPR: return true; ------------------ | Branch (4865:5): [True: 533, False: 2.82k] ------------------ 4866| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (4866:5): [True: 0, False: 3.35k] ------------------ 4867| 3.35k| } 4868| | 4869| 0| case MCK_QPR_8: ------------------ | Branch (4869:3): [True: 0, False: 9.25k] ------------------ 4870| 0| switch (B) { 4871| 0| default: return false; ------------------ | Branch (4871:5): [True: 0, False: 0] ------------------ 4872| 0| case MCK_Reg25: return true; ------------------ | Branch (4872:5): [True: 0, False: 0] ------------------ 4873| 0| case MCK_Reg26: return true; ------------------ | Branch (4873:5): [True: 0, False: 0] ------------------ 4874| 0| case MCK_QPR_VFP2: return true; ------------------ | Branch (4874:5): [True: 0, False: 0] ------------------ 4875| 0| case MCK_Reg23: return true; ------------------ | Branch (4875:5): [True: 0, False: 0] ------------------ 4876| 0| case MCK_Reg24: return true; ------------------ | Branch (4876:5): [True: 0, False: 0] ------------------ 4877| 0| case MCK_QPR: return true; ------------------ | Branch (4877:5): [True: 0, False: 0] ------------------ 4878| 0| case MCK_DPair: return true; ------------------ | Branch (4878:5): [True: 0, False: 0] ------------------ 4879| 0| } 4880| | 4881| 0| case MCK_Reg62: ------------------ | Branch (4881:3): [True: 0, False: 9.25k] ------------------ 4882| 0| switch (B) { 4883| 0| default: return false; ------------------ | Branch (4883:5): [True: 0, False: 0] ------------------ 4884| 0| case MCK_Reg63: return true; ------------------ | Branch (4884:5): [True: 0, False: 0] ------------------ 4885| 0| case MCK_Reg64: return true; ------------------ | Branch (4885:5): [True: 0, False: 0] ------------------ 4886| 0| case MCK_Reg65: return true; ------------------ | Branch (4886:5): [True: 0, False: 0] ------------------ 4887| 0| case MCK_QQQQPR: return true; ------------------ | Branch (4887:5): [True: 0, False: 0] ------------------ 4888| 0| } 4889| | 4890| 0| case MCK_Reg56: ------------------ | Branch (4890:3): [True: 0, False: 9.25k] ------------------ 4891| 0| switch (B) { 4892| 0| default: return false; ------------------ | Branch (4892:5): [True: 0, False: 0] ------------------ 4893| 0| case MCK_Reg57: return true; ------------------ | Branch (4893:5): [True: 0, False: 0] ------------------ 4894| 0| case MCK_Reg54: return true; ------------------ | Branch (4894:5): [True: 0, False: 0] ------------------ 4895| 0| case MCK_Reg55: return true; ------------------ | Branch (4895:5): [True: 0, False: 0] ------------------ 4896| 0| case MCK_Reg52: return true; ------------------ | Branch (4896:5): [True: 0, False: 0] ------------------ 4897| 0| case MCK_Reg53: return true; ------------------ | Branch (4897:5): [True: 0, False: 0] ------------------ 4898| 0| case MCK_Reg50: return true; ------------------ | Branch (4898:5): [True: 0, False: 0] ------------------ 4899| 0| case MCK_Reg51: return true; ------------------ | Branch (4899:5): [True: 0, False: 0] ------------------ 4900| 0| case MCK_DQuad: return true; ------------------ | Branch (4900:5): [True: 0, False: 0] ------------------ 4901| 0| } 4902| | 4903| 0| case MCK_tcGPR: ------------------ | Branch (4903:3): [True: 0, False: 9.25k] ------------------ 4904| 0| switch (B) { 4905| 0| default: return false; ------------------ | Branch (4905:5): [True: 0, False: 0] ------------------ 4906| 0| case MCK_rGPR: return true; ------------------ | Branch (4906:5): [True: 0, False: 0] ------------------ 4907| 0| case MCK_GPRnopc: return true; ------------------ | Branch (4907:5): [True: 0, False: 0] ------------------ 4908| 0| case MCK_GPR: return true; ------------------ | Branch (4908:5): [True: 0, False: 0] ------------------ 4909| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (4909:5): [True: 0, False: 0] ------------------ 4910| 0| } 4911| | 4912| 0| case MCK_Reg102: ------------------ | Branch (4912:3): [True: 0, False: 9.25k] ------------------ 4913| 0| switch (B) { 4914| 0| default: return false; ------------------ | Branch (4914:5): [True: 0, False: 0] ------------------ 4915| 0| case MCK_Reg103: return true; ------------------ | Branch (4915:5): [True: 0, False: 0] ------------------ 4916| 0| case MCK_Reg104: return true; ------------------ | Branch (4916:5): [True: 0, False: 0] ------------------ 4917| 0| case MCK_Reg52: return true; ------------------ | Branch (4917:5): [True: 0, False: 0] ------------------ 4918| 0| case MCK_Reg105: return true; ------------------ | Branch (4918:5): [True: 0, False: 0] ------------------ 4919| 0| case MCK_Reg53: return true; ------------------ | Branch (4919:5): [True: 0, False: 0] ------------------ 4920| 0| case MCK_Reg50: return true; ------------------ | Branch (4920:5): [True: 0, False: 0] ------------------ 4921| 0| case MCK_Reg51: return true; ------------------ | Branch (4921:5): [True: 0, False: 0] ------------------ 4922| 0| case MCK_DQuad: return true; ------------------ | Branch (4922:5): [True: 0, False: 0] ------------------ 4923| 0| } 4924| | 4925| 0| case MCK_Reg93: ------------------ | Branch (4925:3): [True: 0, False: 9.25k] ------------------ 4926| 0| switch (B) { 4927| 0| default: return false; ------------------ | Branch (4927:5): [True: 0, False: 0] ------------------ 4928| 0| case MCK_Reg94: return true; ------------------ | Branch (4928:5): [True: 0, False: 0] ------------------ 4929| 0| case MCK_Reg95: return true; ------------------ | Branch (4929:5): [True: 0, False: 0] ------------------ 4930| 0| case MCK_Reg96: return true; ------------------ | Branch (4930:5): [True: 0, False: 0] ------------------ 4931| 0| case MCK_Reg97: return true; ------------------ | Branch (4931:5): [True: 0, False: 0] ------------------ 4932| 0| case MCK_DTripleSpc: return true; ------------------ | Branch (4932:5): [True: 0, False: 0] ------------------ 4933| 0| } 4934| | 4935| 0| case MCK_Reg75: ------------------ | Branch (4935:3): [True: 0, False: 9.25k] ------------------ 4936| 0| switch (B) { 4937| 0| default: return false; ------------------ | Branch (4937:5): [True: 0, False: 0] ------------------ 4938| 0| case MCK_Reg76: return true; ------------------ | Branch (4938:5): [True: 0, False: 0] ------------------ 4939| 0| case MCK_Reg77: return true; ------------------ | Branch (4939:5): [True: 0, False: 0] ------------------ 4940| 0| case MCK_Reg78: return true; ------------------ | Branch (4940:5): [True: 0, False: 0] ------------------ 4941| 0| case MCK_Reg79: return true; ------------------ | Branch (4941:5): [True: 0, False: 0] ------------------ 4942| 0| case MCK_Reg80: return true; ------------------ | Branch (4942:5): [True: 0, False: 0] ------------------ 4943| 0| case MCK_DTriple: return true; ------------------ | Branch (4943:5): [True: 0, False: 0] ------------------ 4944| 0| } 4945| | 4946| 0| case MCK_Reg69: ------------------ | Branch (4946:3): [True: 0, False: 9.25k] ------------------ 4947| 0| return B == MCK_GPRPair; 4948| | 4949| 0| case MCK_Reg63: ------------------ | Branch (4949:3): [True: 0, False: 9.25k] ------------------ 4950| 0| switch (B) { 4951| 0| default: return false; ------------------ | Branch (4951:5): [True: 0, False: 0] ------------------ 4952| 0| case MCK_Reg64: return true; ------------------ | Branch (4952:5): [True: 0, False: 0] ------------------ 4953| 0| case MCK_Reg65: return true; ------------------ | Branch (4953:5): [True: 0, False: 0] ------------------ 4954| 0| case MCK_QQQQPR: return true; ------------------ | Branch (4954:5): [True: 0, False: 0] ------------------ 4955| 0| } 4956| | 4957| 0| case MCK_Reg57: ------------------ | Branch (4957:3): [True: 0, False: 9.25k] ------------------ 4958| 0| switch (B) { 4959| 0| default: return false; ------------------ | Branch (4959:5): [True: 0, False: 0] ------------------ 4960| 0| case MCK_Reg54: return true; ------------------ | Branch (4960:5): [True: 0, False: 0] ------------------ 4961| 0| case MCK_Reg55: return true; ------------------ | Branch (4961:5): [True: 0, False: 0] ------------------ 4962| 0| case MCK_Reg52: return true; ------------------ | Branch (4962:5): [True: 0, False: 0] ------------------ 4963| 0| case MCK_Reg53: return true; ------------------ | Branch (4963:5): [True: 0, False: 0] ------------------ 4964| 0| case MCK_Reg50: return true; ------------------ | Branch (4964:5): [True: 0, False: 0] ------------------ 4965| 0| case MCK_Reg51: return true; ------------------ | Branch (4965:5): [True: 0, False: 0] ------------------ 4966| 0| case MCK_DQuad: return true; ------------------ | Branch (4966:5): [True: 0, False: 0] ------------------ 4967| 0| } 4968| | 4969| 0| case MCK_Reg39: ------------------ | Branch (4969:3): [True: 0, False: 9.25k] ------------------ 4970| 0| switch (B) { 4971| 0| default: return false; ------------------ | Branch (4971:5): [True: 0, False: 0] ------------------ 4972| 0| case MCK_Reg40: return true; ------------------ | Branch (4972:5): [True: 0, False: 0] ------------------ 4973| 0| case MCK_Reg41: return true; ------------------ | Branch (4973:5): [True: 0, False: 0] ------------------ 4974| 0| case MCK_Reg42: return true; ------------------ | Branch (4974:5): [True: 0, False: 0] ------------------ 4975| 0| case MCK_DPairSpc: return true; ------------------ | Branch (4975:5): [True: 0, False: 0] ------------------ 4976| 0| } 4977| | 4978| 630| case MCK_Reg9: ------------------ | Branch (4978:3): [True: 630, False: 8.62k] ------------------ 4979| 630| switch (B) { 4980| 309| default: return false; ------------------ | Branch (4980:5): [True: 309, False: 321] ------------------ 4981| 0| case MCK_Reg7: return true; ------------------ | Branch (4981:5): [True: 0, False: 630] ------------------ 4982| 0| case MCK_hGPR: return true; ------------------ | Branch (4982:5): [True: 0, False: 630] ------------------ 4983| 53| case MCK_rGPR: return true; ------------------ | Branch (4983:5): [True: 53, False: 577] ------------------ 4984| 190| case MCK_GPRnopc: return true; ------------------ | Branch (4984:5): [True: 190, False: 440] ------------------ 4985| 78| case MCK_GPR: return true; ------------------ | Branch (4985:5): [True: 78, False: 552] ------------------ 4986| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (4986:5): [True: 0, False: 630] ------------------ 4987| 630| } 4988| | 4989| 0| case MCK_Reg103: ------------------ | Branch (4989:3): [True: 0, False: 9.25k] ------------------ 4990| 0| switch (B) { 4991| 0| default: return false; ------------------ | Branch (4991:5): [True: 0, False: 0] ------------------ 4992| 0| case MCK_Reg104: return true; ------------------ | Branch (4992:5): [True: 0, False: 0] ------------------ 4993| 0| case MCK_Reg105: return true; ------------------ | Branch (4993:5): [True: 0, False: 0] ------------------ 4994| 0| case MCK_Reg53: return true; ------------------ | Branch (4994:5): [True: 0, False: 0] ------------------ 4995| 0| case MCK_Reg50: return true; ------------------ | Branch (4995:5): [True: 0, False: 0] ------------------ 4996| 0| case MCK_Reg51: return true; ------------------ | Branch (4996:5): [True: 0, False: 0] ------------------ 4997| 0| case MCK_DQuad: return true; ------------------ | Branch (4997:5): [True: 0, False: 0] ------------------ 4998| 0| } 4999| | 5000| 0| case MCK_Reg89: ------------------ | Branch (5000:3): [True: 0, False: 9.25k] ------------------ 5001| 0| switch (B) { 5002| 0| default: return false; ------------------ | Branch (5002:5): [True: 0, False: 0] ------------------ 5003| 0| case MCK_Reg90: return true; ------------------ | Branch (5003:5): [True: 0, False: 0] ------------------ 5004| 0| case MCK_Reg78: return true; ------------------ | Branch (5004:5): [True: 0, False: 0] ------------------ 5005| 0| case MCK_Reg91: return true; ------------------ | Branch (5005:5): [True: 0, False: 0] ------------------ 5006| 0| case MCK_Reg79: return true; ------------------ | Branch (5006:5): [True: 0, False: 0] ------------------ 5007| 0| case MCK_Reg80: return true; ------------------ | Branch (5007:5): [True: 0, False: 0] ------------------ 5008| 0| case MCK_DTriple: return true; ------------------ | Branch (5008:5): [True: 0, False: 0] ------------------ 5009| 0| } 5010| | 5011| 0| case MCK_Reg84: ------------------ | Branch (5011:3): [True: 0, False: 9.25k] ------------------ 5012| 0| switch (B) { 5013| 0| default: return false; ------------------ | Branch (5013:5): [True: 0, False: 0] ------------------ 5014| 0| case MCK_Reg85: return true; ------------------ | Branch (5014:5): [True: 0, False: 0] ------------------ 5015| 0| case MCK_Reg78: return true; ------------------ | Branch (5015:5): [True: 0, False: 0] ------------------ 5016| 0| case MCK_Reg86: return true; ------------------ | Branch (5016:5): [True: 0, False: 0] ------------------ 5017| 0| case MCK_Reg79: return true; ------------------ | Branch (5017:5): [True: 0, False: 0] ------------------ 5018| 0| case MCK_Reg80: return true; ------------------ | Branch (5018:5): [True: 0, False: 0] ------------------ 5019| 0| case MCK_DTriple: return true; ------------------ | Branch (5019:5): [True: 0, False: 0] ------------------ 5020| 0| } 5021| | 5022| 0| case MCK_Reg76: ------------------ | Branch (5022:3): [True: 0, False: 9.25k] ------------------ 5023| 0| switch (B) { 5024| 0| default: return false; ------------------ | Branch (5024:5): [True: 0, False: 0] ------------------ 5025| 0| case MCK_Reg77: return true; ------------------ | Branch (5025:5): [True: 0, False: 0] ------------------ 5026| 0| case MCK_Reg78: return true; ------------------ | Branch (5026:5): [True: 0, False: 0] ------------------ 5027| 0| case MCK_Reg79: return true; ------------------ | Branch (5027:5): [True: 0, False: 0] ------------------ 5028| 0| case MCK_Reg80: return true; ------------------ | Branch (5028:5): [True: 0, False: 0] ------------------ 5029| 0| case MCK_DTriple: return true; ------------------ | Branch (5029:5): [True: 0, False: 0] ------------------ 5030| 0| } 5031| | 5032| 0| case MCK_Reg64: ------------------ | Branch (5032:3): [True: 0, False: 9.25k] ------------------ 5033| 0| switch (B) { 5034| 0| default: return false; ------------------ | Branch (5034:5): [True: 0, False: 0] ------------------ 5035| 0| case MCK_Reg65: return true; ------------------ | Branch (5035:5): [True: 0, False: 0] ------------------ 5036| 0| case MCK_QQQQPR: return true; ------------------ | Branch (5036:5): [True: 0, False: 0] ------------------ 5037| 0| } 5038| | 5039| 0| case MCK_Reg54: ------------------ | Branch (5039:3): [True: 0, False: 9.25k] ------------------ 5040| 0| switch (B) { 5041| 0| default: return false; ------------------ | Branch (5041:5): [True: 0, False: 0] ------------------ 5042| 0| case MCK_Reg55: return true; ------------------ | Branch (5042:5): [True: 0, False: 0] ------------------ 5043| 0| case MCK_Reg52: return true; ------------------ | Branch (5043:5): [True: 0, False: 0] ------------------ 5044| 0| case MCK_Reg53: return true; ------------------ | Branch (5044:5): [True: 0, False: 0] ------------------ 5045| 0| case MCK_Reg50: return true; ------------------ | Branch (5045:5): [True: 0, False: 0] ------------------ 5046| 0| case MCK_Reg51: return true; ------------------ | Branch (5046:5): [True: 0, False: 0] ------------------ 5047| 0| case MCK_DQuad: return true; ------------------ | Branch (5047:5): [True: 0, False: 0] ------------------ 5048| 0| } 5049| | 5050| 0| case MCK_Reg46: ------------------ | Branch (5050:3): [True: 0, False: 9.25k] ------------------ 5051| 0| switch (B) { 5052| 0| default: return false; ------------------ | Branch (5052:5): [True: 0, False: 0] ------------------ 5053| 0| case MCK_Reg47: return true; ------------------ | Branch (5053:5): [True: 0, False: 0] ------------------ 5054| 0| case MCK_Reg52: return true; ------------------ | Branch (5054:5): [True: 0, False: 0] ------------------ 5055| 0| case MCK_Reg53: return true; ------------------ | Branch (5055:5): [True: 0, False: 0] ------------------ 5056| 0| case MCK_Reg50: return true; ------------------ | Branch (5056:5): [True: 0, False: 0] ------------------ 5057| 0| case MCK_QQPR: return true; ------------------ | Branch (5057:5): [True: 0, False: 0] ------------------ 5058| 0| case MCK_Reg51: return true; ------------------ | Branch (5058:5): [True: 0, False: 0] ------------------ 5059| 0| case MCK_DQuad: return true; ------------------ | Branch (5059:5): [True: 0, False: 0] ------------------ 5060| 0| } 5061| | 5062| 0| case MCK_Reg25: ------------------ | Branch (5062:3): [True: 0, False: 9.25k] ------------------ 5063| 0| switch (B) { 5064| 0| default: return false; ------------------ | Branch (5064:5): [True: 0, False: 0] ------------------ 5065| 0| case MCK_Reg26: return true; ------------------ | Branch (5065:5): [True: 0, False: 0] ------------------ 5066| 0| case MCK_Reg23: return true; ------------------ | Branch (5066:5): [True: 0, False: 0] ------------------ 5067| 0| case MCK_Reg24: return true; ------------------ | Branch (5067:5): [True: 0, False: 0] ------------------ 5068| 0| case MCK_DPair: return true; ------------------ | Branch (5068:5): [True: 0, False: 0] ------------------ 5069| 0| } 5070| | 5071| 0| case MCK_Reg7: ------------------ | Branch (5071:3): [True: 0, False: 9.25k] ------------------ 5072| 0| switch (B) { 5073| 0| default: return false; ------------------ | Branch (5073:5): [True: 0, False: 0] ------------------ 5074| 0| case MCK_hGPR: return true; ------------------ | Branch (5074:5): [True: 0, False: 0] ------------------ 5075| 0| case MCK_GPRnopc: return true; ------------------ | Branch (5075:5): [True: 0, False: 0] ------------------ 5076| 0| case MCK_GPR: return true; ------------------ | Branch (5076:5): [True: 0, False: 0] ------------------ 5077| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (5077:5): [True: 0, False: 0] ------------------ 5078| 0| } 5079| | 5080| 0| case MCK_Reg104: ------------------ | Branch (5080:3): [True: 0, False: 9.25k] ------------------ 5081| 0| switch (B) { 5082| 0| default: return false; ------------------ | Branch (5082:5): [True: 0, False: 0] ------------------ 5083| 0| case MCK_Reg105: return true; ------------------ | Branch (5083:5): [True: 0, False: 0] ------------------ 5084| 0| case MCK_Reg51: return true; ------------------ | Branch (5084:5): [True: 0, False: 0] ------------------ 5085| 0| case MCK_DQuad: return true; ------------------ | Branch (5085:5): [True: 0, False: 0] ------------------ 5086| 0| } 5087| | 5088| 0| case MCK_Reg94: ------------------ | Branch (5088:3): [True: 0, False: 9.25k] ------------------ 5089| 0| switch (B) { 5090| 0| default: return false; ------------------ | Branch (5090:5): [True: 0, False: 0] ------------------ 5091| 0| case MCK_Reg95: return true; ------------------ | Branch (5091:5): [True: 0, False: 0] ------------------ 5092| 0| case MCK_Reg96: return true; ------------------ | Branch (5092:5): [True: 0, False: 0] ------------------ 5093| 0| case MCK_Reg97: return true; ------------------ | Branch (5093:5): [True: 0, False: 0] ------------------ 5094| 0| case MCK_DTripleSpc: return true; ------------------ | Branch (5094:5): [True: 0, False: 0] ------------------ 5095| 0| } 5096| | 5097| 0| case MCK_Reg90: ------------------ | Branch (5097:3): [True: 0, False: 9.25k] ------------------ 5098| 0| switch (B) { 5099| 0| default: return false; ------------------ | Branch (5099:5): [True: 0, False: 0] ------------------ 5100| 0| case MCK_Reg91: return true; ------------------ | Branch (5100:5): [True: 0, False: 0] ------------------ 5101| 0| case MCK_Reg80: return true; ------------------ | Branch (5101:5): [True: 0, False: 0] ------------------ 5102| 0| case MCK_DTriple: return true; ------------------ | Branch (5102:5): [True: 0, False: 0] ------------------ 5103| 0| } 5104| | 5105| 0| case MCK_Reg85: ------------------ | Branch (5105:3): [True: 0, False: 9.25k] ------------------ 5106| 0| switch (B) { 5107| 0| default: return false; ------------------ | Branch (5107:5): [True: 0, False: 0] ------------------ 5108| 0| case MCK_Reg86: return true; ------------------ | Branch (5108:5): [True: 0, False: 0] ------------------ 5109| 0| case MCK_Reg79: return true; ------------------ | Branch (5109:5): [True: 0, False: 0] ------------------ 5110| 0| case MCK_Reg80: return true; ------------------ | Branch (5110:5): [True: 0, False: 0] ------------------ 5111| 0| case MCK_DTriple: return true; ------------------ | Branch (5111:5): [True: 0, False: 0] ------------------ 5112| 0| } 5113| | 5114| 0| case MCK_Reg77: ------------------ | Branch (5114:3): [True: 0, False: 9.25k] ------------------ 5115| 0| switch (B) { 5116| 0| default: return false; ------------------ | Branch (5116:5): [True: 0, False: 0] ------------------ 5117| 0| case MCK_Reg78: return true; ------------------ | Branch (5117:5): [True: 0, False: 0] ------------------ 5118| 0| case MCK_Reg79: return true; ------------------ | Branch (5118:5): [True: 0, False: 0] ------------------ 5119| 0| case MCK_Reg80: return true; ------------------ | Branch (5119:5): [True: 0, False: 0] ------------------ 5120| 0| case MCK_DTriple: return true; ------------------ | Branch (5120:5): [True: 0, False: 0] ------------------ 5121| 0| } 5122| | 5123| 0| case MCK_Reg65: ------------------ | Branch (5123:3): [True: 0, False: 9.25k] ------------------ 5124| 0| return B == MCK_QQQQPR; 5125| | 5126| 0| case MCK_Reg55: ------------------ | Branch (5126:3): [True: 0, False: 9.25k] ------------------ 5127| 0| switch (B) { 5128| 0| default: return false; ------------------ | Branch (5128:5): [True: 0, False: 0] ------------------ 5129| 0| case MCK_Reg52: return true; ------------------ | Branch (5129:5): [True: 0, False: 0] ------------------ 5130| 0| case MCK_Reg53: return true; ------------------ | Branch (5130:5): [True: 0, False: 0] ------------------ 5131| 0| case MCK_Reg50: return true; ------------------ | Branch (5131:5): [True: 0, False: 0] ------------------ 5132| 0| case MCK_Reg51: return true; ------------------ | Branch (5132:5): [True: 0, False: 0] ------------------ 5133| 0| case MCK_DQuad: return true; ------------------ | Branch (5133:5): [True: 0, False: 0] ------------------ 5134| 0| } 5135| | 5136| 0| case MCK_Reg47: ------------------ | Branch (5136:3): [True: 0, False: 9.25k] ------------------ 5137| 0| switch (B) { 5138| 0| default: return false; ------------------ | Branch (5138:5): [True: 0, False: 0] ------------------ 5139| 0| case MCK_Reg50: return true; ------------------ | Branch (5139:5): [True: 0, False: 0] ------------------ 5140| 0| case MCK_QQPR: return true; ------------------ | Branch (5140:5): [True: 0, False: 0] ------------------ 5141| 0| case MCK_Reg51: return true; ------------------ | Branch (5141:5): [True: 0, False: 0] ------------------ 5142| 0| case MCK_DQuad: return true; ------------------ | Branch (5142:5): [True: 0, False: 0] ------------------ 5143| 0| } 5144| | 5145| 0| case MCK_Reg40: ------------------ | Branch (5145:3): [True: 0, False: 9.25k] ------------------ 5146| 0| switch (B) { 5147| 0| default: return false; ------------------ | Branch (5147:5): [True: 0, False: 0] ------------------ 5148| 0| case MCK_Reg41: return true; ------------------ | Branch (5148:5): [True: 0, False: 0] ------------------ 5149| 0| case MCK_Reg42: return true; ------------------ | Branch (5149:5): [True: 0, False: 0] ------------------ 5150| 0| case MCK_DPairSpc: return true; ------------------ | Branch (5150:5): [True: 0, False: 0] ------------------ 5151| 0| } 5152| | 5153| 0| case MCK_Reg26: ------------------ | Branch (5153:3): [True: 0, False: 9.25k] ------------------ 5154| 0| switch (B) { 5155| 0| default: return false; ------------------ | Branch (5155:5): [True: 0, False: 0] ------------------ 5156| 0| case MCK_Reg23: return true; ------------------ | Branch (5156:5): [True: 0, False: 0] ------------------ 5157| 0| case MCK_Reg24: return true; ------------------ | Branch (5157:5): [True: 0, False: 0] ------------------ 5158| 0| case MCK_DPair: return true; ------------------ | Branch (5158:5): [True: 0, False: 0] ------------------ 5159| 0| } 5160| | 5161| 0| case MCK_DPR_8: ------------------ | Branch (5161:3): [True: 0, False: 9.25k] ------------------ 5162| 0| switch (B) { 5163| 0| default: return false; ------------------ | Branch (5163:5): [True: 0, False: 0] ------------------ 5164| 0| case MCK_DPR_VFP2: return true; ------------------ | Branch (5164:5): [True: 0, False: 0] ------------------ 5165| 0| case MCK_DPR: return true; ------------------ | Branch (5165:5): [True: 0, False: 0] ------------------ 5166| 0| } 5167| | 5168| 0| case MCK_QPR_VFP2: ------------------ | Branch (5168:3): [True: 0, False: 9.25k] ------------------ 5169| 0| switch (B) { 5170| 0| default: return false; ------------------ | Branch (5170:5): [True: 0, False: 0] ------------------ 5171| 0| case MCK_Reg23: return true; ------------------ | Branch (5171:5): [True: 0, False: 0] ------------------ 5172| 0| case MCK_Reg24: return true; ------------------ | Branch (5172:5): [True: 0, False: 0] ------------------ 5173| 0| case MCK_QPR: return true; ------------------ | Branch (5173:5): [True: 0, False: 0] ------------------ 5174| 0| case MCK_DPair: return true; ------------------ | Branch (5174:5): [True: 0, False: 0] ------------------ 5175| 0| } 5176| | 5177| 0| case MCK_hGPR: ------------------ | Branch (5177:3): [True: 0, False: 9.25k] ------------------ 5178| 0| return B == MCK_GPR; 5179| | 5180| 1.97k| case MCK_tGPR: ------------------ | Branch (5180:3): [True: 1.97k, False: 7.28k] ------------------ 5181| 1.97k| switch (B) { 5182| 345| default: return false; ------------------ | Branch (5182:5): [True: 345, False: 1.62k] ------------------ 5183| 420| case MCK_rGPR: return true; ------------------ | Branch (5183:5): [True: 420, False: 1.55k] ------------------ 5184| 978| case MCK_GPRnopc: return true; ------------------ | Branch (5184:5): [True: 978, False: 994] ------------------ 5185| 229| case MCK_GPR: return true; ------------------ | Branch (5185:5): [True: 229, False: 1.74k] ------------------ 5186| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (5186:5): [True: 0, False: 1.97k] ------------------ 5187| 1.97k| } 5188| | 5189| 0| case MCK_Reg95: ------------------ | Branch (5189:3): [True: 0, False: 9.25k] ------------------ 5190| 0| switch (B) { 5191| 0| default: return false; ------------------ | Branch (5191:5): [True: 0, False: 0] ------------------ 5192| 0| case MCK_Reg96: return true; ------------------ | Branch (5192:5): [True: 0, False: 0] ------------------ 5193| 0| case MCK_Reg97: return true; ------------------ | Branch (5193:5): [True: 0, False: 0] ------------------ 5194| 0| case MCK_DTripleSpc: return true; ------------------ | Branch (5194:5): [True: 0, False: 0] ------------------ 5195| 0| } 5196| | 5197| 0| case MCK_Reg52: ------------------ | Branch (5197:3): [True: 0, False: 9.25k] ------------------ 5198| 0| switch (B) { 5199| 0| default: return false; ------------------ | Branch (5199:5): [True: 0, False: 0] ------------------ 5200| 0| case MCK_Reg53: return true; ------------------ | Branch (5200:5): [True: 0, False: 0] ------------------ 5201| 0| case MCK_Reg50: return true; ------------------ | Branch (5201:5): [True: 0, False: 0] ------------------ 5202| 0| case MCK_Reg51: return true; ------------------ | Branch (5202:5): [True: 0, False: 0] ------------------ 5203| 0| case MCK_DQuad: return true; ------------------ | Branch (5203:5): [True: 0, False: 0] ------------------ 5204| 0| } 5205| | 5206| 0| case MCK_Reg105: ------------------ | Branch (5206:3): [True: 0, False: 9.25k] ------------------ 5207| 0| return B == MCK_DQuad; 5208| | 5209| 0| case MCK_Reg96: ------------------ | Branch (5209:3): [True: 0, False: 9.25k] ------------------ 5210| 0| switch (B) { 5211| 0| default: return false; ------------------ | Branch (5211:5): [True: 0, False: 0] ------------------ 5212| 0| case MCK_Reg97: return true; ------------------ | Branch (5212:5): [True: 0, False: 0] ------------------ 5213| 0| case MCK_DTripleSpc: return true; ------------------ | Branch (5213:5): [True: 0, False: 0] ------------------ 5214| 0| } 5215| | 5216| 0| case MCK_Reg78: ------------------ | Branch (5216:3): [True: 0, False: 9.25k] ------------------ 5217| 0| switch (B) { 5218| 0| default: return false; ------------------ | Branch (5218:5): [True: 0, False: 0] ------------------ 5219| 0| case MCK_Reg79: return true; ------------------ | Branch (5219:5): [True: 0, False: 0] ------------------ 5220| 0| case MCK_Reg80: return true; ------------------ | Branch (5220:5): [True: 0, False: 0] ------------------ 5221| 0| case MCK_DTriple: return true; ------------------ | Branch (5221:5): [True: 0, False: 0] ------------------ 5222| 0| } 5223| | 5224| 0| case MCK_Reg53: ------------------ | Branch (5224:3): [True: 0, False: 9.25k] ------------------ 5225| 0| switch (B) { 5226| 0| default: return false; ------------------ | Branch (5226:5): [True: 0, False: 0] ------------------ 5227| 0| case MCK_Reg50: return true; ------------------ | Branch (5227:5): [True: 0, False: 0] ------------------ 5228| 0| case MCK_Reg51: return true; ------------------ | Branch (5228:5): [True: 0, False: 0] ------------------ 5229| 0| case MCK_DQuad: return true; ------------------ | Branch (5229:5): [True: 0, False: 0] ------------------ 5230| 0| } 5231| | 5232| 0| case MCK_Reg41: ------------------ | Branch (5232:3): [True: 0, False: 9.25k] ------------------ 5233| 0| switch (B) { 5234| 0| default: return false; ------------------ | Branch (5234:5): [True: 0, False: 0] ------------------ 5235| 0| case MCK_Reg42: return true; ------------------ | Branch (5235:5): [True: 0, False: 0] ------------------ 5236| 0| case MCK_DPairSpc: return true; ------------------ | Branch (5236:5): [True: 0, False: 0] ------------------ 5237| 0| } 5238| | 5239| 0| case MCK_rGPR: ------------------ | Branch (5239:3): [True: 0, False: 9.25k] ------------------ 5240| 0| switch (B) { 5241| 0| default: return false; ------------------ | Branch (5241:5): [True: 0, False: 0] ------------------ 5242| 0| case MCK_GPRnopc: return true; ------------------ | Branch (5242:5): [True: 0, False: 0] ------------------ 5243| 0| case MCK_GPR: return true; ------------------ | Branch (5243:5): [True: 0, False: 0] ------------------ 5244| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (5244:5): [True: 0, False: 0] ------------------ 5245| 0| } 5246| | 5247| 0| case MCK_Reg91: ------------------ | Branch (5247:3): [True: 0, False: 9.25k] ------------------ 5248| 0| return B == MCK_DTriple; 5249| | 5250| 0| case MCK_Reg86: ------------------ | Branch (5250:3): [True: 0, False: 9.25k] ------------------ 5251| 0| return B == MCK_DTriple; 5252| | 5253| 0| case MCK_Reg79: ------------------ | Branch (5253:3): [True: 0, False: 9.25k] ------------------ 5254| 0| switch (B) { 5255| 0| default: return false; ------------------ | Branch (5255:5): [True: 0, False: 0] ------------------ 5256| 0| case MCK_Reg80: return true; ------------------ | Branch (5256:5): [True: 0, False: 0] ------------------ 5257| 0| case MCK_DTriple: return true; ------------------ | Branch (5257:5): [True: 0, False: 0] ------------------ 5258| 0| } 5259| | 5260| 0| case MCK_Reg50: ------------------ | Branch (5260:3): [True: 0, False: 9.25k] ------------------ 5261| 0| switch (B) { 5262| 0| default: return false; ------------------ | Branch (5262:5): [True: 0, False: 0] ------------------ 5263| 0| case MCK_Reg51: return true; ------------------ | Branch (5263:5): [True: 0, False: 0] ------------------ 5264| 0| case MCK_DQuad: return true; ------------------ | Branch (5264:5): [True: 0, False: 0] ------------------ 5265| 0| } 5266| | 5267| 0| case MCK_Reg23: ------------------ | Branch (5267:3): [True: 0, False: 9.25k] ------------------ 5268| 0| switch (B) { 5269| 0| default: return false; ------------------ | Branch (5269:5): [True: 0, False: 0] ------------------ 5270| 0| case MCK_Reg24: return true; ------------------ | Branch (5270:5): [True: 0, False: 0] ------------------ 5271| 0| case MCK_DPair: return true; ------------------ | Branch (5271:5): [True: 0, False: 0] ------------------ 5272| 0| } 5273| | 5274| 0| case MCK_GPRnopc: ------------------ | Branch (5274:3): [True: 0, False: 9.25k] ------------------ 5275| 0| switch (B) { 5276| 0| default: return false; ------------------ | Branch (5276:5): [True: 0, False: 0] ------------------ 5277| 0| case MCK_GPR: return true; ------------------ | Branch (5277:5): [True: 0, False: 0] ------------------ 5278| 0| case MCK_GPRwithAPSR: return true; ------------------ | Branch (5278:5): [True: 0, False: 0] ------------------ 5279| 0| } 5280| | 5281| 0| case MCK_QQPR: ------------------ | Branch (5281:3): [True: 0, False: 9.25k] ------------------ 5282| 0| return B == MCK_DQuad; 5283| | 5284| 0| case MCK_Reg97: ------------------ | Branch (5284:3): [True: 0, False: 9.25k] ------------------ 5285| 0| return B == MCK_DTripleSpc; 5286| | 5287| 0| case MCK_Reg80: ------------------ | Branch (5287:3): [True: 0, False: 9.25k] ------------------ 5288| 0| return B == MCK_DTriple; 5289| | 5290| 0| case MCK_Reg51: ------------------ | Branch (5290:3): [True: 0, False: 9.25k] ------------------ 5291| 0| return B == MCK_DQuad; 5292| | 5293| 0| case MCK_Reg42: ------------------ | Branch (5293:3): [True: 0, False: 9.25k] ------------------ 5294| 0| return B == MCK_DPairSpc; 5295| | 5296| 0| case MCK_Reg24: ------------------ | Branch (5296:3): [True: 0, False: 9.25k] ------------------ 5297| 0| return B == MCK_DPair; 5298| | 5299| 0| case MCK_DPR_VFP2: ------------------ | Branch (5299:3): [True: 0, False: 9.25k] ------------------ 5300| 0| return B == MCK_DPR; 5301| | 5302| 0| case MCK_QPR: ------------------ | Branch (5302:3): [True: 0, False: 9.25k] ------------------ 5303| 0| return B == MCK_DPair; 5304| | 5305| 0| case MCK_SPR_8: ------------------ | Branch (5305:3): [True: 0, False: 9.25k] ------------------ 5306| 0| return B == MCK_SPR; 5307| 9.25k| } 5308| 9.25k|} ARMAsmParser.cpp:_ZL16matchTokenStringN7llvm_ks9StringRefE: 4301| 2.68k|static MatchClassKind matchTokenString(StringRef Name) { 4302| 2.68k| switch (Name.size()) { 4303| 0| default: break; ------------------ | Branch (4303:3): [True: 0, False: 2.68k] ------------------ 4304| 0| case 1: // 6 strings to match. ------------------ | Branch (4304:3): [True: 0, False: 2.68k] ------------------ 4305| 0| switch (Name[0]) { 4306| 0| default: break; ------------------ | Branch (4306:5): [True: 0, False: 0] ------------------ 4307| 0| case '!': // 1 string to match. ------------------ | Branch (4307:5): [True: 0, False: 0] ------------------ 4308| 0| return MCK__EXCLAIM_; // "!" 4309| 0| case '[': // 1 string to match. ------------------ | Branch (4309:5): [True: 0, False: 0] ------------------ 4310| 0| return MCK__91_; // "[" 4311| 0| case ']': // 1 string to match. ------------------ | Branch (4311:5): [True: 0, False: 0] ------------------ 4312| 0| return MCK__93_; // "]" 4313| 0| case '^': // 1 string to match. ------------------ | Branch (4313:5): [True: 0, False: 0] ------------------ 4314| 0| return MCK__94_; // "^" 4315| 0| case '{': // 1 string to match. ------------------ | Branch (4315:5): [True: 0, False: 0] ------------------ 4316| 0| return MCK__123_; // "{" 4317| 0| case '}': // 1 string to match. ------------------ | Branch (4317:5): [True: 0, False: 0] ------------------ 4318| 0| return MCK__125_; // "}" 4319| 0| } 4320| 0| break; 4321| 2.68k| case 2: // 5 strings to match. ------------------ | Branch (4321:3): [True: 2.68k, False: 0] ------------------ 4322| 2.68k| switch (Name[0]) { 4323| 0| default: break; ------------------ | Branch (4323:5): [True: 0, False: 2.68k] ------------------ 4324| 0| case '#': // 1 string to match. ------------------ | Branch (4324:5): [True: 0, False: 2.68k] ------------------ 4325| 0| if (Name[1] != '0') ------------------ | Branch (4325:11): [True: 0, False: 0] ------------------ 4326| 0| break; 4327| 0| return MCK__35_0; // "#0" 4328| 2.68k| case '.': // 4 strings to match. ------------------ | Branch (4328:5): [True: 2.68k, False: 0] ------------------ 4329| 2.68k| switch (Name[1]) { 4330| 0| default: break; ------------------ | Branch (4330:7): [True: 0, False: 2.68k] ------------------ 4331| 0| case '8': // 1 string to match. ------------------ | Branch (4331:7): [True: 0, False: 2.68k] ------------------ 4332| 0| return MCK__DOT_8; // ".8" 4333| 0| case 'd': // 1 string to match. ------------------ | Branch (4333:7): [True: 0, False: 2.68k] ------------------ 4334| 0| return MCK__DOT_d; // ".d" 4335| 0| case 'f': // 1 string to match. ------------------ | Branch (4335:7): [True: 0, False: 2.68k] ------------------ 4336| 0| return MCK__DOT_f; // ".f" 4337| 2.68k| case 'w': // 1 string to match. ------------------ | Branch (4337:7): [True: 2.68k, False: 0] ------------------ 4338| 2.68k| return MCK__DOT_w; // ".w" 4339| 2.68k| } 4340| 0| break; 4341| 2.68k| } 4342| 0| break; 4343| 0| case 3: // 7 strings to match. ------------------ | Branch (4343:3): [True: 0, False: 2.68k] ------------------ 4344| 0| if (Name[0] != '.') ------------------ | Branch (4344:9): [True: 0, False: 0] ------------------ 4345| 0| break; 4346| 0| switch (Name[1]) { 4347| 0| default: break; ------------------ | Branch (4347:5): [True: 0, False: 0] ------------------ 4348| 0| case '1': // 1 string to match. ------------------ | Branch (4348:5): [True: 0, False: 0] ------------------ 4349| 0| if (Name[2] != '6') ------------------ | Branch (4349:11): [True: 0, False: 0] ------------------ 4350| 0| break; 4351| 0| return MCK__DOT_16; // ".16" 4352| 0| case '3': // 1 string to match. ------------------ | Branch (4352:5): [True: 0, False: 0] ------------------ 4353| 0| if (Name[2] != '2') ------------------ | Branch (4353:11): [True: 0, False: 0] ------------------ 4354| 0| break; 4355| 0| return MCK__DOT_32; // ".32" 4356| 0| case '6': // 1 string to match. ------------------ | Branch (4356:5): [True: 0, False: 0] ------------------ 4357| 0| if (Name[2] != '4') ------------------ | Branch (4357:11): [True: 0, False: 0] ------------------ 4358| 0| break; 4359| 0| return MCK__DOT_64; // ".64" 4360| 0| case 'i': // 1 string to match. ------------------ | Branch (4360:5): [True: 0, False: 0] ------------------ 4361| 0| if (Name[2] != '8') ------------------ | Branch (4361:11): [True: 0, False: 0] ------------------ 4362| 0| break; 4363| 0| return MCK__DOT_i8; // ".i8" 4364| 0| case 'p': // 1 string to match. ------------------ | Branch (4364:5): [True: 0, False: 0] ------------------ 4365| 0| if (Name[2] != '8') ------------------ | Branch (4365:11): [True: 0, False: 0] ------------------ 4366| 0| break; 4367| 0| return MCK__DOT_p8; // ".p8" 4368| 0| case 's': // 1 string to match. ------------------ | Branch (4368:5): [True: 0, False: 0] ------------------ 4369| 0| if (Name[2] != '8') ------------------ | Branch (4369:11): [True: 0, False: 0] ------------------ 4370| 0| break; 4371| 0| return MCK__DOT_s8; // ".s8" 4372| 0| case 'u': // 1 string to match. ------------------ | Branch (4372:5): [True: 0, False: 0] ------------------ 4373| 0| if (Name[2] != '8') ------------------ | Branch (4373:11): [True: 0, False: 0] ------------------ 4374| 0| break; 4375| 0| return MCK__DOT_u8; // ".u8" 4376| 0| } 4377| 0| break; 4378| 0| case 4: // 14 strings to match. ------------------ | Branch (4378:3): [True: 0, False: 2.68k] ------------------ 4379| 0| if (Name[0] != '.') ------------------ | Branch (4379:9): [True: 0, False: 0] ------------------ 4380| 0| break; 4381| 0| switch (Name[1]) { 4382| 0| default: break; ------------------ | Branch (4382:5): [True: 0, False: 0] ------------------ 4383| 0| case 'f': // 3 strings to match. ------------------ | Branch (4383:5): [True: 0, False: 0] ------------------ 4384| 0| switch (Name[2]) { 4385| 0| default: break; ------------------ | Branch (4385:7): [True: 0, False: 0] ------------------ 4386| 0| case '1': // 1 string to match. ------------------ | Branch (4386:7): [True: 0, False: 0] ------------------ 4387| 0| if (Name[3] != '6') ------------------ | Branch (4387:13): [True: 0, False: 0] ------------------ 4388| 0| break; 4389| 0| return MCK__DOT_f16; // ".f16" 4390| 0| case '3': // 1 string to match. ------------------ | Branch (4390:7): [True: 0, False: 0] ------------------ 4391| 0| if (Name[3] != '2') ------------------ | Branch (4391:13): [True: 0, False: 0] ------------------ 4392| 0| break; 4393| 0| return MCK__DOT_f32; // ".f32" 4394| 0| case '6': // 1 string to match. ------------------ | Branch (4394:7): [True: 0, False: 0] ------------------ 4395| 0| if (Name[3] != '4') ------------------ | Branch (4395:13): [True: 0, False: 0] ------------------ 4396| 0| break; 4397| 0| return MCK__DOT_f64; // ".f64" 4398| 0| } 4399| 0| break; 4400| 0| case 'i': // 3 strings to match. ------------------ | Branch (4400:5): [True: 0, False: 0] ------------------ 4401| 0| switch (Name[2]) { 4402| 0| default: break; ------------------ | Branch (4402:7): [True: 0, False: 0] ------------------ 4403| 0| case '1': // 1 string to match. ------------------ | Branch (4403:7): [True: 0, False: 0] ------------------ 4404| 0| if (Name[3] != '6') ------------------ | Branch (4404:13): [True: 0, False: 0] ------------------ 4405| 0| break; 4406| 0| return MCK__DOT_i16; // ".i16" 4407| 0| case '3': // 1 string to match. ------------------ | Branch (4407:7): [True: 0, False: 0] ------------------ 4408| 0| if (Name[3] != '2') ------------------ | Branch (4408:13): [True: 0, False: 0] ------------------ 4409| 0| break; 4410| 0| return MCK__DOT_i32; // ".i32" 4411| 0| case '6': // 1 string to match. ------------------ | Branch (4411:7): [True: 0, False: 0] ------------------ 4412| 0| if (Name[3] != '4') ------------------ | Branch (4412:13): [True: 0, False: 0] ------------------ 4413| 0| break; 4414| 0| return MCK__DOT_i64; // ".i64" 4415| 0| } 4416| 0| break; 4417| 0| case 'p': // 2 strings to match. ------------------ | Branch (4417:5): [True: 0, False: 0] ------------------ 4418| 0| switch (Name[2]) { 4419| 0| default: break; ------------------ | Branch (4419:7): [True: 0, False: 0] ------------------ 4420| 0| case '1': // 1 string to match. ------------------ | Branch (4420:7): [True: 0, False: 0] ------------------ 4421| 0| if (Name[3] != '6') ------------------ | Branch (4421:13): [True: 0, False: 0] ------------------ 4422| 0| break; 4423| 0| return MCK__DOT_p16; // ".p16" 4424| 0| case '6': // 1 string to match. ------------------ | Branch (4424:7): [True: 0, False: 0] ------------------ 4425| 0| if (Name[3] != '4') ------------------ | Branch (4425:13): [True: 0, False: 0] ------------------ 4426| 0| break; 4427| 0| return MCK__DOT_p64; // ".p64" 4428| 0| } 4429| 0| break; 4430| 0| case 's': // 3 strings to match. ------------------ | Branch (4430:5): [True: 0, False: 0] ------------------ 4431| 0| switch (Name[2]) { 4432| 0| default: break; ------------------ | Branch (4432:7): [True: 0, False: 0] ------------------ 4433| 0| case '1': // 1 string to match. ------------------ | Branch (4433:7): [True: 0, False: 0] ------------------ 4434| 0| if (Name[3] != '6') ------------------ | Branch (4434:13): [True: 0, False: 0] ------------------ 4435| 0| break; 4436| 0| return MCK__DOT_s16; // ".s16" 4437| 0| case '3': // 1 string to match. ------------------ | Branch (4437:7): [True: 0, False: 0] ------------------ 4438| 0| if (Name[3] != '2') ------------------ | Branch (4438:13): [True: 0, False: 0] ------------------ 4439| 0| break; 4440| 0| return MCK__DOT_s32; // ".s32" 4441| 0| case '6': // 1 string to match. ------------------ | Branch (4441:7): [True: 0, False: 0] ------------------ 4442| 0| if (Name[3] != '4') ------------------ | Branch (4442:13): [True: 0, False: 0] ------------------ 4443| 0| break; 4444| 0| return MCK__DOT_s64; // ".s64" 4445| 0| } 4446| 0| break; 4447| 0| case 'u': // 3 strings to match. ------------------ | Branch (4447:5): [True: 0, False: 0] ------------------ 4448| 0| switch (Name[2]) { 4449| 0| default: break; ------------------ | Branch (4449:7): [True: 0, False: 0] ------------------ 4450| 0| case '1': // 1 string to match. ------------------ | Branch (4450:7): [True: 0, False: 0] ------------------ 4451| 0| if (Name[3] != '6') ------------------ | Branch (4451:13): [True: 0, False: 0] ------------------ 4452| 0| break; 4453| 0| return MCK__DOT_u16; // ".u16" 4454| 0| case '3': // 1 string to match. ------------------ | Branch (4454:7): [True: 0, False: 0] ------------------ 4455| 0| if (Name[3] != '2') ------------------ | Branch (4455:13): [True: 0, False: 0] ------------------ 4456| 0| break; 4457| 0| return MCK__DOT_u32; // ".u32" 4458| 0| case '6': // 1 string to match. ------------------ | Branch (4458:7): [True: 0, False: 0] ------------------ 4459| 0| if (Name[3] != '4') ------------------ | Branch (4459:13): [True: 0, False: 0] ------------------ 4460| 0| break; 4461| 0| return MCK__DOT_u64; // ".u64" 4462| 0| } 4463| 0| break; 4464| 0| } 4465| 0| break; 4466| 2.68k| } 4467| 0| return InvalidMatchClass; 4468| 2.68k|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser15convertToMCInstEjRN7llvm_ks6MCInstEjRKNS1_15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS5_14default_deleteIS7_EEEEEE: 3089| 2.42k| const OperandVector &Operands) { 3090| 2.42k| assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); ------------------ | Branch (3090:3): [True: 2.42k, False: 0] | Branch (3090:3): [True: 2.42k, Folded] | Branch (3090:3): [True: 2.42k, False: 0] ------------------ 3091| 2.42k| const uint8_t *Converter = ConversionTable[Kind]; 3092| 2.42k| Inst.setOpcode(Opcode); 3093| 10.2k| for (const uint8_t *p = Converter; *p; p+= 2) { ------------------ | Branch (3093:38): [True: 7.82k, False: 2.42k] ------------------ 3094| 7.82k| switch (*p) { 3095| 0| default: llvm_unreachable("invalid conversion entry!"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ | Branch (3095:5): [True: 0, False: 7.82k] ------------------ 3096| 0| case CVT_Reg: ------------------ | Branch (3096:5): [True: 0, False: 7.82k] ------------------ 3097| 0| static_cast(*Operands[*(p + 1)]).addRegOperands(Inst, 1); 3098| 0| break; 3099| 301| case CVT_Tied: ------------------ | Branch (3099:5): [True: 301, False: 7.52k] ------------------ 3100| 301| Inst.addOperand(Inst.getOperand(*(p + 1))); 3101| 301| break; 3102| 2.44k| case CVT_95_Reg: ------------------ | Branch (3102:5): [True: 2.44k, False: 5.38k] ------------------ 3103| 2.44k| static_cast(*Operands[*(p + 1)]).addRegOperands(Inst, 1); 3104| 2.44k| break; 3105| 743| case CVT_95_addCCOutOperands: ------------------ | Branch (3105:5): [True: 743, False: 7.08k] ------------------ 3106| 743| static_cast(*Operands[*(p + 1)]).addCCOutOperands(Inst, 1); 3107| 743| break; 3108| 2.00k| case CVT_95_addCondCodeOperands: ------------------ | Branch (3108:5): [True: 2.00k, False: 5.82k] ------------------ 3109| 2.00k| static_cast(*Operands[*(p + 1)]).addCondCodeOperands(Inst, 2); 3110| 2.00k| break; 3111| 0| case CVT_95_addRegShiftedRegOperands: ------------------ | Branch (3111:5): [True: 0, False: 7.82k] ------------------ 3112| 0| static_cast(*Operands[*(p + 1)]).addRegShiftedRegOperands(Inst, 3); 3113| 0| break; 3114| 0| case CVT_95_addModImmOperands: ------------------ | Branch (3114:5): [True: 0, False: 7.82k] ------------------ 3115| 0| static_cast(*Operands[*(p + 1)]).addModImmOperands(Inst, 1); 3116| 0| break; 3117| 0| case CVT_95_addRegShiftedImmOperands: ------------------ | Branch (3117:5): [True: 0, False: 7.82k] ------------------ 3118| 0| static_cast(*Operands[*(p + 1)]).addRegShiftedImmOperands(Inst, 2); 3119| 0| break; 3120| 1.06k| case CVT_95_addImmOperands: ------------------ | Branch (3120:5): [True: 1.06k, False: 6.76k] ------------------ 3121| 1.06k| static_cast(*Operands[*(p + 1)]).addImmOperands(Inst, 1); 3122| 1.06k| break; 3123| 106| case CVT_95_addImm0_95_508s4Operands: ------------------ | Branch (3123:5): [True: 106, False: 7.72k] ------------------ 3124| 106| static_cast(*Operands[*(p + 1)]).addImm0_508s4Operands(Inst, 1); 3125| 106| break; 3126| 5| case CVT_regSP: ------------------ | Branch (3126:5): [True: 5, False: 7.82k] ------------------ 3127| 5| Inst.addOperand(MCOperand::createReg(ARM::SP)); 3128| 5| break; 3129| 5| case CVT_95_addImm0_95_508s4NegOperands: ------------------ | Branch (3129:5): [True: 5, False: 7.82k] ------------------ 3130| 5| static_cast(*Operands[*(p + 1)]).addImm0_508s4NegOperands(Inst, 1); 3131| 5| break; 3132| 26| case CVT_95_addImm0_95_4095NegOperands: ------------------ | Branch (3132:5): [True: 26, False: 7.80k] ------------------ 3133| 26| static_cast(*Operands[*(p + 1)]).addImm0_4095NegOperands(Inst, 1); 3134| 26| break; 3135| 0| case CVT_95_addT2SOImmNegOperands: ------------------ | Branch (3135:5): [True: 0, False: 7.82k] ------------------ 3136| 0| static_cast(*Operands[*(p + 1)]).addT2SOImmNegOperands(Inst, 1); 3137| 0| break; 3138| 0| case CVT_95_addModImmNegOperands: ------------------ | Branch (3138:5): [True: 0, False: 7.82k] ------------------ 3139| 0| static_cast(*Operands[*(p + 1)]).addModImmNegOperands(Inst, 1); 3140| 0| break; 3141| 0| case CVT_95_addImm0_95_1020s4Operands: ------------------ | Branch (3141:5): [True: 0, False: 7.82k] ------------------ 3142| 0| static_cast(*Operands[*(p + 1)]).addImm0_1020s4Operands(Inst, 1); 3143| 0| break; 3144| 55| case CVT_95_addUnsignedOffset_95_b8s2Operands: ------------------ | Branch (3144:5): [True: 55, False: 7.77k] ------------------ 3145| 55| static_cast(*Operands[*(p + 1)]).addUnsignedOffset_b8s2Operands(Inst, 1); 3146| 55| break; 3147| 0| case CVT_95_addAdrLabelOperands: ------------------ | Branch (3147:5): [True: 0, False: 7.82k] ------------------ 3148| 0| static_cast(*Operands[*(p + 1)]).addAdrLabelOperands(Inst, 1); 3149| 0| break; 3150| 0| case CVT_95_addT2SOImmNotOperands: ------------------ | Branch (3150:5): [True: 0, False: 7.82k] ------------------ 3151| 0| static_cast(*Operands[*(p + 1)]).addT2SOImmNotOperands(Inst, 1); 3152| 0| break; 3153| 0| case CVT_95_addModImmNotOperands: ------------------ | Branch (3153:5): [True: 0, False: 7.82k] ------------------ 3154| 0| static_cast(*Operands[*(p + 1)]).addModImmNotOperands(Inst, 1); 3155| 0| break; 3156| 6| case CVT_95_addImmThumbSROperands: ------------------ | Branch (3156:5): [True: 6, False: 7.82k] ------------------ 3157| 6| static_cast(*Operands[*(p + 1)]).addImmThumbSROperands(Inst, 1); 3158| 6| break; 3159| 346| case CVT_cvtThumbBranches: ------------------ | Branch (3159:5): [True: 346, False: 7.48k] ------------------ 3160| 346| cvtThumbBranches(Inst, Operands); 3161| 346| break; 3162| 0| case CVT_95_addBitfieldOperands: ------------------ | Branch (3162:5): [True: 0, False: 7.82k] ------------------ 3163| 0| static_cast(*Operands[*(p + 1)]).addBitfieldOperands(Inst, 1); 3164| 0| break; 3165| 8| case CVT_imm_95_0: ------------------ | Branch (3165:5): [True: 8, False: 7.82k] ------------------ 3166| 8| Inst.addOperand(MCOperand::createImm(0)); 3167| 8| break; 3168| 0| case CVT_95_addCoprocNumOperands: ------------------ | Branch (3168:5): [True: 0, False: 7.82k] ------------------ 3169| 0| static_cast(*Operands[*(p + 1)]).addCoprocNumOperands(Inst, 1); 3170| 0| break; 3171| 0| case CVT_95_addCoprocRegOperands: ------------------ | Branch (3171:5): [True: 0, False: 7.82k] ------------------ 3172| 0| static_cast(*Operands[*(p + 1)]).addCoprocRegOperands(Inst, 1); 3173| 0| break; 3174| 0| case CVT_95_addProcIFlagsOperands: ------------------ | Branch (3174:5): [True: 0, False: 7.82k] ------------------ 3175| 0| static_cast(*Operands[*(p + 1)]).addProcIFlagsOperands(Inst, 1); 3176| 0| break; 3177| 0| case CVT_imm_95_15: ------------------ | Branch (3177:5): [True: 0, False: 7.82k] ------------------ 3178| 0| Inst.addOperand(MCOperand::createImm(15)); 3179| 0| break; 3180| 0| case CVT_95_addMemBarrierOptOperands: ------------------ | Branch (3180:5): [True: 0, False: 7.82k] ------------------ 3181| 0| static_cast(*Operands[*(p + 1)]).addMemBarrierOptOperands(Inst, 1); 3182| 0| break; 3183| 0| case CVT_95_addFPImmOperands: ------------------ | Branch (3183:5): [True: 0, False: 7.82k] ------------------ 3184| 0| static_cast(*Operands[*(p + 1)]).addFPImmOperands(Inst, 1); 3185| 0| break; 3186| 0| case CVT_95_addDPRRegListOperands: ------------------ | Branch (3186:5): [True: 0, False: 7.82k] ------------------ 3187| 0| static_cast(*Operands[*(p + 1)]).addDPRRegListOperands(Inst, 1); 3188| 0| break; 3189| 0| case CVT_imm_95_1: ------------------ | Branch (3189:5): [True: 0, False: 7.82k] ------------------ 3190| 0| Inst.addOperand(MCOperand::createImm(1)); 3191| 0| break; 3192| 0| case CVT_95_addInstSyncBarrierOptOperands: ------------------ | Branch (3192:5): [True: 0, False: 7.82k] ------------------ 3193| 0| static_cast(*Operands[*(p + 1)]).addInstSyncBarrierOptOperands(Inst, 1); 3194| 0| break; 3195| 66| case CVT_95_addITCondCodeOperands: ------------------ | Branch (3195:5): [True: 66, False: 7.76k] ------------------ 3196| 66| static_cast(*Operands[*(p + 1)]).addITCondCodeOperands(Inst, 1); 3197| 66| break; 3198| 66| case CVT_95_addITMaskOperands: ------------------ | Branch (3198:5): [True: 66, False: 7.76k] ------------------ 3199| 66| static_cast(*Operands[*(p + 1)]).addITMaskOperands(Inst, 1); 3200| 66| break; 3201| 0| case CVT_95_addMemNoOffsetOperands: ------------------ | Branch (3201:5): [True: 0, False: 7.82k] ------------------ 3202| 0| static_cast(*Operands[*(p + 1)]).addMemNoOffsetOperands(Inst, 1); 3203| 0| break; 3204| 0| case CVT_95_addAddrMode5Operands: ------------------ | Branch (3204:5): [True: 0, False: 7.82k] ------------------ 3205| 0| static_cast(*Operands[*(p + 1)]).addAddrMode5Operands(Inst, 2); 3206| 0| break; 3207| 0| case CVT_95_addCoprocOptionOperands: ------------------ | Branch (3207:5): [True: 0, False: 7.82k] ------------------ 3208| 0| static_cast(*Operands[*(p + 1)]).addCoprocOptionOperands(Inst, 1); 3209| 0| break; 3210| 0| case CVT_95_addPostIdxImm8s4Operands: ------------------ | Branch (3210:5): [True: 0, False: 7.82k] ------------------ 3211| 0| static_cast(*Operands[*(p + 1)]).addPostIdxImm8s4Operands(Inst, 1); 3212| 0| break; 3213| 0| case CVT_95_addRegListOperands: ------------------ | Branch (3213:5): [True: 0, False: 7.82k] ------------------ 3214| 0| static_cast(*Operands[*(p + 1)]).addRegListOperands(Inst, 1); 3215| 0| break; 3216| 516| case CVT_95_addThumbMemPCOperands: ------------------ | Branch (3216:5): [True: 516, False: 7.31k] ------------------ 3217| 516| static_cast(*Operands[*(p + 1)]).addThumbMemPCOperands(Inst, 1); 3218| 516| break; 3219| 0| case CVT_95_addMemThumbRIs4Operands: ------------------ | Branch (3219:5): [True: 0, False: 7.82k] ------------------ 3220| 0| static_cast(*Operands[*(p + 1)]).addMemThumbRIs4Operands(Inst, 2); 3221| 0| break; 3222| 0| case CVT_95_addMemThumbRROperands: ------------------ | Branch (3222:5): [True: 0, False: 7.82k] ------------------ 3223| 0| static_cast(*Operands[*(p + 1)]).addMemThumbRROperands(Inst, 2); 3224| 0| break; 3225| 0| case CVT_95_addMemThumbSPIOperands: ------------------ | Branch (3225:5): [True: 0, False: 7.82k] ------------------ 3226| 0| static_cast(*Operands[*(p + 1)]).addMemThumbSPIOperands(Inst, 2); 3227| 0| break; 3228| 0| case CVT_95_addMemImm12OffsetOperands: ------------------ | Branch (3228:5): [True: 0, False: 7.82k] ------------------ 3229| 0| static_cast(*Operands[*(p + 1)]).addMemImm12OffsetOperands(Inst, 2); 3230| 0| break; 3231| 0| case CVT_95_addMemNegImm8OffsetOperands: ------------------ | Branch (3231:5): [True: 0, False: 7.82k] ------------------ 3232| 0| static_cast(*Operands[*(p + 1)]).addMemNegImm8OffsetOperands(Inst, 2); 3233| 0| break; 3234| 0| case CVT_95_addMemRegOffsetOperands: ------------------ | Branch (3234:5): [True: 0, False: 7.82k] ------------------ 3235| 0| static_cast(*Operands[*(p + 1)]).addMemRegOffsetOperands(Inst, 3); 3236| 0| break; 3237| 0| case CVT_95_addMemUImm12OffsetOperands: ------------------ | Branch (3237:5): [True: 0, False: 7.82k] ------------------ 3238| 0| static_cast(*Operands[*(p + 1)]).addMemUImm12OffsetOperands(Inst, 2); 3239| 0| break; 3240| 0| case CVT_95_addT2MemRegOffsetOperands: ------------------ | Branch (3240:5): [True: 0, False: 7.82k] ------------------ 3241| 0| static_cast(*Operands[*(p + 1)]).addT2MemRegOffsetOperands(Inst, 3); 3242| 0| break; 3243| 0| case CVT_95_addMemPCRelImm12Operands: ------------------ | Branch (3243:5): [True: 0, False: 7.82k] ------------------ 3244| 0| static_cast(*Operands[*(p + 1)]).addMemPCRelImm12Operands(Inst, 1); 3245| 0| break; 3246| 0| case CVT_95_addMemImm8OffsetOperands: ------------------ | Branch (3246:5): [True: 0, False: 7.82k] ------------------ 3247| 0| static_cast(*Operands[*(p + 1)]).addMemImm8OffsetOperands(Inst, 2); 3248| 0| break; 3249| 0| case CVT_95_addAM2OffsetImmOperands: ------------------ | Branch (3249:5): [True: 0, False: 7.82k] ------------------ 3250| 0| static_cast(*Operands[*(p + 1)]).addAM2OffsetImmOperands(Inst, 2); 3251| 0| break; 3252| 0| case CVT_95_addPostIdxRegShiftedOperands: ------------------ | Branch (3252:5): [True: 0, False: 7.82k] ------------------ 3253| 0| static_cast(*Operands[*(p + 1)]).addPostIdxRegShiftedOperands(Inst, 2); 3254| 0| break; 3255| 0| case CVT_95_addMemThumbRIs1Operands: ------------------ | Branch (3255:5): [True: 0, False: 7.82k] ------------------ 3256| 0| static_cast(*Operands[*(p + 1)]).addMemThumbRIs1Operands(Inst, 2); 3257| 0| break; 3258| 0| case CVT_95_addMemPosImm8OffsetOperands: ------------------ | Branch (3258:5): [True: 0, False: 7.82k] ------------------ 3259| 0| static_cast(*Operands[*(p + 1)]).addMemPosImm8OffsetOperands(Inst, 2); 3260| 0| break; 3261| 0| case CVT_95_addMemImm8s4OffsetOperands: ------------------ | Branch (3261:5): [True: 0, False: 7.82k] ------------------ 3262| 0| static_cast(*Operands[*(p + 1)]).addMemImm8s4OffsetOperands(Inst, 2); 3263| 0| break; 3264| 0| case CVT_95_addAddrMode3Operands: ------------------ | Branch (3264:5): [True: 0, False: 7.82k] ------------------ 3265| 0| static_cast(*Operands[*(p + 1)]).addAddrMode3Operands(Inst, 3); 3266| 0| break; 3267| 0| case CVT_95_addAM3OffsetOperands: ------------------ | Branch (3267:5): [True: 0, False: 7.82k] ------------------ 3268| 0| static_cast(*Operands[*(p + 1)]).addAM3OffsetOperands(Inst, 2); 3269| 0| break; 3270| 0| case CVT_95_addMemImm0_95_1020s4OffsetOperands: ------------------ | Branch (3270:5): [True: 0, False: 7.82k] ------------------ 3271| 0| static_cast(*Operands[*(p + 1)]).addMemImm0_1020s4OffsetOperands(Inst, 2); 3272| 0| break; 3273| 0| case CVT_95_addMemThumbRIs2Operands: ------------------ | Branch (3273:5): [True: 0, False: 7.82k] ------------------ 3274| 0| static_cast(*Operands[*(p + 1)]).addMemThumbRIs2Operands(Inst, 2); 3275| 0| break; 3276| 0| case CVT_95_addPostIdxRegOperands: ------------------ | Branch (3276:5): [True: 0, False: 7.82k] ------------------ 3277| 0| static_cast(*Operands[*(p + 1)]).addPostIdxRegOperands(Inst, 2); 3278| 0| break; 3279| 0| case CVT_95_addPostIdxImm8Operands: ------------------ | Branch (3279:5): [True: 0, False: 7.82k] ------------------ 3280| 0| static_cast(*Operands[*(p + 1)]).addPostIdxImm8Operands(Inst, 1); 3281| 0| break; 3282| 0| case CVT_reg0: ------------------ | Branch (3282:5): [True: 0, False: 7.82k] ------------------ 3283| 0| Inst.addOperand(MCOperand::createReg(0)); 3284| 0| break; 3285| 0| case CVT_regCPSR: ------------------ | Branch (3285:5): [True: 0, False: 7.82k] ------------------ 3286| 0| Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 3287| 0| break; 3288| 0| case CVT_imm_95_14: ------------------ | Branch (3288:5): [True: 0, False: 7.82k] ------------------ 3289| 0| Inst.addOperand(MCOperand::createImm(14)); 3290| 0| break; 3291| 0| case CVT_95_addBankedRegOperands: ------------------ | Branch (3291:5): [True: 0, False: 7.82k] ------------------ 3292| 0| static_cast(*Operands[*(p + 1)]).addBankedRegOperands(Inst, 1); 3293| 0| break; 3294| 65| case CVT_95_addMSRMaskOperands: ------------------ | Branch (3294:5): [True: 65, False: 7.76k] ------------------ 3295| 65| static_cast(*Operands[*(p + 1)]).addMSRMaskOperands(Inst, 1); 3296| 65| break; 3297| 0| case CVT_cvtThumbMultiply: ------------------ | Branch (3297:5): [True: 0, False: 7.82k] ------------------ 3298| 0| cvtThumbMultiply(Inst, Operands); 3299| 0| break; 3300| 0| case CVT_regR8: ------------------ | Branch (3300:5): [True: 0, False: 7.82k] ------------------ 3301| 0| Inst.addOperand(MCOperand::createReg(ARM::R8)); 3302| 0| break; 3303| 0| case CVT_regR0: ------------------ | Branch (3303:5): [True: 0, False: 7.82k] ------------------ 3304| 0| Inst.addOperand(MCOperand::createReg(ARM::R0)); 3305| 0| break; 3306| 0| case CVT_95_addPKHASRImmOperands: ------------------ | Branch (3306:5): [True: 0, False: 7.82k] ------------------ 3307| 0| static_cast(*Operands[*(p + 1)]).addPKHASRImmOperands(Inst, 1); 3308| 0| break; 3309| 0| case CVT_95_addImm1_95_32Operands: ------------------ | Branch (3309:5): [True: 0, False: 7.82k] ------------------ 3310| 0| static_cast(*Operands[*(p + 1)]).addImm1_32Operands(Inst, 1); 3311| 0| break; 3312| 0| case CVT_imm_95_4: ------------------ | Branch (3312:5): [True: 0, False: 7.82k] ------------------ 3313| 0| Inst.addOperand(MCOperand::createImm(4)); 3314| 0| break; 3315| 0| case CVT_imm_95_5: ------------------ | Branch (3315:5): [True: 0, False: 7.82k] ------------------ 3316| 0| Inst.addOperand(MCOperand::createImm(5)); 3317| 0| break; 3318| 0| case CVT_95_addShifterImmOperands: ------------------ | Branch (3318:5): [True: 0, False: 7.82k] ------------------ 3319| 0| static_cast(*Operands[*(p + 1)]).addShifterImmOperands(Inst, 1); 3320| 0| break; 3321| 0| case CVT_95_addImm1_95_16Operands: ------------------ | Branch (3321:5): [True: 0, False: 7.82k] ------------------ 3322| 0| static_cast(*Operands[*(p + 1)]).addImm1_16Operands(Inst, 1); 3323| 0| break; 3324| 0| case CVT_95_addRotImmOperands: ------------------ | Branch (3324:5): [True: 0, False: 7.82k] ------------------ 3325| 0| static_cast(*Operands[*(p + 1)]).addRotImmOperands(Inst, 1); 3326| 0| break; 3327| 0| case CVT_95_addMemTBBOperands: ------------------ | Branch (3327:5): [True: 0, False: 7.82k] ------------------ 3328| 0| static_cast(*Operands[*(p + 1)]).addMemTBBOperands(Inst, 2); 3329| 0| break; 3330| 0| case CVT_95_addMemTBHOperands: ------------------ | Branch (3330:5): [True: 0, False: 7.82k] ------------------ 3331| 0| static_cast(*Operands[*(p + 1)]).addMemTBHOperands(Inst, 2); 3332| 0| break; 3333| 0| case CVT_95_addNEONi16splatNotOperands: ------------------ | Branch (3333:5): [True: 0, False: 7.82k] ------------------ 3334| 0| static_cast(*Operands[*(p + 1)]).addNEONi16splatNotOperands(Inst, 1); 3335| 0| break; 3336| 0| case CVT_95_addNEONi32splatNotOperands: ------------------ | Branch (3336:5): [True: 0, False: 7.82k] ------------------ 3337| 0| static_cast(*Operands[*(p + 1)]).addNEONi32splatNotOperands(Inst, 1); 3338| 0| break; 3339| 0| case CVT_95_addNEONi16splatOperands: ------------------ | Branch (3339:5): [True: 0, False: 7.82k] ------------------ 3340| 0| static_cast(*Operands[*(p + 1)]).addNEONi16splatOperands(Inst, 1); 3341| 0| break; 3342| 0| case CVT_95_addNEONi32splatOperands: ------------------ | Branch (3342:5): [True: 0, False: 7.82k] ------------------ 3343| 0| static_cast(*Operands[*(p + 1)]).addNEONi32splatOperands(Inst, 1); 3344| 0| break; 3345| 0| case CVT_95_addFBits16Operands: ------------------ | Branch (3345:5): [True: 0, False: 7.82k] ------------------ 3346| 0| static_cast(*Operands[*(p + 1)]).addFBits16Operands(Inst, 1); 3347| 0| break; 3348| 0| case CVT_95_addFBits32Operands: ------------------ | Branch (3348:5): [True: 0, False: 7.82k] ------------------ 3349| 0| static_cast(*Operands[*(p + 1)]).addFBits32Operands(Inst, 1); 3350| 0| break; 3351| 0| case CVT_95_addVectorIndex16Operands: ------------------ | Branch (3351:5): [True: 0, False: 7.82k] ------------------ 3352| 0| static_cast(*Operands[*(p + 1)]).addVectorIndex16Operands(Inst, 1); 3353| 0| break; 3354| 0| case CVT_95_addVectorIndex32Operands: ------------------ | Branch (3354:5): [True: 0, False: 7.82k] ------------------ 3355| 0| static_cast(*Operands[*(p + 1)]).addVectorIndex32Operands(Inst, 1); 3356| 0| break; 3357| 0| case CVT_95_addVectorIndex8Operands: ------------------ | Branch (3357:5): [True: 0, False: 7.82k] ------------------ 3358| 0| static_cast(*Operands[*(p + 1)]).addVectorIndex8Operands(Inst, 1); 3359| 0| break; 3360| 0| case CVT_95_addVecListOperands: ------------------ | Branch (3360:5): [True: 0, False: 7.82k] ------------------ 3361| 0| static_cast(*Operands[*(p + 1)]).addVecListOperands(Inst, 1); 3362| 0| break; 3363| 0| case CVT_95_addDupAlignedMemory16Operands: ------------------ | Branch (3363:5): [True: 0, False: 7.82k] ------------------ 3364| 0| static_cast(*Operands[*(p + 1)]).addDupAlignedMemory16Operands(Inst, 2); 3365| 0| break; 3366| 0| case CVT_95_addAlignedMemory64or128Operands: ------------------ | Branch (3366:5): [True: 0, False: 7.82k] ------------------ 3367| 0| static_cast(*Operands[*(p + 1)]).addAlignedMemory64or128Operands(Inst, 2); 3368| 0| break; 3369| 0| case CVT_95_addAlignedMemory64or128or256Operands: ------------------ | Branch (3369:5): [True: 0, False: 7.82k] ------------------ 3370| 0| static_cast(*Operands[*(p + 1)]).addAlignedMemory64or128or256Operands(Inst, 2); 3371| 0| break; 3372| 0| case CVT_95_addAlignedMemory64Operands: ------------------ | Branch (3372:5): [True: 0, False: 7.82k] ------------------ 3373| 0| static_cast(*Operands[*(p + 1)]).addAlignedMemory64Operands(Inst, 2); 3374| 0| break; 3375| 0| case CVT_95_addVecListIndexedOperands: ------------------ | Branch (3375:5): [True: 0, False: 7.82k] ------------------ 3376| 0| static_cast(*Operands[*(p + 1)]).addVecListIndexedOperands(Inst, 2); 3377| 0| break; 3378| 0| case CVT_95_addAlignedMemory16Operands: ------------------ | Branch (3378:5): [True: 0, False: 7.82k] ------------------ 3379| 0| static_cast(*Operands[*(p + 1)]).addAlignedMemory16Operands(Inst, 2); 3380| 0| break; 3381| 0| case CVT_95_addDupAlignedMemory32Operands: ------------------ | Branch (3381:5): [True: 0, False: 7.82k] ------------------ 3382| 0| static_cast(*Operands[*(p + 1)]).addDupAlignedMemory32Operands(Inst, 2); 3383| 0| break; 3384| 0| case CVT_95_addAlignedMemory32Operands: ------------------ | Branch (3384:5): [True: 0, False: 7.82k] ------------------ 3385| 0| static_cast(*Operands[*(p + 1)]).addAlignedMemory32Operands(Inst, 2); 3386| 0| break; 3387| 0| case CVT_95_addDupAlignedMemoryNoneOperands: ------------------ | Branch (3387:5): [True: 0, False: 7.82k] ------------------ 3388| 0| static_cast(*Operands[*(p + 1)]).addDupAlignedMemoryNoneOperands(Inst, 2); 3389| 0| break; 3390| 0| case CVT_95_addAlignedMemoryNoneOperands: ------------------ | Branch (3390:5): [True: 0, False: 7.82k] ------------------ 3391| 0| static_cast(*Operands[*(p + 1)]).addAlignedMemoryNoneOperands(Inst, 2); 3392| 0| break; 3393| 0| case CVT_95_addAlignedMemoryOperands: ------------------ | Branch (3393:5): [True: 0, False: 7.82k] ------------------ 3394| 0| static_cast(*Operands[*(p + 1)]).addAlignedMemoryOperands(Inst, 2); 3395| 0| break; 3396| 0| case CVT_95_addDupAlignedMemory64Operands: ------------------ | Branch (3396:5): [True: 0, False: 7.82k] ------------------ 3397| 0| static_cast(*Operands[*(p + 1)]).addDupAlignedMemory64Operands(Inst, 2); 3398| 0| break; 3399| 0| case CVT_95_addDupAlignedMemory64or128Operands: ------------------ | Branch (3399:5): [True: 0, False: 7.82k] ------------------ 3400| 0| static_cast(*Operands[*(p + 1)]).addDupAlignedMemory64or128Operands(Inst, 2); 3401| 0| break; 3402| 0| case CVT_95_addSPRRegListOperands: ------------------ | Branch (3402:5): [True: 0, False: 7.82k] ------------------ 3403| 0| static_cast(*Operands[*(p + 1)]).addSPRRegListOperands(Inst, 1); 3404| 0| break; 3405| 0| case CVT_95_addAddrMode5FP16Operands: ------------------ | Branch (3405:5): [True: 0, False: 7.82k] ------------------ 3406| 0| static_cast(*Operands[*(p + 1)]).addAddrMode5FP16Operands(Inst, 2); 3407| 0| break; 3408| 0| case CVT_95_addNEONi32vmovOperands: ------------------ | Branch (3408:5): [True: 0, False: 7.82k] ------------------ 3409| 0| static_cast(*Operands[*(p + 1)]).addNEONi32vmovOperands(Inst, 1); 3410| 0| break; 3411| 0| case CVT_95_addNEONvmovByteReplicateOperands: ------------------ | Branch (3411:5): [True: 0, False: 7.82k] ------------------ 3412| 0| static_cast(*Operands[*(p + 1)]).addNEONvmovByteReplicateOperands(Inst, 1); 3413| 0| break; 3414| 0| case CVT_95_addNEONi32vmovNegOperands: ------------------ | Branch (3414:5): [True: 0, False: 7.82k] ------------------ 3415| 0| static_cast(*Operands[*(p + 1)]).addNEONi32vmovNegOperands(Inst, 1); 3416| 0| break; 3417| 0| case CVT_95_addNEONi64splatOperands: ------------------ | Branch (3417:5): [True: 0, False: 7.82k] ------------------ 3418| 0| static_cast(*Operands[*(p + 1)]).addNEONi64splatOperands(Inst, 1); 3419| 0| break; 3420| 0| case CVT_95_addNEONi8splatOperands: ------------------ | Branch (3420:5): [True: 0, False: 7.82k] ------------------ 3421| 0| static_cast(*Operands[*(p + 1)]).addNEONi8splatOperands(Inst, 1); 3422| 0| break; 3423| 0| case CVT_95_addNEONinvByteReplicateOperands: ------------------ | Branch (3423:5): [True: 0, False: 7.82k] ------------------ 3424| 0| static_cast(*Operands[*(p + 1)]).addNEONinvByteReplicateOperands(Inst, 1); 3425| 0| break; 3426| 0| case CVT_imm_95_2: ------------------ | Branch (3426:5): [True: 0, False: 7.82k] ------------------ 3427| 0| Inst.addOperand(MCOperand::createImm(2)); 3428| 0| break; 3429| 0| case CVT_imm_95_3: ------------------ | Branch (3429:5): [True: 0, False: 7.82k] ------------------ 3430| 0| Inst.addOperand(MCOperand::createImm(3)); 3431| 0| break; 3432| 7.82k| } 3433| 7.82k| } 3434| 2.42k|} ARMMCTargetDesc.cpp:_ZN7llvm_ksL18InitARMMCInstrInfoEPNS_11MCInstrInfoE: 7053| 430|static inline void InitARMMCInstrInfo(MCInstrInfo *II) { 7054| 430| II->InitMCInstrInfo(ARMInsts, NULL, NULL, 3007); 7055| 430|} ARMMCCodeEmitter.cpp:_ZNK12_GLOBAL__N_116ARMMCCodeEmitter21getBinaryCodeForInstrERKN7llvm_ks6MCInstERNS1_15SmallVectorImplINS1_7MCFixupEEERKNS1_15MCSubtargetInfoE: 11| 2.24k| const MCSubtargetInfo &STI) const { 12| 2.24k| static const uint64_t InstBits[] = { 13| 2.24k| UINT64_C(0), 14| 2.24k| UINT64_C(0), 15| 2.24k| UINT64_C(0), 16| 2.24k| UINT64_C(0), 17| 2.24k| UINT64_C(0), 18| 2.24k| UINT64_C(0), 19| 2.24k| UINT64_C(0), 20| 2.24k| UINT64_C(0), 21| 2.24k| UINT64_C(0), 22| 2.24k| UINT64_C(0), 23| 2.24k| UINT64_C(0), 24| 2.24k| UINT64_C(0), 25| 2.24k| UINT64_C(0), 26| 2.24k| UINT64_C(0), 27| 2.24k| UINT64_C(0), 28| 2.24k| UINT64_C(0), 29| 2.24k| UINT64_C(0), 30| 2.24k| UINT64_C(0), 31| 2.24k| UINT64_C(0), 32| 2.24k| UINT64_C(0), 33| 2.24k| UINT64_C(0), 34| 2.24k| UINT64_C(0), 35| 2.24k| UINT64_C(0), 36| 2.24k| UINT64_C(0), 37| 2.24k| UINT64_C(0), 38| 2.24k| UINT64_C(44040192), // ADCri 39| 2.24k| UINT64_C(10485760), // ADCrr 40| 2.24k| UINT64_C(10485760), // ADCrsi 41| 2.24k| UINT64_C(10485776), // ADCrsr 42| 2.24k| UINT64_C(0), 43| 2.24k| UINT64_C(0), 44| 2.24k| UINT64_C(0), 45| 2.24k| UINT64_C(0), 46| 2.24k| UINT64_C(41943040), // ADDri 47| 2.24k| UINT64_C(8388608), // ADDrr 48| 2.24k| UINT64_C(8388608), // ADDrsi 49| 2.24k| UINT64_C(8388624), // ADDrsr 50| 2.24k| UINT64_C(0), 51| 2.24k| UINT64_C(0), 52| 2.24k| UINT64_C(34537472), // ADR 53| 2.24k| UINT64_C(4088398656), // AESD 54| 2.24k| UINT64_C(4088398592), // AESE 55| 2.24k| UINT64_C(4088398784), // AESIMC 56| 2.24k| UINT64_C(4088398720), // AESMC 57| 2.24k| UINT64_C(33554432), // ANDri 58| 2.24k| UINT64_C(0), // ANDrr 59| 2.24k| UINT64_C(0), // ANDrsi 60| 2.24k| UINT64_C(16), // ANDrsr 61| 2.24k| UINT64_C(0), 62| 2.24k| UINT64_C(0), 63| 2.24k| UINT64_C(0), 64| 2.24k| UINT64_C(0), 65| 2.24k| UINT64_C(0), 66| 2.24k| UINT64_C(130023455), // BFC 67| 2.24k| UINT64_C(130023440), // BFI 68| 2.24k| UINT64_C(62914560), // BICri 69| 2.24k| UINT64_C(29360128), // BICrr 70| 2.24k| UINT64_C(29360128), // BICrsi 71| 2.24k| UINT64_C(29360144), // BICrsr 72| 2.24k| UINT64_C(3776970864), // BKPT 73| 2.24k| UINT64_C(3942645760), // BL 74| 2.24k| UINT64_C(3778019120), // BLX 75| 2.24k| UINT64_C(19922736), // BLX_pred 76| 2.24k| UINT64_C(4194304000), // BLXi 77| 2.24k| UINT64_C(184549376), // BL_pred 78| 2.24k| UINT64_C(0), 79| 2.24k| UINT64_C(0), 80| 2.24k| UINT64_C(0), 81| 2.24k| UINT64_C(0), 82| 2.24k| UINT64_C(0), 83| 2.24k| UINT64_C(3778019088), // BX 84| 2.24k| UINT64_C(19922720), // BXJ 85| 2.24k| UINT64_C(0), 86| 2.24k| UINT64_C(19922718), // BX_RET 87| 2.24k| UINT64_C(19922704), // BX_pred 88| 2.24k| UINT64_C(167772160), // Bcc 89| 2.24k| UINT64_C(234881024), // CDP 90| 2.24k| UINT64_C(4261412864), // CDP2 91| 2.24k| UINT64_C(4118802463), // CLREX 92| 2.24k| UINT64_C(24055568), // CLZ 93| 2.24k| UINT64_C(57671680), // CMNri 94| 2.24k| UINT64_C(24117248), // CMNzrr 95| 2.24k| UINT64_C(24117248), // CMNzrsi 96| 2.24k| UINT64_C(24117264), // CMNzrsr 97| 2.24k| UINT64_C(55574528), // CMPri 98| 2.24k| UINT64_C(22020096), // CMPrr 99| 2.24k| UINT64_C(22020096), // CMPrsi 100| 2.24k| UINT64_C(22020112), // CMPrsr 101| 2.24k| UINT64_C(0), 102| 2.24k| UINT64_C(0), 103| 2.24k| UINT64_C(4043440128), // CPS1p 104| 2.24k| UINT64_C(4043309056), // CPS2p 105| 2.24k| UINT64_C(4043440128), // CPS3p 106| 2.24k| UINT64_C(3774873664), // CRC32B 107| 2.24k| UINT64_C(3774874176), // CRC32CB 108| 2.24k| UINT64_C(3776971328), // CRC32CH 109| 2.24k| UINT64_C(3779068480), // CRC32CW 110| 2.24k| UINT64_C(3776970816), // CRC32H 111| 2.24k| UINT64_C(3779067968), // CRC32W 112| 2.24k| UINT64_C(52490480), // DBG 113| 2.24k| UINT64_C(4118802512), // DMB 114| 2.24k| UINT64_C(4118802496), // DSB 115| 2.24k| UINT64_C(35651584), // EORri 116| 2.24k| UINT64_C(2097152), // EORrr 117| 2.24k| UINT64_C(2097152), // EORrsi 118| 2.24k| UINT64_C(2097168), // EORrsr 119| 2.24k| UINT64_C(23068782), // ERET 120| 2.24k| UINT64_C(246418176), // FCONSTD 121| 2.24k| UINT64_C(246417664), // FCONSTH 122| 2.24k| UINT64_C(246417920), // FCONSTS 123| 2.24k| UINT64_C(221252353), // FLDMXDB_UPD 124| 2.24k| UINT64_C(210766593), // FLDMXIA 125| 2.24k| UINT64_C(212863745), // FLDMXIA_UPD 126| 2.24k| UINT64_C(250739216), // FMSTAT 127| 2.24k| UINT64_C(220203777), // FSTMXDB_UPD 128| 2.24k| UINT64_C(209718017), // FSTMXIA 129| 2.24k| UINT64_C(211815169), // FSTMXIA_UPD 130| 2.24k| UINT64_C(52490240), // HINT 131| 2.24k| UINT64_C(3774873712), // HLT 132| 2.24k| UINT64_C(3779068016), // HVC 133| 2.24k| UINT64_C(4118802528), // ISB 134| 2.24k| UINT64_C(0), 135| 2.24k| UINT64_C(0), 136| 2.24k| UINT64_C(0), 137| 2.24k| UINT64_C(0), 138| 2.24k| UINT64_C(0), 139| 2.24k| UINT64_C(0), 140| 2.24k| UINT64_C(0), 141| 2.24k| UINT64_C(0), 142| 2.24k| UINT64_C(0), 143| 2.24k| UINT64_C(0), 144| 2.24k| UINT64_C(26217631), // LDA 145| 2.24k| UINT64_C(30411935), // LDAB 146| 2.24k| UINT64_C(26218143), // LDAEX 147| 2.24k| UINT64_C(30412447), // LDAEXB 148| 2.24k| UINT64_C(28315295), // LDAEXD 149| 2.24k| UINT64_C(32509599), // LDAEXH 150| 2.24k| UINT64_C(32509087), // LDAH 151| 2.24k| UINT64_C(4249878528), // LDC2L_OFFSET 152| 2.24k| UINT64_C(4241489920), // LDC2L_OPTION 153| 2.24k| UINT64_C(4235198464), // LDC2L_POST 154| 2.24k| UINT64_C(4251975680), // LDC2L_PRE 155| 2.24k| UINT64_C(4245684224), // LDC2_OFFSET 156| 2.24k| UINT64_C(4237295616), // LDC2_OPTION 157| 2.24k| UINT64_C(4231004160), // LDC2_POST 158| 2.24k| UINT64_C(4247781376), // LDC2_PRE 159| 2.24k| UINT64_C(223346688), // LDCL_OFFSET 160| 2.24k| UINT64_C(214958080), // LDCL_OPTION 161| 2.24k| UINT64_C(208666624), // LDCL_POST 162| 2.24k| UINT64_C(225443840), // LDCL_PRE 163| 2.24k| UINT64_C(219152384), // LDC_OFFSET 164| 2.24k| UINT64_C(210763776), // LDC_OPTION 165| 2.24k| UINT64_C(204472320), // LDC_POST 166| 2.24k| UINT64_C(221249536), // LDC_PRE 167| 2.24k| UINT64_C(135266304), // LDMDA 168| 2.24k| UINT64_C(137363456), // LDMDA_UPD 169| 2.24k| UINT64_C(152043520), // LDMDB 170| 2.24k| UINT64_C(154140672), // LDMDB_UPD 171| 2.24k| UINT64_C(143654912), // LDMIA 172| 2.24k| UINT64_C(0), 173| 2.24k| UINT64_C(145752064), // LDMIA_UPD 174| 2.24k| UINT64_C(160432128), // LDMIB 175| 2.24k| UINT64_C(162529280), // LDMIB_UPD 176| 2.24k| UINT64_C(0), 177| 2.24k| UINT64_C(74448896), // LDRBT_POST_IMM 178| 2.24k| UINT64_C(108003328), // LDRBT_POST_REG 179| 2.24k| UINT64_C(72351744), // LDRB_POST_IMM 180| 2.24k| UINT64_C(105906176), // LDRB_POST_REG 181| 2.24k| UINT64_C(91226112), // LDRB_PRE_IMM 182| 2.24k| UINT64_C(124780544), // LDRB_PRE_REG 183| 2.24k| UINT64_C(89128960), // LDRBi12 184| 2.24k| UINT64_C(122683392), // LDRBrs 185| 2.24k| UINT64_C(16777424), // LDRD 186| 2.24k| UINT64_C(208), // LDRD_POST 187| 2.24k| UINT64_C(18874576), // LDRD_PRE 188| 2.24k| UINT64_C(26218399), // LDREX 189| 2.24k| UINT64_C(30412703), // LDREXB 190| 2.24k| UINT64_C(28315551), // LDREXD 191| 2.24k| UINT64_C(32509855), // LDREXH 192| 2.24k| UINT64_C(17825968), // LDRH 193| 2.24k| UINT64_C(7340208), // LDRHTi 194| 2.24k| UINT64_C(3145904), // LDRHTr 195| 2.24k| UINT64_C(1048752), // LDRH_POST 196| 2.24k| UINT64_C(19923120), // LDRH_PRE 197| 2.24k| UINT64_C(0), 198| 2.24k| UINT64_C(0), 199| 2.24k| UINT64_C(0), 200| 2.24k| UINT64_C(17826000), // LDRSB 201| 2.24k| UINT64_C(7340240), // LDRSBTi 202| 2.24k| UINT64_C(3145936), // LDRSBTr 203| 2.24k| UINT64_C(1048784), // LDRSB_POST 204| 2.24k| UINT64_C(19923152), // LDRSB_PRE 205| 2.24k| UINT64_C(17826032), // LDRSH 206| 2.24k| UINT64_C(7340272), // LDRSHTi 207| 2.24k| UINT64_C(3145968), // LDRSHTr 208| 2.24k| UINT64_C(1048816), // LDRSH_POST 209| 2.24k| UINT64_C(19923184), // LDRSH_PRE 210| 2.24k| UINT64_C(0), 211| 2.24k| UINT64_C(70254592), // LDRT_POST_IMM 212| 2.24k| UINT64_C(103809024), // LDRT_POST_REG 213| 2.24k| UINT64_C(68157440), // LDR_POST_IMM 214| 2.24k| UINT64_C(101711872), // LDR_POST_REG 215| 2.24k| UINT64_C(87031808), // LDR_PRE_IMM 216| 2.24k| UINT64_C(120586240), // LDR_PRE_REG 217| 2.24k| UINT64_C(85917696), // LDRcp 218| 2.24k| UINT64_C(84934656), // LDRi12 219| 2.24k| UINT64_C(118489088), // LDRrs 220| 2.24k| UINT64_C(0), 221| 2.24k| UINT64_C(0), 222| 2.24k| UINT64_C(0), 223| 2.24k| UINT64_C(0), 224| 2.24k| UINT64_C(0), 225| 2.24k| UINT64_C(0), 226| 2.24k| UINT64_C(234881040), // MCR 227| 2.24k| UINT64_C(4261412880), // MCR2 228| 2.24k| UINT64_C(205520896), // MCRR 229| 2.24k| UINT64_C(4232052736), // MCRR2 230| 2.24k| UINT64_C(0), 231| 2.24k| UINT64_C(2097296), // MLA 232| 2.24k| UINT64_C(0), 233| 2.24k| UINT64_C(6291600), // MLS 234| 2.24k| UINT64_C(0), 235| 2.24k| UINT64_C(0), 236| 2.24k| UINT64_C(0), 237| 2.24k| UINT64_C(0), 238| 2.24k| UINT64_C(0), 239| 2.24k| UINT64_C(0), 240| 2.24k| UINT64_C(27324430), // MOVPCLR 241| 2.24k| UINT64_C(0), 242| 2.24k| UINT64_C(54525952), // MOVTi16 243| 2.24k| UINT64_C(0), 244| 2.24k| UINT64_C(0), 245| 2.24k| UINT64_C(0), 246| 2.24k| UINT64_C(60817408), // MOVi 247| 2.24k| UINT64_C(50331648), // MOVi16 248| 2.24k| UINT64_C(0), 249| 2.24k| UINT64_C(0), 250| 2.24k| UINT64_C(27262976), // MOVr 251| 2.24k| UINT64_C(27262976), // MOVr_TC 252| 2.24k| UINT64_C(27262976), // MOVsi 253| 2.24k| UINT64_C(27262992), // MOVsr 254| 2.24k| UINT64_C(0), 255| 2.24k| UINT64_C(0), 256| 2.24k| UINT64_C(235929616), // MRC 257| 2.24k| UINT64_C(4262461456), // MRC2 258| 2.24k| UINT64_C(206569472), // MRRC 259| 2.24k| UINT64_C(4233101312), // MRRC2 260| 2.24k| UINT64_C(17760256), // MRS 261| 2.24k| UINT64_C(16777728), // MRSbanked 262| 2.24k| UINT64_C(21954560), // MRSsys 263| 2.24k| UINT64_C(18935808), // MSR 264| 2.24k| UINT64_C(18936320), // MSRbanked 265| 2.24k| UINT64_C(52490240), // MSRi 266| 2.24k| UINT64_C(144), // MUL 267| 2.24k| UINT64_C(0), 268| 2.24k| UINT64_C(0), 269| 2.24k| UINT64_C(65011712), // MVNi 270| 2.24k| UINT64_C(31457280), // MVNr 271| 2.24k| UINT64_C(31457280), // MVNsi 272| 2.24k| UINT64_C(31457296), // MVNsr 273| 2.24k| UINT64_C(58720256), // ORRri 274| 2.24k| UINT64_C(25165824), // ORRrr 275| 2.24k| UINT64_C(25165824), // ORRrsi 276| 2.24k| UINT64_C(25165840), // ORRrsr 277| 2.24k| UINT64_C(0), 278| 2.24k| UINT64_C(0), 279| 2.24k| UINT64_C(0), 280| 2.24k| UINT64_C(0), 281| 2.24k| UINT64_C(0), 282| 2.24k| UINT64_C(0), 283| 2.24k| UINT64_C(0), 284| 2.24k| UINT64_C(0), 285| 2.24k| UINT64_C(0), 286| 2.24k| UINT64_C(109051920), // PKHBT 287| 2.24k| UINT64_C(109051984), // PKHTB 288| 2.24k| UINT64_C(4111527936), // PLDWi12 289| 2.24k| UINT64_C(4145082368), // PLDWrs 290| 2.24k| UINT64_C(4115722240), // PLDi12 291| 2.24k| UINT64_C(4149276672), // PLDrs 292| 2.24k| UINT64_C(4098945024), // PLIi12 293| 2.24k| UINT64_C(4132499456), // PLIrs 294| 2.24k| UINT64_C(16777296), // QADD 295| 2.24k| UINT64_C(102764304), // QADD16 296| 2.24k| UINT64_C(102764432), // QADD8 297| 2.24k| UINT64_C(102764336), // QASX 298| 2.24k| UINT64_C(20971600), // QDADD 299| 2.24k| UINT64_C(23068752), // QDSUB 300| 2.24k| UINT64_C(102764368), // QSAX 301| 2.24k| UINT64_C(18874448), // QSUB 302| 2.24k| UINT64_C(102764400), // QSUB16 303| 2.24k| UINT64_C(102764528), // QSUB8 304| 2.24k| UINT64_C(117378864), // RBIT 305| 2.24k| UINT64_C(113184560), // REV 306| 2.24k| UINT64_C(113184688), // REV16 307| 2.24k| UINT64_C(117378992), // REVSH 308| 2.24k| UINT64_C(4161800704), // RFEDA 309| 2.24k| UINT64_C(4163897856), // RFEDA_UPD 310| 2.24k| UINT64_C(4178577920), // RFEDB 311| 2.24k| UINT64_C(4180675072), // RFEDB_UPD 312| 2.24k| UINT64_C(4170189312), // RFEIA 313| 2.24k| UINT64_C(4172286464), // RFEIA_UPD 314| 2.24k| UINT64_C(4186966528), // RFEIB 315| 2.24k| UINT64_C(4189063680), // RFEIB_UPD 316| 2.24k| UINT64_C(0), 317| 2.24k| UINT64_C(0), 318| 2.24k| UINT64_C(0), 319| 2.24k| UINT64_C(0), 320| 2.24k| UINT64_C(0), 321| 2.24k| UINT64_C(0), 322| 2.24k| UINT64_C(0), 323| 2.24k| UINT64_C(39845888), // RSBri 324| 2.24k| UINT64_C(6291456), // RSBrr 325| 2.24k| UINT64_C(6291456), // RSBrsi 326| 2.24k| UINT64_C(6291472), // RSBrsr 327| 2.24k| UINT64_C(48234496), // RSCri 328| 2.24k| UINT64_C(14680064), // RSCrr 329| 2.24k| UINT64_C(14680064), // RSCrsi 330| 2.24k| UINT64_C(14680080), // RSCrsr 331| 2.24k| UINT64_C(101715728), // SADD16 332| 2.24k| UINT64_C(101715856), // SADD8 333| 2.24k| UINT64_C(101715760), // SASX 334| 2.24k| UINT64_C(46137344), // SBCri 335| 2.24k| UINT64_C(12582912), // SBCrr 336| 2.24k| UINT64_C(12582912), // SBCrsi 337| 2.24k| UINT64_C(12582928), // SBCrsr 338| 2.24k| UINT64_C(127926352), // SBFX 339| 2.24k| UINT64_C(118550544), // SDIV 340| 2.24k| UINT64_C(109055920), // SEL 341| 2.24k| UINT64_C(4043374592), // SETEND 342| 2.24k| UINT64_C(4044357632), // SETPAN 343| 2.24k| UINT64_C(4060089408), // SHA1C 344| 2.24k| UINT64_C(4088988352), // SHA1H 345| 2.24k| UINT64_C(4062186560), // SHA1M 346| 2.24k| UINT64_C(4061137984), // SHA1P 347| 2.24k| UINT64_C(4063235136), // SHA1SU0 348| 2.24k| UINT64_C(4089054080), // SHA1SU1 349| 2.24k| UINT64_C(4076866624), // SHA256H 350| 2.24k| UINT64_C(4077915200), // SHA256H2 351| 2.24k| UINT64_C(4089054144), // SHA256SU0 352| 2.24k| UINT64_C(4078963776), // SHA256SU1 353| 2.24k| UINT64_C(103812880), // SHADD16 354| 2.24k| UINT64_C(103813008), // SHADD8 355| 2.24k| UINT64_C(103812912), // SHASX 356| 2.24k| UINT64_C(103812944), // SHSAX 357| 2.24k| UINT64_C(103812976), // SHSUB16 358| 2.24k| UINT64_C(103813104), // SHSUB8 359| 2.24k| UINT64_C(23068784), // SMC 360| 2.24k| UINT64_C(16777344), // SMLABB 361| 2.24k| UINT64_C(16777408), // SMLABT 362| 2.24k| UINT64_C(117440528), // SMLAD 363| 2.24k| UINT64_C(117440560), // SMLADX 364| 2.24k| UINT64_C(14680208), // SMLAL 365| 2.24k| UINT64_C(20971648), // SMLALBB 366| 2.24k| UINT64_C(20971712), // SMLALBT 367| 2.24k| UINT64_C(121634832), // SMLALD 368| 2.24k| UINT64_C(121634864), // SMLALDX 369| 2.24k| UINT64_C(20971680), // SMLALTB 370| 2.24k| UINT64_C(20971744), // SMLALTT 371| 2.24k| UINT64_C(0), 372| 2.24k| UINT64_C(16777376), // SMLATB 373| 2.24k| UINT64_C(16777440), // SMLATT 374| 2.24k| UINT64_C(18874496), // SMLAWB 375| 2.24k| UINT64_C(18874560), // SMLAWT 376| 2.24k| UINT64_C(117440592), // SMLSD 377| 2.24k| UINT64_C(117440624), // SMLSDX 378| 2.24k| UINT64_C(121634896), // SMLSLD 379| 2.24k| UINT64_C(121634928), // SMLSLDX 380| 2.24k| UINT64_C(122683408), // SMMLA 381| 2.24k| UINT64_C(122683440), // SMMLAR 382| 2.24k| UINT64_C(122683600), // SMMLS 383| 2.24k| UINT64_C(122683632), // SMMLSR 384| 2.24k| UINT64_C(122744848), // SMMUL 385| 2.24k| UINT64_C(122744880), // SMMULR 386| 2.24k| UINT64_C(117501968), // SMUAD 387| 2.24k| UINT64_C(117502000), // SMUADX 388| 2.24k| UINT64_C(23068800), // SMULBB 389| 2.24k| UINT64_C(23068864), // SMULBT 390| 2.24k| UINT64_C(12583056), // SMULL 391| 2.24k| UINT64_C(0), 392| 2.24k| UINT64_C(23068832), // SMULTB 393| 2.24k| UINT64_C(23068896), // SMULTT 394| 2.24k| UINT64_C(18874528), // SMULWB 395| 2.24k| UINT64_C(18874592), // SMULWT 396| 2.24k| UINT64_C(117502032), // SMUSD 397| 2.24k| UINT64_C(117502064), // SMUSDX 398| 2.24k| UINT64_C(0), 399| 2.24k| UINT64_C(4165797120), // SRSDA 400| 2.24k| UINT64_C(4167894272), // SRSDA_UPD 401| 2.24k| UINT64_C(4182574336), // SRSDB 402| 2.24k| UINT64_C(4184671488), // SRSDB_UPD 403| 2.24k| UINT64_C(4174185728), // SRSIA 404| 2.24k| UINT64_C(4176282880), // SRSIA_UPD 405| 2.24k| UINT64_C(4190962944), // SRSIB 406| 2.24k| UINT64_C(4193060096), // SRSIB_UPD 407| 2.24k| UINT64_C(111149072), // SSAT 408| 2.24k| UINT64_C(111152944), // SSAT16 409| 2.24k| UINT64_C(101715792), // SSAX 410| 2.24k| UINT64_C(101715824), // SSUB16 411| 2.24k| UINT64_C(101715952), // SSUB8 412| 2.24k| UINT64_C(4248829952), // STC2L_OFFSET 413| 2.24k| UINT64_C(4240441344), // STC2L_OPTION 414| 2.24k| UINT64_C(4234149888), // STC2L_POST 415| 2.24k| UINT64_C(4250927104), // STC2L_PRE 416| 2.24k| UINT64_C(4244635648), // STC2_OFFSET 417| 2.24k| UINT64_C(4236247040), // STC2_OPTION 418| 2.24k| UINT64_C(4229955584), // STC2_POST 419| 2.24k| UINT64_C(4246732800), // STC2_PRE 420| 2.24k| UINT64_C(222298112), // STCL_OFFSET 421| 2.24k| UINT64_C(213909504), // STCL_OPTION 422| 2.24k| UINT64_C(207618048), // STCL_POST 423| 2.24k| UINT64_C(224395264), // STCL_PRE 424| 2.24k| UINT64_C(218103808), // STC_OFFSET 425| 2.24k| UINT64_C(209715200), // STC_OPTION 426| 2.24k| UINT64_C(203423744), // STC_POST 427| 2.24k| UINT64_C(220200960), // STC_PRE 428| 2.24k| UINT64_C(25230480), // STL 429| 2.24k| UINT64_C(29424784), // STLB 430| 2.24k| UINT64_C(25169552), // STLEX 431| 2.24k| UINT64_C(29363856), // STLEXB 432| 2.24k| UINT64_C(27266704), // STLEXD 433| 2.24k| UINT64_C(31461008), // STLEXH 434| 2.24k| UINT64_C(31521936), // STLH 435| 2.24k| UINT64_C(134217728), // STMDA 436| 2.24k| UINT64_C(136314880), // STMDA_UPD 437| 2.24k| UINT64_C(150994944), // STMDB 438| 2.24k| UINT64_C(153092096), // STMDB_UPD 439| 2.24k| UINT64_C(142606336), // STMIA 440| 2.24k| UINT64_C(144703488), // STMIA_UPD 441| 2.24k| UINT64_C(159383552), // STMIB 442| 2.24k| UINT64_C(161480704), // STMIB_UPD 443| 2.24k| UINT64_C(0), 444| 2.24k| UINT64_C(73400320), // STRBT_POST_IMM 445| 2.24k| UINT64_C(106954752), // STRBT_POST_REG 446| 2.24k| UINT64_C(71303168), // STRB_POST_IMM 447| 2.24k| UINT64_C(104857600), // STRB_POST_REG 448| 2.24k| UINT64_C(90177536), // STRB_PRE_IMM 449| 2.24k| UINT64_C(123731968), // STRB_PRE_REG 450| 2.24k| UINT64_C(88080384), // STRBi12 451| 2.24k| UINT64_C(0), 452| 2.24k| UINT64_C(0), 453| 2.24k| UINT64_C(121634816), // STRBrs 454| 2.24k| UINT64_C(16777456), // STRD 455| 2.24k| UINT64_C(240), // STRD_POST 456| 2.24k| UINT64_C(18874608), // STRD_PRE 457| 2.24k| UINT64_C(25169808), // STREX 458| 2.24k| UINT64_C(29364112), // STREXB 459| 2.24k| UINT64_C(27266960), // STREXD 460| 2.24k| UINT64_C(31461264), // STREXH 461| 2.24k| UINT64_C(16777392), // STRH 462| 2.24k| UINT64_C(6291632), // STRHTi 463| 2.24k| UINT64_C(2097328), // STRHTr 464| 2.24k| UINT64_C(176), // STRH_POST 465| 2.24k| UINT64_C(18874544), // STRH_PRE 466| 2.24k| UINT64_C(0), 467| 2.24k| UINT64_C(0), 468| 2.24k| UINT64_C(69206016), // STRT_POST_IMM 469| 2.24k| UINT64_C(102760448), // STRT_POST_REG 470| 2.24k| UINT64_C(67108864), // STR_POST_IMM 471| 2.24k| UINT64_C(100663296), // STR_POST_REG 472| 2.24k| UINT64_C(85983232), // STR_PRE_IMM 473| 2.24k| UINT64_C(119537664), // STR_PRE_REG 474| 2.24k| UINT64_C(83886080), // STRi12 475| 2.24k| UINT64_C(0), 476| 2.24k| UINT64_C(0), 477| 2.24k| UINT64_C(117440512), // STRrs 478| 2.24k| UINT64_C(0), 479| 2.24k| UINT64_C(0), 480| 2.24k| UINT64_C(0), 481| 2.24k| UINT64_C(0), 482| 2.24k| UINT64_C(0), 483| 2.24k| UINT64_C(37748736), // SUBri 484| 2.24k| UINT64_C(4194304), // SUBrr 485| 2.24k| UINT64_C(4194304), // SUBrsi 486| 2.24k| UINT64_C(4194320), // SUBrsr 487| 2.24k| UINT64_C(251658240), // SVC 488| 2.24k| UINT64_C(16777360), // SWP 489| 2.24k| UINT64_C(20971664), // SWPB 490| 2.24k| UINT64_C(111149168), // SXTAB 491| 2.24k| UINT64_C(109052016), // SXTAB16 492| 2.24k| UINT64_C(112197744), // SXTAH 493| 2.24k| UINT64_C(112132208), // SXTB 494| 2.24k| UINT64_C(110035056), // SXTB16 495| 2.24k| UINT64_C(113180784), // SXTH 496| 2.24k| UINT64_C(0), 497| 2.24k| UINT64_C(0), 498| 2.24k| UINT64_C(0), 499| 2.24k| UINT64_C(0), 500| 2.24k| UINT64_C(53477376), // TEQri 501| 2.24k| UINT64_C(19922944), // TEQrr 502| 2.24k| UINT64_C(19922944), // TEQrsi 503| 2.24k| UINT64_C(19922960), // TEQrsr 504| 2.24k| UINT64_C(0), 505| 2.24k| UINT64_C(3892305662), // TRAP 506| 2.24k| UINT64_C(3892240112), // TRAPNaCl 507| 2.24k| UINT64_C(51380224), // TSTri 508| 2.24k| UINT64_C(17825792), // TSTrr 509| 2.24k| UINT64_C(17825792), // TSTrsi 510| 2.24k| UINT64_C(17825808), // TSTrsr 511| 2.24k| UINT64_C(105910032), // UADD16 512| 2.24k| UINT64_C(105910160), // UADD8 513| 2.24k| UINT64_C(105910064), // UASX 514| 2.24k| UINT64_C(132120656), // UBFX 515| 2.24k| UINT64_C(3891265776), // UDF 516| 2.24k| UINT64_C(120647696), // UDIV 517| 2.24k| UINT64_C(108007184), // UHADD16 518| 2.24k| UINT64_C(108007312), // UHADD8 519| 2.24k| UINT64_C(108007216), // UHASX 520| 2.24k| UINT64_C(108007248), // UHSAX 521| 2.24k| UINT64_C(108007280), // UHSUB16 522| 2.24k| UINT64_C(108007408), // UHSUB8 523| 2.24k| UINT64_C(4194448), // UMAAL 524| 2.24k| UINT64_C(10485904), // UMLAL 525| 2.24k| UINT64_C(0), 526| 2.24k| UINT64_C(8388752), // UMULL 527| 2.24k| UINT64_C(0), 528| 2.24k| UINT64_C(106958608), // UQADD16 529| 2.24k| UINT64_C(106958736), // UQADD8 530| 2.24k| UINT64_C(106958640), // UQASX 531| 2.24k| UINT64_C(106958672), // UQSAX 532| 2.24k| UINT64_C(106958704), // UQSUB16 533| 2.24k| UINT64_C(106958832), // UQSUB8 534| 2.24k| UINT64_C(125890576), // USAD8 535| 2.24k| UINT64_C(125829136), // USADA8 536| 2.24k| UINT64_C(115343376), // USAT 537| 2.24k| UINT64_C(115347248), // USAT16 538| 2.24k| UINT64_C(105910096), // USAX 539| 2.24k| UINT64_C(105910128), // USUB16 540| 2.24k| UINT64_C(105910256), // USUB8 541| 2.24k| UINT64_C(115343472), // UXTAB 542| 2.24k| UINT64_C(113246320), // UXTAB16 543| 2.24k| UINT64_C(116392048), // UXTAH 544| 2.24k| UINT64_C(116326512), // UXTB 545| 2.24k| UINT64_C(114229360), // UXTB16 546| 2.24k| UINT64_C(117375088), // UXTH 547| 2.24k| UINT64_C(4070573312), // VABALsv2i64 548| 2.24k| UINT64_C(4069524736), // VABALsv4i32 549| 2.24k| UINT64_C(4068476160), // VABALsv8i16 550| 2.24k| UINT64_C(4087350528), // VABALuv2i64 551| 2.24k| UINT64_C(4086301952), // VABALuv4i32 552| 2.24k| UINT64_C(4085253376), // VABALuv8i16 553| 2.24k| UINT64_C(4060088144), // VABAsv16i8 554| 2.24k| UINT64_C(4062185232), // VABAsv2i32 555| 2.24k| UINT64_C(4061136656), // VABAsv4i16 556| 2.24k| UINT64_C(4062185296), // VABAsv4i32 557| 2.24k| UINT64_C(4061136720), // VABAsv8i16 558| 2.24k| UINT64_C(4060088080), // VABAsv8i8 559| 2.24k| UINT64_C(4076865360), // VABAuv16i8 560| 2.24k| UINT64_C(4078962448), // VABAuv2i32 561| 2.24k| UINT64_C(4077913872), // VABAuv4i16 562| 2.24k| UINT64_C(4078962512), // VABAuv4i32 563| 2.24k| UINT64_C(4077913936), // VABAuv8i16 564| 2.24k| UINT64_C(4076865296), // VABAuv8i8 565| 2.24k| UINT64_C(4070573824), // VABDLsv2i64 566| 2.24k| UINT64_C(4069525248), // VABDLsv4i32 567| 2.24k| UINT64_C(4068476672), // VABDLsv8i16 568| 2.24k| UINT64_C(4087351040), // VABDLuv2i64 569| 2.24k| UINT64_C(4086302464), // VABDLuv4i32 570| 2.24k| UINT64_C(4085253888), // VABDLuv8i16 571| 2.24k| UINT64_C(4078963968), // VABDfd 572| 2.24k| UINT64_C(4078964032), // VABDfq 573| 2.24k| UINT64_C(4080012544), // VABDhd 574| 2.24k| UINT64_C(4080012608), // VABDhq 575| 2.24k| UINT64_C(4060088128), // VABDsv16i8 576| 2.24k| UINT64_C(4062185216), // VABDsv2i32 577| 2.24k| UINT64_C(4061136640), // VABDsv4i16 578| 2.24k| UINT64_C(4062185280), // VABDsv4i32 579| 2.24k| UINT64_C(4061136704), // VABDsv8i16 580| 2.24k| UINT64_C(4060088064), // VABDsv8i8 581| 2.24k| UINT64_C(4076865344), // VABDuv16i8 582| 2.24k| UINT64_C(4078962432), // VABDuv2i32 583| 2.24k| UINT64_C(4077913856), // VABDuv4i16 584| 2.24k| UINT64_C(4078962496), // VABDuv4i32 585| 2.24k| UINT64_C(4077913920), // VABDuv8i16 586| 2.24k| UINT64_C(4076865280), // VABDuv8i8 587| 2.24k| UINT64_C(246418368), // VABSD 588| 2.24k| UINT64_C(246417856), // VABSH 589| 2.24k| UINT64_C(246418112), // VABSS 590| 2.24k| UINT64_C(4088989440), // VABSfd 591| 2.24k| UINT64_C(4088989504), // VABSfq 592| 2.24k| UINT64_C(4088727296), // VABShd 593| 2.24k| UINT64_C(4088727360), // VABShq 594| 2.24k| UINT64_C(4088464192), // VABSv16i8 595| 2.24k| UINT64_C(4088988416), // VABSv2i32 596| 2.24k| UINT64_C(4088726272), // VABSv4i16 597| 2.24k| UINT64_C(4088988480), // VABSv4i32 598| 2.24k| UINT64_C(4088726336), // VABSv8i16 599| 2.24k| UINT64_C(4088464128), // VABSv8i8 600| 2.24k| UINT64_C(4076867088), // VACGEfd 601| 2.24k| UINT64_C(4076867152), // VACGEfq 602| 2.24k| UINT64_C(4077915664), // VACGEhd 603| 2.24k| UINT64_C(4077915728), // VACGEhq 604| 2.24k| UINT64_C(4078964240), // VACGTfd 605| 2.24k| UINT64_C(4078964304), // VACGTfq 606| 2.24k| UINT64_C(4080012816), // VACGThd 607| 2.24k| UINT64_C(4080012880), // VACGThq 608| 2.24k| UINT64_C(238029568), // VADDD 609| 2.24k| UINT64_C(238029056), // VADDH 610| 2.24k| UINT64_C(4070573056), // VADDHNv2i32 611| 2.24k| UINT64_C(4069524480), // VADDHNv4i16 612| 2.24k| UINT64_C(4068475904), // VADDHNv8i8 613| 2.24k| UINT64_C(4070572032), // VADDLsv2i64 614| 2.24k| UINT64_C(4069523456), // VADDLsv4i32 615| 2.24k| UINT64_C(4068474880), // VADDLsv8i16 616| 2.24k| UINT64_C(4087349248), // VADDLuv2i64 617| 2.24k| UINT64_C(4086300672), // VADDLuv4i32 618| 2.24k| UINT64_C(4085252096), // VADDLuv8i16 619| 2.24k| UINT64_C(238029312), // VADDS 620| 2.24k| UINT64_C(4070572288), // VADDWsv2i64 621| 2.24k| UINT64_C(4069523712), // VADDWsv4i32 622| 2.24k| UINT64_C(4068475136), // VADDWsv8i16 623| 2.24k| UINT64_C(4087349504), // VADDWuv2i64 624| 2.24k| UINT64_C(4086300928), // VADDWuv4i32 625| 2.24k| UINT64_C(4085252352), // VADDWuv8i16 626| 2.24k| UINT64_C(4060089600), // VADDfd 627| 2.24k| UINT64_C(4060089664), // VADDfq 628| 2.24k| UINT64_C(4061138176), // VADDhd 629| 2.24k| UINT64_C(4061138240), // VADDhq 630| 2.24k| UINT64_C(4060088384), // VADDv16i8 631| 2.24k| UINT64_C(4063234048), // VADDv1i64 632| 2.24k| UINT64_C(4062185472), // VADDv2i32 633| 2.24k| UINT64_C(4063234112), // VADDv2i64 634| 2.24k| UINT64_C(4061136896), // VADDv4i16 635| 2.24k| UINT64_C(4062185536), // VADDv4i32 636| 2.24k| UINT64_C(4061136960), // VADDv8i16 637| 2.24k| UINT64_C(4060088320), // VADDv8i8 638| 2.24k| UINT64_C(4060086544), // VANDd 639| 2.24k| UINT64_C(4060086608), // VANDq 640| 2.24k| UINT64_C(4061135120), // VBICd 641| 2.24k| UINT64_C(4068475184), // VBICiv2i32 642| 2.24k| UINT64_C(4068477232), // VBICiv4i16 643| 2.24k| UINT64_C(4068475248), // VBICiv4i32 644| 2.24k| UINT64_C(4068477296), // VBICiv8i16 645| 2.24k| UINT64_C(4061135184), // VBICq 646| 2.24k| UINT64_C(4080009488), // VBIFd 647| 2.24k| UINT64_C(4080009552), // VBIFq 648| 2.24k| UINT64_C(4078960912), // VBITd 649| 2.24k| UINT64_C(4078960976), // VBITq 650| 2.24k| UINT64_C(4077912336), // VBSLd 651| 2.24k| UINT64_C(4077912400), // VBSLq 652| 2.24k| UINT64_C(4060089856), // VCEQfd 653| 2.24k| UINT64_C(4060089920), // VCEQfq 654| 2.24k| UINT64_C(4061138432), // VCEQhd 655| 2.24k| UINT64_C(4061138496), // VCEQhq 656| 2.24k| UINT64_C(4076865616), // VCEQv16i8 657| 2.24k| UINT64_C(4078962704), // VCEQv2i32 658| 2.24k| UINT64_C(4077914128), // VCEQv4i16 659| 2.24k| UINT64_C(4078962768), // VCEQv4i32 660| 2.24k| UINT64_C(4077914192), // VCEQv8i16 661| 2.24k| UINT64_C(4076865552), // VCEQv8i8 662| 2.24k| UINT64_C(4088463680), // VCEQzv16i8 663| 2.24k| UINT64_C(4088988928), // VCEQzv2f32 664| 2.24k| UINT64_C(4088987904), // VCEQzv2i32 665| 2.24k| UINT64_C(4088726784), // VCEQzv4f16 666| 2.24k| UINT64_C(4088988992), // VCEQzv4f32 667| 2.24k| UINT64_C(4088725760), // VCEQzv4i16 668| 2.24k| UINT64_C(4088987968), // VCEQzv4i32 669| 2.24k| UINT64_C(4088726848), // VCEQzv8f16 670| 2.24k| UINT64_C(4088725824), // VCEQzv8i16 671| 2.24k| UINT64_C(4088463616), // VCEQzv8i8 672| 2.24k| UINT64_C(4076867072), // VCGEfd 673| 2.24k| UINT64_C(4076867136), // VCGEfq 674| 2.24k| UINT64_C(4077915648), // VCGEhd 675| 2.24k| UINT64_C(4077915712), // VCGEhq 676| 2.24k| UINT64_C(4060087120), // VCGEsv16i8 677| 2.24k| UINT64_C(4062184208), // VCGEsv2i32 678| 2.24k| UINT64_C(4061135632), // VCGEsv4i16 679| 2.24k| UINT64_C(4062184272), // VCGEsv4i32 680| 2.24k| UINT64_C(4061135696), // VCGEsv8i16 681| 2.24k| UINT64_C(4060087056), // VCGEsv8i8 682| 2.24k| UINT64_C(4076864336), // VCGEuv16i8 683| 2.24k| UINT64_C(4078961424), // VCGEuv2i32 684| 2.24k| UINT64_C(4077912848), // VCGEuv4i16 685| 2.24k| UINT64_C(4078961488), // VCGEuv4i32 686| 2.24k| UINT64_C(4077912912), // VCGEuv8i16 687| 2.24k| UINT64_C(4076864272), // VCGEuv8i8 688| 2.24k| UINT64_C(4088463552), // VCGEzv16i8 689| 2.24k| UINT64_C(4088988800), // VCGEzv2f32 690| 2.24k| UINT64_C(4088987776), // VCGEzv2i32 691| 2.24k| UINT64_C(4088726656), // VCGEzv4f16 692| 2.24k| UINT64_C(4088988864), // VCGEzv4f32 693| 2.24k| UINT64_C(4088725632), // VCGEzv4i16 694| 2.24k| UINT64_C(4088987840), // VCGEzv4i32 695| 2.24k| UINT64_C(4088726720), // VCGEzv8f16 696| 2.24k| UINT64_C(4088725696), // VCGEzv8i16 697| 2.24k| UINT64_C(4088463488), // VCGEzv8i8 698| 2.24k| UINT64_C(4078964224), // VCGTfd 699| 2.24k| UINT64_C(4078964288), // VCGTfq 700| 2.24k| UINT64_C(4080012800), // VCGThd 701| 2.24k| UINT64_C(4080012864), // VCGThq 702| 2.24k| UINT64_C(4060087104), // VCGTsv16i8 703| 2.24k| UINT64_C(4062184192), // VCGTsv2i32 704| 2.24k| UINT64_C(4061135616), // VCGTsv4i16 705| 2.24k| UINT64_C(4062184256), // VCGTsv4i32 706| 2.24k| UINT64_C(4061135680), // VCGTsv8i16 707| 2.24k| UINT64_C(4060087040), // VCGTsv8i8 708| 2.24k| UINT64_C(4076864320), // VCGTuv16i8 709| 2.24k| UINT64_C(4078961408), // VCGTuv2i32 710| 2.24k| UINT64_C(4077912832), // VCGTuv4i16 711| 2.24k| UINT64_C(4078961472), // VCGTuv4i32 712| 2.24k| UINT64_C(4077912896), // VCGTuv8i16 713| 2.24k| UINT64_C(4076864256), // VCGTuv8i8 714| 2.24k| UINT64_C(4088463424), // VCGTzv16i8 715| 2.24k| UINT64_C(4088988672), // VCGTzv2f32 716| 2.24k| UINT64_C(4088987648), // VCGTzv2i32 717| 2.24k| UINT64_C(4088726528), // VCGTzv4f16 718| 2.24k| UINT64_C(4088988736), // VCGTzv4f32 719| 2.24k| UINT64_C(4088725504), // VCGTzv4i16 720| 2.24k| UINT64_C(4088987712), // VCGTzv4i32 721| 2.24k| UINT64_C(4088726592), // VCGTzv8f16 722| 2.24k| UINT64_C(4088725568), // VCGTzv8i16 723| 2.24k| UINT64_C(4088463360), // VCGTzv8i8 724| 2.24k| UINT64_C(4088463808), // VCLEzv16i8 725| 2.24k| UINT64_C(4088989056), // VCLEzv2f32 726| 2.24k| UINT64_C(4088988032), // VCLEzv2i32 727| 2.24k| UINT64_C(4088726912), // VCLEzv4f16 728| 2.24k| UINT64_C(4088989120), // VCLEzv4f32 729| 2.24k| UINT64_C(4088725888), // VCLEzv4i16 730| 2.24k| UINT64_C(4088988096), // VCLEzv4i32 731| 2.24k| UINT64_C(4088726976), // VCLEzv8f16 732| 2.24k| UINT64_C(4088725952), // VCLEzv8i16 733| 2.24k| UINT64_C(4088463744), // VCLEzv8i8 734| 2.24k| UINT64_C(4088398912), // VCLSv16i8 735| 2.24k| UINT64_C(4088923136), // VCLSv2i32 736| 2.24k| UINT64_C(4088660992), // VCLSv4i16 737| 2.24k| UINT64_C(4088923200), // VCLSv4i32 738| 2.24k| UINT64_C(4088661056), // VCLSv8i16 739| 2.24k| UINT64_C(4088398848), // VCLSv8i8 740| 2.24k| UINT64_C(4088463936), // VCLTzv16i8 741| 2.24k| UINT64_C(4088989184), // VCLTzv2f32 742| 2.24k| UINT64_C(4088988160), // VCLTzv2i32 743| 2.24k| UINT64_C(4088727040), // VCLTzv4f16 744| 2.24k| UINT64_C(4088989248), // VCLTzv4f32 745| 2.24k| UINT64_C(4088726016), // VCLTzv4i16 746| 2.24k| UINT64_C(4088988224), // VCLTzv4i32 747| 2.24k| UINT64_C(4088727104), // VCLTzv8f16 748| 2.24k| UINT64_C(4088726080), // VCLTzv8i16 749| 2.24k| UINT64_C(4088463872), // VCLTzv8i8 750| 2.24k| UINT64_C(4088399040), // VCLZv16i8 751| 2.24k| UINT64_C(4088923264), // VCLZv2i32 752| 2.24k| UINT64_C(4088661120), // VCLZv4i16 753| 2.24k| UINT64_C(4088923328), // VCLZv4i32 754| 2.24k| UINT64_C(4088661184), // VCLZv8i16 755| 2.24k| UINT64_C(4088398976), // VCLZv8i8 756| 2.24k| UINT64_C(246680384), // VCMPD 757| 2.24k| UINT64_C(246680512), // VCMPED 758| 2.24k| UINT64_C(246680000), // VCMPEH 759| 2.24k| UINT64_C(246680256), // VCMPES 760| 2.24k| UINT64_C(246746048), // VCMPEZD 761| 2.24k| UINT64_C(246745536), // VCMPEZH 762| 2.24k| UINT64_C(246745792), // VCMPEZS 763| 2.24k| UINT64_C(246679872), // VCMPH 764| 2.24k| UINT64_C(246680128), // VCMPS 765| 2.24k| UINT64_C(246745920), // VCMPZD 766| 2.24k| UINT64_C(246745408), // VCMPZH 767| 2.24k| UINT64_C(246745664), // VCMPZS 768| 2.24k| UINT64_C(4088399104), // VCNTd 769| 2.24k| UINT64_C(4088399168), // VCNTq 770| 2.24k| UINT64_C(4089118720), // VCVTANSDf 771| 2.24k| UINT64_C(4088856576), // VCVTANSDh 772| 2.24k| UINT64_C(4089118784), // VCVTANSQf 773| 2.24k| UINT64_C(4088856640), // VCVTANSQh 774| 2.24k| UINT64_C(4089118848), // VCVTANUDf 775| 2.24k| UINT64_C(4088856704), // VCVTANUDh 776| 2.24k| UINT64_C(4089118912), // VCVTANUQf 777| 2.24k| UINT64_C(4088856768), // VCVTANUQh 778| 2.24k| UINT64_C(4273736640), // VCVTASD 779| 2.24k| UINT64_C(4273736128), // VCVTASH 780| 2.24k| UINT64_C(4273736384), // VCVTASS 781| 2.24k| UINT64_C(4273736512), // VCVTAUD 782| 2.24k| UINT64_C(4273736000), // VCVTAUH 783| 2.24k| UINT64_C(4273736256), // VCVTAUS 784| 2.24k| UINT64_C(246614848), // VCVTBDH 785| 2.24k| UINT64_C(246549312), // VCVTBHD 786| 2.24k| UINT64_C(246549056), // VCVTBHS 787| 2.24k| UINT64_C(246614592), // VCVTBSH 788| 2.24k| UINT64_C(246876864), // VCVTDS 789| 2.24k| UINT64_C(4089119488), // VCVTMNSDf 790| 2.24k| UINT64_C(4088857344), // VCVTMNSDh 791| 2.24k| UINT64_C(4089119552), // VCVTMNSQf 792| 2.24k| UINT64_C(4088857408), // VCVTMNSQh 793| 2.24k| UINT64_C(4089119616), // VCVTMNUDf 794| 2.24k| UINT64_C(4088857472), // VCVTMNUDh 795| 2.24k| UINT64_C(4089119680), // VCVTMNUQf 796| 2.24k| UINT64_C(4088857536), // VCVTMNUQh 797| 2.24k| UINT64_C(4273933248), // VCVTMSD 798| 2.24k| UINT64_C(4273932736), // VCVTMSH 799| 2.24k| UINT64_C(4273932992), // VCVTMSS 800| 2.24k| UINT64_C(4273933120), // VCVTMUD 801| 2.24k| UINT64_C(4273932608), // VCVTMUH 802| 2.24k| UINT64_C(4273932864), // VCVTMUS 803| 2.24k| UINT64_C(4089118976), // VCVTNNSDf 804| 2.24k| UINT64_C(4088856832), // VCVTNNSDh 805| 2.24k| UINT64_C(4089119040), // VCVTNNSQf 806| 2.24k| UINT64_C(4088856896), // VCVTNNSQh 807| 2.24k| UINT64_C(4089119104), // VCVTNNUDf 808| 2.24k| UINT64_C(4088856960), // VCVTNNUDh 809| 2.24k| UINT64_C(4089119168), // VCVTNNUQf 810| 2.24k| UINT64_C(4088857024), // VCVTNNUQh 811| 2.24k| UINT64_C(4273802176), // VCVTNSD 812| 2.24k| UINT64_C(4273801664), // VCVTNSH 813| 2.24k| UINT64_C(4273801920), // VCVTNSS 814| 2.24k| UINT64_C(4273802048), // VCVTNUD 815| 2.24k| UINT64_C(4273801536), // VCVTNUH 816| 2.24k| UINT64_C(4273801792), // VCVTNUS 817| 2.24k| UINT64_C(4089119232), // VCVTPNSDf 818| 2.24k| UINT64_C(4088857088), // VCVTPNSDh 819| 2.24k| UINT64_C(4089119296), // VCVTPNSQf 820| 2.24k| UINT64_C(4088857152), // VCVTPNSQh 821| 2.24k| UINT64_C(4089119360), // VCVTPNUDf 822| 2.24k| UINT64_C(4088857216), // VCVTPNUDh 823| 2.24k| UINT64_C(4089119424), // VCVTPNUQf 824| 2.24k| UINT64_C(4088857280), // VCVTPNUQh 825| 2.24k| UINT64_C(4273867712), // VCVTPSD 826| 2.24k| UINT64_C(4273867200), // VCVTPSH 827| 2.24k| UINT64_C(4273867456), // VCVTPSS 828| 2.24k| UINT64_C(4273867584), // VCVTPUD 829| 2.24k| UINT64_C(4273867072), // VCVTPUH 830| 2.24k| UINT64_C(4273867328), // VCVTPUS 831| 2.24k| UINT64_C(246877120), // VCVTSD 832| 2.24k| UINT64_C(246614976), // VCVTTDH 833| 2.24k| UINT64_C(246549440), // VCVTTHD 834| 2.24k| UINT64_C(246549184), // VCVTTHS 835| 2.24k| UINT64_C(246614720), // VCVTTSH 836| 2.24k| UINT64_C(4088792576), // VCVTf2h 837| 2.24k| UINT64_C(4089120512), // VCVTf2sd 838| 2.24k| UINT64_C(4089120576), // VCVTf2sq 839| 2.24k| UINT64_C(4089120640), // VCVTf2ud 840| 2.24k| UINT64_C(4089120704), // VCVTf2uq 841| 2.24k| UINT64_C(4068478736), // VCVTf2xsd 842| 2.24k| UINT64_C(4068478800), // VCVTf2xsq 843| 2.24k| UINT64_C(4085255952), // VCVTf2xud 844| 2.24k| UINT64_C(4085256016), // VCVTf2xuq 845| 2.24k| UINT64_C(4088792832), // VCVTh2f 846| 2.24k| UINT64_C(4088858368), // VCVTh2sd 847| 2.24k| UINT64_C(4088858432), // VCVTh2sq 848| 2.24k| UINT64_C(4088858496), // VCVTh2ud 849| 2.24k| UINT64_C(4088858560), // VCVTh2uq 850| 2.24k| UINT64_C(4068478224), // VCVTh2xsd 851| 2.24k| UINT64_C(4068478288), // VCVTh2xsq 852| 2.24k| UINT64_C(4085255440), // VCVTh2xud 853| 2.24k| UINT64_C(4085255504), // VCVTh2xuq 854| 2.24k| UINT64_C(4089120256), // VCVTs2fd 855| 2.24k| UINT64_C(4089120320), // VCVTs2fq 856| 2.24k| UINT64_C(4088858112), // VCVTs2hd 857| 2.24k| UINT64_C(4088858176), // VCVTs2hq 858| 2.24k| UINT64_C(4089120384), // VCVTu2fd 859| 2.24k| UINT64_C(4089120448), // VCVTu2fq 860| 2.24k| UINT64_C(4088858240), // VCVTu2hd 861| 2.24k| UINT64_C(4088858304), // VCVTu2hq 862| 2.24k| UINT64_C(4068478480), // VCVTxs2fd 863| 2.24k| UINT64_C(4068478544), // VCVTxs2fq 864| 2.24k| UINT64_C(4068477968), // VCVTxs2hd 865| 2.24k| UINT64_C(4068478032), // VCVTxs2hq 866| 2.24k| UINT64_C(4085255696), // VCVTxu2fd 867| 2.24k| UINT64_C(4085255760), // VCVTxu2fq 868| 2.24k| UINT64_C(4085255184), // VCVTxu2hd 869| 2.24k| UINT64_C(4085255248), // VCVTxu2hq 870| 2.24k| UINT64_C(243272448), // VDIVD 871| 2.24k| UINT64_C(243271936), // VDIVH 872| 2.24k| UINT64_C(243272192), // VDIVS 873| 2.24k| UINT64_C(243272496), // VDUP16d 874| 2.24k| UINT64_C(245369648), // VDUP16q 875| 2.24k| UINT64_C(243272464), // VDUP32d 876| 2.24k| UINT64_C(245369616), // VDUP32q 877| 2.24k| UINT64_C(247466768), // VDUP8d 878| 2.24k| UINT64_C(249563920), // VDUP8q 879| 2.24k| UINT64_C(4088531968), // VDUPLN16d 880| 2.24k| UINT64_C(4088532032), // VDUPLN16q 881| 2.24k| UINT64_C(4088663040), // VDUPLN32d 882| 2.24k| UINT64_C(4088663104), // VDUPLN32q 883| 2.24k| UINT64_C(4088466432), // VDUPLN8d 884| 2.24k| UINT64_C(4088466496), // VDUPLN8q 885| 2.24k| UINT64_C(4076863760), // VEORd 886| 2.24k| UINT64_C(4076863824), // VEORq 887| 2.24k| UINT64_C(4071620608), // VEXTd16 888| 2.24k| UINT64_C(4071620608), // VEXTd32 889| 2.24k| UINT64_C(4071620608), // VEXTd8 890| 2.24k| UINT64_C(4071620672), // VEXTq16 891| 2.24k| UINT64_C(4071620672), // VEXTq32 892| 2.24k| UINT64_C(4071620672), // VEXTq64 893| 2.24k| UINT64_C(4071620672), // VEXTq8 894| 2.24k| UINT64_C(245369600), // VFMAD 895| 2.24k| UINT64_C(245369088), // VFMAH 896| 2.24k| UINT64_C(245369344), // VFMAS 897| 2.24k| UINT64_C(4060089360), // VFMAfd 898| 2.24k| UINT64_C(4060089424), // VFMAfq 899| 2.24k| UINT64_C(4061137936), // VFMAhd 900| 2.24k| UINT64_C(4061138000), // VFMAhq 901| 2.24k| UINT64_C(245369664), // VFMSD 902| 2.24k| UINT64_C(245369152), // VFMSH 903| 2.24k| UINT64_C(245369408), // VFMSS 904| 2.24k| UINT64_C(4062186512), // VFMSfd 905| 2.24k| UINT64_C(4062186576), // VFMSfq 906| 2.24k| UINT64_C(4063235088), // VFMShd 907| 2.24k| UINT64_C(4063235152), // VFMShq 908| 2.24k| UINT64_C(244321088), // VFNMAD 909| 2.24k| UINT64_C(244320576), // VFNMAH 910| 2.24k| UINT64_C(244320832), // VFNMAS 911| 2.24k| UINT64_C(244321024), // VFNMSD 912| 2.24k| UINT64_C(244320512), // VFNMSH 913| 2.24k| UINT64_C(244320768), // VFNMSS 914| 2.24k| UINT64_C(235932432), // VGETLNi32 915| 2.24k| UINT64_C(235932464), // VGETLNs16 916| 2.24k| UINT64_C(240126736), // VGETLNs8 917| 2.24k| UINT64_C(244321072), // VGETLNu16 918| 2.24k| UINT64_C(248515344), // VGETLNu8 919| 2.24k| UINT64_C(4060086336), // VHADDsv16i8 920| 2.24k| UINT64_C(4062183424), // VHADDsv2i32 921| 2.24k| UINT64_C(4061134848), // VHADDsv4i16 922| 2.24k| UINT64_C(4062183488), // VHADDsv4i32 923| 2.24k| UINT64_C(4061134912), // VHADDsv8i16 924| 2.24k| UINT64_C(4060086272), // VHADDsv8i8 925| 2.24k| UINT64_C(4076863552), // VHADDuv16i8 926| 2.24k| UINT64_C(4078960640), // VHADDuv2i32 927| 2.24k| UINT64_C(4077912064), // VHADDuv4i16 928| 2.24k| UINT64_C(4078960704), // VHADDuv4i32 929| 2.24k| UINT64_C(4077912128), // VHADDuv8i16 930| 2.24k| UINT64_C(4076863488), // VHADDuv8i8 931| 2.24k| UINT64_C(4060086848), // VHSUBsv16i8 932| 2.24k| UINT64_C(4062183936), // VHSUBsv2i32 933| 2.24k| UINT64_C(4061135360), // VHSUBsv4i16 934| 2.24k| UINT64_C(4062184000), // VHSUBsv4i32 935| 2.24k| UINT64_C(4061135424), // VHSUBsv8i16 936| 2.24k| UINT64_C(4060086784), // VHSUBsv8i8 937| 2.24k| UINT64_C(4076864064), // VHSUBuv16i8 938| 2.24k| UINT64_C(4078961152), // VHSUBuv2i32 939| 2.24k| UINT64_C(4077912576), // VHSUBuv4i16 940| 2.24k| UINT64_C(4078961216), // VHSUBuv4i32 941| 2.24k| UINT64_C(4077912640), // VHSUBuv8i16 942| 2.24k| UINT64_C(4076864000), // VHSUBuv8i8 943| 2.24k| UINT64_C(4272949952), // VINSH 944| 2.24k| UINT64_C(4104129615), // VLD1DUPd16 945| 2.24k| UINT64_C(4104129613), // VLD1DUPd16wb_fixed 946| 2.24k| UINT64_C(4104129600), // VLD1DUPd16wb_register 947| 2.24k| UINT64_C(4104129679), // VLD1DUPd32 948| 2.24k| UINT64_C(4104129677), // VLD1DUPd32wb_fixed 949| 2.24k| UINT64_C(4104129664), // VLD1DUPd32wb_register 950| 2.24k| UINT64_C(4104129551), // VLD1DUPd8 951| 2.24k| UINT64_C(4104129549), // VLD1DUPd8wb_fixed 952| 2.24k| UINT64_C(4104129536), // VLD1DUPd8wb_register 953| 2.24k| UINT64_C(4104129647), // VLD1DUPq16 954| 2.24k| UINT64_C(4104129645), // VLD1DUPq16wb_fixed 955| 2.24k| UINT64_C(4104129632), // VLD1DUPq16wb_register 956| 2.24k| UINT64_C(4104129711), // VLD1DUPq32 957| 2.24k| UINT64_C(4104129709), // VLD1DUPq32wb_fixed 958| 2.24k| UINT64_C(4104129696), // VLD1DUPq32wb_register 959| 2.24k| UINT64_C(4104129583), // VLD1DUPq8 960| 2.24k| UINT64_C(4104129581), // VLD1DUPq8wb_fixed 961| 2.24k| UINT64_C(4104129568), // VLD1DUPq8wb_register 962| 2.24k| UINT64_C(4104127503), // VLD1LNd16 963| 2.24k| UINT64_C(4104127488), // VLD1LNd16_UPD 964| 2.24k| UINT64_C(4104128527), // VLD1LNd32 965| 2.24k| UINT64_C(4104128512), // VLD1LNd32_UPD 966| 2.24k| UINT64_C(4104126479), // VLD1LNd8 967| 2.24k| UINT64_C(4104126464), // VLD1LNd8_UPD 968| 2.24k| UINT64_C(0), 969| 2.24k| UINT64_C(0), 970| 2.24k| UINT64_C(0), 971| 2.24k| UINT64_C(0), 972| 2.24k| UINT64_C(0), 973| 2.24k| UINT64_C(0), 974| 2.24k| UINT64_C(0), 975| 2.24k| UINT64_C(0), 976| 2.24k| UINT64_C(0), 977| 2.24k| UINT64_C(0), // VLD1LNq16Pseudo 978| 2.24k| UINT64_C(0), // VLD1LNq16Pseudo_UPD 979| 2.24k| UINT64_C(0), // VLD1LNq32Pseudo 980| 2.24k| UINT64_C(0), // VLD1LNq32Pseudo_UPD 981| 2.24k| UINT64_C(0), // VLD1LNq8Pseudo 982| 2.24k| UINT64_C(0), // VLD1LNq8Pseudo_UPD 983| 2.24k| UINT64_C(4095739727), // VLD1d16 984| 2.24k| UINT64_C(4095738447), // VLD1d16Q 985| 2.24k| UINT64_C(4095738445), // VLD1d16Qwb_fixed 986| 2.24k| UINT64_C(4095738432), // VLD1d16Qwb_register 987| 2.24k| UINT64_C(4095739471), // VLD1d16T 988| 2.24k| UINT64_C(4095739469), // VLD1d16Twb_fixed 989| 2.24k| UINT64_C(4095739456), // VLD1d16Twb_register 990| 2.24k| UINT64_C(4095739725), // VLD1d16wb_fixed 991| 2.24k| UINT64_C(4095739712), // VLD1d16wb_register 992| 2.24k| UINT64_C(4095739791), // VLD1d32 993| 2.24k| UINT64_C(4095738511), // VLD1d32Q 994| 2.24k| UINT64_C(4095738509), // VLD1d32Qwb_fixed 995| 2.24k| UINT64_C(4095738496), // VLD1d32Qwb_register 996| 2.24k| UINT64_C(4095739535), // VLD1d32T 997| 2.24k| UINT64_C(4095739533), // VLD1d32Twb_fixed 998| 2.24k| UINT64_C(4095739520), // VLD1d32Twb_register 999| 2.24k| UINT64_C(4095739789), // VLD1d32wb_fixed 1000| 2.24k| UINT64_C(4095739776), // VLD1d32wb_register 1001| 2.24k| UINT64_C(4095739855), // VLD1d64 1002| 2.24k| UINT64_C(4095738575), // VLD1d64Q 1003| 2.24k| UINT64_C(0), // VLD1d64QPseudo 1004| 2.24k| UINT64_C(0), // VLD1d64QPseudoWB_fixed 1005| 2.24k| UINT64_C(0), // VLD1d64QPseudoWB_register 1006| 2.24k| UINT64_C(4095738573), // VLD1d64Qwb_fixed 1007| 2.24k| UINT64_C(4095738560), // VLD1d64Qwb_register 1008| 2.24k| UINT64_C(4095739599), // VLD1d64T 1009| 2.24k| UINT64_C(0), // VLD1d64TPseudo 1010| 2.24k| UINT64_C(0), // VLD1d64TPseudoWB_fixed 1011| 2.24k| UINT64_C(0), // VLD1d64TPseudoWB_register 1012| 2.24k| UINT64_C(4095739597), // VLD1d64Twb_fixed 1013| 2.24k| UINT64_C(4095739584), // VLD1d64Twb_register 1014| 2.24k| UINT64_C(4095739853), // VLD1d64wb_fixed 1015| 2.24k| UINT64_C(4095739840), // VLD1d64wb_register 1016| 2.24k| UINT64_C(4095739663), // VLD1d8 1017| 2.24k| UINT64_C(4095738383), // VLD1d8Q 1018| 2.24k| UINT64_C(4095738381), // VLD1d8Qwb_fixed 1019| 2.24k| UINT64_C(4095738368), // VLD1d8Qwb_register 1020| 2.24k| UINT64_C(4095739407), // VLD1d8T 1021| 2.24k| UINT64_C(4095739405), // VLD1d8Twb_fixed 1022| 2.24k| UINT64_C(4095739392), // VLD1d8Twb_register 1023| 2.24k| UINT64_C(4095739661), // VLD1d8wb_fixed 1024| 2.24k| UINT64_C(4095739648), // VLD1d8wb_register 1025| 2.24k| UINT64_C(4095740495), // VLD1q16 1026| 2.24k| UINT64_C(4095740493), // VLD1q16wb_fixed 1027| 2.24k| UINT64_C(4095740480), // VLD1q16wb_register 1028| 2.24k| UINT64_C(4095740559), // VLD1q32 1029| 2.24k| UINT64_C(4095740557), // VLD1q32wb_fixed 1030| 2.24k| UINT64_C(4095740544), // VLD1q32wb_register 1031| 2.24k| UINT64_C(4095740623), // VLD1q64 1032| 2.24k| UINT64_C(4095740621), // VLD1q64wb_fixed 1033| 2.24k| UINT64_C(4095740608), // VLD1q64wb_register 1034| 2.24k| UINT64_C(4095740431), // VLD1q8 1035| 2.24k| UINT64_C(4095740429), // VLD1q8wb_fixed 1036| 2.24k| UINT64_C(4095740416), // VLD1q8wb_register 1037| 2.24k| UINT64_C(4104129871), // VLD2DUPd16 1038| 2.24k| UINT64_C(4104129869), // VLD2DUPd16wb_fixed 1039| 2.24k| UINT64_C(4104129856), // VLD2DUPd16wb_register 1040| 2.24k| UINT64_C(4104129903), // VLD2DUPd16x2 1041| 2.24k| UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed 1042| 2.24k| UINT64_C(4104129888), // VLD2DUPd16x2wb_register 1043| 2.24k| UINT64_C(4104129935), // VLD2DUPd32 1044| 2.24k| UINT64_C(4104129933), // VLD2DUPd32wb_fixed 1045| 2.24k| UINT64_C(4104129920), // VLD2DUPd32wb_register 1046| 2.24k| UINT64_C(4104129967), // VLD2DUPd32x2 1047| 2.24k| UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed 1048| 2.24k| UINT64_C(4104129952), // VLD2DUPd32x2wb_register 1049| 2.24k| UINT64_C(4104129807), // VLD2DUPd8 1050| 2.24k| UINT64_C(4104129805), // VLD2DUPd8wb_fixed 1051| 2.24k| UINT64_C(4104129792), // VLD2DUPd8wb_register 1052| 2.24k| UINT64_C(4104129839), // VLD2DUPd8x2 1053| 2.24k| UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed 1054| 2.24k| UINT64_C(4104129824), // VLD2DUPd8x2wb_register 1055| 2.24k| UINT64_C(4104127759), // VLD2LNd16 1056| 2.24k| UINT64_C(0), // VLD2LNd16Pseudo 1057| 2.24k| UINT64_C(0), // VLD2LNd16Pseudo_UPD 1058| 2.24k| UINT64_C(4104127744), // VLD2LNd16_UPD 1059| 2.24k| UINT64_C(4104128783), // VLD2LNd32 1060| 2.24k| UINT64_C(0), // VLD2LNd32Pseudo 1061| 2.24k| UINT64_C(0), // VLD2LNd32Pseudo_UPD 1062| 2.24k| UINT64_C(4104128768), // VLD2LNd32_UPD 1063| 2.24k| UINT64_C(4104126735), // VLD2LNd8 1064| 2.24k| UINT64_C(0), // VLD2LNd8Pseudo 1065| 2.24k| UINT64_C(0), // VLD2LNd8Pseudo_UPD 1066| 2.24k| UINT64_C(4104126720), // VLD2LNd8_UPD 1067| 2.24k| UINT64_C(0), 1068| 2.24k| UINT64_C(0), 1069| 2.24k| UINT64_C(0), 1070| 2.24k| UINT64_C(0), 1071| 2.24k| UINT64_C(0), 1072| 2.24k| UINT64_C(0), 1073| 2.24k| UINT64_C(0), 1074| 2.24k| UINT64_C(0), 1075| 2.24k| UINT64_C(0), 1076| 2.24k| UINT64_C(4104127791), // VLD2LNq16 1077| 2.24k| UINT64_C(0), // VLD2LNq16Pseudo 1078| 2.24k| UINT64_C(0), // VLD2LNq16Pseudo_UPD 1079| 2.24k| UINT64_C(4104127776), // VLD2LNq16_UPD 1080| 2.24k| UINT64_C(4104128847), // VLD2LNq32 1081| 2.24k| UINT64_C(0), // VLD2LNq32Pseudo 1082| 2.24k| UINT64_C(0), // VLD2LNq32Pseudo_UPD 1083| 2.24k| UINT64_C(4104128832), // VLD2LNq32_UPD 1084| 2.24k| UINT64_C(0), 1085| 2.24k| UINT64_C(0), 1086| 2.24k| UINT64_C(0), 1087| 2.24k| UINT64_C(0), 1088| 2.24k| UINT64_C(0), 1089| 2.24k| UINT64_C(0), 1090| 2.24k| UINT64_C(4095740239), // VLD2b16 1091| 2.24k| UINT64_C(4095740237), // VLD2b16wb_fixed 1092| 2.24k| UINT64_C(4095740224), // VLD2b16wb_register 1093| 2.24k| UINT64_C(4095740303), // VLD2b32 1094| 2.24k| UINT64_C(4095740301), // VLD2b32wb_fixed 1095| 2.24k| UINT64_C(4095740288), // VLD2b32wb_register 1096| 2.24k| UINT64_C(4095740175), // VLD2b8 1097| 2.24k| UINT64_C(4095740173), // VLD2b8wb_fixed 1098| 2.24k| UINT64_C(4095740160), // VLD2b8wb_register 1099| 2.24k| UINT64_C(4095739983), // VLD2d16 1100| 2.24k| UINT64_C(4095739981), // VLD2d16wb_fixed 1101| 2.24k| UINT64_C(4095739968), // VLD2d16wb_register 1102| 2.24k| UINT64_C(4095740047), // VLD2d32 1103| 2.24k| UINT64_C(4095740045), // VLD2d32wb_fixed 1104| 2.24k| UINT64_C(4095740032), // VLD2d32wb_register 1105| 2.24k| UINT64_C(4095739919), // VLD2d8 1106| 2.24k| UINT64_C(4095739917), // VLD2d8wb_fixed 1107| 2.24k| UINT64_C(4095739904), // VLD2d8wb_register 1108| 2.24k| UINT64_C(4095738703), // VLD2q16 1109| 2.24k| UINT64_C(0), // VLD2q16Pseudo 1110| 2.24k| UINT64_C(0), // VLD2q16PseudoWB_fixed 1111| 2.24k| UINT64_C(0), // VLD2q16PseudoWB_register 1112| 2.24k| UINT64_C(4095738701), // VLD2q16wb_fixed 1113| 2.24k| UINT64_C(4095738688), // VLD2q16wb_register 1114| 2.24k| UINT64_C(4095738767), // VLD2q32 1115| 2.24k| UINT64_C(0), // VLD2q32Pseudo 1116| 2.24k| UINT64_C(0), // VLD2q32PseudoWB_fixed 1117| 2.24k| UINT64_C(0), // VLD2q32PseudoWB_register 1118| 2.24k| UINT64_C(4095738765), // VLD2q32wb_fixed 1119| 2.24k| UINT64_C(4095738752), // VLD2q32wb_register 1120| 2.24k| UINT64_C(4095738639), // VLD2q8 1121| 2.24k| UINT64_C(0), // VLD2q8Pseudo 1122| 2.24k| UINT64_C(0), // VLD2q8PseudoWB_fixed 1123| 2.24k| UINT64_C(0), // VLD2q8PseudoWB_register 1124| 2.24k| UINT64_C(4095738637), // VLD2q8wb_fixed 1125| 2.24k| UINT64_C(4095738624), // VLD2q8wb_register 1126| 2.24k| UINT64_C(4104130127), // VLD3DUPd16 1127| 2.24k| UINT64_C(0), // VLD3DUPd16Pseudo 1128| 2.24k| UINT64_C(0), // VLD3DUPd16Pseudo_UPD 1129| 2.24k| UINT64_C(4104130112), // VLD3DUPd16_UPD 1130| 2.24k| UINT64_C(4104130191), // VLD3DUPd32 1131| 2.24k| UINT64_C(0), // VLD3DUPd32Pseudo 1132| 2.24k| UINT64_C(0), // VLD3DUPd32Pseudo_UPD 1133| 2.24k| UINT64_C(4104130176), // VLD3DUPd32_UPD 1134| 2.24k| UINT64_C(4104130063), // VLD3DUPd8 1135| 2.24k| UINT64_C(0), // VLD3DUPd8Pseudo 1136| 2.24k| UINT64_C(0), // VLD3DUPd8Pseudo_UPD 1137| 2.24k| UINT64_C(4104130048), // VLD3DUPd8_UPD 1138| 2.24k| UINT64_C(0), 1139| 2.24k| UINT64_C(0), 1140| 2.24k| UINT64_C(0), 1141| 2.24k| UINT64_C(0), 1142| 2.24k| UINT64_C(0), 1143| 2.24k| UINT64_C(0), 1144| 2.24k| UINT64_C(0), 1145| 2.24k| UINT64_C(0), 1146| 2.24k| UINT64_C(0), 1147| 2.24k| UINT64_C(4104130159), // VLD3DUPq16 1148| 2.24k| UINT64_C(4104130144), // VLD3DUPq16_UPD 1149| 2.24k| UINT64_C(4104130223), // VLD3DUPq32 1150| 2.24k| UINT64_C(4104130208), // VLD3DUPq32_UPD 1151| 2.24k| UINT64_C(4104130095), // VLD3DUPq8 1152| 2.24k| UINT64_C(4104130080), // VLD3DUPq8_UPD 1153| 2.24k| UINT64_C(0), 1154| 2.24k| UINT64_C(0), 1155| 2.24k| UINT64_C(0), 1156| 2.24k| UINT64_C(0), 1157| 2.24k| UINT64_C(0), 1158| 2.24k| UINT64_C(0), 1159| 2.24k| UINT64_C(0), 1160| 2.24k| UINT64_C(0), 1161| 2.24k| UINT64_C(0), 1162| 2.24k| UINT64_C(4104128015), // VLD3LNd16 1163| 2.24k| UINT64_C(0), // VLD3LNd16Pseudo 1164| 2.24k| UINT64_C(0), // VLD3LNd16Pseudo_UPD 1165| 2.24k| UINT64_C(4104128000), // VLD3LNd16_UPD 1166| 2.24k| UINT64_C(4104129039), // VLD3LNd32 1167| 2.24k| UINT64_C(0), // VLD3LNd32Pseudo 1168| 2.24k| UINT64_C(0), // VLD3LNd32Pseudo_UPD 1169| 2.24k| UINT64_C(4104129024), // VLD3LNd32_UPD 1170| 2.24k| UINT64_C(4104126991), // VLD3LNd8 1171| 2.24k| UINT64_C(0), // VLD3LNd8Pseudo 1172| 2.24k| UINT64_C(0), // VLD3LNd8Pseudo_UPD 1173| 2.24k| UINT64_C(4104126976), // VLD3LNd8_UPD 1174| 2.24k| UINT64_C(0), 1175| 2.24k| UINT64_C(0), 1176| 2.24k| UINT64_C(0), 1177| 2.24k| UINT64_C(0), 1178| 2.24k| UINT64_C(0), 1179| 2.24k| UINT64_C(0), 1180| 2.24k| UINT64_C(0), 1181| 2.24k| UINT64_C(0), 1182| 2.24k| UINT64_C(0), 1183| 2.24k| UINT64_C(4104128047), // VLD3LNq16 1184| 2.24k| UINT64_C(0), // VLD3LNq16Pseudo 1185| 2.24k| UINT64_C(0), // VLD3LNq16Pseudo_UPD 1186| 2.24k| UINT64_C(4104128032), // VLD3LNq16_UPD 1187| 2.24k| UINT64_C(4104129103), // VLD3LNq32 1188| 2.24k| UINT64_C(0), // VLD3LNq32Pseudo 1189| 2.24k| UINT64_C(0), // VLD3LNq32Pseudo_UPD 1190| 2.24k| UINT64_C(4104129088), // VLD3LNq32_UPD 1191| 2.24k| UINT64_C(0), 1192| 2.24k| UINT64_C(0), 1193| 2.24k| UINT64_C(0), 1194| 2.24k| UINT64_C(0), 1195| 2.24k| UINT64_C(0), 1196| 2.24k| UINT64_C(0), 1197| 2.24k| UINT64_C(4095738959), // VLD3d16 1198| 2.24k| UINT64_C(0), // VLD3d16Pseudo 1199| 2.24k| UINT64_C(0), // VLD3d16Pseudo_UPD 1200| 2.24k| UINT64_C(4095738944), // VLD3d16_UPD 1201| 2.24k| UINT64_C(4095739023), // VLD3d32 1202| 2.24k| UINT64_C(0), // VLD3d32Pseudo 1203| 2.24k| UINT64_C(0), // VLD3d32Pseudo_UPD 1204| 2.24k| UINT64_C(4095739008), // VLD3d32_UPD 1205| 2.24k| UINT64_C(4095738895), // VLD3d8 1206| 2.24k| UINT64_C(0), // VLD3d8Pseudo 1207| 2.24k| UINT64_C(0), // VLD3d8Pseudo_UPD 1208| 2.24k| UINT64_C(4095738880), // VLD3d8_UPD 1209| 2.24k| UINT64_C(0), 1210| 2.24k| UINT64_C(0), 1211| 2.24k| UINT64_C(0), 1212| 2.24k| UINT64_C(0), 1213| 2.24k| UINT64_C(0), 1214| 2.24k| UINT64_C(0), 1215| 2.24k| UINT64_C(0), 1216| 2.24k| UINT64_C(0), 1217| 2.24k| UINT64_C(0), 1218| 2.24k| UINT64_C(4095739215), // VLD3q16 1219| 2.24k| UINT64_C(0), // VLD3q16Pseudo_UPD 1220| 2.24k| UINT64_C(4095739200), // VLD3q16_UPD 1221| 2.24k| UINT64_C(0), // VLD3q16oddPseudo 1222| 2.24k| UINT64_C(0), // VLD3q16oddPseudo_UPD 1223| 2.24k| UINT64_C(4095739279), // VLD3q32 1224| 2.24k| UINT64_C(0), // VLD3q32Pseudo_UPD 1225| 2.24k| UINT64_C(4095739264), // VLD3q32_UPD 1226| 2.24k| UINT64_C(0), // VLD3q32oddPseudo 1227| 2.24k| UINT64_C(0), // VLD3q32oddPseudo_UPD 1228| 2.24k| UINT64_C(4095739151), // VLD3q8 1229| 2.24k| UINT64_C(0), // VLD3q8Pseudo_UPD 1230| 2.24k| UINT64_C(4095739136), // VLD3q8_UPD 1231| 2.24k| UINT64_C(0), // VLD3q8oddPseudo 1232| 2.24k| UINT64_C(0), // VLD3q8oddPseudo_UPD 1233| 2.24k| UINT64_C(0), 1234| 2.24k| UINT64_C(0), 1235| 2.24k| UINT64_C(0), 1236| 2.24k| UINT64_C(0), 1237| 2.24k| UINT64_C(0), 1238| 2.24k| UINT64_C(0), 1239| 2.24k| UINT64_C(0), 1240| 2.24k| UINT64_C(0), 1241| 2.24k| UINT64_C(0), 1242| 2.24k| UINT64_C(4104130383), // VLD4DUPd16 1243| 2.24k| UINT64_C(0), // VLD4DUPd16Pseudo 1244| 2.24k| UINT64_C(0), // VLD4DUPd16Pseudo_UPD 1245| 2.24k| UINT64_C(4104130368), // VLD4DUPd16_UPD 1246| 2.24k| UINT64_C(4104130447), // VLD4DUPd32 1247| 2.24k| UINT64_C(0), // VLD4DUPd32Pseudo 1248| 2.24k| UINT64_C(0), // VLD4DUPd32Pseudo_UPD 1249| 2.24k| UINT64_C(4104130432), // VLD4DUPd32_UPD 1250| 2.24k| UINT64_C(4104130319), // VLD4DUPd8 1251| 2.24k| UINT64_C(0), // VLD4DUPd8Pseudo 1252| 2.24k| UINT64_C(0), // VLD4DUPd8Pseudo_UPD 1253| 2.24k| UINT64_C(4104130304), // VLD4DUPd8_UPD 1254| 2.24k| UINT64_C(0), 1255| 2.24k| UINT64_C(0), 1256| 2.24k| UINT64_C(0), 1257| 2.24k| UINT64_C(0), 1258| 2.24k| UINT64_C(0), 1259| 2.24k| UINT64_C(0), 1260| 2.24k| UINT64_C(0), 1261| 2.24k| UINT64_C(0), 1262| 2.24k| UINT64_C(0), 1263| 2.24k| UINT64_C(4104130415), // VLD4DUPq16 1264| 2.24k| UINT64_C(4104130400), // VLD4DUPq16_UPD 1265| 2.24k| UINT64_C(4104130479), // VLD4DUPq32 1266| 2.24k| UINT64_C(4104130464), // VLD4DUPq32_UPD 1267| 2.24k| UINT64_C(4104130351), // VLD4DUPq8 1268| 2.24k| UINT64_C(4104130336), // VLD4DUPq8_UPD 1269| 2.24k| UINT64_C(0), 1270| 2.24k| UINT64_C(0), 1271| 2.24k| UINT64_C(0), 1272| 2.24k| UINT64_C(0), 1273| 2.24k| UINT64_C(0), 1274| 2.24k| UINT64_C(0), 1275| 2.24k| UINT64_C(0), 1276| 2.24k| UINT64_C(0), 1277| 2.24k| UINT64_C(0), 1278| 2.24k| UINT64_C(4104128271), // VLD4LNd16 1279| 2.24k| UINT64_C(0), // VLD4LNd16Pseudo 1280| 2.24k| UINT64_C(0), // VLD4LNd16Pseudo_UPD 1281| 2.24k| UINT64_C(4104128256), // VLD4LNd16_UPD 1282| 2.24k| UINT64_C(4104129295), // VLD4LNd32 1283| 2.24k| UINT64_C(0), // VLD4LNd32Pseudo 1284| 2.24k| UINT64_C(0), // VLD4LNd32Pseudo_UPD 1285| 2.24k| UINT64_C(4104129280), // VLD4LNd32_UPD 1286| 2.24k| UINT64_C(4104127247), // VLD4LNd8 1287| 2.24k| UINT64_C(0), // VLD4LNd8Pseudo 1288| 2.24k| UINT64_C(0), // VLD4LNd8Pseudo_UPD 1289| 2.24k| UINT64_C(4104127232), // VLD4LNd8_UPD 1290| 2.24k| UINT64_C(0), 1291| 2.24k| UINT64_C(0), 1292| 2.24k| UINT64_C(0), 1293| 2.24k| UINT64_C(0), 1294| 2.24k| UINT64_C(0), 1295| 2.24k| UINT64_C(0), 1296| 2.24k| UINT64_C(0), 1297| 2.24k| UINT64_C(0), 1298| 2.24k| UINT64_C(0), 1299| 2.24k| UINT64_C(4104128303), // VLD4LNq16 1300| 2.24k| UINT64_C(0), // VLD4LNq16Pseudo 1301| 2.24k| UINT64_C(0), // VLD4LNq16Pseudo_UPD 1302| 2.24k| UINT64_C(4104128288), // VLD4LNq16_UPD 1303| 2.24k| UINT64_C(4104129359), // VLD4LNq32 1304| 2.24k| UINT64_C(0), // VLD4LNq32Pseudo 1305| 2.24k| UINT64_C(0), // VLD4LNq32Pseudo_UPD 1306| 2.24k| UINT64_C(4104129344), // VLD4LNq32_UPD 1307| 2.24k| UINT64_C(0), 1308| 2.24k| UINT64_C(0), 1309| 2.24k| UINT64_C(0), 1310| 2.24k| UINT64_C(0), 1311| 2.24k| UINT64_C(0), 1312| 2.24k| UINT64_C(0), 1313| 2.24k| UINT64_C(4095737935), // VLD4d16 1314| 2.24k| UINT64_C(0), // VLD4d16Pseudo 1315| 2.24k| UINT64_C(0), // VLD4d16Pseudo_UPD 1316| 2.24k| UINT64_C(4095737920), // VLD4d16_UPD 1317| 2.24k| UINT64_C(4095737999), // VLD4d32 1318| 2.24k| UINT64_C(0), // VLD4d32Pseudo 1319| 2.24k| UINT64_C(0), // VLD4d32Pseudo_UPD 1320| 2.24k| UINT64_C(4095737984), // VLD4d32_UPD 1321| 2.24k| UINT64_C(4095737871), // VLD4d8 1322| 2.24k| UINT64_C(0), // VLD4d8Pseudo 1323| 2.24k| UINT64_C(0), // VLD4d8Pseudo_UPD 1324| 2.24k| UINT64_C(4095737856), // VLD4d8_UPD 1325| 2.24k| UINT64_C(0), 1326| 2.24k| UINT64_C(0), 1327| 2.24k| UINT64_C(0), 1328| 2.24k| UINT64_C(0), 1329| 2.24k| UINT64_C(0), 1330| 2.24k| UINT64_C(0), 1331| 2.24k| UINT64_C(0), 1332| 2.24k| UINT64_C(0), 1333| 2.24k| UINT64_C(0), 1334| 2.24k| UINT64_C(4095738191), // VLD4q16 1335| 2.24k| UINT64_C(0), // VLD4q16Pseudo_UPD 1336| 2.24k| UINT64_C(4095738176), // VLD4q16_UPD 1337| 2.24k| UINT64_C(0), // VLD4q16oddPseudo 1338| 2.24k| UINT64_C(0), // VLD4q16oddPseudo_UPD 1339| 2.24k| UINT64_C(4095738255), // VLD4q32 1340| 2.24k| UINT64_C(0), // VLD4q32Pseudo_UPD 1341| 2.24k| UINT64_C(4095738240), // VLD4q32_UPD 1342| 2.24k| UINT64_C(0), // VLD4q32oddPseudo 1343| 2.24k| UINT64_C(0), // VLD4q32oddPseudo_UPD 1344| 2.24k| UINT64_C(4095738127), // VLD4q8 1345| 2.24k| UINT64_C(0), // VLD4q8Pseudo_UPD 1346| 2.24k| UINT64_C(4095738112), // VLD4q8_UPD 1347| 2.24k| UINT64_C(0), // VLD4q8oddPseudo 1348| 2.24k| UINT64_C(0), // VLD4q8oddPseudo_UPD 1349| 2.24k| UINT64_C(0), 1350| 2.24k| UINT64_C(0), 1351| 2.24k| UINT64_C(0), 1352| 2.24k| UINT64_C(0), 1353| 2.24k| UINT64_C(0), 1354| 2.24k| UINT64_C(0), 1355| 2.24k| UINT64_C(0), 1356| 2.24k| UINT64_C(0), 1357| 2.24k| UINT64_C(0), 1358| 2.24k| UINT64_C(221252352), // VLDMDDB_UPD 1359| 2.24k| UINT64_C(210766592), // VLDMDIA 1360| 2.24k| UINT64_C(212863744), // VLDMDIA_UPD 1361| 2.24k| UINT64_C(0), // VLDMQIA 1362| 2.24k| UINT64_C(221252096), // VLDMSDB_UPD 1363| 2.24k| UINT64_C(210766336), // VLDMSIA 1364| 2.24k| UINT64_C(212863488), // VLDMSIA_UPD 1365| 2.24k| UINT64_C(219155200), // VLDRD 1366| 2.24k| UINT64_C(219154688), // VLDRH 1367| 2.24k| UINT64_C(219154944), // VLDRS 1368| 2.24k| UINT64_C(204474880), // VLLDM 1369| 2.24k| UINT64_C(203426304), // VLSTM 1370| 2.24k| UINT64_C(4269804288), // VMAXNMD 1371| 2.24k| UINT64_C(4269803776), // VMAXNMH 1372| 2.24k| UINT64_C(4076867344), // VMAXNMNDf 1373| 2.24k| UINT64_C(4077915920), // VMAXNMNDh 1374| 2.24k| UINT64_C(4076867408), // VMAXNMNQf 1375| 2.24k| UINT64_C(4077915984), // VMAXNMNQh 1376| 2.24k| UINT64_C(4269804032), // VMAXNMS 1377| 2.24k| UINT64_C(4060090112), // VMAXfd 1378| 2.24k| UINT64_C(4060090176), // VMAXfq 1379| 2.24k| UINT64_C(4061138688), // VMAXhd 1380| 2.24k| UINT64_C(4061138752), // VMAXhq 1381| 2.24k| UINT64_C(4060087872), // VMAXsv16i8 1382| 2.24k| UINT64_C(4062184960), // VMAXsv2i32 1383| 2.24k| UINT64_C(4061136384), // VMAXsv4i16 1384| 2.24k| UINT64_C(4062185024), // VMAXsv4i32 1385| 2.24k| UINT64_C(4061136448), // VMAXsv8i16 1386| 2.24k| UINT64_C(4060087808), // VMAXsv8i8 1387| 2.24k| UINT64_C(4076865088), // VMAXuv16i8 1388| 2.24k| UINT64_C(4078962176), // VMAXuv2i32 1389| 2.24k| UINT64_C(4077913600), // VMAXuv4i16 1390| 2.24k| UINT64_C(4078962240), // VMAXuv4i32 1391| 2.24k| UINT64_C(4077913664), // VMAXuv8i16 1392| 2.24k| UINT64_C(4076865024), // VMAXuv8i8 1393| 2.24k| UINT64_C(4269804352), // VMINNMD 1394| 2.24k| UINT64_C(4269803840), // VMINNMH 1395| 2.24k| UINT64_C(4078964496), // VMINNMNDf 1396| 2.24k| UINT64_C(4080013072), // VMINNMNDh 1397| 2.24k| UINT64_C(4078964560), // VMINNMNQf 1398| 2.24k| UINT64_C(4080013136), // VMINNMNQh 1399| 2.24k| UINT64_C(4269804096), // VMINNMS 1400| 2.24k| UINT64_C(4062187264), // VMINfd 1401| 2.24k| UINT64_C(4062187328), // VMINfq 1402| 2.24k| UINT64_C(4063235840), // VMINhd 1403| 2.24k| UINT64_C(4063235904), // VMINhq 1404| 2.24k| UINT64_C(4060087888), // VMINsv16i8 1405| 2.24k| UINT64_C(4062184976), // VMINsv2i32 1406| 2.24k| UINT64_C(4061136400), // VMINsv4i16 1407| 2.24k| UINT64_C(4062185040), // VMINsv4i32 1408| 2.24k| UINT64_C(4061136464), // VMINsv8i16 1409| 2.24k| UINT64_C(4060087824), // VMINsv8i8 1410| 2.24k| UINT64_C(4076865104), // VMINuv16i8 1411| 2.24k| UINT64_C(4078962192), // VMINuv2i32 1412| 2.24k| UINT64_C(4077913616), // VMINuv4i16 1413| 2.24k| UINT64_C(4078962256), // VMINuv4i32 1414| 2.24k| UINT64_C(4077913680), // VMINuv8i16 1415| 2.24k| UINT64_C(4076865040), // VMINuv8i8 1416| 2.24k| UINT64_C(234883840), // VMLAD 1417| 2.24k| UINT64_C(234883328), // VMLAH 1418| 2.24k| UINT64_C(4070572608), // VMLALslsv2i32 1419| 2.24k| UINT64_C(4069524032), // VMLALslsv4i16 1420| 2.24k| UINT64_C(4087349824), // VMLALsluv2i32 1421| 2.24k| UINT64_C(4086301248), // VMLALsluv4i16 1422| 2.24k| UINT64_C(4070574080), // VMLALsv2i64 1423| 2.24k| UINT64_C(4069525504), // VMLALsv4i32 1424| 2.24k| UINT64_C(4068476928), // VMLALsv8i16 1425| 2.24k| UINT64_C(4087351296), // VMLALuv2i64 1426| 2.24k| UINT64_C(4086302720), // VMLALuv4i32 1427| 2.24k| UINT64_C(4085254144), // VMLALuv8i16 1428| 2.24k| UINT64_C(234883584), // VMLAS 1429| 2.24k| UINT64_C(4060089616), // VMLAfd 1430| 2.24k| UINT64_C(4060089680), // VMLAfq 1431| 2.24k| UINT64_C(4061138192), // VMLAhd 1432| 2.24k| UINT64_C(4061138256), // VMLAhq 1433| 2.24k| UINT64_C(4070572352), // VMLAslfd 1434| 2.24k| UINT64_C(4087349568), // VMLAslfq 1435| 2.24k| UINT64_C(4069523776), // VMLAslhd 1436| 2.24k| UINT64_C(4086300992), // VMLAslhq 1437| 2.24k| UINT64_C(4070572096), // VMLAslv2i32 1438| 2.24k| UINT64_C(4069523520), // VMLAslv4i16 1439| 2.24k| UINT64_C(4087349312), // VMLAslv4i32 1440| 2.24k| UINT64_C(4086300736), // VMLAslv8i16 1441| 2.24k| UINT64_C(4060088640), // VMLAv16i8 1442| 2.24k| UINT64_C(4062185728), // VMLAv2i32 1443| 2.24k| UINT64_C(4061137152), // VMLAv4i16 1444| 2.24k| UINT64_C(4062185792), // VMLAv4i32 1445| 2.24k| UINT64_C(4061137216), // VMLAv8i16 1446| 2.24k| UINT64_C(4060088576), // VMLAv8i8 1447| 2.24k| UINT64_C(234883904), // VMLSD 1448| 2.24k| UINT64_C(234883392), // VMLSH 1449| 2.24k| UINT64_C(4070573632), // VMLSLslsv2i32 1450| 2.24k| UINT64_C(4069525056), // VMLSLslsv4i16 1451| 2.24k| UINT64_C(4087350848), // VMLSLsluv2i32 1452| 2.24k| UINT64_C(4086302272), // VMLSLsluv4i16 1453| 2.24k| UINT64_C(4070574592), // VMLSLsv2i64 1454| 2.24k| UINT64_C(4069526016), // VMLSLsv4i32 1455| 2.24k| UINT64_C(4068477440), // VMLSLsv8i16 1456| 2.24k| UINT64_C(4087351808), // VMLSLuv2i64 1457| 2.24k| UINT64_C(4086303232), // VMLSLuv4i32 1458| 2.24k| UINT64_C(4085254656), // VMLSLuv8i16 1459| 2.24k| UINT64_C(234883648), // VMLSS 1460| 2.24k| UINT64_C(4062186768), // VMLSfd 1461| 2.24k| UINT64_C(4062186832), // VMLSfq 1462| 2.24k| UINT64_C(4063235344), // VMLShd 1463| 2.24k| UINT64_C(4063235408), // VMLShq 1464| 2.24k| UINT64_C(4070573376), // VMLSslfd 1465| 2.24k| UINT64_C(4087350592), // VMLSslfq 1466| 2.24k| UINT64_C(4069524800), // VMLSslhd 1467| 2.24k| UINT64_C(4086302016), // VMLSslhq 1468| 2.24k| UINT64_C(4070573120), // VMLSslv2i32 1469| 2.24k| UINT64_C(4069524544), // VMLSslv4i16 1470| 2.24k| UINT64_C(4087350336), // VMLSslv4i32 1471| 2.24k| UINT64_C(4086301760), // VMLSslv8i16 1472| 2.24k| UINT64_C(4076865856), // VMLSv16i8 1473| 2.24k| UINT64_C(4078962944), // VMLSv2i32 1474| 2.24k| UINT64_C(4077914368), // VMLSv4i16 1475| 2.24k| UINT64_C(4078963008), // VMLSv4i32 1476| 2.24k| UINT64_C(4077914432), // VMLSv8i16 1477| 2.24k| UINT64_C(4076865792), // VMLSv8i8 1478| 2.24k| UINT64_C(246418240), // VMOVD 1479| 2.24k| UINT64_C(0), 1480| 2.24k| UINT64_C(205523728), // VMOVDRR 1481| 2.24k| UINT64_C(0), 1482| 2.24k| UINT64_C(4272949824), // VMOVH 1483| 2.24k| UINT64_C(234883344), // VMOVHR 1484| 2.24k| UINT64_C(4070574608), // VMOVLsv2i64 1485| 2.24k| UINT64_C(4069526032), // VMOVLsv4i32 1486| 2.24k| UINT64_C(4069001744), // VMOVLsv8i16 1487| 2.24k| UINT64_C(4087351824), // VMOVLuv2i64 1488| 2.24k| UINT64_C(4086303248), // VMOVLuv4i32 1489| 2.24k| UINT64_C(4085778960), // VMOVLuv8i16 1490| 2.24k| UINT64_C(4089053696), // VMOVNv2i32 1491| 2.24k| UINT64_C(4088791552), // VMOVNv4i16 1492| 2.24k| UINT64_C(4088529408), // VMOVNv8i8 1493| 2.24k| UINT64_C(0), 1494| 2.24k| UINT64_C(235931920), // VMOVRH 1495| 2.24k| UINT64_C(206572304), // VMOVRRD 1496| 2.24k| UINT64_C(206572048), // VMOVRRS 1497| 2.24k| UINT64_C(235932176), // VMOVRS 1498| 2.24k| UINT64_C(246417984), // VMOVS 1499| 2.24k| UINT64_C(234883600), // VMOVSR 1500| 2.24k| UINT64_C(205523472), // VMOVSRR 1501| 2.24k| UINT64_C(0), 1502| 2.24k| UINT64_C(4068478544), // VMOVv16i8 1503| 2.24k| UINT64_C(4068478512), // VMOVv1i64 1504| 2.24k| UINT64_C(4068478736), // VMOVv2f32 1505| 2.24k| UINT64_C(4068474896), // VMOVv2i32 1506| 2.24k| UINT64_C(4068478576), // VMOVv2i64 1507| 2.24k| UINT64_C(4068478800), // VMOVv4f32 1508| 2.24k| UINT64_C(4068476944), // VMOVv4i16 1509| 2.24k| UINT64_C(4068474960), // VMOVv4i32 1510| 2.24k| UINT64_C(4068477008), // VMOVv8i16 1511| 2.24k| UINT64_C(4068478480), // VMOVv8i8 1512| 2.24k| UINT64_C(250677776), // VMRS 1513| 2.24k| UINT64_C(251136528), // VMRS_FPEXC 1514| 2.24k| UINT64_C(251202064), // VMRS_FPINST 1515| 2.24k| UINT64_C(251267600), // VMRS_FPINST2 1516| 2.24k| UINT64_C(250612240), // VMRS_FPSID 1517| 2.24k| UINT64_C(251070992), // VMRS_MVFR0 1518| 2.24k| UINT64_C(251005456), // VMRS_MVFR1 1519| 2.24k| UINT64_C(250939920), // VMRS_MVFR2 1520| 2.24k| UINT64_C(249629200), // VMSR 1521| 2.24k| UINT64_C(250087952), // VMSR_FPEXC 1522| 2.24k| UINT64_C(250153488), // VMSR_FPINST 1523| 2.24k| UINT64_C(250219024), // VMSR_FPINST2 1524| 2.24k| UINT64_C(249563664), // VMSR_FPSID 1525| 2.24k| UINT64_C(236980992), // VMULD 1526| 2.24k| UINT64_C(236980480), // VMULH 1527| 2.24k| UINT64_C(4070575616), // VMULLp64 1528| 2.24k| UINT64_C(4068478464), // VMULLp8 1529| 2.24k| UINT64_C(4070574656), // VMULLslsv2i32 1530| 2.24k| UINT64_C(4069526080), // VMULLslsv4i16 1531| 2.24k| UINT64_C(4087351872), // VMULLsluv2i32 1532| 2.24k| UINT64_C(4086303296), // VMULLsluv4i16 1533| 2.24k| UINT64_C(4070575104), // VMULLsv2i64 1534| 2.24k| UINT64_C(4069526528), // VMULLsv4i32 1535| 2.24k| UINT64_C(4068477952), // VMULLsv8i16 1536| 2.24k| UINT64_C(4087352320), // VMULLuv2i64 1537| 2.24k| UINT64_C(4086303744), // VMULLuv4i32 1538| 2.24k| UINT64_C(4085255168), // VMULLuv8i16 1539| 2.24k| UINT64_C(236980736), // VMULS 1540| 2.24k| UINT64_C(4076866832), // VMULfd 1541| 2.24k| UINT64_C(4076866896), // VMULfq 1542| 2.24k| UINT64_C(4077915408), // VMULhd 1543| 2.24k| UINT64_C(4077915472), // VMULhq 1544| 2.24k| UINT64_C(4076865808), // VMULpd 1545| 2.24k| UINT64_C(4076865872), // VMULpq 1546| 2.24k| UINT64_C(4070574400), // VMULslfd 1547| 2.24k| UINT64_C(4087351616), // VMULslfq 1548| 2.24k| UINT64_C(4069525824), // VMULslhd 1549| 2.24k| UINT64_C(4086303040), // VMULslhq 1550| 2.24k| UINT64_C(4070574144), // VMULslv2i32 1551| 2.24k| UINT64_C(4069525568), // VMULslv4i16 1552| 2.24k| UINT64_C(4087351360), // VMULslv4i32 1553| 2.24k| UINT64_C(4086302784), // VMULslv8i16 1554| 2.24k| UINT64_C(4060088656), // VMULv16i8 1555| 2.24k| UINT64_C(4062185744), // VMULv2i32 1556| 2.24k| UINT64_C(4061137168), // VMULv4i16 1557| 2.24k| UINT64_C(4062185808), // VMULv4i32 1558| 2.24k| UINT64_C(4061137232), // VMULv8i16 1559| 2.24k| UINT64_C(4060088592), // VMULv8i8 1560| 2.24k| UINT64_C(4088399232), // VMVNd 1561| 2.24k| UINT64_C(4088399296), // VMVNq 1562| 2.24k| UINT64_C(4068474928), // VMVNv2i32 1563| 2.24k| UINT64_C(4068476976), // VMVNv4i16 1564| 2.24k| UINT64_C(4068474992), // VMVNv4i32 1565| 2.24k| UINT64_C(4068477040), // VMVNv8i16 1566| 2.24k| UINT64_C(246483776), // VNEGD 1567| 2.24k| UINT64_C(246483264), // VNEGH 1568| 2.24k| UINT64_C(246483520), // VNEGS 1569| 2.24k| UINT64_C(4088989632), // VNEGf32q 1570| 2.24k| UINT64_C(4088989568), // VNEGfd 1571| 2.24k| UINT64_C(4088727424), // VNEGhd 1572| 2.24k| UINT64_C(4088727488), // VNEGhq 1573| 2.24k| UINT64_C(4088726400), // VNEGs16d 1574| 2.24k| UINT64_C(4088726464), // VNEGs16q 1575| 2.24k| UINT64_C(4088988544), // VNEGs32d 1576| 2.24k| UINT64_C(4088988608), // VNEGs32q 1577| 2.24k| UINT64_C(4088464256), // VNEGs8d 1578| 2.24k| UINT64_C(4088464320), // VNEGs8q 1579| 2.24k| UINT64_C(235932480), // VNMLAD 1580| 2.24k| UINT64_C(235931968), // VNMLAH 1581| 2.24k| UINT64_C(235932224), // VNMLAS 1582| 2.24k| UINT64_C(235932416), // VNMLSD 1583| 2.24k| UINT64_C(235931904), // VNMLSH 1584| 2.24k| UINT64_C(235932160), // VNMLSS 1585| 2.24k| UINT64_C(236981056), // VNMULD 1586| 2.24k| UINT64_C(236980544), // VNMULH 1587| 2.24k| UINT64_C(236980800), // VNMULS 1588| 2.24k| UINT64_C(4063232272), // VORNd 1589| 2.24k| UINT64_C(4063232336), // VORNq 1590| 2.24k| UINT64_C(4062183696), // VORRd 1591| 2.24k| UINT64_C(4068475152), // VORRiv2i32 1592| 2.24k| UINT64_C(4068477200), // VORRiv4i16 1593| 2.24k| UINT64_C(4068475216), // VORRiv4i32 1594| 2.24k| UINT64_C(4068477264), // VORRiv8i16 1595| 2.24k| UINT64_C(4062183760), // VORRq 1596| 2.24k| UINT64_C(4088399424), // VPADALsv16i8 1597| 2.24k| UINT64_C(4088923648), // VPADALsv2i32 1598| 2.24k| UINT64_C(4088661504), // VPADALsv4i16 1599| 2.24k| UINT64_C(4088923712), // VPADALsv4i32 1600| 2.24k| UINT64_C(4088661568), // VPADALsv8i16 1601| 2.24k| UINT64_C(4088399360), // VPADALsv8i8 1602| 2.24k| UINT64_C(4088399552), // VPADALuv16i8 1603| 2.24k| UINT64_C(4088923776), // VPADALuv2i32 1604| 2.24k| UINT64_C(4088661632), // VPADALuv4i16 1605| 2.24k| UINT64_C(4088923840), // VPADALuv4i32 1606| 2.24k| UINT64_C(4088661696), // VPADALuv8i16 1607| 2.24k| UINT64_C(4088399488), // VPADALuv8i8 1608| 2.24k| UINT64_C(4088398400), // VPADDLsv16i8 1609| 2.24k| UINT64_C(4088922624), // VPADDLsv2i32 1610| 2.24k| UINT64_C(4088660480), // VPADDLsv4i16 1611| 2.24k| UINT64_C(4088922688), // VPADDLsv4i32 1612| 2.24k| UINT64_C(4088660544), // VPADDLsv8i16 1613| 2.24k| UINT64_C(4088398336), // VPADDLsv8i8 1614| 2.24k| UINT64_C(4088398528), // VPADDLuv16i8 1615| 2.24k| UINT64_C(4088922752), // VPADDLuv2i32 1616| 2.24k| UINT64_C(4088660608), // VPADDLuv4i16 1617| 2.24k| UINT64_C(4088922816), // VPADDLuv4i32 1618| 2.24k| UINT64_C(4088660672), // VPADDLuv8i16 1619| 2.24k| UINT64_C(4088398464), // VPADDLuv8i8 1620| 2.24k| UINT64_C(4076866816), // VPADDf 1621| 2.24k| UINT64_C(4077915392), // VPADDh 1622| 2.24k| UINT64_C(4061137680), // VPADDi16 1623| 2.24k| UINT64_C(4062186256), // VPADDi32 1624| 2.24k| UINT64_C(4060089104), // VPADDi8 1625| 2.24k| UINT64_C(4076867328), // VPMAXf 1626| 2.24k| UINT64_C(4077915904), // VPMAXh 1627| 2.24k| UINT64_C(4061137408), // VPMAXs16 1628| 2.24k| UINT64_C(4062185984), // VPMAXs32 1629| 2.24k| UINT64_C(4060088832), // VPMAXs8 1630| 2.24k| UINT64_C(4077914624), // VPMAXu16 1631| 2.24k| UINT64_C(4078963200), // VPMAXu32 1632| 2.24k| UINT64_C(4076866048), // VPMAXu8 1633| 2.24k| UINT64_C(4078964480), // VPMINf 1634| 2.24k| UINT64_C(4080013056), // VPMINh 1635| 2.24k| UINT64_C(4061137424), // VPMINs16 1636| 2.24k| UINT64_C(4062186000), // VPMINs32 1637| 2.24k| UINT64_C(4060088848), // VPMINs8 1638| 2.24k| UINT64_C(4077914640), // VPMINu16 1639| 2.24k| UINT64_C(4078963216), // VPMINu32 1640| 2.24k| UINT64_C(4076866064), // VPMINu8 1641| 2.24k| UINT64_C(4088399680), // VQABSv16i8 1642| 2.24k| UINT64_C(4088923904), // VQABSv2i32 1643| 2.24k| UINT64_C(4088661760), // VQABSv4i16 1644| 2.24k| UINT64_C(4088923968), // VQABSv4i32 1645| 2.24k| UINT64_C(4088661824), // VQABSv8i16 1646| 2.24k| UINT64_C(4088399616), // VQABSv8i8 1647| 2.24k| UINT64_C(4060086352), // VQADDsv16i8 1648| 2.24k| UINT64_C(4063232016), // VQADDsv1i64 1649| 2.24k| UINT64_C(4062183440), // VQADDsv2i32 1650| 2.24k| UINT64_C(4063232080), // VQADDsv2i64 1651| 2.24k| UINT64_C(4061134864), // VQADDsv4i16 1652| 2.24k| UINT64_C(4062183504), // VQADDsv4i32 1653| 2.24k| UINT64_C(4061134928), // VQADDsv8i16 1654| 2.24k| UINT64_C(4060086288), // VQADDsv8i8 1655| 2.24k| UINT64_C(4076863568), // VQADDuv16i8 1656| 2.24k| UINT64_C(4080009232), // VQADDuv1i64 1657| 2.24k| UINT64_C(4078960656), // VQADDuv2i32 1658| 2.24k| UINT64_C(4080009296), // VQADDuv2i64 1659| 2.24k| UINT64_C(4077912080), // VQADDuv4i16 1660| 2.24k| UINT64_C(4078960720), // VQADDuv4i32 1661| 2.24k| UINT64_C(4077912144), // VQADDuv8i16 1662| 2.24k| UINT64_C(4076863504), // VQADDuv8i8 1663| 2.24k| UINT64_C(4070572864), // VQDMLALslv2i32 1664| 2.24k| UINT64_C(4069524288), // VQDMLALslv4i16 1665| 2.24k| UINT64_C(4070574336), // VQDMLALv2i64 1666| 2.24k| UINT64_C(4069525760), // VQDMLALv4i32 1667| 2.24k| UINT64_C(4070573888), // VQDMLSLslv2i32 1668| 2.24k| UINT64_C(4069525312), // VQDMLSLslv4i16 1669| 2.24k| UINT64_C(4070574848), // VQDMLSLv2i64 1670| 2.24k| UINT64_C(4069526272), // VQDMLSLv4i32 1671| 2.24k| UINT64_C(4070575168), // VQDMULHslv2i32 1672| 2.24k| UINT64_C(4069526592), // VQDMULHslv4i16 1673| 2.24k| UINT64_C(4087352384), // VQDMULHslv4i32 1674| 2.24k| UINT64_C(4086303808), // VQDMULHslv8i16 1675| 2.24k| UINT64_C(4062186240), // VQDMULHv2i32 1676| 2.24k| UINT64_C(4061137664), // VQDMULHv4i16 1677| 2.24k| UINT64_C(4062186304), // VQDMULHv4i32 1678| 2.24k| UINT64_C(4061137728), // VQDMULHv8i16 1679| 2.24k| UINT64_C(4070574912), // VQDMULLslv2i32 1680| 2.24k| UINT64_C(4069526336), // VQDMULLslv4i16 1681| 2.24k| UINT64_C(4070575360), // VQDMULLv2i64 1682| 2.24k| UINT64_C(4069526784), // VQDMULLv4i32 1683| 2.24k| UINT64_C(4089053760), // VQMOVNsuv2i32 1684| 2.24k| UINT64_C(4088791616), // VQMOVNsuv4i16 1685| 2.24k| UINT64_C(4088529472), // VQMOVNsuv8i8 1686| 2.24k| UINT64_C(4089053824), // VQMOVNsv2i32 1687| 2.24k| UINT64_C(4088791680), // VQMOVNsv4i16 1688| 2.24k| UINT64_C(4088529536), // VQMOVNsv8i8 1689| 2.24k| UINT64_C(4089053888), // VQMOVNuv2i32 1690| 2.24k| UINT64_C(4088791744), // VQMOVNuv4i16 1691| 2.24k| UINT64_C(4088529600), // VQMOVNuv8i8 1692| 2.24k| UINT64_C(4088399808), // VQNEGv16i8 1693| 2.24k| UINT64_C(4088924032), // VQNEGv2i32 1694| 2.24k| UINT64_C(4088661888), // VQNEGv4i16 1695| 2.24k| UINT64_C(4088924096), // VQNEGv4i32 1696| 2.24k| UINT64_C(4088661952), // VQNEGv8i16 1697| 2.24k| UINT64_C(4088399744), // VQNEGv8i8 1698| 2.24k| UINT64_C(4070575680), // VQRDMLAHslv2i32 1699| 2.24k| UINT64_C(4069527104), // VQRDMLAHslv4i16 1700| 2.24k| UINT64_C(4087352896), // VQRDMLAHslv4i32 1701| 2.24k| UINT64_C(4086304320), // VQRDMLAHslv8i16 1702| 2.24k| UINT64_C(4078963472), // VQRDMLAHv2i32 1703| 2.24k| UINT64_C(4077914896), // VQRDMLAHv4i16 1704| 2.24k| UINT64_C(4078963536), // VQRDMLAHv4i32 1705| 2.24k| UINT64_C(4077914960), // VQRDMLAHv8i16 1706| 2.24k| UINT64_C(4070575936), // VQRDMLSHslv2i32 1707| 2.24k| UINT64_C(4069527360), // VQRDMLSHslv4i16 1708| 2.24k| UINT64_C(4087353152), // VQRDMLSHslv4i32 1709| 2.24k| UINT64_C(4086304576), // VQRDMLSHslv8i16 1710| 2.24k| UINT64_C(4078963728), // VQRDMLSHv2i32 1711| 2.24k| UINT64_C(4077915152), // VQRDMLSHv4i16 1712| 2.24k| UINT64_C(4078963792), // VQRDMLSHv4i32 1713| 2.24k| UINT64_C(4077915216), // VQRDMLSHv8i16 1714| 2.24k| UINT64_C(4070575424), // VQRDMULHslv2i32 1715| 2.24k| UINT64_C(4069526848), // VQRDMULHslv4i16 1716| 2.24k| UINT64_C(4087352640), // VQRDMULHslv4i32 1717| 2.24k| UINT64_C(4086304064), // VQRDMULHslv8i16 1718| 2.24k| UINT64_C(4078963456), // VQRDMULHv2i32 1719| 2.24k| UINT64_C(4077914880), // VQRDMULHv4i16 1720| 2.24k| UINT64_C(4078963520), // VQRDMULHv4i32 1721| 2.24k| UINT64_C(4077914944), // VQRDMULHv8i16 1722| 2.24k| UINT64_C(4060087632), // VQRSHLsv16i8 1723| 2.24k| UINT64_C(4063233296), // VQRSHLsv1i64 1724| 2.24k| UINT64_C(4062184720), // VQRSHLsv2i32 1725| 2.24k| UINT64_C(4063233360), // VQRSHLsv2i64 1726| 2.24k| UINT64_C(4061136144), // VQRSHLsv4i16 1727| 2.24k| UINT64_C(4062184784), // VQRSHLsv4i32 1728| 2.24k| UINT64_C(4061136208), // VQRSHLsv8i16 1729| 2.24k| UINT64_C(4060087568), // VQRSHLsv8i8 1730| 2.24k| UINT64_C(4076864848), // VQRSHLuv16i8 1731| 2.24k| UINT64_C(4080010512), // VQRSHLuv1i64 1732| 2.24k| UINT64_C(4078961936), // VQRSHLuv2i32 1733| 2.24k| UINT64_C(4080010576), // VQRSHLuv2i64 1734| 2.24k| UINT64_C(4077913360), // VQRSHLuv4i16 1735| 2.24k| UINT64_C(4078962000), // VQRSHLuv4i32 1736| 2.24k| UINT64_C(4077913424), // VQRSHLuv8i16 1737| 2.24k| UINT64_C(4076864784), // VQRSHLuv8i8 1738| 2.24k| UINT64_C(4070574416), // VQRSHRNsv2i32 1739| 2.24k| UINT64_C(4069525840), // VQRSHRNsv4i16 1740| 2.24k| UINT64_C(4069001552), // VQRSHRNsv8i8 1741| 2.24k| UINT64_C(4087351632), // VQRSHRNuv2i32 1742| 2.24k| UINT64_C(4086303056), // VQRSHRNuv4i16 1743| 2.24k| UINT64_C(4085778768), // VQRSHRNuv8i8 1744| 2.24k| UINT64_C(4087351376), // VQRSHRUNv2i32 1745| 2.24k| UINT64_C(4086302800), // VQRSHRUNv4i16 1746| 2.24k| UINT64_C(4085778512), // VQRSHRUNv8i8 1747| 2.24k| UINT64_C(4069001040), // VQSHLsiv16i8 1748| 2.24k| UINT64_C(4068476816), // VQSHLsiv1i64 1749| 2.24k| UINT64_C(4070573840), // VQSHLsiv2i32 1750| 2.24k| UINT64_C(4068476880), // VQSHLsiv2i64 1751| 2.24k| UINT64_C(4069525264), // VQSHLsiv4i16 1752| 2.24k| UINT64_C(4070573904), // VQSHLsiv4i32 1753| 2.24k| UINT64_C(4069525328), // VQSHLsiv8i16 1754| 2.24k| UINT64_C(4069000976), // VQSHLsiv8i8 1755| 2.24k| UINT64_C(4085778000), // VQSHLsuv16i8 1756| 2.24k| UINT64_C(4085253776), // VQSHLsuv1i64 1757| 2.24k| UINT64_C(4087350800), // VQSHLsuv2i32 1758| 2.24k| UINT64_C(4085253840), // VQSHLsuv2i64 1759| 2.24k| UINT64_C(4086302224), // VQSHLsuv4i16 1760| 2.24k| UINT64_C(4087350864), // VQSHLsuv4i32 1761| 2.24k| UINT64_C(4086302288), // VQSHLsuv8i16 1762| 2.24k| UINT64_C(4085777936), // VQSHLsuv8i8 1763| 2.24k| UINT64_C(4060087376), // VQSHLsv16i8 1764| 2.24k| UINT64_C(4063233040), // VQSHLsv1i64 1765| 2.24k| UINT64_C(4062184464), // VQSHLsv2i32 1766| 2.24k| UINT64_C(4063233104), // VQSHLsv2i64 1767| 2.24k| UINT64_C(4061135888), // VQSHLsv4i16 1768| 2.24k| UINT64_C(4062184528), // VQSHLsv4i32 1769| 2.24k| UINT64_C(4061135952), // VQSHLsv8i16 1770| 2.24k| UINT64_C(4060087312), // VQSHLsv8i8 1771| 2.24k| UINT64_C(4085778256), // VQSHLuiv16i8 1772| 2.24k| UINT64_C(4085254032), // VQSHLuiv1i64 1773| 2.24k| UINT64_C(4087351056), // VQSHLuiv2i32 1774| 2.24k| UINT64_C(4085254096), // VQSHLuiv2i64 1775| 2.24k| UINT64_C(4086302480), // VQSHLuiv4i16 1776| 2.24k| UINT64_C(4087351120), // VQSHLuiv4i32 1777| 2.24k| UINT64_C(4086302544), // VQSHLuiv8i16 1778| 2.24k| UINT64_C(4085778192), // VQSHLuiv8i8 1779| 2.24k| UINT64_C(4076864592), // VQSHLuv16i8 1780| 2.24k| UINT64_C(4080010256), // VQSHLuv1i64 1781| 2.24k| UINT64_C(4078961680), // VQSHLuv2i32 1782| 2.24k| UINT64_C(4080010320), // VQSHLuv2i64 1783| 2.24k| UINT64_C(4077913104), // VQSHLuv4i16 1784| 2.24k| UINT64_C(4078961744), // VQSHLuv4i32 1785| 2.24k| UINT64_C(4077913168), // VQSHLuv8i16 1786| 2.24k| UINT64_C(4076864528), // VQSHLuv8i8 1787| 2.24k| UINT64_C(4070574352), // VQSHRNsv2i32 1788| 2.24k| UINT64_C(4069525776), // VQSHRNsv4i16 1789| 2.24k| UINT64_C(4069001488), // VQSHRNsv8i8 1790| 2.24k| UINT64_C(4087351568), // VQSHRNuv2i32 1791| 2.24k| UINT64_C(4086302992), // VQSHRNuv4i16 1792| 2.24k| UINT64_C(4085778704), // VQSHRNuv8i8 1793| 2.24k| UINT64_C(4087351312), // VQSHRUNv2i32 1794| 2.24k| UINT64_C(4086302736), // VQSHRUNv4i16 1795| 2.24k| UINT64_C(4085778448), // VQSHRUNv8i8 1796| 2.24k| UINT64_C(4060086864), // VQSUBsv16i8 1797| 2.24k| UINT64_C(4063232528), // VQSUBsv1i64 1798| 2.24k| UINT64_C(4062183952), // VQSUBsv2i32 1799| 2.24k| UINT64_C(4063232592), // VQSUBsv2i64 1800| 2.24k| UINT64_C(4061135376), // VQSUBsv4i16 1801| 2.24k| UINT64_C(4062184016), // VQSUBsv4i32 1802| 2.24k| UINT64_C(4061135440), // VQSUBsv8i16 1803| 2.24k| UINT64_C(4060086800), // VQSUBsv8i8 1804| 2.24k| UINT64_C(4076864080), // VQSUBuv16i8 1805| 2.24k| UINT64_C(4080009744), // VQSUBuv1i64 1806| 2.24k| UINT64_C(4078961168), // VQSUBuv2i32 1807| 2.24k| UINT64_C(4080009808), // VQSUBuv2i64 1808| 2.24k| UINT64_C(4077912592), // VQSUBuv4i16 1809| 2.24k| UINT64_C(4078961232), // VQSUBuv4i32 1810| 2.24k| UINT64_C(4077912656), // VQSUBuv8i16 1811| 2.24k| UINT64_C(4076864016), // VQSUBuv8i8 1812| 2.24k| UINT64_C(4087350272), // VRADDHNv2i32 1813| 2.24k| UINT64_C(4086301696), // VRADDHNv4i16 1814| 2.24k| UINT64_C(4085253120), // VRADDHNv8i8 1815| 2.24k| UINT64_C(4089119744), // VRECPEd 1816| 2.24k| UINT64_C(4089120000), // VRECPEfd 1817| 2.24k| UINT64_C(4089120064), // VRECPEfq 1818| 2.24k| UINT64_C(4088857856), // VRECPEhd 1819| 2.24k| UINT64_C(4088857920), // VRECPEhq 1820| 2.24k| UINT64_C(4089119808), // VRECPEq 1821| 2.24k| UINT64_C(4060090128), // VRECPSfd 1822| 2.24k| UINT64_C(4060090192), // VRECPSfq 1823| 2.24k| UINT64_C(4061138704), // VRECPShd 1824| 2.24k| UINT64_C(4061138768), // VRECPShq 1825| 2.24k| UINT64_C(4088398080), // VREV16d8 1826| 2.24k| UINT64_C(4088398144), // VREV16q8 1827| 2.24k| UINT64_C(4088660096), // VREV32d16 1828| 2.24k| UINT64_C(4088397952), // VREV32d8 1829| 2.24k| UINT64_C(4088660160), // VREV32q16 1830| 2.24k| UINT64_C(4088398016), // VREV32q8 1831| 2.24k| UINT64_C(4088659968), // VREV64d16 1832| 2.24k| UINT64_C(4088922112), // VREV64d32 1833| 2.24k| UINT64_C(4088397824), // VREV64d8 1834| 2.24k| UINT64_C(4088660032), // VREV64q16 1835| 2.24k| UINT64_C(4088922176), // VREV64q32 1836| 2.24k| UINT64_C(4088397888), // VREV64q8 1837| 2.24k| UINT64_C(4060086592), // VRHADDsv16i8 1838| 2.24k| UINT64_C(4062183680), // VRHADDsv2i32 1839| 2.24k| UINT64_C(4061135104), // VRHADDsv4i16 1840| 2.24k| UINT64_C(4062183744), // VRHADDsv4i32 1841| 2.24k| UINT64_C(4061135168), // VRHADDsv8i16 1842| 2.24k| UINT64_C(4060086528), // VRHADDsv8i8 1843| 2.24k| UINT64_C(4076863808), // VRHADDuv16i8 1844| 2.24k| UINT64_C(4078960896), // VRHADDuv2i32 1845| 2.24k| UINT64_C(4077912320), // VRHADDuv4i16 1846| 2.24k| UINT64_C(4078960960), // VRHADDuv4i32 1847| 2.24k| UINT64_C(4077912384), // VRHADDuv8i16 1848| 2.24k| UINT64_C(4076863744), // VRHADDuv8i8 1849| 2.24k| UINT64_C(4273474368), // VRINTAD 1850| 2.24k| UINT64_C(4273473856), // VRINTAH 1851| 2.24k| UINT64_C(4089054464), // VRINTANDf 1852| 2.24k| UINT64_C(4088792320), // VRINTANDh 1853| 2.24k| UINT64_C(4089054528), // VRINTANQf 1854| 2.24k| UINT64_C(4088792384), // VRINTANQh 1855| 2.24k| UINT64_C(4273474112), // VRINTAS 1856| 2.24k| UINT64_C(4273670976), // VRINTMD 1857| 2.24k| UINT64_C(4273670464), // VRINTMH 1858| 2.24k| UINT64_C(4089054848), // VRINTMNDf 1859| 2.24k| UINT64_C(4088792704), // VRINTMNDh 1860| 2.24k| UINT64_C(4089054912), // VRINTMNQf 1861| 2.24k| UINT64_C(4088792768), // VRINTMNQh 1862| 2.24k| UINT64_C(4273670720), // VRINTMS 1863| 2.24k| UINT64_C(4273539904), // VRINTND 1864| 2.24k| UINT64_C(4273539392), // VRINTNH 1865| 2.24k| UINT64_C(4089054208), // VRINTNNDf 1866| 2.24k| UINT64_C(4088792064), // VRINTNNDh 1867| 2.24k| UINT64_C(4089054272), // VRINTNNQf 1868| 2.24k| UINT64_C(4088792128), // VRINTNNQh 1869| 2.24k| UINT64_C(4273539648), // VRINTNS 1870| 2.24k| UINT64_C(4273605440), // VRINTPD 1871| 2.24k| UINT64_C(4273604928), // VRINTPH 1872| 2.24k| UINT64_C(4089055104), // VRINTPNDf 1873| 2.24k| UINT64_C(4088792960), // VRINTPNDh 1874| 2.24k| UINT64_C(4089055168), // VRINTPNQf 1875| 2.24k| UINT64_C(4088793024), // VRINTPNQh 1876| 2.24k| UINT64_C(4273605184), // VRINTPS 1877| 2.24k| UINT64_C(246811456), // VRINTRD 1878| 2.24k| UINT64_C(246810944), // VRINTRH 1879| 2.24k| UINT64_C(246811200), // VRINTRS 1880| 2.24k| UINT64_C(246876992), // VRINTXD 1881| 2.24k| UINT64_C(246876480), // VRINTXH 1882| 2.24k| UINT64_C(4089054336), // VRINTXNDf 1883| 2.24k| UINT64_C(4088792192), // VRINTXNDh 1884| 2.24k| UINT64_C(4089054400), // VRINTXNQf 1885| 2.24k| UINT64_C(4088792256), // VRINTXNQh 1886| 2.24k| UINT64_C(246876736), // VRINTXS 1887| 2.24k| UINT64_C(246811584), // VRINTZD 1888| 2.24k| UINT64_C(246811072), // VRINTZH 1889| 2.24k| UINT64_C(4089054592), // VRINTZNDf 1890| 2.24k| UINT64_C(4088792448), // VRINTZNDh 1891| 2.24k| UINT64_C(4089054656), // VRINTZNQf 1892| 2.24k| UINT64_C(4088792512), // VRINTZNQh 1893| 2.24k| UINT64_C(246811328), // VRINTZS 1894| 2.24k| UINT64_C(4060087616), // VRSHLsv16i8 1895| 2.24k| UINT64_C(4063233280), // VRSHLsv1i64 1896| 2.24k| UINT64_C(4062184704), // VRSHLsv2i32 1897| 2.24k| UINT64_C(4063233344), // VRSHLsv2i64 1898| 2.24k| UINT64_C(4061136128), // VRSHLsv4i16 1899| 2.24k| UINT64_C(4062184768), // VRSHLsv4i32 1900| 2.24k| UINT64_C(4061136192), // VRSHLsv8i16 1901| 2.24k| UINT64_C(4060087552), // VRSHLsv8i8 1902| 2.24k| UINT64_C(4076864832), // VRSHLuv16i8 1903| 2.24k| UINT64_C(4080010496), // VRSHLuv1i64 1904| 2.24k| UINT64_C(4078961920), // VRSHLuv2i32 1905| 2.24k| UINT64_C(4080010560), // VRSHLuv2i64 1906| 2.24k| UINT64_C(4077913344), // VRSHLuv4i16 1907| 2.24k| UINT64_C(4078961984), // VRSHLuv4i32 1908| 2.24k| UINT64_C(4077913408), // VRSHLuv8i16 1909| 2.24k| UINT64_C(4076864768), // VRSHLuv8i8 1910| 2.24k| UINT64_C(4070574160), // VRSHRNv2i32 1911| 2.24k| UINT64_C(4069525584), // VRSHRNv4i16 1912| 2.24k| UINT64_C(4069001296), // VRSHRNv8i8 1913| 2.24k| UINT64_C(4068999760), // VRSHRsv16i8 1914| 2.24k| UINT64_C(4068475536), // VRSHRsv1i64 1915| 2.24k| UINT64_C(4070572560), // VRSHRsv2i32 1916| 2.24k| UINT64_C(4068475600), // VRSHRsv2i64 1917| 2.24k| UINT64_C(4069523984), // VRSHRsv4i16 1918| 2.24k| UINT64_C(4070572624), // VRSHRsv4i32 1919| 2.24k| UINT64_C(4069524048), // VRSHRsv8i16 1920| 2.24k| UINT64_C(4068999696), // VRSHRsv8i8 1921| 2.24k| UINT64_C(4085776976), // VRSHRuv16i8 1922| 2.24k| UINT64_C(4085252752), // VRSHRuv1i64 1923| 2.24k| UINT64_C(4087349776), // VRSHRuv2i32 1924| 2.24k| UINT64_C(4085252816), // VRSHRuv2i64 1925| 2.24k| UINT64_C(4086301200), // VRSHRuv4i16 1926| 2.24k| UINT64_C(4087349840), // VRSHRuv4i32 1927| 2.24k| UINT64_C(4086301264), // VRSHRuv8i16 1928| 2.24k| UINT64_C(4085776912), // VRSHRuv8i8 1929| 2.24k| UINT64_C(4089119872), // VRSQRTEd 1930| 2.24k| UINT64_C(4089120128), // VRSQRTEfd 1931| 2.24k| UINT64_C(4089120192), // VRSQRTEfq 1932| 2.24k| UINT64_C(4088857984), // VRSQRTEhd 1933| 2.24k| UINT64_C(4088858048), // VRSQRTEhq 1934| 2.24k| UINT64_C(4089119936), // VRSQRTEq 1935| 2.24k| UINT64_C(4062187280), // VRSQRTSfd 1936| 2.24k| UINT64_C(4062187344), // VRSQRTSfq 1937| 2.24k| UINT64_C(4063235856), // VRSQRTShd 1938| 2.24k| UINT64_C(4063235920), // VRSQRTShq 1939| 2.24k| UINT64_C(4069000016), // VRSRAsv16i8 1940| 2.24k| UINT64_C(4068475792), // VRSRAsv1i64 1941| 2.24k| UINT64_C(4070572816), // VRSRAsv2i32 1942| 2.24k| UINT64_C(4068475856), // VRSRAsv2i64 1943| 2.24k| UINT64_C(4069524240), // VRSRAsv4i16 1944| 2.24k| UINT64_C(4070572880), // VRSRAsv4i32 1945| 2.24k| UINT64_C(4069524304), // VRSRAsv8i16 1946| 2.24k| UINT64_C(4068999952), // VRSRAsv8i8 1947| 2.24k| UINT64_C(4085777232), // VRSRAuv16i8 1948| 2.24k| UINT64_C(4085253008), // VRSRAuv1i64 1949| 2.24k| UINT64_C(4087350032), // VRSRAuv2i32 1950| 2.24k| UINT64_C(4085253072), // VRSRAuv2i64 1951| 2.24k| UINT64_C(4086301456), // VRSRAuv4i16 1952| 2.24k| UINT64_C(4087350096), // VRSRAuv4i32 1953| 2.24k| UINT64_C(4086301520), // VRSRAuv8i16 1954| 2.24k| UINT64_C(4085777168), // VRSRAuv8i8 1955| 2.24k| UINT64_C(4087350784), // VRSUBHNv2i32 1956| 2.24k| UINT64_C(4086302208), // VRSUBHNv4i16 1957| 2.24k| UINT64_C(4085253632), // VRSUBHNv8i8 1958| 2.24k| UINT64_C(4261415680), // VSELEQD 1959| 2.24k| UINT64_C(4261415168), // VSELEQH 1960| 2.24k| UINT64_C(4261415424), // VSELEQS 1961| 2.24k| UINT64_C(4263512832), // VSELGED 1962| 2.24k| UINT64_C(4263512320), // VSELGEH 1963| 2.24k| UINT64_C(4263512576), // VSELGES 1964| 2.24k| UINT64_C(4264561408), // VSELGTD 1965| 2.24k| UINT64_C(4264560896), // VSELGTH 1966| 2.24k| UINT64_C(4264561152), // VSELGTS 1967| 2.24k| UINT64_C(4262464256), // VSELVSD 1968| 2.24k| UINT64_C(4262463744), // VSELVSH 1969| 2.24k| UINT64_C(4262464000), // VSELVSS 1970| 2.24k| UINT64_C(234883888), // VSETLNi16 1971| 2.24k| UINT64_C(234883856), // VSETLNi32 1972| 2.24k| UINT64_C(239078160), // VSETLNi8 1973| 2.24k| UINT64_C(4088791808), // VSHLLi16 1974| 2.24k| UINT64_C(4089053952), // VSHLLi32 1975| 2.24k| UINT64_C(4088529664), // VSHLLi8 1976| 2.24k| UINT64_C(4070574608), // VSHLLsv2i64 1977| 2.24k| UINT64_C(4069526032), // VSHLLsv4i32 1978| 2.24k| UINT64_C(4069001744), // VSHLLsv8i16 1979| 2.24k| UINT64_C(4087351824), // VSHLLuv2i64 1980| 2.24k| UINT64_C(4086303248), // VSHLLuv4i32 1981| 2.24k| UINT64_C(4085778960), // VSHLLuv8i16 1982| 2.24k| UINT64_C(4069000528), // VSHLiv16i8 1983| 2.24k| UINT64_C(4068476304), // VSHLiv1i64 1984| 2.24k| UINT64_C(4070573328), // VSHLiv2i32 1985| 2.24k| UINT64_C(4068476368), // VSHLiv2i64 1986| 2.24k| UINT64_C(4069524752), // VSHLiv4i16 1987| 2.24k| UINT64_C(4070573392), // VSHLiv4i32 1988| 2.24k| UINT64_C(4069524816), // VSHLiv8i16 1989| 2.24k| UINT64_C(4069000464), // VSHLiv8i8 1990| 2.24k| UINT64_C(4060087360), // VSHLsv16i8 1991| 2.24k| UINT64_C(4063233024), // VSHLsv1i64 1992| 2.24k| UINT64_C(4062184448), // VSHLsv2i32 1993| 2.24k| UINT64_C(4063233088), // VSHLsv2i64 1994| 2.24k| UINT64_C(4061135872), // VSHLsv4i16 1995| 2.24k| UINT64_C(4062184512), // VSHLsv4i32 1996| 2.24k| UINT64_C(4061135936), // VSHLsv8i16 1997| 2.24k| UINT64_C(4060087296), // VSHLsv8i8 1998| 2.24k| UINT64_C(4076864576), // VSHLuv16i8 1999| 2.24k| UINT64_C(4080010240), // VSHLuv1i64 2000| 2.24k| UINT64_C(4078961664), // VSHLuv2i32 2001| 2.24k| UINT64_C(4080010304), // VSHLuv2i64 2002| 2.24k| UINT64_C(4077913088), // VSHLuv4i16 2003| 2.24k| UINT64_C(4078961728), // VSHLuv4i32 2004| 2.24k| UINT64_C(4077913152), // VSHLuv8i16 2005| 2.24k| UINT64_C(4076864512), // VSHLuv8i8 2006| 2.24k| UINT64_C(4070574096), // VSHRNv2i32 2007| 2.24k| UINT64_C(4069525520), // VSHRNv4i16 2008| 2.24k| UINT64_C(4069001232), // VSHRNv8i8 2009| 2.24k| UINT64_C(4068999248), // VSHRsv16i8 2010| 2.24k| UINT64_C(4068475024), // VSHRsv1i64 2011| 2.24k| UINT64_C(4070572048), // VSHRsv2i32 2012| 2.24k| UINT64_C(4068475088), // VSHRsv2i64 2013| 2.24k| UINT64_C(4069523472), // VSHRsv4i16 2014| 2.24k| UINT64_C(4070572112), // VSHRsv4i32 2015| 2.24k| UINT64_C(4069523536), // VSHRsv8i16 2016| 2.24k| UINT64_C(4068999184), // VSHRsv8i8 2017| 2.24k| UINT64_C(4085776464), // VSHRuv16i8 2018| 2.24k| UINT64_C(4085252240), // VSHRuv1i64 2019| 2.24k| UINT64_C(4087349264), // VSHRuv2i32 2020| 2.24k| UINT64_C(4085252304), // VSHRuv2i64 2021| 2.24k| UINT64_C(4086300688), // VSHRuv4i16 2022| 2.24k| UINT64_C(4087349328), // VSHRuv4i32 2023| 2.24k| UINT64_C(4086300752), // VSHRuv8i16 2024| 2.24k| UINT64_C(4085776400), // VSHRuv8i8 2025| 2.24k| UINT64_C(247073600), // VSHTOD 2026| 2.24k| UINT64_C(247073088), // VSHTOH 2027| 2.24k| UINT64_C(247073344), // VSHTOS 2028| 2.24k| UINT64_C(246942656), // VSITOD 2029| 2.24k| UINT64_C(246942144), // VSITOH 2030| 2.24k| UINT64_C(246942400), // VSITOS 2031| 2.24k| UINT64_C(4085777744), // VSLIv16i8 2032| 2.24k| UINT64_C(4085253520), // VSLIv1i64 2033| 2.24k| UINT64_C(4087350544), // VSLIv2i32 2034| 2.24k| UINT64_C(4085253584), // VSLIv2i64 2035| 2.24k| UINT64_C(4086301968), // VSLIv4i16 2036| 2.24k| UINT64_C(4087350608), // VSLIv4i32 2037| 2.24k| UINT64_C(4086302032), // VSLIv8i16 2038| 2.24k| UINT64_C(4085777680), // VSLIv8i8 2039| 2.24k| UINT64_C(247073728), // VSLTOD 2040| 2.24k| UINT64_C(247073216), // VSLTOH 2041| 2.24k| UINT64_C(247073472), // VSLTOS 2042| 2.24k| UINT64_C(246483904), // VSQRTD 2043| 2.24k| UINT64_C(246483392), // VSQRTH 2044| 2.24k| UINT64_C(246483648), // VSQRTS 2045| 2.24k| UINT64_C(4068999504), // VSRAsv16i8 2046| 2.24k| UINT64_C(4068475280), // VSRAsv1i64 2047| 2.24k| UINT64_C(4070572304), // VSRAsv2i32 2048| 2.24k| UINT64_C(4068475344), // VSRAsv2i64 2049| 2.24k| UINT64_C(4069523728), // VSRAsv4i16 2050| 2.24k| UINT64_C(4070572368), // VSRAsv4i32 2051| 2.24k| UINT64_C(4069523792), // VSRAsv8i16 2052| 2.24k| UINT64_C(4068999440), // VSRAsv8i8 2053| 2.24k| UINT64_C(4085776720), // VSRAuv16i8 2054| 2.24k| UINT64_C(4085252496), // VSRAuv1i64 2055| 2.24k| UINT64_C(4087349520), // VSRAuv2i32 2056| 2.24k| UINT64_C(4085252560), // VSRAuv2i64 2057| 2.24k| UINT64_C(4086300944), // VSRAuv4i16 2058| 2.24k| UINT64_C(4087349584), // VSRAuv4i32 2059| 2.24k| UINT64_C(4086301008), // VSRAuv8i16 2060| 2.24k| UINT64_C(4085776656), // VSRAuv8i8 2061| 2.24k| UINT64_C(4085777488), // VSRIv16i8 2062| 2.24k| UINT64_C(4085253264), // VSRIv1i64 2063| 2.24k| UINT64_C(4087350288), // VSRIv2i32 2064| 2.24k| UINT64_C(4085253328), // VSRIv2i64 2065| 2.24k| UINT64_C(4086301712), // VSRIv4i16 2066| 2.24k| UINT64_C(4087350352), // VSRIv4i32 2067| 2.24k| UINT64_C(4086301776), // VSRIv8i16 2068| 2.24k| UINT64_C(4085777424), // VSRIv8i8 2069| 2.24k| UINT64_C(4102030351), // VST1LNd16 2070| 2.24k| UINT64_C(4102030336), // VST1LNd16_UPD 2071| 2.24k| UINT64_C(4102031375), // VST1LNd32 2072| 2.24k| UINT64_C(4102031360), // VST1LNd32_UPD 2073| 2.24k| UINT64_C(4102029327), // VST1LNd8 2074| 2.24k| UINT64_C(4102029312), // VST1LNd8_UPD 2075| 2.24k| UINT64_C(0), 2076| 2.24k| UINT64_C(0), 2077| 2.24k| UINT64_C(0), 2078| 2.24k| UINT64_C(0), 2079| 2.24k| UINT64_C(0), 2080| 2.24k| UINT64_C(0), 2081| 2.24k| UINT64_C(0), 2082| 2.24k| UINT64_C(0), 2083| 2.24k| UINT64_C(0), 2084| 2.24k| UINT64_C(0), // VST1LNq16Pseudo 2085| 2.24k| UINT64_C(0), // VST1LNq16Pseudo_UPD 2086| 2.24k| UINT64_C(0), // VST1LNq32Pseudo 2087| 2.24k| UINT64_C(0), // VST1LNq32Pseudo_UPD 2088| 2.24k| UINT64_C(0), // VST1LNq8Pseudo 2089| 2.24k| UINT64_C(0), // VST1LNq8Pseudo_UPD 2090| 2.24k| UINT64_C(4093642575), // VST1d16 2091| 2.24k| UINT64_C(4093641295), // VST1d16Q 2092| 2.24k| UINT64_C(4093641293), // VST1d16Qwb_fixed 2093| 2.24k| UINT64_C(4093641280), // VST1d16Qwb_register 2094| 2.24k| UINT64_C(4093642319), // VST1d16T 2095| 2.24k| UINT64_C(4093642317), // VST1d16Twb_fixed 2096| 2.24k| UINT64_C(4093642304), // VST1d16Twb_register 2097| 2.24k| UINT64_C(4093642573), // VST1d16wb_fixed 2098| 2.24k| UINT64_C(4093642560), // VST1d16wb_register 2099| 2.24k| UINT64_C(4093642639), // VST1d32 2100| 2.24k| UINT64_C(4093641359), // VST1d32Q 2101| 2.24k| UINT64_C(4093641357), // VST1d32Qwb_fixed 2102| 2.24k| UINT64_C(4093641344), // VST1d32Qwb_register 2103| 2.24k| UINT64_C(4093642383), // VST1d32T 2104| 2.24k| UINT64_C(4093642381), // VST1d32Twb_fixed 2105| 2.24k| UINT64_C(4093642368), // VST1d32Twb_register 2106| 2.24k| UINT64_C(4093642637), // VST1d32wb_fixed 2107| 2.24k| UINT64_C(4093642624), // VST1d32wb_register 2108| 2.24k| UINT64_C(4093642703), // VST1d64 2109| 2.24k| UINT64_C(4093641423), // VST1d64Q 2110| 2.24k| UINT64_C(0), // VST1d64QPseudo 2111| 2.24k| UINT64_C(0), // VST1d64QPseudoWB_fixed 2112| 2.24k| UINT64_C(0), // VST1d64QPseudoWB_register 2113| 2.24k| UINT64_C(4093641421), // VST1d64Qwb_fixed 2114| 2.24k| UINT64_C(4093641408), // VST1d64Qwb_register 2115| 2.24k| UINT64_C(4093642447), // VST1d64T 2116| 2.24k| UINT64_C(0), // VST1d64TPseudo 2117| 2.24k| UINT64_C(0), // VST1d64TPseudoWB_fixed 2118| 2.24k| UINT64_C(0), // VST1d64TPseudoWB_register 2119| 2.24k| UINT64_C(4093642445), // VST1d64Twb_fixed 2120| 2.24k| UINT64_C(4093642432), // VST1d64Twb_register 2121| 2.24k| UINT64_C(4093642701), // VST1d64wb_fixed 2122| 2.24k| UINT64_C(4093642688), // VST1d64wb_register 2123| 2.24k| UINT64_C(4093642511), // VST1d8 2124| 2.24k| UINT64_C(4093641231), // VST1d8Q 2125| 2.24k| UINT64_C(4093641229), // VST1d8Qwb_fixed 2126| 2.24k| UINT64_C(4093641216), // VST1d8Qwb_register 2127| 2.24k| UINT64_C(4093642255), // VST1d8T 2128| 2.24k| UINT64_C(4093642253), // VST1d8Twb_fixed 2129| 2.24k| UINT64_C(4093642240), // VST1d8Twb_register 2130| 2.24k| UINT64_C(4093642509), // VST1d8wb_fixed 2131| 2.24k| UINT64_C(4093642496), // VST1d8wb_register 2132| 2.24k| UINT64_C(4093643343), // VST1q16 2133| 2.24k| UINT64_C(4093643341), // VST1q16wb_fixed 2134| 2.24k| UINT64_C(4093643328), // VST1q16wb_register 2135| 2.24k| UINT64_C(4093643407), // VST1q32 2136| 2.24k| UINT64_C(4093643405), // VST1q32wb_fixed 2137| 2.24k| UINT64_C(4093643392), // VST1q32wb_register 2138| 2.24k| UINT64_C(4093643471), // VST1q64 2139| 2.24k| UINT64_C(4093643469), // VST1q64wb_fixed 2140| 2.24k| UINT64_C(4093643456), // VST1q64wb_register 2141| 2.24k| UINT64_C(4093643279), // VST1q8 2142| 2.24k| UINT64_C(4093643277), // VST1q8wb_fixed 2143| 2.24k| UINT64_C(4093643264), // VST1q8wb_register 2144| 2.24k| UINT64_C(4102030607), // VST2LNd16 2145| 2.24k| UINT64_C(0), // VST2LNd16Pseudo 2146| 2.24k| UINT64_C(0), // VST2LNd16Pseudo_UPD 2147| 2.24k| UINT64_C(4102030592), // VST2LNd16_UPD 2148| 2.24k| UINT64_C(4102031631), // VST2LNd32 2149| 2.24k| UINT64_C(0), // VST2LNd32Pseudo 2150| 2.24k| UINT64_C(0), // VST2LNd32Pseudo_UPD 2151| 2.24k| UINT64_C(4102031616), // VST2LNd32_UPD 2152| 2.24k| UINT64_C(4102029583), // VST2LNd8 2153| 2.24k| UINT64_C(0), // VST2LNd8Pseudo 2154| 2.24k| UINT64_C(0), // VST2LNd8Pseudo_UPD 2155| 2.24k| UINT64_C(4102029568), // VST2LNd8_UPD 2156| 2.24k| UINT64_C(0), 2157| 2.24k| UINT64_C(0), 2158| 2.24k| UINT64_C(0), 2159| 2.24k| UINT64_C(0), 2160| 2.24k| UINT64_C(0), 2161| 2.24k| UINT64_C(0), 2162| 2.24k| UINT64_C(0), 2163| 2.24k| UINT64_C(0), 2164| 2.24k| UINT64_C(0), 2165| 2.24k| UINT64_C(4102030639), // VST2LNq16 2166| 2.24k| UINT64_C(0), // VST2LNq16Pseudo 2167| 2.24k| UINT64_C(0), // VST2LNq16Pseudo_UPD 2168| 2.24k| UINT64_C(4102030624), // VST2LNq16_UPD 2169| 2.24k| UINT64_C(4102031695), // VST2LNq32 2170| 2.24k| UINT64_C(0), // VST2LNq32Pseudo 2171| 2.24k| UINT64_C(0), // VST2LNq32Pseudo_UPD 2172| 2.24k| UINT64_C(4102031680), // VST2LNq32_UPD 2173| 2.24k| UINT64_C(0), 2174| 2.24k| UINT64_C(0), 2175| 2.24k| UINT64_C(0), 2176| 2.24k| UINT64_C(0), 2177| 2.24k| UINT64_C(0), 2178| 2.24k| UINT64_C(0), 2179| 2.24k| UINT64_C(4093643087), // VST2b16 2180| 2.24k| UINT64_C(4093643085), // VST2b16wb_fixed 2181| 2.24k| UINT64_C(4093643072), // VST2b16wb_register 2182| 2.24k| UINT64_C(4093643151), // VST2b32 2183| 2.24k| UINT64_C(4093643149), // VST2b32wb_fixed 2184| 2.24k| UINT64_C(4093643136), // VST2b32wb_register 2185| 2.24k| UINT64_C(4093643023), // VST2b8 2186| 2.24k| UINT64_C(4093643021), // VST2b8wb_fixed 2187| 2.24k| UINT64_C(4093643008), // VST2b8wb_register 2188| 2.24k| UINT64_C(4093642831), // VST2d16 2189| 2.24k| UINT64_C(4093642829), // VST2d16wb_fixed 2190| 2.24k| UINT64_C(4093642816), // VST2d16wb_register 2191| 2.24k| UINT64_C(4093642895), // VST2d32 2192| 2.24k| UINT64_C(4093642893), // VST2d32wb_fixed 2193| 2.24k| UINT64_C(4093642880), // VST2d32wb_register 2194| 2.24k| UINT64_C(4093642767), // VST2d8 2195| 2.24k| UINT64_C(4093642765), // VST2d8wb_fixed 2196| 2.24k| UINT64_C(4093642752), // VST2d8wb_register 2197| 2.24k| UINT64_C(4093641551), // VST2q16 2198| 2.24k| UINT64_C(0), // VST2q16Pseudo 2199| 2.24k| UINT64_C(0), // VST2q16PseudoWB_fixed 2200| 2.24k| UINT64_C(0), // VST2q16PseudoWB_register 2201| 2.24k| UINT64_C(4093641549), // VST2q16wb_fixed 2202| 2.24k| UINT64_C(4093641536), // VST2q16wb_register 2203| 2.24k| UINT64_C(4093641615), // VST2q32 2204| 2.24k| UINT64_C(0), // VST2q32Pseudo 2205| 2.24k| UINT64_C(0), // VST2q32PseudoWB_fixed 2206| 2.24k| UINT64_C(0), // VST2q32PseudoWB_register 2207| 2.24k| UINT64_C(4093641613), // VST2q32wb_fixed 2208| 2.24k| UINT64_C(4093641600), // VST2q32wb_register 2209| 2.24k| UINT64_C(4093641487), // VST2q8 2210| 2.24k| UINT64_C(0), // VST2q8Pseudo 2211| 2.24k| UINT64_C(0), // VST2q8PseudoWB_fixed 2212| 2.24k| UINT64_C(0), // VST2q8PseudoWB_register 2213| 2.24k| UINT64_C(4093641485), // VST2q8wb_fixed 2214| 2.24k| UINT64_C(4093641472), // VST2q8wb_register 2215| 2.24k| UINT64_C(4102030863), // VST3LNd16 2216| 2.24k| UINT64_C(0), // VST3LNd16Pseudo 2217| 2.24k| UINT64_C(0), // VST3LNd16Pseudo_UPD 2218| 2.24k| UINT64_C(4102030848), // VST3LNd16_UPD 2219| 2.24k| UINT64_C(4102031887), // VST3LNd32 2220| 2.24k| UINT64_C(0), // VST3LNd32Pseudo 2221| 2.24k| UINT64_C(0), // VST3LNd32Pseudo_UPD 2222| 2.24k| UINT64_C(4102031872), // VST3LNd32_UPD 2223| 2.24k| UINT64_C(4102029839), // VST3LNd8 2224| 2.24k| UINT64_C(0), // VST3LNd8Pseudo 2225| 2.24k| UINT64_C(0), // VST3LNd8Pseudo_UPD 2226| 2.24k| UINT64_C(4102029824), // VST3LNd8_UPD 2227| 2.24k| UINT64_C(0), 2228| 2.24k| UINT64_C(0), 2229| 2.24k| UINT64_C(0), 2230| 2.24k| UINT64_C(0), 2231| 2.24k| UINT64_C(0), 2232| 2.24k| UINT64_C(0), 2233| 2.24k| UINT64_C(0), 2234| 2.24k| UINT64_C(0), 2235| 2.24k| UINT64_C(0), 2236| 2.24k| UINT64_C(4102030895), // VST3LNq16 2237| 2.24k| UINT64_C(0), // VST3LNq16Pseudo 2238| 2.24k| UINT64_C(0), // VST3LNq16Pseudo_UPD 2239| 2.24k| UINT64_C(4102030880), // VST3LNq16_UPD 2240| 2.24k| UINT64_C(4102031951), // VST3LNq32 2241| 2.24k| UINT64_C(0), // VST3LNq32Pseudo 2242| 2.24k| UINT64_C(0), // VST3LNq32Pseudo_UPD 2243| 2.24k| UINT64_C(4102031936), // VST3LNq32_UPD 2244| 2.24k| UINT64_C(0), 2245| 2.24k| UINT64_C(0), 2246| 2.24k| UINT64_C(0), 2247| 2.24k| UINT64_C(0), 2248| 2.24k| UINT64_C(0), 2249| 2.24k| UINT64_C(0), 2250| 2.24k| UINT64_C(4093641807), // VST3d16 2251| 2.24k| UINT64_C(0), // VST3d16Pseudo 2252| 2.24k| UINT64_C(0), // VST3d16Pseudo_UPD 2253| 2.24k| UINT64_C(4093641792), // VST3d16_UPD 2254| 2.24k| UINT64_C(4093641871), // VST3d32 2255| 2.24k| UINT64_C(0), // VST3d32Pseudo 2256| 2.24k| UINT64_C(0), // VST3d32Pseudo_UPD 2257| 2.24k| UINT64_C(4093641856), // VST3d32_UPD 2258| 2.24k| UINT64_C(4093641743), // VST3d8 2259| 2.24k| UINT64_C(0), // VST3d8Pseudo 2260| 2.24k| UINT64_C(0), // VST3d8Pseudo_UPD 2261| 2.24k| UINT64_C(4093641728), // VST3d8_UPD 2262| 2.24k| UINT64_C(0), 2263| 2.24k| UINT64_C(0), 2264| 2.24k| UINT64_C(0), 2265| 2.24k| UINT64_C(0), 2266| 2.24k| UINT64_C(0), 2267| 2.24k| UINT64_C(0), 2268| 2.24k| UINT64_C(0), 2269| 2.24k| UINT64_C(0), 2270| 2.24k| UINT64_C(0), 2271| 2.24k| UINT64_C(4093642063), // VST3q16 2272| 2.24k| UINT64_C(0), // VST3q16Pseudo_UPD 2273| 2.24k| UINT64_C(4093642048), // VST3q16_UPD 2274| 2.24k| UINT64_C(0), // VST3q16oddPseudo 2275| 2.24k| UINT64_C(0), // VST3q16oddPseudo_UPD 2276| 2.24k| UINT64_C(4093642127), // VST3q32 2277| 2.24k| UINT64_C(0), // VST3q32Pseudo_UPD 2278| 2.24k| UINT64_C(4093642112), // VST3q32_UPD 2279| 2.24k| UINT64_C(0), // VST3q32oddPseudo 2280| 2.24k| UINT64_C(0), // VST3q32oddPseudo_UPD 2281| 2.24k| UINT64_C(4093641999), // VST3q8 2282| 2.24k| UINT64_C(0), // VST3q8Pseudo_UPD 2283| 2.24k| UINT64_C(4093641984), // VST3q8_UPD 2284| 2.24k| UINT64_C(0), // VST3q8oddPseudo 2285| 2.24k| UINT64_C(0), // VST3q8oddPseudo_UPD 2286| 2.24k| UINT64_C(0), 2287| 2.24k| UINT64_C(0), 2288| 2.24k| UINT64_C(0), 2289| 2.24k| UINT64_C(0), 2290| 2.24k| UINT64_C(0), 2291| 2.24k| UINT64_C(0), 2292| 2.24k| UINT64_C(0), 2293| 2.24k| UINT64_C(0), 2294| 2.24k| UINT64_C(0), 2295| 2.24k| UINT64_C(4102031119), // VST4LNd16 2296| 2.24k| UINT64_C(0), // VST4LNd16Pseudo 2297| 2.24k| UINT64_C(0), // VST4LNd16Pseudo_UPD 2298| 2.24k| UINT64_C(4102031104), // VST4LNd16_UPD 2299| 2.24k| UINT64_C(4102032143), // VST4LNd32 2300| 2.24k| UINT64_C(0), // VST4LNd32Pseudo 2301| 2.24k| UINT64_C(0), // VST4LNd32Pseudo_UPD 2302| 2.24k| UINT64_C(4102032128), // VST4LNd32_UPD 2303| 2.24k| UINT64_C(4102030095), // VST4LNd8 2304| 2.24k| UINT64_C(0), // VST4LNd8Pseudo 2305| 2.24k| UINT64_C(0), // VST4LNd8Pseudo_UPD 2306| 2.24k| UINT64_C(4102030080), // VST4LNd8_UPD 2307| 2.24k| UINT64_C(0), 2308| 2.24k| UINT64_C(0), 2309| 2.24k| UINT64_C(0), 2310| 2.24k| UINT64_C(0), 2311| 2.24k| UINT64_C(0), 2312| 2.24k| UINT64_C(0), 2313| 2.24k| UINT64_C(0), 2314| 2.24k| UINT64_C(0), 2315| 2.24k| UINT64_C(0), 2316| 2.24k| UINT64_C(4102031151), // VST4LNq16 2317| 2.24k| UINT64_C(0), // VST4LNq16Pseudo 2318| 2.24k| UINT64_C(0), // VST4LNq16Pseudo_UPD 2319| 2.24k| UINT64_C(4102031136), // VST4LNq16_UPD 2320| 2.24k| UINT64_C(4102032207), // VST4LNq32 2321| 2.24k| UINT64_C(0), // VST4LNq32Pseudo 2322| 2.24k| UINT64_C(0), // VST4LNq32Pseudo_UPD 2323| 2.24k| UINT64_C(4102032192), // VST4LNq32_UPD 2324| 2.24k| UINT64_C(0), 2325| 2.24k| UINT64_C(0), 2326| 2.24k| UINT64_C(0), 2327| 2.24k| UINT64_C(0), 2328| 2.24k| UINT64_C(0), 2329| 2.24k| UINT64_C(0), 2330| 2.24k| UINT64_C(4093640783), // VST4d16 2331| 2.24k| UINT64_C(0), // VST4d16Pseudo 2332| 2.24k| UINT64_C(0), // VST4d16Pseudo_UPD 2333| 2.24k| UINT64_C(4093640768), // VST4d16_UPD 2334| 2.24k| UINT64_C(4093640847), // VST4d32 2335| 2.24k| UINT64_C(0), // VST4d32Pseudo 2336| 2.24k| UINT64_C(0), // VST4d32Pseudo_UPD 2337| 2.24k| UINT64_C(4093640832), // VST4d32_UPD 2338| 2.24k| UINT64_C(4093640719), // VST4d8 2339| 2.24k| UINT64_C(0), // VST4d8Pseudo 2340| 2.24k| UINT64_C(0), // VST4d8Pseudo_UPD 2341| 2.24k| UINT64_C(4093640704), // VST4d8_UPD 2342| 2.24k| UINT64_C(0), 2343| 2.24k| UINT64_C(0), 2344| 2.24k| UINT64_C(0), 2345| 2.24k| UINT64_C(0), 2346| 2.24k| UINT64_C(0), 2347| 2.24k| UINT64_C(0), 2348| 2.24k| UINT64_C(0), 2349| 2.24k| UINT64_C(0), 2350| 2.24k| UINT64_C(0), 2351| 2.24k| UINT64_C(4093641039), // VST4q16 2352| 2.24k| UINT64_C(0), // VST4q16Pseudo_UPD 2353| 2.24k| UINT64_C(4093641024), // VST4q16_UPD 2354| 2.24k| UINT64_C(0), // VST4q16oddPseudo 2355| 2.24k| UINT64_C(0), // VST4q16oddPseudo_UPD 2356| 2.24k| UINT64_C(4093641103), // VST4q32 2357| 2.24k| UINT64_C(0), // VST4q32Pseudo_UPD 2358| 2.24k| UINT64_C(4093641088), // VST4q32_UPD 2359| 2.24k| UINT64_C(0), // VST4q32oddPseudo 2360| 2.24k| UINT64_C(0), // VST4q32oddPseudo_UPD 2361| 2.24k| UINT64_C(4093640975), // VST4q8 2362| 2.24k| UINT64_C(0), // VST4q8Pseudo_UPD 2363| 2.24k| UINT64_C(4093640960), // VST4q8_UPD 2364| 2.24k| UINT64_C(0), // VST4q8oddPseudo 2365| 2.24k| UINT64_C(0), // VST4q8oddPseudo_UPD 2366| 2.24k| UINT64_C(0), 2367| 2.24k| UINT64_C(0), 2368| 2.24k| UINT64_C(0), 2369| 2.24k| UINT64_C(0), 2370| 2.24k| UINT64_C(0), 2371| 2.24k| UINT64_C(0), 2372| 2.24k| UINT64_C(0), 2373| 2.24k| UINT64_C(0), 2374| 2.24k| UINT64_C(0), 2375| 2.24k| UINT64_C(220203776), // VSTMDDB_UPD 2376| 2.24k| UINT64_C(209718016), // VSTMDIA 2377| 2.24k| UINT64_C(211815168), // VSTMDIA_UPD 2378| 2.24k| UINT64_C(0), // VSTMQIA 2379| 2.24k| UINT64_C(220203520), // VSTMSDB_UPD 2380| 2.24k| UINT64_C(209717760), // VSTMSIA 2381| 2.24k| UINT64_C(211814912), // VSTMSIA_UPD 2382| 2.24k| UINT64_C(218106624), // VSTRD 2383| 2.24k| UINT64_C(218106112), // VSTRH 2384| 2.24k| UINT64_C(218106368), // VSTRS 2385| 2.24k| UINT64_C(238029632), // VSUBD 2386| 2.24k| UINT64_C(238029120), // VSUBH 2387| 2.24k| UINT64_C(4070573568), // VSUBHNv2i32 2388| 2.24k| UINT64_C(4069524992), // VSUBHNv4i16 2389| 2.24k| UINT64_C(4068476416), // VSUBHNv8i8 2390| 2.24k| UINT64_C(4070572544), // VSUBLsv2i64 2391| 2.24k| UINT64_C(4069523968), // VSUBLsv4i32 2392| 2.24k| UINT64_C(4068475392), // VSUBLsv8i16 2393| 2.24k| UINT64_C(4087349760), // VSUBLuv2i64 2394| 2.24k| UINT64_C(4086301184), // VSUBLuv4i32 2395| 2.24k| UINT64_C(4085252608), // VSUBLuv8i16 2396| 2.24k| UINT64_C(238029376), // VSUBS 2397| 2.24k| UINT64_C(4070572800), // VSUBWsv2i64 2398| 2.24k| UINT64_C(4069524224), // VSUBWsv4i32 2399| 2.24k| UINT64_C(4068475648), // VSUBWsv8i16 2400| 2.24k| UINT64_C(4087350016), // VSUBWuv2i64 2401| 2.24k| UINT64_C(4086301440), // VSUBWuv4i32 2402| 2.24k| UINT64_C(4085252864), // VSUBWuv8i16 2403| 2.24k| UINT64_C(4062186752), // VSUBfd 2404| 2.24k| UINT64_C(4062186816), // VSUBfq 2405| 2.24k| UINT64_C(4063235328), // VSUBhd 2406| 2.24k| UINT64_C(4063235392), // VSUBhq 2407| 2.24k| UINT64_C(4076865600), // VSUBv16i8 2408| 2.24k| UINT64_C(4080011264), // VSUBv1i64 2409| 2.24k| UINT64_C(4078962688), // VSUBv2i32 2410| 2.24k| UINT64_C(4080011328), // VSUBv2i64 2411| 2.24k| UINT64_C(4077914112), // VSUBv4i16 2412| 2.24k| UINT64_C(4078962752), // VSUBv4i32 2413| 2.24k| UINT64_C(4077914176), // VSUBv8i16 2414| 2.24k| UINT64_C(4076865536), // VSUBv8i8 2415| 2.24k| UINT64_C(4088528896), // VSWPd 2416| 2.24k| UINT64_C(4088528960), // VSWPq 2417| 2.24k| UINT64_C(4088399872), // VTBL1 2418| 2.24k| UINT64_C(4088400128), // VTBL2 2419| 2.24k| UINT64_C(4088400384), // VTBL3 2420| 2.24k| UINT64_C(0), // VTBL3Pseudo 2421| 2.24k| UINT64_C(4088400640), // VTBL4 2422| 2.24k| UINT64_C(0), // VTBL4Pseudo 2423| 2.24k| UINT64_C(4088399936), // VTBX1 2424| 2.24k| UINT64_C(4088400192), // VTBX2 2425| 2.24k| UINT64_C(4088400448), // VTBX3 2426| 2.24k| UINT64_C(0), // VTBX3Pseudo 2427| 2.24k| UINT64_C(4088400704), // VTBX4 2428| 2.24k| UINT64_C(0), // VTBX4Pseudo 2429| 2.24k| UINT64_C(247335744), // VTOSHD 2430| 2.24k| UINT64_C(247335232), // VTOSHH 2431| 2.24k| UINT64_C(247335488), // VTOSHS 2432| 2.24k| UINT64_C(247270208), // VTOSIRD 2433| 2.24k| UINT64_C(247269696), // VTOSIRH 2434| 2.24k| UINT64_C(247269952), // VTOSIRS 2435| 2.24k| UINT64_C(247270336), // VTOSIZD 2436| 2.24k| UINT64_C(247269824), // VTOSIZH 2437| 2.24k| UINT64_C(247270080), // VTOSIZS 2438| 2.24k| UINT64_C(247335872), // VTOSLD 2439| 2.24k| UINT64_C(247335360), // VTOSLH 2440| 2.24k| UINT64_C(247335616), // VTOSLS 2441| 2.24k| UINT64_C(247401280), // VTOUHD 2442| 2.24k| UINT64_C(247400768), // VTOUHH 2443| 2.24k| UINT64_C(247401024), // VTOUHS 2444| 2.24k| UINT64_C(247204672), // VTOUIRD 2445| 2.24k| UINT64_C(247204160), // VTOUIRH 2446| 2.24k| UINT64_C(247204416), // VTOUIRS 2447| 2.24k| UINT64_C(247204800), // VTOUIZD 2448| 2.24k| UINT64_C(247204288), // VTOUIZH 2449| 2.24k| UINT64_C(247204544), // VTOUIZS 2450| 2.24k| UINT64_C(247401408), // VTOULD 2451| 2.24k| UINT64_C(247400896), // VTOULH 2452| 2.24k| UINT64_C(247401152), // VTOULS 2453| 2.24k| UINT64_C(4088791168), // VTRNd16 2454| 2.24k| UINT64_C(4089053312), // VTRNd32 2455| 2.24k| UINT64_C(4088529024), // VTRNd8 2456| 2.24k| UINT64_C(4088791232), // VTRNq16 2457| 2.24k| UINT64_C(4089053376), // VTRNq32 2458| 2.24k| UINT64_C(4088529088), // VTRNq8 2459| 2.24k| UINT64_C(4060088400), // VTSTv16i8 2460| 2.24k| UINT64_C(4062185488), // VTSTv2i32 2461| 2.24k| UINT64_C(4061136912), // VTSTv4i16 2462| 2.24k| UINT64_C(4062185552), // VTSTv4i32 2463| 2.24k| UINT64_C(4061136976), // VTSTv8i16 2464| 2.24k| UINT64_C(4060088336), // VTSTv8i8 2465| 2.24k| UINT64_C(247139136), // VUHTOD 2466| 2.24k| UINT64_C(247138624), // VUHTOH 2467| 2.24k| UINT64_C(247138880), // VUHTOS 2468| 2.24k| UINT64_C(246942528), // VUITOD 2469| 2.24k| UINT64_C(246942016), // VUITOH 2470| 2.24k| UINT64_C(246942272), // VUITOS 2471| 2.24k| UINT64_C(247139264), // VULTOD 2472| 2.24k| UINT64_C(247138752), // VULTOH 2473| 2.24k| UINT64_C(247139008), // VULTOS 2474| 2.24k| UINT64_C(4088791296), // VUZPd16 2475| 2.24k| UINT64_C(4088529152), // VUZPd8 2476| 2.24k| UINT64_C(4088791360), // VUZPq16 2477| 2.24k| UINT64_C(4089053504), // VUZPq32 2478| 2.24k| UINT64_C(4088529216), // VUZPq8 2479| 2.24k| UINT64_C(4088791424), // VZIPd16 2480| 2.24k| UINT64_C(4088529280), // VZIPd8 2481| 2.24k| UINT64_C(4088791488), // VZIPq16 2482| 2.24k| UINT64_C(4089053632), // VZIPq32 2483| 2.24k| UINT64_C(4088529344), // VZIPq8 2484| 2.24k| UINT64_C(0), 2485| 2.24k| UINT64_C(0), 2486| 2.24k| UINT64_C(139460608), // sysLDMDA 2487| 2.24k| UINT64_C(141557760), // sysLDMDA_UPD 2488| 2.24k| UINT64_C(156237824), // sysLDMDB 2489| 2.24k| UINT64_C(158334976), // sysLDMDB_UPD 2490| 2.24k| UINT64_C(147849216), // sysLDMIA 2491| 2.24k| UINT64_C(149946368), // sysLDMIA_UPD 2492| 2.24k| UINT64_C(164626432), // sysLDMIB 2493| 2.24k| UINT64_C(166723584), // sysLDMIB_UPD 2494| 2.24k| UINT64_C(138412032), // sysSTMDA 2495| 2.24k| UINT64_C(140509184), // sysSTMDA_UPD 2496| 2.24k| UINT64_C(155189248), // sysSTMDB 2497| 2.24k| UINT64_C(157286400), // sysSTMDB_UPD 2498| 2.24k| UINT64_C(146800640), // sysSTMIA 2499| 2.24k| UINT64_C(148897792), // sysSTMIA_UPD 2500| 2.24k| UINT64_C(163577856), // sysSTMIB 2501| 2.24k| UINT64_C(165675008), // sysSTMIB_UPD 2502| 2.24k| UINT64_C(0), 2503| 2.24k| UINT64_C(4047503360), // t2ADCri 2504| 2.24k| UINT64_C(3946840064), // t2ADCrr 2505| 2.24k| UINT64_C(3946840064), // t2ADCrs 2506| 2.24k| UINT64_C(0), 2507| 2.24k| UINT64_C(0), 2508| 2.24k| UINT64_C(0), 2509| 2.24k| UINT64_C(4043309056), // t2ADDri 2510| 2.24k| UINT64_C(4060086272), // t2ADDri12 2511| 2.24k| UINT64_C(3942645760), // t2ADDrr 2512| 2.24k| UINT64_C(3942645760), // t2ADDrs 2513| 2.24k| UINT64_C(4061069312), // t2ADR 2514| 2.24k| UINT64_C(4026531840), // t2ANDri 2515| 2.24k| UINT64_C(3925868544), // t2ANDrr 2516| 2.24k| UINT64_C(3925868544), // t2ANDrs 2517| 2.24k| UINT64_C(3931045920), // t2ASRri 2518| 2.24k| UINT64_C(4198559744), // t2ASRrr 2519| 2.24k| UINT64_C(4026568704), // t2B 2520| 2.24k| UINT64_C(4084137984), // t2BFC 2521| 2.24k| UINT64_C(4083154944), // t2BFI 2522| 2.24k| UINT64_C(4028628992), // t2BICri 2523| 2.24k| UINT64_C(3927965696), // t2BICrr 2524| 2.24k| UINT64_C(3927965696), // t2BICrs 2525| 2.24k| UINT64_C(0), 2526| 2.24k| UINT64_C(4089483008), // t2BXJ 2527| 2.24k| UINT64_C(4026564608), // t2Bcc 2528| 2.24k| UINT64_C(3992977408), // t2CDP 2529| 2.24k| UINT64_C(4261412864), // t2CDP2 2530| 2.24k| UINT64_C(4089417519), // t2CLREX 2531| 2.24k| UINT64_C(4205899904), // t2CLZ 2532| 2.24k| UINT64_C(4044361472), // t2CMNri 2533| 2.24k| UINT64_C(3943698176), // t2CMNzrr 2534| 2.24k| UINT64_C(3943698176), // t2CMNzrs 2535| 2.24k| UINT64_C(4054847232), // t2CMPri 2536| 2.24k| UINT64_C(3954183936), // t2CMPrr 2537| 2.24k| UINT64_C(3954183936), // t2CMPrs 2538| 2.24k| UINT64_C(4088365312), // t2CPS1p 2539| 2.24k| UINT64_C(4088365056), // t2CPS2p 2540| 2.24k| UINT64_C(4088365312), // t2CPS3p 2541| 2.24k| UINT64_C(4206948480), // t2CRC32B 2542| 2.24k| UINT64_C(4207997056), // t2CRC32CB 2543| 2.24k| UINT64_C(4207997072), // t2CRC32CH 2544| 2.24k| UINT64_C(4207997088), // t2CRC32CW 2545| 2.24k| UINT64_C(4206948496), // t2CRC32H 2546| 2.24k| UINT64_C(4206948512), // t2CRC32W 2547| 2.24k| UINT64_C(4088365296), // t2DBG 2548| 2.24k| UINT64_C(4153376769), // t2DCPS1 2549| 2.24k| UINT64_C(4153376770), // t2DCPS2 2550| 2.24k| UINT64_C(4153376771), // t2DCPS3 2551| 2.24k| UINT64_C(4089417552), // t2DMB 2552| 2.24k| UINT64_C(4089417536), // t2DSB 2553| 2.24k| UINT64_C(4034920448), // t2EORri 2554| 2.24k| UINT64_C(3934257152), // t2EORrr 2555| 2.24k| UINT64_C(3934257152), // t2EORrs 2556| 2.24k| UINT64_C(4088365056), // t2HINT 2557| 2.24k| UINT64_C(4158685184), // t2HVC 2558| 2.24k| UINT64_C(4089417568), // t2ISB 2559| 2.24k| UINT64_C(48896), // t2IT 2560| 2.24k| UINT64_C(0), // t2Int_eh_sjlj_setjmp 2561| 2.24k| UINT64_C(0), // t2Int_eh_sjlj_setjmp_nofp 2562| 2.24k| UINT64_C(3905949615), // t2LDA 2563| 2.24k| UINT64_C(3905949583), // t2LDAB 2564| 2.24k| UINT64_C(3905949679), // t2LDAEX 2565| 2.24k| UINT64_C(3905949647), // t2LDAEXB 2566| 2.24k| UINT64_C(3905945855), // t2LDAEXD 2567| 2.24k| UINT64_C(3905949663), // t2LDAEXH 2568| 2.24k| UINT64_C(3905949599), // t2LDAH 2569| 2.24k| UINT64_C(4249878528), // t2LDC2L_OFFSET 2570| 2.24k| UINT64_C(4241489920), // t2LDC2L_OPTION 2571| 2.24k| UINT64_C(4235198464), // t2LDC2L_POST 2572| 2.24k| UINT64_C(4251975680), // t2LDC2L_PRE 2573| 2.24k| UINT64_C(4245684224), // t2LDC2_OFFSET 2574| 2.24k| UINT64_C(4237295616), // t2LDC2_OPTION 2575| 2.24k| UINT64_C(4231004160), // t2LDC2_POST 2576| 2.24k| UINT64_C(4247781376), // t2LDC2_PRE 2577| 2.24k| UINT64_C(3981443072), // t2LDCL_OFFSET 2578| 2.24k| UINT64_C(3973054464), // t2LDCL_OPTION 2579| 2.24k| UINT64_C(3966763008), // t2LDCL_POST 2580| 2.24k| UINT64_C(3983540224), // t2LDCL_PRE 2581| 2.24k| UINT64_C(3977248768), // t2LDC_OFFSET 2582| 2.24k| UINT64_C(3968860160), // t2LDC_OPTION 2583| 2.24k| UINT64_C(3962568704), // t2LDC_POST 2584| 2.24k| UINT64_C(3979345920), // t2LDC_PRE 2585| 2.24k| UINT64_C(3910139904), // t2LDMDB 2586| 2.24k| UINT64_C(3912237056), // t2LDMDB_UPD 2587| 2.24k| UINT64_C(3901751296), // t2LDMIA 2588| 2.24k| UINT64_C(0), 2589| 2.24k| UINT64_C(3903848448), // t2LDMIA_UPD 2590| 2.24k| UINT64_C(4161801728), // t2LDRBT 2591| 2.24k| UINT64_C(4161800448), // t2LDRB_POST 2592| 2.24k| UINT64_C(4161801472), // t2LDRB_PRE 2593| 2.24k| UINT64_C(4170186752), // t2LDRBi12 2594| 2.24k| UINT64_C(4161801216), // t2LDRBi8 2595| 2.24k| UINT64_C(4162781184), // t2LDRBpci 2596| 2.24k| UINT64_C(0), 2597| 2.24k| UINT64_C(4161798144), // t2LDRBs 2598| 2.24k| UINT64_C(3899654144), // t2LDRD_POST 2599| 2.24k| UINT64_C(3916431360), // t2LDRD_PRE 2600| 2.24k| UINT64_C(3914334208), // t2LDRDi8 2601| 2.24k| UINT64_C(3897560832), // t2LDREX 2602| 2.24k| UINT64_C(3905949519), // t2LDREXB 2603| 2.24k| UINT64_C(3905945727), // t2LDREXD 2604| 2.24k| UINT64_C(3905949535), // t2LDREXH 2605| 2.24k| UINT64_C(4163898880), // t2LDRHT 2606| 2.24k| UINT64_C(4163897600), // t2LDRH_POST 2607| 2.24k| UINT64_C(4163898624), // t2LDRH_PRE 2608| 2.24k| UINT64_C(4172283904), // t2LDRHi12 2609| 2.24k| UINT64_C(4163898368), // t2LDRHi8 2610| 2.24k| UINT64_C(4164878336), // t2LDRHpci 2611| 2.24k| UINT64_C(0), 2612| 2.24k| UINT64_C(4163895296), // t2LDRHs 2613| 2.24k| UINT64_C(4178578944), // t2LDRSBT 2614| 2.24k| UINT64_C(4178577664), // t2LDRSB_POST 2615| 2.24k| UINT64_C(4178578688), // t2LDRSB_PRE 2616| 2.24k| UINT64_C(4186963968), // t2LDRSBi12 2617| 2.24k| UINT64_C(4178578432), // t2LDRSBi8 2618| 2.24k| UINT64_C(4179558400), // t2LDRSBpci 2619| 2.24k| UINT64_C(0), 2620| 2.24k| UINT64_C(4178575360), // t2LDRSBs 2621| 2.24k| UINT64_C(4180676096), // t2LDRSHT 2622| 2.24k| UINT64_C(4180674816), // t2LDRSH_POST 2623| 2.24k| UINT64_C(4180675840), // t2LDRSH_PRE 2624| 2.24k| UINT64_C(4189061120), // t2LDRSHi12 2625| 2.24k| UINT64_C(4180675584), // t2LDRSHi8 2626| 2.24k| UINT64_C(4181655552), // t2LDRSHpci 2627| 2.24k| UINT64_C(0), 2628| 2.24k| UINT64_C(4180672512), // t2LDRSHs 2629| 2.24k| UINT64_C(4165996032), // t2LDRT 2630| 2.24k| UINT64_C(4165994752), // t2LDR_POST 2631| 2.24k| UINT64_C(4165995776), // t2LDR_PRE 2632| 2.24k| UINT64_C(4174381056), // t2LDRi12 2633| 2.24k| UINT64_C(4165995520), // t2LDRi8 2634| 2.24k| UINT64_C(4166975488), // t2LDRpci 2635| 2.24k| UINT64_C(0), 2636| 2.24k| UINT64_C(0), 2637| 2.24k| UINT64_C(4165992448), // t2LDRs 2638| 2.24k| UINT64_C(0), 2639| 2.24k| UINT64_C(0), 2640| 2.24k| UINT64_C(3931045888), // t2LSLri 2641| 2.24k| UINT64_C(4194365440), // t2LSLrr 2642| 2.24k| UINT64_C(3931045904), // t2LSRri 2643| 2.24k| UINT64_C(4196462592), // t2LSRrr 2644| 2.24k| UINT64_C(3992977424), // t2MCR 2645| 2.24k| UINT64_C(4261412880), // t2MCR2 2646| 2.24k| UINT64_C(3963617280), // t2MCRR 2647| 2.24k| UINT64_C(4232052736), // t2MCRR2 2648| 2.24k| UINT64_C(4211081216), // t2MLA 2649| 2.24k| UINT64_C(4211081232), // t2MLS 2650| 2.24k| UINT64_C(0), 2651| 2.24k| UINT64_C(0), 2652| 2.24k| UINT64_C(0), 2653| 2.24k| UINT64_C(0), 2654| 2.24k| UINT64_C(0), 2655| 2.24k| UINT64_C(0), 2656| 2.24k| UINT64_C(0), 2657| 2.24k| UINT64_C(0), 2658| 2.24k| UINT64_C(0), 2659| 2.24k| UINT64_C(0), 2660| 2.24k| UINT64_C(4072669184), // t2MOVTi16 2661| 2.24k| UINT64_C(0), 2662| 2.24k| UINT64_C(0), 2663| 2.24k| UINT64_C(4031709184), // t2MOVi 2664| 2.24k| UINT64_C(4064280576), // t2MOVi16 2665| 2.24k| UINT64_C(0), 2666| 2.24k| UINT64_C(0), 2667| 2.24k| UINT64_C(3931045888), // t2MOVr 2668| 2.24k| UINT64_C(0), 2669| 2.24k| UINT64_C(0), 2670| 2.24k| UINT64_C(3932094560), // t2MOVsra_flag 2671| 2.24k| UINT64_C(3932094544), // t2MOVsrl_flag 2672| 2.24k| UINT64_C(3994026000), // t2MRC 2673| 2.24k| UINT64_C(4262461456), // t2MRC2 2674| 2.24k| UINT64_C(3964665856), // t2MRRC 2675| 2.24k| UINT64_C(4233101312), // t2MRRC2 2676| 2.24k| UINT64_C(4092559360), // t2MRS_AR 2677| 2.24k| UINT64_C(4092559360), // t2MRS_M 2678| 2.24k| UINT64_C(4091576352), // t2MRSbanked 2679| 2.24k| UINT64_C(4093607936), // t2MRSsys_AR 2680| 2.24k| UINT64_C(4085284864), // t2MSR_AR 2681| 2.24k| UINT64_C(4085284864), // t2MSR_M 2682| 2.24k| UINT64_C(4085284896), // t2MSRbanked 2683| 2.24k| UINT64_C(4211142656), // t2MUL 2684| 2.24k| UINT64_C(0), 2685| 2.24k| UINT64_C(4033806336), // t2MVNi 2686| 2.24k| UINT64_C(3933143040), // t2MVNr 2687| 2.24k| UINT64_C(3933143040), // t2MVNs 2688| 2.24k| UINT64_C(4032823296), // t2ORNri 2689| 2.24k| UINT64_C(3932160000), // t2ORNrr 2690| 2.24k| UINT64_C(3932160000), // t2ORNrs 2691| 2.24k| UINT64_C(4030726144), // t2ORRri 2692| 2.24k| UINT64_C(3930062848), // t2ORRrr 2693| 2.24k| UINT64_C(3930062848), // t2ORRrs 2694| 2.24k| UINT64_C(3938451456), // t2PKHBT 2695| 2.24k| UINT64_C(3938451488), // t2PKHTB 2696| 2.24k| UINT64_C(4172345344), // t2PLDWi12 2697| 2.24k| UINT64_C(4163959808), // t2PLDWi8 2698| 2.24k| UINT64_C(4163956736), // t2PLDWs 2699| 2.24k| UINT64_C(4170248192), // t2PLDi12 2700| 2.24k| UINT64_C(4161862656), // t2PLDi8 2701| 2.24k| UINT64_C(4162842624), // t2PLDpci 2702| 2.24k| UINT64_C(4161859584), // t2PLDs 2703| 2.24k| UINT64_C(4187025408), // t2PLIi12 2704| 2.24k| UINT64_C(4178639872), // t2PLIi8 2705| 2.24k| UINT64_C(4179619840), // t2PLIpci 2706| 2.24k| UINT64_C(4178636800), // t2PLIs 2707| 2.24k| UINT64_C(4202754176), // t2QADD 2708| 2.24k| UINT64_C(4203802640), // t2QADD16 2709| 2.24k| UINT64_C(4202754064), // t2QADD8 2710| 2.24k| UINT64_C(4204851216), // t2QASX 2711| 2.24k| UINT64_C(4202754192), // t2QDADD 2712| 2.24k| UINT64_C(4202754224), // t2QDSUB 2713| 2.24k| UINT64_C(4209045520), // t2QSAX 2714| 2.24k| UINT64_C(4202754208), // t2QSUB 2715| 2.24k| UINT64_C(4207996944), // t2QSUB16 2716| 2.24k| UINT64_C(4206948368), // t2QSUB8 2717| 2.24k| UINT64_C(4203802784), // t2RBIT 2718| 2.24k| UINT64_C(4203802752), // t2REV 2719| 2.24k| UINT64_C(4203802768), // t2REV16 2720| 2.24k| UINT64_C(4203802800), // t2REVSH 2721| 2.24k| UINT64_C(3893411840), // t2RFEDB 2722| 2.24k| UINT64_C(3895508992), // t2RFEDBW 2723| 2.24k| UINT64_C(3918577664), // t2RFEIA 2724| 2.24k| UINT64_C(3920674816), // t2RFEIAW 2725| 2.24k| UINT64_C(3931045936), // t2RORri 2726| 2.24k| UINT64_C(4200656896), // t2RORrr 2727| 2.24k| UINT64_C(3931045936), // t2RRX 2728| 2.24k| UINT64_C(0), 2729| 2.24k| UINT64_C(0), 2730| 2.24k| UINT64_C(4055891968), // t2RSBri 2731| 2.24k| UINT64_C(3955228672), // t2RSBrr 2732| 2.24k| UINT64_C(3955228672), // t2RSBrs 2733| 2.24k| UINT64_C(4203802624), // t2SADD16 2734| 2.24k| UINT64_C(4202754048), // t2SADD8 2735| 2.24k| UINT64_C(4204851200), // t2SASX 2736| 2.24k| UINT64_C(4049600512), // t2SBCri 2737| 2.24k| UINT64_C(3948937216), // t2SBCrr 2738| 2.24k| UINT64_C(3948937216), // t2SBCrs 2739| 2.24k| UINT64_C(4081057792), // t2SBFX 2740| 2.24k| UINT64_C(4220580080), // t2SDIV 2741| 2.24k| UINT64_C(4204851328), // t2SEL 2742| 2.24k| UINT64_C(46608), // t2SETPAN 2743| 2.24k| UINT64_C(3917474175), // t2SG 2744| 2.24k| UINT64_C(4203802656), // t2SHADD16 2745| 2.24k| UINT64_C(4202754080), // t2SHADD8 2746| 2.24k| UINT64_C(4204851232), // t2SHASX 2747| 2.24k| UINT64_C(4209045536), // t2SHSAX 2748| 2.24k| UINT64_C(4207996960), // t2SHSUB16 2749| 2.24k| UINT64_C(4206948384), // t2SHSUB8 2750| 2.24k| UINT64_C(4159733760), // t2SMC 2751| 2.24k| UINT64_C(4212129792), // t2SMLABB 2752| 2.24k| UINT64_C(4212129808), // t2SMLABT 2753| 2.24k| UINT64_C(4213178368), // t2SMLAD 2754| 2.24k| UINT64_C(4213178384), // t2SMLADX 2755| 2.24k| UINT64_C(4223664128), // t2SMLAL 2756| 2.24k| UINT64_C(4223664256), // t2SMLALBB 2757| 2.24k| UINT64_C(4223664272), // t2SMLALBT 2758| 2.24k| UINT64_C(4223664320), // t2SMLALD 2759| 2.24k| UINT64_C(4223664336), // t2SMLALDX 2760| 2.24k| UINT64_C(4223664288), // t2SMLALTB 2761| 2.24k| UINT64_C(4223664304), // t2SMLALTT 2762| 2.24k| UINT64_C(4212129824), // t2SMLATB 2763| 2.24k| UINT64_C(4212129840), // t2SMLATT 2764| 2.24k| UINT64_C(4214226944), // t2SMLAWB 2765| 2.24k| UINT64_C(4214226960), // t2SMLAWT 2766| 2.24k| UINT64_C(4215275520), // t2SMLSD 2767| 2.24k| UINT64_C(4215275536), // t2SMLSDX 2768| 2.24k| UINT64_C(4224712896), // t2SMLSLD 2769| 2.24k| UINT64_C(4224712912), // t2SMLSLDX 2770| 2.24k| UINT64_C(4216324096), // t2SMMLA 2771| 2.24k| UINT64_C(4216324112), // t2SMMLAR 2772| 2.24k| UINT64_C(4217372672), // t2SMMLS 2773| 2.24k| UINT64_C(4217372688), // t2SMMLSR 2774| 2.24k| UINT64_C(4216385536), // t2SMMUL 2775| 2.24k| UINT64_C(4216385552), // t2SMMULR 2776| 2.24k| UINT64_C(4213239808), // t2SMUAD 2777| 2.24k| UINT64_C(4213239824), // t2SMUADX 2778| 2.24k| UINT64_C(4212191232), // t2SMULBB 2779| 2.24k| UINT64_C(4212191248), // t2SMULBT 2780| 2.24k| UINT64_C(4219469824), // t2SMULL 2781| 2.24k| UINT64_C(4212191264), // t2SMULTB 2782| 2.24k| UINT64_C(4212191280), // t2SMULTT 2783| 2.24k| UINT64_C(4214288384), // t2SMULWB 2784| 2.24k| UINT64_C(4214288400), // t2SMULWT 2785| 2.24k| UINT64_C(4215336960), // t2SMUSD 2786| 2.24k| UINT64_C(4215336976), // t2SMUSDX 2787| 2.24k| UINT64_C(3893215232), // t2SRSDB 2788| 2.24k| UINT64_C(3895312384), // t2SRSDB_UPD 2789| 2.24k| UINT64_C(3918381056), // t2SRSIA 2790| 2.24k| UINT64_C(3920478208), // t2SRSIA_UPD 2791| 2.24k| UINT64_C(4076863488), // t2SSAT 2792| 2.24k| UINT64_C(4078960640), // t2SSAT16 2793| 2.24k| UINT64_C(4209045504), // t2SSAX 2794| 2.24k| UINT64_C(4207996928), // t2SSUB16 2795| 2.24k| UINT64_C(4206948352), // t2SSUB8 2796| 2.24k| UINT64_C(4248829952), // t2STC2L_OFFSET 2797| 2.24k| UINT64_C(4240441344), // t2STC2L_OPTION 2798| 2.24k| UINT64_C(4234149888), // t2STC2L_POST 2799| 2.24k| UINT64_C(4250927104), // t2STC2L_PRE 2800| 2.24k| UINT64_C(4244635648), // t2STC2_OFFSET 2801| 2.24k| UINT64_C(4236247040), // t2STC2_OPTION 2802| 2.24k| UINT64_C(4229955584), // t2STC2_POST 2803| 2.24k| UINT64_C(4246732800), // t2STC2_PRE 2804| 2.24k| UINT64_C(3980394496), // t2STCL_OFFSET 2805| 2.24k| UINT64_C(3972005888), // t2STCL_OPTION 2806| 2.24k| UINT64_C(3965714432), // t2STCL_POST 2807| 2.24k| UINT64_C(3982491648), // t2STCL_PRE 2808| 2.24k| UINT64_C(3976200192), // t2STC_OFFSET 2809| 2.24k| UINT64_C(3967811584), // t2STC_OPTION 2810| 2.24k| UINT64_C(3961520128), // t2STC_POST 2811| 2.24k| UINT64_C(3978297344), // t2STC_PRE 2812| 2.24k| UINT64_C(3904901039), // t2STL 2813| 2.24k| UINT64_C(3904901007), // t2STLB 2814| 2.24k| UINT64_C(3904901088), // t2STLEX 2815| 2.24k| UINT64_C(3904901056), // t2STLEXB 2816| 2.24k| UINT64_C(3904897264), // t2STLEXD 2817| 2.24k| UINT64_C(3904901072), // t2STLEXH 2818| 2.24k| UINT64_C(3904901023), // t2STLH 2819| 2.24k| UINT64_C(3909091328), // t2STMDB 2820| 2.24k| UINT64_C(3911188480), // t2STMDB_UPD 2821| 2.24k| UINT64_C(3900702720), // t2STMIA 2822| 2.24k| UINT64_C(3902799872), // t2STMIA_UPD 2823| 2.24k| UINT64_C(4160753152), // t2STRBT 2824| 2.24k| UINT64_C(4160751872), // t2STRB_POST 2825| 2.24k| UINT64_C(4160752896), // t2STRB_PRE 2826| 2.24k| UINT64_C(0), 2827| 2.24k| UINT64_C(4169138176), // t2STRBi12 2828| 2.24k| UINT64_C(4160752640), // t2STRBi8 2829| 2.24k| UINT64_C(4160749568), // t2STRBs 2830| 2.24k| UINT64_C(3898605568), // t2STRD_POST 2831| 2.24k| UINT64_C(3915382784), // t2STRD_PRE 2832| 2.24k| UINT64_C(3913285632), // t2STRDi8 2833| 2.24k| UINT64_C(3896508416), // t2STREX 2834| 2.24k| UINT64_C(3904900928), // t2STREXB 2835| 2.24k| UINT64_C(3904897136), // t2STREXD 2836| 2.24k| UINT64_C(3904900944), // t2STREXH 2837| 2.24k| UINT64_C(4162850304), // t2STRHT 2838| 2.24k| UINT64_C(4162849024), // t2STRH_POST 2839| 2.24k| UINT64_C(4162850048), // t2STRH_PRE 2840| 2.24k| UINT64_C(0), 2841| 2.24k| UINT64_C(4171235328), // t2STRHi12 2842| 2.24k| UINT64_C(4162849792), // t2STRHi8 2843| 2.24k| UINT64_C(4162846720), // t2STRHs 2844| 2.24k| UINT64_C(4164947456), // t2STRT 2845| 2.24k| UINT64_C(4164946176), // t2STR_POST 2846| 2.24k| UINT64_C(4164947200), // t2STR_PRE 2847| 2.24k| UINT64_C(0), 2848| 2.24k| UINT64_C(4173332480), // t2STRi12 2849| 2.24k| UINT64_C(4164946944), // t2STRi8 2850| 2.24k| UINT64_C(4164943872), // t2STRs 2851| 2.24k| UINT64_C(4091449088), // t2SUBS_PC_LR 2852| 2.24k| UINT64_C(0), 2853| 2.24k| UINT64_C(0), 2854| 2.24k| UINT64_C(0), 2855| 2.24k| UINT64_C(4053794816), // t2SUBri 2856| 2.24k| UINT64_C(4070572032), // t2SUBri12 2857| 2.24k| UINT64_C(3953131520), // t2SUBrr 2858| 2.24k| UINT64_C(3953131520), // t2SUBrs 2859| 2.24k| UINT64_C(4198559872), // t2SXTAB 2860| 2.24k| UINT64_C(4196462720), // t2SXTAB16 2861| 2.24k| UINT64_C(4194365568), // t2SXTAH 2862| 2.24k| UINT64_C(4199542912), // t2SXTB 2863| 2.24k| UINT64_C(4197445760), // t2SXTB16 2864| 2.24k| UINT64_C(4195348608), // t2SXTH 2865| 2.24k| UINT64_C(3906007040), // t2TBB 2866| 2.24k| UINT64_C(0), 2867| 2.24k| UINT64_C(3906007056), // t2TBH 2868| 2.24k| UINT64_C(0), 2869| 2.24k| UINT64_C(4035972864), // t2TEQri 2870| 2.24k| UINT64_C(3935309568), // t2TEQrr 2871| 2.24k| UINT64_C(3935309568), // t2TEQrs 2872| 2.24k| UINT64_C(4027584256), // t2TSTri 2873| 2.24k| UINT64_C(3926920960), // t2TSTrr 2874| 2.24k| UINT64_C(3926920960), // t2TSTrs 2875| 2.24k| UINT64_C(3896569856), // t2TT 2876| 2.24k| UINT64_C(3896569984), // t2TTA 2877| 2.24k| UINT64_C(3896570048), // t2TTAT 2878| 2.24k| UINT64_C(3896569920), // t2TTT 2879| 2.24k| UINT64_C(4203802688), // t2UADD16 2880| 2.24k| UINT64_C(4202754112), // t2UADD8 2881| 2.24k| UINT64_C(4204851264), // t2UASX 2882| 2.24k| UINT64_C(4089446400), // t2UBFX 2883| 2.24k| UINT64_C(4159741952), // t2UDF 2884| 2.24k| UINT64_C(4222677232), // t2UDIV 2885| 2.24k| UINT64_C(4203802720), // t2UHADD16 2886| 2.24k| UINT64_C(4202754144), // t2UHADD8 2887| 2.24k| UINT64_C(4204851296), // t2UHASX 2888| 2.24k| UINT64_C(4209045600), // t2UHSAX 2889| 2.24k| UINT64_C(4207997024), // t2UHSUB16 2890| 2.24k| UINT64_C(4206948448), // t2UHSUB8 2891| 2.24k| UINT64_C(4225761376), // t2UMAAL 2892| 2.24k| UINT64_C(4225761280), // t2UMLAL 2893| 2.24k| UINT64_C(4221566976), // t2UMULL 2894| 2.24k| UINT64_C(4203802704), // t2UQADD16 2895| 2.24k| UINT64_C(4202754128), // t2UQADD8 2896| 2.24k| UINT64_C(4204851280), // t2UQASX 2897| 2.24k| UINT64_C(4209045584), // t2UQSAX 2898| 2.24k| UINT64_C(4207997008), // t2UQSUB16 2899| 2.24k| UINT64_C(4206948432), // t2UQSUB8 2900| 2.24k| UINT64_C(4218482688), // t2USAD8 2901| 2.24k| UINT64_C(4218421248), // t2USADA8 2902| 2.24k| UINT64_C(4085252096), // t2USAT 2903| 2.24k| UINT64_C(4087349248), // t2USAT16 2904| 2.24k| UINT64_C(4209045568), // t2USAX 2905| 2.24k| UINT64_C(4207996992), // t2USUB16 2906| 2.24k| UINT64_C(4206948416), // t2USUB8 2907| 2.24k| UINT64_C(4199608448), // t2UXTAB 2908| 2.24k| UINT64_C(4197511296), // t2UXTAB16 2909| 2.24k| UINT64_C(4195414144), // t2UXTAH 2910| 2.24k| UINT64_C(4200591488), // t2UXTB 2911| 2.24k| UINT64_C(4198494336), // t2UXTB16 2912| 2.24k| UINT64_C(4196397184), // t2UXTH 2913| 2.24k| UINT64_C(16704), // tADC 2914| 2.24k| UINT64_C(0), 2915| 2.24k| UINT64_C(17408), // tADDhirr 2916| 2.24k| UINT64_C(7168), // tADDi3 2917| 2.24k| UINT64_C(12288), // tADDi8 2918| 2.24k| UINT64_C(17512), // tADDrSP 2919| 2.24k| UINT64_C(43008), // tADDrSPi 2920| 2.24k| UINT64_C(6144), // tADDrr 2921| 2.24k| UINT64_C(45056), // tADDspi 2922| 2.24k| UINT64_C(17541), // tADDspr 2923| 2.24k| UINT64_C(0), 2924| 2.24k| UINT64_C(0), 2925| 2.24k| UINT64_C(40960), // tADR 2926| 2.24k| UINT64_C(16384), // tAND 2927| 2.24k| UINT64_C(4096), // tASRri 2928| 2.24k| UINT64_C(16640), // tASRrr 2929| 2.24k| UINT64_C(57344), // tB 2930| 2.24k| UINT64_C(17280), // tBIC 2931| 2.24k| UINT64_C(48640), // tBKPT 2932| 2.24k| UINT64_C(4026585088), // tBL 2933| 2.24k| UINT64_C(18308), // tBLXNSr 2934| 2.24k| UINT64_C(4026580992), // tBLXi 2935| 2.24k| UINT64_C(18304), // tBLXr 2936| 2.24k| UINT64_C(0), 2937| 2.24k| UINT64_C(0), 2938| 2.24k| UINT64_C(18176), // tBX 2939| 2.24k| UINT64_C(18180), // tBXNS 2940| 2.24k| UINT64_C(0), 2941| 2.24k| UINT64_C(0), 2942| 2.24k| UINT64_C(0), 2943| 2.24k| UINT64_C(53248), // tBcc 2944| 2.24k| UINT64_C(0), 2945| 2.24k| UINT64_C(47360), // tCBNZ 2946| 2.24k| UINT64_C(45312), // tCBZ 2947| 2.24k| UINT64_C(17088), // tCMNz 2948| 2.24k| UINT64_C(17664), // tCMPhir 2949| 2.24k| UINT64_C(10240), // tCMPi8 2950| 2.24k| UINT64_C(17024), // tCMPr 2951| 2.24k| UINT64_C(46688), // tCPS 2952| 2.24k| UINT64_C(16448), // tEOR 2953| 2.24k| UINT64_C(48896), // tHINT 2954| 2.24k| UINT64_C(47744), // tHLT 2955| 2.24k| UINT64_C(0), // tInt_eh_sjlj_longjmp 2956| 2.24k| UINT64_C(0), // tInt_eh_sjlj_setjmp 2957| 2.24k| UINT64_C(51200), // tLDMIA 2958| 2.24k| UINT64_C(0), 2959| 2.24k| UINT64_C(30720), // tLDRBi 2960| 2.24k| UINT64_C(23552), // tLDRBr 2961| 2.24k| UINT64_C(34816), // tLDRHi 2962| 2.24k| UINT64_C(23040), // tLDRHr 2963| 2.24k| UINT64_C(0), 2964| 2.24k| UINT64_C(0), 2965| 2.24k| UINT64_C(22016), // tLDRSB 2966| 2.24k| UINT64_C(24064), // tLDRSH 2967| 2.24k| UINT64_C(26624), // tLDRi 2968| 2.24k| UINT64_C(18432), // tLDRpci 2969| 2.24k| UINT64_C(0), 2970| 2.24k| UINT64_C(22528), // tLDRr 2971| 2.24k| UINT64_C(38912), // tLDRspi 2972| 2.24k| UINT64_C(0), 2973| 2.24k| UINT64_C(0), 2974| 2.24k| UINT64_C(0), // tLSLri 2975| 2.24k| UINT64_C(16512), // tLSLrr 2976| 2.24k| UINT64_C(2048), // tLSRri 2977| 2.24k| UINT64_C(16576), // tLSRrr 2978| 2.24k| UINT64_C(0), 2979| 2.24k| UINT64_C(0), // tMOVSr 2980| 2.24k| UINT64_C(8192), // tMOVi8 2981| 2.24k| UINT64_C(17920), // tMOVr 2982| 2.24k| UINT64_C(17216), // tMUL 2983| 2.24k| UINT64_C(17344), // tMVN 2984| 2.24k| UINT64_C(17152), // tORR 2985| 2.24k| UINT64_C(17528), // tPICADD 2986| 2.24k| UINT64_C(48128), // tPOP 2987| 2.24k| UINT64_C(0), 2988| 2.24k| UINT64_C(46080), // tPUSH 2989| 2.24k| UINT64_C(47616), // tREV 2990| 2.24k| UINT64_C(47680), // tREV16 2991| 2.24k| UINT64_C(47808), // tREVSH 2992| 2.24k| UINT64_C(16832), // tROR 2993| 2.24k| UINT64_C(16960), // tRSB 2994| 2.24k| UINT64_C(16768), // tSBC 2995| 2.24k| UINT64_C(46672), // tSETEND 2996| 2.24k| UINT64_C(49152), // tSTMIA_UPD 2997| 2.24k| UINT64_C(28672), // tSTRBi 2998| 2.24k| UINT64_C(21504), // tSTRBr 2999| 2.24k| UINT64_C(32768), // tSTRHi 3000| 2.24k| UINT64_C(20992), // tSTRHr 3001| 2.24k| UINT64_C(24576), // tSTRi 3002| 2.24k| UINT64_C(20480), // tSTRr 3003| 2.24k| UINT64_C(36864), // tSTRspi 3004| 2.24k| UINT64_C(7680), // tSUBi3 3005| 2.24k| UINT64_C(14336), // tSUBi8 3006| 2.24k| UINT64_C(6656), // tSUBrr 3007| 2.24k| UINT64_C(45184), // tSUBspi 3008| 2.24k| UINT64_C(57088), // tSVC 3009| 2.24k| UINT64_C(45632), // tSXTB 3010| 2.24k| UINT64_C(45568), // tSXTH 3011| 2.24k| UINT64_C(0), 3012| 2.24k| UINT64_C(0), 3013| 2.24k| UINT64_C(0), 3014| 2.24k| UINT64_C(0), 3015| 2.24k| UINT64_C(57086), // tTRAP 3016| 2.24k| UINT64_C(16896), // tTST 3017| 2.24k| UINT64_C(56832), // tUDF 3018| 2.24k| UINT64_C(45760), // tUXTB 3019| 2.24k| UINT64_C(45696), // tUXTH 3020| 2.24k| UINT64_C(0) 3021| 2.24k| }; 3022| 2.24k| const unsigned opcode = MI.getOpcode(); 3023| 2.24k| uint64_t Value = InstBits[opcode]; 3024| 2.24k| uint64_t op = 0; 3025| 2.24k| (void)op; // suppress warning 3026| 2.24k| switch (opcode) { 3027| 0| case ARM::CLREX: ------------------ | Branch (3027:5): [True: 0, False: 2.24k] ------------------ 3028| 0| case ARM::TRAP: ------------------ | Branch (3028:5): [True: 0, False: 2.24k] ------------------ 3029| 0| case ARM::TRAPNaCl: ------------------ | Branch (3029:5): [True: 0, False: 2.24k] ------------------ 3030| 0| case ARM::VLD1LNq16Pseudo: ------------------ | Branch (3030:5): [True: 0, False: 2.24k] ------------------ 3031| 0| case ARM::VLD1LNq16Pseudo_UPD: ------------------ | Branch (3031:5): [True: 0, False: 2.24k] ------------------ 3032| 0| case ARM::VLD1LNq32Pseudo: ------------------ | Branch (3032:5): [True: 0, False: 2.24k] ------------------ 3033| 0| case ARM::VLD1LNq32Pseudo_UPD: ------------------ | Branch (3033:5): [True: 0, False: 2.24k] ------------------ 3034| 0| case ARM::VLD1LNq8Pseudo: ------------------ | Branch (3034:5): [True: 0, False: 2.24k] ------------------ 3035| 0| case ARM::VLD1LNq8Pseudo_UPD: ------------------ | Branch (3035:5): [True: 0, False: 2.24k] ------------------ 3036| 0| case ARM::VLD1d64QPseudo: ------------------ | Branch (3036:5): [True: 0, False: 2.24k] ------------------ 3037| 0| case ARM::VLD1d64QPseudoWB_fixed: ------------------ | Branch (3037:5): [True: 0, False: 2.24k] ------------------ 3038| 0| case ARM::VLD1d64QPseudoWB_register: ------------------ | Branch (3038:5): [True: 0, False: 2.24k] ------------------ 3039| 0| case ARM::VLD1d64TPseudo: ------------------ | Branch (3039:5): [True: 0, False: 2.24k] ------------------ 3040| 0| case ARM::VLD1d64TPseudoWB_fixed: ------------------ | Branch (3040:5): [True: 0, False: 2.24k] ------------------ 3041| 0| case ARM::VLD1d64TPseudoWB_register: ------------------ | Branch (3041:5): [True: 0, False: 2.24k] ------------------ 3042| 0| case ARM::VLD2LNd16Pseudo: ------------------ | Branch (3042:5): [True: 0, False: 2.24k] ------------------ 3043| 0| case ARM::VLD2LNd16Pseudo_UPD: ------------------ | Branch (3043:5): [True: 0, False: 2.24k] ------------------ 3044| 0| case ARM::VLD2LNd32Pseudo: ------------------ | Branch (3044:5): [True: 0, False: 2.24k] ------------------ 3045| 0| case ARM::VLD2LNd32Pseudo_UPD: ------------------ | Branch (3045:5): [True: 0, False: 2.24k] ------------------ 3046| 0| case ARM::VLD2LNd8Pseudo: ------------------ | Branch (3046:5): [True: 0, False: 2.24k] ------------------ 3047| 0| case ARM::VLD2LNd8Pseudo_UPD: ------------------ | Branch (3047:5): [True: 0, False: 2.24k] ------------------ 3048| 0| case ARM::VLD2LNq16Pseudo: ------------------ | Branch (3048:5): [True: 0, False: 2.24k] ------------------ 3049| 0| case ARM::VLD2LNq16Pseudo_UPD: ------------------ | Branch (3049:5): [True: 0, False: 2.24k] ------------------ 3050| 0| case ARM::VLD2LNq32Pseudo: ------------------ | Branch (3050:5): [True: 0, False: 2.24k] ------------------ 3051| 0| case ARM::VLD2LNq32Pseudo_UPD: ------------------ | Branch (3051:5): [True: 0, False: 2.24k] ------------------ 3052| 0| case ARM::VLD2q16Pseudo: ------------------ | Branch (3052:5): [True: 0, False: 2.24k] ------------------ 3053| 0| case ARM::VLD2q16PseudoWB_fixed: ------------------ | Branch (3053:5): [True: 0, False: 2.24k] ------------------ 3054| 0| case ARM::VLD2q16PseudoWB_register: ------------------ | Branch (3054:5): [True: 0, False: 2.24k] ------------------ 3055| 0| case ARM::VLD2q32Pseudo: ------------------ | Branch (3055:5): [True: 0, False: 2.24k] ------------------ 3056| 0| case ARM::VLD2q32PseudoWB_fixed: ------------------ | Branch (3056:5): [True: 0, False: 2.24k] ------------------ 3057| 0| case ARM::VLD2q32PseudoWB_register: ------------------ | Branch (3057:5): [True: 0, False: 2.24k] ------------------ 3058| 0| case ARM::VLD2q8Pseudo: ------------------ | Branch (3058:5): [True: 0, False: 2.24k] ------------------ 3059| 0| case ARM::VLD2q8PseudoWB_fixed: ------------------ | Branch (3059:5): [True: 0, False: 2.24k] ------------------ 3060| 0| case ARM::VLD2q8PseudoWB_register: ------------------ | Branch (3060:5): [True: 0, False: 2.24k] ------------------ 3061| 0| case ARM::VLD3DUPd16Pseudo: ------------------ | Branch (3061:5): [True: 0, False: 2.24k] ------------------ 3062| 0| case ARM::VLD3DUPd16Pseudo_UPD: ------------------ | Branch (3062:5): [True: 0, False: 2.24k] ------------------ 3063| 0| case ARM::VLD3DUPd32Pseudo: ------------------ | Branch (3063:5): [True: 0, False: 2.24k] ------------------ 3064| 0| case ARM::VLD3DUPd32Pseudo_UPD: ------------------ | Branch (3064:5): [True: 0, False: 2.24k] ------------------ 3065| 0| case ARM::VLD3DUPd8Pseudo: ------------------ | Branch (3065:5): [True: 0, False: 2.24k] ------------------ 3066| 0| case ARM::VLD3DUPd8Pseudo_UPD: ------------------ | Branch (3066:5): [True: 0, False: 2.24k] ------------------ 3067| 0| case ARM::VLD3LNd16Pseudo: ------------------ | Branch (3067:5): [True: 0, False: 2.24k] ------------------ 3068| 0| case ARM::VLD3LNd16Pseudo_UPD: ------------------ | Branch (3068:5): [True: 0, False: 2.24k] ------------------ 3069| 0| case ARM::VLD3LNd32Pseudo: ------------------ | Branch (3069:5): [True: 0, False: 2.24k] ------------------ 3070| 0| case ARM::VLD3LNd32Pseudo_UPD: ------------------ | Branch (3070:5): [True: 0, False: 2.24k] ------------------ 3071| 0| case ARM::VLD3LNd8Pseudo: ------------------ | Branch (3071:5): [True: 0, False: 2.24k] ------------------ 3072| 0| case ARM::VLD3LNd8Pseudo_UPD: ------------------ | Branch (3072:5): [True: 0, False: 2.24k] ------------------ 3073| 0| case ARM::VLD3LNq16Pseudo: ------------------ | Branch (3073:5): [True: 0, False: 2.24k] ------------------ 3074| 0| case ARM::VLD3LNq16Pseudo_UPD: ------------------ | Branch (3074:5): [True: 0, False: 2.24k] ------------------ 3075| 0| case ARM::VLD3LNq32Pseudo: ------------------ | Branch (3075:5): [True: 0, False: 2.24k] ------------------ 3076| 0| case ARM::VLD3LNq32Pseudo_UPD: ------------------ | Branch (3076:5): [True: 0, False: 2.24k] ------------------ 3077| 0| case ARM::VLD3d16Pseudo: ------------------ | Branch (3077:5): [True: 0, False: 2.24k] ------------------ 3078| 0| case ARM::VLD3d16Pseudo_UPD: ------------------ | Branch (3078:5): [True: 0, False: 2.24k] ------------------ 3079| 0| case ARM::VLD3d32Pseudo: ------------------ | Branch (3079:5): [True: 0, False: 2.24k] ------------------ 3080| 0| case ARM::VLD3d32Pseudo_UPD: ------------------ | Branch (3080:5): [True: 0, False: 2.24k] ------------------ 3081| 0| case ARM::VLD3d8Pseudo: ------------------ | Branch (3081:5): [True: 0, False: 2.24k] ------------------ 3082| 0| case ARM::VLD3d8Pseudo_UPD: ------------------ | Branch (3082:5): [True: 0, False: 2.24k] ------------------ 3083| 0| case ARM::VLD3q16Pseudo_UPD: ------------------ | Branch (3083:5): [True: 0, False: 2.24k] ------------------ 3084| 0| case ARM::VLD3q16oddPseudo: ------------------ | Branch (3084:5): [True: 0, False: 2.24k] ------------------ 3085| 0| case ARM::VLD3q16oddPseudo_UPD: ------------------ | Branch (3085:5): [True: 0, False: 2.24k] ------------------ 3086| 0| case ARM::VLD3q32Pseudo_UPD: ------------------ | Branch (3086:5): [True: 0, False: 2.24k] ------------------ 3087| 0| case ARM::VLD3q32oddPseudo: ------------------ | Branch (3087:5): [True: 0, False: 2.24k] ------------------ 3088| 0| case ARM::VLD3q32oddPseudo_UPD: ------------------ | Branch (3088:5): [True: 0, False: 2.24k] ------------------ 3089| 0| case ARM::VLD3q8Pseudo_UPD: ------------------ | Branch (3089:5): [True: 0, False: 2.24k] ------------------ 3090| 0| case ARM::VLD3q8oddPseudo: ------------------ | Branch (3090:5): [True: 0, False: 2.24k] ------------------ 3091| 0| case ARM::VLD3q8oddPseudo_UPD: ------------------ | Branch (3091:5): [True: 0, False: 2.24k] ------------------ 3092| 0| case ARM::VLD4DUPd16Pseudo: ------------------ | Branch (3092:5): [True: 0, False: 2.24k] ------------------ 3093| 0| case ARM::VLD4DUPd16Pseudo_UPD: ------------------ | Branch (3093:5): [True: 0, False: 2.24k] ------------------ 3094| 0| case ARM::VLD4DUPd32Pseudo: ------------------ | Branch (3094:5): [True: 0, False: 2.24k] ------------------ 3095| 0| case ARM::VLD4DUPd32Pseudo_UPD: ------------------ | Branch (3095:5): [True: 0, False: 2.24k] ------------------ 3096| 0| case ARM::VLD4DUPd8Pseudo: ------------------ | Branch (3096:5): [True: 0, False: 2.24k] ------------------ 3097| 0| case ARM::VLD4DUPd8Pseudo_UPD: ------------------ | Branch (3097:5): [True: 0, False: 2.24k] ------------------ 3098| 0| case ARM::VLD4LNd16Pseudo: ------------------ | Branch (3098:5): [True: 0, False: 2.24k] ------------------ 3099| 0| case ARM::VLD4LNd16Pseudo_UPD: ------------------ | Branch (3099:5): [True: 0, False: 2.24k] ------------------ 3100| 0| case ARM::VLD4LNd32Pseudo: ------------------ | Branch (3100:5): [True: 0, False: 2.24k] ------------------ 3101| 0| case ARM::VLD4LNd32Pseudo_UPD: ------------------ | Branch (3101:5): [True: 0, False: 2.24k] ------------------ 3102| 0| case ARM::VLD4LNd8Pseudo: ------------------ | Branch (3102:5): [True: 0, False: 2.24k] ------------------ 3103| 0| case ARM::VLD4LNd8Pseudo_UPD: ------------------ | Branch (3103:5): [True: 0, False: 2.24k] ------------------ 3104| 0| case ARM::VLD4LNq16Pseudo: ------------------ | Branch (3104:5): [True: 0, False: 2.24k] ------------------ 3105| 0| case ARM::VLD4LNq16Pseudo_UPD: ------------------ | Branch (3105:5): [True: 0, False: 2.24k] ------------------ 3106| 0| case ARM::VLD4LNq32Pseudo: ------------------ | Branch (3106:5): [True: 0, False: 2.24k] ------------------ 3107| 0| case ARM::VLD4LNq32Pseudo_UPD: ------------------ | Branch (3107:5): [True: 0, False: 2.24k] ------------------ 3108| 0| case ARM::VLD4d16Pseudo: ------------------ | Branch (3108:5): [True: 0, False: 2.24k] ------------------ 3109| 0| case ARM::VLD4d16Pseudo_UPD: ------------------ | Branch (3109:5): [True: 0, False: 2.24k] ------------------ 3110| 0| case ARM::VLD4d32Pseudo: ------------------ | Branch (3110:5): [True: 0, False: 2.24k] ------------------ 3111| 0| case ARM::VLD4d32Pseudo_UPD: ------------------ | Branch (3111:5): [True: 0, False: 2.24k] ------------------ 3112| 0| case ARM::VLD4d8Pseudo: ------------------ | Branch (3112:5): [True: 0, False: 2.24k] ------------------ 3113| 0| case ARM::VLD4d8Pseudo_UPD: ------------------ | Branch (3113:5): [True: 0, False: 2.24k] ------------------ 3114| 0| case ARM::VLD4q16Pseudo_UPD: ------------------ | Branch (3114:5): [True: 0, False: 2.24k] ------------------ 3115| 0| case ARM::VLD4q16oddPseudo: ------------------ | Branch (3115:5): [True: 0, False: 2.24k] ------------------ 3116| 0| case ARM::VLD4q16oddPseudo_UPD: ------------------ | Branch (3116:5): [True: 0, False: 2.24k] ------------------ 3117| 0| case ARM::VLD4q32Pseudo_UPD: ------------------ | Branch (3117:5): [True: 0, False: 2.24k] ------------------ 3118| 0| case ARM::VLD4q32oddPseudo: ------------------ | Branch (3118:5): [True: 0, False: 2.24k] ------------------ 3119| 0| case ARM::VLD4q32oddPseudo_UPD: ------------------ | Branch (3119:5): [True: 0, False: 2.24k] ------------------ 3120| 0| case ARM::VLD4q8Pseudo_UPD: ------------------ | Branch (3120:5): [True: 0, False: 2.24k] ------------------ 3121| 0| case ARM::VLD4q8oddPseudo: ------------------ | Branch (3121:5): [True: 0, False: 2.24k] ------------------ 3122| 0| case ARM::VLD4q8oddPseudo_UPD: ------------------ | Branch (3122:5): [True: 0, False: 2.24k] ------------------ 3123| 0| case ARM::VLDMQIA: ------------------ | Branch (3123:5): [True: 0, False: 2.24k] ------------------ 3124| 0| case ARM::VST1LNq16Pseudo: ------------------ | Branch (3124:5): [True: 0, False: 2.24k] ------------------ 3125| 0| case ARM::VST1LNq16Pseudo_UPD: ------------------ | Branch (3125:5): [True: 0, False: 2.24k] ------------------ 3126| 0| case ARM::VST1LNq32Pseudo: ------------------ | Branch (3126:5): [True: 0, False: 2.24k] ------------------ 3127| 0| case ARM::VST1LNq32Pseudo_UPD: ------------------ | Branch (3127:5): [True: 0, False: 2.24k] ------------------ 3128| 0| case ARM::VST1LNq8Pseudo: ------------------ | Branch (3128:5): [True: 0, False: 2.24k] ------------------ 3129| 0| case ARM::VST1LNq8Pseudo_UPD: ------------------ | Branch (3129:5): [True: 0, False: 2.24k] ------------------ 3130| 0| case ARM::VST1d64QPseudo: ------------------ | Branch (3130:5): [True: 0, False: 2.24k] ------------------ 3131| 0| case ARM::VST1d64QPseudoWB_fixed: ------------------ | Branch (3131:5): [True: 0, False: 2.24k] ------------------ 3132| 0| case ARM::VST1d64QPseudoWB_register: ------------------ | Branch (3132:5): [True: 0, False: 2.24k] ------------------ 3133| 0| case ARM::VST1d64TPseudo: ------------------ | Branch (3133:5): [True: 0, False: 2.24k] ------------------ 3134| 0| case ARM::VST1d64TPseudoWB_fixed: ------------------ | Branch (3134:5): [True: 0, False: 2.24k] ------------------ 3135| 0| case ARM::VST1d64TPseudoWB_register: ------------------ | Branch (3135:5): [True: 0, False: 2.24k] ------------------ 3136| 0| case ARM::VST2LNd16Pseudo: ------------------ | Branch (3136:5): [True: 0, False: 2.24k] ------------------ 3137| 0| case ARM::VST2LNd16Pseudo_UPD: ------------------ | Branch (3137:5): [True: 0, False: 2.24k] ------------------ 3138| 0| case ARM::VST2LNd32Pseudo: ------------------ | Branch (3138:5): [True: 0, False: 2.24k] ------------------ 3139| 0| case ARM::VST2LNd32Pseudo_UPD: ------------------ | Branch (3139:5): [True: 0, False: 2.24k] ------------------ 3140| 0| case ARM::VST2LNd8Pseudo: ------------------ | Branch (3140:5): [True: 0, False: 2.24k] ------------------ 3141| 0| case ARM::VST2LNd8Pseudo_UPD: ------------------ | Branch (3141:5): [True: 0, False: 2.24k] ------------------ 3142| 0| case ARM::VST2LNq16Pseudo: ------------------ | Branch (3142:5): [True: 0, False: 2.24k] ------------------ 3143| 0| case ARM::VST2LNq16Pseudo_UPD: ------------------ | Branch (3143:5): [True: 0, False: 2.24k] ------------------ 3144| 0| case ARM::VST2LNq32Pseudo: ------------------ | Branch (3144:5): [True: 0, False: 2.24k] ------------------ 3145| 0| case ARM::VST2LNq32Pseudo_UPD: ------------------ | Branch (3145:5): [True: 0, False: 2.24k] ------------------ 3146| 0| case ARM::VST2q16Pseudo: ------------------ | Branch (3146:5): [True: 0, False: 2.24k] ------------------ 3147| 0| case ARM::VST2q16PseudoWB_fixed: ------------------ | Branch (3147:5): [True: 0, False: 2.24k] ------------------ 3148| 0| case ARM::VST2q16PseudoWB_register: ------------------ | Branch (3148:5): [True: 0, False: 2.24k] ------------------ 3149| 0| case ARM::VST2q32Pseudo: ------------------ | Branch (3149:5): [True: 0, False: 2.24k] ------------------ 3150| 0| case ARM::VST2q32PseudoWB_fixed: ------------------ | Branch (3150:5): [True: 0, False: 2.24k] ------------------ 3151| 0| case ARM::VST2q32PseudoWB_register: ------------------ | Branch (3151:5): [True: 0, False: 2.24k] ------------------ 3152| 0| case ARM::VST2q8Pseudo: ------------------ | Branch (3152:5): [True: 0, False: 2.24k] ------------------ 3153| 0| case ARM::VST2q8PseudoWB_fixed: ------------------ | Branch (3153:5): [True: 0, False: 2.24k] ------------------ 3154| 0| case ARM::VST2q8PseudoWB_register: ------------------ | Branch (3154:5): [True: 0, False: 2.24k] ------------------ 3155| 0| case ARM::VST3LNd16Pseudo: ------------------ | Branch (3155:5): [True: 0, False: 2.24k] ------------------ 3156| 0| case ARM::VST3LNd16Pseudo_UPD: ------------------ | Branch (3156:5): [True: 0, False: 2.24k] ------------------ 3157| 0| case ARM::VST3LNd32Pseudo: ------------------ | Branch (3157:5): [True: 0, False: 2.24k] ------------------ 3158| 0| case ARM::VST3LNd32Pseudo_UPD: ------------------ | Branch (3158:5): [True: 0, False: 2.24k] ------------------ 3159| 0| case ARM::VST3LNd8Pseudo: ------------------ | Branch (3159:5): [True: 0, False: 2.24k] ------------------ 3160| 0| case ARM::VST3LNd8Pseudo_UPD: ------------------ | Branch (3160:5): [True: 0, False: 2.24k] ------------------ 3161| 0| case ARM::VST3LNq16Pseudo: ------------------ | Branch (3161:5): [True: 0, False: 2.24k] ------------------ 3162| 0| case ARM::VST3LNq16Pseudo_UPD: ------------------ | Branch (3162:5): [True: 0, False: 2.24k] ------------------ 3163| 0| case ARM::VST3LNq32Pseudo: ------------------ | Branch (3163:5): [True: 0, False: 2.24k] ------------------ 3164| 0| case ARM::VST3LNq32Pseudo_UPD: ------------------ | Branch (3164:5): [True: 0, False: 2.24k] ------------------ 3165| 0| case ARM::VST3d16Pseudo: ------------------ | Branch (3165:5): [True: 0, False: 2.24k] ------------------ 3166| 0| case ARM::VST3d16Pseudo_UPD: ------------------ | Branch (3166:5): [True: 0, False: 2.24k] ------------------ 3167| 0| case ARM::VST3d32Pseudo: ------------------ | Branch (3167:5): [True: 0, False: 2.24k] ------------------ 3168| 0| case ARM::VST3d32Pseudo_UPD: ------------------ | Branch (3168:5): [True: 0, False: 2.24k] ------------------ 3169| 0| case ARM::VST3d8Pseudo: ------------------ | Branch (3169:5): [True: 0, False: 2.24k] ------------------ 3170| 0| case ARM::VST3d8Pseudo_UPD: ------------------ | Branch (3170:5): [True: 0, False: 2.24k] ------------------ 3171| 0| case ARM::VST3q16Pseudo_UPD: ------------------ | Branch (3171:5): [True: 0, False: 2.24k] ------------------ 3172| 0| case ARM::VST3q16oddPseudo: ------------------ | Branch (3172:5): [True: 0, False: 2.24k] ------------------ 3173| 0| case ARM::VST3q16oddPseudo_UPD: ------------------ | Branch (3173:5): [True: 0, False: 2.24k] ------------------ 3174| 0| case ARM::VST3q32Pseudo_UPD: ------------------ | Branch (3174:5): [True: 0, False: 2.24k] ------------------ 3175| 0| case ARM::VST3q32oddPseudo: ------------------ | Branch (3175:5): [True: 0, False: 2.24k] ------------------ 3176| 0| case ARM::VST3q32oddPseudo_UPD: ------------------ | Branch (3176:5): [True: 0, False: 2.24k] ------------------ 3177| 0| case ARM::VST3q8Pseudo_UPD: ------------------ | Branch (3177:5): [True: 0, False: 2.24k] ------------------ 3178| 0| case ARM::VST3q8oddPseudo: ------------------ | Branch (3178:5): [True: 0, False: 2.24k] ------------------ 3179| 0| case ARM::VST3q8oddPseudo_UPD: ------------------ | Branch (3179:5): [True: 0, False: 2.24k] ------------------ 3180| 0| case ARM::VST4LNd16Pseudo: ------------------ | Branch (3180:5): [True: 0, False: 2.24k] ------------------ 3181| 0| case ARM::VST4LNd16Pseudo_UPD: ------------------ | Branch (3181:5): [True: 0, False: 2.24k] ------------------ 3182| 0| case ARM::VST4LNd32Pseudo: ------------------ | Branch (3182:5): [True: 0, False: 2.24k] ------------------ 3183| 0| case ARM::VST4LNd32Pseudo_UPD: ------------------ | Branch (3183:5): [True: 0, False: 2.24k] ------------------ 3184| 0| case ARM::VST4LNd8Pseudo: ------------------ | Branch (3184:5): [True: 0, False: 2.24k] ------------------ 3185| 0| case ARM::VST4LNd8Pseudo_UPD: ------------------ | Branch (3185:5): [True: 0, False: 2.24k] ------------------ 3186| 0| case ARM::VST4LNq16Pseudo: ------------------ | Branch (3186:5): [True: 0, False: 2.24k] ------------------ 3187| 0| case ARM::VST4LNq16Pseudo_UPD: ------------------ | Branch (3187:5): [True: 0, False: 2.24k] ------------------ 3188| 0| case ARM::VST4LNq32Pseudo: ------------------ | Branch (3188:5): [True: 0, False: 2.24k] ------------------ 3189| 0| case ARM::VST4LNq32Pseudo_UPD: ------------------ | Branch (3189:5): [True: 0, False: 2.24k] ------------------ 3190| 0| case ARM::VST4d16Pseudo: ------------------ | Branch (3190:5): [True: 0, False: 2.24k] ------------------ 3191| 0| case ARM::VST4d16Pseudo_UPD: ------------------ | Branch (3191:5): [True: 0, False: 2.24k] ------------------ 3192| 0| case ARM::VST4d32Pseudo: ------------------ | Branch (3192:5): [True: 0, False: 2.24k] ------------------ 3193| 0| case ARM::VST4d32Pseudo_UPD: ------------------ | Branch (3193:5): [True: 0, False: 2.24k] ------------------ 3194| 0| case ARM::VST4d8Pseudo: ------------------ | Branch (3194:5): [True: 0, False: 2.24k] ------------------ 3195| 0| case ARM::VST4d8Pseudo_UPD: ------------------ | Branch (3195:5): [True: 0, False: 2.24k] ------------------ 3196| 0| case ARM::VST4q16Pseudo_UPD: ------------------ | Branch (3196:5): [True: 0, False: 2.24k] ------------------ 3197| 0| case ARM::VST4q16oddPseudo: ------------------ | Branch (3197:5): [True: 0, False: 2.24k] ------------------ 3198| 0| case ARM::VST4q16oddPseudo_UPD: ------------------ | Branch (3198:5): [True: 0, False: 2.24k] ------------------ 3199| 0| case ARM::VST4q32Pseudo_UPD: ------------------ | Branch (3199:5): [True: 0, False: 2.24k] ------------------ 3200| 0| case ARM::VST4q32oddPseudo: ------------------ | Branch (3200:5): [True: 0, False: 2.24k] ------------------ 3201| 0| case ARM::VST4q32oddPseudo_UPD: ------------------ | Branch (3201:5): [True: 0, False: 2.24k] ------------------ 3202| 0| case ARM::VST4q8Pseudo_UPD: ------------------ | Branch (3202:5): [True: 0, False: 2.24k] ------------------ 3203| 0| case ARM::VST4q8oddPseudo: ------------------ | Branch (3203:5): [True: 0, False: 2.24k] ------------------ 3204| 0| case ARM::VST4q8oddPseudo_UPD: ------------------ | Branch (3204:5): [True: 0, False: 2.24k] ------------------ 3205| 0| case ARM::VSTMQIA: ------------------ | Branch (3205:5): [True: 0, False: 2.24k] ------------------ 3206| 0| case ARM::VTBL3Pseudo: ------------------ | Branch (3206:5): [True: 0, False: 2.24k] ------------------ 3207| 0| case ARM::VTBL4Pseudo: ------------------ | Branch (3207:5): [True: 0, False: 2.24k] ------------------ 3208| 0| case ARM::VTBX3Pseudo: ------------------ | Branch (3208:5): [True: 0, False: 2.24k] ------------------ 3209| 0| case ARM::VTBX4Pseudo: ------------------ | Branch (3209:5): [True: 0, False: 2.24k] ------------------ 3210| 0| case ARM::t2CLREX: ------------------ | Branch (3210:5): [True: 0, False: 2.24k] ------------------ 3211| 0| case ARM::t2DCPS1: ------------------ | Branch (3211:5): [True: 0, False: 2.24k] ------------------ 3212| 0| case ARM::t2DCPS2: ------------------ | Branch (3212:5): [True: 0, False: 2.24k] ------------------ 3213| 0| case ARM::t2DCPS3: ------------------ | Branch (3213:5): [True: 0, False: 2.24k] ------------------ 3214| 0| case ARM::t2Int_eh_sjlj_setjmp: ------------------ | Branch (3214:5): [True: 0, False: 2.24k] ------------------ 3215| 0| case ARM::t2Int_eh_sjlj_setjmp_nofp: ------------------ | Branch (3215:5): [True: 0, False: 2.24k] ------------------ 3216| 0| case ARM::t2SG: ------------------ | Branch (3216:5): [True: 0, False: 2.24k] ------------------ 3217| 0| case ARM::tInt_eh_sjlj_longjmp: ------------------ | Branch (3217:5): [True: 0, False: 2.24k] ------------------ 3218| 0| case ARM::tInt_eh_sjlj_setjmp: ------------------ | Branch (3218:5): [True: 0, False: 2.24k] ------------------ 3219| 0| case ARM::tTRAP: { ------------------ | Branch (3219:5): [True: 0, False: 2.24k] ------------------ 3220| 0| break; 3221| 0| } 3222| 0| case ARM::VRINTAD: ------------------ | Branch (3222:5): [True: 0, False: 2.24k] ------------------ 3223| 0| case ARM::VRINTMD: ------------------ | Branch (3223:5): [True: 0, False: 2.24k] ------------------ 3224| 0| case ARM::VRINTND: ------------------ | Branch (3224:5): [True: 0, False: 2.24k] ------------------ 3225| 0| case ARM::VRINTPD: { ------------------ | Branch (3225:5): [True: 0, False: 2.24k] ------------------ 3226| | // op: Dd 3227| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3228| 0| Value |= (op & UINT64_C(16)) << 18; 3229| 0| Value |= (op & UINT64_C(15)) << 12; 3230| | // op: Dm 3231| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3232| 0| Value |= (op & UINT64_C(16)) << 1; 3233| 0| Value |= op & UINT64_C(15); 3234| 0| break; 3235| 0| } 3236| 0| case ARM::VMAXNMD: ------------------ | Branch (3236:5): [True: 0, False: 2.24k] ------------------ 3237| 0| case ARM::VMINNMD: ------------------ | Branch (3237:5): [True: 0, False: 2.24k] ------------------ 3238| 0| case ARM::VSELEQD: ------------------ | Branch (3238:5): [True: 0, False: 2.24k] ------------------ 3239| 0| case ARM::VSELGED: ------------------ | Branch (3239:5): [True: 0, False: 2.24k] ------------------ 3240| 0| case ARM::VSELGTD: ------------------ | Branch (3240:5): [True: 0, False: 2.24k] ------------------ 3241| 0| case ARM::VSELVSD: { ------------------ | Branch (3241:5): [True: 0, False: 2.24k] ------------------ 3242| | // op: Dd 3243| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3244| 0| Value |= (op & UINT64_C(16)) << 18; 3245| 0| Value |= (op & UINT64_C(15)) << 12; 3246| | // op: Dn 3247| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3248| 0| Value |= (op & UINT64_C(15)) << 16; 3249| 0| Value |= (op & UINT64_C(16)) << 3; 3250| | // op: Dm 3251| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3252| 0| Value |= (op & UINT64_C(16)) << 1; 3253| 0| Value |= op & UINT64_C(15); 3254| 0| break; 3255| 0| } 3256| 0| case ARM::CRC32B: ------------------ | Branch (3256:5): [True: 0, False: 2.24k] ------------------ 3257| 0| case ARM::CRC32CB: ------------------ | Branch (3257:5): [True: 0, False: 2.24k] ------------------ 3258| 0| case ARM::CRC32CH: ------------------ | Branch (3258:5): [True: 0, False: 2.24k] ------------------ 3259| 0| case ARM::CRC32CW: ------------------ | Branch (3259:5): [True: 0, False: 2.24k] ------------------ 3260| 0| case ARM::CRC32H: ------------------ | Branch (3260:5): [True: 0, False: 2.24k] ------------------ 3261| 0| case ARM::CRC32W: { ------------------ | Branch (3261:5): [True: 0, False: 2.24k] ------------------ 3262| | // op: Rd 3263| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3264| 0| Value |= (op & UINT64_C(15)) << 12; 3265| | // op: Rn 3266| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3267| 0| Value |= (op & UINT64_C(15)) << 16; 3268| | // op: Rm 3269| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3270| 0| Value |= op & UINT64_C(15); 3271| 0| break; 3272| 0| } 3273| 0| case ARM::t2MRS_AR: ------------------ | Branch (3273:5): [True: 0, False: 2.24k] ------------------ 3274| 0| case ARM::t2MRSsys_AR: { ------------------ | Branch (3274:5): [True: 0, False: 2.24k] ------------------ 3275| | // op: Rd 3276| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3277| 0| Value |= (op & UINT64_C(15)) << 8; 3278| 0| break; 3279| 0| } 3280| 0| case ARM::t2CLZ: ------------------ | Branch (3280:5): [True: 0, False: 2.24k] ------------------ 3281| 0| case ARM::t2RBIT: ------------------ | Branch (3281:5): [True: 0, False: 2.24k] ------------------ 3282| 0| case ARM::t2REV: ------------------ | Branch (3282:5): [True: 0, False: 2.24k] ------------------ 3283| 0| case ARM::t2REV16: ------------------ | Branch (3283:5): [True: 0, False: 2.24k] ------------------ 3284| 0| case ARM::t2REVSH: { ------------------ | Branch (3284:5): [True: 0, False: 2.24k] ------------------ 3285| | // op: Rd 3286| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3287| 0| Value |= (op & UINT64_C(15)) << 8; 3288| | // op: Rm 3289| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3290| 0| Value |= (op & UINT64_C(15)) << 16; 3291| 0| Value |= op & UINT64_C(15); 3292| 0| break; 3293| 0| } 3294| 0| case ARM::t2MOVsra_flag: ------------------ | Branch (3294:5): [True: 0, False: 2.24k] ------------------ 3295| 0| case ARM::t2MOVsrl_flag: { ------------------ | Branch (3295:5): [True: 0, False: 2.24k] ------------------ 3296| | // op: Rd 3297| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3298| 0| Value |= (op & UINT64_C(15)) << 8; 3299| | // op: Rm 3300| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3301| 0| Value |= op & UINT64_C(15); 3302| 0| break; 3303| 0| } 3304| 8| case ARM::t2SXTB: ------------------ | Branch (3304:5): [True: 8, False: 2.23k] ------------------ 3305| 8| case ARM::t2SXTB16: ------------------ | Branch (3305:5): [True: 0, False: 2.24k] ------------------ 3306| 8| case ARM::t2SXTH: ------------------ | Branch (3306:5): [True: 0, False: 2.24k] ------------------ 3307| 8| case ARM::t2UXTB: ------------------ | Branch (3307:5): [True: 0, False: 2.24k] ------------------ 3308| 8| case ARM::t2UXTB16: ------------------ | Branch (3308:5): [True: 0, False: 2.24k] ------------------ 3309| 8| case ARM::t2UXTH: { ------------------ | Branch (3309:5): [True: 0, False: 2.24k] ------------------ 3310| | // op: Rd 3311| 8| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3312| 8| Value |= (op & UINT64_C(15)) << 8; 3313| | // op: Rm 3314| 8| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3315| 8| Value |= op & UINT64_C(15); 3316| | // op: rot 3317| 8| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3318| 8| Value |= (op & UINT64_C(3)) << 4; 3319| 8| break; 3320| 8| } 3321| 0| case ARM::t2CRC32B: ------------------ | Branch (3321:5): [True: 0, False: 2.24k] ------------------ 3322| 0| case ARM::t2CRC32CB: ------------------ | Branch (3322:5): [True: 0, False: 2.24k] ------------------ 3323| 0| case ARM::t2CRC32CH: ------------------ | Branch (3323:5): [True: 0, False: 2.24k] ------------------ 3324| 0| case ARM::t2CRC32CW: ------------------ | Branch (3324:5): [True: 0, False: 2.24k] ------------------ 3325| 0| case ARM::t2CRC32H: ------------------ | Branch (3325:5): [True: 0, False: 2.24k] ------------------ 3326| 0| case ARM::t2CRC32W: ------------------ | Branch (3326:5): [True: 0, False: 2.24k] ------------------ 3327| 0| case ARM::t2MUL: ------------------ | Branch (3327:5): [True: 0, False: 2.24k] ------------------ 3328| 0| case ARM::t2QADD16: ------------------ | Branch (3328:5): [True: 0, False: 2.24k] ------------------ 3329| 0| case ARM::t2QADD8: ------------------ | Branch (3329:5): [True: 0, False: 2.24k] ------------------ 3330| 0| case ARM::t2QASX: ------------------ | Branch (3330:5): [True: 0, False: 2.24k] ------------------ 3331| 0| case ARM::t2QSAX: ------------------ | Branch (3331:5): [True: 0, False: 2.24k] ------------------ 3332| 0| case ARM::t2QSUB16: ------------------ | Branch (3332:5): [True: 0, False: 2.24k] ------------------ 3333| 0| case ARM::t2QSUB8: ------------------ | Branch (3333:5): [True: 0, False: 2.24k] ------------------ 3334| 0| case ARM::t2SADD16: ------------------ | Branch (3334:5): [True: 0, False: 2.24k] ------------------ 3335| 0| case ARM::t2SADD8: ------------------ | Branch (3335:5): [True: 0, False: 2.24k] ------------------ 3336| 0| case ARM::t2SASX: ------------------ | Branch (3336:5): [True: 0, False: 2.24k] ------------------ 3337| 0| case ARM::t2SDIV: ------------------ | Branch (3337:5): [True: 0, False: 2.24k] ------------------ 3338| 0| case ARM::t2SEL: ------------------ | Branch (3338:5): [True: 0, False: 2.24k] ------------------ 3339| 0| case ARM::t2SHADD16: ------------------ | Branch (3339:5): [True: 0, False: 2.24k] ------------------ 3340| 0| case ARM::t2SHADD8: ------------------ | Branch (3340:5): [True: 0, False: 2.24k] ------------------ 3341| 0| case ARM::t2SHASX: ------------------ | Branch (3341:5): [True: 0, False: 2.24k] ------------------ 3342| 0| case ARM::t2SHSAX: ------------------ | Branch (3342:5): [True: 0, False: 2.24k] ------------------ 3343| 0| case ARM::t2SHSUB16: ------------------ | Branch (3343:5): [True: 0, False: 2.24k] ------------------ 3344| 0| case ARM::t2SHSUB8: ------------------ | Branch (3344:5): [True: 0, False: 2.24k] ------------------ 3345| 0| case ARM::t2SMMUL: ------------------ | Branch (3345:5): [True: 0, False: 2.24k] ------------------ 3346| 0| case ARM::t2SMMULR: ------------------ | Branch (3346:5): [True: 0, False: 2.24k] ------------------ 3347| 0| case ARM::t2SMUAD: ------------------ | Branch (3347:5): [True: 0, False: 2.24k] ------------------ 3348| 0| case ARM::t2SMUADX: ------------------ | Branch (3348:5): [True: 0, False: 2.24k] ------------------ 3349| 0| case ARM::t2SMULBB: ------------------ | Branch (3349:5): [True: 0, False: 2.24k] ------------------ 3350| 0| case ARM::t2SMULBT: ------------------ | Branch (3350:5): [True: 0, False: 2.24k] ------------------ 3351| 0| case ARM::t2SMULTB: ------------------ | Branch (3351:5): [True: 0, False: 2.24k] ------------------ 3352| 0| case ARM::t2SMULTT: ------------------ | Branch (3352:5): [True: 0, False: 2.24k] ------------------ 3353| 0| case ARM::t2SMULWB: ------------------ | Branch (3353:5): [True: 0, False: 2.24k] ------------------ 3354| 0| case ARM::t2SMULWT: ------------------ | Branch (3354:5): [True: 0, False: 2.24k] ------------------ 3355| 0| case ARM::t2SMUSD: ------------------ | Branch (3355:5): [True: 0, False: 2.24k] ------------------ 3356| 0| case ARM::t2SMUSDX: ------------------ | Branch (3356:5): [True: 0, False: 2.24k] ------------------ 3357| 0| case ARM::t2SSAX: ------------------ | Branch (3357:5): [True: 0, False: 2.24k] ------------------ 3358| 0| case ARM::t2SSUB16: ------------------ | Branch (3358:5): [True: 0, False: 2.24k] ------------------ 3359| 0| case ARM::t2SSUB8: ------------------ | Branch (3359:5): [True: 0, False: 2.24k] ------------------ 3360| 0| case ARM::t2UADD16: ------------------ | Branch (3360:5): [True: 0, False: 2.24k] ------------------ 3361| 0| case ARM::t2UADD8: ------------------ | Branch (3361:5): [True: 0, False: 2.24k] ------------------ 3362| 0| case ARM::t2UASX: ------------------ | Branch (3362:5): [True: 0, False: 2.24k] ------------------ 3363| 0| case ARM::t2UDIV: ------------------ | Branch (3363:5): [True: 0, False: 2.24k] ------------------ 3364| 0| case ARM::t2UHADD16: ------------------ | Branch (3364:5): [True: 0, False: 2.24k] ------------------ 3365| 0| case ARM::t2UHADD8: ------------------ | Branch (3365:5): [True: 0, False: 2.24k] ------------------ 3366| 0| case ARM::t2UHASX: ------------------ | Branch (3366:5): [True: 0, False: 2.24k] ------------------ 3367| 0| case ARM::t2UHSAX: ------------------ | Branch (3367:5): [True: 0, False: 2.24k] ------------------ 3368| 0| case ARM::t2UHSUB16: ------------------ | Branch (3368:5): [True: 0, False: 2.24k] ------------------ 3369| 0| case ARM::t2UHSUB8: ------------------ | Branch (3369:5): [True: 0, False: 2.24k] ------------------ 3370| 0| case ARM::t2UQADD16: ------------------ | Branch (3370:5): [True: 0, False: 2.24k] ------------------ 3371| 0| case ARM::t2UQADD8: ------------------ | Branch (3371:5): [True: 0, False: 2.24k] ------------------ 3372| 0| case ARM::t2UQASX: ------------------ | Branch (3372:5): [True: 0, False: 2.24k] ------------------ 3373| 0| case ARM::t2UQSAX: ------------------ | Branch (3373:5): [True: 0, False: 2.24k] ------------------ 3374| 0| case ARM::t2UQSUB16: ------------------ | Branch (3374:5): [True: 0, False: 2.24k] ------------------ 3375| 0| case ARM::t2UQSUB8: ------------------ | Branch (3375:5): [True: 0, False: 2.24k] ------------------ 3376| 0| case ARM::t2USAD8: ------------------ | Branch (3376:5): [True: 0, False: 2.24k] ------------------ 3377| 0| case ARM::t2USAX: ------------------ | Branch (3377:5): [True: 0, False: 2.24k] ------------------ 3378| 0| case ARM::t2USUB16: ------------------ | Branch (3378:5): [True: 0, False: 2.24k] ------------------ 3379| 0| case ARM::t2USUB8: { ------------------ | Branch (3379:5): [True: 0, False: 2.24k] ------------------ 3380| | // op: Rd 3381| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3382| 0| Value |= (op & UINT64_C(15)) << 8; 3383| | // op: Rn 3384| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3385| 0| Value |= (op & UINT64_C(15)) << 16; 3386| | // op: Rm 3387| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3388| 0| Value |= op & UINT64_C(15); 3389| 0| break; 3390| 0| } 3391| 0| case ARM::t2MLA: ------------------ | Branch (3391:5): [True: 0, False: 2.24k] ------------------ 3392| 0| case ARM::t2MLS: ------------------ | Branch (3392:5): [True: 0, False: 2.24k] ------------------ 3393| 0| case ARM::t2SMLABB: ------------------ | Branch (3393:5): [True: 0, False: 2.24k] ------------------ 3394| 0| case ARM::t2SMLABT: ------------------ | Branch (3394:5): [True: 0, False: 2.24k] ------------------ 3395| 0| case ARM::t2SMLAD: ------------------ | Branch (3395:5): [True: 0, False: 2.24k] ------------------ 3396| 0| case ARM::t2SMLADX: ------------------ | Branch (3396:5): [True: 0, False: 2.24k] ------------------ 3397| 0| case ARM::t2SMLATB: ------------------ | Branch (3397:5): [True: 0, False: 2.24k] ------------------ 3398| 0| case ARM::t2SMLATT: ------------------ | Branch (3398:5): [True: 0, False: 2.24k] ------------------ 3399| 0| case ARM::t2SMLAWB: ------------------ | Branch (3399:5): [True: 0, False: 2.24k] ------------------ 3400| 0| case ARM::t2SMLAWT: ------------------ | Branch (3400:5): [True: 0, False: 2.24k] ------------------ 3401| 0| case ARM::t2SMLSD: ------------------ | Branch (3401:5): [True: 0, False: 2.24k] ------------------ 3402| 0| case ARM::t2SMLSDX: ------------------ | Branch (3402:5): [True: 0, False: 2.24k] ------------------ 3403| 0| case ARM::t2SMMLA: ------------------ | Branch (3403:5): [True: 0, False: 2.24k] ------------------ 3404| 0| case ARM::t2SMMLAR: ------------------ | Branch (3404:5): [True: 0, False: 2.24k] ------------------ 3405| 0| case ARM::t2SMMLS: ------------------ | Branch (3405:5): [True: 0, False: 2.24k] ------------------ 3406| 0| case ARM::t2SMMLSR: ------------------ | Branch (3406:5): [True: 0, False: 2.24k] ------------------ 3407| 0| case ARM::t2USADA8: { ------------------ | Branch (3407:5): [True: 0, False: 2.24k] ------------------ 3408| | // op: Rd 3409| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3410| 0| Value |= (op & UINT64_C(15)) << 8; 3411| | // op: Rn 3412| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3413| 0| Value |= (op & UINT64_C(15)) << 16; 3414| | // op: Rm 3415| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3416| 0| Value |= op & UINT64_C(15); 3417| | // op: Ra 3418| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3419| 0| Value |= (op & UINT64_C(15)) << 12; 3420| 0| break; 3421| 0| } 3422| 0| case ARM::t2SXTAB: ------------------ | Branch (3422:5): [True: 0, False: 2.24k] ------------------ 3423| 0| case ARM::t2SXTAB16: ------------------ | Branch (3423:5): [True: 0, False: 2.24k] ------------------ 3424| 0| case ARM::t2SXTAH: ------------------ | Branch (3424:5): [True: 0, False: 2.24k] ------------------ 3425| 0| case ARM::t2UXTAB: ------------------ | Branch (3425:5): [True: 0, False: 2.24k] ------------------ 3426| 0| case ARM::t2UXTAB16: ------------------ | Branch (3426:5): [True: 0, False: 2.24k] ------------------ 3427| 0| case ARM::t2UXTAH: { ------------------ | Branch (3427:5): [True: 0, False: 2.24k] ------------------ 3428| | // op: Rd 3429| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3430| 0| Value |= (op & UINT64_C(15)) << 8; 3431| | // op: Rn 3432| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3433| 0| Value |= (op & UINT64_C(15)) << 16; 3434| | // op: Rm 3435| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3436| 0| Value |= op & UINT64_C(15); 3437| | // op: rot 3438| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3439| 0| Value |= (op & UINT64_C(3)) << 4; 3440| 0| break; 3441| 0| } 3442| 0| case ARM::t2PKHBT: ------------------ | Branch (3442:5): [True: 0, False: 2.24k] ------------------ 3443| 0| case ARM::t2PKHTB: { ------------------ | Branch (3443:5): [True: 0, False: 2.24k] ------------------ 3444| | // op: Rd 3445| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3446| 0| Value |= (op & UINT64_C(15)) << 8; 3447| | // op: Rn 3448| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3449| 0| Value |= (op & UINT64_C(15)) << 16; 3450| | // op: Rm 3451| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3452| 0| Value |= op & UINT64_C(15); 3453| | // op: sh 3454| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3455| 0| Value |= (op & UINT64_C(28)) << 10; 3456| 0| Value |= (op & UINT64_C(3)) << 6; 3457| 0| break; 3458| 0| } 3459| 5| case ARM::t2ADDri12: ------------------ | Branch (3459:5): [True: 5, False: 2.23k] ------------------ 3460| 31| case ARM::t2SUBri12: { ------------------ | Branch (3460:5): [True: 26, False: 2.21k] ------------------ 3461| | // op: Rd 3462| 31| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3463| 31| Value |= (op & UINT64_C(15)) << 8; 3464| | // op: Rn 3465| 31| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3466| 31| Value |= (op & UINT64_C(15)) << 16; 3467| | // op: imm 3468| 31| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3469| 31| Value |= (op & UINT64_C(2048)) << 15; 3470| 31| Value |= (op & UINT64_C(1792)) << 4; 3471| 31| Value |= op & UINT64_C(255); 3472| 31| break; 3473| 5| } 3474| 0| case ARM::t2QADD: ------------------ | Branch (3474:5): [True: 0, False: 2.24k] ------------------ 3475| 0| case ARM::t2QDADD: ------------------ | Branch (3475:5): [True: 0, False: 2.24k] ------------------ 3476| 0| case ARM::t2QDSUB: ------------------ | Branch (3476:5): [True: 0, False: 2.24k] ------------------ 3477| 0| case ARM::t2QSUB: { ------------------ | Branch (3477:5): [True: 0, False: 2.24k] ------------------ 3478| | // op: Rd 3479| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3480| 0| Value |= (op & UINT64_C(15)) << 8; 3481| | // op: Rn 3482| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3483| 0| Value |= (op & UINT64_C(15)) << 16; 3484| | // op: Rm 3485| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3486| 0| Value |= op & UINT64_C(15); 3487| 0| break; 3488| 0| } 3489| 0| case ARM::t2BFI: { ------------------ | Branch (3489:5): [True: 0, False: 2.24k] ------------------ 3490| | // op: Rd 3491| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3492| 0| Value |= (op & UINT64_C(15)) << 8; 3493| | // op: Rn 3494| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3495| 0| Value |= (op & UINT64_C(15)) << 16; 3496| | // op: imm 3497| 0| op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 3498| 0| Value |= (op & UINT64_C(28)) << 10; 3499| 0| Value |= (op & UINT64_C(3)) << 6; 3500| 0| Value |= (op & UINT64_C(992)) >> 5; 3501| 0| break; 3502| 0| } 3503| 0| case ARM::t2SSAT16: ------------------ | Branch (3503:5): [True: 0, False: 2.24k] ------------------ 3504| 0| case ARM::t2USAT16: { ------------------ | Branch (3504:5): [True: 0, False: 2.24k] ------------------ 3505| | // op: Rd 3506| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3507| 0| Value |= (op & UINT64_C(15)) << 8; 3508| | // op: Rn 3509| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3510| 0| Value |= (op & UINT64_C(15)) << 16; 3511| | // op: sat_imm 3512| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3513| 0| Value |= op & UINT64_C(15); 3514| 0| break; 3515| 0| } 3516| 0| case ARM::t2SSAT: ------------------ | Branch (3516:5): [True: 0, False: 2.24k] ------------------ 3517| 0| case ARM::t2USAT: { ------------------ | Branch (3517:5): [True: 0, False: 2.24k] ------------------ 3518| | // op: Rd 3519| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3520| 0| Value |= (op & UINT64_C(15)) << 8; 3521| | // op: Rn 3522| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3523| 0| Value |= (op & UINT64_C(15)) << 16; 3524| | // op: sat_imm 3525| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3526| 0| Value |= op & UINT64_C(31); 3527| | // op: sh 3528| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3529| 0| Value |= (op & UINT64_C(32)) << 16; 3530| 0| Value |= (op & UINT64_C(28)) << 10; 3531| 0| Value |= (op & UINT64_C(3)) << 6; 3532| 0| break; 3533| 0| } 3534| 0| case ARM::t2STREX: { ------------------ | Branch (3534:5): [True: 0, False: 2.24k] ------------------ 3535| | // op: Rd 3536| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3537| 0| Value |= (op & UINT64_C(15)) << 8; 3538| | // op: Rt 3539| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3540| 0| Value |= (op & UINT64_C(15)) << 12; 3541| | // op: addr 3542| 0| op = getT2AddrModeImm0_1020s4OpValue(MI, 2, Fixups, STI); 3543| 0| Value |= (op & UINT64_C(3840)) << 8; 3544| 0| Value |= op & UINT64_C(255); 3545| 0| break; 3546| 0| } 3547| 0| case ARM::t2MRS_M: { ------------------ | Branch (3547:5): [True: 0, False: 2.24k] ------------------ 3548| | // op: Rd 3549| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3550| 0| Value |= (op & UINT64_C(15)) << 8; 3551| | // op: SYSm 3552| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3553| 0| Value |= op & UINT64_C(255); 3554| 0| break; 3555| 0| } 3556| 74| case ARM::t2ADR: { ------------------ | Branch (3556:5): [True: 74, False: 2.16k] ------------------ 3557| | // op: Rd 3558| 74| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3559| 74| Value |= (op & UINT64_C(15)) << 8; 3560| | // op: addr 3561| 74| op = getT2AdrLabelOpValue(MI, 1, Fixups, STI); 3562| 74| Value |= (op & UINT64_C(2048)) << 15; 3563| 74| Value |= (op & UINT64_C(4096)) << 11; 3564| 74| Value |= (op & UINT64_C(4096)) << 9; 3565| 74| Value |= (op & UINT64_C(1792)) << 4; 3566| 74| Value |= op & UINT64_C(255); 3567| 74| break; 3568| 0| } 3569| 0| case ARM::t2BFC: { ------------------ | Branch (3569:5): [True: 0, False: 2.24k] ------------------ 3570| | // op: Rd 3571| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3572| 0| Value |= (op & UINT64_C(15)) << 8; 3573| | // op: imm 3574| 0| op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 3575| 0| Value |= (op & UINT64_C(28)) << 10; 3576| 0| Value |= (op & UINT64_C(3)) << 6; 3577| 0| Value |= (op & UINT64_C(992)) >> 5; 3578| 0| break; 3579| 0| } 3580| 0| case ARM::t2MOVi16: { ------------------ | Branch (3580:5): [True: 0, False: 2.24k] ------------------ 3581| | // op: Rd 3582| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3583| 0| Value |= (op & UINT64_C(15)) << 8; 3584| | // op: imm 3585| 0| op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 3586| 0| Value |= (op & UINT64_C(2048)) << 15; 3587| 0| Value |= (op & UINT64_C(61440)) << 4; 3588| 0| Value |= (op & UINT64_C(1792)) << 4; 3589| 0| Value |= op & UINT64_C(255); 3590| 0| break; 3591| 0| } 3592| 0| case ARM::t2MOVTi16: { ------------------ | Branch (3592:5): [True: 0, False: 2.24k] ------------------ 3593| | // op: Rd 3594| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3595| 0| Value |= (op & UINT64_C(15)) << 8; 3596| | // op: imm 3597| 0| op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 3598| 0| Value |= (op & UINT64_C(2048)) << 15; 3599| 0| Value |= (op & UINT64_C(61440)) << 4; 3600| 0| Value |= (op & UINT64_C(1792)) << 4; 3601| 0| Value |= op & UINT64_C(255); 3602| 0| break; 3603| 0| } 3604| 0| case ARM::t2SBFX: ------------------ | Branch (3604:5): [True: 0, False: 2.24k] ------------------ 3605| 0| case ARM::t2UBFX: { ------------------ | Branch (3605:5): [True: 0, False: 2.24k] ------------------ 3606| | // op: Rd 3607| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3608| 0| Value |= (op & UINT64_C(15)) << 8; 3609| | // op: msb 3610| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3611| 0| Value |= op & UINT64_C(31); 3612| | // op: lsb 3613| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3614| 0| Value |= (op & UINT64_C(28)) << 10; 3615| 0| Value |= (op & UINT64_C(3)) << 6; 3616| | // op: Rn 3617| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3618| 0| Value |= (op & UINT64_C(15)) << 16; 3619| 0| break; 3620| 0| } 3621| 55| case ARM::tADR: { ------------------ | Branch (3621:5): [True: 55, False: 2.18k] ------------------ 3622| | // op: Rd 3623| 55| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3624| 55| Value |= (op & UINT64_C(7)) << 8; 3625| | // op: addr 3626| 55| op = getThumbAdrLabelOpValue(MI, 1, Fixups, STI); 3627| 55| Value |= op & UINT64_C(255); 3628| 55| break; 3629| 0| } 3630| 0| case ARM::tMOVi8: { ------------------ | Branch (3630:5): [True: 0, False: 2.24k] ------------------ 3631| | // op: Rd 3632| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3633| 0| Value |= (op & UINT64_C(7)) << 8; 3634| | // op: imm8 3635| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3636| 0| Value |= op & UINT64_C(255); 3637| 0| break; 3638| 0| } 3639| 0| case ARM::tMOVr: { ------------------ | Branch (3639:5): [True: 0, False: 2.24k] ------------------ 3640| | // op: Rd 3641| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3642| 0| Value |= (op & UINT64_C(8)) << 4; 3643| 0| Value |= op & UINT64_C(7); 3644| | // op: Rm 3645| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3646| 0| Value |= (op & UINT64_C(15)) << 3; 3647| 0| break; 3648| 0| } 3649| 0| case ARM::t2STLEX: { ------------------ | Branch (3649:5): [True: 0, False: 2.24k] ------------------ 3650| | // op: Rd 3651| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3652| 0| Value |= op & UINT64_C(15); 3653| | // op: Rt 3654| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3655| 0| Value |= (op & UINT64_C(15)) << 12; 3656| | // op: addr 3657| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3658| 0| Value |= (op & UINT64_C(15)) << 16; 3659| 0| break; 3660| 0| } 3661| 0| case ARM::t2STLEXB: ------------------ | Branch (3661:5): [True: 0, False: 2.24k] ------------------ 3662| 0| case ARM::t2STLEXH: ------------------ | Branch (3662:5): [True: 0, False: 2.24k] ------------------ 3663| 0| case ARM::t2STREXB: ------------------ | Branch (3663:5): [True: 0, False: 2.24k] ------------------ 3664| 0| case ARM::t2STREXH: { ------------------ | Branch (3664:5): [True: 0, False: 2.24k] ------------------ 3665| | // op: Rd 3666| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3667| 0| Value |= op & UINT64_C(15); 3668| | // op: addr 3669| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3670| 0| Value |= (op & UINT64_C(15)) << 16; 3671| | // op: Rt 3672| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3673| 0| Value |= (op & UINT64_C(15)) << 12; 3674| 0| break; 3675| 0| } 3676| 0| case ARM::t2STLEXD: ------------------ | Branch (3676:5): [True: 0, False: 2.24k] ------------------ 3677| 0| case ARM::t2STREXD: { ------------------ | Branch (3677:5): [True: 0, False: 2.24k] ------------------ 3678| | // op: Rd 3679| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3680| 0| Value |= op & UINT64_C(15); 3681| | // op: addr 3682| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3683| 0| Value |= (op & UINT64_C(15)) << 16; 3684| | // op: Rt 3685| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3686| 0| Value |= (op & UINT64_C(15)) << 12; 3687| | // op: Rt2 3688| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3689| 0| Value |= (op & UINT64_C(15)) << 8; 3690| 0| break; 3691| 0| } 3692| 0| case ARM::tMOVSr: { ------------------ | Branch (3692:5): [True: 0, False: 2.24k] ------------------ 3693| | // op: Rd 3694| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3695| 0| Value |= op & UINT64_C(7); 3696| | // op: Rm 3697| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3698| 0| Value |= (op & UINT64_C(7)) << 3; 3699| 0| break; 3700| 0| } 3701| 0| case ARM::tADDi3: ------------------ | Branch (3701:5): [True: 0, False: 2.24k] ------------------ 3702| 0| case ARM::tSUBi3: { ------------------ | Branch (3702:5): [True: 0, False: 2.24k] ------------------ 3703| | // op: Rd 3704| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3705| 0| Value |= op & UINT64_C(7); 3706| | // op: Rm 3707| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3708| 0| Value |= (op & UINT64_C(7)) << 3; 3709| | // op: imm3 3710| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3711| 0| Value |= (op & UINT64_C(7)) << 6; 3712| 0| break; 3713| 0| } 3714| 0| case ARM::tASRri: ------------------ | Branch (3714:5): [True: 0, False: 2.24k] ------------------ 3715| 0| case ARM::tLSLri: ------------------ | Branch (3715:5): [True: 0, False: 2.24k] ------------------ 3716| 0| case ARM::tLSRri: { ------------------ | Branch (3716:5): [True: 0, False: 2.24k] ------------------ 3717| | // op: Rd 3718| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3719| 0| Value |= op & UINT64_C(7); 3720| | // op: Rm 3721| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3722| 0| Value |= (op & UINT64_C(7)) << 3; 3723| | // op: imm5 3724| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3725| 0| Value |= (op & UINT64_C(31)) << 6; 3726| 0| break; 3727| 0| } 3728| 0| case ARM::tMUL: ------------------ | Branch (3728:5): [True: 0, False: 2.24k] ------------------ 3729| 0| case ARM::tMVN: ------------------ | Branch (3729:5): [True: 0, False: 2.24k] ------------------ 3730| 0| case ARM::tRSB: { ------------------ | Branch (3730:5): [True: 0, False: 2.24k] ------------------ 3731| | // op: Rd 3732| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3733| 0| Value |= op & UINT64_C(7); 3734| | // op: Rn 3735| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3736| 0| Value |= (op & UINT64_C(7)) << 3; 3737| 0| break; 3738| 0| } 3739| 0| case ARM::t2SMLALBB: ------------------ | Branch (3739:5): [True: 0, False: 2.24k] ------------------ 3740| 0| case ARM::t2SMLALBT: ------------------ | Branch (3740:5): [True: 0, False: 2.24k] ------------------ 3741| 0| case ARM::t2SMLALD: ------------------ | Branch (3741:5): [True: 0, False: 2.24k] ------------------ 3742| 0| case ARM::t2SMLALDX: ------------------ | Branch (3742:5): [True: 0, False: 2.24k] ------------------ 3743| 0| case ARM::t2SMLALTB: ------------------ | Branch (3743:5): [True: 0, False: 2.24k] ------------------ 3744| 0| case ARM::t2SMLALTT: ------------------ | Branch (3744:5): [True: 0, False: 2.24k] ------------------ 3745| 0| case ARM::t2SMLSLD: { ------------------ | Branch (3745:5): [True: 0, False: 2.24k] ------------------ 3746| | // op: Rd 3747| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3748| 0| Value |= (op & UINT64_C(15)) << 8; 3749| | // op: Rn 3750| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3751| 0| Value |= (op & UINT64_C(15)) << 16; 3752| | // op: Rm 3753| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3754| 0| Value |= op & UINT64_C(15); 3755| | // op: Ra 3756| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3757| 0| Value |= (op & UINT64_C(15)) << 12; 3758| 0| break; 3759| 0| } 3760| 0| case ARM::t2SMLSLDX: { ------------------ | Branch (3760:5): [True: 0, False: 2.24k] ------------------ 3761| | // op: Rd 3762| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3763| 0| Value |= (op & UINT64_C(15)) << 8; 3764| | // op: Rn 3765| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3766| 0| Value |= (op & UINT64_C(15)) << 16; 3767| | // op: Rm 3768| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3769| 0| Value |= op & UINT64_C(15); 3770| | // op: Ra 3771| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3772| 0| Value |= (op & UINT64_C(15)) << 12; 3773| 0| break; 3774| 0| } 3775| 0| case ARM::t2SMLAL: ------------------ | Branch (3775:5): [True: 0, False: 2.24k] ------------------ 3776| 0| case ARM::t2SMULL: ------------------ | Branch (3776:5): [True: 0, False: 2.24k] ------------------ 3777| 0| case ARM::t2UMAAL: ------------------ | Branch (3777:5): [True: 0, False: 2.24k] ------------------ 3778| 0| case ARM::t2UMLAL: ------------------ | Branch (3778:5): [True: 0, False: 2.24k] ------------------ 3779| 0| case ARM::t2UMULL: { ------------------ | Branch (3779:5): [True: 0, False: 2.24k] ------------------ 3780| | // op: RdLo 3781| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3782| 0| Value |= (op & UINT64_C(15)) << 12; 3783| | // op: RdHi 3784| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3785| 0| Value |= (op & UINT64_C(15)) << 8; 3786| | // op: Rn 3787| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3788| 0| Value |= (op & UINT64_C(15)) << 16; 3789| | // op: Rm 3790| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3791| 0| Value |= op & UINT64_C(15); 3792| 0| break; 3793| 0| } 3794| 0| case ARM::tADDi8: ------------------ | Branch (3794:5): [True: 0, False: 2.24k] ------------------ 3795| 3| case ARM::tSUBi8: { ------------------ | Branch (3795:5): [True: 3, False: 2.23k] ------------------ 3796| | // op: Rdn 3797| 3| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3798| 3| Value |= (op & UINT64_C(7)) << 8; 3799| | // op: imm8 3800| 3| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3801| 3| Value |= op & UINT64_C(255); 3802| 3| break; 3803| 0| } 3804| 0| case ARM::tADDrSP: { ------------------ | Branch (3804:5): [True: 0, False: 2.24k] ------------------ 3805| | // op: Rdn 3806| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3807| 0| Value |= (op & UINT64_C(8)) << 4; 3808| 0| Value |= op & UINT64_C(7); 3809| 0| break; 3810| 0| } 3811| 0| case ARM::tADDhirr: { ------------------ | Branch (3811:5): [True: 0, False: 2.24k] ------------------ 3812| | // op: Rdn 3813| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3814| 0| Value |= (op & UINT64_C(8)) << 4; 3815| 0| Value |= op & UINT64_C(7); 3816| | // op: Rm 3817| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3818| 0| Value |= (op & UINT64_C(15)) << 3; 3819| 0| break; 3820| 0| } 3821| 0| case ARM::tADC: ------------------ | Branch (3821:5): [True: 0, False: 2.24k] ------------------ 3822| 0| case ARM::tAND: ------------------ | Branch (3822:5): [True: 0, False: 2.24k] ------------------ 3823| 2| case ARM::tASRrr: ------------------ | Branch (3823:5): [True: 2, False: 2.23k] ------------------ 3824| 2| case ARM::tBIC: ------------------ | Branch (3824:5): [True: 0, False: 2.24k] ------------------ 3825| 2| case ARM::tEOR: ------------------ | Branch (3825:5): [True: 0, False: 2.24k] ------------------ 3826| 35| case ARM::tLSLrr: ------------------ | Branch (3826:5): [True: 33, False: 2.20k] ------------------ 3827| 62| case ARM::tLSRrr: ------------------ | Branch (3827:5): [True: 27, False: 2.21k] ------------------ 3828| 62| case ARM::tORR: ------------------ | Branch (3828:5): [True: 0, False: 2.24k] ------------------ 3829| 62| case ARM::tROR: ------------------ | Branch (3829:5): [True: 0, False: 2.24k] ------------------ 3830| 62| case ARM::tSBC: { ------------------ | Branch (3830:5): [True: 0, False: 2.24k] ------------------ 3831| | // op: Rdn 3832| 62| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3833| 62| Value |= op & UINT64_C(7); 3834| | // op: Rm 3835| 62| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3836| 62| Value |= (op & UINT64_C(7)) << 3; 3837| 62| break; 3838| 62| } 3839| 0| case ARM::tBX: ------------------ | Branch (3839:5): [True: 0, False: 2.24k] ------------------ 3840| 0| case ARM::tBXNS: { ------------------ | Branch (3840:5): [True: 0, False: 2.24k] ------------------ 3841| | // op: Rm 3842| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3843| 0| Value |= (op & UINT64_C(15)) << 3; 3844| 0| break; 3845| 0| } 3846| 0| case ARM::tCMPhir: { ------------------ | Branch (3846:5): [True: 0, False: 2.24k] ------------------ 3847| | // op: Rm 3848| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3849| 0| Value |= (op & UINT64_C(15)) << 3; 3850| | // op: Rn 3851| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3852| 0| Value |= (op & UINT64_C(8)) << 4; 3853| 0| Value |= op & UINT64_C(7); 3854| 0| break; 3855| 0| } 3856| 0| case ARM::tREV: ------------------ | Branch (3856:5): [True: 0, False: 2.24k] ------------------ 3857| 0| case ARM::tREV16: ------------------ | Branch (3857:5): [True: 0, False: 2.24k] ------------------ 3858| 0| case ARM::tREVSH: ------------------ | Branch (3858:5): [True: 0, False: 2.24k] ------------------ 3859| 0| case ARM::tSXTB: ------------------ | Branch (3859:5): [True: 0, False: 2.24k] ------------------ 3860| 0| case ARM::tSXTH: ------------------ | Branch (3860:5): [True: 0, False: 2.24k] ------------------ 3861| 0| case ARM::tUXTB: ------------------ | Branch (3861:5): [True: 0, False: 2.24k] ------------------ 3862| 0| case ARM::tUXTH: { ------------------ | Branch (3862:5): [True: 0, False: 2.24k] ------------------ 3863| | // op: Rm 3864| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3865| 0| Value |= (op & UINT64_C(7)) << 3; 3866| | // op: Rd 3867| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3868| 0| Value |= op & UINT64_C(7); 3869| 0| break; 3870| 0| } 3871| 0| case ARM::tCMNz: ------------------ | Branch (3871:5): [True: 0, False: 2.24k] ------------------ 3872| 0| case ARM::tCMPr: ------------------ | Branch (3872:5): [True: 0, False: 2.24k] ------------------ 3873| 0| case ARM::tTST: { ------------------ | Branch (3873:5): [True: 0, False: 2.24k] ------------------ 3874| | // op: Rm 3875| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3876| 0| Value |= (op & UINT64_C(7)) << 3; 3877| | // op: Rn 3878| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3879| 0| Value |= op & UINT64_C(7); 3880| 0| break; 3881| 0| } 3882| 0| case ARM::tADDspr: { ------------------ | Branch (3882:5): [True: 0, False: 2.24k] ------------------ 3883| | // op: Rm 3884| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3885| 0| Value |= (op & UINT64_C(15)) << 3; 3886| 0| break; 3887| 0| } 3888| 0| case ARM::tADDrr: ------------------ | Branch (3888:5): [True: 0, False: 2.24k] ------------------ 3889| 62| case ARM::tSUBrr: { ------------------ | Branch (3889:5): [True: 62, False: 2.17k] ------------------ 3890| | // op: Rm 3891| 62| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3892| 62| Value |= (op & UINT64_C(7)) << 6; 3893| | // op: Rn 3894| 62| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3895| 62| Value |= (op & UINT64_C(7)) << 3; 3896| | // op: Rd 3897| 62| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3898| 62| Value |= op & UINT64_C(7); 3899| 62| break; 3900| 0| } 3901| 0| case ARM::RFEDA: ------------------ | Branch (3901:5): [True: 0, False: 2.24k] ------------------ 3902| 0| case ARM::RFEDA_UPD: ------------------ | Branch (3902:5): [True: 0, False: 2.24k] ------------------ 3903| 0| case ARM::RFEDB: ------------------ | Branch (3903:5): [True: 0, False: 2.24k] ------------------ 3904| 0| case ARM::RFEDB_UPD: ------------------ | Branch (3904:5): [True: 0, False: 2.24k] ------------------ 3905| 0| case ARM::RFEIA: ------------------ | Branch (3905:5): [True: 0, False: 2.24k] ------------------ 3906| 0| case ARM::RFEIA_UPD: ------------------ | Branch (3906:5): [True: 0, False: 2.24k] ------------------ 3907| 0| case ARM::RFEIB: ------------------ | Branch (3907:5): [True: 0, False: 2.24k] ------------------ 3908| 0| case ARM::RFEIB_UPD: ------------------ | Branch (3908:5): [True: 0, False: 2.24k] ------------------ 3909| 0| case ARM::t2RFEDB: ------------------ | Branch (3909:5): [True: 0, False: 2.24k] ------------------ 3910| 0| case ARM::t2RFEDBW: ------------------ | Branch (3910:5): [True: 0, False: 2.24k] ------------------ 3911| 0| case ARM::t2RFEIA: ------------------ | Branch (3911:5): [True: 0, False: 2.24k] ------------------ 3912| 0| case ARM::t2RFEIAW: { ------------------ | Branch (3912:5): [True: 0, False: 2.24k] ------------------ 3913| | // op: Rn 3914| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3915| 0| Value |= (op & UINT64_C(15)) << 16; 3916| 0| break; 3917| 0| } 3918| 0| case ARM::t2CMNzrr: ------------------ | Branch (3918:5): [True: 0, False: 2.24k] ------------------ 3919| 0| case ARM::t2CMPrr: ------------------ | Branch (3919:5): [True: 0, False: 2.24k] ------------------ 3920| 0| case ARM::t2TBB: ------------------ | Branch (3920:5): [True: 0, False: 2.24k] ------------------ 3921| 0| case ARM::t2TBH: ------------------ | Branch (3921:5): [True: 0, False: 2.24k] ------------------ 3922| 0| case ARM::t2TEQrr: ------------------ | Branch (3922:5): [True: 0, False: 2.24k] ------------------ 3923| 0| case ARM::t2TSTrr: { ------------------ | Branch (3923:5): [True: 0, False: 2.24k] ------------------ 3924| | // op: Rn 3925| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3926| 0| Value |= (op & UINT64_C(15)) << 16; 3927| | // op: Rm 3928| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3929| 0| Value |= op & UINT64_C(15); 3930| 0| break; 3931| 0| } 3932| 0| case ARM::t2CMNzrs: ------------------ | Branch (3932:5): [True: 0, False: 2.24k] ------------------ 3933| 0| case ARM::t2CMPrs: ------------------ | Branch (3933:5): [True: 0, False: 2.24k] ------------------ 3934| 0| case ARM::t2TEQrs: ------------------ | Branch (3934:5): [True: 0, False: 2.24k] ------------------ 3935| 0| case ARM::t2TSTrs: { ------------------ | Branch (3935:5): [True: 0, False: 2.24k] ------------------ 3936| | // op: Rn 3937| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3938| 0| Value |= (op & UINT64_C(15)) << 16; 3939| | // op: ShiftedRm 3940| 0| op = getT2SORegOpValue(MI, 1, Fixups, STI); 3941| 0| Value |= (op & UINT64_C(3584)) << 3; 3942| 0| Value |= (op & UINT64_C(480)) >> 1; 3943| 0| Value |= op & UINT64_C(15); 3944| 0| break; 3945| 0| } 3946| 0| case ARM::t2CMNri: ------------------ | Branch (3946:5): [True: 0, False: 2.24k] ------------------ 3947| 0| case ARM::t2CMPri: ------------------ | Branch (3947:5): [True: 0, False: 2.24k] ------------------ 3948| 0| case ARM::t2TEQri: ------------------ | Branch (3948:5): [True: 0, False: 2.24k] ------------------ 3949| 0| case ARM::t2TSTri: { ------------------ | Branch (3949:5): [True: 0, False: 2.24k] ------------------ 3950| | // op: Rn 3951| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3952| 0| Value |= (op & UINT64_C(15)) << 16; 3953| | // op: imm 3954| 0| op = getT2SOImmOpValue(MI, 1, Fixups, STI); 3955| 0| Value |= (op & UINT64_C(2048)) << 15; 3956| 0| Value |= (op & UINT64_C(1792)) << 4; 3957| 0| Value |= op & UINT64_C(255); 3958| 0| break; 3959| 0| } 3960| 0| case ARM::t2STMDB: ------------------ | Branch (3960:5): [True: 0, False: 2.24k] ------------------ 3961| 0| case ARM::t2STMIA: { ------------------ | Branch (3961:5): [True: 0, False: 2.24k] ------------------ 3962| | // op: Rn 3963| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3964| 0| Value |= (op & UINT64_C(15)) << 16; 3965| | // op: regs 3966| 0| op = getRegisterListOpValue(MI, 3, Fixups, STI); 3967| 0| Value |= op & UINT64_C(16384); 3968| 0| Value |= op & UINT64_C(8191); 3969| 0| break; 3970| 0| } 3971| 0| case ARM::t2LDMDB: ------------------ | Branch (3971:5): [True: 0, False: 2.24k] ------------------ 3972| 0| case ARM::t2LDMIA: { ------------------ | Branch (3972:5): [True: 0, False: 2.24k] ------------------ 3973| | // op: Rn 3974| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3975| 0| Value |= (op & UINT64_C(15)) << 16; 3976| | // op: regs 3977| 0| op = getRegisterListOpValue(MI, 3, Fixups, STI); 3978| 0| Value |= op & UINT64_C(65535); 3979| 0| break; 3980| 0| } 3981| 0| case ARM::tCMPi8: { ------------------ | Branch (3981:5): [True: 0, False: 2.24k] ------------------ 3982| | // op: Rn 3983| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3984| 0| Value |= (op & UINT64_C(7)) << 8; 3985| | // op: imm8 3986| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3987| 0| Value |= op & UINT64_C(255); 3988| 0| break; 3989| 0| } 3990| 0| case ARM::tLDMIA: { ------------------ | Branch (3990:5): [True: 0, False: 2.24k] ------------------ 3991| | // op: Rn 3992| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3993| 0| Value |= (op & UINT64_C(7)) << 8; 3994| | // op: regs 3995| 0| op = getRegisterListOpValue(MI, 3, Fixups, STI); 3996| 0| Value |= op & UINT64_C(255); 3997| 0| break; 3998| 0| } 3999| 0| case ARM::t2TT: ------------------ | Branch (3999:5): [True: 0, False: 2.24k] ------------------ 4000| 0| case ARM::t2TTA: ------------------ | Branch (4000:5): [True: 0, False: 2.24k] ------------------ 4001| 0| case ARM::t2TTAT: ------------------ | Branch (4001:5): [True: 0, False: 2.24k] ------------------ 4002| 0| case ARM::t2TTT: { ------------------ | Branch (4002:5): [True: 0, False: 2.24k] ------------------ 4003| | // op: Rn 4004| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4005| 0| Value |= (op & UINT64_C(15)) << 16; 4006| | // op: Rt 4007| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4008| 0| Value |= (op & UINT64_C(15)) << 8; 4009| 0| break; 4010| 0| } 4011| 0| case ARM::t2STMDB_UPD: ------------------ | Branch (4011:5): [True: 0, False: 2.24k] ------------------ 4012| 0| case ARM::t2STMIA_UPD: { ------------------ | Branch (4012:5): [True: 0, False: 2.24k] ------------------ 4013| | // op: Rn 4014| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4015| 0| Value |= (op & UINT64_C(15)) << 16; 4016| | // op: regs 4017| 0| op = getRegisterListOpValue(MI, 4, Fixups, STI); 4018| 0| Value |= op & UINT64_C(16384); 4019| 0| Value |= op & UINT64_C(8191); 4020| 0| break; 4021| 0| } 4022| 0| case ARM::t2LDMDB_UPD: ------------------ | Branch (4022:5): [True: 0, False: 2.24k] ------------------ 4023| 0| case ARM::t2LDMIA_UPD: { ------------------ | Branch (4023:5): [True: 0, False: 2.24k] ------------------ 4024| | // op: Rn 4025| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4026| 0| Value |= (op & UINT64_C(15)) << 16; 4027| | // op: regs 4028| 0| op = getRegisterListOpValue(MI, 4, Fixups, STI); 4029| 0| Value |= op & UINT64_C(65535); 4030| 0| break; 4031| 0| } 4032| 0| case ARM::tSTMIA_UPD: { ------------------ | Branch (4032:5): [True: 0, False: 2.24k] ------------------ 4033| | // op: Rn 4034| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4035| 0| Value |= (op & UINT64_C(7)) << 8; 4036| | // op: regs 4037| 0| op = getRegisterListOpValue(MI, 4, Fixups, STI); 4038| 0| Value |= op & UINT64_C(255); 4039| 0| break; 4040| 0| } 4041| 0| case ARM::t2LDRB_POST: ------------------ | Branch (4041:5): [True: 0, False: 2.24k] ------------------ 4042| 0| case ARM::t2LDRH_POST: ------------------ | Branch (4042:5): [True: 0, False: 2.24k] ------------------ 4043| 0| case ARM::t2LDRSB_POST: ------------------ | Branch (4043:5): [True: 0, False: 2.24k] ------------------ 4044| 0| case ARM::t2LDRSH_POST: ------------------ | Branch (4044:5): [True: 0, False: 2.24k] ------------------ 4045| 0| case ARM::t2LDR_POST: { ------------------ | Branch (4045:5): [True: 0, False: 2.24k] ------------------ 4046| | // op: Rt 4047| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4048| 0| Value |= (op & UINT64_C(15)) << 12; 4049| | // op: Rn 4050| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4051| 0| Value |= (op & UINT64_C(15)) << 16; 4052| | // op: offset 4053| 0| op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 4054| 0| Value |= (op & UINT64_C(256)) << 1; 4055| 0| Value |= op & UINT64_C(255); 4056| 0| break; 4057| 0| } 4058| 0| case ARM::t2MRRC: ------------------ | Branch (4058:5): [True: 0, False: 2.24k] ------------------ 4059| 0| case ARM::t2MRRC2: { ------------------ | Branch (4059:5): [True: 0, False: 2.24k] ------------------ 4060| | // op: Rt 4061| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4062| 0| Value |= (op & UINT64_C(15)) << 12; 4063| | // op: Rt2 4064| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4065| 0| Value |= (op & UINT64_C(15)) << 16; 4066| | // op: cop 4067| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4068| 0| Value |= (op & UINT64_C(15)) << 8; 4069| | // op: opc1 4070| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4071| 0| Value |= (op & UINT64_C(15)) << 4; 4072| | // op: CRm 4073| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4074| 0| Value |= op & UINT64_C(15); 4075| 0| break; 4076| 0| } 4077| 0| case ARM::t2LDRD_POST: { ------------------ | Branch (4077:5): [True: 0, False: 2.24k] ------------------ 4078| | // op: Rt 4079| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4080| 0| Value |= (op & UINT64_C(15)) << 12; 4081| | // op: Rt2 4082| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4083| 0| Value |= (op & UINT64_C(15)) << 8; 4084| | // op: addr 4085| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4086| 0| Value |= (op & UINT64_C(15)) << 16; 4087| | // op: imm 4088| 0| op = getT2Imm8s4OpValue(MI, 4, Fixups, STI); 4089| 0| Value |= (op & UINT64_C(256)) << 15; 4090| 0| Value |= op & UINT64_C(255); 4091| 0| break; 4092| 0| } 4093| 0| case ARM::t2LDRDi8: ------------------ | Branch (4093:5): [True: 0, False: 2.24k] ------------------ 4094| 0| case ARM::t2STRDi8: { ------------------ | Branch (4094:5): [True: 0, False: 2.24k] ------------------ 4095| | // op: Rt 4096| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4097| 0| Value |= (op & UINT64_C(15)) << 12; 4098| | // op: Rt2 4099| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4100| 0| Value |= (op & UINT64_C(15)) << 8; 4101| | // op: addr 4102| 0| op = getT2AddrModeImm8s4OpValue(MI, 2, Fixups, STI); 4103| 0| Value |= (op & UINT64_C(256)) << 15; 4104| 0| Value |= (op & UINT64_C(7680)) << 7; 4105| 0| Value |= op & UINT64_C(255); 4106| 0| break; 4107| 0| } 4108| 0| case ARM::t2LDRD_PRE: { ------------------ | Branch (4108:5): [True: 0, False: 2.24k] ------------------ 4109| | // op: Rt 4110| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4111| 0| Value |= (op & UINT64_C(15)) << 12; 4112| | // op: Rt2 4113| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4114| 0| Value |= (op & UINT64_C(15)) << 8; 4115| | // op: addr 4116| 0| op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 4117| 0| Value |= (op & UINT64_C(256)) << 15; 4118| 0| Value |= (op & UINT64_C(7680)) << 7; 4119| 0| Value |= op & UINT64_C(255); 4120| 0| break; 4121| 0| } 4122| 0| case ARM::t2LDRBi12: ------------------ | Branch (4122:5): [True: 0, False: 2.24k] ------------------ 4123| 0| case ARM::t2LDRHi12: ------------------ | Branch (4123:5): [True: 0, False: 2.24k] ------------------ 4124| 0| case ARM::t2LDRSBi12: ------------------ | Branch (4124:5): [True: 0, False: 2.24k] ------------------ 4125| 0| case ARM::t2LDRSHi12: ------------------ | Branch (4125:5): [True: 0, False: 2.24k] ------------------ 4126| 0| case ARM::t2LDRi12: ------------------ | Branch (4126:5): [True: 0, False: 2.24k] ------------------ 4127| 0| case ARM::t2STRBi12: ------------------ | Branch (4127:5): [True: 0, False: 2.24k] ------------------ 4128| 0| case ARM::t2STRHi12: ------------------ | Branch (4128:5): [True: 0, False: 2.24k] ------------------ 4129| 0| case ARM::t2STRi12: { ------------------ | Branch (4129:5): [True: 0, False: 2.24k] ------------------ 4130| | // op: Rt 4131| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4132| 0| Value |= (op & UINT64_C(15)) << 12; 4133| | // op: addr 4134| 0| op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 4135| 0| Value |= (op & UINT64_C(122880)) << 3; 4136| 0| Value |= op & UINT64_C(4095); 4137| 0| break; 4138| 0| } 4139| 0| case ARM::t2LDRBpci: ------------------ | Branch (4139:5): [True: 0, False: 2.24k] ------------------ 4140| 72| case ARM::t2LDRHpci: ------------------ | Branch (4140:5): [True: 72, False: 2.16k] ------------------ 4141| 72| case ARM::t2LDRSBpci: ------------------ | Branch (4141:5): [True: 0, False: 2.24k] ------------------ 4142| 72| case ARM::t2LDRSHpci: ------------------ | Branch (4142:5): [True: 0, False: 2.24k] ------------------ 4143| 88| case ARM::t2LDRpci: { ------------------ | Branch (4143:5): [True: 16, False: 2.22k] ------------------ 4144| | // op: Rt 4145| 88| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4146| 88| Value |= (op & UINT64_C(15)) << 12; 4147| | // op: addr 4148| 88| op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 4149| 88| Value |= (op & UINT64_C(4096)) << 11; 4150| 88| Value |= op & UINT64_C(4095); 4151| 88| break; 4152| 72| } 4153| 0| case ARM::t2LDA: ------------------ | Branch (4153:5): [True: 0, False: 2.24k] ------------------ 4154| 0| case ARM::t2LDAB: ------------------ | Branch (4154:5): [True: 0, False: 2.24k] ------------------ 4155| 0| case ARM::t2LDAEX: ------------------ | Branch (4155:5): [True: 0, False: 2.24k] ------------------ 4156| 0| case ARM::t2LDAH: ------------------ | Branch (4156:5): [True: 0, False: 2.24k] ------------------ 4157| 0| case ARM::t2STL: ------------------ | Branch (4157:5): [True: 0, False: 2.24k] ------------------ 4158| 0| case ARM::t2STLB: ------------------ | Branch (4158:5): [True: 0, False: 2.24k] ------------------ 4159| 0| case ARM::t2STLH: { ------------------ | Branch (4159:5): [True: 0, False: 2.24k] ------------------ 4160| | // op: Rt 4161| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4162| 0| Value |= (op & UINT64_C(15)) << 12; 4163| | // op: addr 4164| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4165| 0| Value |= (op & UINT64_C(15)) << 16; 4166| 0| break; 4167| 0| } 4168| 0| case ARM::t2LDREX: { ------------------ | Branch (4168:5): [True: 0, False: 2.24k] ------------------ 4169| | // op: Rt 4170| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4171| 0| Value |= (op & UINT64_C(15)) << 12; 4172| | // op: addr 4173| 0| op = getT2AddrModeImm0_1020s4OpValue(MI, 1, Fixups, STI); 4174| 0| Value |= (op & UINT64_C(3840)) << 8; 4175| 0| Value |= op & UINT64_C(255); 4176| 0| break; 4177| 0| } 4178| 0| case ARM::t2LDRBi8: ------------------ | Branch (4178:5): [True: 0, False: 2.24k] ------------------ 4179| 0| case ARM::t2LDRHi8: ------------------ | Branch (4179:5): [True: 0, False: 2.24k] ------------------ 4180| 0| case ARM::t2LDRSBi8: ------------------ | Branch (4180:5): [True: 0, False: 2.24k] ------------------ 4181| 0| case ARM::t2LDRSHi8: ------------------ | Branch (4181:5): [True: 0, False: 2.24k] ------------------ 4182| 0| case ARM::t2LDRi8: ------------------ | Branch (4182:5): [True: 0, False: 2.24k] ------------------ 4183| 0| case ARM::t2STRBi8: ------------------ | Branch (4183:5): [True: 0, False: 2.24k] ------------------ 4184| 0| case ARM::t2STRHi8: ------------------ | Branch (4184:5): [True: 0, False: 2.24k] ------------------ 4185| 0| case ARM::t2STRi8: { ------------------ | Branch (4185:5): [True: 0, False: 2.24k] ------------------ 4186| | // op: Rt 4187| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4188| 0| Value |= (op & UINT64_C(15)) << 12; 4189| | // op: addr 4190| 0| op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI); 4191| 0| Value |= (op & UINT64_C(7680)) << 7; 4192| 0| Value |= (op & UINT64_C(256)) << 1; 4193| 0| Value |= op & UINT64_C(255); 4194| 0| break; 4195| 0| } 4196| 0| case ARM::t2LDRBT: ------------------ | Branch (4196:5): [True: 0, False: 2.24k] ------------------ 4197| 0| case ARM::t2LDRHT: ------------------ | Branch (4197:5): [True: 0, False: 2.24k] ------------------ 4198| 0| case ARM::t2LDRSBT: ------------------ | Branch (4198:5): [True: 0, False: 2.24k] ------------------ 4199| 0| case ARM::t2LDRSHT: ------------------ | Branch (4199:5): [True: 0, False: 2.24k] ------------------ 4200| 0| case ARM::t2LDRT: ------------------ | Branch (4200:5): [True: 0, False: 2.24k] ------------------ 4201| 0| case ARM::t2STRBT: ------------------ | Branch (4201:5): [True: 0, False: 2.24k] ------------------ 4202| 0| case ARM::t2STRHT: ------------------ | Branch (4202:5): [True: 0, False: 2.24k] ------------------ 4203| 0| case ARM::t2STRT: { ------------------ | Branch (4203:5): [True: 0, False: 2.24k] ------------------ 4204| | // op: Rt 4205| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4206| 0| Value |= (op & UINT64_C(15)) << 12; 4207| | // op: addr 4208| 0| op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI); 4209| 0| Value |= (op & UINT64_C(7680)) << 7; 4210| 0| Value |= op & UINT64_C(255); 4211| 0| break; 4212| 0| } 4213| 0| case ARM::t2LDRB_PRE: ------------------ | Branch (4213:5): [True: 0, False: 2.24k] ------------------ 4214| 0| case ARM::t2LDRH_PRE: ------------------ | Branch (4214:5): [True: 0, False: 2.24k] ------------------ 4215| 0| case ARM::t2LDRSB_PRE: ------------------ | Branch (4215:5): [True: 0, False: 2.24k] ------------------ 4216| 0| case ARM::t2LDRSH_PRE: ------------------ | Branch (4216:5): [True: 0, False: 2.24k] ------------------ 4217| 0| case ARM::t2LDR_PRE: { ------------------ | Branch (4217:5): [True: 0, False: 2.24k] ------------------ 4218| | // op: Rt 4219| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4220| 0| Value |= (op & UINT64_C(15)) << 12; 4221| | // op: addr 4222| 0| op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI); 4223| 0| Value |= (op & UINT64_C(7680)) << 7; 4224| 0| Value |= (op & UINT64_C(256)) << 1; 4225| 0| Value |= op & UINT64_C(255); 4226| 0| break; 4227| 0| } 4228| 0| case ARM::t2LDRBs: ------------------ | Branch (4228:5): [True: 0, False: 2.24k] ------------------ 4229| 0| case ARM::t2LDRHs: ------------------ | Branch (4229:5): [True: 0, False: 2.24k] ------------------ 4230| 0| case ARM::t2LDRSBs: ------------------ | Branch (4230:5): [True: 0, False: 2.24k] ------------------ 4231| 0| case ARM::t2LDRSHs: ------------------ | Branch (4231:5): [True: 0, False: 2.24k] ------------------ 4232| 0| case ARM::t2LDRs: ------------------ | Branch (4232:5): [True: 0, False: 2.24k] ------------------ 4233| 0| case ARM::t2STRBs: ------------------ | Branch (4233:5): [True: 0, False: 2.24k] ------------------ 4234| 0| case ARM::t2STRHs: ------------------ | Branch (4234:5): [True: 0, False: 2.24k] ------------------ 4235| 0| case ARM::t2STRs: { ------------------ | Branch (4235:5): [True: 0, False: 2.24k] ------------------ 4236| | // op: Rt 4237| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4238| 0| Value |= (op & UINT64_C(15)) << 12; 4239| | // op: addr 4240| 0| op = getT2AddrModeSORegOpValue(MI, 1, Fixups, STI); 4241| 0| Value |= (op & UINT64_C(960)) << 10; 4242| 0| Value |= (op & UINT64_C(3)) << 4; 4243| 0| Value |= (op & UINT64_C(60)) >> 2; 4244| 0| break; 4245| 0| } 4246| 0| case ARM::MRC2: ------------------ | Branch (4246:5): [True: 0, False: 2.24k] ------------------ 4247| 0| case ARM::t2MRC: ------------------ | Branch (4247:5): [True: 0, False: 2.24k] ------------------ 4248| 0| case ARM::t2MRC2: { ------------------ | Branch (4248:5): [True: 0, False: 2.24k] ------------------ 4249| | // op: Rt 4250| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4251| 0| Value |= (op & UINT64_C(15)) << 12; 4252| | // op: cop 4253| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4254| 0| Value |= (op & UINT64_C(15)) << 8; 4255| | // op: opc1 4256| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4257| 0| Value |= (op & UINT64_C(7)) << 21; 4258| | // op: opc2 4259| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 4260| 0| Value |= (op & UINT64_C(7)) << 5; 4261| | // op: CRm 4262| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4263| 0| Value |= op & UINT64_C(15); 4264| | // op: CRn 4265| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4266| 0| Value |= (op & UINT64_C(15)) << 16; 4267| 0| break; 4268| 0| } 4269| 516| case ARM::tLDRpci: { ------------------ | Branch (4269:5): [True: 516, False: 1.72k] ------------------ 4270| | // op: Rt 4271| 516| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4272| 516| Value |= (op & UINT64_C(7)) << 8; 4273| | // op: addr 4274| 516| op = getAddrModePCOpValue(MI, 1, Fixups, STI); 4275| 516| Value |= op & UINT64_C(255); 4276| 516| break; 4277| 0| } 4278| 0| case ARM::tLDRspi: ------------------ | Branch (4278:5): [True: 0, False: 2.24k] ------------------ 4279| 0| case ARM::tSTRspi: { ------------------ | Branch (4279:5): [True: 0, False: 2.24k] ------------------ 4280| | // op: Rt 4281| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4282| 0| Value |= (op & UINT64_C(7)) << 8; 4283| | // op: addr 4284| 0| op = getAddrModeThumbSPOpValue(MI, 1, Fixups, STI); 4285| 0| Value |= op & UINT64_C(255); 4286| 0| break; 4287| 0| } 4288| 0| case ARM::tLDRBi: ------------------ | Branch (4288:5): [True: 0, False: 2.24k] ------------------ 4289| 0| case ARM::tLDRHi: ------------------ | Branch (4289:5): [True: 0, False: 2.24k] ------------------ 4290| 0| case ARM::tLDRi: ------------------ | Branch (4290:5): [True: 0, False: 2.24k] ------------------ 4291| 0| case ARM::tSTRBi: ------------------ | Branch (4291:5): [True: 0, False: 2.24k] ------------------ 4292| 0| case ARM::tSTRHi: ------------------ | Branch (4292:5): [True: 0, False: 2.24k] ------------------ 4293| 0| case ARM::tSTRi: { ------------------ | Branch (4293:5): [True: 0, False: 2.24k] ------------------ 4294| | // op: Rt 4295| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4296| 0| Value |= op & UINT64_C(7); 4297| | // op: addr 4298| 0| op = getAddrModeISOpValue(MI, 1, Fixups, STI); 4299| 0| Value |= (op & UINT64_C(255)) << 3; 4300| 0| break; 4301| 0| } 4302| 0| case ARM::tLDRBr: ------------------ | Branch (4302:5): [True: 0, False: 2.24k] ------------------ 4303| 0| case ARM::tLDRHr: ------------------ | Branch (4303:5): [True: 0, False: 2.24k] ------------------ 4304| 0| case ARM::tLDRSB: ------------------ | Branch (4304:5): [True: 0, False: 2.24k] ------------------ 4305| 0| case ARM::tLDRSH: ------------------ | Branch (4305:5): [True: 0, False: 2.24k] ------------------ 4306| 0| case ARM::tLDRr: ------------------ | Branch (4306:5): [True: 0, False: 2.24k] ------------------ 4307| 0| case ARM::tSTRBr: ------------------ | Branch (4307:5): [True: 0, False: 2.24k] ------------------ 4308| 0| case ARM::tSTRHr: ------------------ | Branch (4308:5): [True: 0, False: 2.24k] ------------------ 4309| 0| case ARM::tSTRr: { ------------------ | Branch (4309:5): [True: 0, False: 2.24k] ------------------ 4310| | // op: Rt 4311| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4312| 0| Value |= op & UINT64_C(7); 4313| | // op: addr 4314| 0| op = getThumbAddrModeRegRegOpValue(MI, 1, Fixups, STI); 4315| 0| Value |= (op & UINT64_C(63)) << 3; 4316| 0| break; 4317| 0| } 4318| 0| case ARM::t2STRB_POST: ------------------ | Branch (4318:5): [True: 0, False: 2.24k] ------------------ 4319| 0| case ARM::t2STRH_POST: ------------------ | Branch (4319:5): [True: 0, False: 2.24k] ------------------ 4320| 0| case ARM::t2STR_POST: { ------------------ | Branch (4320:5): [True: 0, False: 2.24k] ------------------ 4321| | // op: Rt 4322| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4323| 0| Value |= (op & UINT64_C(15)) << 12; 4324| | // op: Rn 4325| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4326| 0| Value |= (op & UINT64_C(15)) << 16; 4327| | // op: offset 4328| 0| op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 4329| 0| Value |= (op & UINT64_C(256)) << 1; 4330| 0| Value |= op & UINT64_C(255); 4331| 0| break; 4332| 0| } 4333| 0| case ARM::t2STRD_POST: { ------------------ | Branch (4333:5): [True: 0, False: 2.24k] ------------------ 4334| | // op: Rt 4335| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4336| 0| Value |= (op & UINT64_C(15)) << 12; 4337| | // op: Rt2 4338| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4339| 0| Value |= (op & UINT64_C(15)) << 8; 4340| | // op: addr 4341| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4342| 0| Value |= (op & UINT64_C(15)) << 16; 4343| | // op: imm 4344| 0| op = getT2Imm8s4OpValue(MI, 4, Fixups, STI); 4345| 0| Value |= (op & UINT64_C(256)) << 15; 4346| 0| Value |= op & UINT64_C(255); 4347| 0| break; 4348| 0| } 4349| 0| case ARM::t2STRD_PRE: { ------------------ | Branch (4349:5): [True: 0, False: 2.24k] ------------------ 4350| | // op: Rt 4351| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4352| 0| Value |= (op & UINT64_C(15)) << 12; 4353| | // op: Rt2 4354| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4355| 0| Value |= (op & UINT64_C(15)) << 8; 4356| | // op: addr 4357| 0| op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 4358| 0| Value |= (op & UINT64_C(256)) << 15; 4359| 0| Value |= (op & UINT64_C(7680)) << 7; 4360| 0| Value |= op & UINT64_C(255); 4361| 0| break; 4362| 0| } 4363| 0| case ARM::t2STRB_PRE: ------------------ | Branch (4363:5): [True: 0, False: 2.24k] ------------------ 4364| 0| case ARM::t2STRH_PRE: ------------------ | Branch (4364:5): [True: 0, False: 2.24k] ------------------ 4365| 0| case ARM::t2STR_PRE: { ------------------ | Branch (4365:5): [True: 0, False: 2.24k] ------------------ 4366| | // op: Rt 4367| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4368| 0| Value |= (op & UINT64_C(15)) << 12; 4369| | // op: addr 4370| 0| op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI); 4371| 0| Value |= (op & UINT64_C(7680)) << 7; 4372| 0| Value |= (op & UINT64_C(256)) << 1; 4373| 0| Value |= op & UINT64_C(255); 4374| 0| break; 4375| 0| } 4376| 0| case ARM::MCRR2: ------------------ | Branch (4376:5): [True: 0, False: 2.24k] ------------------ 4377| 0| case ARM::MRRC2: ------------------ | Branch (4377:5): [True: 0, False: 2.24k] ------------------ 4378| 0| case ARM::t2MCRR: ------------------ | Branch (4378:5): [True: 0, False: 2.24k] ------------------ 4379| 0| case ARM::t2MCRR2: { ------------------ | Branch (4379:5): [True: 0, False: 2.24k] ------------------ 4380| | // op: Rt 4381| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4382| 0| Value |= (op & UINT64_C(15)) << 12; 4383| | // op: Rt2 4384| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4385| 0| Value |= (op & UINT64_C(15)) << 16; 4386| | // op: cop 4387| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4388| 0| Value |= (op & UINT64_C(15)) << 8; 4389| | // op: opc1 4390| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4391| 0| Value |= (op & UINT64_C(15)) << 4; 4392| | // op: CRm 4393| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4394| 0| Value |= op & UINT64_C(15); 4395| 0| break; 4396| 0| } 4397| 0| case ARM::MCR2: ------------------ | Branch (4397:5): [True: 0, False: 2.24k] ------------------ 4398| 0| case ARM::t2MCR: ------------------ | Branch (4398:5): [True: 0, False: 2.24k] ------------------ 4399| 0| case ARM::t2MCR2: { ------------------ | Branch (4399:5): [True: 0, False: 2.24k] ------------------ 4400| | // op: Rt 4401| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4402| 0| Value |= (op & UINT64_C(15)) << 12; 4403| | // op: cop 4404| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4405| 0| Value |= (op & UINT64_C(15)) << 8; 4406| | // op: opc1 4407| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4408| 0| Value |= (op & UINT64_C(7)) << 21; 4409| | // op: opc2 4410| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 4411| 0| Value |= (op & UINT64_C(7)) << 5; 4412| | // op: CRm 4413| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4414| 0| Value |= op & UINT64_C(15); 4415| | // op: CRn 4416| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4417| 0| Value |= (op & UINT64_C(15)) << 16; 4418| 0| break; 4419| 0| } 4420| 0| case ARM::t2MSR_M: { ------------------ | Branch (4420:5): [True: 0, False: 2.24k] ------------------ 4421| | // op: SYSm 4422| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4423| 0| Value |= op & UINT64_C(3072); 4424| 0| Value |= op & UINT64_C(255); 4425| | // op: Rn 4426| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4427| 0| Value |= (op & UINT64_C(15)) << 16; 4428| 0| break; 4429| 0| } 4430| 0| case ARM::VCVTASD: ------------------ | Branch (4430:5): [True: 0, False: 2.24k] ------------------ 4431| 0| case ARM::VCVTAUD: ------------------ | Branch (4431:5): [True: 0, False: 2.24k] ------------------ 4432| 0| case ARM::VCVTMSD: ------------------ | Branch (4432:5): [True: 0, False: 2.24k] ------------------ 4433| 0| case ARM::VCVTMUD: ------------------ | Branch (4433:5): [True: 0, False: 2.24k] ------------------ 4434| 0| case ARM::VCVTNSD: ------------------ | Branch (4434:5): [True: 0, False: 2.24k] ------------------ 4435| 0| case ARM::VCVTNUD: ------------------ | Branch (4435:5): [True: 0, False: 2.24k] ------------------ 4436| 0| case ARM::VCVTPSD: ------------------ | Branch (4436:5): [True: 0, False: 2.24k] ------------------ 4437| 0| case ARM::VCVTPUD: { ------------------ | Branch (4437:5): [True: 0, False: 2.24k] ------------------ 4438| | // op: Sd 4439| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4440| 0| Value |= (op & UINT64_C(1)) << 22; 4441| 0| Value |= (op & UINT64_C(30)) << 11; 4442| | // op: Dm 4443| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4444| 0| Value |= (op & UINT64_C(16)) << 1; 4445| 0| Value |= op & UINT64_C(15); 4446| 0| break; 4447| 0| } 4448| 0| case ARM::VCVTASH: ------------------ | Branch (4448:5): [True: 0, False: 2.24k] ------------------ 4449| 0| case ARM::VCVTASS: ------------------ | Branch (4449:5): [True: 0, False: 2.24k] ------------------ 4450| 0| case ARM::VCVTAUH: ------------------ | Branch (4450:5): [True: 0, False: 2.24k] ------------------ 4451| 0| case ARM::VCVTAUS: ------------------ | Branch (4451:5): [True: 0, False: 2.24k] ------------------ 4452| 0| case ARM::VCVTMSH: ------------------ | Branch (4452:5): [True: 0, False: 2.24k] ------------------ 4453| 0| case ARM::VCVTMSS: ------------------ | Branch (4453:5): [True: 0, False: 2.24k] ------------------ 4454| 0| case ARM::VCVTMUH: ------------------ | Branch (4454:5): [True: 0, False: 2.24k] ------------------ 4455| 0| case ARM::VCVTMUS: ------------------ | Branch (4455:5): [True: 0, False: 2.24k] ------------------ 4456| 0| case ARM::VCVTNSH: ------------------ | Branch (4456:5): [True: 0, False: 2.24k] ------------------ 4457| 0| case ARM::VCVTNSS: ------------------ | Branch (4457:5): [True: 0, False: 2.24k] ------------------ 4458| 0| case ARM::VCVTNUH: ------------------ | Branch (4458:5): [True: 0, False: 2.24k] ------------------ 4459| 0| case ARM::VCVTNUS: ------------------ | Branch (4459:5): [True: 0, False: 2.24k] ------------------ 4460| 0| case ARM::VCVTPSH: ------------------ | Branch (4460:5): [True: 0, False: 2.24k] ------------------ 4461| 0| case ARM::VCVTPSS: ------------------ | Branch (4461:5): [True: 0, False: 2.24k] ------------------ 4462| 0| case ARM::VCVTPUH: ------------------ | Branch (4462:5): [True: 0, False: 2.24k] ------------------ 4463| 0| case ARM::VCVTPUS: ------------------ | Branch (4463:5): [True: 0, False: 2.24k] ------------------ 4464| 0| case ARM::VINSH: ------------------ | Branch (4464:5): [True: 0, False: 2.24k] ------------------ 4465| 0| case ARM::VMOVH: ------------------ | Branch (4465:5): [True: 0, False: 2.24k] ------------------ 4466| 0| case ARM::VRINTAH: ------------------ | Branch (4466:5): [True: 0, False: 2.24k] ------------------ 4467| 0| case ARM::VRINTAS: ------------------ | Branch (4467:5): [True: 0, False: 2.24k] ------------------ 4468| 0| case ARM::VRINTMH: ------------------ | Branch (4468:5): [True: 0, False: 2.24k] ------------------ 4469| 0| case ARM::VRINTMS: ------------------ | Branch (4469:5): [True: 0, False: 2.24k] ------------------ 4470| 0| case ARM::VRINTNH: ------------------ | Branch (4470:5): [True: 0, False: 2.24k] ------------------ 4471| 0| case ARM::VRINTNS: ------------------ | Branch (4471:5): [True: 0, False: 2.24k] ------------------ 4472| 0| case ARM::VRINTPH: ------------------ | Branch (4472:5): [True: 0, False: 2.24k] ------------------ 4473| 0| case ARM::VRINTPS: { ------------------ | Branch (4473:5): [True: 0, False: 2.24k] ------------------ 4474| | // op: Sd 4475| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4476| 0| Value |= (op & UINT64_C(1)) << 22; 4477| 0| Value |= (op & UINT64_C(30)) << 11; 4478| | // op: Sm 4479| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4480| 0| Value |= (op & UINT64_C(1)) << 5; 4481| 0| Value |= (op & UINT64_C(30)) >> 1; 4482| 0| break; 4483| 0| } 4484| 0| case ARM::VMAXNMH: ------------------ | Branch (4484:5): [True: 0, False: 2.24k] ------------------ 4485| 0| case ARM::VMAXNMS: ------------------ | Branch (4485:5): [True: 0, False: 2.24k] ------------------ 4486| 0| case ARM::VMINNMH: ------------------ | Branch (4486:5): [True: 0, False: 2.24k] ------------------ 4487| 0| case ARM::VMINNMS: ------------------ | Branch (4487:5): [True: 0, False: 2.24k] ------------------ 4488| 0| case ARM::VSELEQH: ------------------ | Branch (4488:5): [True: 0, False: 2.24k] ------------------ 4489| 0| case ARM::VSELEQS: ------------------ | Branch (4489:5): [True: 0, False: 2.24k] ------------------ 4490| 0| case ARM::VSELGEH: ------------------ | Branch (4490:5): [True: 0, False: 2.24k] ------------------ 4491| 0| case ARM::VSELGES: ------------------ | Branch (4491:5): [True: 0, False: 2.24k] ------------------ 4492| 0| case ARM::VSELGTH: ------------------ | Branch (4492:5): [True: 0, False: 2.24k] ------------------ 4493| 0| case ARM::VSELGTS: ------------------ | Branch (4493:5): [True: 0, False: 2.24k] ------------------ 4494| 0| case ARM::VSELVSH: ------------------ | Branch (4494:5): [True: 0, False: 2.24k] ------------------ 4495| 0| case ARM::VSELVSS: { ------------------ | Branch (4495:5): [True: 0, False: 2.24k] ------------------ 4496| | // op: Sd 4497| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4498| 0| Value |= (op & UINT64_C(1)) << 22; 4499| 0| Value |= (op & UINT64_C(30)) << 11; 4500| | // op: Sn 4501| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4502| 0| Value |= (op & UINT64_C(30)) << 15; 4503| 0| Value |= (op & UINT64_C(1)) << 7; 4504| | // op: Sm 4505| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4506| 0| Value |= (op & UINT64_C(1)) << 5; 4507| 0| Value |= (op & UINT64_C(30)) >> 1; 4508| 0| break; 4509| 0| } 4510| 0| case ARM::VDUP16d: ------------------ | Branch (4510:5): [True: 0, False: 2.24k] ------------------ 4511| 0| case ARM::VDUP16q: ------------------ | Branch (4511:5): [True: 0, False: 2.24k] ------------------ 4512| 0| case ARM::VDUP32d: ------------------ | Branch (4512:5): [True: 0, False: 2.24k] ------------------ 4513| 0| case ARM::VDUP32q: ------------------ | Branch (4513:5): [True: 0, False: 2.24k] ------------------ 4514| 0| case ARM::VDUP8d: ------------------ | Branch (4514:5): [True: 0, False: 2.24k] ------------------ 4515| 0| case ARM::VDUP8q: { ------------------ | Branch (4515:5): [True: 0, False: 2.24k] ------------------ 4516| | // op: V 4517| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4518| 0| Value |= (op & UINT64_C(15)) << 16; 4519| 0| Value |= (op & UINT64_C(16)) << 3; 4520| | // op: R 4521| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4522| 0| Value |= (op & UINT64_C(15)) << 12; 4523| | // op: p 4524| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4525| 0| Value |= (op & UINT64_C(15)) << 28; 4526| 0| Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4527| 0| break; 4528| 0| } 4529| 0| case ARM::VSETLNi32: { ------------------ | Branch (4529:5): [True: 0, False: 2.24k] ------------------ 4530| | // op: V 4531| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4532| 0| Value |= (op & UINT64_C(15)) << 16; 4533| 0| Value |= (op & UINT64_C(16)) << 3; 4534| | // op: R 4535| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4536| 0| Value |= (op & UINT64_C(15)) << 12; 4537| | // op: p 4538| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4539| 0| Value |= (op & UINT64_C(15)) << 28; 4540| | // op: lane 4541| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4542| 0| Value |= (op & UINT64_C(1)) << 21; 4543| 0| Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4544| 0| break; 4545| 0| } 4546| 0| case ARM::VSETLNi16: { ------------------ | Branch (4546:5): [True: 0, False: 2.24k] ------------------ 4547| | // op: V 4548| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4549| 0| Value |= (op & UINT64_C(15)) << 16; 4550| 0| Value |= (op & UINT64_C(16)) << 3; 4551| | // op: R 4552| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4553| 0| Value |= (op & UINT64_C(15)) << 12; 4554| | // op: p 4555| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4556| 0| Value |= (op & UINT64_C(15)) << 28; 4557| | // op: lane 4558| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4559| 0| Value |= (op & UINT64_C(2)) << 20; 4560| 0| Value |= (op & UINT64_C(1)) << 6; 4561| 0| Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4562| 0| break; 4563| 0| } 4564| 0| case ARM::VSETLNi8: { ------------------ | Branch (4564:5): [True: 0, False: 2.24k] ------------------ 4565| | // op: V 4566| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4567| 0| Value |= (op & UINT64_C(15)) << 16; 4568| 0| Value |= (op & UINT64_C(16)) << 3; 4569| | // op: R 4570| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4571| 0| Value |= (op & UINT64_C(15)) << 12; 4572| | // op: p 4573| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4574| 0| Value |= (op & UINT64_C(15)) << 28; 4575| | // op: lane 4576| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4577| 0| Value |= (op & UINT64_C(4)) << 19; 4578| 0| Value |= (op & UINT64_C(3)) << 5; 4579| 0| Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4580| 0| break; 4581| 0| } 4582| 0| case ARM::VGETLNi32: { ------------------ | Branch (4582:5): [True: 0, False: 2.24k] ------------------ 4583| | // op: V 4584| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4585| 0| Value |= (op & UINT64_C(15)) << 16; 4586| 0| Value |= (op & UINT64_C(16)) << 3; 4587| | // op: R 4588| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4589| 0| Value |= (op & UINT64_C(15)) << 12; 4590| | // op: p 4591| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4592| 0| Value |= (op & UINT64_C(15)) << 28; 4593| | // op: lane 4594| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4595| 0| Value |= (op & UINT64_C(1)) << 21; 4596| 0| Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4597| 0| break; 4598| 0| } 4599| 0| case ARM::VGETLNs16: ------------------ | Branch (4599:5): [True: 0, False: 2.24k] ------------------ 4600| 0| case ARM::VGETLNu16: { ------------------ | Branch (4600:5): [True: 0, False: 2.24k] ------------------ 4601| | // op: V 4602| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4603| 0| Value |= (op & UINT64_C(15)) << 16; 4604| 0| Value |= (op & UINT64_C(16)) << 3; 4605| | // op: R 4606| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4607| 0| Value |= (op & UINT64_C(15)) << 12; 4608| | // op: p 4609| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4610| 0| Value |= (op & UINT64_C(15)) << 28; 4611| | // op: lane 4612| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4613| 0| Value |= (op & UINT64_C(2)) << 20; 4614| 0| Value |= (op & UINT64_C(1)) << 6; 4615| 0| Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4616| 0| break; 4617| 0| } 4618| 0| case ARM::VGETLNs8: ------------------ | Branch (4618:5): [True: 0, False: 2.24k] ------------------ 4619| 0| case ARM::VGETLNu8: { ------------------ | Branch (4619:5): [True: 0, False: 2.24k] ------------------ 4620| | // op: V 4621| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4622| 0| Value |= (op & UINT64_C(15)) << 16; 4623| 0| Value |= (op & UINT64_C(16)) << 3; 4624| | // op: R 4625| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4626| 0| Value |= (op & UINT64_C(15)) << 12; 4627| | // op: p 4628| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4629| 0| Value |= (op & UINT64_C(15)) << 28; 4630| | // op: lane 4631| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4632| 0| Value |= (op & UINT64_C(4)) << 19; 4633| 0| Value |= (op & UINT64_C(3)) << 5; 4634| 0| Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4635| 0| break; 4636| 0| } 4637| 0| case ARM::VLD1LNd8: { ------------------ | Branch (4637:5): [True: 0, False: 2.24k] ------------------ 4638| | // op: Vd 4639| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4640| 0| Value |= (op & UINT64_C(16)) << 18; 4641| 0| Value |= (op & UINT64_C(15)) << 12; 4642| | // op: Rn 4643| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4644| 0| Value |= (op & UINT64_C(15)) << 16; 4645| | // op: lane 4646| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4647| 0| Value |= (op & UINT64_C(7)) << 5; 4648| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4649| 0| break; 4650| 0| } 4651| 0| case ARM::VLD1d16: ------------------ | Branch (4651:5): [True: 0, False: 2.24k] ------------------ 4652| 0| case ARM::VLD1d16T: ------------------ | Branch (4652:5): [True: 0, False: 2.24k] ------------------ 4653| 0| case ARM::VLD1d32: ------------------ | Branch (4653:5): [True: 0, False: 2.24k] ------------------ 4654| 0| case ARM::VLD1d32T: ------------------ | Branch (4654:5): [True: 0, False: 2.24k] ------------------ 4655| 0| case ARM::VLD1d64: ------------------ | Branch (4655:5): [True: 0, False: 2.24k] ------------------ 4656| 0| case ARM::VLD1d64T: ------------------ | Branch (4656:5): [True: 0, False: 2.24k] ------------------ 4657| 0| case ARM::VLD1d8: ------------------ | Branch (4657:5): [True: 0, False: 2.24k] ------------------ 4658| 0| case ARM::VLD1d8T: { ------------------ | Branch (4658:5): [True: 0, False: 2.24k] ------------------ 4659| | // op: Vd 4660| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4661| 0| Value |= (op & UINT64_C(16)) << 18; 4662| 0| Value |= (op & UINT64_C(15)) << 12; 4663| | // op: Rn 4664| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4665| 0| Value |= (op & UINT64_C(15)) << 16; 4666| 0| Value |= op & UINT64_C(16); 4667| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4668| 0| break; 4669| 0| } 4670| 0| case ARM::VLD1LNd16: { ------------------ | Branch (4670:5): [True: 0, False: 2.24k] ------------------ 4671| | // op: Vd 4672| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4673| 0| Value |= (op & UINT64_C(16)) << 18; 4674| 0| Value |= (op & UINT64_C(15)) << 12; 4675| | // op: Rn 4676| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4677| 0| Value |= (op & UINT64_C(15)) << 16; 4678| 0| Value |= op & UINT64_C(48); 4679| | // op: lane 4680| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4681| 0| Value |= (op & UINT64_C(3)) << 6; 4682| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4683| 0| break; 4684| 0| } 4685| 0| case ARM::VLD1d16Q: ------------------ | Branch (4685:5): [True: 0, False: 2.24k] ------------------ 4686| 0| case ARM::VLD1d32Q: ------------------ | Branch (4686:5): [True: 0, False: 2.24k] ------------------ 4687| 0| case ARM::VLD1d64Q: ------------------ | Branch (4687:5): [True: 0, False: 2.24k] ------------------ 4688| 0| case ARM::VLD1d8Q: ------------------ | Branch (4688:5): [True: 0, False: 2.24k] ------------------ 4689| 0| case ARM::VLD1q16: ------------------ | Branch (4689:5): [True: 0, False: 2.24k] ------------------ 4690| 0| case ARM::VLD1q32: ------------------ | Branch (4690:5): [True: 0, False: 2.24k] ------------------ 4691| 0| case ARM::VLD1q64: ------------------ | Branch (4691:5): [True: 0, False: 2.24k] ------------------ 4692| 0| case ARM::VLD1q8: ------------------ | Branch (4692:5): [True: 0, False: 2.24k] ------------------ 4693| 0| case ARM::VLD2b16: ------------------ | Branch (4693:5): [True: 0, False: 2.24k] ------------------ 4694| 0| case ARM::VLD2b32: ------------------ | Branch (4694:5): [True: 0, False: 2.24k] ------------------ 4695| 0| case ARM::VLD2b8: ------------------ | Branch (4695:5): [True: 0, False: 2.24k] ------------------ 4696| 0| case ARM::VLD2d16: ------------------ | Branch (4696:5): [True: 0, False: 2.24k] ------------------ 4697| 0| case ARM::VLD2d32: ------------------ | Branch (4697:5): [True: 0, False: 2.24k] ------------------ 4698| 0| case ARM::VLD2d8: ------------------ | Branch (4698:5): [True: 0, False: 2.24k] ------------------ 4699| 0| case ARM::VLD2q16: ------------------ | Branch (4699:5): [True: 0, False: 2.24k] ------------------ 4700| 0| case ARM::VLD2q32: ------------------ | Branch (4700:5): [True: 0, False: 2.24k] ------------------ 4701| 0| case ARM::VLD2q8: { ------------------ | Branch (4701:5): [True: 0, False: 2.24k] ------------------ 4702| | // op: Vd 4703| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4704| 0| Value |= (op & UINT64_C(16)) << 18; 4705| 0| Value |= (op & UINT64_C(15)) << 12; 4706| | // op: Rn 4707| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4708| 0| Value |= (op & UINT64_C(15)) << 16; 4709| 0| Value |= op & UINT64_C(48); 4710| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4711| 0| break; 4712| 0| } 4713| 0| case ARM::VLD1LNd8_UPD: { ------------------ | Branch (4713:5): [True: 0, False: 2.24k] ------------------ 4714| | // op: Vd 4715| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4716| 0| Value |= (op & UINT64_C(16)) << 18; 4717| 0| Value |= (op & UINT64_C(15)) << 12; 4718| | // op: Rn 4719| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4720| 0| Value |= (op & UINT64_C(15)) << 16; 4721| | // op: Rm 4722| 0| op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 4723| 0| Value |= op & UINT64_C(15); 4724| | // op: lane 4725| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4726| 0| Value |= (op & UINT64_C(7)) << 5; 4727| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4728| 0| break; 4729| 0| } 4730| 0| case ARM::VLD1LNd32_UPD: { ------------------ | Branch (4730:5): [True: 0, False: 2.24k] ------------------ 4731| | // op: Vd 4732| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4733| 0| Value |= (op & UINT64_C(16)) << 18; 4734| 0| Value |= (op & UINT64_C(15)) << 12; 4735| | // op: Rn 4736| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4737| 0| Value |= (op & UINT64_C(15)) << 16; 4738| 0| Value |= (op & UINT64_C(16)) << 1; 4739| 0| Value |= op & UINT64_C(16); 4740| | // op: Rm 4741| 0| op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 4742| 0| Value |= op & UINT64_C(15); 4743| | // op: lane 4744| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4745| 0| Value |= (op & UINT64_C(1)) << 7; 4746| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4747| 0| break; 4748| 0| } 4749| 0| case ARM::VLD1LNd16_UPD: { ------------------ | Branch (4749:5): [True: 0, False: 2.24k] ------------------ 4750| | // op: Vd 4751| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4752| 0| Value |= (op & UINT64_C(16)) << 18; 4753| 0| Value |= (op & UINT64_C(15)) << 12; 4754| | // op: Rn 4755| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4756| 0| Value |= (op & UINT64_C(15)) << 16; 4757| 0| Value |= op & UINT64_C(16); 4758| | // op: Rm 4759| 0| op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 4760| 0| Value |= op & UINT64_C(15); 4761| | // op: lane 4762| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4763| 0| Value |= (op & UINT64_C(3)) << 6; 4764| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4765| 0| break; 4766| 0| } 4767| 0| case ARM::VLD1d16Twb_register: ------------------ | Branch (4767:5): [True: 0, False: 2.24k] ------------------ 4768| 0| case ARM::VLD1d16wb_register: ------------------ | Branch (4768:5): [True: 0, False: 2.24k] ------------------ 4769| 0| case ARM::VLD1d32Twb_register: ------------------ | Branch (4769:5): [True: 0, False: 2.24k] ------------------ 4770| 0| case ARM::VLD1d32wb_register: ------------------ | Branch (4770:5): [True: 0, False: 2.24k] ------------------ 4771| 0| case ARM::VLD1d64Twb_register: ------------------ | Branch (4771:5): [True: 0, False: 2.24k] ------------------ 4772| 0| case ARM::VLD1d64wb_register: ------------------ | Branch (4772:5): [True: 0, False: 2.24k] ------------------ 4773| 0| case ARM::VLD1d8Twb_register: ------------------ | Branch (4773:5): [True: 0, False: 2.24k] ------------------ 4774| 0| case ARM::VLD1d8wb_register: { ------------------ | Branch (4774:5): [True: 0, False: 2.24k] ------------------ 4775| | // op: Vd 4776| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4777| 0| Value |= (op & UINT64_C(16)) << 18; 4778| 0| Value |= (op & UINT64_C(15)) << 12; 4779| | // op: Rn 4780| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4781| 0| Value |= (op & UINT64_C(15)) << 16; 4782| 0| Value |= op & UINT64_C(16); 4783| | // op: Rm 4784| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4785| 0| Value |= op & UINT64_C(15); 4786| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4787| 0| break; 4788| 0| } 4789| 0| case ARM::VLD2LNd32: ------------------ | Branch (4789:5): [True: 0, False: 2.24k] ------------------ 4790| 0| case ARM::VLD2LNq32: { ------------------ | Branch (4790:5): [True: 0, False: 2.24k] ------------------ 4791| | // op: Vd 4792| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4793| 0| Value |= (op & UINT64_C(16)) << 18; 4794| 0| Value |= (op & UINT64_C(15)) << 12; 4795| | // op: Rn 4796| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4797| 0| Value |= (op & UINT64_C(15)) << 16; 4798| 0| Value |= op & UINT64_C(16); 4799| | // op: lane 4800| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4801| 0| Value |= (op & UINT64_C(1)) << 7; 4802| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4803| 0| break; 4804| 0| } 4805| 0| case ARM::VLD2LNd16: ------------------ | Branch (4805:5): [True: 0, False: 2.24k] ------------------ 4806| 0| case ARM::VLD2LNq16: { ------------------ | Branch (4806:5): [True: 0, False: 2.24k] ------------------ 4807| | // op: Vd 4808| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4809| 0| Value |= (op & UINT64_C(16)) << 18; 4810| 0| Value |= (op & UINT64_C(15)) << 12; 4811| | // op: Rn 4812| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4813| 0| Value |= (op & UINT64_C(15)) << 16; 4814| 0| Value |= op & UINT64_C(16); 4815| | // op: lane 4816| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4817| 0| Value |= (op & UINT64_C(3)) << 6; 4818| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4819| 0| break; 4820| 0| } 4821| 0| case ARM::VLD2LNd8: { ------------------ | Branch (4821:5): [True: 0, False: 2.24k] ------------------ 4822| | // op: Vd 4823| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4824| 0| Value |= (op & UINT64_C(16)) << 18; 4825| 0| Value |= (op & UINT64_C(15)) << 12; 4826| | // op: Rn 4827| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4828| 0| Value |= (op & UINT64_C(15)) << 16; 4829| 0| Value |= op & UINT64_C(16); 4830| | // op: lane 4831| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4832| 0| Value |= (op & UINT64_C(7)) << 5; 4833| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4834| 0| break; 4835| 0| } 4836| 0| case ARM::VLD1d16Twb_fixed: ------------------ | Branch (4836:5): [True: 0, False: 2.24k] ------------------ 4837| 0| case ARM::VLD1d16wb_fixed: ------------------ | Branch (4837:5): [True: 0, False: 2.24k] ------------------ 4838| 0| case ARM::VLD1d32Twb_fixed: ------------------ | Branch (4838:5): [True: 0, False: 2.24k] ------------------ 4839| 0| case ARM::VLD1d32wb_fixed: ------------------ | Branch (4839:5): [True: 0, False: 2.24k] ------------------ 4840| 0| case ARM::VLD1d64Twb_fixed: ------------------ | Branch (4840:5): [True: 0, False: 2.24k] ------------------ 4841| 0| case ARM::VLD1d64wb_fixed: ------------------ | Branch (4841:5): [True: 0, False: 2.24k] ------------------ 4842| 0| case ARM::VLD1d8Twb_fixed: ------------------ | Branch (4842:5): [True: 0, False: 2.24k] ------------------ 4843| 0| case ARM::VLD1d8wb_fixed: { ------------------ | Branch (4843:5): [True: 0, False: 2.24k] ------------------ 4844| | // op: Vd 4845| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4846| 0| Value |= (op & UINT64_C(16)) << 18; 4847| 0| Value |= (op & UINT64_C(15)) << 12; 4848| | // op: Rn 4849| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4850| 0| Value |= (op & UINT64_C(15)) << 16; 4851| 0| Value |= op & UINT64_C(16); 4852| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4853| 0| break; 4854| 0| } 4855| 0| case ARM::VLD1d16Qwb_register: ------------------ | Branch (4855:5): [True: 0, False: 2.24k] ------------------ 4856| 0| case ARM::VLD1d32Qwb_register: ------------------ | Branch (4856:5): [True: 0, False: 2.24k] ------------------ 4857| 0| case ARM::VLD1d64Qwb_register: ------------------ | Branch (4857:5): [True: 0, False: 2.24k] ------------------ 4858| 0| case ARM::VLD1d8Qwb_register: ------------------ | Branch (4858:5): [True: 0, False: 2.24k] ------------------ 4859| 0| case ARM::VLD1q16wb_register: ------------------ | Branch (4859:5): [True: 0, False: 2.24k] ------------------ 4860| 0| case ARM::VLD1q32wb_register: ------------------ | Branch (4860:5): [True: 0, False: 2.24k] ------------------ 4861| 0| case ARM::VLD1q64wb_register: ------------------ | Branch (4861:5): [True: 0, False: 2.24k] ------------------ 4862| 0| case ARM::VLD1q8wb_register: ------------------ | Branch (4862:5): [True: 0, False: 2.24k] ------------------ 4863| 0| case ARM::VLD2b16wb_register: ------------------ | Branch (4863:5): [True: 0, False: 2.24k] ------------------ 4864| 0| case ARM::VLD2b32wb_register: ------------------ | Branch (4864:5): [True: 0, False: 2.24k] ------------------ 4865| 0| case ARM::VLD2b8wb_register: ------------------ | Branch (4865:5): [True: 0, False: 2.24k] ------------------ 4866| 0| case ARM::VLD2d16wb_register: ------------------ | Branch (4866:5): [True: 0, False: 2.24k] ------------------ 4867| 0| case ARM::VLD2d32wb_register: ------------------ | Branch (4867:5): [True: 0, False: 2.24k] ------------------ 4868| 0| case ARM::VLD2d8wb_register: ------------------ | Branch (4868:5): [True: 0, False: 2.24k] ------------------ 4869| 0| case ARM::VLD2q16wb_register: ------------------ | Branch (4869:5): [True: 0, False: 2.24k] ------------------ 4870| 0| case ARM::VLD2q32wb_register: ------------------ | Branch (4870:5): [True: 0, False: 2.24k] ------------------ 4871| 0| case ARM::VLD2q8wb_register: { ------------------ | Branch (4871:5): [True: 0, False: 2.24k] ------------------ 4872| | // op: Vd 4873| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4874| 0| Value |= (op & UINT64_C(16)) << 18; 4875| 0| Value |= (op & UINT64_C(15)) << 12; 4876| | // op: Rn 4877| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4878| 0| Value |= (op & UINT64_C(15)) << 16; 4879| 0| Value |= op & UINT64_C(48); 4880| | // op: Rm 4881| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4882| 0| Value |= op & UINT64_C(15); 4883| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4884| 0| break; 4885| 0| } 4886| 0| case ARM::VLD1d16Qwb_fixed: ------------------ | Branch (4886:5): [True: 0, False: 2.24k] ------------------ 4887| 0| case ARM::VLD1d32Qwb_fixed: ------------------ | Branch (4887:5): [True: 0, False: 2.24k] ------------------ 4888| 0| case ARM::VLD1d64Qwb_fixed: ------------------ | Branch (4888:5): [True: 0, False: 2.24k] ------------------ 4889| 0| case ARM::VLD1d8Qwb_fixed: ------------------ | Branch (4889:5): [True: 0, False: 2.24k] ------------------ 4890| 0| case ARM::VLD1q16wb_fixed: ------------------ | Branch (4890:5): [True: 0, False: 2.24k] ------------------ 4891| 0| case ARM::VLD1q32wb_fixed: ------------------ | Branch (4891:5): [True: 0, False: 2.24k] ------------------ 4892| 0| case ARM::VLD1q64wb_fixed: ------------------ | Branch (4892:5): [True: 0, False: 2.24k] ------------------ 4893| 0| case ARM::VLD1q8wb_fixed: ------------------ | Branch (4893:5): [True: 0, False: 2.24k] ------------------ 4894| 0| case ARM::VLD2b16wb_fixed: ------------------ | Branch (4894:5): [True: 0, False: 2.24k] ------------------ 4895| 0| case ARM::VLD2b32wb_fixed: ------------------ | Branch (4895:5): [True: 0, False: 2.24k] ------------------ 4896| 0| case ARM::VLD2b8wb_fixed: ------------------ | Branch (4896:5): [True: 0, False: 2.24k] ------------------ 4897| 0| case ARM::VLD2d16wb_fixed: ------------------ | Branch (4897:5): [True: 0, False: 2.24k] ------------------ 4898| 0| case ARM::VLD2d32wb_fixed: ------------------ | Branch (4898:5): [True: 0, False: 2.24k] ------------------ 4899| 0| case ARM::VLD2d8wb_fixed: ------------------ | Branch (4899:5): [True: 0, False: 2.24k] ------------------ 4900| 0| case ARM::VLD2q16wb_fixed: ------------------ | Branch (4900:5): [True: 0, False: 2.24k] ------------------ 4901| 0| case ARM::VLD2q32wb_fixed: ------------------ | Branch (4901:5): [True: 0, False: 2.24k] ------------------ 4902| 0| case ARM::VLD2q8wb_fixed: { ------------------ | Branch (4902:5): [True: 0, False: 2.24k] ------------------ 4903| | // op: Vd 4904| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4905| 0| Value |= (op & UINT64_C(16)) << 18; 4906| 0| Value |= (op & UINT64_C(15)) << 12; 4907| | // op: Rn 4908| 0| op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4909| 0| Value |= (op & UINT64_C(15)) << 16; 4910| 0| Value |= op & UINT64_C(48); 4911| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4912| 0| break; 4913| 0| } 4914| 0| case ARM::VLD3LNd32: ------------------ | Branch (4914:5): [True: 0, False: 2.24k] ------------------ 4915| 0| case ARM::VLD3LNq32: { ------------------ | Branch (4915:5): [True: 0, False: 2.24k] ------------------ 4916| | // op: Vd 4917| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4918| 0| Value |= (op & UINT64_C(16)) << 18; 4919| 0| Value |= (op & UINT64_C(15)) << 12; 4920| | // op: Rn 4921| 0| op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4922| 0| Value |= (op & UINT64_C(15)) << 16; 4923| | // op: lane 4924| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4925| 0| Value |= (op & UINT64_C(1)) << 7; 4926| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4927| 0| break; 4928| 0| } 4929| 0| case ARM::VLD3LNd16: ------------------ | Branch (4929:5): [True: 0, False: 2.24k] ------------------ 4930| 0| case ARM::VLD3LNq16: { ------------------ | Branch (4930:5): [True: 0, False: 2.24k] ------------------ 4931| | // op: Vd 4932| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4933| 0| Value |= (op & UINT64_C(16)) << 18; 4934| 0| Value |= (op & UINT64_C(15)) << 12; 4935| | // op: Rn 4936| 0| op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4937| 0| Value |= (op & UINT64_C(15)) << 16; 4938| | // op: lane 4939| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4940| 0| Value |= (op & UINT64_C(3)) << 6; 4941| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4942| 0| break; 4943| 0| } 4944| 0| case ARM::VLD3LNd8: { ------------------ | Branch (4944:5): [True: 0, False: 2.24k] ------------------ 4945| | // op: Vd 4946| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4947| 0| Value |= (op & UINT64_C(16)) << 18; 4948| 0| Value |= (op & UINT64_C(15)) << 12; 4949| | // op: Rn 4950| 0| op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4951| 0| Value |= (op & UINT64_C(15)) << 16; 4952| | // op: lane 4953| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4954| 0| Value |= (op & UINT64_C(7)) << 5; 4955| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4956| 0| break; 4957| 0| } 4958| 0| case ARM::VLD2LNd32_UPD: ------------------ | Branch (4958:5): [True: 0, False: 2.24k] ------------------ 4959| 0| case ARM::VLD2LNq32_UPD: { ------------------ | Branch (4959:5): [True: 0, False: 2.24k] ------------------ 4960| | // op: Vd 4961| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4962| 0| Value |= (op & UINT64_C(16)) << 18; 4963| 0| Value |= (op & UINT64_C(15)) << 12; 4964| | // op: Rn 4965| 0| op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4966| 0| Value |= (op & UINT64_C(15)) << 16; 4967| 0| Value |= op & UINT64_C(16); 4968| | // op: Rm 4969| 0| op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 4970| 0| Value |= op & UINT64_C(15); 4971| | // op: lane 4972| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4973| 0| Value |= (op & UINT64_C(1)) << 7; 4974| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4975| 0| break; 4976| 0| } 4977| 0| case ARM::VLD2LNd16_UPD: ------------------ | Branch (4977:5): [True: 0, False: 2.24k] ------------------ 4978| 0| case ARM::VLD2LNq16_UPD: { ------------------ | Branch (4978:5): [True: 0, False: 2.24k] ------------------ 4979| | // op: Vd 4980| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4981| 0| Value |= (op & UINT64_C(16)) << 18; 4982| 0| Value |= (op & UINT64_C(15)) << 12; 4983| | // op: Rn 4984| 0| op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4985| 0| Value |= (op & UINT64_C(15)) << 16; 4986| 0| Value |= op & UINT64_C(16); 4987| | // op: Rm 4988| 0| op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 4989| 0| Value |= op & UINT64_C(15); 4990| | // op: lane 4991| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4992| 0| Value |= (op & UINT64_C(3)) << 6; 4993| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4994| 0| break; 4995| 0| } 4996| 0| case ARM::VLD2LNd8_UPD: { ------------------ | Branch (4996:5): [True: 0, False: 2.24k] ------------------ 4997| | // op: Vd 4998| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4999| 0| Value |= (op & UINT64_C(16)) << 18; 5000| 0| Value |= (op & UINT64_C(15)) << 12; 5001| | // op: Rn 5002| 0| op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5003| 0| Value |= (op & UINT64_C(15)) << 16; 5004| 0| Value |= op & UINT64_C(16); 5005| | // op: Rm 5006| 0| op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 5007| 0| Value |= op & UINT64_C(15); 5008| | // op: lane 5009| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 5010| 0| Value |= (op & UINT64_C(7)) << 5; 5011| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5012| 0| break; 5013| 0| } 5014| 0| case ARM::VLD3d16: ------------------ | Branch (5014:5): [True: 0, False: 2.24k] ------------------ 5015| 0| case ARM::VLD3d32: ------------------ | Branch (5015:5): [True: 0, False: 2.24k] ------------------ 5016| 0| case ARM::VLD3d8: ------------------ | Branch (5016:5): [True: 0, False: 2.24k] ------------------ 5017| 0| case ARM::VLD3q16: ------------------ | Branch (5017:5): [True: 0, False: 2.24k] ------------------ 5018| 0| case ARM::VLD3q32: ------------------ | Branch (5018:5): [True: 0, False: 2.24k] ------------------ 5019| 0| case ARM::VLD3q8: { ------------------ | Branch (5019:5): [True: 0, False: 2.24k] ------------------ 5020| | // op: Vd 5021| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5022| 0| Value |= (op & UINT64_C(16)) << 18; 5023| 0| Value |= (op & UINT64_C(15)) << 12; 5024| | // op: Rn 5025| 0| op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5026| 0| Value |= (op & UINT64_C(15)) << 16; 5027| 0| Value |= op & UINT64_C(16); 5028| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5029| 0| break; 5030| 0| } 5031| 0| case ARM::VLD3LNd32_UPD: ------------------ | Branch (5031:5): [True: 0, False: 2.24k] ------------------ 5032| 0| case ARM::VLD3LNq32_UPD: { ------------------ | Branch (5032:5): [True: 0, False: 2.24k] ------------------ 5033| | // op: Vd 5034| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5035| 0| Value |= (op & UINT64_C(16)) << 18; 5036| 0| Value |= (op & UINT64_C(15)) << 12; 5037| | // op: Rn 5038| 0| op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5039| 0| Value |= (op & UINT64_C(15)) << 16; 5040| | // op: Rm 5041| 0| op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5042| 0| Value |= op & UINT64_C(15); 5043| | // op: lane 5044| 0| op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5045| 0| Value |= (op & UINT64_C(1)) << 7; 5046| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5047| 0| break; 5048| 0| } 5049| 0| case ARM::VLD3LNd16_UPD: ------------------ | Branch (5049:5): [True: 0, False: 2.24k] ------------------ 5050| 0| case ARM::VLD3LNq16_UPD: { ------------------ | Branch (5050:5): [True: 0, False: 2.24k] ------------------ 5051| | // op: Vd 5052| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5053| 0| Value |= (op & UINT64_C(16)) << 18; 5054| 0| Value |= (op & UINT64_C(15)) << 12; 5055| | // op: Rn 5056| 0| op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5057| 0| Value |= (op & UINT64_C(15)) << 16; 5058| | // op: Rm 5059| 0| op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5060| 0| Value |= op & UINT64_C(15); 5061| | // op: lane 5062| 0| op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5063| 0| Value |= (op & UINT64_C(3)) << 6; 5064| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5065| 0| break; 5066| 0| } 5067| 0| case ARM::VLD3LNd8_UPD: { ------------------ | Branch (5067:5): [True: 0, False: 2.24k] ------------------ 5068| | // op: Vd 5069| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5070| 0| Value |= (op & UINT64_C(16)) << 18; 5071| 0| Value |= (op & UINT64_C(15)) << 12; 5072| | // op: Rn 5073| 0| op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5074| 0| Value |= (op & UINT64_C(15)) << 16; 5075| | // op: Rm 5076| 0| op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5077| 0| Value |= op & UINT64_C(15); 5078| | // op: lane 5079| 0| op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5080| 0| Value |= (op & UINT64_C(7)) << 5; 5081| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5082| 0| break; 5083| 0| } 5084| 0| case ARM::VLD3d16_UPD: ------------------ | Branch (5084:5): [True: 0, False: 2.24k] ------------------ 5085| 0| case ARM::VLD3d32_UPD: ------------------ | Branch (5085:5): [True: 0, False: 2.24k] ------------------ 5086| 0| case ARM::VLD3d8_UPD: ------------------ | Branch (5086:5): [True: 0, False: 2.24k] ------------------ 5087| 0| case ARM::VLD3q16_UPD: ------------------ | Branch (5087:5): [True: 0, False: 2.24k] ------------------ 5088| 0| case ARM::VLD3q32_UPD: ------------------ | Branch (5088:5): [True: 0, False: 2.24k] ------------------ 5089| 0| case ARM::VLD3q8_UPD: { ------------------ | Branch (5089:5): [True: 0, False: 2.24k] ------------------ 5090| | // op: Vd 5091| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5092| 0| Value |= (op & UINT64_C(16)) << 18; 5093| 0| Value |= (op & UINT64_C(15)) << 12; 5094| | // op: Rn 5095| 0| op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5096| 0| Value |= (op & UINT64_C(15)) << 16; 5097| 0| Value |= op & UINT64_C(16); 5098| | // op: Rm 5099| 0| op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5100| 0| Value |= op & UINT64_C(15); 5101| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5102| 0| break; 5103| 0| } 5104| 0| case ARM::VLD4LNd16: ------------------ | Branch (5104:5): [True: 0, False: 2.24k] ------------------ 5105| 0| case ARM::VLD4LNq16: { ------------------ | Branch (5105:5): [True: 0, False: 2.24k] ------------------ 5106| | // op: Vd 5107| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5108| 0| Value |= (op & UINT64_C(16)) << 18; 5109| 0| Value |= (op & UINT64_C(15)) << 12; 5110| | // op: Rn 5111| 0| op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5112| 0| Value |= (op & UINT64_C(15)) << 16; 5113| 0| Value |= op & UINT64_C(16); 5114| | // op: lane 5115| 0| op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5116| 0| Value |= (op & UINT64_C(3)) << 6; 5117| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5118| 0| break; 5119| 0| } 5120| 0| case ARM::VLD4LNd8: { ------------------ | Branch (5120:5): [True: 0, False: 2.24k] ------------------ 5121| | // op: Vd 5122| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5123| 0| Value |= (op & UINT64_C(16)) << 18; 5124| 0| Value |= (op & UINT64_C(15)) << 12; 5125| | // op: Rn 5126| 0| op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5127| 0| Value |= (op & UINT64_C(15)) << 16; 5128| 0| Value |= op & UINT64_C(16); 5129| | // op: lane 5130| 0| op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5131| 0| Value |= (op & UINT64_C(7)) << 5; 5132| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5133| 0| break; 5134| 0| } 5135| 0| case ARM::VLD4LNd32: ------------------ | Branch (5135:5): [True: 0, False: 2.24k] ------------------ 5136| 0| case ARM::VLD4LNq32: { ------------------ | Branch (5136:5): [True: 0, False: 2.24k] ------------------ 5137| | // op: Vd 5138| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5139| 0| Value |= (op & UINT64_C(16)) << 18; 5140| 0| Value |= (op & UINT64_C(15)) << 12; 5141| | // op: Rn 5142| 0| op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5143| 0| Value |= (op & UINT64_C(15)) << 16; 5144| 0| Value |= op & UINT64_C(48); 5145| | // op: lane 5146| 0| op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5147| 0| Value |= (op & UINT64_C(1)) << 7; 5148| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5149| 0| break; 5150| 0| } 5151| 0| case ARM::VLD4d16: ------------------ | Branch (5151:5): [True: 0, False: 2.24k] ------------------ 5152| 0| case ARM::VLD4d32: ------------------ | Branch (5152:5): [True: 0, False: 2.24k] ------------------ 5153| 0| case ARM::VLD4d8: ------------------ | Branch (5153:5): [True: 0, False: 2.24k] ------------------ 5154| 0| case ARM::VLD4q16: ------------------ | Branch (5154:5): [True: 0, False: 2.24k] ------------------ 5155| 0| case ARM::VLD4q32: ------------------ | Branch (5155:5): [True: 0, False: 2.24k] ------------------ 5156| 0| case ARM::VLD4q8: { ------------------ | Branch (5156:5): [True: 0, False: 2.24k] ------------------ 5157| | // op: Vd 5158| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5159| 0| Value |= (op & UINT64_C(16)) << 18; 5160| 0| Value |= (op & UINT64_C(15)) << 12; 5161| | // op: Rn 5162| 0| op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5163| 0| Value |= (op & UINT64_C(15)) << 16; 5164| 0| Value |= op & UINT64_C(48); 5165| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5166| 0| break; 5167| 0| } 5168| 0| case ARM::VLD4LNd16_UPD: ------------------ | Branch (5168:5): [True: 0, False: 2.24k] ------------------ 5169| 0| case ARM::VLD4LNq16_UPD: { ------------------ | Branch (5169:5): [True: 0, False: 2.24k] ------------------ 5170| | // op: Vd 5171| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5172| 0| Value |= (op & UINT64_C(16)) << 18; 5173| 0| Value |= (op & UINT64_C(15)) << 12; 5174| | // op: Rn 5175| 0| op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5176| 0| Value |= (op & UINT64_C(15)) << 16; 5177| 0| Value |= op & UINT64_C(16); 5178| | // op: Rm 5179| 0| op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5180| 0| Value |= op & UINT64_C(15); 5181| | // op: lane 5182| 0| op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5183| 0| Value |= (op & UINT64_C(3)) << 6; 5184| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5185| 0| break; 5186| 0| } 5187| 0| case ARM::VLD4LNd8_UPD: { ------------------ | Branch (5187:5): [True: 0, False: 2.24k] ------------------ 5188| | // op: Vd 5189| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5190| 0| Value |= (op & UINT64_C(16)) << 18; 5191| 0| Value |= (op & UINT64_C(15)) << 12; 5192| | // op: Rn 5193| 0| op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5194| 0| Value |= (op & UINT64_C(15)) << 16; 5195| 0| Value |= op & UINT64_C(16); 5196| | // op: Rm 5197| 0| op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5198| 0| Value |= op & UINT64_C(15); 5199| | // op: lane 5200| 0| op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5201| 0| Value |= (op & UINT64_C(7)) << 5; 5202| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5203| 0| break; 5204| 0| } 5205| 0| case ARM::VLD4LNd32_UPD: ------------------ | Branch (5205:5): [True: 0, False: 2.24k] ------------------ 5206| 0| case ARM::VLD4LNq32_UPD: { ------------------ | Branch (5206:5): [True: 0, False: 2.24k] ------------------ 5207| | // op: Vd 5208| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5209| 0| Value |= (op & UINT64_C(16)) << 18; 5210| 0| Value |= (op & UINT64_C(15)) << 12; 5211| | // op: Rn 5212| 0| op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5213| 0| Value |= (op & UINT64_C(15)) << 16; 5214| 0| Value |= op & UINT64_C(48); 5215| | // op: Rm 5216| 0| op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5217| 0| Value |= op & UINT64_C(15); 5218| | // op: lane 5219| 0| op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5220| 0| Value |= (op & UINT64_C(1)) << 7; 5221| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5222| 0| break; 5223| 0| } 5224| 0| case ARM::VLD4d16_UPD: ------------------ | Branch (5224:5): [True: 0, False: 2.24k] ------------------ 5225| 0| case ARM::VLD4d32_UPD: ------------------ | Branch (5225:5): [True: 0, False: 2.24k] ------------------ 5226| 0| case ARM::VLD4d8_UPD: ------------------ | Branch (5226:5): [True: 0, False: 2.24k] ------------------ 5227| 0| case ARM::VLD4q16_UPD: ------------------ | Branch (5227:5): [True: 0, False: 2.24k] ------------------ 5228| 0| case ARM::VLD4q32_UPD: ------------------ | Branch (5228:5): [True: 0, False: 2.24k] ------------------ 5229| 0| case ARM::VLD4q8_UPD: { ------------------ | Branch (5229:5): [True: 0, False: 2.24k] ------------------ 5230| | // op: Vd 5231| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5232| 0| Value |= (op & UINT64_C(16)) << 18; 5233| 0| Value |= (op & UINT64_C(15)) << 12; 5234| | // op: Rn 5235| 0| op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5236| 0| Value |= (op & UINT64_C(15)) << 16; 5237| 0| Value |= op & UINT64_C(48); 5238| | // op: Rm 5239| 0| op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5240| 0| Value |= op & UINT64_C(15); 5241| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5242| 0| break; 5243| 0| } 5244| 0| case ARM::VLD1DUPd16: ------------------ | Branch (5244:5): [True: 0, False: 2.24k] ------------------ 5245| 0| case ARM::VLD1DUPd32: ------------------ | Branch (5245:5): [True: 0, False: 2.24k] ------------------ 5246| 0| case ARM::VLD1DUPd8: ------------------ | Branch (5246:5): [True: 0, False: 2.24k] ------------------ 5247| 0| case ARM::VLD1DUPq16: ------------------ | Branch (5247:5): [True: 0, False: 2.24k] ------------------ 5248| 0| case ARM::VLD1DUPq32: ------------------ | Branch (5248:5): [True: 0, False: 2.24k] ------------------ 5249| 0| case ARM::VLD1DUPq8: ------------------ | Branch (5249:5): [True: 0, False: 2.24k] ------------------ 5250| 0| case ARM::VLD2DUPd16: ------------------ | Branch (5250:5): [True: 0, False: 2.24k] ------------------ 5251| 0| case ARM::VLD2DUPd16x2: ------------------ | Branch (5251:5): [True: 0, False: 2.24k] ------------------ 5252| 0| case ARM::VLD2DUPd32: ------------------ | Branch (5252:5): [True: 0, False: 2.24k] ------------------ 5253| 0| case ARM::VLD2DUPd32x2: ------------------ | Branch (5253:5): [True: 0, False: 2.24k] ------------------ 5254| 0| case ARM::VLD2DUPd8: ------------------ | Branch (5254:5): [True: 0, False: 2.24k] ------------------ 5255| 0| case ARM::VLD2DUPd8x2: { ------------------ | Branch (5255:5): [True: 0, False: 2.24k] ------------------ 5256| | // op: Vd 5257| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5258| 0| Value |= (op & UINT64_C(16)) << 18; 5259| 0| Value |= (op & UINT64_C(15)) << 12; 5260| | // op: Rn 5261| 0| op = getAddrMode6DupAddressOpValue(MI, 1, Fixups, STI); 5262| 0| Value |= (op & UINT64_C(15)) << 16; 5263| 0| Value |= op & UINT64_C(16); 5264| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5265| 0| break; 5266| 0| } 5267| 0| case ARM::VLD1DUPd16wb_register: ------------------ | Branch (5267:5): [True: 0, False: 2.24k] ------------------ 5268| 0| case ARM::VLD1DUPd32wb_register: ------------------ | Branch (5268:5): [True: 0, False: 2.24k] ------------------ 5269| 0| case ARM::VLD1DUPd8wb_register: ------------------ | Branch (5269:5): [True: 0, False: 2.24k] ------------------ 5270| 0| case ARM::VLD1DUPq16wb_register: ------------------ | Branch (5270:5): [True: 0, False: 2.24k] ------------------ 5271| 0| case ARM::VLD1DUPq32wb_register: ------------------ | Branch (5271:5): [True: 0, False: 2.24k] ------------------ 5272| 0| case ARM::VLD1DUPq8wb_register: ------------------ | Branch (5272:5): [True: 0, False: 2.24k] ------------------ 5273| 0| case ARM::VLD2DUPd16wb_register: ------------------ | Branch (5273:5): [True: 0, False: 2.24k] ------------------ 5274| 0| case ARM::VLD2DUPd16x2wb_register: ------------------ | Branch (5274:5): [True: 0, False: 2.24k] ------------------ 5275| 0| case ARM::VLD2DUPd32wb_register: ------------------ | Branch (5275:5): [True: 0, False: 2.24k] ------------------ 5276| 0| case ARM::VLD2DUPd32x2wb_register: ------------------ | Branch (5276:5): [True: 0, False: 2.24k] ------------------ 5277| 0| case ARM::VLD2DUPd8wb_register: ------------------ | Branch (5277:5): [True: 0, False: 2.24k] ------------------ 5278| 0| case ARM::VLD2DUPd8x2wb_register: { ------------------ | Branch (5278:5): [True: 0, False: 2.24k] ------------------ 5279| | // op: Vd 5280| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5281| 0| Value |= (op & UINT64_C(16)) << 18; 5282| 0| Value |= (op & UINT64_C(15)) << 12; 5283| | // op: Rn 5284| 0| op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 5285| 0| Value |= (op & UINT64_C(15)) << 16; 5286| 0| Value |= op & UINT64_C(16); 5287| | // op: Rm 5288| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 5289| 0| Value |= op & UINT64_C(15); 5290| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5291| 0| break; 5292| 0| } 5293| 0| case ARM::VLD1DUPd16wb_fixed: ------------------ | Branch (5293:5): [True: 0, False: 2.24k] ------------------ 5294| 0| case ARM::VLD1DUPd32wb_fixed: ------------------ | Branch (5294:5): [True: 0, False: 2.24k] ------------------ 5295| 0| case ARM::VLD1DUPd8wb_fixed: ------------------ | Branch (5295:5): [True: 0, False: 2.24k] ------------------ 5296| 0| case ARM::VLD1DUPq16wb_fixed: ------------------ | Branch (5296:5): [True: 0, False: 2.24k] ------------------ 5297| 0| case ARM::VLD1DUPq32wb_fixed: ------------------ | Branch (5297:5): [True: 0, False: 2.24k] ------------------ 5298| 0| case ARM::VLD1DUPq8wb_fixed: ------------------ | Branch (5298:5): [True: 0, False: 2.24k] ------------------ 5299| 0| case ARM::VLD2DUPd16wb_fixed: ------------------ | Branch (5299:5): [True: 0, False: 2.24k] ------------------ 5300| 0| case ARM::VLD2DUPd16x2wb_fixed: ------------------ | Branch (5300:5): [True: 0, False: 2.24k] ------------------ 5301| 0| case ARM::VLD2DUPd32wb_fixed: ------------------ | Branch (5301:5): [True: 0, False: 2.24k] ------------------ 5302| 0| case ARM::VLD2DUPd32x2wb_fixed: ------------------ | Branch (5302:5): [True: 0, False: 2.24k] ------------------ 5303| 0| case ARM::VLD2DUPd8wb_fixed: ------------------ | Branch (5303:5): [True: 0, False: 2.24k] ------------------ 5304| 0| case ARM::VLD2DUPd8x2wb_fixed: { ------------------ | Branch (5304:5): [True: 0, False: 2.24k] ------------------ 5305| | // op: Vd 5306| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5307| 0| Value |= (op & UINT64_C(16)) << 18; 5308| 0| Value |= (op & UINT64_C(15)) << 12; 5309| | // op: Rn 5310| 0| op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 5311| 0| Value |= (op & UINT64_C(15)) << 16; 5312| 0| Value |= op & UINT64_C(16); 5313| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5314| 0| break; 5315| 0| } 5316| 0| case ARM::VLD3DUPd16: ------------------ | Branch (5316:5): [True: 0, False: 2.24k] ------------------ 5317| 0| case ARM::VLD3DUPd32: ------------------ | Branch (5317:5): [True: 0, False: 2.24k] ------------------ 5318| 0| case ARM::VLD3DUPd8: ------------------ | Branch (5318:5): [True: 0, False: 2.24k] ------------------ 5319| 0| case ARM::VLD3DUPq16: ------------------ | Branch (5319:5): [True: 0, False: 2.24k] ------------------ 5320| 0| case ARM::VLD3DUPq32: ------------------ | Branch (5320:5): [True: 0, False: 2.24k] ------------------ 5321| 0| case ARM::VLD3DUPq8: { ------------------ | Branch (5321:5): [True: 0, False: 2.24k] ------------------ 5322| | // op: Vd 5323| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5324| 0| Value |= (op & UINT64_C(16)) << 18; 5325| 0| Value |= (op & UINT64_C(15)) << 12; 5326| | // op: Rn 5327| 0| op = getAddrMode6DupAddressOpValue(MI, 3, Fixups, STI); 5328| 0| Value |= (op & UINT64_C(15)) << 16; 5329| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5330| 0| break; 5331| 0| } 5332| 0| case ARM::VLD3DUPd16_UPD: ------------------ | Branch (5332:5): [True: 0, False: 2.24k] ------------------ 5333| 0| case ARM::VLD3DUPd32_UPD: ------------------ | Branch (5333:5): [True: 0, False: 2.24k] ------------------ 5334| 0| case ARM::VLD3DUPd8_UPD: ------------------ | Branch (5334:5): [True: 0, False: 2.24k] ------------------ 5335| 0| case ARM::VLD3DUPq16_UPD: ------------------ | Branch (5335:5): [True: 0, False: 2.24k] ------------------ 5336| 0| case ARM::VLD3DUPq32_UPD: ------------------ | Branch (5336:5): [True: 0, False: 2.24k] ------------------ 5337| 0| case ARM::VLD3DUPq8_UPD: { ------------------ | Branch (5337:5): [True: 0, False: 2.24k] ------------------ 5338| | // op: Vd 5339| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5340| 0| Value |= (op & UINT64_C(16)) << 18; 5341| 0| Value |= (op & UINT64_C(15)) << 12; 5342| | // op: Rn 5343| 0| op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5344| 0| Value |= (op & UINT64_C(15)) << 16; 5345| | // op: Rm 5346| 0| op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5347| 0| Value |= op & UINT64_C(15); 5348| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5349| 0| break; 5350| 0| } 5351| 0| case ARM::VLD4DUPd32: ------------------ | Branch (5351:5): [True: 0, False: 2.24k] ------------------ 5352| 0| case ARM::VLD4DUPq32: { ------------------ | Branch (5352:5): [True: 0, False: 2.24k] ------------------ 5353| | // op: Vd 5354| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5355| 0| Value |= (op & UINT64_C(16)) << 18; 5356| 0| Value |= (op & UINT64_C(15)) << 12; 5357| | // op: Rn 5358| 0| op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5359| 0| Value |= (op & UINT64_C(15)) << 16; 5360| 0| Value |= (op & UINT64_C(32)) << 1; 5361| 0| Value |= op & UINT64_C(16); 5362| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5363| 0| break; 5364| 0| } 5365| 0| case ARM::VLD4DUPd16: ------------------ | Branch (5365:5): [True: 0, False: 2.24k] ------------------ 5366| 0| case ARM::VLD4DUPd8: ------------------ | Branch (5366:5): [True: 0, False: 2.24k] ------------------ 5367| 0| case ARM::VLD4DUPq16: ------------------ | Branch (5367:5): [True: 0, False: 2.24k] ------------------ 5368| 0| case ARM::VLD4DUPq8: { ------------------ | Branch (5368:5): [True: 0, False: 2.24k] ------------------ 5369| | // op: Vd 5370| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5371| 0| Value |= (op & UINT64_C(16)) << 18; 5372| 0| Value |= (op & UINT64_C(15)) << 12; 5373| | // op: Rn 5374| 0| op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5375| 0| Value |= (op & UINT64_C(15)) << 16; 5376| 0| Value |= op & UINT64_C(16); 5377| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5378| 0| break; 5379| 0| } 5380| 0| case ARM::VLD4DUPd32_UPD: ------------------ | Branch (5380:5): [True: 0, False: 2.24k] ------------------ 5381| 0| case ARM::VLD4DUPq32_UPD: { ------------------ | Branch (5381:5): [True: 0, False: 2.24k] ------------------ 5382| | // op: Vd 5383| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5384| 0| Value |= (op & UINT64_C(16)) << 18; 5385| 0| Value |= (op & UINT64_C(15)) << 12; 5386| | // op: Rn 5387| 0| op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 5388| 0| Value |= (op & UINT64_C(15)) << 16; 5389| 0| Value |= (op & UINT64_C(32)) << 1; 5390| 0| Value |= op & UINT64_C(16); 5391| | // op: Rm 5392| 0| op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5393| 0| Value |= op & UINT64_C(15); 5394| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5395| 0| break; 5396| 0| } 5397| 0| case ARM::VLD4DUPd16_UPD: ------------------ | Branch (5397:5): [True: 0, False: 2.24k] ------------------ 5398| 0| case ARM::VLD4DUPd8_UPD: ------------------ | Branch (5398:5): [True: 0, False: 2.24k] ------------------ 5399| 0| case ARM::VLD4DUPq16_UPD: ------------------ | Branch (5399:5): [True: 0, False: 2.24k] ------------------ 5400| 0| case ARM::VLD4DUPq8_UPD: { ------------------ | Branch (5400:5): [True: 0, False: 2.24k] ------------------ 5401| | // op: Vd 5402| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5403| 0| Value |= (op & UINT64_C(16)) << 18; 5404| 0| Value |= (op & UINT64_C(15)) << 12; 5405| | // op: Rn 5406| 0| op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 5407| 0| Value |= (op & UINT64_C(15)) << 16; 5408| 0| Value |= op & UINT64_C(16); 5409| | // op: Rm 5410| 0| op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5411| 0| Value |= op & UINT64_C(15); 5412| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5413| 0| break; 5414| 0| } 5415| 0| case ARM::VLD1LNd32: { ------------------ | Branch (5415:5): [True: 0, False: 2.24k] ------------------ 5416| | // op: Vd 5417| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5418| 0| Value |= (op & UINT64_C(16)) << 18; 5419| 0| Value |= (op & UINT64_C(15)) << 12; 5420| | // op: Rn 5421| 0| op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 5422| 0| Value |= (op & UINT64_C(15)) << 16; 5423| 0| Value |= op & UINT64_C(48); 5424| | // op: lane 5425| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 5426| 0| Value |= (op & UINT64_C(1)) << 7; 5427| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5428| 0| break; 5429| 0| } 5430| 0| case ARM::VMOVv16i8: ------------------ | Branch (5430:5): [True: 0, False: 2.24k] ------------------ 5431| 0| case ARM::VMOVv1i64: ------------------ | Branch (5431:5): [True: 0, False: 2.24k] ------------------ 5432| 0| case ARM::VMOVv2f32: ------------------ | Branch (5432:5): [True: 0, False: 2.24k] ------------------ 5433| 0| case ARM::VMOVv2i64: ------------------ | Branch (5433:5): [True: 0, False: 2.24k] ------------------ 5434| 0| case ARM::VMOVv4f32: ------------------ | Branch (5434:5): [True: 0, False: 2.24k] ------------------ 5435| 0| case ARM::VMOVv8i8: { ------------------ | Branch (5435:5): [True: 0, False: 2.24k] ------------------ 5436| | // op: Vd 5437| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5438| 0| Value |= (op & UINT64_C(16)) << 18; 5439| 0| Value |= (op & UINT64_C(15)) << 12; 5440| | // op: SIMM 5441| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5442| 0| Value |= (op & UINT64_C(128)) << 17; 5443| 0| Value |= (op & UINT64_C(112)) << 12; 5444| 0| Value |= op & UINT64_C(15); 5445| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5446| 0| break; 5447| 0| } 5448| 0| case ARM::VBICiv2i32: ------------------ | Branch (5448:5): [True: 0, False: 2.24k] ------------------ 5449| 0| case ARM::VBICiv4i32: ------------------ | Branch (5449:5): [True: 0, False: 2.24k] ------------------ 5450| 0| case ARM::VORRiv2i32: ------------------ | Branch (5450:5): [True: 0, False: 2.24k] ------------------ 5451| 0| case ARM::VORRiv4i32: { ------------------ | Branch (5451:5): [True: 0, False: 2.24k] ------------------ 5452| | // op: Vd 5453| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5454| 0| Value |= (op & UINT64_C(16)) << 18; 5455| 0| Value |= (op & UINT64_C(15)) << 12; 5456| | // op: SIMM 5457| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5458| 0| Value |= (op & UINT64_C(128)) << 17; 5459| 0| Value |= (op & UINT64_C(112)) << 12; 5460| 0| Value |= op & UINT64_C(1536); 5461| 0| Value |= op & UINT64_C(15); 5462| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5463| 0| break; 5464| 0| } 5465| 0| case ARM::VMOVv2i32: ------------------ | Branch (5465:5): [True: 0, False: 2.24k] ------------------ 5466| 0| case ARM::VMOVv4i32: ------------------ | Branch (5466:5): [True: 0, False: 2.24k] ------------------ 5467| 0| case ARM::VMVNv2i32: ------------------ | Branch (5467:5): [True: 0, False: 2.24k] ------------------ 5468| 0| case ARM::VMVNv4i32: { ------------------ | Branch (5468:5): [True: 0, False: 2.24k] ------------------ 5469| | // op: Vd 5470| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5471| 0| Value |= (op & UINT64_C(16)) << 18; 5472| 0| Value |= (op & UINT64_C(15)) << 12; 5473| | // op: SIMM 5474| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5475| 0| Value |= (op & UINT64_C(128)) << 17; 5476| 0| Value |= (op & UINT64_C(112)) << 12; 5477| 0| Value |= op & UINT64_C(3840); 5478| 0| Value |= op & UINT64_C(15); 5479| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5480| 0| break; 5481| 0| } 5482| 0| case ARM::VBICiv4i16: ------------------ | Branch (5482:5): [True: 0, False: 2.24k] ------------------ 5483| 0| case ARM::VBICiv8i16: ------------------ | Branch (5483:5): [True: 0, False: 2.24k] ------------------ 5484| 0| case ARM::VMOVv4i16: ------------------ | Branch (5484:5): [True: 0, False: 2.24k] ------------------ 5485| 0| case ARM::VMOVv8i16: ------------------ | Branch (5485:5): [True: 0, False: 2.24k] ------------------ 5486| 0| case ARM::VMVNv4i16: ------------------ | Branch (5486:5): [True: 0, False: 2.24k] ------------------ 5487| 0| case ARM::VMVNv8i16: ------------------ | Branch (5487:5): [True: 0, False: 2.24k] ------------------ 5488| 0| case ARM::VORRiv4i16: ------------------ | Branch (5488:5): [True: 0, False: 2.24k] ------------------ 5489| 0| case ARM::VORRiv8i16: { ------------------ | Branch (5489:5): [True: 0, False: 2.24k] ------------------ 5490| | // op: Vd 5491| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5492| 0| Value |= (op & UINT64_C(16)) << 18; 5493| 0| Value |= (op & UINT64_C(15)) << 12; 5494| | // op: SIMM 5495| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5496| 0| Value |= (op & UINT64_C(128)) << 17; 5497| 0| Value |= (op & UINT64_C(112)) << 12; 5498| 0| Value |= op & UINT64_C(512); 5499| 0| Value |= op & UINT64_C(15); 5500| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5501| 0| break; 5502| 0| } 5503| 0| case ARM::VQSHLsiv4i16: ------------------ | Branch (5503:5): [True: 0, False: 2.24k] ------------------ 5504| 0| case ARM::VQSHLsiv8i16: ------------------ | Branch (5504:5): [True: 0, False: 2.24k] ------------------ 5505| 0| case ARM::VQSHLsuv4i16: ------------------ | Branch (5505:5): [True: 0, False: 2.24k] ------------------ 5506| 0| case ARM::VQSHLsuv8i16: ------------------ | Branch (5506:5): [True: 0, False: 2.24k] ------------------ 5507| 0| case ARM::VQSHLuiv4i16: ------------------ | Branch (5507:5): [True: 0, False: 2.24k] ------------------ 5508| 0| case ARM::VQSHLuiv8i16: ------------------ | Branch (5508:5): [True: 0, False: 2.24k] ------------------ 5509| 0| case ARM::VSHLLsv4i32: ------------------ | Branch (5509:5): [True: 0, False: 2.24k] ------------------ 5510| 0| case ARM::VSHLLuv4i32: ------------------ | Branch (5510:5): [True: 0, False: 2.24k] ------------------ 5511| 0| case ARM::VSHLiv4i16: ------------------ | Branch (5511:5): [True: 0, False: 2.24k] ------------------ 5512| 0| case ARM::VSHLiv8i16: { ------------------ | Branch (5512:5): [True: 0, False: 2.24k] ------------------ 5513| | // op: Vd 5514| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5515| 0| Value |= (op & UINT64_C(16)) << 18; 5516| 0| Value |= (op & UINT64_C(15)) << 12; 5517| | // op: Vm 5518| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5519| 0| Value |= (op & UINT64_C(16)) << 1; 5520| 0| Value |= op & UINT64_C(15); 5521| | // op: SIMM 5522| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5523| 0| Value |= (op & UINT64_C(15)) << 16; 5524| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5525| 0| break; 5526| 0| } 5527| 0| case ARM::VQSHLsiv2i32: ------------------ | Branch (5527:5): [True: 0, False: 2.24k] ------------------ 5528| 0| case ARM::VQSHLsiv4i32: ------------------ | Branch (5528:5): [True: 0, False: 2.24k] ------------------ 5529| 0| case ARM::VQSHLsuv2i32: ------------------ | Branch (5529:5): [True: 0, False: 2.24k] ------------------ 5530| 0| case ARM::VQSHLsuv4i32: ------------------ | Branch (5530:5): [True: 0, False: 2.24k] ------------------ 5531| 0| case ARM::VQSHLuiv2i32: ------------------ | Branch (5531:5): [True: 0, False: 2.24k] ------------------ 5532| 0| case ARM::VQSHLuiv4i32: ------------------ | Branch (5532:5): [True: 0, False: 2.24k] ------------------ 5533| 0| case ARM::VSHLLsv2i64: ------------------ | Branch (5533:5): [True: 0, False: 2.24k] ------------------ 5534| 0| case ARM::VSHLLuv2i64: ------------------ | Branch (5534:5): [True: 0, False: 2.24k] ------------------ 5535| 0| case ARM::VSHLiv2i32: ------------------ | Branch (5535:5): [True: 0, False: 2.24k] ------------------ 5536| 0| case ARM::VSHLiv4i32: { ------------------ | Branch (5536:5): [True: 0, False: 2.24k] ------------------ 5537| | // op: Vd 5538| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5539| 0| Value |= (op & UINT64_C(16)) << 18; 5540| 0| Value |= (op & UINT64_C(15)) << 12; 5541| | // op: Vm 5542| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5543| 0| Value |= (op & UINT64_C(16)) << 1; 5544| 0| Value |= op & UINT64_C(15); 5545| | // op: SIMM 5546| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5547| 0| Value |= (op & UINT64_C(31)) << 16; 5548| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5549| 0| break; 5550| 0| } 5551| 0| case ARM::VQSHLsiv1i64: ------------------ | Branch (5551:5): [True: 0, False: 2.24k] ------------------ 5552| 0| case ARM::VQSHLsiv2i64: ------------------ | Branch (5552:5): [True: 0, False: 2.24k] ------------------ 5553| 0| case ARM::VQSHLsuv1i64: ------------------ | Branch (5553:5): [True: 0, False: 2.24k] ------------------ 5554| 0| case ARM::VQSHLsuv2i64: ------------------ | Branch (5554:5): [True: 0, False: 2.24k] ------------------ 5555| 0| case ARM::VQSHLuiv1i64: ------------------ | Branch (5555:5): [True: 0, False: 2.24k] ------------------ 5556| 0| case ARM::VQSHLuiv2i64: ------------------ | Branch (5556:5): [True: 0, False: 2.24k] ------------------ 5557| 0| case ARM::VSHLiv1i64: ------------------ | Branch (5557:5): [True: 0, False: 2.24k] ------------------ 5558| 0| case ARM::VSHLiv2i64: { ------------------ | Branch (5558:5): [True: 0, False: 2.24k] ------------------ 5559| | // op: Vd 5560| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5561| 0| Value |= (op & UINT64_C(16)) << 18; 5562| 0| Value |= (op & UINT64_C(15)) << 12; 5563| | // op: Vm 5564| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5565| 0| Value |= (op & UINT64_C(16)) << 1; 5566| 0| Value |= op & UINT64_C(15); 5567| | // op: SIMM 5568| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5569| 0| Value |= (op & UINT64_C(63)) << 16; 5570| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5571| 0| break; 5572| 0| } 5573| 0| case ARM::VQSHLsiv16i8: ------------------ | Branch (5573:5): [True: 0, False: 2.24k] ------------------ 5574| 0| case ARM::VQSHLsiv8i8: ------------------ | Branch (5574:5): [True: 0, False: 2.24k] ------------------ 5575| 0| case ARM::VQSHLsuv16i8: ------------------ | Branch (5575:5): [True: 0, False: 2.24k] ------------------ 5576| 0| case ARM::VQSHLsuv8i8: ------------------ | Branch (5576:5): [True: 0, False: 2.24k] ------------------ 5577| 0| case ARM::VQSHLuiv16i8: ------------------ | Branch (5577:5): [True: 0, False: 2.24k] ------------------ 5578| 0| case ARM::VQSHLuiv8i8: ------------------ | Branch (5578:5): [True: 0, False: 2.24k] ------------------ 5579| 0| case ARM::VSHLLsv8i16: ------------------ | Branch (5579:5): [True: 0, False: 2.24k] ------------------ 5580| 0| case ARM::VSHLLuv8i16: ------------------ | Branch (5580:5): [True: 0, False: 2.24k] ------------------ 5581| 0| case ARM::VSHLiv16i8: ------------------ | Branch (5581:5): [True: 0, False: 2.24k] ------------------ 5582| 0| case ARM::VSHLiv8i8: { ------------------ | Branch (5582:5): [True: 0, False: 2.24k] ------------------ 5583| | // op: Vd 5584| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5585| 0| Value |= (op & UINT64_C(16)) << 18; 5586| 0| Value |= (op & UINT64_C(15)) << 12; 5587| | // op: Vm 5588| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5589| 0| Value |= (op & UINT64_C(16)) << 1; 5590| 0| Value |= op & UINT64_C(15); 5591| | // op: SIMM 5592| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5593| 0| Value |= (op & UINT64_C(7)) << 16; 5594| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5595| 0| break; 5596| 0| } 5597| 0| case ARM::VCVTf2xsd: ------------------ | Branch (5597:5): [True: 0, False: 2.24k] ------------------ 5598| 0| case ARM::VCVTf2xsq: ------------------ | Branch (5598:5): [True: 0, False: 2.24k] ------------------ 5599| 0| case ARM::VCVTf2xud: ------------------ | Branch (5599:5): [True: 0, False: 2.24k] ------------------ 5600| 0| case ARM::VCVTf2xuq: ------------------ | Branch (5600:5): [True: 0, False: 2.24k] ------------------ 5601| 0| case ARM::VCVTh2xsd: ------------------ | Branch (5601:5): [True: 0, False: 2.24k] ------------------ 5602| 0| case ARM::VCVTh2xsq: ------------------ | Branch (5602:5): [True: 0, False: 2.24k] ------------------ 5603| 0| case ARM::VCVTh2xud: ------------------ | Branch (5603:5): [True: 0, False: 2.24k] ------------------ 5604| 0| case ARM::VCVTh2xuq: ------------------ | Branch (5604:5): [True: 0, False: 2.24k] ------------------ 5605| 0| case ARM::VCVTxs2fd: ------------------ | Branch (5605:5): [True: 0, False: 2.24k] ------------------ 5606| 0| case ARM::VCVTxs2fq: ------------------ | Branch (5606:5): [True: 0, False: 2.24k] ------------------ 5607| 0| case ARM::VCVTxs2hd: ------------------ | Branch (5607:5): [True: 0, False: 2.24k] ------------------ 5608| 0| case ARM::VCVTxs2hq: ------------------ | Branch (5608:5): [True: 0, False: 2.24k] ------------------ 5609| 0| case ARM::VCVTxu2fd: ------------------ | Branch (5609:5): [True: 0, False: 2.24k] ------------------ 5610| 0| case ARM::VCVTxu2fq: ------------------ | Branch (5610:5): [True: 0, False: 2.24k] ------------------ 5611| 0| case ARM::VCVTxu2hd: ------------------ | Branch (5611:5): [True: 0, False: 2.24k] ------------------ 5612| 0| case ARM::VCVTxu2hq: { ------------------ | Branch (5612:5): [True: 0, False: 2.24k] ------------------ 5613| | // op: Vd 5614| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5615| 0| Value |= (op & UINT64_C(16)) << 18; 5616| 0| Value |= (op & UINT64_C(15)) << 12; 5617| | // op: Vm 5618| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5619| 0| Value |= (op & UINT64_C(16)) << 1; 5620| 0| Value |= op & UINT64_C(15); 5621| | // op: SIMM 5622| 0| op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 5623| 0| Value |= (op & UINT64_C(63)) << 16; 5624| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5625| 0| break; 5626| 0| } 5627| 0| case ARM::VQRSHRNsv4i16: ------------------ | Branch (5627:5): [True: 0, False: 2.24k] ------------------ 5628| 0| case ARM::VQRSHRNuv4i16: ------------------ | Branch (5628:5): [True: 0, False: 2.24k] ------------------ 5629| 0| case ARM::VQRSHRUNv4i16: ------------------ | Branch (5629:5): [True: 0, False: 2.24k] ------------------ 5630| 0| case ARM::VQSHRNsv4i16: ------------------ | Branch (5630:5): [True: 0, False: 2.24k] ------------------ 5631| 0| case ARM::VQSHRNuv4i16: ------------------ | Branch (5631:5): [True: 0, False: 2.24k] ------------------ 5632| 0| case ARM::VQSHRUNv4i16: ------------------ | Branch (5632:5): [True: 0, False: 2.24k] ------------------ 5633| 0| case ARM::VRSHRNv4i16: ------------------ | Branch (5633:5): [True: 0, False: 2.24k] ------------------ 5634| 0| case ARM::VRSHRsv4i16: ------------------ | Branch (5634:5): [True: 0, False: 2.24k] ------------------ 5635| 0| case ARM::VRSHRsv8i16: ------------------ | Branch (5635:5): [True: 0, False: 2.24k] ------------------ 5636| 0| case ARM::VRSHRuv4i16: ------------------ | Branch (5636:5): [True: 0, False: 2.24k] ------------------ 5637| 0| case ARM::VRSHRuv8i16: ------------------ | Branch (5637:5): [True: 0, False: 2.24k] ------------------ 5638| 0| case ARM::VSHRNv4i16: ------------------ | Branch (5638:5): [True: 0, False: 2.24k] ------------------ 5639| 0| case ARM::VSHRsv4i16: ------------------ | Branch (5639:5): [True: 0, False: 2.24k] ------------------ 5640| 0| case ARM::VSHRsv8i16: ------------------ | Branch (5640:5): [True: 0, False: 2.24k] ------------------ 5641| 0| case ARM::VSHRuv4i16: ------------------ | Branch (5641:5): [True: 0, False: 2.24k] ------------------ 5642| 0| case ARM::VSHRuv8i16: { ------------------ | Branch (5642:5): [True: 0, False: 2.24k] ------------------ 5643| | // op: Vd 5644| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5645| 0| Value |= (op & UINT64_C(16)) << 18; 5646| 0| Value |= (op & UINT64_C(15)) << 12; 5647| | // op: Vm 5648| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5649| 0| Value |= (op & UINT64_C(16)) << 1; 5650| 0| Value |= op & UINT64_C(15); 5651| | // op: SIMM 5652| 0| op = getShiftRight16Imm(MI, 2, Fixups, STI); 5653| 0| Value |= (op & UINT64_C(15)) << 16; 5654| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5655| 0| break; 5656| 0| } 5657| 0| case ARM::VQRSHRNsv2i32: ------------------ | Branch (5657:5): [True: 0, False: 2.24k] ------------------ 5658| 0| case ARM::VQRSHRNuv2i32: ------------------ | Branch (5658:5): [True: 0, False: 2.24k] ------------------ 5659| 0| case ARM::VQRSHRUNv2i32: ------------------ | Branch (5659:5): [True: 0, False: 2.24k] ------------------ 5660| 0| case ARM::VQSHRNsv2i32: ------------------ | Branch (5660:5): [True: 0, False: 2.24k] ------------------ 5661| 0| case ARM::VQSHRNuv2i32: ------------------ | Branch (5661:5): [True: 0, False: 2.24k] ------------------ 5662| 0| case ARM::VQSHRUNv2i32: ------------------ | Branch (5662:5): [True: 0, False: 2.24k] ------------------ 5663| 0| case ARM::VRSHRNv2i32: ------------------ | Branch (5663:5): [True: 0, False: 2.24k] ------------------ 5664| 0| case ARM::VRSHRsv2i32: ------------------ | Branch (5664:5): [True: 0, False: 2.24k] ------------------ 5665| 0| case ARM::VRSHRsv4i32: ------------------ | Branch (5665:5): [True: 0, False: 2.24k] ------------------ 5666| 0| case ARM::VRSHRuv2i32: ------------------ | Branch (5666:5): [True: 0, False: 2.24k] ------------------ 5667| 0| case ARM::VRSHRuv4i32: ------------------ | Branch (5667:5): [True: 0, False: 2.24k] ------------------ 5668| 0| case ARM::VSHRNv2i32: ------------------ | Branch (5668:5): [True: 0, False: 2.24k] ------------------ 5669| 0| case ARM::VSHRsv2i32: ------------------ | Branch (5669:5): [True: 0, False: 2.24k] ------------------ 5670| 0| case ARM::VSHRsv4i32: ------------------ | Branch (5670:5): [True: 0, False: 2.24k] ------------------ 5671| 0| case ARM::VSHRuv2i32: ------------------ | Branch (5671:5): [True: 0, False: 2.24k] ------------------ 5672| 0| case ARM::VSHRuv4i32: { ------------------ | Branch (5672:5): [True: 0, False: 2.24k] ------------------ 5673| | // op: Vd 5674| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5675| 0| Value |= (op & UINT64_C(16)) << 18; 5676| 0| Value |= (op & UINT64_C(15)) << 12; 5677| | // op: Vm 5678| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5679| 0| Value |= (op & UINT64_C(16)) << 1; 5680| 0| Value |= op & UINT64_C(15); 5681| | // op: SIMM 5682| 0| op = getShiftRight32Imm(MI, 2, Fixups, STI); 5683| 0| Value |= (op & UINT64_C(31)) << 16; 5684| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5685| 0| break; 5686| 0| } 5687| 0| case ARM::VRSHRsv1i64: ------------------ | Branch (5687:5): [True: 0, False: 2.24k] ------------------ 5688| 0| case ARM::VRSHRsv2i64: ------------------ | Branch (5688:5): [True: 0, False: 2.24k] ------------------ 5689| 0| case ARM::VRSHRuv1i64: ------------------ | Branch (5689:5): [True: 0, False: 2.24k] ------------------ 5690| 0| case ARM::VRSHRuv2i64: ------------------ | Branch (5690:5): [True: 0, False: 2.24k] ------------------ 5691| 0| case ARM::VSHRsv1i64: ------------------ | Branch (5691:5): [True: 0, False: 2.24k] ------------------ 5692| 0| case ARM::VSHRsv2i64: ------------------ | Branch (5692:5): [True: 0, False: 2.24k] ------------------ 5693| 0| case ARM::VSHRuv1i64: ------------------ | Branch (5693:5): [True: 0, False: 2.24k] ------------------ 5694| 0| case ARM::VSHRuv2i64: { ------------------ | Branch (5694:5): [True: 0, False: 2.24k] ------------------ 5695| | // op: Vd 5696| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5697| 0| Value |= (op & UINT64_C(16)) << 18; 5698| 0| Value |= (op & UINT64_C(15)) << 12; 5699| | // op: Vm 5700| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5701| 0| Value |= (op & UINT64_C(16)) << 1; 5702| 0| Value |= op & UINT64_C(15); 5703| | // op: SIMM 5704| 0| op = getShiftRight64Imm(MI, 2, Fixups, STI); 5705| 0| Value |= (op & UINT64_C(63)) << 16; 5706| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5707| 0| break; 5708| 0| } 5709| 0| case ARM::VQRSHRNsv8i8: ------------------ | Branch (5709:5): [True: 0, False: 2.24k] ------------------ 5710| 0| case ARM::VQRSHRNuv8i8: ------------------ | Branch (5710:5): [True: 0, False: 2.24k] ------------------ 5711| 0| case ARM::VQRSHRUNv8i8: ------------------ | Branch (5711:5): [True: 0, False: 2.24k] ------------------ 5712| 0| case ARM::VQSHRNsv8i8: ------------------ | Branch (5712:5): [True: 0, False: 2.24k] ------------------ 5713| 0| case ARM::VQSHRNuv8i8: ------------------ | Branch (5713:5): [True: 0, False: 2.24k] ------------------ 5714| 0| case ARM::VQSHRUNv8i8: ------------------ | Branch (5714:5): [True: 0, False: 2.24k] ------------------ 5715| 0| case ARM::VRSHRNv8i8: ------------------ | Branch (5715:5): [True: 0, False: 2.24k] ------------------ 5716| 0| case ARM::VRSHRsv16i8: ------------------ | Branch (5716:5): [True: 0, False: 2.24k] ------------------ 5717| 0| case ARM::VRSHRsv8i8: ------------------ | Branch (5717:5): [True: 0, False: 2.24k] ------------------ 5718| 0| case ARM::VRSHRuv16i8: ------------------ | Branch (5718:5): [True: 0, False: 2.24k] ------------------ 5719| 0| case ARM::VRSHRuv8i8: ------------------ | Branch (5719:5): [True: 0, False: 2.24k] ------------------ 5720| 0| case ARM::VSHRNv8i8: ------------------ | Branch (5720:5): [True: 0, False: 2.24k] ------------------ 5721| 0| case ARM::VSHRsv16i8: ------------------ | Branch (5721:5): [True: 0, False: 2.24k] ------------------ 5722| 0| case ARM::VSHRsv8i8: ------------------ | Branch (5722:5): [True: 0, False: 2.24k] ------------------ 5723| 0| case ARM::VSHRuv16i8: ------------------ | Branch (5723:5): [True: 0, False: 2.24k] ------------------ 5724| 0| case ARM::VSHRuv8i8: { ------------------ | Branch (5724:5): [True: 0, False: 2.24k] ------------------ 5725| | // op: Vd 5726| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5727| 0| Value |= (op & UINT64_C(16)) << 18; 5728| 0| Value |= (op & UINT64_C(15)) << 12; 5729| | // op: Vm 5730| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5731| 0| Value |= (op & UINT64_C(16)) << 1; 5732| 0| Value |= op & UINT64_C(15); 5733| | // op: SIMM 5734| 0| op = getShiftRight8Imm(MI, 2, Fixups, STI); 5735| 0| Value |= (op & UINT64_C(7)) << 16; 5736| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5737| 0| break; 5738| 0| } 5739| 0| case ARM::VDUPLN32d: ------------------ | Branch (5739:5): [True: 0, False: 2.24k] ------------------ 5740| 0| case ARM::VDUPLN32q: { ------------------ | Branch (5740:5): [True: 0, False: 2.24k] ------------------ 5741| | // op: Vd 5742| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5743| 0| Value |= (op & UINT64_C(16)) << 18; 5744| 0| Value |= (op & UINT64_C(15)) << 12; 5745| | // op: Vm 5746| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5747| 0| Value |= (op & UINT64_C(16)) << 1; 5748| 0| Value |= op & UINT64_C(15); 5749| | // op: lane 5750| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5751| 0| Value |= (op & UINT64_C(1)) << 19; 5752| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5753| 0| break; 5754| 0| } 5755| 0| case ARM::VDUPLN16d: ------------------ | Branch (5755:5): [True: 0, False: 2.24k] ------------------ 5756| 0| case ARM::VDUPLN16q: { ------------------ | Branch (5756:5): [True: 0, False: 2.24k] ------------------ 5757| | // op: Vd 5758| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5759| 0| Value |= (op & UINT64_C(16)) << 18; 5760| 0| Value |= (op & UINT64_C(15)) << 12; 5761| | // op: Vm 5762| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5763| 0| Value |= (op & UINT64_C(16)) << 1; 5764| 0| Value |= op & UINT64_C(15); 5765| | // op: lane 5766| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5767| 0| Value |= (op & UINT64_C(3)) << 18; 5768| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5769| 0| break; 5770| 0| } 5771| 0| case ARM::VDUPLN8d: ------------------ | Branch (5771:5): [True: 0, False: 2.24k] ------------------ 5772| 0| case ARM::VDUPLN8q: { ------------------ | Branch (5772:5): [True: 0, False: 2.24k] ------------------ 5773| | // op: Vd 5774| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5775| 0| Value |= (op & UINT64_C(16)) << 18; 5776| 0| Value |= (op & UINT64_C(15)) << 12; 5777| | // op: Vm 5778| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5779| 0| Value |= (op & UINT64_C(16)) << 1; 5780| 0| Value |= op & UINT64_C(15); 5781| | // op: lane 5782| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5783| 0| Value |= (op & UINT64_C(7)) << 17; 5784| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5785| 0| break; 5786| 0| } 5787| 0| case ARM::AESIMC: ------------------ | Branch (5787:5): [True: 0, False: 2.24k] ------------------ 5788| 0| case ARM::AESMC: ------------------ | Branch (5788:5): [True: 0, False: 2.24k] ------------------ 5789| 0| case ARM::SHA1H: ------------------ | Branch (5789:5): [True: 0, False: 2.24k] ------------------ 5790| 0| case ARM::VABSfd: ------------------ | Branch (5790:5): [True: 0, False: 2.24k] ------------------ 5791| 0| case ARM::VABSfq: ------------------ | Branch (5791:5): [True: 0, False: 2.24k] ------------------ 5792| 0| case ARM::VABShd: ------------------ | Branch (5792:5): [True: 0, False: 2.24k] ------------------ 5793| 0| case ARM::VABShq: ------------------ | Branch (5793:5): [True: 0, False: 2.24k] ------------------ 5794| 0| case ARM::VABSv16i8: ------------------ | Branch (5794:5): [True: 0, False: 2.24k] ------------------ 5795| 0| case ARM::VABSv2i32: ------------------ | Branch (5795:5): [True: 0, False: 2.24k] ------------------ 5796| 0| case ARM::VABSv4i16: ------------------ | Branch (5796:5): [True: 0, False: 2.24k] ------------------ 5797| 0| case ARM::VABSv4i32: ------------------ | Branch (5797:5): [True: 0, False: 2.24k] ------------------ 5798| 0| case ARM::VABSv8i16: ------------------ | Branch (5798:5): [True: 0, False: 2.24k] ------------------ 5799| 0| case ARM::VABSv8i8: ------------------ | Branch (5799:5): [True: 0, False: 2.24k] ------------------ 5800| 0| case ARM::VCEQzv16i8: ------------------ | Branch (5800:5): [True: 0, False: 2.24k] ------------------ 5801| 0| case ARM::VCEQzv2f32: ------------------ | Branch (5801:5): [True: 0, False: 2.24k] ------------------ 5802| 0| case ARM::VCEQzv2i32: ------------------ | Branch (5802:5): [True: 0, False: 2.24k] ------------------ 5803| 0| case ARM::VCEQzv4f16: ------------------ | Branch (5803:5): [True: 0, False: 2.24k] ------------------ 5804| 0| case ARM::VCEQzv4f32: ------------------ | Branch (5804:5): [True: 0, False: 2.24k] ------------------ 5805| 0| case ARM::VCEQzv4i16: ------------------ | Branch (5805:5): [True: 0, False: 2.24k] ------------------ 5806| 0| case ARM::VCEQzv4i32: ------------------ | Branch (5806:5): [True: 0, False: 2.24k] ------------------ 5807| 0| case ARM::VCEQzv8f16: ------------------ | Branch (5807:5): [True: 0, False: 2.24k] ------------------ 5808| 0| case ARM::VCEQzv8i16: ------------------ | Branch (5808:5): [True: 0, False: 2.24k] ------------------ 5809| 0| case ARM::VCEQzv8i8: ------------------ | Branch (5809:5): [True: 0, False: 2.24k] ------------------ 5810| 0| case ARM::VCGEzv16i8: ------------------ | Branch (5810:5): [True: 0, False: 2.24k] ------------------ 5811| 0| case ARM::VCGEzv2f32: ------------------ | Branch (5811:5): [True: 0, False: 2.24k] ------------------ 5812| 0| case ARM::VCGEzv2i32: ------------------ | Branch (5812:5): [True: 0, False: 2.24k] ------------------ 5813| 0| case ARM::VCGEzv4f16: ------------------ | Branch (5813:5): [True: 0, False: 2.24k] ------------------ 5814| 0| case ARM::VCGEzv4f32: ------------------ | Branch (5814:5): [True: 0, False: 2.24k] ------------------ 5815| 0| case ARM::VCGEzv4i16: ------------------ | Branch (5815:5): [True: 0, False: 2.24k] ------------------ 5816| 0| case ARM::VCGEzv4i32: ------------------ | Branch (5816:5): [True: 0, False: 2.24k] ------------------ 5817| 0| case ARM::VCGEzv8f16: ------------------ | Branch (5817:5): [True: 0, False: 2.24k] ------------------ 5818| 0| case ARM::VCGEzv8i16: ------------------ | Branch (5818:5): [True: 0, False: 2.24k] ------------------ 5819| 0| case ARM::VCGEzv8i8: ------------------ | Branch (5819:5): [True: 0, False: 2.24k] ------------------ 5820| 0| case ARM::VCGTzv16i8: ------------------ | Branch (5820:5): [True: 0, False: 2.24k] ------------------ 5821| 0| case ARM::VCGTzv2f32: ------------------ | Branch (5821:5): [True: 0, False: 2.24k] ------------------ 5822| 0| case ARM::VCGTzv2i32: ------------------ | Branch (5822:5): [True: 0, False: 2.24k] ------------------ 5823| 0| case ARM::VCGTzv4f16: ------------------ | Branch (5823:5): [True: 0, False: 2.24k] ------------------ 5824| 0| case ARM::VCGTzv4f32: ------------------ | Branch (5824:5): [True: 0, False: 2.24k] ------------------ 5825| 0| case ARM::VCGTzv4i16: ------------------ | Branch (5825:5): [True: 0, False: 2.24k] ------------------ 5826| 0| case ARM::VCGTzv4i32: ------------------ | Branch (5826:5): [True: 0, False: 2.24k] ------------------ 5827| 0| case ARM::VCGTzv8f16: ------------------ | Branch (5827:5): [True: 0, False: 2.24k] ------------------ 5828| 0| case ARM::VCGTzv8i16: ------------------ | Branch (5828:5): [True: 0, False: 2.24k] ------------------ 5829| 0| case ARM::VCGTzv8i8: ------------------ | Branch (5829:5): [True: 0, False: 2.24k] ------------------ 5830| 0| case ARM::VCLEzv16i8: ------------------ | Branch (5830:5): [True: 0, False: 2.24k] ------------------ 5831| 0| case ARM::VCLEzv2f32: ------------------ | Branch (5831:5): [True: 0, False: 2.24k] ------------------ 5832| 0| case ARM::VCLEzv2i32: ------------------ | Branch (5832:5): [True: 0, False: 2.24k] ------------------ 5833| 0| case ARM::VCLEzv4f16: ------------------ | Branch (5833:5): [True: 0, False: 2.24k] ------------------ 5834| 0| case ARM::VCLEzv4f32: ------------------ | Branch (5834:5): [True: 0, False: 2.24k] ------------------ 5835| 0| case ARM::VCLEzv4i16: ------------------ | Branch (5835:5): [True: 0, False: 2.24k] ------------------ 5836| 0| case ARM::VCLEzv4i32: ------------------ | Branch (5836:5): [True: 0, False: 2.24k] ------------------ 5837| 0| case ARM::VCLEzv8f16: ------------------ | Branch (5837:5): [True: 0, False: 2.24k] ------------------ 5838| 0| case ARM::VCLEzv8i16: ------------------ | Branch (5838:5): [True: 0, False: 2.24k] ------------------ 5839| 0| case ARM::VCLEzv8i8: ------------------ | Branch (5839:5): [True: 0, False: 2.24k] ------------------ 5840| 0| case ARM::VCLSv16i8: ------------------ | Branch (5840:5): [True: 0, False: 2.24k] ------------------ 5841| 0| case ARM::VCLSv2i32: ------------------ | Branch (5841:5): [True: 0, False: 2.24k] ------------------ 5842| 0| case ARM::VCLSv4i16: ------------------ | Branch (5842:5): [True: 0, False: 2.24k] ------------------ 5843| 0| case ARM::VCLSv4i32: ------------------ | Branch (5843:5): [True: 0, False: 2.24k] ------------------ 5844| 0| case ARM::VCLSv8i16: ------------------ | Branch (5844:5): [True: 0, False: 2.24k] ------------------ 5845| 0| case ARM::VCLSv8i8: ------------------ | Branch (5845:5): [True: 0, False: 2.24k] ------------------ 5846| 0| case ARM::VCLTzv16i8: ------------------ | Branch (5846:5): [True: 0, False: 2.24k] ------------------ 5847| 0| case ARM::VCLTzv2f32: ------------------ | Branch (5847:5): [True: 0, False: 2.24k] ------------------ 5848| 0| case ARM::VCLTzv2i32: ------------------ | Branch (5848:5): [True: 0, False: 2.24k] ------------------ 5849| 0| case ARM::VCLTzv4f16: ------------------ | Branch (5849:5): [True: 0, False: 2.24k] ------------------ 5850| 0| case ARM::VCLTzv4f32: ------------------ | Branch (5850:5): [True: 0, False: 2.24k] ------------------ 5851| 0| case ARM::VCLTzv4i16: ------------------ | Branch (5851:5): [True: 0, False: 2.24k] ------------------ 5852| 0| case ARM::VCLTzv4i32: ------------------ | Branch (5852:5): [True: 0, False: 2.24k] ------------------ 5853| 0| case ARM::VCLTzv8f16: ------------------ | Branch (5853:5): [True: 0, False: 2.24k] ------------------ 5854| 0| case ARM::VCLTzv8i16: ------------------ | Branch (5854:5): [True: 0, False: 2.24k] ------------------ 5855| 0| case ARM::VCLTzv8i8: ------------------ | Branch (5855:5): [True: 0, False: 2.24k] ------------------ 5856| 0| case ARM::VCLZv16i8: ------------------ | Branch (5856:5): [True: 0, False: 2.24k] ------------------ 5857| 0| case ARM::VCLZv2i32: ------------------ | Branch (5857:5): [True: 0, False: 2.24k] ------------------ 5858| 0| case ARM::VCLZv4i16: ------------------ | Branch (5858:5): [True: 0, False: 2.24k] ------------------ 5859| 0| case ARM::VCLZv4i32: ------------------ | Branch (5859:5): [True: 0, False: 2.24k] ------------------ 5860| 0| case ARM::VCLZv8i16: ------------------ | Branch (5860:5): [True: 0, False: 2.24k] ------------------ 5861| 0| case ARM::VCLZv8i8: ------------------ | Branch (5861:5): [True: 0, False: 2.24k] ------------------ 5862| 0| case ARM::VCNTd: ------------------ | Branch (5862:5): [True: 0, False: 2.24k] ------------------ 5863| 0| case ARM::VCNTq: ------------------ | Branch (5863:5): [True: 0, False: 2.24k] ------------------ 5864| 0| case ARM::VCVTf2h: ------------------ | Branch (5864:5): [True: 0, False: 2.24k] ------------------ 5865| 0| case ARM::VCVTf2sd: ------------------ | Branch (5865:5): [True: 0, False: 2.24k] ------------------ 5866| 0| case ARM::VCVTf2sq: ------------------ | Branch (5866:5): [True: 0, False: 2.24k] ------------------ 5867| 0| case ARM::VCVTf2ud: ------------------ | Branch (5867:5): [True: 0, False: 2.24k] ------------------ 5868| 0| case ARM::VCVTf2uq: ------------------ | Branch (5868:5): [True: 0, False: 2.24k] ------------------ 5869| 0| case ARM::VCVTh2f: ------------------ | Branch (5869:5): [True: 0, False: 2.24k] ------------------ 5870| 0| case ARM::VCVTh2sd: ------------------ | Branch (5870:5): [True: 0, False: 2.24k] ------------------ 5871| 0| case ARM::VCVTh2sq: ------------------ | Branch (5871:5): [True: 0, False: 2.24k] ------------------ 5872| 0| case ARM::VCVTh2ud: ------------------ | Branch (5872:5): [True: 0, False: 2.24k] ------------------ 5873| 0| case ARM::VCVTh2uq: ------------------ | Branch (5873:5): [True: 0, False: 2.24k] ------------------ 5874| 0| case ARM::VCVTs2fd: ------------------ | Branch (5874:5): [True: 0, False: 2.24k] ------------------ 5875| 0| case ARM::VCVTs2fq: ------------------ | Branch (5875:5): [True: 0, False: 2.24k] ------------------ 5876| 0| case ARM::VCVTs2hd: ------------------ | Branch (5876:5): [True: 0, False: 2.24k] ------------------ 5877| 0| case ARM::VCVTs2hq: ------------------ | Branch (5877:5): [True: 0, False: 2.24k] ------------------ 5878| 0| case ARM::VCVTu2fd: ------------------ | Branch (5878:5): [True: 0, False: 2.24k] ------------------ 5879| 0| case ARM::VCVTu2fq: ------------------ | Branch (5879:5): [True: 0, False: 2.24k] ------------------ 5880| 0| case ARM::VCVTu2hd: ------------------ | Branch (5880:5): [True: 0, False: 2.24k] ------------------ 5881| 0| case ARM::VCVTu2hq: ------------------ | Branch (5881:5): [True: 0, False: 2.24k] ------------------ 5882| 0| case ARM::VMOVLsv2i64: ------------------ | Branch (5882:5): [True: 0, False: 2.24k] ------------------ 5883| 0| case ARM::VMOVLsv4i32: ------------------ | Branch (5883:5): [True: 0, False: 2.24k] ------------------ 5884| 0| case ARM::VMOVLsv8i16: ------------------ | Branch (5884:5): [True: 0, False: 2.24k] ------------------ 5885| 0| case ARM::VMOVLuv2i64: ------------------ | Branch (5885:5): [True: 0, False: 2.24k] ------------------ 5886| 0| case ARM::VMOVLuv4i32: ------------------ | Branch (5886:5): [True: 0, False: 2.24k] ------------------ 5887| 0| case ARM::VMOVLuv8i16: ------------------ | Branch (5887:5): [True: 0, False: 2.24k] ------------------ 5888| 0| case ARM::VMOVNv2i32: ------------------ | Branch (5888:5): [True: 0, False: 2.24k] ------------------ 5889| 0| case ARM::VMOVNv4i16: ------------------ | Branch (5889:5): [True: 0, False: 2.24k] ------------------ 5890| 0| case ARM::VMOVNv8i8: ------------------ | Branch (5890:5): [True: 0, False: 2.24k] ------------------ 5891| 0| case ARM::VMVNd: ------------------ | Branch (5891:5): [True: 0, False: 2.24k] ------------------ 5892| 0| case ARM::VMVNq: ------------------ | Branch (5892:5): [True: 0, False: 2.24k] ------------------ 5893| 0| case ARM::VNEGf32q: ------------------ | Branch (5893:5): [True: 0, False: 2.24k] ------------------ 5894| 0| case ARM::VNEGfd: ------------------ | Branch (5894:5): [True: 0, False: 2.24k] ------------------ 5895| 0| case ARM::VNEGhd: ------------------ | Branch (5895:5): [True: 0, False: 2.24k] ------------------ 5896| 0| case ARM::VNEGhq: ------------------ | Branch (5896:5): [True: 0, False: 2.24k] ------------------ 5897| 0| case ARM::VNEGs16d: ------------------ | Branch (5897:5): [True: 0, False: 2.24k] ------------------ 5898| 0| case ARM::VNEGs16q: ------------------ | Branch (5898:5): [True: 0, False: 2.24k] ------------------ 5899| 0| case ARM::VNEGs32d: ------------------ | Branch (5899:5): [True: 0, False: 2.24k] ------------------ 5900| 0| case ARM::VNEGs32q: ------------------ | Branch (5900:5): [True: 0, False: 2.24k] ------------------ 5901| 0| case ARM::VNEGs8d: ------------------ | Branch (5901:5): [True: 0, False: 2.24k] ------------------ 5902| 0| case ARM::VNEGs8q: ------------------ | Branch (5902:5): [True: 0, False: 2.24k] ------------------ 5903| 0| case ARM::VPADDLsv16i8: ------------------ | Branch (5903:5): [True: 0, False: 2.24k] ------------------ 5904| 0| case ARM::VPADDLsv2i32: ------------------ | Branch (5904:5): [True: 0, False: 2.24k] ------------------ 5905| 0| case ARM::VPADDLsv4i16: ------------------ | Branch (5905:5): [True: 0, False: 2.24k] ------------------ 5906| 0| case ARM::VPADDLsv4i32: ------------------ | Branch (5906:5): [True: 0, False: 2.24k] ------------------ 5907| 0| case ARM::VPADDLsv8i16: ------------------ | Branch (5907:5): [True: 0, False: 2.24k] ------------------ 5908| 0| case ARM::VPADDLsv8i8: ------------------ | Branch (5908:5): [True: 0, False: 2.24k] ------------------ 5909| 0| case ARM::VPADDLuv16i8: ------------------ | Branch (5909:5): [True: 0, False: 2.24k] ------------------ 5910| 0| case ARM::VPADDLuv2i32: ------------------ | Branch (5910:5): [True: 0, False: 2.24k] ------------------ 5911| 0| case ARM::VPADDLuv4i16: ------------------ | Branch (5911:5): [True: 0, False: 2.24k] ------------------ 5912| 0| case ARM::VPADDLuv4i32: ------------------ | Branch (5912:5): [True: 0, False: 2.24k] ------------------ 5913| 0| case ARM::VPADDLuv8i16: ------------------ | Branch (5913:5): [True: 0, False: 2.24k] ------------------ 5914| 0| case ARM::VPADDLuv8i8: ------------------ | Branch (5914:5): [True: 0, False: 2.24k] ------------------ 5915| 0| case ARM::VQABSv16i8: ------------------ | Branch (5915:5): [True: 0, False: 2.24k] ------------------ 5916| 0| case ARM::VQABSv2i32: ------------------ | Branch (5916:5): [True: 0, False: 2.24k] ------------------ 5917| 0| case ARM::VQABSv4i16: ------------------ | Branch (5917:5): [True: 0, False: 2.24k] ------------------ 5918| 0| case ARM::VQABSv4i32: ------------------ | Branch (5918:5): [True: 0, False: 2.24k] ------------------ 5919| 0| case ARM::VQABSv8i16: ------------------ | Branch (5919:5): [True: 0, False: 2.24k] ------------------ 5920| 0| case ARM::VQABSv8i8: ------------------ | Branch (5920:5): [True: 0, False: 2.24k] ------------------ 5921| 0| case ARM::VQMOVNsuv2i32: ------------------ | Branch (5921:5): [True: 0, False: 2.24k] ------------------ 5922| 0| case ARM::VQMOVNsuv4i16: ------------------ | Branch (5922:5): [True: 0, False: 2.24k] ------------------ 5923| 0| case ARM::VQMOVNsuv8i8: ------------------ | Branch (5923:5): [True: 0, False: 2.24k] ------------------ 5924| 0| case ARM::VQMOVNsv2i32: ------------------ | Branch (5924:5): [True: 0, False: 2.24k] ------------------ 5925| 0| case ARM::VQMOVNsv4i16: ------------------ | Branch (5925:5): [True: 0, False: 2.24k] ------------------ 5926| 0| case ARM::VQMOVNsv8i8: ------------------ | Branch (5926:5): [True: 0, False: 2.24k] ------------------ 5927| 0| case ARM::VQMOVNuv2i32: ------------------ | Branch (5927:5): [True: 0, False: 2.24k] ------------------ 5928| 0| case ARM::VQMOVNuv4i16: ------------------ | Branch (5928:5): [True: 0, False: 2.24k] ------------------ 5929| 0| case ARM::VQMOVNuv8i8: ------------------ | Branch (5929:5): [True: 0, False: 2.24k] ------------------ 5930| 0| case ARM::VQNEGv16i8: ------------------ | Branch (5930:5): [True: 0, False: 2.24k] ------------------ 5931| 0| case ARM::VQNEGv2i32: ------------------ | Branch (5931:5): [True: 0, False: 2.24k] ------------------ 5932| 0| case ARM::VQNEGv4i16: ------------------ | Branch (5932:5): [True: 0, False: 2.24k] ------------------ 5933| 0| case ARM::VQNEGv4i32: ------------------ | Branch (5933:5): [True: 0, False: 2.24k] ------------------ 5934| 0| case ARM::VQNEGv8i16: ------------------ | Branch (5934:5): [True: 0, False: 2.24k] ------------------ 5935| 0| case ARM::VQNEGv8i8: ------------------ | Branch (5935:5): [True: 0, False: 2.24k] ------------------ 5936| 0| case ARM::VRECPEd: ------------------ | Branch (5936:5): [True: 0, False: 2.24k] ------------------ 5937| 0| case ARM::VRECPEfd: ------------------ | Branch (5937:5): [True: 0, False: 2.24k] ------------------ 5938| 0| case ARM::VRECPEfq: ------------------ | Branch (5938:5): [True: 0, False: 2.24k] ------------------ 5939| 0| case ARM::VRECPEhd: ------------------ | Branch (5939:5): [True: 0, False: 2.24k] ------------------ 5940| 0| case ARM::VRECPEhq: ------------------ | Branch (5940:5): [True: 0, False: 2.24k] ------------------ 5941| 0| case ARM::VRECPEq: ------------------ | Branch (5941:5): [True: 0, False: 2.24k] ------------------ 5942| 0| case ARM::VREV16d8: ------------------ | Branch (5942:5): [True: 0, False: 2.24k] ------------------ 5943| 0| case ARM::VREV16q8: ------------------ | Branch (5943:5): [True: 0, False: 2.24k] ------------------ 5944| 0| case ARM::VREV32d16: ------------------ | Branch (5944:5): [True: 0, False: 2.24k] ------------------ 5945| 0| case ARM::VREV32d8: ------------------ | Branch (5945:5): [True: 0, False: 2.24k] ------------------ 5946| 0| case ARM::VREV32q16: ------------------ | Branch (5946:5): [True: 0, False: 2.24k] ------------------ 5947| 0| case ARM::VREV32q8: ------------------ | Branch (5947:5): [True: 0, False: 2.24k] ------------------ 5948| 0| case ARM::VREV64d16: ------------------ | Branch (5948:5): [True: 0, False: 2.24k] ------------------ 5949| 0| case ARM::VREV64d32: ------------------ | Branch (5949:5): [True: 0, False: 2.24k] ------------------ 5950| 0| case ARM::VREV64d8: ------------------ | Branch (5950:5): [True: 0, False: 2.24k] ------------------ 5951| 0| case ARM::VREV64q16: ------------------ | Branch (5951:5): [True: 0, False: 2.24k] ------------------ 5952| 0| case ARM::VREV64q32: ------------------ | Branch (5952:5): [True: 0, False: 2.24k] ------------------ 5953| 0| case ARM::VREV64q8: ------------------ | Branch (5953:5): [True: 0, False: 2.24k] ------------------ 5954| 0| case ARM::VRSQRTEd: ------------------ | Branch (5954:5): [True: 0, False: 2.24k] ------------------ 5955| 0| case ARM::VRSQRTEfd: ------------------ | Branch (5955:5): [True: 0, False: 2.24k] ------------------ 5956| 0| case ARM::VRSQRTEfq: ------------------ | Branch (5956:5): [True: 0, False: 2.24k] ------------------ 5957| 0| case ARM::VRSQRTEhd: ------------------ | Branch (5957:5): [True: 0, False: 2.24k] ------------------ 5958| 0| case ARM::VRSQRTEhq: ------------------ | Branch (5958:5): [True: 0, False: 2.24k] ------------------ 5959| 0| case ARM::VRSQRTEq: ------------------ | Branch (5959:5): [True: 0, False: 2.24k] ------------------ 5960| 0| case ARM::VSHLLi16: ------------------ | Branch (5960:5): [True: 0, False: 2.24k] ------------------ 5961| 0| case ARM::VSHLLi32: ------------------ | Branch (5961:5): [True: 0, False: 2.24k] ------------------ 5962| 0| case ARM::VSHLLi8: ------------------ | Branch (5962:5): [True: 0, False: 2.24k] ------------------ 5963| 0| case ARM::VSWPd: ------------------ | Branch (5963:5): [True: 0, False: 2.24k] ------------------ 5964| 0| case ARM::VSWPq: ------------------ | Branch (5964:5): [True: 0, False: 2.24k] ------------------ 5965| 0| case ARM::VTRNd16: ------------------ | Branch (5965:5): [True: 0, False: 2.24k] ------------------ 5966| 0| case ARM::VTRNd32: ------------------ | Branch (5966:5): [True: 0, False: 2.24k] ------------------ 5967| 0| case ARM::VTRNd8: ------------------ | Branch (5967:5): [True: 0, False: 2.24k] ------------------ 5968| 0| case ARM::VTRNq16: ------------------ | Branch (5968:5): [True: 0, False: 2.24k] ------------------ 5969| 0| case ARM::VTRNq32: ------------------ | Branch (5969:5): [True: 0, False: 2.24k] ------------------ 5970| 0| case ARM::VTRNq8: ------------------ | Branch (5970:5): [True: 0, False: 2.24k] ------------------ 5971| 0| case ARM::VUZPd16: ------------------ | Branch (5971:5): [True: 0, False: 2.24k] ------------------ 5972| 0| case ARM::VUZPd8: ------------------ | Branch (5972:5): [True: 0, False: 2.24k] ------------------ 5973| 0| case ARM::VUZPq16: ------------------ | Branch (5973:5): [True: 0, False: 2.24k] ------------------ 5974| 0| case ARM::VUZPq32: ------------------ | Branch (5974:5): [True: 0, False: 2.24k] ------------------ 5975| 0| case ARM::VUZPq8: ------------------ | Branch (5975:5): [True: 0, False: 2.24k] ------------------ 5976| 0| case ARM::VZIPd16: ------------------ | Branch (5976:5): [True: 0, False: 2.24k] ------------------ 5977| 0| case ARM::VZIPd8: ------------------ | Branch (5977:5): [True: 0, False: 2.24k] ------------------ 5978| 0| case ARM::VZIPq16: ------------------ | Branch (5978:5): [True: 0, False: 2.24k] ------------------ 5979| 0| case ARM::VZIPq32: ------------------ | Branch (5979:5): [True: 0, False: 2.24k] ------------------ 5980| 0| case ARM::VZIPq8: { ------------------ | Branch (5980:5): [True: 0, False: 2.24k] ------------------ 5981| | // op: Vd 5982| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5983| 0| Value |= (op & UINT64_C(16)) << 18; 5984| 0| Value |= (op & UINT64_C(15)) << 12; 5985| | // op: Vm 5986| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5987| 0| Value |= (op & UINT64_C(16)) << 1; 5988| 0| Value |= op & UINT64_C(15); 5989| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5990| 0| break; 5991| 0| } 5992| 0| case ARM::VCVTANSDf: ------------------ | Branch (5992:5): [True: 0, False: 2.24k] ------------------ 5993| 0| case ARM::VCVTANSDh: ------------------ | Branch (5993:5): [True: 0, False: 2.24k] ------------------ 5994| 0| case ARM::VCVTANSQf: ------------------ | Branch (5994:5): [True: 0, False: 2.24k] ------------------ 5995| 0| case ARM::VCVTANSQh: ------------------ | Branch (5995:5): [True: 0, False: 2.24k] ------------------ 5996| 0| case ARM::VCVTANUDf: ------------------ | Branch (5996:5): [True: 0, False: 2.24k] ------------------ 5997| 0| case ARM::VCVTANUDh: ------------------ | Branch (5997:5): [True: 0, False: 2.24k] ------------------ 5998| 0| case ARM::VCVTANUQf: ------------------ | Branch (5998:5): [True: 0, False: 2.24k] ------------------ 5999| 0| case ARM::VCVTANUQh: ------------------ | Branch (5999:5): [True: 0, False: 2.24k] ------------------ 6000| 0| case ARM::VCVTMNSDf: ------------------ | Branch (6000:5): [True: 0, False: 2.24k] ------------------ 6001| 0| case ARM::VCVTMNSDh: ------------------ | Branch (6001:5): [True: 0, False: 2.24k] ------------------ 6002| 0| case ARM::VCVTMNSQf: ------------------ | Branch (6002:5): [True: 0, False: 2.24k] ------------------ 6003| 0| case ARM::VCVTMNSQh: ------------------ | Branch (6003:5): [True: 0, False: 2.24k] ------------------ 6004| 0| case ARM::VCVTMNUDf: ------------------ | Branch (6004:5): [True: 0, False: 2.24k] ------------------ 6005| 0| case ARM::VCVTMNUDh: ------------------ | Branch (6005:5): [True: 0, False: 2.24k] ------------------ 6006| 0| case ARM::VCVTMNUQf: ------------------ | Branch (6006:5): [True: 0, False: 2.24k] ------------------ 6007| 0| case ARM::VCVTMNUQh: ------------------ | Branch (6007:5): [True: 0, False: 2.24k] ------------------ 6008| 0| case ARM::VCVTNNSDf: ------------------ | Branch (6008:5): [True: 0, False: 2.24k] ------------------ 6009| 0| case ARM::VCVTNNSDh: ------------------ | Branch (6009:5): [True: 0, False: 2.24k] ------------------ 6010| 0| case ARM::VCVTNNSQf: ------------------ | Branch (6010:5): [True: 0, False: 2.24k] ------------------ 6011| 0| case ARM::VCVTNNSQh: ------------------ | Branch (6011:5): [True: 0, False: 2.24k] ------------------ 6012| 0| case ARM::VCVTNNUDf: ------------------ | Branch (6012:5): [True: 0, False: 2.24k] ------------------ 6013| 0| case ARM::VCVTNNUDh: ------------------ | Branch (6013:5): [True: 0, False: 2.24k] ------------------ 6014| 0| case ARM::VCVTNNUQf: ------------------ | Branch (6014:5): [True: 0, False: 2.24k] ------------------ 6015| 0| case ARM::VCVTNNUQh: ------------------ | Branch (6015:5): [True: 0, False: 2.24k] ------------------ 6016| 0| case ARM::VCVTPNSDf: ------------------ | Branch (6016:5): [True: 0, False: 2.24k] ------------------ 6017| 0| case ARM::VCVTPNSDh: ------------------ | Branch (6017:5): [True: 0, False: 2.24k] ------------------ 6018| 0| case ARM::VCVTPNSQf: ------------------ | Branch (6018:5): [True: 0, False: 2.24k] ------------------ 6019| 0| case ARM::VCVTPNSQh: ------------------ | Branch (6019:5): [True: 0, False: 2.24k] ------------------ 6020| 0| case ARM::VCVTPNUDf: ------------------ | Branch (6020:5): [True: 0, False: 2.24k] ------------------ 6021| 0| case ARM::VCVTPNUDh: ------------------ | Branch (6021:5): [True: 0, False: 2.24k] ------------------ 6022| 0| case ARM::VCVTPNUQf: ------------------ | Branch (6022:5): [True: 0, False: 2.24k] ------------------ 6023| 0| case ARM::VCVTPNUQh: ------------------ | Branch (6023:5): [True: 0, False: 2.24k] ------------------ 6024| 0| case ARM::VRINTANDf: ------------------ | Branch (6024:5): [True: 0, False: 2.24k] ------------------ 6025| 0| case ARM::VRINTANDh: ------------------ | Branch (6025:5): [True: 0, False: 2.24k] ------------------ 6026| 0| case ARM::VRINTANQf: ------------------ | Branch (6026:5): [True: 0, False: 2.24k] ------------------ 6027| 0| case ARM::VRINTANQh: ------------------ | Branch (6027:5): [True: 0, False: 2.24k] ------------------ 6028| 0| case ARM::VRINTMNDf: ------------------ | Branch (6028:5): [True: 0, False: 2.24k] ------------------ 6029| 0| case ARM::VRINTMNDh: ------------------ | Branch (6029:5): [True: 0, False: 2.24k] ------------------ 6030| 0| case ARM::VRINTMNQf: ------------------ | Branch (6030:5): [True: 0, False: 2.24k] ------------------ 6031| 0| case ARM::VRINTMNQh: ------------------ | Branch (6031:5): [True: 0, False: 2.24k] ------------------ 6032| 0| case ARM::VRINTNNDf: ------------------ | Branch (6032:5): [True: 0, False: 2.24k] ------------------ 6033| 0| case ARM::VRINTNNDh: ------------------ | Branch (6033:5): [True: 0, False: 2.24k] ------------------ 6034| 0| case ARM::VRINTNNQf: ------------------ | Branch (6034:5): [True: 0, False: 2.24k] ------------------ 6035| 0| case ARM::VRINTNNQh: ------------------ | Branch (6035:5): [True: 0, False: 2.24k] ------------------ 6036| 0| case ARM::VRINTPNDf: ------------------ | Branch (6036:5): [True: 0, False: 2.24k] ------------------ 6037| 0| case ARM::VRINTPNDh: ------------------ | Branch (6037:5): [True: 0, False: 2.24k] ------------------ 6038| 0| case ARM::VRINTPNQf: ------------------ | Branch (6038:5): [True: 0, False: 2.24k] ------------------ 6039| 0| case ARM::VRINTPNQh: ------------------ | Branch (6039:5): [True: 0, False: 2.24k] ------------------ 6040| 0| case ARM::VRINTXNDf: ------------------ | Branch (6040:5): [True: 0, False: 2.24k] ------------------ 6041| 0| case ARM::VRINTXNDh: ------------------ | Branch (6041:5): [True: 0, False: 2.24k] ------------------ 6042| 0| case ARM::VRINTXNQf: ------------------ | Branch (6042:5): [True: 0, False: 2.24k] ------------------ 6043| 0| case ARM::VRINTXNQh: ------------------ | Branch (6043:5): [True: 0, False: 2.24k] ------------------ 6044| 0| case ARM::VRINTZNDf: ------------------ | Branch (6044:5): [True: 0, False: 2.24k] ------------------ 6045| 0| case ARM::VRINTZNDh: ------------------ | Branch (6045:5): [True: 0, False: 2.24k] ------------------ 6046| 0| case ARM::VRINTZNQf: ------------------ | Branch (6046:5): [True: 0, False: 2.24k] ------------------ 6047| 0| case ARM::VRINTZNQh: { ------------------ | Branch (6047:5): [True: 0, False: 2.24k] ------------------ 6048| | // op: Vd 6049| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6050| 0| Value |= (op & UINT64_C(16)) << 18; 6051| 0| Value |= (op & UINT64_C(15)) << 12; 6052| | // op: Vm 6053| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6054| 0| Value |= (op & UINT64_C(16)) << 1; 6055| 0| Value |= op & UINT64_C(15); 6056| 0| Value = NEONThumb2V8PostEncoder(MI, Value, STI); 6057| 0| break; 6058| 0| } 6059| 0| case ARM::VSLIv4i16: ------------------ | Branch (6059:5): [True: 0, False: 2.24k] ------------------ 6060| 0| case ARM::VSLIv8i16: { ------------------ | Branch (6060:5): [True: 0, False: 2.24k] ------------------ 6061| | // op: Vd 6062| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6063| 0| Value |= (op & UINT64_C(16)) << 18; 6064| 0| Value |= (op & UINT64_C(15)) << 12; 6065| | // op: Vm 6066| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6067| 0| Value |= (op & UINT64_C(16)) << 1; 6068| 0| Value |= op & UINT64_C(15); 6069| | // op: SIMM 6070| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6071| 0| Value |= (op & UINT64_C(15)) << 16; 6072| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6073| 0| break; 6074| 0| } 6075| 0| case ARM::VSLIv2i32: ------------------ | Branch (6075:5): [True: 0, False: 2.24k] ------------------ 6076| 0| case ARM::VSLIv4i32: { ------------------ | Branch (6076:5): [True: 0, False: 2.24k] ------------------ 6077| | // op: Vd 6078| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6079| 0| Value |= (op & UINT64_C(16)) << 18; 6080| 0| Value |= (op & UINT64_C(15)) << 12; 6081| | // op: Vm 6082| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6083| 0| Value |= (op & UINT64_C(16)) << 1; 6084| 0| Value |= op & UINT64_C(15); 6085| | // op: SIMM 6086| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6087| 0| Value |= (op & UINT64_C(31)) << 16; 6088| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6089| 0| break; 6090| 0| } 6091| 0| case ARM::VSLIv1i64: ------------------ | Branch (6091:5): [True: 0, False: 2.24k] ------------------ 6092| 0| case ARM::VSLIv2i64: { ------------------ | Branch (6092:5): [True: 0, False: 2.24k] ------------------ 6093| | // op: Vd 6094| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6095| 0| Value |= (op & UINT64_C(16)) << 18; 6096| 0| Value |= (op & UINT64_C(15)) << 12; 6097| | // op: Vm 6098| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6099| 0| Value |= (op & UINT64_C(16)) << 1; 6100| 0| Value |= op & UINT64_C(15); 6101| | // op: SIMM 6102| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6103| 0| Value |= (op & UINT64_C(63)) << 16; 6104| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6105| 0| break; 6106| 0| } 6107| 0| case ARM::VSLIv16i8: ------------------ | Branch (6107:5): [True: 0, False: 2.24k] ------------------ 6108| 0| case ARM::VSLIv8i8: { ------------------ | Branch (6108:5): [True: 0, False: 2.24k] ------------------ 6109| | // op: Vd 6110| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6111| 0| Value |= (op & UINT64_C(16)) << 18; 6112| 0| Value |= (op & UINT64_C(15)) << 12; 6113| | // op: Vm 6114| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6115| 0| Value |= (op & UINT64_C(16)) << 1; 6116| 0| Value |= op & UINT64_C(15); 6117| | // op: SIMM 6118| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6119| 0| Value |= (op & UINT64_C(7)) << 16; 6120| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6121| 0| break; 6122| 0| } 6123| 0| case ARM::VRSRAsv4i16: ------------------ | Branch (6123:5): [True: 0, False: 2.24k] ------------------ 6124| 0| case ARM::VRSRAsv8i16: ------------------ | Branch (6124:5): [True: 0, False: 2.24k] ------------------ 6125| 0| case ARM::VRSRAuv4i16: ------------------ | Branch (6125:5): [True: 0, False: 2.24k] ------------------ 6126| 0| case ARM::VRSRAuv8i16: ------------------ | Branch (6126:5): [True: 0, False: 2.24k] ------------------ 6127| 0| case ARM::VSRAsv4i16: ------------------ | Branch (6127:5): [True: 0, False: 2.24k] ------------------ 6128| 0| case ARM::VSRAsv8i16: ------------------ | Branch (6128:5): [True: 0, False: 2.24k] ------------------ 6129| 0| case ARM::VSRAuv4i16: ------------------ | Branch (6129:5): [True: 0, False: 2.24k] ------------------ 6130| 0| case ARM::VSRAuv8i16: ------------------ | Branch (6130:5): [True: 0, False: 2.24k] ------------------ 6131| 0| case ARM::VSRIv4i16: ------------------ | Branch (6131:5): [True: 0, False: 2.24k] ------------------ 6132| 0| case ARM::VSRIv8i16: { ------------------ | Branch (6132:5): [True: 0, False: 2.24k] ------------------ 6133| | // op: Vd 6134| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6135| 0| Value |= (op & UINT64_C(16)) << 18; 6136| 0| Value |= (op & UINT64_C(15)) << 12; 6137| | // op: Vm 6138| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6139| 0| Value |= (op & UINT64_C(16)) << 1; 6140| 0| Value |= op & UINT64_C(15); 6141| | // op: SIMM 6142| 0| op = getShiftRight16Imm(MI, 3, Fixups, STI); 6143| 0| Value |= (op & UINT64_C(15)) << 16; 6144| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6145| 0| break; 6146| 0| } 6147| 0| case ARM::VRSRAsv2i32: ------------------ | Branch (6147:5): [True: 0, False: 2.24k] ------------------ 6148| 0| case ARM::VRSRAsv4i32: ------------------ | Branch (6148:5): [True: 0, False: 2.24k] ------------------ 6149| 0| case ARM::VRSRAuv2i32: ------------------ | Branch (6149:5): [True: 0, False: 2.24k] ------------------ 6150| 0| case ARM::VRSRAuv4i32: ------------------ | Branch (6150:5): [True: 0, False: 2.24k] ------------------ 6151| 0| case ARM::VSRAsv2i32: ------------------ | Branch (6151:5): [True: 0, False: 2.24k] ------------------ 6152| 0| case ARM::VSRAsv4i32: ------------------ | Branch (6152:5): [True: 0, False: 2.24k] ------------------ 6153| 0| case ARM::VSRAuv2i32: ------------------ | Branch (6153:5): [True: 0, False: 2.24k] ------------------ 6154| 0| case ARM::VSRAuv4i32: ------------------ | Branch (6154:5): [True: 0, False: 2.24k] ------------------ 6155| 0| case ARM::VSRIv2i32: ------------------ | Branch (6155:5): [True: 0, False: 2.24k] ------------------ 6156| 0| case ARM::VSRIv4i32: { ------------------ | Branch (6156:5): [True: 0, False: 2.24k] ------------------ 6157| | // op: Vd 6158| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6159| 0| Value |= (op & UINT64_C(16)) << 18; 6160| 0| Value |= (op & UINT64_C(15)) << 12; 6161| | // op: Vm 6162| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6163| 0| Value |= (op & UINT64_C(16)) << 1; 6164| 0| Value |= op & UINT64_C(15); 6165| | // op: SIMM 6166| 0| op = getShiftRight32Imm(MI, 3, Fixups, STI); 6167| 0| Value |= (op & UINT64_C(31)) << 16; 6168| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6169| 0| break; 6170| 0| } 6171| 0| case ARM::VRSRAsv1i64: ------------------ | Branch (6171:5): [True: 0, False: 2.24k] ------------------ 6172| 0| case ARM::VRSRAsv2i64: ------------------ | Branch (6172:5): [True: 0, False: 2.24k] ------------------ 6173| 0| case ARM::VRSRAuv1i64: ------------------ | Branch (6173:5): [True: 0, False: 2.24k] ------------------ 6174| 0| case ARM::VRSRAuv2i64: ------------------ | Branch (6174:5): [True: 0, False: 2.24k] ------------------ 6175| 0| case ARM::VSRAsv1i64: ------------------ | Branch (6175:5): [True: 0, False: 2.24k] ------------------ 6176| 0| case ARM::VSRAsv2i64: ------------------ | Branch (6176:5): [True: 0, False: 2.24k] ------------------ 6177| 0| case ARM::VSRAuv1i64: ------------------ | Branch (6177:5): [True: 0, False: 2.24k] ------------------ 6178| 0| case ARM::VSRAuv2i64: ------------------ | Branch (6178:5): [True: 0, False: 2.24k] ------------------ 6179| 0| case ARM::VSRIv1i64: ------------------ | Branch (6179:5): [True: 0, False: 2.24k] ------------------ 6180| 0| case ARM::VSRIv2i64: { ------------------ | Branch (6180:5): [True: 0, False: 2.24k] ------------------ 6181| | // op: Vd 6182| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6183| 0| Value |= (op & UINT64_C(16)) << 18; 6184| 0| Value |= (op & UINT64_C(15)) << 12; 6185| | // op: Vm 6186| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6187| 0| Value |= (op & UINT64_C(16)) << 1; 6188| 0| Value |= op & UINT64_C(15); 6189| | // op: SIMM 6190| 0| op = getShiftRight64Imm(MI, 3, Fixups, STI); 6191| 0| Value |= (op & UINT64_C(63)) << 16; 6192| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6193| 0| break; 6194| 0| } 6195| 0| case ARM::VRSRAsv16i8: ------------------ | Branch (6195:5): [True: 0, False: 2.24k] ------------------ 6196| 0| case ARM::VRSRAsv8i8: ------------------ | Branch (6196:5): [True: 0, False: 2.24k] ------------------ 6197| 0| case ARM::VRSRAuv16i8: ------------------ | Branch (6197:5): [True: 0, False: 2.24k] ------------------ 6198| 0| case ARM::VRSRAuv8i8: ------------------ | Branch (6198:5): [True: 0, False: 2.24k] ------------------ 6199| 0| case ARM::VSRAsv16i8: ------------------ | Branch (6199:5): [True: 0, False: 2.24k] ------------------ 6200| 0| case ARM::VSRAsv8i8: ------------------ | Branch (6200:5): [True: 0, False: 2.24k] ------------------ 6201| 0| case ARM::VSRAuv16i8: ------------------ | Branch (6201:5): [True: 0, False: 2.24k] ------------------ 6202| 0| case ARM::VSRAuv8i8: ------------------ | Branch (6202:5): [True: 0, False: 2.24k] ------------------ 6203| 0| case ARM::VSRIv16i8: ------------------ | Branch (6203:5): [True: 0, False: 2.24k] ------------------ 6204| 0| case ARM::VSRIv8i8: { ------------------ | Branch (6204:5): [True: 0, False: 2.24k] ------------------ 6205| | // op: Vd 6206| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6207| 0| Value |= (op & UINT64_C(16)) << 18; 6208| 0| Value |= (op & UINT64_C(15)) << 12; 6209| | // op: Vm 6210| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6211| 0| Value |= (op & UINT64_C(16)) << 1; 6212| 0| Value |= op & UINT64_C(15); 6213| | // op: SIMM 6214| 0| op = getShiftRight8Imm(MI, 3, Fixups, STI); 6215| 0| Value |= (op & UINT64_C(7)) << 16; 6216| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6217| 0| break; 6218| 0| } 6219| 0| case ARM::AESD: ------------------ | Branch (6219:5): [True: 0, False: 2.24k] ------------------ 6220| 0| case ARM::AESE: ------------------ | Branch (6220:5): [True: 0, False: 2.24k] ------------------ 6221| 0| case ARM::SHA1SU1: ------------------ | Branch (6221:5): [True: 0, False: 2.24k] ------------------ 6222| 0| case ARM::SHA256SU0: ------------------ | Branch (6222:5): [True: 0, False: 2.24k] ------------------ 6223| 0| case ARM::VPADALsv16i8: ------------------ | Branch (6223:5): [True: 0, False: 2.24k] ------------------ 6224| 0| case ARM::VPADALsv2i32: ------------------ | Branch (6224:5): [True: 0, False: 2.24k] ------------------ 6225| 0| case ARM::VPADALsv4i16: ------------------ | Branch (6225:5): [True: 0, False: 2.24k] ------------------ 6226| 0| case ARM::VPADALsv4i32: ------------------ | Branch (6226:5): [True: 0, False: 2.24k] ------------------ 6227| 0| case ARM::VPADALsv8i16: ------------------ | Branch (6227:5): [True: 0, False: 2.24k] ------------------ 6228| 0| case ARM::VPADALsv8i8: ------------------ | Branch (6228:5): [True: 0, False: 2.24k] ------------------ 6229| 0| case ARM::VPADALuv16i8: ------------------ | Branch (6229:5): [True: 0, False: 2.24k] ------------------ 6230| 0| case ARM::VPADALuv2i32: ------------------ | Branch (6230:5): [True: 0, False: 2.24k] ------------------ 6231| 0| case ARM::VPADALuv4i16: ------------------ | Branch (6231:5): [True: 0, False: 2.24k] ------------------ 6232| 0| case ARM::VPADALuv4i32: ------------------ | Branch (6232:5): [True: 0, False: 2.24k] ------------------ 6233| 0| case ARM::VPADALuv8i16: ------------------ | Branch (6233:5): [True: 0, False: 2.24k] ------------------ 6234| 0| case ARM::VPADALuv8i8: { ------------------ | Branch (6234:5): [True: 0, False: 2.24k] ------------------ 6235| | // op: Vd 6236| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6237| 0| Value |= (op & UINT64_C(16)) << 18; 6238| 0| Value |= (op & UINT64_C(15)) << 12; 6239| | // op: Vm 6240| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6241| 0| Value |= (op & UINT64_C(16)) << 1; 6242| 0| Value |= op & UINT64_C(15); 6243| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6244| 0| break; 6245| 0| } 6246| 0| case ARM::VEXTd32: { ------------------ | Branch (6246:5): [True: 0, False: 2.24k] ------------------ 6247| | // op: Vd 6248| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6249| 0| Value |= (op & UINT64_C(16)) << 18; 6250| 0| Value |= (op & UINT64_C(15)) << 12; 6251| | // op: Vn 6252| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6253| 0| Value |= (op & UINT64_C(15)) << 16; 6254| 0| Value |= (op & UINT64_C(16)) << 3; 6255| | // op: Vm 6256| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6257| 0| Value |= (op & UINT64_C(16)) << 1; 6258| 0| Value |= op & UINT64_C(15); 6259| | // op: index 6260| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6261| 0| Value |= (op & UINT64_C(1)) << 10; 6262| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6263| 0| break; 6264| 0| } 6265| 0| case ARM::VEXTq64: { ------------------ | Branch (6265:5): [True: 0, False: 2.24k] ------------------ 6266| | // op: Vd 6267| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6268| 0| Value |= (op & UINT64_C(16)) << 18; 6269| 0| Value |= (op & UINT64_C(15)) << 12; 6270| | // op: Vn 6271| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6272| 0| Value |= (op & UINT64_C(15)) << 16; 6273| 0| Value |= (op & UINT64_C(16)) << 3; 6274| | // op: Vm 6275| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6276| 0| Value |= (op & UINT64_C(16)) << 1; 6277| 0| Value |= op & UINT64_C(15); 6278| | // op: index 6279| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6280| 0| Value |= (op & UINT64_C(1)) << 11; 6281| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6282| 0| break; 6283| 0| } 6284| 0| case ARM::VEXTq8: { ------------------ | Branch (6284:5): [True: 0, False: 2.24k] ------------------ 6285| | // op: Vd 6286| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6287| 0| Value |= (op & UINT64_C(16)) << 18; 6288| 0| Value |= (op & UINT64_C(15)) << 12; 6289| | // op: Vn 6290| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6291| 0| Value |= (op & UINT64_C(15)) << 16; 6292| 0| Value |= (op & UINT64_C(16)) << 3; 6293| | // op: Vm 6294| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6295| 0| Value |= (op & UINT64_C(16)) << 1; 6296| 0| Value |= op & UINT64_C(15); 6297| | // op: index 6298| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6299| 0| Value |= (op & UINT64_C(15)) << 8; 6300| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6301| 0| break; 6302| 0| } 6303| 0| case ARM::VEXTq32: { ------------------ | Branch (6303:5): [True: 0, False: 2.24k] ------------------ 6304| | // op: Vd 6305| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6306| 0| Value |= (op & UINT64_C(16)) << 18; 6307| 0| Value |= (op & UINT64_C(15)) << 12; 6308| | // op: Vn 6309| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6310| 0| Value |= (op & UINT64_C(15)) << 16; 6311| 0| Value |= (op & UINT64_C(16)) << 3; 6312| | // op: Vm 6313| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6314| 0| Value |= (op & UINT64_C(16)) << 1; 6315| 0| Value |= op & UINT64_C(15); 6316| | // op: index 6317| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6318| 0| Value |= (op & UINT64_C(3)) << 10; 6319| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6320| 0| break; 6321| 0| } 6322| 0| case ARM::VEXTd16: { ------------------ | Branch (6322:5): [True: 0, False: 2.24k] ------------------ 6323| | // op: Vd 6324| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6325| 0| Value |= (op & UINT64_C(16)) << 18; 6326| 0| Value |= (op & UINT64_C(15)) << 12; 6327| | // op: Vn 6328| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6329| 0| Value |= (op & UINT64_C(15)) << 16; 6330| 0| Value |= (op & UINT64_C(16)) << 3; 6331| | // op: Vm 6332| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6333| 0| Value |= (op & UINT64_C(16)) << 1; 6334| 0| Value |= op & UINT64_C(15); 6335| | // op: index 6336| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6337| 0| Value |= (op & UINT64_C(3)) << 9; 6338| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6339| 0| break; 6340| 0| } 6341| 0| case ARM::VEXTd8: { ------------------ | Branch (6341:5): [True: 0, False: 2.24k] ------------------ 6342| | // op: Vd 6343| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6344| 0| Value |= (op & UINT64_C(16)) << 18; 6345| 0| Value |= (op & UINT64_C(15)) << 12; 6346| | // op: Vn 6347| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6348| 0| Value |= (op & UINT64_C(15)) << 16; 6349| 0| Value |= (op & UINT64_C(16)) << 3; 6350| | // op: Vm 6351| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6352| 0| Value |= (op & UINT64_C(16)) << 1; 6353| 0| Value |= op & UINT64_C(15); 6354| | // op: index 6355| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6356| 0| Value |= (op & UINT64_C(7)) << 8; 6357| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6358| 0| break; 6359| 0| } 6360| 0| case ARM::VEXTq16: { ------------------ | Branch (6360:5): [True: 0, False: 2.24k] ------------------ 6361| | // op: Vd 6362| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6363| 0| Value |= (op & UINT64_C(16)) << 18; 6364| 0| Value |= (op & UINT64_C(15)) << 12; 6365| | // op: Vn 6366| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6367| 0| Value |= (op & UINT64_C(15)) << 16; 6368| 0| Value |= (op & UINT64_C(16)) << 3; 6369| | // op: Vm 6370| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6371| 0| Value |= (op & UINT64_C(16)) << 1; 6372| 0| Value |= op & UINT64_C(15); 6373| | // op: index 6374| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6375| 0| Value |= (op & UINT64_C(7)) << 9; 6376| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6377| 0| break; 6378| 0| } 6379| 0| case ARM::VABDLsv2i64: ------------------ | Branch (6379:5): [True: 0, False: 2.24k] ------------------ 6380| 0| case ARM::VABDLsv4i32: ------------------ | Branch (6380:5): [True: 0, False: 2.24k] ------------------ 6381| 0| case ARM::VABDLsv8i16: ------------------ | Branch (6381:5): [True: 0, False: 2.24k] ------------------ 6382| 0| case ARM::VABDLuv2i64: ------------------ | Branch (6382:5): [True: 0, False: 2.24k] ------------------ 6383| 0| case ARM::VABDLuv4i32: ------------------ | Branch (6383:5): [True: 0, False: 2.24k] ------------------ 6384| 0| case ARM::VABDLuv8i16: ------------------ | Branch (6384:5): [True: 0, False: 2.24k] ------------------ 6385| 0| case ARM::VABDfd: ------------------ | Branch (6385:5): [True: 0, False: 2.24k] ------------------ 6386| 0| case ARM::VABDfq: ------------------ | Branch (6386:5): [True: 0, False: 2.24k] ------------------ 6387| 0| case ARM::VABDhd: ------------------ | Branch (6387:5): [True: 0, False: 2.24k] ------------------ 6388| 0| case ARM::VABDhq: ------------------ | Branch (6388:5): [True: 0, False: 2.24k] ------------------ 6389| 0| case ARM::VABDsv16i8: ------------------ | Branch (6389:5): [True: 0, False: 2.24k] ------------------ 6390| 0| case ARM::VABDsv2i32: ------------------ | Branch (6390:5): [True: 0, False: 2.24k] ------------------ 6391| 0| case ARM::VABDsv4i16: ------------------ | Branch (6391:5): [True: 0, False: 2.24k] ------------------ 6392| 0| case ARM::VABDsv4i32: ------------------ | Branch (6392:5): [True: 0, False: 2.24k] ------------------ 6393| 0| case ARM::VABDsv8i16: ------------------ | Branch (6393:5): [True: 0, False: 2.24k] ------------------ 6394| 0| case ARM::VABDsv8i8: ------------------ | Branch (6394:5): [True: 0, False: 2.24k] ------------------ 6395| 0| case ARM::VABDuv16i8: ------------------ | Branch (6395:5): [True: 0, False: 2.24k] ------------------ 6396| 0| case ARM::VABDuv2i32: ------------------ | Branch (6396:5): [True: 0, False: 2.24k] ------------------ 6397| 0| case ARM::VABDuv4i16: ------------------ | Branch (6397:5): [True: 0, False: 2.24k] ------------------ 6398| 0| case ARM::VABDuv4i32: ------------------ | Branch (6398:5): [True: 0, False: 2.24k] ------------------ 6399| 0| case ARM::VABDuv8i16: ------------------ | Branch (6399:5): [True: 0, False: 2.24k] ------------------ 6400| 0| case ARM::VABDuv8i8: ------------------ | Branch (6400:5): [True: 0, False: 2.24k] ------------------ 6401| 0| case ARM::VACGEfd: ------------------ | Branch (6401:5): [True: 0, False: 2.24k] ------------------ 6402| 0| case ARM::VACGEfq: ------------------ | Branch (6402:5): [True: 0, False: 2.24k] ------------------ 6403| 0| case ARM::VACGEhd: ------------------ | Branch (6403:5): [True: 0, False: 2.24k] ------------------ 6404| 0| case ARM::VACGEhq: ------------------ | Branch (6404:5): [True: 0, False: 2.24k] ------------------ 6405| 0| case ARM::VACGTfd: ------------------ | Branch (6405:5): [True: 0, False: 2.24k] ------------------ 6406| 0| case ARM::VACGTfq: ------------------ | Branch (6406:5): [True: 0, False: 2.24k] ------------------ 6407| 0| case ARM::VACGThd: ------------------ | Branch (6407:5): [True: 0, False: 2.24k] ------------------ 6408| 0| case ARM::VACGThq: ------------------ | Branch (6408:5): [True: 0, False: 2.24k] ------------------ 6409| 0| case ARM::VADDHNv2i32: ------------------ | Branch (6409:5): [True: 0, False: 2.24k] ------------------ 6410| 0| case ARM::VADDHNv4i16: ------------------ | Branch (6410:5): [True: 0, False: 2.24k] ------------------ 6411| 0| case ARM::VADDHNv8i8: ------------------ | Branch (6411:5): [True: 0, False: 2.24k] ------------------ 6412| 0| case ARM::VADDLsv2i64: ------------------ | Branch (6412:5): [True: 0, False: 2.24k] ------------------ 6413| 0| case ARM::VADDLsv4i32: ------------------ | Branch (6413:5): [True: 0, False: 2.24k] ------------------ 6414| 0| case ARM::VADDLsv8i16: ------------------ | Branch (6414:5): [True: 0, False: 2.24k] ------------------ 6415| 0| case ARM::VADDLuv2i64: ------------------ | Branch (6415:5): [True: 0, False: 2.24k] ------------------ 6416| 0| case ARM::VADDLuv4i32: ------------------ | Branch (6416:5): [True: 0, False: 2.24k] ------------------ 6417| 0| case ARM::VADDLuv8i16: ------------------ | Branch (6417:5): [True: 0, False: 2.24k] ------------------ 6418| 0| case ARM::VADDWsv2i64: ------------------ | Branch (6418:5): [True: 0, False: 2.24k] ------------------ 6419| 0| case ARM::VADDWsv4i32: ------------------ | Branch (6419:5): [True: 0, False: 2.24k] ------------------ 6420| 0| case ARM::VADDWsv8i16: ------------------ | Branch (6420:5): [True: 0, False: 2.24k] ------------------ 6421| 0| case ARM::VADDWuv2i64: ------------------ | Branch (6421:5): [True: 0, False: 2.24k] ------------------ 6422| 0| case ARM::VADDWuv4i32: ------------------ | Branch (6422:5): [True: 0, False: 2.24k] ------------------ 6423| 0| case ARM::VADDWuv8i16: ------------------ | Branch (6423:5): [True: 0, False: 2.24k] ------------------ 6424| 0| case ARM::VADDfd: ------------------ | Branch (6424:5): [True: 0, False: 2.24k] ------------------ 6425| 0| case ARM::VADDfq: ------------------ | Branch (6425:5): [True: 0, False: 2.24k] ------------------ 6426| 0| case ARM::VADDhd: ------------------ | Branch (6426:5): [True: 0, False: 2.24k] ------------------ 6427| 0| case ARM::VADDhq: ------------------ | Branch (6427:5): [True: 0, False: 2.24k] ------------------ 6428| 0| case ARM::VADDv16i8: ------------------ | Branch (6428:5): [True: 0, False: 2.24k] ------------------ 6429| 0| case ARM::VADDv1i64: ------------------ | Branch (6429:5): [True: 0, False: 2.24k] ------------------ 6430| 0| case ARM::VADDv2i32: ------------------ | Branch (6430:5): [True: 0, False: 2.24k] ------------------ 6431| 0| case ARM::VADDv2i64: ------------------ | Branch (6431:5): [True: 0, False: 2.24k] ------------------ 6432| 0| case ARM::VADDv4i16: ------------------ | Branch (6432:5): [True: 0, False: 2.24k] ------------------ 6433| 0| case ARM::VADDv4i32: ------------------ | Branch (6433:5): [True: 0, False: 2.24k] ------------------ 6434| 0| case ARM::VADDv8i16: ------------------ | Branch (6434:5): [True: 0, False: 2.24k] ------------------ 6435| 0| case ARM::VADDv8i8: ------------------ | Branch (6435:5): [True: 0, False: 2.24k] ------------------ 6436| 0| case ARM::VANDd: ------------------ | Branch (6436:5): [True: 0, False: 2.24k] ------------------ 6437| 0| case ARM::VANDq: ------------------ | Branch (6437:5): [True: 0, False: 2.24k] ------------------ 6438| 0| case ARM::VBICd: ------------------ | Branch (6438:5): [True: 0, False: 2.24k] ------------------ 6439| 0| case ARM::VBICq: ------------------ | Branch (6439:5): [True: 0, False: 2.24k] ------------------ 6440| 0| case ARM::VCEQfd: ------------------ | Branch (6440:5): [True: 0, False: 2.24k] ------------------ 6441| 0| case ARM::VCEQfq: ------------------ | Branch (6441:5): [True: 0, False: 2.24k] ------------------ 6442| 0| case ARM::VCEQhd: ------------------ | Branch (6442:5): [True: 0, False: 2.24k] ------------------ 6443| 0| case ARM::VCEQhq: ------------------ | Branch (6443:5): [True: 0, False: 2.24k] ------------------ 6444| 0| case ARM::VCEQv16i8: ------------------ | Branch (6444:5): [True: 0, False: 2.24k] ------------------ 6445| 0| case ARM::VCEQv2i32: ------------------ | Branch (6445:5): [True: 0, False: 2.24k] ------------------ 6446| 0| case ARM::VCEQv4i16: ------------------ | Branch (6446:5): [True: 0, False: 2.24k] ------------------ 6447| 0| case ARM::VCEQv4i32: ------------------ | Branch (6447:5): [True: 0, False: 2.24k] ------------------ 6448| 0| case ARM::VCEQv8i16: ------------------ | Branch (6448:5): [True: 0, False: 2.24k] ------------------ 6449| 0| case ARM::VCEQv8i8: ------------------ | Branch (6449:5): [True: 0, False: 2.24k] ------------------ 6450| 0| case ARM::VCGEfd: ------------------ | Branch (6450:5): [True: 0, False: 2.24k] ------------------ 6451| 0| case ARM::VCGEfq: ------------------ | Branch (6451:5): [True: 0, False: 2.24k] ------------------ 6452| 0| case ARM::VCGEhd: ------------------ | Branch (6452:5): [True: 0, False: 2.24k] ------------------ 6453| 0| case ARM::VCGEhq: ------------------ | Branch (6453:5): [True: 0, False: 2.24k] ------------------ 6454| 0| case ARM::VCGEsv16i8: ------------------ | Branch (6454:5): [True: 0, False: 2.24k] ------------------ 6455| 0| case ARM::VCGEsv2i32: ------------------ | Branch (6455:5): [True: 0, False: 2.24k] ------------------ 6456| 0| case ARM::VCGEsv4i16: ------------------ | Branch (6456:5): [True: 0, False: 2.24k] ------------------ 6457| 0| case ARM::VCGEsv4i32: ------------------ | Branch (6457:5): [True: 0, False: 2.24k] ------------------ 6458| 0| case ARM::VCGEsv8i16: ------------------ | Branch (6458:5): [True: 0, False: 2.24k] ------------------ 6459| 0| case ARM::VCGEsv8i8: ------------------ | Branch (6459:5): [True: 0, False: 2.24k] ------------------ 6460| 0| case ARM::VCGEuv16i8: ------------------ | Branch (6460:5): [True: 0, False: 2.24k] ------------------ 6461| 0| case ARM::VCGEuv2i32: ------------------ | Branch (6461:5): [True: 0, False: 2.24k] ------------------ 6462| 0| case ARM::VCGEuv4i16: ------------------ | Branch (6462:5): [True: 0, False: 2.24k] ------------------ 6463| 0| case ARM::VCGEuv4i32: ------------------ | Branch (6463:5): [True: 0, False: 2.24k] ------------------ 6464| 0| case ARM::VCGEuv8i16: ------------------ | Branch (6464:5): [True: 0, False: 2.24k] ------------------ 6465| 0| case ARM::VCGEuv8i8: ------------------ | Branch (6465:5): [True: 0, False: 2.24k] ------------------ 6466| 0| case ARM::VCGTfd: ------------------ | Branch (6466:5): [True: 0, False: 2.24k] ------------------ 6467| 0| case ARM::VCGTfq: ------------------ | Branch (6467:5): [True: 0, False: 2.24k] ------------------ 6468| 0| case ARM::VCGThd: ------------------ | Branch (6468:5): [True: 0, False: 2.24k] ------------------ 6469| 0| case ARM::VCGThq: ------------------ | Branch (6469:5): [True: 0, False: 2.24k] ------------------ 6470| 0| case ARM::VCGTsv16i8: ------------------ | Branch (6470:5): [True: 0, False: 2.24k] ------------------ 6471| 0| case ARM::VCGTsv2i32: ------------------ | Branch (6471:5): [True: 0, False: 2.24k] ------------------ 6472| 0| case ARM::VCGTsv4i16: ------------------ | Branch (6472:5): [True: 0, False: 2.24k] ------------------ 6473| 0| case ARM::VCGTsv4i32: ------------------ | Branch (6473:5): [True: 0, False: 2.24k] ------------------ 6474| 0| case ARM::VCGTsv8i16: ------------------ | Branch (6474:5): [True: 0, False: 2.24k] ------------------ 6475| 0| case ARM::VCGTsv8i8: ------------------ | Branch (6475:5): [True: 0, False: 2.24k] ------------------ 6476| 0| case ARM::VCGTuv16i8: ------------------ | Branch (6476:5): [True: 0, False: 2.24k] ------------------ 6477| 0| case ARM::VCGTuv2i32: ------------------ | Branch (6477:5): [True: 0, False: 2.24k] ------------------ 6478| 0| case ARM::VCGTuv4i16: ------------------ | Branch (6478:5): [True: 0, False: 2.24k] ------------------ 6479| 0| case ARM::VCGTuv4i32: ------------------ | Branch (6479:5): [True: 0, False: 2.24k] ------------------ 6480| 0| case ARM::VCGTuv8i16: ------------------ | Branch (6480:5): [True: 0, False: 2.24k] ------------------ 6481| 0| case ARM::VCGTuv8i8: ------------------ | Branch (6481:5): [True: 0, False: 2.24k] ------------------ 6482| 0| case ARM::VEORd: ------------------ | Branch (6482:5): [True: 0, False: 2.24k] ------------------ 6483| 0| case ARM::VEORq: ------------------ | Branch (6483:5): [True: 0, False: 2.24k] ------------------ 6484| 0| case ARM::VHADDsv16i8: ------------------ | Branch (6484:5): [True: 0, False: 2.24k] ------------------ 6485| 0| case ARM::VHADDsv2i32: ------------------ | Branch (6485:5): [True: 0, False: 2.24k] ------------------ 6486| 0| case ARM::VHADDsv4i16: ------------------ | Branch (6486:5): [True: 0, False: 2.24k] ------------------ 6487| 0| case ARM::VHADDsv4i32: ------------------ | Branch (6487:5): [True: 0, False: 2.24k] ------------------ 6488| 0| case ARM::VHADDsv8i16: ------------------ | Branch (6488:5): [True: 0, False: 2.24k] ------------------ 6489| 0| case ARM::VHADDsv8i8: ------------------ | Branch (6489:5): [True: 0, False: 2.24k] ------------------ 6490| 0| case ARM::VHADDuv16i8: ------------------ | Branch (6490:5): [True: 0, False: 2.24k] ------------------ 6491| 0| case ARM::VHADDuv2i32: ------------------ | Branch (6491:5): [True: 0, False: 2.24k] ------------------ 6492| 0| case ARM::VHADDuv4i16: ------------------ | Branch (6492:5): [True: 0, False: 2.24k] ------------------ 6493| 0| case ARM::VHADDuv4i32: ------------------ | Branch (6493:5): [True: 0, False: 2.24k] ------------------ 6494| 0| case ARM::VHADDuv8i16: ------------------ | Branch (6494:5): [True: 0, False: 2.24k] ------------------ 6495| 0| case ARM::VHADDuv8i8: ------------------ | Branch (6495:5): [True: 0, False: 2.24k] ------------------ 6496| 0| case ARM::VHSUBsv16i8: ------------------ | Branch (6496:5): [True: 0, False: 2.24k] ------------------ 6497| 0| case ARM::VHSUBsv2i32: ------------------ | Branch (6497:5): [True: 0, False: 2.24k] ------------------ 6498| 0| case ARM::VHSUBsv4i16: ------------------ | Branch (6498:5): [True: 0, False: 2.24k] ------------------ 6499| 0| case ARM::VHSUBsv4i32: ------------------ | Branch (6499:5): [True: 0, False: 2.24k] ------------------ 6500| 0| case ARM::VHSUBsv8i16: ------------------ | Branch (6500:5): [True: 0, False: 2.24k] ------------------ 6501| 0| case ARM::VHSUBsv8i8: ------------------ | Branch (6501:5): [True: 0, False: 2.24k] ------------------ 6502| 0| case ARM::VHSUBuv16i8: ------------------ | Branch (6502:5): [True: 0, False: 2.24k] ------------------ 6503| 0| case ARM::VHSUBuv2i32: ------------------ | Branch (6503:5): [True: 0, False: 2.24k] ------------------ 6504| 0| case ARM::VHSUBuv4i16: ------------------ | Branch (6504:5): [True: 0, False: 2.24k] ------------------ 6505| 0| case ARM::VHSUBuv4i32: ------------------ | Branch (6505:5): [True: 0, False: 2.24k] ------------------ 6506| 0| case ARM::VHSUBuv8i16: ------------------ | Branch (6506:5): [True: 0, False: 2.24k] ------------------ 6507| 0| case ARM::VHSUBuv8i8: ------------------ | Branch (6507:5): [True: 0, False: 2.24k] ------------------ 6508| 0| case ARM::VMAXfd: ------------------ | Branch (6508:5): [True: 0, False: 2.24k] ------------------ 6509| 0| case ARM::VMAXfq: ------------------ | Branch (6509:5): [True: 0, False: 2.24k] ------------------ 6510| 0| case ARM::VMAXhd: ------------------ | Branch (6510:5): [True: 0, False: 2.24k] ------------------ 6511| 0| case ARM::VMAXhq: ------------------ | Branch (6511:5): [True: 0, False: 2.24k] ------------------ 6512| 0| case ARM::VMAXsv16i8: ------------------ | Branch (6512:5): [True: 0, False: 2.24k] ------------------ 6513| 0| case ARM::VMAXsv2i32: ------------------ | Branch (6513:5): [True: 0, False: 2.24k] ------------------ 6514| 0| case ARM::VMAXsv4i16: ------------------ | Branch (6514:5): [True: 0, False: 2.24k] ------------------ 6515| 0| case ARM::VMAXsv4i32: ------------------ | Branch (6515:5): [True: 0, False: 2.24k] ------------------ 6516| 0| case ARM::VMAXsv8i16: ------------------ | Branch (6516:5): [True: 0, False: 2.24k] ------------------ 6517| 0| case ARM::VMAXsv8i8: ------------------ | Branch (6517:5): [True: 0, False: 2.24k] ------------------ 6518| 0| case ARM::VMAXuv16i8: ------------------ | Branch (6518:5): [True: 0, False: 2.24k] ------------------ 6519| 0| case ARM::VMAXuv2i32: ------------------ | Branch (6519:5): [True: 0, False: 2.24k] ------------------ 6520| 0| case ARM::VMAXuv4i16: ------------------ | Branch (6520:5): [True: 0, False: 2.24k] ------------------ 6521| 0| case ARM::VMAXuv4i32: ------------------ | Branch (6521:5): [True: 0, False: 2.24k] ------------------ 6522| 0| case ARM::VMAXuv8i16: ------------------ | Branch (6522:5): [True: 0, False: 2.24k] ------------------ 6523| 0| case ARM::VMAXuv8i8: ------------------ | Branch (6523:5): [True: 0, False: 2.24k] ------------------ 6524| 0| case ARM::VMINfd: ------------------ | Branch (6524:5): [True: 0, False: 2.24k] ------------------ 6525| 0| case ARM::VMINfq: ------------------ | Branch (6525:5): [True: 0, False: 2.24k] ------------------ 6526| 0| case ARM::VMINhd: ------------------ | Branch (6526:5): [True: 0, False: 2.24k] ------------------ 6527| 0| case ARM::VMINhq: ------------------ | Branch (6527:5): [True: 0, False: 2.24k] ------------------ 6528| 0| case ARM::VMINsv16i8: ------------------ | Branch (6528:5): [True: 0, False: 2.24k] ------------------ 6529| 0| case ARM::VMINsv2i32: ------------------ | Branch (6529:5): [True: 0, False: 2.24k] ------------------ 6530| 0| case ARM::VMINsv4i16: ------------------ | Branch (6530:5): [True: 0, False: 2.24k] ------------------ 6531| 0| case ARM::VMINsv4i32: ------------------ | Branch (6531:5): [True: 0, False: 2.24k] ------------------ 6532| 0| case ARM::VMINsv8i16: ------------------ | Branch (6532:5): [True: 0, False: 2.24k] ------------------ 6533| 0| case ARM::VMINsv8i8: ------------------ | Branch (6533:5): [True: 0, False: 2.24k] ------------------ 6534| 0| case ARM::VMINuv16i8: ------------------ | Branch (6534:5): [True: 0, False: 2.24k] ------------------ 6535| 0| case ARM::VMINuv2i32: ------------------ | Branch (6535:5): [True: 0, False: 2.24k] ------------------ 6536| 0| case ARM::VMINuv4i16: ------------------ | Branch (6536:5): [True: 0, False: 2.24k] ------------------ 6537| 0| case ARM::VMINuv4i32: ------------------ | Branch (6537:5): [True: 0, False: 2.24k] ------------------ 6538| 0| case ARM::VMINuv8i16: ------------------ | Branch (6538:5): [True: 0, False: 2.24k] ------------------ 6539| 0| case ARM::VMINuv8i8: ------------------ | Branch (6539:5): [True: 0, False: 2.24k] ------------------ 6540| 0| case ARM::VMULLp64: ------------------ | Branch (6540:5): [True: 0, False: 2.24k] ------------------ 6541| 0| case ARM::VMULLp8: ------------------ | Branch (6541:5): [True: 0, False: 2.24k] ------------------ 6542| 0| case ARM::VMULLsv2i64: ------------------ | Branch (6542:5): [True: 0, False: 2.24k] ------------------ 6543| 0| case ARM::VMULLsv4i32: ------------------ | Branch (6543:5): [True: 0, False: 2.24k] ------------------ 6544| 0| case ARM::VMULLsv8i16: ------------------ | Branch (6544:5): [True: 0, False: 2.24k] ------------------ 6545| 0| case ARM::VMULLuv2i64: ------------------ | Branch (6545:5): [True: 0, False: 2.24k] ------------------ 6546| 0| case ARM::VMULLuv4i32: ------------------ | Branch (6546:5): [True: 0, False: 2.24k] ------------------ 6547| 0| case ARM::VMULLuv8i16: ------------------ | Branch (6547:5): [True: 0, False: 2.24k] ------------------ 6548| 0| case ARM::VMULfd: ------------------ | Branch (6548:5): [True: 0, False: 2.24k] ------------------ 6549| 0| case ARM::VMULfq: ------------------ | Branch (6549:5): [True: 0, False: 2.24k] ------------------ 6550| 0| case ARM::VMULhd: ------------------ | Branch (6550:5): [True: 0, False: 2.24k] ------------------ 6551| 0| case ARM::VMULhq: ------------------ | Branch (6551:5): [True: 0, False: 2.24k] ------------------ 6552| 0| case ARM::VMULpd: ------------------ | Branch (6552:5): [True: 0, False: 2.24k] ------------------ 6553| 0| case ARM::VMULpq: ------------------ | Branch (6553:5): [True: 0, False: 2.24k] ------------------ 6554| 0| case ARM::VMULv16i8: ------------------ | Branch (6554:5): [True: 0, False: 2.24k] ------------------ 6555| 0| case ARM::VMULv2i32: ------------------ | Branch (6555:5): [True: 0, False: 2.24k] ------------------ 6556| 0| case ARM::VMULv4i16: ------------------ | Branch (6556:5): [True: 0, False: 2.24k] ------------------ 6557| 0| case ARM::VMULv4i32: ------------------ | Branch (6557:5): [True: 0, False: 2.24k] ------------------ 6558| 0| case ARM::VMULv8i16: ------------------ | Branch (6558:5): [True: 0, False: 2.24k] ------------------ 6559| 0| case ARM::VMULv8i8: ------------------ | Branch (6559:5): [True: 0, False: 2.24k] ------------------ 6560| 0| case ARM::VORNd: ------------------ | Branch (6560:5): [True: 0, False: 2.24k] ------------------ 6561| 0| case ARM::VORNq: ------------------ | Branch (6561:5): [True: 0, False: 2.24k] ------------------ 6562| 0| case ARM::VORRd: ------------------ | Branch (6562:5): [True: 0, False: 2.24k] ------------------ 6563| 0| case ARM::VORRq: ------------------ | Branch (6563:5): [True: 0, False: 2.24k] ------------------ 6564| 0| case ARM::VPADDf: ------------------ | Branch (6564:5): [True: 0, False: 2.24k] ------------------ 6565| 0| case ARM::VPADDh: ------------------ | Branch (6565:5): [True: 0, False: 2.24k] ------------------ 6566| 0| case ARM::VPADDi16: ------------------ | Branch (6566:5): [True: 0, False: 2.24k] ------------------ 6567| 0| case ARM::VPADDi32: ------------------ | Branch (6567:5): [True: 0, False: 2.24k] ------------------ 6568| 0| case ARM::VPADDi8: ------------------ | Branch (6568:5): [True: 0, False: 2.24k] ------------------ 6569| 0| case ARM::VPMAXf: ------------------ | Branch (6569:5): [True: 0, False: 2.24k] ------------------ 6570| 0| case ARM::VPMAXh: ------------------ | Branch (6570:5): [True: 0, False: 2.24k] ------------------ 6571| 0| case ARM::VPMAXs16: ------------------ | Branch (6571:5): [True: 0, False: 2.24k] ------------------ 6572| 0| case ARM::VPMAXs32: ------------------ | Branch (6572:5): [True: 0, False: 2.24k] ------------------ 6573| 0| case ARM::VPMAXs8: ------------------ | Branch (6573:5): [True: 0, False: 2.24k] ------------------ 6574| 0| case ARM::VPMAXu16: ------------------ | Branch (6574:5): [True: 0, False: 2.24k] ------------------ 6575| 0| case ARM::VPMAXu32: ------------------ | Branch (6575:5): [True: 0, False: 2.24k] ------------------ 6576| 0| case ARM::VPMAXu8: ------------------ | Branch (6576:5): [True: 0, False: 2.24k] ------------------ 6577| 0| case ARM::VPMINf: ------------------ | Branch (6577:5): [True: 0, False: 2.24k] ------------------ 6578| 0| case ARM::VPMINh: ------------------ | Branch (6578:5): [True: 0, False: 2.24k] ------------------ 6579| 0| case ARM::VPMINs16: ------------------ | Branch (6579:5): [True: 0, False: 2.24k] ------------------ 6580| 0| case ARM::VPMINs32: ------------------ | Branch (6580:5): [True: 0, False: 2.24k] ------------------ 6581| 0| case ARM::VPMINs8: ------------------ | Branch (6581:5): [True: 0, False: 2.24k] ------------------ 6582| 0| case ARM::VPMINu16: ------------------ | Branch (6582:5): [True: 0, False: 2.24k] ------------------ 6583| 0| case ARM::VPMINu32: ------------------ | Branch (6583:5): [True: 0, False: 2.24k] ------------------ 6584| 0| case ARM::VPMINu8: ------------------ | Branch (6584:5): [True: 0, False: 2.24k] ------------------ 6585| 0| case ARM::VQADDsv16i8: ------------------ | Branch (6585:5): [True: 0, False: 2.24k] ------------------ 6586| 0| case ARM::VQADDsv1i64: ------------------ | Branch (6586:5): [True: 0, False: 2.24k] ------------------ 6587| 0| case ARM::VQADDsv2i32: ------------------ | Branch (6587:5): [True: 0, False: 2.24k] ------------------ 6588| 0| case ARM::VQADDsv2i64: ------------------ | Branch (6588:5): [True: 0, False: 2.24k] ------------------ 6589| 0| case ARM::VQADDsv4i16: ------------------ | Branch (6589:5): [True: 0, False: 2.24k] ------------------ 6590| 0| case ARM::VQADDsv4i32: ------------------ | Branch (6590:5): [True: 0, False: 2.24k] ------------------ 6591| 0| case ARM::VQADDsv8i16: ------------------ | Branch (6591:5): [True: 0, False: 2.24k] ------------------ 6592| 0| case ARM::VQADDsv8i8: ------------------ | Branch (6592:5): [True: 0, False: 2.24k] ------------------ 6593| 0| case ARM::VQADDuv16i8: ------------------ | Branch (6593:5): [True: 0, False: 2.24k] ------------------ 6594| 0| case ARM::VQADDuv1i64: ------------------ | Branch (6594:5): [True: 0, False: 2.24k] ------------------ 6595| 0| case ARM::VQADDuv2i32: ------------------ | Branch (6595:5): [True: 0, False: 2.24k] ------------------ 6596| 0| case ARM::VQADDuv2i64: ------------------ | Branch (6596:5): [True: 0, False: 2.24k] ------------------ 6597| 0| case ARM::VQADDuv4i16: ------------------ | Branch (6597:5): [True: 0, False: 2.24k] ------------------ 6598| 0| case ARM::VQADDuv4i32: ------------------ | Branch (6598:5): [True: 0, False: 2.24k] ------------------ 6599| 0| case ARM::VQADDuv8i16: ------------------ | Branch (6599:5): [True: 0, False: 2.24k] ------------------ 6600| 0| case ARM::VQADDuv8i8: ------------------ | Branch (6600:5): [True: 0, False: 2.24k] ------------------ 6601| 0| case ARM::VQDMULHv2i32: ------------------ | Branch (6601:5): [True: 0, False: 2.24k] ------------------ 6602| 0| case ARM::VQDMULHv4i16: ------------------ | Branch (6602:5): [True: 0, False: 2.24k] ------------------ 6603| 0| case ARM::VQDMULHv4i32: ------------------ | Branch (6603:5): [True: 0, False: 2.24k] ------------------ 6604| 0| case ARM::VQDMULHv8i16: ------------------ | Branch (6604:5): [True: 0, False: 2.24k] ------------------ 6605| 0| case ARM::VQDMULLv2i64: ------------------ | Branch (6605:5): [True: 0, False: 2.24k] ------------------ 6606| 0| case ARM::VQDMULLv4i32: ------------------ | Branch (6606:5): [True: 0, False: 2.24k] ------------------ 6607| 0| case ARM::VQRDMULHv2i32: ------------------ | Branch (6607:5): [True: 0, False: 2.24k] ------------------ 6608| 0| case ARM::VQRDMULHv4i16: ------------------ | Branch (6608:5): [True: 0, False: 2.24k] ------------------ 6609| 0| case ARM::VQRDMULHv4i32: ------------------ | Branch (6609:5): [True: 0, False: 2.24k] ------------------ 6610| 0| case ARM::VQRDMULHv8i16: ------------------ | Branch (6610:5): [True: 0, False: 2.24k] ------------------ 6611| 0| case ARM::VQSUBsv16i8: ------------------ | Branch (6611:5): [True: 0, False: 2.24k] ------------------ 6612| 0| case ARM::VQSUBsv1i64: ------------------ | Branch (6612:5): [True: 0, False: 2.24k] ------------------ 6613| 0| case ARM::VQSUBsv2i32: ------------------ | Branch (6613:5): [True: 0, False: 2.24k] ------------------ 6614| 0| case ARM::VQSUBsv2i64: ------------------ | Branch (6614:5): [True: 0, False: 2.24k] ------------------ 6615| 0| case ARM::VQSUBsv4i16: ------------------ | Branch (6615:5): [True: 0, False: 2.24k] ------------------ 6616| 0| case ARM::VQSUBsv4i32: ------------------ | Branch (6616:5): [True: 0, False: 2.24k] ------------------ 6617| 0| case ARM::VQSUBsv8i16: ------------------ | Branch (6617:5): [True: 0, False: 2.24k] ------------------ 6618| 0| case ARM::VQSUBsv8i8: ------------------ | Branch (6618:5): [True: 0, False: 2.24k] ------------------ 6619| 0| case ARM::VQSUBuv16i8: ------------------ | Branch (6619:5): [True: 0, False: 2.24k] ------------------ 6620| 0| case ARM::VQSUBuv1i64: ------------------ | Branch (6620:5): [True: 0, False: 2.24k] ------------------ 6621| 0| case ARM::VQSUBuv2i32: ------------------ | Branch (6621:5): [True: 0, False: 2.24k] ------------------ 6622| 0| case ARM::VQSUBuv2i64: ------------------ | Branch (6622:5): [True: 0, False: 2.24k] ------------------ 6623| 0| case ARM::VQSUBuv4i16: ------------------ | Branch (6623:5): [True: 0, False: 2.24k] ------------------ 6624| 0| case ARM::VQSUBuv4i32: ------------------ | Branch (6624:5): [True: 0, False: 2.24k] ------------------ 6625| 0| case ARM::VQSUBuv8i16: ------------------ | Branch (6625:5): [True: 0, False: 2.24k] ------------------ 6626| 0| case ARM::VQSUBuv8i8: ------------------ | Branch (6626:5): [True: 0, False: 2.24k] ------------------ 6627| 0| case ARM::VRADDHNv2i32: ------------------ | Branch (6627:5): [True: 0, False: 2.24k] ------------------ 6628| 0| case ARM::VRADDHNv4i16: ------------------ | Branch (6628:5): [True: 0, False: 2.24k] ------------------ 6629| 0| case ARM::VRADDHNv8i8: ------------------ | Branch (6629:5): [True: 0, False: 2.24k] ------------------ 6630| 0| case ARM::VRECPSfd: ------------------ | Branch (6630:5): [True: 0, False: 2.24k] ------------------ 6631| 0| case ARM::VRECPSfq: ------------------ | Branch (6631:5): [True: 0, False: 2.24k] ------------------ 6632| 0| case ARM::VRECPShd: ------------------ | Branch (6632:5): [True: 0, False: 2.24k] ------------------ 6633| 0| case ARM::VRECPShq: ------------------ | Branch (6633:5): [True: 0, False: 2.24k] ------------------ 6634| 0| case ARM::VRHADDsv16i8: ------------------ | Branch (6634:5): [True: 0, False: 2.24k] ------------------ 6635| 0| case ARM::VRHADDsv2i32: ------------------ | Branch (6635:5): [True: 0, False: 2.24k] ------------------ 6636| 0| case ARM::VRHADDsv4i16: ------------------ | Branch (6636:5): [True: 0, False: 2.24k] ------------------ 6637| 0| case ARM::VRHADDsv4i32: ------------------ | Branch (6637:5): [True: 0, False: 2.24k] ------------------ 6638| 0| case ARM::VRHADDsv8i16: ------------------ | Branch (6638:5): [True: 0, False: 2.24k] ------------------ 6639| 0| case ARM::VRHADDsv8i8: ------------------ | Branch (6639:5): [True: 0, False: 2.24k] ------------------ 6640| 0| case ARM::VRHADDuv16i8: ------------------ | Branch (6640:5): [True: 0, False: 2.24k] ------------------ 6641| 0| case ARM::VRHADDuv2i32: ------------------ | Branch (6641:5): [True: 0, False: 2.24k] ------------------ 6642| 0| case ARM::VRHADDuv4i16: ------------------ | Branch (6642:5): [True: 0, False: 2.24k] ------------------ 6643| 0| case ARM::VRHADDuv4i32: ------------------ | Branch (6643:5): [True: 0, False: 2.24k] ------------------ 6644| 0| case ARM::VRHADDuv8i16: ------------------ | Branch (6644:5): [True: 0, False: 2.24k] ------------------ 6645| 0| case ARM::VRHADDuv8i8: ------------------ | Branch (6645:5): [True: 0, False: 2.24k] ------------------ 6646| 0| case ARM::VRSQRTSfd: ------------------ | Branch (6646:5): [True: 0, False: 2.24k] ------------------ 6647| 0| case ARM::VRSQRTSfq: ------------------ | Branch (6647:5): [True: 0, False: 2.24k] ------------------ 6648| 0| case ARM::VRSQRTShd: ------------------ | Branch (6648:5): [True: 0, False: 2.24k] ------------------ 6649| 0| case ARM::VRSQRTShq: ------------------ | Branch (6649:5): [True: 0, False: 2.24k] ------------------ 6650| 0| case ARM::VRSUBHNv2i32: ------------------ | Branch (6650:5): [True: 0, False: 2.24k] ------------------ 6651| 0| case ARM::VRSUBHNv4i16: ------------------ | Branch (6651:5): [True: 0, False: 2.24k] ------------------ 6652| 0| case ARM::VRSUBHNv8i8: ------------------ | Branch (6652:5): [True: 0, False: 2.24k] ------------------ 6653| 0| case ARM::VSUBHNv2i32: ------------------ | Branch (6653:5): [True: 0, False: 2.24k] ------------------ 6654| 0| case ARM::VSUBHNv4i16: ------------------ | Branch (6654:5): [True: 0, False: 2.24k] ------------------ 6655| 0| case ARM::VSUBHNv8i8: ------------------ | Branch (6655:5): [True: 0, False: 2.24k] ------------------ 6656| 0| case ARM::VSUBLsv2i64: ------------------ | Branch (6656:5): [True: 0, False: 2.24k] ------------------ 6657| 0| case ARM::VSUBLsv4i32: ------------------ | Branch (6657:5): [True: 0, False: 2.24k] ------------------ 6658| 0| case ARM::VSUBLsv8i16: ------------------ | Branch (6658:5): [True: 0, False: 2.24k] ------------------ 6659| 0| case ARM::VSUBLuv2i64: ------------------ | Branch (6659:5): [True: 0, False: 2.24k] ------------------ 6660| 0| case ARM::VSUBLuv4i32: ------------------ | Branch (6660:5): [True: 0, False: 2.24k] ------------------ 6661| 0| case ARM::VSUBLuv8i16: ------------------ | Branch (6661:5): [True: 0, False: 2.24k] ------------------ 6662| 0| case ARM::VSUBWsv2i64: ------------------ | Branch (6662:5): [True: 0, False: 2.24k] ------------------ 6663| 0| case ARM::VSUBWsv4i32: ------------------ | Branch (6663:5): [True: 0, False: 2.24k] ------------------ 6664| 0| case ARM::VSUBWsv8i16: ------------------ | Branch (6664:5): [True: 0, False: 2.24k] ------------------ 6665| 0| case ARM::VSUBWuv2i64: ------------------ | Branch (6665:5): [True: 0, False: 2.24k] ------------------ 6666| 0| case ARM::VSUBWuv4i32: ------------------ | Branch (6666:5): [True: 0, False: 2.24k] ------------------ 6667| 0| case ARM::VSUBWuv8i16: ------------------ | Branch (6667:5): [True: 0, False: 2.24k] ------------------ 6668| 0| case ARM::VSUBfd: ------------------ | Branch (6668:5): [True: 0, False: 2.24k] ------------------ 6669| 0| case ARM::VSUBfq: ------------------ | Branch (6669:5): [True: 0, False: 2.24k] ------------------ 6670| 0| case ARM::VSUBhd: ------------------ | Branch (6670:5): [True: 0, False: 2.24k] ------------------ 6671| 0| case ARM::VSUBhq: ------------------ | Branch (6671:5): [True: 0, False: 2.24k] ------------------ 6672| 0| case ARM::VSUBv16i8: ------------------ | Branch (6672:5): [True: 0, False: 2.24k] ------------------ 6673| 0| case ARM::VSUBv1i64: ------------------ | Branch (6673:5): [True: 0, False: 2.24k] ------------------ 6674| 0| case ARM::VSUBv2i32: ------------------ | Branch (6674:5): [True: 0, False: 2.24k] ------------------ 6675| 0| case ARM::VSUBv2i64: ------------------ | Branch (6675:5): [True: 0, False: 2.24k] ------------------ 6676| 0| case ARM::VSUBv4i16: ------------------ | Branch (6676:5): [True: 0, False: 2.24k] ------------------ 6677| 0| case ARM::VSUBv4i32: ------------------ | Branch (6677:5): [True: 0, False: 2.24k] ------------------ 6678| 0| case ARM::VSUBv8i16: ------------------ | Branch (6678:5): [True: 0, False: 2.24k] ------------------ 6679| 0| case ARM::VSUBv8i8: ------------------ | Branch (6679:5): [True: 0, False: 2.24k] ------------------ 6680| 0| case ARM::VTBL1: ------------------ | Branch (6680:5): [True: 0, False: 2.24k] ------------------ 6681| 0| case ARM::VTBL2: ------------------ | Branch (6681:5): [True: 0, False: 2.24k] ------------------ 6682| 0| case ARM::VTBL3: ------------------ | Branch (6682:5): [True: 0, False: 2.24k] ------------------ 6683| 0| case ARM::VTBL4: ------------------ | Branch (6683:5): [True: 0, False: 2.24k] ------------------ 6684| 0| case ARM::VTSTv16i8: ------------------ | Branch (6684:5): [True: 0, False: 2.24k] ------------------ 6685| 0| case ARM::VTSTv2i32: ------------------ | Branch (6685:5): [True: 0, False: 2.24k] ------------------ 6686| 0| case ARM::VTSTv4i16: ------------------ | Branch (6686:5): [True: 0, False: 2.24k] ------------------ 6687| 0| case ARM::VTSTv4i32: ------------------ | Branch (6687:5): [True: 0, False: 2.24k] ------------------ 6688| 0| case ARM::VTSTv8i16: ------------------ | Branch (6688:5): [True: 0, False: 2.24k] ------------------ 6689| 0| case ARM::VTSTv8i8: { ------------------ | Branch (6689:5): [True: 0, False: 2.24k] ------------------ 6690| | // op: Vd 6691| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6692| 0| Value |= (op & UINT64_C(16)) << 18; 6693| 0| Value |= (op & UINT64_C(15)) << 12; 6694| | // op: Vn 6695| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6696| 0| Value |= (op & UINT64_C(15)) << 16; 6697| 0| Value |= (op & UINT64_C(16)) << 3; 6698| | // op: Vm 6699| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6700| 0| Value |= (op & UINT64_C(16)) << 1; 6701| 0| Value |= op & UINT64_C(15); 6702| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6703| 0| break; 6704| 0| } 6705| 0| case ARM::VMAXNMNDf: ------------------ | Branch (6705:5): [True: 0, False: 2.24k] ------------------ 6706| 0| case ARM::VMAXNMNDh: ------------------ | Branch (6706:5): [True: 0, False: 2.24k] ------------------ 6707| 0| case ARM::VMAXNMNQf: ------------------ | Branch (6707:5): [True: 0, False: 2.24k] ------------------ 6708| 0| case ARM::VMAXNMNQh: ------------------ | Branch (6708:5): [True: 0, False: 2.24k] ------------------ 6709| 0| case ARM::VMINNMNDf: ------------------ | Branch (6709:5): [True: 0, False: 2.24k] ------------------ 6710| 0| case ARM::VMINNMNDh: ------------------ | Branch (6710:5): [True: 0, False: 2.24k] ------------------ 6711| 0| case ARM::VMINNMNQf: ------------------ | Branch (6711:5): [True: 0, False: 2.24k] ------------------ 6712| 0| case ARM::VMINNMNQh: { ------------------ | Branch (6712:5): [True: 0, False: 2.24k] ------------------ 6713| | // op: Vd 6714| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6715| 0| Value |= (op & UINT64_C(16)) << 18; 6716| 0| Value |= (op & UINT64_C(15)) << 12; 6717| | // op: Vn 6718| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6719| 0| Value |= (op & UINT64_C(15)) << 16; 6720| 0| Value |= (op & UINT64_C(16)) << 3; 6721| | // op: Vm 6722| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6723| 0| Value |= (op & UINT64_C(16)) << 1; 6724| 0| Value |= op & UINT64_C(15); 6725| 0| Value = NEONThumb2V8PostEncoder(MI, Value, STI); 6726| 0| break; 6727| 0| } 6728| 0| case ARM::VMULLslsv2i32: ------------------ | Branch (6728:5): [True: 0, False: 2.24k] ------------------ 6729| 0| case ARM::VMULLsluv2i32: ------------------ | Branch (6729:5): [True: 0, False: 2.24k] ------------------ 6730| 0| case ARM::VMULslfd: ------------------ | Branch (6730:5): [True: 0, False: 2.24k] ------------------ 6731| 0| case ARM::VMULslfq: ------------------ | Branch (6731:5): [True: 0, False: 2.24k] ------------------ 6732| 0| case ARM::VMULslv2i32: ------------------ | Branch (6732:5): [True: 0, False: 2.24k] ------------------ 6733| 0| case ARM::VMULslv4i32: ------------------ | Branch (6733:5): [True: 0, False: 2.24k] ------------------ 6734| 0| case ARM::VQDMULHslv2i32: ------------------ | Branch (6734:5): [True: 0, False: 2.24k] ------------------ 6735| 0| case ARM::VQDMULHslv4i32: ------------------ | Branch (6735:5): [True: 0, False: 2.24k] ------------------ 6736| 0| case ARM::VQDMULLslv2i32: ------------------ | Branch (6736:5): [True: 0, False: 2.24k] ------------------ 6737| 0| case ARM::VQRDMULHslv2i32: ------------------ | Branch (6737:5): [True: 0, False: 2.24k] ------------------ 6738| 0| case ARM::VQRDMULHslv4i32: { ------------------ | Branch (6738:5): [True: 0, False: 2.24k] ------------------ 6739| | // op: Vd 6740| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6741| 0| Value |= (op & UINT64_C(16)) << 18; 6742| 0| Value |= (op & UINT64_C(15)) << 12; 6743| | // op: Vn 6744| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6745| 0| Value |= (op & UINT64_C(15)) << 16; 6746| 0| Value |= (op & UINT64_C(16)) << 3; 6747| | // op: Vm 6748| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6749| 0| Value |= op & UINT64_C(15); 6750| | // op: lane 6751| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6752| 0| Value |= (op & UINT64_C(1)) << 5; 6753| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6754| 0| break; 6755| 0| } 6756| 0| case ARM::VMULLslsv4i16: ------------------ | Branch (6756:5): [True: 0, False: 2.24k] ------------------ 6757| 0| case ARM::VMULLsluv4i16: ------------------ | Branch (6757:5): [True: 0, False: 2.24k] ------------------ 6758| 0| case ARM::VMULslhd: ------------------ | Branch (6758:5): [True: 0, False: 2.24k] ------------------ 6759| 0| case ARM::VMULslhq: ------------------ | Branch (6759:5): [True: 0, False: 2.24k] ------------------ 6760| 0| case ARM::VMULslv4i16: ------------------ | Branch (6760:5): [True: 0, False: 2.24k] ------------------ 6761| 0| case ARM::VMULslv8i16: ------------------ | Branch (6761:5): [True: 0, False: 2.24k] ------------------ 6762| 0| case ARM::VQDMULHslv4i16: ------------------ | Branch (6762:5): [True: 0, False: 2.24k] ------------------ 6763| 0| case ARM::VQDMULHslv8i16: ------------------ | Branch (6763:5): [True: 0, False: 2.24k] ------------------ 6764| 0| case ARM::VQDMULLslv4i16: ------------------ | Branch (6764:5): [True: 0, False: 2.24k] ------------------ 6765| 0| case ARM::VQRDMULHslv4i16: ------------------ | Branch (6765:5): [True: 0, False: 2.24k] ------------------ 6766| 0| case ARM::VQRDMULHslv8i16: { ------------------ | Branch (6766:5): [True: 0, False: 2.24k] ------------------ 6767| | // op: Vd 6768| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6769| 0| Value |= (op & UINT64_C(16)) << 18; 6770| 0| Value |= (op & UINT64_C(15)) << 12; 6771| | // op: Vn 6772| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6773| 0| Value |= (op & UINT64_C(15)) << 16; 6774| 0| Value |= (op & UINT64_C(16)) << 3; 6775| | // op: Vm 6776| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6777| 0| Value |= op & UINT64_C(7); 6778| | // op: lane 6779| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6780| 0| Value |= (op & UINT64_C(2)) << 4; 6781| 0| Value |= (op & UINT64_C(1)) << 3; 6782| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6783| 0| break; 6784| 0| } 6785| 0| case ARM::VQRSHLsv16i8: ------------------ | Branch (6785:5): [True: 0, False: 2.24k] ------------------ 6786| 0| case ARM::VQRSHLsv1i64: ------------------ | Branch (6786:5): [True: 0, False: 2.24k] ------------------ 6787| 0| case ARM::VQRSHLsv2i32: ------------------ | Branch (6787:5): [True: 0, False: 2.24k] ------------------ 6788| 0| case ARM::VQRSHLsv2i64: ------------------ | Branch (6788:5): [True: 0, False: 2.24k] ------------------ 6789| 0| case ARM::VQRSHLsv4i16: ------------------ | Branch (6789:5): [True: 0, False: 2.24k] ------------------ 6790| 0| case ARM::VQRSHLsv4i32: ------------------ | Branch (6790:5): [True: 0, False: 2.24k] ------------------ 6791| 0| case ARM::VQRSHLsv8i16: ------------------ | Branch (6791:5): [True: 0, False: 2.24k] ------------------ 6792| 0| case ARM::VQRSHLsv8i8: ------------------ | Branch (6792:5): [True: 0, False: 2.24k] ------------------ 6793| 0| case ARM::VQRSHLuv16i8: ------------------ | Branch (6793:5): [True: 0, False: 2.24k] ------------------ 6794| 0| case ARM::VQRSHLuv1i64: ------------------ | Branch (6794:5): [True: 0, False: 2.24k] ------------------ 6795| 0| case ARM::VQRSHLuv2i32: ------------------ | Branch (6795:5): [True: 0, False: 2.24k] ------------------ 6796| 0| case ARM::VQRSHLuv2i64: ------------------ | Branch (6796:5): [True: 0, False: 2.24k] ------------------ 6797| 0| case ARM::VQRSHLuv4i16: ------------------ | Branch (6797:5): [True: 0, False: 2.24k] ------------------ 6798| 0| case ARM::VQRSHLuv4i32: ------------------ | Branch (6798:5): [True: 0, False: 2.24k] ------------------ 6799| 0| case ARM::VQRSHLuv8i16: ------------------ | Branch (6799:5): [True: 0, False: 2.24k] ------------------ 6800| 0| case ARM::VQRSHLuv8i8: ------------------ | Branch (6800:5): [True: 0, False: 2.24k] ------------------ 6801| 0| case ARM::VQSHLsv16i8: ------------------ | Branch (6801:5): [True: 0, False: 2.24k] ------------------ 6802| 0| case ARM::VQSHLsv1i64: ------------------ | Branch (6802:5): [True: 0, False: 2.24k] ------------------ 6803| 0| case ARM::VQSHLsv2i32: ------------------ | Branch (6803:5): [True: 0, False: 2.24k] ------------------ 6804| 0| case ARM::VQSHLsv2i64: ------------------ | Branch (6804:5): [True: 0, False: 2.24k] ------------------ 6805| 0| case ARM::VQSHLsv4i16: ------------------ | Branch (6805:5): [True: 0, False: 2.24k] ------------------ 6806| 0| case ARM::VQSHLsv4i32: ------------------ | Branch (6806:5): [True: 0, False: 2.24k] ------------------ 6807| 0| case ARM::VQSHLsv8i16: ------------------ | Branch (6807:5): [True: 0, False: 2.24k] ------------------ 6808| 0| case ARM::VQSHLsv8i8: ------------------ | Branch (6808:5): [True: 0, False: 2.24k] ------------------ 6809| 0| case ARM::VQSHLuv16i8: ------------------ | Branch (6809:5): [True: 0, False: 2.24k] ------------------ 6810| 0| case ARM::VQSHLuv1i64: ------------------ | Branch (6810:5): [True: 0, False: 2.24k] ------------------ 6811| 0| case ARM::VQSHLuv2i32: ------------------ | Branch (6811:5): [True: 0, False: 2.24k] ------------------ 6812| 0| case ARM::VQSHLuv2i64: ------------------ | Branch (6812:5): [True: 0, False: 2.24k] ------------------ 6813| 0| case ARM::VQSHLuv4i16: ------------------ | Branch (6813:5): [True: 0, False: 2.24k] ------------------ 6814| 0| case ARM::VQSHLuv4i32: ------------------ | Branch (6814:5): [True: 0, False: 2.24k] ------------------ 6815| 0| case ARM::VQSHLuv8i16: ------------------ | Branch (6815:5): [True: 0, False: 2.24k] ------------------ 6816| 0| case ARM::VQSHLuv8i8: ------------------ | Branch (6816:5): [True: 0, False: 2.24k] ------------------ 6817| 0| case ARM::VRSHLsv16i8: ------------------ | Branch (6817:5): [True: 0, False: 2.24k] ------------------ 6818| 0| case ARM::VRSHLsv1i64: ------------------ | Branch (6818:5): [True: 0, False: 2.24k] ------------------ 6819| 0| case ARM::VRSHLsv2i32: ------------------ | Branch (6819:5): [True: 0, False: 2.24k] ------------------ 6820| 0| case ARM::VRSHLsv2i64: ------------------ | Branch (6820:5): [True: 0, False: 2.24k] ------------------ 6821| 0| case ARM::VRSHLsv4i16: ------------------ | Branch (6821:5): [True: 0, False: 2.24k] ------------------ 6822| 0| case ARM::VRSHLsv4i32: ------------------ | Branch (6822:5): [True: 0, False: 2.24k] ------------------ 6823| 0| case ARM::VRSHLsv8i16: ------------------ | Branch (6823:5): [True: 0, False: 2.24k] ------------------ 6824| 0| case ARM::VRSHLsv8i8: ------------------ | Branch (6824:5): [True: 0, False: 2.24k] ------------------ 6825| 0| case ARM::VRSHLuv16i8: ------------------ | Branch (6825:5): [True: 0, False: 2.24k] ------------------ 6826| 0| case ARM::VRSHLuv1i64: ------------------ | Branch (6826:5): [True: 0, False: 2.24k] ------------------ 6827| 0| case ARM::VRSHLuv2i32: ------------------ | Branch (6827:5): [True: 0, False: 2.24k] ------------------ 6828| 0| case ARM::VRSHLuv2i64: ------------------ | Branch (6828:5): [True: 0, False: 2.24k] ------------------ 6829| 0| case ARM::VRSHLuv4i16: ------------------ | Branch (6829:5): [True: 0, False: 2.24k] ------------------ 6830| 0| case ARM::VRSHLuv4i32: ------------------ | Branch (6830:5): [True: 0, False: 2.24k] ------------------ 6831| 0| case ARM::VRSHLuv8i16: ------------------ | Branch (6831:5): [True: 0, False: 2.24k] ------------------ 6832| 0| case ARM::VRSHLuv8i8: ------------------ | Branch (6832:5): [True: 0, False: 2.24k] ------------------ 6833| 0| case ARM::VSHLsv16i8: ------------------ | Branch (6833:5): [True: 0, False: 2.24k] ------------------ 6834| 0| case ARM::VSHLsv1i64: ------------------ | Branch (6834:5): [True: 0, False: 2.24k] ------------------ 6835| 0| case ARM::VSHLsv2i32: ------------------ | Branch (6835:5): [True: 0, False: 2.24k] ------------------ 6836| 0| case ARM::VSHLsv2i64: ------------------ | Branch (6836:5): [True: 0, False: 2.24k] ------------------ 6837| 0| case ARM::VSHLsv4i16: ------------------ | Branch (6837:5): [True: 0, False: 2.24k] ------------------ 6838| 0| case ARM::VSHLsv4i32: ------------------ | Branch (6838:5): [True: 0, False: 2.24k] ------------------ 6839| 0| case ARM::VSHLsv8i16: ------------------ | Branch (6839:5): [True: 0, False: 2.24k] ------------------ 6840| 0| case ARM::VSHLsv8i8: ------------------ | Branch (6840:5): [True: 0, False: 2.24k] ------------------ 6841| 0| case ARM::VSHLuv16i8: ------------------ | Branch (6841:5): [True: 0, False: 2.24k] ------------------ 6842| 0| case ARM::VSHLuv1i64: ------------------ | Branch (6842:5): [True: 0, False: 2.24k] ------------------ 6843| 0| case ARM::VSHLuv2i32: ------------------ | Branch (6843:5): [True: 0, False: 2.24k] ------------------ 6844| 0| case ARM::VSHLuv2i64: ------------------ | Branch (6844:5): [True: 0, False: 2.24k] ------------------ 6845| 0| case ARM::VSHLuv4i16: ------------------ | Branch (6845:5): [True: 0, False: 2.24k] ------------------ 6846| 0| case ARM::VSHLuv4i32: ------------------ | Branch (6846:5): [True: 0, False: 2.24k] ------------------ 6847| 0| case ARM::VSHLuv8i16: ------------------ | Branch (6847:5): [True: 0, False: 2.24k] ------------------ 6848| 0| case ARM::VSHLuv8i8: { ------------------ | Branch (6848:5): [True: 0, False: 2.24k] ------------------ 6849| | // op: Vd 6850| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6851| 0| Value |= (op & UINT64_C(16)) << 18; 6852| 0| Value |= (op & UINT64_C(15)) << 12; 6853| | // op: Vn 6854| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6855| 0| Value |= (op & UINT64_C(15)) << 16; 6856| 0| Value |= (op & UINT64_C(16)) << 3; 6857| | // op: Vm 6858| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6859| 0| Value |= (op & UINT64_C(16)) << 1; 6860| 0| Value |= op & UINT64_C(15); 6861| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6862| 0| break; 6863| 0| } 6864| 0| case ARM::SHA1C: ------------------ | Branch (6864:5): [True: 0, False: 2.24k] ------------------ 6865| 0| case ARM::SHA1M: ------------------ | Branch (6865:5): [True: 0, False: 2.24k] ------------------ 6866| 0| case ARM::SHA1P: ------------------ | Branch (6866:5): [True: 0, False: 2.24k] ------------------ 6867| 0| case ARM::SHA1SU0: ------------------ | Branch (6867:5): [True: 0, False: 2.24k] ------------------ 6868| 0| case ARM::SHA256H: ------------------ | Branch (6868:5): [True: 0, False: 2.24k] ------------------ 6869| 0| case ARM::SHA256H2: ------------------ | Branch (6869:5): [True: 0, False: 2.24k] ------------------ 6870| 0| case ARM::SHA256SU1: ------------------ | Branch (6870:5): [True: 0, False: 2.24k] ------------------ 6871| 0| case ARM::VABALsv2i64: ------------------ | Branch (6871:5): [True: 0, False: 2.24k] ------------------ 6872| 0| case ARM::VABALsv4i32: ------------------ | Branch (6872:5): [True: 0, False: 2.24k] ------------------ 6873| 0| case ARM::VABALsv8i16: ------------------ | Branch (6873:5): [True: 0, False: 2.24k] ------------------ 6874| 0| case ARM::VABALuv2i64: ------------------ | Branch (6874:5): [True: 0, False: 2.24k] ------------------ 6875| 0| case ARM::VABALuv4i32: ------------------ | Branch (6875:5): [True: 0, False: 2.24k] ------------------ 6876| 0| case ARM::VABALuv8i16: ------------------ | Branch (6876:5): [True: 0, False: 2.24k] ------------------ 6877| 0| case ARM::VABAsv16i8: ------------------ | Branch (6877:5): [True: 0, False: 2.24k] ------------------ 6878| 0| case ARM::VABAsv2i32: ------------------ | Branch (6878:5): [True: 0, False: 2.24k] ------------------ 6879| 0| case ARM::VABAsv4i16: ------------------ | Branch (6879:5): [True: 0, False: 2.24k] ------------------ 6880| 0| case ARM::VABAsv4i32: ------------------ | Branch (6880:5): [True: 0, False: 2.24k] ------------------ 6881| 0| case ARM::VABAsv8i16: ------------------ | Branch (6881:5): [True: 0, False: 2.24k] ------------------ 6882| 0| case ARM::VABAsv8i8: ------------------ | Branch (6882:5): [True: 0, False: 2.24k] ------------------ 6883| 0| case ARM::VABAuv16i8: ------------------ | Branch (6883:5): [True: 0, False: 2.24k] ------------------ 6884| 0| case ARM::VABAuv2i32: ------------------ | Branch (6884:5): [True: 0, False: 2.24k] ------------------ 6885| 0| case ARM::VABAuv4i16: ------------------ | Branch (6885:5): [True: 0, False: 2.24k] ------------------ 6886| 0| case ARM::VABAuv4i32: ------------------ | Branch (6886:5): [True: 0, False: 2.24k] ------------------ 6887| 0| case ARM::VABAuv8i16: ------------------ | Branch (6887:5): [True: 0, False: 2.24k] ------------------ 6888| 0| case ARM::VABAuv8i8: ------------------ | Branch (6888:5): [True: 0, False: 2.24k] ------------------ 6889| 0| case ARM::VBIFd: ------------------ | Branch (6889:5): [True: 0, False: 2.24k] ------------------ 6890| 0| case ARM::VBIFq: ------------------ | Branch (6890:5): [True: 0, False: 2.24k] ------------------ 6891| 0| case ARM::VBITd: ------------------ | Branch (6891:5): [True: 0, False: 2.24k] ------------------ 6892| 0| case ARM::VBITq: ------------------ | Branch (6892:5): [True: 0, False: 2.24k] ------------------ 6893| 0| case ARM::VBSLd: ------------------ | Branch (6893:5): [True: 0, False: 2.24k] ------------------ 6894| 0| case ARM::VBSLq: ------------------ | Branch (6894:5): [True: 0, False: 2.24k] ------------------ 6895| 0| case ARM::VFMAfd: ------------------ | Branch (6895:5): [True: 0, False: 2.24k] ------------------ 6896| 0| case ARM::VFMAfq: ------------------ | Branch (6896:5): [True: 0, False: 2.24k] ------------------ 6897| 0| case ARM::VFMAhd: ------------------ | Branch (6897:5): [True: 0, False: 2.24k] ------------------ 6898| 0| case ARM::VFMAhq: ------------------ | Branch (6898:5): [True: 0, False: 2.24k] ------------------ 6899| 0| case ARM::VFMSfd: ------------------ | Branch (6899:5): [True: 0, False: 2.24k] ------------------ 6900| 0| case ARM::VFMSfq: ------------------ | Branch (6900:5): [True: 0, False: 2.24k] ------------------ 6901| 0| case ARM::VFMShd: ------------------ | Branch (6901:5): [True: 0, False: 2.24k] ------------------ 6902| 0| case ARM::VFMShq: ------------------ | Branch (6902:5): [True: 0, False: 2.24k] ------------------ 6903| 0| case ARM::VMLALsv2i64: ------------------ | Branch (6903:5): [True: 0, False: 2.24k] ------------------ 6904| 0| case ARM::VMLALsv4i32: ------------------ | Branch (6904:5): [True: 0, False: 2.24k] ------------------ 6905| 0| case ARM::VMLALsv8i16: ------------------ | Branch (6905:5): [True: 0, False: 2.24k] ------------------ 6906| 0| case ARM::VMLALuv2i64: ------------------ | Branch (6906:5): [True: 0, False: 2.24k] ------------------ 6907| 0| case ARM::VMLALuv4i32: ------------------ | Branch (6907:5): [True: 0, False: 2.24k] ------------------ 6908| 0| case ARM::VMLALuv8i16: ------------------ | Branch (6908:5): [True: 0, False: 2.24k] ------------------ 6909| 0| case ARM::VMLAfd: ------------------ | Branch (6909:5): [True: 0, False: 2.24k] ------------------ 6910| 0| case ARM::VMLAfq: ------------------ | Branch (6910:5): [True: 0, False: 2.24k] ------------------ 6911| 0| case ARM::VMLAhd: ------------------ | Branch (6911:5): [True: 0, False: 2.24k] ------------------ 6912| 0| case ARM::VMLAhq: ------------------ | Branch (6912:5): [True: 0, False: 2.24k] ------------------ 6913| 0| case ARM::VMLAv16i8: ------------------ | Branch (6913:5): [True: 0, False: 2.24k] ------------------ 6914| 0| case ARM::VMLAv2i32: ------------------ | Branch (6914:5): [True: 0, False: 2.24k] ------------------ 6915| 0| case ARM::VMLAv4i16: ------------------ | Branch (6915:5): [True: 0, False: 2.24k] ------------------ 6916| 0| case ARM::VMLAv4i32: ------------------ | Branch (6916:5): [True: 0, False: 2.24k] ------------------ 6917| 0| case ARM::VMLAv8i16: ------------------ | Branch (6917:5): [True: 0, False: 2.24k] ------------------ 6918| 0| case ARM::VMLAv8i8: ------------------ | Branch (6918:5): [True: 0, False: 2.24k] ------------------ 6919| 0| case ARM::VMLSLsv2i64: ------------------ | Branch (6919:5): [True: 0, False: 2.24k] ------------------ 6920| 0| case ARM::VMLSLsv4i32: ------------------ | Branch (6920:5): [True: 0, False: 2.24k] ------------------ 6921| 0| case ARM::VMLSLsv8i16: ------------------ | Branch (6921:5): [True: 0, False: 2.24k] ------------------ 6922| 0| case ARM::VMLSLuv2i64: ------------------ | Branch (6922:5): [True: 0, False: 2.24k] ------------------ 6923| 0| case ARM::VMLSLuv4i32: ------------------ | Branch (6923:5): [True: 0, False: 2.24k] ------------------ 6924| 0| case ARM::VMLSLuv8i16: ------------------ | Branch (6924:5): [True: 0, False: 2.24k] ------------------ 6925| 0| case ARM::VMLSfd: ------------------ | Branch (6925:5): [True: 0, False: 2.24k] ------------------ 6926| 0| case ARM::VMLSfq: ------------------ | Branch (6926:5): [True: 0, False: 2.24k] ------------------ 6927| 0| case ARM::VMLShd: ------------------ | Branch (6927:5): [True: 0, False: 2.24k] ------------------ 6928| 0| case ARM::VMLShq: ------------------ | Branch (6928:5): [True: 0, False: 2.24k] ------------------ 6929| 0| case ARM::VMLSv16i8: ------------------ | Branch (6929:5): [True: 0, False: 2.24k] ------------------ 6930| 0| case ARM::VMLSv2i32: ------------------ | Branch (6930:5): [True: 0, False: 2.24k] ------------------ 6931| 0| case ARM::VMLSv4i16: ------------------ | Branch (6931:5): [True: 0, False: 2.24k] ------------------ 6932| 0| case ARM::VMLSv4i32: ------------------ | Branch (6932:5): [True: 0, False: 2.24k] ------------------ 6933| 0| case ARM::VMLSv8i16: ------------------ | Branch (6933:5): [True: 0, False: 2.24k] ------------------ 6934| 0| case ARM::VMLSv8i8: ------------------ | Branch (6934:5): [True: 0, False: 2.24k] ------------------ 6935| 0| case ARM::VQDMLALv2i64: ------------------ | Branch (6935:5): [True: 0, False: 2.24k] ------------------ 6936| 0| case ARM::VQDMLALv4i32: ------------------ | Branch (6936:5): [True: 0, False: 2.24k] ------------------ 6937| 0| case ARM::VQDMLSLv2i64: ------------------ | Branch (6937:5): [True: 0, False: 2.24k] ------------------ 6938| 0| case ARM::VQDMLSLv4i32: ------------------ | Branch (6938:5): [True: 0, False: 2.24k] ------------------ 6939| 0| case ARM::VQRDMLAHv2i32: ------------------ | Branch (6939:5): [True: 0, False: 2.24k] ------------------ 6940| 0| case ARM::VQRDMLAHv4i16: ------------------ | Branch (6940:5): [True: 0, False: 2.24k] ------------------ 6941| 0| case ARM::VQRDMLAHv4i32: ------------------ | Branch (6941:5): [True: 0, False: 2.24k] ------------------ 6942| 0| case ARM::VQRDMLAHv8i16: ------------------ | Branch (6942:5): [True: 0, False: 2.24k] ------------------ 6943| 0| case ARM::VQRDMLSHv2i32: ------------------ | Branch (6943:5): [True: 0, False: 2.24k] ------------------ 6944| 0| case ARM::VQRDMLSHv4i16: ------------------ | Branch (6944:5): [True: 0, False: 2.24k] ------------------ 6945| 0| case ARM::VQRDMLSHv4i32: ------------------ | Branch (6945:5): [True: 0, False: 2.24k] ------------------ 6946| 0| case ARM::VQRDMLSHv8i16: ------------------ | Branch (6946:5): [True: 0, False: 2.24k] ------------------ 6947| 0| case ARM::VTBX1: ------------------ | Branch (6947:5): [True: 0, False: 2.24k] ------------------ 6948| 0| case ARM::VTBX2: ------------------ | Branch (6948:5): [True: 0, False: 2.24k] ------------------ 6949| 0| case ARM::VTBX3: ------------------ | Branch (6949:5): [True: 0, False: 2.24k] ------------------ 6950| 0| case ARM::VTBX4: { ------------------ | Branch (6950:5): [True: 0, False: 2.24k] ------------------ 6951| | // op: Vd 6952| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6953| 0| Value |= (op & UINT64_C(16)) << 18; 6954| 0| Value |= (op & UINT64_C(15)) << 12; 6955| | // op: Vn 6956| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6957| 0| Value |= (op & UINT64_C(15)) << 16; 6958| 0| Value |= (op & UINT64_C(16)) << 3; 6959| | // op: Vm 6960| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6961| 0| Value |= (op & UINT64_C(16)) << 1; 6962| 0| Value |= op & UINT64_C(15); 6963| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6964| 0| break; 6965| 0| } 6966| 0| case ARM::VMLALslsv2i32: ------------------ | Branch (6966:5): [True: 0, False: 2.24k] ------------------ 6967| 0| case ARM::VMLALsluv2i32: ------------------ | Branch (6967:5): [True: 0, False: 2.24k] ------------------ 6968| 0| case ARM::VMLAslfd: ------------------ | Branch (6968:5): [True: 0, False: 2.24k] ------------------ 6969| 0| case ARM::VMLAslfq: ------------------ | Branch (6969:5): [True: 0, False: 2.24k] ------------------ 6970| 0| case ARM::VMLAslv2i32: ------------------ | Branch (6970:5): [True: 0, False: 2.24k] ------------------ 6971| 0| case ARM::VMLAslv4i32: ------------------ | Branch (6971:5): [True: 0, False: 2.24k] ------------------ 6972| 0| case ARM::VMLSLslsv2i32: ------------------ | Branch (6972:5): [True: 0, False: 2.24k] ------------------ 6973| 0| case ARM::VMLSLsluv2i32: ------------------ | Branch (6973:5): [True: 0, False: 2.24k] ------------------ 6974| 0| case ARM::VMLSslfd: ------------------ | Branch (6974:5): [True: 0, False: 2.24k] ------------------ 6975| 0| case ARM::VMLSslfq: ------------------ | Branch (6975:5): [True: 0, False: 2.24k] ------------------ 6976| 0| case ARM::VMLSslv2i32: ------------------ | Branch (6976:5): [True: 0, False: 2.24k] ------------------ 6977| 0| case ARM::VMLSslv4i32: ------------------ | Branch (6977:5): [True: 0, False: 2.24k] ------------------ 6978| 0| case ARM::VQDMLALslv2i32: ------------------ | Branch (6978:5): [True: 0, False: 2.24k] ------------------ 6979| 0| case ARM::VQDMLSLslv2i32: ------------------ | Branch (6979:5): [True: 0, False: 2.24k] ------------------ 6980| 0| case ARM::VQRDMLAHslv2i32: ------------------ | Branch (6980:5): [True: 0, False: 2.24k] ------------------ 6981| 0| case ARM::VQRDMLAHslv4i32: ------------------ | Branch (6981:5): [True: 0, False: 2.24k] ------------------ 6982| 0| case ARM::VQRDMLSHslv2i32: ------------------ | Branch (6982:5): [True: 0, False: 2.24k] ------------------ 6983| 0| case ARM::VQRDMLSHslv4i32: { ------------------ | Branch (6983:5): [True: 0, False: 2.24k] ------------------ 6984| | // op: Vd 6985| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6986| 0| Value |= (op & UINT64_C(16)) << 18; 6987| 0| Value |= (op & UINT64_C(15)) << 12; 6988| | // op: Vn 6989| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6990| 0| Value |= (op & UINT64_C(15)) << 16; 6991| 0| Value |= (op & UINT64_C(16)) << 3; 6992| | // op: Vm 6993| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6994| 0| Value |= op & UINT64_C(15); 6995| | // op: lane 6996| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6997| 0| Value |= (op & UINT64_C(1)) << 5; 6998| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6999| 0| break; 7000| 0| } 7001| 0| case ARM::VMLALslsv4i16: ------------------ | Branch (7001:5): [True: 0, False: 2.24k] ------------------ 7002| 0| case ARM::VMLALsluv4i16: ------------------ | Branch (7002:5): [True: 0, False: 2.24k] ------------------ 7003| 0| case ARM::VMLAslhd: ------------------ | Branch (7003:5): [True: 0, False: 2.24k] ------------------ 7004| 0| case ARM::VMLAslhq: ------------------ | Branch (7004:5): [True: 0, False: 2.24k] ------------------ 7005| 0| case ARM::VMLAslv4i16: ------------------ | Branch (7005:5): [True: 0, False: 2.24k] ------------------ 7006| 0| case ARM::VMLAslv8i16: ------------------ | Branch (7006:5): [True: 0, False: 2.24k] ------------------ 7007| 0| case ARM::VMLSLslsv4i16: ------------------ | Branch (7007:5): [True: 0, False: 2.24k] ------------------ 7008| 0| case ARM::VMLSLsluv4i16: ------------------ | Branch (7008:5): [True: 0, False: 2.24k] ------------------ 7009| 0| case ARM::VMLSslhd: ------------------ | Branch (7009:5): [True: 0, False: 2.24k] ------------------ 7010| 0| case ARM::VMLSslhq: ------------------ | Branch (7010:5): [True: 0, False: 2.24k] ------------------ 7011| 0| case ARM::VMLSslv4i16: ------------------ | Branch (7011:5): [True: 0, False: 2.24k] ------------------ 7012| 0| case ARM::VMLSslv8i16: ------------------ | Branch (7012:5): [True: 0, False: 2.24k] ------------------ 7013| 0| case ARM::VQDMLALslv4i16: ------------------ | Branch (7013:5): [True: 0, False: 2.24k] ------------------ 7014| 0| case ARM::VQDMLSLslv4i16: ------------------ | Branch (7014:5): [True: 0, False: 2.24k] ------------------ 7015| 0| case ARM::VQRDMLAHslv4i16: ------------------ | Branch (7015:5): [True: 0, False: 2.24k] ------------------ 7016| 0| case ARM::VQRDMLAHslv8i16: ------------------ | Branch (7016:5): [True: 0, False: 2.24k] ------------------ 7017| 0| case ARM::VQRDMLSHslv4i16: ------------------ | Branch (7017:5): [True: 0, False: 2.24k] ------------------ 7018| 0| case ARM::VQRDMLSHslv8i16: { ------------------ | Branch (7018:5): [True: 0, False: 2.24k] ------------------ 7019| | // op: Vd 7020| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7021| 0| Value |= (op & UINT64_C(16)) << 18; 7022| 0| Value |= (op & UINT64_C(15)) << 12; 7023| | // op: Vn 7024| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7025| 0| Value |= (op & UINT64_C(15)) << 16; 7026| 0| Value |= (op & UINT64_C(16)) << 3; 7027| | // op: Vm 7028| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7029| 0| Value |= op & UINT64_C(7); 7030| | // op: lane 7031| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7032| 0| Value |= (op & UINT64_C(2)) << 4; 7033| 0| Value |= (op & UINT64_C(1)) << 3; 7034| 0| Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 7035| 0| break; 7036| 0| } 7037| 0| case ARM::VST1LNd8: { ------------------ | Branch (7037:5): [True: 0, False: 2.24k] ------------------ 7038| | // op: Vd 7039| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7040| 0| Value |= (op & UINT64_C(16)) << 18; 7041| 0| Value |= (op & UINT64_C(15)) << 12; 7042| | // op: Rn 7043| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7044| 0| Value |= (op & UINT64_C(15)) << 16; 7045| | // op: lane 7046| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7047| 0| Value |= (op & UINT64_C(7)) << 5; 7048| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7049| 0| break; 7050| 0| } 7051| 0| case ARM::VST3LNd32: ------------------ | Branch (7051:5): [True: 0, False: 2.24k] ------------------ 7052| 0| case ARM::VST3LNq32: { ------------------ | Branch (7052:5): [True: 0, False: 2.24k] ------------------ 7053| | // op: Vd 7054| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7055| 0| Value |= (op & UINT64_C(16)) << 18; 7056| 0| Value |= (op & UINT64_C(15)) << 12; 7057| | // op: Rn 7058| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7059| 0| Value |= (op & UINT64_C(15)) << 16; 7060| | // op: lane 7061| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7062| 0| Value |= (op & UINT64_C(1)) << 7; 7063| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7064| 0| break; 7065| 0| } 7066| 0| case ARM::VST3LNd16: ------------------ | Branch (7066:5): [True: 0, False: 2.24k] ------------------ 7067| 0| case ARM::VST3LNq16: { ------------------ | Branch (7067:5): [True: 0, False: 2.24k] ------------------ 7068| | // op: Vd 7069| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7070| 0| Value |= (op & UINT64_C(16)) << 18; 7071| 0| Value |= (op & UINT64_C(15)) << 12; 7072| | // op: Rn 7073| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7074| 0| Value |= (op & UINT64_C(15)) << 16; 7075| | // op: lane 7076| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7077| 0| Value |= (op & UINT64_C(3)) << 6; 7078| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7079| 0| break; 7080| 0| } 7081| 0| case ARM::VST3LNd8: { ------------------ | Branch (7081:5): [True: 0, False: 2.24k] ------------------ 7082| | // op: Vd 7083| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7084| 0| Value |= (op & UINT64_C(16)) << 18; 7085| 0| Value |= (op & UINT64_C(15)) << 12; 7086| | // op: Rn 7087| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7088| 0| Value |= (op & UINT64_C(15)) << 16; 7089| | // op: lane 7090| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7091| 0| Value |= (op & UINT64_C(7)) << 5; 7092| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7093| 0| break; 7094| 0| } 7095| 0| case ARM::VST1LNd16: { ------------------ | Branch (7095:5): [True: 0, False: 2.24k] ------------------ 7096| | // op: Vd 7097| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7098| 0| Value |= (op & UINT64_C(16)) << 18; 7099| 0| Value |= (op & UINT64_C(15)) << 12; 7100| | // op: Rn 7101| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7102| 0| Value |= (op & UINT64_C(15)) << 16; 7103| 0| Value |= op & UINT64_C(16); 7104| | // op: lane 7105| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7106| 0| Value |= (op & UINT64_C(3)) << 6; 7107| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7108| 0| break; 7109| 0| } 7110| 0| case ARM::VST2LNd32: ------------------ | Branch (7110:5): [True: 0, False: 2.24k] ------------------ 7111| 0| case ARM::VST2LNq32: { ------------------ | Branch (7111:5): [True: 0, False: 2.24k] ------------------ 7112| | // op: Vd 7113| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7114| 0| Value |= (op & UINT64_C(16)) << 18; 7115| 0| Value |= (op & UINT64_C(15)) << 12; 7116| | // op: Rn 7117| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7118| 0| Value |= (op & UINT64_C(15)) << 16; 7119| 0| Value |= op & UINT64_C(16); 7120| | // op: lane 7121| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7122| 0| Value |= (op & UINT64_C(1)) << 7; 7123| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7124| 0| break; 7125| 0| } 7126| 0| case ARM::VST2LNd16: ------------------ | Branch (7126:5): [True: 0, False: 2.24k] ------------------ 7127| 0| case ARM::VST2LNq16: { ------------------ | Branch (7127:5): [True: 0, False: 2.24k] ------------------ 7128| | // op: Vd 7129| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7130| 0| Value |= (op & UINT64_C(16)) << 18; 7131| 0| Value |= (op & UINT64_C(15)) << 12; 7132| | // op: Rn 7133| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7134| 0| Value |= (op & UINT64_C(15)) << 16; 7135| 0| Value |= op & UINT64_C(16); 7136| | // op: lane 7137| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7138| 0| Value |= (op & UINT64_C(3)) << 6; 7139| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7140| 0| break; 7141| 0| } 7142| 0| case ARM::VST2LNd8: { ------------------ | Branch (7142:5): [True: 0, False: 2.24k] ------------------ 7143| | // op: Vd 7144| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7145| 0| Value |= (op & UINT64_C(16)) << 18; 7146| 0| Value |= (op & UINT64_C(15)) << 12; 7147| | // op: Rn 7148| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7149| 0| Value |= (op & UINT64_C(15)) << 16; 7150| 0| Value |= op & UINT64_C(16); 7151| | // op: lane 7152| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7153| 0| Value |= (op & UINT64_C(7)) << 5; 7154| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7155| 0| break; 7156| 0| } 7157| 0| case ARM::VST4LNd16: ------------------ | Branch (7157:5): [True: 0, False: 2.24k] ------------------ 7158| 0| case ARM::VST4LNq16: { ------------------ | Branch (7158:5): [True: 0, False: 2.24k] ------------------ 7159| | // op: Vd 7160| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7161| 0| Value |= (op & UINT64_C(16)) << 18; 7162| 0| Value |= (op & UINT64_C(15)) << 12; 7163| | // op: Rn 7164| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7165| 0| Value |= (op & UINT64_C(15)) << 16; 7166| 0| Value |= op & UINT64_C(16); 7167| | // op: lane 7168| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7169| 0| Value |= (op & UINT64_C(3)) << 6; 7170| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7171| 0| break; 7172| 0| } 7173| 0| case ARM::VST4LNd8: { ------------------ | Branch (7173:5): [True: 0, False: 2.24k] ------------------ 7174| | // op: Vd 7175| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7176| 0| Value |= (op & UINT64_C(16)) << 18; 7177| 0| Value |= (op & UINT64_C(15)) << 12; 7178| | // op: Rn 7179| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7180| 0| Value |= (op & UINT64_C(15)) << 16; 7181| 0| Value |= op & UINT64_C(16); 7182| | // op: lane 7183| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7184| 0| Value |= (op & UINT64_C(7)) << 5; 7185| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7186| 0| break; 7187| 0| } 7188| 0| case ARM::VST1d16: ------------------ | Branch (7188:5): [True: 0, False: 2.24k] ------------------ 7189| 0| case ARM::VST1d16T: ------------------ | Branch (7189:5): [True: 0, False: 2.24k] ------------------ 7190| 0| case ARM::VST1d32: ------------------ | Branch (7190:5): [True: 0, False: 2.24k] ------------------ 7191| 0| case ARM::VST1d32T: ------------------ | Branch (7191:5): [True: 0, False: 2.24k] ------------------ 7192| 0| case ARM::VST1d64: ------------------ | Branch (7192:5): [True: 0, False: 2.24k] ------------------ 7193| 0| case ARM::VST1d64T: ------------------ | Branch (7193:5): [True: 0, False: 2.24k] ------------------ 7194| 0| case ARM::VST1d8: ------------------ | Branch (7194:5): [True: 0, False: 2.24k] ------------------ 7195| 0| case ARM::VST1d8T: ------------------ | Branch (7195:5): [True: 0, False: 2.24k] ------------------ 7196| 0| case ARM::VST3d16: ------------------ | Branch (7196:5): [True: 0, False: 2.24k] ------------------ 7197| 0| case ARM::VST3d32: ------------------ | Branch (7197:5): [True: 0, False: 2.24k] ------------------ 7198| 0| case ARM::VST3d8: ------------------ | Branch (7198:5): [True: 0, False: 2.24k] ------------------ 7199| 0| case ARM::VST3q16: ------------------ | Branch (7199:5): [True: 0, False: 2.24k] ------------------ 7200| 0| case ARM::VST3q32: ------------------ | Branch (7200:5): [True: 0, False: 2.24k] ------------------ 7201| 0| case ARM::VST3q8: { ------------------ | Branch (7201:5): [True: 0, False: 2.24k] ------------------ 7202| | // op: Vd 7203| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7204| 0| Value |= (op & UINT64_C(16)) << 18; 7205| 0| Value |= (op & UINT64_C(15)) << 12; 7206| | // op: Rn 7207| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7208| 0| Value |= (op & UINT64_C(15)) << 16; 7209| 0| Value |= op & UINT64_C(16); 7210| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7211| 0| break; 7212| 0| } 7213| 0| case ARM::VST4LNd32: ------------------ | Branch (7213:5): [True: 0, False: 2.24k] ------------------ 7214| 0| case ARM::VST4LNq32: { ------------------ | Branch (7214:5): [True: 0, False: 2.24k] ------------------ 7215| | // op: Vd 7216| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7217| 0| Value |= (op & UINT64_C(16)) << 18; 7218| 0| Value |= (op & UINT64_C(15)) << 12; 7219| | // op: Rn 7220| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7221| 0| Value |= (op & UINT64_C(15)) << 16; 7222| 0| Value |= op & UINT64_C(48); 7223| | // op: lane 7224| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7225| 0| Value |= (op & UINT64_C(1)) << 7; 7226| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7227| 0| break; 7228| 0| } 7229| 0| case ARM::VST1d16Q: ------------------ | Branch (7229:5): [True: 0, False: 2.24k] ------------------ 7230| 0| case ARM::VST1d32Q: ------------------ | Branch (7230:5): [True: 0, False: 2.24k] ------------------ 7231| 0| case ARM::VST1d64Q: ------------------ | Branch (7231:5): [True: 0, False: 2.24k] ------------------ 7232| 0| case ARM::VST1d8Q: ------------------ | Branch (7232:5): [True: 0, False: 2.24k] ------------------ 7233| 0| case ARM::VST1q16: ------------------ | Branch (7233:5): [True: 0, False: 2.24k] ------------------ 7234| 0| case ARM::VST1q32: ------------------ | Branch (7234:5): [True: 0, False: 2.24k] ------------------ 7235| 0| case ARM::VST1q64: ------------------ | Branch (7235:5): [True: 0, False: 2.24k] ------------------ 7236| 0| case ARM::VST1q8: ------------------ | Branch (7236:5): [True: 0, False: 2.24k] ------------------ 7237| 0| case ARM::VST2b16: ------------------ | Branch (7237:5): [True: 0, False: 2.24k] ------------------ 7238| 0| case ARM::VST2b32: ------------------ | Branch (7238:5): [True: 0, False: 2.24k] ------------------ 7239| 0| case ARM::VST2b8: ------------------ | Branch (7239:5): [True: 0, False: 2.24k] ------------------ 7240| 0| case ARM::VST2d16: ------------------ | Branch (7240:5): [True: 0, False: 2.24k] ------------------ 7241| 0| case ARM::VST2d32: ------------------ | Branch (7241:5): [True: 0, False: 2.24k] ------------------ 7242| 0| case ARM::VST2d8: ------------------ | Branch (7242:5): [True: 0, False: 2.24k] ------------------ 7243| 0| case ARM::VST2q16: ------------------ | Branch (7243:5): [True: 0, False: 2.24k] ------------------ 7244| 0| case ARM::VST2q32: ------------------ | Branch (7244:5): [True: 0, False: 2.24k] ------------------ 7245| 0| case ARM::VST2q8: ------------------ | Branch (7245:5): [True: 0, False: 2.24k] ------------------ 7246| 0| case ARM::VST4d16: ------------------ | Branch (7246:5): [True: 0, False: 2.24k] ------------------ 7247| 0| case ARM::VST4d32: ------------------ | Branch (7247:5): [True: 0, False: 2.24k] ------------------ 7248| 0| case ARM::VST4d8: ------------------ | Branch (7248:5): [True: 0, False: 2.24k] ------------------ 7249| 0| case ARM::VST4q16: ------------------ | Branch (7249:5): [True: 0, False: 2.24k] ------------------ 7250| 0| case ARM::VST4q32: ------------------ | Branch (7250:5): [True: 0, False: 2.24k] ------------------ 7251| 0| case ARM::VST4q8: { ------------------ | Branch (7251:5): [True: 0, False: 2.24k] ------------------ 7252| | // op: Vd 7253| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7254| 0| Value |= (op & UINT64_C(16)) << 18; 7255| 0| Value |= (op & UINT64_C(15)) << 12; 7256| | // op: Rn 7257| 0| op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7258| 0| Value |= (op & UINT64_C(15)) << 16; 7259| 0| Value |= op & UINT64_C(48); 7260| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7261| 0| break; 7262| 0| } 7263| 0| case ARM::VST1LNd32: { ------------------ | Branch (7263:5): [True: 0, False: 2.24k] ------------------ 7264| | // op: Vd 7265| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7266| 0| Value |= (op & UINT64_C(16)) << 18; 7267| 0| Value |= (op & UINT64_C(15)) << 12; 7268| | // op: Rn 7269| 0| op = getAddrMode6OneLane32AddressOpValue(MI, 0, Fixups, STI); 7270| 0| Value |= (op & UINT64_C(15)) << 16; 7271| 0| Value |= op & UINT64_C(48); 7272| | // op: lane 7273| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7274| 0| Value |= (op & UINT64_C(1)) << 7; 7275| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7276| 0| break; 7277| 0| } 7278| 0| case ARM::VST1d16wb_fixed: ------------------ | Branch (7278:5): [True: 0, False: 2.24k] ------------------ 7279| 0| case ARM::VST1d32wb_fixed: ------------------ | Branch (7279:5): [True: 0, False: 2.24k] ------------------ 7280| 0| case ARM::VST1d64wb_fixed: ------------------ | Branch (7280:5): [True: 0, False: 2.24k] ------------------ 7281| 0| case ARM::VST1d8wb_fixed: { ------------------ | Branch (7281:5): [True: 0, False: 2.24k] ------------------ 7282| | // op: Vd 7283| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7284| 0| Value |= (op & UINT64_C(16)) << 18; 7285| 0| Value |= (op & UINT64_C(15)) << 12; 7286| | // op: Rn 7287| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7288| 0| Value |= (op & UINT64_C(15)) << 16; 7289| 0| Value |= op & UINT64_C(16); 7290| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7291| 0| break; 7292| 0| } 7293| 0| case ARM::VST1d16Qwb_fixed: ------------------ | Branch (7293:5): [True: 0, False: 2.24k] ------------------ 7294| 0| case ARM::VST1d16Twb_fixed: ------------------ | Branch (7294:5): [True: 0, False: 2.24k] ------------------ 7295| 0| case ARM::VST1d32Qwb_fixed: ------------------ | Branch (7295:5): [True: 0, False: 2.24k] ------------------ 7296| 0| case ARM::VST1d32Twb_fixed: ------------------ | Branch (7296:5): [True: 0, False: 2.24k] ------------------ 7297| 0| case ARM::VST1d64Qwb_fixed: ------------------ | Branch (7297:5): [True: 0, False: 2.24k] ------------------ 7298| 0| case ARM::VST1d64Twb_fixed: ------------------ | Branch (7298:5): [True: 0, False: 2.24k] ------------------ 7299| 0| case ARM::VST1d8Qwb_fixed: ------------------ | Branch (7299:5): [True: 0, False: 2.24k] ------------------ 7300| 0| case ARM::VST1d8Twb_fixed: ------------------ | Branch (7300:5): [True: 0, False: 2.24k] ------------------ 7301| 0| case ARM::VST1q16wb_fixed: ------------------ | Branch (7301:5): [True: 0, False: 2.24k] ------------------ 7302| 0| case ARM::VST1q32wb_fixed: ------------------ | Branch (7302:5): [True: 0, False: 2.24k] ------------------ 7303| 0| case ARM::VST1q64wb_fixed: ------------------ | Branch (7303:5): [True: 0, False: 2.24k] ------------------ 7304| 0| case ARM::VST1q8wb_fixed: ------------------ | Branch (7304:5): [True: 0, False: 2.24k] ------------------ 7305| 0| case ARM::VST2b16wb_fixed: ------------------ | Branch (7305:5): [True: 0, False: 2.24k] ------------------ 7306| 0| case ARM::VST2b32wb_fixed: ------------------ | Branch (7306:5): [True: 0, False: 2.24k] ------------------ 7307| 0| case ARM::VST2b8wb_fixed: ------------------ | Branch (7307:5): [True: 0, False: 2.24k] ------------------ 7308| 0| case ARM::VST2d16wb_fixed: ------------------ | Branch (7308:5): [True: 0, False: 2.24k] ------------------ 7309| 0| case ARM::VST2d32wb_fixed: ------------------ | Branch (7309:5): [True: 0, False: 2.24k] ------------------ 7310| 0| case ARM::VST2d8wb_fixed: ------------------ | Branch (7310:5): [True: 0, False: 2.24k] ------------------ 7311| 0| case ARM::VST2q16wb_fixed: ------------------ | Branch (7311:5): [True: 0, False: 2.24k] ------------------ 7312| 0| case ARM::VST2q32wb_fixed: ------------------ | Branch (7312:5): [True: 0, False: 2.24k] ------------------ 7313| 0| case ARM::VST2q8wb_fixed: { ------------------ | Branch (7313:5): [True: 0, False: 2.24k] ------------------ 7314| | // op: Vd 7315| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7316| 0| Value |= (op & UINT64_C(16)) << 18; 7317| 0| Value |= (op & UINT64_C(15)) << 12; 7318| | // op: Rn 7319| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7320| 0| Value |= (op & UINT64_C(15)) << 16; 7321| 0| Value |= op & UINT64_C(48); 7322| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7323| 0| break; 7324| 0| } 7325| 0| case ARM::VST1LNd8_UPD: { ------------------ | Branch (7325:5): [True: 0, False: 2.24k] ------------------ 7326| | // op: Vd 7327| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7328| 0| Value |= (op & UINT64_C(16)) << 18; 7329| 0| Value |= (op & UINT64_C(15)) << 12; 7330| | // op: Rn 7331| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7332| 0| Value |= (op & UINT64_C(15)) << 16; 7333| | // op: Rm 7334| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7335| 0| Value |= op & UINT64_C(15); 7336| | // op: lane 7337| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7338| 0| Value |= (op & UINT64_C(7)) << 5; 7339| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7340| 0| break; 7341| 0| } 7342| 0| case ARM::VST3LNd32_UPD: ------------------ | Branch (7342:5): [True: 0, False: 2.24k] ------------------ 7343| 0| case ARM::VST3LNq32_UPD: { ------------------ | Branch (7343:5): [True: 0, False: 2.24k] ------------------ 7344| | // op: Vd 7345| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7346| 0| Value |= (op & UINT64_C(16)) << 18; 7347| 0| Value |= (op & UINT64_C(15)) << 12; 7348| | // op: Rn 7349| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7350| 0| Value |= (op & UINT64_C(15)) << 16; 7351| | // op: Rm 7352| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7353| 0| Value |= op & UINT64_C(15); 7354| | // op: lane 7355| 0| op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7356| 0| Value |= (op & UINT64_C(1)) << 7; 7357| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7358| 0| break; 7359| 0| } 7360| 0| case ARM::VST3LNd16_UPD: ------------------ | Branch (7360:5): [True: 0, False: 2.24k] ------------------ 7361| 0| case ARM::VST3LNq16_UPD: { ------------------ | Branch (7361:5): [True: 0, False: 2.24k] ------------------ 7362| | // op: Vd 7363| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7364| 0| Value |= (op & UINT64_C(16)) << 18; 7365| 0| Value |= (op & UINT64_C(15)) << 12; 7366| | // op: Rn 7367| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7368| 0| Value |= (op & UINT64_C(15)) << 16; 7369| | // op: Rm 7370| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7371| 0| Value |= op & UINT64_C(15); 7372| | // op: lane 7373| 0| op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7374| 0| Value |= (op & UINT64_C(3)) << 6; 7375| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7376| 0| break; 7377| 0| } 7378| 0| case ARM::VST3LNd8_UPD: { ------------------ | Branch (7378:5): [True: 0, False: 2.24k] ------------------ 7379| | // op: Vd 7380| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7381| 0| Value |= (op & UINT64_C(16)) << 18; 7382| 0| Value |= (op & UINT64_C(15)) << 12; 7383| | // op: Rn 7384| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7385| 0| Value |= (op & UINT64_C(15)) << 16; 7386| | // op: Rm 7387| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7388| 0| Value |= op & UINT64_C(15); 7389| | // op: lane 7390| 0| op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7391| 0| Value |= (op & UINT64_C(7)) << 5; 7392| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7393| 0| break; 7394| 0| } 7395| 0| case ARM::VST1LNd16_UPD: { ------------------ | Branch (7395:5): [True: 0, False: 2.24k] ------------------ 7396| | // op: Vd 7397| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7398| 0| Value |= (op & UINT64_C(16)) << 18; 7399| 0| Value |= (op & UINT64_C(15)) << 12; 7400| | // op: Rn 7401| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7402| 0| Value |= (op & UINT64_C(15)) << 16; 7403| 0| Value |= op & UINT64_C(16); 7404| | // op: Rm 7405| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7406| 0| Value |= op & UINT64_C(15); 7407| | // op: lane 7408| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7409| 0| Value |= (op & UINT64_C(3)) << 6; 7410| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7411| 0| break; 7412| 0| } 7413| 0| case ARM::VST2LNd32_UPD: ------------------ | Branch (7413:5): [True: 0, False: 2.24k] ------------------ 7414| 0| case ARM::VST2LNq32_UPD: { ------------------ | Branch (7414:5): [True: 0, False: 2.24k] ------------------ 7415| | // op: Vd 7416| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7417| 0| Value |= (op & UINT64_C(16)) << 18; 7418| 0| Value |= (op & UINT64_C(15)) << 12; 7419| | // op: Rn 7420| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7421| 0| Value |= (op & UINT64_C(15)) << 16; 7422| 0| Value |= op & UINT64_C(16); 7423| | // op: Rm 7424| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7425| 0| Value |= op & UINT64_C(15); 7426| | // op: lane 7427| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7428| 0| Value |= (op & UINT64_C(1)) << 7; 7429| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7430| 0| break; 7431| 0| } 7432| 0| case ARM::VST2LNd16_UPD: ------------------ | Branch (7432:5): [True: 0, False: 2.24k] ------------------ 7433| 0| case ARM::VST2LNq16_UPD: { ------------------ | Branch (7433:5): [True: 0, False: 2.24k] ------------------ 7434| | // op: Vd 7435| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7436| 0| Value |= (op & UINT64_C(16)) << 18; 7437| 0| Value |= (op & UINT64_C(15)) << 12; 7438| | // op: Rn 7439| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7440| 0| Value |= (op & UINT64_C(15)) << 16; 7441| 0| Value |= op & UINT64_C(16); 7442| | // op: Rm 7443| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7444| 0| Value |= op & UINT64_C(15); 7445| | // op: lane 7446| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7447| 0| Value |= (op & UINT64_C(3)) << 6; 7448| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7449| 0| break; 7450| 0| } 7451| 0| case ARM::VST2LNd8_UPD: { ------------------ | Branch (7451:5): [True: 0, False: 2.24k] ------------------ 7452| | // op: Vd 7453| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7454| 0| Value |= (op & UINT64_C(16)) << 18; 7455| 0| Value |= (op & UINT64_C(15)) << 12; 7456| | // op: Rn 7457| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7458| 0| Value |= (op & UINT64_C(15)) << 16; 7459| 0| Value |= op & UINT64_C(16); 7460| | // op: Rm 7461| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7462| 0| Value |= op & UINT64_C(15); 7463| | // op: lane 7464| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7465| 0| Value |= (op & UINT64_C(7)) << 5; 7466| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7467| 0| break; 7468| 0| } 7469| 0| case ARM::VST4LNd16_UPD: ------------------ | Branch (7469:5): [True: 0, False: 2.24k] ------------------ 7470| 0| case ARM::VST4LNq16_UPD: { ------------------ | Branch (7470:5): [True: 0, False: 2.24k] ------------------ 7471| | // op: Vd 7472| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7473| 0| Value |= (op & UINT64_C(16)) << 18; 7474| 0| Value |= (op & UINT64_C(15)) << 12; 7475| | // op: Rn 7476| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7477| 0| Value |= (op & UINT64_C(15)) << 16; 7478| 0| Value |= op & UINT64_C(16); 7479| | // op: Rm 7480| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7481| 0| Value |= op & UINT64_C(15); 7482| | // op: lane 7483| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7484| 0| Value |= (op & UINT64_C(3)) << 6; 7485| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7486| 0| break; 7487| 0| } 7488| 0| case ARM::VST4LNd8_UPD: { ------------------ | Branch (7488:5): [True: 0, False: 2.24k] ------------------ 7489| | // op: Vd 7490| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7491| 0| Value |= (op & UINT64_C(16)) << 18; 7492| 0| Value |= (op & UINT64_C(15)) << 12; 7493| | // op: Rn 7494| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7495| 0| Value |= (op & UINT64_C(15)) << 16; 7496| 0| Value |= op & UINT64_C(16); 7497| | // op: Rm 7498| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7499| 0| Value |= op & UINT64_C(15); 7500| | // op: lane 7501| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7502| 0| Value |= (op & UINT64_C(7)) << 5; 7503| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7504| 0| break; 7505| 0| } 7506| 0| case ARM::VST3d16_UPD: ------------------ | Branch (7506:5): [True: 0, False: 2.24k] ------------------ 7507| 0| case ARM::VST3d32_UPD: ------------------ | Branch (7507:5): [True: 0, False: 2.24k] ------------------ 7508| 0| case ARM::VST3d8_UPD: ------------------ | Branch (7508:5): [True: 0, False: 2.24k] ------------------ 7509| 0| case ARM::VST3q16_UPD: ------------------ | Branch (7509:5): [True: 0, False: 2.24k] ------------------ 7510| 0| case ARM::VST3q32_UPD: ------------------ | Branch (7510:5): [True: 0, False: 2.24k] ------------------ 7511| 0| case ARM::VST3q8_UPD: { ------------------ | Branch (7511:5): [True: 0, False: 2.24k] ------------------ 7512| | // op: Vd 7513| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7514| 0| Value |= (op & UINT64_C(16)) << 18; 7515| 0| Value |= (op & UINT64_C(15)) << 12; 7516| | // op: Rn 7517| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7518| 0| Value |= (op & UINT64_C(15)) << 16; 7519| 0| Value |= op & UINT64_C(16); 7520| | // op: Rm 7521| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7522| 0| Value |= op & UINT64_C(15); 7523| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7524| 0| break; 7525| 0| } 7526| 0| case ARM::VST1d16wb_register: ------------------ | Branch (7526:5): [True: 0, False: 2.24k] ------------------ 7527| 0| case ARM::VST1d32wb_register: ------------------ | Branch (7527:5): [True: 0, False: 2.24k] ------------------ 7528| 0| case ARM::VST1d64wb_register: ------------------ | Branch (7528:5): [True: 0, False: 2.24k] ------------------ 7529| 0| case ARM::VST1d8wb_register: { ------------------ | Branch (7529:5): [True: 0, False: 2.24k] ------------------ 7530| | // op: Vd 7531| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7532| 0| Value |= (op & UINT64_C(16)) << 18; 7533| 0| Value |= (op & UINT64_C(15)) << 12; 7534| | // op: Rn 7535| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7536| 0| Value |= (op & UINT64_C(15)) << 16; 7537| 0| Value |= op & UINT64_C(16); 7538| | // op: Rm 7539| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7540| 0| Value |= op & UINT64_C(15); 7541| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7542| 0| break; 7543| 0| } 7544| 0| case ARM::VST4LNd32_UPD: ------------------ | Branch (7544:5): [True: 0, False: 2.24k] ------------------ 7545| 0| case ARM::VST4LNq32_UPD: { ------------------ | Branch (7545:5): [True: 0, False: 2.24k] ------------------ 7546| | // op: Vd 7547| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7548| 0| Value |= (op & UINT64_C(16)) << 18; 7549| 0| Value |= (op & UINT64_C(15)) << 12; 7550| | // op: Rn 7551| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7552| 0| Value |= (op & UINT64_C(15)) << 16; 7553| 0| Value |= op & UINT64_C(48); 7554| | // op: Rm 7555| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7556| 0| Value |= op & UINT64_C(15); 7557| | // op: lane 7558| 0| op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7559| 0| Value |= (op & UINT64_C(1)) << 7; 7560| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7561| 0| break; 7562| 0| } 7563| 0| case ARM::VST4d16_UPD: ------------------ | Branch (7563:5): [True: 0, False: 2.24k] ------------------ 7564| 0| case ARM::VST4d32_UPD: ------------------ | Branch (7564:5): [True: 0, False: 2.24k] ------------------ 7565| 0| case ARM::VST4d8_UPD: ------------------ | Branch (7565:5): [True: 0, False: 2.24k] ------------------ 7566| 0| case ARM::VST4q16_UPD: ------------------ | Branch (7566:5): [True: 0, False: 2.24k] ------------------ 7567| 0| case ARM::VST4q32_UPD: ------------------ | Branch (7567:5): [True: 0, False: 2.24k] ------------------ 7568| 0| case ARM::VST4q8_UPD: { ------------------ | Branch (7568:5): [True: 0, False: 2.24k] ------------------ 7569| | // op: Vd 7570| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7571| 0| Value |= (op & UINT64_C(16)) << 18; 7572| 0| Value |= (op & UINT64_C(15)) << 12; 7573| | // op: Rn 7574| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7575| 0| Value |= (op & UINT64_C(15)) << 16; 7576| 0| Value |= op & UINT64_C(48); 7577| | // op: Rm 7578| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7579| 0| Value |= op & UINT64_C(15); 7580| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7581| 0| break; 7582| 0| } 7583| 0| case ARM::VST1d16Qwb_register: ------------------ | Branch (7583:5): [True: 0, False: 2.24k] ------------------ 7584| 0| case ARM::VST1d16Twb_register: ------------------ | Branch (7584:5): [True: 0, False: 2.24k] ------------------ 7585| 0| case ARM::VST1d32Qwb_register: ------------------ | Branch (7585:5): [True: 0, False: 2.24k] ------------------ 7586| 0| case ARM::VST1d32Twb_register: ------------------ | Branch (7586:5): [True: 0, False: 2.24k] ------------------ 7587| 0| case ARM::VST1d64Qwb_register: ------------------ | Branch (7587:5): [True: 0, False: 2.24k] ------------------ 7588| 0| case ARM::VST1d64Twb_register: ------------------ | Branch (7588:5): [True: 0, False: 2.24k] ------------------ 7589| 0| case ARM::VST1d8Qwb_register: ------------------ | Branch (7589:5): [True: 0, False: 2.24k] ------------------ 7590| 0| case ARM::VST1d8Twb_register: ------------------ | Branch (7590:5): [True: 0, False: 2.24k] ------------------ 7591| 0| case ARM::VST1q16wb_register: ------------------ | Branch (7591:5): [True: 0, False: 2.24k] ------------------ 7592| 0| case ARM::VST1q32wb_register: ------------------ | Branch (7592:5): [True: 0, False: 2.24k] ------------------ 7593| 0| case ARM::VST1q64wb_register: ------------------ | Branch (7593:5): [True: 0, False: 2.24k] ------------------ 7594| 0| case ARM::VST1q8wb_register: ------------------ | Branch (7594:5): [True: 0, False: 2.24k] ------------------ 7595| 0| case ARM::VST2b16wb_register: ------------------ | Branch (7595:5): [True: 0, False: 2.24k] ------------------ 7596| 0| case ARM::VST2b32wb_register: ------------------ | Branch (7596:5): [True: 0, False: 2.24k] ------------------ 7597| 0| case ARM::VST2b8wb_register: ------------------ | Branch (7597:5): [True: 0, False: 2.24k] ------------------ 7598| 0| case ARM::VST2d16wb_register: ------------------ | Branch (7598:5): [True: 0, False: 2.24k] ------------------ 7599| 0| case ARM::VST2d32wb_register: ------------------ | Branch (7599:5): [True: 0, False: 2.24k] ------------------ 7600| 0| case ARM::VST2d8wb_register: ------------------ | Branch (7600:5): [True: 0, False: 2.24k] ------------------ 7601| 0| case ARM::VST2q16wb_register: ------------------ | Branch (7601:5): [True: 0, False: 2.24k] ------------------ 7602| 0| case ARM::VST2q32wb_register: ------------------ | Branch (7602:5): [True: 0, False: 2.24k] ------------------ 7603| 0| case ARM::VST2q8wb_register: { ------------------ | Branch (7603:5): [True: 0, False: 2.24k] ------------------ 7604| | // op: Vd 7605| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7606| 0| Value |= (op & UINT64_C(16)) << 18; 7607| 0| Value |= (op & UINT64_C(15)) << 12; 7608| | // op: Rn 7609| 0| op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7610| 0| Value |= (op & UINT64_C(15)) << 16; 7611| 0| Value |= op & UINT64_C(48); 7612| | // op: Rm 7613| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7614| 0| Value |= op & UINT64_C(15); 7615| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7616| 0| break; 7617| 0| } 7618| 0| case ARM::VST1LNd32_UPD: { ------------------ | Branch (7618:5): [True: 0, False: 2.24k] ------------------ 7619| | // op: Vd 7620| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7621| 0| Value |= (op & UINT64_C(16)) << 18; 7622| 0| Value |= (op & UINT64_C(15)) << 12; 7623| | // op: Rn 7624| 0| op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 7625| 0| Value |= (op & UINT64_C(15)) << 16; 7626| 0| Value |= op & UINT64_C(48); 7627| | // op: Rm 7628| 0| op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7629| 0| Value |= op & UINT64_C(15); 7630| | // op: lane 7631| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7632| 0| Value |= (op & UINT64_C(1)) << 7; 7633| 0| Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7634| 0| break; 7635| 0| } 7636| 0| case ARM::LDC2L_OFFSET: ------------------ | Branch (7636:5): [True: 0, False: 2.24k] ------------------ 7637| 0| case ARM::LDC2L_PRE: ------------------ | Branch (7637:5): [True: 0, False: 2.24k] ------------------ 7638| 0| case ARM::LDC2_OFFSET: ------------------ | Branch (7638:5): [True: 0, False: 2.24k] ------------------ 7639| 0| case ARM::LDC2_PRE: ------------------ | Branch (7639:5): [True: 0, False: 2.24k] ------------------ 7640| 0| case ARM::STC2L_OFFSET: ------------------ | Branch (7640:5): [True: 0, False: 2.24k] ------------------ 7641| 0| case ARM::STC2L_PRE: ------------------ | Branch (7641:5): [True: 0, False: 2.24k] ------------------ 7642| 0| case ARM::STC2_OFFSET: ------------------ | Branch (7642:5): [True: 0, False: 2.24k] ------------------ 7643| 0| case ARM::STC2_PRE: ------------------ | Branch (7643:5): [True: 0, False: 2.24k] ------------------ 7644| 0| case ARM::t2LDC2L_OFFSET: ------------------ | Branch (7644:5): [True: 0, False: 2.24k] ------------------ 7645| 0| case ARM::t2LDC2L_PRE: ------------------ | Branch (7645:5): [True: 0, False: 2.24k] ------------------ 7646| 0| case ARM::t2LDC2_OFFSET: ------------------ | Branch (7646:5): [True: 0, False: 2.24k] ------------------ 7647| 0| case ARM::t2LDC2_PRE: ------------------ | Branch (7647:5): [True: 0, False: 2.24k] ------------------ 7648| 0| case ARM::t2LDCL_OFFSET: ------------------ | Branch (7648:5): [True: 0, False: 2.24k] ------------------ 7649| 0| case ARM::t2LDCL_PRE: ------------------ | Branch (7649:5): [True: 0, False: 2.24k] ------------------ 7650| 0| case ARM::t2LDC_OFFSET: ------------------ | Branch (7650:5): [True: 0, False: 2.24k] ------------------ 7651| 0| case ARM::t2LDC_PRE: ------------------ | Branch (7651:5): [True: 0, False: 2.24k] ------------------ 7652| 0| case ARM::t2STC2L_OFFSET: ------------------ | Branch (7652:5): [True: 0, False: 2.24k] ------------------ 7653| 0| case ARM::t2STC2L_PRE: ------------------ | Branch (7653:5): [True: 0, False: 2.24k] ------------------ 7654| 0| case ARM::t2STC2_OFFSET: ------------------ | Branch (7654:5): [True: 0, False: 2.24k] ------------------ 7655| 0| case ARM::t2STC2_PRE: ------------------ | Branch (7655:5): [True: 0, False: 2.24k] ------------------ 7656| 0| case ARM::t2STCL_OFFSET: ------------------ | Branch (7656:5): [True: 0, False: 2.24k] ------------------ 7657| 0| case ARM::t2STCL_PRE: ------------------ | Branch (7657:5): [True: 0, False: 2.24k] ------------------ 7658| 0| case ARM::t2STC_OFFSET: ------------------ | Branch (7658:5): [True: 0, False: 2.24k] ------------------ 7659| 0| case ARM::t2STC_PRE: { ------------------ | Branch (7659:5): [True: 0, False: 2.24k] ------------------ 7660| | // op: addr 7661| 0| op = getAddrMode5OpValue(MI, 2, Fixups, STI); 7662| 0| Value |= (op & UINT64_C(256)) << 15; 7663| 0| Value |= (op & UINT64_C(7680)) << 7; 7664| 0| Value |= op & UINT64_C(255); 7665| | // op: cop 7666| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7667| 0| Value |= (op & UINT64_C(15)) << 8; 7668| | // op: CRd 7669| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7670| 0| Value |= (op & UINT64_C(15)) << 12; 7671| 0| break; 7672| 0| } 7673| 0| case ARM::t2PLDWi12: ------------------ | Branch (7673:5): [True: 0, False: 2.24k] ------------------ 7674| 0| case ARM::t2PLDi12: ------------------ | Branch (7674:5): [True: 0, False: 2.24k] ------------------ 7675| 0| case ARM::t2PLIi12: { ------------------ | Branch (7675:5): [True: 0, False: 2.24k] ------------------ 7676| | // op: addr 7677| 0| op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 7678| 0| Value |= (op & UINT64_C(122880)) << 3; 7679| 0| Value |= op & UINT64_C(4095); 7680| 0| break; 7681| 0| } 7682| 0| case ARM::PLDWi12: ------------------ | Branch (7682:5): [True: 0, False: 2.24k] ------------------ 7683| 0| case ARM::PLDi12: ------------------ | Branch (7683:5): [True: 0, False: 2.24k] ------------------ 7684| 0| case ARM::PLIi12: { ------------------ | Branch (7684:5): [True: 0, False: 2.24k] ------------------ 7685| | // op: addr 7686| 0| op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 7687| 0| Value |= (op & UINT64_C(4096)) << 11; 7688| 0| Value |= (op & UINT64_C(122880)) << 3; 7689| 0| Value |= op & UINT64_C(4095); 7690| 0| break; 7691| 0| } 7692| 13| case ARM::t2PLDpci: ------------------ | Branch (7692:5): [True: 13, False: 2.22k] ------------------ 7693| 13| case ARM::t2PLIpci: { ------------------ | Branch (7693:5): [True: 0, False: 2.24k] ------------------ 7694| | // op: addr 7695| 13| op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 7696| 13| Value |= (op & UINT64_C(4096)) << 11; 7697| 13| Value |= op & UINT64_C(4095); 7698| 13| break; 7699| 13| } 7700| 0| case ARM::t2LDAEXB: ------------------ | Branch (7700:5): [True: 0, False: 2.24k] ------------------ 7701| 0| case ARM::t2LDAEXH: ------------------ | Branch (7701:5): [True: 0, False: 2.24k] ------------------ 7702| 0| case ARM::t2LDREXB: ------------------ | Branch (7702:5): [True: 0, False: 2.24k] ------------------ 7703| 0| case ARM::t2LDREXH: { ------------------ | Branch (7703:5): [True: 0, False: 2.24k] ------------------ 7704| | // op: addr 7705| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7706| 0| Value |= (op & UINT64_C(15)) << 16; 7707| | // op: Rt 7708| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7709| 0| Value |= (op & UINT64_C(15)) << 12; 7710| 0| break; 7711| 0| } 7712| 0| case ARM::t2LDAEXD: ------------------ | Branch (7712:5): [True: 0, False: 2.24k] ------------------ 7713| 0| case ARM::t2LDREXD: { ------------------ | Branch (7713:5): [True: 0, False: 2.24k] ------------------ 7714| | // op: addr 7715| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7716| 0| Value |= (op & UINT64_C(15)) << 16; 7717| | // op: Rt 7718| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7719| 0| Value |= (op & UINT64_C(15)) << 12; 7720| | // op: Rt2 7721| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7722| 0| Value |= (op & UINT64_C(15)) << 8; 7723| 0| break; 7724| 0| } 7725| 0| case ARM::t2PLDWi8: ------------------ | Branch (7725:5): [True: 0, False: 2.24k] ------------------ 7726| 0| case ARM::t2PLDi8: ------------------ | Branch (7726:5): [True: 0, False: 2.24k] ------------------ 7727| 0| case ARM::t2PLIi8: { ------------------ | Branch (7727:5): [True: 0, False: 2.24k] ------------------ 7728| | // op: addr 7729| 0| op = getT2AddrModeImm8OpValue(MI, 0, Fixups, STI); 7730| 0| Value |= (op & UINT64_C(7680)) << 7; 7731| 0| Value |= op & UINT64_C(255); 7732| 0| break; 7733| 0| } 7734| 0| case ARM::t2PLDWs: ------------------ | Branch (7734:5): [True: 0, False: 2.24k] ------------------ 7735| 0| case ARM::t2PLDs: ------------------ | Branch (7735:5): [True: 0, False: 2.24k] ------------------ 7736| 0| case ARM::t2PLIs: { ------------------ | Branch (7736:5): [True: 0, False: 2.24k] ------------------ 7737| | // op: addr 7738| 0| op = getT2AddrModeSORegOpValue(MI, 0, Fixups, STI); 7739| 0| Value |= (op & UINT64_C(960)) << 10; 7740| 0| Value |= (op & UINT64_C(3)) << 4; 7741| 0| Value |= (op & UINT64_C(60)) >> 2; 7742| 0| break; 7743| 0| } 7744| 0| case ARM::t2MSRbanked: { ------------------ | Branch (7744:5): [True: 0, False: 2.24k] ------------------ 7745| | // op: banked 7746| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7747| 0| Value |= (op & UINT64_C(32)) << 15; 7748| 0| Value |= (op & UINT64_C(15)) << 8; 7749| 0| Value |= op & UINT64_C(16); 7750| | // op: Rn 7751| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7752| 0| Value |= (op & UINT64_C(15)) << 16; 7753| 0| break; 7754| 0| } 7755| 0| case ARM::t2MRSbanked: { ------------------ | Branch (7755:5): [True: 0, False: 2.24k] ------------------ 7756| | // op: banked 7757| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7758| 0| Value |= (op & UINT64_C(32)) << 15; 7759| 0| Value |= (op & UINT64_C(15)) << 16; 7760| 0| Value |= op & UINT64_C(16); 7761| | // op: Rd 7762| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7763| 0| Value |= (op & UINT64_C(15)) << 8; 7764| 0| break; 7765| 0| } 7766| 0| case ARM::t2IT: { ------------------ | Branch (7766:5): [True: 0, False: 2.24k] ------------------ 7767| | // op: cc 7768| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7769| 0| Value |= (op & UINT64_C(15)) << 4; 7770| | // op: mask 7771| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7772| 0| Value |= op & UINT64_C(15); 7773| 0| break; 7774| 0| } 7775| 0| case ARM::tADDrSPi: { ------------------ | Branch (7775:5): [True: 0, False: 2.24k] ------------------ 7776| | // op: dst 7777| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7778| 0| Value |= (op & UINT64_C(7)) << 8; 7779| | // op: imm 7780| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7781| 0| Value |= op & UINT64_C(255); 7782| 0| break; 7783| 0| } 7784| 0| case ARM::BX: { ------------------ | Branch (7784:5): [True: 0, False: 2.24k] ------------------ 7785| | // op: dst 7786| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7787| 0| Value |= op & UINT64_C(15); 7788| 0| break; 7789| 0| } 7790| 0| case ARM::tPICADD: { ------------------ | Branch (7790:5): [True: 0, False: 2.24k] ------------------ 7791| | // op: dst 7792| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7793| 0| Value |= op & UINT64_C(7); 7794| 0| break; 7795| 0| } 7796| 0| case ARM::tSETEND: { ------------------ | Branch (7796:5): [True: 0, False: 2.24k] ------------------ 7797| | // op: end 7798| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7799| 0| Value |= (op & UINT64_C(1)) << 3; 7800| 0| break; 7801| 0| } 7802| 0| case ARM::SETEND: { ------------------ | Branch (7802:5): [True: 0, False: 2.24k] ------------------ 7803| | // op: end 7804| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7805| 0| Value |= (op & UINT64_C(1)) << 9; 7806| 0| break; 7807| 0| } 7808| 0| case ARM::BL: { ------------------ | Branch (7808:5): [True: 0, False: 2.24k] ------------------ 7809| | // op: func 7810| 0| op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 7811| 0| Value |= op & UINT64_C(16777215); 7812| 0| break; 7813| 0| } 7814| 0| case ARM::t2BXJ: { ------------------ | Branch (7814:5): [True: 0, False: 2.24k] ------------------ 7815| | // op: func 7816| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7817| 0| Value |= (op & UINT64_C(15)) << 16; 7818| 0| break; 7819| 0| } 7820| 0| case ARM::BLX: { ------------------ | Branch (7820:5): [True: 0, False: 2.24k] ------------------ 7821| | // op: func 7822| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7823| 0| Value |= op & UINT64_C(15); 7824| 0| break; 7825| 0| } 7826| 0| case ARM::tBLXNSr: ------------------ | Branch (7826:5): [True: 0, False: 2.24k] ------------------ 7827| 0| case ARM::tBLXr: { ------------------ | Branch (7827:5): [True: 0, False: 2.24k] ------------------ 7828| | // op: func 7829| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7830| 0| Value |= (op & UINT64_C(15)) << 3; 7831| 0| break; 7832| 0| } 7833| 87| case ARM::tBL: { ------------------ | Branch (7833:5): [True: 87, False: 2.15k] ------------------ 7834| | // op: func 7835| 87| op = getThumbBLTargetOpValue(MI, 2, Fixups, STI); 7836| 87| Value |= (op & UINT64_C(8388608)) << 3; 7837| 87| Value |= (op & UINT64_C(2095104)) << 5; 7838| 87| Value |= (op & UINT64_C(4194304)) >> 9; 7839| 87| Value |= (op & UINT64_C(2097152)) >> 10; 7840| 87| Value |= op & UINT64_C(2047); 7841| 87| break; 7842| 0| } 7843| 1| case ARM::tBLXi: { ------------------ | Branch (7843:5): [True: 1, False: 2.23k] ------------------ 7844| | // op: func 7845| 1| op = getThumbBLXTargetOpValue(MI, 2, Fixups, STI); 7846| 1| Value |= (op & UINT64_C(8388608)) << 3; 7847| 1| Value |= (op & UINT64_C(2095104)) << 5; 7848| 1| Value |= (op & UINT64_C(4194304)) >> 9; 7849| 1| Value |= (op & UINT64_C(2097152)) >> 10; 7850| 1| Value |= op & UINT64_C(2046); 7851| 1| break; 7852| 0| } 7853| 0| case ARM::t2SETPAN: { ------------------ | Branch (7853:5): [True: 0, False: 2.24k] ------------------ 7854| | // op: imm 7855| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7856| 0| Value |= (op & UINT64_C(1)) << 3; 7857| 0| break; 7858| 0| } 7859| 0| case ARM::SETPAN: { ------------------ | Branch (7859:5): [True: 0, False: 2.24k] ------------------ 7860| | // op: imm 7861| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7862| 0| Value |= (op & UINT64_C(1)) << 9; 7863| 0| break; 7864| 0| } 7865| 0| case ARM::tHINT: { ------------------ | Branch (7865:5): [True: 0, False: 2.24k] ------------------ 7866| | // op: imm 7867| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7868| 0| Value |= (op & UINT64_C(15)) << 4; 7869| 0| break; 7870| 0| } 7871| 0| case ARM::HVC: { ------------------ | Branch (7871:5): [True: 0, False: 2.24k] ------------------ 7872| | // op: imm 7873| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7874| 0| Value |= (op & UINT64_C(65520)) << 4; 7875| 0| Value |= op & UINT64_C(15); 7876| 0| break; 7877| 0| } 7878| 0| case ARM::t2HINT: ------------------ | Branch (7878:5): [True: 0, False: 2.24k] ------------------ 7879| 0| case ARM::t2SUBS_PC_LR: ------------------ | Branch (7879:5): [True: 0, False: 2.24k] ------------------ 7880| 0| case ARM::tSVC: { ------------------ | Branch (7880:5): [True: 0, False: 2.24k] ------------------ 7881| | // op: imm 7882| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7883| 0| Value |= op & UINT64_C(255); 7884| 0| break; 7885| 0| } 7886| 92| case ARM::tADDspi: ------------------ | Branch (7886:5): [True: 92, False: 2.14k] ------------------ 7887| 111| case ARM::tSUBspi: { ------------------ | Branch (7887:5): [True: 19, False: 2.22k] ------------------ 7888| | // op: imm 7889| 111| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7890| 111| Value |= op & UINT64_C(127); 7891| 111| break; 7892| 92| } 7893| 0| case ARM::t2HVC: ------------------ | Branch (7893:5): [True: 0, False: 2.24k] ------------------ 7894| 0| case ARM::t2UDF: { ------------------ | Branch (7894:5): [True: 0, False: 2.24k] ------------------ 7895| | // op: imm16 7896| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7897| 0| Value |= (op & UINT64_C(61440)) << 4; 7898| 0| Value |= op & UINT64_C(4095); 7899| 0| break; 7900| 0| } 7901| 0| case ARM::UDF: { ------------------ | Branch (7901:5): [True: 0, False: 2.24k] ------------------ 7902| | // op: imm16 7903| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7904| 0| Value |= (op & UINT64_C(65520)) << 4; 7905| 0| Value |= op & UINT64_C(15); 7906| 0| break; 7907| 0| } 7908| 0| case ARM::tUDF: { ------------------ | Branch (7908:5): [True: 0, False: 2.24k] ------------------ 7909| | // op: imm8 7910| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7911| 0| Value |= op & UINT64_C(255); 7912| 0| break; 7913| 0| } 7914| 0| case ARM::tCPS: { ------------------ | Branch (7914:5): [True: 0, False: 2.24k] ------------------ 7915| | // op: imod 7916| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7917| 0| Value |= (op & UINT64_C(1)) << 4; 7918| | // op: iflags 7919| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7920| 0| Value |= op & UINT64_C(7); 7921| 0| break; 7922| 0| } 7923| 0| case ARM::CPS2p: { ------------------ | Branch (7923:5): [True: 0, False: 2.24k] ------------------ 7924| | // op: imod 7925| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7926| 0| Value |= (op & UINT64_C(3)) << 18; 7927| | // op: iflags 7928| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7929| 0| Value |= (op & UINT64_C(7)) << 6; 7930| 0| break; 7931| 0| } 7932| 0| case ARM::CPS3p: { ------------------ | Branch (7932:5): [True: 0, False: 2.24k] ------------------ 7933| | // op: imod 7934| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7935| 0| Value |= (op & UINT64_C(3)) << 18; 7936| | // op: iflags 7937| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7938| 0| Value |= (op & UINT64_C(7)) << 6; 7939| | // op: mode 7940| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7941| 0| Value |= op & UINT64_C(31); 7942| 0| break; 7943| 0| } 7944| 0| case ARM::t2CPS2p: { ------------------ | Branch (7944:5): [True: 0, False: 2.24k] ------------------ 7945| | // op: imod 7946| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7947| 0| Value |= (op & UINT64_C(3)) << 9; 7948| | // op: iflags 7949| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7950| 0| Value |= (op & UINT64_C(7)) << 5; 7951| 0| break; 7952| 0| } 7953| 0| case ARM::t2CPS3p: { ------------------ | Branch (7953:5): [True: 0, False: 2.24k] ------------------ 7954| | // op: imod 7955| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7956| 0| Value |= (op & UINT64_C(3)) << 9; 7957| | // op: iflags 7958| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7959| 0| Value |= (op & UINT64_C(7)) << 5; 7960| | // op: mode 7961| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7962| 0| Value |= op & UINT64_C(31); 7963| 0| break; 7964| 0| } 7965| 65| case ARM::t2MSR_AR: { ------------------ | Branch (7965:5): [True: 65, False: 2.17k] ------------------ 7966| | // op: mask 7967| 65| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7968| 65| Value |= (op & UINT64_C(16)) << 16; 7969| 65| Value |= (op & UINT64_C(15)) << 8; 7970| | // op: Rn 7971| 65| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7972| 65| Value |= (op & UINT64_C(15)) << 16; 7973| 65| break; 7974| 0| } 7975| 0| case ARM::CPS1p: ------------------ | Branch (7975:5): [True: 0, False: 2.24k] ------------------ 7976| 0| case ARM::SRSDA: ------------------ | Branch (7976:5): [True: 0, False: 2.24k] ------------------ 7977| 0| case ARM::SRSDA_UPD: ------------------ | Branch (7977:5): [True: 0, False: 2.24k] ------------------ 7978| 0| case ARM::SRSDB: ------------------ | Branch (7978:5): [True: 0, False: 2.24k] ------------------ 7979| 0| case ARM::SRSDB_UPD: ------------------ | Branch (7979:5): [True: 0, False: 2.24k] ------------------ 7980| 0| case ARM::SRSIA: ------------------ | Branch (7980:5): [True: 0, False: 2.24k] ------------------ 7981| 0| case ARM::SRSIA_UPD: ------------------ | Branch (7981:5): [True: 0, False: 2.24k] ------------------ 7982| 0| case ARM::SRSIB: ------------------ | Branch (7982:5): [True: 0, False: 2.24k] ------------------ 7983| 0| case ARM::SRSIB_UPD: ------------------ | Branch (7983:5): [True: 0, False: 2.24k] ------------------ 7984| 0| case ARM::t2CPS1p: ------------------ | Branch (7984:5): [True: 0, False: 2.24k] ------------------ 7985| 0| case ARM::t2SRSDB: ------------------ | Branch (7985:5): [True: 0, False: 2.24k] ------------------ 7986| 0| case ARM::t2SRSDB_UPD: ------------------ | Branch (7986:5): [True: 0, False: 2.24k] ------------------ 7987| 0| case ARM::t2SRSIA: ------------------ | Branch (7987:5): [True: 0, False: 2.24k] ------------------ 7988| 0| case ARM::t2SRSIA_UPD: { ------------------ | Branch (7988:5): [True: 0, False: 2.24k] ------------------ 7989| | // op: mode 7990| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7991| 0| Value |= op & UINT64_C(31); 7992| 0| break; 7993| 0| } 7994| 0| case ARM::LDC2L_POST: ------------------ | Branch (7994:5): [True: 0, False: 2.24k] ------------------ 7995| 0| case ARM::LDC2_POST: ------------------ | Branch (7995:5): [True: 0, False: 2.24k] ------------------ 7996| 0| case ARM::STC2L_POST: ------------------ | Branch (7996:5): [True: 0, False: 2.24k] ------------------ 7997| 0| case ARM::STC2_POST: ------------------ | Branch (7997:5): [True: 0, False: 2.24k] ------------------ 7998| 0| case ARM::t2LDC2L_POST: ------------------ | Branch (7998:5): [True: 0, False: 2.24k] ------------------ 7999| 0| case ARM::t2LDC2_POST: ------------------ | Branch (7999:5): [True: 0, False: 2.24k] ------------------ 8000| 0| case ARM::t2LDCL_POST: ------------------ | Branch (8000:5): [True: 0, False: 2.24k] ------------------ 8001| 0| case ARM::t2LDC_POST: ------------------ | Branch (8001:5): [True: 0, False: 2.24k] ------------------ 8002| 0| case ARM::t2STC2L_POST: ------------------ | Branch (8002:5): [True: 0, False: 2.24k] ------------------ 8003| 0| case ARM::t2STC2_POST: ------------------ | Branch (8003:5): [True: 0, False: 2.24k] ------------------ 8004| 0| case ARM::t2STCL_POST: ------------------ | Branch (8004:5): [True: 0, False: 2.24k] ------------------ 8005| 0| case ARM::t2STC_POST: { ------------------ | Branch (8005:5): [True: 0, False: 2.24k] ------------------ 8006| | // op: offset 8007| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8008| 0| Value |= (op & UINT64_C(256)) << 15; 8009| 0| Value |= op & UINT64_C(255); 8010| | // op: addr 8011| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8012| 0| Value |= (op & UINT64_C(15)) << 16; 8013| | // op: cop 8014| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8015| 0| Value |= (op & UINT64_C(15)) << 8; 8016| | // op: CRd 8017| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8018| 0| Value |= (op & UINT64_C(15)) << 12; 8019| 0| break; 8020| 0| } 8021| 0| case ARM::CDP2: ------------------ | Branch (8021:5): [True: 0, False: 2.24k] ------------------ 8022| 0| case ARM::t2CDP: ------------------ | Branch (8022:5): [True: 0, False: 2.24k] ------------------ 8023| 0| case ARM::t2CDP2: { ------------------ | Branch (8023:5): [True: 0, False: 2.24k] ------------------ 8024| | // op: opc1 8025| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8026| 0| Value |= (op & UINT64_C(15)) << 20; 8027| | // op: CRn 8028| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8029| 0| Value |= (op & UINT64_C(15)) << 16; 8030| | // op: CRd 8031| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8032| 0| Value |= (op & UINT64_C(15)) << 12; 8033| | // op: cop 8034| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8035| 0| Value |= (op & UINT64_C(15)) << 8; 8036| | // op: opc2 8037| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 8038| 0| Value |= (op & UINT64_C(7)) << 5; 8039| | // op: CRm 8040| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8041| 0| Value |= op & UINT64_C(15); 8042| 0| break; 8043| 0| } 8044| 0| case ARM::t2SMC: { ------------------ | Branch (8044:5): [True: 0, False: 2.24k] ------------------ 8045| | // op: opt 8046| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8047| 0| Value |= (op & UINT64_C(15)) << 16; 8048| 0| break; 8049| 0| } 8050| 0| case ARM::DMB: ------------------ | Branch (8050:5): [True: 0, False: 2.24k] ------------------ 8051| 0| case ARM::DSB: ------------------ | Branch (8051:5): [True: 0, False: 2.24k] ------------------ 8052| 0| case ARM::ISB: ------------------ | Branch (8052:5): [True: 0, False: 2.24k] ------------------ 8053| 0| case ARM::t2DBG: ------------------ | Branch (8053:5): [True: 0, False: 2.24k] ------------------ 8054| 0| case ARM::t2DMB: ------------------ | Branch (8054:5): [True: 0, False: 2.24k] ------------------ 8055| 0| case ARM::t2DSB: ------------------ | Branch (8055:5): [True: 0, False: 2.24k] ------------------ 8056| 0| case ARM::t2ISB: { ------------------ | Branch (8056:5): [True: 0, False: 2.24k] ------------------ 8057| | // op: opt 8058| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8059| 0| Value |= op & UINT64_C(15); 8060| 0| break; 8061| 0| } 8062| 0| case ARM::LDC2L_OPTION: ------------------ | Branch (8062:5): [True: 0, False: 2.24k] ------------------ 8063| 0| case ARM::LDC2_OPTION: ------------------ | Branch (8063:5): [True: 0, False: 2.24k] ------------------ 8064| 0| case ARM::STC2L_OPTION: ------------------ | Branch (8064:5): [True: 0, False: 2.24k] ------------------ 8065| 0| case ARM::STC2_OPTION: ------------------ | Branch (8065:5): [True: 0, False: 2.24k] ------------------ 8066| 0| case ARM::t2LDC2L_OPTION: ------------------ | Branch (8066:5): [True: 0, False: 2.24k] ------------------ 8067| 0| case ARM::t2LDC2_OPTION: ------------------ | Branch (8067:5): [True: 0, False: 2.24k] ------------------ 8068| 0| case ARM::t2LDCL_OPTION: ------------------ | Branch (8068:5): [True: 0, False: 2.24k] ------------------ 8069| 0| case ARM::t2LDC_OPTION: ------------------ | Branch (8069:5): [True: 0, False: 2.24k] ------------------ 8070| 0| case ARM::t2STC2L_OPTION: ------------------ | Branch (8070:5): [True: 0, False: 2.24k] ------------------ 8071| 0| case ARM::t2STC2_OPTION: ------------------ | Branch (8071:5): [True: 0, False: 2.24k] ------------------ 8072| 0| case ARM::t2STCL_OPTION: ------------------ | Branch (8072:5): [True: 0, False: 2.24k] ------------------ 8073| 0| case ARM::t2STC_OPTION: { ------------------ | Branch (8073:5): [True: 0, False: 2.24k] ------------------ 8074| | // op: option 8075| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8076| 0| Value |= op & UINT64_C(255); 8077| | // op: addr 8078| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8079| 0| Value |= (op & UINT64_C(15)) << 16; 8080| | // op: cop 8081| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8082| 0| Value |= (op & UINT64_C(15)) << 8; 8083| | // op: CRd 8084| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8085| 0| Value |= (op & UINT64_C(15)) << 12; 8086| 0| break; 8087| 0| } 8088| 0| case ARM::BX_RET: ------------------ | Branch (8088:5): [True: 0, False: 2.24k] ------------------ 8089| 0| case ARM::ERET: ------------------ | Branch (8089:5): [True: 0, False: 2.24k] ------------------ 8090| 0| case ARM::MOVPCLR: { ------------------ | Branch (8090:5): [True: 0, False: 2.24k] ------------------ 8091| | // op: p 8092| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8093| 0| Value |= (op & UINT64_C(15)) << 28; 8094| 0| break; 8095| 0| } 8096| 0| case ARM::FMSTAT: { ------------------ | Branch (8096:5): [True: 0, False: 2.24k] ------------------ 8097| | // op: p 8098| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8099| 0| Value |= (op & UINT64_C(15)) << 28; 8100| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8101| 0| break; 8102| 0| } 8103| 0| case ARM::t2Bcc: { ------------------ | Branch (8103:5): [True: 0, False: 2.24k] ------------------ 8104| | // op: p 8105| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8106| 0| Value |= (op & UINT64_C(15)) << 22; 8107| | // op: target 8108| 0| op = getBranchTargetOpValue(MI, 0, Fixups, STI); 8109| 0| Value |= (op & UINT64_C(1048576)) << 6; 8110| 0| Value |= (op & UINT64_C(258048)) << 4; 8111| 0| Value |= (op & UINT64_C(262144)) >> 5; 8112| 0| Value |= (op & UINT64_C(524288)) >> 8; 8113| 0| Value |= (op & UINT64_C(4094)) >> 1; 8114| 0| break; 8115| 0| } 8116| 0| case ARM::VCMPEZD: ------------------ | Branch (8116:5): [True: 0, False: 2.24k] ------------------ 8117| 0| case ARM::VCMPZD: { ------------------ | Branch (8117:5): [True: 0, False: 2.24k] ------------------ 8118| | // op: p 8119| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8120| 0| Value |= (op & UINT64_C(15)) << 28; 8121| | // op: Dd 8122| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8123| 0| Value |= (op & UINT64_C(16)) << 18; 8124| 0| Value |= (op & UINT64_C(15)) << 12; 8125| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8126| 0| break; 8127| 0| } 8128| 0| case ARM::MRS: ------------------ | Branch (8128:5): [True: 0, False: 2.24k] ------------------ 8129| 0| case ARM::MRSsys: { ------------------ | Branch (8129:5): [True: 0, False: 2.24k] ------------------ 8130| | // op: p 8131| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8132| 0| Value |= (op & UINT64_C(15)) << 28; 8133| | // op: Rd 8134| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8135| 0| Value |= (op & UINT64_C(15)) << 12; 8136| 0| break; 8137| 0| } 8138| 0| case ARM::VLDMSIA: ------------------ | Branch (8138:5): [True: 0, False: 2.24k] ------------------ 8139| 0| case ARM::VSTMSIA: { ------------------ | Branch (8139:5): [True: 0, False: 2.24k] ------------------ 8140| | // op: p 8141| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8142| 0| Value |= (op & UINT64_C(15)) << 28; 8143| | // op: Rn 8144| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8145| 0| Value |= (op & UINT64_C(15)) << 16; 8146| | // op: regs 8147| 0| op = getRegisterListOpValue(MI, 3, Fixups, STI); 8148| 0| Value |= (op & UINT64_C(256)) << 14; 8149| 0| Value |= (op & UINT64_C(7680)) << 3; 8150| 0| Value |= op & UINT64_C(255); 8151| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8152| 0| break; 8153| 0| } 8154| 0| case ARM::FLDMXIA: ------------------ | Branch (8154:5): [True: 0, False: 2.24k] ------------------ 8155| 0| case ARM::FSTMXIA: { ------------------ | Branch (8155:5): [True: 0, False: 2.24k] ------------------ 8156| | // op: p 8157| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8158| 0| Value |= (op & UINT64_C(15)) << 28; 8159| | // op: Rn 8160| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8161| 0| Value |= (op & UINT64_C(15)) << 16; 8162| | // op: regs 8163| 0| op = getRegisterListOpValue(MI, 3, Fixups, STI); 8164| 0| Value |= (op & UINT64_C(3840)) << 4; 8165| 0| Value |= op & UINT64_C(254); 8166| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8167| 0| break; 8168| 0| } 8169| 0| case ARM::VLDMDIA: ------------------ | Branch (8169:5): [True: 0, False: 2.24k] ------------------ 8170| 0| case ARM::VSTMDIA: { ------------------ | Branch (8170:5): [True: 0, False: 2.24k] ------------------ 8171| | // op: p 8172| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8173| 0| Value |= (op & UINT64_C(15)) << 28; 8174| | // op: Rn 8175| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8176| 0| Value |= (op & UINT64_C(15)) << 16; 8177| | // op: regs 8178| 0| op = getRegisterListOpValue(MI, 3, Fixups, STI); 8179| 0| Value |= (op & UINT64_C(4096)) << 10; 8180| 0| Value |= (op & UINT64_C(3840)) << 4; 8181| 0| Value |= op & UINT64_C(254); 8182| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8183| 0| break; 8184| 0| } 8185| 0| case ARM::VLLDM: ------------------ | Branch (8185:5): [True: 0, False: 2.24k] ------------------ 8186| 0| case ARM::VLSTM: { ------------------ | Branch (8186:5): [True: 0, False: 2.24k] ------------------ 8187| | // op: p 8188| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8189| 0| Value |= (op & UINT64_C(15)) << 28; 8190| | // op: Rn 8191| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8192| 0| Value |= (op & UINT64_C(15)) << 16; 8193| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8194| 0| break; 8195| 0| } 8196| 0| case ARM::VMRS: ------------------ | Branch (8196:5): [True: 0, False: 2.24k] ------------------ 8197| 0| case ARM::VMRS_FPEXC: ------------------ | Branch (8197:5): [True: 0, False: 2.24k] ------------------ 8198| 0| case ARM::VMRS_FPINST: ------------------ | Branch (8198:5): [True: 0, False: 2.24k] ------------------ 8199| 0| case ARM::VMRS_FPINST2: ------------------ | Branch (8199:5): [True: 0, False: 2.24k] ------------------ 8200| 0| case ARM::VMRS_FPSID: ------------------ | Branch (8200:5): [True: 0, False: 2.24k] ------------------ 8201| 0| case ARM::VMRS_MVFR0: ------------------ | Branch (8201:5): [True: 0, False: 2.24k] ------------------ 8202| 0| case ARM::VMRS_MVFR1: ------------------ | Branch (8202:5): [True: 0, False: 2.24k] ------------------ 8203| 0| case ARM::VMRS_MVFR2: { ------------------ | Branch (8203:5): [True: 0, False: 2.24k] ------------------ 8204| | // op: p 8205| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8206| 0| Value |= (op & UINT64_C(15)) << 28; 8207| | // op: Rt 8208| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8209| 0| Value |= (op & UINT64_C(15)) << 12; 8210| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8211| 0| break; 8212| 0| } 8213| 0| case ARM::VCMPEZH: ------------------ | Branch (8213:5): [True: 0, False: 2.24k] ------------------ 8214| 0| case ARM::VCMPEZS: ------------------ | Branch (8214:5): [True: 0, False: 2.24k] ------------------ 8215| 0| case ARM::VCMPZH: ------------------ | Branch (8215:5): [True: 0, False: 2.24k] ------------------ 8216| 0| case ARM::VCMPZS: { ------------------ | Branch (8216:5): [True: 0, False: 2.24k] ------------------ 8217| | // op: p 8218| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8219| 0| Value |= (op & UINT64_C(15)) << 28; 8220| | // op: Sd 8221| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8222| 0| Value |= (op & UINT64_C(1)) << 22; 8223| 0| Value |= (op & UINT64_C(30)) << 11; 8224| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8225| 0| break; 8226| 0| } 8227| 0| case ARM::BX_pred: { ------------------ | Branch (8227:5): [True: 0, False: 2.24k] ------------------ 8228| | // op: p 8229| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8230| 0| Value |= (op & UINT64_C(15)) << 28; 8231| | // op: dst 8232| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8233| 0| Value |= op & UINT64_C(15); 8234| 0| break; 8235| 0| } 8236| 0| case ARM::BL_pred: { ------------------ | Branch (8236:5): [True: 0, False: 2.24k] ------------------ 8237| | // op: p 8238| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8239| 0| Value |= (op & UINT64_C(15)) << 28; 8240| | // op: func 8241| 0| op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 8242| 0| Value |= op & UINT64_C(16777215); 8243| 0| break; 8244| 0| } 8245| 0| case ARM::BLX_pred: ------------------ | Branch (8245:5): [True: 0, False: 2.24k] ------------------ 8246| 0| case ARM::BXJ: { ------------------ | Branch (8246:5): [True: 0, False: 2.24k] ------------------ 8247| | // op: p 8248| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8249| 0| Value |= (op & UINT64_C(15)) << 28; 8250| | // op: func 8251| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8252| 0| Value |= op & UINT64_C(15); 8253| 0| break; 8254| 0| } 8255| 0| case ARM::HINT: { ------------------ | Branch (8255:5): [True: 0, False: 2.24k] ------------------ 8256| | // op: p 8257| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8258| 0| Value |= (op & UINT64_C(15)) << 28; 8259| | // op: imm 8260| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8261| 0| Value |= op & UINT64_C(255); 8262| 0| break; 8263| 0| } 8264| 0| case ARM::DBG: ------------------ | Branch (8264:5): [True: 0, False: 2.24k] ------------------ 8265| 0| case ARM::SMC: { ------------------ | Branch (8265:5): [True: 0, False: 2.24k] ------------------ 8266| | // op: p 8267| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8268| 0| Value |= (op & UINT64_C(15)) << 28; 8269| | // op: opt 8270| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8271| 0| Value |= op & UINT64_C(15); 8272| 0| break; 8273| 0| } 8274| 0| case ARM::LDMDA: ------------------ | Branch (8274:5): [True: 0, False: 2.24k] ------------------ 8275| 0| case ARM::LDMDB: ------------------ | Branch (8275:5): [True: 0, False: 2.24k] ------------------ 8276| 0| case ARM::LDMIA: ------------------ | Branch (8276:5): [True: 0, False: 2.24k] ------------------ 8277| 0| case ARM::LDMIB: ------------------ | Branch (8277:5): [True: 0, False: 2.24k] ------------------ 8278| 0| case ARM::STMDA: ------------------ | Branch (8278:5): [True: 0, False: 2.24k] ------------------ 8279| 0| case ARM::STMDB: ------------------ | Branch (8279:5): [True: 0, False: 2.24k] ------------------ 8280| 0| case ARM::STMIA: ------------------ | Branch (8280:5): [True: 0, False: 2.24k] ------------------ 8281| 0| case ARM::STMIB: ------------------ | Branch (8281:5): [True: 0, False: 2.24k] ------------------ 8282| 0| case ARM::sysLDMDA: ------------------ | Branch (8282:5): [True: 0, False: 2.24k] ------------------ 8283| 0| case ARM::sysLDMDB: ------------------ | Branch (8283:5): [True: 0, False: 2.24k] ------------------ 8284| 0| case ARM::sysLDMIA: ------------------ | Branch (8284:5): [True: 0, False: 2.24k] ------------------ 8285| 0| case ARM::sysLDMIB: ------------------ | Branch (8285:5): [True: 0, False: 2.24k] ------------------ 8286| 0| case ARM::sysSTMDA: ------------------ | Branch (8286:5): [True: 0, False: 2.24k] ------------------ 8287| 0| case ARM::sysSTMDB: ------------------ | Branch (8287:5): [True: 0, False: 2.24k] ------------------ 8288| 0| case ARM::sysSTMIA: ------------------ | Branch (8288:5): [True: 0, False: 2.24k] ------------------ 8289| 0| case ARM::sysSTMIB: { ------------------ | Branch (8289:5): [True: 0, False: 2.24k] ------------------ 8290| | // op: p 8291| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8292| 0| Value |= (op & UINT64_C(15)) << 28; 8293| | // op: regs 8294| 0| op = getRegisterListOpValue(MI, 3, Fixups, STI); 8295| 0| Value |= op & UINT64_C(65535); 8296| | // op: Rn 8297| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8298| 0| Value |= (op & UINT64_C(15)) << 16; 8299| 0| break; 8300| 0| } 8301| 0| case ARM::VMSR: ------------------ | Branch (8301:5): [True: 0, False: 2.24k] ------------------ 8302| 0| case ARM::VMSR_FPEXC: ------------------ | Branch (8302:5): [True: 0, False: 2.24k] ------------------ 8303| 0| case ARM::VMSR_FPINST: ------------------ | Branch (8303:5): [True: 0, False: 2.24k] ------------------ 8304| 0| case ARM::VMSR_FPINST2: ------------------ | Branch (8304:5): [True: 0, False: 2.24k] ------------------ 8305| 0| case ARM::VMSR_FPSID: { ------------------ | Branch (8305:5): [True: 0, False: 2.24k] ------------------ 8306| | // op: p 8307| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8308| 0| Value |= (op & UINT64_C(15)) << 28; 8309| | // op: src 8310| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8311| 0| Value |= (op & UINT64_C(15)) << 12; 8312| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8313| 0| break; 8314| 0| } 8315| 0| case ARM::SVC: { ------------------ | Branch (8315:5): [True: 0, False: 2.24k] ------------------ 8316| | // op: p 8317| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8318| 0| Value |= (op & UINT64_C(15)) << 28; 8319| | // op: svc 8320| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8321| 0| Value |= op & UINT64_C(16777215); 8322| 0| break; 8323| 0| } 8324| 234| case ARM::Bcc: { ------------------ | Branch (8324:5): [True: 234, False: 2.00k] ------------------ 8325| | // op: p 8326| 234| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8327| 234| Value |= (op & UINT64_C(15)) << 28; 8328| | // op: target 8329| 234| op = getARMBranchTargetOpValue(MI, 0, Fixups, STI); 8330| 234| Value |= op & UINT64_C(16777215); 8331| 234| break; 8332| 0| } 8333| 0| case ARM::tBcc: { ------------------ | Branch (8333:5): [True: 0, False: 2.24k] ------------------ 8334| | // op: p 8335| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8336| 0| Value |= (op & UINT64_C(15)) << 8; 8337| | // op: target 8338| 0| op = getThumbBCCTargetOpValue(MI, 0, Fixups, STI); 8339| 0| Value |= op & UINT64_C(255); 8340| 0| break; 8341| 0| } 8342| 0| case ARM::VABSD: ------------------ | Branch (8342:5): [True: 0, False: 2.24k] ------------------ 8343| 0| case ARM::VCMPD: ------------------ | Branch (8343:5): [True: 0, False: 2.24k] ------------------ 8344| 0| case ARM::VCMPED: ------------------ | Branch (8344:5): [True: 0, False: 2.24k] ------------------ 8345| 0| case ARM::VMOVD: ------------------ | Branch (8345:5): [True: 0, False: 2.24k] ------------------ 8346| 0| case ARM::VNEGD: ------------------ | Branch (8346:5): [True: 0, False: 2.24k] ------------------ 8347| 0| case ARM::VRINTRD: ------------------ | Branch (8347:5): [True: 0, False: 2.24k] ------------------ 8348| 0| case ARM::VRINTXD: ------------------ | Branch (8348:5): [True: 0, False: 2.24k] ------------------ 8349| 0| case ARM::VRINTZD: ------------------ | Branch (8349:5): [True: 0, False: 2.24k] ------------------ 8350| 0| case ARM::VSQRTD: { ------------------ | Branch (8350:5): [True: 0, False: 2.24k] ------------------ 8351| | // op: p 8352| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8353| 0| Value |= (op & UINT64_C(15)) << 28; 8354| | // op: Dd 8355| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8356| 0| Value |= (op & UINT64_C(16)) << 18; 8357| 0| Value |= (op & UINT64_C(15)) << 12; 8358| | // op: Dm 8359| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8360| 0| Value |= (op & UINT64_C(16)) << 1; 8361| 0| Value |= op & UINT64_C(15); 8362| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8363| 0| break; 8364| 0| } 8365| 0| case ARM::VCVTBHD: ------------------ | Branch (8365:5): [True: 0, False: 2.24k] ------------------ 8366| 0| case ARM::VCVTTHD: ------------------ | Branch (8366:5): [True: 0, False: 2.24k] ------------------ 8367| 0| case ARM::VSITOD: ------------------ | Branch (8367:5): [True: 0, False: 2.24k] ------------------ 8368| 0| case ARM::VUITOD: { ------------------ | Branch (8368:5): [True: 0, False: 2.24k] ------------------ 8369| | // op: p 8370| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8371| 0| Value |= (op & UINT64_C(15)) << 28; 8372| | // op: Dd 8373| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8374| 0| Value |= (op & UINT64_C(16)) << 18; 8375| 0| Value |= (op & UINT64_C(15)) << 12; 8376| | // op: Sm 8377| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8378| 0| Value |= (op & UINT64_C(1)) << 5; 8379| 0| Value |= (op & UINT64_C(30)) >> 1; 8380| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8381| 0| break; 8382| 0| } 8383| 0| case ARM::FCONSTD: { ------------------ | Branch (8383:5): [True: 0, False: 2.24k] ------------------ 8384| | // op: p 8385| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8386| 0| Value |= (op & UINT64_C(15)) << 28; 8387| | // op: Dd 8388| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8389| 0| Value |= (op & UINT64_C(16)) << 18; 8390| 0| Value |= (op & UINT64_C(15)) << 12; 8391| | // op: imm 8392| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8393| 0| Value |= (op & UINT64_C(240)) << 12; 8394| 0| Value |= op & UINT64_C(15); 8395| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8396| 0| break; 8397| 0| } 8398| 0| case ARM::VCVTBDH: ------------------ | Branch (8398:5): [True: 0, False: 2.24k] ------------------ 8399| 0| case ARM::VCVTTDH: { ------------------ | Branch (8399:5): [True: 0, False: 2.24k] ------------------ 8400| | // op: p 8401| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8402| 0| Value |= (op & UINT64_C(15)) << 28; 8403| | // op: Dm 8404| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8405| 0| Value |= (op & UINT64_C(16)) << 1; 8406| 0| Value |= op & UINT64_C(15); 8407| | // op: Sd 8408| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8409| 0| Value |= (op & UINT64_C(1)) << 22; 8410| 0| Value |= (op & UINT64_C(30)) << 11; 8411| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8412| 0| break; 8413| 0| } 8414| 0| case ARM::CLZ: ------------------ | Branch (8414:5): [True: 0, False: 2.24k] ------------------ 8415| 0| case ARM::RBIT: ------------------ | Branch (8415:5): [True: 0, False: 2.24k] ------------------ 8416| 0| case ARM::REV: ------------------ | Branch (8416:5): [True: 0, False: 2.24k] ------------------ 8417| 0| case ARM::REV16: ------------------ | Branch (8417:5): [True: 0, False: 2.24k] ------------------ 8418| 0| case ARM::REVSH: { ------------------ | Branch (8418:5): [True: 0, False: 2.24k] ------------------ 8419| | // op: p 8420| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8421| 0| Value |= (op & UINT64_C(15)) << 28; 8422| | // op: Rd 8423| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8424| 0| Value |= (op & UINT64_C(15)) << 12; 8425| | // op: Rm 8426| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8427| 0| Value |= op & UINT64_C(15); 8428| 0| break; 8429| 0| } 8430| 0| case ARM::MOVi16: { ------------------ | Branch (8430:5): [True: 0, False: 2.24k] ------------------ 8431| | // op: p 8432| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8433| 0| Value |= (op & UINT64_C(15)) << 28; 8434| | // op: Rd 8435| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8436| 0| Value |= (op & UINT64_C(15)) << 12; 8437| | // op: imm 8438| 0| op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 8439| 0| Value |= (op & UINT64_C(61440)) << 4; 8440| 0| Value |= op & UINT64_C(4095); 8441| 0| break; 8442| 0| } 8443| 0| case ARM::ADR: { ------------------ | Branch (8443:5): [True: 0, False: 2.24k] ------------------ 8444| | // op: p 8445| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8446| 0| Value |= (op & UINT64_C(15)) << 28; 8447| | // op: Rd 8448| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8449| 0| Value |= (op & UINT64_C(15)) << 12; 8450| | // op: label 8451| 0| op = getAdrLabelOpValue(MI, 1, Fixups, STI); 8452| 0| Value |= (op & UINT64_C(12288)) << 10; 8453| 0| Value |= op & UINT64_C(4095); 8454| 0| break; 8455| 0| } 8456| 0| case ARM::CMNzrr: ------------------ | Branch (8456:5): [True: 0, False: 2.24k] ------------------ 8457| 0| case ARM::CMPrr: ------------------ | Branch (8457:5): [True: 0, False: 2.24k] ------------------ 8458| 0| case ARM::TEQrr: ------------------ | Branch (8458:5): [True: 0, False: 2.24k] ------------------ 8459| 0| case ARM::TSTrr: { ------------------ | Branch (8459:5): [True: 0, False: 2.24k] ------------------ 8460| | // op: p 8461| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8462| 0| Value |= (op & UINT64_C(15)) << 28; 8463| | // op: Rn 8464| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8465| 0| Value |= (op & UINT64_C(15)) << 16; 8466| | // op: Rm 8467| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8468| 0| Value |= op & UINT64_C(15); 8469| 0| break; 8470| 0| } 8471| 0| case ARM::CMNri: ------------------ | Branch (8471:5): [True: 0, False: 2.24k] ------------------ 8472| 0| case ARM::CMPri: ------------------ | Branch (8472:5): [True: 0, False: 2.24k] ------------------ 8473| 0| case ARM::TEQri: ------------------ | Branch (8473:5): [True: 0, False: 2.24k] ------------------ 8474| 0| case ARM::TSTri: { ------------------ | Branch (8474:5): [True: 0, False: 2.24k] ------------------ 8475| | // op: p 8476| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8477| 0| Value |= (op & UINT64_C(15)) << 28; 8478| | // op: Rn 8479| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8480| 0| Value |= (op & UINT64_C(15)) << 16; 8481| | // op: imm 8482| 0| op = getModImmOpValue(MI, 1, Fixups, STI); 8483| 0| Value |= op & UINT64_C(4095); 8484| 0| break; 8485| 0| } 8486| 0| case ARM::VLDMSDB_UPD: ------------------ | Branch (8486:5): [True: 0, False: 2.24k] ------------------ 8487| 0| case ARM::VLDMSIA_UPD: ------------------ | Branch (8487:5): [True: 0, False: 2.24k] ------------------ 8488| 0| case ARM::VSTMSDB_UPD: ------------------ | Branch (8488:5): [True: 0, False: 2.24k] ------------------ 8489| 0| case ARM::VSTMSIA_UPD: { ------------------ | Branch (8489:5): [True: 0, False: 2.24k] ------------------ 8490| | // op: p 8491| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8492| 0| Value |= (op & UINT64_C(15)) << 28; 8493| | // op: Rn 8494| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8495| 0| Value |= (op & UINT64_C(15)) << 16; 8496| | // op: regs 8497| 0| op = getRegisterListOpValue(MI, 4, Fixups, STI); 8498| 0| Value |= (op & UINT64_C(256)) << 14; 8499| 0| Value |= (op & UINT64_C(7680)) << 3; 8500| 0| Value |= op & UINT64_C(255); 8501| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8502| 0| break; 8503| 0| } 8504| 0| case ARM::FLDMXDB_UPD: ------------------ | Branch (8504:5): [True: 0, False: 2.24k] ------------------ 8505| 0| case ARM::FLDMXIA_UPD: ------------------ | Branch (8505:5): [True: 0, False: 2.24k] ------------------ 8506| 0| case ARM::FSTMXDB_UPD: ------------------ | Branch (8506:5): [True: 0, False: 2.24k] ------------------ 8507| 0| case ARM::FSTMXIA_UPD: { ------------------ | Branch (8507:5): [True: 0, False: 2.24k] ------------------ 8508| | // op: p 8509| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8510| 0| Value |= (op & UINT64_C(15)) << 28; 8511| | // op: Rn 8512| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8513| 0| Value |= (op & UINT64_C(15)) << 16; 8514| | // op: regs 8515| 0| op = getRegisterListOpValue(MI, 4, Fixups, STI); 8516| 0| Value |= (op & UINT64_C(3840)) << 4; 8517| 0| Value |= op & UINT64_C(254); 8518| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8519| 0| break; 8520| 0| } 8521| 0| case ARM::VLDMDDB_UPD: ------------------ | Branch (8521:5): [True: 0, False: 2.24k] ------------------ 8522| 0| case ARM::VLDMDIA_UPD: ------------------ | Branch (8522:5): [True: 0, False: 2.24k] ------------------ 8523| 0| case ARM::VSTMDDB_UPD: ------------------ | Branch (8523:5): [True: 0, False: 2.24k] ------------------ 8524| 0| case ARM::VSTMDIA_UPD: { ------------------ | Branch (8524:5): [True: 0, False: 2.24k] ------------------ 8525| | // op: p 8526| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8527| 0| Value |= (op & UINT64_C(15)) << 28; 8528| | // op: Rn 8529| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8530| 0| Value |= (op & UINT64_C(15)) << 16; 8531| | // op: regs 8532| 0| op = getRegisterListOpValue(MI, 4, Fixups, STI); 8533| 0| Value |= (op & UINT64_C(4096)) << 10; 8534| 0| Value |= (op & UINT64_C(3840)) << 4; 8535| 0| Value |= op & UINT64_C(254); 8536| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8537| 0| break; 8538| 0| } 8539| 0| case ARM::VMOVRH: ------------------ | Branch (8539:5): [True: 0, False: 2.24k] ------------------ 8540| 0| case ARM::VMOVRS: { ------------------ | Branch (8540:5): [True: 0, False: 2.24k] ------------------ 8541| | // op: p 8542| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8543| 0| Value |= (op & UINT64_C(15)) << 28; 8544| | // op: Rt 8545| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8546| 0| Value |= (op & UINT64_C(15)) << 12; 8547| | // op: Sn 8548| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8549| 0| Value |= (op & UINT64_C(30)) << 15; 8550| 0| Value |= (op & UINT64_C(1)) << 7; 8551| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8552| 0| break; 8553| 0| } 8554| 0| case ARM::LDA: ------------------ | Branch (8554:5): [True: 0, False: 2.24k] ------------------ 8555| 0| case ARM::LDAB: ------------------ | Branch (8555:5): [True: 0, False: 2.24k] ------------------ 8556| 0| case ARM::LDAEX: ------------------ | Branch (8556:5): [True: 0, False: 2.24k] ------------------ 8557| 0| case ARM::LDAEXB: ------------------ | Branch (8557:5): [True: 0, False: 2.24k] ------------------ 8558| 0| case ARM::LDAEXD: ------------------ | Branch (8558:5): [True: 0, False: 2.24k] ------------------ 8559| 0| case ARM::LDAEXH: ------------------ | Branch (8559:5): [True: 0, False: 2.24k] ------------------ 8560| 0| case ARM::LDAH: ------------------ | Branch (8560:5): [True: 0, False: 2.24k] ------------------ 8561| 0| case ARM::LDREX: ------------------ | Branch (8561:5): [True: 0, False: 2.24k] ------------------ 8562| 0| case ARM::LDREXB: ------------------ | Branch (8562:5): [True: 0, False: 2.24k] ------------------ 8563| 0| case ARM::LDREXD: ------------------ | Branch (8563:5): [True: 0, False: 2.24k] ------------------ 8564| 0| case ARM::LDREXH: { ------------------ | Branch (8564:5): [True: 0, False: 2.24k] ------------------ 8565| | // op: p 8566| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8567| 0| Value |= (op & UINT64_C(15)) << 28; 8568| | // op: Rt 8569| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8570| 0| Value |= (op & UINT64_C(15)) << 12; 8571| | // op: addr 8572| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8573| 0| Value |= (op & UINT64_C(15)) << 16; 8574| 0| break; 8575| 0| } 8576| 0| case ARM::STL: ------------------ | Branch (8576:5): [True: 0, False: 2.24k] ------------------ 8577| 0| case ARM::STLB: ------------------ | Branch (8577:5): [True: 0, False: 2.24k] ------------------ 8578| 0| case ARM::STLH: { ------------------ | Branch (8578:5): [True: 0, False: 2.24k] ------------------ 8579| | // op: p 8580| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8581| 0| Value |= (op & UINT64_C(15)) << 28; 8582| | // op: Rt 8583| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8584| 0| Value |= op & UINT64_C(15); 8585| | // op: addr 8586| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8587| 0| Value |= (op & UINT64_C(15)) << 16; 8588| 0| break; 8589| 0| } 8590| 0| case ARM::VCVTSD: ------------------ | Branch (8590:5): [True: 0, False: 2.24k] ------------------ 8591| 0| case ARM::VTOSIRD: ------------------ | Branch (8591:5): [True: 0, False: 2.24k] ------------------ 8592| 0| case ARM::VTOSIZD: ------------------ | Branch (8592:5): [True: 0, False: 2.24k] ------------------ 8593| 0| case ARM::VTOUIRD: ------------------ | Branch (8593:5): [True: 0, False: 2.24k] ------------------ 8594| 0| case ARM::VTOUIZD: { ------------------ | Branch (8594:5): [True: 0, False: 2.24k] ------------------ 8595| | // op: p 8596| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8597| 0| Value |= (op & UINT64_C(15)) << 28; 8598| | // op: Sd 8599| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8600| 0| Value |= (op & UINT64_C(1)) << 22; 8601| 0| Value |= (op & UINT64_C(30)) << 11; 8602| | // op: Dm 8603| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8604| 0| Value |= (op & UINT64_C(16)) << 1; 8605| 0| Value |= op & UINT64_C(15); 8606| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8607| 0| break; 8608| 0| } 8609| 0| case ARM::VABSH: ------------------ | Branch (8609:5): [True: 0, False: 2.24k] ------------------ 8610| 0| case ARM::VABSS: ------------------ | Branch (8610:5): [True: 0, False: 2.24k] ------------------ 8611| 0| case ARM::VCMPEH: ------------------ | Branch (8611:5): [True: 0, False: 2.24k] ------------------ 8612| 0| case ARM::VCMPES: ------------------ | Branch (8612:5): [True: 0, False: 2.24k] ------------------ 8613| 0| case ARM::VCMPH: ------------------ | Branch (8613:5): [True: 0, False: 2.24k] ------------------ 8614| 0| case ARM::VCMPS: ------------------ | Branch (8614:5): [True: 0, False: 2.24k] ------------------ 8615| 0| case ARM::VCVTBHS: ------------------ | Branch (8615:5): [True: 0, False: 2.24k] ------------------ 8616| 0| case ARM::VCVTBSH: ------------------ | Branch (8616:5): [True: 0, False: 2.24k] ------------------ 8617| 0| case ARM::VCVTTHS: ------------------ | Branch (8617:5): [True: 0, False: 2.24k] ------------------ 8618| 0| case ARM::VCVTTSH: ------------------ | Branch (8618:5): [True: 0, False: 2.24k] ------------------ 8619| 0| case ARM::VMOVS: ------------------ | Branch (8619:5): [True: 0, False: 2.24k] ------------------ 8620| 0| case ARM::VNEGH: ------------------ | Branch (8620:5): [True: 0, False: 2.24k] ------------------ 8621| 0| case ARM::VNEGS: ------------------ | Branch (8621:5): [True: 0, False: 2.24k] ------------------ 8622| 0| case ARM::VRINTRH: ------------------ | Branch (8622:5): [True: 0, False: 2.24k] ------------------ 8623| 0| case ARM::VRINTRS: ------------------ | Branch (8623:5): [True: 0, False: 2.24k] ------------------ 8624| 0| case ARM::VRINTXH: ------------------ | Branch (8624:5): [True: 0, False: 2.24k] ------------------ 8625| 0| case ARM::VRINTXS: ------------------ | Branch (8625:5): [True: 0, False: 2.24k] ------------------ 8626| 0| case ARM::VRINTZH: ------------------ | Branch (8626:5): [True: 0, False: 2.24k] ------------------ 8627| 0| case ARM::VRINTZS: ------------------ | Branch (8627:5): [True: 0, False: 2.24k] ------------------ 8628| 0| case ARM::VSITOH: ------------------ | Branch (8628:5): [True: 0, False: 2.24k] ------------------ 8629| 0| case ARM::VSITOS: ------------------ | Branch (8629:5): [True: 0, False: 2.24k] ------------------ 8630| 0| case ARM::VSQRTH: ------------------ | Branch (8630:5): [True: 0, False: 2.24k] ------------------ 8631| 0| case ARM::VSQRTS: ------------------ | Branch (8631:5): [True: 0, False: 2.24k] ------------------ 8632| 0| case ARM::VTOSIRH: ------------------ | Branch (8632:5): [True: 0, False: 2.24k] ------------------ 8633| 0| case ARM::VTOSIRS: ------------------ | Branch (8633:5): [True: 0, False: 2.24k] ------------------ 8634| 0| case ARM::VTOSIZH: ------------------ | Branch (8634:5): [True: 0, False: 2.24k] ------------------ 8635| 0| case ARM::VTOSIZS: ------------------ | Branch (8635:5): [True: 0, False: 2.24k] ------------------ 8636| 0| case ARM::VTOUIRH: ------------------ | Branch (8636:5): [True: 0, False: 2.24k] ------------------ 8637| 0| case ARM::VTOUIRS: ------------------ | Branch (8637:5): [True: 0, False: 2.24k] ------------------ 8638| 0| case ARM::VTOUIZH: ------------------ | Branch (8638:5): [True: 0, False: 2.24k] ------------------ 8639| 0| case ARM::VTOUIZS: ------------------ | Branch (8639:5): [True: 0, False: 2.24k] ------------------ 8640| 0| case ARM::VUITOH: ------------------ | Branch (8640:5): [True: 0, False: 2.24k] ------------------ 8641| 0| case ARM::VUITOS: { ------------------ | Branch (8641:5): [True: 0, False: 2.24k] ------------------ 8642| | // op: p 8643| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8644| 0| Value |= (op & UINT64_C(15)) << 28; 8645| | // op: Sd 8646| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8647| 0| Value |= (op & UINT64_C(1)) << 22; 8648| 0| Value |= (op & UINT64_C(30)) << 11; 8649| | // op: Sm 8650| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8651| 0| Value |= (op & UINT64_C(1)) << 5; 8652| 0| Value |= (op & UINT64_C(30)) >> 1; 8653| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8654| 0| break; 8655| 0| } 8656| 0| case ARM::FCONSTH: ------------------ | Branch (8656:5): [True: 0, False: 2.24k] ------------------ 8657| 0| case ARM::FCONSTS: { ------------------ | Branch (8657:5): [True: 0, False: 2.24k] ------------------ 8658| | // op: p 8659| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8660| 0| Value |= (op & UINT64_C(15)) << 28; 8661| | // op: Sd 8662| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8663| 0| Value |= (op & UINT64_C(1)) << 22; 8664| 0| Value |= (op & UINT64_C(30)) << 11; 8665| | // op: imm 8666| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8667| 0| Value |= (op & UINT64_C(240)) << 12; 8668| 0| Value |= op & UINT64_C(15); 8669| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8670| 0| break; 8671| 0| } 8672| 0| case ARM::VCVTDS: { ------------------ | Branch (8672:5): [True: 0, False: 2.24k] ------------------ 8673| | // op: p 8674| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8675| 0| Value |= (op & UINT64_C(15)) << 28; 8676| | // op: Sm 8677| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8678| 0| Value |= (op & UINT64_C(1)) << 5; 8679| 0| Value |= (op & UINT64_C(30)) >> 1; 8680| | // op: Dd 8681| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8682| 0| Value |= (op & UINT64_C(16)) << 18; 8683| 0| Value |= (op & UINT64_C(15)) << 12; 8684| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8685| 0| break; 8686| 0| } 8687| 0| case ARM::VMOVHR: ------------------ | Branch (8687:5): [True: 0, False: 2.24k] ------------------ 8688| 0| case ARM::VMOVSR: { ------------------ | Branch (8688:5): [True: 0, False: 2.24k] ------------------ 8689| | // op: p 8690| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8691| 0| Value |= (op & UINT64_C(15)) << 28; 8692| | // op: Sn 8693| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8694| 0| Value |= (op & UINT64_C(30)) << 15; 8695| 0| Value |= (op & UINT64_C(1)) << 7; 8696| | // op: Rt 8697| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8698| 0| Value |= (op & UINT64_C(15)) << 12; 8699| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8700| 0| break; 8701| 0| } 8702| 0| case ARM::MSRbanked: { ------------------ | Branch (8702:5): [True: 0, False: 2.24k] ------------------ 8703| | // op: p 8704| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8705| 0| Value |= (op & UINT64_C(15)) << 28; 8706| | // op: banked 8707| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8708| 0| Value |= (op & UINT64_C(32)) << 17; 8709| 0| Value |= (op & UINT64_C(15)) << 16; 8710| 0| Value |= (op & UINT64_C(16)) << 4; 8711| | // op: Rn 8712| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8713| 0| Value |= op & UINT64_C(15); 8714| 0| break; 8715| 0| } 8716| 0| case ARM::MRSbanked: { ------------------ | Branch (8716:5): [True: 0, False: 2.24k] ------------------ 8717| | // op: p 8718| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8719| 0| Value |= (op & UINT64_C(15)) << 28; 8720| | // op: banked 8721| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8722| 0| Value |= (op & UINT64_C(32)) << 17; 8723| 0| Value |= (op & UINT64_C(15)) << 16; 8724| 0| Value |= (op & UINT64_C(16)) << 4; 8725| | // op: Rd 8726| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8727| 0| Value |= (op & UINT64_C(15)) << 12; 8728| 0| break; 8729| 0| } 8730| 0| case ARM::MSR: { ------------------ | Branch (8730:5): [True: 0, False: 2.24k] ------------------ 8731| | // op: p 8732| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8733| 0| Value |= (op & UINT64_C(15)) << 28; 8734| | // op: mask 8735| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8736| 0| Value |= (op & UINT64_C(16)) << 18; 8737| 0| Value |= (op & UINT64_C(15)) << 16; 8738| | // op: Rn 8739| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8740| 0| Value |= op & UINT64_C(15); 8741| 0| break; 8742| 0| } 8743| 0| case ARM::MSRi: { ------------------ | Branch (8743:5): [True: 0, False: 2.24k] ------------------ 8744| | // op: p 8745| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8746| 0| Value |= (op & UINT64_C(15)) << 28; 8747| | // op: mask 8748| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8749| 0| Value |= (op & UINT64_C(16)) << 18; 8750| 0| Value |= (op & UINT64_C(15)) << 16; 8751| | // op: imm 8752| 0| op = getModImmOpValue(MI, 1, Fixups, STI); 8753| 0| Value |= op & UINT64_C(4095); 8754| 0| break; 8755| 0| } 8756| 0| case ARM::LDMDA_UPD: ------------------ | Branch (8756:5): [True: 0, False: 2.24k] ------------------ 8757| 0| case ARM::LDMDB_UPD: ------------------ | Branch (8757:5): [True: 0, False: 2.24k] ------------------ 8758| 0| case ARM::LDMIA_UPD: ------------------ | Branch (8758:5): [True: 0, False: 2.24k] ------------------ 8759| 0| case ARM::LDMIB_UPD: ------------------ | Branch (8759:5): [True: 0, False: 2.24k] ------------------ 8760| 0| case ARM::STMDA_UPD: ------------------ | Branch (8760:5): [True: 0, False: 2.24k] ------------------ 8761| 0| case ARM::STMDB_UPD: ------------------ | Branch (8761:5): [True: 0, False: 2.24k] ------------------ 8762| 0| case ARM::STMIA_UPD: ------------------ | Branch (8762:5): [True: 0, False: 2.24k] ------------------ 8763| 0| case ARM::STMIB_UPD: ------------------ | Branch (8763:5): [True: 0, False: 2.24k] ------------------ 8764| 0| case ARM::sysLDMDA_UPD: ------------------ | Branch (8764:5): [True: 0, False: 2.24k] ------------------ 8765| 0| case ARM::sysLDMDB_UPD: ------------------ | Branch (8765:5): [True: 0, False: 2.24k] ------------------ 8766| 0| case ARM::sysLDMIA_UPD: ------------------ | Branch (8766:5): [True: 0, False: 2.24k] ------------------ 8767| 0| case ARM::sysLDMIB_UPD: ------------------ | Branch (8767:5): [True: 0, False: 2.24k] ------------------ 8768| 0| case ARM::sysSTMDA_UPD: ------------------ | Branch (8768:5): [True: 0, False: 2.24k] ------------------ 8769| 0| case ARM::sysSTMDB_UPD: ------------------ | Branch (8769:5): [True: 0, False: 2.24k] ------------------ 8770| 0| case ARM::sysSTMIA_UPD: ------------------ | Branch (8770:5): [True: 0, False: 2.24k] ------------------ 8771| 0| case ARM::sysSTMIB_UPD: { ------------------ | Branch (8771:5): [True: 0, False: 2.24k] ------------------ 8772| | // op: p 8773| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8774| 0| Value |= (op & UINT64_C(15)) << 28; 8775| | // op: regs 8776| 0| op = getRegisterListOpValue(MI, 4, Fixups, STI); 8777| 0| Value |= op & UINT64_C(65535); 8778| | // op: Rn 8779| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8780| 0| Value |= (op & UINT64_C(15)) << 16; 8781| 0| break; 8782| 0| } 8783| 128| case ARM::MOVr: ------------------ | Branch (8783:5): [True: 128, False: 2.11k] ------------------ 8784| 128| case ARM::MOVr_TC: ------------------ | Branch (8784:5): [True: 0, False: 2.24k] ------------------ 8785| 128| case ARM::MVNr: { ------------------ | Branch (8785:5): [True: 0, False: 2.24k] ------------------ 8786| | // op: p 8787| 128| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8788| 128| Value |= (op & UINT64_C(15)) << 28; 8789| | // op: s 8790| 128| op = getCCOutOpValue(MI, 4, Fixups, STI); 8791| 128| Value |= (op & UINT64_C(1)) << 20; 8792| | // op: Rd 8793| 128| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8794| 128| Value |= (op & UINT64_C(15)) << 12; 8795| | // op: Rm 8796| 128| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8797| 128| Value |= op & UINT64_C(15); 8798| 128| break; 8799| 128| } 8800| 0| case ARM::MOVi: ------------------ | Branch (8800:5): [True: 0, False: 2.24k] ------------------ 8801| 0| case ARM::MVNi: { ------------------ | Branch (8801:5): [True: 0, False: 2.24k] ------------------ 8802| | // op: p 8803| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8804| 0| Value |= (op & UINT64_C(15)) << 28; 8805| | // op: s 8806| 0| op = getCCOutOpValue(MI, 4, Fixups, STI); 8807| 0| Value |= (op & UINT64_C(1)) << 20; 8808| | // op: Rd 8809| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8810| 0| Value |= (op & UINT64_C(15)) << 12; 8811| | // op: imm 8812| 0| op = getModImmOpValue(MI, 1, Fixups, STI); 8813| 0| Value |= op & UINT64_C(4095); 8814| 0| break; 8815| 0| } 8816| 0| case ARM::VADDD: ------------------ | Branch (8816:5): [True: 0, False: 2.24k] ------------------ 8817| 0| case ARM::VDIVD: ------------------ | Branch (8817:5): [True: 0, False: 2.24k] ------------------ 8818| 0| case ARM::VMULD: ------------------ | Branch (8818:5): [True: 0, False: 2.24k] ------------------ 8819| 0| case ARM::VNMULD: ------------------ | Branch (8819:5): [True: 0, False: 2.24k] ------------------ 8820| 0| case ARM::VSUBD: { ------------------ | Branch (8820:5): [True: 0, False: 2.24k] ------------------ 8821| | // op: p 8822| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8823| 0| Value |= (op & UINT64_C(15)) << 28; 8824| | // op: Dd 8825| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8826| 0| Value |= (op & UINT64_C(16)) << 18; 8827| 0| Value |= (op & UINT64_C(15)) << 12; 8828| | // op: Dn 8829| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8830| 0| Value |= (op & UINT64_C(15)) << 16; 8831| 0| Value |= (op & UINT64_C(16)) << 3; 8832| | // op: Dm 8833| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8834| 0| Value |= (op & UINT64_C(16)) << 1; 8835| 0| Value |= op & UINT64_C(15); 8836| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8837| 0| break; 8838| 0| } 8839| 0| case ARM::VLDRD: ------------------ | Branch (8839:5): [True: 0, False: 2.24k] ------------------ 8840| 0| case ARM::VSTRD: { ------------------ | Branch (8840:5): [True: 0, False: 2.24k] ------------------ 8841| | // op: p 8842| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8843| 0| Value |= (op & UINT64_C(15)) << 28; 8844| | // op: Dd 8845| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8846| 0| Value |= (op & UINT64_C(16)) << 18; 8847| 0| Value |= (op & UINT64_C(15)) << 12; 8848| | // op: addr 8849| 0| op = getAddrMode5OpValue(MI, 1, Fixups, STI); 8850| 0| Value |= (op & UINT64_C(256)) << 15; 8851| 0| Value |= (op & UINT64_C(7680)) << 7; 8852| 0| Value |= op & UINT64_C(255); 8853| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8854| 0| break; 8855| 0| } 8856| 0| case ARM::VMOVDRR: { ------------------ | Branch (8856:5): [True: 0, False: 2.24k] ------------------ 8857| | // op: p 8858| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8859| 0| Value |= (op & UINT64_C(15)) << 28; 8860| | // op: Dm 8861| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8862| 0| Value |= (op & UINT64_C(16)) << 1; 8863| 0| Value |= op & UINT64_C(15); 8864| | // op: Rt 8865| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8866| 0| Value |= (op & UINT64_C(15)) << 12; 8867| | // op: Rt2 8868| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8869| 0| Value |= (op & UINT64_C(15)) << 16; 8870| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8871| 0| break; 8872| 0| } 8873| 0| case ARM::VMOVRRD: { ------------------ | Branch (8873:5): [True: 0, False: 2.24k] ------------------ 8874| | // op: p 8875| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8876| 0| Value |= (op & UINT64_C(15)) << 28; 8877| | // op: Dm 8878| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8879| 0| Value |= (op & UINT64_C(16)) << 1; 8880| 0| Value |= op & UINT64_C(15); 8881| | // op: Rt 8882| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8883| 0| Value |= (op & UINT64_C(15)) << 12; 8884| | // op: Rt2 8885| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8886| 0| Value |= (op & UINT64_C(15)) << 16; 8887| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 8888| 0| break; 8889| 0| } 8890| 0| case ARM::SXTB: ------------------ | Branch (8890:5): [True: 0, False: 2.24k] ------------------ 8891| 0| case ARM::SXTB16: ------------------ | Branch (8891:5): [True: 0, False: 2.24k] ------------------ 8892| 0| case ARM::SXTH: ------------------ | Branch (8892:5): [True: 0, False: 2.24k] ------------------ 8893| 0| case ARM::UXTB: ------------------ | Branch (8893:5): [True: 0, False: 2.24k] ------------------ 8894| 0| case ARM::UXTB16: ------------------ | Branch (8894:5): [True: 0, False: 2.24k] ------------------ 8895| 0| case ARM::UXTH: { ------------------ | Branch (8895:5): [True: 0, False: 2.24k] ------------------ 8896| | // op: p 8897| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8898| 0| Value |= (op & UINT64_C(15)) << 28; 8899| | // op: Rd 8900| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8901| 0| Value |= (op & UINT64_C(15)) << 12; 8902| | // op: Rm 8903| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8904| 0| Value |= op & UINT64_C(15); 8905| | // op: rot 8906| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8907| 0| Value |= (op & UINT64_C(3)) << 10; 8908| 0| break; 8909| 0| } 8910| 0| case ARM::SEL: { ------------------ | Branch (8910:5): [True: 0, False: 2.24k] ------------------ 8911| | // op: p 8912| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8913| 0| Value |= (op & UINT64_C(15)) << 28; 8914| | // op: Rd 8915| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8916| 0| Value |= (op & UINT64_C(15)) << 12; 8917| | // op: Rn 8918| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8919| 0| Value |= (op & UINT64_C(15)) << 16; 8920| | // op: Rm 8921| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8922| 0| Value |= op & UINT64_C(15); 8923| 0| break; 8924| 0| } 8925| 0| case ARM::BFC: { ------------------ | Branch (8925:5): [True: 0, False: 2.24k] ------------------ 8926| | // op: p 8927| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8928| 0| Value |= (op & UINT64_C(15)) << 28; 8929| | // op: Rd 8930| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8931| 0| Value |= (op & UINT64_C(15)) << 12; 8932| | // op: imm 8933| 0| op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 8934| 0| Value |= (op & UINT64_C(992)) << 11; 8935| 0| Value |= (op & UINT64_C(31)) << 7; 8936| 0| break; 8937| 0| } 8938| 0| case ARM::MOVTi16: { ------------------ | Branch (8938:5): [True: 0, False: 2.24k] ------------------ 8939| | // op: p 8940| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8941| 0| Value |= (op & UINT64_C(15)) << 28; 8942| | // op: Rd 8943| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8944| 0| Value |= (op & UINT64_C(15)) << 12; 8945| | // op: imm 8946| 0| op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 8947| 0| Value |= (op & UINT64_C(61440)) << 4; 8948| 0| Value |= op & UINT64_C(4095); 8949| 0| break; 8950| 0| } 8951| 0| case ARM::SSAT16: ------------------ | Branch (8951:5): [True: 0, False: 2.24k] ------------------ 8952| 0| case ARM::USAT16: { ------------------ | Branch (8952:5): [True: 0, False: 2.24k] ------------------ 8953| | // op: p 8954| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8955| 0| Value |= (op & UINT64_C(15)) << 28; 8956| | // op: Rd 8957| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8958| 0| Value |= (op & UINT64_C(15)) << 12; 8959| | // op: sat_imm 8960| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8961| 0| Value |= (op & UINT64_C(15)) << 16; 8962| | // op: Rn 8963| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8964| 0| Value |= op & UINT64_C(15); 8965| 0| break; 8966| 0| } 8967| 0| case ARM::SDIV: ------------------ | Branch (8967:5): [True: 0, False: 2.24k] ------------------ 8968| 0| case ARM::SMMUL: ------------------ | Branch (8968:5): [True: 0, False: 2.24k] ------------------ 8969| 0| case ARM::SMMULR: ------------------ | Branch (8969:5): [True: 0, False: 2.24k] ------------------ 8970| 0| case ARM::UDIV: ------------------ | Branch (8970:5): [True: 0, False: 2.24k] ------------------ 8971| 0| case ARM::USAD8: { ------------------ | Branch (8971:5): [True: 0, False: 2.24k] ------------------ 8972| | // op: p 8973| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8974| 0| Value |= (op & UINT64_C(15)) << 28; 8975| | // op: Rd 8976| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8977| 0| Value |= (op & UINT64_C(15)) << 16; 8978| | // op: Rn 8979| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8980| 0| Value |= op & UINT64_C(15); 8981| | // op: Rm 8982| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8983| 0| Value |= (op & UINT64_C(15)) << 8; 8984| 0| break; 8985| 0| } 8986| 0| case ARM::CMNzrsi: ------------------ | Branch (8986:5): [True: 0, False: 2.24k] ------------------ 8987| 0| case ARM::CMPrsi: ------------------ | Branch (8987:5): [True: 0, False: 2.24k] ------------------ 8988| 0| case ARM::TEQrsi: ------------------ | Branch (8988:5): [True: 0, False: 2.24k] ------------------ 8989| 0| case ARM::TSTrsi: { ------------------ | Branch (8989:5): [True: 0, False: 2.24k] ------------------ 8990| | // op: p 8991| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8992| 0| Value |= (op & UINT64_C(15)) << 28; 8993| | // op: Rn 8994| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8995| 0| Value |= (op & UINT64_C(15)) << 16; 8996| | // op: shift 8997| 0| op = getSORegImmOpValue(MI, 1, Fixups, STI); 8998| 0| Value |= op & UINT64_C(4064); 8999| 0| Value |= op & UINT64_C(15); 9000| 0| break; 9001| 0| } 9002| 0| case ARM::QADD16: ------------------ | Branch (9002:5): [True: 0, False: 2.24k] ------------------ 9003| 0| case ARM::QADD8: ------------------ | Branch (9003:5): [True: 0, False: 2.24k] ------------------ 9004| 0| case ARM::QASX: ------------------ | Branch (9004:5): [True: 0, False: 2.24k] ------------------ 9005| 0| case ARM::QSAX: ------------------ | Branch (9005:5): [True: 0, False: 2.24k] ------------------ 9006| 0| case ARM::QSUB16: ------------------ | Branch (9006:5): [True: 0, False: 2.24k] ------------------ 9007| 0| case ARM::QSUB8: ------------------ | Branch (9007:5): [True: 0, False: 2.24k] ------------------ 9008| 0| case ARM::SADD16: ------------------ | Branch (9008:5): [True: 0, False: 2.24k] ------------------ 9009| 0| case ARM::SADD8: ------------------ | Branch (9009:5): [True: 0, False: 2.24k] ------------------ 9010| 0| case ARM::SASX: ------------------ | Branch (9010:5): [True: 0, False: 2.24k] ------------------ 9011| 0| case ARM::SHADD16: ------------------ | Branch (9011:5): [True: 0, False: 2.24k] ------------------ 9012| 0| case ARM::SHADD8: ------------------ | Branch (9012:5): [True: 0, False: 2.24k] ------------------ 9013| 0| case ARM::SHASX: ------------------ | Branch (9013:5): [True: 0, False: 2.24k] ------------------ 9014| 0| case ARM::SHSAX: ------------------ | Branch (9014:5): [True: 0, False: 2.24k] ------------------ 9015| 0| case ARM::SHSUB16: ------------------ | Branch (9015:5): [True: 0, False: 2.24k] ------------------ 9016| 0| case ARM::SHSUB8: ------------------ | Branch (9016:5): [True: 0, False: 2.24k] ------------------ 9017| 0| case ARM::SSAX: ------------------ | Branch (9017:5): [True: 0, False: 2.24k] ------------------ 9018| 0| case ARM::SSUB16: ------------------ | Branch (9018:5): [True: 0, False: 2.24k] ------------------ 9019| 0| case ARM::SSUB8: ------------------ | Branch (9019:5): [True: 0, False: 2.24k] ------------------ 9020| 0| case ARM::UADD16: ------------------ | Branch (9020:5): [True: 0, False: 2.24k] ------------------ 9021| 0| case ARM::UADD8: ------------------ | Branch (9021:5): [True: 0, False: 2.24k] ------------------ 9022| 0| case ARM::UASX: ------------------ | Branch (9022:5): [True: 0, False: 2.24k] ------------------ 9023| 0| case ARM::UHADD16: ------------------ | Branch (9023:5): [True: 0, False: 2.24k] ------------------ 9024| 0| case ARM::UHADD8: ------------------ | Branch (9024:5): [True: 0, False: 2.24k] ------------------ 9025| 0| case ARM::UHASX: ------------------ | Branch (9025:5): [True: 0, False: 2.24k] ------------------ 9026| 0| case ARM::UHSAX: ------------------ | Branch (9026:5): [True: 0, False: 2.24k] ------------------ 9027| 0| case ARM::UHSUB16: ------------------ | Branch (9027:5): [True: 0, False: 2.24k] ------------------ 9028| 0| case ARM::UHSUB8: ------------------ | Branch (9028:5): [True: 0, False: 2.24k] ------------------ 9029| 0| case ARM::UQADD16: ------------------ | Branch (9029:5): [True: 0, False: 2.24k] ------------------ 9030| 0| case ARM::UQADD8: ------------------ | Branch (9030:5): [True: 0, False: 2.24k] ------------------ 9031| 0| case ARM::UQASX: ------------------ | Branch (9031:5): [True: 0, False: 2.24k] ------------------ 9032| 0| case ARM::UQSAX: ------------------ | Branch (9032:5): [True: 0, False: 2.24k] ------------------ 9033| 0| case ARM::UQSUB16: ------------------ | Branch (9033:5): [True: 0, False: 2.24k] ------------------ 9034| 0| case ARM::UQSUB8: ------------------ | Branch (9034:5): [True: 0, False: 2.24k] ------------------ 9035| 0| case ARM::USAX: ------------------ | Branch (9035:5): [True: 0, False: 2.24k] ------------------ 9036| 0| case ARM::USUB16: ------------------ | Branch (9036:5): [True: 0, False: 2.24k] ------------------ 9037| 0| case ARM::USUB8: { ------------------ | Branch (9037:5): [True: 0, False: 2.24k] ------------------ 9038| | // op: p 9039| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9040| 0| Value |= (op & UINT64_C(15)) << 28; 9041| | // op: Rn 9042| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9043| 0| Value |= (op & UINT64_C(15)) << 16; 9044| | // op: Rd 9045| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9046| 0| Value |= (op & UINT64_C(15)) << 12; 9047| | // op: Rm 9048| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9049| 0| Value |= op & UINT64_C(15); 9050| 0| break; 9051| 0| } 9052| 0| case ARM::SMUAD: ------------------ | Branch (9052:5): [True: 0, False: 2.24k] ------------------ 9053| 0| case ARM::SMUADX: ------------------ | Branch (9053:5): [True: 0, False: 2.24k] ------------------ 9054| 0| case ARM::SMULBB: ------------------ | Branch (9054:5): [True: 0, False: 2.24k] ------------------ 9055| 0| case ARM::SMULBT: ------------------ | Branch (9055:5): [True: 0, False: 2.24k] ------------------ 9056| 0| case ARM::SMULTB: ------------------ | Branch (9056:5): [True: 0, False: 2.24k] ------------------ 9057| 0| case ARM::SMULTT: ------------------ | Branch (9057:5): [True: 0, False: 2.24k] ------------------ 9058| 0| case ARM::SMULWB: ------------------ | Branch (9058:5): [True: 0, False: 2.24k] ------------------ 9059| 0| case ARM::SMULWT: ------------------ | Branch (9059:5): [True: 0, False: 2.24k] ------------------ 9060| 0| case ARM::SMUSD: ------------------ | Branch (9060:5): [True: 0, False: 2.24k] ------------------ 9061| 0| case ARM::SMUSDX: { ------------------ | Branch (9061:5): [True: 0, False: 2.24k] ------------------ 9062| | // op: p 9063| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9064| 0| Value |= (op & UINT64_C(15)) << 28; 9065| | // op: Rn 9066| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9067| 0| Value |= op & UINT64_C(15); 9068| | // op: Rm 9069| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9070| 0| Value |= (op & UINT64_C(15)) << 8; 9071| | // op: Rd 9072| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9073| 0| Value |= (op & UINT64_C(15)) << 16; 9074| 0| break; 9075| 0| } 9076| 0| case ARM::QADD: ------------------ | Branch (9076:5): [True: 0, False: 2.24k] ------------------ 9077| 0| case ARM::QDADD: ------------------ | Branch (9077:5): [True: 0, False: 2.24k] ------------------ 9078| 0| case ARM::QDSUB: ------------------ | Branch (9078:5): [True: 0, False: 2.24k] ------------------ 9079| 0| case ARM::QSUB: { ------------------ | Branch (9079:5): [True: 0, False: 2.24k] ------------------ 9080| | // op: p 9081| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9082| 0| Value |= (op & UINT64_C(15)) << 28; 9083| | // op: Rn 9084| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9085| 0| Value |= (op & UINT64_C(15)) << 16; 9086| | // op: Rd 9087| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9088| 0| Value |= (op & UINT64_C(15)) << 12; 9089| | // op: Rm 9090| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9091| 0| Value |= op & UINT64_C(15); 9092| 0| break; 9093| 0| } 9094| 0| case ARM::SWP: ------------------ | Branch (9094:5): [True: 0, False: 2.24k] ------------------ 9095| 0| case ARM::SWPB: { ------------------ | Branch (9095:5): [True: 0, False: 2.24k] ------------------ 9096| | // op: p 9097| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9098| 0| Value |= (op & UINT64_C(15)) << 28; 9099| | // op: Rt 9100| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9101| 0| Value |= (op & UINT64_C(15)) << 12; 9102| | // op: Rt2 9103| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9104| 0| Value |= op & UINT64_C(15); 9105| | // op: addr 9106| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9107| 0| Value |= (op & UINT64_C(15)) << 16; 9108| 0| break; 9109| 0| } 9110| 0| case ARM::LDRBi12: ------------------ | Branch (9110:5): [True: 0, False: 2.24k] ------------------ 9111| 0| case ARM::LDRi12: ------------------ | Branch (9111:5): [True: 0, False: 2.24k] ------------------ 9112| 0| case ARM::STRBi12: ------------------ | Branch (9112:5): [True: 0, False: 2.24k] ------------------ 9113| 0| case ARM::STRi12: { ------------------ | Branch (9113:5): [True: 0, False: 2.24k] ------------------ 9114| | // op: p 9115| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9116| 0| Value |= (op & UINT64_C(15)) << 28; 9117| | // op: Rt 9118| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9119| 0| Value |= (op & UINT64_C(15)) << 12; 9120| | // op: addr 9121| 0| op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 9122| 0| Value |= (op & UINT64_C(4096)) << 11; 9123| 0| Value |= (op & UINT64_C(122880)) << 3; 9124| 0| Value |= op & UINT64_C(4095); 9125| 0| break; 9126| 0| } 9127| 0| case ARM::LDRcp: { ------------------ | Branch (9127:5): [True: 0, False: 2.24k] ------------------ 9128| | // op: p 9129| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9130| 0| Value |= (op & UINT64_C(15)) << 28; 9131| | // op: Rt 9132| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9133| 0| Value |= (op & UINT64_C(15)) << 12; 9134| | // op: addr 9135| 0| op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 9136| 0| Value |= (op & UINT64_C(4096)) << 11; 9137| 0| Value |= op & UINT64_C(4095); 9138| 0| break; 9139| 0| } 9140| 0| case ARM::STLEX: ------------------ | Branch (9140:5): [True: 0, False: 2.24k] ------------------ 9141| 0| case ARM::STLEXB: ------------------ | Branch (9141:5): [True: 0, False: 2.24k] ------------------ 9142| 0| case ARM::STLEXD: ------------------ | Branch (9142:5): [True: 0, False: 2.24k] ------------------ 9143| 0| case ARM::STLEXH: ------------------ | Branch (9143:5): [True: 0, False: 2.24k] ------------------ 9144| 0| case ARM::STREX: ------------------ | Branch (9144:5): [True: 0, False: 2.24k] ------------------ 9145| 0| case ARM::STREXB: ------------------ | Branch (9145:5): [True: 0, False: 2.24k] ------------------ 9146| 0| case ARM::STREXD: ------------------ | Branch (9146:5): [True: 0, False: 2.24k] ------------------ 9147| 0| case ARM::STREXH: { ------------------ | Branch (9147:5): [True: 0, False: 2.24k] ------------------ 9148| | // op: p 9149| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9150| 0| Value |= (op & UINT64_C(15)) << 28; 9151| | // op: Rt 9152| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9153| 0| Value |= op & UINT64_C(15); 9154| | // op: addr 9155| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9156| 0| Value |= (op & UINT64_C(15)) << 16; 9157| | // op: Rd 9158| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9159| 0| Value |= (op & UINT64_C(15)) << 12; 9160| 0| break; 9161| 0| } 9162| 0| case ARM::VADDH: ------------------ | Branch (9162:5): [True: 0, False: 2.24k] ------------------ 9163| 0| case ARM::VADDS: ------------------ | Branch (9163:5): [True: 0, False: 2.24k] ------------------ 9164| 0| case ARM::VDIVH: ------------------ | Branch (9164:5): [True: 0, False: 2.24k] ------------------ 9165| 0| case ARM::VDIVS: ------------------ | Branch (9165:5): [True: 0, False: 2.24k] ------------------ 9166| 0| case ARM::VMULH: ------------------ | Branch (9166:5): [True: 0, False: 2.24k] ------------------ 9167| 0| case ARM::VMULS: ------------------ | Branch (9167:5): [True: 0, False: 2.24k] ------------------ 9168| 0| case ARM::VNMULH: ------------------ | Branch (9168:5): [True: 0, False: 2.24k] ------------------ 9169| 0| case ARM::VNMULS: ------------------ | Branch (9169:5): [True: 0, False: 2.24k] ------------------ 9170| 0| case ARM::VSUBH: ------------------ | Branch (9170:5): [True: 0, False: 2.24k] ------------------ 9171| 0| case ARM::VSUBS: { ------------------ | Branch (9171:5): [True: 0, False: 2.24k] ------------------ 9172| | // op: p 9173| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9174| 0| Value |= (op & UINT64_C(15)) << 28; 9175| | // op: Sd 9176| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9177| 0| Value |= (op & UINT64_C(1)) << 22; 9178| 0| Value |= (op & UINT64_C(30)) << 11; 9179| | // op: Sn 9180| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9181| 0| Value |= (op & UINT64_C(30)) << 15; 9182| 0| Value |= (op & UINT64_C(1)) << 7; 9183| | // op: Sm 9184| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9185| 0| Value |= (op & UINT64_C(1)) << 5; 9186| 0| Value |= (op & UINT64_C(30)) >> 1; 9187| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9188| 0| break; 9189| 0| } 9190| 0| case ARM::VLDRH: ------------------ | Branch (9190:5): [True: 0, False: 2.24k] ------------------ 9191| 0| case ARM::VSTRH: { ------------------ | Branch (9191:5): [True: 0, False: 2.24k] ------------------ 9192| | // op: p 9193| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9194| 0| Value |= (op & UINT64_C(15)) << 28; 9195| | // op: Sd 9196| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9197| 0| Value |= (op & UINT64_C(1)) << 22; 9198| 0| Value |= (op & UINT64_C(30)) << 11; 9199| | // op: addr 9200| 0| op = getAddrMode5FP16OpValue(MI, 1, Fixups, STI); 9201| 0| Value |= (op & UINT64_C(256)) << 15; 9202| 0| Value |= (op & UINT64_C(7680)) << 7; 9203| 0| Value |= op & UINT64_C(255); 9204| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9205| 0| break; 9206| 0| } 9207| 0| case ARM::VLDRS: ------------------ | Branch (9207:5): [True: 0, False: 2.24k] ------------------ 9208| 0| case ARM::VSTRS: { ------------------ | Branch (9208:5): [True: 0, False: 2.24k] ------------------ 9209| | // op: p 9210| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9211| 0| Value |= (op & UINT64_C(15)) << 28; 9212| | // op: Sd 9213| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9214| 0| Value |= (op & UINT64_C(1)) << 22; 9215| 0| Value |= (op & UINT64_C(30)) << 11; 9216| | // op: addr 9217| 0| op = getAddrMode5OpValue(MI, 1, Fixups, STI); 9218| 0| Value |= (op & UINT64_C(256)) << 15; 9219| 0| Value |= (op & UINT64_C(7680)) << 7; 9220| 0| Value |= op & UINT64_C(255); 9221| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9222| 0| break; 9223| 0| } 9224| 0| case ARM::VSHTOH: ------------------ | Branch (9224:5): [True: 0, False: 2.24k] ------------------ 9225| 0| case ARM::VSHTOS: ------------------ | Branch (9225:5): [True: 0, False: 2.24k] ------------------ 9226| 0| case ARM::VSLTOH: ------------------ | Branch (9226:5): [True: 0, False: 2.24k] ------------------ 9227| 0| case ARM::VSLTOS: ------------------ | Branch (9227:5): [True: 0, False: 2.24k] ------------------ 9228| 0| case ARM::VTOSHH: ------------------ | Branch (9228:5): [True: 0, False: 2.24k] ------------------ 9229| 0| case ARM::VTOSHS: ------------------ | Branch (9229:5): [True: 0, False: 2.24k] ------------------ 9230| 0| case ARM::VTOSLH: ------------------ | Branch (9230:5): [True: 0, False: 2.24k] ------------------ 9231| 0| case ARM::VTOSLS: ------------------ | Branch (9231:5): [True: 0, False: 2.24k] ------------------ 9232| 0| case ARM::VTOUHH: ------------------ | Branch (9232:5): [True: 0, False: 2.24k] ------------------ 9233| 0| case ARM::VTOUHS: ------------------ | Branch (9233:5): [True: 0, False: 2.24k] ------------------ 9234| 0| case ARM::VTOULH: ------------------ | Branch (9234:5): [True: 0, False: 2.24k] ------------------ 9235| 0| case ARM::VTOULS: ------------------ | Branch (9235:5): [True: 0, False: 2.24k] ------------------ 9236| 0| case ARM::VUHTOH: ------------------ | Branch (9236:5): [True: 0, False: 2.24k] ------------------ 9237| 0| case ARM::VUHTOS: ------------------ | Branch (9237:5): [True: 0, False: 2.24k] ------------------ 9238| 0| case ARM::VULTOH: ------------------ | Branch (9238:5): [True: 0, False: 2.24k] ------------------ 9239| 0| case ARM::VULTOS: { ------------------ | Branch (9239:5): [True: 0, False: 2.24k] ------------------ 9240| | // op: p 9241| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9242| 0| Value |= (op & UINT64_C(15)) << 28; 9243| | // op: fbits 9244| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9245| 0| Value |= (op & UINT64_C(1)) << 5; 9246| 0| Value |= (op & UINT64_C(30)) >> 1; 9247| | // op: dst 9248| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9249| 0| Value |= (op & UINT64_C(1)) << 22; 9250| 0| Value |= (op & UINT64_C(30)) << 11; 9251| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9252| 0| break; 9253| 0| } 9254| 0| case ARM::VSHTOD: ------------------ | Branch (9254:5): [True: 0, False: 2.24k] ------------------ 9255| 0| case ARM::VSLTOD: ------------------ | Branch (9255:5): [True: 0, False: 2.24k] ------------------ 9256| 0| case ARM::VTOSHD: ------------------ | Branch (9256:5): [True: 0, False: 2.24k] ------------------ 9257| 0| case ARM::VTOSLD: ------------------ | Branch (9257:5): [True: 0, False: 2.24k] ------------------ 9258| 0| case ARM::VTOUHD: ------------------ | Branch (9258:5): [True: 0, False: 2.24k] ------------------ 9259| 0| case ARM::VTOULD: ------------------ | Branch (9259:5): [True: 0, False: 2.24k] ------------------ 9260| 0| case ARM::VUHTOD: ------------------ | Branch (9260:5): [True: 0, False: 2.24k] ------------------ 9261| 0| case ARM::VULTOD: { ------------------ | Branch (9261:5): [True: 0, False: 2.24k] ------------------ 9262| | // op: p 9263| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9264| 0| Value |= (op & UINT64_C(15)) << 28; 9265| | // op: fbits 9266| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9267| 0| Value |= (op & UINT64_C(1)) << 5; 9268| 0| Value |= (op & UINT64_C(30)) >> 1; 9269| | // op: dst 9270| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9271| 0| Value |= (op & UINT64_C(16)) << 18; 9272| 0| Value |= (op & UINT64_C(15)) << 12; 9273| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9274| 0| break; 9275| 0| } 9276| 0| case ARM::ADCrr: ------------------ | Branch (9276:5): [True: 0, False: 2.24k] ------------------ 9277| 36| case ARM::ADDrr: ------------------ | Branch (9277:5): [True: 36, False: 2.20k] ------------------ 9278| 36| case ARM::ANDrr: ------------------ | Branch (9278:5): [True: 0, False: 2.24k] ------------------ 9279| 36| case ARM::BICrr: ------------------ | Branch (9279:5): [True: 0, False: 2.24k] ------------------ 9280| 36| case ARM::EORrr: ------------------ | Branch (9280:5): [True: 0, False: 2.24k] ------------------ 9281| 36| case ARM::ORRrr: ------------------ | Branch (9281:5): [True: 0, False: 2.24k] ------------------ 9282| 36| case ARM::RSBrr: ------------------ | Branch (9282:5): [True: 0, False: 2.24k] ------------------ 9283| 36| case ARM::RSCrr: ------------------ | Branch (9283:5): [True: 0, False: 2.24k] ------------------ 9284| 36| case ARM::SBCrr: ------------------ | Branch (9284:5): [True: 0, False: 2.24k] ------------------ 9285| 36| case ARM::SUBrr: { ------------------ | Branch (9285:5): [True: 0, False: 2.24k] ------------------ 9286| | // op: p 9287| 36| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9288| 36| Value |= (op & UINT64_C(15)) << 28; 9289| | // op: s 9290| 36| op = getCCOutOpValue(MI, 5, Fixups, STI); 9291| 36| Value |= (op & UINT64_C(1)) << 20; 9292| | // op: Rd 9293| 36| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9294| 36| Value |= (op & UINT64_C(15)) << 12; 9295| | // op: Rn 9296| 36| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9297| 36| Value |= (op & UINT64_C(15)) << 16; 9298| | // op: Rm 9299| 36| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9300| 36| Value |= op & UINT64_C(15); 9301| 36| break; 9302| 36| } 9303| 0| case ARM::ADCri: ------------------ | Branch (9303:5): [True: 0, False: 2.24k] ------------------ 9304| 0| case ARM::ADDri: ------------------ | Branch (9304:5): [True: 0, False: 2.24k] ------------------ 9305| 0| case ARM::ANDri: ------------------ | Branch (9305:5): [True: 0, False: 2.24k] ------------------ 9306| 0| case ARM::BICri: ------------------ | Branch (9306:5): [True: 0, False: 2.24k] ------------------ 9307| 0| case ARM::EORri: ------------------ | Branch (9307:5): [True: 0, False: 2.24k] ------------------ 9308| 0| case ARM::ORRri: ------------------ | Branch (9308:5): [True: 0, False: 2.24k] ------------------ 9309| 0| case ARM::RSBri: ------------------ | Branch (9309:5): [True: 0, False: 2.24k] ------------------ 9310| 0| case ARM::RSCri: ------------------ | Branch (9310:5): [True: 0, False: 2.24k] ------------------ 9311| 0| case ARM::SBCri: ------------------ | Branch (9311:5): [True: 0, False: 2.24k] ------------------ 9312| 0| case ARM::SUBri: { ------------------ | Branch (9312:5): [True: 0, False: 2.24k] ------------------ 9313| | // op: p 9314| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9315| 0| Value |= (op & UINT64_C(15)) << 28; 9316| | // op: s 9317| 0| op = getCCOutOpValue(MI, 5, Fixups, STI); 9318| 0| Value |= (op & UINT64_C(1)) << 20; 9319| | // op: Rd 9320| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9321| 0| Value |= (op & UINT64_C(15)) << 12; 9322| | // op: Rn 9323| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9324| 0| Value |= (op & UINT64_C(15)) << 16; 9325| | // op: imm 9326| 0| op = getModImmOpValue(MI, 2, Fixups, STI); 9327| 0| Value |= op & UINT64_C(4095); 9328| 0| break; 9329| 0| } 9330| 0| case ARM::MVNsi: { ------------------ | Branch (9330:5): [True: 0, False: 2.24k] ------------------ 9331| | // op: p 9332| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9333| 0| Value |= (op & UINT64_C(15)) << 28; 9334| | // op: s 9335| 0| op = getCCOutOpValue(MI, 5, Fixups, STI); 9336| 0| Value |= (op & UINT64_C(1)) << 20; 9337| | // op: Rd 9338| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9339| 0| Value |= (op & UINT64_C(15)) << 12; 9340| | // op: shift 9341| 0| op = getSORegImmOpValue(MI, 1, Fixups, STI); 9342| 0| Value |= op & UINT64_C(4064); 9343| 0| Value |= op & UINT64_C(15); 9344| 0| break; 9345| 0| } 9346| 1| case ARM::MOVsi: { ------------------ | Branch (9346:5): [True: 1, False: 2.23k] ------------------ 9347| | // op: p 9348| 1| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9349| 1| Value |= (op & UINT64_C(15)) << 28; 9350| | // op: s 9351| 1| op = getCCOutOpValue(MI, 5, Fixups, STI); 9352| 1| Value |= (op & UINT64_C(1)) << 20; 9353| | // op: Rd 9354| 1| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9355| 1| Value |= (op & UINT64_C(15)) << 12; 9356| | // op: src 9357| 1| op = getSORegImmOpValue(MI, 1, Fixups, STI); 9358| 1| Value |= op & UINT64_C(4064); 9359| 1| Value |= op & UINT64_C(15); 9360| 1| break; 9361| 0| } 9362| 0| case ARM::MUL: { ------------------ | Branch (9362:5): [True: 0, False: 2.24k] ------------------ 9363| | // op: p 9364| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9365| 0| Value |= (op & UINT64_C(15)) << 28; 9366| | // op: s 9367| 0| op = getCCOutOpValue(MI, 5, Fixups, STI); 9368| 0| Value |= (op & UINT64_C(1)) << 20; 9369| | // op: Rd 9370| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9371| 0| Value |= (op & UINT64_C(15)) << 16; 9372| | // op: Rm 9373| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9374| 0| Value |= (op & UINT64_C(15)) << 8; 9375| | // op: Rn 9376| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9377| 0| Value |= op & UINT64_C(15); 9378| 0| break; 9379| 0| } 9380| 0| case ARM::VFMAD: ------------------ | Branch (9380:5): [True: 0, False: 2.24k] ------------------ 9381| 0| case ARM::VFMSD: ------------------ | Branch (9381:5): [True: 0, False: 2.24k] ------------------ 9382| 0| case ARM::VFNMAD: ------------------ | Branch (9382:5): [True: 0, False: 2.24k] ------------------ 9383| 0| case ARM::VFNMSD: ------------------ | Branch (9383:5): [True: 0, False: 2.24k] ------------------ 9384| 0| case ARM::VMLAD: ------------------ | Branch (9384:5): [True: 0, False: 2.24k] ------------------ 9385| 0| case ARM::VMLSD: ------------------ | Branch (9385:5): [True: 0, False: 2.24k] ------------------ 9386| 0| case ARM::VNMLAD: ------------------ | Branch (9386:5): [True: 0, False: 2.24k] ------------------ 9387| 0| case ARM::VNMLSD: { ------------------ | Branch (9387:5): [True: 0, False: 2.24k] ------------------ 9388| | // op: p 9389| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9390| 0| Value |= (op & UINT64_C(15)) << 28; 9391| | // op: Dd 9392| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9393| 0| Value |= (op & UINT64_C(16)) << 18; 9394| 0| Value |= (op & UINT64_C(15)) << 12; 9395| | // op: Dn 9396| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9397| 0| Value |= (op & UINT64_C(15)) << 16; 9398| 0| Value |= (op & UINT64_C(16)) << 3; 9399| | // op: Dm 9400| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9401| 0| Value |= (op & UINT64_C(16)) << 1; 9402| 0| Value |= op & UINT64_C(15); 9403| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9404| 0| break; 9405| 0| } 9406| 0| case ARM::SXTAB: ------------------ | Branch (9406:5): [True: 0, False: 2.24k] ------------------ 9407| 0| case ARM::SXTAB16: ------------------ | Branch (9407:5): [True: 0, False: 2.24k] ------------------ 9408| 0| case ARM::SXTAH: ------------------ | Branch (9408:5): [True: 0, False: 2.24k] ------------------ 9409| 0| case ARM::UXTAB: ------------------ | Branch (9409:5): [True: 0, False: 2.24k] ------------------ 9410| 0| case ARM::UXTAB16: ------------------ | Branch (9410:5): [True: 0, False: 2.24k] ------------------ 9411| 0| case ARM::UXTAH: { ------------------ | Branch (9411:5): [True: 0, False: 2.24k] ------------------ 9412| | // op: p 9413| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9414| 0| Value |= (op & UINT64_C(15)) << 28; 9415| | // op: Rd 9416| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9417| 0| Value |= (op & UINT64_C(15)) << 12; 9418| | // op: Rm 9419| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9420| 0| Value |= op & UINT64_C(15); 9421| | // op: Rn 9422| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9423| 0| Value |= (op & UINT64_C(15)) << 16; 9424| | // op: rot 9425| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9426| 0| Value |= (op & UINT64_C(3)) << 10; 9427| 0| break; 9428| 0| } 9429| 0| case ARM::PKHBT: ------------------ | Branch (9429:5): [True: 0, False: 2.24k] ------------------ 9430| 0| case ARM::PKHTB: { ------------------ | Branch (9430:5): [True: 0, False: 2.24k] ------------------ 9431| | // op: p 9432| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9433| 0| Value |= (op & UINT64_C(15)) << 28; 9434| | // op: Rd 9435| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9436| 0| Value |= (op & UINT64_C(15)) << 12; 9437| | // op: Rn 9438| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9439| 0| Value |= (op & UINT64_C(15)) << 16; 9440| | // op: Rm 9441| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9442| 0| Value |= op & UINT64_C(15); 9443| | // op: sh 9444| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9445| 0| Value |= (op & UINT64_C(31)) << 7; 9446| 0| break; 9447| 0| } 9448| 0| case ARM::SBFX: ------------------ | Branch (9448:5): [True: 0, False: 2.24k] ------------------ 9449| 0| case ARM::UBFX: { ------------------ | Branch (9449:5): [True: 0, False: 2.24k] ------------------ 9450| | // op: p 9451| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9452| 0| Value |= (op & UINT64_C(15)) << 28; 9453| | // op: Rd 9454| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9455| 0| Value |= (op & UINT64_C(15)) << 12; 9456| | // op: Rn 9457| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9458| 0| Value |= op & UINT64_C(15); 9459| | // op: lsb 9460| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9461| 0| Value |= (op & UINT64_C(31)) << 7; 9462| | // op: width 9463| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9464| 0| Value |= (op & UINT64_C(31)) << 16; 9465| 0| break; 9466| 0| } 9467| 0| case ARM::BFI: { ------------------ | Branch (9467:5): [True: 0, False: 2.24k] ------------------ 9468| | // op: p 9469| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9470| 0| Value |= (op & UINT64_C(15)) << 28; 9471| | // op: Rd 9472| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9473| 0| Value |= (op & UINT64_C(15)) << 12; 9474| | // op: Rn 9475| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9476| 0| Value |= op & UINT64_C(15); 9477| | // op: imm 9478| 0| op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 9479| 0| Value |= (op & UINT64_C(992)) << 11; 9480| 0| Value |= (op & UINT64_C(31)) << 7; 9481| 0| break; 9482| 0| } 9483| 0| case ARM::SSAT: ------------------ | Branch (9483:5): [True: 0, False: 2.24k] ------------------ 9484| 0| case ARM::USAT: { ------------------ | Branch (9484:5): [True: 0, False: 2.24k] ------------------ 9485| | // op: p 9486| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9487| 0| Value |= (op & UINT64_C(15)) << 28; 9488| | // op: Rd 9489| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9490| 0| Value |= (op & UINT64_C(15)) << 12; 9491| | // op: sat_imm 9492| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9493| 0| Value |= (op & UINT64_C(31)) << 16; 9494| | // op: Rn 9495| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9496| 0| Value |= op & UINT64_C(15); 9497| | // op: sh 9498| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9499| 0| Value |= (op & UINT64_C(31)) << 7; 9500| 0| Value |= (op & UINT64_C(32)) << 1; 9501| 0| break; 9502| 0| } 9503| 0| case ARM::MLS: { ------------------ | Branch (9503:5): [True: 0, False: 2.24k] ------------------ 9504| | // op: p 9505| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9506| 0| Value |= (op & UINT64_C(15)) << 28; 9507| | // op: Rd 9508| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9509| 0| Value |= (op & UINT64_C(15)) << 16; 9510| | // op: Rm 9511| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9512| 0| Value |= (op & UINT64_C(15)) << 8; 9513| | // op: Rn 9514| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9515| 0| Value |= op & UINT64_C(15); 9516| | // op: Ra 9517| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9518| 0| Value |= (op & UINT64_C(15)) << 12; 9519| 0| break; 9520| 0| } 9521| 0| case ARM::SMMLA: ------------------ | Branch (9521:5): [True: 0, False: 2.24k] ------------------ 9522| 0| case ARM::SMMLAR: ------------------ | Branch (9522:5): [True: 0, False: 2.24k] ------------------ 9523| 0| case ARM::SMMLS: ------------------ | Branch (9523:5): [True: 0, False: 2.24k] ------------------ 9524| 0| case ARM::SMMLSR: ------------------ | Branch (9524:5): [True: 0, False: 2.24k] ------------------ 9525| 0| case ARM::USADA8: { ------------------ | Branch (9525:5): [True: 0, False: 2.24k] ------------------ 9526| | // op: p 9527| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9528| 0| Value |= (op & UINT64_C(15)) << 28; 9529| | // op: Rd 9530| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9531| 0| Value |= (op & UINT64_C(15)) << 16; 9532| | // op: Rn 9533| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9534| 0| Value |= op & UINT64_C(15); 9535| | // op: Rm 9536| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9537| 0| Value |= (op & UINT64_C(15)) << 8; 9538| | // op: Ra 9539| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9540| 0| Value |= (op & UINT64_C(15)) << 12; 9541| 0| break; 9542| 0| } 9543| 0| case ARM::UMAAL: { ------------------ | Branch (9543:5): [True: 0, False: 2.24k] ------------------ 9544| | // op: p 9545| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9546| 0| Value |= (op & UINT64_C(15)) << 28; 9547| | // op: RdLo 9548| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9549| 0| Value |= (op & UINT64_C(15)) << 12; 9550| | // op: RdHi 9551| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9552| 0| Value |= (op & UINT64_C(15)) << 16; 9553| | // op: Rm 9554| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9555| 0| Value |= (op & UINT64_C(15)) << 8; 9556| | // op: Rn 9557| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9558| 0| Value |= op & UINT64_C(15); 9559| 0| break; 9560| 0| } 9561| 0| case ARM::CMNzrsr: ------------------ | Branch (9561:5): [True: 0, False: 2.24k] ------------------ 9562| 0| case ARM::CMPrsr: ------------------ | Branch (9562:5): [True: 0, False: 2.24k] ------------------ 9563| 0| case ARM::TEQrsr: ------------------ | Branch (9563:5): [True: 0, False: 2.24k] ------------------ 9564| 0| case ARM::TSTrsr: { ------------------ | Branch (9564:5): [True: 0, False: 2.24k] ------------------ 9565| | // op: p 9566| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9567| 0| Value |= (op & UINT64_C(15)) << 28; 9568| | // op: Rn 9569| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9570| 0| Value |= (op & UINT64_C(15)) << 16; 9571| | // op: shift 9572| 0| op = getSORegRegOpValue(MI, 1, Fixups, STI); 9573| 0| Value |= op & UINT64_C(3840); 9574| 0| Value |= op & UINT64_C(96); 9575| 0| Value |= op & UINT64_C(15); 9576| 0| break; 9577| 0| } 9578| 0| case ARM::SMLAD: ------------------ | Branch (9578:5): [True: 0, False: 2.24k] ------------------ 9579| 0| case ARM::SMLADX: ------------------ | Branch (9579:5): [True: 0, False: 2.24k] ------------------ 9580| 0| case ARM::SMLSD: ------------------ | Branch (9580:5): [True: 0, False: 2.24k] ------------------ 9581| 0| case ARM::SMLSDX: { ------------------ | Branch (9581:5): [True: 0, False: 2.24k] ------------------ 9582| | // op: p 9583| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9584| 0| Value |= (op & UINT64_C(15)) << 28; 9585| | // op: Rn 9586| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9587| 0| Value |= op & UINT64_C(15); 9588| | // op: Rm 9589| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9590| 0| Value |= (op & UINT64_C(15)) << 8; 9591| | // op: Ra 9592| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9593| 0| Value |= (op & UINT64_C(15)) << 12; 9594| | // op: Rd 9595| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9596| 0| Value |= (op & UINT64_C(15)) << 16; 9597| 0| break; 9598| 0| } 9599| 0| case ARM::SMLABB: ------------------ | Branch (9599:5): [True: 0, False: 2.24k] ------------------ 9600| 0| case ARM::SMLABT: ------------------ | Branch (9600:5): [True: 0, False: 2.24k] ------------------ 9601| 0| case ARM::SMLATB: ------------------ | Branch (9601:5): [True: 0, False: 2.24k] ------------------ 9602| 0| case ARM::SMLATT: ------------------ | Branch (9602:5): [True: 0, False: 2.24k] ------------------ 9603| 0| case ARM::SMLAWB: ------------------ | Branch (9603:5): [True: 0, False: 2.24k] ------------------ 9604| 0| case ARM::SMLAWT: { ------------------ | Branch (9604:5): [True: 0, False: 2.24k] ------------------ 9605| | // op: p 9606| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9607| 0| Value |= (op & UINT64_C(15)) << 28; 9608| | // op: Rn 9609| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9610| 0| Value |= op & UINT64_C(15); 9611| | // op: Rm 9612| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9613| 0| Value |= (op & UINT64_C(15)) << 8; 9614| | // op: Rd 9615| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9616| 0| Value |= (op & UINT64_C(15)) << 16; 9617| | // op: Ra 9618| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9619| 0| Value |= (op & UINT64_C(15)) << 12; 9620| 0| break; 9621| 0| } 9622| 0| case ARM::SMLALBB: ------------------ | Branch (9622:5): [True: 0, False: 2.24k] ------------------ 9623| 0| case ARM::SMLALBT: ------------------ | Branch (9623:5): [True: 0, False: 2.24k] ------------------ 9624| 0| case ARM::SMLALD: ------------------ | Branch (9624:5): [True: 0, False: 2.24k] ------------------ 9625| 0| case ARM::SMLALDX: ------------------ | Branch (9625:5): [True: 0, False: 2.24k] ------------------ 9626| 0| case ARM::SMLALTB: ------------------ | Branch (9626:5): [True: 0, False: 2.24k] ------------------ 9627| 0| case ARM::SMLALTT: ------------------ | Branch (9627:5): [True: 0, False: 2.24k] ------------------ 9628| 0| case ARM::SMLSLD: ------------------ | Branch (9628:5): [True: 0, False: 2.24k] ------------------ 9629| 0| case ARM::SMLSLDX: { ------------------ | Branch (9629:5): [True: 0, False: 2.24k] ------------------ 9630| | // op: p 9631| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9632| 0| Value |= (op & UINT64_C(15)) << 28; 9633| | // op: Rn 9634| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9635| 0| Value |= op & UINT64_C(15); 9636| | // op: Rm 9637| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9638| 0| Value |= (op & UINT64_C(15)) << 8; 9639| | // op: RdLo 9640| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9641| 0| Value |= (op & UINT64_C(15)) << 12; 9642| | // op: RdHi 9643| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9644| 0| Value |= (op & UINT64_C(15)) << 16; 9645| 0| break; 9646| 0| } 9647| 0| case ARM::LDRB_PRE_IMM: ------------------ | Branch (9647:5): [True: 0, False: 2.24k] ------------------ 9648| 0| case ARM::LDR_PRE_IMM: { ------------------ | Branch (9648:5): [True: 0, False: 2.24k] ------------------ 9649| | // op: p 9650| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9651| 0| Value |= (op & UINT64_C(15)) << 28; 9652| | // op: Rt 9653| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9654| 0| Value |= (op & UINT64_C(15)) << 12; 9655| | // op: addr 9656| 0| op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 9657| 0| Value |= (op & UINT64_C(4096)) << 11; 9658| 0| Value |= (op & UINT64_C(122880)) << 3; 9659| 0| Value |= op & UINT64_C(4095); 9660| 0| break; 9661| 0| } 9662| 0| case ARM::LDRBrs: ------------------ | Branch (9662:5): [True: 0, False: 2.24k] ------------------ 9663| 0| case ARM::LDRrs: ------------------ | Branch (9663:5): [True: 0, False: 2.24k] ------------------ 9664| 0| case ARM::STRBrs: ------------------ | Branch (9664:5): [True: 0, False: 2.24k] ------------------ 9665| 0| case ARM::STRrs: { ------------------ | Branch (9665:5): [True: 0, False: 2.24k] ------------------ 9666| | // op: p 9667| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9668| 0| Value |= (op & UINT64_C(15)) << 28; 9669| | // op: Rt 9670| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9671| 0| Value |= (op & UINT64_C(15)) << 12; 9672| | // op: shift 9673| 0| op = getLdStSORegOpValue(MI, 1, Fixups, STI); 9674| 0| Value |= (op & UINT64_C(4096)) << 11; 9675| 0| Value |= (op & UINT64_C(122880)) << 3; 9676| 0| Value |= op & UINT64_C(4064); 9677| 0| Value |= op & UINT64_C(15); 9678| 0| break; 9679| 0| } 9680| 0| case ARM::STRB_PRE_IMM: ------------------ | Branch (9680:5): [True: 0, False: 2.24k] ------------------ 9681| 0| case ARM::STR_PRE_IMM: { ------------------ | Branch (9681:5): [True: 0, False: 2.24k] ------------------ 9682| | // op: p 9683| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9684| 0| Value |= (op & UINT64_C(15)) << 28; 9685| | // op: Rt 9686| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9687| 0| Value |= (op & UINT64_C(15)) << 12; 9688| | // op: addr 9689| 0| op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 9690| 0| Value |= (op & UINT64_C(4096)) << 11; 9691| 0| Value |= (op & UINT64_C(122880)) << 3; 9692| 0| Value |= op & UINT64_C(4095); 9693| 0| break; 9694| 0| } 9695| 0| case ARM::VFMAH: ------------------ | Branch (9695:5): [True: 0, False: 2.24k] ------------------ 9696| 0| case ARM::VFMAS: ------------------ | Branch (9696:5): [True: 0, False: 2.24k] ------------------ 9697| 0| case ARM::VFMSH: ------------------ | Branch (9697:5): [True: 0, False: 2.24k] ------------------ 9698| 0| case ARM::VFMSS: ------------------ | Branch (9698:5): [True: 0, False: 2.24k] ------------------ 9699| 0| case ARM::VFNMAH: ------------------ | Branch (9699:5): [True: 0, False: 2.24k] ------------------ 9700| 0| case ARM::VFNMAS: ------------------ | Branch (9700:5): [True: 0, False: 2.24k] ------------------ 9701| 0| case ARM::VFNMSH: ------------------ | Branch (9701:5): [True: 0, False: 2.24k] ------------------ 9702| 0| case ARM::VFNMSS: ------------------ | Branch (9702:5): [True: 0, False: 2.24k] ------------------ 9703| 0| case ARM::VMLAH: ------------------ | Branch (9703:5): [True: 0, False: 2.24k] ------------------ 9704| 0| case ARM::VMLAS: ------------------ | Branch (9704:5): [True: 0, False: 2.24k] ------------------ 9705| 0| case ARM::VMLSH: ------------------ | Branch (9705:5): [True: 0, False: 2.24k] ------------------ 9706| 0| case ARM::VMLSS: ------------------ | Branch (9706:5): [True: 0, False: 2.24k] ------------------ 9707| 0| case ARM::VNMLAH: ------------------ | Branch (9707:5): [True: 0, False: 2.24k] ------------------ 9708| 0| case ARM::VNMLAS: ------------------ | Branch (9708:5): [True: 0, False: 2.24k] ------------------ 9709| 0| case ARM::VNMLSH: ------------------ | Branch (9709:5): [True: 0, False: 2.24k] ------------------ 9710| 0| case ARM::VNMLSS: { ------------------ | Branch (9710:5): [True: 0, False: 2.24k] ------------------ 9711| | // op: p 9712| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9713| 0| Value |= (op & UINT64_C(15)) << 28; 9714| | // op: Sd 9715| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9716| 0| Value |= (op & UINT64_C(1)) << 22; 9717| 0| Value |= (op & UINT64_C(30)) << 11; 9718| | // op: Sn 9719| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9720| 0| Value |= (op & UINT64_C(30)) << 15; 9721| 0| Value |= (op & UINT64_C(1)) << 7; 9722| | // op: Sm 9723| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9724| 0| Value |= (op & UINT64_C(1)) << 5; 9725| 0| Value |= (op & UINT64_C(30)) >> 1; 9726| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9727| 0| break; 9728| 0| } 9729| 0| case ARM::LDRH: ------------------ | Branch (9729:5): [True: 0, False: 2.24k] ------------------ 9730| 0| case ARM::LDRSB: ------------------ | Branch (9730:5): [True: 0, False: 2.24k] ------------------ 9731| 0| case ARM::LDRSH: ------------------ | Branch (9731:5): [True: 0, False: 2.24k] ------------------ 9732| 0| case ARM::STRH: { ------------------ | Branch (9732:5): [True: 0, False: 2.24k] ------------------ 9733| | // op: p 9734| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9735| 0| Value |= (op & UINT64_C(15)) << 28; 9736| | // op: addr 9737| 0| op = getAddrMode3OpValue(MI, 1, Fixups, STI); 9738| 0| Value |= (op & UINT64_C(256)) << 15; 9739| 0| Value |= (op & UINT64_C(8192)) << 9; 9740| 0| Value |= (op & UINT64_C(7680)) << 7; 9741| 0| Value |= (op & UINT64_C(240)) << 4; 9742| 0| Value |= op & UINT64_C(15); 9743| | // op: Rt 9744| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9745| 0| Value |= (op & UINT64_C(15)) << 12; 9746| 0| break; 9747| 0| } 9748| 0| case ARM::LDCL_OFFSET: ------------------ | Branch (9748:5): [True: 0, False: 2.24k] ------------------ 9749| 0| case ARM::LDCL_PRE: ------------------ | Branch (9749:5): [True: 0, False: 2.24k] ------------------ 9750| 0| case ARM::LDC_OFFSET: ------------------ | Branch (9750:5): [True: 0, False: 2.24k] ------------------ 9751| 0| case ARM::LDC_PRE: ------------------ | Branch (9751:5): [True: 0, False: 2.24k] ------------------ 9752| 0| case ARM::STCL_OFFSET: ------------------ | Branch (9752:5): [True: 0, False: 2.24k] ------------------ 9753| 0| case ARM::STCL_PRE: ------------------ | Branch (9753:5): [True: 0, False: 2.24k] ------------------ 9754| 0| case ARM::STC_OFFSET: ------------------ | Branch (9754:5): [True: 0, False: 2.24k] ------------------ 9755| 0| case ARM::STC_PRE: { ------------------ | Branch (9755:5): [True: 0, False: 2.24k] ------------------ 9756| | // op: p 9757| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9758| 0| Value |= (op & UINT64_C(15)) << 28; 9759| | // op: addr 9760| 0| op = getAddrMode5OpValue(MI, 2, Fixups, STI); 9761| 0| Value |= (op & UINT64_C(256)) << 15; 9762| 0| Value |= (op & UINT64_C(7680)) << 7; 9763| 0| Value |= op & UINT64_C(255); 9764| | // op: cop 9765| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9766| 0| Value |= (op & UINT64_C(15)) << 8; 9767| | // op: CRd 9768| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9769| 0| Value |= (op & UINT64_C(15)) << 12; 9770| 0| break; 9771| 0| } 9772| 0| case ARM::LDRHTi: ------------------ | Branch (9772:5): [True: 0, False: 2.24k] ------------------ 9773| 0| case ARM::LDRSBTi: ------------------ | Branch (9773:5): [True: 0, False: 2.24k] ------------------ 9774| 0| case ARM::LDRSHTi: { ------------------ | Branch (9774:5): [True: 0, False: 2.24k] ------------------ 9775| | // op: p 9776| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9777| 0| Value |= (op & UINT64_C(15)) << 28; 9778| | // op: addr 9779| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9780| 0| Value |= (op & UINT64_C(15)) << 16; 9781| | // op: Rt 9782| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9783| 0| Value |= (op & UINT64_C(15)) << 12; 9784| | // op: offset 9785| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9786| 0| Value |= (op & UINT64_C(256)) << 15; 9787| 0| Value |= (op & UINT64_C(240)) << 4; 9788| 0| Value |= op & UINT64_C(15); 9789| 0| break; 9790| 0| } 9791| 0| case ARM::STRHTi: { ------------------ | Branch (9791:5): [True: 0, False: 2.24k] ------------------ 9792| | // op: p 9793| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9794| 0| Value |= (op & UINT64_C(15)) << 28; 9795| | // op: addr 9796| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9797| 0| Value |= (op & UINT64_C(15)) << 16; 9798| | // op: Rt 9799| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9800| 0| Value |= (op & UINT64_C(15)) << 12; 9801| | // op: offset 9802| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9803| 0| Value |= (op & UINT64_C(256)) << 15; 9804| 0| Value |= (op & UINT64_C(240)) << 4; 9805| 0| Value |= op & UINT64_C(15); 9806| 0| break; 9807| 0| } 9808| 0| case ARM::VMOVSRR: { ------------------ | Branch (9808:5): [True: 0, False: 2.24k] ------------------ 9809| | // op: p 9810| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9811| 0| Value |= (op & UINT64_C(15)) << 28; 9812| | // op: dst1 9813| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9814| 0| Value |= (op & UINT64_C(1)) << 5; 9815| 0| Value |= (op & UINT64_C(30)) >> 1; 9816| | // op: src1 9817| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9818| 0| Value |= (op & UINT64_C(15)) << 12; 9819| | // op: src2 9820| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9821| 0| Value |= (op & UINT64_C(15)) << 16; 9822| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9823| 0| break; 9824| 0| } 9825| 0| case ARM::LDCL_POST: ------------------ | Branch (9825:5): [True: 0, False: 2.24k] ------------------ 9826| 0| case ARM::LDC_POST: ------------------ | Branch (9826:5): [True: 0, False: 2.24k] ------------------ 9827| 0| case ARM::STCL_POST: ------------------ | Branch (9827:5): [True: 0, False: 2.24k] ------------------ 9828| 0| case ARM::STC_POST: { ------------------ | Branch (9828:5): [True: 0, False: 2.24k] ------------------ 9829| | // op: p 9830| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9831| 0| Value |= (op & UINT64_C(15)) << 28; 9832| | // op: offset 9833| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9834| 0| Value |= (op & UINT64_C(256)) << 15; 9835| 0| Value |= op & UINT64_C(255); 9836| | // op: addr 9837| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9838| 0| Value |= (op & UINT64_C(15)) << 16; 9839| | // op: cop 9840| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9841| 0| Value |= (op & UINT64_C(15)) << 8; 9842| | // op: CRd 9843| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9844| 0| Value |= (op & UINT64_C(15)) << 12; 9845| 0| break; 9846| 0| } 9847| 0| case ARM::LDCL_OPTION: ------------------ | Branch (9847:5): [True: 0, False: 2.24k] ------------------ 9848| 0| case ARM::LDC_OPTION: ------------------ | Branch (9848:5): [True: 0, False: 2.24k] ------------------ 9849| 0| case ARM::STCL_OPTION: ------------------ | Branch (9849:5): [True: 0, False: 2.24k] ------------------ 9850| 0| case ARM::STC_OPTION: { ------------------ | Branch (9850:5): [True: 0, False: 2.24k] ------------------ 9851| | // op: p 9852| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9853| 0| Value |= (op & UINT64_C(15)) << 28; 9854| | // op: option 9855| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9856| 0| Value |= op & UINT64_C(255); 9857| | // op: addr 9858| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9859| 0| Value |= (op & UINT64_C(15)) << 16; 9860| | // op: cop 9861| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9862| 0| Value |= (op & UINT64_C(15)) << 8; 9863| | // op: CRd 9864| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9865| 0| Value |= (op & UINT64_C(15)) << 12; 9866| 0| break; 9867| 0| } 9868| 0| case ARM::ADCrsi: ------------------ | Branch (9868:5): [True: 0, False: 2.24k] ------------------ 9869| 0| case ARM::ADDrsi: ------------------ | Branch (9869:5): [True: 0, False: 2.24k] ------------------ 9870| 0| case ARM::ANDrsi: ------------------ | Branch (9870:5): [True: 0, False: 2.24k] ------------------ 9871| 0| case ARM::BICrsi: ------------------ | Branch (9871:5): [True: 0, False: 2.24k] ------------------ 9872| 0| case ARM::EORrsi: ------------------ | Branch (9872:5): [True: 0, False: 2.24k] ------------------ 9873| 0| case ARM::ORRrsi: ------------------ | Branch (9873:5): [True: 0, False: 2.24k] ------------------ 9874| 0| case ARM::RSBrsi: ------------------ | Branch (9874:5): [True: 0, False: 2.24k] ------------------ 9875| 0| case ARM::RSCrsi: ------------------ | Branch (9875:5): [True: 0, False: 2.24k] ------------------ 9876| 0| case ARM::SBCrsi: ------------------ | Branch (9876:5): [True: 0, False: 2.24k] ------------------ 9877| 0| case ARM::SUBrsi: { ------------------ | Branch (9877:5): [True: 0, False: 2.24k] ------------------ 9878| | // op: p 9879| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9880| 0| Value |= (op & UINT64_C(15)) << 28; 9881| | // op: s 9882| 0| op = getCCOutOpValue(MI, 6, Fixups, STI); 9883| 0| Value |= (op & UINT64_C(1)) << 20; 9884| | // op: Rd 9885| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9886| 0| Value |= (op & UINT64_C(15)) << 12; 9887| | // op: Rn 9888| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9889| 0| Value |= (op & UINT64_C(15)) << 16; 9890| | // op: shift 9891| 0| op = getSORegImmOpValue(MI, 2, Fixups, STI); 9892| 0| Value |= op & UINT64_C(4064); 9893| 0| Value |= op & UINT64_C(15); 9894| 0| break; 9895| 0| } 9896| 0| case ARM::MVNsr: { ------------------ | Branch (9896:5): [True: 0, False: 2.24k] ------------------ 9897| | // op: p 9898| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9899| 0| Value |= (op & UINT64_C(15)) << 28; 9900| | // op: s 9901| 0| op = getCCOutOpValue(MI, 6, Fixups, STI); 9902| 0| Value |= (op & UINT64_C(1)) << 20; 9903| | // op: Rd 9904| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9905| 0| Value |= (op & UINT64_C(15)) << 12; 9906| | // op: shift 9907| 0| op = getSORegRegOpValue(MI, 1, Fixups, STI); 9908| 0| Value |= op & UINT64_C(3840); 9909| 0| Value |= op & UINT64_C(96); 9910| 0| Value |= op & UINT64_C(15); 9911| 0| break; 9912| 0| } 9913| 0| case ARM::MOVsr: { ------------------ | Branch (9913:5): [True: 0, False: 2.24k] ------------------ 9914| | // op: p 9915| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9916| 0| Value |= (op & UINT64_C(15)) << 28; 9917| | // op: s 9918| 0| op = getCCOutOpValue(MI, 6, Fixups, STI); 9919| 0| Value |= (op & UINT64_C(1)) << 20; 9920| | // op: Rd 9921| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9922| 0| Value |= (op & UINT64_C(15)) << 12; 9923| | // op: src 9924| 0| op = getSORegRegOpValue(MI, 1, Fixups, STI); 9925| 0| Value |= op & UINT64_C(3840); 9926| 0| Value |= op & UINT64_C(96); 9927| 0| Value |= op & UINT64_C(15); 9928| 0| break; 9929| 0| } 9930| 0| case ARM::MLA: { ------------------ | Branch (9930:5): [True: 0, False: 2.24k] ------------------ 9931| | // op: p 9932| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9933| 0| Value |= (op & UINT64_C(15)) << 28; 9934| | // op: s 9935| 0| op = getCCOutOpValue(MI, 6, Fixups, STI); 9936| 0| Value |= (op & UINT64_C(1)) << 20; 9937| | // op: Rd 9938| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9939| 0| Value |= (op & UINT64_C(15)) << 16; 9940| | // op: Rm 9941| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9942| 0| Value |= (op & UINT64_C(15)) << 8; 9943| | // op: Rn 9944| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9945| 0| Value |= op & UINT64_C(15); 9946| | // op: Ra 9947| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9948| 0| Value |= (op & UINT64_C(15)) << 12; 9949| 0| break; 9950| 0| } 9951| 0| case ARM::SMULL: ------------------ | Branch (9951:5): [True: 0, False: 2.24k] ------------------ 9952| 0| case ARM::UMULL: { ------------------ | Branch (9952:5): [True: 0, False: 2.24k] ------------------ 9953| | // op: p 9954| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9955| 0| Value |= (op & UINT64_C(15)) << 28; 9956| | // op: s 9957| 0| op = getCCOutOpValue(MI, 6, Fixups, STI); 9958| 0| Value |= (op & UINT64_C(1)) << 20; 9959| | // op: RdLo 9960| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9961| 0| Value |= (op & UINT64_C(15)) << 12; 9962| | // op: RdHi 9963| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9964| 0| Value |= (op & UINT64_C(15)) << 16; 9965| | // op: Rm 9966| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9967| 0| Value |= (op & UINT64_C(15)) << 8; 9968| | // op: Rn 9969| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9970| 0| Value |= op & UINT64_C(15); 9971| 0| break; 9972| 0| } 9973| 0| case ARM::VMOVRRS: { ------------------ | Branch (9973:5): [True: 0, False: 2.24k] ------------------ 9974| | // op: p 9975| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9976| 0| Value |= (op & UINT64_C(15)) << 28; 9977| | // op: src1 9978| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9979| 0| Value |= (op & UINT64_C(1)) << 5; 9980| 0| Value |= (op & UINT64_C(30)) >> 1; 9981| | // op: Rt 9982| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9983| 0| Value |= (op & UINT64_C(15)) << 12; 9984| | // op: Rt2 9985| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9986| 0| Value |= (op & UINT64_C(15)) << 16; 9987| 0| Value = VFPThumb2PostEncoder(MI, Value, STI); 9988| 0| break; 9989| 0| } 9990| 0| case ARM::MRRC: { ------------------ | Branch (9990:5): [True: 0, False: 2.24k] ------------------ 9991| | // op: p 9992| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 9993| 0| Value |= (op & UINT64_C(15)) << 28; 9994| | // op: Rt 9995| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9996| 0| Value |= (op & UINT64_C(15)) << 12; 9997| | // op: Rt2 9998| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9999| 0| Value |= (op & UINT64_C(15)) << 16; 10000| | // op: cop 10001| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10002| 0| Value |= (op & UINT64_C(15)) << 8; 10003| | // op: opc1 10004| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10005| 0| Value |= (op & UINT64_C(15)) << 4; 10006| | // op: CRm 10007| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10008| 0| Value |= op & UINT64_C(15); 10009| 0| break; 10010| 0| } 10011| 0| case ARM::LDRH_PRE: ------------------ | Branch (10011:5): [True: 0, False: 2.24k] ------------------ 10012| 0| case ARM::LDRSB_PRE: ------------------ | Branch (10012:5): [True: 0, False: 2.24k] ------------------ 10013| 0| case ARM::LDRSH_PRE: { ------------------ | Branch (10013:5): [True: 0, False: 2.24k] ------------------ 10014| | // op: p 10015| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10016| 0| Value |= (op & UINT64_C(15)) << 28; 10017| | // op: Rt 10018| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10019| 0| Value |= (op & UINT64_C(15)) << 12; 10020| | // op: addr 10021| 0| op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10022| 0| Value |= (op & UINT64_C(256)) << 15; 10023| 0| Value |= (op & UINT64_C(8192)) << 9; 10024| 0| Value |= (op & UINT64_C(7680)) << 7; 10025| 0| Value |= (op & UINT64_C(240)) << 4; 10026| 0| Value |= op & UINT64_C(15); 10027| 0| break; 10028| 0| } 10029| 0| case ARM::LDRB_PRE_REG: ------------------ | Branch (10029:5): [True: 0, False: 2.24k] ------------------ 10030| 0| case ARM::LDR_PRE_REG: { ------------------ | Branch (10030:5): [True: 0, False: 2.24k] ------------------ 10031| | // op: p 10032| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10033| 0| Value |= (op & UINT64_C(15)) << 28; 10034| | // op: Rt 10035| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10036| 0| Value |= (op & UINT64_C(15)) << 12; 10037| | // op: addr 10038| 0| op = getLdStSORegOpValue(MI, 2, Fixups, STI); 10039| 0| Value |= (op & UINT64_C(4096)) << 11; 10040| 0| Value |= (op & UINT64_C(122880)) << 3; 10041| 0| Value |= op & UINT64_C(4064); 10042| 0| Value |= op & UINT64_C(15); 10043| 0| break; 10044| 0| } 10045| 0| case ARM::LDRBT_POST_REG: ------------------ | Branch (10045:5): [True: 0, False: 2.24k] ------------------ 10046| 0| case ARM::LDRB_POST_REG: ------------------ | Branch (10046:5): [True: 0, False: 2.24k] ------------------ 10047| 0| case ARM::LDRT_POST_REG: ------------------ | Branch (10047:5): [True: 0, False: 2.24k] ------------------ 10048| 0| case ARM::LDR_POST_REG: { ------------------ | Branch (10048:5): [True: 0, False: 2.24k] ------------------ 10049| | // op: p 10050| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10051| 0| Value |= (op & UINT64_C(15)) << 28; 10052| | // op: Rt 10053| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10054| 0| Value |= (op & UINT64_C(15)) << 12; 10055| | // op: offset 10056| 0| op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10057| 0| Value |= (op & UINT64_C(4096)) << 11; 10058| 0| Value |= op & UINT64_C(4064); 10059| 0| Value |= op & UINT64_C(15); 10060| | // op: addr 10061| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10062| 0| Value |= (op & UINT64_C(15)) << 16; 10063| 0| break; 10064| 0| } 10065| 0| case ARM::LDRBT_POST_IMM: ------------------ | Branch (10065:5): [True: 0, False: 2.24k] ------------------ 10066| 0| case ARM::LDRB_POST_IMM: ------------------ | Branch (10066:5): [True: 0, False: 2.24k] ------------------ 10067| 0| case ARM::LDRT_POST_IMM: ------------------ | Branch (10067:5): [True: 0, False: 2.24k] ------------------ 10068| 0| case ARM::LDR_POST_IMM: { ------------------ | Branch (10068:5): [True: 0, False: 2.24k] ------------------ 10069| | // op: p 10070| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10071| 0| Value |= (op & UINT64_C(15)) << 28; 10072| | // op: Rt 10073| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10074| 0| Value |= (op & UINT64_C(15)) << 12; 10075| | // op: offset 10076| 0| op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10077| 0| Value |= (op & UINT64_C(4096)) << 11; 10078| 0| Value |= op & UINT64_C(4095); 10079| | // op: addr 10080| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10081| 0| Value |= (op & UINT64_C(15)) << 16; 10082| 0| break; 10083| 0| } 10084| 0| case ARM::LDRH_POST: ------------------ | Branch (10084:5): [True: 0, False: 2.24k] ------------------ 10085| 0| case ARM::LDRSB_POST: ------------------ | Branch (10085:5): [True: 0, False: 2.24k] ------------------ 10086| 0| case ARM::LDRSH_POST: { ------------------ | Branch (10086:5): [True: 0, False: 2.24k] ------------------ 10087| | // op: p 10088| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10089| 0| Value |= (op & UINT64_C(15)) << 28; 10090| | // op: Rt 10091| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10092| 0| Value |= (op & UINT64_C(15)) << 12; 10093| | // op: offset 10094| 0| op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 10095| 0| Value |= (op & UINT64_C(256)) << 15; 10096| 0| Value |= (op & UINT64_C(512)) << 13; 10097| 0| Value |= (op & UINT64_C(240)) << 4; 10098| 0| Value |= op & UINT64_C(15); 10099| | // op: addr 10100| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10101| 0| Value |= (op & UINT64_C(15)) << 16; 10102| 0| break; 10103| 0| } 10104| 0| case ARM::STRH_PRE: { ------------------ | Branch (10104:5): [True: 0, False: 2.24k] ------------------ 10105| | // op: p 10106| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10107| 0| Value |= (op & UINT64_C(15)) << 28; 10108| | // op: Rt 10109| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10110| 0| Value |= (op & UINT64_C(15)) << 12; 10111| | // op: addr 10112| 0| op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10113| 0| Value |= (op & UINT64_C(256)) << 15; 10114| 0| Value |= (op & UINT64_C(8192)) << 9; 10115| 0| Value |= (op & UINT64_C(7680)) << 7; 10116| 0| Value |= (op & UINT64_C(240)) << 4; 10117| 0| Value |= op & UINT64_C(15); 10118| 0| break; 10119| 0| } 10120| 0| case ARM::STRB_PRE_REG: ------------------ | Branch (10120:5): [True: 0, False: 2.24k] ------------------ 10121| 0| case ARM::STR_PRE_REG: { ------------------ | Branch (10121:5): [True: 0, False: 2.24k] ------------------ 10122| | // op: p 10123| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10124| 0| Value |= (op & UINT64_C(15)) << 28; 10125| | // op: Rt 10126| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10127| 0| Value |= (op & UINT64_C(15)) << 12; 10128| | // op: addr 10129| 0| op = getLdStSORegOpValue(MI, 2, Fixups, STI); 10130| 0| Value |= (op & UINT64_C(4096)) << 11; 10131| 0| Value |= (op & UINT64_C(122880)) << 3; 10132| 0| Value |= op & UINT64_C(4064); 10133| 0| Value |= op & UINT64_C(15); 10134| 0| break; 10135| 0| } 10136| 0| case ARM::STRBT_POST_REG: ------------------ | Branch (10136:5): [True: 0, False: 2.24k] ------------------ 10137| 0| case ARM::STRB_POST_REG: ------------------ | Branch (10137:5): [True: 0, False: 2.24k] ------------------ 10138| 0| case ARM::STRT_POST_REG: ------------------ | Branch (10138:5): [True: 0, False: 2.24k] ------------------ 10139| 0| case ARM::STR_POST_REG: { ------------------ | Branch (10139:5): [True: 0, False: 2.24k] ------------------ 10140| | // op: p 10141| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10142| 0| Value |= (op & UINT64_C(15)) << 28; 10143| | // op: Rt 10144| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10145| 0| Value |= (op & UINT64_C(15)) << 12; 10146| | // op: offset 10147| 0| op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10148| 0| Value |= (op & UINT64_C(4096)) << 11; 10149| 0| Value |= op & UINT64_C(4064); 10150| 0| Value |= op & UINT64_C(15); 10151| | // op: addr 10152| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10153| 0| Value |= (op & UINT64_C(15)) << 16; 10154| 0| break; 10155| 0| } 10156| 0| case ARM::STRBT_POST_IMM: ------------------ | Branch (10156:5): [True: 0, False: 2.24k] ------------------ 10157| 0| case ARM::STRB_POST_IMM: ------------------ | Branch (10157:5): [True: 0, False: 2.24k] ------------------ 10158| 0| case ARM::STRT_POST_IMM: ------------------ | Branch (10158:5): [True: 0, False: 2.24k] ------------------ 10159| 0| case ARM::STR_POST_IMM: { ------------------ | Branch (10159:5): [True: 0, False: 2.24k] ------------------ 10160| | // op: p 10161| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10162| 0| Value |= (op & UINT64_C(15)) << 28; 10163| | // op: Rt 10164| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10165| 0| Value |= (op & UINT64_C(15)) << 12; 10166| | // op: offset 10167| 0| op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10168| 0| Value |= (op & UINT64_C(4096)) << 11; 10169| 0| Value |= op & UINT64_C(4095); 10170| | // op: addr 10171| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10172| 0| Value |= (op & UINT64_C(15)) << 16; 10173| 0| break; 10174| 0| } 10175| 0| case ARM::STRH_POST: { ------------------ | Branch (10175:5): [True: 0, False: 2.24k] ------------------ 10176| | // op: p 10177| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10178| 0| Value |= (op & UINT64_C(15)) << 28; 10179| | // op: Rt 10180| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10181| 0| Value |= (op & UINT64_C(15)) << 12; 10182| | // op: offset 10183| 0| op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 10184| 0| Value |= (op & UINT64_C(256)) << 15; 10185| 0| Value |= (op & UINT64_C(512)) << 13; 10186| 0| Value |= (op & UINT64_C(240)) << 4; 10187| 0| Value |= op & UINT64_C(15); 10188| | // op: addr 10189| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10190| 0| Value |= (op & UINT64_C(15)) << 16; 10191| 0| break; 10192| 0| } 10193| 0| case ARM::MCRR: { ------------------ | Branch (10193:5): [True: 0, False: 2.24k] ------------------ 10194| | // op: p 10195| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10196| 0| Value |= (op & UINT64_C(15)) << 28; 10197| | // op: Rt 10198| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10199| 0| Value |= (op & UINT64_C(15)) << 12; 10200| | // op: Rt2 10201| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10202| 0| Value |= (op & UINT64_C(15)) << 16; 10203| | // op: cop 10204| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10205| 0| Value |= (op & UINT64_C(15)) << 8; 10206| | // op: opc1 10207| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10208| 0| Value |= (op & UINT64_C(15)) << 4; 10209| | // op: CRm 10210| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10211| 0| Value |= op & UINT64_C(15); 10212| 0| break; 10213| 0| } 10214| 0| case ARM::LDRD: ------------------ | Branch (10214:5): [True: 0, False: 2.24k] ------------------ 10215| 0| case ARM::STRD: { ------------------ | Branch (10215:5): [True: 0, False: 2.24k] ------------------ 10216| | // op: p 10217| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10218| 0| Value |= (op & UINT64_C(15)) << 28; 10219| | // op: addr 10220| 0| op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10221| 0| Value |= (op & UINT64_C(256)) << 15; 10222| 0| Value |= (op & UINT64_C(8192)) << 9; 10223| 0| Value |= (op & UINT64_C(7680)) << 7; 10224| 0| Value |= (op & UINT64_C(240)) << 4; 10225| 0| Value |= op & UINT64_C(15); 10226| | // op: Rt 10227| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10228| 0| Value |= (op & UINT64_C(15)) << 12; 10229| 0| break; 10230| 0| } 10231| 0| case ARM::LDRHTr: ------------------ | Branch (10231:5): [True: 0, False: 2.24k] ------------------ 10232| 0| case ARM::LDRSBTr: ------------------ | Branch (10232:5): [True: 0, False: 2.24k] ------------------ 10233| 0| case ARM::LDRSHTr: { ------------------ | Branch (10233:5): [True: 0, False: 2.24k] ------------------ 10234| | // op: p 10235| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10236| 0| Value |= (op & UINT64_C(15)) << 28; 10237| | // op: addr 10238| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10239| 0| Value |= (op & UINT64_C(15)) << 16; 10240| | // op: Rt 10241| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10242| 0| Value |= (op & UINT64_C(15)) << 12; 10243| | // op: Rm 10244| 0| op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 10245| 0| Value |= (op & UINT64_C(16)) << 19; 10246| 0| Value |= op & UINT64_C(15); 10247| 0| break; 10248| 0| } 10249| 0| case ARM::STRHTr: { ------------------ | Branch (10249:5): [True: 0, False: 2.24k] ------------------ 10250| | // op: p 10251| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10252| 0| Value |= (op & UINT64_C(15)) << 28; 10253| | // op: addr 10254| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10255| 0| Value |= (op & UINT64_C(15)) << 16; 10256| | // op: Rt 10257| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10258| 0| Value |= (op & UINT64_C(15)) << 12; 10259| | // op: Rm 10260| 0| op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 10261| 0| Value |= (op & UINT64_C(16)) << 19; 10262| 0| Value |= op & UINT64_C(15); 10263| 0| break; 10264| 0| } 10265| 0| case ARM::ADCrsr: ------------------ | Branch (10265:5): [True: 0, False: 2.24k] ------------------ 10266| 0| case ARM::ADDrsr: ------------------ | Branch (10266:5): [True: 0, False: 2.24k] ------------------ 10267| 0| case ARM::ANDrsr: ------------------ | Branch (10267:5): [True: 0, False: 2.24k] ------------------ 10268| 0| case ARM::BICrsr: ------------------ | Branch (10268:5): [True: 0, False: 2.24k] ------------------ 10269| 0| case ARM::EORrsr: ------------------ | Branch (10269:5): [True: 0, False: 2.24k] ------------------ 10270| 0| case ARM::ORRrsr: ------------------ | Branch (10270:5): [True: 0, False: 2.24k] ------------------ 10271| 0| case ARM::RSBrsr: ------------------ | Branch (10271:5): [True: 0, False: 2.24k] ------------------ 10272| 0| case ARM::RSCrsr: ------------------ | Branch (10272:5): [True: 0, False: 2.24k] ------------------ 10273| 0| case ARM::SBCrsr: ------------------ | Branch (10273:5): [True: 0, False: 2.24k] ------------------ 10274| 0| case ARM::SUBrsr: { ------------------ | Branch (10274:5): [True: 0, False: 2.24k] ------------------ 10275| | // op: p 10276| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10277| 0| Value |= (op & UINT64_C(15)) << 28; 10278| | // op: s 10279| 0| op = getCCOutOpValue(MI, 7, Fixups, STI); 10280| 0| Value |= (op & UINT64_C(1)) << 20; 10281| | // op: Rd 10282| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10283| 0| Value |= (op & UINT64_C(15)) << 12; 10284| | // op: Rn 10285| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10286| 0| Value |= (op & UINT64_C(15)) << 16; 10287| | // op: shift 10288| 0| op = getSORegRegOpValue(MI, 2, Fixups, STI); 10289| 0| Value |= op & UINT64_C(3840); 10290| 0| Value |= op & UINT64_C(96); 10291| 0| Value |= op & UINT64_C(15); 10292| 0| break; 10293| 0| } 10294| 0| case ARM::LDRD_PRE: { ------------------ | Branch (10294:5): [True: 0, False: 2.24k] ------------------ 10295| | // op: p 10296| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10297| 0| Value |= (op & UINT64_C(15)) << 28; 10298| | // op: Rt 10299| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10300| 0| Value |= (op & UINT64_C(15)) << 12; 10301| | // op: addr 10302| 0| op = getAddrMode3OpValue(MI, 3, Fixups, STI); 10303| 0| Value |= (op & UINT64_C(256)) << 15; 10304| 0| Value |= (op & UINT64_C(8192)) << 9; 10305| 0| Value |= (op & UINT64_C(7680)) << 7; 10306| 0| Value |= (op & UINT64_C(240)) << 4; 10307| 0| Value |= op & UINT64_C(15); 10308| 0| break; 10309| 0| } 10310| 0| case ARM::MRC: { ------------------ | Branch (10310:5): [True: 0, False: 2.24k] ------------------ 10311| | // op: p 10312| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10313| 0| Value |= (op & UINT64_C(15)) << 28; 10314| | // op: Rt 10315| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10316| 0| Value |= (op & UINT64_C(15)) << 12; 10317| | // op: cop 10318| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10319| 0| Value |= (op & UINT64_C(15)) << 8; 10320| | // op: opc1 10321| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10322| 0| Value |= (op & UINT64_C(7)) << 21; 10323| | // op: opc2 10324| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10325| 0| Value |= (op & UINT64_C(7)) << 5; 10326| | // op: CRm 10327| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10328| 0| Value |= op & UINT64_C(15); 10329| | // op: CRn 10330| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10331| 0| Value |= (op & UINT64_C(15)) << 16; 10332| 0| break; 10333| 0| } 10334| 0| case ARM::LDRD_POST: { ------------------ | Branch (10334:5): [True: 0, False: 2.24k] ------------------ 10335| | // op: p 10336| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10337| 0| Value |= (op & UINT64_C(15)) << 28; 10338| | // op: Rt 10339| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10340| 0| Value |= (op & UINT64_C(15)) << 12; 10341| | // op: offset 10342| 0| op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 10343| 0| Value |= (op & UINT64_C(256)) << 15; 10344| 0| Value |= (op & UINT64_C(512)) << 13; 10345| 0| Value |= (op & UINT64_C(240)) << 4; 10346| 0| Value |= op & UINT64_C(15); 10347| | // op: addr 10348| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10349| 0| Value |= (op & UINT64_C(15)) << 16; 10350| 0| break; 10351| 0| } 10352| 0| case ARM::STRD_PRE: { ------------------ | Branch (10352:5): [True: 0, False: 2.24k] ------------------ 10353| | // op: p 10354| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10355| 0| Value |= (op & UINT64_C(15)) << 28; 10356| | // op: Rt 10357| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10358| 0| Value |= (op & UINT64_C(15)) << 12; 10359| | // op: addr 10360| 0| op = getAddrMode3OpValue(MI, 3, Fixups, STI); 10361| 0| Value |= (op & UINT64_C(256)) << 15; 10362| 0| Value |= (op & UINT64_C(8192)) << 9; 10363| 0| Value |= (op & UINT64_C(7680)) << 7; 10364| 0| Value |= (op & UINT64_C(240)) << 4; 10365| 0| Value |= op & UINT64_C(15); 10366| 0| break; 10367| 0| } 10368| 0| case ARM::STRD_POST: { ------------------ | Branch (10368:5): [True: 0, False: 2.24k] ------------------ 10369| | // op: p 10370| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10371| 0| Value |= (op & UINT64_C(15)) << 28; 10372| | // op: Rt 10373| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10374| 0| Value |= (op & UINT64_C(15)) << 12; 10375| | // op: offset 10376| 0| op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 10377| 0| Value |= (op & UINT64_C(256)) << 15; 10378| 0| Value |= (op & UINT64_C(512)) << 13; 10379| 0| Value |= (op & UINT64_C(240)) << 4; 10380| 0| Value |= op & UINT64_C(15); 10381| | // op: addr 10382| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10383| 0| Value |= (op & UINT64_C(15)) << 16; 10384| 0| break; 10385| 0| } 10386| 0| case ARM::MCR: { ------------------ | Branch (10386:5): [True: 0, False: 2.24k] ------------------ 10387| | // op: p 10388| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10389| 0| Value |= (op & UINT64_C(15)) << 28; 10390| | // op: Rt 10391| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10392| 0| Value |= (op & UINT64_C(15)) << 12; 10393| | // op: cop 10394| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10395| 0| Value |= (op & UINT64_C(15)) << 8; 10396| | // op: opc1 10397| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10398| 0| Value |= (op & UINT64_C(7)) << 21; 10399| | // op: opc2 10400| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10401| 0| Value |= (op & UINT64_C(7)) << 5; 10402| | // op: CRm 10403| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10404| 0| Value |= op & UINT64_C(15); 10405| | // op: CRn 10406| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10407| 0| Value |= (op & UINT64_C(15)) << 16; 10408| 0| break; 10409| 0| } 10410| 0| case ARM::CDP: { ------------------ | Branch (10410:5): [True: 0, False: 2.24k] ------------------ 10411| | // op: p 10412| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10413| 0| Value |= (op & UINT64_C(15)) << 28; 10414| | // op: opc1 10415| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10416| 0| Value |= (op & UINT64_C(15)) << 20; 10417| | // op: CRn 10418| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10419| 0| Value |= (op & UINT64_C(15)) << 16; 10420| | // op: CRd 10421| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10422| 0| Value |= (op & UINT64_C(15)) << 12; 10423| | // op: cop 10424| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10425| 0| Value |= (op & UINT64_C(15)) << 8; 10426| | // op: opc2 10427| 0| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10428| 0| Value |= (op & UINT64_C(7)) << 5; 10429| | // op: CRm 10430| 0| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10431| 0| Value |= op & UINT64_C(15); 10432| 0| break; 10433| 0| } 10434| 0| case ARM::SMLAL: ------------------ | Branch (10434:5): [True: 0, False: 2.24k] ------------------ 10435| 0| case ARM::UMLAL: { ------------------ | Branch (10435:5): [True: 0, False: 2.24k] ------------------ 10436| | // op: p 10437| 0| op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10438| 0| Value |= (op & UINT64_C(15)) << 28; 10439| | // op: s 10440| 0| op = getCCOutOpValue(MI, 8, Fixups, STI); 10441| 0| Value |= (op & UINT64_C(1)) << 20; 10442| | // op: RdLo 10443| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10444| 0| Value |= (op & UINT64_C(15)) << 12; 10445| | // op: RdHi 10446| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10447| 0| Value |= (op & UINT64_C(15)) << 16; 10448| | // op: Rm 10449| 0| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10450| 0| Value |= (op & UINT64_C(15)) << 8; 10451| | // op: Rn 10452| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10453| 0| Value |= op & UINT64_C(15); 10454| 0| break; 10455| 0| } 10456| 0| case ARM::tPUSH: { ------------------ | Branch (10456:5): [True: 0, False: 2.24k] ------------------ 10457| | // op: regs 10458| 0| op = getRegisterListOpValue(MI, 2, Fixups, STI); 10459| 0| Value |= (op & UINT64_C(16384)) >> 6; 10460| 0| Value |= op & UINT64_C(255); 10461| 0| break; 10462| 0| } 10463| 0| case ARM::tPOP: { ------------------ | Branch (10463:5): [True: 0, False: 2.24k] ------------------ 10464| | // op: regs 10465| 0| op = getRegisterListOpValue(MI, 2, Fixups, STI); 10466| 0| Value |= (op & UINT64_C(32768)) >> 7; 10467| 0| Value |= op & UINT64_C(255); 10468| 0| break; 10469| 0| } 10470| 0| case ARM::t2MOVr: ------------------ | Branch (10470:5): [True: 0, False: 2.24k] ------------------ 10471| 0| case ARM::t2MVNr: ------------------ | Branch (10471:5): [True: 0, False: 2.24k] ------------------ 10472| 0| case ARM::t2RRX: { ------------------ | Branch (10472:5): [True: 0, False: 2.24k] ------------------ 10473| | // op: s 10474| 0| op = getCCOutOpValue(MI, 4, Fixups, STI); 10475| 0| Value |= (op & UINT64_C(1)) << 20; 10476| | // op: Rd 10477| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10478| 0| Value |= (op & UINT64_C(15)) << 8; 10479| | // op: Rm 10480| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10481| 0| Value |= op & UINT64_C(15); 10482| 0| break; 10483| 0| } 10484| 0| case ARM::t2MOVi: ------------------ | Branch (10484:5): [True: 0, False: 2.24k] ------------------ 10485| 0| case ARM::t2MVNi: { ------------------ | Branch (10485:5): [True: 0, False: 2.24k] ------------------ 10486| | // op: s 10487| 0| op = getCCOutOpValue(MI, 4, Fixups, STI); 10488| 0| Value |= (op & UINT64_C(1)) << 20; 10489| | // op: Rd 10490| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10491| 0| Value |= (op & UINT64_C(15)) << 8; 10492| | // op: imm 10493| 0| op = getT2SOImmOpValue(MI, 1, Fixups, STI); 10494| 0| Value |= (op & UINT64_C(2048)) << 15; 10495| 0| Value |= (op & UINT64_C(1792)) << 4; 10496| 0| Value |= op & UINT64_C(255); 10497| 0| break; 10498| 0| } 10499| 2| case ARM::t2ASRri: ------------------ | Branch (10499:5): [True: 2, False: 2.23k] ------------------ 10500| 2| case ARM::t2LSLri: ------------------ | Branch (10500:5): [True: 0, False: 2.24k] ------------------ 10501| 3| case ARM::t2LSRri: ------------------ | Branch (10501:5): [True: 1, False: 2.23k] ------------------ 10502| 3| case ARM::t2RORri: { ------------------ | Branch (10502:5): [True: 0, False: 2.24k] ------------------ 10503| | // op: s 10504| 3| op = getCCOutOpValue(MI, 5, Fixups, STI); 10505| 3| Value |= (op & UINT64_C(1)) << 20; 10506| | // op: Rd 10507| 3| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10508| 3| Value |= (op & UINT64_C(15)) << 8; 10509| | // op: Rm 10510| 3| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10511| 3| Value |= op & UINT64_C(15); 10512| | // op: imm 10513| 3| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10514| 3| Value |= (op & UINT64_C(28)) << 10; 10515| 3| Value |= (op & UINT64_C(3)) << 6; 10516| 3| break; 10517| 3| } 10518| 0| case ARM::t2ADCrr: ------------------ | Branch (10518:5): [True: 0, False: 2.24k] ------------------ 10519| 0| case ARM::t2ADDrr: ------------------ | Branch (10519:5): [True: 0, False: 2.24k] ------------------ 10520| 0| case ARM::t2ANDrr: ------------------ | Branch (10520:5): [True: 0, False: 2.24k] ------------------ 10521| 0| case ARM::t2ASRrr: ------------------ | Branch (10521:5): [True: 0, False: 2.24k] ------------------ 10522| 0| case ARM::t2BICrr: ------------------ | Branch (10522:5): [True: 0, False: 2.24k] ------------------ 10523| 0| case ARM::t2EORrr: ------------------ | Branch (10523:5): [True: 0, False: 2.24k] ------------------ 10524| 0| case ARM::t2LSLrr: ------------------ | Branch (10524:5): [True: 0, False: 2.24k] ------------------ 10525| 0| case ARM::t2LSRrr: ------------------ | Branch (10525:5): [True: 0, False: 2.24k] ------------------ 10526| 0| case ARM::t2ORNrr: ------------------ | Branch (10526:5): [True: 0, False: 2.24k] ------------------ 10527| 0| case ARM::t2ORRrr: ------------------ | Branch (10527:5): [True: 0, False: 2.24k] ------------------ 10528| 0| case ARM::t2RORrr: ------------------ | Branch (10528:5): [True: 0, False: 2.24k] ------------------ 10529| 0| case ARM::t2RSBrr: ------------------ | Branch (10529:5): [True: 0, False: 2.24k] ------------------ 10530| 0| case ARM::t2SBCrr: ------------------ | Branch (10530:5): [True: 0, False: 2.24k] ------------------ 10531| 0| case ARM::t2SUBrr: { ------------------ | Branch (10531:5): [True: 0, False: 2.24k] ------------------ 10532| | // op: s 10533| 0| op = getCCOutOpValue(MI, 5, Fixups, STI); 10534| 0| Value |= (op & UINT64_C(1)) << 20; 10535| | // op: Rd 10536| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10537| 0| Value |= (op & UINT64_C(15)) << 8; 10538| | // op: Rn 10539| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10540| 0| Value |= (op & UINT64_C(15)) << 16; 10541| | // op: Rm 10542| 0| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10543| 0| Value |= op & UINT64_C(15); 10544| 0| break; 10545| 0| } 10546| 0| case ARM::t2ADCri: ------------------ | Branch (10546:5): [True: 0, False: 2.24k] ------------------ 10547| 44| case ARM::t2ADDri: ------------------ | Branch (10547:5): [True: 44, False: 2.19k] ------------------ 10548| 44| case ARM::t2ANDri: ------------------ | Branch (10548:5): [True: 0, False: 2.24k] ------------------ 10549| 44| case ARM::t2BICri: ------------------ | Branch (10549:5): [True: 0, False: 2.24k] ------------------ 10550| 44| case ARM::t2EORri: ------------------ | Branch (10550:5): [True: 0, False: 2.24k] ------------------ 10551| 44| case ARM::t2ORNri: ------------------ | Branch (10551:5): [True: 0, False: 2.24k] ------------------ 10552| 44| case ARM::t2ORRri: ------------------ | Branch (10552:5): [True: 0, False: 2.24k] ------------------ 10553| 44| case ARM::t2RSBri: ------------------ | Branch (10553:5): [True: 0, False: 2.24k] ------------------ 10554| 44| case ARM::t2SBCri: ------------------ | Branch (10554:5): [True: 0, False: 2.24k] ------------------ 10555| 318| case ARM::t2SUBri: { ------------------ | Branch (10555:5): [True: 274, False: 1.96k] ------------------ 10556| | // op: s 10557| 318| op = getCCOutOpValue(MI, 5, Fixups, STI); 10558| 318| Value |= (op & UINT64_C(1)) << 20; 10559| | // op: Rd 10560| 318| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10561| 318| Value |= (op & UINT64_C(15)) << 8; 10562| | // op: Rn 10563| 318| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10564| 318| Value |= (op & UINT64_C(15)) << 16; 10565| | // op: imm 10566| 318| op = getT2SOImmOpValue(MI, 2, Fixups, STI); 10567| 318| Value |= (op & UINT64_C(2048)) << 15; 10568| 318| Value |= (op & UINT64_C(1792)) << 4; 10569| 318| Value |= op & UINT64_C(255); 10570| 318| break; 10571| 44| } 10572| 0| case ARM::t2MVNs: { ------------------ | Branch (10572:5): [True: 0, False: 2.24k] ------------------ 10573| | // op: s 10574| 0| op = getCCOutOpValue(MI, 5, Fixups, STI); 10575| 0| Value |= (op & UINT64_C(1)) << 20; 10576| | // op: Rd 10577| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10578| 0| Value |= (op & UINT64_C(15)) << 8; 10579| | // op: ShiftedRm 10580| 0| op = getT2SORegOpValue(MI, 1, Fixups, STI); 10581| 0| Value |= (op & UINT64_C(3584)) << 3; 10582| 0| Value |= (op & UINT64_C(480)) >> 1; 10583| 0| Value |= op & UINT64_C(15); 10584| 0| break; 10585| 44| } 10586| 0| case ARM::t2ADCrs: ------------------ | Branch (10586:5): [True: 0, False: 2.24k] ------------------ 10587| 0| case ARM::t2ADDrs: ------------------ | Branch (10587:5): [True: 0, False: 2.24k] ------------------ 10588| 0| case ARM::t2ANDrs: ------------------ | Branch (10588:5): [True: 0, False: 2.24k] ------------------ 10589| 0| case ARM::t2BICrs: ------------------ | Branch (10589:5): [True: 0, False: 2.24k] ------------------ 10590| 0| case ARM::t2EORrs: ------------------ | Branch (10590:5): [True: 0, False: 2.24k] ------------------ 10591| 0| case ARM::t2ORNrs: ------------------ | Branch (10591:5): [True: 0, False: 2.24k] ------------------ 10592| 0| case ARM::t2ORRrs: ------------------ | Branch (10592:5): [True: 0, False: 2.24k] ------------------ 10593| 0| case ARM::t2RSBrs: ------------------ | Branch (10593:5): [True: 0, False: 2.24k] ------------------ 10594| 0| case ARM::t2SBCrs: ------------------ | Branch (10594:5): [True: 0, False: 2.24k] ------------------ 10595| 0| case ARM::t2SUBrs: { ------------------ | Branch (10595:5): [True: 0, False: 2.24k] ------------------ 10596| | // op: s 10597| 0| op = getCCOutOpValue(MI, 6, Fixups, STI); 10598| 0| Value |= (op & UINT64_C(1)) << 20; 10599| | // op: Rd 10600| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10601| 0| Value |= (op & UINT64_C(15)) << 8; 10602| | // op: Rn 10603| 0| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10604| 0| Value |= (op & UINT64_C(15)) << 16; 10605| | // op: ShiftedRm 10606| 0| op = getT2SORegOpValue(MI, 2, Fixups, STI); 10607| 0| Value |= (op & UINT64_C(3584)) << 3; 10608| 0| Value |= (op & UINT64_C(480)) >> 1; 10609| 0| Value |= op & UINT64_C(15); 10610| 0| break; 10611| 0| } 10612| 0| case ARM::PLDWrs: ------------------ | Branch (10612:5): [True: 0, False: 2.24k] ------------------ 10613| 0| case ARM::PLDrs: ------------------ | Branch (10613:5): [True: 0, False: 2.24k] ------------------ 10614| 0| case ARM::PLIrs: { ------------------ | Branch (10614:5): [True: 0, False: 2.24k] ------------------ 10615| | // op: shift 10616| 0| op = getLdStSORegOpValue(MI, 0, Fixups, STI); 10617| 0| Value |= (op & UINT64_C(4096)) << 11; 10618| 0| Value |= (op & UINT64_C(122880)) << 3; 10619| 0| Value |= op & UINT64_C(4064); 10620| 0| Value |= op & UINT64_C(15); 10621| 0| break; 10622| 0| } 10623| 1| case ARM::BLXi: { ------------------ | Branch (10623:5): [True: 1, False: 2.23k] ------------------ 10624| | // op: target 10625| 1| op = getARMBLXTargetOpValue(MI, 0, Fixups, STI); 10626| 1| Value |= (op & UINT64_C(1)) << 24; 10627| 1| Value |= (op & UINT64_C(33554430)) >> 1; 10628| 1| break; 10629| 0| } 10630| 279| case ARM::tB: { ------------------ | Branch (10630:5): [True: 279, False: 1.96k] ------------------ 10631| | // op: target 10632| 279| op = getThumbBRTargetOpValue(MI, 0, Fixups, STI); 10633| 279| Value |= op & UINT64_C(2047); 10634| 279| break; 10635| 0| } 10636| 0| case ARM::tCBNZ: ------------------ | Branch (10636:5): [True: 0, False: 2.24k] ------------------ 10637| 0| case ARM::tCBZ: { ------------------ | Branch (10637:5): [True: 0, False: 2.24k] ------------------ 10638| | // op: target 10639| 0| op = getThumbCBTargetOpValue(MI, 1, Fixups, STI); 10640| 0| Value |= (op & UINT64_C(32)) << 4; 10641| 0| Value |= (op & UINT64_C(31)) << 3; 10642| | // op: Rn 10643| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10644| 0| Value |= op & UINT64_C(7); 10645| 0| break; 10646| 0| } 10647| 64| case ARM::t2B: { ------------------ | Branch (10647:5): [True: 64, False: 2.17k] ------------------ 10648| | // op: target 10649| 64| op = getUnconditionalBranchTargetOpValue(MI, 0, Fixups, STI); 10650| 64| Value |= (op & UINT64_C(8388608)) << 3; 10651| 64| Value |= (op & UINT64_C(2095104)) << 5; 10652| 64| Value |= (op & UINT64_C(4194304)) >> 9; 10653| 64| Value |= (op & UINT64_C(2097152)) >> 10; 10654| 64| Value |= op & UINT64_C(2047); 10655| 64| break; 10656| 0| } 10657| 0| case ARM::BKPT: ------------------ | Branch (10657:5): [True: 0, False: 2.24k] ------------------ 10658| 0| case ARM::HLT: { ------------------ | Branch (10658:5): [True: 0, False: 2.24k] ------------------ 10659| | // op: val 10660| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10661| 0| Value |= (op & UINT64_C(65520)) << 4; 10662| 0| Value |= op & UINT64_C(15); 10663| 0| break; 10664| 0| } 10665| 0| case ARM::tBKPT: { ------------------ | Branch (10665:5): [True: 0, False: 2.24k] ------------------ 10666| | // op: val 10667| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10668| 0| Value |= op & UINT64_C(255); 10669| 0| break; 10670| 0| } 10671| 0| case ARM::tHLT: { ------------------ | Branch (10671:5): [True: 0, False: 2.24k] ------------------ 10672| | // op: val 10673| 0| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10674| 0| Value |= op & UINT64_C(63); 10675| 0| break; 10676| 0| } 10677| 0| default: ------------------ | Branch (10677:3): [True: 0, False: 2.24k] ------------------ 10678| 0| std::string msg; 10679| 0| raw_string_ostream Msg(msg); 10680| 0| Msg << "Not supported instr: " << MI; 10681| 0| report_fatal_error(Msg.str()); 10682| 2.24k| } 10683| 2.24k| return Value; 10684| 2.24k|} ARMMCTargetDesc.cpp:_ZN7llvm_ksL21InitARMMCRegisterInfoEPNS_14MCRegisterInfoEjjjj: 3195| 430|static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { 3196| 430| RI->InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 100, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57, 3197| 430|ARMSubRegIdxRanges, ARMRegEncodingTable); 3198| | 3199| 430| switch (DwarfFlavour) { 3200| 0| default: ------------------ | Branch (3200:3): [True: 0, False: 430] ------------------ 3201| 0| llvm_unreachable("Unknown DWARF flavour"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 3202| 430| case 0: ------------------ | Branch (3202:3): [True: 430, False: 0] ------------------ 3203| 430| RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false); 3204| 430| break; 3205| 430| } 3206| 430| switch (EHFlavour) { 3207| 0| default: ------------------ | Branch (3207:3): [True: 0, False: 430] ------------------ 3208| 0| llvm_unreachable("Unknown DWARF flavour"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 3209| 430| case 0: ------------------ | Branch (3209:3): [True: 430, False: 0] ------------------ 3210| 430| RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true); 3211| 430| break; 3212| 430| } 3213| 430| switch (DwarfFlavour) { 3214| 0| default: ------------------ | Branch (3214:3): [True: 0, False: 430] ------------------ 3215| 0| llvm_unreachable("Unknown DWARF flavour"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 3216| 430| case 0: ------------------ | Branch (3216:3): [True: 430, False: 0] ------------------ 3217| 430| RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false); 3218| 430| break; 3219| 430| } 3220| 430| switch (EHFlavour) { 3221| 0| default: ------------------ | Branch (3221:3): [True: 0, False: 430] ------------------ 3222| 0| llvm_unreachable("Unknown DWARF flavour"); ------------------ | | 99| 0| ::llvm_ks::llvm_unreachable_internal(msg, __FILE__, __LINE__) ------------------ 3223| 430| case 0: ------------------ | Branch (3223:3): [True: 430, False: 0] ------------------ 3224| 430| RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true); 3225| 430| break; 3226| 430| } 3227| 430|} ARMMCTargetDesc.cpp:_ZN7llvm_ksL28createARMMCSubtargetInfoImplERKNS_6TripleENS_9StringRefES3_: 339| 860|static inline MCSubtargetInfo *createARMMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) { 340| | return new MCSubtargetInfo(TT, CPU, FS, ARMFeatureKV, ARMSubTypeKV, NULL); 341| 860|} LLVMInitializeARMAsmParser: 10210| 1|extern "C" void LLVMInitializeARMAsmParser() { 10211| 1| RegisterMCAsmParser X(TheARMLETarget); 10212| 1| RegisterMCAsmParser Y(TheARMBETarget); 10213| 1| RegisterMCAsmParser A(TheThumbLETarget); 10214| 1| RegisterMCAsmParser B(TheThumbBETarget); 10215| 1|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParserC2ERKN7llvm_ks15MCSubtargetInfoERNS1_11MCAsmParserERKNS1_11MCInstrInfoERKNS1_15MCTargetOptionsE: 364| 430| : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) { 365| 430| MCAsmParserExtension::Initialize(Parser); 366| | 367| 430| MCStreamer &S = getParser().getStreamer(); 368| 430| if (S.getTargetStreamer() == nullptr) ------------------ | Branch (368:9): [True: 430, False: 0] ------------------ 369| 430| new ARMTargetStreamer(S); 370| | 371| | // Cache the MCRegisterInfo. 372| 430| MRI = getContext().getRegisterInfo(); 373| | 374| | // Initialize the set of available features. 375| 430| setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 376| | 377| | // Not in an ITBlock to start with. 378| 430| ITState.CurPosition = ~0U; 379| | 380| 430| NextSymbolIsThumb = false; 381| 430| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_113UnwindContextC2ERN7llvm_ks11MCAsmParserE: 73| 430| UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser16tryParseRegisterEv: 2980| 16.5k|int ARMAsmParser::tryParseRegister() { 2981| 16.5k| MCAsmParser &Parser = getParser(); 2982| 16.5k| const AsmToken &Tok = Parser.getTok(); 2983| 16.5k| if (Tok.isNot(AsmToken::Identifier)) return -1; ------------------ | Branch (2983:7): [True: 1, False: 16.5k] ------------------ 2984| | 2985| 16.5k| std::string lowerCase = Tok.getString().lower(); 2986| 16.5k| unsigned RegNum = MatchRegisterName(lowerCase); 2987| 16.5k| if (!RegNum) { ------------------ | Branch (2987:7): [True: 15.2k, False: 1.31k] ------------------ 2988| 15.2k| RegNum = StringSwitch(lowerCase) 2989| 15.2k| .Case("r13", ARM::SP) 2990| 15.2k| .Case("r14", ARM::LR) 2991| 15.2k| .Case("r15", ARM::PC) 2992| 15.2k| .Case("ip", ARM::R12) 2993| | // Additional register name aliases for 'gas' compatibility. 2994| 15.2k| .Case("a1", ARM::R0) 2995| 15.2k| .Case("a2", ARM::R1) 2996| 15.2k| .Case("a3", ARM::R2) 2997| 15.2k| .Case("a4", ARM::R3) 2998| 15.2k| .Case("v1", ARM::R4) 2999| 15.2k| .Case("v2", ARM::R5) 3000| 15.2k| .Case("v3", ARM::R6) 3001| 15.2k| .Case("v4", ARM::R7) 3002| 15.2k| .Case("v5", ARM::R8) 3003| 15.2k| .Case("v6", ARM::R9) 3004| 15.2k| .Case("v7", ARM::R10) 3005| 15.2k| .Case("v8", ARM::R11) 3006| 15.2k| .Case("sb", ARM::R9) 3007| 15.2k| .Case("sl", ARM::R10) 3008| 15.2k| .Case("fp", ARM::R11) 3009| 15.2k| .Default(0); 3010| 15.2k| } 3011| 16.5k| if (!RegNum) { ------------------ | Branch (3011:7): [True: 13.6k, False: 2.96k] ------------------ 3012| | // Check for aliases registered via .req. Canonicalize to lower case. 3013| | // That's more consistent since register names are case insensitive, and 3014| | // it's how the original entry was passed in from MC/MCParser/AsmParser. 3015| 13.6k| StringMap::const_iterator Entry = RegisterReqs.find(lowerCase); 3016| | // If no match, return failure. 3017| 13.6k| if (Entry == RegisterReqs.end()) ------------------ | Branch (3017:9): [True: 13.6k, False: 0] ------------------ 3018| 13.6k| return -1; 3019| 0| Parser.Lex(); // Eat identifier token. 3020| 0| return Entry->getValue(); 3021| 13.6k| } 3022| | 3023| | // Some FPUs only have 16 D registers, so D16-D31 are invalid 3024| 2.96k| if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31) ------------------ | Branch (3024:7): [True: 0, False: 2.96k] | Branch (3024:19): [True: 0, False: 0] | Branch (3024:41): [True: 0, False: 0] ------------------ 3025| 0| return -1; 3026| | 3027| 2.96k| Parser.Lex(); // Eat identifier token. 3028| | 3029| 2.96k| return RegNum; 3030| 2.96k|} ARMAsmParser.cpp:_ZNK12_GLOBAL__N_112ARMAsmParser6hasD16Ev: 288| 2.96k| bool hasD16() const { 289| 2.96k| return getSTI().getFeatureBits()[ARM::FeatureD16]; 290| 2.96k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser16ParseInstructionERN7llvm_ks20ParseInstructionInfoENS1_9StringRefENS1_5SMLocERNS1_15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS7_14default_deleteIS9_EEEEEERj: 5867| 3.40k|{ 5868| 3.40k| MCAsmParser &Parser = getParser(); 5869| | // FIXME: Can this be done via tablegen in some fashion? 5870| 3.40k| bool RequireVFPRegisterListCheck; 5871| 3.40k| bool AcceptSinglePrecisionOnly; 5872| 3.40k| bool AcceptDoublePrecisionOnly; 5873| 3.40k| RequireVFPRegisterListCheck = 5874| 3.40k| RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly, 5875| 3.40k| AcceptDoublePrecisionOnly); 5876| | 5877| | // Apply mnemonic aliases before doing anything else, as the destination 5878| | // mnemonic may include suffices and we want to handle them normally. 5879| | // The generic tblgen'erated code does this later, at the start of 5880| | // MatchInstructionImpl(), but that's too late for aliases that include 5881| | // any sort of suffix. 5882| 3.40k| uint64_t AvailableFeatures = getAvailableFeatures(); 5883| 3.40k| unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5884| 3.40k| applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5885| | 5886| | // First check for the ARM-specific .req directive. 5887| 3.40k| if (Parser.getTok().is(AsmToken::Identifier) && ------------------ | Branch (5887:7): [True: 2.03k, False: 1.36k] | Branch (5887:7): [True: 0, False: 3.40k] ------------------ 5888| 2.03k| Parser.getTok().getIdentifier() == ".req") { ------------------ | Branch (5888:7): [True: 0, False: 2.03k] ------------------ 5889| 0| parseDirectiveReq(Name, NameLoc); 5890| | // We always return 'error' for this, as we're done with this 5891| | // statement and don't need to match the 'instruction." 5892| 0| ErrorCode = KS_ERR_ASM_DIRECTIVE_INVALID; 5893| 0| return true; 5894| 0| } 5895| | 5896| | // Create the leading tokens for the mnemonic, split by '.' characters. 5897| 3.40k| size_t Start = 0, Next = Name.find('.'); 5898| 3.40k| StringRef Mnemonic = Name.slice(Start, Next); 5899| | 5900| | // Split out the predication code and carry setting flag from the mnemonic. 5901| 3.40k| unsigned PredicationCode; 5902| 3.40k| unsigned ProcessorIMod; 5903| 3.40k| bool CarrySetting; 5904| 3.40k| StringRef ITMask; 5905| 3.40k| Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5906| 3.40k| ProcessorIMod, ITMask); 5907| | 5908| | // In Thumb1, only the branch (B) instruction can be predicated. 5909| 3.40k| if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { ------------------ | Branch (5909:7): [True: 107, False: 3.29k] | Branch (5909:7): [True: 0, False: 3.40k] | Branch (5909:23): [True: 0, False: 107] | Branch (5909:55): [True: 0, False: 0] ------------------ 5910| 0| Parser.eatToEndOfStatement(); 5911| | //return Error(NameLoc, "conditional execution not supported in Thumb1"); 5912| 0| ErrorCode = KS_ERR_ASM_MNEMONICFAIL; 5913| 0| return true; 5914| 0| } 5915| | 5916| 3.40k| Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5917| | 5918| | // Handle the IT instruction ITMask. Convert it to a bitmask. This 5919| | // is the mask as it will be for the IT encoding if the conditional 5920| | // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5921| | // where the conditional bit0 is zero, the instruction post-processing 5922| | // will adjust the mask accordingly. 5923| 3.40k| if (Mnemonic == "it") { ------------------ | Branch (5923:7): [True: 69, False: 3.33k] ------------------ 5924| 69| SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5925| 69| if (ITMask.size() > 3) { ------------------ | Branch (5925:9): [True: 0, False: 69] ------------------ 5926| 0| Parser.eatToEndOfStatement(); 5927| | //return Error(Loc, "too many conditions on IT instruction"); 5928| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 5929| 0| return true; 5930| 0| } 5931| 69| unsigned Mask = 8; 5932| 72| for (unsigned i = ITMask.size(); i != 0; --i) { ------------------ | Branch (5932:38): [True: 3, False: 69] ------------------ 5933| 3| char pos = ITMask[i - 1]; 5934| 3| if (pos != 't' && pos != 'e') { ------------------ | Branch (5934:11): [True: 0, False: 3] | Branch (5934:25): [True: 0, False: 0] ------------------ 5935| 0| Parser.eatToEndOfStatement(); 5936| | //return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5937| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 5938| 0| return true; 5939| 0| } 5940| 3| Mask >>= 1; 5941| 3| if (ITMask[i - 1] == 't') ------------------ | Branch (5941:11): [True: 3, False: 0] ------------------ 5942| 3| Mask |= 8; 5943| 3| } 5944| 69| Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5945| 69| } 5946| | 5947| | // FIXME: This is all a pretty gross hack. We should automatically handle 5948| | // optional operands like this via tblgen. 5949| | 5950| | // Next, add the CCOut and ConditionCode operands, if needed. 5951| | // 5952| | // For mnemonics which can ever incorporate a carry setting bit or predication 5953| | // code, our matching model involves us always generating CCOut and 5954| | // ConditionCode operands to match the mnemonic "as written" and then we let 5955| | // the matcher deal with finding the right instruction or generating an 5956| | // appropriate error. 5957| 3.40k| bool CanAcceptCarrySet, CanAcceptPredicationCode; 5958| 3.40k| getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode); 5959| | 5960| | // If we had a carry-set on an instruction that can't do that, issue an 5961| | // error. 5962| 3.40k| if (!CanAcceptCarrySet && CarrySetting) { ------------------ | Branch (5962:7): [True: 2.64k, False: 763] | Branch (5962:29): [True: 4, False: 2.63k] ------------------ 5963| 4| Parser.eatToEndOfStatement(); 5964| | //return Error(NameLoc, "instruction '" + Mnemonic + 5965| | // "' can not set flags, but 's' suffix specified"); 5966| 4| ErrorCode = KS_ERR_ASM_MNEMONICFAIL; 5967| 4| return true; 5968| 4| } 5969| | // If we had a predication code on an instruction that can't do that, issue an 5970| | // error. 5971| 3.39k| if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { ------------------ | Branch (5971:7): [True: 77, False: 3.32k] | Branch (5971:36): [True: 0, False: 77] ------------------ 5972| 0| Parser.eatToEndOfStatement(); 5973| | //return Error(NameLoc, "instruction '" + Mnemonic + 5974| | // "' is not predicable, but condition code specified"); 5975| 0| ErrorCode = KS_ERR_ASM_MNEMONICFAIL; 5976| 0| return true; 5977| 0| } 5978| | 5979| | // Add the carry setting operand, if necessary. 5980| 3.39k| if (CanAcceptCarrySet) { ------------------ | Branch (5980:7): [True: 763, False: 2.63k] ------------------ 5981| 763| SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5982| 763| Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, ------------------ | Branch (5982:48): [True: 385, False: 378] ------------------ 5983| 763| Loc)); 5984| 763| } 5985| | 5986| | // Add the predication code operand, if necessary. 5987| 3.39k| if (CanAcceptPredicationCode) { ------------------ | Branch (5987:7): [True: 3.32k, False: 77] ------------------ 5988| 3.32k| SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5989| 3.32k| CarrySetting); 5990| 3.32k| Operands.push_back(ARMOperand::CreateCondCode( 5991| 3.32k| ARMCC::CondCodes(PredicationCode), Loc)); 5992| 3.32k| } 5993| | 5994| | // Add the processor imod operand, if necessary. 5995| 3.39k| if (ProcessorIMod) { ------------------ | Branch (5995:7): [True: 0, False: 3.39k] ------------------ 5996| 0| Operands.push_back(ARMOperand::CreateImm( 5997| 0| MCConstantExpr::create(ProcessorIMod, getContext()), 5998| 0| NameLoc, NameLoc)); 5999| 3.39k| } else if (Mnemonic == "cps" && isMClass()) { ------------------ | Branch (5999:14): [True: 4, False: 3.39k] | Branch (5999:14): [True: 0, False: 3.39k] | Branch (5999:35): [True: 0, False: 4] ------------------ 6000| | //return Error(NameLoc, "instruction 'cps' requires effect for M-class"); 6001| 0| ErrorCode = KS_ERR_ASM_MNEMONICFAIL; 6002| 0| return true; 6003| 0| } 6004| | 6005| | // Add the remaining tokens in the mnemonic. 6006| 8.43k| while (Next != StringRef::npos) { ------------------ | Branch (6006:10): [True: 5.03k, False: 3.39k] ------------------ 6007| 5.03k| Start = Next; 6008| 5.03k| Next = Name.find('.', Start + 1); 6009| 5.03k| StringRef ExtraToken = Name.slice(Start, Next); 6010| | 6011| | // Some NEON instructions have an optional datatype suffix that is 6012| | // completely ignored. Check for that. 6013| 5.03k| if (isDataTypeToken(ExtraToken) && ------------------ | Branch (6013:9): [True: 638, False: 4.39k] ------------------ 6014| 638| doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) ------------------ | Branch (6014:9): [True: 0, False: 638] ------------------ 6015| 0| continue; 6016| | 6017| | // For for ARM mode generate an error if the .n qualifier is used. 6018| 5.03k| if (ExtraToken == ".n" && !isThumb()) { ------------------ | Branch (6018:9): [True: 1, False: 5.03k] | Branch (6018:9): [True: 0, False: 5.03k] | Branch (6018:31): [True: 0, False: 1] ------------------ 6019| | //SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 6020| 0| Parser.eatToEndOfStatement(); 6021| | //return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 6022| | // "arm mode"); 6023| 0| ErrorCode = KS_ERR_ASM_MNEMONICFAIL; 6024| 0| return true; 6025| 0| } 6026| | 6027| | // The .n qualifier is always discarded as that is what the tables 6028| | // and matcher expect. In ARM mode the .w qualifier has no effect, 6029| | // so discard it to avoid errors that can be caused by the matcher. 6030| 5.03k| if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { ------------------ | Branch (6030:9): [True: 5.03k, False: 1] | Branch (6030:9): [True: 5.03k, False: 1] | Branch (6030:32): [True: 5.03k, False: 4] | Branch (6030:45): [True: 4, False: 0] ------------------ 6031| 5.03k| SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 6032| 5.03k| Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 6033| 5.03k| } 6034| 5.03k| } 6035| | 6036| | // Read the remaining operands. 6037| 3.39k| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (6037:7): [True: 3.35k, False: 45] ------------------ 6038| | // Read the first operand. 6039| 3.35k| if (parseOperand(Operands, Mnemonic, ErrorCode)) { ------------------ | Branch (6039:9): [True: 881, False: 2.47k] ------------------ 6040| 881| Parser.eatToEndOfStatement(); 6041| 881| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 6042| 881| return true; 6043| 881| } 6044| | 6045| 21.0k| while (getLexer().is(AsmToken::Comma)) { ------------------ | Branch (6045:12): [True: 18.6k, False: 2.38k] ------------------ 6046| 18.6k| Parser.Lex(); // Eat the comma. 6047| | 6048| | // Parse and remember the operand. 6049| 18.6k| if (parseOperand(Operands, Mnemonic, ErrorCode)) { ------------------ | Branch (6049:11): [True: 92, False: 18.5k] ------------------ 6050| 92| Parser.eatToEndOfStatement(); 6051| 92| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 6052| 92| return true; 6053| 92| } 6054| 18.6k| } 6055| 2.47k| } 6056| | 6057| 2.42k| if (getLexer().isNot(AsmToken::EndOfStatement)) { ------------------ | Branch (6057:7): [True: 83, False: 2.34k] ------------------ 6058| | //SMLoc Loc = getLexer().getLoc(); 6059| 83| Parser.eatToEndOfStatement(); 6060| | //return Error(Loc, "unexpected token in argument list"); 6061| 83| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 6062| 83| return true; 6063| 83| } 6064| | 6065| 2.34k| Parser.Lex(); // Consume the EndOfStatement 6066| | 6067| 2.34k| if (RequireVFPRegisterListCheck) { ------------------ | Branch (6067:7): [True: 0, False: 2.34k] ------------------ 6068| 0| ARMOperand &Op = static_cast(*Operands.back()); 6069| 0| if (AcceptSinglePrecisionOnly && !Op.isSPRRegList()) { ------------------ | Branch (6069:9): [True: 0, False: 0] | Branch (6069:38): [True: 0, False: 0] ------------------ 6070| | //return Error(Op.getStartLoc(), 6071| | // "VFP/Neon single precision register expected"); 6072| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 6073| 0| return true; 6074| 0| } 6075| 0| if (AcceptDoublePrecisionOnly && !Op.isDPRRegList()) { ------------------ | Branch (6075:9): [True: 0, False: 0] | Branch (6075:38): [True: 0, False: 0] ------------------ 6076| | //return Error(Op.getStartLoc(), 6077| | // "VFP/Neon double precision register expected"); 6078| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 6079| 0| return true; 6080| 0| } 6081| 0| } 6082| | 6083| 2.34k| tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); 6084| | 6085| | // Some instructions, mostly Thumb, have forms for the same mnemonic that 6086| | // do and don't have a cc_out optional-def operand. With some spot-checks 6087| | // of the operand list, we can figure out which variant we're trying to 6088| | // parse and adjust accordingly before actually matching. We shouldn't ever 6089| | // try to remove a cc_out operand that was explicitly set on the 6090| | // mnemonic, of course (CarrySetting == true). Reason number #317 the 6091| | // table driven matcher doesn't fit well with the ARM instruction set. 6092| 2.34k| if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) ------------------ | Branch (6092:7): [True: 1.95k, False: 385] | Branch (6092:24): [True: 170, False: 1.78k] ------------------ 6093| 170| Operands.erase(Operands.begin() + 1); 6094| | 6095| | // Some instructions have the same mnemonic, but don't always 6096| | // have a predicate. Distinguish them here and delete the 6097| | // predicate if needed. 6098| 2.34k| if (shouldOmitPredicateOperand(Mnemonic, Operands)) ------------------ | Branch (6098:7): [True: 0, False: 2.34k] ------------------ 6099| 0| Operands.erase(Operands.begin() + 1); 6100| | 6101| | // ARM mode 'blx' need special handling, as the register operand version 6102| | // is predicable, but the label operand version is not. So, we can't rely 6103| | // on the Mnemonic based checking to correctly figure out when to put 6104| | // a k_CondCode operand in the list. If we're trying to match the label 6105| | // version, remove the k_CondCode operand here. 6106| 2.34k| if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && ------------------ | Branch (6106:7): [True: 468, False: 1.87k] | Branch (6106:7): [True: 1, False: 2.34k] | Branch (6106:21): [True: 1, False: 467] | Branch (6106:42): [True: 1, False: 0] ------------------ 6107| 1| static_cast(*Operands[2]).isImm()) ------------------ | Branch (6107:7): [True: 1, False: 0] ------------------ 6108| 1| Operands.erase(Operands.begin() + 1); 6109| | 6110| | // Adjust operands of ldrexd/strexd to MCK_GPRPair. 6111| | // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 6112| | // a single GPRPair reg operand is used in the .td file to replace the two 6113| | // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 6114| | // expressed as a GPRPair, so we have to manually merge them. 6115| | // FIXME: We would really like to be able to tablegen'erate this. 6116| 2.34k| if (!isThumb() && Operands.size() > 4 && ------------------ | Branch (6116:7): [True: 468, False: 1.87k] | Branch (6116:7): [True: 0, False: 2.34k] | Branch (6116:21): [True: 166, False: 302] ------------------ 6117| 166| (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || ------------------ | Branch (6117:8): [True: 0, False: 166] | Branch (6117:32): [True: 0, False: 166] | Branch (6117:56): [True: 0, False: 166] ------------------ 6118| 166| Mnemonic == "stlexd")) { ------------------ | Branch (6118:8): [True: 0, False: 166] ------------------ 6119| 0| bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); ------------------ | Branch (6119:20): [True: 0, False: 0] | Branch (6119:44): [True: 0, False: 0] ------------------ 6120| 0| unsigned Idx = isLoad ? 2 : 3; ------------------ | Branch (6120:20): [True: 0, False: 0] ------------------ 6121| 0| ARMOperand &Op1 = static_cast(*Operands[Idx]); 6122| 0| ARMOperand &Op2 = static_cast(*Operands[Idx + 1]); 6123| | 6124| 0| const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 6125| | // Adjust only if Op1 and Op2 are GPRs. 6126| 0| if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && ------------------ | Branch (6126:9): [True: 0, False: 0] | Branch (6126:24): [True: 0, False: 0] | Branch (6126:39): [True: 0, False: 0] ------------------ 6127| 0| MRC.contains(Op2.getReg())) { ------------------ | Branch (6127:9): [True: 0, False: 0] ------------------ 6128| 0| unsigned Reg1 = Op1.getReg(); 6129| 0| unsigned Reg2 = Op2.getReg(); 6130| 0| unsigned Rt = MRI->getEncodingValue(Reg1); 6131| 0| unsigned Rt2 = MRI->getEncodingValue(Reg2); 6132| | 6133| | // Rt2 must be Rt + 1 and Rt must be even. 6134| 0| if (Rt + 1 != Rt2 || (Rt & 1)) { ------------------ | Branch (6134:11): [True: 0, False: 0] | Branch (6134:28): [True: 0, False: 0] ------------------ 6135| | //Error(Op2.getStartLoc(), isLoad 6136| | // ? "destination operands must be sequential" 6137| | // : "source operands must be sequential"); 6138| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 6139| 0| return true; 6140| 0| } 6141| 0| unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 6142| 0| &(MRI->getRegClass(ARM::GPRPairRegClassID))); 6143| 0| Operands[Idx] = 6144| 0| ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); 6145| 0| Operands.erase(Operands.begin() + Idx + 1); 6146| 0| } 6147| 0| } 6148| | 6149| | // GNU Assembler extension (compatibility) 6150| 2.34k| if ((Mnemonic == "ldrd" || Mnemonic == "strd")) { ------------------ | Branch (6150:7): [True: 0, False: 2.34k] | Branch (6150:8): [True: 0, False: 2.34k] | Branch (6150:30): [True: 0, False: 2.34k] ------------------ 6151| 0| if (Operands.size() < 4) { ------------------ | Branch (6151:9): [True: 0, False: 0] ------------------ 6152| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 6153| 0| return true; 6154| 0| } 6155| 0| ARMOperand &Op2 = static_cast(*Operands[2]); 6156| 0| ARMOperand &Op3 = static_cast(*Operands[3]); 6157| 0| if (Op3.isMem()) { ------------------ | Branch (6157:9): [True: 0, False: 0] ------------------ 6158| 0| assert(Op2.isReg() && "expected register argument"); ------------------ | Branch (6158:7): [True: 0, False: 0] | Branch (6158:7): [True: 0, Folded] | Branch (6158:7): [True: 0, False: 0] ------------------ 6159| | 6160| 0| unsigned SuperReg = MRI->getMatchingSuperReg( 6161| 0| Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID)); 6162| | 6163| 0| assert(SuperReg && "expected register pair"); ------------------ | Branch (6163:7): [True: 0, False: 0] | Branch (6163:7): [True: 0, Folded] | Branch (6163:7): [True: 0, False: 0] ------------------ 6164| | 6165| 0| unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); 6166| | 6167| 0| Operands.insert( 6168| 0| Operands.begin() + 3, 6169| 0| ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc())); 6170| 0| } 6171| 0| } 6172| | 6173| | // FIXME: As said above, this is all a pretty gross hack. This instruction 6174| | // does not fit with other "subs" and tblgen. 6175| | // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 6176| | // so the Mnemonic is the original name "subs" and delete the predicate 6177| | // operand so it will match the table entry. 6178| 2.34k| if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && ------------------ | Branch (6178:7): [True: 1.80k, False: 538] | Branch (6178:7): [True: 0, False: 2.34k] | Branch (6178:23): [True: 354, False: 1.45k] | Branch (6178:44): [True: 65, False: 289] ------------------ 6179| 65| static_cast(*Operands[3]).isReg() && ------------------ | Branch (6179:7): [True: 65, False: 0] ------------------ 6180| 65| static_cast(*Operands[3]).getReg() == ARM::PC && ------------------ | Branch (6180:7): [True: 0, False: 65] ------------------ 6181| 0| static_cast(*Operands[4]).isReg() && ------------------ | Branch (6181:7): [True: 0, False: 0] ------------------ 6182| 0| static_cast(*Operands[4]).getReg() == ARM::LR && ------------------ | Branch (6182:7): [True: 0, False: 0] ------------------ 6183| 0| static_cast(*Operands[5]).isImm()) { ------------------ | Branch (6183:7): [True: 0, False: 0] ------------------ 6184| 0| Operands.front() = ARMOperand::CreateToken(Name, NameLoc); 6185| 0| Operands.erase(Operands.begin() + 1); 6186| 0| } 6187| 2.34k| return false; 6188| 2.34k|} ARMAsmParser.cpp:_ZL28RequiresVFPRegListValidationN7llvm_ks9StringRefERbS1_: 5847| 3.40k| bool &AcceptDoublePrecisionOnly) { 5848| 3.40k| if (Inst.size() < 7) ------------------ | Branch (5848:7): [True: 2.90k, False: 502] ------------------ 5849| 2.90k| return false; 5850| | 5851| 502| if (Inst.startswith("fldm") || Inst.startswith("fstm")) { ------------------ | Branch (5851:7): [True: 88, False: 414] | Branch (5851:7): [True: 88, False: 414] | Branch (5851:34): [True: 0, False: 414] ------------------ 5852| 88| StringRef AddressingMode = Inst.substr(4, 2); 5853| 88| if (AddressingMode == "ia" || AddressingMode == "db" || ------------------ | Branch (5853:9): [True: 0, False: 88] | Branch (5853:9): [True: 40, False: 48] | Branch (5853:35): [True: 0, False: 88] ------------------ 5854| 88| AddressingMode == "ea" || AddressingMode == "fd") { ------------------ | Branch (5854:9): [True: 40, False: 48] | Branch (5854:35): [True: 0, False: 48] ------------------ 5855| 40| AcceptSinglePrecisionOnly = Inst[6] == 's'; 5856| 40| AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x'; ------------------ | Branch (5856:35): [True: 0, False: 40] | Branch (5856:53): [True: 39, False: 1] ------------------ 5857| 40| return true; 5858| 40| } 5859| 88| } 5860| | 5861| 462| return false; 5862| 502|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser13splitMnemonicEN7llvm_ks9StringRefERjRbS3_RS2_: 5447| 3.40k| StringRef &ITMask) { 5448| 3.40k| PredicationCode = ARMCC::AL; 5449| 3.40k| CarrySetting = false; 5450| 3.40k| ProcessorIMod = 0; 5451| | 5452| | // Ignore some mnemonics we know aren't predicated forms. 5453| | // 5454| | // FIXME: Would be nice to autogen this. 5455| 3.40k| if ((Mnemonic == "movs" && isThumb()) || ------------------ | Branch (5455:7): [True: 4, False: 3.39k] | Branch (5455:8): [True: 0, False: 3.40k] | Branch (5455:30): [True: 0, False: 0] ------------------ 5456| 3.40k| Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || ------------------ | Branch (5456:7): [True: 0, False: 3.40k] | Branch (5456:30): [True: 0, False: 3.40k] | Branch (5456:54): [True: 0, False: 3.40k] ------------------ 5457| 3.40k| Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || ------------------ | Branch (5457:7): [True: 0, False: 3.40k] | Branch (5457:30): [True: 0, False: 3.40k] | Branch (5457:54): [True: 0, False: 3.40k] ------------------ 5458| 3.40k| Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || ------------------ | Branch (5458:7): [True: 0, False: 3.40k] | Branch (5458:30): [True: 0, False: 3.40k] | Branch (5458:54): [True: 0, False: 3.40k] ------------------ 5459| 3.40k| Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || ------------------ | Branch (5459:7): [True: 0, False: 3.40k] | Branch (5459:30): [True: 0, False: 3.40k] | Branch (5459:54): [True: 0, False: 3.40k] ------------------ 5460| 3.40k| Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || ------------------ | Branch (5460:7): [True: 0, False: 3.40k] | Branch (5460:30): [True: 0, False: 3.40k] | Branch (5460:54): [True: 2, False: 3.40k] ------------------ 5461| 3.40k| Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || ------------------ | Branch (5461:7): [True: 0, False: 3.40k] | Branch (5461:30): [True: 0, False: 3.40k] | Branch (5461:54): [True: 0, False: 3.40k] ------------------ 5462| 3.40k| Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || ------------------ | Branch (5462:7): [True: 0, False: 3.40k] | Branch (5462:30): [True: 0, False: 3.40k] | Branch (5462:54): [True: 0, False: 3.40k] ------------------ 5463| 3.40k| Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || ------------------ | Branch (5463:7): [True: 0, False: 3.40k] | Branch (5463:30): [True: 0, False: 3.40k] | Branch (5463:54): [True: 0, False: 3.40k] ------------------ 5464| 3.40k| Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || ------------------ | Branch (5464:7): [True: 0, False: 3.40k] | Branch (5464:30): [True: 0, False: 3.40k] | Branch (5464:54): [True: 0, False: 3.40k] ------------------ 5465| 3.40k| Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || ------------------ | Branch (5465:7): [True: 0, False: 3.40k] | Branch (5465:30): [True: 0, False: 3.40k] | Branch (5465:54): [True: 0, False: 3.40k] ------------------ 5466| 3.40k| Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || ------------------ | Branch (5466:7): [True: 0, False: 3.40k] | Branch (5466:30): [True: 0, False: 3.40k] | Branch (5466:54): [True: 0, False: 3.40k] ------------------ 5467| 3.40k| Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" || ------------------ | Branch (5467:7): [True: 0, False: 3.40k] | Branch (5467:31): [True: 0, False: 3.40k] | Branch (5467:55): [True: 0, False: 3.40k] ------------------ 5468| 3.40k| Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" || ------------------ | Branch (5468:7): [True: 2, False: 3.39k] | Branch (5468:38): [True: 0, False: 3.39k] | Branch (5468:60): [True: 0, False: 3.39k] ------------------ 5469| 3.39k| Mnemonic == "bxns" || Mnemonic == "blxns") ------------------ | Branch (5469:7): [True: 0, False: 3.39k] | Branch (5469:30): [True: 0, False: 3.39k] ------------------ 5470| 4| return Mnemonic; 5471| | 5472| | // First, split out any predication code. Ignore mnemonics we know aren't 5473| | // predicated but do have a carry-set and so weren't caught above. 5474| 3.39k| if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && ------------------ | Branch (5474:7): [True: 3.39k, False: 0] | Branch (5474:7): [True: 3.23k, False: 162] | Branch (5474:29): [True: 3.39k, False: 0] | Branch (5474:51): [True: 3.39k, False: 0] ------------------ 5475| 3.39k| Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && ------------------ | Branch (5475:7): [True: 3.39k, False: 0] | Branch (5475:29): [True: 3.39k, False: 0] | Branch (5475:53): [True: 3.39k, False: 0] ------------------ 5476| 3.39k| Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && ------------------ | Branch (5476:7): [True: 3.39k, False: 0] | Branch (5476:31): [True: 3.39k, False: 0] | Branch (5476:55): [True: 3.23k, False: 162] ------------------ 5477| 3.23k| Mnemonic != "sbcs" && Mnemonic != "rscs") { ------------------ | Branch (5477:7): [True: 3.23k, False: 0] | Branch (5477:29): [True: 3.23k, False: 0] ------------------ 5478| 3.23k| unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) 5479| 3.23k| .Case("eq", ARMCC::EQ) 5480| 3.23k| .Case("ne", ARMCC::NE) 5481| 3.23k| .Case("hs", ARMCC::HS) 5482| 3.23k| .Case("cs", ARMCC::HS) 5483| 3.23k| .Case("lo", ARMCC::LO) 5484| 3.23k| .Case("cc", ARMCC::LO) 5485| 3.23k| .Case("mi", ARMCC::MI) 5486| 3.23k| .Case("pl", ARMCC::PL) 5487| 3.23k| .Case("vs", ARMCC::VS) 5488| 3.23k| .Case("vc", ARMCC::VC) 5489| 3.23k| .Case("hi", ARMCC::HI) 5490| 3.23k| .Case("ls", ARMCC::LS) 5491| 3.23k| .Case("ge", ARMCC::GE) 5492| 3.23k| .Case("lt", ARMCC::LT) 5493| 3.23k| .Case("gt", ARMCC::GT) 5494| 3.23k| .Case("le", ARMCC::LE) 5495| 3.23k| .Case("al", ARMCC::AL) 5496| 3.23k| .Default(~0U); 5497| 3.23k| if (CC != ~0U) { ------------------ | Branch (5497:9): [True: 234, False: 3.00k] ------------------ 5498| 234| Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 5499| 234| PredicationCode = CC; 5500| 234| } 5501| 3.23k| } 5502| | 5503| | // Next, determine if we have a carry setting bit. We explicitly ignore all 5504| | // the instructions we know end in 's'. 5505| 3.39k| if (Mnemonic.endswith("s") && ------------------ | Branch (5505:7): [True: 393, False: 3.00k] | Branch (5505:7): [True: 389, False: 3.01k] ------------------ 5506| 393| !(Mnemonic == "cps" || Mnemonic == "mls" || ------------------ | Branch (5506:9): [True: 4, False: 389] | Branch (5506:30): [True: 0, False: 389] ------------------ 5507| 389| Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || ------------------ | Branch (5507:9): [True: 0, False: 389] | Branch (5507:30): [True: 0, False: 389] | Branch (5507:53): [True: 0, False: 389] ------------------ 5508| 389| Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || ------------------ | Branch (5508:9): [True: 0, False: 389] | Branch (5508:31): [True: 0, False: 389] | Branch (5508:53): [True: 0, False: 389] ------------------ 5509| 389| Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || ------------------ | Branch (5509:9): [True: 0, False: 389] | Branch (5509:32): [True: 0, False: 389] | Branch (5509:55): [True: 0, False: 389] ------------------ 5510| 389| Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || ------------------ | Branch (5510:9): [True: 0, False: 389] | Branch (5510:34): [True: 0, False: 389] | Branch (5510:55): [True: 0, False: 389] ------------------ 5511| 389| Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || ------------------ | Branch (5511:9): [True: 0, False: 389] | Branch (5511:31): [True: 0, False: 389] | Branch (5511:55): [True: 0, False: 389] ------------------ 5512| 389| Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || ------------------ | Branch (5512:9): [True: 0, False: 389] | Branch (5512:31): [True: 0, False: 389] | Branch (5512:54): [True: 0, False: 389] ------------------ 5513| 389| Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || ------------------ | Branch (5513:9): [True: 0, False: 389] | Branch (5513:32): [True: 0, False: 389] | Branch (5513:55): [True: 0, False: 389] ------------------ 5514| 389| Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || ------------------ | Branch (5514:9): [True: 0, False: 389] | Branch (5514:31): [True: 0, False: 389] | Branch (5514:54): [True: 0, False: 389] ------------------ 5515| 389| (Mnemonic == "movs" && isThumb()))) { ------------------ | Branch (5515:10): [True: 0, False: 389] | Branch (5515:32): [True: 0, False: 0] ------------------ 5516| 389| Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 5517| 389| CarrySetting = true; 5518| 389| } 5519| | 5520| | // The "cps" instruction can have a interrupt mode operand which is glued into 5521| | // the mnemonic. Check if this is the case, split it and parse the imod op 5522| 3.39k| if (Mnemonic.startswith("cps")) { ------------------ | Branch (5522:7): [True: 4, False: 3.39k] ------------------ 5523| | // Split out any imod code. 5524| 4| unsigned IMod = 5525| 4| StringSwitch(Mnemonic.substr(Mnemonic.size()-2, 2)) 5526| 4| .Case("ie", ARM_PROC::IE) 5527| 4| .Case("id", ARM_PROC::ID) 5528| 4| .Default(~0U); 5529| 4| if (IMod != ~0U) { ------------------ | Branch (5529:9): [True: 0, False: 4] ------------------ 5530| 0| Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 5531| 0| ProcessorIMod = IMod; 5532| 0| } 5533| 4| } 5534| | 5535| | // The "it" instruction has the condition mask on the end of the mnemonic. 5536| 3.39k| if (Mnemonic.startswith("it")) { ------------------ | Branch (5536:7): [True: 69, False: 3.33k] ------------------ 5537| 69| ITMask = Mnemonic.slice(2, Mnemonic.size()); 5538| 69| Mnemonic = Mnemonic.slice(0, 2); 5539| 69| } 5540| | 5541| 3.39k| return Mnemonic; 5542| 3.40k|} ARMAsmParser.cpp:_ZNK12_GLOBAL__N_112ARMAsmParser10isThumbOneEv: 252| 8.83k| bool isThumbOne() const { 253| 8.83k| return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; ------------------ | Branch (253:12): [True: 7.86k, False: 977] | Branch (253:25): [True: 338, False: 7.52k] ------------------ 254| 8.83k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_110ARMOperand11CreateTokenEN7llvm_ks9StringRefENS1_5SMLocE: 2589| 8.43k| static std::unique_ptr CreateToken(StringRef Str, SMLoc S) { 2590| 8.43k| auto Op = make_unique(k_Token); 2591| 8.43k| Op->Tok.Data = Str.data(); 2592| 8.43k| Op->Tok.Length = Str.size(); 2593| 8.43k| Op->StartLoc = S; 2594| 8.43k| Op->EndLoc = S; 2595| 8.43k| return Op; 2596| 8.43k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_110ARMOperandC2ENS0_6KindTyE: 581| 33.6k| ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand7isTokenEv: 1045| 33.4k| bool isToken() const override { return Kind == k_Token; } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand5isImmEv: 665| 9.09k| bool isImm() const override { return Kind == k_Immediate; } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand5isRegEv: 1041| 14.6k| bool isReg() const override { return Kind == k_Register; } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand6getRegEv: 612| 12.8k| unsigned getReg() const override { 613| 12.8k| assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); ------------------ | Branch (613:5): [True: 11.9k, False: 891] | Branch (613:5): [True: 891, False: 0] | Branch (613:5): [True: 12.8k, Folded] | Branch (613:5): [True: 12.8k, False: 0] ------------------ 614| 12.8k| return Reg.RegNum; 615| 12.8k| } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand5isMemEv: 1048| 218| bool isMem() const override { return Kind == k_Memory; } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand11getCondCodeEv: 597| 5.11k| ARMCC::CondCodes getCondCode() const { 598| 5.11k| assert(Kind == k_CondCode && "Invalid access!"); ------------------ | Branch (598:5): [True: 5.11k, False: 0] | Branch (598:5): [True: 5.11k, Folded] | Branch (598:5): [True: 5.11k, False: 0] ------------------ 599| 5.11k| return CC.Val; 600| 5.11k| } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand10getMSRMaskEv: 648| 65| unsigned getMSRMask() const { 649| 65| assert(Kind == k_MSRMask && "Invalid access!"); ------------------ | Branch (649:5): [True: 65, False: 0] | Branch (649:5): [True: 65, Folded] | Branch (649:5): [True: 65, False: 0] ------------------ 650| 65| return MMask.Val; 651| 65| } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand6getImmEv: 623| 3.47k| const MCExpr *getImm() const { 624| 3.47k| assert(isImm() && "Invalid access!"); ------------------ | Branch (624:5): [True: 3.47k, False: 0] | Branch (624:5): [True: 3.47k, Folded] | Branch (624:5): [True: 3.47k, False: 0] ------------------ 625| 3.47k| return Imm.Val; 626| 3.47k| } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_110ARMOperand8getTokenEv: 607| 5.06k| StringRef getToken() const { 608| 5.06k| assert(Kind == k_Token && "Invalid access!"); ------------------ | Branch (608:5): [True: 5.06k, False: 0] | Branch (608:5): [True: 5.06k, Folded] | Branch (608:5): [True: 5.06k, False: 0] ------------------ 609| 5.06k| return StringRef(Tok.Data, Tok.Length); 610| 5.06k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_110ARMOperand12CreateITMaskEjN7llvm_ks5SMLocE: 2539| 69| static std::unique_ptr CreateITMask(unsigned Mask, SMLoc S) { 2540| 69| auto Op = make_unique(k_ITCondMask); 2541| 69| Op->ITMask.Mask = Mask; 2542| 69| Op->StartLoc = S; 2543| 69| Op->EndLoc = S; 2544| 69| return Op; 2545| 69| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser21getMnemonicAcceptInfoEN7llvm_ks9StringRefES2_RbS3_: 5550| 3.40k| bool &CanAcceptPredicationCode) { 5551| 3.40k| CanAcceptCarrySet = 5552| 3.40k| Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || ------------------ | Branch (5552:7): [True: 0, False: 3.40k] | Branch (5552:28): [True: 163, False: 3.24k] | Branch (5552:49): [True: 28, False: 3.21k] ------------------ 5553| 3.21k| Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || ------------------ | Branch (5553:7): [True: 0, False: 3.21k] | Branch (5553:28): [True: 0, False: 3.21k] | Branch (5553:49): [True: 354, False: 2.85k] ------------------ 5554| 2.85k| Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" || ------------------ | Branch (5554:7): [True: 212, False: 2.64k] | Branch (5554:28): [True: 0, False: 2.64k] | Branch (5554:49): [True: 0, False: 2.64k] ------------------ 5555| 2.64k| Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" || ------------------ | Branch (5555:7): [True: 0, False: 2.64k] | Branch (5555:28): [True: 4, False: 2.64k] | Branch (5555:49): [True: 0, False: 2.64k] ------------------ 5556| 2.64k| Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" || ------------------ | Branch (5556:7): [True: 0, False: 2.64k] | Branch (5556:28): [True: 0, False: 2.64k] | Branch (5556:49): [True: 0, False: 2.64k] ------------------ 5557| 2.64k| Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" || ------------------ | Branch (5557:7): [True: 0, False: 2.64k] | Branch (5557:28): [True: 0, False: 2.64k] | Branch (5557:49): [True: 0, False: 2.64k] ------------------ 5558| 2.64k| Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" || ------------------ | Branch (5558:7): [True: 0, False: 2.64k] | Branch (5558:28): [True: 2, False: 2.64k] | Branch (5558:49): [True: 0, False: 2.64k] ------------------ 5559| 2.64k| (!isThumb() && ------------------ | Branch (5559:8): [True: 308, False: 2.33k] ------------------ 5560| 308| (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" || ------------------ | Branch (5560:9): [True: 0, False: 308] | Branch (5560:32): [True: 0, False: 308] | Branch (5560:53): [True: 0, False: 308] ------------------ 5561| 308| Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull")); ------------------ | Branch (5561:9): [True: 0, False: 308] | Branch (5561:32): [True: 0, False: 308] | Branch (5561:55): [True: 0, False: 308] ------------------ 5562| | 5563| 3.40k| if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || ------------------ | Branch (5563:7): [True: 0, False: 3.40k] | Branch (5563:7): [True: 77, False: 3.32k] | Branch (5563:29): [True: 0, False: 3.40k] | Branch (5563:51): [True: 0, False: 3.40k] ------------------ 5564| 3.40k| Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || ------------------ | Branch (5564:7): [True: 4, False: 3.39k] | Branch (5564:28): [True: 69, False: 3.33k] | Branch (5564:48): [True: 0, False: 3.33k] ------------------ 5565| 3.33k| Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" || ------------------ | Branch (5565:7): [True: 0, False: 3.33k] | Branch (5565:29): [True: 2, False: 3.32k] | Branch (5565:50): [True: 0, False: 3.32k] ------------------ 5566| 3.32k| Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") || ------------------ | Branch (5566:7): [True: 0, False: 3.32k] | Branch (5566:39): [True: 0, False: 3.32k] ------------------ 5567| 3.32k| Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" || ------------------ | Branch (5567:7): [True: 2, False: 3.32k] | Branch (5567:38): [True: 0, False: 3.32k] ------------------ 5568| 3.32k| Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" || ------------------ | Branch (5568:7): [True: 0, False: 3.32k] | Branch (5568:31): [True: 0, False: 3.32k] | Branch (5568:54): [True: 0, False: 3.32k] ------------------ 5569| 3.32k| Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" || ------------------ | Branch (5569:7): [True: 0, False: 3.32k] | Branch (5569:30): [True: 0, False: 3.32k] | Branch (5569:53): [True: 0, False: 3.32k] ------------------ 5570| 3.32k| Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" || ------------------ | Branch (5570:7): [True: 0, False: 3.32k] | Branch (5570:31): [True: 0, False: 3.32k] | Branch (5570:55): [True: 0, False: 3.32k] ------------------ 5571| 3.32k| Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" || ------------------ | Branch (5571:7): [True: 0, False: 3.32k] | Branch (5571:37): [True: 0, False: 3.32k] | Branch (5571:58): [True: 0, False: 3.32k] ------------------ 5572| 3.32k| Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || ------------------ | Branch (5572:7): [True: 0, False: 3.32k] | Branch (5572:38): [True: 0, False: 3.32k] ------------------ 5573| 3.32k| (FullInst.startswith("vmull") && FullInst.endswith(".p64")) || ------------------ | Branch (5573:8): [True: 0, False: 3.32k] | Branch (5573:40): [True: 0, False: 0] ------------------ 5574| 3.32k| Mnemonic == "vmovx" || Mnemonic == "vins") { ------------------ | Branch (5574:7): [True: 0, False: 3.32k] | Branch (5574:30): [True: 0, False: 3.32k] ------------------ 5575| | // These mnemonics are never predicable 5576| 77| CanAcceptPredicationCode = false; 5577| 3.32k| } else if (!isThumb()) { ------------------ | Branch (5577:14): [True: 409, False: 2.91k] ------------------ 5578| | // Some instructions are only predicable in Thumb mode 5579| 409| CanAcceptPredicationCode = 5580| 409| Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && ------------------ | Branch (5580:9): [True: 409, False: 0] | Branch (5580:31): [True: 409, False: 0] | Branch (5580:54): [True: 409, False: 0] ------------------ 5581| 409| Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && ------------------ | Branch (5581:9): [True: 409, False: 0] | Branch (5581:32): [True: 409, False: 0] | Branch (5581:54): [True: 409, False: 0] ------------------ 5582| 409| Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && ------------------ | Branch (5582:9): [True: 409, False: 0] | Branch (5582:30): [True: 409, False: 0] | Branch (5582:51): [True: 409, False: 0] ------------------ 5583| 409| Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && ------------------ | Branch (5583:9): [True: 409, False: 0] | Branch (5583:30): [True: 409, False: 0] | Branch (5583:51): [True: 409, False: 0] ------------------ 5584| 409| Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" && ------------------ | Branch (5584:9): [True: 409, False: 0] | Branch (5584:31): [True: 409, False: 0] | Branch (5584:54): [True: 409, False: 0] ------------------ 5585| 409| Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") && ------------------ | Branch (5585:9): [True: 409, False: 0] | Branch (5585:32): [True: 409, False: 0] ------------------ 5586| 409| !Mnemonic.startswith("srs"); ------------------ | Branch (5586:9): [True: 409, False: 0] ------------------ 5587| 2.91k| } else if (isThumbOne()) { ------------------ | Branch (5587:14): [True: 107, False: 2.81k] ------------------ 5588| 107| if (hasV6MOps()) ------------------ | Branch (5588:9): [True: 12, False: 95] ------------------ 5589| 12| CanAcceptPredicationCode = Mnemonic != "movs"; 5590| 95| else 5591| 95| CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; ------------------ | Branch (5591:34): [True: 95, False: 0] | Branch (5591:55): [True: 95, False: 0] ------------------ 5592| 107| } else 5593| 2.81k| CanAcceptPredicationCode = true; 5594| 3.40k|} ARMAsmParser.cpp:_ZNK12_GLOBAL__N_112ARMAsmParser9hasV6MOpsEv: 264| 107| bool hasV6MOps() const { 265| 107| return getSTI().getFeatureBits()[ARM::HasV6MOps]; 266| 107| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_110ARMOperand11CreateCCOutEjN7llvm_ks5SMLocE: 2581| 763| static std::unique_ptr CreateCCOut(unsigned RegNum, SMLoc S) { 2582| 763| auto Op = make_unique(k_CCOut); 2583| 763| Op->Reg.RegNum = RegNum; 2584| 763| Op->StartLoc = S; 2585| 763| Op->EndLoc = S; 2586| 763| return Op; 2587| 763| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_110ARMOperand14CreateCondCodeEN7llvm_ks5ARMCC9CondCodesENS1_5SMLocE: 2548| 3.38k| SMLoc S) { 2549| 3.38k| auto Op = make_unique(k_CondCode); 2550| 3.38k| Op->CC.Val = CC; 2551| 3.38k| Op->StartLoc = S; 2552| 3.38k| Op->EndLoc = S; 2553| 3.38k| return Op; 2554| 3.38k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_110ARMOperand9CreateImmEPKN7llvm_ks6MCExprENS1_5SMLocES5_: 2744| 18.0k| SMLoc E) { 2745| 18.0k| auto Op = make_unique(k_Immediate); 2746| 18.0k| Op->Imm.Val = Val; 2747| 18.0k| Op->StartLoc = S; 2748| 18.0k| Op->EndLoc = E; 2749| 18.0k| return Op; 2750| 18.0k| } ARMAsmParser.cpp:_ZNK12_GLOBAL__N_112ARMAsmParser8isMClassEv: 300| 182| bool isMClass() const { 301| 182| return getSTI().getFeatureBits()[ARM::FeatureMClass]; 302| 182| } ARMAsmParser.cpp:_ZL15isDataTypeTokenN7llvm_ks9StringRefE: 5827| 5.03k|static bool isDataTypeToken(StringRef Tok) { 5828| 5.03k| return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || ------------------ | Branch (5828:10): [True: 132, False: 4.90k] | Branch (5828:25): [True: 0, False: 4.90k] | Branch (5828:41): [True: 21, False: 4.88k] | Branch (5828:57): [True: 0, False: 4.88k] ------------------ 5829| 4.88k| Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || ------------------ | Branch (5829:5): [True: 1, False: 4.88k] | Branch (5829:21): [True: 0, False: 4.88k] | Branch (5829:38): [True: 45, False: 4.83k] | Branch (5829:55): [True: 32, False: 4.80k] ------------------ 5830| 4.80k| Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || ------------------ | Branch (5830:5): [True: 150, False: 4.65k] | Branch (5830:21): [True: 0, False: 4.65k] | Branch (5830:38): [True: 0, False: 4.65k] | Branch (5830:55): [True: 0, False: 4.65k] ------------------ 5831| 4.65k| Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || ------------------ | Branch (5831:5): [True: 256, False: 4.40k] | Branch (5831:21): [True: 0, False: 4.40k] | Branch (5831:38): [True: 0, False: 4.40k] | Branch (5831:55): [True: 0, False: 4.40k] ------------------ 5832| 4.40k| Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || ------------------ | Branch (5832:5): [True: 0, False: 4.40k] | Branch (5832:21): [True: 0, False: 4.40k] | Branch (5832:38): [True: 1, False: 4.39k] | Branch (5832:55): [True: 0, False: 4.39k] ------------------ 5833| 4.39k| Tok == ".f" || Tok == ".d"; ------------------ | Branch (5833:5): [True: 0, False: 4.39k] | Branch (5833:20): [True: 0, False: 4.39k] ------------------ 5834| 5.03k|} ARMAsmParser.cpp:_ZL24doesIgnoreDataTypeSuffixN7llvm_ks9StringRefES0_: 5839| 638|static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5840| 638| return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); ------------------ | Branch (5840:10): [True: 0, False: 638] | Branch (5840:41): [True: 0, False: 638] ------------------ 5841| 638|} ARMAsmParser.cpp:_ZNK12_GLOBAL__N_112ARMAsmParser7isThumbEv: 248| 43.5k| bool isThumb() const { 249| | // FIXME: Can tablegen auto-generate this? 250| 43.5k| return getSTI().getFeatureBits()[ARM::ModeThumb]; 251| 43.5k| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser12parseOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEENS1_9StringRefERj: 5223| 22.0k|{ 5224| 22.0k| MCAsmParser &Parser = getParser(); 5225| 22.0k| SMLoc S, E; 5226| | 5227| | // Check if the current operand has a custom associated parser, if so, try to 5228| | // custom parse the operand, or fallback to the general approach. 5229| 22.0k| OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic, ErrorCode); 5230| 22.0k| if (ResTy == MatchOperand_Success) ------------------ | Branch (5230:7): [True: 131, False: 21.9k] ------------------ 5231| 131| return false; 5232| | // If there wasn't a custom match, try the generic matcher below. Otherwise, 5233| | // there was a match, but an error occurred, in which case, just return that 5234| | // the operand parsing failed. 5235| 21.9k| if (ResTy == MatchOperand_ParseFail) ------------------ | Branch (5235:7): [True: 1, False: 21.8k] ------------------ 5236| 1| return true; 5237| | 5238| 21.8k| switch (getLexer().getKind()) { 5239| 37| default: ------------------ | Branch (5239:3): [True: 37, False: 21.8k] ------------------ 5240| | //Error(Parser.getTok().getLoc(), "unexpected token in operand"); 5241| 37| ErrorCode = KS_ERR_ASM_ARM_INVALIDOPERAND; 5242| 37| return true; 5243| 14.3k| case AsmToken::Identifier: { ------------------ | Branch (5243:3): [True: 14.3k, False: 7.50k] ------------------ 5244| | // If we've seen a branch mnemonic, the next operand must be a label. This 5245| | // is true even if the label is a register name. So "br r1" means branch to 5246| | // label "r1". 5247| 14.3k| bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; ------------------ | Branch (5247:24): [True: 9, False: 14.3k] | Branch (5247:43): [True: 0, False: 14.3k] ------------------ 5248| 14.3k| if (!ExpectLabel) { ------------------ | Branch (5248:9): [True: 14.3k, False: 9] ------------------ 5249| 14.3k| if (!tryParseRegisterWithWriteBack(Operands)) ------------------ | Branch (5249:11): [True: 2.92k, False: 11.4k] ------------------ 5250| 2.92k| return false; 5251| 11.4k| int Res = tryParseShiftRegister(Operands); 5252| 11.4k| if (Res == 0) // success ------------------ | Branch (5252:11): [True: 0, False: 11.4k] ------------------ 5253| 0| return false; 5254| 11.4k| else if (Res == -1) // irrecoverable error ------------------ | Branch (5254:16): [True: 0, False: 11.4k] ------------------ 5255| 0| return true; 5256| | // If this is VMRS, check for the apsr_nzcv operand. 5257| 11.4k| if (Mnemonic == "vmrs" && ------------------ | Branch (5257:11): [True: 0, False: 11.4k] | Branch (5257:11): [True: 0, False: 11.4k] ------------------ 5258| 0| Parser.getTok().getString().equals_lower("apsr_nzcv")) { ------------------ | Branch (5258:11): [True: 0, False: 0] ------------------ 5259| 0| S = Parser.getTok().getLoc(); 5260| 0| Parser.Lex(); 5261| 0| Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 5262| 0| return false; 5263| 0| } 5264| 11.4k| } 5265| | 5266| | // Fall though for the Identifier case that is not a register or a 5267| | // special name. 5268| 14.3k| } 5269| 11.8k| case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) ------------------ | Branch (5269:3): [True: 404, False: 21.4k] ------------------ 5270| 13.2k| case AsmToken::Integer: // things like 1f and 2b as a branch targets ------------------ | Branch (5270:3): [True: 1.38k, False: 20.5k] ------------------ 5271| 13.2k| case AsmToken::String: // quoted label names. ------------------ | Branch (5271:3): [True: 5, False: 21.8k] ------------------ 5272| 18.0k| case AsmToken::Dot: { // . as a branch target ------------------ | Branch (5272:3): [True: 4.77k, False: 17.1k] ------------------ 5273| | // This was not a register so parse other operands that start with an 5274| | // identifier (like labels) as expressions and create them as immediates. 5275| 18.0k| const MCExpr *IdVal; 5276| 18.0k| S = Parser.getTok().getLoc(); 5277| 18.0k| if (getParser().parseExpression(IdVal)) ------------------ | Branch (5277:9): [True: 670, False: 17.3k] ------------------ 5278| 670| return true; 5279| 17.3k| E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5280| 17.3k| Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 5281| 17.3k| return false; 5282| 18.0k| } 5283| 35| case AsmToken::LBrac: ------------------ | Branch (5283:3): [True: 35, False: 21.8k] ------------------ 5284| 35| return parseMemory(Operands); 5285| 0| case AsmToken::LCurly: ------------------ | Branch (5285:3): [True: 0, False: 21.8k] ------------------ 5286| 0| return parseRegisterList(Operands); 5287| 4| case AsmToken::Dollar: ------------------ | Branch (5287:3): [True: 4, False: 21.8k] ------------------ 5288| 276| case AsmToken::Hash: { ------------------ | Branch (5288:3): [True: 272, False: 21.6k] ------------------ 5289| | // #42 -> immediate. 5290| 276| S = Parser.getTok().getLoc(); 5291| 276| Parser.Lex(); 5292| | 5293| 276| if (Parser.getTok().isNot(AsmToken::Colon)) { ------------------ | Branch (5293:9): [True: 276, False: 0] ------------------ 5294| 276| bool isNegative = Parser.getTok().is(AsmToken::Minus); 5295| 276| const MCExpr *ImmVal; 5296| 276| if (getParser().parseExpression(ImmVal)) ------------------ | Branch (5296:11): [True: 157, False: 119] ------------------ 5297| 157| return true; 5298| 119| const MCConstantExpr *CE = dyn_cast(ImmVal); 5299| 119| if (CE) { ------------------ | Branch (5299:11): [True: 13, False: 106] ------------------ 5300| 13| int32_t Val = CE->getValue(); 5301| 13| if (isNegative && Val == 0) ------------------ | Branch (5301:13): [True: 13, False: 0] | Branch (5301:27): [True: 0, False: 13] ------------------ 5302| 0| ImmVal = MCConstantExpr::create(INT32_MIN, getContext()); 5303| 13| } 5304| 119| E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5305| 119| Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 5306| | 5307| | // There can be a trailing '!' on operands that we want as a separate 5308| | // '!' Token operand. Handle that here. For example, the compatibility 5309| | // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 5310| 119| if (Parser.getTok().is(AsmToken::Exclaim)) { ------------------ | Branch (5310:11): [True: 0, False: 119] ------------------ 5311| 0| Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 5312| 0| Parser.getTok().getLoc())); 5313| 0| Parser.Lex(); // Eat exclaim token 5314| 0| } 5315| 119| return false; 5316| 276| } 5317| | // w/ a ':' after the '#', it's just like a plain ':'. 5318| | // FALLTHROUGH 5319| 276| } 5320| 0| case AsmToken::Colon: { ------------------ | Branch (5320:3): [True: 0, False: 21.8k] ------------------ 5321| 0| S = Parser.getTok().getLoc(); 5322| | // ":lower16:" and ":upper16:" expression prefixes 5323| | // FIXME: Check it's an expression prefix, 5324| | // e.g. (FOO - :lower16:BAR) isn't legal. 5325| 0| ARMMCExpr::VariantKind RefKind; 5326| 0| if (parsePrefix(RefKind)) ------------------ | Branch (5326:9): [True: 0, False: 0] ------------------ 5327| 0| return true; 5328| | 5329| 0| const MCExpr *SubExprVal; 5330| 0| if (getParser().parseExpression(SubExprVal)) ------------------ | Branch (5330:9): [True: 0, False: 0] ------------------ 5331| 0| return true; 5332| | 5333| 0| const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal, 5334| 0| getContext()); 5335| 0| E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5336| 0| Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 5337| 0| return false; 5338| 0| } 5339| 589| case AsmToken::Equal: { ------------------ | Branch (5339:3): [True: 589, False: 21.3k] ------------------ 5340| 589| S = Parser.getTok().getLoc(); 5341| 589| if (Mnemonic != "ldr") { // only parse for ldr pseudo (e.g. ldr r0, =val) ------------------ | Branch (5341:9): [True: 2, False: 587] ------------------ 5342| | //return Error(S, "unexpected token in operand"); 5343| 2| ErrorCode = KS_ERR_ASM_ARM_INVALIDOPERAND; 5344| 2| return true; 5345| 2| } 5346| | 5347| 587| Parser.Lex(); // Eat '=' 5348| 587| const MCExpr *SubExprVal; 5349| 587| if (getParser().parseExpression(SubExprVal)) ------------------ | Branch (5349:9): [True: 71, False: 516] ------------------ 5350| 71| return true; 5351| 516| E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5352| | 5353| 516| const MCExpr *CPLoc = 5354| 516| getTargetStreamer().addConstantPoolEntry(SubExprVal, S); 5355| 516| Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E)); 5356| 516| return false; 5357| 587| } 5358| 21.8k| } 5359| 21.8k|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser21parseBankedRegOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 4190| 86|ARMAsmParser::parseBankedRegOperand(OperandVector &Operands, unsigned int &ErrorCode) { 4191| 86| MCAsmParser &Parser = getParser(); 4192| 86| SMLoc S = Parser.getTok().getLoc(); 4193| 86| const AsmToken &Tok = Parser.getTok(); 4194| 86| if (!Tok.is(AsmToken::Identifier)) ------------------ | Branch (4194:7): [True: 9, False: 77] ------------------ 4195| 9| return MatchOperand_NoMatch; 4196| 77| StringRef RegName = Tok.getString(); 4197| | 4198| | // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM 4199| | // and bit 5 is R. 4200| 77| unsigned Encoding = StringSwitch(RegName.lower()) 4201| 77| .Case("r8_usr", 0x00) 4202| 77| .Case("r9_usr", 0x01) 4203| 77| .Case("r10_usr", 0x02) 4204| 77| .Case("r11_usr", 0x03) 4205| 77| .Case("r12_usr", 0x04) 4206| 77| .Case("sp_usr", 0x05) 4207| 77| .Case("lr_usr", 0x06) 4208| 77| .Case("r8_fiq", 0x08) 4209| 77| .Case("r9_fiq", 0x09) 4210| 77| .Case("r10_fiq", 0x0a) 4211| 77| .Case("r11_fiq", 0x0b) 4212| 77| .Case("r12_fiq", 0x0c) 4213| 77| .Case("sp_fiq", 0x0d) 4214| 77| .Case("lr_fiq", 0x0e) 4215| 77| .Case("lr_irq", 0x10) 4216| 77| .Case("sp_irq", 0x11) 4217| 77| .Case("lr_svc", 0x12) 4218| 77| .Case("sp_svc", 0x13) 4219| 77| .Case("lr_abt", 0x14) 4220| 77| .Case("sp_abt", 0x15) 4221| 77| .Case("lr_und", 0x16) 4222| 77| .Case("sp_und", 0x17) 4223| 77| .Case("lr_mon", 0x1c) 4224| 77| .Case("sp_mon", 0x1d) 4225| 77| .Case("elr_hyp", 0x1e) 4226| 77| .Case("sp_hyp", 0x1f) 4227| 77| .Case("spsr_fiq", 0x2e) 4228| 77| .Case("spsr_irq", 0x30) 4229| 77| .Case("spsr_svc", 0x32) 4230| 77| .Case("spsr_abt", 0x34) 4231| 77| .Case("spsr_und", 0x36) 4232| 77| .Case("spsr_mon", 0x3c) 4233| 77| .Case("spsr_hyp", 0x3e) 4234| 77| .Default(~0U); 4235| | 4236| 77| if (Encoding == ~0U) ------------------ | Branch (4236:7): [True: 77, False: 0] ------------------ 4237| 77| return MatchOperand_NoMatch; 4238| | 4239| 0| Parser.Lex(); // Eat identifier token. 4240| 0| Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); 4241| 0| return MatchOperand_Success; 4242| 77|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser21parseCoprocNumOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 3280| 312|ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands, unsigned int &ErrorCode) { 3281| 312| MCAsmParser &Parser = getParser(); 3282| 312| SMLoc S = Parser.getTok().getLoc(); 3283| 312| const AsmToken &Tok = Parser.getTok(); 3284| 312| if (Tok.isNot(AsmToken::Identifier)) ------------------ | Branch (3284:7): [True: 272, False: 40] ------------------ 3285| 272| return MatchOperand_NoMatch; 3286| | 3287| 40| int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 3288| 40| if (Num == -1) ------------------ | Branch (3288:7): [True: 40, False: 0] ------------------ 3289| 40| return MatchOperand_NoMatch; 3290| | // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions 3291| 0| if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11)) ------------------ | Branch (3291:8): [True: 0, False: 0] | Branch (3291:22): [True: 0, False: 0] | Branch (3291:38): [True: 0, False: 0] | Branch (3291:51): [True: 0, False: 0] ------------------ 3292| 0| return MatchOperand_NoMatch; 3293| | 3294| 0| Parser.Lex(); // Eat identifier token. 3295| 0| Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 3296| 0| return MatchOperand_Success; 3297| 0|} ARMAsmParser.cpp:_ZL27MatchCoprocessorOperandNameN7llvm_ks9StringRefEc: 3200| 324|static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 3201| | // Use the same layout as the tablegen'erated register name matcher. Ugly, 3202| | // but efficient. 3203| 324| if (Name.size() < 2 || Name[0] != CoprocOp) ------------------ | Branch (3203:7): [True: 0, False: 324] | Branch (3203:26): [True: 324, False: 0] ------------------ 3204| 324| return -1; 3205| 0| Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); ------------------ | Branch (3205:10): [True: 0, False: 0] ------------------ 3206| | 3207| 0| switch (Name.size()) { 3208| 0| default: return -1; ------------------ | Branch (3208:3): [True: 0, False: 0] ------------------ 3209| 0| case 1: ------------------ | Branch (3209:3): [True: 0, False: 0] ------------------ 3210| 0| switch (Name[0]) { 3211| 0| default: return -1; ------------------ | Branch (3211:5): [True: 0, False: 0] ------------------ 3212| 0| case '0': return 0; ------------------ | Branch (3212:5): [True: 0, False: 0] ------------------ 3213| 0| case '1': return 1; ------------------ | Branch (3213:5): [True: 0, False: 0] ------------------ 3214| 0| case '2': return 2; ------------------ | Branch (3214:5): [True: 0, False: 0] ------------------ 3215| 0| case '3': return 3; ------------------ | Branch (3215:5): [True: 0, False: 0] ------------------ 3216| 0| case '4': return 4; ------------------ | Branch (3216:5): [True: 0, False: 0] ------------------ 3217| 0| case '5': return 5; ------------------ | Branch (3217:5): [True: 0, False: 0] ------------------ 3218| 0| case '6': return 6; ------------------ | Branch (3218:5): [True: 0, False: 0] ------------------ 3219| 0| case '7': return 7; ------------------ | Branch (3219:5): [True: 0, False: 0] ------------------ 3220| 0| case '8': return 8; ------------------ | Branch (3220:5): [True: 0, False: 0] ------------------ 3221| 0| case '9': return 9; ------------------ | Branch (3221:5): [True: 0, False: 0] ------------------ 3222| 0| } 3223| 0| case 2: ------------------ | Branch (3223:3): [True: 0, False: 0] ------------------ 3224| 0| if (Name[0] != '1') ------------------ | Branch (3224:9): [True: 0, False: 0] ------------------ 3225| 0| return -1; 3226| 0| switch (Name[1]) { 3227| 0| default: return -1; ------------------ | Branch (3227:5): [True: 0, False: 0] ------------------ 3228| | // CP10 and CP11 are VFP/NEON and so vector instructions should be used. 3229| | // However, old cores (v5/v6) did use them in that way. 3230| 0| case '0': return 10; ------------------ | Branch (3230:5): [True: 0, False: 0] ------------------ 3231| 0| case '1': return 11; ------------------ | Branch (3231:5): [True: 0, False: 0] ------------------ 3232| 0| case '2': return 12; ------------------ | Branch (3232:5): [True: 0, False: 0] ------------------ 3233| 0| case '3': return 13; ------------------ | Branch (3233:5): [True: 0, False: 0] ------------------ 3234| 0| case '4': return 14; ------------------ | Branch (3234:5): [True: 0, False: 0] ------------------ 3235| 0| case '5': return 15; ------------------ | Branch (3235:5): [True: 0, False: 0] ------------------ 3236| 0| } 3237| 0| } 3238| 0|} ARMAsmParser.cpp:_ZNK12_GLOBAL__N_112ARMAsmParser8hasV8OpsEv: 270| 504| bool hasV8Ops() const { 271| 504| return getSTI().getFeatureBits()[ARM::HasV8Ops]; 272| 504| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser24parseCoprocOptionOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 3323| 81|{ 3324| 81| MCAsmParser &Parser = getParser(); 3325| 81| SMLoc S = Parser.getTok().getLoc(); 3326| | 3327| | // If this isn't a '{', this isn't a coprocessor immediate operand. 3328| 81| if (Parser.getTok().isNot(AsmToken::LCurly)) ------------------ | Branch (3328:7): [True: 81, False: 0] ------------------ 3329| 81| return MatchOperand_NoMatch; 3330| 0| Parser.Lex(); // Eat the '{' 3331| | 3332| 0| const MCExpr *Expr; 3333| | //SMLoc Loc = Parser.getTok().getLoc(); 3334| 0| if (getParser().parseExpression(Expr)) { ------------------ | Branch (3334:7): [True: 0, False: 0] ------------------ 3335| | //Error(Loc, "illegal expression"); 3336| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3337| 0| return MatchOperand_ParseFail; 3338| 0| } 3339| 0| const MCConstantExpr *CE = dyn_cast(Expr); 3340| 0| if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { ------------------ | Branch (3340:7): [True: 0, False: 0] | Branch (3340:14): [True: 0, False: 0] | Branch (3340:36): [True: 0, False: 0] ------------------ 3341| | //Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 3342| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3343| 0| return MatchOperand_ParseFail; 3344| 0| } 3345| 0| int Val = CE->getValue(); 3346| | 3347| | // Check for and consume the closing '}' 3348| 0| if (Parser.getTok().isNot(AsmToken::RCurly)) ------------------ | Branch (3348:7): [True: 0, False: 0] ------------------ 3349| 0| return MatchOperand_ParseFail; 3350| 0| SMLoc E = Parser.getTok().getEndLoc(); 3351| 0| Parser.Lex(); // Eat the '}' 3352| | 3353| 0| Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 3354| 0| return MatchOperand_Success; 3355| 0|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser21parseCoprocRegOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 3303| 324|ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands, unsigned int &ErrorCode) { 3304| 324| MCAsmParser &Parser = getParser(); 3305| 324| SMLoc S = Parser.getTok().getLoc(); 3306| 324| const AsmToken &Tok = Parser.getTok(); 3307| 324| if (Tok.isNot(AsmToken::Identifier)) ------------------ | Branch (3307:7): [True: 40, False: 284] ------------------ 3308| 40| return MatchOperand_NoMatch; 3309| | 3310| 284| int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 3311| 284| if (Reg == -1) ------------------ | Branch (3311:7): [True: 284, False: 0] ------------------ 3312| 284| return MatchOperand_NoMatch; 3313| | 3314| 0| Parser.Lex(); // Eat identifier token. 3315| 0| Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 3316| 0| return MatchOperand_Success; 3317| 284|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser10parseFPImmERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 5133| 48|ARMAsmParser::parseFPImm(OperandVector &Operands, unsigned int &ErrorCode) { 5134| 48| MCAsmParser &Parser = getParser(); 5135| | // Anything that can accept a floating point constant as an operand 5136| | // needs to go through here, as the regular parseExpression is 5137| | // integer only. 5138| | // 5139| | // This routine still creates a generic Immediate operand, containing 5140| | // a bitcast of the 64-bit floating point value. The various operands 5141| | // that accept floats can check whether the value is valid for them 5142| | // via the standard is*() predicates. 5143| | 5144| 48| SMLoc S = Parser.getTok().getLoc(); 5145| | 5146| 48| if (Parser.getTok().isNot(AsmToken::Hash) && ------------------ | Branch (5146:7): [True: 48, False: 0] ------------------ 5147| 48| Parser.getTok().isNot(AsmToken::Dollar)) ------------------ | Branch (5147:7): [True: 48, False: 0] ------------------ 5148| 48| return MatchOperand_NoMatch; 5149| | 5150| | // Disambiguate the VMOV forms that can accept an FP immediate. 5151| | // vmov.f32 , #imm 5152| | // vmov.f64 , #imm 5153| | // vmov.f32 , #imm @ vector f32x2 5154| | // vmov.f32 , #imm @ vector f32x4 5155| | // 5156| | // There are also the NEON VMOV instructions which expect an 5157| | // integer constant. Make sure we don't try to parse an FPImm 5158| | // for these: 5159| | // vmov.i{8|16|32|64} , #imm 5160| 0| ARMOperand &TyOp = static_cast(*Operands[2]); 5161| 0| bool isVmovf = TyOp.isToken() && ------------------ | Branch (5161:18): [True: 0, False: 0] ------------------ 5162| 0| (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" || ------------------ | Branch (5162:19): [True: 0, False: 0] | Branch (5162:48): [True: 0, False: 0] ------------------ 5163| 0| TyOp.getToken() == ".f16"); ------------------ | Branch (5163:19): [True: 0, False: 0] ------------------ 5164| 0| ARMOperand &Mnemonic = static_cast(*Operands[0]); 5165| 0| bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" || ------------------ | Branch (5165:19): [True: 0, False: 0] | Branch (5165:42): [True: 0, False: 0] ------------------ 5166| 0| Mnemonic.getToken() == "fconsts"); ------------------ | Branch (5166:42): [True: 0, False: 0] ------------------ 5167| 0| if (!(isVmovf || isFconst)) ------------------ | Branch (5167:9): [True: 0, False: 0] | Branch (5167:20): [True: 0, False: 0] ------------------ 5168| 0| return MatchOperand_NoMatch; 5169| | 5170| 0| Parser.Lex(); // Eat '#' or '$'. 5171| | 5172| | // Handle negation, as that still comes through as a separate token. 5173| 0| bool isNegative = false; 5174| 0| if (Parser.getTok().is(AsmToken::Minus)) { ------------------ | Branch (5174:7): [True: 0, False: 0] ------------------ 5175| 0| isNegative = true; 5176| 0| Parser.Lex(); 5177| 0| } 5178| 0| const AsmToken &Tok = Parser.getTok(); 5179| | //SMLoc Loc = Tok.getLoc(); 5180| 0| if (Tok.is(AsmToken::Real) && isVmovf) { ------------------ | Branch (5180:7): [True: 0, False: 0] | Branch (5180:33): [True: 0, False: 0] ------------------ 5181| 0| APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 5182| 0| if (RealVal.bitcastToAPInt().getActiveBits() > 64) ------------------ | Branch (5182:9): [True: 0, False: 0] ------------------ 5183| 0| return MatchOperand_ParseFail; 5184| 0| uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 5185| | // If we had a '-' in front, toggle the sign bit. 5186| 0| IntVal ^= (uint64_t)isNegative << 31; 5187| 0| Parser.Lex(); // Eat the token. 5188| 0| Operands.push_back(ARMOperand::CreateImm( 5189| 0| MCConstantExpr::create(IntVal, getContext()), 5190| 0| S, Parser.getTok().getLoc())); 5191| 0| return MatchOperand_Success; 5192| 0| } 5193| | // Also handle plain integers. Instructions which allow floating point 5194| | // immediates also allow a raw encoded 8-bit value. 5195| 0| if (Tok.is(AsmToken::Integer) && isFconst) { ------------------ | Branch (5195:7): [True: 0, False: 0] | Branch (5195:36): [True: 0, False: 0] ------------------ 5196| 0| bool valid; 5197| 0| int64_t Val = Tok.getIntVal(valid); 5198| 0| if (!valid) ------------------ | Branch (5198:9): [True: 0, False: 0] ------------------ 5199| 0| return MatchOperand_ParseFail; 5200| 0| Parser.Lex(); // Eat the token. 5201| 0| if (Val > 255 || Val < 0) { ------------------ | Branch (5201:9): [True: 0, False: 0] | Branch (5201:22): [True: 0, False: 0] ------------------ 5202| | //Error(Loc, "encoded floating point value out of range"); 5203| 0| return MatchOperand_ParseFail; 5204| 0| } 5205| 0| float RealVal = ARM_AM::getFPImmFloat(Val); 5206| 0| if (APFloat(RealVal).bitcastToAPInt().getActiveBits() > 64) ------------------ | Branch (5206:9): [True: 0, False: 0] ------------------ 5207| 0| return MatchOperand_ParseFail; 5208| 0| Val = APFloat(RealVal).bitcastToAPInt().getZExtValue(); 5209| | 5210| 0| Operands.push_back(ARMOperand::CreateImm( 5211| 0| MCConstantExpr::create(Val, getContext()), S, 5212| 0| Parser.getTok().getLoc())); 5213| 0| return MatchOperand_Success; 5214| 0| } 5215| | 5216| | //Error(Loc, "invalid floating point immediate"); 5217| 0| return MatchOperand_ParseFail; 5218| 0|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser19parseMSRMaskOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 4037| 187|ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands, unsigned int &ErrorCode) { 4038| 187| MCAsmParser &Parser = getParser(); 4039| 187| SMLoc S = Parser.getTok().getLoc(); 4040| 187| const AsmToken &Tok = Parser.getTok(); 4041| 187| if (!Tok.is(AsmToken::Identifier)) ------------------ | Branch (4041:7): [True: 9, False: 178] ------------------ 4042| 9| return MatchOperand_NoMatch; 4043| 178| StringRef Mask = Tok.getString(); 4044| | 4045| 178| if (isMClass()) { ------------------ | Branch (4045:7): [True: 101, False: 77] ------------------ 4046| | // See ARMv6-M 10.1.1 4047| 101| std::string Name = Mask.lower(); 4048| 101| unsigned FlagsVal = StringSwitch(Name) 4049| | // Note: in the documentation: 4050| | // ARM deprecates using MSR APSR without a _ qualifier as an alias 4051| | // for MSR APSR_nzcvq. 4052| | // but we do make it an alias here. This is so to get the "mask encoding" 4053| | // bits correct on MSR APSR writes. 4054| | // 4055| | // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 4056| | // should really only be allowed when writing a special register. Note 4057| | // they get dropped in the MRS instruction reading a special register as 4058| | // the SYSm field is only 8 bits. 4059| 101| .Case("apsr", 0x800) 4060| 101| .Case("apsr_nzcvq", 0x800) 4061| 101| .Case("apsr_g", 0x400) 4062| 101| .Case("apsr_nzcvqg", 0xc00) 4063| 101| .Case("iapsr", 0x801) 4064| 101| .Case("iapsr_nzcvq", 0x801) 4065| 101| .Case("iapsr_g", 0x401) 4066| 101| .Case("iapsr_nzcvqg", 0xc01) 4067| 101| .Case("eapsr", 0x802) 4068| 101| .Case("eapsr_nzcvq", 0x802) 4069| 101| .Case("eapsr_g", 0x402) 4070| 101| .Case("eapsr_nzcvqg", 0xc02) 4071| 101| .Case("xpsr", 0x803) 4072| 101| .Case("xpsr_nzcvq", 0x803) 4073| 101| .Case("xpsr_g", 0x403) 4074| 101| .Case("xpsr_nzcvqg", 0xc03) 4075| 101| .Case("ipsr", 0x805) 4076| 101| .Case("epsr", 0x806) 4077| 101| .Case("iepsr", 0x807) 4078| 101| .Case("msp", 0x808) 4079| 101| .Case("psp", 0x809) 4080| 101| .Case("primask", 0x810) 4081| 101| .Case("basepri", 0x811) 4082| 101| .Case("basepri_max", 0x812) 4083| 101| .Case("faultmask", 0x813) 4084| 101| .Case("control", 0x814) 4085| 101| .Case("msplim", 0x80a) 4086| 101| .Case("psplim", 0x80b) 4087| 101| .Case("msp_ns", 0x888) 4088| 101| .Case("psp_ns", 0x889) 4089| 101| .Case("msplim_ns", 0x88a) 4090| 101| .Case("psplim_ns", 0x88b) 4091| 101| .Case("primask_ns", 0x890) 4092| 101| .Case("basepri_ns", 0x891) 4093| 101| .Case("basepri_max_ns", 0x892) 4094| 101| .Case("faultmask_ns", 0x893) 4095| 101| .Case("control_ns", 0x894) 4096| 101| .Case("sp_ns", 0x898) 4097| 101| .Default(~0U); 4098| | 4099| 101| if (FlagsVal == ~0U) ------------------ | Branch (4099:9): [True: 101, False: 0] ------------------ 4100| 101| return MatchOperand_NoMatch; 4101| | 4102| 0| if (!hasDSP() && (FlagsVal & 0x400)) ------------------ | Branch (4102:9): [True: 0, False: 0] | Branch (4102:22): [True: 0, False: 0] ------------------ 4103| | // The _g and _nzcvqg versions are only valid if the DSP extension is 4104| | // available. 4105| 0| return MatchOperand_NoMatch; 4106| | 4107| 0| if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) ------------------ | Branch (4107:9): [True: 0, False: 0] | Branch (4107:24): [True: 0, False: 0] | Branch (4107:45): [True: 0, False: 0] ------------------ 4108| | // basepri, basepri_max and faultmask only valid for V7m. 4109| 0| return MatchOperand_NoMatch; 4110| | 4111| 0| if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b || ------------------ | Branch (4111:9): [True: 0, False: 0] | Branch (4111:28): [True: 0, False: 0] | Branch (4111:49): [True: 0, False: 0] ------------------ 4112| 0| (FlagsVal > 0x814 && FlagsVal < 0xc00))) ------------------ | Branch (4112:31): [True: 0, False: 0] | Branch (4112:51): [True: 0, False: 0] ------------------ 4113| 0| return MatchOperand_NoMatch; 4114| | 4115| 0| if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b || ------------------ | Branch (4115:9): [True: 0, False: 0] | Branch (4115:31): [True: 0, False: 0] | Branch (4115:52): [True: 0, False: 0] ------------------ 4116| 0| (FlagsVal > 0x890 && FlagsVal <= 0x893))) ------------------ | Branch (4116:32): [True: 0, False: 0] | Branch (4116:52): [True: 0, False: 0] ------------------ 4117| 0| return MatchOperand_NoMatch; 4118| | 4119| 0| Parser.Lex(); // Eat identifier token. 4120| 0| Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 4121| 0| return MatchOperand_Success; 4122| 0| } 4123| | 4124| | // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 4125| 77| size_t Start = 0, Next = Mask.find('_'); 4126| 77| StringRef Flags = ""; 4127| 77| std::string SpecReg = Mask.slice(Start, Next).lower(); 4128| 77| if (Next != StringRef::npos) ------------------ | Branch (4128:7): [True: 5, False: 72] ------------------ 4129| 5| Flags = Mask.slice(Next+1, Mask.size()); 4130| | 4131| | // FlagsVal contains the complete mask: 4132| | // 3-0: Mask 4133| | // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4134| 77| unsigned FlagsVal = 0; 4135| | 4136| 77| if (SpecReg == "apsr") { ------------------ | Branch (4136:7): [True: 0, False: 77] ------------------ 4137| 0| FlagsVal = StringSwitch(Flags) 4138| 0| .Case("nzcvq", 0x8) // same as CPSR_f 4139| 0| .Case("g", 0x4) // same as CPSR_s 4140| 0| .Case("nzcvqg", 0xc) // same as CPSR_fs 4141| 0| .Default(~0U); 4142| | 4143| 0| if (FlagsVal == ~0U) { ------------------ | Branch (4143:9): [True: 0, False: 0] ------------------ 4144| 0| if (!Flags.empty()) ------------------ | Branch (4144:11): [True: 0, False: 0] ------------------ 4145| 0| return MatchOperand_NoMatch; 4146| 0| else 4147| 0| FlagsVal = 8; // No flag 4148| 0| } 4149| 77| } else if (SpecReg == "cpsr" || SpecReg == "spsr") { ------------------ | Branch (4149:14): [True: 0, False: 77] | Branch (4149:35): [True: 65, False: 12] ------------------ 4150| | // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 4151| 65| if (Flags == "all" || Flags == "") ------------------ | Branch (4151:9): [True: 0, False: 65] | Branch (4151:9): [True: 65, False: 0] | Branch (4151:27): [True: 65, False: 0] ------------------ 4152| 65| Flags = "fc"; 4153| 195| for (int i = 0, e = Flags.size(); i != e; ++i) { ------------------ | Branch (4153:39): [True: 130, False: 65] ------------------ 4154| 130| unsigned Flag = StringSwitch(Flags.substr(i, 1)) 4155| 130| .Case("c", 1) 4156| 130| .Case("x", 2) 4157| 130| .Case("s", 4) 4158| 130| .Case("f", 8) 4159| 130| .Default(~0U); 4160| | 4161| | // If some specific flag is already set, it means that some letter is 4162| | // present more than once, this is not acceptable. 4163| 130| if (FlagsVal == ~0U || (FlagsVal & Flag)) ------------------ | Branch (4163:11): [True: 0, False: 130] | Branch (4163:30): [True: 0, False: 130] ------------------ 4164| 0| return MatchOperand_NoMatch; 4165| 130| FlagsVal |= Flag; 4166| 130| } 4167| 65| } else // No match for special register. 4168| 12| return MatchOperand_NoMatch; 4169| | 4170| | // Special register without flags is NOT equivalent to "fc" flags. 4171| | // NOTE: This is a divergence from gas' behavior. Uncommenting the following 4172| | // two lines would enable gas compatibility at the expense of breaking 4173| | // round-tripping. 4174| | // 4175| | // if (!FlagsVal) 4176| | // FlagsVal = 0x9; 4177| | 4178| | // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4179| 65| if (SpecReg == "spsr") ------------------ | Branch (4179:7): [True: 65, False: 0] ------------------ 4180| 65| FlagsVal |= 16; 4181| | 4182| 65| Parser.Lex(); // Eat identifier token. 4183| 65| Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 4184| 65| return MatchOperand_Success; 4185| 77|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_110ARMOperand13CreateMSRMaskEjN7llvm_ks5SMLocE: 2811| 65| static std::unique_ptr CreateMSRMask(unsigned MMask, SMLoc S) { 2812| 65| auto Op = make_unique(k_MSRMask); 2813| 65| Op->MMask.Val = MMask; 2814| 65| Op->StartLoc = S; 2815| 65| Op->EndLoc = S; 2816| 65| return Op; 2817| 65| } ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser25parseMemBarrierOptOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 3870| 4|ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands, unsigned int &ErrorCode) { 3871| 4| MCAsmParser &Parser = getParser(); 3872| 4| SMLoc S = Parser.getTok().getLoc(); 3873| 4| const AsmToken &Tok = Parser.getTok(); 3874| 4| unsigned Opt; 3875| | 3876| 4| if (Tok.is(AsmToken::Identifier)) { ------------------ | Branch (3876:7): [True: 4, False: 0] ------------------ 3877| 4| StringRef OptStr = Tok.getString(); 3878| | 3879| 4| Opt = StringSwitch(OptStr.slice(0, OptStr.size()).lower()) 3880| 4| .Case("sy", ARM_MB::SY) 3881| 4| .Case("st", ARM_MB::ST) 3882| 4| .Case("ld", ARM_MB::LD) 3883| 4| .Case("sh", ARM_MB::ISH) 3884| 4| .Case("ish", ARM_MB::ISH) 3885| 4| .Case("shst", ARM_MB::ISHST) 3886| 4| .Case("ishst", ARM_MB::ISHST) 3887| 4| .Case("ishld", ARM_MB::ISHLD) 3888| 4| .Case("nsh", ARM_MB::NSH) 3889| 4| .Case("un", ARM_MB::NSH) 3890| 4| .Case("nshst", ARM_MB::NSHST) 3891| 4| .Case("nshld", ARM_MB::NSHLD) 3892| 4| .Case("unst", ARM_MB::NSHST) 3893| 4| .Case("osh", ARM_MB::OSH) 3894| 4| .Case("oshst", ARM_MB::OSHST) 3895| 4| .Case("oshld", ARM_MB::OSHLD) 3896| 4| .Default(~0U); 3897| | 3898| | // ishld, oshld, nshld and ld are only available from ARMv8. 3899| 4| if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || ------------------ | Branch (3899:9): [True: 0, False: 4] | Branch (3899:25): [True: 0, False: 0] | Branch (3899:49): [True: 0, False: 0] ------------------ 3900| 0| Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) ------------------ | Branch (3900:25): [True: 0, False: 0] | Branch (3900:49): [True: 0, False: 0] ------------------ 3901| 0| Opt = ~0U; 3902| | 3903| 4| if (Opt == ~0U) ------------------ | Branch (3903:9): [True: 4, False: 0] ------------------ 3904| 4| return MatchOperand_NoMatch; 3905| | 3906| 0| Parser.Lex(); // Eat identifier token. 3907| 0| } else if (Tok.is(AsmToken::Hash) || ------------------ | Branch (3907:14): [True: 0, False: 0] ------------------ 3908| 0| Tok.is(AsmToken::Dollar) || ------------------ | Branch (3908:14): [True: 0, False: 0] ------------------ 3909| 0| Tok.is(AsmToken::Integer)) { ------------------ | Branch (3909:14): [True: 0, False: 0] ------------------ 3910| 0| if (Parser.getTok().isNot(AsmToken::Integer)) ------------------ | Branch (3910:9): [True: 0, False: 0] ------------------ 3911| 0| Parser.Lex(); // Eat '#' or '$'. 3912| | 3913| | //SMLoc Loc = Parser.getTok().getLoc(); 3914| | 3915| 0| const MCExpr *MemBarrierID; 3916| 0| if (getParser().parseExpression(MemBarrierID)) { ------------------ | Branch (3916:9): [True: 0, False: 0] ------------------ 3917| | //Error(Loc, "illegal expression"); 3918| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3919| 0| return MatchOperand_ParseFail; 3920| 0| } 3921| | 3922| 0| const MCConstantExpr *CE = dyn_cast(MemBarrierID); 3923| 0| if (!CE) { ------------------ | Branch (3923:9): [True: 0, False: 0] ------------------ 3924| | //Error(Loc, "constant expression expected"); 3925| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3926| 0| return MatchOperand_ParseFail; 3927| 0| } 3928| | 3929| 0| int Val = CE->getValue(); 3930| 0| if (Val & ~0xf) { ------------------ | Branch (3930:9): [True: 0, False: 0] ------------------ 3931| | //Error(Loc, "immediate value out of range"); 3932| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3933| 0| return MatchOperand_ParseFail; 3934| 0| } 3935| | 3936| 0| Opt = ARM_MB::RESERVED_0 + Val; 3937| 0| } else 3938| 0| return MatchOperand_ParseFail; 3939| | 3940| 0| Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3941| 0| return MatchOperand_Success; 3942| 4|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser11parseModImmERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 4466| 75|{ 4467| 75| MCAsmParser &Parser = getParser(); 4468| 75| MCAsmLexer &Lexer = getLexer(); 4469| 75| int64_t Imm1, Imm2; 4470| | 4471| 75| SMLoc S = Parser.getTok().getLoc(); 4472| | 4473| | // 1) A mod_imm operand can appear in the place of a register name: 4474| | // add r0, #mod_imm 4475| | // add r0, r0, #mod_imm 4476| | // to correctly handle the latter, we bail out as soon as we see an 4477| | // identifier. 4478| | // 4479| | // 2) Similarly, we do not want to parse into complex operands: 4480| | // mov r0, #mod_imm 4481| | // mov r0, :lower16:(_foo) 4482| 75| if (Parser.getTok().is(AsmToken::Identifier) || ------------------ | Branch (4482:7): [True: 74, False: 1] ------------------ 4483| 1| Parser.getTok().is(AsmToken::Colon)) ------------------ | Branch (4483:7): [True: 0, False: 1] ------------------ 4484| 74| return MatchOperand_NoMatch; 4485| | 4486| | // Hash (dollar) is optional as per the ARMARM 4487| 1| if (Parser.getTok().is(AsmToken::Hash) || ------------------ | Branch (4487:7): [True: 0, False: 1] ------------------ 4488| 1| Parser.getTok().is(AsmToken::Dollar)) { ------------------ | Branch (4488:7): [True: 0, False: 1] ------------------ 4489| | // Avoid parsing into complex operands (#:) 4490| 0| if (Lexer.peekTok().is(AsmToken::Colon)) ------------------ | Branch (4490:9): [True: 0, False: 0] ------------------ 4491| 0| return MatchOperand_NoMatch; 4492| | 4493| | // Eat the hash (dollar) 4494| 0| Parser.Lex(); 4495| 0| } 4496| | 4497| 1| SMLoc Sx1, Ex1; 4498| 1| Sx1 = Parser.getTok().getLoc(); 4499| 1| const MCExpr *Imm1Exp; 4500| 1| if (getParser().parseExpression(Imm1Exp, Ex1)) { ------------------ | Branch (4500:7): [True: 1, False: 0] ------------------ 4501| | //Error(Sx1, "malformed expression"); 4502| 1| ErrorCode = KS_ERR_ASM_ARM_INVALIDOPERAND; 4503| 1| return MatchOperand_ParseFail; 4504| 1| } 4505| | 4506| 0| const MCConstantExpr *CE = dyn_cast(Imm1Exp); 4507| | 4508| 0| if (CE) { ------------------ | Branch (4508:7): [True: 0, False: 0] ------------------ 4509| | // Immediate must fit within 32-bits 4510| 0| Imm1 = CE->getValue(); 4511| 0| int Enc = ARM_AM::getSOImmVal(Imm1); 4512| 0| if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { ------------------ | Branch (4512:9): [True: 0, False: 0] | Branch (4512:22): [True: 0, False: 0] ------------------ 4513| | // We have a match! 4514| 0| Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), 4515| 0| (Enc & 0xF00) >> 7, 4516| 0| Sx1, Ex1)); 4517| 0| return MatchOperand_Success; 4518| 0| } 4519| | 4520| | // We have parsed an immediate which is not for us, fallback to a plain 4521| | // immediate. This can happen for instruction aliases. For an example, 4522| | // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform 4523| | // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite 4524| | // instruction with a mod_imm operand. The alias is defined such that the 4525| | // parser method is shared, that's why we have to do this here. 4526| 0| if (Parser.getTok().is(AsmToken::EndOfStatement)) { ------------------ | Branch (4526:9): [True: 0, False: 0] ------------------ 4527| 0| Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); 4528| 0| return MatchOperand_Success; 4529| 0| } 4530| 0| } else { 4531| | // Operands like #(l1 - l2) can only be evaluated at a later stage (via an 4532| | // MCFixup). Fallback to a plain immediate. 4533| 0| Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); 4534| 0| return MatchOperand_Success; 4535| 0| } 4536| | 4537| | // From this point onward, we expect the input to be a (#bits, #rot) pair 4538| 0| if (Parser.getTok().isNot(AsmToken::Comma)) { ------------------ | Branch (4538:7): [True: 0, False: 0] ------------------ 4539| | //Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]"); 4540| 0| ErrorCode = KS_ERR_ASM_ARM_INVALIDOPERAND; 4541| 0| return MatchOperand_ParseFail; 4542| 0| } 4543| | 4544| 0| if (Imm1 & ~0xFF) { ------------------ | Branch (4544:7): [True: 0, False: 0] ------------------ 4545| | // Error(Sx1, "immediate operand must a number in the range [0, 255]"); 4546| 0| ErrorCode = KS_ERR_ASM_ARM_INVALIDOPERAND; 4547| 0| return MatchOperand_ParseFail; 4548| 0| } 4549| | 4550| | // Eat the comma 4551| 0| Parser.Lex(); 4552| | 4553| | // Repeat for #rot 4554| 0| SMLoc Sx2, Ex2; 4555| 0| Sx2 = Parser.getTok().getLoc(); 4556| | 4557| | // Eat the optional hash (dollar) 4558| 0| if (Parser.getTok().is(AsmToken::Hash) || ------------------ | Branch (4558:7): [True: 0, False: 0] ------------------ 4559| 0| Parser.getTok().is(AsmToken::Dollar)) ------------------ | Branch (4559:7): [True: 0, False: 0] ------------------ 4560| 0| Parser.Lex(); 4561| | 4562| 0| const MCExpr *Imm2Exp; 4563| 0| if (getParser().parseExpression(Imm2Exp, Ex2)) { ------------------ | Branch (4563:7): [True: 0, False: 0] ------------------ 4564| | // Error(Sx2, "malformed expression"); 4565| 0| ErrorCode = KS_ERR_ASM_ARM_INVALIDOPERAND; 4566| 0| return MatchOperand_ParseFail; 4567| 0| } 4568| | 4569| 0| CE = dyn_cast(Imm2Exp); 4570| | 4571| 0| if (CE) { ------------------ | Branch (4571:7): [True: 0, False: 0] ------------------ 4572| 0| Imm2 = CE->getValue(); 4573| 0| if (!(Imm2 & ~0x1E)) { ------------------ | Branch (4573:9): [True: 0, False: 0] ------------------ 4574| | // We have a match! 4575| 0| Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); 4576| 0| return MatchOperand_Success; 4577| 0| } 4578| | // Error(Sx2, "immediate operand must an even number in the range [0, 30]"); 4579| 0| ErrorCode = KS_ERR_ASM_ARM_INVALIDOPERAND; 4580| 0| return MatchOperand_ParseFail; 4581| 0| } else { 4582| | // Error(Sx2, "constant expression expected"); 4583| 0| ErrorCode = KS_ERR_ASM_ARM_INVALIDOPERAND; 4584| 0| return MatchOperand_ParseFail; 4585| 0| } 4586| 0|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser22parseProcIFlagsOperandERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 4002| 252|ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands, unsigned int &ErrorCode) { 4003| 252| MCAsmParser &Parser = getParser(); 4004| 252| SMLoc S = Parser.getTok().getLoc(); 4005| 252| const AsmToken &Tok = Parser.getTok(); 4006| 252| if (!Tok.is(AsmToken::Identifier)) ------------------ | Branch (4006:7): [True: 124, False: 128] ------------------ 4007| 124| return MatchOperand_NoMatch; 4008| 128| StringRef IFlagsStr = Tok.getString(); 4009| | 4010| | // An iflags string of "none" is interpreted to mean that none of the AIF 4011| | // bits are set. Not a terribly useful instruction, but a valid encoding. 4012| 128| unsigned IFlags = 0; 4013| 128| if (IFlagsStr != "none") { ------------------ | Branch (4013:7): [True: 128, False: 0] ------------------ 4014| 186| for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { ------------------ | Branch (4014:47): [True: 186, False: 0] ------------------ 4015| 186| unsigned Flag = StringSwitch(IFlagsStr.substr(i, 1)) 4016| 186| .Case("a", ARM_PROC::A) 4017| 186| .Case("i", ARM_PROC::I) 4018| 186| .Case("f", ARM_PROC::F) 4019| 186| .Default(~0U); 4020| | 4021| | // If some specific iflag is already set, it means that some letter is 4022| | // present more than once, this is not acceptable. 4023| 186| if (Flag == ~0U || (IFlags & Flag)) ------------------ | Branch (4023:11): [True: 128, False: 58] | Branch (4023:26): [True: 0, False: 58] ------------------ 4024| 128| return MatchOperand_NoMatch; 4025| | 4026| 58| IFlags |= Flag; 4027| 58| } 4028| 128| } 4029| | 4030| 0| Parser.Lex(); // Eat identifier token. 4031| 0| Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 4032| 0| return MatchOperand_Success; 4033| 128|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser11parseRotImmERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 4414| 38|ARMAsmParser::parseRotImm(OperandVector &Operands, unsigned int &ErrorCode) { 4415| 38| MCAsmParser &Parser = getParser(); 4416| 38| const AsmToken &Tok = Parser.getTok(); 4417| 38| SMLoc S = Tok.getLoc(); 4418| 38| if (Tok.isNot(AsmToken::Identifier)) ------------------ | Branch (4418:7): [True: 8, False: 30] ------------------ 4419| 8| return MatchOperand_NoMatch; 4420| 30| StringRef ShiftName = Tok.getString(); 4421| 30| if (ShiftName != "ror" && ShiftName != "ROR") ------------------ | Branch (4421:7): [True: 30, False: 0] | Branch (4421:7): [True: 30, False: 0] | Branch (4421:29): [True: 30, False: 0] ------------------ 4422| 30| return MatchOperand_NoMatch; 4423| 0| Parser.Lex(); // Eat the operator. 4424| | 4425| | // A '#' and a rotate amount. 4426| 0| if (Parser.getTok().isNot(AsmToken::Hash) && ------------------ | Branch (4426:7): [True: 0, False: 0] ------------------ 4427| 0| Parser.getTok().isNot(AsmToken::Dollar)) { ------------------ | Branch (4427:7): [True: 0, False: 0] ------------------ 4428| | //Error(Parser.getTok().getLoc(), "'#' expected"); 4429| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 4430| 0| return MatchOperand_ParseFail; 4431| 0| } 4432| 0| Parser.Lex(); // Eat hash token. 4433| | //SMLoc ExLoc = Parser.getTok().getLoc(); 4434| | 4435| 0| const MCExpr *ShiftAmount; 4436| 0| SMLoc EndLoc; 4437| 0| if (getParser().parseExpression(ShiftAmount, EndLoc)) { ------------------ | Branch (4437:7): [True: 0, False: 0] ------------------ 4438| | //Error(ExLoc, "malformed rotate expression"); 4439| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 4440| 0| return MatchOperand_ParseFail; 4441| 0| } 4442| 0| const MCConstantExpr *CE = dyn_cast(ShiftAmount); 4443| 0| if (!CE) { ------------------ | Branch (4443:7): [True: 0, False: 0] ------------------ 4444| | //Error(ExLoc, "rotate amount must be an immediate"); 4445| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 4446| 0| return MatchOperand_ParseFail; 4447| 0| } 4448| | 4449| 0| int64_t Val = CE->getValue(); 4450| | // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 4451| | // normally, zero is represented in asm by omitting the rotate operand 4452| | // entirely. 4453| 0| if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { ------------------ | Branch (4453:7): [True: 0, False: 0] | Branch (4453:19): [True: 0, False: 0] | Branch (4453:32): [True: 0, False: 0] | Branch (4453:45): [True: 0, False: 0] ------------------ 4454| | //Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 4455| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 4456| 0| return MatchOperand_ParseFail; 4457| 0| } 4458| | 4459| 0| Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 4460| | 4461| 0| return MatchOperand_Success; 4462| 0|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser15parseVectorListERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 3604| 4.69k|{ 3605| 4.69k| MCAsmParser &Parser = getParser(); 3606| 4.69k| VectorLaneTy LaneKind; 3607| 4.69k| unsigned LaneIndex; 3608| 4.69k| SMLoc S = Parser.getTok().getLoc(); 3609| | // As an extension (to match gas), support a plain D register or Q register 3610| | // (without encosing curly braces) as a single or double entry list, 3611| | // respectively. 3612| 4.69k| if (Parser.getTok().is(AsmToken::Identifier)) { ------------------ | Branch (3612:7): [True: 2.14k, False: 2.55k] ------------------ 3613| 2.14k| SMLoc E = Parser.getTok().getEndLoc(); 3614| 2.14k| int Reg = tryParseRegister(); 3615| 2.14k| if (Reg == -1) ------------------ | Branch (3615:9): [True: 2.14k, False: 0] ------------------ 3616| 2.14k| return MatchOperand_NoMatch; 3617| 0| if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { ------------------ | Branch (3617:9): [True: 0, False: 0] ------------------ 3618| 0| OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E, ErrorCode); 3619| 0| if (Res != MatchOperand_Success) ------------------ | Branch (3619:11): [True: 0, False: 0] ------------------ 3620| 0| return Res; 3621| 0| switch (LaneKind) { ------------------ | Branch (3621:15): [True: 0, False: 0] ------------------ 3622| 0| case NoLanes: ------------------ | Branch (3622:7): [True: 0, False: 0] ------------------ 3623| 0| Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3624| 0| break; 3625| 0| case AllLanes: ------------------ | Branch (3625:7): [True: 0, False: 0] ------------------ 3626| 0| Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3627| 0| S, E)); 3628| 0| break; 3629| 0| case IndexedLane: ------------------ | Branch (3629:7): [True: 0, False: 0] ------------------ 3630| 0| Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3631| 0| LaneIndex, 3632| 0| false, S, E)); 3633| 0| break; 3634| 0| } 3635| 0| return MatchOperand_Success; 3636| 0| } 3637| 0| if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { ------------------ | Branch (3637:9): [True: 0, False: 0] ------------------ 3638| 0| Reg = getDRegFromQReg(Reg); 3639| 0| OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E, ErrorCode); 3640| 0| if (Res != MatchOperand_Success) ------------------ | Branch (3640:11): [True: 0, False: 0] ------------------ 3641| 0| return Res; 3642| 0| switch (LaneKind) { ------------------ | Branch (3642:15): [True: 0, False: 0] ------------------ 3643| 0| case NoLanes: ------------------ | Branch (3643:7): [True: 0, False: 0] ------------------ 3644| 0| Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3645| 0| &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3646| 0| Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3647| 0| break; 3648| 0| case AllLanes: ------------------ | Branch (3648:7): [True: 0, False: 0] ------------------ 3649| 0| Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3650| 0| &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3651| 0| Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3652| 0| S, E)); 3653| 0| break; 3654| 0| case IndexedLane: ------------------ | Branch (3654:7): [True: 0, False: 0] ------------------ 3655| 0| Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3656| 0| LaneIndex, 3657| 0| false, S, E)); 3658| 0| break; 3659| 0| } 3660| 0| return MatchOperand_Success; 3661| 0| } 3662| | //Error(S, "vector register expected"); 3663| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3664| 0| return MatchOperand_ParseFail; 3665| 0| } 3666| | 3667| 2.55k| if (Parser.getTok().isNot(AsmToken::LCurly)) ------------------ | Branch (3667:7): [True: 2.55k, False: 0] ------------------ 3668| 2.55k| return MatchOperand_NoMatch; 3669| | 3670| 0| Parser.Lex(); // Eat '{' token. 3671| 0| SMLoc RegLoc = Parser.getTok().getLoc(); 3672| | 3673| 0| int Reg = tryParseRegister(); 3674| 0| if (Reg == -1) { ------------------ | Branch (3674:7): [True: 0, False: 0] ------------------ 3675| | //Error(RegLoc, "register expected"); 3676| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3677| 0| return MatchOperand_ParseFail; 3678| 0| } 3679| 0| unsigned Count = 1; 3680| 0| int Spacing = 0; 3681| 0| unsigned FirstReg = Reg; 3682| | // The list is of D registers, but we also allow Q regs and just interpret 3683| | // them as the two D sub-registers. 3684| 0| if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { ------------------ | Branch (3684:7): [True: 0, False: 0] ------------------ 3685| 0| FirstReg = Reg = getDRegFromQReg(Reg); 3686| 0| Spacing = 1; // double-spacing requires explicit D registers, otherwise 3687| | // it's ambiguous with four-register single spaced. 3688| 0| ++Reg; 3689| 0| ++Count; 3690| 0| } 3691| | 3692| 0| SMLoc E; 3693| 0| if (parseVectorLane(LaneKind, LaneIndex, E, ErrorCode) != MatchOperand_Success) ------------------ | Branch (3693:7): [True: 0, False: 0] ------------------ 3694| 0| return MatchOperand_ParseFail; 3695| | 3696| 0| while (Parser.getTok().is(AsmToken::Comma) || ------------------ | Branch (3696:10): [True: 0, False: 0] ------------------ 3697| 0| Parser.getTok().is(AsmToken::Minus)) { ------------------ | Branch (3697:10): [True: 0, False: 0] ------------------ 3698| 0| if (Parser.getTok().is(AsmToken::Minus)) { ------------------ | Branch (3698:9): [True: 0, False: 0] ------------------ 3699| 0| if (!Spacing) ------------------ | Branch (3699:11): [True: 0, False: 0] ------------------ 3700| 0| Spacing = 1; // Register range implies a single spaced list. 3701| 0| else if (Spacing == 2) { ------------------ | Branch (3701:16): [True: 0, False: 0] ------------------ 3702| | //Error(Parser.getTok().getLoc(), 3703| | // "sequential registers in double spaced list"); 3704| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3705| 0| return MatchOperand_ParseFail; 3706| 0| } 3707| 0| Parser.Lex(); // Eat the minus. 3708| | //SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3709| 0| int EndReg = tryParseRegister(); 3710| 0| if (EndReg == -1) { ------------------ | Branch (3710:11): [True: 0, False: 0] ------------------ 3711| | //Error(AfterMinusLoc, "register expected"); 3712| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3713| 0| return MatchOperand_ParseFail; 3714| 0| } 3715| | // Allow Q regs and just interpret them as the two D sub-registers. 3716| 0| if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) ------------------ | Branch (3716:11): [True: 0, False: 0] ------------------ 3717| 0| EndReg = getDRegFromQReg(EndReg) + 1; 3718| | // If the register is the same as the start reg, there's nothing 3719| | // more to do. 3720| 0| if (Reg == EndReg) ------------------ | Branch (3720:11): [True: 0, False: 0] ------------------ 3721| 0| continue; 3722| | // The register must be in the same register class as the first. 3723| 0| if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { ------------------ | Branch (3723:11): [True: 0, False: 0] ------------------ 3724| | //Error(AfterMinusLoc, "invalid register in register list"); 3725| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3726| 0| return MatchOperand_ParseFail; 3727| 0| } 3728| | // Ranges must go from low to high. 3729| 0| if (Reg > EndReg) { ------------------ | Branch (3729:11): [True: 0, False: 0] ------------------ 3730| | //Error(AfterMinusLoc, "bad range in register list"); 3731| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3732| 0| return MatchOperand_ParseFail; 3733| 0| } 3734| | // Parse the lane specifier if present. 3735| 0| VectorLaneTy NextLaneKind; 3736| 0| unsigned NextLaneIndex; 3737| 0| if (parseVectorLane(NextLaneKind, NextLaneIndex, E, ErrorCode) != ------------------ | Branch (3737:11): [True: 0, False: 0] ------------------ 3738| 0| MatchOperand_Success) 3739| 0| return MatchOperand_ParseFail; 3740| 0| if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { ------------------ | Branch (3740:11): [True: 0, False: 0] | Branch (3740:39): [True: 0, False: 0] ------------------ 3741| | //Error(AfterMinusLoc, "mismatched lane index in register list"); 3742| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3743| 0| return MatchOperand_ParseFail; 3744| 0| } 3745| | 3746| | // Add all the registers in the range to the register list. 3747| 0| Count += EndReg - Reg; 3748| 0| Reg = EndReg; 3749| 0| continue; 3750| 0| } 3751| 0| Parser.Lex(); // Eat the comma. 3752| 0| RegLoc = Parser.getTok().getLoc(); 3753| 0| int OldReg = Reg; 3754| 0| Reg = tryParseRegister(); 3755| 0| if (Reg == -1) { ------------------ | Branch (3755:9): [True: 0, False: 0] ------------------ 3756| | //Error(RegLoc, "register expected"); 3757| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3758| 0| return MatchOperand_ParseFail; 3759| 0| } 3760| | // vector register lists must be contiguous. 3761| | // It's OK to use the enumeration values directly here rather, as the 3762| | // VFP register classes have the enum sorted properly. 3763| | // 3764| | // The list is of D registers, but we also allow Q regs and just interpret 3765| | // them as the two D sub-registers. 3766| 0| if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { ------------------ | Branch (3766:9): [True: 0, False: 0] ------------------ 3767| 0| if (!Spacing) ------------------ | Branch (3767:11): [True: 0, False: 0] ------------------ 3768| 0| Spacing = 1; // Register range implies a single spaced list. 3769| 0| else if (Spacing == 2) { ------------------ | Branch (3769:16): [True: 0, False: 0] ------------------ 3770| | //Error(RegLoc, 3771| | // "invalid register in double-spaced list (must be 'D' register')"); 3772| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3773| 0| return MatchOperand_ParseFail; 3774| 0| } 3775| 0| Reg = getDRegFromQReg(Reg); 3776| 0| if (Reg != OldReg + 1) { ------------------ | Branch (3776:11): [True: 0, False: 0] ------------------ 3777| | //Error(RegLoc, "non-contiguous register range"); 3778| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3779| 0| return MatchOperand_ParseFail; 3780| 0| } 3781| 0| ++Reg; 3782| 0| Count += 2; 3783| | // Parse the lane specifier if present. 3784| 0| VectorLaneTy NextLaneKind; 3785| 0| unsigned NextLaneIndex; 3786| | //SMLoc LaneLoc = Parser.getTok().getLoc(); 3787| 0| if (parseVectorLane(NextLaneKind, NextLaneIndex, E, ErrorCode) != ------------------ | Branch (3787:11): [True: 0, False: 0] ------------------ 3788| 0| MatchOperand_Success) 3789| 0| return MatchOperand_ParseFail; 3790| 0| if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { ------------------ | Branch (3790:11): [True: 0, False: 0] | Branch (3790:39): [True: 0, False: 0] ------------------ 3791| | //Error(LaneLoc, "mismatched lane index in register list"); 3792| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3793| 0| return MatchOperand_ParseFail; 3794| 0| } 3795| 0| continue; 3796| 0| } 3797| | // Normal D register. 3798| | // Figure out the register spacing (single or double) of the list if 3799| | // we don't know it already. 3800| 0| if (!Spacing) ------------------ | Branch (3800:9): [True: 0, False: 0] ------------------ 3801| 0| Spacing = 1 + (Reg == OldReg + 2); 3802| | 3803| | // Just check that it's contiguous and keep going. 3804| 0| if (Reg != OldReg + Spacing) { ------------------ | Branch (3804:9): [True: 0, False: 0] ------------------ 3805| | //Error(RegLoc, "non-contiguous register range"); 3806| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3807| 0| return MatchOperand_ParseFail; 3808| 0| } 3809| 0| ++Count; 3810| | // Parse the lane specifier if present. 3811| 0| VectorLaneTy NextLaneKind; 3812| 0| unsigned NextLaneIndex; 3813| | //SMLoc EndLoc = Parser.getTok().getLoc(); 3814| 0| if (parseVectorLane(NextLaneKind, NextLaneIndex, E, ErrorCode) != MatchOperand_Success) ------------------ | Branch (3814:9): [True: 0, False: 0] ------------------ 3815| 0| return MatchOperand_ParseFail; 3816| 0| if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { ------------------ | Branch (3816:9): [True: 0, False: 0] | Branch (3816:37): [True: 0, False: 0] ------------------ 3817| | //Error(EndLoc, "mismatched lane index in register list"); 3818| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3819| 0| return MatchOperand_ParseFail; 3820| 0| } 3821| 0| } 3822| | 3823| 0| if (Parser.getTok().isNot(AsmToken::RCurly)) { ------------------ | Branch (3823:7): [True: 0, False: 0] ------------------ 3824| | //Error(Parser.getTok().getLoc(), "'}' expected"); 3825| 0| ErrorCode = KS_ERR_ASM_INVALIDOPERAND; 3826| 0| return MatchOperand_ParseFail; 3827| 0| } 3828| 0| E = Parser.getTok().getEndLoc(); 3829| 0| Parser.Lex(); // Eat '}' token. 3830| | 3831| 0| switch (LaneKind) { ------------------ | Branch (3831:11): [True: 0, False: 0] ------------------ 3832| 0| case NoLanes: ------------------ | Branch (3832:3): [True: 0, False: 0] ------------------ 3833| | // Two-register operands have been converted to the 3834| | // composite register classes. 3835| 0| if (Count == 2) { ------------------ | Branch (3835:9): [True: 0, False: 0] ------------------ 3836| 0| const MCRegisterClass *RC = (Spacing == 1) ? ------------------ | Branch (3836:35): [True: 0, False: 0] ------------------ 3837| 0| &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3838| 0| &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3839| 0| FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3840| 0| } 3841| | 3842| 0| Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3843| 0| (Spacing == 2), S, E)); 3844| 0| break; 3845| 0| case AllLanes: ------------------ | Branch (3845:3): [True: 0, False: 0] ------------------ 3846| | // Two-register operands have been converted to the 3847| | // composite register classes. 3848| 0| if (Count == 2) { ------------------ | Branch (3848:9): [True: 0, False: 0] ------------------ 3849| 0| const MCRegisterClass *RC = (Spacing == 1) ? ------------------ | Branch (3849:35): [True: 0, False: 0] ------------------ 3850| 0| &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3851| 0| &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3852| 0| FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3853| 0| } 3854| 0| Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3855| 0| (Spacing == 2), 3856| 0| S, E)); 3857| 0| break; 3858| 0| case IndexedLane: ------------------ | Branch (3858:3): [True: 0, False: 0] ------------------ 3859| 0| Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3860| 0| LaneIndex, 3861| 0| (Spacing == 2), 3862| 0| S, E)); 3863| 0| break; 3864| 0| } 3865| 0| return MatchOperand_Success; 3866| 0|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser15parseITCondCodeERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEERj: 3242| 103|ARMAsmParser::parseITCondCode(OperandVector &Operands, unsigned int &ErrorCode) { 3243| 103| MCAsmParser &Parser = getParser(); 3244| 103| SMLoc S = Parser.getTok().getLoc(); 3245| 103| const AsmToken &Tok = Parser.getTok(); 3246| 103| if (!Tok.is(AsmToken::Identifier)) ------------------ | Branch (3246:7): [True: 6, False: 97] ------------------ 3247| 6| return MatchOperand_NoMatch; 3248| 97| unsigned CC = StringSwitch(Tok.getString().lower()) 3249| 97| .Case("eq", ARMCC::EQ) 3250| 97| .Case("ne", ARMCC::NE) 3251| 97| .Case("hs", ARMCC::HS) 3252| 97| .Case("cs", ARMCC::HS) 3253| 97| .Case("lo", ARMCC::LO) 3254| 97| .Case("cc", ARMCC::LO) 3255| 97| .Case("mi", ARMCC::MI) 3256| 97| .Case("pl", ARMCC::PL) 3257| 97| .Case("vs", ARMCC::VS) 3258| 97| .Case("vc", ARMCC::VC) 3259| 97| .Case("hi", ARMCC::HI) 3260| 97| .Case("ls", ARMCC::LS) 3261| 97| .Case("ge", ARMCC::GE) 3262| 97| .Case("lt", ARMCC::LT) 3263| 97| .Case("gt", ARMCC::GT) 3264| 97| .Case("le", ARMCC::LE) 3265| 97| .Case("al", ARMCC::AL) 3266| 97| .Default(~0U); 3267| 97| if (CC == ~0U) ------------------ | Branch (3267:7): [True: 31, False: 66] ------------------ 3268| 31| return MatchOperand_NoMatch; 3269| 66| Parser.Lex(); // Eat the token. 3270| | 3271| 66| Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 3272| | 3273| 66| return MatchOperand_Success; 3274| 97|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser29tryParseRegisterWithWriteBackERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEE: 3143| 14.3k|{ 3144| 14.3k| MCAsmParser &Parser = getParser(); 3145| 14.3k| const AsmToken &RegTok = Parser.getTok(); 3146| 14.3k| int RegNo = tryParseRegister(); 3147| 14.3k| if (RegNo == -1) ------------------ | Branch (3147:7): [True: 11.4k, False: 2.92k] ------------------ 3148| 11.4k| return true; 3149| | 3150| 2.92k| Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 3151| 2.92k| RegTok.getEndLoc())); 3152| | 3153| 2.92k| const AsmToken &ExclaimTok = Parser.getTok(); 3154| 2.92k| if (ExclaimTok.is(AsmToken::Exclaim)) { ------------------ | Branch (3154:7): [True: 0, False: 2.92k] ------------------ 3155| 0| Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 3156| 0| ExclaimTok.getLoc())); 3157| 0| Parser.Lex(); // Eat exclaim token 3158| 0| return false; 3159| 0| } 3160| | 3161| | // Also check for an index operand. This is only legal for vector registers, 3162| | // but that'll get caught OK in operand matching, so we don't need to 3163| | // explicitly filter everything else out here. 3164| 2.92k| if (Parser.getTok().is(AsmToken::LBrac)) { ------------------ | Branch (3164:7): [True: 0, False: 2.92k] ------------------ 3165| 0| SMLoc SIdx = Parser.getTok().getLoc(); 3166| 0| Parser.Lex(); // Eat left bracket token. 3167| | 3168| 0| const MCExpr *ImmVal; 3169| 0| if (getParser().parseExpression(ImmVal)) ------------------ | Branch (3169:9): [True: 0, False: 0] ------------------ 3170| 0| return true; 3171| 0| const MCConstantExpr *MCE = dyn_cast(ImmVal); 3172| 0| if (!MCE) ------------------ | Branch (3172:9): [True: 0, False: 0] ------------------ 3173| | //return TokError("immediate value expected for vector index"); 3174| 0| return true; 3175| | 3176| 0| if (Parser.getTok().isNot(AsmToken::RBrac)) ------------------ | Branch (3176:9): [True: 0, False: 0] ------------------ 3177| | //return Error(Parser.getTok().getLoc(), "']' expected"); 3178| 0| return true; 3179| | 3180| 0| SMLoc E = Parser.getTok().getEndLoc(); 3181| 0| Parser.Lex(); // Eat right bracket token. 3182| | 3183| 0| Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 3184| 0| SIdx, E, 3185| 0| getContext())); 3186| 0| } 3187| | 3188| 2.92k| return false; 3189| 2.92k|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser21tryParseShiftRegisterERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEE: 3038| 11.4k|{ 3039| 11.4k| MCAsmParser &Parser = getParser(); 3040| 11.4k| SMLoc S = Parser.getTok().getLoc(); 3041| 11.4k| const AsmToken &Tok = Parser.getTok(); 3042| 11.4k| if (Tok.isNot(AsmToken::Identifier)) ------------------ | Branch (3042:7): [True: 0, False: 11.4k] ------------------ 3043| 0| return -1; 3044| | 3045| 11.4k| std::string lowerCase = Tok.getString().lower(); 3046| 11.4k| ARM_AM::ShiftOpc ShiftTy = StringSwitch(lowerCase) 3047| 11.4k| .Case("asl", ARM_AM::lsl) 3048| 11.4k| .Case("lsl", ARM_AM::lsl) 3049| 11.4k| .Case("lsr", ARM_AM::lsr) 3050| 11.4k| .Case("asr", ARM_AM::asr) 3051| 11.4k| .Case("ror", ARM_AM::ror) 3052| 11.4k| .Case("rrx", ARM_AM::rrx) 3053| 11.4k| .Default(ARM_AM::no_shift); 3054| | 3055| 11.4k| if (ShiftTy == ARM_AM::no_shift) ------------------ | Branch (3055:7): [True: 11.4k, False: 0] ------------------ 3056| 11.4k| return 1; 3057| | 3058| 0| Parser.Lex(); // Eat the operator. 3059| | 3060| | // The source register for the shift has already been added to the 3061| | // operand list, so we need to pop it off and combine it into the shifted 3062| | // register operand instead. 3063| 0| std::unique_ptr PrevOp( 3064| 0| (ARMOperand *)Operands.pop_back_val().release()); 3065| 0| if (!PrevOp->isReg()) ------------------ | Branch (3065:7): [True: 0, False: 0] ------------------ 3066| | //return Error(PrevOp->getStartLoc(), "shift must be of a register"); 3067| 0| return -1; 3068| 0| int SrcReg = PrevOp->getReg(); 3069| | 3070| 0| SMLoc EndLoc; 3071| 0| int64_t Imm = 0; 3072| 0| int ShiftReg = 0; 3073| 0| if (ShiftTy == ARM_AM::rrx) { ------------------ | Branch (3073:7): [True: 0, False: 0] ------------------ 3074| | // RRX Doesn't have an explicit shift amount. The encoder expects 3075| | // the shift register to be the same as the source register. Seems odd, 3076| | // but OK. 3077| 0| ShiftReg = SrcReg; 3078| 0| } else { 3079| | // Figure out if this is shifted by a constant or a register (for non-RRX). 3080| 0| if (Parser.getTok().is(AsmToken::Hash) || ------------------ | Branch (3080:9): [True: 0, False: 0] ------------------ 3081| 0| Parser.getTok().is(AsmToken::Dollar)) { ------------------ | Branch (3081:9): [True: 0, False: 0] ------------------ 3082| 0| Parser.Lex(); // Eat hash. 3083| | //SMLoc ImmLoc = Parser.getTok().getLoc(); 3084| 0| const MCExpr *ShiftExpr = nullptr; 3085| 0| if (getParser().parseExpression(ShiftExpr, EndLoc)) { ------------------ | Branch (3085:11): [True: 0, False: 0] ------------------ 3086| | //Error(ImmLoc, "invalid immediate shift value"); 3087| 0| return -1; 3088| 0| } 3089| | // The expression must be evaluatable as an immediate. 3090| 0| const MCConstantExpr *CE = dyn_cast(ShiftExpr); 3091| 0| if (!CE) { ------------------ | Branch (3091:11): [True: 0, False: 0] ------------------ 3092| | //Error(ImmLoc, "invalid immediate shift value"); 3093| 0| return -1; 3094| 0| } 3095| | // Range check the immediate. 3096| | // lsl, ror: 0 <= imm <= 31 3097| | // lsr, asr: 0 <= imm <= 32 3098| 0| Imm = CE->getValue(); 3099| 0| if (Imm < 0 || ------------------ | Branch (3099:11): [True: 0, False: 0] ------------------ 3100| 0| ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || ------------------ | Branch (3100:13): [True: 0, False: 0] | Branch (3100:39): [True: 0, False: 0] | Branch (3100:66): [True: 0, False: 0] ------------------ 3101| 0| ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { ------------------ | Branch (3101:13): [True: 0, False: 0] | Branch (3101:39): [True: 0, False: 0] | Branch (3101:66): [True: 0, False: 0] ------------------ 3102| | //Error(ImmLoc, "immediate shift value out of range"); 3103| 0| return -1; 3104| 0| } 3105| | // shift by zero is a nop. Always send it through as lsl. 3106| | // ('as' compatibility) 3107| 0| if (Imm == 0) ------------------ | Branch (3107:11): [True: 0, False: 0] ------------------ 3108| 0| ShiftTy = ARM_AM::lsl; 3109| 0| } else if (Parser.getTok().is(AsmToken::Identifier)) { ------------------ | Branch (3109:16): [True: 0, False: 0] ------------------ 3110| | //SMLoc L = Parser.getTok().getLoc(); 3111| 0| EndLoc = Parser.getTok().getEndLoc(); 3112| 0| ShiftReg = tryParseRegister(); 3113| 0| if (ShiftReg == -1) { ------------------ | Branch (3113:11): [True: 0, False: 0] ------------------ 3114| | //Error(L, "expected immediate or register in shift operand"); 3115| 0| return -1; 3116| 0| } 3117| 0| } else { 3118| | //Error(Parser.getTok().getLoc(), 3119| | // "expected immediate or register in shift operand"); 3120| 0| return -1; 3121| 0| } 3122| 0| } 3123| | 3124| 0| if (ShiftReg && ShiftTy != ARM_AM::rrx) ------------------ | Branch (3124:7): [True: 0, False: 0] | Branch (3124:19): [True: 0, False: 0] ------------------ 3125| 0| Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 3126| 0| ShiftReg, Imm, 3127| 0| S, EndLoc)); 3128| 0| else 3129| 0| Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 3130| 0| S, EndLoc)); 3131| | 3132| 0| return 0; 3133| 0|} ARMAsmParser.cpp:_ZN12_GLOBAL__N_112ARMAsmParser11parseMemoryERN7llvm_ks15SmallVectorImplINSt3__110unique_ptrINS1_18MCParsedAsmOperandENS3_14default_deleteIS5_EEEEEE: 4868| 35|{ 4869| 35| MCAsmParser &Parser = getParser(); 4870| 35| SMLoc S, E; 4871| 35| assert(Parser.getTok().is(AsmToken::LBrac) && ------------------ | Branch (4871:3): [True: 35, False: 0] | Branch (4871:3): [True: 35, Folded] | Branch (4871:3): [True: 35, False: 0] ------------------ 4872| 35| "Token is not a Left Bracket"); 4873| 35| S = Parser.getTok().getLoc(); 4874| 35| Parser.Lex(); // Eat left bracket token. 4875| | 4876| | //const AsmToken &BaseRegTok = Parser.getTok(); 4877| 35| int BaseRegNum = tryParseRegister(); 4878| 35| if (BaseRegNum == -1) ------------------ | Branch (4878:7): [True: 0, False: 35] ------------------ 4879| | //return Error(BaseRegTok.getLoc(), "register expected"); 4880| 0| return true; 4881| | 4882| | // The next token must either be a comma, a colon or a closing bracket. 4883| 35| const AsmToken &Tok = Parser.getTok(); 4884| 35| if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && ------------------ | Branch (4884:7): [True: 35, False: 0] | Branch (4884:35): [True: 0, False: 35] ------------------ 4885| 0| !Tok.is(AsmToken::RBrac)) ------------------ | Branch (4885:7): [True: 0, False: 0] ------------------ 4886| | //return Error(Tok.getLoc(), "malformed memory operand"); 4887| 0| return true; 4888| | 4889| 35| if (Tok.is(AsmToken::RBrac)) { ------------------ | Branch (4889:7): [True: 0, False: 35] ------------------ 4890| 0| E = Tok.getEndLoc(); 4891| 0| Parser.Lex(); // Eat right bracket token. 4892| | 4893| 0| Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 4894| 0| ARM_AM::no_shift, 0, 0, false, 4895| 0| S, E)); 4896| | 4897| | // If there's a pre-indexing writeback marker, '!', just add it as a token 4898| | // operand. It's rather odd, but syntactically valid. 4899| 0| if (Parser.getTok().is(AsmToken::Exclaim)) { ------------------ | Branch (4899:9): [True: 0, False: 0] ------------------ 4900| 0| Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4901| 0| Parser.Lex(); // Eat the '!'. 4902| 0| } 4903| | 4904| 0| return false; 4905| 0| } 4906| | 4907| 35| assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && ------------------ | Branch (4907:3): [True: 0, False: 35] | Branch (4907:3): [True: 35, False: 0] | Branch (4907:3): [True: 35, Folded] | Branch (4907:3): [True: 35, False: 0] ------------------ 4908| 35| "Lost colon or comma in memory operand?!"); 4909| 35| if (Tok.is(AsmToken::Comma)) { ------------------ | Branch (4909:7): [True: 35, False: 0] ------------------ 4910| 35| Parser.Lex(); // Eat the comma. 4911| 35| } 4912| | 4913| | // If we have a ':', it's an alignment specifier. 4914| 35| if (Parser.getTok().is(AsmToken::Colon)) { ------------------ | Branch (4914:7): [True: 0, False: 35] ------------------ 4915| 0| Parser.Lex(); // Eat the ':'. 4916| 0| E = Parser.getTok().getLoc(); 4917| 0| SMLoc AlignmentLoc = Tok.getLoc(); 4918| | 4919| 0| const MCExpr *Expr; 4920| 0| if (getParser().parseExpression(Expr)) ------------------ | Branch (4920:9): [True: 0, False: 0] ------------------ 4921| 0| return true; 4922| | 4923| | // The expression has to be a constant. Memory references with relocations 4924| | // don't come through here, as they use the