(kicad_pcb (version 20211014) (generator pcbnew)
  (general
    (thickness 0.57)
  )
  (paper "A4")
  (layers
    (0 "F.Cu" signal)
    (31 "B.Cu" signal)
    (32 "B.Adhes" user "B.Adhesive")
    (33 "F.Adhes" user "F.Adhesive")
    (34 "B.Paste" user)
    (35 "F.Paste" user)
    (36 "B.SilkS" user "B.Silkscreen")
    (37 "F.SilkS" user "F.Silkscreen")
    (38 "B.Mask" user)
    (39 "F.Mask" user)
    (40 "Dwgs.User" user "User.Drawings")
    (41 "Cmts.User" user "User.Comments")
    (42 "Eco1.User" user "User.Eco1")
    (43 "Eco2.User" user "User.Eco2")
    (44 "Edge.Cuts" user)
    (45 "Margin" user)
    (46 "B.CrtYd" user "B.Courtyard")
    (47 "F.CrtYd" user "F.Courtyard")
    (48 "B.Fab" user)
    (49 "F.Fab" user)
    (50 "User.1" user)
    (51 "User.2" user)
    (52 "User.3" user)
    (53 "User.4" user)
    (54 "User.5" user)
    (55 "User.6" user)
    (56 "User.7" user)
    (57 "User.8" user)
    (58 "User.9" user)
  )
  (setup
    (stackup
      (layer "F.SilkS" (type "Top Silk Screen"))
      (layer "F.Paste" (type "Top Solder Paste"))
      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
      (layer "F.Cu" (type "copper") (thickness 0.035))
      (layer "dielectric 1" (type "core") (thickness 0.48) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
      (layer "B.Cu" (type "copper") (thickness 0.035))
      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
      (layer "B.Paste" (type "Bottom Solder Paste"))
      (layer "B.SilkS" (type "Bottom Silk Screen"))
      (copper_finish "None")
      (dielectric_constraints no)
    )
    (pad_to_mask_clearance 0)
    (pcbplotparams
      (layerselection 0x00010fc_ffffffff)
      (disableapertmacros false)
      (usegerberextensions false)
      (usegerberattributes true)
      (usegerberadvancedattributes true)
      (creategerberjobfile true)
      (svguseinch false)
      (svgprecision 6)
      (excludeedgelayer true)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (dxfpolygonmode true)
      (dxfimperialunits true)
      (dxfusepcbnewfont true)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (sketchpadsonfab false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory "")
    )
  )
  (net 0 "")
  (net 1 "GND")
  (net 2 "NRST")
  (net 3 "SWDIO")
  (net 4 "SWCLK")
  (net 5 "BOOT0")
  (net 6 "VBUS")
  (net 7 "VCC")
  (net 8 "N$2")
  (net 9 "N$4")
  (net 10 "DCMI_D0")
  (net 11 "DCMI_D1")
  (net 12 "DCMI_PCLK")
  (net 13 "DCMI_HSYNC")
  (net 14 "DCMI_VSYNC")
  (net 15 "DCMI_CLK")
  (net 16 "DCMI_RST")
  (net 17 "DCMI_PWDN")
  (net 18 "DCMI_D2")
  (net 19 "DCMI_D3")
  (net 20 "DCMI_D4")
  (net 21 "DCMI_D5")
  (net 22 "DCMI_D6")
  (net 23 "DCMI_D7")
  (net 24 "SD_CD")
  (net 25 "SDIO_D0")
  (net 26 "SDIO_D1")
  (net 27 "SDIO_D2")
  (net 28 "SDIO_CLK")
  (net 29 "SDIO_CMD")
  (net 30 "LED_G")
  (net 31 "LED_B")
  (net 32 "LED_R")
  (net 33 "TIM4_CH1")
  (net 34 "TIM4_CH2")
  (net 35 "SDIO_D3")
  (net 36 "N$5")
  (net 37 "FS_DP")
  (net 38 "N$8")
  (net 39 "LED_IR")
  (net 40 "N$14")
  (net 41 "N$10")
  (net 42 "FS_DM")
  (net 43 "VCAP2")
  (net 44 "VCAP1")
  (net 45 "I2C1_SCL")
  (net 46 "I2C1_SDA")
  (net 47 "SPI2_SCLK")
  (net 48 "I2C2_SCL")
  (net 49 "I2C2_SDA")
  (net 50 "N$12")
  (net 51 "RAW")
  (net 52 "DAC")
  (net 53 "SPI2_NSS")
  (net 54 "SPI2_MISO")
  (net 55 "SPI2_MOSI")
  (net 56 "FREX")
  (net 57 "EXPST")
  (net 58 "TIM4_CH3")
  (net 59 "N$17")
  (net 60 "N$6")
  (net 61 "N$9")
  (net 62 "VIN")
  (net 63 "N$7")
  (net 64 "SW")
  (net 65 "DCMI_FSIN")
  (net 66 "UART2_TX")
  (net 67 "UART2_RX")
  (net 68 "SPI3_SCLK/TRACESWO")
  (net 69 "SPI3_MISO")
  (net 70 "SPI3_MOSI")
  (net 71 "GPIO1")
  (net 72 "GPIO2")
  (net 73 "SPI3_SSEL")
  (net 74 "GPIO3")
  (net 75 "N$11")
  (net 76 "VDDA")
  (net 77 "RSVD1")
  (net 78 "RSVD2")
  (net 79 "RSVD3")
  (net 80 "RSVD5")
  (net 81 "RSVD6")
  (net 82 "RSVD4")
  (net 83 "N$13")
  (net 84 "N$30")
  (net 85 "N$31")
  (net 86 "N$32")
  (net 87 "N$33")
  (net 88 "N$34")
  (footprint "qstache 2 layer rev7:0603-RES" placed (layer "F.Cu")
    (tedit 0)
    (at 237.68 112.566 -90)
    (fp_text reference "R5" (at -1.524 -0.127) (layer "F.SilkS"))
    (fp_text value "100K" (at -1.016 1.143 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.85 0 270) (size 1.1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.85 0 270) (size 1.1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 83 "N$13") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-CAP" placed (layer "F.Cu")
    (tedit 0)
    (at 231.127 132.127 -90)
    (fp_text reference "C5" (at -1.651 0.635) (layer "F.SilkS"))
    (fp_text value "0.1uF" (at -1.0795 1.143 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0 270) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 50 "N$12") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0 270) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-RES" placed (layer "F.Cu")
    (tedit 0)
    (at 219.127 120.127 90)
    (fp_text reference "R4" (at 1.651 -0.889) (layer "F.SilkS"))
    (fp_text value "4.7K" (at -1.016 1.143 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.85 0 90) (size 1.1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.85 0 90) (size 1.1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 46 "I2C1_SDA") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-CAP" placed (layer "F.Cu")
    (tedit 0)
    (at 216.127 132.127)
    (fp_text reference "C48" (at 0.486206 -0.896153) (layer "F.SilkS"))
    (fp_text value "2.2uF" (at -1.079504 1.143004) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 43 "VCAP2") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:SOT23-5" placed (layer "F.Cu")
    (tedit 0)
    (at 249.127 115.127 -90)
    (descr "<b>Small Outline Transistor</b>")
    (fp_text reference "U5" (at -1.397 1.905) (layer "F.SilkS"))
    (fp_text value "TPS731XX" (at -0.9525 0.1905 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.95 1.3001 270) (size 0.55 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0 1.3001 270) (size 0.55 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "3" smd rect (at 0.95 1.3001 270) (size 0.55 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "4" smd rect (at 0.95 -1.3001 270) (size 0.55 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 75 "N$11") (solder_mask_margin 0.0762))
    (pad "5" smd rect (at -0.95 -1.3001 270) (size 0.55 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 76 "VDDA") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-CAP" placed (layer "F.Cu")
    (tedit 0)
    (at 226.127 125.127 90)
    (fp_text reference "C10" (at 1.651 -0.635) (layer "F.SilkS"))
    (fp_text value "0.1uF" (at -1.0795 1.143 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0 90) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0 90) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:SOD-323" placed (layer "F.Cu")
    (tedit 0)
    (at 220.127 134.127 180)
    (fp_text reference "D3" (at -0.862 0.97) (layer "F.SilkS"))
    (fp_text value "SDM2U20SD3-7" (at -1.016 1.397) (layer "F.Fab"))
    (pad "1" smd rect (at -1.15 0 180) (size 0.63 0.83) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 51 "RAW") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 1.15 0 180) (size 0.63 0.83) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 62 "VIN") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:CRYSTAL-2.5X2.0" placed (layer "F.Cu")
    (tedit 0)
    (at 243.127 132.127 -90)
    (fp_text reference "Y1" (at -0.863387 -1.879918 90) (layer "F.SilkS"))
    (fp_text value "7S-12.000MAHE-T" (at 3.534007 -1.895 90) (layer "F.SilkS"))
    (pad "1" smd rect (at -0.95 0.8 270) (size 1 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 9 "N$4") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.9 0.8 270) (size 1 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "3" smd rect (at 0.9 -0.75 270) (size 1 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 8 "N$2") (solder_mask_margin 0.0762))
    (pad "4" smd rect (at -0.95 -0.75 270) (size 1 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-CAP" placed (layer "F.Cu")
    (tedit 0)
    (at 216.127 129.127)
    (fp_text reference "C1" (at -1.524 -0.889) (layer "F.SilkS"))
    (fp_text value "1uF" (at -1.016 1.143) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 2 "NRST") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-CAP" placed (layer "F.Cu")
    (tedit 0)
    (at 215.127 106.127)
    (fp_text reference "C7" (at -1.524 0.762 90) (layer "F.SilkS"))
    (fp_text value "0.1uF" (at -1.016 1.143) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 75 "N$11") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-CAP" placed (layer "F.Cu")
    (tedit 0)
    (at 234.127 132.127 -90)
    (fp_text reference "C4" (at -1.651 0.635) (layer "F.SilkS"))
    (fp_text value "1uF" (at -1.0795 1.143 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0 270) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 50 "N$12") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0 270) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603" placed (layer "F.Cu")
    (tedit 0)
    (at 233.908 114.852 180)
    (fp_text reference "L2" (at -0.889 0.889) (layer "F.SilkS"))
    (fp_text value "MPZ1608S181ATAH0" (at -1.0795 1.143) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0 180) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 63 "N$7") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0 180) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 6 "VBUS") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0805" placed (layer "F.Cu")
    (tedit 0)
    (at 244.127 120.127 90)
    (fp_text reference "C3" (at 0.762 -0.889 90) (layer "F.SilkS"))
    (fp_text value "10uF" (at -1.016 1.397 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.9 0 90) (size 0.8 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.9 0 90) (size 0.8 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603" placed (layer "F.Cu")
    (tedit 0)
    (at 223.127 130.127 -90)
    (fp_text reference "L1" (at -1.651 0.635) (layer "F.SilkS"))
    (fp_text value "MPZ1608S181ATAH0" (at -1.0795 1.143 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0 270) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 50 "N$12") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0 270) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-CAP" placed (layer "F.Cu")
    (tedit 0)
    (at 236.68 108.566 180)
    (fp_text reference "C41" (at -4.640203 -19.606366) (layer "F.SilkS"))
    (fp_text value "12pF" (at -7.138503 -19.366997) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0 180) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0 180) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 9 "N$4") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-RES" placed (layer "F.Cu")
    (tedit 0)
    (at 222.186 114.637 -90)
    (fp_text reference "R9" (at -1.454 0.6) (layer "F.SilkS"))
    (fp_text value "10K" (at -1.0795 1.143 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.85 0 270) (size 1.1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.85 0 270) (size 1.1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 62 "VIN") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0805" placed (layer "F.Cu")
    (tedit 0)
    (at 216.127 110.127 90)
    (fp_text reference "C12" (at 1.524 -1.143) (layer "F.SilkS"))
    (fp_text value "10uF" (at -1.016 1.397 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.9 0 90) (size 0.8 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.9 0 90) (size 0.8 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 76 "VDDA") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:SOT23-3" placed (layer "F.Cu")
    (tedit 0)
    (at 226.127 120.127)
    (fp_text reference "Q1" (at -1.397 -1.143) (layer "F.SilkS"))
    (fp_text value "BSS138" (at -1.016 0.1905) (layer "F.Fab"))
    (pad "1" smd rect (at -0.95 1) (size 0.8 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 36 "N$5") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.95 1) (size 0.8 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "3" smd rect (at 0 -1.1) (size 0.8 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 40 "N$14") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:MICROUSB-RIGHT" (layer "F.Cu")
    (tedit 0)
    (at 179.4891 105.7021 90)
    (descr "<b>Description:</b> Package for Micro USB Type B connector. Based on FCI 10118193-0001LF.<br>")
    (fp_text reference "X1" (at -4.572 -2.446 90) (layer "F.SilkS"))
    (fp_text value "MF-CON-MICROUSB-RIGHT" (at 0 0 90) (layer "F.Fab") hide)
    (pad "1" smd rect (at -1.3 -1.27 270) (size 0.4 1.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 63 "N$7") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at -0.65 -1.27 270) (size 0.4 1.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 42 "FS_DM") (solder_mask_margin 0.0762))
    (pad "3" smd rect (at 0 -1.27 270) (size 0.4 1.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 37 "FS_DP") (solder_mask_margin 0.0762))
    (pad "4" smd rect (at 0.65 -1.27 270) (size 0.4 1.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "5" smd rect (at 1.3 -1.27 270) (size 0.4 1.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "S1" thru_hole circle (at -3.3 1.405 270) (size 1.87 1.87) (drill 1.1) (layers *.Cu *.Mask)
      (solder_mask_margin 0.0762))
    (pad "S2" thru_hole circle (at 3.3 1.405 270) (size 1.87 1.87) (drill 1.1) (layers *.Cu *.Mask)
      (solder_mask_margin 0.0762))
    (pad "S3" smd rect (at -3.2 -1.27 180) (size 1.4 1.6) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "S4" smd rect (at 3.2 -1.27 180) (size 1.4 1.6) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "S5" smd rect (at -1.2 1.405 90) (size 1.9 1.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "S6" smd rect (at 1.2 1.405 90) (size 1.9 1.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:9774030151R" (layer "F.Cu")
    (tedit 0)
    (at 163.6141 61.0616)
    (fp_text reference "M2" (at 0 0) (layer "F.SilkS") hide)
    (fp_text value "9774030243R" (at 0 0) (layer "F.Fab") hide)
    (pad "P$1" thru_hole circle (at 0 0) (size 4.5 4.5) (drill 3) (layers *.Cu *.Mask)
      (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:0603-CAP" placed (layer "F.Cu")
    (tedit 0)
    (at 219.127 125.127 90)
    (fp_text reference "C6" (at 1.778 -0.635) (layer "F.SilkS"))
    (fp_text value "0.1uF" (at -1.0795 1.143 90) (layer "F.Fab"))
    (pad "1" smd rect (at -0.8 0 90) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at 0.8 0 90) (size 1 1) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:1X06" (layer "F.Cu")
    (tedit 0)
    (at 154.7241 120.2436 -90)
    (descr "<b>PIN HEADER</b>")
    (fp_text reference "JP3" (at -7.6962 -1.8288 -90) (layer "F.SilkS") hide)
    (fp_text value "" (at -7.62 3.175 90) (layer "F.Fab"))
    (pad "1" thru_hole roundrect (at -6.35 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
      (chamfer_ratio 0.25) (chamfer top_left top_right bottom_left bottom_right)
      (net 68 "SPI3_SCLK/TRACESWO") (solder_mask_margin 0.0762))
    (pad "2" thru_hole roundrect (at -3.81 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
      (chamfer_ratio 0.25) (chamfer top_left top_right bottom_left bottom_right)
      (net 4 "SWCLK") (solder_mask_margin 0.0762))
    (pad "3" thru_hole roundrect (at -1.27 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
      (chamfer_ratio 0.25) (chamfer top_left top_right bottom_left bottom_right)
      (net 3 "SWDIO") (solder_mask_margin 0.0762))
    (pad "4" thru_hole roundrect (at 1.27 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
      (chamfer_ratio 0.25) (chamfer top_left top_right bottom_left bottom_right)
      (net 2 "NRST") (solder_mask_margin 0.0762))
    (pad "5" thru_hole roundrect (at 3.81 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
      (chamfer_ratio 0.25) (chamfer top_left top_right bottom_left bottom_right)
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "6" thru_hole roundrect (at 6.35 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
      (chamfer_ratio 0.25) (chamfer top_left top_right bottom_left bottom_right)
      (net 1 "GND") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:LQFP100" placed (layer "F.Cu")
    (tedit 0)
    (at 254.127 127.127)
    (descr "<b>Low Profile Quad Flat Pack</b>")
    (fp_text reference "U1" (at -6.175 -8.62) (layer "F.SilkS"))
    (fp_text value "STM32H743VIT6" (at -5.135 1.095) (layer "F.Fab"))
    (pad "1" smd rect (at -7.72 -6) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 39 "LED_IR") (solder_mask_margin 0.0762))
    (pad "2" smd rect (at -7.72 -5.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "3" smd rect (at -7.72 -5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 20 "DCMI_D4") (solder_mask_margin 0.0762))
    (pad "4" smd rect (at -7.72 -4.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 22 "DCMI_D6") (solder_mask_margin 0.0762))
    (pad "5" smd rect (at -7.72 -4) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 23 "DCMI_D7") (solder_mask_margin 0.0762))
    (pad "6" smd rect (at -7.72 -3.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "7" smd rect (at -7.72 -3) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "8" smd rect (at -7.72 -2.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "9" smd rect (at -7.72 -2) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "10" smd rect (at -7.72 -1.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "11" smd rect (at -7.72 -1) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "12" smd rect (at -7.72 -0.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 9 "N$4") (solder_mask_margin 0.0762))
    (pad "13" smd rect (at -7.72 0) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 8 "N$2") (solder_mask_margin 0.0762))
    (pad "14" smd rect (at -7.72 0.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 2 "NRST") (solder_mask_margin 0.0762))
    (pad "15" smd rect (at -7.72 1) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 32 "LED_R") (solder_mask_margin 0.0762))
    (pad "16" smd rect (at -7.72 1.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 30 "LED_G") (solder_mask_margin 0.0762))
    (pad "17" smd rect (at -7.72 2) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 31 "LED_B") (solder_mask_margin 0.0762))
    (pad "18" smd rect (at -7.72 2.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "19" smd rect (at -7.72 3) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "20" smd rect (at -7.72 3.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 50 "N$12") (solder_mask_margin 0.0762))
    (pad "21" smd rect (at -7.72 4) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 50 "N$12") (solder_mask_margin 0.0762))
    (pad "22" smd rect (at -7.72 4.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 85 "N$31") (solder_mask_margin 0.0762))
    (pad "23" smd rect (at -7.72 5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 86 "N$32") (solder_mask_margin 0.0762))
    (pad "24" smd rect (at -7.72 5.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 87 "N$33") (solder_mask_margin 0.0762))
    (pad "25" smd rect (at -7.72 6) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 88 "N$34") (solder_mask_margin 0.0762))
    (pad "26" smd rect (at -6 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "27" smd rect (at -5.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "28" smd rect (at -5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 13 "DCMI_HSYNC") (solder_mask_margin 0.0762))
    (pad "29" smd rect (at -4.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 52 "DAC") (solder_mask_margin 0.0762))
    (pad "30" smd rect (at -4 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 12 "DCMI_PCLK") (solder_mask_margin 0.0762))
    (pad "31" smd rect (at -3.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "32" smd rect (at -3 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "33" smd rect (at -2.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "34" smd rect (at -2 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "35" smd rect (at -1.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "36" smd rect (at -1 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "37" smd rect (at -0.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "38" smd rect (at 0 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "39" smd rect (at 0.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "40" smd rect (at 1 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "41" smd rect (at 1.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "42" smd rect (at 2 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "43" smd rect (at 2.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "44" smd rect (at 3 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "45" smd rect (at 3.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "46" smd rect (at 4 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 48 "I2C2_SCL") (solder_mask_margin 0.0762))
    (pad "47" smd rect (at 4.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 49 "I2C2_SDA") (solder_mask_margin 0.0762))
    (pad "48" smd rect (at 5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 44 "VCAP1") (solder_mask_margin 0.0762))
    (pad "49" smd rect (at 5.5 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "50" smd rect (at 6 7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "51" smd rect (at 7.72 6) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 53 "SPI2_NSS") (solder_mask_margin 0.0762))
    (pad "52" smd rect (at 7.72 5.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 47 "SPI2_SCLK") (solder_mask_margin 0.0762))
    (pad "53" smd rect (at 7.72 5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 54 "SPI2_MISO") (solder_mask_margin 0.0762))
    (pad "54" smd rect (at 7.72 4.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 55 "SPI2_MOSI") (solder_mask_margin 0.0762))
    (pad "55" smd rect (at 7.72 4) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 57 "EXPST") (solder_mask_margin 0.0762))
    (pad "56" smd rect (at 7.72 3.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 56 "FREX") (solder_mask_margin 0.0762))
    (pad "57" smd rect (at 7.72 3) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "58" smd rect (at 7.72 2.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (solder_mask_margin 0.0762))
    (pad "59" smd rect (at 7.72 2) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 33 "TIM4_CH1") (solder_mask_margin 0.0762))
    (pad "60" smd rect (at 7.72 1.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 34 "TIM4_CH2") (solder_mask_margin 0.0762))
    (pad "61" smd rect (at 7.72 1) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 58 "TIM4_CH3") (solder_mask_margin 0.0762))
    (pad "62" smd rect (at 7.72 0.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 84 "N$30") (solder_mask_margin 0.0762))
    (pad "63" smd rect (at 7.72 0) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 10 "DCMI_D0") (solder_mask_margin 0.0762))
    (pad "64" smd rect (at 7.72 -0.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 11 "DCMI_D1") (solder_mask_margin 0.0762))
    (pad "65" smd rect (at 7.72 -1) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 25 "SDIO_D0") (solder_mask_margin 0.0762))
    (pad "66" smd rect (at 7.72 -1.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 26 "SDIO_D1") (solder_mask_margin 0.0762))
    (pad "67" smd rect (at 7.72 -2) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 15 "DCMI_CLK") (solder_mask_margin 0.0762))
    (pad "68" smd rect (at 7.72 -2.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 6 "VBUS") (solder_mask_margin 0.0762))
    (pad "69" smd rect (at 7.72 -3) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 16 "DCMI_RST") (solder_mask_margin 0.0762))
    (pad "70" smd rect (at 7.72 -3.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 42 "FS_DM") (solder_mask_margin 0.0762))
    (pad "71" smd rect (at 7.72 -4) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 37 "FS_DP") (solder_mask_margin 0.0762))
    (pad "72" smd rect (at 7.72 -4.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 3 "SWDIO") (solder_mask_margin 0.0762))
    (pad "73" smd rect (at 7.72 -5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 43 "VCAP2") (solder_mask_margin 0.0762))
    (pad "74" smd rect (at 7.72 -5.5) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "75" smd rect (at 7.72 -6) (size 0.9 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "76" smd rect (at 6 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 4 "SWCLK") (solder_mask_margin 0.0762))
    (pad "77" smd rect (at 5.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 73 "SPI3_SSEL") (solder_mask_margin 0.0762))
    (pad "78" smd rect (at 5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 27 "SDIO_D2") (solder_mask_margin 0.0762))
    (pad "79" smd rect (at 4.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 35 "SDIO_D3") (solder_mask_margin 0.0762))
    (pad "80" smd rect (at 4 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 28 "SDIO_CLK") (solder_mask_margin 0.0762))
    (pad "81" smd rect (at 3.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 24 "SD_CD") (solder_mask_margin 0.0762))
    (pad "82" smd rect (at 3 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 74 "GPIO3") (solder_mask_margin 0.0762))
    (pad "83" smd rect (at 2.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 29 "SDIO_CMD") (solder_mask_margin 0.0762))
    (pad "84" smd rect (at 2 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 71 "GPIO1") (solder_mask_margin 0.0762))
    (pad "85" smd rect (at 1.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 72 "GPIO2") (solder_mask_margin 0.0762))
    (pad "86" smd rect (at 1 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 66 "UART2_TX") (solder_mask_margin 0.0762))
    (pad "87" smd rect (at 0.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 67 "UART2_RX") (solder_mask_margin 0.0762))
    (pad "88" smd rect (at 0 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 17 "DCMI_PWDN") (solder_mask_margin 0.0762))
    (pad "89" smd rect (at -0.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 68 "SPI3_SCLK/TRACESWO") (solder_mask_margin 0.0762))
    (pad "90" smd rect (at -1 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 69 "SPI3_MISO") (solder_mask_margin 0.0762))
    (pad "91" smd rect (at -1.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 70 "SPI3_MOSI") (solder_mask_margin 0.0762))
    (pad "92" smd rect (at -2 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 21 "DCMI_D5") (solder_mask_margin 0.0762))
    (pad "93" smd rect (at -2.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 14 "DCMI_VSYNC") (solder_mask_margin 0.0762))
    (pad "94" smd rect (at -3 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "BOOT0") (solder_mask_margin 0.0762))
    (pad "95" smd rect (at -3.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 45 "I2C1_SCL") (solder_mask_margin 0.0762))
    (pad "96" smd rect (at -4 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 46 "I2C1_SDA") (solder_mask_margin 0.0762))
    (pad "97" smd rect (at -4.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 18 "DCMI_D2") (solder_mask_margin 0.0762))
    (pad "98" smd rect (at -5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 19 "DCMI_D3") (solder_mask_margin 0.0762))
    (pad "99" smd rect (at -5.5 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "100" smd rect (at -6 -7.72) (size 0.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:EIA3216" placed (layer "F.Cu")
    (tedit 0)
    (at 237.127 124.127 -90)
    (fp_text reference "C15" (at -2.778 1.27) (layer "F.SilkS"))
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    (pad "G$3" smd rect (at 2.27 11.075 90) (size 1.9 1.35) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "G$4" smd rect (at 8.24 11.075 90) (size 1.9 1.35) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "P$1" smd rect (at 9.105 0.25 270) (size 0.85 1.1) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 27 "SDIO_D2") (solder_mask_margin 0.0762))
    (pad "P$2" smd rect (at 8.005 0.25 270) (size 0.85 1.1) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 35 "SDIO_D3") (solder_mask_margin 0.0762))
    (pad "P$3" smd rect (at 6.905 0.25 270) (size 0.85 1.1) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 29 "SDIO_CMD") (solder_mask_margin 0.0762))
    (pad "P$4" smd rect (at 5.805 0.25 270) (size 0.85 1.1) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 7 "VCC") (solder_mask_margin 0.0762))
    (pad "P$5" smd rect (at 4.705 0.25 270) (size 0.85 1.1) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 28 "SDIO_CLK") (solder_mask_margin 0.0762))
    (pad "P$6" smd rect (at 3.605 0.25 270) (size 0.85 1.1) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 1 "GND") (solder_mask_margin 0.0762))
    (pad "P$7" smd rect (at 2.505 0.25 270) (size 0.85 1.1) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 25 "SDIO_D0") (solder_mask_margin 0.0762))
    (pad "P$8" smd rect (at 1.455 0.25 270) (size 0.75 1.1) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 26 "SDIO_D1") (solder_mask_margin 0.0762))
  )
  (footprint "qstache 2 layer rev7:WEEE" placed (layer "B.Cu")
    (tedit 0)
    (at 262.127 135.127 180)
    (fp_text reference "U$1" (at 0 0) (layer "B.SilkS") hide)
    (fp_text value "" (at 0 0) (layer "B.Fab") hide)
  )
  (gr_rect (start 182.626 165.227) (end 119.38 47.117) (layer "Edge.Cuts") (width 0.05) (fill none))
)
