Verilog to Routing - VPR
netlist_fwd.h
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1 #ifndef NETLIST_FWD_H
2 #define NETLIST_FWD_H
3 #include "vtr_strong_id.h"
4 
5 /*
6  * Ids
7  * ---
8  * The Netlist uses unique IDs passed in by derived classes to identify any component of the netlist.
9  * To avoid type-conversion errors (e.g. passing a PinId where a NetId was expected),
10  * we use vtr::StrongId's to disallow such conversions. See vtr_strong_id.h for details.
11  */
12 template<typename BlockId, typename PortId, typename PinId, typename NetId>
13 class Netlist;
14 
16 typedef unsigned BitIndex;
17 
19 enum class PortType : char {
20  INPUT,
21  OUTPUT,
22  CLOCK
23 };
24 
25 enum class PinType : char {
26  DRIVER,
27  SINK,
28  OPEN
29 };
30 
31 #endif
PortType
The type of a port in the Netlist.
Definition: netlist_fwd.h:19
unsigned BitIndex
A signal index in a port.
Definition: netlist_fwd.h:13
PinType
Definition: netlist_fwd.h:25
Definition: netlist.h:446