Electronic Design Interchange Format (EDIF) is a standard data exchange format for electronic design automation (EDA) tools. It's widely used in the electronics industry to facilitate data exchange between different EDA tools and platforms. Understanding EDIF rules is crucial for seamless integration and interoperability between these tools. Let's delve into the key aspects of EDIF rules.
EDIF was first introduced in 1987 by a consortium of EDA vendors. It has since evolved through several revisions, with the current version being EDIF 2.0.1. This standard defines a set of rules and guidelines for describing electronic designs in a neutral, text-based format.
EDIF File Structure
EDIF files are plain text files with a .edi extension. They consist of a sequence of records, each starting with a record type code followed by record-specific data. The file structure adheres to a specific hierarchy, with design, library, and cell being the top-level entities.
The EDIF file structure is hierarchical, allowing for the organization of designs into libraries and cells. This structure enables the creation of reusable design components and promotes modular design practices.
Design Entity
The design entity is the top-level entity in an EDIF file. It represents the entire design or a significant portion of it. A design entity can contain other design entities, libraries, and cells, creating a hierarchical structure.
Design entities can be netlists, which describe the connectivity of a design, or structural representations, which provide a more detailed view of the design's components and their interconnections.
Library and Cell Entities
Libraries in EDIF are collections of reusable design entities, known as cells. A cell can represent a simple component like an inverter or a complex block like a processor. Libraries allow designers to create and share standard cells, promoting consistency and reuse across designs.
Cells can be instantiated within other cells or designs, creating a hierarchical design structure. Each instance of a cell can have its own parameters and connectivity, allowing for flexible and customizable design blocks.
EDIF Data Types and Attributes
EDIF defines a set of data types and attributes to describe electronic design elements and their properties. These include integers, reals, strings, booleans, and enumerated types. Attributes provide additional information about design entities, such as their name, type, or value.
EDIF also supports arrays and structures, allowing for complex data types to be represented. This enables the description of intricate design elements and their relationships.
Net and Pin Attributes
EDIF provides special attributes for nets and pins, which are crucial for describing the connectivity of a design. Nets represent electrical connections between pins, while pins are the points of connection on design entities.
Attributes like net name, pin name, net type (e.g., signal, power, ground), and pin direction (input, output, bidirectional) help define the connectivity and functionality of a design.
Parameter Attributes
Parameters in EDIF allow designers to customize the behavior of design entities. Parameters can be associated with cells, nets, or other design entities and can be used to control various aspects of the design, such as component sizes, voltages, or timing constraints.
EDIF supports both fixed and variable parameters. Fixed parameters have a constant value, while variable parameters can be adjusted to meet specific design requirements.
EDIF Compatibility and Conversion
EDIF's primary goal is to enable data exchange between different EDA tools. To ensure compatibility, EDIF files must adhere to specific rules and conventions. These include using standard record types and data formats, adhering to the defined hierarchy, and using valid EDIF syntax.
EDIF conversion tools are used to translate designs between EDIF and other file formats, such as OASIS, GDSII, or proprietary formats. These tools must follow the EDIF rules to ensure accurate and lossless conversion.
EDIF-to-OASIS Conversion
Open Access Silicon (OASIS) is a standard data exchange format for physical design data. EDIF-to-OASIS conversion is a common process in the EDA flow, enabling the exchange of design data between different tools and platforms.
During conversion, the EDIF hierarchy is mapped to the OASIS hierarchy, and design entities are translated into their corresponding OASIS representations. Special care must be taken to preserve design intent and connectivity during the conversion process.
EDIF-to-GDSII Conversion
GDSII (Graphic Data System II) is a binary format used to represent physical design data. EDIF-to-GDSII conversion is required when generating photomasks for semiconductor manufacturing.
During conversion, the EDIF hierarchy is flattened, and design entities are translated into geometric shapes. The connectivity information in EDIF is not preserved in GDSII, as GDSII is a layout-only format.
In the dynamic world of electronic design automation, understanding and adhering to EDIF rules is essential for seamless data exchange and interoperability between EDA tools. As the industry continues to evolve, so too will the EDIF standard, ensuring its continued relevance in the EDA landscape.