generic_dram¶

Predefined DRAM tests. DRAM is called “Memory” in AVL.

Inherit¶

component_list

[
  "dram"
]

config_file

"/usr/local/factory/py/hwid/v3/default_probe_statement.json"

overridden_rules

[
  [
    "dram",
    ">",
    0
  ]
]

{
  "args": {
    "mode": "create"
  },
  "label": "i18n! Create Cache",
  "pytest_name": "mrc_cache"
}

{
  "args": {
    "mode": "verify_update"
  },
  "label": "i18n! Verify Cache Update",
  "pytest_name": "mrc_cache"
}

{
  "args": {
    "mode": "verify_no_update"
  },
  "label": "i18n! Verify Cache No Update",
  "pytest_name": "mrc_cache"
}