Coverage for /pythoncovmergedfiles/medio/medio/usr/local/lib/python3.8/site-packages/archinfo/arch_ppc32.py: 88%

1from .arch import Arch, register_arch, Endness, Register 

2from .tls import TLSArchInfo 

3 

4try: 

5 import capstone as _capstone 

6except ImportError: 

7 _capstone = None 

8 

9try: 

10 import keystone as _keystone 

11except ImportError: 

12 _keystone = None 

13 

14try: 

15 import pyvex as _pyvex 

16except ImportError: 

17 _pyvex = None 

18 

19# Note: PowerPC doesn't have pc, so guest_CIA is commented as IP (no arch visible register) 

20# PowerPC doesn't have stack base pointer, so bp_offset is set to -1 below 

21# Normally r1 is used as stack pointer 

22 

23 

24class ArchPPC32(Arch): 

25 def __init__(self, endness=Endness.LE): 

26 super().__init__(endness) 

27 if endness == Endness.BE: 

28 self.function_prologs = { 

29 # stwu r1, -off(r1); mflr r0 

30 rb"\x94\x21[\x00-\xff]{2}\x7c\x08\x02\xa6" 

31 } 

32 self.function_epilogs = { 

33 # mtlr reg; ... ; blr 

34 rb"[\x00-\xff]{2}\x03\xa6([\x00-\xff]{4}){0,6}\x4e\x80\x00\x20" 

35 } 

36 

37 self.argument_register_positions = ( 

38 { 

39 self.registers["r3"][0]: 0, 

40 self.registers["r4"][0]: 1, 

41 self.registers["r5"][0]: 2, 

42 self.registers["r6"][0]: 3, 

43 self.registers["r7"][0]: 4, 

44 self.registers["r8"][0]: 5, 

45 self.registers["r9"][0]: 6, 

46 self.registers["r10"][0]: 7, 

47 } 

48 if _pyvex is not None 

49 else None 

50 ) 

51 

52 bits = 32 

53 vex_arch = "VexArchPPC32" 

54 name = "PPC32" 

55 qemu_name = "ppc" 

56 ida_processor = "ppc" 

57 linux_name = "ppc750" # ? 

58 triplet = "powerpc-linux-gnu" 

59 max_inst_bytes = 4 

60 # https://www.ibm.com/developerworks/community/forums/html/topic?id=77777777-0000-0000-0000-000013836863 

61 # claims that r15 is the base pointer but that is NOT what I see in practice 

62 ret_offset = 28 

63 syscall_num_offset = 16 

64 call_pushes_ret = False 

65 stack_change = -4 

66 sizeof = {"short": 16, "int": 32, "long": 32, "long long": 64} 

67 if _capstone: 

68 cs_arch = _capstone.CS_ARCH_PPC 

69 cs_mode = _capstone.CS_MODE_32 + _capstone.CS_MODE_LITTLE_ENDIAN 

70 if _keystone: 

71 ks_arch = _keystone.KS_ARCH_PPC 

72 ks_mode = _keystone.KS_MODE_32 + _keystone.KS_MODE_LITTLE_ENDIAN 

73 # Unicorn not supported 

74 # uc_arch = _unicorn.UC_ARCH_PPC if _unicorn else None 

75 # uc_mode = (_unicorn.UC_MODE_32 + _unicorn.UC_MODE_LITTLE_ENDIAN) if _unicorn else None 

76 ret_instruction = b"\x20\x00\x80\x4e" 

77 nop_instruction = b"\x00\x00\x00\x60" 

78 instruction_alignment = 4 

79 register_list = [ 

80 Register(name="gpr0", size=4, alias_names=("r0",), general_purpose=True), 

81 Register( 

82 name="gpr1", 

83 size=4, 

84 alias_names=("r1", "sp"), 

85 general_purpose=True, 

86 default_value=(Arch.initial_sp, True, "global"), 

87 ), 

88 Register(name="gpr2", size=4, alias_names=("r2",), general_purpose=True), 

89 Register( 

90 name="gpr3", size=4, alias_names=("r3",), general_purpose=True, argument=True, linux_entry_value="argc" 

91 ), 

92 Register( 

93 name="gpr4", size=4, alias_names=("r4",), general_purpose=True, argument=True, linux_entry_value="argv" 

94 ), 

95 Register( 

96 name="gpr5", size=4, alias_names=("r5",), general_purpose=True, argument=True, linux_entry_value="envp" 

97 ), 

98 Register( 

99 name="gpr6", size=4, alias_names=("r6",), general_purpose=True, argument=True, linux_entry_value="auxv" 

100 ), 

101 Register( 

102 name="gpr7", 

103 size=4, 

104 alias_names=("r7",), 

105 general_purpose=True, 

106 argument=True, 

107 linux_entry_value="ld_destructor", 

108 ), 

109 Register(name="gpr8", size=4, alias_names=("r8",), general_purpose=True, argument=True), 

110 Register(name="gpr9", size=4, alias_names=("r9",), general_purpose=True, argument=True), 

111 Register(name="gpr10", size=4, alias_names=("r10",), general_purpose=True, argument=True), 

112 Register(name="gpr11", size=4, alias_names=("r11",), general_purpose=True), 

113 Register(name="gpr12", size=4, alias_names=("r12",), general_purpose=True), 

114 Register(name="gpr13", size=4, alias_names=("r13",), general_purpose=True), 

115 Register(name="gpr14", size=4, alias_names=("r14",), general_purpose=True), 

116 Register(name="gpr15", size=4, alias_names=("r15",), general_purpose=True), 

117 Register(name="gpr16", size=4, alias_names=("r16",), general_purpose=True), 

118 Register(name="gpr17", size=4, alias_names=("r17",), general_purpose=True), 

119 Register(name="gpr18", size=4, alias_names=("r18",), general_purpose=True), 

120 Register(name="gpr19", size=4, alias_names=("r19",), general_purpose=True), 

121 Register(name="gpr20", size=4, alias_names=("r20",), general_purpose=True), 

122 Register(name="gpr21", size=4, alias_names=("r21",), general_purpose=True), 

123 Register(name="gpr22", size=4, alias_names=("r22",), general_purpose=True), 

124 Register(name="gpr23", size=4, alias_names=("r23",), general_purpose=True), 

125 Register(name="gpr24", size=4, alias_names=("r24",), general_purpose=True), 

126 Register(name="gpr25", size=4, alias_names=("r25",), general_purpose=True, persistent=True), 

127 Register(name="gpr26", size=4, alias_names=("r26",), general_purpose=True), 

128 Register(name="gpr27", size=4, alias_names=("r27",), general_purpose=True), 

129 Register(name="gpr28", size=4, alias_names=("r28",), general_purpose=True), 

130 Register(name="gpr29", size=4, alias_names=("r29",), general_purpose=True), 

131 Register(name="gpr30", size=4, alias_names=("r30",), general_purpose=True), 

132 Register(name="gpr31", size=4, alias_names=("r31", "bp"), general_purpose=True), 

133 Register(name="vsr0", size=16, subregisters=[("fpr0", 0, 8)], alias_names=("v0",), floating_point=True), 

134 Register(name="vsr1", size=16, subregisters=[("fpr1", 0, 8)], alias_names=("v1",), floating_point=True), 

135 Register(name="vsr2", size=16, subregisters=[("fpr2", 0, 8)], alias_names=("v2",), floating_point=True), 

136 Register(name="vsr3", size=16, subregisters=[("fpr3", 0, 8)], alias_names=("v3",), floating_point=True), 

137 Register(name="vsr4", size=16, subregisters=[("fpr4", 0, 8)], alias_names=("v4",), floating_point=True), 

138 Register(name="vsr5", size=16, subregisters=[("fpr5", 0, 8)], alias_names=("v5",), floating_point=True), 

139 Register(name="vsr6", size=16, subregisters=[("fpr6", 0, 8)], alias_names=("v6",), floating_point=True), 

140 Register(name="vsr7", size=16, subregisters=[("fpr7", 0, 8)], alias_names=("v7",), floating_point=True), 

141 Register(name="vsr8", size=16, subregisters=[("fpr8", 0, 8)], alias_names=("v8",), floating_point=True), 

142 Register(name="vsr9", size=16, subregisters=[("fpr9", 0, 8)], alias_names=("v9",), floating_point=True), 

143 Register(name="vsr10", size=16, subregisters=[("fpr10", 0, 8)], alias_names=("v10",), floating_point=True), 

144 Register(name="vsr11", size=16, subregisters=[("fpr11", 0, 8)], alias_names=("v11",), floating_point=True), 

145 Register(name="vsr12", size=16, subregisters=[("fpr12", 0, 8)], alias_names=("v12",), floating_point=True), 

146 Register(name="vsr13", size=16, subregisters=[("fpr13", 0, 8)], alias_names=("v13",), floating_point=True), 

147 Register(name="vsr14", size=16, subregisters=[("fpr14", 0, 8)], alias_names=("v14",), floating_point=True), 

148 Register(name="vsr15", size=16, subregisters=[("fpr15", 0, 8)], alias_names=("v15",), floating_point=True), 

149 Register(name="vsr16", size=16, subregisters=[("fpr16", 0, 8)], alias_names=("v16",), floating_point=True), 

150 Register(name="vsr17", size=16, subregisters=[("fpr17", 0, 8)], alias_names=("v17",), floating_point=True), 

151 Register(name="vsr18", size=16, subregisters=[("fpr18", 0, 8)], alias_names=("v18",), floating_point=True), 

152 Register(name="vsr19", size=16, subregisters=[("fpr19", 0, 8)], alias_names=("v19",), floating_point=True), 

153 Register(name="vsr20", size=16, subregisters=[("fpr20", 0, 8)], alias_names=("v20",), floating_point=True), 

154 Register(name="vsr21", size=16, subregisters=[("fpr21", 0, 8)], alias_names=("v21",), floating_point=True), 

155 Register(name="vsr22", size=16, subregisters=[("fpr22", 0, 8)], alias_names=("v22",), floating_point=True), 

156 Register(name="vsr23", size=16, subregisters=[("fpr23", 0, 8)], alias_names=("v23",), floating_point=True), 

157 Register(name="vsr24", size=16, subregisters=[("fpr24", 0, 8)], alias_names=("v24",), floating_point=True), 

158 Register(name="vsr25", size=16, subregisters=[("fpr25", 0, 8)], alias_names=("v25",), floating_point=True), 

159 Register(name="vsr26", size=16, subregisters=[("fpr26", 0, 8)], alias_names=("v26",), floating_point=True), 

160 Register(name="vsr27", size=16, subregisters=[("fpr27", 0, 8)], alias_names=("v27",), floating_point=True), 

161 Register(name="vsr28", size=16, subregisters=[("fpr28", 0, 8)], alias_names=("v28",), floating_point=True), 

162 Register(name="vsr29", size=16, subregisters=[("fpr29", 0, 8)], alias_names=("v29",), floating_point=True), 

163 Register(name="vsr30", size=16, subregisters=[("fpr30", 0, 8)], alias_names=("v30",), floating_point=True), 

164 Register(name="vsr31", size=16, subregisters=[("fpr31", 0, 8)], alias_names=("v31",), floating_point=True), 

165 Register(name="vsr32", size=16, alias_names=("v32",), vector=True), 

166 Register(name="vsr33", size=16, alias_names=("v33",), vector=True), 

167 Register(name="vsr34", size=16, alias_names=("v34",), vector=True), 

168 Register(name="vsr35", size=16, alias_names=("v35",), vector=True), 

169 Register(name="vsr36", size=16, alias_names=("v36",), vector=True), 

170 Register(name="vsr37", size=16, alias_names=("v37",), vector=True), 

171 Register(name="vsr38", size=16, alias_names=("v38",), vector=True), 

172 Register(name="vsr39", size=16, alias_names=("v39",), vector=True), 

173 Register(name="vsr40", size=16, alias_names=("v40",), vector=True), 

174 Register(name="vsr41", size=16, alias_names=("v41",), vector=True), 

175 Register(name="vsr42", size=16, alias_names=("v42",), vector=True), 

176 Register(name="vsr43", size=16, alias_names=("v43",), vector=True), 

177 Register(name="vsr44", size=16, alias_names=("v44",), vector=True), 

178 Register(name="vsr45", size=16, alias_names=("v45",), vector=True), 

179 Register(name="vsr46", size=16, alias_names=("v46",), vector=True), 

180 Register(name="vsr47", size=16, alias_names=("v47",), vector=True), 

181 Register(name="vsr48", size=16, alias_names=("v48",), vector=True), 

182 Register(name="vsr49", size=16, alias_names=("v49",), vector=True), 

183 Register(name="vsr50", size=16, alias_names=("v50",), vector=True), 

184 Register(name="vsr51", size=16, alias_names=("v51",), vector=True), 

185 Register(name="vsr52", size=16, alias_names=("v52",), vector=True), 

186 Register(name="vsr53", size=16, alias_names=("v53",), vector=True), 

187 Register(name="vsr54", size=16, alias_names=("v54",), vector=True), 

188 Register(name="vsr55", size=16, alias_names=("v55",), vector=True), 

189 Register(name="vsr56", size=16, alias_names=("v56",), vector=True), 

190 Register(name="vsr57", size=16, alias_names=("v57",), vector=True), 

191 Register(name="vsr58", size=16, alias_names=("v58",), vector=True), 

192 Register(name="vsr59", size=16, alias_names=("v59",), vector=True), 

193 Register(name="vsr60", size=16, alias_names=("v60",), vector=True), 

194 Register(name="vsr61", size=16, alias_names=("v61",), vector=True), 

195 Register(name="vsr62", size=16, alias_names=("v62",), vector=True), 

196 Register(name="vsr63", size=16, alias_names=("v63",), vector=True), 

197 Register(name="cia", size=4, alias_names=("ip", "pc")), 

198 Register(name="lr", size=4), 

199 Register(name="ctr", size=4), 

200 Register(name="xer_so", size=1), 

201 Register(name="xer_ov", size=1), 

202 Register(name="xer_ca", size=1), 

203 Register(name="xer_bc", size=1), 

204 Register(name="cr0_321", size=1), 

205 Register(name="cr0_0", size=1, alias_names=("cr0",)), 

206 Register(name="cr1_321", size=1), 

207 Register(name="cr1_0", size=1, alias_names=("cr1",)), 

208 Register(name="cr2_321", size=1), 

209 Register(name="cr2_0", size=1, alias_names=("cr2",)), 

210 Register(name="cr3_321", size=1), 

211 Register(name="cr3_0", size=1, alias_names=("cr3",)), 

212 Register(name="cr4_321", size=1), 

213 Register(name="cr4_0", size=1, alias_names=("cr4",)), 

214 Register(name="cr5_321", size=1), 

215 Register(name="cr5_0", size=1, alias_names=("cr5",)), 

216 Register(name="cr6_321", size=1), 

217 Register(name="cr6_0", size=1, alias_names=("cr6",)), 

218 Register(name="cr7_321", size=1), 

219 Register(name="cr7_0", size=1, alias_names=("cr7",)), 

220 Register(name="fpround", size=1, floating_point=True), 

221 Register(name="dfpround", size=1, floating_point=True), 

222 Register(name="c_fpcc", size=1, floating_point=True), 

223 Register(name="vrsave", size=4, vector=True), 

224 Register(name="vscr", size=4, vector=True), 

225 Register(name="emnote", size=4, artificial=True), 

226 Register(name="cmstart", size=4), 

227 Register(name="cmlen", size=4), 

228 Register(name="nraddr", size=4), 

229 Register(name="nraddr_gpr2", size=4), 

230 Register(name="redir_sp", size=4), 

231 Register(name="redir_stack", size=128), 

232 Register(name="ip_at_syscall", size=4, artificial=True), 

233 Register(name="sprg3_ro", size=4), 

234 Register(name="tfhar", size=8), 

235 Register(name="texasr", size=8), 

236 Register(name="tfiar", size=8), 

237 Register(name="ppr", size=8), 

238 Register(name="texasru", size=4), 

239 Register(name="pspb", size=4), 

240 ] 

241 

242 function_prologs = { 

243 rb"[\x00-\xff]{2}\x21\x94\xa6\x02\x08\x7c", # stwu r1, -off(r1); mflr r0 

244 } 

245 function_epilogs = {rb"\xa6\x03[\x00-\xff]{2}([\x00-\xff]{4}){0,6}\x20\x00\x80\x4e"} # mtlr reg; ... ; blr 

246 

247 got_section_name = ".plt" 

248 ld_linux_name = "ld.so.1" 

249 elf_tls = TLSArchInfo(1, 52, [], [48], [], 0x7000, 0x8000) 

250 

251 dwarf_registers = [ 

252 "gpr0", 

253 "gpr1", 

254 "gpr2", 

255 "gpr3", 

256 "gpr4", 

257 "gpr5", 

258 "gpr6", 

259 "gpr7", 

260 "gpr8", 

261 "gpr9", 

262 "gpr10", 

263 "gpr11", 

264 "gpr12", 

265 "gpr13", 

266 "gpr14", 

267 "gpr15", 

268 "gpr16", 

269 "gpr17", 

270 "gpr18", 

271 "gpr19", 

272 "gpr20", 

273 "gpr21", 

274 "gpr22", 

275 "gpr23", 

276 "gpr24", 

277 "gpr25", 

278 "gpr26", 

279 "gpr27", 

280 "gpr28", 

281 "gpr29", 

282 "gpr30", 

283 "gpr31", 

284 "vsr0", 

285 "vsr1", 

286 "vsr2", 

287 "vsr3", 

288 "vsr4", 

289 "vsr5", 

290 "vsr6", 

291 "vsr7", 

292 "vsr8", 

293 "vsr9", 

294 "vsr10", 

295 "vsr11", 

296 "vsr12", 

297 "vsr13", 

298 "vsr14", 

299 "vsr15", 

300 "vsr16", 

301 "vsr17", 

302 "vsr18", 

303 "vsr19", 

304 "vsr20", 

305 "vsr21", 

306 "vsr22", 

307 "vsr23", 

308 "vsr24", 

309 "vsr25", 

310 "vsr26", 

311 "vsr27", 

312 "vsr28", 

313 "vsr29", 

314 "vsr30", 

315 "vsr31", 

316 "cr", 

317 "fpscr", 

318 ] 

319 

320 

321register_arch([r".*p\w*pc.*be"], 32, "Iend_BE", ArchPPC32) 

322register_arch([r".*p\w*pc.*"], 32, "any", ArchPPC32)