Coverage for /pythoncovmergedfiles/medio/medio/usr/local/lib/python3.8/site-packages/archinfo/arch_ppc64.py: 89%

1from .arch import Arch, register_arch, Endness, Register 

2from .tls import TLSArchInfo 

3 

4try: 

5 import capstone as _capstone 

6except ImportError: 

7 _capstone = None 

8 

9try: 

10 import keystone as _keystone 

11except ImportError: 

12 _keystone = None 

13 

14try: 

15 import pyvex as _pyvex 

16except ImportError: 

17 _pyvex = None 

18 

19# Note: PowerPC doesn't have pc, so guest_CIA is commented as IP (no arch visible register) 

20# Normally r1 is used as stack pointer 

21 

22 

23class ArchPPC64(Arch): 

24 def __init__(self, endness=Endness.LE): 

25 super().__init__(endness) 

26 if endness == Endness.BE: 

27 self.function_prologs = { 

28 rb"\x94\x21[\x00-\xff]{2}\x7c\x08\x02\xa6", # stwu r1, -off(r1); mflr r0 

29 rb"(?!\x94\x21[\x00-\xff]{2})\x7c\x08\x02\xa6", # mflr r0 

30 rb"\xf8\x61[\x00-\xff]{2}", # std r3, -off(r1) 

31 } 

32 self.function_epilogs = { 

33 rb"[\x00-\xff]{2}\x03\xa6([\x00-\xff]{4}){0,6}\x4e\x80\x00\x20" # mtlr reg; ... ; blr 

34 } 

35 self.triplet = "powerpc-linux-gnu" 

36 self.argument_register_positions = ( 

37 { 

38 self.registers["r3"][0]: 0, 

39 self.registers["r4"][0]: 1, 

40 self.registers["r5"][0]: 2, 

41 self.registers["r6"][0]: 3, 

42 self.registers["r7"][0]: 4, 

43 self.registers["r8"][0]: 5, 

44 self.registers["r9"][0]: 6, 

45 self.registers["r10"][0]: 7, 

46 # fp registers 

47 self.registers["vsr1"][0]: 0, 

48 self.registers["vsr2"][0]: 1, 

49 self.registers["vsr3"][0]: 2, 

50 self.registers["vsr4"][0]: 3, 

51 self.registers["vsr5"][0]: 4, 

52 self.registers["vsr6"][0]: 5, 

53 self.registers["vsr7"][0]: 6, 

54 self.registers["vsr8"][0]: 7, 

55 self.registers["vsr9"][0]: 8, 

56 self.registers["vsr10"][0]: 9, 

57 self.registers["vsr11"][0]: 10, 

58 self.registers["vsr12"][0]: 11, 

59 self.registers["vsr13"][0]: 12, 

60 # vector registers 

61 self.registers["vsr2"][0]: 0, 

62 self.registers["vsr3"][0]: 1, 

63 self.registers["vsr4"][0]: 2, 

64 self.registers["vsr5"][0]: 3, 

65 self.registers["vsr6"][0]: 4, 

66 self.registers["vsr7"][0]: 5, 

67 self.registers["vsr8"][0]: 6, 

68 self.registers["vsr9"][0]: 7, 

69 self.registers["vsr10"][0]: 8, 

70 self.registers["vsr11"][0]: 9, 

71 self.registers["vsr12"][0]: 10, 

72 self.registers["vsr13"][0]: 11, 

73 } 

74 if _pyvex is not None 

75 else None 

76 ) 

77 

78 bits = 64 

79 vex_arch = "VexArchPPC64" 

80 name = "PPC64" 

81 qemu_name = "ppc64" 

82 ida_processor = "ppc64" 

83 triplet = "powerpc64le-linux-gnu" 

84 linux_name = "ppc750" 

85 max_inst_bytes = 4 

86 ret_offset = 40 

87 syscall_num_offset = 16 

88 call_pushes_ret = False 

89 stack_change = -8 

90 initial_sp = 0xFFFFFFFFFF000000 

91 sizeof = {"short": 16, "int": 32, "long": 64, "long long": 64} 

92 if _capstone: 

93 cs_arch = _capstone.CS_ARCH_PPC 

94 cs_mode = _capstone.CS_MODE_64 + _capstone.CS_MODE_LITTLE_ENDIAN 

95 if _keystone: 

96 ks_arch = _keystone.KS_ARCH_PPC 

97 ks_mode = _keystone.KS_MODE_64 + _keystone.KS_MODE_LITTLE_ENDIAN 

98 # Unicorn not supported 

99 # uc_arch = _unicorn.UC_ARCH_PPC if _unicorn else None 

100 # uc_mode = (_unicorn.UC_MODE_64 + _unicorn.UC_MODE_LITTLE_ENDIAN) if _unicorn else None 

101 ret_instruction = b"\x20\x00\x80\x4e" 

102 nop_instruction = b"\x00\x00\x00\x60" 

103 instruction_alignment = 4 

104 register_list = [ 

105 Register(name="gpr0", size=8, alias_names=("r0",), general_purpose=True), 

106 Register( 

107 name="gpr1", 

108 size=8, 

109 alias_names=("r1", "sp"), 

110 general_purpose=True, 

111 default_value=(initial_sp, True, "global"), 

112 ), 

113 Register( 

114 name="gpr2", 

115 size=8, 

116 alias_names=("r2", "rtoc"), 

117 general_purpose=True, 

118 persistent=True, 

119 linux_entry_value="toc", 

120 ), 

121 Register( 

122 name="gpr3", size=8, alias_names=("r3",), general_purpose=True, argument=True, linux_entry_value="argc" 

123 ), 

124 Register( 

125 name="gpr4", size=8, alias_names=("r4",), general_purpose=True, argument=True, linux_entry_value="argv" 

126 ), 

127 Register( 

128 name="gpr5", size=8, alias_names=("r5",), general_purpose=True, argument=True, linux_entry_value="envp" 

129 ), 

130 Register( 

131 name="gpr6", size=8, alias_names=("r6",), general_purpose=True, argument=True, linux_entry_value="auxv" 

132 ), 

133 Register( 

134 name="gpr7", 

135 size=8, 

136 alias_names=("r7",), 

137 general_purpose=True, 

138 argument=True, 

139 linux_entry_value="ld_destructor", 

140 ), 

141 Register(name="gpr8", size=8, alias_names=("r8",), general_purpose=True, argument=True), 

142 Register(name="gpr9", size=8, alias_names=("r9",), general_purpose=True, argument=True), 

143 Register(name="gpr10", size=8, alias_names=("r10",), general_purpose=True, argument=True), 

144 Register(name="gpr11", size=8, alias_names=("r11",), general_purpose=True), 

145 Register(name="gpr12", size=8, alias_names=("r12",), general_purpose=True, linux_entry_value="entry"), 

146 Register(name="gpr13", size=8, alias_names=("r13",), general_purpose=True), 

147 Register(name="gpr14", size=8, alias_names=("r14",), general_purpose=True), 

148 Register(name="gpr15", size=8, alias_names=("r15",), general_purpose=True), 

149 Register(name="gpr16", size=8, alias_names=("r16",), general_purpose=True), 

150 Register(name="gpr17", size=8, alias_names=("r17",), general_purpose=True), 

151 Register(name="gpr18", size=8, alias_names=("r18",), general_purpose=True), 

152 Register(name="gpr19", size=8, alias_names=("r19",), general_purpose=True), 

153 Register(name="gpr20", size=8, alias_names=("r20",), general_purpose=True), 

154 Register(name="gpr21", size=8, alias_names=("r21",), general_purpose=True), 

155 Register(name="gpr22", size=8, alias_names=("r22",), general_purpose=True), 

156 Register(name="gpr23", size=8, alias_names=("r23",), general_purpose=True), 

157 Register(name="gpr24", size=8, alias_names=("r24",), general_purpose=True), 

158 Register(name="gpr25", size=8, alias_names=("r25",), general_purpose=True, persistent=True), 

159 Register(name="gpr26", size=8, alias_names=("r26",), general_purpose=True), 

160 Register(name="gpr27", size=8, alias_names=("r27",), general_purpose=True), 

161 Register(name="gpr28", size=8, alias_names=("r28",), general_purpose=True), 

162 Register(name="gpr29", size=8, alias_names=("r29",), general_purpose=True), 

163 Register(name="gpr30", size=8, alias_names=("r30",), general_purpose=True), 

164 Register(name="gpr31", size=8, alias_names=("r31", "bp"), general_purpose=True), 

165 Register(name="vsr0", size=16, subregisters=[("fpr0", 0, 8)], alias_names=("v0",), floating_point=True), 

166 Register(name="vsr1", size=16, subregisters=[("fpr1", 0, 8)], alias_names=("v1",), floating_point=True), 

167 Register(name="vsr2", size=16, subregisters=[("fpr2", 0, 8)], alias_names=("v2",), floating_point=True), 

168 Register(name="vsr3", size=16, subregisters=[("fpr3", 0, 8)], alias_names=("v3",), floating_point=True), 

169 Register(name="vsr4", size=16, subregisters=[("fpr4", 0, 8)], alias_names=("v4",), floating_point=True), 

170 Register(name="vsr5", size=16, subregisters=[("fpr5", 0, 8)], alias_names=("v5",), floating_point=True), 

171 Register(name="vsr6", size=16, subregisters=[("fpr6", 0, 8)], alias_names=("v6",), floating_point=True), 

172 Register(name="vsr7", size=16, subregisters=[("fpr7", 0, 8)], alias_names=("v7",), floating_point=True), 

173 Register(name="vsr8", size=16, subregisters=[("fpr8", 0, 8)], alias_names=("v8",), floating_point=True), 

174 Register(name="vsr9", size=16, subregisters=[("fpr9", 0, 8)], alias_names=("v9",), floating_point=True), 

175 Register(name="vsr10", size=16, subregisters=[("fpr10", 0, 8)], alias_names=("v10",), floating_point=True), 

176 Register(name="vsr11", size=16, subregisters=[("fpr11", 0, 8)], alias_names=("v11",), floating_point=True), 

177 Register(name="vsr12", size=16, subregisters=[("fpr12", 0, 8)], alias_names=("v12",), floating_point=True), 

178 Register(name="vsr13", size=16, subregisters=[("fpr13", 0, 8)], alias_names=("v13",), floating_point=True), 

179 Register(name="vsr14", size=16, subregisters=[("fpr14", 0, 8)], alias_names=("v14",), floating_point=True), 

180 Register(name="vsr15", size=16, subregisters=[("fpr15", 0, 8)], alias_names=("v15",), floating_point=True), 

181 Register(name="vsr16", size=16, subregisters=[("fpr16", 0, 8)], alias_names=("v16",), floating_point=True), 

182 Register(name="vsr17", size=16, subregisters=[("fpr17", 0, 8)], alias_names=("v17",), floating_point=True), 

183 Register(name="vsr18", size=16, subregisters=[("fpr18", 0, 8)], alias_names=("v18",), floating_point=True), 

184 Register(name="vsr19", size=16, subregisters=[("fpr19", 0, 8)], alias_names=("v19",), floating_point=True), 

185 Register(name="vsr20", size=16, subregisters=[("fpr20", 0, 8)], alias_names=("v20",), floating_point=True), 

186 Register(name="vsr21", size=16, subregisters=[("fpr21", 0, 8)], alias_names=("v21",), floating_point=True), 

187 Register(name="vsr22", size=16, subregisters=[("fpr22", 0, 8)], alias_names=("v22",), floating_point=True), 

188 Register(name="vsr23", size=16, subregisters=[("fpr23", 0, 8)], alias_names=("v23",), floating_point=True), 

189 Register(name="vsr24", size=16, subregisters=[("fpr24", 0, 8)], alias_names=("v24",), floating_point=True), 

190 Register(name="vsr25", size=16, subregisters=[("fpr25", 0, 8)], alias_names=("v25",), floating_point=True), 

191 Register(name="vsr26", size=16, subregisters=[("fpr26", 0, 8)], alias_names=("v26",), floating_point=True), 

192 Register(name="vsr27", size=16, subregisters=[("fpr27", 0, 8)], alias_names=("v27",), floating_point=True), 

193 Register(name="vsr28", size=16, subregisters=[("fpr28", 0, 8)], alias_names=("v28",), floating_point=True), 

194 Register(name="vsr29", size=16, subregisters=[("fpr29", 0, 8)], alias_names=("v29",), floating_point=True), 

195 Register(name="vsr30", size=16, subregisters=[("fpr30", 0, 8)], alias_names=("v30",), floating_point=True), 

196 Register(name="vsr31", size=16, subregisters=[("fpr31", 0, 8)], alias_names=("v31",), floating_point=True), 

197 Register(name="vsr32", size=16, alias_names=("v32",), vector=True), 

198 Register(name="vsr33", size=16, alias_names=("v33",), vector=True), 

199 Register(name="vsr34", size=16, alias_names=("v34",), vector=True), 

200 Register(name="vsr35", size=16, alias_names=("v35",), vector=True), 

201 Register(name="vsr36", size=16, alias_names=("v36",), vector=True), 

202 Register(name="vsr37", size=16, alias_names=("v37",), vector=True), 

203 Register(name="vsr38", size=16, alias_names=("v38",), vector=True), 

204 Register(name="vsr39", size=16, alias_names=("v39",), vector=True), 

205 Register(name="vsr40", size=16, alias_names=("v40",), vector=True), 

206 Register(name="vsr41", size=16, alias_names=("v41",), vector=True), 

207 Register(name="vsr42", size=16, alias_names=("v42",), vector=True), 

208 Register(name="vsr43", size=16, alias_names=("v43",), vector=True), 

209 Register(name="vsr44", size=16, alias_names=("v44",), vector=True), 

210 Register(name="vsr45", size=16, alias_names=("v45",), vector=True), 

211 Register(name="vsr46", size=16, alias_names=("v46",), vector=True), 

212 Register(name="vsr47", size=16, alias_names=("v47",), vector=True), 

213 Register(name="vsr48", size=16, alias_names=("v48",), vector=True), 

214 Register(name="vsr49", size=16, alias_names=("v49",), vector=True), 

215 Register(name="vsr50", size=16, alias_names=("v50",), vector=True), 

216 Register(name="vsr51", size=16, alias_names=("v51",), vector=True), 

217 Register(name="vsr52", size=16, alias_names=("v52",), vector=True), 

218 Register(name="vsr53", size=16, alias_names=("v53",), vector=True), 

219 Register(name="vsr54", size=16, alias_names=("v54",), vector=True), 

220 Register(name="vsr55", size=16, alias_names=("v55",), vector=True), 

221 Register(name="vsr56", size=16, alias_names=("v56",), vector=True), 

222 Register(name="vsr57", size=16, alias_names=("v57",), vector=True), 

223 Register(name="vsr58", size=16, alias_names=("v58",), vector=True), 

224 Register(name="vsr59", size=16, alias_names=("v59",), vector=True), 

225 Register(name="vsr60", size=16, alias_names=("v60",), vector=True), 

226 Register(name="vsr61", size=16, alias_names=("v61",), vector=True), 

227 Register(name="vsr62", size=16, alias_names=("v62",), vector=True), 

228 Register(name="vsr63", size=16, alias_names=("v63",), vector=True), 

229 Register(name="cia", size=8, alias_names=("ip", "pc")), 

230 Register(name="lr", size=8), 

231 Register(name="ctr", size=8), 

232 Register(name="xer_so", size=1), 

233 Register(name="xer_ov", size=1), 

234 Register(name="xer_ca", size=1), 

235 Register(name="xer_bc", size=1), 

236 Register(name="cr0_321", size=1), 

237 Register(name="cr0_0", size=1, alias_names=("cr0",)), 

238 Register(name="cr1_321", size=1), 

239 Register(name="cr1_0", size=1, alias_names=("cr1",)), 

240 Register(name="cr2_321", size=1), 

241 Register(name="cr2_0", size=1, alias_names=("cr2",)), 

242 Register(name="cr3_321", size=1), 

243 Register(name="cr3_0", size=1, alias_names=("cr3",)), 

244 Register(name="cr4_321", size=1), 

245 Register(name="cr4_0", size=1, alias_names=("cr4",)), 

246 Register(name="cr5_321", size=1), 

247 Register(name="cr5_0", size=1, alias_names=("cr5",)), 

248 Register(name="cr6_321", size=1), 

249 Register(name="cr6_0", size=1, alias_names=("cr6",)), 

250 Register(name="cr7_321", size=1), 

251 Register(name="cr7_0", size=1, alias_names=("cr7",)), 

252 Register(name="fpround", size=1, floating_point=True), 

253 Register(name="dfpround", size=1, floating_point=True), 

254 Register(name="c_fpcc", size=1, floating_point=True), 

255 Register(name="vrsave", size=4, vector=True), 

256 Register(name="vscr", size=4, vector=True), 

257 Register(name="emnote", size=4, artificial=True), 

258 Register(name="cmstart", size=8), 

259 Register(name="cmlen", size=8), 

260 Register(name="nraddr", size=8), 

261 Register(name="nraddr_gpr2", size=8), 

262 Register(name="redir_sp", size=8), 

263 Register(name="redir_stack", size=256), 

264 Register(name="ip_at_syscall", size=8, artificial=True), 

265 Register(name="sprg3_ro", size=8), 

266 Register(name="tfhar", size=8), 

267 Register(name="texasr", size=8), 

268 Register(name="tfiar", size=8), 

269 Register(name="ppr", size=8), 

270 Register(name="texasru", size=4), 

271 Register(name="pspb", size=4), 

272 ] 

273 

274 # see https://github.com/riscv/riscv-binutils-gdb/blob/82dcb8613e1b1fb2989deffde1d3c9729695ff9c/include/elf/ppc64.h 

275 dynamic_tag_translation = { 

276 0x70000000: "DT_PPC64_GLINK", 

277 0x70000001: "DT_PPC64_OPD", 

278 0x70000002: "DT_PPC64_OPDSZ", 

279 0x70000003: "DT_PPC64_OPT", 

280 } 

281 

282 function_prologs = { 

283 rb"[\x00-\xff]{2}\x21\x94\xa6\x02\x08\x7c", # stwu r1, -off(r1); mflr r0 

284 } 

285 function_epilogs = {rb"\xa6\x03[\x00-\xff]{2}([\x00-\xff]{4}){0,6}\x20\x00\x80\x4e"} # mtlr reg; ... ; blr 

286 

287 got_section_name = ".plt" 

288 ld_linux_name = "ld64.so.1" 

289 elf_tls = TLSArchInfo(1, 92, [], [84], [], 0x7000, 0x8000) 

290 

291 dwarf_registers = [ 

292 "gpr0", 

293 "gpr1", 

294 "gpr2", 

295 "gpr3", 

296 "gpr4", 

297 "gpr5", 

298 "gpr6", 

299 "gpr7", 

300 "gpr8", 

301 "gpr9", 

302 "gpr10", 

303 "gpr11", 

304 "gpr12", 

305 "gpr13", 

306 "gpr14", 

307 "gpr15", 

308 "gpr16", 

309 "gpr17", 

310 "gpr18", 

311 "gpr19", 

312 "gpr20", 

313 "gpr21", 

314 "gpr22", 

315 "gpr23", 

316 "gpr24", 

317 "gpr25", 

318 "gpr26", 

319 "gpr27", 

320 "gpr28", 

321 "gpr29", 

322 "gpr30", 

323 "gpr31", 

324 "vsr0", 

325 "vsr1", 

326 "vsr2", 

327 "vsr3", 

328 "vsr4", 

329 "vsr5", 

330 "vsr6", 

331 "vsr7", 

332 "vsr8", 

333 "vsr9", 

334 "vsr10", 

335 "vsr11", 

336 "vsr12", 

337 "vsr13", 

338 "vsr14", 

339 "vsr15", 

340 "vsr16", 

341 "vsr17", 

342 "vsr18", 

343 "vsr19", 

344 "vsr20", 

345 "vsr21", 

346 "vsr22", 

347 "vsr23", 

348 "vsr24", 

349 "vsr25", 

350 "vsr26", 

351 "vsr27", 

352 "vsr28", 

353 "vsr29", 

354 "vsr30", 

355 "vsr31", 

356 "cr", 

357 "fpscr", 

358 "msr", 

359 "<none>", # 67 - 79 

360 "<none>", 

361 "<none>", 

362 "sr0", 

363 "sr1", 

364 "sr2", 

365 "sr3", 

366 "sr4", 

367 "sr5", 

368 "sr6", 

369 "sr7", 

370 "sr8", 

371 "sr9", 

372 "sr10", 

373 "sr11", 

374 "sr12", 

375 "sr13", 

376 "sr14", 

377 "sr15", 

378 "sr16", 

379 "sr17", 

380 "sr18", 

381 "sr19", 

382 "sr20", 

383 "sr21", 

384 "sr22", 

385 "sr23", 

386 "sr24", 

387 "sr25", 

388 "sr26", 

389 "sr27", 

390 "sr28", 

391 "sr29", 

392 "sr30", 

393 "sr31", 

394 ] 

395 

396 

397register_arch([r".*p\w*pc.*be"], 64, "Iend_BE", ArchPPC64) 

398register_arch([r".*p\w*pc.*"], 64, "any", ArchPPC64)