SymbiFlow - the GCC of FPGAs

SymbiFlow aims to push FPGAs towards more widespread adoption by optimising and automating FPGA development workflows with a set of pluggable open source tools.

Its goal is to become a complete FOSS toolchain that is:

Fully Open Source
Multi Platform
Pluggable / Interchangeable

Free & Open Source

Multi-platform

Vendor-neutral

Interchangeable
tool suite

Growing
community

Look inside
and improve

Xilinx Series 7 fully open source toolchain!

Tim Ansell | Hackday 2019
VPR device models from Verilog with V2X

Karol Gugala | ORConf 2019
Xilinx Artix 7 support in SymbiFlow

Tim Ansell | ORConf 2019
Improving VPR I/O

Fahrican Koşar | ORConf 2019
An update on SymbiFlow

Tim Ansell | ORConf 2018
The nextpnr FOSS FPGA place-and-route tool

Clifford Wolf | ORConf 2018

Tweets by symbiflow

Xilinx 7-Series

The most popular Xilinx
FPGA family

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Lattice ice40

World's smallest FPGAs
for mobile devices

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Lattice ecp5

Low cost FPGAs with
high performance features

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QuickLogic EOS S3

FPGA + CPU
sensor processing platform

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add more?

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To understand how SymbiFlow works, it is best to start with an overview of
the general EDA tooling ecosystem and then proceed to see what
the SymbiFlow project consists of.

For both ASIC- and FPGA-oriented EDA tooling, there are three major areas:

hardware description
frontend
backend

While there are a number of open hardware description languages, such as Verilog, VHDL, Migen and Chisel, the frontend and backend tooling has been lacking established standard, vendor-neutral solutions. SymbiFlow focuses on filling this gap.

To become a complete FOSS FPGA toolchain, SymbiFlow needs a number of tools and projects to be in place to provide an end-to-end flow. Thus, SymbiFlow serves as an umbrella framework for several activities, the central of which focuses on the creation of FPGA SymbiFlow Architecture Definitions, i.e. documentation of how specific FPGAs work internally.

Those definitions and serve as input to backend tools like nextpnr and Verilog to Routing, and frontend tools like Yosys. They are created within separate collaborating projects targeting different FPGAs - Project X-Ray for Xilinx 7-Series, Project IceStorm for Lattice iCE40 and Project Trellis for Lattice ECP5 FPGAs.

	Project Icestorm	Project Trellis	Project X-Ray	QuickLogic Database
Basic Tiles: Logic Block RAM
Advanced Tiles: DSP Hard Blocks Clock Tiles IO Tiles
Routing: Logic Clock