Verilog to Routing - VPR
logic_vec.h
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1 #ifndef LOGIC_VEC_H
2 #define LOGIC_VEC_H
3 
4 #include <vector>
5 #include <ostream>
6 
7 #include "vtr_logic.h"
8 
9 std::ostream& operator<<(std::ostream& os, vtr::LogicValue val);
10 
12 class LogicVec {
13  public:
14  LogicVec() = default;
15  LogicVec(size_t size_val, //Number of logic values
16  vtr::LogicValue init_value) //Default value
17  : values_(size_val, init_value) {}
18  LogicVec(std::vector<vtr::LogicValue> values)
19  : values_(values) {}
20 
22  const vtr::LogicValue& operator[](size_t i) const { return values_[i]; }
23  vtr::LogicValue& operator[](size_t i) { return values_[i]; }
24 
26  size_t size() const { return values_.size(); }
27 
29  friend std::ostream& operator<<(std::ostream& os, LogicVec logic_vec) {
30  os << logic_vec.values_.size() << "'b";
31  //Print in reverse since th convention is MSB on the left, LSB on the right
32  //but we store things in array order (putting LSB on left, MSB on right)
33  for (auto iter = logic_vec.begin(); iter != logic_vec.end(); iter++) {
34  os << *iter;
35  }
36  return os;
37  }
38 
39  //Standard iterators
40  std::vector<vtr::LogicValue>::reverse_iterator begin() { return values_.rbegin(); }
41  std::vector<vtr::LogicValue>::reverse_iterator end() { return values_.rend(); }
42  std::vector<vtr::LogicValue>::const_reverse_iterator begin() const { return values_.crbegin(); }
43  std::vector<vtr::LogicValue>::const_reverse_iterator end() const { return values_.crend(); }
44 
45  private:
46  std::vector<vtr::LogicValue> values_;
47 };
48 
49 #endif
std::vector< vtr::LogicValue >::reverse_iterator end()
Definition: logic_vec.h:41
size_t size() const
Size accessor.
Definition: logic_vec.h:26
vtr::LogicValue & operator[](size_t i)
Definition: logic_vec.h:23
std::vector< vtr::LogicValue >::reverse_iterator begin()
Definition: logic_vec.h:40
std::vector< vtr::LogicValue >::const_reverse_iterator begin() const
Definition: logic_vec.h:42
std::ostream & operator<<(std::ostream &os, vtr::LogicValue val)
Output operator for vtr::LogicValue.
Definition: logic_vec.cpp:5
LogicVec()=default
std::vector< vtr::LogicValue > values_
Definition: logic_vec.h:46
friend std::ostream & operator<<(std::ostream &os, LogicVec logic_vec)
Output operator which writes the logic vector in verilog format.
Definition: logic_vec.h:29
const vtr::LogicValue & operator[](size_t i) const
Array indexing operator.
Definition: logic_vec.h:22
LogicVec(size_t size_val, vtr::LogicValue init_value)
Definition: logic_vec.h:15
std::vector< vtr::LogicValue >::const_reverse_iterator end() const
Definition: logic_vec.h:43
LogicVec(std::vector< vtr::LogicValue > values)
Definition: logic_vec.h:18
A vector-like object containing logic values.
Definition: logic_vec.h:12