Verilog to Routing - VPR
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#include <memory>
#include <string>
#include <sstream>
#include "vtr_logic.h"
#include "AnalysisDelayCalculator.h"
Go to the source code of this file.
Functions | |
void | netlist_writer (const std::string basename, std::shared_ptr< const AnalysisDelayCalculator > delay_calc) |
Writes out the post-synthesis implementation netlists in BLIF and Verilog formats, along with an SDF for delay annotations. More... | |
void netlist_writer | ( | const std::string | basename, |
std::shared_ptr< const AnalysisDelayCalculator > | delay_calc | ||
) |
Writes out the post-synthesis implementation netlists in BLIF and Verilog formats, along with an SDF for delay annotations.
All written filenames end in {basename}_post_synthesis.{fmt} where {basename} is the basename argument and {fmt} is the file format (e.g. v, blif, sdf)
Writes out the post-synthesis implementation netlists in BLIF and Verilog formats, along with an SDF for delay annotations.