Defines the detailed routing architecture of the FPGA.
Only important if the route_type is DETAILED.
- Parameters
-
| directionality | Should the tracks be uni-directional or bi-directional? (UDSD by AY) |
| switch_block_type | Pattern of switches at each switch block. I assume Fs is always 3. If the type is SUBSET, I use a Xilinx-like switch block where track i in one channel always connects to track i in other channels. If type is WILTON, I use a switch block where track i does not always connect to track i in other channels. See Steve Wilton, Phd Thesis, University of Toronto, 1996. The UNIVERSAL switch block is from Y. W. Chang et al, TODAES, Jan. 1996, pp. 80 - 101. A CUSTOM switch block has also been added which allows a user to describe custom permutation functions and connection patterns. See comment at top of SRC/route/build_switchblocks.c |
| switchblocks | A vector of custom switch block descriptions that is used with the CUSTOM switch block type. See comment at top of SRC/route/build_switchblocks.c |
| delayless_switch | Index of a zero delay switch (used to connect things that should have no delay). |
| wire_to_arch_ipin_switch | keeps track of the type of architecture switch that connects wires to ipins |
| wire_to_rr_ipin_switch | keeps track of the type of RR graph switch that connects wires to ipins in the RR graph |
| R_minW_nmos | Resistance (in Ohms) of a minimum width nmos transistor. Used only in the FPGA area model. |
| R_minW_pmos | Resistance (in Ohms) of a minimum width pmos transistor. |
| read_rr_graph_filename | File to read the RR graph from (overrides architecture) |
| write_rr_graph_filename | File to write the RR graph to after generation |
