Verilog to Routing - VPR
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s_grid_tile is the minimum tile of the fpga More...
#include <device_grid.h>
Data Fields | |
t_physical_tile_type_ptr | type = nullptr |
int | width_offset = 0 |
int | height_offset = 0 |
const t_metadata_dict * | meta = nullptr |
s_grid_tile is the minimum tile of the fpga
int t_grid_tile::height_offset = 0 |
Number of grid tiles reserved based on height (top) of a block
const t_metadata_dict* t_grid_tile::meta = nullptr |
t_physical_tile_type_ptr t_grid_tile::type = nullptr |
Pointer to type descriptor, NULL for illegal
int t_grid_tile::width_offset = 0 |
Number of grid tiles reserved based on width (right) of a block