Verilog to Routing - VPR
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Assignment represents the logical connection between two nets. More...
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Assignment (std::string lval, std::string rval) | |
void | print_verilog (std::ostream &os, std::string indent) |
void | print_blif (std::ostream &os, std::string indent) |
Private Attributes | |
std::string | lval_ |
std::string | rval_ |
Assignment represents the logical connection between two nets.
This is synonomous with verilog's 'assign x = y' which connects two nets with logical identity, assigning the value of 'y' to 'x'
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lval | The left value (assigned to) |
rval | The right value (assigned from) |
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