vpr_context.h

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#ifndef VPR_CONTEXT_H
#define VPR_CONTEXT_H
#include <unordered_map>
#include <memory>
#include <vector>

#include "vpr_types.h"
#include "vtr_ndmatrix.h"
#include "vtr_vector.h"
#include "atom_netlist.h"
#include "clustered_netlist.h"
#include "rr_graph_storage.h"
#include "rr_node.h"
#include "rr_rc_data.h"
#include "tatum/TimingGraph.hpp"
#include "tatum/TimingConstraints.hpp"
#include "power.h"
#include "power_components.h"
#include "device_grid.h"
#include "clock_network_builders.h"
#include "clock_connection_builders.h"
#include "route_traceback.h"
#include "router_lookahead.h"
#include "place_macro.h"
#include "compressed_grid.h"
#include "metadata_storage.h"

struct Context {
    //Contexts are non-copyable
    Context() = default;
    Context(Context&) = delete;
    Context& operator=(Context&) = delete;
    virtual ~Context() = default;
};

struct AtomContext : public Context {
    /********************************************************************
     * Atom Netlist
     ********************************************************************/

    AtomNetlist nlist;

    AtomLookup lookup;
};

struct TimingContext : public Context {
    /********************************************************************
     * Timing
     ********************************************************************/

    std::shared_ptr<tatum::TimingGraph> graph;

    std::shared_ptr<tatum::TimingConstraints> constraints;

    t_timing_analysis_profile_info stats;
};

namespace std {
template<>
struct hash<std::tuple<int, int, short>> {
    std::size_t operator()(const std::tuple<int, int, short>& ok) const noexcept {
        std::size_t seed = std::hash<int>{}(std::get<0>(ok));
        vtr::hash_combine(seed, std::get<1>(ok));
        vtr::hash_combine(seed, std::get<2>(ok));
        return seed;
    }
};
} // namespace std

struct DeviceContext : public Context {
    /*********************************************************************
     * Physical FPGA architecture
     *********************************************************************/

    /*
     * x and y dimensions of the FPGA itself
     */

    DeviceGrid grid; 
    /*
     * Empty types
     */

    t_physical_tile_type_ptr EMPTY_PHYSICAL_TILE_TYPE;
    t_logical_block_type_ptr EMPTY_LOGICAL_BLOCK_TYPE;

    /*
     * block_types are blocks that can be moved by the placer
     * such as: I/Os, CLBs, memories, multipliers, etc
     * Different types of physical block are contained in type descriptors
     */

    std::vector<t_physical_tile_type> physical_tile_types;
    std::vector<t_logical_block_type> logical_block_types;

    bool has_multiple_equivalent_tiles;

    /*******************************************************************
     * Routing related
     ********************************************************************/

    t_chan_width chan_width;

    /*
     * Structures to define the routing architecture of the FPGA.
     */

    t_rr_graph_storage rr_nodes; // autogenerated in build_rr_graph

    std::vector<t_rr_indexed_data> rr_indexed_data; // [0 .. num_rr_indexed_data-1]

    std::vector<t_rr_rc_data> rr_rc_data;

    std::vector<std::vector<int>> rr_non_config_node_sets;

    std::unordered_map<int, int> rr_node_to_non_config_node_set;

    t_rr_node_indices rr_node_indices; // [0..NUM_RR_TYPES-1][0..grid.width()-1][0..grid.width()-1][0..size-1]

    std::vector<t_rr_switch_inf> rr_switch_inf; // autogenerated in build_rr_graph based on switch fan-in. [0..(num_rr_switches-1)]

    std::vector<t_segment_inf> rr_segments;

    int num_arch_switches;
    t_arch_switch_inf* arch_switch_inf; // [0..(num_arch_switches-1)]

    /*
     * Clock Networks
     */

    std::vector<std::unique_ptr<ClockNetwork>> clock_networks;
    std::vector<std::unique_ptr<ClockConnection>> clock_connections;

    int virtual_clock_network_root_idx;

    MetadataStorage<int> rr_node_metadata;
    MetadataStorage<std::tuple<int, int, short>> rr_edge_metadata;

    std::vector<std::map<int, int>> switch_fanin_remap;

    /*******************************************************************
     * Architecture
     ********************************************************************/
    const t_arch* arch;

    /*******************************************************************
     * Clock Network
     ********************************************************************/
    t_clock_arch* clock_arch;

    std::string read_rr_graph_filename;
};

struct PowerContext : public Context {
    /*******************************************************************
     * Power
     ********************************************************************/
    t_solution_inf solution_inf;
    t_power_output* output;
    t_power_commonly_used* commonly_used;
    t_power_tech* tech;
    t_power_arch* arch;
    vtr::vector<ClusterNetId, t_net_power> clb_net_power;

    std::unordered_map<AtomNetId, t_net_power> atom_net_power;
    t_power_components by_component;
};

struct ClusteringContext : public Context {
    /********************************************************************
     * CLB Netlist
     ********************************************************************/

    ClusteredNetlist clb_nlist;
};

struct PlacementContext : public Context {
    vtr::vector_map<ClusterBlockId, t_block_loc> block_locs;

    vtr::vector_map<ClusterPinId, int> physical_pins;

    vtr::Matrix<t_grid_blocks> grid_blocks; //[0..device_ctx.grid.width()-1][0..device_ctx.grid.width()-1]

    std::vector<t_pl_macro> pl_macros;

    t_compressed_block_grids compressed_block_grids;

    std::string placement_id;
};

struct RoutingContext : public Context {
    /* [0..num_nets-1] of linked list start pointers.  Defines the routing.  */
    vtr::vector<ClusterNetId, t_traceback> trace;
    vtr::vector<ClusterNetId, std::unordered_set<int>> trace_nodes;

    vtr::vector<ClusterNetId, std::vector<int>> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */
    vtr::vector<ClusterNetId, uint8_t> is_clock_net;              /* [0..num_nets-1] */

    vtr::vector<ClusterBlockId, std::vector<int>> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */

    std::vector<t_rr_node_route_inf> rr_node_route_inf; /* [0..device_ctx.num_rr_nodes-1] */

    vtr::dynamic_bitset<> non_configurable_bitset; /*[0...device_ctx.num_rr_nodes] */

    t_net_routing_status net_status;

    vtr::vector<ClusterNetId, t_bb> route_bb; /* [0..cluster_ctx.clb_nlist.nets().size()-1]*/

    t_clb_opins_used clb_opins_used_locally; //[0..cluster_ctx.clb_nlist.blocks().size()-1][0..num_class-1]

    std::string routing_id;

    vtr::Cache<std::tuple<e_router_lookahead, std::string, std::vector<t_segment_inf>>,
               RouterLookahead>
        cached_router_lookahead_;
};

class VprContext : public Context {
  public:
    const AtomContext& atom() const { return atom_; }
    AtomContext& mutable_atom() { return atom_; }

    const DeviceContext& device() const { return device_; }
    DeviceContext& mutable_device() { return device_; }

    const TimingContext& timing() const { return timing_; }
    TimingContext& mutable_timing() { return timing_; }

    const PowerContext& power() const { return power_; }
    PowerContext& mutable_power() { return power_; }

    const ClusteringContext& clustering() const { return clustering_; }
    ClusteringContext& mutable_clustering() { return clustering_; }

    const PlacementContext& placement() const { return placement_; }
    PlacementContext& mutable_placement() { return placement_; }

    const RoutingContext& routing() const { return routing_; }
    RoutingContext& mutable_routing() { return routing_; }

  private:
    DeviceContext device_;

    AtomContext atom_;

    TimingContext timing_;
    PowerContext power_;

    ClusteringContext clustering_;
    PlacementContext placement_;
    RoutingContext routing_;
};

#endif